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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019, Intel Corporation
*/
#include <linux/slab.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/agilex-clock.h>
#include "stratix10-clk.h"
static const struct clk_parent_data pll_mux[] = {
{ .fw_name = "osc1",
.name = "osc1", },
{ .fw_name = "cb-intosc-hs-div2-clk",
.name = "cb-intosc-hs-div2-clk", },
{ .fw_name = "f2s-free-clk",
.name = "f2s-free-clk", },
};
static const struct clk_parent_data boot_mux[] = {
{ .fw_name = "osc1",
.name = "osc1", },
{ .fw_name = "cb-intosc-hs-div2-clk",
.name = "cb-intosc-hs-div2-clk", },
};
static const struct clk_parent_data mpu_free_mux[] = {
{ .fw_name = "main_pll_c0",
.name = "main_pll_c0", },
{ .fw_name = "peri_pll_c0",
.name = "peri_pll_c0", },
{ .fw_name = "osc1",
.name = "osc1", },
{ .fw_name = "cb-intosc-hs-div2-clk",
.name = "cb-intosc-hs-div2-clk", },
{ .fw_name = "f2s-free-clk",
.name = "f2s-free-clk", },
};
static const struct clk_parent_data noc_free_mux[] = {
{ .fw_name = "main_pll_c1",
.name = "main_pll_c1", },
{ .fw_name = "peri_pll_c1",
.name = "peri_pll_c1", },
{ .fw_name = "osc1",
.name = "osc1", },
{ .fw_name = "cb-intosc-hs-div2-clk",
.name = "cb-intosc-hs-div2-clk", },
{ .fw_name = "f2s-free-clk",
.name = "f2s-free-clk", },
};
static const struct clk_parent_data emaca_free_mux[] = {
{ .fw_name = "main_pll_c2",
.name = "main_pll_c2", },
{ .fw_name = "peri_pll_c2",
.name = "peri_pll_c2", },
{ .fw_name = "osc1",
.name = "osc1", },
{ .fw_name = "cb-intosc-hs-div2-clk",
.name = "cb-intosc-hs-div2-clk", },
{ .fw_name = "f2s-free-clk",
.name = "f2s-free-clk", },
};
static const struct clk_parent_data emacb_free_mux[] = {
{ .fw_name = "main_pll_c3",
.name = "main_pll_c3", },
{ .fw_name = "peri_pll_c3",
.name = "peri_pll_c3", },
{ .fw_name = "osc1",
.name = "osc1", },
{ .fw_name = "cb-intosc-hs-div2-clk",
.name = "cb-intosc-hs-div2-clk", },
{ .fw_name = "f2s-free-clk",
.name = "f2s-free-clk", },
};
static const struct clk_parent_data emac_ptp_free_mux[] = {
{ .fw_name = "main_pll_c3",
.name = "main_pll_c3", },
{ .fw_name = "peri_pll_c3",
.name = "peri_pll_c3", },
{ .fw_name = "osc1",
.name = "osc1", },
{ .fw_name = "cb-intosc-hs-div2-clk",
.name = "cb-intosc-hs-div2-clk", },
{ .fw_name = "f2s-free-clk",
.name = "f2s-free-clk", },
};
static const struct clk_parent_data gpio_db_free_mux[] = {
{ .fw_name = "main_pll_c3",
.name = "main_pll_c3", },
{ .fw_name = "peri_pll_c3",
.name = "peri_pll_c3", },
{ .fw_name = "osc1",
.name = "osc1", },
{ .fw_name = "cb-intosc-hs-div2-clk",
.name = "cb-intosc-hs-div2-clk", },
{ .fw_name = "f2s-free-clk",
.name = "f2s-free-clk", },
};
static const struct clk_parent_data psi_ref_free_mux[] = {
{ .fw_name = "main_pll_c2",
.name = "main_pll_c2", },
{ .fw_name = "peri_pll_c2",
.name = "peri_pll_c2", },
{ .fw_name = "osc1",
.name = "osc1", },
{ .fw_name = "cb-intosc-hs-div2-clk",
.name = "cb-intosc-hs-div2-clk", },
{ .fw_name = "f2s-free-clk",
.name = "f2s-free-clk", },
};
static const struct clk_parent_data sdmmc_free_mux[] = {
{ .fw_name = "main_pll_c3",
.name = "main_pll_c3", },
{ .fw_name = "peri_pll_c3",
.name = "peri_pll_c3", },
{ .fw_name = "osc1",
.name = "osc1", },
{ .fw_name = "cb-intosc-hs-div2-clk",
.name = "cb-intosc-hs-div2-clk", },
{ .fw_name = "f2s-free-clk",
.name = "f2s-free-clk", },
};
static const struct clk_parent_data s2f_usr0_free_mux[] = {
{ .fw_name = "main_pll_c2",
.name = "main_pll_c2", },
{ .fw_name = "peri_pll_c2",
.name = "peri_pll_c2", },
{ .fw_name = "osc1",
.name = "osc1", },
{ .fw_name = "cb-intosc-hs-div2-clk",
.name = "cb-intosc-hs-div2-clk", },
{ .fw_name = "f2s-free-clk",
.name = "f2s-free-clk", },
};
static const struct clk_parent_data s2f_usr1_free_mux[] = {
{ .fw_name = "main_pll_c2",
.name = "main_pll_c2", },
{ .fw_name = "peri_pll_c2",
.name = "peri_pll_c2", },
{ .fw_name = "osc1",
.name = "osc1", },
{ .fw_name = "cb-intosc-hs-div2-clk",
.name = "cb-intosc-hs-div2-clk", },
{ .fw_name = "f2s-free-clk",
.name = "f2s-free-clk", },
};
static const struct clk_parent_data mpu_mux[] = {
{ .fw_name = "mpu_free_clk",
.name = "mpu_free_clk", },
{ .fw_name = "boot_clk",
.name = "boot_clk", },
};
static const struct clk_parent_data emac_mux[] = {
{ .fw_name = "emaca_free_clk",
.name = "emaca_free_clk", },
{ .fw_name = "emacb_free_clk",
.name = "emacb_free_clk", },
{ .fw_name = "boot_clk",
.name = "boot_clk", },
};
static const struct clk_parent_data noc_mux[] = {
{ .fw_name = "noc_free_clk",
.name = "noc_free_clk", },
{ .fw_name = "boot_clk",
.name = "boot_clk", },
};
static const struct clk_parent_data sdmmc_mux[] = {
{ .fw_name = "sdmmc_free_clk",
.name = "sdmmc_free_clk", },
{ .fw_name = "boot_clk",
.name = "boot_clk", },
};
static const struct clk_parent_data s2f_user0_mux[] = {
{ .fw_name = "s2f_user0_free_clk",
.name = "s2f_user0_free_clk", },
{ .fw_name = "boot_clk",
.name = "boot_clk", },
};
static const struct clk_parent_data s2f_user1_mux[] = {
{ .fw_name = "s2f_user1_free_clk",
.name = "s2f_user1_free_clk", },
{ .fw_name = "boot_clk",
.name = "boot_clk", },
};
static const struct clk_parent_data psi_mux[] = {
{ .fw_name = "psi_ref_free_clk",
.name = "psi_ref_free_clk", },
{ .fw_name = "boot_clk",
.name = "boot_clk", },
};
static const struct clk_parent_data gpio_db_mux[] = {
{ .fw_name = "gpio_db_free_clk",
.name = "gpio_db_free_clk", },
{ .fw_name = "boot_clk",
.name = "boot_clk", },
};
static const struct clk_parent_data emac_ptp_mux[] = {
{ .fw_name = "emac_ptp_free_clk",
.name = "emac_ptp_free_clk", },
{ .fw_name = "boot_clk",
.name = "boot_clk", },
};
/* clocks in AO (always on) controller */
static const struct stratix10_pll_clock agilex_pll_clks[] = {
{ AGILEX_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
0x0},
{ AGILEX_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
0, 0x48},
{ AGILEX_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
0, 0x9c},
};
static const struct n5x_perip_c_clock n5x_main_perip_c_clks[] = {
{ AGILEX_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, 0x54, 0},
{ AGILEX_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, 0x54, 8},
{ AGILEX_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0, 0x54, 16},
{ AGILEX_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0, 0x54, 24},
{ AGILEX_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0, 0xA8, 0},
{ AGILEX_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0, 0xA8, 8},
{ AGILEX_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0, 0xA8, 16},
{ AGILEX_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0, 0xA8, 24},
};
static const struct stratix10_perip_c_clock agilex_main_perip_c_clks[] = {
{ AGILEX_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, 0x58},
{ AGILEX_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, 0x5C},
{ AGILEX_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0, 0x64},
{ AGILEX_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0, 0x68},
{ AGILEX_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0, 0xAC},
{ AGILEX_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0, 0xB0},
{ AGILEX_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0, 0xB8},
{ AGILEX_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0, 0xBC},
};
static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = {
{ AGILEX_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux),
0, 0x3C, 0, 0, 0},
{ AGILEX_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
0, 0x40, 0, 0, 0},
{ AGILEX_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0,
0, 4, 0x30, 1},
{ AGILEX_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
0, 0xD4, 0, 0x88, 0},
{ AGILEX_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
0, 0xD8, 0, 0x88, 1},
{ AGILEX_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux,
ARRAY_SIZE(emac_ptp_free_mux), 0, 0xDC, 0, 0x88, 2},
{ AGILEX_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
ARRAY_SIZE(gpio_db_free_mux), 0, 0xE0, 0, 0x88, 3},
{ AGILEX_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux,
ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0, 0},
{ AGILEX_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, s2f_usr0_free_mux,
ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0x30, 2},
{ AGILEX_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux,
ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88, 5},
{ AGILEX_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
ARRAY_SIZE(psi_ref_free_mux), 0, 0xF0, 0, 0x88, 6},
};
static const struct stratix10_gate_clock agilex_gate_clks[] = {
{ AGILEX_MPU_CLK, "mpu_clk", NULL, mpu_mux, ARRAY_SIZE(mpu_mux), 0, 0x24,
0, 0, 0, 0, 0x30, 0, 0},
{ AGILEX_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x24,
0, 0, 0, 0, 0, 0, 4},
{ AGILEX_MPU_CCU_CLK, "mpu_ccu_clk", "mpu_clk", NULL, 1, 0, 0x24,
0, 0, 0, 0, 0, 0, 2},
{ AGILEX_L4_MAIN_CLK, "l4_main_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
1, 0x44, 0, 2, 0x30, 1, 0},
{ AGILEX_L4_MP_CLK, "l4_mp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
2, 0x44, 8, 2, 0x30, 1, 0},
/*
* The l4_sp_clk feeds a 100 MHz clock to various peripherals, one of them
* being the SP timers, thus cannot get gated.
*/
{ AGILEX_L4_SP_CLK, "l4_sp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), CLK_IS_CRITICAL, 0x24,
3, 0x44, 16, 2, 0x30, 1, 0},
{ AGILEX_CS_AT_CLK, "cs_at_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
4, 0x44, 24, 2, 0x30, 1, 0},
{ AGILEX_CS_TRACE_CLK, "cs_trace_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
4, 0x44, 26, 2, 0x30, 1, 0},
{ AGILEX_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x24,
4, 0x44, 28, 1, 0, 0, 0},
{ AGILEX_CS_TIMER_CLK, "cs_timer_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x24,
5, 0, 0, 0, 0x30, 1, 0},
{ AGILEX_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
0, 0, 0, 0, 0x94, 26, 0},
{ AGILEX_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
1, 0, 0, 0, 0x94, 27, 0},
{ AGILEX_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
2, 0, 0, 0, 0x94, 28, 0},
{ AGILEX_EMAC_PTP_CLK, "emac_ptp_clk", NULL, emac_ptp_mux, ARRAY_SIZE(emac_ptp_mux), 0, 0x7C,
3, 0, 0, 0, 0x88, 2, 0},
{ AGILEX_GPIO_DB_CLK, "gpio_db_clk", NULL, gpio_db_mux, ARRAY_SIZE(gpio_db_mux), 0, 0x7C,
4, 0x98, 0, 16, 0x88, 3, 0},
{ AGILEX_SDMMC_CLK, "sdmmc_clk", NULL, sdmmc_mux, ARRAY_SIZE(sdmmc_mux), 0, 0x7C,
5, 0, 0, 0, 0x88, 4, 4},
{ AGILEX_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_user0_mux, ARRAY_SIZE(s2f_user0_mux), 0, 0x24,
6, 0, 0, 0, 0x30, 2, 0},
{ AGILEX_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux, ARRAY_SIZE(s2f_user1_mux), 0, 0x7C,
6, 0, 0, 0, 0x88, 5, 0},
{ AGILEX_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux, ARRAY_SIZE(psi_mux), 0, 0x7C,
7, 0, 0, 0, 0x88, 6, 0},
{ AGILEX_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
8, 0, 0, 0, 0, 0, 0},
{ AGILEX_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
9, 0, 0, 0, 0, 0, 0},
{ AGILEX_NAND_X_CLK, "nand_x_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
10, 0, 0, 0, 0, 0, 0},
{ AGILEX_NAND_CLK, "nand_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
10, 0, 0, 0, 0, 0, 4},
{ AGILEX_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
10, 0, 0, 0, 0, 0, 4},
};
static int n5x_clk_register_c_perip(const struct n5x_perip_c_clock *clks,
int nums, struct stratix10_clock_data *data)
{
struct clk_hw *hw_clk;
void __iomem *base = data->base;
int i;
for (i = 0; i < nums; i++) {
hw_clk = n5x_register_periph(&clks[i], base);
if (IS_ERR(hw_clk)) {
pr_err("%s: failed to register clock %s\n",
__func__, clks[i].name);
continue;
}
data->clk_data.hws[clks[i].id] = hw_clk;
}
return 0;
}
static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
int nums, struct stratix10_clock_data *data)
{
struct clk_hw *hw_clk;
void __iomem *base = data->base;
int i;
for (i = 0; i < nums; i++) {
hw_clk = s10_register_periph(&clks[i], base);
if (IS_ERR(hw_clk)) {
pr_err("%s: failed to register clock %s\n",
__func__, clks[i].name);
continue;
}
data->clk_data.hws[clks[i].id] = hw_clk;
}
return 0;
}
static int agilex_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
int nums, struct stratix10_clock_data *data)
{
struct clk_hw *hw_clk;
void __iomem *base = data->base;
int i;
for (i = 0; i < nums; i++) {
hw_clk = s10_register_cnt_periph(&clks[i], base);
if (IS_ERR(hw_clk)) {
pr_err("%s: failed to register clock %s\n",
__func__, clks[i].name);
continue;
}
data->clk_data.hws[clks[i].id] = hw_clk;
}
return 0;
}
static int agilex_clk_register_gate(const struct stratix10_gate_clock *clks,
int nums, struct stratix10_clock_data *data)
{
struct clk_hw *hw_clk;
void __iomem *base = data->base;
int i;
for (i = 0; i < nums; i++) {
hw_clk = agilex_register_gate(&clks[i], base);
if (IS_ERR(hw_clk)) {
pr_err("%s: failed to register clock %s\n",
__func__, clks[i].name);
continue;
}
data->clk_data.hws[clks[i].id] = hw_clk;
}
return 0;
}
static int agilex_clk_register_pll(const struct stratix10_pll_clock *clks,
int nums, struct stratix10_clock_data *data)
{
struct clk_hw *hw_clk;
void __iomem *base = data->base;
int i;
for (i = 0; i < nums; i++) {
hw_clk = agilex_register_pll(&clks[i], base);
if (IS_ERR(hw_clk)) {
pr_err("%s: failed to register clock %s\n",
__func__, clks[i].name);
continue;
}
data->clk_data.hws[clks[i].id] = hw_clk;
}
return 0;
}
static int n5x_clk_register_pll(const struct stratix10_pll_clock *clks,
int nums, struct stratix10_clock_data *data)
{
struct clk_hw *hw_clk;
void __iomem *base = data->base;
int i;
for (i = 0; i < nums; i++) {
hw_clk = n5x_register_pll(&clks[i], base);
if (IS_ERR(hw_clk)) {
pr_err("%s: failed to register clock %s\n",
__func__, clks[i].name);
continue;
}
data->clk_data.hws[clks[i].id] = hw_clk;
}
return 0;
}
static int agilex_clkmgr_init(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device *dev = &pdev->dev;
struct stratix10_clock_data *clk_data;
void __iomem *base;
int i, num_clks;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
num_clks = AGILEX_NUM_CLKS;
clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
num_clks), GFP_KERNEL);
if (!clk_data)
return -ENOMEM;
for (i = 0; i < num_clks; i++)
clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
clk_data->base = base;
clk_data->clk_data.num = num_clks;
agilex_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data);
agilex_clk_register_c_perip(agilex_main_perip_c_clks,
ARRAY_SIZE(agilex_main_perip_c_clks), clk_data);
agilex_clk_register_cnt_perip(agilex_main_perip_cnt_clks,
ARRAY_SIZE(agilex_main_perip_cnt_clks),
clk_data);
agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks),
clk_data);
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
return 0;
}
static int n5x_clkmgr_init(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device *dev = &pdev->dev;
struct stratix10_clock_data *clk_data;
void __iomem *base;
int i, num_clks;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
num_clks = AGILEX_NUM_CLKS;
clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
num_clks), GFP_KERNEL);
if (!clk_data)
return -ENOMEM;
for (i = 0; i < num_clks; i++)
clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
clk_data->base = base;
clk_data->clk_data.num = num_clks;
n5x_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data);
n5x_clk_register_c_perip(n5x_main_perip_c_clks,
ARRAY_SIZE(n5x_main_perip_c_clks), clk_data);
agilex_clk_register_cnt_perip(agilex_main_perip_cnt_clks,
ARRAY_SIZE(agilex_main_perip_cnt_clks),
clk_data);
agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks),
clk_data);
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
return 0;
}
static int agilex_clkmgr_probe(struct platform_device *pdev)
{
int (*probe_func)(struct platform_device *init_func);
probe_func = of_device_get_match_data(&pdev->dev);
if (!probe_func)
return -ENODEV;
return probe_func(pdev);
}
static const struct of_device_id agilex_clkmgr_match_table[] = {
{ .compatible = "intel,agilex-clkmgr",
.data = agilex_clkmgr_init },
{ .compatible = "intel,easic-n5x-clkmgr",
.data = n5x_clkmgr_init },
{ }
};
static struct platform_driver agilex_clkmgr_driver = {
.probe = agilex_clkmgr_probe,
.driver = {
.name = "agilex-clkmgr",
.suppress_bind_attrs = true,
.of_match_table = agilex_clkmgr_match_table,
},
};
static int __init agilex_clk_init(void)
{
return platform_driver_register(&agilex_clkmgr_driver);
}
core_initcall(agilex_clk_init);
| linux-master | drivers/clk/socfpga/clk-agilex.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015 Altera Corporation. All rights reserved
*/
#include <linux/slab.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "clk.h"
/* Clock Manager offsets */
#define CLK_MGR_PLL_CLK_SRC_SHIFT 8
#define CLK_MGR_PLL_CLK_SRC_MASK 0x3
/* Clock bypass bits */
#define SOCFPGA_PLL_BG_PWRDWN 0
#define SOCFPGA_PLL_PWR_DOWN 1
#define SOCFPGA_PLL_EXT_ENA 2
#define SOCFPGA_PLL_DIVF_MASK 0x00001FFF
#define SOCFPGA_PLL_DIVF_SHIFT 0
#define SOCFPGA_PLL_DIVQ_MASK 0x003F0000
#define SOCFPGA_PLL_DIVQ_SHIFT 16
#define SOCFGPA_MAX_PARENTS 5
#define SOCFPGA_MAIN_PLL_CLK "main_pll"
#define SOCFPGA_PERIP_PLL_CLK "periph_pll"
#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
void __iomem *clk_mgr_a10_base_addr;
static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
unsigned long divf, divq, reg;
unsigned long long vco_freq;
/* read VCO1 reg for numerator and denominator */
reg = readl(socfpgaclk->hw.reg + 0x4);
divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
vco_freq = (unsigned long long)parent_rate * (divf + 1);
do_div(vco_freq, (1 + divq));
return (unsigned long)vco_freq;
}
static u8 clk_pll_get_parent(struct clk_hw *hwclk)
{
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
u32 pll_src;
pll_src = readl(socfpgaclk->hw.reg);
return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
CLK_MGR_PLL_CLK_SRC_MASK;
}
static const struct clk_ops clk_pll_ops = {
.recalc_rate = clk_pll_recalc_rate,
.get_parent = clk_pll_get_parent,
};
static void __init __socfpga_pll_init(struct device_node *node,
const struct clk_ops *ops)
{
u32 reg;
struct clk_hw *hw_clk;
struct socfpga_pll *pll_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFGPA_MAX_PARENTS];
struct clk_init_data init;
struct device_node *clkmgr_np;
int rc;
int i = 0;
of_property_read_u32(node, "reg", ®);
pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
if (WARN_ON(!pll_clk))
return;
clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
clk_mgr_a10_base_addr = of_iomap(clkmgr_np, 0);
of_node_put(clkmgr_np);
BUG_ON(!clk_mgr_a10_base_addr);
pll_clk->hw.reg = clk_mgr_a10_base_addr + reg;
of_property_read_string(node, "clock-output-names", &clk_name);
init.name = clk_name;
init.ops = ops;
init.flags = 0;
while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] =
of_clk_get_parent_name(node, i)) != NULL)
i++;
init.num_parents = i;
init.parent_names = parent_name;
pll_clk->hw.hw.init = &init;
pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
hw_clk = &pll_clk->hw.hw;
rc = clk_hw_register(NULL, hw_clk);
if (rc) {
pr_err("Could not register clock:%s\n", clk_name);
goto err_clk_hw_register;
}
rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw_clk);
if (rc) {
pr_err("Could not register clock provider for node:%s\n",
clk_name);
goto err_of_clk_add_hw_provider;
}
return;
err_of_clk_add_hw_provider:
clk_hw_unregister(hw_clk);
err_clk_hw_register:
kfree(pll_clk);
}
void __init socfpga_a10_pll_init(struct device_node *node)
{
__socfpga_pll_init(node, &clk_pll_ops);
}
| linux-master | drivers/clk/socfpga/clk-pll-a10.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2011-2012 Calxeda, Inc.
* Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
*
* Based from clk-highbank.c
*/
#include <linux/slab.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include "clk.h"
#define SOCFPGA_L4_MP_CLK "l4_mp_clk"
#define SOCFPGA_L4_SP_CLK "l4_sp_clk"
#define SOCFPGA_NAND_CLK "nand_clk"
#define SOCFPGA_NAND_X_CLK "nand_x_clk"
#define SOCFPGA_MMC_CLK "sdmmc_clk"
#define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8
#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
/* SDMMC Group for System Manager defines */
#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108
static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
{
u32 l4_src;
u32 perpll_src;
const char *name = clk_hw_get_name(hwclk);
if (streq(name, SOCFPGA_L4_MP_CLK)) {
l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
return l4_src & 0x1;
}
if (streq(name, SOCFPGA_L4_SP_CLK)) {
l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
return !!(l4_src & 2);
}
perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
if (streq(name, SOCFPGA_MMC_CLK))
return perpll_src & 0x3;
if (streq(name, SOCFPGA_NAND_CLK) ||
streq(name, SOCFPGA_NAND_X_CLK))
return (perpll_src >> 2) & 3;
/* QSPI clock */
return (perpll_src >> 4) & 3;
}
static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
{
u32 src_reg;
const char *name = clk_hw_get_name(hwclk);
if (streq(name, SOCFPGA_L4_MP_CLK)) {
src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
src_reg &= ~0x1;
src_reg |= parent;
writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
} else if (streq(name, SOCFPGA_L4_SP_CLK)) {
src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
src_reg &= ~0x2;
src_reg |= (parent << 1);
writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
} else {
src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
if (streq(name, SOCFPGA_MMC_CLK)) {
src_reg &= ~0x3;
src_reg |= parent;
} else if (streq(name, SOCFPGA_NAND_CLK) ||
streq(name, SOCFPGA_NAND_X_CLK)) {
src_reg &= ~0xC;
src_reg |= (parent << 2);
} else {/* QSPI clock */
src_reg &= ~0x30;
src_reg |= (parent << 4);
}
writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
}
return 0;
}
static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
u32 div = 1, val;
if (socfpgaclk->fixed_div)
div = socfpgaclk->fixed_div;
else if (socfpgaclk->div_reg) {
val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
val &= GENMASK(socfpgaclk->width - 1, 0);
/* Check for GPIO_DB_CLK by its offset */
if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
div = val + 1;
else
div = (1 << val);
}
return parent_rate / div;
}
static struct clk_ops gateclk_ops = {
.recalc_rate = socfpga_clk_recalc_rate,
.determine_rate = clk_hw_determine_rate_no_reparent,
.get_parent = socfpga_clk_get_parent,
.set_parent = socfpga_clk_set_parent,
};
void __init socfpga_gate_init(struct device_node *node)
{
u32 clk_gate[2];
u32 div_reg[3];
u32 fixed_div;
struct clk_hw *hw_clk;
struct socfpga_gate_clk *socfpga_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
struct clk_ops *ops;
int rc;
socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
if (WARN_ON(!socfpga_clk))
return;
ops = kmemdup(&gateclk_ops, sizeof(gateclk_ops), GFP_KERNEL);
if (WARN_ON(!ops))
goto err_kmemdup;
rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
if (rc)
clk_gate[0] = 0;
if (clk_gate[0]) {
socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
socfpga_clk->hw.bit_idx = clk_gate[1];
ops->enable = clk_gate_ops.enable;
ops->disable = clk_gate_ops.disable;
}
rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
if (rc)
socfpga_clk->fixed_div = 0;
else
socfpga_clk->fixed_div = fixed_div;
rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
if (!rc) {
socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
socfpga_clk->shift = div_reg[1];
socfpga_clk->width = div_reg[2];
} else {
socfpga_clk->div_reg = NULL;
}
of_property_read_string(node, "clock-output-names", &clk_name);
init.name = clk_name;
init.ops = ops;
init.flags = 0;
init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
if (init.num_parents < 2) {
ops->get_parent = NULL;
ops->set_parent = NULL;
}
init.parent_names = parent_name;
socfpga_clk->hw.hw.init = &init;
hw_clk = &socfpga_clk->hw.hw;
rc = clk_hw_register(NULL, hw_clk);
if (rc) {
pr_err("Could not register clock:%s\n", clk_name);
goto err_clk_hw_register;
}
rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw_clk);
if (rc) {
pr_err("Could not register clock provider for node:%s\n",
clk_name);
goto err_of_clk_add_hw_provider;
}
return;
err_of_clk_add_hw_provider:
clk_hw_unregister(hw_clk);
err_clk_hw_register:
kfree(ops);
err_kmemdup:
kfree(socfpga_clk);
}
| linux-master | drivers/clk/socfpga/clk-gate.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017, Intel Corporation
*/
#include <linux/slab.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include "stratix10-clk.h"
#include "clk.h"
/* Clock Manager offsets */
#define CLK_MGR_PLL_CLK_SRC_SHIFT 16
#define CLK_MGR_PLL_CLK_SRC_MASK 0x3
/* PLL Clock enable bits */
#define SOCFPGA_PLL_POWER 0
#define SOCFPGA_PLL_RESET_MASK 0x2
#define SOCFPGA_PLL_REFDIV_MASK 0x00003F00
#define SOCFPGA_PLL_REFDIV_SHIFT 8
#define SOCFPGA_PLL_AREFDIV_MASK 0x00000F00
#define SOCFPGA_PLL_DREFDIV_MASK 0x00003000
#define SOCFPGA_PLL_DREFDIV_SHIFT 12
#define SOCFPGA_PLL_MDIV_MASK 0xFF000000
#define SOCFPGA_PLL_MDIV_SHIFT 24
#define SOCFPGA_AGILEX_PLL_MDIV_MASK 0x000003FF
#define SWCTRLBTCLKSEL_MASK 0x200
#define SWCTRLBTCLKSEL_SHIFT 9
#define SOCFPGA_N5X_PLLDIV_FDIV_MASK GENMASK(16, 8)
#define SOCFPGA_N5X_PLLDIV_FDIV_SHIFT 8
#define SOCFPGA_N5X_PLLDIV_RDIV_MASK GENMASK(5, 0)
#define SOCFPGA_N5X_PLLDIV_QDIV_MASK GENMASK(26, 24)
#define SOCFPGA_N5X_PLLDIV_QDIV_SHIFT 24
#define SOCFPGA_BOOT_CLK "boot_clk"
#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
static unsigned long n5x_clk_pll_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
unsigned long fdiv, reg, rdiv, qdiv;
u32 power = 1;
/* read VCO1 reg for numerator and denominator */
reg = readl(socfpgaclk->hw.reg + 0x8);
fdiv = (reg & SOCFPGA_N5X_PLLDIV_FDIV_MASK) >> SOCFPGA_N5X_PLLDIV_FDIV_SHIFT;
rdiv = (reg & SOCFPGA_N5X_PLLDIV_RDIV_MASK);
qdiv = (reg & SOCFPGA_N5X_PLLDIV_QDIV_MASK) >> SOCFPGA_N5X_PLLDIV_QDIV_SHIFT;
while (qdiv) {
power *= 2;
qdiv--;
}
return ((parent_rate * 2 * (fdiv + 1)) / ((rdiv + 1) * power));
}
static unsigned long agilex_clk_pll_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
unsigned long arefdiv, reg, mdiv;
unsigned long long vco_freq;
/* read VCO1 reg for numerator and denominator */
reg = readl(socfpgaclk->hw.reg);
arefdiv = (reg & SOCFPGA_PLL_AREFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
vco_freq = (unsigned long long)parent_rate / arefdiv;
/* Read mdiv and fdiv from the fdbck register */
reg = readl(socfpgaclk->hw.reg + 0x24);
mdiv = reg & SOCFPGA_AGILEX_PLL_MDIV_MASK;
vco_freq = (unsigned long long)vco_freq * mdiv;
return (unsigned long)vco_freq;
}
static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
unsigned long mdiv;
unsigned long refdiv;
unsigned long reg;
unsigned long long vco_freq;
/* read VCO1 reg for numerator and denominator */
reg = readl(socfpgaclk->hw.reg);
refdiv = (reg & SOCFPGA_PLL_REFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
vco_freq = parent_rate;
do_div(vco_freq, refdiv);
/* Read mdiv and fdiv from the fdbck register */
reg = readl(socfpgaclk->hw.reg + 0x4);
mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT;
vco_freq = (unsigned long long)vco_freq * (mdiv + 6);
return (unsigned long)vco_freq;
}
static unsigned long clk_boot_clk_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
u32 div;
div = ((readl(socfpgaclk->hw.reg) &
SWCTRLBTCLKSEL_MASK) >>
SWCTRLBTCLKSEL_SHIFT);
div += 1;
return parent_rate / div;
}
static u8 clk_pll_get_parent(struct clk_hw *hwclk)
{
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
u32 pll_src;
pll_src = readl(socfpgaclk->hw.reg);
return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
CLK_MGR_PLL_CLK_SRC_MASK;
}
static u8 clk_boot_get_parent(struct clk_hw *hwclk)
{
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
u32 pll_src;
pll_src = readl(socfpgaclk->hw.reg);
return (pll_src >> SWCTRLBTCLKSEL_SHIFT) &
SWCTRLBTCLKSEL_MASK;
}
static int clk_pll_prepare(struct clk_hw *hwclk)
{
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
u32 reg;
/* Bring PLL out of reset */
reg = readl(socfpgaclk->hw.reg);
reg |= SOCFPGA_PLL_RESET_MASK;
writel(reg, socfpgaclk->hw.reg);
return 0;
}
static int n5x_clk_pll_prepare(struct clk_hw *hwclk)
{
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
u32 reg;
/* Bring PLL out of reset */
reg = readl(socfpgaclk->hw.reg + 0x4);
reg |= SOCFPGA_PLL_RESET_MASK;
writel(reg, socfpgaclk->hw.reg + 0x4);
return 0;
}
static const struct clk_ops n5x_clk_pll_ops = {
.recalc_rate = n5x_clk_pll_recalc_rate,
.get_parent = clk_pll_get_parent,
.prepare = n5x_clk_pll_prepare,
};
static const struct clk_ops agilex_clk_pll_ops = {
.recalc_rate = agilex_clk_pll_recalc_rate,
.get_parent = clk_pll_get_parent,
.prepare = clk_pll_prepare,
};
static const struct clk_ops clk_pll_ops = {
.recalc_rate = clk_pll_recalc_rate,
.get_parent = clk_pll_get_parent,
.prepare = clk_pll_prepare,
};
static const struct clk_ops clk_boot_ops = {
.recalc_rate = clk_boot_clk_recalc_rate,
.get_parent = clk_boot_get_parent,
.prepare = clk_pll_prepare,
};
struct clk_hw *s10_register_pll(const struct stratix10_pll_clock *clks,
void __iomem *reg)
{
struct clk_hw *hw_clk;
struct socfpga_pll *pll_clk;
struct clk_init_data init;
const char *name = clks->name;
int ret;
pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
if (WARN_ON(!pll_clk))
return NULL;
pll_clk->hw.reg = reg + clks->offset;
if (streq(name, SOCFPGA_BOOT_CLK))
init.ops = &clk_boot_ops;
else
init.ops = &clk_pll_ops;
init.name = name;
init.flags = clks->flags;
init.num_parents = clks->num_parents;
init.parent_names = NULL;
init.parent_data = clks->parent_data;
pll_clk->hw.hw.init = &init;
pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
hw_clk = &pll_clk->hw.hw;
ret = clk_hw_register(NULL, hw_clk);
if (ret) {
kfree(pll_clk);
return ERR_PTR(ret);
}
return hw_clk;
}
struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks,
void __iomem *reg)
{
struct clk_hw *hw_clk;
struct socfpga_pll *pll_clk;
struct clk_init_data init;
const char *name = clks->name;
int ret;
pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
if (WARN_ON(!pll_clk))
return NULL;
pll_clk->hw.reg = reg + clks->offset;
if (streq(name, SOCFPGA_BOOT_CLK))
init.ops = &clk_boot_ops;
else
init.ops = &agilex_clk_pll_ops;
init.name = name;
init.flags = clks->flags;
init.num_parents = clks->num_parents;
init.parent_names = NULL;
init.parent_data = clks->parent_data;
pll_clk->hw.hw.init = &init;
pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
hw_clk = &pll_clk->hw.hw;
ret = clk_hw_register(NULL, hw_clk);
if (ret) {
kfree(pll_clk);
return ERR_PTR(ret);
}
return hw_clk;
}
struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks,
void __iomem *reg)
{
struct clk_hw *hw_clk;
struct socfpga_pll *pll_clk;
struct clk_init_data init;
const char *name = clks->name;
int ret;
pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
if (WARN_ON(!pll_clk))
return NULL;
pll_clk->hw.reg = reg + clks->offset;
if (streq(name, SOCFPGA_BOOT_CLK))
init.ops = &clk_boot_ops;
else
init.ops = &n5x_clk_pll_ops;
init.name = name;
init.flags = clks->flags;
init.num_parents = clks->num_parents;
init.parent_names = NULL;
init.parent_data = clks->parent_data;
pll_clk->hw.hw.init = &init;
pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
hw_clk = &pll_clk->hw.hw;
ret = clk_hw_register(NULL, hw_clk);
if (ret) {
kfree(pll_clk);
return ERR_PTR(ret);
}
return hw_clk;
}
| linux-master | drivers/clk/socfpga/clk-pll-s10.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 [email protected]
* Copyright (C) 2021 Samuel Holland <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu-sun20i-d1-r.h"
static const struct clk_parent_data r_ahb_apb0_parents[] = {
{ .fw_name = "hosc" },
{ .fw_name = "losc" },
{ .fw_name = "iosc" },
{ .fw_name = "pll-periph" },
};
static SUNXI_CCU_MP_DATA_WITH_MUX(r_ahb_clk, "r-ahb",
r_ahb_apb0_parents, 0x000,
0, 5, /* M */
8, 2, /* P */
24, 3, /* mux */
0);
static const struct clk_hw *r_ahb_hw = &r_ahb_clk.common.hw;
static SUNXI_CCU_MP_DATA_WITH_MUX(r_apb0_clk, "r-apb0",
r_ahb_apb0_parents, 0x00c,
0, 5, /* M */
8, 2, /* P */
24, 3, /* mux */
0);
static const struct clk_hw *r_apb0_hw = &r_apb0_clk.common.hw;
static SUNXI_CCU_GATE_HWS(bus_r_timer_clk, "bus-r-timer", &r_apb0_hw,
0x11c, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_r_twd_clk, "bus-r-twd", &r_apb0_hw,
0x12c, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_r_ppu_clk, "bus-r-ppu", &r_apb0_hw,
0x1ac, BIT(0), 0);
static const struct clk_parent_data r_ir_rx_parents[] = {
{ .fw_name = "losc" },
{ .fw_name = "hosc" },
};
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_ir_rx_clk, "r-ir-rx",
r_ir_rx_parents, 0x1c0,
0, 5, /* M */
8, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE_HWS(bus_r_ir_rx_clk, "bus-r-ir-rx", &r_apb0_hw,
0x1cc, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_r_rtc_clk, "bus-r-rtc", &r_ahb_hw,
0x20c, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_r_cpucfg_clk, "bus-r-cpucfg", &r_apb0_hw,
0x22c, BIT(0), 0);
static struct ccu_common *sun20i_d1_r_ccu_clks[] = {
&r_ahb_clk.common,
&r_apb0_clk.common,
&bus_r_timer_clk.common,
&bus_r_twd_clk.common,
&bus_r_ppu_clk.common,
&r_ir_rx_clk.common,
&bus_r_ir_rx_clk.common,
&bus_r_rtc_clk.common,
&bus_r_cpucfg_clk.common,
};
static struct clk_hw_onecell_data sun20i_d1_r_hw_clks = {
.num = CLK_NUMBER,
.hws = {
[CLK_R_AHB] = &r_ahb_clk.common.hw,
[CLK_R_APB0] = &r_apb0_clk.common.hw,
[CLK_BUS_R_TIMER] = &bus_r_timer_clk.common.hw,
[CLK_BUS_R_TWD] = &bus_r_twd_clk.common.hw,
[CLK_BUS_R_PPU] = &bus_r_ppu_clk.common.hw,
[CLK_R_IR_RX] = &r_ir_rx_clk.common.hw,
[CLK_BUS_R_IR_RX] = &bus_r_ir_rx_clk.common.hw,
[CLK_BUS_R_RTC] = &bus_r_rtc_clk.common.hw,
[CLK_BUS_R_CPUCFG] = &bus_r_cpucfg_clk.common.hw,
},
};
static struct ccu_reset_map sun20i_d1_r_ccu_resets[] = {
[RST_BUS_R_TIMER] = { 0x11c, BIT(16) },
[RST_BUS_R_TWD] = { 0x12c, BIT(16) },
[RST_BUS_R_PPU] = { 0x1ac, BIT(16) },
[RST_BUS_R_IR_RX] = { 0x1cc, BIT(16) },
[RST_BUS_R_RTC] = { 0x20c, BIT(16) },
[RST_BUS_R_CPUCFG] = { 0x22c, BIT(16) },
};
static const struct sunxi_ccu_desc sun20i_d1_r_ccu_desc = {
.ccu_clks = sun20i_d1_r_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun20i_d1_r_ccu_clks),
.hw_clks = &sun20i_d1_r_hw_clks,
.resets = sun20i_d1_r_ccu_resets,
.num_resets = ARRAY_SIZE(sun20i_d1_r_ccu_resets),
};
static int sun20i_d1_r_ccu_probe(struct platform_device *pdev)
{
void __iomem *reg;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun20i_d1_r_ccu_desc);
}
static const struct of_device_id sun20i_d1_r_ccu_ids[] = {
{ .compatible = "allwinner,sun20i-d1-r-ccu" },
{ }
};
static struct platform_driver sun20i_d1_r_ccu_driver = {
.probe = sun20i_d1_r_ccu_probe,
.driver = {
.name = "sun20i-d1-r-ccu",
.suppress_bind_attrs = true,
.of_match_table = sun20i_d1_r_ccu_ids,
},
};
module_platform_driver(sun20i_d1_r_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun20i-d1-r.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Maxime Ripard
* Maxime Ripard <[email protected]>
*/
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/reset-controller.h>
#include "ccu_reset.h"
static int ccu_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct ccu_reset *ccu = rcdev_to_ccu_reset(rcdev);
const struct ccu_reset_map *map = &ccu->reset_map[id];
unsigned long flags;
u32 reg;
spin_lock_irqsave(ccu->lock, flags);
reg = readl(ccu->base + map->reg);
writel(reg & ~map->bit, ccu->base + map->reg);
spin_unlock_irqrestore(ccu->lock, flags);
return 0;
}
static int ccu_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct ccu_reset *ccu = rcdev_to_ccu_reset(rcdev);
const struct ccu_reset_map *map = &ccu->reset_map[id];
unsigned long flags;
u32 reg;
spin_lock_irqsave(ccu->lock, flags);
reg = readl(ccu->base + map->reg);
writel(reg | map->bit, ccu->base + map->reg);
spin_unlock_irqrestore(ccu->lock, flags);
return 0;
}
static int ccu_reset_reset(struct reset_controller_dev *rcdev,
unsigned long id)
{
ccu_reset_assert(rcdev, id);
udelay(10);
ccu_reset_deassert(rcdev, id);
return 0;
}
static int ccu_reset_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct ccu_reset *ccu = rcdev_to_ccu_reset(rcdev);
const struct ccu_reset_map *map = &ccu->reset_map[id];
/*
* The reset control API expects 0 if reset is not asserted,
* which is the opposite of what our hardware uses.
*/
return !(map->bit & readl(ccu->base + map->reg));
}
const struct reset_control_ops ccu_reset_ops = {
.assert = ccu_reset_assert,
.deassert = ccu_reset_deassert,
.reset = ccu_reset_reset,
.status = ccu_reset_status,
};
EXPORT_SYMBOL_NS_GPL(ccu_reset_ops, SUNXI_CCU);
| linux-master | drivers/clk/sunxi-ng/ccu_reset.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Maxime Ripard
* Maxime Ripard <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include "ccu_gate.h"
#include "ccu_nkm.h"
struct _ccu_nkm {
unsigned long n, min_n, max_n;
unsigned long k, min_k, max_k;
unsigned long m, min_m, max_m;
};
static unsigned long ccu_nkm_find_best_with_parent_adj(struct ccu_common *common,
struct clk_hw *parent_hw,
unsigned long *parent, unsigned long rate,
struct _ccu_nkm *nkm)
{
unsigned long best_rate = 0, best_parent_rate = *parent, tmp_parent = *parent;
unsigned long best_n = 0, best_k = 0, best_m = 0;
unsigned long _n, _k, _m;
for (_k = nkm->min_k; _k <= nkm->max_k; _k++) {
for (_n = nkm->min_n; _n <= nkm->max_n; _n++) {
for (_m = nkm->min_m; _m <= nkm->max_m; _m++) {
unsigned long tmp_rate;
tmp_parent = clk_hw_round_rate(parent_hw, rate * _m / (_n * _k));
tmp_rate = tmp_parent * _n * _k / _m;
if (ccu_is_better_rate(common, rate, tmp_rate, best_rate) ||
(tmp_parent == *parent && tmp_rate == best_rate)) {
best_rate = tmp_rate;
best_parent_rate = tmp_parent;
best_n = _n;
best_k = _k;
best_m = _m;
}
}
}
}
nkm->n = best_n;
nkm->k = best_k;
nkm->m = best_m;
*parent = best_parent_rate;
return best_rate;
}
static unsigned long ccu_nkm_find_best(unsigned long parent, unsigned long rate,
struct _ccu_nkm *nkm, struct ccu_common *common)
{
unsigned long best_rate = 0;
unsigned long best_n = 0, best_k = 0, best_m = 0;
unsigned long _n, _k, _m;
for (_k = nkm->min_k; _k <= nkm->max_k; _k++) {
for (_n = nkm->min_n; _n <= nkm->max_n; _n++) {
for (_m = nkm->min_m; _m <= nkm->max_m; _m++) {
unsigned long tmp_rate;
tmp_rate = parent * _n * _k / _m;
if (ccu_is_better_rate(common, rate, tmp_rate, best_rate)) {
best_rate = tmp_rate;
best_n = _n;
best_k = _k;
best_m = _m;
}
}
}
}
nkm->n = best_n;
nkm->k = best_k;
nkm->m = best_m;
return best_rate;
}
static void ccu_nkm_disable(struct clk_hw *hw)
{
struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
return ccu_gate_helper_disable(&nkm->common, nkm->enable);
}
static int ccu_nkm_enable(struct clk_hw *hw)
{
struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
return ccu_gate_helper_enable(&nkm->common, nkm->enable);
}
static int ccu_nkm_is_enabled(struct clk_hw *hw)
{
struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
return ccu_gate_helper_is_enabled(&nkm->common, nkm->enable);
}
static unsigned long ccu_nkm_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
unsigned long n, m, k, rate;
u32 reg;
reg = readl(nkm->common.base + nkm->common.reg);
n = reg >> nkm->n.shift;
n &= (1 << nkm->n.width) - 1;
n += nkm->n.offset;
if (!n)
n++;
k = reg >> nkm->k.shift;
k &= (1 << nkm->k.width) - 1;
k += nkm->k.offset;
if (!k)
k++;
m = reg >> nkm->m.shift;
m &= (1 << nkm->m.width) - 1;
m += nkm->m.offset;
if (!m)
m++;
rate = parent_rate * n * k / m;
if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nkm->fixed_post_div;
return rate;
}
static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
struct clk_hw *parent_hw,
unsigned long *parent_rate,
unsigned long rate,
void *data)
{
struct ccu_nkm *nkm = data;
struct _ccu_nkm _nkm;
_nkm.min_n = nkm->n.min ?: 1;
_nkm.max_n = nkm->n.max ?: 1 << nkm->n.width;
_nkm.min_k = nkm->k.min ?: 1;
_nkm.max_k = nkm->k.max ?: 1 << nkm->k.width;
_nkm.min_m = 1;
_nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate *= nkm->fixed_post_div;
if (!clk_hw_can_set_rate_parent(&nkm->common.hw))
rate = ccu_nkm_find_best(*parent_rate, rate, &_nkm, &nkm->common);
else
rate = ccu_nkm_find_best_with_parent_adj(&nkm->common, parent_hw, parent_rate, rate,
&_nkm);
if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nkm->fixed_post_div;
return rate;
}
static int ccu_nkm_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
return ccu_mux_helper_determine_rate(&nkm->common, &nkm->mux,
req, ccu_nkm_round_rate, nkm);
}
static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
struct _ccu_nkm _nkm;
unsigned long flags;
u32 reg;
if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate *= nkm->fixed_post_div;
_nkm.min_n = nkm->n.min ?: 1;
_nkm.max_n = nkm->n.max ?: 1 << nkm->n.width;
_nkm.min_k = nkm->k.min ?: 1;
_nkm.max_k = nkm->k.max ?: 1 << nkm->k.width;
_nkm.min_m = 1;
_nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
ccu_nkm_find_best(parent_rate, rate, &_nkm, &nkm->common);
spin_lock_irqsave(nkm->common.lock, flags);
reg = readl(nkm->common.base + nkm->common.reg);
reg &= ~GENMASK(nkm->n.width + nkm->n.shift - 1, nkm->n.shift);
reg &= ~GENMASK(nkm->k.width + nkm->k.shift - 1, nkm->k.shift);
reg &= ~GENMASK(nkm->m.width + nkm->m.shift - 1, nkm->m.shift);
reg |= (_nkm.n - nkm->n.offset) << nkm->n.shift;
reg |= (_nkm.k - nkm->k.offset) << nkm->k.shift;
reg |= (_nkm.m - nkm->m.offset) << nkm->m.shift;
writel(reg, nkm->common.base + nkm->common.reg);
spin_unlock_irqrestore(nkm->common.lock, flags);
ccu_helper_wait_for_lock(&nkm->common, nkm->lock);
return 0;
}
static u8 ccu_nkm_get_parent(struct clk_hw *hw)
{
struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
return ccu_mux_helper_get_parent(&nkm->common, &nkm->mux);
}
static int ccu_nkm_set_parent(struct clk_hw *hw, u8 index)
{
struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
return ccu_mux_helper_set_parent(&nkm->common, &nkm->mux, index);
}
const struct clk_ops ccu_nkm_ops = {
.disable = ccu_nkm_disable,
.enable = ccu_nkm_enable,
.is_enabled = ccu_nkm_is_enabled,
.get_parent = ccu_nkm_get_parent,
.set_parent = ccu_nkm_set_parent,
.determine_rate = ccu_nkm_determine_rate,
.recalc_rate = ccu_nkm_recalc_rate,
.set_rate = ccu_nkm_set_rate,
};
EXPORT_SYMBOL_NS_GPL(ccu_nkm_ops, SUNXI_CCU);
| linux-master | drivers/clk/sunxi-ng/ccu_nkm.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2017 Icenowy Zheng <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu_mult.h"
#include "ccu_nk.h"
#include "ccu_nkm.h"
#include "ccu_nkmp.h"
#include "ccu_nm.h"
#include "ccu-sun50i-h6.h"
/*
* The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
* P should only be used for output frequencies lower than 288 MHz.
*
* For now we can just model it as a multiplier clock, and force P to /1.
*
* The M factor is present in the register's description, but not in the
* frequency formula, and it's documented as "M is only used for backdoor
* testing", so it's not modelled and then force to 0.
*/
#define SUN50I_H6_PLL_CPUX_REG 0x000
static struct ccu_mult pll_cpux_clk = {
.enable = BIT(31),
.lock = BIT(28),
.mult = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.common = {
.reg = 0x000,
.hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
&ccu_mult_ops,
CLK_SET_RATE_UNGATE),
},
};
/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
#define SUN50I_H6_PLL_DDR0_REG 0x010
static struct ccu_nkmp pll_ddr0_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
.common = {
.reg = 0x010,
.hw.init = CLK_HW_INIT("pll-ddr0", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
#define SUN50I_H6_PLL_PERIPH0_REG 0x020
static struct ccu_nkmp pll_periph0_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
.fixed_post_div = 4,
.common = {
.reg = 0x020,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
#define SUN50I_H6_PLL_PERIPH1_REG 0x028
static struct ccu_nkmp pll_periph1_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
.fixed_post_div = 4,
.common = {
.reg = 0x028,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
/* For GPU PLL, using an output divider for DFS causes system to fail */
#define SUN50I_H6_PLL_GPU_REG 0x030
static struct ccu_nkmp pll_gpu_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.common = {
.reg = 0x030,
.hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
/*
* For Video PLLs, the output divider is described as "used for testing"
* in the user manual. So it's not modelled and forced to 0.
*/
#define SUN50I_H6_PLL_VIDEO0_REG 0x040
static struct ccu_nm pll_video0_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.fixed_post_div = 4,
.min_rate = 288000000,
.max_rate = 2400000000UL,
.common = {
.reg = 0x040,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-video0", "osc24M",
&ccu_nm_ops,
CLK_SET_RATE_UNGATE),
},
};
#define SUN50I_H6_PLL_VIDEO1_REG 0x048
static struct ccu_nm pll_video1_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.fixed_post_div = 4,
.min_rate = 288000000,
.max_rate = 2400000000UL,
.common = {
.reg = 0x048,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-video1", "osc24M",
&ccu_nm_ops,
CLK_SET_RATE_UNGATE),
},
};
#define SUN50I_H6_PLL_VE_REG 0x058
static struct ccu_nkmp pll_ve_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
.common = {
.reg = 0x058,
.hw.init = CLK_HW_INIT("pll-ve", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
#define SUN50I_H6_PLL_DE_REG 0x060
static struct ccu_nkmp pll_de_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
.common = {
.reg = 0x060,
.hw.init = CLK_HW_INIT("pll-de", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
#define SUN50I_H6_PLL_HSIC_REG 0x070
static struct ccu_nkmp pll_hsic_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
.common = {
.reg = 0x070,
.hw.init = CLK_HW_INIT("pll-hsic", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
/*
* The Audio PLL is supposed to have 3 outputs: 2 fixed factors from
* the base (2x and 4x), and one variable divider (the one true pll audio).
*
* We don't have any need for the variable divider for now, so we just
* hardcode it to match with the clock names.
*/
#define SUN50I_H6_PLL_AUDIO_REG 0x078
static struct ccu_sdm_setting pll_audio_sdm_table[] = {
{ .rate = 541900800, .pattern = 0xc001288d, .m = 1, .n = 22 },
{ .rate = 589824000, .pattern = 0xc00126e9, .m = 1, .n = 24 },
};
static struct ccu_nm pll_audio_base_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table,
BIT(24), 0x178, BIT(31)),
.common = {
.features = CCU_FEATURE_SIGMA_DELTA_MOD,
.reg = 0x078,
.hw.init = CLK_HW_INIT("pll-audio-base", "osc24M",
&ccu_nm_ops,
CLK_SET_RATE_UNGATE),
},
};
static const char * const cpux_parents[] = { "osc24M", "osc32k",
"iosc", "pll-cpux" };
static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
0x500, 24, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x500, 0, 2, 0);
static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0);
static const char * const psi_ahb1_ahb2_parents[] = { "osc24M", "osc32k",
"iosc", "pll-periph0" };
static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
psi_ahb1_ahb2_parents,
0x510,
0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
static const char * const ahb3_apb1_apb2_parents[] = { "osc24M", "osc32k",
"psi-ahb1-ahb2",
"pll-periph0" };
static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c,
0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520,
0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
"pll-ddr0", "pll-periph0-4x" };
static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x540,
0, 3, /* M */
24, 2, /* mux */
BIT(31), /* gate */
CLK_IS_CRITICAL);
static const char * const de_parents[] = { "pll-de", "pll-periph0-2x" };
static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 0x600,
0, 4, /* M */
24, 1, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
0x60c, BIT(0), 0);
static const char * const deinterlace_parents[] = { "pll-periph0",
"pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace",
deinterlace_parents,
0x620,
0, 4, /* M */
24, 1, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2",
0x62c, BIT(0), 0);
/* Keep GPU_CLK divider const to avoid DFS instability. */
static const char * const gpu_parents[] = { "pll-gpu" };
static SUNXI_CCU_MUX_WITH_GATE(gpu_clk, "gpu", gpu_parents, 0x670,
24, 1, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
0x67c, BIT(0), 0);
/* Also applies to EMCE */
static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x" };
static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
0, 4, /* M */
8, 2, /* N */
24, 1, /* mux */
BIT(31),/* gate */
0);
static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
0x68c, BIT(0), 0);
static const char * const ve_parents[] = { "pll-ve" };
static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
0, 3, /* M */
24, 1, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
0x69c, BIT(0), 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(emce_clk, "emce", ce_parents, 0x6b0,
0, 4, /* M */
8, 2, /* N */
24, 1, /* mux */
BIT(31),/* gate */
0);
static SUNXI_CCU_GATE(bus_emce_clk, "bus-emce", "psi-ahb1-ahb2",
0x6bc, BIT(0), 0);
static const char * const vp9_parents[] = { "pll-ve", "pll-periph0-2x" };
static SUNXI_CCU_M_WITH_MUX_GATE(vp9_clk, "vp9", vp9_parents, 0x6c0,
0, 3, /* M */
24, 1, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(bus_vp9_clk, "bus-vp9", "psi-ahb1-ahb2",
0x6cc, BIT(0), 0);
static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
0x70c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "psi-ahb1-ahb2",
0x71c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "psi-ahb1-ahb2",
0x72c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2",
0x73c, BIT(0), 0);
static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x740, BIT(31), 0);
static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2",
0x78c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2",
0x79c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0);
static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0);
static const char * const dram_parents[] = { "pll-ddr0" };
static struct ccu_div dram_clk = {
.div = _SUNXI_CCU_DIV(0, 2),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0x800,
.hw.init = CLK_HW_INIT_PARENTS("dram",
dram_parents,
&ccu_div_ops,
CLK_IS_CRITICAL),
},
};
static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus",
0x804, BIT(0), 0);
static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus",
0x804, BIT(1), 0);
static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus",
0x804, BIT(2), 0);
static SUNXI_CCU_GATE(mbus_ts_clk, "mbus-ts", "mbus",
0x804, BIT(3), 0);
static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus",
0x804, BIT(5), 0);
static SUNXI_CCU_GATE(mbus_csi_clk, "mbus-csi", "mbus",
0x804, BIT(8), 0);
static SUNXI_CCU_GATE(mbus_deinterlace_clk, "mbus-deinterlace", "mbus",
0x804, BIT(11), 0);
static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2",
0x80c, BIT(0), CLK_IS_CRITICAL);
static const char * const nand_spi_parents[] = { "osc24M", "pll-periph0",
"pll-periph1", "pll-periph0-2x",
"pll-periph1-2x" };
static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", nand_spi_parents, 0x810,
0, 4, /* M */
8, 2, /* N */
24, 3, /* mux */
BIT(31),/* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", nand_spi_parents, 0x814,
0, 4, /* M */
8, 2, /* N */
24, 3, /* mux */
BIT(31),/* gate */
0);
static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0);
static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x",
"pll-periph1-2x" };
static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830,
0, 4, /* M */
8, 2, /* N */
24, 2, /* mux */
BIT(31), /* gate */
2, /* post-div */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
0, 4, /* M */
8, 2, /* N */
24, 2, /* mux */
BIT(31), /* gate */
2, /* post-div */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838,
0, 4, /* M */
8, 2, /* N */
24, 2, /* mux */
BIT(31), /* gate */
2, /* post-div */
0);
static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0);
static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0);
static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0);
static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0);
static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0);
static SUNXI_CCU_GATE(bus_scr0_clk, "bus-scr0", "apb2", 0x93c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_scr1_clk, "bus-scr1", "apb2", 0x93c, BIT(1), 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", nand_spi_parents, 0x940,
0, 4, /* M */
8, 2, /* N */
24, 3, /* mux */
BIT(31),/* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", nand_spi_parents, 0x944,
0, 4, /* M */
8, 2, /* N */
24, 3, /* mux */
BIT(31),/* gate */
0);
static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb3", 0x97c, BIT(0), 0);
static const char * const ts_parents[] = { "osc24M", "pll-periph0" };
static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x9b0,
0, 4, /* M */
8, 2, /* N */
24, 1, /* mux */
BIT(31),/* gate */
0);
static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0);
static const char * const ir_tx_parents[] = { "osc32k", "osc24M" };
static SUNXI_CCU_MP_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_tx_parents, 0x9c0,
0, 4, /* M */
8, 2, /* N */
24, 1, /* mux */
BIT(31),/* gate */
0);
static SUNXI_CCU_GATE(bus_ir_tx_clk, "bus-ir-tx", "apb1", 0x9cc, BIT(0), 0);
static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
static const char * const audio_parents[] = { "pll-audio", "pll-audio-2x", "pll-audio-4x" };
static struct ccu_div i2s3_clk = {
.enable = BIT(31),
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0xa0c,
.hw.init = CLK_HW_INIT_PARENTS("i2s3",
audio_parents,
&ccu_div_ops,
CLK_SET_RATE_PARENT),
},
};
static struct ccu_div i2s0_clk = {
.enable = BIT(31),
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0xa10,
.hw.init = CLK_HW_INIT_PARENTS("i2s0",
audio_parents,
&ccu_div_ops,
CLK_SET_RATE_PARENT),
},
};
static struct ccu_div i2s1_clk = {
.enable = BIT(31),
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0xa14,
.hw.init = CLK_HW_INIT_PARENTS("i2s1",
audio_parents,
&ccu_div_ops,
CLK_SET_RATE_PARENT),
},
};
static struct ccu_div i2s2_clk = {
.enable = BIT(31),
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0xa18,
.hw.init = CLK_HW_INIT_PARENTS("i2s2",
audio_parents,
&ccu_div_ops,
CLK_SET_RATE_PARENT),
},
};
static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 0xa1c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 0xa1c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 0xa1c, BIT(2), 0);
static SUNXI_CCU_GATE(bus_i2s3_clk, "bus-i2s3", "apb1", 0xa1c, BIT(3), 0);
static struct ccu_div spdif_clk = {
.enable = BIT(31),
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0xa20,
.hw.init = CLK_HW_INIT_PARENTS("spdif",
audio_parents,
&ccu_div_ops,
0),
},
};
static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0);
static struct ccu_div dmic_clk = {
.enable = BIT(31),
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0xa40,
.hw.init = CLK_HW_INIT_PARENTS("dmic",
audio_parents,
&ccu_div_ops,
0),
},
};
static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0);
static struct ccu_div audio_hub_clk = {
.enable = BIT(31),
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0xa60,
.hw.init = CLK_HW_INIT_PARENTS("audio-hub",
audio_parents,
&ccu_div_ops,
0),
},
};
static SUNXI_CCU_GATE(bus_audio_hub_clk, "bus-audio-hub", "apb1", 0xa6c, BIT(0), 0);
/*
* There are OHCI 12M clock source selection bits for 2 USB 2.0 ports.
* We will force them to 0 (12M divided from 48M).
*/
#define SUN50I_H6_USB0_CLK_REG 0xa70
#define SUN50I_H6_USB3_CLK_REG 0xa7c
static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0);
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0xa70, BIT(29), 0);
static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 0xa74, BIT(29), 0);
static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc12M", 0xa7c, BIT(31), 0);
static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc12M", 0xa7c, BIT(29), 0);
static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M", 0xa7c, BIT(27), 0);
static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", 0xa7c, BIT(26), 0);
static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb3", 0xa8c, BIT(3), 0);
static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0);
static SUNXI_CCU_GATE(bus_xhci_clk, "bus-xhci", "ahb3", 0xa8c, BIT(5), 0);
static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb3", 0xa8c, BIT(7), 0);
static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0);
static struct clk_fixed_factor pll_periph0_4x_clk;
static CLK_FIXED_FACTOR_HW(pcie_ref_100m_clk, "pcie-ref-100M",
&pll_periph0_4x_clk.hw, 24, 1, 0);
static SUNXI_CCU_GATE(pcie_ref_clk, "pcie-ref", "pcie-ref-100M",
0xab0, BIT(31), 0);
static SUNXI_CCU_GATE(pcie_ref_out_clk, "pcie-ref-out", "pcie-ref",
0xab0, BIT(30), 0);
static SUNXI_CCU_M_WITH_GATE(pcie_maxi_clk, "pcie-maxi",
"pll-periph0", 0xab4,
0, 4, /* M */
BIT(31), /* gate */
0);
static SUNXI_CCU_M_WITH_GATE(pcie_aux_clk, "pcie-aux", "osc24M", 0xab8,
0, 5, /* M */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(bus_pcie_clk, "bus-pcie", "psi-ahb1-ahb2",
0xabc, BIT(0), 0);
static const char * const hdmi_parents[] = { "pll-video0", "pll-video1",
"pll-video1-4x" };
static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 0xb00,
0, 4, /* M */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0xb04, BIT(31), 0);
static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" };
static const struct ccu_mux_fixed_prediv hdmi_cec_predivs[] = {
{ .index = 1, .div = 36621 },
};
#define SUN50I_H6_HDMI_CEC_CLK_REG 0xb10
static struct ccu_mux hdmi_cec_clk = {
.enable = BIT(31),
.mux = {
.shift = 24,
.width = 2,
.fixed_predivs = hdmi_cec_predivs,
.n_predivs = ARRAY_SIZE(hdmi_cec_predivs),
},
.common = {
.reg = 0xb10,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("hdmi-cec",
hdmi_cec_parents,
&ccu_mux_ops,
0),
},
};
static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb3", 0xb1c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb3",
0xb5c, BIT(0), 0);
static const char * const tcon_lcd0_parents[] = { "pll-video0",
"pll-video0-4x",
"pll-video1" };
static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0",
tcon_lcd0_parents, 0xb60,
24, 3, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3",
0xb7c, BIT(0), 0);
static const char * const tcon_tv0_parents[] = { "pll-video0",
"pll-video0-4x",
"pll-video1",
"pll-video1-4x" };
static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0",
tcon_tv0_parents, 0xb80,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3",
0xb9c, BIT(0), 0);
static SUNXI_CCU_GATE(csi_cci_clk, "csi-cci", "osc24M", 0xc00, BIT(0), 0);
static const char * const csi_top_parents[] = { "pll-video0", "pll-ve",
"pll-periph0" };
static const u8 csi_top_table[] = { 0, 2, 3 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_top_clk, "csi-top",
csi_top_parents, csi_top_table, 0xc04,
0, 4, /* M */
24, 3, /* mux */
BIT(31), /* gate */
0);
static const char * const csi_mclk_parents[] = { "osc24M", "pll-video0",
"pll-periph0", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk",
csi_mclk_parents, 0xc08,
0, 5, /* M */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb3", 0xc2c, BIT(0), 0);
static const char * const hdcp_parents[] = { "pll-periph0", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(hdcp_clk, "hdcp", hdcp_parents, 0xc40,
0, 4, /* M */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(bus_hdcp_clk, "bus-hdcp", "ahb3", 0xc4c, BIT(0), 0);
/* Fixed factor clocks */
static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
static const struct clk_hw *clk_parent_pll_audio[] = {
&pll_audio_base_clk.common.hw
};
/*
* The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200
* rates can be set exactly in conjunction with sigma-delta modulation.
*/
static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
clk_parent_pll_audio,
24, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
clk_parent_pll_audio,
4, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
clk_parent_pll_audio,
2, 1, CLK_SET_RATE_PARENT);
static const struct clk_hw *pll_periph0_parents[] = {
&pll_periph0_clk.common.hw
};
static CLK_FIXED_FACTOR_HWS(pll_periph0_4x_clk, "pll-periph0-4x",
pll_periph0_parents,
1, 4, 0);
static CLK_FIXED_FACTOR_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
pll_periph0_parents,
1, 2, 0);
static const struct clk_hw *pll_periph1_parents[] = {
&pll_periph1_clk.common.hw
};
static CLK_FIXED_FACTOR_HWS(pll_periph1_4x_clk, "pll-periph1-4x",
pll_periph1_parents,
1, 4, 0);
static CLK_FIXED_FACTOR_HWS(pll_periph1_2x_clk, "pll-periph1-2x",
pll_periph1_parents,
1, 2, 0);
static CLK_FIXED_FACTOR_HW(pll_video0_4x_clk, "pll-video0-4x",
&pll_video0_clk.common.hw,
1, 4, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HW(pll_video1_4x_clk, "pll-video1-4x",
&pll_video1_clk.common.hw,
1, 4, CLK_SET_RATE_PARENT);
static struct ccu_common *sun50i_h6_ccu_clks[] = {
&pll_cpux_clk.common,
&pll_ddr0_clk.common,
&pll_periph0_clk.common,
&pll_periph1_clk.common,
&pll_gpu_clk.common,
&pll_video0_clk.common,
&pll_video1_clk.common,
&pll_ve_clk.common,
&pll_de_clk.common,
&pll_hsic_clk.common,
&pll_audio_base_clk.common,
&cpux_clk.common,
&axi_clk.common,
&cpux_apb_clk.common,
&psi_ahb1_ahb2_clk.common,
&ahb3_clk.common,
&apb1_clk.common,
&apb2_clk.common,
&mbus_clk.common,
&de_clk.common,
&bus_de_clk.common,
&deinterlace_clk.common,
&bus_deinterlace_clk.common,
&gpu_clk.common,
&bus_gpu_clk.common,
&ce_clk.common,
&bus_ce_clk.common,
&ve_clk.common,
&bus_ve_clk.common,
&emce_clk.common,
&bus_emce_clk.common,
&vp9_clk.common,
&bus_vp9_clk.common,
&bus_dma_clk.common,
&bus_msgbox_clk.common,
&bus_spinlock_clk.common,
&bus_hstimer_clk.common,
&avs_clk.common,
&bus_dbg_clk.common,
&bus_psi_clk.common,
&bus_pwm_clk.common,
&bus_iommu_clk.common,
&dram_clk.common,
&mbus_dma_clk.common,
&mbus_ve_clk.common,
&mbus_ce_clk.common,
&mbus_ts_clk.common,
&mbus_nand_clk.common,
&mbus_csi_clk.common,
&mbus_deinterlace_clk.common,
&bus_dram_clk.common,
&nand0_clk.common,
&nand1_clk.common,
&bus_nand_clk.common,
&mmc0_clk.common,
&mmc1_clk.common,
&mmc2_clk.common,
&bus_mmc0_clk.common,
&bus_mmc1_clk.common,
&bus_mmc2_clk.common,
&bus_uart0_clk.common,
&bus_uart1_clk.common,
&bus_uart2_clk.common,
&bus_uart3_clk.common,
&bus_i2c0_clk.common,
&bus_i2c1_clk.common,
&bus_i2c2_clk.common,
&bus_i2c3_clk.common,
&bus_scr0_clk.common,
&bus_scr1_clk.common,
&spi0_clk.common,
&spi1_clk.common,
&bus_spi0_clk.common,
&bus_spi1_clk.common,
&bus_emac_clk.common,
&ts_clk.common,
&bus_ts_clk.common,
&ir_tx_clk.common,
&bus_ir_tx_clk.common,
&bus_ths_clk.common,
&i2s3_clk.common,
&i2s0_clk.common,
&i2s1_clk.common,
&i2s2_clk.common,
&bus_i2s0_clk.common,
&bus_i2s1_clk.common,
&bus_i2s2_clk.common,
&bus_i2s3_clk.common,
&spdif_clk.common,
&bus_spdif_clk.common,
&dmic_clk.common,
&bus_dmic_clk.common,
&audio_hub_clk.common,
&bus_audio_hub_clk.common,
&usb_ohci0_clk.common,
&usb_phy0_clk.common,
&usb_phy1_clk.common,
&usb_ohci3_clk.common,
&usb_phy3_clk.common,
&usb_hsic_12m_clk.common,
&usb_hsic_clk.common,
&bus_ohci0_clk.common,
&bus_ohci3_clk.common,
&bus_ehci0_clk.common,
&bus_xhci_clk.common,
&bus_ehci3_clk.common,
&bus_otg_clk.common,
&pcie_ref_clk.common,
&pcie_ref_out_clk.common,
&pcie_maxi_clk.common,
&pcie_aux_clk.common,
&bus_pcie_clk.common,
&hdmi_clk.common,
&hdmi_slow_clk.common,
&hdmi_cec_clk.common,
&bus_hdmi_clk.common,
&bus_tcon_top_clk.common,
&tcon_lcd0_clk.common,
&bus_tcon_lcd0_clk.common,
&tcon_tv0_clk.common,
&bus_tcon_tv0_clk.common,
&csi_cci_clk.common,
&csi_top_clk.common,
&csi_mclk_clk.common,
&bus_csi_clk.common,
&hdcp_clk.common,
&bus_hdcp_clk.common,
};
static struct clk_hw_onecell_data sun50i_h6_hw_clks = {
.hws = {
[CLK_OSC12M] = &osc12M_clk.hw,
[CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
[CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
[CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
[CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
[CLK_PLL_PERIPH0_4X] = &pll_periph0_4x_clk.hw,
[CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
[CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
[CLK_PLL_PERIPH1_4X] = &pll_periph1_4x_clk.hw,
[CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
[CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
[CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.hw,
[CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
[CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.hw,
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
[CLK_PLL_DE] = &pll_de_clk.common.hw,
[CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
[CLK_CPUX] = &cpux_clk.common.hw,
[CLK_AXI] = &axi_clk.common.hw,
[CLK_CPUX_APB] = &cpux_apb_clk.common.hw,
[CLK_PSI_AHB1_AHB2] = &psi_ahb1_ahb2_clk.common.hw,
[CLK_AHB3] = &ahb3_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_APB2] = &apb2_clk.common.hw,
[CLK_MBUS] = &mbus_clk.common.hw,
[CLK_DE] = &de_clk.common.hw,
[CLK_BUS_DE] = &bus_de_clk.common.hw,
[CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
[CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
[CLK_GPU] = &gpu_clk.common.hw,
[CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
[CLK_CE] = &ce_clk.common.hw,
[CLK_BUS_CE] = &bus_ce_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_BUS_VE] = &bus_ve_clk.common.hw,
[CLK_EMCE] = &emce_clk.common.hw,
[CLK_BUS_EMCE] = &bus_emce_clk.common.hw,
[CLK_VP9] = &vp9_clk.common.hw,
[CLK_BUS_VP9] = &bus_vp9_clk.common.hw,
[CLK_BUS_DMA] = &bus_dma_clk.common.hw,
[CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
[CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
[CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
[CLK_BUS_PSI] = &bus_psi_clk.common.hw,
[CLK_BUS_PWM] = &bus_pwm_clk.common.hw,
[CLK_BUS_IOMMU] = &bus_iommu_clk.common.hw,
[CLK_DRAM] = &dram_clk.common.hw,
[CLK_MBUS_DMA] = &mbus_dma_clk.common.hw,
[CLK_MBUS_VE] = &mbus_ve_clk.common.hw,
[CLK_MBUS_CE] = &mbus_ce_clk.common.hw,
[CLK_MBUS_TS] = &mbus_ts_clk.common.hw,
[CLK_MBUS_NAND] = &mbus_nand_clk.common.hw,
[CLK_MBUS_CSI] = &mbus_csi_clk.common.hw,
[CLK_MBUS_DEINTERLACE] = &mbus_deinterlace_clk.common.hw,
[CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
[CLK_NAND0] = &nand0_clk.common.hw,
[CLK_NAND1] = &nand1_clk.common.hw,
[CLK_BUS_NAND] = &bus_nand_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
[CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
[CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
[CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
[CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
[CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
[CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
[CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
[CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
[CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
[CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
[CLK_BUS_SCR0] = &bus_scr0_clk.common.hw,
[CLK_BUS_SCR1] = &bus_scr1_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
[CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
[CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
[CLK_TS] = &ts_clk.common.hw,
[CLK_BUS_TS] = &bus_ts_clk.common.hw,
[CLK_IR_TX] = &ir_tx_clk.common.hw,
[CLK_BUS_IR_TX] = &bus_ir_tx_clk.common.hw,
[CLK_BUS_THS] = &bus_ths_clk.common.hw,
[CLK_I2S3] = &i2s3_clk.common.hw,
[CLK_I2S0] = &i2s0_clk.common.hw,
[CLK_I2S1] = &i2s1_clk.common.hw,
[CLK_I2S2] = &i2s2_clk.common.hw,
[CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
[CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
[CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
[CLK_BUS_I2S3] = &bus_i2s3_clk.common.hw,
[CLK_SPDIF] = &spdif_clk.common.hw,
[CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
[CLK_DMIC] = &dmic_clk.common.hw,
[CLK_BUS_DMIC] = &bus_dmic_clk.common.hw,
[CLK_AUDIO_HUB] = &audio_hub_clk.common.hw,
[CLK_BUS_AUDIO_HUB] = &bus_audio_hub_clk.common.hw,
[CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
[CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
[CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw,
[CLK_USB_PHY3] = &usb_phy3_clk.common.hw,
[CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw,
[CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
[CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
[CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw,
[CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
[CLK_BUS_XHCI] = &bus_xhci_clk.common.hw,
[CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw,
[CLK_BUS_OTG] = &bus_otg_clk.common.hw,
[CLK_PCIE_REF_100M] = &pcie_ref_100m_clk.hw,
[CLK_PCIE_REF] = &pcie_ref_clk.common.hw,
[CLK_PCIE_REF_OUT] = &pcie_ref_out_clk.common.hw,
[CLK_PCIE_MAXI] = &pcie_maxi_clk.common.hw,
[CLK_PCIE_AUX] = &pcie_aux_clk.common.hw,
[CLK_BUS_PCIE] = &bus_pcie_clk.common.hw,
[CLK_HDMI] = &hdmi_clk.common.hw,
[CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw,
[CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw,
[CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
[CLK_BUS_TCON_TOP] = &bus_tcon_top_clk.common.hw,
[CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw,
[CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw,
[CLK_TCON_TV0] = &tcon_tv0_clk.common.hw,
[CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw,
[CLK_CSI_CCI] = &csi_cci_clk.common.hw,
[CLK_CSI_TOP] = &csi_top_clk.common.hw,
[CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
[CLK_BUS_CSI] = &bus_csi_clk.common.hw,
[CLK_HDCP] = &hdcp_clk.common.hw,
[CLK_BUS_HDCP] = &bus_hdcp_clk.common.hw,
},
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun50i_h6_ccu_resets[] = {
[RST_MBUS] = { 0x540, BIT(30) },
[RST_BUS_DE] = { 0x60c, BIT(16) },
[RST_BUS_DEINTERLACE] = { 0x62c, BIT(16) },
[RST_BUS_GPU] = { 0x67c, BIT(16) },
[RST_BUS_CE] = { 0x68c, BIT(16) },
[RST_BUS_VE] = { 0x69c, BIT(16) },
[RST_BUS_EMCE] = { 0x6bc, BIT(16) },
[RST_BUS_VP9] = { 0x6cc, BIT(16) },
[RST_BUS_DMA] = { 0x70c, BIT(16) },
[RST_BUS_MSGBOX] = { 0x71c, BIT(16) },
[RST_BUS_SPINLOCK] = { 0x72c, BIT(16) },
[RST_BUS_HSTIMER] = { 0x73c, BIT(16) },
[RST_BUS_DBG] = { 0x78c, BIT(16) },
[RST_BUS_PSI] = { 0x79c, BIT(16) },
[RST_BUS_PWM] = { 0x7ac, BIT(16) },
[RST_BUS_IOMMU] = { 0x7bc, BIT(16) },
[RST_BUS_DRAM] = { 0x80c, BIT(16) },
[RST_BUS_NAND] = { 0x82c, BIT(16) },
[RST_BUS_MMC0] = { 0x84c, BIT(16) },
[RST_BUS_MMC1] = { 0x84c, BIT(17) },
[RST_BUS_MMC2] = { 0x84c, BIT(18) },
[RST_BUS_UART0] = { 0x90c, BIT(16) },
[RST_BUS_UART1] = { 0x90c, BIT(17) },
[RST_BUS_UART2] = { 0x90c, BIT(18) },
[RST_BUS_UART3] = { 0x90c, BIT(19) },
[RST_BUS_I2C0] = { 0x91c, BIT(16) },
[RST_BUS_I2C1] = { 0x91c, BIT(17) },
[RST_BUS_I2C2] = { 0x91c, BIT(18) },
[RST_BUS_I2C3] = { 0x91c, BIT(19) },
[RST_BUS_SCR0] = { 0x93c, BIT(16) },
[RST_BUS_SCR1] = { 0x93c, BIT(17) },
[RST_BUS_SPI0] = { 0x96c, BIT(16) },
[RST_BUS_SPI1] = { 0x96c, BIT(17) },
[RST_BUS_EMAC] = { 0x97c, BIT(16) },
[RST_BUS_TS] = { 0x9bc, BIT(16) },
[RST_BUS_IR_TX] = { 0x9cc, BIT(16) },
[RST_BUS_THS] = { 0x9fc, BIT(16) },
[RST_BUS_I2S0] = { 0xa1c, BIT(16) },
[RST_BUS_I2S1] = { 0xa1c, BIT(17) },
[RST_BUS_I2S2] = { 0xa1c, BIT(18) },
[RST_BUS_I2S3] = { 0xa1c, BIT(19) },
[RST_BUS_SPDIF] = { 0xa2c, BIT(16) },
[RST_BUS_DMIC] = { 0xa4c, BIT(16) },
[RST_BUS_AUDIO_HUB] = { 0xa6c, BIT(16) },
[RST_USB_PHY0] = { 0xa70, BIT(30) },
[RST_USB_PHY1] = { 0xa74, BIT(30) },
[RST_USB_PHY3] = { 0xa7c, BIT(30) },
[RST_USB_HSIC] = { 0xa7c, BIT(28) },
[RST_BUS_OHCI0] = { 0xa8c, BIT(16) },
[RST_BUS_OHCI3] = { 0xa8c, BIT(19) },
[RST_BUS_EHCI0] = { 0xa8c, BIT(20) },
[RST_BUS_XHCI] = { 0xa8c, BIT(21) },
[RST_BUS_EHCI3] = { 0xa8c, BIT(23) },
[RST_BUS_OTG] = { 0xa8c, BIT(24) },
[RST_BUS_PCIE] = { 0xabc, BIT(16) },
[RST_PCIE_POWERUP] = { 0xabc, BIT(17) },
[RST_BUS_HDMI] = { 0xb1c, BIT(16) },
[RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) },
[RST_BUS_TCON_TOP] = { 0xb5c, BIT(16) },
[RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) },
[RST_BUS_TCON_TV0] = { 0xb9c, BIT(16) },
[RST_BUS_CSI] = { 0xc2c, BIT(16) },
[RST_BUS_HDCP] = { 0xc4c, BIT(16) },
};
static const struct sunxi_ccu_desc sun50i_h6_ccu_desc = {
.ccu_clks = sun50i_h6_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun50i_h6_ccu_clks),
.hw_clks = &sun50i_h6_hw_clks,
.resets = sun50i_h6_ccu_resets,
.num_resets = ARRAY_SIZE(sun50i_h6_ccu_resets),
};
static const u32 pll_regs[] = {
SUN50I_H6_PLL_CPUX_REG,
SUN50I_H6_PLL_DDR0_REG,
SUN50I_H6_PLL_PERIPH0_REG,
SUN50I_H6_PLL_PERIPH1_REG,
SUN50I_H6_PLL_GPU_REG,
SUN50I_H6_PLL_VIDEO0_REG,
SUN50I_H6_PLL_VIDEO1_REG,
SUN50I_H6_PLL_VE_REG,
SUN50I_H6_PLL_DE_REG,
SUN50I_H6_PLL_HSIC_REG,
SUN50I_H6_PLL_AUDIO_REG,
};
static const u32 pll_video_regs[] = {
SUN50I_H6_PLL_VIDEO0_REG,
SUN50I_H6_PLL_VIDEO1_REG,
};
static const u32 usb2_clk_regs[] = {
SUN50I_H6_USB0_CLK_REG,
SUN50I_H6_USB3_CLK_REG,
};
static int sun50i_h6_ccu_probe(struct platform_device *pdev)
{
void __iomem *reg;
u32 val;
int i;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
/*
* Force PLL_GPU output divider bits to 0 and adjust
* multiplier to sensible default value of 432 MHz.
*/
val = readl(reg + SUN50I_H6_PLL_GPU_REG);
val &= ~(GENMASK(15, 8) | BIT(0));
val |= 17 << 8;
writel(val, reg + SUN50I_H6_PLL_GPU_REG);
/* Force GPU_CLK divider bits to 0 */
val = readl(reg + gpu_clk.common.reg);
val &= ~GENMASK(3, 0);
writel(val, reg + gpu_clk.common.reg);
/* Enable the lock bits on all PLLs */
for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
val = readl(reg + pll_regs[i]);
val |= BIT(29);
writel(val, reg + pll_regs[i]);
}
/*
* Force the output divider of video PLLs to 0.
*
* See the comment before pll-video0 definition for the reason.
*/
for (i = 0; i < ARRAY_SIZE(pll_video_regs); i++) {
val = readl(reg + pll_video_regs[i]);
val &= ~BIT(0);
writel(val, reg + pll_video_regs[i]);
}
/*
* Force OHCI 12M clock sources to 00 (12MHz divided from 48MHz)
*
* This clock mux is still mysterious, and the code just enforces
* it to have a valid clock parent.
*/
for (i = 0; i < ARRAY_SIZE(usb2_clk_regs); i++) {
val = readl(reg + usb2_clk_regs[i]);
val &= ~GENMASK(25, 24);
writel (val, reg + usb2_clk_regs[i]);
}
/*
* Force the post-divider of pll-audio to 12 and the output divider
* of it to 2, so 24576000 and 22579200 rates can be set exactly.
*/
val = readl(reg + SUN50I_H6_PLL_AUDIO_REG);
val &= ~(GENMASK(21, 16) | BIT(0));
writel(val | (11 << 16) | BIT(0), reg + SUN50I_H6_PLL_AUDIO_REG);
/*
* First clock parent (osc32K) is unusable for CEC. But since there
* is no good way to force parent switch (both run with same frequency),
* just set second clock parent here.
*/
val = readl(reg + SUN50I_H6_HDMI_CEC_CLK_REG);
val |= BIT(24);
writel(val, reg + SUN50I_H6_HDMI_CEC_CLK_REG);
return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h6_ccu_desc);
}
static const struct of_device_id sun50i_h6_ccu_ids[] = {
{ .compatible = "allwinner,sun50i-h6-ccu" },
{ }
};
static struct platform_driver sun50i_h6_ccu_driver = {
.probe = sun50i_h6_ccu_probe,
.driver = {
.name = "sun50i-h6-ccu",
.suppress_bind_attrs = true,
.of_match_table = sun50i_h6_ccu_ids,
},
};
module_platform_driver(sun50i_h6_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun50i-h6.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 [email protected]
* Copyright (C) 2021 Samuel Holland <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "../clk.h"
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu_mult.h"
#include "ccu_nk.h"
#include "ccu_nkm.h"
#include "ccu_nkmp.h"
#include "ccu_nm.h"
#include "ccu-sun20i-d1.h"
static const struct clk_parent_data osc24M[] = {
{ .fw_name = "hosc" }
};
/*
* For the CPU PLL, the output divider is described as "only for testing"
* in the user manual. So it's not modelled and forced to 0.
*/
#define SUN20I_D1_PLL_CPUX_REG 0x000
static struct ccu_mult pll_cpux_clk = {
.enable = BIT(27),
.lock = BIT(28),
.mult = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.common = {
.reg = 0x000,
.hw.init = CLK_HW_INIT_PARENTS_DATA("pll-cpux", osc24M,
&ccu_mult_ops,
CLK_SET_RATE_UNGATE),
},
};
/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
#define SUN20I_D1_PLL_DDR0_REG 0x010
static struct ccu_nkmp pll_ddr0_clk = {
.enable = BIT(27),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
.common = {
.reg = 0x010,
.hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ddr0", osc24M,
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
#define SUN20I_D1_PLL_PERIPH0_REG 0x020
static struct ccu_nm pll_periph0_4x_clk = {
.enable = BIT(27),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.common = {
.reg = 0x020,
.hw.init = CLK_HW_INIT_PARENTS_DATA("pll-periph0-4x", osc24M,
&ccu_nm_ops,
CLK_SET_RATE_UNGATE),
},
};
static const struct clk_hw *pll_periph0_4x_hws[] = {
&pll_periph0_4x_clk.common.hw
};
static SUNXI_CCU_M_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
pll_periph0_4x_hws, 0x020, 16, 3, 0);
static SUNXI_CCU_M_HWS(pll_periph0_800M_clk, "pll-periph0-800M",
pll_periph0_4x_hws, 0x020, 20, 3, 0);
static const struct clk_hw *pll_periph0_2x_hws[] = {
&pll_periph0_2x_clk.common.hw
};
static CLK_FIXED_FACTOR_HWS(pll_periph0_clk, "pll-periph0",
pll_periph0_2x_hws, 2, 1, 0);
static const struct clk_hw *pll_periph0_hws[] = { &pll_periph0_clk.hw };
static CLK_FIXED_FACTOR_HWS(pll_periph0_div3_clk, "pll-periph0-div3",
pll_periph0_2x_hws, 6, 1, 0);
/*
* For Video PLLs, the output divider is described as "only for testing"
* in the user manual. So it's not modelled and forced to 0.
*/
#define SUN20I_D1_PLL_VIDEO0_REG 0x040
static struct ccu_nm pll_video0_4x_clk = {
.enable = BIT(27),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.min_rate = 252000000U,
.max_rate = 2400000000U,
.common = {
.reg = 0x040,
.hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video0-4x", osc24M,
&ccu_nm_ops,
CLK_SET_RATE_UNGATE),
},
};
static const struct clk_hw *pll_video0_4x_hws[] = {
&pll_video0_4x_clk.common.hw
};
static CLK_FIXED_FACTOR_HWS(pll_video0_2x_clk, "pll-video0-2x",
pll_video0_4x_hws, 2, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_video0_clk, "pll-video0",
pll_video0_4x_hws, 4, 1, CLK_SET_RATE_PARENT);
#define SUN20I_D1_PLL_VIDEO1_REG 0x048
static struct ccu_nm pll_video1_4x_clk = {
.enable = BIT(27),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.min_rate = 252000000U,
.max_rate = 2400000000U,
.common = {
.reg = 0x048,
.hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video1-4x", osc24M,
&ccu_nm_ops,
CLK_SET_RATE_UNGATE),
},
};
static const struct clk_hw *pll_video1_4x_hws[] = {
&pll_video1_4x_clk.common.hw
};
static CLK_FIXED_FACTOR_HWS(pll_video1_2x_clk, "pll-video1-2x",
pll_video1_4x_hws, 2, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_video1_clk, "pll-video1",
pll_video1_4x_hws, 4, 1, CLK_SET_RATE_PARENT);
#define SUN20I_D1_PLL_VE_REG 0x058
static struct ccu_nkmp pll_ve_clk = {
.enable = BIT(27),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
.common = {
.reg = 0x058,
.hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ve", osc24M,
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
/*
* PLL_AUDIO0 has m0, m1 dividers in addition to the usual N, M factors.
* Since we only need one frequency from this PLL (22.5792 x 4 == 90.3168 MHz),
* ignore them for now. Enforce the default for them, which is m1 = 0, m0 = 0.
* The M factor must be an even number to produce a 50% duty cycle output.
*/
#define SUN20I_D1_PLL_AUDIO0_REG 0x078
static struct ccu_sdm_setting pll_audio0_sdm_table[] = {
{ .rate = 90316800, .pattern = 0xc001288d, .m = 6, .n = 22 },
};
static struct ccu_nm pll_audio0_4x_clk = {
.enable = BIT(27),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(16, 6),
.sdm = _SUNXI_CCU_SDM(pll_audio0_sdm_table, BIT(24),
0x178, BIT(31)),
.min_rate = 180000000U,
.max_rate = 3000000000U,
.common = {
.reg = 0x078,
.features = CCU_FEATURE_SIGMA_DELTA_MOD,
.hw.init = CLK_HW_INIT_PARENTS_DATA("pll-audio0-4x", osc24M,
&ccu_nm_ops,
CLK_SET_RATE_UNGATE),
},
};
static const struct clk_hw *pll_audio0_4x_hws[] = {
&pll_audio0_4x_clk.common.hw
};
static CLK_FIXED_FACTOR_HWS(pll_audio0_2x_clk, "pll-audio0-2x",
pll_audio0_4x_hws, 2, 1, 0);
static CLK_FIXED_FACTOR_HWS(pll_audio0_clk, "pll-audio0",
pll_audio0_4x_hws, 4, 1, 0);
/*
* PLL_AUDIO1 doesn't need Fractional-N. The output is usually 614.4 MHz for
* audio. The ADC or DAC should divide the PLL output further to 24.576 MHz.
*/
#define SUN20I_D1_PLL_AUDIO1_REG 0x080
static struct ccu_nm pll_audio1_clk = {
.enable = BIT(27),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1),
.min_rate = 180000000U,
.max_rate = 3000000000U,
.common = {
.reg = 0x080,
.hw.init = CLK_HW_INIT_PARENTS_DATA("pll-audio1", osc24M,
&ccu_nm_ops,
CLK_SET_RATE_UNGATE),
},
};
static const struct clk_hw *pll_audio1_hws[] = {
&pll_audio1_clk.common.hw
};
static SUNXI_CCU_M_HWS(pll_audio1_div2_clk, "pll-audio1-div2",
pll_audio1_hws, 0x080, 16, 3, 0);
static SUNXI_CCU_M_HWS(pll_audio1_div5_clk, "pll-audio1-div5",
pll_audio1_hws, 0x080, 20, 3, 0);
/*
* The CPUX gate is not modelled - it is in a separate register (0x504)
* and has a special key field. The clock does not need to be ungated anyway.
*/
static const struct clk_parent_data cpux_parents[] = {
{ .fw_name = "hosc" },
{ .fw_name = "losc" },
{ .fw_name = "iosc" },
{ .hw = &pll_cpux_clk.common.hw },
{ .hw = &pll_periph0_clk.hw },
{ .hw = &pll_periph0_2x_clk.common.hw },
{ .hw = &pll_periph0_800M_clk.common.hw },
};
static SUNXI_CCU_MUX_DATA(cpux_clk, "cpux", cpux_parents,
0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
static const struct clk_hw *cpux_hws[] = { &cpux_clk.common.hw };
static SUNXI_CCU_M_HWS(cpux_axi_clk, "cpux-axi",
cpux_hws, 0x500, 0, 2, 0);
static SUNXI_CCU_M_HWS(cpux_apb_clk, "cpux-apb",
cpux_hws, 0x500, 8, 2, 0);
static const struct clk_parent_data psi_ahb_parents[] = {
{ .fw_name = "hosc" },
{ .fw_name = "losc" },
{ .fw_name = "iosc" },
{ .hw = &pll_periph0_clk.hw },
};
static SUNXI_CCU_MP_DATA_WITH_MUX(psi_ahb_clk, "psi-ahb", psi_ahb_parents, 0x510,
0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
static const struct clk_parent_data apb0_apb1_parents[] = {
{ .fw_name = "hosc" },
{ .fw_name = "losc" },
{ .hw = &psi_ahb_clk.common.hw },
{ .hw = &pll_periph0_clk.hw },
};
static SUNXI_CCU_MP_DATA_WITH_MUX(apb0_clk, "apb0", apb0_apb1_parents, 0x520,
0, 5, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
static SUNXI_CCU_MP_DATA_WITH_MUX(apb1_clk, "apb1", apb0_apb1_parents, 0x524,
0, 5, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
static const struct clk_hw *psi_ahb_hws[] = { &psi_ahb_clk.common.hw };
static const struct clk_hw *apb0_hws[] = { &apb0_clk.common.hw };
static const struct clk_hw *apb1_hws[] = { &apb1_clk.common.hw };
static const struct clk_hw *de_di_g2d_parents[] = {
&pll_periph0_2x_clk.common.hw,
&pll_video0_4x_clk.common.hw,
&pll_video1_4x_clk.common.hw,
&pll_audio1_div2_clk.common.hw,
};
static SUNXI_CCU_M_HW_WITH_MUX_GATE(de_clk, "de", de_di_g2d_parents, 0x600,
0, 5, /* M */
24, 3, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE_HWS(bus_de_clk, "bus-de", psi_ahb_hws,
0x60c, BIT(0), 0);
static SUNXI_CCU_M_HW_WITH_MUX_GATE(di_clk, "di", de_di_g2d_parents, 0x620,
0, 5, /* M */
24, 3, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE_HWS(bus_di_clk, "bus-di", psi_ahb_hws,
0x62c, BIT(0), 0);
static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", de_di_g2d_parents, 0x630,
0, 5, /* M */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE_HWS(bus_g2d_clk, "bus-g2d", psi_ahb_hws,
0x63c, BIT(0), 0);
static const struct clk_parent_data ce_parents[] = {
{ .fw_name = "hosc" },
{ .hw = &pll_periph0_2x_clk.common.hw },
{ .hw = &pll_periph0_clk.hw },
};
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE_HWS(bus_ce_clk, "bus-ce", psi_ahb_hws,
0x68c, BIT(0), 0);
static const struct clk_hw *ve_parents[] = {
&pll_ve_clk.common.hw,
&pll_periph0_2x_clk.common.hw,
};
static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
0, 5, /* M */
24, 1, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE_HWS(bus_ve_clk, "bus-ve", psi_ahb_hws,
0x69c, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_dma_clk, "bus-dma", psi_ahb_hws,
0x70c, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_msgbox0_clk, "bus-msgbox0", psi_ahb_hws,
0x71c, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_msgbox1_clk, "bus-msgbox1", psi_ahb_hws,
0x71c, BIT(1), 0);
static SUNXI_CCU_GATE_HWS(bus_msgbox2_clk, "bus-msgbox2", psi_ahb_hws,
0x71c, BIT(2), 0);
static SUNXI_CCU_GATE_HWS(bus_spinlock_clk, "bus-spinlock", psi_ahb_hws,
0x72c, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_hstimer_clk, "bus-hstimer", psi_ahb_hws,
0x73c, BIT(0), 0);
static SUNXI_CCU_GATE_DATA(avs_clk, "avs", osc24M,
0x740, BIT(31), 0);
static SUNXI_CCU_GATE_HWS(bus_dbg_clk, "bus-dbg", psi_ahb_hws,
0x78c, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_pwm_clk, "bus-pwm", apb0_hws,
0x7ac, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_iommu_clk, "bus-iommu", apb0_hws,
0x7bc, BIT(0), 0);
static const struct clk_hw *dram_parents[] = {
&pll_ddr0_clk.common.hw,
&pll_audio1_div2_clk.common.hw,
&pll_periph0_2x_clk.common.hw,
&pll_periph0_800M_clk.common.hw,
};
static SUNXI_CCU_MP_HW_WITH_MUX_GATE(dram_clk, "dram", dram_parents, 0x800,
0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
BIT(31), CLK_IS_CRITICAL);
static CLK_FIXED_FACTOR_HW(mbus_clk, "mbus",
&dram_clk.common.hw, 4, 1, 0);
static const struct clk_hw *mbus_hws[] = { &mbus_clk.hw };
static SUNXI_CCU_GATE_HWS(mbus_dma_clk, "mbus-dma", mbus_hws,
0x804, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(mbus_ve_clk, "mbus-ve", mbus_hws,
0x804, BIT(1), 0);
static SUNXI_CCU_GATE_HWS(mbus_ce_clk, "mbus-ce", mbus_hws,
0x804, BIT(2), 0);
static SUNXI_CCU_GATE_HWS(mbus_tvin_clk, "mbus-tvin", mbus_hws,
0x804, BIT(7), 0);
static SUNXI_CCU_GATE_HWS(mbus_csi_clk, "mbus-csi", mbus_hws,
0x804, BIT(8), 0);
static SUNXI_CCU_GATE_HWS(mbus_g2d_clk, "mbus-g2d", mbus_hws,
0x804, BIT(10), 0);
static SUNXI_CCU_GATE_HWS(mbus_riscv_clk, "mbus-riscv", mbus_hws,
0x804, BIT(11), 0);
static SUNXI_CCU_GATE_HWS(bus_dram_clk, "bus-dram", psi_ahb_hws,
0x80c, BIT(0), CLK_IS_CRITICAL);
static const struct clk_parent_data mmc0_mmc1_parents[] = {
{ .fw_name = "hosc" },
{ .hw = &pll_periph0_clk.hw },
{ .hw = &pll_periph0_2x_clk.common.hw },
{ .hw = &pll_audio1_div2_clk.common.hw },
};
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc0_mmc1_parents, 0x830,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc0_mmc1_parents, 0x834,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static const struct clk_parent_data mmc2_parents[] = {
{ .fw_name = "hosc" },
{ .hw = &pll_periph0_clk.hw },
{ .hw = &pll_periph0_2x_clk.common.hw },
{ .hw = &pll_periph0_800M_clk.common.hw },
{ .hw = &pll_audio1_div2_clk.common.hw },
};
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc2_parents, 0x838,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, "bus-mmc0", psi_ahb_hws,
0x84c, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_mmc1_clk, "bus-mmc1", psi_ahb_hws,
0x84c, BIT(1), 0);
static SUNXI_CCU_GATE_HWS(bus_mmc2_clk, "bus-mmc2", psi_ahb_hws,
0x84c, BIT(2), 0);
static SUNXI_CCU_GATE_HWS(bus_uart0_clk, "bus-uart0", apb1_hws,
0x90c, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_uart1_clk, "bus-uart1", apb1_hws,
0x90c, BIT(1), 0);
static SUNXI_CCU_GATE_HWS(bus_uart2_clk, "bus-uart2", apb1_hws,
0x90c, BIT(2), 0);
static SUNXI_CCU_GATE_HWS(bus_uart3_clk, "bus-uart3", apb1_hws,
0x90c, BIT(3), 0);
static SUNXI_CCU_GATE_HWS(bus_uart4_clk, "bus-uart4", apb1_hws,
0x90c, BIT(4), 0);
static SUNXI_CCU_GATE_HWS(bus_uart5_clk, "bus-uart5", apb1_hws,
0x90c, BIT(5), 0);
static SUNXI_CCU_GATE_HWS(bus_i2c0_clk, "bus-i2c0", apb1_hws,
0x91c, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_i2c1_clk, "bus-i2c1", apb1_hws,
0x91c, BIT(1), 0);
static SUNXI_CCU_GATE_HWS(bus_i2c2_clk, "bus-i2c2", apb1_hws,
0x91c, BIT(2), 0);
static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, "bus-i2c3", apb1_hws,
0x91c, BIT(3), 0);
static SUNXI_CCU_GATE_HWS(bus_can0_clk, "bus-can0", apb1_hws,
0x92c, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_can1_clk, "bus-can1", apb1_hws,
0x92c, BIT(1), 0);
static const struct clk_parent_data spi_parents[] = {
{ .fw_name = "hosc" },
{ .hw = &pll_periph0_clk.hw },
{ .hw = &pll_periph0_2x_clk.common.hw },
{ .hw = &pll_audio1_div2_clk.common.hw },
{ .hw = &pll_audio1_div5_clk.common.hw },
};
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi0_clk, "spi0", spi_parents, 0x940,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi1_clk, "spi1", spi_parents, 0x944,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE_HWS(bus_spi0_clk, "bus-spi0", psi_ahb_hws,
0x96c, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_spi1_clk, "bus-spi1", psi_ahb_hws,
0x96c, BIT(1), 0);
static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac_25M_clk, "emac-25M", pll_periph0_hws,
0x970, BIT(31) | BIT(30), 24, 0);
static SUNXI_CCU_GATE_HWS(bus_emac_clk, "bus-emac", psi_ahb_hws,
0x97c, BIT(0), 0);
static const struct clk_parent_data ir_tx_ledc_parents[] = {
{ .fw_name = "hosc" },
{ .hw = &pll_periph0_clk.hw },
};
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_tx_ledc_parents, 0x9c0,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE_HWS(bus_ir_tx_clk, "bus-ir-tx", apb0_hws,
0x9cc, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_gpadc_clk, "bus-gpadc", apb0_hws,
0x9ec, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_ths_clk, "bus-ths", apb0_hws,
0x9fc, BIT(0), 0);
static const struct clk_hw *i2s_spdif_tx_parents[] = {
&pll_audio0_clk.hw,
&pll_audio0_4x_clk.common.hw,
&pll_audio1_div2_clk.common.hw,
&pll_audio1_div5_clk.common.hw,
};
static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s0_clk, "i2s0", i2s_spdif_tx_parents, 0xa10,
0, 5, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s1_clk, "i2s1", i2s_spdif_tx_parents, 0xa14,
0, 5, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s2_clk, "i2s2", i2s_spdif_tx_parents, 0xa18,
0, 5, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static const struct clk_hw *i2s2_asrc_parents[] = {
&pll_audio0_4x_clk.common.hw,
&pll_periph0_clk.hw,
&pll_audio1_div2_clk.common.hw,
&pll_audio1_div5_clk.common.hw,
};
static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s2_asrc_clk, "i2s2-asrc", i2s2_asrc_parents, 0xa1c,
0, 5, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE_HWS(bus_i2s0_clk, "bus-i2s0", apb0_hws,
0xa20, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_i2s1_clk, "bus-i2s1", apb0_hws,
0xa20, BIT(1), 0);
static SUNXI_CCU_GATE_HWS(bus_i2s2_clk, "bus-i2s2", apb0_hws,
0xa20, BIT(2), 0);
static SUNXI_CCU_MP_HW_WITH_MUX_GATE(spdif_tx_clk, "spdif-tx", i2s_spdif_tx_parents, 0xa24,
0, 5, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static const struct clk_hw *spdif_rx_parents[] = {
&pll_periph0_clk.hw,
&pll_audio1_div2_clk.common.hw,
&pll_audio1_div5_clk.common.hw,
};
static SUNXI_CCU_MP_HW_WITH_MUX_GATE(spdif_rx_clk, "spdif-rx", spdif_rx_parents, 0xa28,
0, 5, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE_HWS(bus_spdif_clk, "bus-spdif", apb0_hws,
0xa2c, BIT(0), 0);
static const struct clk_hw *dmic_codec_parents[] = {
&pll_audio0_clk.hw,
&pll_audio1_div2_clk.common.hw,
&pll_audio1_div5_clk.common.hw,
};
static SUNXI_CCU_MP_HW_WITH_MUX_GATE(dmic_clk, "dmic", dmic_codec_parents, 0xa40,
0, 5, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE_HWS(bus_dmic_clk, "bus-dmic", apb0_hws,
0xa4c, BIT(0), 0);
static SUNXI_CCU_MP_HW_WITH_MUX_GATE(audio_dac_clk, "audio-dac", dmic_codec_parents, 0xa50,
0, 5, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_HW_WITH_MUX_GATE(audio_adc_clk, "audio-adc", dmic_codec_parents, 0xa54,
0, 5, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE_HWS(bus_audio_clk, "bus-audio", apb0_hws,
0xa5c, BIT(0), 0);
/*
* The first parent is a 48 MHz input clock divided by 4. That 48 MHz clock is
* a 2x multiplier from osc24M synchronized by pll-periph0, and is also used by
* the OHCI module.
*/
static const struct clk_parent_data usb_ohci_parents[] = {
{ .hw = &pll_periph0_clk.hw },
{ .fw_name = "hosc" },
{ .fw_name = "losc" },
};
static const struct ccu_mux_fixed_prediv usb_ohci_predivs[] = {
{ .index = 0, .div = 50 },
{ .index = 1, .div = 2 },
};
static struct ccu_mux usb_ohci0_clk = {
.enable = BIT(31),
.mux = {
.shift = 24,
.width = 2,
.fixed_predivs = usb_ohci_predivs,
.n_predivs = ARRAY_SIZE(usb_ohci_predivs),
},
.common = {
.reg = 0xa70,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS_DATA("usb-ohci0",
usb_ohci_parents,
&ccu_mux_ops,
0),
},
};
static struct ccu_mux usb_ohci1_clk = {
.enable = BIT(31),
.mux = {
.shift = 24,
.width = 2,
.fixed_predivs = usb_ohci_predivs,
.n_predivs = ARRAY_SIZE(usb_ohci_predivs),
},
.common = {
.reg = 0xa74,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS_DATA("usb-ohci1",
usb_ohci_parents,
&ccu_mux_ops,
0),
},
};
static SUNXI_CCU_GATE_HWS(bus_ohci0_clk, "bus-ohci0", psi_ahb_hws,
0xa8c, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_ohci1_clk, "bus-ohci1", psi_ahb_hws,
0xa8c, BIT(1), 0);
static SUNXI_CCU_GATE_HWS(bus_ehci0_clk, "bus-ehci0", psi_ahb_hws,
0xa8c, BIT(4), 0);
static SUNXI_CCU_GATE_HWS(bus_ehci1_clk, "bus-ehci1", psi_ahb_hws,
0xa8c, BIT(5), 0);
static SUNXI_CCU_GATE_HWS(bus_otg_clk, "bus-otg", psi_ahb_hws,
0xa8c, BIT(8), 0);
static SUNXI_CCU_GATE_HWS(bus_lradc_clk, "bus-lradc", apb0_hws,
0xa9c, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_dpss_top_clk, "bus-dpss-top", psi_ahb_hws,
0xabc, BIT(0), 0);
static SUNXI_CCU_GATE_DATA(hdmi_24M_clk, "hdmi-24M", osc24M,
0xb04, BIT(31), 0);
static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, "hdmi-cec-32k",
pll_periph0_2x_hws,
0xb10, BIT(30), 36621, 0);
static const struct clk_parent_data hdmi_cec_parents[] = {
{ .fw_name = "losc" },
{ .hw = &hdmi_cec_32k_clk.common.hw },
};
static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_cec_clk, "hdmi-cec", hdmi_cec_parents, 0xb10,
24, 1, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE_HWS(bus_hdmi_clk, "bus-hdmi", psi_ahb_hws,
0xb1c, BIT(0), 0);
static const struct clk_parent_data mipi_dsi_parents[] = {
{ .fw_name = "hosc" },
{ .hw = &pll_periph0_clk.hw },
{ .hw = &pll_video0_2x_clk.hw },
{ .hw = &pll_video1_2x_clk.hw },
{ .hw = &pll_audio1_div2_clk.common.hw },
};
static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", mipi_dsi_parents, 0xb24,
0, 4, /* M */
24, 3, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE_HWS(bus_mipi_dsi_clk, "bus-mipi-dsi", psi_ahb_hws,
0xb4c, BIT(0), 0);
static const struct clk_hw *tcon_tve_parents[] = {
&pll_video0_clk.hw,
&pll_video0_4x_clk.common.hw,
&pll_video1_clk.hw,
&pll_video1_4x_clk.common.hw,
&pll_periph0_2x_clk.common.hw,
&pll_audio1_div2_clk.common.hw,
};
static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_tve_parents, 0xb60,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE_HWS(bus_tcon_lcd0_clk, "bus-tcon-lcd0", psi_ahb_hws,
0xb7c, BIT(0), 0);
static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tcon_tv_clk, "tcon-tv", tcon_tve_parents, 0xb80,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE_HWS(bus_tcon_tv_clk, "bus-tcon-tv", psi_ahb_hws,
0xb9c, BIT(0), 0);
static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tve_clk, "tve", tcon_tve_parents, 0xbb0,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE_HWS(bus_tve_top_clk, "bus-tve-top", psi_ahb_hws,
0xbbc, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_tve_clk, "bus-tve", psi_ahb_hws,
0xbbc, BIT(1), 0);
static const struct clk_parent_data tvd_parents[] = {
{ .fw_name = "hosc" },
{ .hw = &pll_video0_clk.hw },
{ .hw = &pll_video1_clk.hw },
{ .hw = &pll_periph0_clk.hw },
};
static SUNXI_CCU_M_DATA_WITH_MUX_GATE(tvd_clk, "tvd", tvd_parents, 0xbc0,
0, 5, /* M */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE_HWS(bus_tvd_top_clk, "bus-tvd-top", psi_ahb_hws,
0xbdc, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_tvd_clk, "bus-tvd", psi_ahb_hws,
0xbdc, BIT(1), 0);
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(ledc_clk, "ledc", ir_tx_ledc_parents, 0xbf0,
0, 4, /* M */
8, 2, /* P */
24, 1, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE_HWS(bus_ledc_clk, "bus-ledc", psi_ahb_hws,
0xbfc, BIT(0), 0);
static const struct clk_hw *csi_top_parents[] = {
&pll_periph0_2x_clk.common.hw,
&pll_video0_2x_clk.hw,
&pll_video1_2x_clk.hw,
};
static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_top_clk, "csi-top", csi_top_parents, 0xc04,
0, 4, /* M */
24, 3, /* mux */
BIT(31), /* gate */
0);
static const struct clk_parent_data csi_mclk_parents[] = {
{ .fw_name = "hosc" },
{ .hw = &pll_periph0_clk.hw },
{ .hw = &pll_video0_clk.hw },
{ .hw = &pll_video1_clk.hw },
{ .hw = &pll_audio1_div2_clk.common.hw },
{ .hw = &pll_audio1_div5_clk.common.hw },
};
static SUNXI_CCU_M_DATA_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents, 0xc08,
0, 5, /* M */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE_HWS(bus_csi_clk, "bus-csi", psi_ahb_hws,
0xc1c, BIT(0), 0);
static const struct clk_parent_data tpadc_parents[] = {
{ .fw_name = "hosc" },
{ .hw = &pll_audio0_clk.hw },
};
static SUNXI_CCU_MUX_DATA_WITH_GATE(tpadc_clk, "tpadc", tpadc_parents, 0xc50,
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE_HWS(bus_tpadc_clk, "bus-tpadc", apb0_hws,
0xc5c, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(bus_tzma_clk, "bus-tzma", apb0_hws,
0xc6c, BIT(0), 0);
static const struct clk_parent_data dsp_parents[] = {
{ .fw_name = "hosc" },
{ .fw_name = "losc" },
{ .fw_name = "iosc" },
{ .hw = &pll_periph0_2x_clk.common.hw },
{ .hw = &pll_audio1_div2_clk.common.hw },
};
static SUNXI_CCU_M_DATA_WITH_MUX_GATE(dsp_clk, "dsp", dsp_parents, 0xc70,
0, 5, /* M */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE_HWS(bus_dsp_cfg_clk, "bus-dsp-cfg", psi_ahb_hws,
0xc7c, BIT(1), 0);
/*
* The RISC-V gate is not modelled - it is in a separate register (0xd04)
* and has a special key field. The clock is critical anyway.
*/
static const struct clk_parent_data riscv_parents[] = {
{ .fw_name = "hosc" },
{ .fw_name = "losc" },
{ .fw_name = "iosc" },
{ .hw = &pll_periph0_800M_clk.common.hw },
{ .hw = &pll_periph0_clk.hw },
{ .hw = &pll_cpux_clk.common.hw },
{ .hw = &pll_audio1_div2_clk.common.hw },
};
static SUNXI_CCU_M_DATA_WITH_MUX(riscv_clk, "riscv", riscv_parents, 0xd00,
0, 5, /* M */
24, 3, /* mux */
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
/* The riscv-axi clk must be divided by at least 2. */
static struct clk_div_table riscv_axi_table[] = {
{ .val = 1, .div = 2 },
{ .val = 2, .div = 3 },
{ .val = 3, .div = 4 },
{ /* Sentinel */ }
};
static SUNXI_CCU_DIV_TABLE_HW(riscv_axi_clk, "riscv-axi", &riscv_clk.common.hw,
0xd00, 8, 2, riscv_axi_table, 0);
static SUNXI_CCU_GATE_HWS(bus_riscv_cfg_clk, "bus-riscv-cfg", psi_ahb_hws,
0xd0c, BIT(0), CLK_IS_CRITICAL);
static SUNXI_CCU_GATE_DATA(fanout_24M_clk, "fanout-24M", osc24M,
0xf30, BIT(0), 0);
static SUNXI_CCU_GATE_DATA_WITH_PREDIV(fanout_12M_clk, "fanout-12M", osc24M,
0xf30, BIT(1), 2, 0);
static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M", pll_periph0_2x_hws,
0xf30, BIT(2), 75, 0);
static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M", pll_periph0_hws,
0xf30, BIT(3), 24, 0);
static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_32k_clk, "fanout-32k", pll_periph0_2x_hws,
0xf30, BIT(4), 36621, 0);
/* This clock has a second divider that is not modelled and forced to 0. */
#define SUN20I_D1_FANOUT_27M_REG 0xf34
static const struct clk_hw *fanout_27M_parents[] = {
&pll_video0_clk.hw,
&pll_video1_clk.hw,
};
static SUNXI_CCU_M_HW_WITH_MUX_GATE(fanout_27M_clk, "fanout-27M", fanout_27M_parents, 0xf34,
0, 5, /* M */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_M_HWS_WITH_GATE(fanout_pclk_clk, "fanout-pclk", apb0_hws, 0xf38,
0, 5, /* M */
BIT(31), /* gate */
0);
static const struct clk_hw *fanout_parents[] = {
&fanout_32k_clk.common.hw,
&fanout_12M_clk.common.hw,
&fanout_16M_clk.common.hw,
&fanout_24M_clk.common.hw,
&fanout_25M_clk.common.hw,
&fanout_27M_clk.common.hw,
&fanout_pclk_clk.common.hw,
};
static SUNXI_CCU_MUX_HW_WITH_GATE(fanout0_clk, "fanout0", fanout_parents, 0xf3c,
0, 3, /* mux */
BIT(21), /* gate */
0);
static SUNXI_CCU_MUX_HW_WITH_GATE(fanout1_clk, "fanout1", fanout_parents, 0xf3c,
3, 3, /* mux */
BIT(22), /* gate */
0);
static SUNXI_CCU_MUX_HW_WITH_GATE(fanout2_clk, "fanout2", fanout_parents, 0xf3c,
6, 3, /* mux */
BIT(23), /* gate */
0);
static struct ccu_common *sun20i_d1_ccu_clks[] = {
&pll_cpux_clk.common,
&pll_ddr0_clk.common,
&pll_periph0_4x_clk.common,
&pll_periph0_2x_clk.common,
&pll_periph0_800M_clk.common,
&pll_video0_4x_clk.common,
&pll_video1_4x_clk.common,
&pll_ve_clk.common,
&pll_audio0_4x_clk.common,
&pll_audio1_clk.common,
&pll_audio1_div2_clk.common,
&pll_audio1_div5_clk.common,
&cpux_clk.common,
&cpux_axi_clk.common,
&cpux_apb_clk.common,
&psi_ahb_clk.common,
&apb0_clk.common,
&apb1_clk.common,
&de_clk.common,
&bus_de_clk.common,
&di_clk.common,
&bus_di_clk.common,
&g2d_clk.common,
&bus_g2d_clk.common,
&ce_clk.common,
&bus_ce_clk.common,
&ve_clk.common,
&bus_ve_clk.common,
&bus_dma_clk.common,
&bus_msgbox0_clk.common,
&bus_msgbox1_clk.common,
&bus_msgbox2_clk.common,
&bus_spinlock_clk.common,
&bus_hstimer_clk.common,
&avs_clk.common,
&bus_dbg_clk.common,
&bus_pwm_clk.common,
&bus_iommu_clk.common,
&dram_clk.common,
&mbus_dma_clk.common,
&mbus_ve_clk.common,
&mbus_ce_clk.common,
&mbus_tvin_clk.common,
&mbus_csi_clk.common,
&mbus_g2d_clk.common,
&mbus_riscv_clk.common,
&bus_dram_clk.common,
&mmc0_clk.common,
&mmc1_clk.common,
&mmc2_clk.common,
&bus_mmc0_clk.common,
&bus_mmc1_clk.common,
&bus_mmc2_clk.common,
&bus_uart0_clk.common,
&bus_uart1_clk.common,
&bus_uart2_clk.common,
&bus_uart3_clk.common,
&bus_uart4_clk.common,
&bus_uart5_clk.common,
&bus_i2c0_clk.common,
&bus_i2c1_clk.common,
&bus_i2c2_clk.common,
&bus_i2c3_clk.common,
&bus_can0_clk.common,
&bus_can1_clk.common,
&spi0_clk.common,
&spi1_clk.common,
&bus_spi0_clk.common,
&bus_spi1_clk.common,
&emac_25M_clk.common,
&bus_emac_clk.common,
&ir_tx_clk.common,
&bus_ir_tx_clk.common,
&bus_gpadc_clk.common,
&bus_ths_clk.common,
&i2s0_clk.common,
&i2s1_clk.common,
&i2s2_clk.common,
&i2s2_asrc_clk.common,
&bus_i2s0_clk.common,
&bus_i2s1_clk.common,
&bus_i2s2_clk.common,
&spdif_tx_clk.common,
&spdif_rx_clk.common,
&bus_spdif_clk.common,
&dmic_clk.common,
&bus_dmic_clk.common,
&audio_dac_clk.common,
&audio_adc_clk.common,
&bus_audio_clk.common,
&usb_ohci0_clk.common,
&usb_ohci1_clk.common,
&bus_ohci0_clk.common,
&bus_ohci1_clk.common,
&bus_ehci0_clk.common,
&bus_ehci1_clk.common,
&bus_otg_clk.common,
&bus_lradc_clk.common,
&bus_dpss_top_clk.common,
&hdmi_24M_clk.common,
&hdmi_cec_32k_clk.common,
&hdmi_cec_clk.common,
&bus_hdmi_clk.common,
&mipi_dsi_clk.common,
&bus_mipi_dsi_clk.common,
&tcon_lcd0_clk.common,
&bus_tcon_lcd0_clk.common,
&tcon_tv_clk.common,
&bus_tcon_tv_clk.common,
&tve_clk.common,
&bus_tve_top_clk.common,
&bus_tve_clk.common,
&tvd_clk.common,
&bus_tvd_top_clk.common,
&bus_tvd_clk.common,
&ledc_clk.common,
&bus_ledc_clk.common,
&csi_top_clk.common,
&csi_mclk_clk.common,
&bus_csi_clk.common,
&tpadc_clk.common,
&bus_tpadc_clk.common,
&bus_tzma_clk.common,
&dsp_clk.common,
&bus_dsp_cfg_clk.common,
&riscv_clk.common,
&riscv_axi_clk.common,
&bus_riscv_cfg_clk.common,
&fanout_24M_clk.common,
&fanout_12M_clk.common,
&fanout_16M_clk.common,
&fanout_25M_clk.common,
&fanout_32k_clk.common,
&fanout_27M_clk.common,
&fanout_pclk_clk.common,
&fanout0_clk.common,
&fanout1_clk.common,
&fanout2_clk.common,
};
static struct clk_hw_onecell_data sun20i_d1_hw_clks = {
.num = CLK_NUMBER,
.hws = {
[CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
[CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
[CLK_PLL_PERIPH0_4X] = &pll_periph0_4x_clk.common.hw,
[CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.common.hw,
[CLK_PLL_PERIPH0_800M] = &pll_periph0_800M_clk.common.hw,
[CLK_PLL_PERIPH0] = &pll_periph0_clk.hw,
[CLK_PLL_PERIPH0_DIV3] = &pll_periph0_div3_clk.hw,
[CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.common.hw,
[CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
[CLK_PLL_VIDEO0] = &pll_video0_clk.hw,
[CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.common.hw,
[CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
[CLK_PLL_VIDEO1] = &pll_video1_clk.hw,
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
[CLK_PLL_AUDIO0_4X] = &pll_audio0_4x_clk.common.hw,
[CLK_PLL_AUDIO0_2X] = &pll_audio0_2x_clk.hw,
[CLK_PLL_AUDIO0] = &pll_audio0_clk.hw,
[CLK_PLL_AUDIO1] = &pll_audio1_clk.common.hw,
[CLK_PLL_AUDIO1_DIV2] = &pll_audio1_div2_clk.common.hw,
[CLK_PLL_AUDIO1_DIV5] = &pll_audio1_div5_clk.common.hw,
[CLK_CPUX] = &cpux_clk.common.hw,
[CLK_CPUX_AXI] = &cpux_axi_clk.common.hw,
[CLK_CPUX_APB] = &cpux_apb_clk.common.hw,
[CLK_PSI_AHB] = &psi_ahb_clk.common.hw,
[CLK_APB0] = &apb0_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_MBUS] = &mbus_clk.hw,
[CLK_DE] = &de_clk.common.hw,
[CLK_BUS_DE] = &bus_de_clk.common.hw,
[CLK_DI] = &di_clk.common.hw,
[CLK_BUS_DI] = &bus_di_clk.common.hw,
[CLK_G2D] = &g2d_clk.common.hw,
[CLK_BUS_G2D] = &bus_g2d_clk.common.hw,
[CLK_CE] = &ce_clk.common.hw,
[CLK_BUS_CE] = &bus_ce_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_BUS_VE] = &bus_ve_clk.common.hw,
[CLK_BUS_DMA] = &bus_dma_clk.common.hw,
[CLK_BUS_MSGBOX0] = &bus_msgbox0_clk.common.hw,
[CLK_BUS_MSGBOX1] = &bus_msgbox1_clk.common.hw,
[CLK_BUS_MSGBOX2] = &bus_msgbox2_clk.common.hw,
[CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
[CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
[CLK_BUS_PWM] = &bus_pwm_clk.common.hw,
[CLK_BUS_IOMMU] = &bus_iommu_clk.common.hw,
[CLK_DRAM] = &dram_clk.common.hw,
[CLK_MBUS_DMA] = &mbus_dma_clk.common.hw,
[CLK_MBUS_VE] = &mbus_ve_clk.common.hw,
[CLK_MBUS_CE] = &mbus_ce_clk.common.hw,
[CLK_MBUS_TVIN] = &mbus_tvin_clk.common.hw,
[CLK_MBUS_CSI] = &mbus_csi_clk.common.hw,
[CLK_MBUS_G2D] = &mbus_g2d_clk.common.hw,
[CLK_MBUS_RISCV] = &mbus_riscv_clk.common.hw,
[CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
[CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
[CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
[CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
[CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
[CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
[CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
[CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
[CLK_BUS_UART5] = &bus_uart5_clk.common.hw,
[CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
[CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
[CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
[CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
[CLK_BUS_CAN0] = &bus_can0_clk.common.hw,
[CLK_BUS_CAN1] = &bus_can1_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
[CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
[CLK_EMAC_25M] = &emac_25M_clk.common.hw,
[CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
[CLK_IR_TX] = &ir_tx_clk.common.hw,
[CLK_BUS_IR_TX] = &bus_ir_tx_clk.common.hw,
[CLK_BUS_GPADC] = &bus_gpadc_clk.common.hw,
[CLK_BUS_THS] = &bus_ths_clk.common.hw,
[CLK_I2S0] = &i2s0_clk.common.hw,
[CLK_I2S1] = &i2s1_clk.common.hw,
[CLK_I2S2] = &i2s2_clk.common.hw,
[CLK_I2S2_ASRC] = &i2s2_asrc_clk.common.hw,
[CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
[CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
[CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
[CLK_SPDIF_TX] = &spdif_tx_clk.common.hw,
[CLK_SPDIF_RX] = &spdif_rx_clk.common.hw,
[CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
[CLK_DMIC] = &dmic_clk.common.hw,
[CLK_BUS_DMIC] = &bus_dmic_clk.common.hw,
[CLK_AUDIO_DAC] = &audio_dac_clk.common.hw,
[CLK_AUDIO_ADC] = &audio_adc_clk.common.hw,
[CLK_BUS_AUDIO] = &bus_audio_clk.common.hw,
[CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
[CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
[CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
[CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
[CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
[CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
[CLK_BUS_OTG] = &bus_otg_clk.common.hw,
[CLK_BUS_LRADC] = &bus_lradc_clk.common.hw,
[CLK_BUS_DPSS_TOP] = &bus_dpss_top_clk.common.hw,
[CLK_HDMI_24M] = &hdmi_24M_clk.common.hw,
[CLK_HDMI_CEC_32K] = &hdmi_cec_32k_clk.common.hw,
[CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw,
[CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
[CLK_MIPI_DSI] = &mipi_dsi_clk.common.hw,
[CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
[CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw,
[CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw,
[CLK_TCON_TV] = &tcon_tv_clk.common.hw,
[CLK_BUS_TCON_TV] = &bus_tcon_tv_clk.common.hw,
[CLK_TVE] = &tve_clk.common.hw,
[CLK_BUS_TVE_TOP] = &bus_tve_top_clk.common.hw,
[CLK_BUS_TVE] = &bus_tve_clk.common.hw,
[CLK_TVD] = &tvd_clk.common.hw,
[CLK_BUS_TVD_TOP] = &bus_tvd_top_clk.common.hw,
[CLK_BUS_TVD] = &bus_tvd_clk.common.hw,
[CLK_LEDC] = &ledc_clk.common.hw,
[CLK_BUS_LEDC] = &bus_ledc_clk.common.hw,
[CLK_CSI_TOP] = &csi_top_clk.common.hw,
[CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
[CLK_BUS_CSI] = &bus_csi_clk.common.hw,
[CLK_TPADC] = &tpadc_clk.common.hw,
[CLK_BUS_TPADC] = &bus_tpadc_clk.common.hw,
[CLK_BUS_TZMA] = &bus_tzma_clk.common.hw,
[CLK_DSP] = &dsp_clk.common.hw,
[CLK_BUS_DSP_CFG] = &bus_dsp_cfg_clk.common.hw,
[CLK_RISCV] = &riscv_clk.common.hw,
[CLK_RISCV_AXI] = &riscv_axi_clk.common.hw,
[CLK_BUS_RISCV_CFG] = &bus_riscv_cfg_clk.common.hw,
[CLK_FANOUT_24M] = &fanout_24M_clk.common.hw,
[CLK_FANOUT_12M] = &fanout_12M_clk.common.hw,
[CLK_FANOUT_16M] = &fanout_16M_clk.common.hw,
[CLK_FANOUT_25M] = &fanout_25M_clk.common.hw,
[CLK_FANOUT_32K] = &fanout_32k_clk.common.hw,
[CLK_FANOUT_27M] = &fanout_27M_clk.common.hw,
[CLK_FANOUT_PCLK] = &fanout_pclk_clk.common.hw,
[CLK_FANOUT0] = &fanout0_clk.common.hw,
[CLK_FANOUT1] = &fanout1_clk.common.hw,
[CLK_FANOUT2] = &fanout2_clk.common.hw,
},
};
static struct ccu_reset_map sun20i_d1_ccu_resets[] = {
[RST_MBUS] = { 0x540, BIT(30) },
[RST_BUS_DE] = { 0x60c, BIT(16) },
[RST_BUS_DI] = { 0x62c, BIT(16) },
[RST_BUS_G2D] = { 0x63c, BIT(16) },
[RST_BUS_CE] = { 0x68c, BIT(16) },
[RST_BUS_VE] = { 0x69c, BIT(16) },
[RST_BUS_DMA] = { 0x70c, BIT(16) },
[RST_BUS_MSGBOX0] = { 0x71c, BIT(16) },
[RST_BUS_MSGBOX1] = { 0x71c, BIT(17) },
[RST_BUS_MSGBOX2] = { 0x71c, BIT(18) },
[RST_BUS_SPINLOCK] = { 0x72c, BIT(16) },
[RST_BUS_HSTIMER] = { 0x73c, BIT(16) },
[RST_BUS_DBG] = { 0x78c, BIT(16) },
[RST_BUS_PWM] = { 0x7ac, BIT(16) },
[RST_BUS_DRAM] = { 0x80c, BIT(16) },
[RST_BUS_MMC0] = { 0x84c, BIT(16) },
[RST_BUS_MMC1] = { 0x84c, BIT(17) },
[RST_BUS_MMC2] = { 0x84c, BIT(18) },
[RST_BUS_UART0] = { 0x90c, BIT(16) },
[RST_BUS_UART1] = { 0x90c, BIT(17) },
[RST_BUS_UART2] = { 0x90c, BIT(18) },
[RST_BUS_UART3] = { 0x90c, BIT(19) },
[RST_BUS_UART4] = { 0x90c, BIT(20) },
[RST_BUS_UART5] = { 0x90c, BIT(21) },
[RST_BUS_I2C0] = { 0x91c, BIT(16) },
[RST_BUS_I2C1] = { 0x91c, BIT(17) },
[RST_BUS_I2C2] = { 0x91c, BIT(18) },
[RST_BUS_I2C3] = { 0x91c, BIT(19) },
[RST_BUS_CAN0] = { 0x92c, BIT(16) },
[RST_BUS_CAN1] = { 0x92c, BIT(17) },
[RST_BUS_SPI0] = { 0x96c, BIT(16) },
[RST_BUS_SPI1] = { 0x96c, BIT(17) },
[RST_BUS_EMAC] = { 0x97c, BIT(16) },
[RST_BUS_IR_TX] = { 0x9cc, BIT(16) },
[RST_BUS_GPADC] = { 0x9ec, BIT(16) },
[RST_BUS_THS] = { 0x9fc, BIT(16) },
[RST_BUS_I2S0] = { 0xa20, BIT(16) },
[RST_BUS_I2S1] = { 0xa20, BIT(17) },
[RST_BUS_I2S2] = { 0xa20, BIT(18) },
[RST_BUS_SPDIF] = { 0xa2c, BIT(16) },
[RST_BUS_DMIC] = { 0xa4c, BIT(16) },
[RST_BUS_AUDIO] = { 0xa5c, BIT(16) },
[RST_USB_PHY0] = { 0xa70, BIT(30) },
[RST_USB_PHY1] = { 0xa74, BIT(30) },
[RST_BUS_OHCI0] = { 0xa8c, BIT(16) },
[RST_BUS_OHCI1] = { 0xa8c, BIT(17) },
[RST_BUS_EHCI0] = { 0xa8c, BIT(20) },
[RST_BUS_EHCI1] = { 0xa8c, BIT(21) },
[RST_BUS_OTG] = { 0xa8c, BIT(24) },
[RST_BUS_LRADC] = { 0xa9c, BIT(16) },
[RST_BUS_DPSS_TOP] = { 0xabc, BIT(16) },
[RST_BUS_HDMI_MAIN] = { 0xb1c, BIT(16) },
[RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) },
[RST_BUS_MIPI_DSI] = { 0xb4c, BIT(16) },
[RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) },
[RST_BUS_TCON_TV] = { 0xb9c, BIT(16) },
[RST_BUS_LVDS0] = { 0xbac, BIT(16) },
[RST_BUS_TVE_TOP] = { 0xbbc, BIT(16) },
[RST_BUS_TVE] = { 0xbbc, BIT(17) },
[RST_BUS_TVD_TOP] = { 0xbdc, BIT(16) },
[RST_BUS_TVD] = { 0xbdc, BIT(17) },
[RST_BUS_LEDC] = { 0xbfc, BIT(16) },
[RST_BUS_CSI] = { 0xc1c, BIT(16) },
[RST_BUS_TPADC] = { 0xc5c, BIT(16) },
[RST_DSP] = { 0xc7c, BIT(16) },
[RST_BUS_DSP_CFG] = { 0xc7c, BIT(17) },
[RST_BUS_DSP_DBG] = { 0xc7c, BIT(18) },
[RST_BUS_RISCV_CFG] = { 0xd0c, BIT(16) },
};
static const struct sunxi_ccu_desc sun20i_d1_ccu_desc = {
.ccu_clks = sun20i_d1_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun20i_d1_ccu_clks),
.hw_clks = &sun20i_d1_hw_clks,
.resets = sun20i_d1_ccu_resets,
.num_resets = ARRAY_SIZE(sun20i_d1_ccu_resets),
};
static const u32 pll_regs[] = {
SUN20I_D1_PLL_CPUX_REG,
SUN20I_D1_PLL_DDR0_REG,
SUN20I_D1_PLL_PERIPH0_REG,
SUN20I_D1_PLL_VIDEO0_REG,
SUN20I_D1_PLL_VIDEO1_REG,
SUN20I_D1_PLL_VE_REG,
SUN20I_D1_PLL_AUDIO0_REG,
SUN20I_D1_PLL_AUDIO1_REG,
};
static const u32 pll_video_regs[] = {
SUN20I_D1_PLL_VIDEO0_REG,
SUN20I_D1_PLL_VIDEO1_REG,
};
static struct ccu_mux_nb sun20i_d1_riscv_nb = {
.common = &riscv_clk.common,
.cm = &riscv_clk.mux,
.delay_us = 1,
.bypass_index = 4, /* index of pll-periph0 */
};
static int sun20i_d1_ccu_probe(struct platform_device *pdev)
{
void __iomem *reg;
u32 val;
int i, ret;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
/* Enable the enable, LDO, and lock bits on all PLLs. */
for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
val = readl(reg + pll_regs[i]);
val |= BIT(31) | BIT(30) | BIT(29);
writel(val, reg + pll_regs[i]);
}
/* Force PLL_CPUX factor M to 0. */
val = readl(reg + SUN20I_D1_PLL_CPUX_REG);
val &= ~GENMASK(1, 0);
writel(val, reg + SUN20I_D1_PLL_CPUX_REG);
/*
* Force the output divider of video PLLs to 0.
*
* See the comment before pll-video0 definition for the reason.
*/
for (i = 0; i < ARRAY_SIZE(pll_video_regs); i++) {
val = readl(reg + pll_video_regs[i]);
val &= ~BIT(0);
writel(val, reg + pll_video_regs[i]);
}
/* Enforce m1 = 0, m0 = 0 for PLL_AUDIO0 */
val = readl(reg + SUN20I_D1_PLL_AUDIO0_REG);
val &= ~BIT(1) | BIT(0);
writel(val, reg + SUN20I_D1_PLL_AUDIO0_REG);
/* Force fanout-27M factor N to 0. */
val = readl(reg + SUN20I_D1_FANOUT_27M_REG);
val &= ~GENMASK(9, 8);
writel(val, reg + SUN20I_D1_FANOUT_27M_REG);
ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun20i_d1_ccu_desc);
if (ret)
return ret;
/* Reparent CPU during PLL CPUX rate changes */
ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
&sun20i_d1_riscv_nb);
return 0;
}
static const struct of_device_id sun20i_d1_ccu_ids[] = {
{ .compatible = "allwinner,sun20i-d1-ccu" },
{ }
};
static struct platform_driver sun20i_d1_ccu_driver = {
.probe = sun20i_d1_ccu_probe,
.driver = {
.name = "sun20i-d1-ccu",
.suppress_bind_attrs = true,
.of_match_table = sun20i_d1_ccu_ids,
},
};
module_platform_driver(sun20i_d1_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun20i-d1.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Maxime Ripard
* Maxime Ripard <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include "ccu_phase.h"
static int ccu_phase_get_phase(struct clk_hw *hw)
{
struct ccu_phase *phase = hw_to_ccu_phase(hw);
struct clk_hw *parent, *grandparent;
unsigned int parent_rate, grandparent_rate;
u16 step, parent_div;
u32 reg;
u8 delay;
reg = readl(phase->common.base + phase->common.reg);
delay = (reg >> phase->shift);
delay &= (1 << phase->width) - 1;
if (!delay)
return 180;
/* Get our parent clock, it's the one that can adjust its rate */
parent = clk_hw_get_parent(hw);
if (!parent)
return -EINVAL;
/* And its rate */
parent_rate = clk_hw_get_rate(parent);
if (!parent_rate)
return -EINVAL;
/* Now, get our parent's parent (most likely some PLL) */
grandparent = clk_hw_get_parent(parent);
if (!grandparent)
return -EINVAL;
/* And its rate */
grandparent_rate = clk_hw_get_rate(grandparent);
if (!grandparent_rate)
return -EINVAL;
/* Get our parent clock divider */
parent_div = grandparent_rate / parent_rate;
step = DIV_ROUND_CLOSEST(360, parent_div);
return delay * step;
}
static int ccu_phase_set_phase(struct clk_hw *hw, int degrees)
{
struct ccu_phase *phase = hw_to_ccu_phase(hw);
struct clk_hw *parent, *grandparent;
unsigned int parent_rate, grandparent_rate;
unsigned long flags;
u32 reg;
u8 delay;
/* Get our parent clock, it's the one that can adjust its rate */
parent = clk_hw_get_parent(hw);
if (!parent)
return -EINVAL;
/* And its rate */
parent_rate = clk_hw_get_rate(parent);
if (!parent_rate)
return -EINVAL;
/* Now, get our parent's parent (most likely some PLL) */
grandparent = clk_hw_get_parent(parent);
if (!grandparent)
return -EINVAL;
/* And its rate */
grandparent_rate = clk_hw_get_rate(grandparent);
if (!grandparent_rate)
return -EINVAL;
if (degrees != 180) {
u16 step, parent_div;
/* Get our parent divider */
parent_div = grandparent_rate / parent_rate;
/*
* We can only outphase the clocks by multiple of the
* PLL's period.
*
* Since our parent clock is only a divider, and the
* formula to get the outphasing in degrees is deg =
* 360 * delta / period
*
* If we simplify this formula, we can see that the
* only thing that we're concerned about is the number
* of period we want to outphase our clock from, and
* the divider set by our parent clock.
*/
step = DIV_ROUND_CLOSEST(360, parent_div);
delay = DIV_ROUND_CLOSEST(degrees, step);
} else {
delay = 0;
}
spin_lock_irqsave(phase->common.lock, flags);
reg = readl(phase->common.base + phase->common.reg);
reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift);
writel(reg | (delay << phase->shift),
phase->common.base + phase->common.reg);
spin_unlock_irqrestore(phase->common.lock, flags);
return 0;
}
const struct clk_ops ccu_phase_ops = {
.get_phase = ccu_phase_get_phase,
.set_phase = ccu_phase_set_phase,
};
EXPORT_SYMBOL_NS_GPL(ccu_phase_ops, SUNXI_CCU);
| linux-master | drivers/clk/sunxi-ng/ccu_phase.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include "ccu_common.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_reset.h"
#include "ccu-sun9i-a80-de.h"
static SUNXI_CCU_GATE(fe0_clk, "fe0", "fe0-div",
0x00, BIT(0), 0);
static SUNXI_CCU_GATE(fe1_clk, "fe1", "fe1-div",
0x00, BIT(1), 0);
static SUNXI_CCU_GATE(fe2_clk, "fe2", "fe2-div",
0x00, BIT(2), 0);
static SUNXI_CCU_GATE(iep_deu0_clk, "iep-deu0", "de",
0x00, BIT(4), 0);
static SUNXI_CCU_GATE(iep_deu1_clk, "iep-deu1", "de",
0x00, BIT(5), 0);
static SUNXI_CCU_GATE(be0_clk, "be0", "be0-div",
0x00, BIT(8), 0);
static SUNXI_CCU_GATE(be1_clk, "be1", "be1-div",
0x00, BIT(9), 0);
static SUNXI_CCU_GATE(be2_clk, "be2", "be2-div",
0x00, BIT(10), 0);
static SUNXI_CCU_GATE(iep_drc0_clk, "iep-drc0", "de",
0x00, BIT(12), 0);
static SUNXI_CCU_GATE(iep_drc1_clk, "iep-drc1", "de",
0x00, BIT(13), 0);
static SUNXI_CCU_GATE(merge_clk, "merge", "de",
0x00, BIT(20), 0);
static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "sdram",
0x04, BIT(0), 0);
static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "sdram",
0x04, BIT(1), 0);
static SUNXI_CCU_GATE(dram_fe2_clk, "dram-fe2", "sdram",
0x04, BIT(2), 0);
static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "sdram",
0x04, BIT(4), 0);
static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "sdram",
0x04, BIT(5), 0);
static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "sdram",
0x04, BIT(8), 0);
static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "sdram",
0x04, BIT(9), 0);
static SUNXI_CCU_GATE(dram_be2_clk, "dram-be2", "sdram",
0x04, BIT(10), 0);
static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "sdram",
0x04, BIT(12), 0);
static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "sdram",
0x04, BIT(13), 0);
static SUNXI_CCU_GATE(bus_fe0_clk, "bus-fe0", "bus-de",
0x08, BIT(0), 0);
static SUNXI_CCU_GATE(bus_fe1_clk, "bus-fe1", "bus-de",
0x08, BIT(1), 0);
static SUNXI_CCU_GATE(bus_fe2_clk, "bus-fe2", "bus-de",
0x08, BIT(2), 0);
static SUNXI_CCU_GATE(bus_deu0_clk, "bus-deu0", "bus-de",
0x08, BIT(4), 0);
static SUNXI_CCU_GATE(bus_deu1_clk, "bus-deu1", "bus-de",
0x08, BIT(5), 0);
static SUNXI_CCU_GATE(bus_be0_clk, "bus-be0", "bus-de",
0x08, BIT(8), 0);
static SUNXI_CCU_GATE(bus_be1_clk, "bus-be1", "bus-de",
0x08, BIT(9), 0);
static SUNXI_CCU_GATE(bus_be2_clk, "bus-be2", "bus-de",
0x08, BIT(10), 0);
static SUNXI_CCU_GATE(bus_drc0_clk, "bus-drc0", "bus-de",
0x08, BIT(12), 0);
static SUNXI_CCU_GATE(bus_drc1_clk, "bus-drc1", "bus-de",
0x08, BIT(13), 0);
static SUNXI_CCU_M(fe0_div_clk, "fe0-div", "de", 0x20, 0, 4, 0);
static SUNXI_CCU_M(fe1_div_clk, "fe1-div", "de", 0x20, 4, 4, 0);
static SUNXI_CCU_M(fe2_div_clk, "fe2-div", "de", 0x20, 8, 4, 0);
static SUNXI_CCU_M(be0_div_clk, "be0-div", "de", 0x20, 16, 4, 0);
static SUNXI_CCU_M(be1_div_clk, "be1-div", "de", 0x20, 20, 4, 0);
static SUNXI_CCU_M(be2_div_clk, "be2-div", "de", 0x20, 24, 4, 0);
static struct ccu_common *sun9i_a80_de_clks[] = {
&fe0_clk.common,
&fe1_clk.common,
&fe2_clk.common,
&iep_deu0_clk.common,
&iep_deu1_clk.common,
&be0_clk.common,
&be1_clk.common,
&be2_clk.common,
&iep_drc0_clk.common,
&iep_drc1_clk.common,
&merge_clk.common,
&dram_fe0_clk.common,
&dram_fe1_clk.common,
&dram_fe2_clk.common,
&dram_deu0_clk.common,
&dram_deu1_clk.common,
&dram_be0_clk.common,
&dram_be1_clk.common,
&dram_be2_clk.common,
&dram_drc0_clk.common,
&dram_drc1_clk.common,
&bus_fe0_clk.common,
&bus_fe1_clk.common,
&bus_fe2_clk.common,
&bus_deu0_clk.common,
&bus_deu1_clk.common,
&bus_be0_clk.common,
&bus_be1_clk.common,
&bus_be2_clk.common,
&bus_drc0_clk.common,
&bus_drc1_clk.common,
&fe0_div_clk.common,
&fe1_div_clk.common,
&fe2_div_clk.common,
&be0_div_clk.common,
&be1_div_clk.common,
&be2_div_clk.common,
};
static struct clk_hw_onecell_data sun9i_a80_de_hw_clks = {
.hws = {
[CLK_FE0] = &fe0_clk.common.hw,
[CLK_FE1] = &fe1_clk.common.hw,
[CLK_FE2] = &fe2_clk.common.hw,
[CLK_IEP_DEU0] = &iep_deu0_clk.common.hw,
[CLK_IEP_DEU1] = &iep_deu1_clk.common.hw,
[CLK_BE0] = &be0_clk.common.hw,
[CLK_BE1] = &be1_clk.common.hw,
[CLK_BE2] = &be2_clk.common.hw,
[CLK_IEP_DRC0] = &iep_drc0_clk.common.hw,
[CLK_IEP_DRC1] = &iep_drc1_clk.common.hw,
[CLK_MERGE] = &merge_clk.common.hw,
[CLK_DRAM_FE0] = &dram_fe0_clk.common.hw,
[CLK_DRAM_FE1] = &dram_fe1_clk.common.hw,
[CLK_DRAM_FE2] = &dram_fe2_clk.common.hw,
[CLK_DRAM_DEU0] = &dram_deu0_clk.common.hw,
[CLK_DRAM_DEU1] = &dram_deu1_clk.common.hw,
[CLK_DRAM_BE0] = &dram_be0_clk.common.hw,
[CLK_DRAM_BE1] = &dram_be1_clk.common.hw,
[CLK_DRAM_BE2] = &dram_be2_clk.common.hw,
[CLK_DRAM_DRC0] = &dram_drc0_clk.common.hw,
[CLK_DRAM_DRC1] = &dram_drc1_clk.common.hw,
[CLK_BUS_FE0] = &bus_fe0_clk.common.hw,
[CLK_BUS_FE1] = &bus_fe1_clk.common.hw,
[CLK_BUS_FE2] = &bus_fe2_clk.common.hw,
[CLK_BUS_DEU0] = &bus_deu0_clk.common.hw,
[CLK_BUS_DEU1] = &bus_deu1_clk.common.hw,
[CLK_BUS_BE0] = &bus_be0_clk.common.hw,
[CLK_BUS_BE1] = &bus_be1_clk.common.hw,
[CLK_BUS_BE2] = &bus_be2_clk.common.hw,
[CLK_BUS_DRC0] = &bus_drc0_clk.common.hw,
[CLK_BUS_DRC1] = &bus_drc1_clk.common.hw,
[CLK_FE0_DIV] = &fe0_div_clk.common.hw,
[CLK_FE1_DIV] = &fe1_div_clk.common.hw,
[CLK_FE2_DIV] = &fe2_div_clk.common.hw,
[CLK_BE0_DIV] = &be0_div_clk.common.hw,
[CLK_BE1_DIV] = &be1_div_clk.common.hw,
[CLK_BE2_DIV] = &be2_div_clk.common.hw,
},
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun9i_a80_de_resets[] = {
[RST_FE0] = { 0x0c, BIT(0) },
[RST_FE1] = { 0x0c, BIT(1) },
[RST_FE2] = { 0x0c, BIT(2) },
[RST_DEU0] = { 0x0c, BIT(4) },
[RST_DEU1] = { 0x0c, BIT(5) },
[RST_BE0] = { 0x0c, BIT(8) },
[RST_BE1] = { 0x0c, BIT(9) },
[RST_BE2] = { 0x0c, BIT(10) },
[RST_DRC0] = { 0x0c, BIT(12) },
[RST_DRC1] = { 0x0c, BIT(13) },
[RST_MERGE] = { 0x0c, BIT(20) },
};
static const struct sunxi_ccu_desc sun9i_a80_de_clk_desc = {
.ccu_clks = sun9i_a80_de_clks,
.num_ccu_clks = ARRAY_SIZE(sun9i_a80_de_clks),
.hw_clks = &sun9i_a80_de_hw_clks,
.resets = sun9i_a80_de_resets,
.num_resets = ARRAY_SIZE(sun9i_a80_de_resets),
};
static int sun9i_a80_de_clk_probe(struct platform_device *pdev)
{
struct clk *bus_clk;
struct reset_control *rstc;
void __iomem *reg;
int ret;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
bus_clk = devm_clk_get(&pdev->dev, "bus");
if (IS_ERR(bus_clk))
return dev_err_probe(&pdev->dev, PTR_ERR(bus_clk),
"Couldn't get bus clk\n");
rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (IS_ERR(rstc))
return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
"Couldn't get reset control\n");
/* The bus clock needs to be enabled for us to access the registers */
ret = clk_prepare_enable(bus_clk);
if (ret) {
dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret);
return ret;
}
/* The reset control needs to be asserted for the controls to work */
ret = reset_control_deassert(rstc);
if (ret) {
dev_err(&pdev->dev,
"Couldn't deassert reset control: %d\n", ret);
goto err_disable_clk;
}
ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun9i_a80_de_clk_desc);
if (ret)
goto err_assert_reset;
return 0;
err_assert_reset:
reset_control_assert(rstc);
err_disable_clk:
clk_disable_unprepare(bus_clk);
return ret;
}
static const struct of_device_id sun9i_a80_de_clk_ids[] = {
{ .compatible = "allwinner,sun9i-a80-de-clks" },
{ }
};
static struct platform_driver sun9i_a80_de_clk_driver = {
.probe = sun9i_a80_de_clk_probe,
.driver = {
.name = "sun9i-a80-de-clks",
.suppress_bind_attrs = true,
.of_match_table = sun9i_a80_de_clk_ids,
},
};
module_platform_driver(sun9i_a80_de_clk_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016 Maxime Ripard. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu_mult.h"
#include "ccu_nk.h"
#include "ccu_nkm.h"
#include "ccu_nkmp.h"
#include "ccu_nm.h"
#include "ccu_phase.h"
#include "ccu_sdm.h"
#include "ccu-sun5i.h"
static struct ccu_nkmp pll_core_clk = {
.enable = BIT(31),
.n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
.k = _SUNXI_CCU_MULT(4, 2),
.m = _SUNXI_CCU_DIV(0, 2),
.p = _SUNXI_CCU_DIV(16, 2),
.common = {
.reg = 0x000,
.hw.init = CLK_HW_INIT("pll-core",
"hosc",
&ccu_nkmp_ops,
0),
},
};
/*
* The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
* the base (2x, 4x and 8x), and one variable divider (the one true
* pll audio).
*
* With sigma-delta modulation for fractional-N on the audio PLL,
* we have to use specific dividers. This means the variable divider
* can no longer be used, as the audio codec requests the exact clock
* rates we support through this mechanism. So we now hard code the
* variable divider to 1. This means the clock rates will no longer
* match the clock names.
*/
#define SUN5I_PLL_AUDIO_REG 0x008
static struct ccu_sdm_setting pll_audio_sdm_table[] = {
{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
};
static struct ccu_nm pll_audio_base_clk = {
.enable = BIT(31),
.n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
/*
* The datasheet is wrong here, this doesn't have any
* offset
*/
.m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
.sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, 0,
0x00c, BIT(31)),
.common = {
.reg = 0x008,
.features = CCU_FEATURE_SIGMA_DELTA_MOD,
.hw.init = CLK_HW_INIT("pll-audio-base",
"hosc",
&ccu_nm_ops,
0),
},
};
static struct ccu_mult pll_video0_clk = {
.enable = BIT(31),
.mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
.frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
270000000, 297000000),
.common = {
.reg = 0x010,
.features = (CCU_FEATURE_FRACTIONAL |
CCU_FEATURE_ALL_PREDIV),
.prediv = 8,
.hw.init = CLK_HW_INIT("pll-video0",
"hosc",
&ccu_mult_ops,
0),
},
};
static struct ccu_nkmp pll_ve_clk = {
.enable = BIT(31),
.n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
.k = _SUNXI_CCU_MULT(4, 2),
.m = _SUNXI_CCU_DIV(0, 2),
.p = _SUNXI_CCU_DIV(16, 2),
.common = {
.reg = 0x018,
.hw.init = CLK_HW_INIT("pll-ve",
"hosc",
&ccu_nkmp_ops,
0),
},
};
static struct ccu_nk pll_ddr_base_clk = {
.enable = BIT(31),
.n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
.k = _SUNXI_CCU_MULT(4, 2),
.common = {
.reg = 0x020,
.hw.init = CLK_HW_INIT("pll-ddr-base",
"hosc",
&ccu_nk_ops,
0),
},
};
static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,
CLK_IS_CRITICAL);
static struct ccu_div pll_ddr_other_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(16, 2, CLK_DIVIDER_POWER_OF_TWO),
.common = {
.reg = 0x020,
.hw.init = CLK_HW_INIT("pll-ddr-other", "pll-ddr-base",
&ccu_div_ops,
0),
},
};
static struct ccu_nk pll_periph_clk = {
.enable = BIT(31),
.n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
.k = _SUNXI_CCU_MULT(4, 2),
.fixed_post_div = 2,
.common = {
.reg = 0x028,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-periph",
"hosc",
&ccu_nk_ops,
0),
},
};
static struct ccu_mult pll_video1_clk = {
.enable = BIT(31),
.mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
.frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
270000000, 297000000),
.common = {
.reg = 0x030,
.features = (CCU_FEATURE_FRACTIONAL |
CCU_FEATURE_ALL_PREDIV),
.prediv = 8,
.hw.init = CLK_HW_INIT("pll-video1",
"hosc",
&ccu_mult_ops,
0),
},
};
static SUNXI_CCU_GATE(hosc_clk, "hosc", "osc24M", 0x050, BIT(0), 0);
#define SUN5I_AHB_REG 0x054
static const char * const cpu_parents[] = { "osc32k", "hosc",
"pll-core" , "pll-periph" };
static const struct ccu_mux_fixed_prediv cpu_predivs[] = {
{ .index = 3, .div = 3, },
};
static struct ccu_mux cpu_clk = {
.mux = {
.shift = 16,
.width = 2,
.fixed_predivs = cpu_predivs,
.n_predivs = ARRAY_SIZE(cpu_predivs),
},
.common = {
.reg = 0x054,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("cpu",
cpu_parents,
&ccu_mux_ops,
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
}
};
static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x054, 0, 2, 0);
static const char * const ahb_parents[] = { "axi" , "cpu", "pll-periph" };
static const struct ccu_mux_fixed_prediv ahb_predivs[] = {
{ .index = 2, .div = 2, },
};
static struct ccu_div ahb_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = {
.shift = 6,
.width = 2,
.fixed_predivs = ahb_predivs,
.n_predivs = ARRAY_SIZE(ahb_predivs),
},
.common = {
.reg = 0x054,
.hw.init = CLK_HW_INIT_PARENTS("ahb",
ahb_parents,
&ccu_div_ops,
0),
},
};
static struct clk_div_table apb0_div_table[] = {
{ .val = 0, .div = 2 },
{ .val = 1, .div = 2 },
{ .val = 2, .div = 4 },
{ .val = 3, .div = 8 },
{ /* Sentinel */ },
};
static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
0x054, 8, 2, apb0_div_table, 0);
static const char * const apb1_parents[] = { "hosc", "pll-periph", "osc32k" };
static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x058,
0, 5, /* M */
16, 2, /* P */
24, 2, /* mux */
0);
static SUNXI_CCU_GATE(axi_dram_clk, "axi-dram", "axi",
0x05c, BIT(0), 0);
static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
0x060, BIT(0), 0);
static SUNXI_CCU_GATE(ahb_ehci_clk, "ahb-ehci", "ahb",
0x060, BIT(1), 0);
static SUNXI_CCU_GATE(ahb_ohci_clk, "ahb-ohci", "ahb",
0x060, BIT(2), 0);
static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
0x060, BIT(5), 0);
static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
0x060, BIT(6), 0);
static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
0x060, BIT(7), 0);
static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
0x060, BIT(8), 0);
static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
0x060, BIT(9), 0);
static SUNXI_CCU_GATE(ahb_mmc2_clk, "ahb-mmc2", "ahb",
0x060, BIT(10), 0);
static SUNXI_CCU_GATE(ahb_nand_clk, "ahb-nand", "ahb",
0x060, BIT(13), 0);
static SUNXI_CCU_GATE(ahb_sdram_clk, "ahb-sdram", "ahb",
0x060, BIT(14), CLK_IS_CRITICAL);
static SUNXI_CCU_GATE(ahb_emac_clk, "ahb-emac", "ahb",
0x060, BIT(17), 0);
static SUNXI_CCU_GATE(ahb_ts_clk, "ahb-ts", "ahb",
0x060, BIT(18), 0);
static SUNXI_CCU_GATE(ahb_spi0_clk, "ahb-spi0", "ahb",
0x060, BIT(20), 0);
static SUNXI_CCU_GATE(ahb_spi1_clk, "ahb-spi1", "ahb",
0x060, BIT(21), 0);
static SUNXI_CCU_GATE(ahb_spi2_clk, "ahb-spi2", "ahb",
0x060, BIT(22), 0);
static SUNXI_CCU_GATE(ahb_gps_clk, "ahb-gps", "ahb",
0x060, BIT(26), 0);
static SUNXI_CCU_GATE(ahb_hstimer_clk, "ahb-hstimer", "ahb",
0x060, BIT(28), 0);
static SUNXI_CCU_GATE(ahb_ve_clk, "ahb-ve", "ahb",
0x064, BIT(0), 0);
static SUNXI_CCU_GATE(ahb_tve_clk, "ahb-tve", "ahb",
0x064, BIT(2), 0);
static SUNXI_CCU_GATE(ahb_lcd_clk, "ahb-lcd", "ahb",
0x064, BIT(4), 0);
static SUNXI_CCU_GATE(ahb_csi_clk, "ahb-csi", "ahb",
0x064, BIT(8), 0);
static SUNXI_CCU_GATE(ahb_hdmi_clk, "ahb-hdmi", "ahb",
0x064, BIT(11), 0);
static SUNXI_CCU_GATE(ahb_de_be_clk, "ahb-de-be", "ahb",
0x064, BIT(12), 0);
static SUNXI_CCU_GATE(ahb_de_fe_clk, "ahb-de-fe", "ahb",
0x064, BIT(14), 0);
static SUNXI_CCU_GATE(ahb_iep_clk, "ahb-iep", "ahb",
0x064, BIT(19), 0);
static SUNXI_CCU_GATE(ahb_gpu_clk, "ahb-gpu", "ahb",
0x064, BIT(20), 0);
static SUNXI_CCU_GATE(apb0_codec_clk, "apb0-codec", "apb0",
0x068, BIT(0), 0);
static SUNXI_CCU_GATE(apb0_spdif_clk, "apb0-spdif", "apb0",
0x068, BIT(1), 0);
static SUNXI_CCU_GATE(apb0_i2s_clk, "apb0-i2s", "apb0",
0x068, BIT(3), 0);
static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0",
0x068, BIT(5), 0);
static SUNXI_CCU_GATE(apb0_ir_clk, "apb0-ir", "apb0",
0x068, BIT(6), 0);
static SUNXI_CCU_GATE(apb0_keypad_clk, "apb0-keypad", "apb0",
0x068, BIT(10), 0);
static SUNXI_CCU_GATE(apb1_i2c0_clk, "apb1-i2c0", "apb1",
0x06c, BIT(0), 0);
static SUNXI_CCU_GATE(apb1_i2c1_clk, "apb1-i2c1", "apb1",
0x06c, BIT(1), 0);
static SUNXI_CCU_GATE(apb1_i2c2_clk, "apb1-i2c2", "apb1",
0x06c, BIT(2), 0);
static SUNXI_CCU_GATE(apb1_uart0_clk, "apb1-uart0", "apb1",
0x06c, BIT(16), 0);
static SUNXI_CCU_GATE(apb1_uart1_clk, "apb1-uart1", "apb1",
0x06c, BIT(17), 0);
static SUNXI_CCU_GATE(apb1_uart2_clk, "apb1-uart2", "apb1",
0x06c, BIT(18), 0);
static SUNXI_CCU_GATE(apb1_uart3_clk, "apb1-uart3", "apb1",
0x06c, BIT(19), 0);
static const char * const mod0_default_parents[] = { "hosc", "pll-periph",
"pll-ddr-other" };
static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", mod0_default_parents, 0x0b0,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
"pll-audio-2x", "pll-audio" };
static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_parents,
0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static const char * const spdif_parents[] = { "pll-audio-8x", "pll-audio-4x",
"pll-audio-2x", "pll-audio" };
static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", spdif_parents,
0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static const char * const keypad_parents[] = { "hosc", "losc"};
static const u8 keypad_table[] = { 0, 2 };
static struct ccu_mp keypad_clk = {
.enable = BIT(31),
.m = _SUNXI_CCU_DIV(8, 5),
.p = _SUNXI_CCU_DIV(20, 2),
.mux = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
.common = {
.reg = 0x0c4,
.hw.init = CLK_HW_INIT_PARENTS("keypad",
keypad_parents,
&ccu_mp_ops,
0),
},
};
static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "pll-periph",
0x0cc, BIT(6), 0);
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "pll-periph",
0x0cc, BIT(8), 0);
static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "pll-periph",
0x0cc, BIT(9), 0);
static const char * const gps_parents[] = { "hosc", "pll-periph",
"pll-video1", "pll-ve" };
static SUNXI_CCU_M_WITH_MUX_GATE(gps_clk, "gps", gps_parents,
0x0d0, 0, 3, 24, 2, BIT(31), 0);
static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
0x100, BIT(0), 0);
static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr",
0x100, BIT(1), 0);
static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "pll-ddr",
0x100, BIT(3), 0);
static SUNXI_CCU_GATE(dram_tve_clk, "dram-tve", "pll-ddr",
0x100, BIT(5), 0);
static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr",
0x100, BIT(25), 0);
static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr",
0x100, BIT(26), 0);
static SUNXI_CCU_GATE(dram_ace_clk, "dram-ace", "pll-ddr",
0x100, BIT(29), 0);
static SUNXI_CCU_GATE(dram_iep_clk, "dram-iep", "pll-ddr",
0x100, BIT(31), 0);
static const char * const de_parents[] = { "pll-video0", "pll-video1",
"pll-ddr-other" };
static SUNXI_CCU_M_WITH_MUX_GATE(de_be_clk, "de-be", de_parents,
0x104, 0, 4, 24, 2, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(de_fe_clk, "de-fe", de_parents,
0x10c, 0, 4, 24, 2, BIT(31), 0);
static const char * const tcon_parents[] = { "pll-video0", "pll-video1",
"pll-video0-2x", "pll-video1-2x" };
static SUNXI_CCU_MUX_WITH_GATE(tcon_ch0_clk, "tcon-ch0-sclk", tcon_parents,
0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_GATE(tcon_ch1_sclk2_clk, "tcon-ch1-sclk2",
tcon_parents,
0x12c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(tcon_ch1_sclk1_clk, "tcon-ch1-sclk1", "tcon-ch1-sclk2",
0x12c, 11, 1, BIT(15), CLK_SET_RATE_PARENT);
static const char * const csi_parents[] = { "hosc", "pll-video0", "pll-video1",
"pll-video0-2x", "pll-video1-2x" };
static const u8 csi_table[] = { 0, 1, 2, 5, 6 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi",
csi_parents, csi_table,
0x134, 0, 5, 24, 3, BIT(31), 0);
static SUNXI_CCU_GATE(ve_clk, "ve", "pll-ve",
0x13c, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
0x140, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(avs_clk, "avs", "hosc",
0x144, BIT(31), 0);
static const char * const hdmi_parents[] = { "pll-video0", "pll-video0-2x" };
static const u8 hdmi_table[] = { 0, 2 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(hdmi_clk, "hdmi",
hdmi_parents, hdmi_table,
0x150, 0, 4, 24, 2, BIT(31),
CLK_SET_RATE_PARENT);
static const char * const gpu_parents[] = { "pll-video0", "pll-ve",
"pll-ddr-other", "pll-video1",
"pll-video1-2x" };
static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents,
0x154, 0, 4, 24, 3, BIT(31), 0);
static const char * const mbus_parents[] = { "hosc", "pll-periph", "pll-ddr" };
static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
0x15c, 0, 4, 16, 2, 24, 2, BIT(31), CLK_IS_CRITICAL);
static SUNXI_CCU_GATE(iep_clk, "iep", "de-be",
0x160, BIT(31), 0);
static struct ccu_common *sun5i_a10s_ccu_clks[] = {
&hosc_clk.common,
&pll_core_clk.common,
&pll_audio_base_clk.common,
&pll_video0_clk.common,
&pll_ve_clk.common,
&pll_ddr_base_clk.common,
&pll_ddr_clk.common,
&pll_ddr_other_clk.common,
&pll_periph_clk.common,
&pll_video1_clk.common,
&cpu_clk.common,
&axi_clk.common,
&ahb_clk.common,
&apb0_clk.common,
&apb1_clk.common,
&axi_dram_clk.common,
&ahb_otg_clk.common,
&ahb_ehci_clk.common,
&ahb_ohci_clk.common,
&ahb_ss_clk.common,
&ahb_dma_clk.common,
&ahb_bist_clk.common,
&ahb_mmc0_clk.common,
&ahb_mmc1_clk.common,
&ahb_mmc2_clk.common,
&ahb_nand_clk.common,
&ahb_sdram_clk.common,
&ahb_emac_clk.common,
&ahb_ts_clk.common,
&ahb_spi0_clk.common,
&ahb_spi1_clk.common,
&ahb_spi2_clk.common,
&ahb_gps_clk.common,
&ahb_hstimer_clk.common,
&ahb_ve_clk.common,
&ahb_tve_clk.common,
&ahb_lcd_clk.common,
&ahb_csi_clk.common,
&ahb_hdmi_clk.common,
&ahb_de_be_clk.common,
&ahb_de_fe_clk.common,
&ahb_iep_clk.common,
&ahb_gpu_clk.common,
&apb0_codec_clk.common,
&apb0_spdif_clk.common,
&apb0_i2s_clk.common,
&apb0_pio_clk.common,
&apb0_ir_clk.common,
&apb0_keypad_clk.common,
&apb1_i2c0_clk.common,
&apb1_i2c1_clk.common,
&apb1_i2c2_clk.common,
&apb1_uart0_clk.common,
&apb1_uart1_clk.common,
&apb1_uart2_clk.common,
&apb1_uart3_clk.common,
&nand_clk.common,
&mmc0_clk.common,
&mmc1_clk.common,
&mmc2_clk.common,
&ts_clk.common,
&ss_clk.common,
&spi0_clk.common,
&spi1_clk.common,
&spi2_clk.common,
&ir_clk.common,
&i2s_clk.common,
&spdif_clk.common,
&keypad_clk.common,
&usb_ohci_clk.common,
&usb_phy0_clk.common,
&usb_phy1_clk.common,
&gps_clk.common,
&dram_ve_clk.common,
&dram_csi_clk.common,
&dram_ts_clk.common,
&dram_tve_clk.common,
&dram_de_fe_clk.common,
&dram_de_be_clk.common,
&dram_ace_clk.common,
&dram_iep_clk.common,
&de_be_clk.common,
&de_fe_clk.common,
&tcon_ch0_clk.common,
&tcon_ch1_sclk2_clk.common,
&tcon_ch1_sclk1_clk.common,
&csi_clk.common,
&ve_clk.common,
&codec_clk.common,
&avs_clk.common,
&hdmi_clk.common,
&gpu_clk.common,
&mbus_clk.common,
&iep_clk.common,
};
static const struct clk_hw *clk_parent_pll_audio[] = {
&pll_audio_base_clk.common.hw
};
/* We hardcode the divider to 1 for now */
static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
clk_parent_pll_audio,
1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
clk_parent_pll_audio,
2, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
clk_parent_pll_audio,
1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
clk_parent_pll_audio,
1, 2, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
&pll_video0_clk.common.hw,
1, 2, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
&pll_video1_clk.common.hw,
1, 2, CLK_SET_RATE_PARENT);
static struct clk_hw_onecell_data sun5i_a10s_hw_clks = {
.hws = {
[CLK_HOSC] = &hosc_clk.common.hw,
[CLK_PLL_CORE] = &pll_core_clk.common.hw,
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
[CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
[CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
[CLK_PLL_DDR_BASE] = &pll_ddr_base_clk.common.hw,
[CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
[CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,
[CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
[CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
[CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
[CLK_CPU] = &cpu_clk.common.hw,
[CLK_AXI] = &axi_clk.common.hw,
[CLK_AHB] = &ahb_clk.common.hw,
[CLK_APB0] = &apb0_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_DRAM_AXI] = &axi_dram_clk.common.hw,
[CLK_AHB_OTG] = &ahb_otg_clk.common.hw,
[CLK_AHB_EHCI] = &ahb_ehci_clk.common.hw,
[CLK_AHB_OHCI] = &ahb_ohci_clk.common.hw,
[CLK_AHB_SS] = &ahb_ss_clk.common.hw,
[CLK_AHB_DMA] = &ahb_dma_clk.common.hw,
[CLK_AHB_BIST] = &ahb_bist_clk.common.hw,
[CLK_AHB_MMC0] = &ahb_mmc0_clk.common.hw,
[CLK_AHB_MMC1] = &ahb_mmc1_clk.common.hw,
[CLK_AHB_MMC2] = &ahb_mmc2_clk.common.hw,
[CLK_AHB_NAND] = &ahb_nand_clk.common.hw,
[CLK_AHB_SDRAM] = &ahb_sdram_clk.common.hw,
[CLK_AHB_EMAC] = &ahb_emac_clk.common.hw,
[CLK_AHB_TS] = &ahb_ts_clk.common.hw,
[CLK_AHB_SPI0] = &ahb_spi0_clk.common.hw,
[CLK_AHB_SPI1] = &ahb_spi1_clk.common.hw,
[CLK_AHB_SPI2] = &ahb_spi2_clk.common.hw,
[CLK_AHB_GPS] = &ahb_gps_clk.common.hw,
[CLK_AHB_HSTIMER] = &ahb_hstimer_clk.common.hw,
[CLK_AHB_VE] = &ahb_ve_clk.common.hw,
[CLK_AHB_TVE] = &ahb_tve_clk.common.hw,
[CLK_AHB_LCD] = &ahb_lcd_clk.common.hw,
[CLK_AHB_CSI] = &ahb_csi_clk.common.hw,
[CLK_AHB_HDMI] = &ahb_hdmi_clk.common.hw,
[CLK_AHB_DE_BE] = &ahb_de_be_clk.common.hw,
[CLK_AHB_DE_FE] = &ahb_de_fe_clk.common.hw,
[CLK_AHB_IEP] = &ahb_iep_clk.common.hw,
[CLK_AHB_GPU] = &ahb_gpu_clk.common.hw,
[CLK_APB0_CODEC] = &apb0_codec_clk.common.hw,
[CLK_APB0_I2S] = &apb0_i2s_clk.common.hw,
[CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
[CLK_APB0_IR] = &apb0_ir_clk.common.hw,
[CLK_APB0_KEYPAD] = &apb0_keypad_clk.common.hw,
[CLK_APB1_I2C0] = &apb1_i2c0_clk.common.hw,
[CLK_APB1_I2C1] = &apb1_i2c1_clk.common.hw,
[CLK_APB1_I2C2] = &apb1_i2c2_clk.common.hw,
[CLK_APB1_UART0] = &apb1_uart0_clk.common.hw,
[CLK_APB1_UART1] = &apb1_uart1_clk.common.hw,
[CLK_APB1_UART2] = &apb1_uart2_clk.common.hw,
[CLK_APB1_UART3] = &apb1_uart3_clk.common.hw,
[CLK_NAND] = &nand_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_TS] = &ts_clk.common.hw,
[CLK_SS] = &ss_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI2] = &spi2_clk.common.hw,
[CLK_IR] = &ir_clk.common.hw,
[CLK_I2S] = &i2s_clk.common.hw,
[CLK_KEYPAD] = &keypad_clk.common.hw,
[CLK_USB_OHCI] = &usb_ohci_clk.common.hw,
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
[CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
[CLK_GPS] = &gps_clk.common.hw,
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
[CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
[CLK_DRAM_TS] = &dram_ts_clk.common.hw,
[CLK_DRAM_TVE] = &dram_tve_clk.common.hw,
[CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
[CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
[CLK_DRAM_ACE] = &dram_ace_clk.common.hw,
[CLK_DRAM_IEP] = &dram_iep_clk.common.hw,
[CLK_DE_BE] = &de_be_clk.common.hw,
[CLK_DE_FE] = &de_fe_clk.common.hw,
[CLK_TCON_CH0] = &tcon_ch0_clk.common.hw,
[CLK_TCON_CH1_SCLK] = &tcon_ch1_sclk2_clk.common.hw,
[CLK_TCON_CH1] = &tcon_ch1_sclk1_clk.common.hw,
[CLK_CSI] = &csi_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_CODEC] = &codec_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_HDMI] = &hdmi_clk.common.hw,
[CLK_GPU] = &gpu_clk.common.hw,
[CLK_MBUS] = &mbus_clk.common.hw,
[CLK_IEP] = &iep_clk.common.hw,
},
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun5i_a10s_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_GPS] = { 0x0d0, BIT(30) },
[RST_DE_BE] = { 0x104, BIT(30) },
[RST_DE_FE] = { 0x10c, BIT(30) },
[RST_TVE] = { 0x118, BIT(29) },
[RST_LCD] = { 0x118, BIT(30) },
[RST_CSI] = { 0x134, BIT(30) },
[RST_VE] = { 0x13c, BIT(0) },
[RST_GPU] = { 0x154, BIT(30) },
[RST_IEP] = { 0x160, BIT(30) },
};
static const struct sunxi_ccu_desc sun5i_a10s_ccu_desc = {
.ccu_clks = sun5i_a10s_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun5i_a10s_ccu_clks),
.hw_clks = &sun5i_a10s_hw_clks,
.resets = sun5i_a10s_ccu_resets,
.num_resets = ARRAY_SIZE(sun5i_a10s_ccu_resets),
};
/*
* The A13 is the A10s minus the TS, GPS, HDMI, I2S and the keypad
*/
static struct clk_hw_onecell_data sun5i_a13_hw_clks = {
.hws = {
[CLK_HOSC] = &hosc_clk.common.hw,
[CLK_PLL_CORE] = &pll_core_clk.common.hw,
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
[CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
[CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
[CLK_PLL_DDR_BASE] = &pll_ddr_base_clk.common.hw,
[CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
[CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,
[CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
[CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
[CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
[CLK_CPU] = &cpu_clk.common.hw,
[CLK_AXI] = &axi_clk.common.hw,
[CLK_AHB] = &ahb_clk.common.hw,
[CLK_APB0] = &apb0_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_DRAM_AXI] = &axi_dram_clk.common.hw,
[CLK_AHB_OTG] = &ahb_otg_clk.common.hw,
[CLK_AHB_EHCI] = &ahb_ehci_clk.common.hw,
[CLK_AHB_OHCI] = &ahb_ohci_clk.common.hw,
[CLK_AHB_SS] = &ahb_ss_clk.common.hw,
[CLK_AHB_DMA] = &ahb_dma_clk.common.hw,
[CLK_AHB_BIST] = &ahb_bist_clk.common.hw,
[CLK_AHB_MMC0] = &ahb_mmc0_clk.common.hw,
[CLK_AHB_MMC1] = &ahb_mmc1_clk.common.hw,
[CLK_AHB_MMC2] = &ahb_mmc2_clk.common.hw,
[CLK_AHB_NAND] = &ahb_nand_clk.common.hw,
[CLK_AHB_SDRAM] = &ahb_sdram_clk.common.hw,
[CLK_AHB_EMAC] = &ahb_emac_clk.common.hw,
[CLK_AHB_SPI0] = &ahb_spi0_clk.common.hw,
[CLK_AHB_SPI1] = &ahb_spi1_clk.common.hw,
[CLK_AHB_SPI2] = &ahb_spi2_clk.common.hw,
[CLK_AHB_HSTIMER] = &ahb_hstimer_clk.common.hw,
[CLK_AHB_VE] = &ahb_ve_clk.common.hw,
[CLK_AHB_TVE] = &ahb_tve_clk.common.hw,
[CLK_AHB_LCD] = &ahb_lcd_clk.common.hw,
[CLK_AHB_CSI] = &ahb_csi_clk.common.hw,
[CLK_AHB_DE_BE] = &ahb_de_be_clk.common.hw,
[CLK_AHB_DE_FE] = &ahb_de_fe_clk.common.hw,
[CLK_AHB_IEP] = &ahb_iep_clk.common.hw,
[CLK_AHB_GPU] = &ahb_gpu_clk.common.hw,
[CLK_APB0_CODEC] = &apb0_codec_clk.common.hw,
[CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
[CLK_APB0_IR] = &apb0_ir_clk.common.hw,
[CLK_APB1_I2C0] = &apb1_i2c0_clk.common.hw,
[CLK_APB1_I2C1] = &apb1_i2c1_clk.common.hw,
[CLK_APB1_I2C2] = &apb1_i2c2_clk.common.hw,
[CLK_APB1_UART0] = &apb1_uart0_clk.common.hw,
[CLK_APB1_UART1] = &apb1_uart1_clk.common.hw,
[CLK_APB1_UART2] = &apb1_uart2_clk.common.hw,
[CLK_APB1_UART3] = &apb1_uart3_clk.common.hw,
[CLK_NAND] = &nand_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_SS] = &ss_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI2] = &spi2_clk.common.hw,
[CLK_IR] = &ir_clk.common.hw,
[CLK_USB_OHCI] = &usb_ohci_clk.common.hw,
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
[CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
[CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
[CLK_DRAM_TVE] = &dram_tve_clk.common.hw,
[CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
[CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
[CLK_DRAM_ACE] = &dram_ace_clk.common.hw,
[CLK_DRAM_IEP] = &dram_iep_clk.common.hw,
[CLK_DE_BE] = &de_be_clk.common.hw,
[CLK_DE_FE] = &de_fe_clk.common.hw,
[CLK_TCON_CH0] = &tcon_ch0_clk.common.hw,
[CLK_TCON_CH1_SCLK] = &tcon_ch1_sclk2_clk.common.hw,
[CLK_TCON_CH1] = &tcon_ch1_sclk1_clk.common.hw,
[CLK_CSI] = &csi_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_CODEC] = &codec_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_GPU] = &gpu_clk.common.hw,
[CLK_MBUS] = &mbus_clk.common.hw,
[CLK_IEP] = &iep_clk.common.hw,
},
.num = CLK_NUMBER,
};
static const struct sunxi_ccu_desc sun5i_a13_ccu_desc = {
.ccu_clks = sun5i_a10s_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun5i_a10s_ccu_clks),
.hw_clks = &sun5i_a13_hw_clks,
.resets = sun5i_a10s_ccu_resets,
.num_resets = ARRAY_SIZE(sun5i_a10s_ccu_resets),
};
/*
* The GR8 is the A10s CCU minus the HDMI and keypad, plus SPDIF
*/
static struct clk_hw_onecell_data sun5i_gr8_hw_clks = {
.hws = {
[CLK_HOSC] = &hosc_clk.common.hw,
[CLK_PLL_CORE] = &pll_core_clk.common.hw,
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
[CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
[CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
[CLK_PLL_DDR_BASE] = &pll_ddr_base_clk.common.hw,
[CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
[CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,
[CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
[CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
[CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
[CLK_CPU] = &cpu_clk.common.hw,
[CLK_AXI] = &axi_clk.common.hw,
[CLK_AHB] = &ahb_clk.common.hw,
[CLK_APB0] = &apb0_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_DRAM_AXI] = &axi_dram_clk.common.hw,
[CLK_AHB_OTG] = &ahb_otg_clk.common.hw,
[CLK_AHB_EHCI] = &ahb_ehci_clk.common.hw,
[CLK_AHB_OHCI] = &ahb_ohci_clk.common.hw,
[CLK_AHB_SS] = &ahb_ss_clk.common.hw,
[CLK_AHB_DMA] = &ahb_dma_clk.common.hw,
[CLK_AHB_BIST] = &ahb_bist_clk.common.hw,
[CLK_AHB_MMC0] = &ahb_mmc0_clk.common.hw,
[CLK_AHB_MMC1] = &ahb_mmc1_clk.common.hw,
[CLK_AHB_MMC2] = &ahb_mmc2_clk.common.hw,
[CLK_AHB_NAND] = &ahb_nand_clk.common.hw,
[CLK_AHB_SDRAM] = &ahb_sdram_clk.common.hw,
[CLK_AHB_EMAC] = &ahb_emac_clk.common.hw,
[CLK_AHB_TS] = &ahb_ts_clk.common.hw,
[CLK_AHB_SPI0] = &ahb_spi0_clk.common.hw,
[CLK_AHB_SPI1] = &ahb_spi1_clk.common.hw,
[CLK_AHB_SPI2] = &ahb_spi2_clk.common.hw,
[CLK_AHB_GPS] = &ahb_gps_clk.common.hw,
[CLK_AHB_HSTIMER] = &ahb_hstimer_clk.common.hw,
[CLK_AHB_VE] = &ahb_ve_clk.common.hw,
[CLK_AHB_TVE] = &ahb_tve_clk.common.hw,
[CLK_AHB_LCD] = &ahb_lcd_clk.common.hw,
[CLK_AHB_CSI] = &ahb_csi_clk.common.hw,
[CLK_AHB_DE_BE] = &ahb_de_be_clk.common.hw,
[CLK_AHB_DE_FE] = &ahb_de_fe_clk.common.hw,
[CLK_AHB_IEP] = &ahb_iep_clk.common.hw,
[CLK_AHB_GPU] = &ahb_gpu_clk.common.hw,
[CLK_APB0_CODEC] = &apb0_codec_clk.common.hw,
[CLK_APB0_SPDIF] = &apb0_spdif_clk.common.hw,
[CLK_APB0_I2S] = &apb0_i2s_clk.common.hw,
[CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
[CLK_APB0_IR] = &apb0_ir_clk.common.hw,
[CLK_APB1_I2C0] = &apb1_i2c0_clk.common.hw,
[CLK_APB1_I2C1] = &apb1_i2c1_clk.common.hw,
[CLK_APB1_I2C2] = &apb1_i2c2_clk.common.hw,
[CLK_APB1_UART0] = &apb1_uart0_clk.common.hw,
[CLK_APB1_UART1] = &apb1_uart1_clk.common.hw,
[CLK_APB1_UART2] = &apb1_uart2_clk.common.hw,
[CLK_APB1_UART3] = &apb1_uart3_clk.common.hw,
[CLK_NAND] = &nand_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_TS] = &ts_clk.common.hw,
[CLK_SS] = &ss_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI2] = &spi2_clk.common.hw,
[CLK_IR] = &ir_clk.common.hw,
[CLK_I2S] = &i2s_clk.common.hw,
[CLK_SPDIF] = &spdif_clk.common.hw,
[CLK_USB_OHCI] = &usb_ohci_clk.common.hw,
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
[CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
[CLK_GPS] = &gps_clk.common.hw,
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
[CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
[CLK_DRAM_TS] = &dram_ts_clk.common.hw,
[CLK_DRAM_TVE] = &dram_tve_clk.common.hw,
[CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
[CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
[CLK_DRAM_ACE] = &dram_ace_clk.common.hw,
[CLK_DRAM_IEP] = &dram_iep_clk.common.hw,
[CLK_DE_BE] = &de_be_clk.common.hw,
[CLK_DE_FE] = &de_fe_clk.common.hw,
[CLK_TCON_CH0] = &tcon_ch0_clk.common.hw,
[CLK_TCON_CH1_SCLK] = &tcon_ch1_sclk2_clk.common.hw,
[CLK_TCON_CH1] = &tcon_ch1_sclk1_clk.common.hw,
[CLK_CSI] = &csi_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_CODEC] = &codec_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_GPU] = &gpu_clk.common.hw,
[CLK_MBUS] = &mbus_clk.common.hw,
[CLK_IEP] = &iep_clk.common.hw,
},
.num = CLK_NUMBER,
};
static const struct sunxi_ccu_desc sun5i_gr8_ccu_desc = {
.ccu_clks = sun5i_a10s_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun5i_a10s_ccu_clks),
.hw_clks = &sun5i_gr8_hw_clks,
.resets = sun5i_a10s_ccu_resets,
.num_resets = ARRAY_SIZE(sun5i_a10s_ccu_resets),
};
static void __init sun5i_ccu_init(struct device_node *node,
const struct sunxi_ccu_desc *desc)
{
void __iomem *reg;
u32 val;
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg)) {
pr_err("%pOF: Could not map the clock registers\n", node);
return;
}
/* Force the PLL-Audio-1x divider to 1 */
val = readl(reg + SUN5I_PLL_AUDIO_REG);
val &= ~GENMASK(29, 26);
writel(val | (0 << 26), reg + SUN5I_PLL_AUDIO_REG);
/*
* Use the peripheral PLL as the AHB parent, instead of CPU /
* AXI which have rate changes due to cpufreq.
*
* This is especially a big deal for the HS timer whose parent
* clock is AHB.
*/
val = readl(reg + SUN5I_AHB_REG);
val &= ~GENMASK(7, 6);
writel(val | (2 << 6), reg + SUN5I_AHB_REG);
of_sunxi_ccu_probe(node, reg, desc);
}
static void __init sun5i_a10s_ccu_setup(struct device_node *node)
{
sun5i_ccu_init(node, &sun5i_a10s_ccu_desc);
}
CLK_OF_DECLARE(sun5i_a10s_ccu, "allwinner,sun5i-a10s-ccu",
sun5i_a10s_ccu_setup);
static void __init sun5i_a13_ccu_setup(struct device_node *node)
{
sun5i_ccu_init(node, &sun5i_a13_ccu_desc);
}
CLK_OF_DECLARE(sun5i_a13_ccu, "allwinner,sun5i-a13-ccu",
sun5i_a13_ccu_setup);
static void __init sun5i_gr8_ccu_setup(struct device_node *node)
{
sun5i_ccu_init(node, &sun5i_gr8_ccu_desc);
}
CLK_OF_DECLARE(sun5i_gr8_ccu, "nextthing,gr8-ccu",
sun5i_gr8_ccu_setup);
| linux-master | drivers/clk/sunxi-ng/ccu-sun5i.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016 Maxime Ripard. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu_mult.h"
#include "ccu_nk.h"
#include "ccu_nkm.h"
#include "ccu_nkmp.h"
#include "ccu_nm.h"
#include "ccu_phase.h"
#include "ccu_sdm.h"
#include "ccu-sun8i-a23-a33.h"
static struct ccu_nkmp pll_cpux_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT(8, 5),
.k = _SUNXI_CCU_MULT(4, 2),
.m = _SUNXI_CCU_DIV(0, 2),
.p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
.common = {
.reg = 0x000,
.hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
&ccu_nkmp_ops,
0),
},
};
/*
* The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
* the base (2x, 4x and 8x), and one variable divider (the one true
* pll audio).
*
* With sigma-delta modulation for fractional-N on the audio PLL,
* we have to use specific dividers. This means the variable divider
* can no longer be used, as the audio codec requests the exact clock
* rates we support through this mechanism. So we now hard code the
* variable divider to 1. This means the clock rates will no longer
* match the clock names.
*/
#define SUN8I_A23_PLL_AUDIO_REG 0x008
static struct ccu_sdm_setting pll_audio_sdm_table[] = {
{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
};
static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
"osc24M", 0x008,
8, 7, /* N */
0, 5, /* M */
pll_audio_sdm_table, BIT(24),
0x284, BIT(31),
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
"osc24M", 0x010,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
"osc24M", 0x018,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
"osc24M", 0x020,
8, 5, /* N */
4, 2, /* K */
0, 2, /* M */
BIT(31), /* gate */
BIT(28), /* lock */
0);
static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
"osc24M", 0x028,
8, 5, /* N */
4, 2, /* K */
BIT(31), /* gate */
BIT(28), /* lock */
2, /* post-div */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
"osc24M", 0x038,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
/*
* The MIPI PLL has 2 modes: "MIPI" and "HDMI".
*
* The MIPI mode is a standard NKM-style clock. The HDMI mode is an
* integer / fractional clock with switchable multipliers and dividers.
* This is not supported here. We hardcode the PLL to MIPI mode.
*/
#define SUN8I_A23_PLL_MIPI_REG 0x040
static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
"pll-video", 0x040,
8, 4, /* N */
4, 2, /* K */
0, 4, /* M */
BIT(31) | BIT(23) | BIT(22), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
"osc24M", 0x044,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
"osc24M", 0x048,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static const char * const cpux_parents[] = { "osc32k", "osc24M",
"pll-cpux" , "pll-cpux" };
static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
0x050, 16, 2, CLK_IS_CRITICAL);
static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
static const char * const ahb1_parents[] = { "osc32k", "osc24M",
"axi" , "pll-periph" };
static const struct ccu_mux_var_prediv ahb1_predivs[] = {
{ .index = 3, .shift = 6, .width = 2 },
};
static struct ccu_div ahb1_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = {
.shift = 12,
.width = 2,
.var_predivs = ahb1_predivs,
.n_var_predivs = ARRAY_SIZE(ahb1_predivs),
},
.common = {
.reg = 0x054,
.features = CCU_FEATURE_VARIABLE_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("ahb1",
ahb1_parents,
&ccu_div_ops,
0),
},
};
static struct clk_div_table apb1_div_table[] = {
{ .val = 0, .div = 2 },
{ .val = 1, .div = 2 },
{ .val = 2, .div = 4 },
{ .val = 3, .div = 8 },
{ /* Sentinel */ },
};
static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
0x054, 8, 2, apb1_div_table, 0);
static const char * const apb2_parents[] = { "osc32k", "osc24M",
"pll-periph" , "pll-periph" };
static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
0, 5, /* M */
16, 2, /* P */
24, 2, /* mux */
0);
static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
0x060, BIT(1), 0);
static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
0x060, BIT(6), 0);
static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
0x060, BIT(8), 0);
static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
0x060, BIT(9), 0);
static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
0x060, BIT(10), 0);
static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
0x060, BIT(13), 0);
static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
0x060, BIT(14), 0);
static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
0x060, BIT(19), 0);
static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
0x060, BIT(20), 0);
static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
0x060, BIT(21), 0);
static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
0x060, BIT(24), 0);
static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1",
0x060, BIT(26), 0);
static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1",
0x060, BIT(29), 0);
static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
0x064, BIT(0), 0);
static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb1",
0x064, BIT(4), 0);
static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
0x064, BIT(8), 0);
static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb1",
0x064, BIT(12), 0);
static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1",
0x064, BIT(14), 0);
static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
0x064, BIT(20), 0);
static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
0x064, BIT(21), 0);
static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
0x064, BIT(22), 0);
static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1",
0x064, BIT(25), 0);
static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
0x068, BIT(0), 0);
static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
0x068, BIT(5), 0);
static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
0x068, BIT(12), 0);
static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
0x068, BIT(13), 0);
static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
0x06c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
0x06c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
0x06c, BIT(2), 0);
static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
0x06c, BIT(16), 0);
static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
0x06c, BIT(17), 0);
static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
0x06c, BIT(18), 0);
static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
0x06c, BIT(19), 0);
static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
0x06c, BIT(20), 0);
static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
0x088, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
0x088, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
0x08c, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
0x08c, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
0x090, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
0x090, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
"pll-audio-2x", "pll-audio" };
static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
/* TODO: the parent for most of the USB clocks is not known */
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
0x0cc, BIT(8), 0);
static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
0x0cc, BIT(9), 0);
static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
0x0cc, BIT(10), 0);
static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M",
0x0cc, BIT(11), 0);
static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M",
0x0cc, BIT(16), 0);
static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
0x100, BIT(0), 0);
static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr",
0x100, BIT(1), 0);
static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "pll-ddr",
0x100, BIT(16), 0);
static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr",
0x100, BIT(24), 0);
static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr",
0x100, BIT(26), 0);
static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
"pll-gpu", "pll-de" };
static const u8 de_table[] = { 0, 2, 3, 5 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
de_parents, de_table,
0x104, 0, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
de_parents, de_table,
0x10c, 0, 4, 24, 3, BIT(31), 0);
static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
"pll-mipi" };
static const u8 lcd_ch0_table[] = { 0, 2, 4 };
static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
lcd_ch0_parents, lcd_ch0_table,
0x118, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
static const u8 lcd_ch1_table[] = { 0, 2 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
lcd_ch1_parents, lcd_ch1_table,
0x12c, 0, 4, 24, 2, BIT(31), 0);
static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
"pll-mipi", "pll-ve" };
static const u8 csi_sclk_table[] = { 0, 3, 4, 5 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
csi_sclk_parents, csi_sclk_table,
0x134, 16, 4, 24, 3, BIT(31), 0);
static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
"osc24M" };
static const u8 csi_mclk_table[] = { 0, 3, 5 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
csi_mclk_parents, csi_mclk_table,
0x134, 0, 5, 8, 3, BIT(15), 0);
static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
0x140, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
0x144, BIT(31), 0);
static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
"pll-ddr" };
static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
static const u8 dsi_sclk_table[] = { 0, 2 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
dsi_sclk_parents, dsi_sclk_table,
0x168, 16, 4, 24, 2, BIT(31), 0);
static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
static const u8 dsi_dphy_table[] = { 0, 2 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
dsi_dphy_parents, dsi_dphy_table,
0x168, 0, 4, 8, 2, BIT(15), 0);
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc",
de_parents, de_table,
0x180, 0, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
0x1a0, 0, 3, BIT(31), 0);
static const char * const ats_parents[] = { "osc24M", "pll-periph" };
static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents,
0x1b0, 0, 3, 24, 2, BIT(31), 0);
static struct ccu_common *sun8i_a23_ccu_clks[] = {
&pll_cpux_clk.common,
&pll_audio_base_clk.common,
&pll_video_clk.common,
&pll_ve_clk.common,
&pll_ddr_clk.common,
&pll_periph_clk.common,
&pll_gpu_clk.common,
&pll_mipi_clk.common,
&pll_hsic_clk.common,
&pll_de_clk.common,
&cpux_clk.common,
&axi_clk.common,
&ahb1_clk.common,
&apb1_clk.common,
&apb2_clk.common,
&bus_mipi_dsi_clk.common,
&bus_dma_clk.common,
&bus_mmc0_clk.common,
&bus_mmc1_clk.common,
&bus_mmc2_clk.common,
&bus_nand_clk.common,
&bus_dram_clk.common,
&bus_hstimer_clk.common,
&bus_spi0_clk.common,
&bus_spi1_clk.common,
&bus_otg_clk.common,
&bus_ehci_clk.common,
&bus_ohci_clk.common,
&bus_ve_clk.common,
&bus_lcd_clk.common,
&bus_csi_clk.common,
&bus_de_fe_clk.common,
&bus_de_be_clk.common,
&bus_gpu_clk.common,
&bus_msgbox_clk.common,
&bus_spinlock_clk.common,
&bus_drc_clk.common,
&bus_codec_clk.common,
&bus_pio_clk.common,
&bus_i2s0_clk.common,
&bus_i2s1_clk.common,
&bus_i2c0_clk.common,
&bus_i2c1_clk.common,
&bus_i2c2_clk.common,
&bus_uart0_clk.common,
&bus_uart1_clk.common,
&bus_uart2_clk.common,
&bus_uart3_clk.common,
&bus_uart4_clk.common,
&nand_clk.common,
&mmc0_clk.common,
&mmc0_sample_clk.common,
&mmc0_output_clk.common,
&mmc1_clk.common,
&mmc1_sample_clk.common,
&mmc1_output_clk.common,
&mmc2_clk.common,
&mmc2_sample_clk.common,
&mmc2_output_clk.common,
&spi0_clk.common,
&spi1_clk.common,
&i2s0_clk.common,
&i2s1_clk.common,
&usb_phy0_clk.common,
&usb_phy1_clk.common,
&usb_hsic_clk.common,
&usb_hsic_12M_clk.common,
&usb_ohci_clk.common,
&dram_ve_clk.common,
&dram_csi_clk.common,
&dram_drc_clk.common,
&dram_de_fe_clk.common,
&dram_de_be_clk.common,
&de_be_clk.common,
&de_fe_clk.common,
&lcd_ch0_clk.common,
&lcd_ch1_clk.common,
&csi_sclk_clk.common,
&csi_mclk_clk.common,
&ve_clk.common,
&ac_dig_clk.common,
&avs_clk.common,
&mbus_clk.common,
&dsi_sclk_clk.common,
&dsi_dphy_clk.common,
&drc_clk.common,
&gpu_clk.common,
&ats_clk.common,
};
static const struct clk_hw *clk_parent_pll_audio[] = {
&pll_audio_base_clk.common.hw
};
/* We hardcode the divider to 1 for now */
static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
clk_parent_pll_audio,
1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
clk_parent_pll_audio,
2, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
clk_parent_pll_audio,
1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
clk_parent_pll_audio,
1, 2, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
&pll_periph_clk.common.hw,
1, 2, 0);
static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
&pll_video_clk.common.hw,
1, 2, 0);
static struct clk_hw_onecell_data sun8i_a23_hw_clks = {
.hws = {
[CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
[CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
[CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw,
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
[CLK_PLL_DDR0] = &pll_ddr_clk.common.hw,
[CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
[CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw,
[CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
[CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
[CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
[CLK_PLL_DE] = &pll_de_clk.common.hw,
[CLK_CPUX] = &cpux_clk.common.hw,
[CLK_AXI] = &axi_clk.common.hw,
[CLK_AHB1] = &ahb1_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_APB2] = &apb2_clk.common.hw,
[CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
[CLK_BUS_DMA] = &bus_dma_clk.common.hw,
[CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
[CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
[CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
[CLK_BUS_NAND] = &bus_nand_clk.common.hw,
[CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
[CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
[CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
[CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
[CLK_BUS_OTG] = &bus_otg_clk.common.hw,
[CLK_BUS_EHCI] = &bus_ehci_clk.common.hw,
[CLK_BUS_OHCI] = &bus_ohci_clk.common.hw,
[CLK_BUS_VE] = &bus_ve_clk.common.hw,
[CLK_BUS_LCD] = &bus_lcd_clk.common.hw,
[CLK_BUS_CSI] = &bus_csi_clk.common.hw,
[CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw,
[CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw,
[CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
[CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
[CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
[CLK_BUS_DRC] = &bus_drc_clk.common.hw,
[CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
[CLK_BUS_PIO] = &bus_pio_clk.common.hw,
[CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
[CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
[CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
[CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
[CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
[CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
[CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
[CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
[CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
[CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
[CLK_NAND] = &nand_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
[CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
[CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
[CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_I2S0] = &i2s0_clk.common.hw,
[CLK_I2S1] = &i2s1_clk.common.hw,
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
[CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
[CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
[CLK_USB_HSIC_12M] = &usb_hsic_12M_clk.common.hw,
[CLK_USB_OHCI] = &usb_ohci_clk.common.hw,
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
[CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
[CLK_DRAM_DRC] = &dram_drc_clk.common.hw,
[CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
[CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
[CLK_DE_BE] = &de_be_clk.common.hw,
[CLK_DE_FE] = &de_fe_clk.common.hw,
[CLK_LCD_CH0] = &lcd_ch0_clk.common.hw,
[CLK_LCD_CH1] = &lcd_ch1_clk.common.hw,
[CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
[CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_AC_DIG] = &ac_dig_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_MBUS] = &mbus_clk.common.hw,
[CLK_DSI_SCLK] = &dsi_sclk_clk.common.hw,
[CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
[CLK_DRC] = &drc_clk.common.hw,
[CLK_GPU] = &gpu_clk.common.hw,
[CLK_ATS] = &ats_clk.common.hw,
},
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun8i_a23_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_HSIC] = { 0x0cc, BIT(2) },
[RST_MBUS] = { 0x0fc, BIT(31) },
[RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
[RST_BUS_DMA] = { 0x2c0, BIT(6) },
[RST_BUS_MMC0] = { 0x2c0, BIT(8) },
[RST_BUS_MMC1] = { 0x2c0, BIT(9) },
[RST_BUS_MMC2] = { 0x2c0, BIT(10) },
[RST_BUS_NAND] = { 0x2c0, BIT(13) },
[RST_BUS_DRAM] = { 0x2c0, BIT(14) },
[RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
[RST_BUS_SPI0] = { 0x2c0, BIT(20) },
[RST_BUS_SPI1] = { 0x2c0, BIT(21) },
[RST_BUS_OTG] = { 0x2c0, BIT(24) },
[RST_BUS_EHCI] = { 0x2c0, BIT(26) },
[RST_BUS_OHCI] = { 0x2c0, BIT(29) },
[RST_BUS_VE] = { 0x2c4, BIT(0) },
[RST_BUS_LCD] = { 0x2c4, BIT(4) },
[RST_BUS_CSI] = { 0x2c4, BIT(8) },
[RST_BUS_DE_BE] = { 0x2c4, BIT(12) },
[RST_BUS_DE_FE] = { 0x2c4, BIT(14) },
[RST_BUS_GPU] = { 0x2c4, BIT(20) },
[RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
[RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
[RST_BUS_DRC] = { 0x2c4, BIT(25) },
[RST_BUS_LVDS] = { 0x2c8, BIT(0) },
[RST_BUS_CODEC] = { 0x2d0, BIT(0) },
[RST_BUS_I2S0] = { 0x2d0, BIT(12) },
[RST_BUS_I2S1] = { 0x2d0, BIT(13) },
[RST_BUS_I2C0] = { 0x2d8, BIT(0) },
[RST_BUS_I2C1] = { 0x2d8, BIT(1) },
[RST_BUS_I2C2] = { 0x2d8, BIT(2) },
[RST_BUS_UART0] = { 0x2d8, BIT(16) },
[RST_BUS_UART1] = { 0x2d8, BIT(17) },
[RST_BUS_UART2] = { 0x2d8, BIT(18) },
[RST_BUS_UART3] = { 0x2d8, BIT(19) },
[RST_BUS_UART4] = { 0x2d8, BIT(20) },
};
static const struct sunxi_ccu_desc sun8i_a23_ccu_desc = {
.ccu_clks = sun8i_a23_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_a23_ccu_clks),
.hw_clks = &sun8i_a23_hw_clks,
.resets = sun8i_a23_ccu_resets,
.num_resets = ARRAY_SIZE(sun8i_a23_ccu_resets),
};
static int sun8i_a23_ccu_probe(struct platform_device *pdev)
{
void __iomem *reg;
u32 val;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
/* Force the PLL-Audio-1x divider to 1 */
val = readl(reg + SUN8I_A23_PLL_AUDIO_REG);
val &= ~GENMASK(19, 16);
writel(val | (0 << 16), reg + SUN8I_A23_PLL_AUDIO_REG);
/* Force PLL-MIPI to MIPI mode */
val = readl(reg + SUN8I_A23_PLL_MIPI_REG);
val &= ~BIT(16);
writel(val, reg + SUN8I_A23_PLL_MIPI_REG);
return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_a23_ccu_desc);
}
static const struct of_device_id sun8i_a23_ccu_ids[] = {
{ .compatible = "allwinner,sun8i-a23-ccu" },
{ }
};
static struct platform_driver sun8i_a23_ccu_driver = {
.probe = sun8i_a23_ccu_probe,
.driver = {
.name = "sun8i-a23-ccu",
.suppress_bind_attrs = true,
.of_match_table = sun8i_a23_ccu_ids,
},
};
module_platform_driver(sun8i_a23_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun8i-a23.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Maxime Ripard
* Maxime Ripard <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include "ccu_gate.h"
#include "ccu_nk.h"
struct _ccu_nk {
unsigned long n, min_n, max_n;
unsigned long k, min_k, max_k;
};
static unsigned long ccu_nk_find_best(unsigned long parent, unsigned long rate,
struct _ccu_nk *nk)
{
unsigned long best_rate = 0;
unsigned int best_k = 0, best_n = 0;
unsigned int _k, _n;
for (_k = nk->min_k; _k <= nk->max_k; _k++) {
for (_n = nk->min_n; _n <= nk->max_n; _n++) {
unsigned long tmp_rate = parent * _n * _k;
if (tmp_rate > rate)
continue;
if ((rate - tmp_rate) < (rate - best_rate)) {
best_rate = tmp_rate;
best_k = _k;
best_n = _n;
}
}
}
nk->k = best_k;
nk->n = best_n;
return best_rate;
}
static void ccu_nk_disable(struct clk_hw *hw)
{
struct ccu_nk *nk = hw_to_ccu_nk(hw);
return ccu_gate_helper_disable(&nk->common, nk->enable);
}
static int ccu_nk_enable(struct clk_hw *hw)
{
struct ccu_nk *nk = hw_to_ccu_nk(hw);
return ccu_gate_helper_enable(&nk->common, nk->enable);
}
static int ccu_nk_is_enabled(struct clk_hw *hw)
{
struct ccu_nk *nk = hw_to_ccu_nk(hw);
return ccu_gate_helper_is_enabled(&nk->common, nk->enable);
}
static unsigned long ccu_nk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct ccu_nk *nk = hw_to_ccu_nk(hw);
unsigned long rate, n, k;
u32 reg;
reg = readl(nk->common.base + nk->common.reg);
n = reg >> nk->n.shift;
n &= (1 << nk->n.width) - 1;
n += nk->n.offset;
if (!n)
n++;
k = reg >> nk->k.shift;
k &= (1 << nk->k.width) - 1;
k += nk->k.offset;
if (!k)
k++;
rate = parent_rate * n * k;
if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nk->fixed_post_div;
return rate;
}
static long ccu_nk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
struct ccu_nk *nk = hw_to_ccu_nk(hw);
struct _ccu_nk _nk;
if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate *= nk->fixed_post_div;
_nk.min_n = nk->n.min ?: 1;
_nk.max_n = nk->n.max ?: 1 << nk->n.width;
_nk.min_k = nk->k.min ?: 1;
_nk.max_k = nk->k.max ?: 1 << nk->k.width;
rate = ccu_nk_find_best(*parent_rate, rate, &_nk);
if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate = rate / nk->fixed_post_div;
return rate;
}
static int ccu_nk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct ccu_nk *nk = hw_to_ccu_nk(hw);
unsigned long flags;
struct _ccu_nk _nk;
u32 reg;
if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate = rate * nk->fixed_post_div;
_nk.min_n = nk->n.min ?: 1;
_nk.max_n = nk->n.max ?: 1 << nk->n.width;
_nk.min_k = nk->k.min ?: 1;
_nk.max_k = nk->k.max ?: 1 << nk->k.width;
ccu_nk_find_best(parent_rate, rate, &_nk);
spin_lock_irqsave(nk->common.lock, flags);
reg = readl(nk->common.base + nk->common.reg);
reg &= ~GENMASK(nk->n.width + nk->n.shift - 1, nk->n.shift);
reg &= ~GENMASK(nk->k.width + nk->k.shift - 1, nk->k.shift);
reg |= (_nk.k - nk->k.offset) << nk->k.shift;
reg |= (_nk.n - nk->n.offset) << nk->n.shift;
writel(reg, nk->common.base + nk->common.reg);
spin_unlock_irqrestore(nk->common.lock, flags);
ccu_helper_wait_for_lock(&nk->common, nk->lock);
return 0;
}
const struct clk_ops ccu_nk_ops = {
.disable = ccu_nk_disable,
.enable = ccu_nk_enable,
.is_enabled = ccu_nk_is_enabled,
.recalc_rate = ccu_nk_recalc_rate,
.round_rate = ccu_nk_round_rate,
.set_rate = ccu_nk_set_rate,
};
EXPORT_SYMBOL_NS_GPL(ccu_nk_ops, SUNXI_CCU);
| linux-master | drivers/clk/sunxi-ng/ccu_nk.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2017 Icenowy Zheng <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu_nm.h"
#include "ccu-sun50i-h6-r.h"
/*
* Information about AR100 and AHB/APB clocks in R_CCU are gathered from
* clock definitions in the BSP source code.
*/
static const char * const ar100_r_apb2_parents[] = { "osc24M", "osc32k",
"iosc", "pll-periph0" };
static const struct ccu_mux_var_prediv ar100_r_apb2_predivs[] = {
{ .index = 3, .shift = 0, .width = 5 },
};
static struct ccu_div ar100_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = {
.shift = 24,
.width = 2,
.var_predivs = ar100_r_apb2_predivs,
.n_var_predivs = ARRAY_SIZE(ar100_r_apb2_predivs),
},
.common = {
.reg = 0x000,
.features = CCU_FEATURE_VARIABLE_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("ar100",
ar100_r_apb2_parents,
&ccu_div_ops,
0),
},
};
static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0);
static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0);
static struct ccu_div r_apb2_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = {
.shift = 24,
.width = 2,
.var_predivs = ar100_r_apb2_predivs,
.n_var_predivs = ARRAY_SIZE(ar100_r_apb2_predivs),
},
.common = {
.reg = 0x010,
.features = CCU_FEATURE_VARIABLE_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("r-apb2",
ar100_r_apb2_parents,
&ccu_div_ops,
0),
},
};
/*
* Information about the gate/resets are gathered from the clock header file
* in the BSP source code, although most of them are unused. The existence
* of the hardware block is verified with "3.1 Memory Mapping" chapter in
* "Allwinner H6 V200 User Manual V1.1"; and the parent APB buses are verified
* with "3.3.2.1 System Bus Tree" chapter inthe same document.
*/
static SUNXI_CCU_GATE(r_apb1_timer_clk, "r-apb1-timer", "r-apb1",
0x11c, BIT(0), 0);
static SUNXI_CCU_GATE(r_apb1_twd_clk, "r-apb1-twd", "r-apb1",
0x12c, BIT(0), 0);
static SUNXI_CCU_GATE(r_apb1_pwm_clk, "r-apb1-pwm", "r-apb1",
0x13c, BIT(0), 0);
static SUNXI_CCU_GATE(r_apb2_uart_clk, "r-apb2-uart", "r-apb2",
0x18c, BIT(0), 0);
static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
0x19c, BIT(0), 0);
static SUNXI_CCU_GATE(r_apb2_rsb_clk, "r-apb2-rsb", "r-apb2",
0x1bc, BIT(0), 0);
static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
0x1cc, BIT(0), 0);
static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
0x1ec, BIT(0), 0);
static SUNXI_CCU_GATE(r_apb1_rtc_clk, "r-apb1-rtc", "r-apb1",
0x20c, BIT(0), CLK_IGNORE_UNUSED);
/* Information of IR(RX) mod clock is gathered from BSP source code */
static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
r_mod0_default_parents, 0x1c0,
0, 5, /* M */
8, 2, /* P */
24, 1, /* mux */
BIT(31), /* gate */
0);
/*
* BSP didn't use the 1-wire function at all now, and the information about
* this mod clock is guessed from the IR mod clock above. The existence of
* this mod clock is proven by BSP clock header, and the dividers are verified
* by contents in the 1-wire related chapter of the User Manual.
*/
static SUNXI_CCU_MP_WITH_MUX_GATE(w1_clk, "w1",
r_mod0_default_parents, 0x1e0,
0, 5, /* M */
8, 2, /* P */
24, 1, /* mux */
BIT(31), /* gate */
0);
static struct ccu_common *sun50i_h6_r_ccu_clks[] = {
&ar100_clk.common,
&r_apb1_clk.common,
&r_apb2_clk.common,
&r_apb1_timer_clk.common,
&r_apb1_twd_clk.common,
&r_apb1_pwm_clk.common,
&r_apb2_uart_clk.common,
&r_apb2_i2c_clk.common,
&r_apb2_rsb_clk.common,
&r_apb1_ir_clk.common,
&r_apb1_w1_clk.common,
&r_apb1_rtc_clk.common,
&ir_clk.common,
&w1_clk.common,
};
static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
.hws = {
[CLK_AR100] = &ar100_clk.common.hw,
[CLK_R_AHB] = &r_ahb_clk.hw,
[CLK_R_APB1] = &r_apb1_clk.common.hw,
[CLK_R_APB2] = &r_apb2_clk.common.hw,
[CLK_R_APB1_TIMER] = &r_apb1_timer_clk.common.hw,
[CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw,
[CLK_R_APB1_PWM] = &r_apb1_pwm_clk.common.hw,
[CLK_R_APB2_UART] = &r_apb2_uart_clk.common.hw,
[CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw,
[CLK_R_APB2_RSB] = &r_apb2_rsb_clk.common.hw,
[CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw,
[CLK_R_APB1_W1] = &r_apb1_w1_clk.common.hw,
[CLK_R_APB1_RTC] = &r_apb1_rtc_clk.common.hw,
[CLK_IR] = &ir_clk.common.hw,
[CLK_W1] = &w1_clk.common.hw,
},
.num = CLK_NUMBER,
};
static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = {
.hws = {
[CLK_R_AHB] = &r_ahb_clk.hw,
[CLK_R_APB1] = &r_apb1_clk.common.hw,
[CLK_R_APB2] = &r_apb2_clk.common.hw,
[CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw,
[CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw,
[CLK_R_APB2_RSB] = &r_apb2_rsb_clk.common.hw,
[CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw,
[CLK_R_APB1_RTC] = &r_apb1_rtc_clk.common.hw,
[CLK_IR] = &ir_clk.common.hw,
},
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
[RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
[RST_R_APB1_TWD] = { 0x12c, BIT(16) },
[RST_R_APB1_PWM] = { 0x13c, BIT(16) },
[RST_R_APB2_UART] = { 0x18c, BIT(16) },
[RST_R_APB2_I2C] = { 0x19c, BIT(16) },
[RST_R_APB2_RSB] = { 0x1bc, BIT(16) },
[RST_R_APB1_IR] = { 0x1cc, BIT(16) },
[RST_R_APB1_W1] = { 0x1ec, BIT(16) },
};
static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = {
[RST_R_APB1_TWD] = { 0x12c, BIT(16) },
[RST_R_APB2_I2C] = { 0x19c, BIT(16) },
[RST_R_APB2_RSB] = { 0x1bc, BIT(16) },
[RST_R_APB1_IR] = { 0x1cc, BIT(16) },
};
static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
.ccu_clks = sun50i_h6_r_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks),
.hw_clks = &sun50i_h6_r_hw_clks,
.resets = sun50i_h6_r_ccu_resets,
.num_resets = ARRAY_SIZE(sun50i_h6_r_ccu_resets),
};
static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = {
.ccu_clks = sun50i_h6_r_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks),
.hw_clks = &sun50i_h616_r_hw_clks,
.resets = sun50i_h616_r_ccu_resets,
.num_resets = ARRAY_SIZE(sun50i_h616_r_ccu_resets),
};
static int sun50i_h6_r_ccu_probe(struct platform_device *pdev)
{
const struct sunxi_ccu_desc *desc;
void __iomem *reg;
desc = of_device_get_match_data(&pdev->dev);
if (!desc)
return -EINVAL;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
return devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
}
static const struct of_device_id sun50i_h6_r_ccu_ids[] = {
{
.compatible = "allwinner,sun50i-h6-r-ccu",
.data = &sun50i_h6_r_ccu_desc,
},
{
.compatible = "allwinner,sun50i-h616-r-ccu",
.data = &sun50i_h616_r_ccu_desc,
},
{ }
};
static struct platform_driver sun50i_h6_r_ccu_driver = {
.probe = sun50i_h6_r_ccu_probe,
.driver = {
.name = "sun50i-h6-r-ccu",
.suppress_bind_attrs = true,
.of_match_table = sun50i_h6_r_ccu_ids,
},
};
module_platform_driver(sun50i_h6_r_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016 Maxime Ripard. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu_mult.h"
#include "ccu_nk.h"
#include "ccu_nkm.h"
#include "ccu_nkmp.h"
#include "ccu_nm.h"
#include "ccu_phase.h"
#include "ccu-sun50i-a64.h"
static struct ccu_nkmp pll_cpux_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT(8, 5),
.k = _SUNXI_CCU_MULT(4, 2),
.m = _SUNXI_CCU_DIV(0, 2),
.p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
.common = {
.reg = 0x000,
.hw.init = CLK_HW_INIT("pll-cpux",
"osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
/*
* The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
* the base (2x, 4x and 8x), and one variable divider (the one true
* pll audio).
*
* With sigma-delta modulation for fractional-N on the audio PLL,
* we have to use specific dividers. This means the variable divider
* can no longer be used, as the audio codec requests the exact clock
* rates we support through this mechanism. So we now hard code the
* variable divider to 1. This means the clock rates will no longer
* match the clock names.
*/
#define SUN50I_A64_PLL_AUDIO_REG 0x008
static struct ccu_sdm_setting pll_audio_sdm_table[] = {
{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
};
static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
"osc24M", 0x008,
8, 7, /* N */
0, 5, /* M */
pll_audio_sdm_table, BIT(24),
0x284, BIT(31),
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST(pll_video0_clk, "pll-video0",
"osc24M", 0x010,
192000000, /* Minimum rate */
1008000000, /* Maximum rate */
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
"osc24M", 0x018,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
"osc24M", 0x020,
8, 5, /* N */
4, 2, /* K */
0, 2, /* M */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static struct ccu_nk pll_periph0_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT(8, 5),
.k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
.fixed_post_div = 2,
.common = {
.reg = 0x028,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
&ccu_nk_ops, CLK_SET_RATE_UNGATE),
},
};
static struct ccu_nk pll_periph1_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT(8, 5),
.k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
.fixed_post_div = 2,
.common = {
.reg = 0x02c,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
&ccu_nk_ops, CLK_SET_RATE_UNGATE),
},
};
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
"osc24M", 0x030,
192000000, /* Minimum rate */
1008000000, /* Maximum rate */
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
"osc24M", 0x038,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
/*
* The output function can be changed to something more complex that
* we do not handle yet.
*
* Hardcode the mode so that we don't fall in that case.
*/
#define SUN50I_A64_PLL_MIPI_REG 0x040
static struct ccu_nkm pll_mipi_clk = {
/*
* The bit 23 and 22 are called "LDO{1,2}_EN" on the SoC's
* user manual, and by experiments the PLL doesn't work without
* these bits toggled.
*/
.enable = BIT(31) | BIT(23) | BIT(22),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT(8, 4),
.k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
.m = _SUNXI_CCU_DIV(0, 4),
.common = {
.reg = 0x040,
.hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
&ccu_nkm_ops,
CLK_SET_RATE_UNGATE | CLK_SET_RATE_PARENT),
.features = CCU_FEATURE_CLOSEST_RATE,
},
};
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
"osc24M", 0x044,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
"osc24M", 0x048,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
"osc24M", 0x04c,
8, 7, /* N */
0, 2, /* M */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static const char * const cpux_parents[] = { "osc32k", "osc24M",
"pll-cpux", "pll-cpux" };
static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
static const char * const ahb1_parents[] = { "osc32k", "osc24M",
"axi", "pll-periph0" };
static const struct ccu_mux_var_prediv ahb1_predivs[] = {
{ .index = 3, .shift = 6, .width = 2 },
};
static struct ccu_div ahb1_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = {
.shift = 12,
.width = 2,
.var_predivs = ahb1_predivs,
.n_var_predivs = ARRAY_SIZE(ahb1_predivs),
},
.common = {
.reg = 0x054,
.features = CCU_FEATURE_VARIABLE_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("ahb1",
ahb1_parents,
&ccu_div_ops,
0),
},
};
static struct clk_div_table apb1_div_table[] = {
{ .val = 0, .div = 2 },
{ .val = 1, .div = 2 },
{ .val = 2, .div = 4 },
{ .val = 3, .div = 8 },
{ /* Sentinel */ },
};
static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
0x054, 8, 2, apb1_div_table, 0);
static const char * const apb2_parents[] = { "osc32k", "osc24M",
"pll-periph0-2x",
"pll-periph0-2x" };
static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
0, 5, /* M */
16, 2, /* P */
24, 2, /* mux */
0);
static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
{ .index = 1, .div = 2 },
};
static struct ccu_mux ahb2_clk = {
.mux = {
.shift = 0,
.width = 1,
.fixed_predivs = ahb2_fixed_predivs,
.n_predivs = ARRAY_SIZE(ahb2_fixed_predivs),
},
.common = {
.reg = 0x05c,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("ahb2",
ahb2_parents,
&ccu_mux_ops,
0),
},
};
static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
0x060, BIT(1), 0);
static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
0x060, BIT(5), 0);
static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
0x060, BIT(6), 0);
static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
0x060, BIT(8), 0);
static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
0x060, BIT(9), 0);
static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
0x060, BIT(10), 0);
static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
0x060, BIT(13), 0);
static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
0x060, BIT(14), 0);
static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
0x060, BIT(17), 0);
static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
0x060, BIT(18), 0);
static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
0x060, BIT(19), 0);
static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
0x060, BIT(20), 0);
static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
0x060, BIT(21), 0);
static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
0x060, BIT(23), 0);
static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
0x060, BIT(24), 0);
static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",
0x060, BIT(25), 0);
static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
0x060, BIT(28), 0);
static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2",
0x060, BIT(29), 0);
static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
0x064, BIT(0), 0);
static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
0x064, BIT(3), 0);
static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1",
0x064, BIT(4), 0);
static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
0x064, BIT(5), 0);
static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
0x064, BIT(8), 0);
static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",
0x064, BIT(11), 0);
static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
0x064, BIT(12), 0);
static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
0x064, BIT(20), 0);
static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
0x064, BIT(21), 0);
static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
0x064, BIT(22), 0);
static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
0x068, BIT(0), 0);
static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
0x068, BIT(1), 0);
static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
0x068, BIT(5), 0);
static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
0x068, BIT(8), 0);
static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
0x068, BIT(12), 0);
static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
0x068, BIT(13), 0);
static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
0x068, BIT(14), 0);
static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
0x06c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
0x06c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
0x06c, BIT(2), 0);
static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
0x06c, BIT(5), 0);
static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
0x06c, BIT(16), 0);
static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
0x06c, BIT(17), 0);
static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
0x06c, BIT(18), 0);
static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
0x06c, BIT(19), 0);
static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
0x06c, BIT(20), 0);
static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
0x070, BIT(7), 0);
static struct clk_div_table ths_div_table[] = {
{ .val = 0, .div = 1 },
{ .val = 1, .div = 2 },
{ .val = 2, .div = 4 },
{ .val = 3, .div = 6 },
{ /* Sentinel */ },
};
static const char * const ths_parents[] = { "osc24M" };
static struct ccu_div ths_clk = {
.enable = BIT(31),
.div = _SUNXI_CCU_DIV_TABLE(0, 2, ths_div_table),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0x074,
.hw.init = CLK_HW_INIT_PARENTS("ths",
ths_parents,
&ccu_div_ops,
0),
},
};
static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
"pll-periph1" };
static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
/*
* MMC clocks are the new timing mode (see A83T & H3) variety, but without
* the mode switch. This means they have a 2x post divider between the clock
* and the MMC module. This is not documented in the manual, but is taken
* into consideration when setting the mmc module clocks in the BSP kernel.
* Without it, MMC performance is degraded.
*
* We model it here to be consistent with other SoCs supporting this mode.
* The alternative would be to add the 2x multiplier when setting the MMC
* module clock in the MMC driver, just for the A64.
*/
static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x",
"pll-periph1-2x" };
static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0",
mmc_default_parents, 0x088,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
2, /* post-div */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1",
mmc_default_parents, 0x08c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
2, /* post-div */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2",
mmc_default_parents, 0x090,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
2, /* post-div */
0);
static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
0, 4, /* M */
16, 2, /* P */
24, 4, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
"pll-audio-2x", "pll-audio" };
static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
0x0cc, BIT(8), 0);
static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
0x0cc, BIT(9), 0);
static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
0x0cc, BIT(10), 0);
static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M",
0x0cc, BIT(11), 0);
static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M",
0x0cc, BIT(16), 0);
static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0",
0x0cc, BIT(17), 0);
static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
0x100, BIT(0), 0);
static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
0x100, BIT(1), 0);
static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
0x100, BIT(2), 0);
static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
0x100, BIT(3), 0);
static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
0x104, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
/*
* DSI output seems to work only when PLL_MIPI selected. Set it and prevent
* the mux from reparenting.
*/
#define SUN50I_A64_TCON0_CLK_REG 0x118
static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
static const u8 tcon0_table[] = { 0, 2, };
static SUNXI_CCU_MUX_TABLE_WITH_GATE_CLOSEST(tcon0_clk, "tcon0", tcon0_parents,
tcon0_table, 0x118, 24, 3, BIT(31),
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
static const u8 tcon1_table[] = { 0, 2, };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(tcon1_clk, "tcon1", tcon1_parents,
tcon1_table, 0x11c,
0, 4, /* M */
24, 2, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
0x124, 0, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
0x130, BIT(31), 0);
static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
0x134, 16, 4, 24, 3, BIT(31), 0);
static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
0x134, 0, 5, 8, 3, BIT(15), 0);
static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
0x140, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",
0x140, BIT(30), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
0x144, BIT(31), 0);
static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
static SUNXI_CCU_M_WITH_MUX_GATE_CLOSEST(hdmi_clk, "hdmi", hdmi_parents,
0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
0x154, BIT(31), 0);
static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
"pll-ddr0", "pll-ddr1" };
static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
static const u8 dsi_dphy_table[] = { 0, 2, };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(dsi_dphy_clk, "dsi-dphy",
dsi_dphy_parents, dsi_dphy_table,
0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
/* Fixed Factor clocks */
static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
static const struct clk_hw *clk_parent_pll_audio[] = {
&pll_audio_base_clk.common.hw
};
/* We hardcode the divider to 1 for now */
static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
clk_parent_pll_audio,
1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
clk_parent_pll_audio,
2, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
clk_parent_pll_audio,
1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
clk_parent_pll_audio,
1, 2, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
&pll_periph0_clk.common.hw,
1, 2, 0);
static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
&pll_periph1_clk.common.hw,
1, 2, 0);
static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
&pll_video0_clk.common.hw,
1, 2, CLK_SET_RATE_PARENT);
static struct ccu_common *sun50i_a64_ccu_clks[] = {
&pll_cpux_clk.common,
&pll_audio_base_clk.common,
&pll_video0_clk.common,
&pll_ve_clk.common,
&pll_ddr0_clk.common,
&pll_periph0_clk.common,
&pll_periph1_clk.common,
&pll_video1_clk.common,
&pll_gpu_clk.common,
&pll_mipi_clk.common,
&pll_hsic_clk.common,
&pll_de_clk.common,
&pll_ddr1_clk.common,
&cpux_clk.common,
&axi_clk.common,
&ahb1_clk.common,
&apb1_clk.common,
&apb2_clk.common,
&ahb2_clk.common,
&bus_mipi_dsi_clk.common,
&bus_ce_clk.common,
&bus_dma_clk.common,
&bus_mmc0_clk.common,
&bus_mmc1_clk.common,
&bus_mmc2_clk.common,
&bus_nand_clk.common,
&bus_dram_clk.common,
&bus_emac_clk.common,
&bus_ts_clk.common,
&bus_hstimer_clk.common,
&bus_spi0_clk.common,
&bus_spi1_clk.common,
&bus_otg_clk.common,
&bus_ehci0_clk.common,
&bus_ehci1_clk.common,
&bus_ohci0_clk.common,
&bus_ohci1_clk.common,
&bus_ve_clk.common,
&bus_tcon0_clk.common,
&bus_tcon1_clk.common,
&bus_deinterlace_clk.common,
&bus_csi_clk.common,
&bus_hdmi_clk.common,
&bus_de_clk.common,
&bus_gpu_clk.common,
&bus_msgbox_clk.common,
&bus_spinlock_clk.common,
&bus_codec_clk.common,
&bus_spdif_clk.common,
&bus_pio_clk.common,
&bus_ths_clk.common,
&bus_i2s0_clk.common,
&bus_i2s1_clk.common,
&bus_i2s2_clk.common,
&bus_i2c0_clk.common,
&bus_i2c1_clk.common,
&bus_i2c2_clk.common,
&bus_scr_clk.common,
&bus_uart0_clk.common,
&bus_uart1_clk.common,
&bus_uart2_clk.common,
&bus_uart3_clk.common,
&bus_uart4_clk.common,
&bus_dbg_clk.common,
&ths_clk.common,
&nand_clk.common,
&mmc0_clk.common,
&mmc1_clk.common,
&mmc2_clk.common,
&ts_clk.common,
&ce_clk.common,
&spi0_clk.common,
&spi1_clk.common,
&i2s0_clk.common,
&i2s1_clk.common,
&i2s2_clk.common,
&spdif_clk.common,
&usb_phy0_clk.common,
&usb_phy1_clk.common,
&usb_hsic_clk.common,
&usb_hsic_12m_clk.common,
&usb_ohci0_clk.common,
&usb_ohci1_clk.common,
&dram_clk.common,
&dram_ve_clk.common,
&dram_csi_clk.common,
&dram_deinterlace_clk.common,
&dram_ts_clk.common,
&de_clk.common,
&tcon0_clk.common,
&tcon1_clk.common,
&deinterlace_clk.common,
&csi_misc_clk.common,
&csi_sclk_clk.common,
&csi_mclk_clk.common,
&ve_clk.common,
&ac_dig_clk.common,
&ac_dig_4x_clk.common,
&avs_clk.common,
&hdmi_clk.common,
&hdmi_ddc_clk.common,
&mbus_clk.common,
&dsi_dphy_clk.common,
&gpu_clk.common,
};
static struct clk_hw_onecell_data sun50i_a64_hw_clks = {
.hws = {
[CLK_OSC_12M] = &osc12M_clk.hw,
[CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
[CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
[CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
[CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
[CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
[CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
[CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
[CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
[CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
[CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
[CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
[CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
[CLK_PLL_DE] = &pll_de_clk.common.hw,
[CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
[CLK_CPUX] = &cpux_clk.common.hw,
[CLK_AXI] = &axi_clk.common.hw,
[CLK_AHB1] = &ahb1_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_APB2] = &apb2_clk.common.hw,
[CLK_AHB2] = &ahb2_clk.common.hw,
[CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
[CLK_BUS_CE] = &bus_ce_clk.common.hw,
[CLK_BUS_DMA] = &bus_dma_clk.common.hw,
[CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
[CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
[CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
[CLK_BUS_NAND] = &bus_nand_clk.common.hw,
[CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
[CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
[CLK_BUS_TS] = &bus_ts_clk.common.hw,
[CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
[CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
[CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
[CLK_BUS_OTG] = &bus_otg_clk.common.hw,
[CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
[CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
[CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
[CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
[CLK_BUS_VE] = &bus_ve_clk.common.hw,
[CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
[CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
[CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
[CLK_BUS_CSI] = &bus_csi_clk.common.hw,
[CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
[CLK_BUS_DE] = &bus_de_clk.common.hw,
[CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
[CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
[CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
[CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
[CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
[CLK_BUS_PIO] = &bus_pio_clk.common.hw,
[CLK_BUS_THS] = &bus_ths_clk.common.hw,
[CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
[CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
[CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
[CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
[CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
[CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
[CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
[CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
[CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
[CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
[CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
[CLK_BUS_SCR] = &bus_scr_clk.common.hw,
[CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
[CLK_THS] = &ths_clk.common.hw,
[CLK_NAND] = &nand_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_TS] = &ts_clk.common.hw,
[CLK_CE] = &ce_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_I2S0] = &i2s0_clk.common.hw,
[CLK_I2S1] = &i2s1_clk.common.hw,
[CLK_I2S2] = &i2s2_clk.common.hw,
[CLK_SPDIF] = &spdif_clk.common.hw,
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
[CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
[CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
[CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw,
[CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
[CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
[CLK_DRAM] = &dram_clk.common.hw,
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
[CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
[CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
[CLK_DRAM_TS] = &dram_ts_clk.common.hw,
[CLK_DE] = &de_clk.common.hw,
[CLK_TCON0] = &tcon0_clk.common.hw,
[CLK_TCON1] = &tcon1_clk.common.hw,
[CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
[CLK_CSI_MISC] = &csi_misc_clk.common.hw,
[CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
[CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_AC_DIG] = &ac_dig_clk.common.hw,
[CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_HDMI] = &hdmi_clk.common.hw,
[CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
[CLK_MBUS] = &mbus_clk.common.hw,
[CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
[CLK_GPU] = &gpu_clk.common.hw,
},
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun50i_a64_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_HSIC] = { 0x0cc, BIT(2) },
[RST_DRAM] = { 0x0f4, BIT(31) },
[RST_MBUS] = { 0x0fc, BIT(31) },
[RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
[RST_BUS_CE] = { 0x2c0, BIT(5) },
[RST_BUS_DMA] = { 0x2c0, BIT(6) },
[RST_BUS_MMC0] = { 0x2c0, BIT(8) },
[RST_BUS_MMC1] = { 0x2c0, BIT(9) },
[RST_BUS_MMC2] = { 0x2c0, BIT(10) },
[RST_BUS_NAND] = { 0x2c0, BIT(13) },
[RST_BUS_DRAM] = { 0x2c0, BIT(14) },
[RST_BUS_EMAC] = { 0x2c0, BIT(17) },
[RST_BUS_TS] = { 0x2c0, BIT(18) },
[RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
[RST_BUS_SPI0] = { 0x2c0, BIT(20) },
[RST_BUS_SPI1] = { 0x2c0, BIT(21) },
[RST_BUS_OTG] = { 0x2c0, BIT(23) },
[RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
[RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
[RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
[RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
[RST_BUS_VE] = { 0x2c4, BIT(0) },
[RST_BUS_TCON0] = { 0x2c4, BIT(3) },
[RST_BUS_TCON1] = { 0x2c4, BIT(4) },
[RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
[RST_BUS_CSI] = { 0x2c4, BIT(8) },
[RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
[RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
[RST_BUS_DE] = { 0x2c4, BIT(12) },
[RST_BUS_GPU] = { 0x2c4, BIT(20) },
[RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
[RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
[RST_BUS_DBG] = { 0x2c4, BIT(31) },
[RST_BUS_LVDS] = { 0x2c8, BIT(0) },
[RST_BUS_CODEC] = { 0x2d0, BIT(0) },
[RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
[RST_BUS_THS] = { 0x2d0, BIT(8) },
[RST_BUS_I2S0] = { 0x2d0, BIT(12) },
[RST_BUS_I2S1] = { 0x2d0, BIT(13) },
[RST_BUS_I2S2] = { 0x2d0, BIT(14) },
[RST_BUS_I2C0] = { 0x2d8, BIT(0) },
[RST_BUS_I2C1] = { 0x2d8, BIT(1) },
[RST_BUS_I2C2] = { 0x2d8, BIT(2) },
[RST_BUS_SCR] = { 0x2d8, BIT(5) },
[RST_BUS_UART0] = { 0x2d8, BIT(16) },
[RST_BUS_UART1] = { 0x2d8, BIT(17) },
[RST_BUS_UART2] = { 0x2d8, BIT(18) },
[RST_BUS_UART3] = { 0x2d8, BIT(19) },
[RST_BUS_UART4] = { 0x2d8, BIT(20) },
};
static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = {
.ccu_clks = sun50i_a64_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun50i_a64_ccu_clks),
.hw_clks = &sun50i_a64_hw_clks,
.resets = sun50i_a64_ccu_resets,
.num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets),
};
static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {
.common = &pll_cpux_clk.common,
/* copy from pll_cpux_clk */
.enable = BIT(31),
.lock = BIT(28),
};
static struct ccu_mux_nb sun50i_a64_cpu_nb = {
.common = &cpux_clk.common,
.cm = &cpux_clk.mux,
.delay_us = 1, /* > 8 clock cycles at 24 MHz */
.bypass_index = 1, /* index of 24 MHz oscillator */
};
static int sun50i_a64_ccu_probe(struct platform_device *pdev)
{
void __iomem *reg;
u32 val;
int ret;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
/* Force the PLL-Audio-1x divider to 1 */
val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);
val &= ~GENMASK(19, 16);
writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
/* Set PLL MIPI as parent for TCON0 */
val = readl(reg + SUN50I_A64_TCON0_CLK_REG);
val &= ~GENMASK(26, 24);
writel(val | (0 << 24), reg + SUN50I_A64_TCON0_CLK_REG);
ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc);
if (ret)
return ret;
/* Gate then ungate PLL CPU after any rate changes */
ccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);
/* Reparent CPU during PLL CPU rate changes */
ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
&sun50i_a64_cpu_nb);
return 0;
}
static const struct of_device_id sun50i_a64_ccu_ids[] = {
{ .compatible = "allwinner,sun50i-a64-ccu" },
{ }
};
static struct platform_driver sun50i_a64_ccu_driver = {
.probe = sun50i_a64_ccu_probe,
.driver = {
.name = "sun50i-a64-ccu",
.suppress_bind_attrs = true,
.of_match_table = sun50i_a64_ccu_ids,
},
};
module_platform_driver(sun50i_a64_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun50i-a64.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Yangtao Li <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu_nm.h"
#include "ccu-sun50i-a100-r.h"
static const char * const cpus_r_apb2_parents[] = { "dcxo24M", "osc32k",
"iosc", "pll-periph0" };
static const struct ccu_mux_var_prediv cpus_r_apb2_predivs[] = {
{ .index = 3, .shift = 0, .width = 5 },
};
static struct ccu_div r_cpus_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = {
.shift = 24,
.width = 2,
.var_predivs = cpus_r_apb2_predivs,
.n_var_predivs = ARRAY_SIZE(cpus_r_apb2_predivs),
},
.common = {
.reg = 0x000,
.features = CCU_FEATURE_VARIABLE_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("cpus",
cpus_r_apb2_parents,
&ccu_div_ops,
0),
},
};
static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &r_cpus_clk.common.hw, 1, 1, 0);
static struct ccu_div r_apb1_clk = {
.div = _SUNXI_CCU_DIV(0, 2),
.common = {
.reg = 0x00c,
.hw.init = CLK_HW_INIT("r-apb1",
"r-ahb",
&ccu_div_ops,
0),
},
};
static struct ccu_div r_apb2_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = {
.shift = 24,
.width = 2,
.var_predivs = cpus_r_apb2_predivs,
.n_var_predivs = ARRAY_SIZE(cpus_r_apb2_predivs),
},
.common = {
.reg = 0x010,
.features = CCU_FEATURE_VARIABLE_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("r-apb2",
cpus_r_apb2_parents,
&ccu_div_ops,
0),
},
};
static const struct clk_parent_data clk_parent_r_apb1[] = {
{ .hw = &r_apb1_clk.common.hw },
};
static const struct clk_parent_data clk_parent_r_apb2[] = {
{ .hw = &r_apb2_clk.common.hw },
};
static SUNXI_CCU_GATE_DATA(r_apb1_timer_clk, "r-apb1-timer", clk_parent_r_apb1,
0x11c, BIT(0), 0);
static SUNXI_CCU_GATE_DATA(r_apb1_twd_clk, "r-apb1-twd", clk_parent_r_apb1,
0x12c, BIT(0), 0);
static const char * const r_apb1_pwm_clk_parents[] = { "dcxo24M", "osc32k",
"iosc" };
static SUNXI_CCU_MUX(r_apb1_pwm_clk, "r-apb1-pwm", r_apb1_pwm_clk_parents,
0x130, 24, 2, 0);
static SUNXI_CCU_GATE_DATA(r_apb1_bus_pwm_clk, "r-apb1-bus-pwm",
clk_parent_r_apb1, 0x13c, BIT(0), 0);
static SUNXI_CCU_GATE_DATA(r_apb1_ppu_clk, "r-apb1-ppu", clk_parent_r_apb1,
0x17c, BIT(0), 0);
static SUNXI_CCU_GATE_DATA(r_apb2_uart_clk, "r-apb2-uart", clk_parent_r_apb2,
0x18c, BIT(0), 0);
static SUNXI_CCU_GATE_DATA(r_apb2_i2c0_clk, "r-apb2-i2c0", clk_parent_r_apb2,
0x19c, BIT(0), 0);
static SUNXI_CCU_GATE_DATA(r_apb2_i2c1_clk, "r-apb2-i2c1", clk_parent_r_apb2,
0x19c, BIT(1), 0);
static const char * const r_apb1_ir_rx_parents[] = { "osc32k", "dcxo24M" };
static SUNXI_CCU_MP_WITH_MUX_GATE(r_apb1_ir_rx_clk, "r-apb1-ir-rx",
r_apb1_ir_rx_parents, 0x1c0,
0, 5, /* M */
8, 2, /* P */
24, 1, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE_DATA(r_apb1_bus_ir_rx_clk, "r-apb1-bus-ir-rx",
clk_parent_r_apb1, 0x1cc, BIT(0), 0);
static SUNXI_CCU_GATE(r_ahb_bus_rtc_clk, "r-ahb-rtc", "r-ahb",
0x20c, BIT(0), 0);
static struct ccu_common *sun50i_a100_r_ccu_clks[] = {
&r_cpus_clk.common,
&r_apb1_clk.common,
&r_apb2_clk.common,
&r_apb1_timer_clk.common,
&r_apb1_twd_clk.common,
&r_apb1_pwm_clk.common,
&r_apb1_bus_pwm_clk.common,
&r_apb1_ppu_clk.common,
&r_apb2_uart_clk.common,
&r_apb2_i2c0_clk.common,
&r_apb2_i2c1_clk.common,
&r_apb1_ir_rx_clk.common,
&r_apb1_bus_ir_rx_clk.common,
&r_ahb_bus_rtc_clk.common,
};
static struct clk_hw_onecell_data sun50i_a100_r_hw_clks = {
.hws = {
[CLK_R_CPUS] = &r_cpus_clk.common.hw,
[CLK_R_AHB] = &r_ahb_clk.hw,
[CLK_R_APB1] = &r_apb1_clk.common.hw,
[CLK_R_APB2] = &r_apb2_clk.common.hw,
[CLK_R_APB1_TIMER] = &r_apb1_timer_clk.common.hw,
[CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw,
[CLK_R_APB1_PWM] = &r_apb1_pwm_clk.common.hw,
[CLK_R_APB1_BUS_PWM] = &r_apb1_bus_pwm_clk.common.hw,
[CLK_R_APB1_PPU] = &r_apb1_ppu_clk.common.hw,
[CLK_R_APB2_UART] = &r_apb2_uart_clk.common.hw,
[CLK_R_APB2_I2C0] = &r_apb2_i2c0_clk.common.hw,
[CLK_R_APB2_I2C1] = &r_apb2_i2c1_clk.common.hw,
[CLK_R_APB1_IR] = &r_apb1_ir_rx_clk.common.hw,
[CLK_R_APB1_BUS_IR] = &r_apb1_bus_ir_rx_clk.common.hw,
[CLK_R_AHB_BUS_RTC] = &r_ahb_bus_rtc_clk.common.hw,
},
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun50i_a100_r_ccu_resets[] = {
[RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
[RST_R_APB1_BUS_PWM] = { 0x13c, BIT(16) },
[RST_R_APB1_PPU] = { 0x17c, BIT(16) },
[RST_R_APB2_UART] = { 0x18c, BIT(16) },
[RST_R_APB2_I2C0] = { 0x19c, BIT(16) },
[RST_R_APB2_I2C1] = { 0x19c, BIT(17) },
[RST_R_APB1_BUS_IR] = { 0x1cc, BIT(16) },
[RST_R_AHB_BUS_RTC] = { 0x20c, BIT(16) },
};
static const struct sunxi_ccu_desc sun50i_a100_r_ccu_desc = {
.ccu_clks = sun50i_a100_r_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun50i_a100_r_ccu_clks),
.hw_clks = &sun50i_a100_r_hw_clks,
.resets = sun50i_a100_r_ccu_resets,
.num_resets = ARRAY_SIZE(sun50i_a100_r_ccu_resets),
};
static int sun50i_a100_r_ccu_probe(struct platform_device *pdev)
{
void __iomem *reg;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a100_r_ccu_desc);
}
static const struct of_device_id sun50i_a100_r_ccu_ids[] = {
{ .compatible = "allwinner,sun50i-a100-r-ccu" },
{ }
};
static struct platform_driver sun50i_a100_r_ccu_driver = {
.probe = sun50i_a100_r_ccu_probe,
.driver = {
.name = "sun50i-a100-r-ccu",
.suppress_bind_attrs = true,
.of_match_table = sun50i_a100_r_ccu_ids,
},
};
module_platform_driver(sun50i_a100_r_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016 Maxime Ripard. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu_mult.h"
#include "ccu_nk.h"
#include "ccu_nkm.h"
#include "ccu_nkmp.h"
#include "ccu_nm.h"
#include "ccu_phase.h"
#include "ccu-sun8i-a23-a33.h"
static struct ccu_nkmp pll_cpux_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT(8, 5),
.k = _SUNXI_CCU_MULT(4, 2),
.m = _SUNXI_CCU_DIV(0, 2),
.p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
.common = {
.reg = 0x000,
.hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
&ccu_nkmp_ops,
0),
},
};
/*
* The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
* the base (2x, 4x and 8x), and one variable divider (the one true
* pll audio).
*
* With sigma-delta modulation for fractional-N on the audio PLL,
* we have to use specific dividers. This means the variable divider
* can no longer be used, as the audio codec requests the exact clock
* rates we support through this mechanism. So we now hard code the
* variable divider to 1. This means the clock rates will no longer
* match the clock names.
*/
#define SUN8I_A33_PLL_AUDIO_REG 0x008
static struct ccu_sdm_setting pll_audio_sdm_table[] = {
{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
};
static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
"osc24M", 0x008,
8, 7, /* N */
0, 5, /* M */
pll_audio_sdm_table, BIT(24),
0x284, BIT(31),
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
"osc24M", 0x010,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
"osc24M", 0x018,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
"osc24M", 0x020,
8, 5, /* N */
4, 2, /* K */
0, 2, /* M */
BIT(31), /* gate */
BIT(28), /* lock */
0);
static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
"osc24M", 0x028,
8, 5, /* N */
4, 2, /* K */
BIT(31), /* gate */
BIT(28), /* lock */
2, /* post-div */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
"osc24M", 0x038,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
/*
* The MIPI PLL has 2 modes: "MIPI" and "HDMI".
*
* The MIPI mode is a standard NKM-style clock. The HDMI mode is an
* integer / fractional clock with switchable multipliers and dividers.
* This is not supported here. We hardcode the PLL to MIPI mode.
*/
#define SUN8I_A33_PLL_MIPI_REG 0x040
static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
"pll-video", 0x040,
8, 4, /* N */
4, 2, /* K */
0, 4, /* M */
BIT(31) | BIT(23) | BIT(22), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
"osc24M", 0x044,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
"osc24M", 0x048,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static struct ccu_mult pll_ddr1_clk = {
.enable = BIT(31),
.lock = BIT(28),
.mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 6, 0, 12, 0),
.common = {
.reg = 0x04c,
.hw.init = CLK_HW_INIT("pll-ddr1", "osc24M",
&ccu_mult_ops,
CLK_SET_RATE_UNGATE),
},
};
static const char * const cpux_parents[] = { "osc32k", "osc24M",
"pll-cpux" , "pll-cpux" };
static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
static const char * const ahb1_parents[] = { "osc32k", "osc24M",
"axi" , "pll-periph" };
static const struct ccu_mux_var_prediv ahb1_predivs[] = {
{ .index = 3, .shift = 6, .width = 2 },
};
static struct ccu_div ahb1_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = {
.shift = 12,
.width = 2,
.var_predivs = ahb1_predivs,
.n_var_predivs = ARRAY_SIZE(ahb1_predivs),
},
.common = {
.reg = 0x054,
.features = CCU_FEATURE_VARIABLE_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("ahb1",
ahb1_parents,
&ccu_div_ops,
0),
},
};
static struct clk_div_table apb1_div_table[] = {
{ .val = 0, .div = 2 },
{ .val = 1, .div = 2 },
{ .val = 2, .div = 4 },
{ .val = 3, .div = 8 },
{ /* Sentinel */ },
};
static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
0x054, 8, 2, apb1_div_table, 0);
static const char * const apb2_parents[] = { "osc32k", "osc24M",
"pll-periph" , "pll-periph" };
static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
0, 5, /* M */
16, 2, /* P */
24, 2, /* mux */
0);
static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
0x060, BIT(1), 0);
static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1",
0x060, BIT(5), 0);
static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
0x060, BIT(6), 0);
static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
0x060, BIT(8), 0);
static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
0x060, BIT(9), 0);
static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
0x060, BIT(10), 0);
static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
0x060, BIT(13), 0);
static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
0x060, BIT(14), 0);
static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
0x060, BIT(19), 0);
static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
0x060, BIT(20), 0);
static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
0x060, BIT(21), 0);
static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
0x060, BIT(24), 0);
static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1",
0x060, BIT(26), 0);
static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1",
0x060, BIT(29), 0);
static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
0x064, BIT(0), 0);
static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb1",
0x064, BIT(4), 0);
static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
0x064, BIT(8), 0);
static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb1",
0x064, BIT(12), 0);
static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1",
0x064, BIT(14), 0);
static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
0x064, BIT(20), 0);
static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
0x064, BIT(21), 0);
static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
0x064, BIT(22), 0);
static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1",
0x064, BIT(25), 0);
static SUNXI_CCU_GATE(bus_sat_clk, "bus-sat", "ahb1",
0x064, BIT(26), 0);
static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
0x068, BIT(0), 0);
static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
0x068, BIT(5), 0);
static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
0x068, BIT(12), 0);
static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
0x068, BIT(13), 0);
static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
0x06c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
0x06c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
0x06c, BIT(2), 0);
static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
0x06c, BIT(16), 0);
static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
0x06c, BIT(17), 0);
static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
0x06c, BIT(18), 0);
static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
0x06c, BIT(19), 0);
static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
0x06c, BIT(20), 0);
static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
0x088, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
0x088, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
0x08c, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
0x08c, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
0x090, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
0x090, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
"pll-audio-2x", "pll-audio" };
static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
/* TODO: the parent for most of the USB clocks is not known */
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
0x0cc, BIT(8), 0);
static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
0x0cc, BIT(9), 0);
static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
0x0cc, BIT(10), 0);
static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M",
0x0cc, BIT(11), 0);
static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M",
0x0cc, BIT(16), 0);
static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr",
0x0f4, 0, 4, CLK_IS_CRITICAL);
static const char * const pll_ddr_parents[] = { "pll-ddr0", "pll-ddr1" };
static SUNXI_CCU_MUX(pll_ddr_clk, "pll-ddr", pll_ddr_parents,
0x0f8, 16, 1, 0);
static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
0x100, BIT(0), 0);
static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
0x100, BIT(1), 0);
static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "dram",
0x100, BIT(16), 0);
static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "dram",
0x100, BIT(24), 0);
static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "dram",
0x100, BIT(26), 0);
static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
"pll-gpu", "pll-de" };
static const u8 de_table[] = { 0, 2, 3, 5 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
de_parents, de_table,
0x104, 0, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
de_parents, de_table,
0x10c, 0, 4, 24, 3, BIT(31), 0);
static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
"pll-mipi" };
static const u8 lcd_ch0_table[] = { 0, 2, 4 };
static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
lcd_ch0_parents, lcd_ch0_table,
0x118, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
static const u8 lcd_ch1_table[] = { 0, 2 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
lcd_ch1_parents, lcd_ch1_table,
0x12c, 0, 4, 24, 2, BIT(31), 0);
static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
"pll-mipi", "pll-ve" };
static const u8 csi_sclk_table[] = { 0, 3, 4, 5 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
csi_sclk_parents, csi_sclk_table,
0x134, 16, 4, 24, 3, BIT(31), 0);
static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
"osc24M" };
static const u8 csi_mclk_table[] = { 0, 3, 5 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
csi_mclk_parents, csi_mclk_table,
0x134, 0, 5, 8, 3, BIT(15), 0);
static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
0x140, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",
0x140, BIT(30), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
0x144, BIT(31), 0);
static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
"pll-ddr0", "pll-ddr1" };
static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
static const u8 dsi_sclk_table[] = { 0, 2 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
dsi_sclk_parents, dsi_sclk_table,
0x168, 16, 4, 24, 2, BIT(31), 0);
static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
static const u8 dsi_dphy_table[] = { 0, 2 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
dsi_dphy_parents, dsi_dphy_table,
0x168, 0, 4, 8, 2, BIT(15), 0);
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc",
de_parents, de_table,
0x180, 0, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
static const char * const ats_parents[] = { "osc24M", "pll-periph" };
static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents,
0x1b0, 0, 3, 24, 2, BIT(31), 0);
static struct ccu_common *sun8i_a33_ccu_clks[] = {
&pll_cpux_clk.common,
&pll_audio_base_clk.common,
&pll_video_clk.common,
&pll_ve_clk.common,
&pll_ddr0_clk.common,
&pll_periph_clk.common,
&pll_gpu_clk.common,
&pll_mipi_clk.common,
&pll_hsic_clk.common,
&pll_de_clk.common,
&pll_ddr1_clk.common,
&pll_ddr_clk.common,
&cpux_clk.common,
&axi_clk.common,
&ahb1_clk.common,
&apb1_clk.common,
&apb2_clk.common,
&bus_mipi_dsi_clk.common,
&bus_ss_clk.common,
&bus_dma_clk.common,
&bus_mmc0_clk.common,
&bus_mmc1_clk.common,
&bus_mmc2_clk.common,
&bus_nand_clk.common,
&bus_dram_clk.common,
&bus_hstimer_clk.common,
&bus_spi0_clk.common,
&bus_spi1_clk.common,
&bus_otg_clk.common,
&bus_ehci_clk.common,
&bus_ohci_clk.common,
&bus_ve_clk.common,
&bus_lcd_clk.common,
&bus_csi_clk.common,
&bus_de_fe_clk.common,
&bus_de_be_clk.common,
&bus_gpu_clk.common,
&bus_msgbox_clk.common,
&bus_spinlock_clk.common,
&bus_drc_clk.common,
&bus_sat_clk.common,
&bus_codec_clk.common,
&bus_pio_clk.common,
&bus_i2s0_clk.common,
&bus_i2s1_clk.common,
&bus_i2c0_clk.common,
&bus_i2c1_clk.common,
&bus_i2c2_clk.common,
&bus_uart0_clk.common,
&bus_uart1_clk.common,
&bus_uart2_clk.common,
&bus_uart3_clk.common,
&bus_uart4_clk.common,
&nand_clk.common,
&mmc0_clk.common,
&mmc0_sample_clk.common,
&mmc0_output_clk.common,
&mmc1_clk.common,
&mmc1_sample_clk.common,
&mmc1_output_clk.common,
&mmc2_clk.common,
&mmc2_sample_clk.common,
&mmc2_output_clk.common,
&ss_clk.common,
&spi0_clk.common,
&spi1_clk.common,
&i2s0_clk.common,
&i2s1_clk.common,
&usb_phy0_clk.common,
&usb_phy1_clk.common,
&usb_hsic_clk.common,
&usb_hsic_12M_clk.common,
&usb_ohci_clk.common,
&dram_clk.common,
&dram_ve_clk.common,
&dram_csi_clk.common,
&dram_drc_clk.common,
&dram_de_fe_clk.common,
&dram_de_be_clk.common,
&de_be_clk.common,
&de_fe_clk.common,
&lcd_ch0_clk.common,
&lcd_ch1_clk.common,
&csi_sclk_clk.common,
&csi_mclk_clk.common,
&ve_clk.common,
&ac_dig_clk.common,
&ac_dig_4x_clk.common,
&avs_clk.common,
&mbus_clk.common,
&dsi_sclk_clk.common,
&dsi_dphy_clk.common,
&drc_clk.common,
&gpu_clk.common,
&ats_clk.common,
};
static const struct clk_hw *clk_parent_pll_audio[] = {
&pll_audio_base_clk.common.hw
};
/* We hardcode the divider to 1 for now */
static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
clk_parent_pll_audio,
1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
clk_parent_pll_audio,
2, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
clk_parent_pll_audio,
1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
clk_parent_pll_audio,
1, 2, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
&pll_periph_clk.common.hw,
1, 2, 0);
static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
&pll_video_clk.common.hw,
1, 2, 0);
static struct clk_hw_onecell_data sun8i_a33_hw_clks = {
.hws = {
[CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
[CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
[CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw,
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
[CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
[CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
[CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw,
[CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
[CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
[CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
[CLK_PLL_DE] = &pll_de_clk.common.hw,
[CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
[CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
[CLK_CPUX] = &cpux_clk.common.hw,
[CLK_AXI] = &axi_clk.common.hw,
[CLK_AHB1] = &ahb1_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_APB2] = &apb2_clk.common.hw,
[CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
[CLK_BUS_SS] = &bus_ss_clk.common.hw,
[CLK_BUS_DMA] = &bus_dma_clk.common.hw,
[CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
[CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
[CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
[CLK_BUS_NAND] = &bus_nand_clk.common.hw,
[CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
[CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
[CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
[CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
[CLK_BUS_OTG] = &bus_otg_clk.common.hw,
[CLK_BUS_EHCI] = &bus_ehci_clk.common.hw,
[CLK_BUS_OHCI] = &bus_ohci_clk.common.hw,
[CLK_BUS_VE] = &bus_ve_clk.common.hw,
[CLK_BUS_LCD] = &bus_lcd_clk.common.hw,
[CLK_BUS_CSI] = &bus_csi_clk.common.hw,
[CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw,
[CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw,
[CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
[CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
[CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
[CLK_BUS_DRC] = &bus_drc_clk.common.hw,
[CLK_BUS_SAT] = &bus_sat_clk.common.hw,
[CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
[CLK_BUS_PIO] = &bus_pio_clk.common.hw,
[CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
[CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
[CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
[CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
[CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
[CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
[CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
[CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
[CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
[CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
[CLK_NAND] = &nand_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
[CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
[CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
[CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
[CLK_SS] = &ss_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_I2S0] = &i2s0_clk.common.hw,
[CLK_I2S1] = &i2s1_clk.common.hw,
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
[CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
[CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
[CLK_USB_HSIC_12M] = &usb_hsic_12M_clk.common.hw,
[CLK_USB_OHCI] = &usb_ohci_clk.common.hw,
[CLK_DRAM] = &dram_clk.common.hw,
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
[CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
[CLK_DRAM_DRC] = &dram_drc_clk.common.hw,
[CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
[CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
[CLK_DE_BE] = &de_be_clk.common.hw,
[CLK_DE_FE] = &de_fe_clk.common.hw,
[CLK_LCD_CH0] = &lcd_ch0_clk.common.hw,
[CLK_LCD_CH1] = &lcd_ch1_clk.common.hw,
[CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
[CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_AC_DIG] = &ac_dig_clk.common.hw,
[CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_MBUS] = &mbus_clk.common.hw,
[CLK_DSI_SCLK] = &dsi_sclk_clk.common.hw,
[CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
[CLK_DRC] = &drc_clk.common.hw,
[CLK_GPU] = &gpu_clk.common.hw,
[CLK_ATS] = &ats_clk.common.hw,
},
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun8i_a33_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_HSIC] = { 0x0cc, BIT(2) },
[RST_MBUS] = { 0x0fc, BIT(31) },
[RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
[RST_BUS_SS] = { 0x2c0, BIT(5) },
[RST_BUS_DMA] = { 0x2c0, BIT(6) },
[RST_BUS_MMC0] = { 0x2c0, BIT(8) },
[RST_BUS_MMC1] = { 0x2c0, BIT(9) },
[RST_BUS_MMC2] = { 0x2c0, BIT(10) },
[RST_BUS_NAND] = { 0x2c0, BIT(13) },
[RST_BUS_DRAM] = { 0x2c0, BIT(14) },
[RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
[RST_BUS_SPI0] = { 0x2c0, BIT(20) },
[RST_BUS_SPI1] = { 0x2c0, BIT(21) },
[RST_BUS_OTG] = { 0x2c0, BIT(24) },
[RST_BUS_EHCI] = { 0x2c0, BIT(26) },
[RST_BUS_OHCI] = { 0x2c0, BIT(29) },
[RST_BUS_VE] = { 0x2c4, BIT(0) },
[RST_BUS_LCD] = { 0x2c4, BIT(4) },
[RST_BUS_CSI] = { 0x2c4, BIT(8) },
[RST_BUS_DE_BE] = { 0x2c4, BIT(12) },
[RST_BUS_DE_FE] = { 0x2c4, BIT(14) },
[RST_BUS_GPU] = { 0x2c4, BIT(20) },
[RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
[RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
[RST_BUS_DRC] = { 0x2c4, BIT(25) },
[RST_BUS_SAT] = { 0x2c4, BIT(26) },
[RST_BUS_LVDS] = { 0x2c8, BIT(0) },
[RST_BUS_CODEC] = { 0x2d0, BIT(0) },
[RST_BUS_I2S0] = { 0x2d0, BIT(12) },
[RST_BUS_I2S1] = { 0x2d0, BIT(13) },
[RST_BUS_I2C0] = { 0x2d8, BIT(0) },
[RST_BUS_I2C1] = { 0x2d8, BIT(1) },
[RST_BUS_I2C2] = { 0x2d8, BIT(2) },
[RST_BUS_UART0] = { 0x2d8, BIT(16) },
[RST_BUS_UART1] = { 0x2d8, BIT(17) },
[RST_BUS_UART2] = { 0x2d8, BIT(18) },
[RST_BUS_UART3] = { 0x2d8, BIT(19) },
[RST_BUS_UART4] = { 0x2d8, BIT(20) },
};
static const struct sunxi_ccu_desc sun8i_a33_ccu_desc = {
.ccu_clks = sun8i_a33_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_a33_ccu_clks),
.hw_clks = &sun8i_a33_hw_clks,
.resets = sun8i_a33_ccu_resets,
.num_resets = ARRAY_SIZE(sun8i_a33_ccu_resets),
};
static struct ccu_pll_nb sun8i_a33_pll_cpu_nb = {
.common = &pll_cpux_clk.common,
/* copy from pll_cpux_clk */
.enable = BIT(31),
.lock = BIT(28),
};
static struct ccu_mux_nb sun8i_a33_cpu_nb = {
.common = &cpux_clk.common,
.cm = &cpux_clk.mux,
.delay_us = 1, /* > 8 clock cycles at 24 MHz */
.bypass_index = 1, /* index of 24 MHz oscillator */
};
static int sun8i_a33_ccu_probe(struct platform_device *pdev)
{
void __iomem *reg;
int ret;
u32 val;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
/* Force the PLL-Audio-1x divider to 1 */
val = readl(reg + SUN8I_A33_PLL_AUDIO_REG);
val &= ~GENMASK(19, 16);
writel(val | (0 << 16), reg + SUN8I_A33_PLL_AUDIO_REG);
/* Force PLL-MIPI to MIPI mode */
val = readl(reg + SUN8I_A33_PLL_MIPI_REG);
val &= ~BIT(16);
writel(val, reg + SUN8I_A33_PLL_MIPI_REG);
ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_a33_ccu_desc);
if (ret)
return ret;
/* Gate then ungate PLL CPU after any rate changes */
ccu_pll_notifier_register(&sun8i_a33_pll_cpu_nb);
/* Reparent CPU during PLL CPU rate changes */
ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
&sun8i_a33_cpu_nb);
return 0;
}
static const struct of_device_id sun8i_a33_ccu_ids[] = {
{ .compatible = "allwinner,sun8i-a33-ccu" },
{ }
};
static struct platform_driver sun8i_a33_ccu_driver = {
.probe = sun8i_a33_ccu_probe,
.driver = {
.name = "sun8i-a33-ccu",
.suppress_bind_attrs = true,
.of_match_table = sun8i_a33_ccu_ids,
},
};
module_platform_driver(sun8i_a33_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun8i-a33.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Maxime Ripard
* Maxime Ripard <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include "ccu_gate.h"
#include "ccu_div.h"
static unsigned long ccu_div_round_rate(struct ccu_mux_internal *mux,
struct clk_hw *parent,
unsigned long *parent_rate,
unsigned long rate,
void *data)
{
struct ccu_div *cd = data;
if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate *= cd->fixed_post_div;
rate = divider_round_rate_parent(&cd->common.hw, parent,
rate, parent_rate,
cd->div.table, cd->div.width,
cd->div.flags);
if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= cd->fixed_post_div;
return rate;
}
static void ccu_div_disable(struct clk_hw *hw)
{
struct ccu_div *cd = hw_to_ccu_div(hw);
return ccu_gate_helper_disable(&cd->common, cd->enable);
}
static int ccu_div_enable(struct clk_hw *hw)
{
struct ccu_div *cd = hw_to_ccu_div(hw);
return ccu_gate_helper_enable(&cd->common, cd->enable);
}
static int ccu_div_is_enabled(struct clk_hw *hw)
{
struct ccu_div *cd = hw_to_ccu_div(hw);
return ccu_gate_helper_is_enabled(&cd->common, cd->enable);
}
static unsigned long ccu_div_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct ccu_div *cd = hw_to_ccu_div(hw);
unsigned long val;
u32 reg;
reg = readl(cd->common.base + cd->common.reg);
val = reg >> cd->div.shift;
val &= (1 << cd->div.width) - 1;
parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1,
parent_rate);
val = divider_recalc_rate(hw, parent_rate, val, cd->div.table,
cd->div.flags, cd->div.width);
if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
val /= cd->fixed_post_div;
return val;
}
static int ccu_div_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct ccu_div *cd = hw_to_ccu_div(hw);
return ccu_mux_helper_determine_rate(&cd->common, &cd->mux,
req, ccu_div_round_rate, cd);
}
static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct ccu_div *cd = hw_to_ccu_div(hw);
unsigned long flags;
unsigned long val;
u32 reg;
parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1,
parent_rate);
if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate *= cd->fixed_post_div;
val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width,
cd->div.flags);
spin_lock_irqsave(cd->common.lock, flags);
reg = readl(cd->common.base + cd->common.reg);
reg &= ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift);
writel(reg | (val << cd->div.shift),
cd->common.base + cd->common.reg);
spin_unlock_irqrestore(cd->common.lock, flags);
return 0;
}
static u8 ccu_div_get_parent(struct clk_hw *hw)
{
struct ccu_div *cd = hw_to_ccu_div(hw);
return ccu_mux_helper_get_parent(&cd->common, &cd->mux);
}
static int ccu_div_set_parent(struct clk_hw *hw, u8 index)
{
struct ccu_div *cd = hw_to_ccu_div(hw);
return ccu_mux_helper_set_parent(&cd->common, &cd->mux, index);
}
const struct clk_ops ccu_div_ops = {
.disable = ccu_div_disable,
.enable = ccu_div_enable,
.is_enabled = ccu_div_is_enabled,
.get_parent = ccu_div_get_parent,
.set_parent = ccu_div_set_parent,
.determine_rate = ccu_div_determine_rate,
.recalc_rate = ccu_div_recalc_rate,
.set_rate = ccu_div_set_rate,
};
EXPORT_SYMBOL_NS_GPL(ccu_div_ops, SUNXI_CCU);
| linux-master | drivers/clk/sunxi-ng/ccu_div.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2016 Icenowy Zheng <[email protected]>
*
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu_mult.h"
#include "ccu_nk.h"
#include "ccu_nkm.h"
#include "ccu_nkmp.h"
#include "ccu_nm.h"
#include "ccu_phase.h"
#include "ccu-suniv-f1c100s.h"
static struct ccu_nkmp pll_cpu_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT(8, 5),
.k = _SUNXI_CCU_MULT(4, 2),
.m = _SUNXI_CCU_DIV(0, 2),
/* MAX is guessed by the BSP table */
.p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
.common = {
.reg = 0x000,
.hw.init = CLK_HW_INIT("pll-cpu", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
/*
* The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
* the base (2x, 4x and 8x), and one variable divider (the one true
* pll audio).
*
* We don't have any need for the variable divider for now, so we just
* hardcode it to match with the clock names
*/
#define SUNIV_PLL_AUDIO_REG 0x008
static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
"osc24M", 0x008,
8, 7, /* N */
0, 5, /* M */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
"osc24M", 0x010,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
"osc24M", 0x018,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr",
"osc24M", 0x020,
8, 5, /* N */
4, 2, /* K */
0, 2, /* M */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_IS_CRITICAL);
static struct ccu_nk pll_periph_clk = {
.enable = BIT(31),
.lock = BIT(28),
.k = _SUNXI_CCU_MULT(4, 2),
.n = _SUNXI_CCU_MULT(8, 5),
.common = {
.reg = 0x028,
.hw.init = CLK_HW_INIT("pll-periph", "osc24M",
&ccu_nk_ops, 0),
},
};
static const char * const cpu_parents[] = { "osc32k", "osc24M",
"pll-cpu", "pll-cpu" };
static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
static const char * const ahb_parents[] = { "osc32k", "osc24M",
"cpu", "pll-periph" };
static const struct ccu_mux_var_prediv ahb_predivs[] = {
{ .index = 3, .shift = 6, .width = 2 },
};
static struct ccu_div ahb_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = {
.shift = 12,
.width = 2,
.var_predivs = ahb_predivs,
.n_var_predivs = ARRAY_SIZE(ahb_predivs),
},
.common = {
.reg = 0x054,
.features = CCU_FEATURE_VARIABLE_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("ahb",
ahb_parents,
&ccu_div_ops,
0),
},
};
static struct clk_div_table apb_div_table[] = {
{ .val = 0, .div = 2 },
{ .val = 1, .div = 2 },
{ .val = 2, .div = 4 },
{ .val = 3, .div = 8 },
{ /* Sentinel */ },
};
static SUNXI_CCU_DIV_TABLE(apb_clk, "apb", "ahb",
0x054, 8, 2, apb_div_table, 0);
static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb",
0x060, BIT(6), 0);
static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb",
0x060, BIT(8), 0);
static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb",
0x060, BIT(9), 0);
static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb",
0x060, BIT(14), 0);
static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb",
0x060, BIT(20), 0);
static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb",
0x060, BIT(21), 0);
static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb",
0x060, BIT(24), 0);
static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb",
0x064, BIT(0), 0);
static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb",
0x064, BIT(4), 0);
static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb",
0x064, BIT(5), 0);
static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb",
0x064, BIT(8), 0);
static SUNXI_CCU_GATE(bus_tvd_clk, "bus-tvd", "ahb",
0x064, BIT(9), 0);
static SUNXI_CCU_GATE(bus_tve_clk, "bus-tve", "ahb",
0x064, BIT(10), 0);
static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb",
0x064, BIT(12), 0);
static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb",
0x064, BIT(14), 0);
static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb",
0x068, BIT(0), 0);
static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb",
0x068, BIT(1), 0);
static SUNXI_CCU_GATE(bus_ir_clk, "bus-ir", "apb",
0x068, BIT(2), 0);
static SUNXI_CCU_GATE(bus_rsb_clk, "bus-rsb", "apb",
0x068, BIT(3), 0);
static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb",
0x068, BIT(12), 0);
static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb",
0x068, BIT(16), 0);
static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb",
0x068, BIT(17), 0);
static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb",
0x068, BIT(18), 0);
static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb",
0x068, BIT(19), 0);
static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb",
0x068, BIT(20), 0);
static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb",
0x068, BIT(21), 0);
static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb",
0x068, BIT(22), 0);
static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
0x088, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
0x088, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
0x08c, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
0x08c, 8, 3, 0);
static const char * const i2s_spdif_parents[] = { "pll-audio-8x",
"pll-audio-4x",
"pll-audio-2x",
"pll-audio" };
static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_spdif_parents,
0x0b0, 16, 2, BIT(31), 0);
static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents,
0x0b4, 16, 2, BIT(31), 0);
static const char * const ir_parents[] = { "osc32k", "osc24M" };
static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
ir_parents, 0x0b8,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
0x0cc, BIT(1), 0);
static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
0x100, BIT(0), 0);
static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr",
0x100, BIT(1), 0);
static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace",
"pll-ddr", 0x100, BIT(2), 0);
static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "pll-ddr",
0x100, BIT(3), 0);
static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr",
0x100, BIT(24), 0);
static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr",
0x100, BIT(26), 0);
static const char * const de_parents[] = { "pll-video", "pll-periph" };
static const u8 de_table[] = { 0, 2, };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
de_parents, de_table,
0x104, 0, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
de_parents, de_table,
0x10c, 0, 4, 24, 3, BIT(31), 0);
static const char * const tcon_parents[] = { "pll-video", "pll-video-2x" };
static const u8 tcon_table[] = { 0, 2, };
static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon_clk, "tcon",
tcon_parents, tcon_table,
0x118, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
static const char * const deinterlace_parents[] = { "pll-video",
"pll-video-2x" };
static const u8 deinterlace_table[] = { 0, 2, };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(deinterlace_clk, "deinterlace",
deinterlace_parents, deinterlace_table,
0x11c, 0, 4, 24, 3, BIT(31), 0);
static const char * const tve_clk2_parents[] = { "pll-video",
"pll-video-2x" };
static const u8 tve_clk2_table[] = { 0, 2, };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(tve_clk2_clk, "tve-clk2",
tve_clk2_parents, tve_clk2_table,
0x120, 0, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_M_WITH_GATE(tve_clk1_clk, "tve-clk1", "tve-clk2",
0x120, 8, 1, BIT(15), 0);
static const char * const tvd_parents[] = { "pll-video", "osc24M",
"pll-video-2x" };
static SUNXI_CCU_M_WITH_MUX_GATE(tvd_clk, "tvd", tvd_parents,
0x124, 0, 4, 24, 3, BIT(31), 0);
static const char * const csi_parents[] = { "pll-video", "osc24M" };
static const u8 csi_table[] = { 0, 5, };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi", csi_parents, csi_table,
0x120, 0, 4, 8, 3, BIT(15), 0);
/*
* TODO: BSP says the parent is pll-audio, however common sense and experience
* told us it should be pll-ve. pll-ve is totally not used in BSP code.
*/
static SUNXI_CCU_GATE(ve_clk, "ve", "pll-audio", 0x13c, BIT(31), 0);
static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio", 0x140, BIT(31), 0);
static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0);
static struct ccu_common *suniv_ccu_clks[] = {
&pll_cpu_clk.common,
&pll_audio_base_clk.common,
&pll_video_clk.common,
&pll_ve_clk.common,
&pll_ddr0_clk.common,
&pll_periph_clk.common,
&cpu_clk.common,
&ahb_clk.common,
&apb_clk.common,
&bus_dma_clk.common,
&bus_mmc0_clk.common,
&bus_mmc1_clk.common,
&bus_dram_clk.common,
&bus_spi0_clk.common,
&bus_spi1_clk.common,
&bus_otg_clk.common,
&bus_ve_clk.common,
&bus_lcd_clk.common,
&bus_deinterlace_clk.common,
&bus_csi_clk.common,
&bus_tve_clk.common,
&bus_tvd_clk.common,
&bus_de_be_clk.common,
&bus_de_fe_clk.common,
&bus_codec_clk.common,
&bus_spdif_clk.common,
&bus_ir_clk.common,
&bus_rsb_clk.common,
&bus_i2s0_clk.common,
&bus_i2c0_clk.common,
&bus_i2c1_clk.common,
&bus_i2c2_clk.common,
&bus_pio_clk.common,
&bus_uart0_clk.common,
&bus_uart1_clk.common,
&bus_uart2_clk.common,
&mmc0_clk.common,
&mmc0_sample_clk.common,
&mmc0_output_clk.common,
&mmc1_clk.common,
&mmc1_sample_clk.common,
&mmc1_output_clk.common,
&i2s_clk.common,
&spdif_clk.common,
&ir_clk.common,
&usb_phy0_clk.common,
&dram_ve_clk.common,
&dram_csi_clk.common,
&dram_deinterlace_clk.common,
&dram_tvd_clk.common,
&dram_de_fe_clk.common,
&dram_de_be_clk.common,
&de_be_clk.common,
&de_fe_clk.common,
&tcon_clk.common,
&deinterlace_clk.common,
&tve_clk2_clk.common,
&tve_clk1_clk.common,
&tvd_clk.common,
&csi_clk.common,
&ve_clk.common,
&codec_clk.common,
&avs_clk.common,
};
static const struct clk_hw *clk_parent_pll_audio[] = {
&pll_audio_base_clk.common.hw
};
static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
clk_parent_pll_audio,
4, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
clk_parent_pll_audio,
2, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
clk_parent_pll_audio,
1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
clk_parent_pll_audio,
1, 2, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
&pll_video_clk.common.hw,
1, 2, 0);
static struct clk_hw_onecell_data suniv_hw_clks = {
.hws = {
[CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
[CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
[CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw,
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
[CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
[CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
[CLK_CPU] = &cpu_clk.common.hw,
[CLK_AHB] = &ahb_clk.common.hw,
[CLK_APB] = &apb_clk.common.hw,
[CLK_BUS_DMA] = &bus_dma_clk.common.hw,
[CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
[CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
[CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
[CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
[CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
[CLK_BUS_OTG] = &bus_otg_clk.common.hw,
[CLK_BUS_VE] = &bus_ve_clk.common.hw,
[CLK_BUS_LCD] = &bus_lcd_clk.common.hw,
[CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
[CLK_BUS_CSI] = &bus_csi_clk.common.hw,
[CLK_BUS_TVD] = &bus_tvd_clk.common.hw,
[CLK_BUS_TVE] = &bus_tve_clk.common.hw,
[CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw,
[CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw,
[CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
[CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
[CLK_BUS_IR] = &bus_ir_clk.common.hw,
[CLK_BUS_RSB] = &bus_rsb_clk.common.hw,
[CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
[CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
[CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
[CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
[CLK_BUS_PIO] = &bus_pio_clk.common.hw,
[CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
[CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
[CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
[CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
[CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
[CLK_I2S] = &i2s_clk.common.hw,
[CLK_SPDIF] = &spdif_clk.common.hw,
[CLK_IR] = &ir_clk.common.hw,
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
[CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
[CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
[CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
[CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
[CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
[CLK_DE_BE] = &de_be_clk.common.hw,
[CLK_DE_FE] = &de_fe_clk.common.hw,
[CLK_TCON] = &tcon_clk.common.hw,
[CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
[CLK_TVE2_CLK] = &tve_clk2_clk.common.hw,
[CLK_TVE1_CLK] = &tve_clk1_clk.common.hw,
[CLK_TVD] = &tvd_clk.common.hw,
[CLK_CSI] = &csi_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_CODEC] = &codec_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
},
.num = CLK_NUMBER,
};
static struct ccu_reset_map suniv_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_BUS_DMA] = { 0x2c0, BIT(6) },
[RST_BUS_MMC0] = { 0x2c0, BIT(8) },
[RST_BUS_MMC1] = { 0x2c0, BIT(9) },
[RST_BUS_DRAM] = { 0x2c0, BIT(14) },
[RST_BUS_SPI0] = { 0x2c0, BIT(20) },
[RST_BUS_SPI1] = { 0x2c0, BIT(21) },
[RST_BUS_OTG] = { 0x2c0, BIT(24) },
[RST_BUS_VE] = { 0x2c4, BIT(0) },
[RST_BUS_LCD] = { 0x2c4, BIT(4) },
[RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
[RST_BUS_CSI] = { 0x2c4, BIT(8) },
[RST_BUS_TVD] = { 0x2c4, BIT(9) },
[RST_BUS_TVE] = { 0x2c4, BIT(10) },
[RST_BUS_DE_BE] = { 0x2c4, BIT(12) },
[RST_BUS_DE_FE] = { 0x2c4, BIT(14) },
[RST_BUS_CODEC] = { 0x2d0, BIT(0) },
[RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
[RST_BUS_IR] = { 0x2d0, BIT(2) },
[RST_BUS_RSB] = { 0x2d0, BIT(3) },
[RST_BUS_I2S0] = { 0x2d0, BIT(12) },
[RST_BUS_I2C0] = { 0x2d0, BIT(16) },
[RST_BUS_I2C1] = { 0x2d0, BIT(17) },
[RST_BUS_I2C2] = { 0x2d0, BIT(18) },
[RST_BUS_UART0] = { 0x2d0, BIT(20) },
[RST_BUS_UART1] = { 0x2d0, BIT(21) },
[RST_BUS_UART2] = { 0x2d0, BIT(22) },
};
static const struct sunxi_ccu_desc suniv_ccu_desc = {
.ccu_clks = suniv_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(suniv_ccu_clks),
.hw_clks = &suniv_hw_clks,
.resets = suniv_ccu_resets,
.num_resets = ARRAY_SIZE(suniv_ccu_resets),
};
static struct ccu_pll_nb suniv_pll_cpu_nb = {
.common = &pll_cpu_clk.common,
/* copy from pll_cpu_clk */
.enable = BIT(31),
.lock = BIT(28),
};
static struct ccu_mux_nb suniv_cpu_nb = {
.common = &cpu_clk.common,
.cm = &cpu_clk.mux,
.delay_us = 1, /* > 8 clock cycles at 24 MHz */
.bypass_index = 1, /* index of 24 MHz oscillator */
};
static int suniv_f1c100s_ccu_probe(struct platform_device *pdev)
{
void __iomem *reg;
int ret;
u32 val;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
/* Force the PLL-Audio-1x divider to 4 */
val = readl(reg + SUNIV_PLL_AUDIO_REG);
val &= ~GENMASK(19, 16);
writel(val | (3 << 16), reg + SUNIV_PLL_AUDIO_REG);
ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &suniv_ccu_desc);
if (ret)
return ret;
/* Gate then ungate PLL CPU after any rate changes */
ccu_pll_notifier_register(&suniv_pll_cpu_nb);
/* Reparent CPU during PLL CPU rate changes */
ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
&suniv_cpu_nb);
return 0;
}
static const struct of_device_id suniv_f1c100s_ccu_ids[] = {
{ .compatible = "allwinner,suniv-f1c100s-ccu" },
{ }
};
static struct platform_driver suniv_f1c100s_ccu_driver = {
.probe = suniv_f1c100s_ccu_probe,
.driver = {
.name = "suniv-f1c100s-ccu",
.suppress_bind_attrs = true,
.of_match_table = suniv_f1c100s_ccu_ids,
},
};
module_platform_driver(suniv_f1c100s_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Maxime Ripard
* Maxime Ripard <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include "ccu_gate.h"
void ccu_gate_helper_disable(struct ccu_common *common, u32 gate)
{
unsigned long flags;
u32 reg;
if (!gate)
return;
spin_lock_irqsave(common->lock, flags);
reg = readl(common->base + common->reg);
writel(reg & ~gate, common->base + common->reg);
spin_unlock_irqrestore(common->lock, flags);
}
EXPORT_SYMBOL_NS_GPL(ccu_gate_helper_disable, SUNXI_CCU);
static void ccu_gate_disable(struct clk_hw *hw)
{
struct ccu_gate *cg = hw_to_ccu_gate(hw);
return ccu_gate_helper_disable(&cg->common, cg->enable);
}
int ccu_gate_helper_enable(struct ccu_common *common, u32 gate)
{
unsigned long flags;
u32 reg;
if (!gate)
return 0;
spin_lock_irqsave(common->lock, flags);
reg = readl(common->base + common->reg);
writel(reg | gate, common->base + common->reg);
spin_unlock_irqrestore(common->lock, flags);
return 0;
}
EXPORT_SYMBOL_NS_GPL(ccu_gate_helper_enable, SUNXI_CCU);
static int ccu_gate_enable(struct clk_hw *hw)
{
struct ccu_gate *cg = hw_to_ccu_gate(hw);
return ccu_gate_helper_enable(&cg->common, cg->enable);
}
int ccu_gate_helper_is_enabled(struct ccu_common *common, u32 gate)
{
if (!gate)
return 1;
return readl(common->base + common->reg) & gate;
}
EXPORT_SYMBOL_NS_GPL(ccu_gate_helper_is_enabled, SUNXI_CCU);
static int ccu_gate_is_enabled(struct clk_hw *hw)
{
struct ccu_gate *cg = hw_to_ccu_gate(hw);
return ccu_gate_helper_is_enabled(&cg->common, cg->enable);
}
static unsigned long ccu_gate_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct ccu_gate *cg = hw_to_ccu_gate(hw);
unsigned long rate = parent_rate;
if (cg->common.features & CCU_FEATURE_ALL_PREDIV)
rate /= cg->common.prediv;
return rate;
}
static long ccu_gate_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct ccu_gate *cg = hw_to_ccu_gate(hw);
int div = 1;
if (cg->common.features & CCU_FEATURE_ALL_PREDIV)
div = cg->common.prediv;
if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
unsigned long best_parent = rate;
if (cg->common.features & CCU_FEATURE_ALL_PREDIV)
best_parent *= div;
*prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
}
return *prate / div;
}
static int ccu_gate_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
/*
* We must report success but we can do so unconditionally because
* clk_factor_round_rate returns values that ensure this call is a
* nop.
*/
return 0;
}
const struct clk_ops ccu_gate_ops = {
.disable = ccu_gate_disable,
.enable = ccu_gate_enable,
.is_enabled = ccu_gate_is_enabled,
.round_rate = ccu_gate_round_rate,
.set_rate = ccu_gate_set_rate,
.recalc_rate = ccu_gate_recalc_rate,
};
EXPORT_SYMBOL_NS_GPL(ccu_gate_ops, SUNXI_CCU);
| linux-master | drivers/clk/sunxi-ng/ccu_gate.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2016 Maxime Ripard
*
* Maxime Ripard <[email protected]>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/slab.h>
#include "ccu_common.h"
#include "ccu_gate.h"
#include "ccu_reset.h"
struct sunxi_ccu {
const struct sunxi_ccu_desc *desc;
spinlock_t lock;
struct ccu_reset reset;
};
void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock)
{
void __iomem *addr;
u32 reg;
if (!lock)
return;
if (common->features & CCU_FEATURE_LOCK_REG)
addr = common->base + common->lock_reg;
else
addr = common->base + common->reg;
WARN_ON(readl_relaxed_poll_timeout(addr, reg, reg & lock, 100, 70000));
}
EXPORT_SYMBOL_NS_GPL(ccu_helper_wait_for_lock, SUNXI_CCU);
bool ccu_is_better_rate(struct ccu_common *common,
unsigned long target_rate,
unsigned long current_rate,
unsigned long best_rate)
{
if (common->features & CCU_FEATURE_CLOSEST_RATE)
return abs(current_rate - target_rate) < abs(best_rate - target_rate);
return current_rate <= target_rate && current_rate > best_rate;
}
EXPORT_SYMBOL_NS_GPL(ccu_is_better_rate, SUNXI_CCU);
/*
* This clock notifier is called when the frequency of a PLL clock is
* changed. In common PLL designs, changes to the dividers take effect
* almost immediately, while changes to the multipliers (implemented
* as dividers in the feedback loop) take a few cycles to work into
* the feedback loop for the PLL to stablize.
*
* Sometimes when the PLL clock rate is changed, the decrease in the
* divider is too much for the decrease in the multiplier to catch up.
* The PLL clock rate will spike, and in some cases, might lock up
* completely.
*
* This notifier callback will gate and then ungate the clock,
* effectively resetting it, so it proceeds to work. Care must be
* taken to reparent consumers to other temporary clocks during the
* rate change, and that this notifier callback must be the first
* to be registered.
*/
static int ccu_pll_notifier_cb(struct notifier_block *nb,
unsigned long event, void *data)
{
struct ccu_pll_nb *pll = to_ccu_pll_nb(nb);
int ret = 0;
if (event != POST_RATE_CHANGE)
goto out;
ccu_gate_helper_disable(pll->common, pll->enable);
ret = ccu_gate_helper_enable(pll->common, pll->enable);
if (ret)
goto out;
ccu_helper_wait_for_lock(pll->common, pll->lock);
out:
return notifier_from_errno(ret);
}
int ccu_pll_notifier_register(struct ccu_pll_nb *pll_nb)
{
pll_nb->clk_nb.notifier_call = ccu_pll_notifier_cb;
return clk_notifier_register(pll_nb->common->hw.clk,
&pll_nb->clk_nb);
}
EXPORT_SYMBOL_NS_GPL(ccu_pll_notifier_register, SUNXI_CCU);
static int sunxi_ccu_probe(struct sunxi_ccu *ccu, struct device *dev,
struct device_node *node, void __iomem *reg,
const struct sunxi_ccu_desc *desc)
{
struct ccu_reset *reset;
int i, ret;
ccu->desc = desc;
spin_lock_init(&ccu->lock);
for (i = 0; i < desc->num_ccu_clks; i++) {
struct ccu_common *cclk = desc->ccu_clks[i];
if (!cclk)
continue;
cclk->base = reg;
cclk->lock = &ccu->lock;
}
for (i = 0; i < desc->hw_clks->num ; i++) {
struct clk_hw *hw = desc->hw_clks->hws[i];
const char *name;
if (!hw)
continue;
name = hw->init->name;
if (dev)
ret = clk_hw_register(dev, hw);
else
ret = of_clk_hw_register(node, hw);
if (ret) {
pr_err("Couldn't register clock %d - %s\n", i, name);
goto err_clk_unreg;
}
}
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
desc->hw_clks);
if (ret)
goto err_clk_unreg;
reset = &ccu->reset;
reset->rcdev.of_node = node;
reset->rcdev.ops = &ccu_reset_ops;
reset->rcdev.owner = dev ? dev->driver->owner : THIS_MODULE;
reset->rcdev.nr_resets = desc->num_resets;
reset->base = reg;
reset->lock = &ccu->lock;
reset->reset_map = desc->resets;
ret = reset_controller_register(&reset->rcdev);
if (ret)
goto err_del_provider;
return 0;
err_del_provider:
of_clk_del_provider(node);
err_clk_unreg:
while (--i >= 0) {
struct clk_hw *hw = desc->hw_clks->hws[i];
if (!hw)
continue;
clk_hw_unregister(hw);
}
return ret;
}
static void devm_sunxi_ccu_release(struct device *dev, void *res)
{
struct sunxi_ccu *ccu = res;
const struct sunxi_ccu_desc *desc = ccu->desc;
int i;
reset_controller_unregister(&ccu->reset.rcdev);
of_clk_del_provider(dev->of_node);
for (i = 0; i < desc->hw_clks->num; i++) {
struct clk_hw *hw = desc->hw_clks->hws[i];
if (!hw)
continue;
clk_hw_unregister(hw);
}
}
int devm_sunxi_ccu_probe(struct device *dev, void __iomem *reg,
const struct sunxi_ccu_desc *desc)
{
struct sunxi_ccu *ccu;
int ret;
ccu = devres_alloc(devm_sunxi_ccu_release, sizeof(*ccu), GFP_KERNEL);
if (!ccu)
return -ENOMEM;
ret = sunxi_ccu_probe(ccu, dev, dev->of_node, reg, desc);
if (ret) {
devres_free(ccu);
return ret;
}
devres_add(dev, ccu);
return 0;
}
EXPORT_SYMBOL_NS_GPL(devm_sunxi_ccu_probe, SUNXI_CCU);
void of_sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
const struct sunxi_ccu_desc *desc)
{
struct sunxi_ccu *ccu;
int ret;
ccu = kzalloc(sizeof(*ccu), GFP_KERNEL);
if (!ccu)
return;
ret = sunxi_ccu_probe(ccu, NULL, node, reg, desc);
if (ret) {
pr_err("%pOF: probing clocks failed: %d\n", node, ret);
kfree(ccu);
}
}
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu_common.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Maxime Ripard
* Maxime Ripard <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include "ccu_gate.h"
#include "ccu_nkmp.h"
struct _ccu_nkmp {
unsigned long n, min_n, max_n;
unsigned long k, min_k, max_k;
unsigned long m, min_m, max_m;
unsigned long p, min_p, max_p;
};
static unsigned long ccu_nkmp_calc_rate(unsigned long parent,
unsigned long n, unsigned long k,
unsigned long m, unsigned long p)
{
u64 rate = parent;
rate *= n * k;
do_div(rate, m * p);
return rate;
}
static unsigned long ccu_nkmp_find_best(unsigned long parent, unsigned long rate,
struct _ccu_nkmp *nkmp)
{
unsigned long best_rate = 0;
unsigned long best_n = 0, best_k = 0, best_m = 0, best_p = 0;
unsigned long _n, _k, _m, _p;
for (_k = nkmp->min_k; _k <= nkmp->max_k; _k++) {
for (_n = nkmp->min_n; _n <= nkmp->max_n; _n++) {
for (_m = nkmp->min_m; _m <= nkmp->max_m; _m++) {
for (_p = nkmp->min_p; _p <= nkmp->max_p; _p <<= 1) {
unsigned long tmp_rate;
tmp_rate = ccu_nkmp_calc_rate(parent,
_n, _k,
_m, _p);
if (tmp_rate > rate)
continue;
if ((rate - tmp_rate) < (rate - best_rate)) {
best_rate = tmp_rate;
best_n = _n;
best_k = _k;
best_m = _m;
best_p = _p;
}
}
}
}
}
nkmp->n = best_n;
nkmp->k = best_k;
nkmp->m = best_m;
nkmp->p = best_p;
return best_rate;
}
static void ccu_nkmp_disable(struct clk_hw *hw)
{
struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
return ccu_gate_helper_disable(&nkmp->common, nkmp->enable);
}
static int ccu_nkmp_enable(struct clk_hw *hw)
{
struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
return ccu_gate_helper_enable(&nkmp->common, nkmp->enable);
}
static int ccu_nkmp_is_enabled(struct clk_hw *hw)
{
struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
return ccu_gate_helper_is_enabled(&nkmp->common, nkmp->enable);
}
static unsigned long ccu_nkmp_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
unsigned long n, m, k, p, rate;
u32 reg;
reg = readl(nkmp->common.base + nkmp->common.reg);
n = reg >> nkmp->n.shift;
n &= (1 << nkmp->n.width) - 1;
n += nkmp->n.offset;
if (!n)
n++;
k = reg >> nkmp->k.shift;
k &= (1 << nkmp->k.width) - 1;
k += nkmp->k.offset;
if (!k)
k++;
m = reg >> nkmp->m.shift;
m &= (1 << nkmp->m.width) - 1;
m += nkmp->m.offset;
if (!m)
m++;
p = reg >> nkmp->p.shift;
p &= (1 << nkmp->p.width) - 1;
rate = ccu_nkmp_calc_rate(parent_rate, n, k, m, 1 << p);
if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nkmp->fixed_post_div;
return rate;
}
static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
struct _ccu_nkmp _nkmp;
if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate *= nkmp->fixed_post_div;
if (nkmp->max_rate && rate > nkmp->max_rate) {
rate = nkmp->max_rate;
if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nkmp->fixed_post_div;
return rate;
}
_nkmp.min_n = nkmp->n.min ?: 1;
_nkmp.max_n = nkmp->n.max ?: 1 << nkmp->n.width;
_nkmp.min_k = nkmp->k.min ?: 1;
_nkmp.max_k = nkmp->k.max ?: 1 << nkmp->k.width;
_nkmp.min_m = 1;
_nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width;
_nkmp.min_p = 1;
_nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1);
rate = ccu_nkmp_find_best(*parent_rate, rate, &_nkmp);
if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate = rate / nkmp->fixed_post_div;
return rate;
}
static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
u32 n_mask = 0, k_mask = 0, m_mask = 0, p_mask = 0;
struct _ccu_nkmp _nkmp;
unsigned long flags;
u32 reg;
if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate = rate * nkmp->fixed_post_div;
_nkmp.min_n = nkmp->n.min ?: 1;
_nkmp.max_n = nkmp->n.max ?: 1 << nkmp->n.width;
_nkmp.min_k = nkmp->k.min ?: 1;
_nkmp.max_k = nkmp->k.max ?: 1 << nkmp->k.width;
_nkmp.min_m = 1;
_nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width;
_nkmp.min_p = 1;
_nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1);
ccu_nkmp_find_best(parent_rate, rate, &_nkmp);
/*
* If width is 0, GENMASK() macro may not generate expected mask (0)
* as it falls under undefined behaviour by C standard due to shifts
* which are equal or greater than width of left operand. This can
* be easily avoided by explicitly checking if width is 0.
*/
if (nkmp->n.width)
n_mask = GENMASK(nkmp->n.width + nkmp->n.shift - 1,
nkmp->n.shift);
if (nkmp->k.width)
k_mask = GENMASK(nkmp->k.width + nkmp->k.shift - 1,
nkmp->k.shift);
if (nkmp->m.width)
m_mask = GENMASK(nkmp->m.width + nkmp->m.shift - 1,
nkmp->m.shift);
if (nkmp->p.width)
p_mask = GENMASK(nkmp->p.width + nkmp->p.shift - 1,
nkmp->p.shift);
spin_lock_irqsave(nkmp->common.lock, flags);
reg = readl(nkmp->common.base + nkmp->common.reg);
reg &= ~(n_mask | k_mask | m_mask | p_mask);
reg |= ((_nkmp.n - nkmp->n.offset) << nkmp->n.shift) & n_mask;
reg |= ((_nkmp.k - nkmp->k.offset) << nkmp->k.shift) & k_mask;
reg |= ((_nkmp.m - nkmp->m.offset) << nkmp->m.shift) & m_mask;
reg |= (ilog2(_nkmp.p) << nkmp->p.shift) & p_mask;
writel(reg, nkmp->common.base + nkmp->common.reg);
spin_unlock_irqrestore(nkmp->common.lock, flags);
ccu_helper_wait_for_lock(&nkmp->common, nkmp->lock);
return 0;
}
const struct clk_ops ccu_nkmp_ops = {
.disable = ccu_nkmp_disable,
.enable = ccu_nkmp_enable,
.is_enabled = ccu_nkmp_is_enabled,
.recalc_rate = ccu_nkmp_recalc_rate,
.round_rate = ccu_nkmp_round_rate,
.set_rate = ccu_nkmp_set_rate,
};
EXPORT_SYMBOL_NS_GPL(ccu_nkmp_ops, SUNXI_CCU);
| linux-master | drivers/clk/sunxi-ng/ccu_nkmp.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 Chen-Yu Tsai. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/clk/sunxi-ng.h>
#include <linux/io.h>
#include "ccu_common.h"
/**
* sunxi_ccu_set_mmc_timing_mode - Configure the MMC clock timing mode
* @clk: clock to be configured
* @new_mode: true for new timing mode introduced in A83T and later
*
* Return: %0 on success, %-ENOTSUPP if the clock does not support
* switching modes.
*/
int sunxi_ccu_set_mmc_timing_mode(struct clk *clk, bool new_mode)
{
struct clk_hw *hw = __clk_get_hw(clk);
struct ccu_common *cm = hw_to_ccu_common(hw);
unsigned long flags;
u32 val;
if (!(cm->features & CCU_FEATURE_MMC_TIMING_SWITCH))
return -ENOTSUPP;
spin_lock_irqsave(cm->lock, flags);
val = readl(cm->base + cm->reg);
if (new_mode)
val |= CCU_MMC_NEW_TIMING_MODE;
else
val &= ~CCU_MMC_NEW_TIMING_MODE;
writel(val, cm->base + cm->reg);
spin_unlock_irqrestore(cm->lock, flags);
return 0;
}
EXPORT_SYMBOL_GPL(sunxi_ccu_set_mmc_timing_mode);
/**
* sunxi_ccu_get_mmc_timing_mode: Get the current MMC clock timing mode
* @clk: clock to query
*
* Return: %0 if the clock is in old timing mode, > %0 if it is in
* new timing mode, and %-ENOTSUPP if the clock does not support
* this function.
*/
int sunxi_ccu_get_mmc_timing_mode(struct clk *clk)
{
struct clk_hw *hw = __clk_get_hw(clk);
struct ccu_common *cm = hw_to_ccu_common(hw);
if (!(cm->features & CCU_FEATURE_MMC_TIMING_SWITCH))
return -ENOTSUPP;
return !!(readl(cm->base + cm->reg) & CCU_MMC_NEW_TIMING_MODE);
}
EXPORT_SYMBOL_GPL(sunxi_ccu_get_mmc_timing_mode);
| linux-master | drivers/clk/sunxi-ng/ccu_mmc_timing.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Maxime Ripard
* Maxime Ripard <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include "ccu_frac.h"
bool ccu_frac_helper_is_enabled(struct ccu_common *common,
struct ccu_frac_internal *cf)
{
if (!(common->features & CCU_FEATURE_FRACTIONAL))
return false;
return !(readl(common->base + common->reg) & cf->enable);
}
EXPORT_SYMBOL_NS_GPL(ccu_frac_helper_is_enabled, SUNXI_CCU);
void ccu_frac_helper_enable(struct ccu_common *common,
struct ccu_frac_internal *cf)
{
unsigned long flags;
u32 reg;
if (!(common->features & CCU_FEATURE_FRACTIONAL))
return;
spin_lock_irqsave(common->lock, flags);
reg = readl(common->base + common->reg);
writel(reg & ~cf->enable, common->base + common->reg);
spin_unlock_irqrestore(common->lock, flags);
}
EXPORT_SYMBOL_NS_GPL(ccu_frac_helper_enable, SUNXI_CCU);
void ccu_frac_helper_disable(struct ccu_common *common,
struct ccu_frac_internal *cf)
{
unsigned long flags;
u32 reg;
if (!(common->features & CCU_FEATURE_FRACTIONAL))
return;
spin_lock_irqsave(common->lock, flags);
reg = readl(common->base + common->reg);
writel(reg | cf->enable, common->base + common->reg);
spin_unlock_irqrestore(common->lock, flags);
}
EXPORT_SYMBOL_NS_GPL(ccu_frac_helper_disable, SUNXI_CCU);
bool ccu_frac_helper_has_rate(struct ccu_common *common,
struct ccu_frac_internal *cf,
unsigned long rate)
{
if (!(common->features & CCU_FEATURE_FRACTIONAL))
return false;
return (cf->rates[0] == rate) || (cf->rates[1] == rate);
}
EXPORT_SYMBOL_NS_GPL(ccu_frac_helper_has_rate, SUNXI_CCU);
unsigned long ccu_frac_helper_read_rate(struct ccu_common *common,
struct ccu_frac_internal *cf)
{
u32 reg;
pr_debug("%s: Read fractional\n", clk_hw_get_name(&common->hw));
if (!(common->features & CCU_FEATURE_FRACTIONAL))
return 0;
pr_debug("%s: clock is fractional (rates %lu and %lu)\n",
clk_hw_get_name(&common->hw), cf->rates[0], cf->rates[1]);
reg = readl(common->base + common->reg);
pr_debug("%s: clock reg is 0x%x (select is 0x%x)\n",
clk_hw_get_name(&common->hw), reg, cf->select);
return (reg & cf->select) ? cf->rates[1] : cf->rates[0];
}
EXPORT_SYMBOL_NS_GPL(ccu_frac_helper_read_rate, SUNXI_CCU);
int ccu_frac_helper_set_rate(struct ccu_common *common,
struct ccu_frac_internal *cf,
unsigned long rate, u32 lock)
{
unsigned long flags;
u32 reg, sel;
if (!(common->features & CCU_FEATURE_FRACTIONAL))
return -EINVAL;
if (cf->rates[0] == rate)
sel = 0;
else if (cf->rates[1] == rate)
sel = cf->select;
else
return -EINVAL;
spin_lock_irqsave(common->lock, flags);
reg = readl(common->base + common->reg);
reg &= ~cf->select;
writel(reg | sel, common->base + common->reg);
spin_unlock_irqrestore(common->lock, flags);
ccu_helper_wait_for_lock(common, lock);
return 0;
}
EXPORT_SYMBOL_NS_GPL(ccu_frac_helper_set_rate, SUNXI_CCU);
| linux-master | drivers/clk/sunxi-ng/ccu_frac.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2017 Chen-Yu Tsai <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include "ccu_sdm.h"
bool ccu_sdm_helper_is_enabled(struct ccu_common *common,
struct ccu_sdm_internal *sdm)
{
if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD))
return false;
if (sdm->enable && !(readl(common->base + common->reg) & sdm->enable))
return false;
return !!(readl(common->base + sdm->tuning_reg) & sdm->tuning_enable);
}
EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_is_enabled, SUNXI_CCU);
void ccu_sdm_helper_enable(struct ccu_common *common,
struct ccu_sdm_internal *sdm,
unsigned long rate)
{
unsigned long flags;
unsigned int i;
u32 reg;
if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD))
return;
/* Set the pattern */
for (i = 0; i < sdm->table_size; i++)
if (sdm->table[i].rate == rate)
writel(sdm->table[i].pattern,
common->base + sdm->tuning_reg);
/* Make sure SDM is enabled */
spin_lock_irqsave(common->lock, flags);
reg = readl(common->base + sdm->tuning_reg);
writel(reg | sdm->tuning_enable, common->base + sdm->tuning_reg);
spin_unlock_irqrestore(common->lock, flags);
spin_lock_irqsave(common->lock, flags);
reg = readl(common->base + common->reg);
writel(reg | sdm->enable, common->base + common->reg);
spin_unlock_irqrestore(common->lock, flags);
}
EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_enable, SUNXI_CCU);
void ccu_sdm_helper_disable(struct ccu_common *common,
struct ccu_sdm_internal *sdm)
{
unsigned long flags;
u32 reg;
if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD))
return;
spin_lock_irqsave(common->lock, flags);
reg = readl(common->base + common->reg);
writel(reg & ~sdm->enable, common->base + common->reg);
spin_unlock_irqrestore(common->lock, flags);
spin_lock_irqsave(common->lock, flags);
reg = readl(common->base + sdm->tuning_reg);
writel(reg & ~sdm->tuning_enable, common->base + sdm->tuning_reg);
spin_unlock_irqrestore(common->lock, flags);
}
EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_disable, SUNXI_CCU);
/*
* Sigma delta modulation provides a way to do fractional-N frequency
* synthesis, in essence allowing the PLL to output any frequency
* within its operational range. On earlier SoCs such as the A10/A20,
* some PLLs support this. On later SoCs, all PLLs support this.
*
* The datasheets do not explain what the "wave top" and "wave bottom"
* parameters mean or do, nor how to calculate the effective output
* frequency. The only examples (and real world usage) are for the audio
* PLL to generate 24.576 and 22.5792 MHz clock rates used by the audio
* peripherals. The author lacks the underlying domain knowledge to
* pursue this.
*
* The goal and function of the following code is to support the two
* clock rates used by the audio subsystem, allowing for proper audio
* playback and capture without any pitch or speed changes.
*/
bool ccu_sdm_helper_has_rate(struct ccu_common *common,
struct ccu_sdm_internal *sdm,
unsigned long rate)
{
unsigned int i;
if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD))
return false;
for (i = 0; i < sdm->table_size; i++)
if (sdm->table[i].rate == rate)
return true;
return false;
}
EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_has_rate, SUNXI_CCU);
unsigned long ccu_sdm_helper_read_rate(struct ccu_common *common,
struct ccu_sdm_internal *sdm,
u32 m, u32 n)
{
unsigned int i;
u32 reg;
pr_debug("%s: Read sigma-delta modulation setting\n",
clk_hw_get_name(&common->hw));
if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD))
return 0;
pr_debug("%s: clock is sigma-delta modulated\n",
clk_hw_get_name(&common->hw));
reg = readl(common->base + sdm->tuning_reg);
pr_debug("%s: pattern reg is 0x%x",
clk_hw_get_name(&common->hw), reg);
for (i = 0; i < sdm->table_size; i++)
if (sdm->table[i].pattern == reg &&
sdm->table[i].m == m && sdm->table[i].n == n)
return sdm->table[i].rate;
/* We can't calculate the effective clock rate, so just fail. */
return 0;
}
EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_read_rate, SUNXI_CCU);
int ccu_sdm_helper_get_factors(struct ccu_common *common,
struct ccu_sdm_internal *sdm,
unsigned long rate,
unsigned long *m, unsigned long *n)
{
unsigned int i;
if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD))
return -EINVAL;
for (i = 0; i < sdm->table_size; i++)
if (sdm->table[i].rate == rate) {
*m = sdm->table[i].m;
*n = sdm->table[i].n;
return 0;
}
/* nothing found */
return -EINVAL;
}
EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_get_factors, SUNXI_CCU);
| linux-master | drivers/clk/sunxi-ng/ccu_sdm.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016 Icenowy Zheng <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu_nm.h"
#include "ccu-sun8i-r.h"
static const struct clk_parent_data ar100_parents[] = {
{ .fw_name = "losc" },
{ .fw_name = "hosc" },
{ .fw_name = "pll-periph" },
{ .fw_name = "iosc" },
};
static const struct ccu_mux_var_prediv ar100_predivs[] = {
{ .index = 2, .shift = 8, .width = 5 },
};
static struct ccu_div ar100_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = {
.shift = 16,
.width = 2,
.var_predivs = ar100_predivs,
.n_var_predivs = ARRAY_SIZE(ar100_predivs),
},
.common = {
.reg = 0x00,
.features = CCU_FEATURE_VARIABLE_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS_DATA("ar100",
ar100_parents,
&ccu_div_ops,
0),
},
};
static CLK_FIXED_FACTOR_HW(ahb0_clk, "ahb0", &ar100_clk.common.hw, 1, 1, 0);
static SUNXI_CCU_M(apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0);
/*
* Define the parent as an array that can be reused to save space
* instead of having compound literals for each gate. Also have it
* non-const so we can change it on the A83T.
*/
static const struct clk_hw *apb0_gate_parent[] = { &apb0_clk.common.hw };
static SUNXI_CCU_GATE_HWS(apb0_pio_clk, "apb0-pio",
apb0_gate_parent, 0x28, BIT(0), 0);
static SUNXI_CCU_GATE_HWS(apb0_ir_clk, "apb0-ir",
apb0_gate_parent, 0x28, BIT(1), 0);
static SUNXI_CCU_GATE_HWS(apb0_timer_clk, "apb0-timer",
apb0_gate_parent, 0x28, BIT(2), 0);
static SUNXI_CCU_GATE_HWS(apb0_rsb_clk, "apb0-rsb",
apb0_gate_parent, 0x28, BIT(3), 0);
static SUNXI_CCU_GATE_HWS(apb0_uart_clk, "apb0-uart",
apb0_gate_parent, 0x28, BIT(4), 0);
static SUNXI_CCU_GATE_HWS(apb0_i2c_clk, "apb0-i2c",
apb0_gate_parent, 0x28, BIT(6), 0);
static SUNXI_CCU_GATE_HWS(apb0_twd_clk, "apb0-twd",
apb0_gate_parent, 0x28, BIT(7), 0);
static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
r_mod0_default_parents, 0x54,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static const struct clk_parent_data a83t_r_mod0_parents[] = {
{ .fw_name = "iosc" },
{ .fw_name = "hosc" },
};
static const struct ccu_mux_fixed_prediv a83t_ir_predivs[] = {
{ .index = 0, .div = 16 },
};
static struct ccu_mp a83t_ir_clk = {
.enable = BIT(31),
.m = _SUNXI_CCU_DIV(0, 4),
.p = _SUNXI_CCU_DIV(16, 2),
.mux = {
.shift = 24,
.width = 2,
.fixed_predivs = a83t_ir_predivs,
.n_predivs = ARRAY_SIZE(a83t_ir_predivs),
},
.common = {
.reg = 0x54,
.features = CCU_FEATURE_VARIABLE_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS_DATA("ir",
a83t_r_mod0_parents,
&ccu_mp_ops,
0),
},
};
static struct ccu_common *sun8i_r_ccu_clks[] = {
&ar100_clk.common,
&apb0_clk.common,
&apb0_pio_clk.common,
&apb0_ir_clk.common,
&apb0_timer_clk.common,
&apb0_rsb_clk.common,
&apb0_uart_clk.common,
&apb0_i2c_clk.common,
&apb0_twd_clk.common,
&ir_clk.common,
&a83t_ir_clk.common,
};
static struct clk_hw_onecell_data sun8i_a83t_r_hw_clks = {
.hws = {
[CLK_AR100] = &ar100_clk.common.hw,
[CLK_AHB0] = &ahb0_clk.hw,
[CLK_APB0] = &apb0_clk.common.hw,
[CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
[CLK_APB0_IR] = &apb0_ir_clk.common.hw,
[CLK_APB0_TIMER] = &apb0_timer_clk.common.hw,
[CLK_APB0_RSB] = &apb0_rsb_clk.common.hw,
[CLK_APB0_UART] = &apb0_uart_clk.common.hw,
[CLK_APB0_I2C] = &apb0_i2c_clk.common.hw,
[CLK_APB0_TWD] = &apb0_twd_clk.common.hw,
[CLK_IR] = &a83t_ir_clk.common.hw,
},
.num = CLK_NUMBER,
};
static struct clk_hw_onecell_data sun8i_h3_r_hw_clks = {
.hws = {
[CLK_AR100] = &ar100_clk.common.hw,
[CLK_AHB0] = &ahb0_clk.hw,
[CLK_APB0] = &apb0_clk.common.hw,
[CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
[CLK_APB0_IR] = &apb0_ir_clk.common.hw,
[CLK_APB0_TIMER] = &apb0_timer_clk.common.hw,
[CLK_APB0_UART] = &apb0_uart_clk.common.hw,
[CLK_APB0_I2C] = &apb0_i2c_clk.common.hw,
[CLK_APB0_TWD] = &apb0_twd_clk.common.hw,
[CLK_IR] = &ir_clk.common.hw,
},
.num = CLK_NUMBER,
};
static struct clk_hw_onecell_data sun50i_a64_r_hw_clks = {
.hws = {
[CLK_AR100] = &ar100_clk.common.hw,
[CLK_AHB0] = &ahb0_clk.hw,
[CLK_APB0] = &apb0_clk.common.hw,
[CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
[CLK_APB0_IR] = &apb0_ir_clk.common.hw,
[CLK_APB0_TIMER] = &apb0_timer_clk.common.hw,
[CLK_APB0_RSB] = &apb0_rsb_clk.common.hw,
[CLK_APB0_UART] = &apb0_uart_clk.common.hw,
[CLK_APB0_I2C] = &apb0_i2c_clk.common.hw,
[CLK_APB0_TWD] = &apb0_twd_clk.common.hw,
[CLK_IR] = &ir_clk.common.hw,
},
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun8i_a83t_r_ccu_resets[] = {
[RST_APB0_IR] = { 0xb0, BIT(1) },
[RST_APB0_TIMER] = { 0xb0, BIT(2) },
[RST_APB0_RSB] = { 0xb0, BIT(3) },
[RST_APB0_UART] = { 0xb0, BIT(4) },
[RST_APB0_I2C] = { 0xb0, BIT(6) },
};
static struct ccu_reset_map sun8i_h3_r_ccu_resets[] = {
[RST_APB0_IR] = { 0xb0, BIT(1) },
[RST_APB0_TIMER] = { 0xb0, BIT(2) },
[RST_APB0_UART] = { 0xb0, BIT(4) },
[RST_APB0_I2C] = { 0xb0, BIT(6) },
};
static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = {
[RST_APB0_IR] = { 0xb0, BIT(1) },
[RST_APB0_TIMER] = { 0xb0, BIT(2) },
[RST_APB0_RSB] = { 0xb0, BIT(3) },
[RST_APB0_UART] = { 0xb0, BIT(4) },
[RST_APB0_I2C] = { 0xb0, BIT(6) },
};
static const struct sunxi_ccu_desc sun8i_a83t_r_ccu_desc = {
.ccu_clks = sun8i_r_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_r_ccu_clks),
.hw_clks = &sun8i_a83t_r_hw_clks,
.resets = sun8i_a83t_r_ccu_resets,
.num_resets = ARRAY_SIZE(sun8i_a83t_r_ccu_resets),
};
static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = {
.ccu_clks = sun8i_r_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_r_ccu_clks),
.hw_clks = &sun8i_h3_r_hw_clks,
.resets = sun8i_h3_r_ccu_resets,
.num_resets = ARRAY_SIZE(sun8i_h3_r_ccu_resets),
};
static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = {
.ccu_clks = sun8i_r_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_r_ccu_clks),
.hw_clks = &sun50i_a64_r_hw_clks,
.resets = sun50i_a64_r_ccu_resets,
.num_resets = ARRAY_SIZE(sun50i_a64_r_ccu_resets),
};
static int sun8i_r_ccu_probe(struct platform_device *pdev)
{
const struct sunxi_ccu_desc *desc;
void __iomem *reg;
desc = of_device_get_match_data(&pdev->dev);
if (!desc)
return -EINVAL;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
return devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
}
static const struct of_device_id sun8i_r_ccu_ids[] = {
{
.compatible = "allwinner,sun8i-a83t-r-ccu",
.data = &sun8i_a83t_r_ccu_desc,
},
{
.compatible = "allwinner,sun8i-h3-r-ccu",
.data = &sun8i_h3_r_ccu_desc,
},
{
.compatible = "allwinner,sun50i-a64-r-ccu",
.data = &sun50i_a64_r_ccu_desc,
},
{ }
};
static struct platform_driver sun8i_r_ccu_driver = {
.probe = sun8i_r_ccu_probe,
.driver = {
.name = "sun8i-r-ccu",
.suppress_bind_attrs = true,
.of_match_table = sun8i_r_ccu_ids,
},
};
module_platform_driver(sun8i_r_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun8i-r.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 Icenowy Zheng <[email protected]>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include "ccu_common.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_reset.h"
#include "ccu-sun8i-de2.h"
static SUNXI_CCU_GATE(bus_mixer0_clk, "bus-mixer0", "bus-de",
0x04, BIT(0), 0);
static SUNXI_CCU_GATE(bus_mixer1_clk, "bus-mixer1", "bus-de",
0x04, BIT(1), 0);
static SUNXI_CCU_GATE(bus_wb_clk, "bus-wb", "bus-de",
0x04, BIT(2), 0);
static SUNXI_CCU_GATE(bus_rot_clk, "bus-rot", "bus-de",
0x04, BIT(3), 0);
static SUNXI_CCU_GATE(mixer0_clk, "mixer0", "mixer0-div",
0x00, BIT(0), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(mixer1_clk, "mixer1", "mixer1-div",
0x00, BIT(1), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(wb_clk, "wb", "wb-div",
0x00, BIT(2), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(rot_clk, "rot", "rot-div",
0x00, BIT(3), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4,
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(mixer1_div_clk, "mixer1-div", "de", 0x0c, 4, 4,
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4,
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(rot_div_clk, "rot-div", "de", 0x0c, 0x0c, 4,
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(mixer0_div_a83_clk, "mixer0-div", "pll-de", 0x0c, 0, 4,
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4,
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4,
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(rot_div_a83_clk, "rot-div", "pll-de", 0x0c, 0x0c, 4,
CLK_SET_RATE_PARENT);
static struct ccu_common *sun8i_de2_ccu_clks[] = {
&mixer0_clk.common,
&mixer1_clk.common,
&wb_clk.common,
&rot_clk.common,
&bus_mixer0_clk.common,
&bus_mixer1_clk.common,
&bus_wb_clk.common,
&bus_rot_clk.common,
&mixer0_div_clk.common,
&mixer1_div_clk.common,
&wb_div_clk.common,
&rot_div_clk.common,
&mixer0_div_a83_clk.common,
&mixer1_div_a83_clk.common,
&wb_div_a83_clk.common,
&rot_div_a83_clk.common,
};
static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
.hws = {
[CLK_MIXER0] = &mixer0_clk.common.hw,
[CLK_MIXER1] = &mixer1_clk.common.hw,
[CLK_WB] = &wb_clk.common.hw,
[CLK_ROT] = &rot_clk.common.hw,
[CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,
[CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,
[CLK_BUS_WB] = &bus_wb_clk.common.hw,
[CLK_BUS_ROT] = &bus_rot_clk.common.hw,
[CLK_MIXER0_DIV] = &mixer0_div_a83_clk.common.hw,
[CLK_MIXER1_DIV] = &mixer1_div_a83_clk.common.hw,
[CLK_WB_DIV] = &wb_div_a83_clk.common.hw,
[CLK_ROT_DIV] = &rot_div_a83_clk.common.hw,
},
.num = CLK_NUMBER_WITH_ROT,
};
static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = {
.hws = {
[CLK_MIXER0] = &mixer0_clk.common.hw,
[CLK_MIXER1] = &mixer1_clk.common.hw,
[CLK_WB] = &wb_clk.common.hw,
[CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,
[CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,
[CLK_BUS_WB] = &bus_wb_clk.common.hw,
[CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw,
[CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw,
[CLK_WB_DIV] = &wb_div_clk.common.hw,
},
.num = CLK_NUMBER_WITHOUT_ROT,
};
static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = {
.hws = {
[CLK_MIXER0] = &mixer0_clk.common.hw,
[CLK_WB] = &wb_clk.common.hw,
[CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,
[CLK_BUS_WB] = &bus_wb_clk.common.hw,
[CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw,
[CLK_WB_DIV] = &wb_div_clk.common.hw,
},
.num = CLK_NUMBER_WITHOUT_ROT,
};
static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = {
.hws = {
[CLK_MIXER0] = &mixer0_clk.common.hw,
[CLK_MIXER1] = &mixer1_clk.common.hw,
[CLK_WB] = &wb_clk.common.hw,
[CLK_ROT] = &rot_clk.common.hw,
[CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,
[CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,
[CLK_BUS_WB] = &bus_wb_clk.common.hw,
[CLK_BUS_ROT] = &bus_rot_clk.common.hw,
[CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw,
[CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw,
[CLK_WB_DIV] = &wb_div_clk.common.hw,
[CLK_ROT_DIV] = &rot_div_clk.common.hw,
},
.num = CLK_NUMBER_WITH_ROT,
};
static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
/*
* Mixer1 reset line is shared with wb, so only RST_WB is
* exported here.
*/
[RST_WB] = { 0x08, BIT(2) },
[RST_ROT] = { 0x08, BIT(3) },
};
static struct ccu_reset_map sun8i_h3_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
/*
* Mixer1 reset line is shared with wb, so only RST_WB is
* exported here.
* V3s doesn't have mixer1, so it also shares this struct.
*/
[RST_WB] = { 0x08, BIT(2) },
};
static struct ccu_reset_map sun50i_a64_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
[RST_MIXER1] = { 0x08, BIT(1) },
[RST_WB] = { 0x08, BIT(2) },
[RST_ROT] = { 0x08, BIT(3) },
};
static struct ccu_reset_map sun50i_h5_de2_resets[] = {
[RST_MIXER0] = { 0x08, BIT(0) },
[RST_MIXER1] = { 0x08, BIT(1) },
[RST_WB] = { 0x08, BIT(2) },
};
static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
.ccu_clks = sun8i_de2_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_de2_ccu_clks),
.hw_clks = &sun8i_a83t_de2_hw_clks,
.resets = sun8i_a83t_de2_resets,
.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
};
static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
.ccu_clks = sun8i_de2_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_de2_ccu_clks),
.hw_clks = &sun8i_h3_de2_hw_clks,
.resets = sun8i_h3_de2_resets,
.num_resets = ARRAY_SIZE(sun8i_h3_de2_resets),
};
static const struct sunxi_ccu_desc sun8i_r40_de2_clk_desc = {
.ccu_clks = sun8i_de2_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_de2_ccu_clks),
.hw_clks = &sun50i_a64_de2_hw_clks,
.resets = sun8i_a83t_de2_resets,
.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
};
static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
.ccu_clks = sun8i_de2_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_de2_ccu_clks),
.hw_clks = &sun8i_v3s_de2_hw_clks,
.resets = sun8i_a83t_de2_resets,
.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
};
static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
.ccu_clks = sun8i_de2_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_de2_ccu_clks),
.hw_clks = &sun50i_a64_de2_hw_clks,
.resets = sun50i_a64_de2_resets,
.num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
};
static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {
.ccu_clks = sun8i_de2_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_de2_ccu_clks),
.hw_clks = &sun8i_h3_de2_hw_clks,
.resets = sun50i_h5_de2_resets,
.num_resets = ARRAY_SIZE(sun50i_h5_de2_resets),
};
static int sunxi_de2_clk_probe(struct platform_device *pdev)
{
struct clk *bus_clk, *mod_clk;
struct reset_control *rstc;
void __iomem *reg;
const struct sunxi_ccu_desc *ccu_desc;
int ret;
ccu_desc = of_device_get_match_data(&pdev->dev);
if (!ccu_desc)
return -EINVAL;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
bus_clk = devm_clk_get(&pdev->dev, "bus");
if (IS_ERR(bus_clk))
return dev_err_probe(&pdev->dev, PTR_ERR(bus_clk),
"Couldn't get bus clk\n");
mod_clk = devm_clk_get(&pdev->dev, "mod");
if (IS_ERR(mod_clk))
return dev_err_probe(&pdev->dev, PTR_ERR(mod_clk),
"Couldn't get mod clk\n");
rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (IS_ERR(rstc))
return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
"Couldn't get reset control\n");
/* The clocks need to be enabled for us to access the registers */
ret = clk_prepare_enable(bus_clk);
if (ret) {
dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret);
return ret;
}
ret = clk_prepare_enable(mod_clk);
if (ret) {
dev_err(&pdev->dev, "Couldn't enable mod clk: %d\n", ret);
goto err_disable_bus_clk;
}
/* The reset control needs to be asserted for the controls to work */
ret = reset_control_deassert(rstc);
if (ret) {
dev_err(&pdev->dev,
"Couldn't deassert reset control: %d\n", ret);
goto err_disable_mod_clk;
}
ret = devm_sunxi_ccu_probe(&pdev->dev, reg, ccu_desc);
if (ret)
goto err_assert_reset;
return 0;
err_assert_reset:
reset_control_assert(rstc);
err_disable_mod_clk:
clk_disable_unprepare(mod_clk);
err_disable_bus_clk:
clk_disable_unprepare(bus_clk);
return ret;
}
static const struct of_device_id sunxi_de2_clk_ids[] = {
{
.compatible = "allwinner,sun8i-a83t-de2-clk",
.data = &sun8i_a83t_de2_clk_desc,
},
{
.compatible = "allwinner,sun8i-h3-de2-clk",
.data = &sun8i_h3_de2_clk_desc,
},
{
.compatible = "allwinner,sun8i-r40-de2-clk",
.data = &sun8i_r40_de2_clk_desc,
},
{
.compatible = "allwinner,sun8i-v3s-de2-clk",
.data = &sun8i_v3s_de2_clk_desc,
},
{
.compatible = "allwinner,sun50i-a64-de2-clk",
.data = &sun50i_a64_de2_clk_desc,
},
{
.compatible = "allwinner,sun50i-h5-de2-clk",
.data = &sun50i_h5_de2_clk_desc,
},
{
.compatible = "allwinner,sun50i-h6-de3-clk",
.data = &sun50i_h5_de2_clk_desc,
},
{ }
};
static struct platform_driver sunxi_de2_clk_driver = {
.probe = sunxi_de2_clk_probe,
.driver = {
.name = "sunxi-de2-clks",
.of_match_table = sunxi_de2_clk_ids,
},
};
module_platform_driver(sunxi_de2_clk_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun8i-de2.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Maxime Ripard
* Maxime Ripard <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include "ccu_gate.h"
#include "ccu_mult.h"
struct _ccu_mult {
unsigned long mult, min, max;
};
static void ccu_mult_find_best(unsigned long parent, unsigned long rate,
struct _ccu_mult *mult)
{
int _mult;
_mult = rate / parent;
if (_mult < mult->min)
_mult = mult->min;
if (_mult > mult->max)
_mult = mult->max;
mult->mult = _mult;
}
static unsigned long ccu_mult_round_rate(struct ccu_mux_internal *mux,
struct clk_hw *parent,
unsigned long *parent_rate,
unsigned long rate,
void *data)
{
struct ccu_mult *cm = data;
struct _ccu_mult _cm;
_cm.min = cm->mult.min;
if (cm->mult.max)
_cm.max = cm->mult.max;
else
_cm.max = (1 << cm->mult.width) + cm->mult.offset - 1;
ccu_mult_find_best(*parent_rate, rate, &_cm);
return *parent_rate * _cm.mult;
}
static void ccu_mult_disable(struct clk_hw *hw)
{
struct ccu_mult *cm = hw_to_ccu_mult(hw);
return ccu_gate_helper_disable(&cm->common, cm->enable);
}
static int ccu_mult_enable(struct clk_hw *hw)
{
struct ccu_mult *cm = hw_to_ccu_mult(hw);
return ccu_gate_helper_enable(&cm->common, cm->enable);
}
static int ccu_mult_is_enabled(struct clk_hw *hw)
{
struct ccu_mult *cm = hw_to_ccu_mult(hw);
return ccu_gate_helper_is_enabled(&cm->common, cm->enable);
}
static unsigned long ccu_mult_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct ccu_mult *cm = hw_to_ccu_mult(hw);
unsigned long val;
u32 reg;
if (ccu_frac_helper_is_enabled(&cm->common, &cm->frac))
return ccu_frac_helper_read_rate(&cm->common, &cm->frac);
reg = readl(cm->common.base + cm->common.reg);
val = reg >> cm->mult.shift;
val &= (1 << cm->mult.width) - 1;
parent_rate = ccu_mux_helper_apply_prediv(&cm->common, &cm->mux, -1,
parent_rate);
return parent_rate * (val + cm->mult.offset);
}
static int ccu_mult_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct ccu_mult *cm = hw_to_ccu_mult(hw);
return ccu_mux_helper_determine_rate(&cm->common, &cm->mux,
req, ccu_mult_round_rate, cm);
}
static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct ccu_mult *cm = hw_to_ccu_mult(hw);
struct _ccu_mult _cm;
unsigned long flags;
u32 reg;
if (ccu_frac_helper_has_rate(&cm->common, &cm->frac, rate)) {
ccu_frac_helper_enable(&cm->common, &cm->frac);
return ccu_frac_helper_set_rate(&cm->common, &cm->frac,
rate, cm->lock);
} else {
ccu_frac_helper_disable(&cm->common, &cm->frac);
}
parent_rate = ccu_mux_helper_apply_prediv(&cm->common, &cm->mux, -1,
parent_rate);
_cm.min = cm->mult.min;
if (cm->mult.max)
_cm.max = cm->mult.max;
else
_cm.max = (1 << cm->mult.width) + cm->mult.offset - 1;
ccu_mult_find_best(parent_rate, rate, &_cm);
spin_lock_irqsave(cm->common.lock, flags);
reg = readl(cm->common.base + cm->common.reg);
reg &= ~GENMASK(cm->mult.width + cm->mult.shift - 1, cm->mult.shift);
reg |= ((_cm.mult - cm->mult.offset) << cm->mult.shift);
writel(reg, cm->common.base + cm->common.reg);
spin_unlock_irqrestore(cm->common.lock, flags);
ccu_helper_wait_for_lock(&cm->common, cm->lock);
return 0;
}
static u8 ccu_mult_get_parent(struct clk_hw *hw)
{
struct ccu_mult *cm = hw_to_ccu_mult(hw);
return ccu_mux_helper_get_parent(&cm->common, &cm->mux);
}
static int ccu_mult_set_parent(struct clk_hw *hw, u8 index)
{
struct ccu_mult *cm = hw_to_ccu_mult(hw);
return ccu_mux_helper_set_parent(&cm->common, &cm->mux, index);
}
const struct clk_ops ccu_mult_ops = {
.disable = ccu_mult_disable,
.enable = ccu_mult_enable,
.is_enabled = ccu_mult_is_enabled,
.get_parent = ccu_mult_get_parent,
.set_parent = ccu_mult_set_parent,
.determine_rate = ccu_mult_determine_rate,
.recalc_rate = ccu_mult_recalc_rate,
.set_rate = ccu_mult_set_rate,
};
EXPORT_SYMBOL_NS_GPL(ccu_mult_ops, SUNXI_CCU);
| linux-master | drivers/clk/sunxi-ng/ccu_mult.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Maxime Ripard
* Maxime Ripard <[email protected]>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/io.h>
#include "ccu_gate.h"
#include "ccu_mux.h"
#define CCU_MUX_KEY_VALUE 0x16aa0000
static u16 ccu_mux_get_prediv(struct ccu_common *common,
struct ccu_mux_internal *cm,
int parent_index)
{
u16 prediv = 1;
u32 reg;
if (!((common->features & CCU_FEATURE_FIXED_PREDIV) ||
(common->features & CCU_FEATURE_VARIABLE_PREDIV) ||
(common->features & CCU_FEATURE_ALL_PREDIV)))
return 1;
if (common->features & CCU_FEATURE_ALL_PREDIV)
return common->prediv;
reg = readl(common->base + common->reg);
if (parent_index < 0) {
parent_index = reg >> cm->shift;
parent_index &= (1 << cm->width) - 1;
}
if (common->features & CCU_FEATURE_FIXED_PREDIV) {
int i;
for (i = 0; i < cm->n_predivs; i++)
if (parent_index == cm->fixed_predivs[i].index)
prediv = cm->fixed_predivs[i].div;
}
if (common->features & CCU_FEATURE_VARIABLE_PREDIV) {
int i;
for (i = 0; i < cm->n_var_predivs; i++)
if (parent_index == cm->var_predivs[i].index) {
u8 div;
div = reg >> cm->var_predivs[i].shift;
div &= (1 << cm->var_predivs[i].width) - 1;
prediv = div + 1;
}
}
return prediv;
}
unsigned long ccu_mux_helper_apply_prediv(struct ccu_common *common,
struct ccu_mux_internal *cm,
int parent_index,
unsigned long parent_rate)
{
return parent_rate / ccu_mux_get_prediv(common, cm, parent_index);
}
EXPORT_SYMBOL_NS_GPL(ccu_mux_helper_apply_prediv, SUNXI_CCU);
static unsigned long ccu_mux_helper_unapply_prediv(struct ccu_common *common,
struct ccu_mux_internal *cm,
int parent_index,
unsigned long parent_rate)
{
return parent_rate * ccu_mux_get_prediv(common, cm, parent_index);
}
int ccu_mux_helper_determine_rate(struct ccu_common *common,
struct ccu_mux_internal *cm,
struct clk_rate_request *req,
unsigned long (*round)(struct ccu_mux_internal *,
struct clk_hw *,
unsigned long *,
unsigned long,
void *),
void *data)
{
unsigned long best_parent_rate = 0, best_rate = 0;
struct clk_hw *best_parent, *hw = &common->hw;
unsigned int i;
if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
unsigned long adj_parent_rate;
best_parent = clk_hw_get_parent(hw);
best_parent_rate = clk_hw_get_rate(best_parent);
adj_parent_rate = ccu_mux_helper_apply_prediv(common, cm, -1,
best_parent_rate);
best_rate = round(cm, best_parent, &adj_parent_rate,
req->rate, data);
/*
* adj_parent_rate might have been modified by our clock.
* Unapply the pre-divider if there's one, and give
* the actual frequency the parent needs to run at.
*/
best_parent_rate = ccu_mux_helper_unapply_prediv(common, cm, -1,
adj_parent_rate);
goto out;
}
for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
unsigned long tmp_rate, parent_rate;
struct clk_hw *parent;
parent = clk_hw_get_parent_by_index(hw, i);
if (!parent)
continue;
parent_rate = ccu_mux_helper_apply_prediv(common, cm, i,
clk_hw_get_rate(parent));
tmp_rate = round(cm, parent, &parent_rate, req->rate, data);
/*
* parent_rate might have been modified by our clock.
* Unapply the pre-divider if there's one, and give
* the actual frequency the parent needs to run at.
*/
parent_rate = ccu_mux_helper_unapply_prediv(common, cm, i,
parent_rate);
if (tmp_rate == req->rate) {
best_parent = parent;
best_parent_rate = parent_rate;
best_rate = tmp_rate;
goto out;
}
if (ccu_is_better_rate(common, req->rate, tmp_rate, best_rate)) {
best_rate = tmp_rate;
best_parent_rate = parent_rate;
best_parent = parent;
}
}
if (best_rate == 0)
return -EINVAL;
out:
req->best_parent_hw = best_parent;
req->best_parent_rate = best_parent_rate;
req->rate = best_rate;
return 0;
}
EXPORT_SYMBOL_NS_GPL(ccu_mux_helper_determine_rate, SUNXI_CCU);
u8 ccu_mux_helper_get_parent(struct ccu_common *common,
struct ccu_mux_internal *cm)
{
u32 reg;
u8 parent;
reg = readl(common->base + common->reg);
parent = reg >> cm->shift;
parent &= (1 << cm->width) - 1;
if (cm->table) {
int num_parents = clk_hw_get_num_parents(&common->hw);
int i;
for (i = 0; i < num_parents; i++)
if (cm->table[i] == parent)
return i;
}
return parent;
}
EXPORT_SYMBOL_NS_GPL(ccu_mux_helper_get_parent, SUNXI_CCU);
int ccu_mux_helper_set_parent(struct ccu_common *common,
struct ccu_mux_internal *cm,
u8 index)
{
unsigned long flags;
u32 reg;
if (cm->table)
index = cm->table[index];
spin_lock_irqsave(common->lock, flags);
reg = readl(common->base + common->reg);
/* The key field always reads as zero. */
if (common->features & CCU_FEATURE_KEY_FIELD)
reg |= CCU_MUX_KEY_VALUE;
reg &= ~GENMASK(cm->width + cm->shift - 1, cm->shift);
writel(reg | (index << cm->shift), common->base + common->reg);
spin_unlock_irqrestore(common->lock, flags);
return 0;
}
EXPORT_SYMBOL_NS_GPL(ccu_mux_helper_set_parent, SUNXI_CCU);
static void ccu_mux_disable(struct clk_hw *hw)
{
struct ccu_mux *cm = hw_to_ccu_mux(hw);
return ccu_gate_helper_disable(&cm->common, cm->enable);
}
static int ccu_mux_enable(struct clk_hw *hw)
{
struct ccu_mux *cm = hw_to_ccu_mux(hw);
return ccu_gate_helper_enable(&cm->common, cm->enable);
}
static int ccu_mux_is_enabled(struct clk_hw *hw)
{
struct ccu_mux *cm = hw_to_ccu_mux(hw);
return ccu_gate_helper_is_enabled(&cm->common, cm->enable);
}
static u8 ccu_mux_get_parent(struct clk_hw *hw)
{
struct ccu_mux *cm = hw_to_ccu_mux(hw);
return ccu_mux_helper_get_parent(&cm->common, &cm->mux);
}
static int ccu_mux_set_parent(struct clk_hw *hw, u8 index)
{
struct ccu_mux *cm = hw_to_ccu_mux(hw);
return ccu_mux_helper_set_parent(&cm->common, &cm->mux, index);
}
static int ccu_mux_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct ccu_mux *cm = hw_to_ccu_mux(hw);
if (cm->common.features & CCU_FEATURE_CLOSEST_RATE)
return clk_mux_determine_rate_flags(hw, req, CLK_MUX_ROUND_CLOSEST);
return clk_mux_determine_rate_flags(hw, req, 0);
}
static unsigned long ccu_mux_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct ccu_mux *cm = hw_to_ccu_mux(hw);
return ccu_mux_helper_apply_prediv(&cm->common, &cm->mux, -1,
parent_rate);
}
const struct clk_ops ccu_mux_ops = {
.disable = ccu_mux_disable,
.enable = ccu_mux_enable,
.is_enabled = ccu_mux_is_enabled,
.get_parent = ccu_mux_get_parent,
.set_parent = ccu_mux_set_parent,
.determine_rate = ccu_mux_determine_rate,
.recalc_rate = ccu_mux_recalc_rate,
};
EXPORT_SYMBOL_NS_GPL(ccu_mux_ops, SUNXI_CCU);
/*
* This clock notifier is called when the frequency of the of the parent
* PLL clock is to be changed. The idea is to switch the parent to a
* stable clock, such as the main oscillator, while the PLL frequency
* stabilizes.
*/
static int ccu_mux_notifier_cb(struct notifier_block *nb,
unsigned long event, void *data)
{
struct ccu_mux_nb *mux = to_ccu_mux_nb(nb);
int ret = 0;
if (event == PRE_RATE_CHANGE) {
mux->original_index = ccu_mux_helper_get_parent(mux->common,
mux->cm);
ret = ccu_mux_helper_set_parent(mux->common, mux->cm,
mux->bypass_index);
} else if (event == POST_RATE_CHANGE) {
ret = ccu_mux_helper_set_parent(mux->common, mux->cm,
mux->original_index);
}
udelay(mux->delay_us);
return notifier_from_errno(ret);
}
int ccu_mux_notifier_register(struct clk *clk, struct ccu_mux_nb *mux_nb)
{
mux_nb->clk_nb.notifier_call = ccu_mux_notifier_cb;
return clk_notifier_register(clk, &mux_nb->clk_nb);
}
EXPORT_SYMBOL_NS_GPL(ccu_mux_notifier_register, SUNXI_CCU);
| linux-master | drivers/clk/sunxi-ng/ccu_mux.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016 Maxime Ripard. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu_mult.h"
#include "ccu_nk.h"
#include "ccu_nkm.h"
#include "ccu_nkmp.h"
#include "ccu_nm.h"
#include "ccu_phase.h"
#include "ccu_sdm.h"
#include "ccu-sun8i-h3.h"
static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
"osc24M", 0x000,
8, 5, /* N */
4, 2, /* K */
0, 2, /* M */
16, 2, /* P */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
/*
* The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
* the base (2x, 4x and 8x), and one variable divider (the one true
* pll audio).
*
* With sigma-delta modulation for fractional-N on the audio PLL,
* we have to use specific dividers. This means the variable divider
* can no longer be used, as the audio codec requests the exact clock
* rates we support through this mechanism. So we now hard code the
* variable divider to 1. This means the clock rates will no longer
* match the clock names.
*/
#define SUN8I_H3_PLL_AUDIO_REG 0x008
static struct ccu_sdm_setting pll_audio_sdm_table[] = {
{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
};
static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
"osc24M", 0x008,
8, 7, /* N */
0, 5, /* M */
pll_audio_sdm_table, BIT(24),
0x284, BIT(31),
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video_clk, "pll-video",
"osc24M", 0x0010,
192000000, /* Minimum rate */
912000000, /* Maximum rate */
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
"osc24M", 0x0018,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
"osc24M", 0x020,
8, 5, /* N */
4, 2, /* K */
0, 2, /* M */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
"osc24M", 0x028,
8, 5, /* N */
4, 2, /* K */
BIT(31), /* gate */
BIT(28), /* lock */
2, /* post-div */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
"osc24M", 0x0038,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
"osc24M", 0x044,
8, 5, /* N */
4, 2, /* K */
BIT(31), /* gate */
BIT(28), /* lock */
2, /* post-div */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
"osc24M", 0x0048,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static const char * const cpux_parents[] = { "osc32k", "osc24M",
"pll-cpux" , "pll-cpux" };
static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
static const char * const ahb1_parents[] = { "osc32k", "osc24M",
"axi" , "pll-periph0" };
static const struct ccu_mux_var_prediv ahb1_predivs[] = {
{ .index = 3, .shift = 6, .width = 2 },
};
static struct ccu_div ahb1_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = {
.shift = 12,
.width = 2,
.var_predivs = ahb1_predivs,
.n_var_predivs = ARRAY_SIZE(ahb1_predivs),
},
.common = {
.reg = 0x054,
.features = CCU_FEATURE_VARIABLE_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("ahb1",
ahb1_parents,
&ccu_div_ops,
0),
},
};
static struct clk_div_table apb1_div_table[] = {
{ .val = 0, .div = 2 },
{ .val = 1, .div = 2 },
{ .val = 2, .div = 4 },
{ .val = 3, .div = 8 },
{ /* Sentinel */ },
};
static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
0x054, 8, 2, apb1_div_table, 0);
static const char * const apb2_parents[] = { "osc32k", "osc24M",
"pll-periph0" , "pll-periph0" };
static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
0, 5, /* M */
16, 2, /* P */
24, 2, /* mux */
0);
static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" };
static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
{ .index = 1, .div = 2 },
};
static struct ccu_mux ahb2_clk = {
.mux = {
.shift = 0,
.width = 1,
.fixed_predivs = ahb2_fixed_predivs,
.n_predivs = ARRAY_SIZE(ahb2_fixed_predivs),
},
.common = {
.reg = 0x05c,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("ahb2",
ahb2_parents,
&ccu_mux_ops,
0),
},
};
static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
0x060, BIT(5), 0);
static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
0x060, BIT(6), 0);
static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
0x060, BIT(8), 0);
static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
0x060, BIT(9), 0);
static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
0x060, BIT(10), 0);
static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
0x060, BIT(13), 0);
static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
0x060, BIT(14), 0);
static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
0x060, BIT(17), 0);
static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
0x060, BIT(18), 0);
static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
0x060, BIT(19), 0);
static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
0x060, BIT(20), 0);
static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
0x060, BIT(21), 0);
static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
0x060, BIT(23), 0);
static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
0x060, BIT(24), 0);
static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",
0x060, BIT(25), 0);
static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb2",
0x060, BIT(26), 0);
static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb2",
0x060, BIT(27), 0);
static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
0x060, BIT(28), 0);
static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2",
0x060, BIT(29), 0);
static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb2",
0x060, BIT(30), 0);
static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb2",
0x060, BIT(31), 0);
static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
0x064, BIT(0), 0);
static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
0x064, BIT(3), 0);
static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1",
0x064, BIT(4), 0);
static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
0x064, BIT(5), 0);
static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
0x064, BIT(8), 0);
static SUNXI_CCU_GATE(bus_tve_clk, "bus-tve", "ahb1",
0x064, BIT(9), 0);
static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",
0x064, BIT(11), 0);
static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
0x064, BIT(12), 0);
static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
0x064, BIT(20), 0);
static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
0x064, BIT(21), 0);
static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
0x064, BIT(22), 0);
static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
0x068, BIT(0), 0);
static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
0x068, BIT(1), 0);
static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
0x068, BIT(5), 0);
static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
0x068, BIT(8), 0);
static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
0x068, BIT(12), 0);
static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
0x068, BIT(13), 0);
static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
0x068, BIT(14), 0);
static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
0x06c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
0x06c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
0x06c, BIT(2), 0);
static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
0x06c, BIT(16), 0);
static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
0x06c, BIT(17), 0);
static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
0x06c, BIT(18), 0);
static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
0x06c, BIT(19), 0);
static SUNXI_CCU_GATE(bus_scr0_clk, "bus-scr0", "apb2",
0x06c, BIT(20), 0);
static SUNXI_CCU_GATE(bus_scr1_clk, "bus-scr1", "apb2",
0x06c, BIT(21), 0);
static SUNXI_CCU_GATE(bus_ephy_clk, "bus-ephy", "ahb1",
0x070, BIT(0), 0);
static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
0x070, BIT(7), 0);
static struct clk_div_table ths_div_table[] = {
{ .val = 0, .div = 1 },
{ .val = 1, .div = 2 },
{ .val = 2, .div = 4 },
{ .val = 3, .div = 6 },
{ /* Sentinel */ },
};
static SUNXI_CCU_DIV_TABLE_WITH_GATE(ths_clk, "ths", "osc24M",
0x074, 0, 2, ths_div_table, BIT(31), 0);
static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
"pll-periph1" };
static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
0x088, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
0x088, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
0x08c, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
0x08c, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
0x090, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
0x090, 8, 3, 0);
static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mod0_default_parents, 0x09c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
"pll-audio-2x", "pll-audio" };
static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
0x0cc, BIT(8), 0);
static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
0x0cc, BIT(9), 0);
static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
0x0cc, BIT(10), 0);
static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc24M",
0x0cc, BIT(11), 0);
static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
0x0cc, BIT(16), 0);
static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc24M",
0x0cc, BIT(17), 0);
static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M",
0x0cc, BIT(18), 0);
static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc24M",
0x0cc, BIT(19), 0);
/* H3 has broken MDFS hardware, so the mux/divider cannot be changed. */
static CLK_FIXED_FACTOR_HW(h3_dram_clk, "dram",
&pll_ddr_clk.common.hw,
1, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
static const char * const h5_dram_parents[] = { "pll-ddr", "pll-periph0-2x" };
static SUNXI_CCU_M_WITH_MUX(h5_dram_clk, "dram", h5_dram_parents,
0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
0x100, BIT(0), 0);
static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
0x100, BIT(1), 0);
static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
0x100, BIT(2), 0);
static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
0x100, BIT(3), 0);
static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
0x104, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
static const char * const tcon_parents[] = { "pll-video" };
static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
0x118, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
static const char * const tve_parents[] = { "pll-de", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(tve_clk, "tve", tve_parents,
0x120, 0, 4, 24, 3, BIT(31), 0);
static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
0x124, 0, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
0x130, BIT(31), 0);
static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
0x134, 16, 4, 24, 3, BIT(31), 0);
static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
0x134, 0, 5, 8, 3, BIT(15), 0);
static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
0x140, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
0x144, BIT(31), 0);
static const char * const hdmi_parents[] = { "pll-video" };
static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
0x150, 0, 4, 24, 2, BIT(31),
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
0x154, BIT(31), 0);
static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", "pll-ddr" };
static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
static struct ccu_common *sun8i_h3_ccu_clks[] = {
&pll_cpux_clk.common,
&pll_audio_base_clk.common,
&pll_video_clk.common,
&pll_ve_clk.common,
&pll_ddr_clk.common,
&pll_periph0_clk.common,
&pll_gpu_clk.common,
&pll_periph1_clk.common,
&pll_de_clk.common,
&cpux_clk.common,
&axi_clk.common,
&ahb1_clk.common,
&apb1_clk.common,
&apb2_clk.common,
&ahb2_clk.common,
&bus_ce_clk.common,
&bus_dma_clk.common,
&bus_mmc0_clk.common,
&bus_mmc1_clk.common,
&bus_mmc2_clk.common,
&bus_nand_clk.common,
&bus_dram_clk.common,
&bus_emac_clk.common,
&bus_ts_clk.common,
&bus_hstimer_clk.common,
&bus_spi0_clk.common,
&bus_spi1_clk.common,
&bus_otg_clk.common,
&bus_ehci0_clk.common,
&bus_ehci1_clk.common,
&bus_ehci2_clk.common,
&bus_ehci3_clk.common,
&bus_ohci0_clk.common,
&bus_ohci1_clk.common,
&bus_ohci2_clk.common,
&bus_ohci3_clk.common,
&bus_ve_clk.common,
&bus_tcon0_clk.common,
&bus_tcon1_clk.common,
&bus_deinterlace_clk.common,
&bus_csi_clk.common,
&bus_tve_clk.common,
&bus_hdmi_clk.common,
&bus_de_clk.common,
&bus_gpu_clk.common,
&bus_msgbox_clk.common,
&bus_spinlock_clk.common,
&bus_codec_clk.common,
&bus_spdif_clk.common,
&bus_pio_clk.common,
&bus_ths_clk.common,
&bus_i2s0_clk.common,
&bus_i2s1_clk.common,
&bus_i2s2_clk.common,
&bus_i2c0_clk.common,
&bus_i2c1_clk.common,
&bus_i2c2_clk.common,
&bus_uart0_clk.common,
&bus_uart1_clk.common,
&bus_uart2_clk.common,
&bus_uart3_clk.common,
&bus_scr0_clk.common,
&bus_scr1_clk.common,
&bus_ephy_clk.common,
&bus_dbg_clk.common,
&ths_clk.common,
&nand_clk.common,
&mmc0_clk.common,
&mmc0_sample_clk.common,
&mmc0_output_clk.common,
&mmc1_clk.common,
&mmc1_sample_clk.common,
&mmc1_output_clk.common,
&mmc2_clk.common,
&mmc2_sample_clk.common,
&mmc2_output_clk.common,
&ts_clk.common,
&ce_clk.common,
&spi0_clk.common,
&spi1_clk.common,
&i2s0_clk.common,
&i2s1_clk.common,
&i2s2_clk.common,
&spdif_clk.common,
&usb_phy0_clk.common,
&usb_phy1_clk.common,
&usb_phy2_clk.common,
&usb_phy3_clk.common,
&usb_ohci0_clk.common,
&usb_ohci1_clk.common,
&usb_ohci2_clk.common,
&usb_ohci3_clk.common,
&h5_dram_clk.common,
&dram_ve_clk.common,
&dram_csi_clk.common,
&dram_deinterlace_clk.common,
&dram_ts_clk.common,
&de_clk.common,
&tcon_clk.common,
&tve_clk.common,
&deinterlace_clk.common,
&csi_misc_clk.common,
&csi_sclk_clk.common,
&csi_mclk_clk.common,
&ve_clk.common,
&ac_dig_clk.common,
&avs_clk.common,
&hdmi_clk.common,
&hdmi_ddc_clk.common,
&mbus_clk.common,
&gpu_clk.common,
};
static const struct clk_hw *clk_parent_pll_audio[] = {
&pll_audio_base_clk.common.hw
};
/* We hardcode the divider to 1 for now */
static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
clk_parent_pll_audio,
1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
clk_parent_pll_audio,
2, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
clk_parent_pll_audio,
1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
clk_parent_pll_audio,
1, 2, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
&pll_periph0_clk.common.hw,
1, 2, 0);
static struct clk_hw_onecell_data sun8i_h3_hw_clks = {
.hws = {
[CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
[CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
[CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
[CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
[CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
[CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
[CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
[CLK_PLL_DE] = &pll_de_clk.common.hw,
[CLK_CPUX] = &cpux_clk.common.hw,
[CLK_AXI] = &axi_clk.common.hw,
[CLK_AHB1] = &ahb1_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_APB2] = &apb2_clk.common.hw,
[CLK_AHB2] = &ahb2_clk.common.hw,
[CLK_BUS_CE] = &bus_ce_clk.common.hw,
[CLK_BUS_DMA] = &bus_dma_clk.common.hw,
[CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
[CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
[CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
[CLK_BUS_NAND] = &bus_nand_clk.common.hw,
[CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
[CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
[CLK_BUS_TS] = &bus_ts_clk.common.hw,
[CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
[CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
[CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
[CLK_BUS_OTG] = &bus_otg_clk.common.hw,
[CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
[CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
[CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw,
[CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw,
[CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
[CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
[CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw,
[CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw,
[CLK_BUS_VE] = &bus_ve_clk.common.hw,
[CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
[CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
[CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
[CLK_BUS_CSI] = &bus_csi_clk.common.hw,
[CLK_BUS_TVE] = &bus_tve_clk.common.hw,
[CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
[CLK_BUS_DE] = &bus_de_clk.common.hw,
[CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
[CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
[CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
[CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
[CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
[CLK_BUS_PIO] = &bus_pio_clk.common.hw,
[CLK_BUS_THS] = &bus_ths_clk.common.hw,
[CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
[CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
[CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
[CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
[CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
[CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
[CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
[CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
[CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
[CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
[CLK_BUS_SCR0] = &bus_scr0_clk.common.hw,
[CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
[CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
[CLK_THS] = &ths_clk.common.hw,
[CLK_NAND] = &nand_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
[CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
[CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
[CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
[CLK_TS] = &ts_clk.common.hw,
[CLK_CE] = &ce_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_I2S0] = &i2s0_clk.common.hw,
[CLK_I2S1] = &i2s1_clk.common.hw,
[CLK_I2S2] = &i2s2_clk.common.hw,
[CLK_SPDIF] = &spdif_clk.common.hw,
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
[CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
[CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
[CLK_USB_PHY3] = &usb_phy3_clk.common.hw,
[CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
[CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
[CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
[CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw,
[CLK_DRAM] = &h3_dram_clk.hw,
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
[CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
[CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
[CLK_DRAM_TS] = &dram_ts_clk.common.hw,
[CLK_DE] = &de_clk.common.hw,
[CLK_TCON0] = &tcon_clk.common.hw,
[CLK_TVE] = &tve_clk.common.hw,
[CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
[CLK_CSI_MISC] = &csi_misc_clk.common.hw,
[CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
[CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_AC_DIG] = &ac_dig_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_HDMI] = &hdmi_clk.common.hw,
[CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
[CLK_MBUS] = &mbus_clk.common.hw,
[CLK_GPU] = &gpu_clk.common.hw,
},
.num = CLK_NUMBER_H3,
};
static struct clk_hw_onecell_data sun50i_h5_hw_clks = {
.hws = {
[CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
[CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
[CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
[CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
[CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
[CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
[CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
[CLK_PLL_DE] = &pll_de_clk.common.hw,
[CLK_CPUX] = &cpux_clk.common.hw,
[CLK_AXI] = &axi_clk.common.hw,
[CLK_AHB1] = &ahb1_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_APB2] = &apb2_clk.common.hw,
[CLK_AHB2] = &ahb2_clk.common.hw,
[CLK_BUS_CE] = &bus_ce_clk.common.hw,
[CLK_BUS_DMA] = &bus_dma_clk.common.hw,
[CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
[CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
[CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
[CLK_BUS_NAND] = &bus_nand_clk.common.hw,
[CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
[CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
[CLK_BUS_TS] = &bus_ts_clk.common.hw,
[CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
[CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
[CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
[CLK_BUS_OTG] = &bus_otg_clk.common.hw,
[CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
[CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
[CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw,
[CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw,
[CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
[CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
[CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw,
[CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw,
[CLK_BUS_VE] = &bus_ve_clk.common.hw,
[CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
[CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
[CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
[CLK_BUS_CSI] = &bus_csi_clk.common.hw,
[CLK_BUS_TVE] = &bus_tve_clk.common.hw,
[CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
[CLK_BUS_DE] = &bus_de_clk.common.hw,
[CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
[CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
[CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
[CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
[CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
[CLK_BUS_PIO] = &bus_pio_clk.common.hw,
[CLK_BUS_THS] = &bus_ths_clk.common.hw,
[CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
[CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
[CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
[CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
[CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
[CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
[CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
[CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
[CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
[CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
[CLK_BUS_SCR0] = &bus_scr0_clk.common.hw,
[CLK_BUS_SCR1] = &bus_scr1_clk.common.hw,
[CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
[CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
[CLK_THS] = &ths_clk.common.hw,
[CLK_NAND] = &nand_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_TS] = &ts_clk.common.hw,
[CLK_CE] = &ce_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_I2S0] = &i2s0_clk.common.hw,
[CLK_I2S1] = &i2s1_clk.common.hw,
[CLK_I2S2] = &i2s2_clk.common.hw,
[CLK_SPDIF] = &spdif_clk.common.hw,
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
[CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
[CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
[CLK_USB_PHY3] = &usb_phy3_clk.common.hw,
[CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
[CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
[CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
[CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw,
[CLK_DRAM] = &h5_dram_clk.common.hw,
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
[CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
[CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
[CLK_DRAM_TS] = &dram_ts_clk.common.hw,
[CLK_DE] = &de_clk.common.hw,
[CLK_TCON0] = &tcon_clk.common.hw,
[CLK_TVE] = &tve_clk.common.hw,
[CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
[CLK_CSI_MISC] = &csi_misc_clk.common.hw,
[CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
[CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_AC_DIG] = &ac_dig_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_HDMI] = &hdmi_clk.common.hw,
[CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
[CLK_MBUS] = &mbus_clk.common.hw,
[CLK_GPU] = &gpu_clk.common.hw,
},
.num = CLK_NUMBER_H5,
};
static struct ccu_reset_map sun8i_h3_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_PHY2] = { 0x0cc, BIT(2) },
[RST_USB_PHY3] = { 0x0cc, BIT(3) },
[RST_MBUS] = { 0x0fc, BIT(31) },
[RST_BUS_CE] = { 0x2c0, BIT(5) },
[RST_BUS_DMA] = { 0x2c0, BIT(6) },
[RST_BUS_MMC0] = { 0x2c0, BIT(8) },
[RST_BUS_MMC1] = { 0x2c0, BIT(9) },
[RST_BUS_MMC2] = { 0x2c0, BIT(10) },
[RST_BUS_NAND] = { 0x2c0, BIT(13) },
[RST_BUS_DRAM] = { 0x2c0, BIT(14) },
[RST_BUS_EMAC] = { 0x2c0, BIT(17) },
[RST_BUS_TS] = { 0x2c0, BIT(18) },
[RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
[RST_BUS_SPI0] = { 0x2c0, BIT(20) },
[RST_BUS_SPI1] = { 0x2c0, BIT(21) },
[RST_BUS_OTG] = { 0x2c0, BIT(23) },
[RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
[RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
[RST_BUS_EHCI2] = { 0x2c0, BIT(26) },
[RST_BUS_EHCI3] = { 0x2c0, BIT(27) },
[RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
[RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
[RST_BUS_OHCI2] = { 0x2c0, BIT(30) },
[RST_BUS_OHCI3] = { 0x2c0, BIT(31) },
[RST_BUS_VE] = { 0x2c4, BIT(0) },
[RST_BUS_TCON0] = { 0x2c4, BIT(3) },
[RST_BUS_TCON1] = { 0x2c4, BIT(4) },
[RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
[RST_BUS_CSI] = { 0x2c4, BIT(8) },
[RST_BUS_TVE] = { 0x2c4, BIT(9) },
[RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
[RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
[RST_BUS_DE] = { 0x2c4, BIT(12) },
[RST_BUS_GPU] = { 0x2c4, BIT(20) },
[RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
[RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
[RST_BUS_DBG] = { 0x2c4, BIT(31) },
[RST_BUS_EPHY] = { 0x2c8, BIT(2) },
[RST_BUS_CODEC] = { 0x2d0, BIT(0) },
[RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
[RST_BUS_THS] = { 0x2d0, BIT(8) },
[RST_BUS_I2S0] = { 0x2d0, BIT(12) },
[RST_BUS_I2S1] = { 0x2d0, BIT(13) },
[RST_BUS_I2S2] = { 0x2d0, BIT(14) },
[RST_BUS_I2C0] = { 0x2d8, BIT(0) },
[RST_BUS_I2C1] = { 0x2d8, BIT(1) },
[RST_BUS_I2C2] = { 0x2d8, BIT(2) },
[RST_BUS_UART0] = { 0x2d8, BIT(16) },
[RST_BUS_UART1] = { 0x2d8, BIT(17) },
[RST_BUS_UART2] = { 0x2d8, BIT(18) },
[RST_BUS_UART3] = { 0x2d8, BIT(19) },
[RST_BUS_SCR0] = { 0x2d8, BIT(20) },
};
static struct ccu_reset_map sun50i_h5_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_PHY2] = { 0x0cc, BIT(2) },
[RST_USB_PHY3] = { 0x0cc, BIT(3) },
[RST_MBUS] = { 0x0fc, BIT(31) },
[RST_BUS_CE] = { 0x2c0, BIT(5) },
[RST_BUS_DMA] = { 0x2c0, BIT(6) },
[RST_BUS_MMC0] = { 0x2c0, BIT(8) },
[RST_BUS_MMC1] = { 0x2c0, BIT(9) },
[RST_BUS_MMC2] = { 0x2c0, BIT(10) },
[RST_BUS_NAND] = { 0x2c0, BIT(13) },
[RST_BUS_DRAM] = { 0x2c0, BIT(14) },
[RST_BUS_EMAC] = { 0x2c0, BIT(17) },
[RST_BUS_TS] = { 0x2c0, BIT(18) },
[RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
[RST_BUS_SPI0] = { 0x2c0, BIT(20) },
[RST_BUS_SPI1] = { 0x2c0, BIT(21) },
[RST_BUS_OTG] = { 0x2c0, BIT(23) },
[RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
[RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
[RST_BUS_EHCI2] = { 0x2c0, BIT(26) },
[RST_BUS_EHCI3] = { 0x2c0, BIT(27) },
[RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
[RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
[RST_BUS_OHCI2] = { 0x2c0, BIT(30) },
[RST_BUS_OHCI3] = { 0x2c0, BIT(31) },
[RST_BUS_VE] = { 0x2c4, BIT(0) },
[RST_BUS_TCON0] = { 0x2c4, BIT(3) },
[RST_BUS_TCON1] = { 0x2c4, BIT(4) },
[RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
[RST_BUS_CSI] = { 0x2c4, BIT(8) },
[RST_BUS_TVE] = { 0x2c4, BIT(9) },
[RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
[RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
[RST_BUS_DE] = { 0x2c4, BIT(12) },
[RST_BUS_GPU] = { 0x2c4, BIT(20) },
[RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
[RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
[RST_BUS_DBG] = { 0x2c4, BIT(31) },
[RST_BUS_EPHY] = { 0x2c8, BIT(2) },
[RST_BUS_CODEC] = { 0x2d0, BIT(0) },
[RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
[RST_BUS_THS] = { 0x2d0, BIT(8) },
[RST_BUS_I2S0] = { 0x2d0, BIT(12) },
[RST_BUS_I2S1] = { 0x2d0, BIT(13) },
[RST_BUS_I2S2] = { 0x2d0, BIT(14) },
[RST_BUS_I2C0] = { 0x2d8, BIT(0) },
[RST_BUS_I2C1] = { 0x2d8, BIT(1) },
[RST_BUS_I2C2] = { 0x2d8, BIT(2) },
[RST_BUS_UART0] = { 0x2d8, BIT(16) },
[RST_BUS_UART1] = { 0x2d8, BIT(17) },
[RST_BUS_UART2] = { 0x2d8, BIT(18) },
[RST_BUS_UART3] = { 0x2d8, BIT(19) },
[RST_BUS_SCR0] = { 0x2d8, BIT(20) },
[RST_BUS_SCR1] = { 0x2d8, BIT(20) },
};
static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {
.ccu_clks = sun8i_h3_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_h3_ccu_clks),
.hw_clks = &sun8i_h3_hw_clks,
.resets = sun8i_h3_ccu_resets,
.num_resets = ARRAY_SIZE(sun8i_h3_ccu_resets),
};
static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
.ccu_clks = sun8i_h3_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_h3_ccu_clks),
.hw_clks = &sun50i_h5_hw_clks,
.resets = sun50i_h5_ccu_resets,
.num_resets = ARRAY_SIZE(sun50i_h5_ccu_resets),
};
static struct ccu_pll_nb sun8i_h3_pll_cpu_nb = {
.common = &pll_cpux_clk.common,
/* copy from pll_cpux_clk */
.enable = BIT(31),
.lock = BIT(28),
};
static struct ccu_mux_nb sun8i_h3_cpu_nb = {
.common = &cpux_clk.common,
.cm = &cpux_clk.mux,
.delay_us = 1, /* > 8 clock cycles at 24 MHz */
.bypass_index = 1, /* index of 24 MHz oscillator */
};
static int sun8i_h3_ccu_probe(struct platform_device *pdev)
{
const struct sunxi_ccu_desc *desc;
void __iomem *reg;
int ret;
u32 val;
desc = of_device_get_match_data(&pdev->dev);
if (!desc)
return -EINVAL;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
/* Force the PLL-Audio-1x divider to 1 */
val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);
val &= ~GENMASK(19, 16);
writel(val | (0 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
ret = devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
if (ret)
return ret;
/* Gate then ungate PLL CPU after any rate changes */
ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb);
/* Reparent CPU during PLL CPU rate changes */
ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
&sun8i_h3_cpu_nb);
return 0;
}
static const struct of_device_id sun8i_h3_ccu_ids[] = {
{
.compatible = "allwinner,sun8i-h3-ccu",
.data = &sun8i_h3_ccu_desc,
},
{
.compatible = "allwinner,sun50i-h5-ccu",
.data = &sun50i_h5_ccu_desc,
},
{ }
};
static struct platform_driver sun8i_h3_ccu_driver = {
.probe = sun8i_h3_ccu_probe,
.driver = {
.name = "sun8i-h3-ccu",
.suppress_bind_attrs = true,
.of_match_table = sun8i_h3_ccu_ids,
},
};
module_platform_driver(sun8i_h3_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun8i-h3.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Arm Ltd.
* Based on the H6 CCU driver, which is:
* Copyright (c) 2017 Icenowy Zheng <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu_mult.h"
#include "ccu_nk.h"
#include "ccu_nkm.h"
#include "ccu_nkmp.h"
#include "ccu_nm.h"
#include "ccu-sun50i-h616.h"
/*
* The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
* P should only be used for output frequencies lower than 288 MHz.
*
* For now we can just model it as a multiplier clock, and force P to /1.
*
* The M factor is present in the register's description, but not in the
* frequency formula, and it's documented as "M is only used for backdoor
* testing", so it's not modelled and then force to 0.
*/
#define SUN50I_H616_PLL_CPUX_REG 0x000
static struct ccu_mult pll_cpux_clk = {
.enable = BIT(31),
.lock = BIT(28),
.mult = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.common = {
.reg = 0x000,
.hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
&ccu_mult_ops,
CLK_SET_RATE_UNGATE),
},
};
/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
#define SUN50I_H616_PLL_DDR0_REG 0x010
static struct ccu_nkmp pll_ddr0_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
.common = {
.reg = 0x010,
.hw.init = CLK_HW_INIT("pll-ddr0", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
#define SUN50I_H616_PLL_DDR1_REG 0x018
static struct ccu_nkmp pll_ddr1_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
.common = {
.reg = 0x018,
.hw.init = CLK_HW_INIT("pll-ddr1", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
#define SUN50I_H616_PLL_PERIPH0_REG 0x020
static struct ccu_nkmp pll_periph0_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
.fixed_post_div = 2,
.common = {
.reg = 0x020,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
#define SUN50I_H616_PLL_PERIPH1_REG 0x028
static struct ccu_nkmp pll_periph1_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
.fixed_post_div = 2,
.common = {
.reg = 0x028,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
#define SUN50I_H616_PLL_GPU_REG 0x030
static struct ccu_nkmp pll_gpu_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
.common = {
.reg = 0x030,
.hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
/*
* For Video PLLs, the output divider is described as "used for testing"
* in the user manual. So it's not modelled and forced to 0.
*/
#define SUN50I_H616_PLL_VIDEO0_REG 0x040
static struct ccu_nm pll_video0_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.fixed_post_div = 4,
.min_rate = 288000000,
.max_rate = 2400000000UL,
.common = {
.reg = 0x040,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-video0", "osc24M",
&ccu_nm_ops,
CLK_SET_RATE_UNGATE),
},
};
#define SUN50I_H616_PLL_VIDEO1_REG 0x048
static struct ccu_nm pll_video1_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.fixed_post_div = 4,
.min_rate = 288000000,
.max_rate = 2400000000UL,
.common = {
.reg = 0x048,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-video1", "osc24M",
&ccu_nm_ops,
CLK_SET_RATE_UNGATE),
},
};
#define SUN50I_H616_PLL_VIDEO2_REG 0x050
static struct ccu_nm pll_video2_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.fixed_post_div = 4,
.min_rate = 288000000,
.max_rate = 2400000000UL,
.common = {
.reg = 0x050,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-video2", "osc24M",
&ccu_nm_ops,
CLK_SET_RATE_UNGATE),
},
};
#define SUN50I_H616_PLL_VE_REG 0x058
static struct ccu_nkmp pll_ve_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
.common = {
.reg = 0x058,
.hw.init = CLK_HW_INIT("pll-ve", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
#define SUN50I_H616_PLL_DE_REG 0x060
static struct ccu_nkmp pll_de_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
.common = {
.reg = 0x060,
.hw.init = CLK_HW_INIT("pll-de", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
/*
* TODO: Determine SDM settings for the audio PLL. The manual suggests
* PLL_FACTOR_N=16, PLL_POST_DIV_P=2, OUTPUT_DIV=2, pattern=0xe000c49b
* for 24.576 MHz, and PLL_FACTOR_N=22, PLL_POST_DIV_P=3, OUTPUT_DIV=2,
* pattern=0xe001288c for 22.5792 MHz.
* This clashes with our fixed PLL_POST_DIV_P.
*/
#define SUN50I_H616_PLL_AUDIO_REG 0x078
static struct ccu_nm pll_audio_hs_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.common = {
.reg = 0x078,
.hw.init = CLK_HW_INIT("pll-audio-hs", "osc24M",
&ccu_nm_ops,
CLK_SET_RATE_UNGATE),
},
};
static const char * const cpux_parents[] = { "osc24M", "osc32k",
"iosc", "pll-cpux", "pll-periph0" };
static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x500, 0, 2, 0);
static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0);
static const char * const psi_ahb1_ahb2_parents[] = { "osc24M", "osc32k",
"iosc", "pll-periph0" };
static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
psi_ahb1_ahb2_parents,
0x510,
0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
static const char * const ahb3_apb1_apb2_parents[] = { "osc24M", "osc32k",
"psi-ahb1-ahb2",
"pll-periph0" };
static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c,
0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520,
0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
"pll-ddr0", "pll-ddr1" };
static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x540,
0, 3, /* M */
24, 2, /* mux */
BIT(31), /* gate */
CLK_IS_CRITICAL);
static const char * const de_parents[] = { "pll-de", "pll-periph0-2x" };
static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 0x600,
0, 4, /* M */
24, 1, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
0x60c, BIT(0), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace",
de_parents,
0x620,
0, 4, /* M */
24, 1, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2",
0x62c, BIT(0), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(g2d_clk, "g2d", de_parents, 0x630,
0, 4, /* M */
24, 1, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(bus_g2d_clk, "bus-g2d", "psi-ahb1-ahb2",
0x63c, BIT(0), 0);
static const char * const gpu0_parents[] = { "pll-gpu", "gpu1" };
static SUNXI_CCU_M_WITH_MUX_GATE(gpu0_clk, "gpu0", gpu0_parents, 0x670,
0, 2, /* M */
24, 1, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(gpu1_clk, "gpu1", "pll-periph0-2x", 0x674,
0, 2, /* M */
BIT(31),/* gate */
0);
static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
0x67c, BIT(0), 0);
static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x" };
static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
0, 4, /* M */
8, 2, /* N */
24, 1, /* mux */
BIT(31),/* gate */
0);
static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
0x68c, BIT(0), 0);
static const char * const ve_parents[] = { "pll-ve" };
static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
0, 3, /* M */
24, 1, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
0x69c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
0x70c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2",
0x73c, BIT(0), 0);
static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x740, BIT(31), 0);
static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2",
0x78c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2",
0x79c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0);
static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0);
static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
static struct ccu_div dram_clk = {
.div = _SUNXI_CCU_DIV(0, 2),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0x800,
.hw.init = CLK_HW_INIT_PARENTS("dram",
dram_parents,
&ccu_div_ops,
CLK_IS_CRITICAL),
},
};
static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus",
0x804, BIT(0), 0);
static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus",
0x804, BIT(1), 0);
static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus",
0x804, BIT(2), 0);
static SUNXI_CCU_GATE(mbus_ts_clk, "mbus-ts", "mbus",
0x804, BIT(3), 0);
static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus",
0x804, BIT(5), 0);
static SUNXI_CCU_GATE(mbus_g2d_clk, "mbus-g2d", "mbus",
0x804, BIT(10), 0);
static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2",
0x80c, BIT(0), CLK_IS_CRITICAL);
static const char * const nand_spi_parents[] = { "osc24M", "pll-periph0",
"pll-periph1", "pll-periph0-2x",
"pll-periph1-2x" };
static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", nand_spi_parents, 0x810,
0, 4, /* M */
8, 2, /* N */
24, 3, /* mux */
BIT(31),/* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", nand_spi_parents, 0x814,
0, 4, /* M */
8, 2, /* N */
24, 3, /* mux */
BIT(31),/* gate */
0);
static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0);
static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x",
"pll-periph1-2x" };
static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830,
0, 4, /* M */
8, 2, /* N */
24, 2, /* mux */
BIT(31), /* gate */
2, /* post-div */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
0, 4, /* M */
8, 2, /* N */
24, 2, /* mux */
BIT(31), /* gate */
2, /* post-div */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838,
0, 4, /* M */
8, 2, /* N */
24, 2, /* mux */
BIT(31), /* gate */
2, /* post-div */
0);
static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0);
static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0);
static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0);
static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 0x90c, BIT(4), 0);
static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb2", 0x90c, BIT(5), 0);
static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0);
static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0);
static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb2", 0x91c, BIT(4), 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", nand_spi_parents, 0x940,
0, 4, /* M */
8, 2, /* N */
24, 3, /* mux */
BIT(31),/* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", nand_spi_parents, 0x944,
0, 4, /* M */
8, 2, /* N */
24, 3, /* mux */
BIT(31),/* gate */
0);
static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0);
static SUNXI_CCU_GATE(emac_25m_clk, "emac-25m", "ahb3", 0x970,
BIT(31) | BIT(30), 0);
static SUNXI_CCU_GATE(bus_emac0_clk, "bus-emac0", "ahb3", 0x97c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_emac1_clk, "bus-emac1", "ahb3", 0x97c, BIT(1), 0);
static const char * const ts_parents[] = { "osc24M", "pll-periph0" };
static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x9b0,
0, 4, /* M */
8, 2, /* N */
24, 1, /* mux */
BIT(31),/* gate */
0);
static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0);
static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
static const char * const audio_parents[] = { "pll-audio-1x", "pll-audio-2x",
"pll-audio-4x", "pll-audio-hs" };
static struct ccu_div spdif_clk = {
.enable = BIT(31),
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0xa20,
.hw.init = CLK_HW_INIT_PARENTS("spdif",
audio_parents,
&ccu_div_ops,
0),
},
};
static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0);
static struct ccu_div dmic_clk = {
.enable = BIT(31),
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0xa40,
.hw.init = CLK_HW_INIT_PARENTS("dmic",
audio_parents,
&ccu_div_ops,
0),
},
};
static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_1x_clk, "audio-codec-1x",
audio_parents, 0xa50,
0, 4, /* M */
24, 2, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_4x_clk, "audio-codec-4x",
audio_parents, 0xa54,
0, 4, /* M */
24, 2, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(bus_audio_codec_clk, "bus-audio-codec", "apb1", 0xa5c,
BIT(0), 0);
static struct ccu_div audio_hub_clk = {
.enable = BIT(31),
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0xa60,
.hw.init = CLK_HW_INIT_PARENTS("audio-hub",
audio_parents,
&ccu_div_ops,
0),
},
};
static SUNXI_CCU_GATE(bus_audio_hub_clk, "bus-audio-hub", "apb1", 0xa6c, BIT(0), 0);
/*
* There are OHCI 12M clock source selection bits for the four USB 2.0 ports.
* We will force them to 0 (12M divided from 48M).
*/
#define SUN50I_H616_USB0_CLK_REG 0xa70
#define SUN50I_H616_USB1_CLK_REG 0xa74
#define SUN50I_H616_USB2_CLK_REG 0xa78
#define SUN50I_H616_USB3_CLK_REG 0xa7c
static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0);
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0xa70, BIT(29), 0);
static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M", 0xa74, BIT(31), 0);
static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 0xa74, BIT(29), 0);
static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc12M", 0xa78, BIT(31), 0);
static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M", 0xa78, BIT(29), 0);
static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc12M", 0xa7c, BIT(31), 0);
static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc24M", 0xa7c, BIT(29), 0);
static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb3", 0xa8c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb3", 0xa8c, BIT(2), 0);
static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb3", 0xa8c, BIT(3), 0);
static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0);
static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb3", 0xa8c, BIT(5), 0);
static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb3", 0xa8c, BIT(6), 0);
static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb3", 0xa8c, BIT(7), 0);
static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0);
static SUNXI_CCU_GATE(bus_keyadc_clk, "bus-keyadc", "apb1", 0xa9c, BIT(0), 0);
static const char * const hdmi_parents[] = { "pll-video0", "pll-video0-4x",
"pll-video2", "pll-video2-4x" };
static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 0xb00,
0, 4, /* M */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0xb04, BIT(31), 0);
static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" };
static const struct ccu_mux_fixed_prediv hdmi_cec_predivs[] = {
{ .index = 1, .div = 36621 },
};
#define SUN50I_H616_HDMI_CEC_CLK_REG 0xb10
static struct ccu_mux hdmi_cec_clk = {
.enable = BIT(31) | BIT(30),
.mux = {
.shift = 24,
.width = 2,
.fixed_predivs = hdmi_cec_predivs,
.n_predivs = ARRAY_SIZE(hdmi_cec_predivs),
},
.common = {
.reg = 0xb10,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("hdmi-cec",
hdmi_cec_parents,
&ccu_mux_ops,
0),
},
};
static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb3", 0xb1c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb3",
0xb5c, BIT(0), 0);
static const char * const tcon_tv_parents[] = { "pll-video0",
"pll-video0-4x",
"pll-video1",
"pll-video1-4x" };
static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0",
tcon_tv_parents, 0xb80,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1",
tcon_tv_parents, 0xb84,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3",
0xb9c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_tcon_tv1_clk, "bus-tcon-tv1", "ahb3",
0xb9c, BIT(1), 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(tve0_clk, "tve0",
tcon_tv_parents, 0xbb0,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(bus_tve_top_clk, "bus-tve-top", "ahb3",
0xbbc, BIT(0), 0);
static SUNXI_CCU_GATE(bus_tve0_clk, "bus-tve0", "ahb3",
0xbbc, BIT(1), 0);
static const char * const hdcp_parents[] = { "pll-periph0", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(hdcp_clk, "hdcp", hdcp_parents, 0xc40,
0, 4, /* M */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(bus_hdcp_clk, "bus-hdcp", "ahb3", 0xc4c, BIT(0), 0);
/* Fixed factor clocks */
static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
static const struct clk_hw *clk_parent_pll_audio[] = {
&pll_audio_hs_clk.common.hw
};
/*
* The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200
* rates can be set exactly in conjunction with sigma-delta modulation.
*/
static CLK_FIXED_FACTOR_HWS(pll_audio_1x_clk, "pll-audio-1x",
clk_parent_pll_audio,
96, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
clk_parent_pll_audio,
48, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
clk_parent_pll_audio,
24, 1, CLK_SET_RATE_PARENT);
static const struct clk_hw *pll_periph0_parents[] = {
&pll_periph0_clk.common.hw
};
static CLK_FIXED_FACTOR_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
pll_periph0_parents,
1, 2, 0);
static const struct clk_hw *pll_periph0_2x_hws[] = {
&pll_periph0_2x_clk.hw
};
static CLK_FIXED_FACTOR_HWS(pll_system_32k_clk, "pll-system-32k",
pll_periph0_2x_hws, 36621, 1, 0);
static const struct clk_hw *pll_periph1_parents[] = {
&pll_periph1_clk.common.hw
};
static CLK_FIXED_FACTOR_HWS(pll_periph1_2x_clk, "pll-periph1-2x",
pll_periph1_parents,
1, 2, 0);
static CLK_FIXED_FACTOR_HW(pll_video0_4x_clk, "pll-video0-4x",
&pll_video0_clk.common.hw,
1, 4, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HW(pll_video1_4x_clk, "pll-video1-4x",
&pll_video1_clk.common.hw,
1, 4, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HW(pll_video2_4x_clk, "pll-video2-4x",
&pll_video2_clk.common.hw,
1, 4, CLK_SET_RATE_PARENT);
static struct ccu_common *sun50i_h616_ccu_clks[] = {
&pll_cpux_clk.common,
&pll_ddr0_clk.common,
&pll_ddr1_clk.common,
&pll_periph0_clk.common,
&pll_periph1_clk.common,
&pll_gpu_clk.common,
&pll_video0_clk.common,
&pll_video1_clk.common,
&pll_video2_clk.common,
&pll_ve_clk.common,
&pll_de_clk.common,
&pll_audio_hs_clk.common,
&cpux_clk.common,
&axi_clk.common,
&cpux_apb_clk.common,
&psi_ahb1_ahb2_clk.common,
&ahb3_clk.common,
&apb1_clk.common,
&apb2_clk.common,
&mbus_clk.common,
&de_clk.common,
&bus_de_clk.common,
&deinterlace_clk.common,
&bus_deinterlace_clk.common,
&g2d_clk.common,
&bus_g2d_clk.common,
&gpu0_clk.common,
&bus_gpu_clk.common,
&gpu1_clk.common,
&ce_clk.common,
&bus_ce_clk.common,
&ve_clk.common,
&bus_ve_clk.common,
&bus_dma_clk.common,
&bus_hstimer_clk.common,
&avs_clk.common,
&bus_dbg_clk.common,
&bus_psi_clk.common,
&bus_pwm_clk.common,
&bus_iommu_clk.common,
&dram_clk.common,
&mbus_dma_clk.common,
&mbus_ve_clk.common,
&mbus_ce_clk.common,
&mbus_ts_clk.common,
&mbus_nand_clk.common,
&mbus_g2d_clk.common,
&bus_dram_clk.common,
&nand0_clk.common,
&nand1_clk.common,
&bus_nand_clk.common,
&mmc0_clk.common,
&mmc1_clk.common,
&mmc2_clk.common,
&bus_mmc0_clk.common,
&bus_mmc1_clk.common,
&bus_mmc2_clk.common,
&bus_uart0_clk.common,
&bus_uart1_clk.common,
&bus_uart2_clk.common,
&bus_uart3_clk.common,
&bus_uart4_clk.common,
&bus_uart5_clk.common,
&bus_i2c0_clk.common,
&bus_i2c1_clk.common,
&bus_i2c2_clk.common,
&bus_i2c3_clk.common,
&bus_i2c4_clk.common,
&spi0_clk.common,
&spi1_clk.common,
&bus_spi0_clk.common,
&bus_spi1_clk.common,
&emac_25m_clk.common,
&bus_emac0_clk.common,
&bus_emac1_clk.common,
&ts_clk.common,
&bus_ts_clk.common,
&bus_ths_clk.common,
&spdif_clk.common,
&bus_spdif_clk.common,
&dmic_clk.common,
&bus_dmic_clk.common,
&audio_codec_1x_clk.common,
&audio_codec_4x_clk.common,
&bus_audio_codec_clk.common,
&audio_hub_clk.common,
&bus_audio_hub_clk.common,
&usb_ohci0_clk.common,
&usb_phy0_clk.common,
&usb_ohci1_clk.common,
&usb_phy1_clk.common,
&usb_ohci2_clk.common,
&usb_phy2_clk.common,
&usb_ohci3_clk.common,
&usb_phy3_clk.common,
&bus_ohci0_clk.common,
&bus_ohci1_clk.common,
&bus_ohci2_clk.common,
&bus_ohci3_clk.common,
&bus_ehci0_clk.common,
&bus_ehci1_clk.common,
&bus_ehci2_clk.common,
&bus_ehci3_clk.common,
&bus_otg_clk.common,
&bus_keyadc_clk.common,
&hdmi_clk.common,
&hdmi_slow_clk.common,
&hdmi_cec_clk.common,
&bus_hdmi_clk.common,
&bus_tcon_top_clk.common,
&tcon_tv0_clk.common,
&tcon_tv1_clk.common,
&bus_tcon_tv0_clk.common,
&bus_tcon_tv1_clk.common,
&tve0_clk.common,
&bus_tve_top_clk.common,
&bus_tve0_clk.common,
&hdcp_clk.common,
&bus_hdcp_clk.common,
};
static struct clk_hw_onecell_data sun50i_h616_hw_clks = {
.hws = {
[CLK_OSC12M] = &osc12M_clk.hw,
[CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
[CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
[CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
[CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
[CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
[CLK_PLL_SYSTEM_32K] = &pll_system_32k_clk.hw,
[CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
[CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
[CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
[CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
[CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.hw,
[CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
[CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.hw,
[CLK_PLL_VIDEO2] = &pll_video2_clk.common.hw,
[CLK_PLL_VIDEO2_4X] = &pll_video2_4x_clk.hw,
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
[CLK_PLL_DE] = &pll_de_clk.common.hw,
[CLK_PLL_AUDIO_HS] = &pll_audio_hs_clk.common.hw,
[CLK_PLL_AUDIO_1X] = &pll_audio_1x_clk.hw,
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
[CLK_CPUX] = &cpux_clk.common.hw,
[CLK_AXI] = &axi_clk.common.hw,
[CLK_CPUX_APB] = &cpux_apb_clk.common.hw,
[CLK_PSI_AHB1_AHB2] = &psi_ahb1_ahb2_clk.common.hw,
[CLK_AHB3] = &ahb3_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_APB2] = &apb2_clk.common.hw,
[CLK_MBUS] = &mbus_clk.common.hw,
[CLK_DE] = &de_clk.common.hw,
[CLK_BUS_DE] = &bus_de_clk.common.hw,
[CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
[CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
[CLK_G2D] = &g2d_clk.common.hw,
[CLK_BUS_G2D] = &bus_g2d_clk.common.hw,
[CLK_GPU0] = &gpu0_clk.common.hw,
[CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
[CLK_GPU1] = &gpu1_clk.common.hw,
[CLK_CE] = &ce_clk.common.hw,
[CLK_BUS_CE] = &bus_ce_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_BUS_VE] = &bus_ve_clk.common.hw,
[CLK_BUS_DMA] = &bus_dma_clk.common.hw,
[CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
[CLK_BUS_PSI] = &bus_psi_clk.common.hw,
[CLK_BUS_PWM] = &bus_pwm_clk.common.hw,
[CLK_BUS_IOMMU] = &bus_iommu_clk.common.hw,
[CLK_DRAM] = &dram_clk.common.hw,
[CLK_MBUS_DMA] = &mbus_dma_clk.common.hw,
[CLK_MBUS_VE] = &mbus_ve_clk.common.hw,
[CLK_MBUS_CE] = &mbus_ce_clk.common.hw,
[CLK_MBUS_TS] = &mbus_ts_clk.common.hw,
[CLK_MBUS_NAND] = &mbus_nand_clk.common.hw,
[CLK_MBUS_G2D] = &mbus_g2d_clk.common.hw,
[CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
[CLK_NAND0] = &nand0_clk.common.hw,
[CLK_NAND1] = &nand1_clk.common.hw,
[CLK_BUS_NAND] = &bus_nand_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
[CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
[CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
[CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
[CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
[CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
[CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
[CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
[CLK_BUS_UART5] = &bus_uart5_clk.common.hw,
[CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
[CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
[CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
[CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
[CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
[CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
[CLK_EMAC_25M] = &emac_25m_clk.common.hw,
[CLK_BUS_EMAC0] = &bus_emac0_clk.common.hw,
[CLK_BUS_EMAC1] = &bus_emac1_clk.common.hw,
[CLK_TS] = &ts_clk.common.hw,
[CLK_BUS_TS] = &bus_ts_clk.common.hw,
[CLK_BUS_THS] = &bus_ths_clk.common.hw,
[CLK_SPDIF] = &spdif_clk.common.hw,
[CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
[CLK_DMIC] = &dmic_clk.common.hw,
[CLK_BUS_DMIC] = &bus_dmic_clk.common.hw,
[CLK_AUDIO_CODEC_1X] = &audio_codec_1x_clk.common.hw,
[CLK_AUDIO_CODEC_4X] = &audio_codec_4x_clk.common.hw,
[CLK_BUS_AUDIO_CODEC] = &bus_audio_codec_clk.common.hw,
[CLK_AUDIO_HUB] = &audio_hub_clk.common.hw,
[CLK_BUS_AUDIO_HUB] = &bus_audio_hub_clk.common.hw,
[CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
[CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
[CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
[CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
[CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
[CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw,
[CLK_USB_PHY3] = &usb_phy3_clk.common.hw,
[CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
[CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
[CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw,
[CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw,
[CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
[CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
[CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw,
[CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw,
[CLK_BUS_OTG] = &bus_otg_clk.common.hw,
[CLK_BUS_KEYADC] = &bus_keyadc_clk.common.hw,
[CLK_HDMI] = &hdmi_clk.common.hw,
[CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw,
[CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw,
[CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
[CLK_BUS_TCON_TOP] = &bus_tcon_top_clk.common.hw,
[CLK_TCON_TV0] = &tcon_tv0_clk.common.hw,
[CLK_TCON_TV1] = &tcon_tv1_clk.common.hw,
[CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw,
[CLK_BUS_TCON_TV1] = &bus_tcon_tv1_clk.common.hw,
[CLK_TVE0] = &tve0_clk.common.hw,
[CLK_BUS_TVE_TOP] = &bus_tve_top_clk.common.hw,
[CLK_BUS_TVE0] = &bus_tve0_clk.common.hw,
[CLK_HDCP] = &hdcp_clk.common.hw,
[CLK_BUS_HDCP] = &bus_hdcp_clk.common.hw,
},
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun50i_h616_ccu_resets[] = {
[RST_MBUS] = { 0x540, BIT(30) },
[RST_BUS_DE] = { 0x60c, BIT(16) },
[RST_BUS_DEINTERLACE] = { 0x62c, BIT(16) },
[RST_BUS_GPU] = { 0x67c, BIT(16) },
[RST_BUS_CE] = { 0x68c, BIT(16) },
[RST_BUS_VE] = { 0x69c, BIT(16) },
[RST_BUS_DMA] = { 0x70c, BIT(16) },
[RST_BUS_HSTIMER] = { 0x73c, BIT(16) },
[RST_BUS_DBG] = { 0x78c, BIT(16) },
[RST_BUS_PSI] = { 0x79c, BIT(16) },
[RST_BUS_PWM] = { 0x7ac, BIT(16) },
[RST_BUS_IOMMU] = { 0x7bc, BIT(16) },
[RST_BUS_DRAM] = { 0x80c, BIT(16) },
[RST_BUS_NAND] = { 0x82c, BIT(16) },
[RST_BUS_MMC0] = { 0x84c, BIT(16) },
[RST_BUS_MMC1] = { 0x84c, BIT(17) },
[RST_BUS_MMC2] = { 0x84c, BIT(18) },
[RST_BUS_UART0] = { 0x90c, BIT(16) },
[RST_BUS_UART1] = { 0x90c, BIT(17) },
[RST_BUS_UART2] = { 0x90c, BIT(18) },
[RST_BUS_UART3] = { 0x90c, BIT(19) },
[RST_BUS_UART4] = { 0x90c, BIT(20) },
[RST_BUS_UART5] = { 0x90c, BIT(21) },
[RST_BUS_I2C0] = { 0x91c, BIT(16) },
[RST_BUS_I2C1] = { 0x91c, BIT(17) },
[RST_BUS_I2C2] = { 0x91c, BIT(18) },
[RST_BUS_I2C3] = { 0x91c, BIT(19) },
[RST_BUS_I2C4] = { 0x91c, BIT(20) },
[RST_BUS_SPI0] = { 0x96c, BIT(16) },
[RST_BUS_SPI1] = { 0x96c, BIT(17) },
[RST_BUS_EMAC0] = { 0x97c, BIT(16) },
[RST_BUS_EMAC1] = { 0x97c, BIT(17) },
[RST_BUS_TS] = { 0x9bc, BIT(16) },
[RST_BUS_THS] = { 0x9fc, BIT(16) },
[RST_BUS_SPDIF] = { 0xa2c, BIT(16) },
[RST_BUS_DMIC] = { 0xa4c, BIT(16) },
[RST_BUS_AUDIO_CODEC] = { 0xa5c, BIT(16) },
[RST_BUS_AUDIO_HUB] = { 0xa6c, BIT(16) },
[RST_USB_PHY0] = { 0xa70, BIT(30) },
[RST_USB_PHY1] = { 0xa74, BIT(30) },
[RST_USB_PHY2] = { 0xa78, BIT(30) },
[RST_USB_PHY3] = { 0xa7c, BIT(30) },
[RST_BUS_OHCI0] = { 0xa8c, BIT(16) },
[RST_BUS_OHCI1] = { 0xa8c, BIT(17) },
[RST_BUS_OHCI2] = { 0xa8c, BIT(18) },
[RST_BUS_OHCI3] = { 0xa8c, BIT(19) },
[RST_BUS_EHCI0] = { 0xa8c, BIT(20) },
[RST_BUS_EHCI1] = { 0xa8c, BIT(21) },
[RST_BUS_EHCI2] = { 0xa8c, BIT(22) },
[RST_BUS_EHCI3] = { 0xa8c, BIT(23) },
[RST_BUS_OTG] = { 0xa8c, BIT(24) },
[RST_BUS_KEYADC] = { 0xa9c, BIT(16) },
[RST_BUS_HDMI] = { 0xb1c, BIT(16) },
[RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) },
[RST_BUS_TCON_TOP] = { 0xb5c, BIT(16) },
[RST_BUS_TCON_TV0] = { 0xb9c, BIT(16) },
[RST_BUS_TCON_TV1] = { 0xb9c, BIT(17) },
[RST_BUS_TVE_TOP] = { 0xbbc, BIT(16) },
[RST_BUS_TVE0] = { 0xbbc, BIT(17) },
[RST_BUS_HDCP] = { 0xc4c, BIT(16) },
};
static const struct sunxi_ccu_desc sun50i_h616_ccu_desc = {
.ccu_clks = sun50i_h616_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun50i_h616_ccu_clks),
.hw_clks = &sun50i_h616_hw_clks,
.resets = sun50i_h616_ccu_resets,
.num_resets = ARRAY_SIZE(sun50i_h616_ccu_resets),
};
static const u32 pll_regs[] = {
SUN50I_H616_PLL_CPUX_REG,
SUN50I_H616_PLL_DDR0_REG,
SUN50I_H616_PLL_DDR1_REG,
SUN50I_H616_PLL_PERIPH0_REG,
SUN50I_H616_PLL_PERIPH1_REG,
SUN50I_H616_PLL_GPU_REG,
SUN50I_H616_PLL_VIDEO0_REG,
SUN50I_H616_PLL_VIDEO1_REG,
SUN50I_H616_PLL_VIDEO2_REG,
SUN50I_H616_PLL_VE_REG,
SUN50I_H616_PLL_DE_REG,
SUN50I_H616_PLL_AUDIO_REG,
};
static const u32 pll_video_regs[] = {
SUN50I_H616_PLL_VIDEO0_REG,
SUN50I_H616_PLL_VIDEO1_REG,
SUN50I_H616_PLL_VIDEO2_REG,
};
static const u32 usb2_clk_regs[] = {
SUN50I_H616_USB0_CLK_REG,
SUN50I_H616_USB1_CLK_REG,
SUN50I_H616_USB2_CLK_REG,
SUN50I_H616_USB3_CLK_REG,
};
static int sun50i_h616_ccu_probe(struct platform_device *pdev)
{
void __iomem *reg;
u32 val;
int i;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
/* Enable the lock bits and the output enable bits on all PLLs */
for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
val = readl(reg + pll_regs[i]);
val |= BIT(29) | BIT(27);
writel(val, reg + pll_regs[i]);
}
/*
* Force the output divider of video PLLs to 0.
*
* See the comment before pll-video0 definition for the reason.
*/
for (i = 0; i < ARRAY_SIZE(pll_video_regs); i++) {
val = readl(reg + pll_video_regs[i]);
val &= ~BIT(0);
writel(val, reg + pll_video_regs[i]);
}
/*
* Force OHCI 12M clock sources to 00 (12MHz divided from 48MHz)
*
* This clock mux is still mysterious, and the code just enforces
* it to have a valid clock parent.
*/
for (i = 0; i < ARRAY_SIZE(usb2_clk_regs); i++) {
val = readl(reg + usb2_clk_regs[i]);
val &= ~GENMASK(25, 24);
writel(val, reg + usb2_clk_regs[i]);
}
/*
* Force the post-divider of pll-audio to 12 and the output divider
* of it to 2, so 24576000 and 22579200 rates can be set exactly.
*/
val = readl(reg + SUN50I_H616_PLL_AUDIO_REG);
val &= ~(GENMASK(21, 16) | BIT(0));
writel(val | (11 << 16) | BIT(0), reg + SUN50I_H616_PLL_AUDIO_REG);
/*
* First clock parent (osc32K) is unusable for CEC. But since there
* is no good way to force parent switch (both run with same frequency),
* just set second clock parent here.
*/
val = readl(reg + SUN50I_H616_HDMI_CEC_CLK_REG);
val |= BIT(24);
writel(val, reg + SUN50I_H616_HDMI_CEC_CLK_REG);
return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h616_ccu_desc);
}
static const struct of_device_id sun50i_h616_ccu_ids[] = {
{ .compatible = "allwinner,sun50i-h616-ccu" },
{ }
};
static struct platform_driver sun50i_h616_ccu_driver = {
.probe = sun50i_h616_ccu_probe,
.driver = {
.name = "sun50i-h616-ccu",
.suppress_bind_attrs = true,
.of_match_table = sun50i_h616_ccu_ids,
},
};
module_platform_driver(sun50i_h616_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun50i-h616.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Maxime Ripard
* Maxime Ripard <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include "ccu_frac.h"
#include "ccu_gate.h"
#include "ccu_nm.h"
struct _ccu_nm {
unsigned long n, min_n, max_n;
unsigned long m, min_m, max_m;
};
static unsigned long ccu_nm_calc_rate(unsigned long parent,
unsigned long n, unsigned long m)
{
u64 rate = parent;
rate *= n;
do_div(rate, m);
return rate;
}
static unsigned long ccu_nm_find_best(struct ccu_common *common, unsigned long parent,
unsigned long rate, struct _ccu_nm *nm)
{
unsigned long best_rate = 0;
unsigned long best_n = 0, best_m = 0;
unsigned long _n, _m;
for (_n = nm->min_n; _n <= nm->max_n; _n++) {
for (_m = nm->min_m; _m <= nm->max_m; _m++) {
unsigned long tmp_rate = ccu_nm_calc_rate(parent,
_n, _m);
if (ccu_is_better_rate(common, rate, tmp_rate, best_rate)) {
best_rate = tmp_rate;
best_n = _n;
best_m = _m;
}
}
}
nm->n = best_n;
nm->m = best_m;
return best_rate;
}
static void ccu_nm_disable(struct clk_hw *hw)
{
struct ccu_nm *nm = hw_to_ccu_nm(hw);
return ccu_gate_helper_disable(&nm->common, nm->enable);
}
static int ccu_nm_enable(struct clk_hw *hw)
{
struct ccu_nm *nm = hw_to_ccu_nm(hw);
return ccu_gate_helper_enable(&nm->common, nm->enable);
}
static int ccu_nm_is_enabled(struct clk_hw *hw)
{
struct ccu_nm *nm = hw_to_ccu_nm(hw);
return ccu_gate_helper_is_enabled(&nm->common, nm->enable);
}
static unsigned long ccu_nm_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct ccu_nm *nm = hw_to_ccu_nm(hw);
unsigned long rate;
unsigned long n, m;
u32 reg;
if (ccu_frac_helper_is_enabled(&nm->common, &nm->frac)) {
rate = ccu_frac_helper_read_rate(&nm->common, &nm->frac);
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nm->fixed_post_div;
return rate;
}
reg = readl(nm->common.base + nm->common.reg);
n = reg >> nm->n.shift;
n &= (1 << nm->n.width) - 1;
n += nm->n.offset;
if (!n)
n++;
m = reg >> nm->m.shift;
m &= (1 << nm->m.width) - 1;
m += nm->m.offset;
if (!m)
m++;
if (ccu_sdm_helper_is_enabled(&nm->common, &nm->sdm))
rate = ccu_sdm_helper_read_rate(&nm->common, &nm->sdm, m, n);
else
rate = ccu_nm_calc_rate(parent_rate, n, m);
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nm->fixed_post_div;
return rate;
}
static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
struct ccu_nm *nm = hw_to_ccu_nm(hw);
struct _ccu_nm _nm;
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate *= nm->fixed_post_div;
if (rate < nm->min_rate) {
rate = nm->min_rate;
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nm->fixed_post_div;
return rate;
}
if (nm->max_rate && rate > nm->max_rate) {
rate = nm->max_rate;
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nm->fixed_post_div;
return rate;
}
if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) {
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nm->fixed_post_div;
return rate;
}
if (ccu_sdm_helper_has_rate(&nm->common, &nm->sdm, rate)) {
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nm->fixed_post_div;
return rate;
}
_nm.min_n = nm->n.min ?: 1;
_nm.max_n = nm->n.max ?: 1 << nm->n.width;
_nm.min_m = 1;
_nm.max_m = nm->m.max ?: 1 << nm->m.width;
rate = ccu_nm_find_best(&nm->common, *parent_rate, rate, &_nm);
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nm->fixed_post_div;
return rate;
}
static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct ccu_nm *nm = hw_to_ccu_nm(hw);
struct _ccu_nm _nm;
unsigned long flags;
u32 reg;
/* Adjust target rate according to post-dividers */
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate = rate * nm->fixed_post_div;
if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) {
spin_lock_irqsave(nm->common.lock, flags);
/* most SoCs require M to be 0 if fractional mode is used */
reg = readl(nm->common.base + nm->common.reg);
reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift);
writel(reg, nm->common.base + nm->common.reg);
spin_unlock_irqrestore(nm->common.lock, flags);
ccu_frac_helper_enable(&nm->common, &nm->frac);
return ccu_frac_helper_set_rate(&nm->common, &nm->frac,
rate, nm->lock);
} else {
ccu_frac_helper_disable(&nm->common, &nm->frac);
}
_nm.min_n = nm->n.min ?: 1;
_nm.max_n = nm->n.max ?: 1 << nm->n.width;
_nm.min_m = 1;
_nm.max_m = nm->m.max ?: 1 << nm->m.width;
if (ccu_sdm_helper_has_rate(&nm->common, &nm->sdm, rate)) {
ccu_sdm_helper_enable(&nm->common, &nm->sdm, rate);
/* Sigma delta modulation requires specific N and M factors */
ccu_sdm_helper_get_factors(&nm->common, &nm->sdm, rate,
&_nm.m, &_nm.n);
} else {
ccu_sdm_helper_disable(&nm->common, &nm->sdm);
ccu_nm_find_best(&nm->common, parent_rate, rate, &_nm);
}
spin_lock_irqsave(nm->common.lock, flags);
reg = readl(nm->common.base + nm->common.reg);
reg &= ~GENMASK(nm->n.width + nm->n.shift - 1, nm->n.shift);
reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift);
reg |= (_nm.n - nm->n.offset) << nm->n.shift;
reg |= (_nm.m - nm->m.offset) << nm->m.shift;
writel(reg, nm->common.base + nm->common.reg);
spin_unlock_irqrestore(nm->common.lock, flags);
ccu_helper_wait_for_lock(&nm->common, nm->lock);
return 0;
}
const struct clk_ops ccu_nm_ops = {
.disable = ccu_nm_disable,
.enable = ccu_nm_enable,
.is_enabled = ccu_nm_is_enabled,
.recalc_rate = ccu_nm_recalc_rate,
.round_rate = ccu_nm_round_rate,
.set_rate = ccu_nm_set_rate,
};
EXPORT_SYMBOL_NS_GPL(ccu_nm_ops, SUNXI_CCU);
| linux-master | drivers/clk/sunxi-ng/ccu_nm.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016 Chen-Yu Tsai
*
* Chen-Yu Tsai <[email protected]>
*
* Based on ccu-sun8i-h3.c by Maxime Ripard.
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu_mult.h"
#include "ccu_mux.h"
#include "ccu_nk.h"
#include "ccu_nkm.h"
#include "ccu_nkmp.h"
#include "ccu_nm.h"
#include "ccu_phase.h"
#include "ccu_sdm.h"
#include "ccu-sun6i-a31.h"
static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
"osc24M", 0x000,
8, 5, /* N */
4, 2, /* K */
0, 2, /* M */
BIT(31), /* gate */
BIT(28), /* lock */
0);
/*
* The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
* the base (2x, 4x and 8x), and one variable divider (the one true
* pll audio).
*
* With sigma-delta modulation for fractional-N on the audio PLL,
* we have to use specific dividers. This means the variable divider
* can no longer be used, as the audio codec requests the exact clock
* rates we support through this mechanism. So we now hard code the
* variable divider to 1. This means the clock rates will no longer
* match the clock names.
*/
#define SUN6I_A31_PLL_AUDIO_REG 0x008
static struct ccu_sdm_setting pll_audio_sdm_table[] = {
{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
};
static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
"osc24M", 0x008,
8, 7, /* N */
0, 5, /* M */
pll_audio_sdm_table, BIT(24),
0x284, BIT(31),
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
"osc24M", 0x010,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
"osc24M", 0x018,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
"osc24M", 0x020,
8, 5, /* N */
4, 2, /* K */
0, 2, /* M */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
"osc24M", 0x028,
8, 5, /* N */
4, 2, /* K */
BIT(31), /* gate */
BIT(28), /* lock */
2, /* post-div */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
"osc24M", 0x030,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
"osc24M", 0x038,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
/*
* The MIPI PLL has 2 modes: "MIPI" and "HDMI".
*
* The MIPI mode is a standard NKM-style clock. The HDMI mode is an
* integer / fractional clock with switchable multipliers and dividers.
* This is not supported here. We hardcode the PLL to MIPI mode.
*/
#define SUN6I_A31_PLL_MIPI_REG 0x040
static const char * const pll_mipi_parents[] = { "pll-video0", "pll-video1" };
static SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(pll_mipi_clk, "pll-mipi",
pll_mipi_parents, 0x040,
8, 4, /* N */
4, 2, /* K */
0, 4, /* M */
21, 0, /* mux */
BIT(31) | BIT(23) | BIT(22), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll9_clk, "pll9",
"osc24M", 0x044,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll10_clk, "pll10",
"osc24M", 0x048,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static const char * const cpux_parents[] = { "osc32k", "osc24M",
"pll-cpu", "pll-cpu" };
static SUNXI_CCU_MUX(cpu_clk, "cpu", cpux_parents,
0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
static struct clk_div_table axi_div_table[] = {
{ .val = 0, .div = 1 },
{ .val = 1, .div = 2 },
{ .val = 2, .div = 3 },
{ .val = 3, .div = 4 },
{ .val = 4, .div = 4 },
{ .val = 5, .div = 4 },
{ .val = 6, .div = 4 },
{ .val = 7, .div = 4 },
{ /* Sentinel */ },
};
static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu",
0x050, 0, 3, axi_div_table, 0);
#define SUN6I_A31_AHB1_REG 0x054
static const char * const ahb1_parents[] = { "osc32k", "osc24M",
"axi", "pll-periph" };
static const struct ccu_mux_var_prediv ahb1_predivs[] = {
{ .index = 3, .shift = 6, .width = 2 },
};
static struct ccu_div ahb1_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = {
.shift = 12,
.width = 2,
.var_predivs = ahb1_predivs,
.n_var_predivs = ARRAY_SIZE(ahb1_predivs),
},
.common = {
.reg = 0x054,
.features = CCU_FEATURE_VARIABLE_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("ahb1",
ahb1_parents,
&ccu_div_ops,
0),
},
};
static struct clk_div_table apb1_div_table[] = {
{ .val = 0, .div = 2 },
{ .val = 1, .div = 2 },
{ .val = 2, .div = 4 },
{ .val = 3, .div = 8 },
{ /* Sentinel */ },
};
static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
0x054, 8, 2, apb1_div_table, 0);
static const char * const apb2_parents[] = { "osc32k", "osc24M",
"pll-periph", "pll-periph" };
static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
0, 5, /* M */
16, 2, /* P */
24, 2, /* mux */
0);
static SUNXI_CCU_GATE(ahb1_mipidsi_clk, "ahb1-mipidsi", "ahb1",
0x060, BIT(1), 0);
static SUNXI_CCU_GATE(ahb1_ss_clk, "ahb1-ss", "ahb1",
0x060, BIT(5), 0);
static SUNXI_CCU_GATE(ahb1_dma_clk, "ahb1-dma", "ahb1",
0x060, BIT(6), 0);
static SUNXI_CCU_GATE(ahb1_mmc0_clk, "ahb1-mmc0", "ahb1",
0x060, BIT(8), 0);
static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1",
0x060, BIT(9), 0);
static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1",
0x060, BIT(10), 0);
static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1",
0x060, BIT(11), 0);
static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1",
0x060, BIT(12), 0);
static SUNXI_CCU_GATE(ahb1_nand0_clk, "ahb1-nand0", "ahb1",
0x060, BIT(13), 0);
static SUNXI_CCU_GATE(ahb1_sdram_clk, "ahb1-sdram", "ahb1",
0x060, BIT(14), 0);
static SUNXI_CCU_GATE(ahb1_emac_clk, "ahb1-emac", "ahb1",
0x060, BIT(17), 0);
static SUNXI_CCU_GATE(ahb1_ts_clk, "ahb1-ts", "ahb1",
0x060, BIT(18), 0);
static SUNXI_CCU_GATE(ahb1_hstimer_clk, "ahb1-hstimer", "ahb1",
0x060, BIT(19), 0);
static SUNXI_CCU_GATE(ahb1_spi0_clk, "ahb1-spi0", "ahb1",
0x060, BIT(20), 0);
static SUNXI_CCU_GATE(ahb1_spi1_clk, "ahb1-spi1", "ahb1",
0x060, BIT(21), 0);
static SUNXI_CCU_GATE(ahb1_spi2_clk, "ahb1-spi2", "ahb1",
0x060, BIT(22), 0);
static SUNXI_CCU_GATE(ahb1_spi3_clk, "ahb1-spi3", "ahb1",
0x060, BIT(23), 0);
static SUNXI_CCU_GATE(ahb1_otg_clk, "ahb1-otg", "ahb1",
0x060, BIT(24), 0);
static SUNXI_CCU_GATE(ahb1_ehci0_clk, "ahb1-ehci0", "ahb1",
0x060, BIT(26), 0);
static SUNXI_CCU_GATE(ahb1_ehci1_clk, "ahb1-ehci1", "ahb1",
0x060, BIT(27), 0);
static SUNXI_CCU_GATE(ahb1_ohci0_clk, "ahb1-ohci0", "ahb1",
0x060, BIT(29), 0);
static SUNXI_CCU_GATE(ahb1_ohci1_clk, "ahb1-ohci1", "ahb1",
0x060, BIT(30), 0);
static SUNXI_CCU_GATE(ahb1_ohci2_clk, "ahb1-ohci2", "ahb1",
0x060, BIT(31), 0);
static SUNXI_CCU_GATE(ahb1_ve_clk, "ahb1-ve", "ahb1",
0x064, BIT(0), 0);
static SUNXI_CCU_GATE(ahb1_lcd0_clk, "ahb1-lcd0", "ahb1",
0x064, BIT(4), 0);
static SUNXI_CCU_GATE(ahb1_lcd1_clk, "ahb1-lcd1", "ahb1",
0x064, BIT(5), 0);
static SUNXI_CCU_GATE(ahb1_csi_clk, "ahb1-csi", "ahb1",
0x064, BIT(8), 0);
static SUNXI_CCU_GATE(ahb1_hdmi_clk, "ahb1-hdmi", "ahb1",
0x064, BIT(11), 0);
static SUNXI_CCU_GATE(ahb1_be0_clk, "ahb1-be0", "ahb1",
0x064, BIT(12), 0);
static SUNXI_CCU_GATE(ahb1_be1_clk, "ahb1-be1", "ahb1",
0x064, BIT(13), 0);
static SUNXI_CCU_GATE(ahb1_fe0_clk, "ahb1-fe0", "ahb1",
0x064, BIT(14), 0);
static SUNXI_CCU_GATE(ahb1_fe1_clk, "ahb1-fe1", "ahb1",
0x064, BIT(15), 0);
static SUNXI_CCU_GATE(ahb1_mp_clk, "ahb1-mp", "ahb1",
0x064, BIT(18), 0);
static SUNXI_CCU_GATE(ahb1_gpu_clk, "ahb1-gpu", "ahb1",
0x064, BIT(20), 0);
static SUNXI_CCU_GATE(ahb1_deu0_clk, "ahb1-deu0", "ahb1",
0x064, BIT(23), 0);
static SUNXI_CCU_GATE(ahb1_deu1_clk, "ahb1-deu1", "ahb1",
0x064, BIT(24), 0);
static SUNXI_CCU_GATE(ahb1_drc0_clk, "ahb1-drc0", "ahb1",
0x064, BIT(25), 0);
static SUNXI_CCU_GATE(ahb1_drc1_clk, "ahb1-drc1", "ahb1",
0x064, BIT(26), 0);
static SUNXI_CCU_GATE(apb1_codec_clk, "apb1-codec", "apb1",
0x068, BIT(0), 0);
static SUNXI_CCU_GATE(apb1_spdif_clk, "apb1-spdif", "apb1",
0x068, BIT(1), 0);
static SUNXI_CCU_GATE(apb1_digital_mic_clk, "apb1-digital-mic", "apb1",
0x068, BIT(4), 0);
static SUNXI_CCU_GATE(apb1_pio_clk, "apb1-pio", "apb1",
0x068, BIT(5), 0);
static SUNXI_CCU_GATE(apb1_daudio0_clk, "apb1-daudio0", "apb1",
0x068, BIT(12), 0);
static SUNXI_CCU_GATE(apb1_daudio1_clk, "apb1-daudio1", "apb1",
0x068, BIT(13), 0);
static SUNXI_CCU_GATE(apb2_i2c0_clk, "apb2-i2c0", "apb2",
0x06c, BIT(0), 0);
static SUNXI_CCU_GATE(apb2_i2c1_clk, "apb2-i2c1", "apb2",
0x06c, BIT(1), 0);
static SUNXI_CCU_GATE(apb2_i2c2_clk, "apb2-i2c2", "apb2",
0x06c, BIT(2), 0);
static SUNXI_CCU_GATE(apb2_i2c3_clk, "apb2-i2c3", "apb2",
0x06c, BIT(3), 0);
static SUNXI_CCU_GATE(apb2_uart0_clk, "apb2-uart0", "apb2",
0x06c, BIT(16), 0);
static SUNXI_CCU_GATE(apb2_uart1_clk, "apb2-uart1", "apb2",
0x06c, BIT(17), 0);
static SUNXI_CCU_GATE(apb2_uart2_clk, "apb2-uart2", "apb2",
0x06c, BIT(18), 0);
static SUNXI_CCU_GATE(apb2_uart3_clk, "apb2-uart3", "apb2",
0x06c, BIT(19), 0);
static SUNXI_CCU_GATE(apb2_uart4_clk, "apb2-uart4", "apb2",
0x06c, BIT(20), 0);
static SUNXI_CCU_GATE(apb2_uart5_clk, "apb2-uart5", "apb2",
0x06c, BIT(21), 0);
static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", mod0_default_parents,
0x080,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", mod0_default_parents,
0x084,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents,
0x088,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
0x088, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
0x088, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents,
0x08c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
0x08c, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
0x08c, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents,
0x090,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
0x090, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
0x090, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents,
0x094,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3_sample", "mmc3",
0x094, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3_output", "mmc3",
0x094, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static const char * const daudio_parents[] = { "pll-audio-8x", "pll-audio-4x",
"pll-audio-2x", "pll-audio" };
static SUNXI_CCU_MUX_WITH_GATE(daudio0_clk, "daudio0", daudio_parents,
0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_MUX_WITH_GATE(daudio1_clk, "daudio1", daudio_parents,
0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", daudio_parents,
0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
0x0cc, BIT(8), 0);
static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
0x0cc, BIT(9), 0);
static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
0x0cc, BIT(10), 0);
static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
0x0cc, BIT(16), 0);
static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc24M",
0x0cc, BIT(17), 0);
static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M",
0x0cc, BIT(18), 0);
/* TODO emac clk not supported yet */
static const char * const dram_parents[] = { "pll-ddr", "pll-periph" };
static SUNXI_CCU_MP_WITH_MUX_GATE(mdfs_clk, "mdfs", dram_parents, 0x0f0,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
CLK_IS_CRITICAL);
static SUNXI_CCU_M_WITH_MUX(sdram0_clk, "sdram0", dram_parents,
0x0f4, 0, 4, 4, 1, CLK_IS_CRITICAL);
static SUNXI_CCU_M_WITH_MUX(sdram1_clk, "sdram1", dram_parents,
0x0f4, 8, 4, 12, 1, CLK_IS_CRITICAL);
static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "mdfs",
0x100, BIT(0), 0);
static SUNXI_CCU_GATE(dram_csi_isp_clk, "dram-csi-isp", "mdfs",
0x100, BIT(1), 0);
static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "mdfs",
0x100, BIT(3), 0);
static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "mdfs",
0x100, BIT(16), 0);
static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "mdfs",
0x100, BIT(17), 0);
static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "mdfs",
0x100, BIT(18), 0);
static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "mdfs",
0x100, BIT(19), 0);
static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "mdfs",
0x100, BIT(24), 0);
static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "mdfs",
0x100, BIT(25), 0);
static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "mdfs",
0x100, BIT(26), 0);
static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "mdfs",
0x100, BIT(27), 0);
static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "mdfs",
0x100, BIT(28), 0);
static const char * const de_parents[] = { "pll-video0", "pll-video1",
"pll-periph-2x", "pll-gpu",
"pll9", "pll10" };
static SUNXI_CCU_M_WITH_MUX_GATE(be0_clk, "be0", de_parents,
0x104, 0, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(be1_clk, "be1", de_parents,
0x108, 0, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(fe0_clk, "fe0", de_parents,
0x10c, 0, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(fe1_clk, "fe1", de_parents,
0x110, 0, 4, 24, 3, BIT(31), 0);
static const char * const mp_parents[] = { "pll-video0", "pll-video1",
"pll9", "pll10" };
static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", mp_parents,
0x114, 0, 4, 24, 3, BIT(31), 0);
static const char * const lcd_ch0_parents[] = { "pll-video0", "pll-video1",
"pll-video0-2x",
"pll-video1-2x", "pll-mipi" };
static SUNXI_CCU_MUX_WITH_GATE(lcd0_ch0_clk, "lcd0-ch0", lcd_ch0_parents,
0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_MUX_WITH_GATE(lcd1_ch0_clk, "lcd1-ch0", lcd_ch0_parents,
0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
static const char * const lcd_ch1_parents[] = { "pll-video0", "pll-video1",
"pll-video0-2x",
"pll-video1-2x" };
static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch1_clk, "lcd0-ch1", lcd_ch1_parents,
0x12c, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents,
0x130, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1",
"pll9", "pll10", "pll-mipi",
"pll-ve" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi0_sclk_clk, "csi0-sclk", csi_sclk_parents,
0x134, 16, 4, 24, 3, BIT(31), 0);
static const char * const csi_mclk_parents[] = { "pll-video0", "pll-video1",
"osc24M" };
static const u8 csi_mclk_table[] = { 0, 1, 5 };
static struct ccu_div csi0_mclk_clk = {
.enable = BIT(15),
.div = _SUNXI_CCU_DIV(0, 4),
.mux = _SUNXI_CCU_MUX_TABLE(8, 3, csi_mclk_table),
.common = {
.reg = 0x134,
.hw.init = CLK_HW_INIT_PARENTS("csi0-mclk",
csi_mclk_parents,
&ccu_div_ops,
0),
},
};
static struct ccu_div csi1_mclk_clk = {
.enable = BIT(15),
.div = _SUNXI_CCU_DIV(0, 4),
.mux = _SUNXI_CCU_MUX_TABLE(8, 3, csi_mclk_table),
.common = {
.reg = 0x138,
.hw.init = CLK_HW_INIT_PARENTS("csi1-mclk",
csi_mclk_parents,
&ccu_div_ops,
0),
},
};
static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
0x13c, 16, 3, BIT(31), 0);
static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
0x140, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
0x144, BIT(31), 0);
static SUNXI_CCU_GATE(digital_mic_clk, "digital-mic", "pll-audio",
0x148, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", lcd_ch1_parents,
0x150, 0, 4, 24, 2, BIT(31),
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(hdmi_ddc_clk, "ddc", "osc24M", 0x150, BIT(30), 0);
static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
static const char * const mbus_parents[] = { "osc24M", "pll-periph",
"pll-ddr" };
static SUNXI_CCU_MP_WITH_MUX_GATE(mbus0_clk, "mbus0", mbus_parents, 0x15c,
0, 3, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
CLK_IS_CRITICAL);
static SUNXI_CCU_MP_WITH_MUX_GATE(mbus1_clk, "mbus1", mbus_parents, 0x160,
0, 3, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
CLK_IS_CRITICAL);
static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", lcd_ch1_parents,
0x168, 16, 3, 24, 2, BIT(31),
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_dphy_clk, "mipi-dsi-dphy",
lcd_ch1_parents, 0x168, 0, 3, 8, 2,
BIT(15), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_dphy_clk, "mipi-csi-dphy",
lcd_ch1_parents, 0x16c, 0, 3, 8, 2,
BIT(15), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc0_clk, "iep-drc0", de_parents,
0x180, 0, 3, 24, 2, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc1_clk, "iep-drc1", de_parents,
0x184, 0, 3, 24, 2, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu0_clk, "iep-deu0", de_parents,
0x188, 0, 3, 24, 2, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu1_clk, "iep-deu1", de_parents,
0x18c, 0, 3, 24, 2, BIT(31), 0);
static const char * const gpu_parents[] = { "pll-gpu", "pll-periph-2x",
"pll-video0", "pll-video1",
"pll9", "pll10" };
static const struct ccu_mux_fixed_prediv gpu_predivs[] = {
{ .index = 1, .div = 3, },
};
static struct ccu_div gpu_core_clk = {
.enable = BIT(31),
.div = _SUNXI_CCU_DIV(0, 3),
.mux = {
.shift = 24,
.width = 3,
.fixed_predivs = gpu_predivs,
.n_predivs = ARRAY_SIZE(gpu_predivs),
},
.common = {
.reg = 0x1a0,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("gpu-core",
gpu_parents,
&ccu_div_ops,
0),
},
};
static struct ccu_div gpu_memory_clk = {
.enable = BIT(31),
.div = _SUNXI_CCU_DIV(0, 3),
.mux = {
.shift = 24,
.width = 3,
.fixed_predivs = gpu_predivs,
.n_predivs = ARRAY_SIZE(gpu_predivs),
},
.common = {
.reg = 0x1a4,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("gpu-memory",
gpu_parents,
&ccu_div_ops,
0),
},
};
static struct ccu_div gpu_hyd_clk = {
.enable = BIT(31),
.div = _SUNXI_CCU_DIV(0, 3),
.mux = {
.shift = 24,
.width = 3,
.fixed_predivs = gpu_predivs,
.n_predivs = ARRAY_SIZE(gpu_predivs),
},
.common = {
.reg = 0x1a8,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("gpu-hyd",
gpu_parents,
&ccu_div_ops,
0),
},
};
static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", mod0_default_parents, 0x1b0,
0, 3, /* M */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_M_WITH_MUX_GATE(trace_clk, "trace", mod0_default_parents,
0x1b0,
0, 3, /* M */
24, 2, /* mux */
BIT(31), /* gate */
0);
static const char * const clk_out_parents[] = { "osc24M", "osc32k", "osc24M",
"axi", "ahb1" };
static const u8 clk_out_table[] = { 0, 1, 2, 11, 13 };
static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {
{ .index = 0, .div = 750, },
{ .index = 3, .div = 4, },
{ .index = 4, .div = 4, },
};
static struct ccu_mp out_a_clk = {
.enable = BIT(31),
.m = _SUNXI_CCU_DIV(8, 5),
.p = _SUNXI_CCU_DIV(20, 2),
.mux = {
.shift = 24,
.width = 4,
.table = clk_out_table,
.fixed_predivs = clk_out_predivs,
.n_predivs = ARRAY_SIZE(clk_out_predivs),
},
.common = {
.reg = 0x300,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("out-a",
clk_out_parents,
&ccu_mp_ops,
0),
},
};
static struct ccu_mp out_b_clk = {
.enable = BIT(31),
.m = _SUNXI_CCU_DIV(8, 5),
.p = _SUNXI_CCU_DIV(20, 2),
.mux = {
.shift = 24,
.width = 4,
.table = clk_out_table,
.fixed_predivs = clk_out_predivs,
.n_predivs = ARRAY_SIZE(clk_out_predivs),
},
.common = {
.reg = 0x304,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("out-b",
clk_out_parents,
&ccu_mp_ops,
0),
},
};
static struct ccu_mp out_c_clk = {
.enable = BIT(31),
.m = _SUNXI_CCU_DIV(8, 5),
.p = _SUNXI_CCU_DIV(20, 2),
.mux = {
.shift = 24,
.width = 4,
.table = clk_out_table,
.fixed_predivs = clk_out_predivs,
.n_predivs = ARRAY_SIZE(clk_out_predivs),
},
.common = {
.reg = 0x308,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("out-c",
clk_out_parents,
&ccu_mp_ops,
0),
},
};
static struct ccu_common *sun6i_a31_ccu_clks[] = {
&pll_cpu_clk.common,
&pll_audio_base_clk.common,
&pll_video0_clk.common,
&pll_ve_clk.common,
&pll_ddr_clk.common,
&pll_periph_clk.common,
&pll_video1_clk.common,
&pll_gpu_clk.common,
&pll_mipi_clk.common,
&pll9_clk.common,
&pll10_clk.common,
&cpu_clk.common,
&axi_clk.common,
&ahb1_clk.common,
&apb1_clk.common,
&apb2_clk.common,
&ahb1_mipidsi_clk.common,
&ahb1_ss_clk.common,
&ahb1_dma_clk.common,
&ahb1_mmc0_clk.common,
&ahb1_mmc1_clk.common,
&ahb1_mmc2_clk.common,
&ahb1_mmc3_clk.common,
&ahb1_nand1_clk.common,
&ahb1_nand0_clk.common,
&ahb1_sdram_clk.common,
&ahb1_emac_clk.common,
&ahb1_ts_clk.common,
&ahb1_hstimer_clk.common,
&ahb1_spi0_clk.common,
&ahb1_spi1_clk.common,
&ahb1_spi2_clk.common,
&ahb1_spi3_clk.common,
&ahb1_otg_clk.common,
&ahb1_ehci0_clk.common,
&ahb1_ehci1_clk.common,
&ahb1_ohci0_clk.common,
&ahb1_ohci1_clk.common,
&ahb1_ohci2_clk.common,
&ahb1_ve_clk.common,
&ahb1_lcd0_clk.common,
&ahb1_lcd1_clk.common,
&ahb1_csi_clk.common,
&ahb1_hdmi_clk.common,
&ahb1_be0_clk.common,
&ahb1_be1_clk.common,
&ahb1_fe0_clk.common,
&ahb1_fe1_clk.common,
&ahb1_mp_clk.common,
&ahb1_gpu_clk.common,
&ahb1_deu0_clk.common,
&ahb1_deu1_clk.common,
&ahb1_drc0_clk.common,
&ahb1_drc1_clk.common,
&apb1_codec_clk.common,
&apb1_spdif_clk.common,
&apb1_digital_mic_clk.common,
&apb1_pio_clk.common,
&apb1_daudio0_clk.common,
&apb1_daudio1_clk.common,
&apb2_i2c0_clk.common,
&apb2_i2c1_clk.common,
&apb2_i2c2_clk.common,
&apb2_i2c3_clk.common,
&apb2_uart0_clk.common,
&apb2_uart1_clk.common,
&apb2_uart2_clk.common,
&apb2_uart3_clk.common,
&apb2_uart4_clk.common,
&apb2_uart5_clk.common,
&nand0_clk.common,
&nand1_clk.common,
&mmc0_clk.common,
&mmc0_sample_clk.common,
&mmc0_output_clk.common,
&mmc1_clk.common,
&mmc1_sample_clk.common,
&mmc1_output_clk.common,
&mmc2_clk.common,
&mmc2_sample_clk.common,
&mmc2_output_clk.common,
&mmc3_clk.common,
&mmc3_sample_clk.common,
&mmc3_output_clk.common,
&ts_clk.common,
&ss_clk.common,
&spi0_clk.common,
&spi1_clk.common,
&spi2_clk.common,
&spi3_clk.common,
&daudio0_clk.common,
&daudio1_clk.common,
&spdif_clk.common,
&usb_phy0_clk.common,
&usb_phy1_clk.common,
&usb_phy2_clk.common,
&usb_ohci0_clk.common,
&usb_ohci1_clk.common,
&usb_ohci2_clk.common,
&mdfs_clk.common,
&sdram0_clk.common,
&sdram1_clk.common,
&dram_ve_clk.common,
&dram_csi_isp_clk.common,
&dram_ts_clk.common,
&dram_drc0_clk.common,
&dram_drc1_clk.common,
&dram_deu0_clk.common,
&dram_deu1_clk.common,
&dram_fe0_clk.common,
&dram_fe1_clk.common,
&dram_be0_clk.common,
&dram_be1_clk.common,
&dram_mp_clk.common,
&be0_clk.common,
&be1_clk.common,
&fe0_clk.common,
&fe1_clk.common,
&mp_clk.common,
&lcd0_ch0_clk.common,
&lcd1_ch0_clk.common,
&lcd0_ch1_clk.common,
&lcd1_ch1_clk.common,
&csi0_sclk_clk.common,
&csi0_mclk_clk.common,
&csi1_mclk_clk.common,
&ve_clk.common,
&codec_clk.common,
&avs_clk.common,
&digital_mic_clk.common,
&hdmi_clk.common,
&hdmi_ddc_clk.common,
&ps_clk.common,
&mbus0_clk.common,
&mbus1_clk.common,
&mipi_dsi_clk.common,
&mipi_dsi_dphy_clk.common,
&mipi_csi_dphy_clk.common,
&iep_drc0_clk.common,
&iep_drc1_clk.common,
&iep_deu0_clk.common,
&iep_deu1_clk.common,
&gpu_core_clk.common,
&gpu_memory_clk.common,
&gpu_hyd_clk.common,
&ats_clk.common,
&trace_clk.common,
&out_a_clk.common,
&out_b_clk.common,
&out_c_clk.common,
};
static const struct clk_hw *clk_parent_pll_audio[] = {
&pll_audio_base_clk.common.hw
};
/* We hardcode the divider to 1 for now */
static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
clk_parent_pll_audio,
1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
clk_parent_pll_audio,
2, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
clk_parent_pll_audio,
1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
clk_parent_pll_audio,
1, 2, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
&pll_periph_clk.common.hw,
1, 2, 0);
static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
&pll_video0_clk.common.hw,
1, 2, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
&pll_video1_clk.common.hw,
1, 2, CLK_SET_RATE_PARENT);
static struct clk_hw_onecell_data sun6i_a31_hw_clks = {
.hws = {
[CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
[CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
[CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
[CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
[CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
[CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw,
[CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
[CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
[CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
[CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
[CLK_PLL9] = &pll9_clk.common.hw,
[CLK_PLL10] = &pll10_clk.common.hw,
[CLK_CPU] = &cpu_clk.common.hw,
[CLK_AXI] = &axi_clk.common.hw,
[CLK_AHB1] = &ahb1_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_APB2] = &apb2_clk.common.hw,
[CLK_AHB1_MIPIDSI] = &ahb1_mipidsi_clk.common.hw,
[CLK_AHB1_SS] = &ahb1_ss_clk.common.hw,
[CLK_AHB1_DMA] = &ahb1_dma_clk.common.hw,
[CLK_AHB1_MMC0] = &ahb1_mmc0_clk.common.hw,
[CLK_AHB1_MMC1] = &ahb1_mmc1_clk.common.hw,
[CLK_AHB1_MMC2] = &ahb1_mmc2_clk.common.hw,
[CLK_AHB1_MMC3] = &ahb1_mmc3_clk.common.hw,
[CLK_AHB1_NAND1] = &ahb1_nand1_clk.common.hw,
[CLK_AHB1_NAND0] = &ahb1_nand0_clk.common.hw,
[CLK_AHB1_SDRAM] = &ahb1_sdram_clk.common.hw,
[CLK_AHB1_EMAC] = &ahb1_emac_clk.common.hw,
[CLK_AHB1_TS] = &ahb1_ts_clk.common.hw,
[CLK_AHB1_HSTIMER] = &ahb1_hstimer_clk.common.hw,
[CLK_AHB1_SPI0] = &ahb1_spi0_clk.common.hw,
[CLK_AHB1_SPI1] = &ahb1_spi1_clk.common.hw,
[CLK_AHB1_SPI2] = &ahb1_spi2_clk.common.hw,
[CLK_AHB1_SPI3] = &ahb1_spi3_clk.common.hw,
[CLK_AHB1_OTG] = &ahb1_otg_clk.common.hw,
[CLK_AHB1_EHCI0] = &ahb1_ehci0_clk.common.hw,
[CLK_AHB1_EHCI1] = &ahb1_ehci1_clk.common.hw,
[CLK_AHB1_OHCI0] = &ahb1_ohci0_clk.common.hw,
[CLK_AHB1_OHCI1] = &ahb1_ohci1_clk.common.hw,
[CLK_AHB1_OHCI2] = &ahb1_ohci2_clk.common.hw,
[CLK_AHB1_VE] = &ahb1_ve_clk.common.hw,
[CLK_AHB1_LCD0] = &ahb1_lcd0_clk.common.hw,
[CLK_AHB1_LCD1] = &ahb1_lcd1_clk.common.hw,
[CLK_AHB1_CSI] = &ahb1_csi_clk.common.hw,
[CLK_AHB1_HDMI] = &ahb1_hdmi_clk.common.hw,
[CLK_AHB1_BE0] = &ahb1_be0_clk.common.hw,
[CLK_AHB1_BE1] = &ahb1_be1_clk.common.hw,
[CLK_AHB1_FE0] = &ahb1_fe0_clk.common.hw,
[CLK_AHB1_FE1] = &ahb1_fe1_clk.common.hw,
[CLK_AHB1_MP] = &ahb1_mp_clk.common.hw,
[CLK_AHB1_GPU] = &ahb1_gpu_clk.common.hw,
[CLK_AHB1_DEU0] = &ahb1_deu0_clk.common.hw,
[CLK_AHB1_DEU1] = &ahb1_deu1_clk.common.hw,
[CLK_AHB1_DRC0] = &ahb1_drc0_clk.common.hw,
[CLK_AHB1_DRC1] = &ahb1_drc1_clk.common.hw,
[CLK_APB1_CODEC] = &apb1_codec_clk.common.hw,
[CLK_APB1_SPDIF] = &apb1_spdif_clk.common.hw,
[CLK_APB1_DIGITAL_MIC] = &apb1_digital_mic_clk.common.hw,
[CLK_APB1_PIO] = &apb1_pio_clk.common.hw,
[CLK_APB1_DAUDIO0] = &apb1_daudio0_clk.common.hw,
[CLK_APB1_DAUDIO1] = &apb1_daudio1_clk.common.hw,
[CLK_APB2_I2C0] = &apb2_i2c0_clk.common.hw,
[CLK_APB2_I2C1] = &apb2_i2c1_clk.common.hw,
[CLK_APB2_I2C2] = &apb2_i2c2_clk.common.hw,
[CLK_APB2_I2C3] = &apb2_i2c3_clk.common.hw,
[CLK_APB2_UART0] = &apb2_uart0_clk.common.hw,
[CLK_APB2_UART1] = &apb2_uart1_clk.common.hw,
[CLK_APB2_UART2] = &apb2_uart2_clk.common.hw,
[CLK_APB2_UART3] = &apb2_uart3_clk.common.hw,
[CLK_APB2_UART4] = &apb2_uart4_clk.common.hw,
[CLK_APB2_UART5] = &apb2_uart5_clk.common.hw,
[CLK_NAND0] = &nand0_clk.common.hw,
[CLK_NAND1] = &nand1_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
[CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
[CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
[CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
[CLK_MMC3] = &mmc3_clk.common.hw,
[CLK_MMC3_SAMPLE] = &mmc3_sample_clk.common.hw,
[CLK_MMC3_OUTPUT] = &mmc3_output_clk.common.hw,
[CLK_TS] = &ts_clk.common.hw,
[CLK_SS] = &ss_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI2] = &spi2_clk.common.hw,
[CLK_SPI3] = &spi3_clk.common.hw,
[CLK_DAUDIO0] = &daudio0_clk.common.hw,
[CLK_DAUDIO1] = &daudio1_clk.common.hw,
[CLK_SPDIF] = &spdif_clk.common.hw,
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
[CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
[CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
[CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
[CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
[CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
[CLK_MDFS] = &mdfs_clk.common.hw,
[CLK_SDRAM0] = &sdram0_clk.common.hw,
[CLK_SDRAM1] = &sdram1_clk.common.hw,
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
[CLK_DRAM_CSI_ISP] = &dram_csi_isp_clk.common.hw,
[CLK_DRAM_TS] = &dram_ts_clk.common.hw,
[CLK_DRAM_DRC0] = &dram_drc0_clk.common.hw,
[CLK_DRAM_DRC1] = &dram_drc1_clk.common.hw,
[CLK_DRAM_DEU0] = &dram_deu0_clk.common.hw,
[CLK_DRAM_DEU1] = &dram_deu1_clk.common.hw,
[CLK_DRAM_FE0] = &dram_fe0_clk.common.hw,
[CLK_DRAM_FE1] = &dram_fe1_clk.common.hw,
[CLK_DRAM_BE0] = &dram_be0_clk.common.hw,
[CLK_DRAM_BE1] = &dram_be1_clk.common.hw,
[CLK_DRAM_MP] = &dram_mp_clk.common.hw,
[CLK_BE0] = &be0_clk.common.hw,
[CLK_BE1] = &be1_clk.common.hw,
[CLK_FE0] = &fe0_clk.common.hw,
[CLK_FE1] = &fe1_clk.common.hw,
[CLK_MP] = &mp_clk.common.hw,
[CLK_LCD0_CH0] = &lcd0_ch0_clk.common.hw,
[CLK_LCD1_CH0] = &lcd1_ch0_clk.common.hw,
[CLK_LCD0_CH1] = &lcd0_ch1_clk.common.hw,
[CLK_LCD1_CH1] = &lcd1_ch1_clk.common.hw,
[CLK_CSI0_SCLK] = &csi0_sclk_clk.common.hw,
[CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
[CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_CODEC] = &codec_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_DIGITAL_MIC] = &digital_mic_clk.common.hw,
[CLK_HDMI] = &hdmi_clk.common.hw,
[CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
[CLK_PS] = &ps_clk.common.hw,
[CLK_MBUS0] = &mbus0_clk.common.hw,
[CLK_MBUS1] = &mbus1_clk.common.hw,
[CLK_MIPI_DSI] = &mipi_dsi_clk.common.hw,
[CLK_MIPI_DSI_DPHY] = &mipi_dsi_dphy_clk.common.hw,
[CLK_MIPI_CSI_DPHY] = &mipi_csi_dphy_clk.common.hw,
[CLK_IEP_DRC0] = &iep_drc0_clk.common.hw,
[CLK_IEP_DRC1] = &iep_drc1_clk.common.hw,
[CLK_IEP_DEU0] = &iep_deu0_clk.common.hw,
[CLK_IEP_DEU1] = &iep_deu1_clk.common.hw,
[CLK_GPU_CORE] = &gpu_core_clk.common.hw,
[CLK_GPU_MEMORY] = &gpu_memory_clk.common.hw,
[CLK_GPU_HYD] = &gpu_hyd_clk.common.hw,
[CLK_ATS] = &ats_clk.common.hw,
[CLK_TRACE] = &trace_clk.common.hw,
[CLK_OUT_A] = &out_a_clk.common.hw,
[CLK_OUT_B] = &out_b_clk.common.hw,
[CLK_OUT_C] = &out_c_clk.common.hw,
},
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun6i_a31_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_PHY2] = { 0x0cc, BIT(2) },
[RST_AHB1_MIPI_DSI] = { 0x2c0, BIT(1) },
[RST_AHB1_SS] = { 0x2c0, BIT(5) },
[RST_AHB1_DMA] = { 0x2c0, BIT(6) },
[RST_AHB1_MMC0] = { 0x2c0, BIT(8) },
[RST_AHB1_MMC1] = { 0x2c0, BIT(9) },
[RST_AHB1_MMC2] = { 0x2c0, BIT(10) },
[RST_AHB1_MMC3] = { 0x2c0, BIT(11) },
[RST_AHB1_NAND1] = { 0x2c0, BIT(12) },
[RST_AHB1_NAND0] = { 0x2c0, BIT(13) },
[RST_AHB1_SDRAM] = { 0x2c0, BIT(14) },
[RST_AHB1_EMAC] = { 0x2c0, BIT(17) },
[RST_AHB1_TS] = { 0x2c0, BIT(18) },
[RST_AHB1_HSTIMER] = { 0x2c0, BIT(19) },
[RST_AHB1_SPI0] = { 0x2c0, BIT(20) },
[RST_AHB1_SPI1] = { 0x2c0, BIT(21) },
[RST_AHB1_SPI2] = { 0x2c0, BIT(22) },
[RST_AHB1_SPI3] = { 0x2c0, BIT(23) },
[RST_AHB1_OTG] = { 0x2c0, BIT(24) },
[RST_AHB1_EHCI0] = { 0x2c0, BIT(26) },
[RST_AHB1_EHCI1] = { 0x2c0, BIT(27) },
[RST_AHB1_OHCI0] = { 0x2c0, BIT(29) },
[RST_AHB1_OHCI1] = { 0x2c0, BIT(30) },
[RST_AHB1_OHCI2] = { 0x2c0, BIT(31) },
[RST_AHB1_VE] = { 0x2c4, BIT(0) },
[RST_AHB1_LCD0] = { 0x2c4, BIT(4) },
[RST_AHB1_LCD1] = { 0x2c4, BIT(5) },
[RST_AHB1_CSI] = { 0x2c4, BIT(8) },
[RST_AHB1_HDMI] = { 0x2c4, BIT(11) },
[RST_AHB1_BE0] = { 0x2c4, BIT(12) },
[RST_AHB1_BE1] = { 0x2c4, BIT(13) },
[RST_AHB1_FE0] = { 0x2c4, BIT(14) },
[RST_AHB1_FE1] = { 0x2c4, BIT(15) },
[RST_AHB1_MP] = { 0x2c4, BIT(18) },
[RST_AHB1_GPU] = { 0x2c4, BIT(20) },
[RST_AHB1_DEU0] = { 0x2c4, BIT(23) },
[RST_AHB1_DEU1] = { 0x2c4, BIT(24) },
[RST_AHB1_DRC0] = { 0x2c4, BIT(25) },
[RST_AHB1_DRC1] = { 0x2c4, BIT(26) },
[RST_AHB1_LVDS] = { 0x2c8, BIT(0) },
[RST_APB1_CODEC] = { 0x2d0, BIT(0) },
[RST_APB1_SPDIF] = { 0x2d0, BIT(1) },
[RST_APB1_DIGITAL_MIC] = { 0x2d0, BIT(4) },
[RST_APB1_DAUDIO0] = { 0x2d0, BIT(12) },
[RST_APB1_DAUDIO1] = { 0x2d0, BIT(13) },
[RST_APB2_I2C0] = { 0x2d8, BIT(0) },
[RST_APB2_I2C1] = { 0x2d8, BIT(1) },
[RST_APB2_I2C2] = { 0x2d8, BIT(2) },
[RST_APB2_I2C3] = { 0x2d8, BIT(3) },
[RST_APB2_UART0] = { 0x2d8, BIT(16) },
[RST_APB2_UART1] = { 0x2d8, BIT(17) },
[RST_APB2_UART2] = { 0x2d8, BIT(18) },
[RST_APB2_UART3] = { 0x2d8, BIT(19) },
[RST_APB2_UART4] = { 0x2d8, BIT(20) },
[RST_APB2_UART5] = { 0x2d8, BIT(21) },
};
static const struct sunxi_ccu_desc sun6i_a31_ccu_desc = {
.ccu_clks = sun6i_a31_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun6i_a31_ccu_clks),
.hw_clks = &sun6i_a31_hw_clks,
.resets = sun6i_a31_ccu_resets,
.num_resets = ARRAY_SIZE(sun6i_a31_ccu_resets),
};
static struct ccu_mux_nb sun6i_a31_cpu_nb = {
.common = &cpu_clk.common,
.cm = &cpu_clk.mux,
.delay_us = 1, /* > 8 clock cycles at 24 MHz */
.bypass_index = 1, /* index of 24 MHz oscillator */
};
static int sun6i_a31_ccu_probe(struct platform_device *pdev)
{
void __iomem *reg;
int ret;
u32 val;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
/* Force the PLL-Audio-1x divider to 1 */
val = readl(reg + SUN6I_A31_PLL_AUDIO_REG);
val &= ~GENMASK(19, 16);
writel(val | (0 << 16), reg + SUN6I_A31_PLL_AUDIO_REG);
/* Force PLL-MIPI to MIPI mode */
val = readl(reg + SUN6I_A31_PLL_MIPI_REG);
val &= BIT(16);
writel(val, reg + SUN6I_A31_PLL_MIPI_REG);
/* Force AHB1 to PLL6 / 3 */
val = readl(reg + SUN6I_A31_AHB1_REG);
/* set PLL6 pre-div = 3 */
val &= ~GENMASK(7, 6);
val |= 0x2 << 6;
/* select PLL6 / pre-div */
val &= ~GENMASK(13, 12);
val |= 0x3 << 12;
writel(val, reg + SUN6I_A31_AHB1_REG);
ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun6i_a31_ccu_desc);
if (ret)
return ret;
ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
&sun6i_a31_cpu_nb);
return 0;
}
static const struct of_device_id sun6i_a31_ccu_ids[] = {
{ .compatible = "allwinner,sun6i-a31-ccu" },
{ }
};
static struct platform_driver sun6i_a31_ccu_driver = {
.probe = sun6i_a31_ccu_probe,
.driver = {
.name = "sun6i-a31-ccu",
.suppress_bind_attrs = true,
.of_match_table = sun6i_a31_ccu_ids,
},
};
module_platform_driver(sun6i_a31_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun6i-a31.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Maxime Ripard
* Maxime Ripard <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include "ccu_gate.h"
#include "ccu_mp.h"
static unsigned long ccu_mp_find_best(unsigned long parent, unsigned long rate,
unsigned int max_m, unsigned int max_p,
unsigned int *m, unsigned int *p)
{
unsigned long best_rate = 0;
unsigned int best_m = 0, best_p = 0;
unsigned int _m, _p;
for (_p = 1; _p <= max_p; _p <<= 1) {
for (_m = 1; _m <= max_m; _m++) {
unsigned long tmp_rate = parent / _p / _m;
if (tmp_rate > rate)
continue;
if ((rate - tmp_rate) < (rate - best_rate)) {
best_rate = tmp_rate;
best_m = _m;
best_p = _p;
}
}
}
*m = best_m;
*p = best_p;
return best_rate;
}
static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw,
unsigned long *parent,
unsigned long rate,
unsigned int max_m,
unsigned int max_p)
{
unsigned long parent_rate_saved;
unsigned long parent_rate, now;
unsigned long best_rate = 0;
unsigned int _m, _p, div;
unsigned long maxdiv;
parent_rate_saved = *parent;
/*
* The maximum divider we can use without overflowing
* unsigned long in rate * m * p below
*/
maxdiv = max_m * max_p;
maxdiv = min(ULONG_MAX / rate, maxdiv);
for (_p = 1; _p <= max_p; _p <<= 1) {
for (_m = 1; _m <= max_m; _m++) {
div = _m * _p;
if (div > maxdiv)
break;
if (rate * div == parent_rate_saved) {
/*
* It's the most ideal case if the requested
* rate can be divided from parent clock without
* needing to change parent rate, so return the
* divider immediately.
*/
*parent = parent_rate_saved;
return rate;
}
parent_rate = clk_hw_round_rate(hw, rate * div);
now = parent_rate / div;
if (now <= rate && now > best_rate) {
best_rate = now;
*parent = parent_rate;
if (now == rate)
return rate;
}
}
}
return best_rate;
}
static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux,
struct clk_hw *hw,
unsigned long *parent_rate,
unsigned long rate,
void *data)
{
struct ccu_mp *cmp = data;
unsigned int max_m, max_p;
unsigned int m, p;
if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate *= cmp->fixed_post_div;
max_m = cmp->m.max ?: 1 << cmp->m.width;
max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
if (!clk_hw_can_set_rate_parent(&cmp->common.hw)) {
rate = ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
} else {
rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate,
max_m, max_p);
}
if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= cmp->fixed_post_div;
return rate;
}
static void ccu_mp_disable(struct clk_hw *hw)
{
struct ccu_mp *cmp = hw_to_ccu_mp(hw);
return ccu_gate_helper_disable(&cmp->common, cmp->enable);
}
static int ccu_mp_enable(struct clk_hw *hw)
{
struct ccu_mp *cmp = hw_to_ccu_mp(hw);
return ccu_gate_helper_enable(&cmp->common, cmp->enable);
}
static int ccu_mp_is_enabled(struct clk_hw *hw)
{
struct ccu_mp *cmp = hw_to_ccu_mp(hw);
return ccu_gate_helper_is_enabled(&cmp->common, cmp->enable);
}
static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct ccu_mp *cmp = hw_to_ccu_mp(hw);
unsigned long rate;
unsigned int m, p;
u32 reg;
/* Adjust parent_rate according to pre-dividers */
parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1,
parent_rate);
reg = readl(cmp->common.base + cmp->common.reg);
m = reg >> cmp->m.shift;
m &= (1 << cmp->m.width) - 1;
m += cmp->m.offset;
if (!m)
m++;
p = reg >> cmp->p.shift;
p &= (1 << cmp->p.width) - 1;
rate = (parent_rate >> p) / m;
if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= cmp->fixed_post_div;
return rate;
}
static int ccu_mp_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct ccu_mp *cmp = hw_to_ccu_mp(hw);
return ccu_mux_helper_determine_rate(&cmp->common, &cmp->mux,
req, ccu_mp_round_rate, cmp);
}
static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct ccu_mp *cmp = hw_to_ccu_mp(hw);
unsigned long flags;
unsigned int max_m, max_p;
unsigned int m, p;
u32 reg;
/* Adjust parent_rate according to pre-dividers */
parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1,
parent_rate);
max_m = cmp->m.max ?: 1 << cmp->m.width;
max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
/* Adjust target rate according to post-dividers */
if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate = rate * cmp->fixed_post_div;
ccu_mp_find_best(parent_rate, rate, max_m, max_p, &m, &p);
spin_lock_irqsave(cmp->common.lock, flags);
reg = readl(cmp->common.base + cmp->common.reg);
reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift);
reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift);
reg |= (m - cmp->m.offset) << cmp->m.shift;
reg |= ilog2(p) << cmp->p.shift;
writel(reg, cmp->common.base + cmp->common.reg);
spin_unlock_irqrestore(cmp->common.lock, flags);
return 0;
}
static u8 ccu_mp_get_parent(struct clk_hw *hw)
{
struct ccu_mp *cmp = hw_to_ccu_mp(hw);
return ccu_mux_helper_get_parent(&cmp->common, &cmp->mux);
}
static int ccu_mp_set_parent(struct clk_hw *hw, u8 index)
{
struct ccu_mp *cmp = hw_to_ccu_mp(hw);
return ccu_mux_helper_set_parent(&cmp->common, &cmp->mux, index);
}
const struct clk_ops ccu_mp_ops = {
.disable = ccu_mp_disable,
.enable = ccu_mp_enable,
.is_enabled = ccu_mp_is_enabled,
.get_parent = ccu_mp_get_parent,
.set_parent = ccu_mp_set_parent,
.determine_rate = ccu_mp_determine_rate,
.recalc_rate = ccu_mp_recalc_rate,
.set_rate = ccu_mp_set_rate,
};
EXPORT_SYMBOL_NS_GPL(ccu_mp_ops, SUNXI_CCU);
/*
* Support for MMC timing mode switching
*
* The MMC clocks on some SoCs support switching between old and
* new timing modes. A platform specific API is provided to query
* and set the timing mode on supported SoCs.
*
* In addition, a special class of ccu_mp_ops is provided, which
* takes in to account the timing mode switch. When the new timing
* mode is active, the clock output rate is halved. This new class
* is a wrapper around the generic ccu_mp_ops. When clock rates
* are passed through to ccu_mp_ops callbacks, they are doubled
* if the new timing mode bit is set, to account for the post
* divider. Conversely, when clock rates are passed back, they
* are halved if the mode bit is set.
*/
static unsigned long ccu_mp_mmc_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
unsigned long rate = ccu_mp_recalc_rate(hw, parent_rate);
struct ccu_common *cm = hw_to_ccu_common(hw);
u32 val = readl(cm->base + cm->reg);
if (val & CCU_MMC_NEW_TIMING_MODE)
return rate / 2;
return rate;
}
static int ccu_mp_mmc_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct ccu_common *cm = hw_to_ccu_common(hw);
u32 val = readl(cm->base + cm->reg);
int ret;
/* adjust the requested clock rate */
if (val & CCU_MMC_NEW_TIMING_MODE) {
req->rate *= 2;
req->min_rate *= 2;
req->max_rate *= 2;
}
ret = ccu_mp_determine_rate(hw, req);
/* re-adjust the requested clock rate back */
if (val & CCU_MMC_NEW_TIMING_MODE) {
req->rate /= 2;
req->min_rate /= 2;
req->max_rate /= 2;
}
return ret;
}
static int ccu_mp_mmc_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct ccu_common *cm = hw_to_ccu_common(hw);
u32 val = readl(cm->base + cm->reg);
if (val & CCU_MMC_NEW_TIMING_MODE)
rate *= 2;
return ccu_mp_set_rate(hw, rate, parent_rate);
}
const struct clk_ops ccu_mp_mmc_ops = {
.disable = ccu_mp_disable,
.enable = ccu_mp_enable,
.is_enabled = ccu_mp_is_enabled,
.get_parent = ccu_mp_get_parent,
.set_parent = ccu_mp_set_parent,
.determine_rate = ccu_mp_mmc_determine_rate,
.recalc_rate = ccu_mp_mmc_recalc_rate,
.set_rate = ccu_mp_mmc_set_rate,
};
EXPORT_SYMBOL_NS_GPL(ccu_mp_mmc_ops, SUNXI_CCU);
| linux-master | drivers/clk/sunxi-ng/ccu_mp.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 Samuel Holland <[email protected]>
//
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/clk/sunxi-ng.h>
#include "ccu_common.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mux.h"
#include "ccu-sun6i-rtc.h"
#define IOSC_ACCURACY 300000000 /* 30% */
#define IOSC_RATE 16000000
#define LOSC_RATE 32768
#define LOSC_RATE_SHIFT 15
#define LOSC_CTRL_REG 0x0
#define LOSC_CTRL_KEY 0x16aa0000
#define IOSC_32K_CLK_DIV_REG 0x8
#define IOSC_32K_CLK_DIV GENMASK(4, 0)
#define IOSC_32K_PRE_DIV 32
#define IOSC_CLK_CALI_REG 0xc
#define IOSC_CLK_CALI_DIV_ONES 22
#define IOSC_CLK_CALI_EN BIT(1)
#define IOSC_CLK_CALI_SRC_SEL BIT(0)
#define LOSC_OUT_GATING_REG 0x60
#define DCXO_CTRL_REG 0x160
#define DCXO_CTRL_CLK16M_RC_EN BIT(0)
struct sun6i_rtc_match_data {
bool have_ext_osc32k : 1;
bool have_iosc_calibration : 1;
bool rtc_32k_single_parent : 1;
const struct clk_parent_data *osc32k_fanout_parents;
u8 osc32k_fanout_nparents;
};
static bool have_iosc_calibration;
static int ccu_iosc_enable(struct clk_hw *hw)
{
struct ccu_common *cm = hw_to_ccu_common(hw);
return ccu_gate_helper_enable(cm, DCXO_CTRL_CLK16M_RC_EN);
}
static void ccu_iosc_disable(struct clk_hw *hw)
{
struct ccu_common *cm = hw_to_ccu_common(hw);
return ccu_gate_helper_disable(cm, DCXO_CTRL_CLK16M_RC_EN);
}
static int ccu_iosc_is_enabled(struct clk_hw *hw)
{
struct ccu_common *cm = hw_to_ccu_common(hw);
return ccu_gate_helper_is_enabled(cm, DCXO_CTRL_CLK16M_RC_EN);
}
static unsigned long ccu_iosc_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct ccu_common *cm = hw_to_ccu_common(hw);
if (have_iosc_calibration) {
u32 reg = readl(cm->base + IOSC_CLK_CALI_REG);
/*
* Recover the IOSC frequency by shifting the ones place of
* (fixed-point divider * 32768) into bit zero.
*/
if (reg & IOSC_CLK_CALI_EN)
return reg >> (IOSC_CLK_CALI_DIV_ONES - LOSC_RATE_SHIFT);
}
return IOSC_RATE;
}
static unsigned long ccu_iosc_recalc_accuracy(struct clk_hw *hw,
unsigned long parent_accuracy)
{
return IOSC_ACCURACY;
}
static const struct clk_ops ccu_iosc_ops = {
.enable = ccu_iosc_enable,
.disable = ccu_iosc_disable,
.is_enabled = ccu_iosc_is_enabled,
.recalc_rate = ccu_iosc_recalc_rate,
.recalc_accuracy = ccu_iosc_recalc_accuracy,
};
static struct ccu_common iosc_clk = {
.reg = DCXO_CTRL_REG,
.hw.init = CLK_HW_INIT_NO_PARENT("iosc", &ccu_iosc_ops,
CLK_GET_RATE_NOCACHE),
};
static int ccu_iosc_32k_prepare(struct clk_hw *hw)
{
struct ccu_common *cm = hw_to_ccu_common(hw);
u32 val;
if (!have_iosc_calibration)
return 0;
val = readl(cm->base + IOSC_CLK_CALI_REG);
writel(val | IOSC_CLK_CALI_EN | IOSC_CLK_CALI_SRC_SEL,
cm->base + IOSC_CLK_CALI_REG);
return 0;
}
static void ccu_iosc_32k_unprepare(struct clk_hw *hw)
{
struct ccu_common *cm = hw_to_ccu_common(hw);
u32 val;
if (!have_iosc_calibration)
return;
val = readl(cm->base + IOSC_CLK_CALI_REG);
writel(val & ~(IOSC_CLK_CALI_EN | IOSC_CLK_CALI_SRC_SEL),
cm->base + IOSC_CLK_CALI_REG);
}
static unsigned long ccu_iosc_32k_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct ccu_common *cm = hw_to_ccu_common(hw);
u32 val;
if (have_iosc_calibration) {
val = readl(cm->base + IOSC_CLK_CALI_REG);
/* Assume the calibrated 32k clock is accurate. */
if (val & IOSC_CLK_CALI_SRC_SEL)
return LOSC_RATE;
}
val = readl(cm->base + IOSC_32K_CLK_DIV_REG) & IOSC_32K_CLK_DIV;
return parent_rate / IOSC_32K_PRE_DIV / (val + 1);
}
static unsigned long ccu_iosc_32k_recalc_accuracy(struct clk_hw *hw,
unsigned long parent_accuracy)
{
struct ccu_common *cm = hw_to_ccu_common(hw);
u32 val;
if (have_iosc_calibration) {
val = readl(cm->base + IOSC_CLK_CALI_REG);
/* Assume the calibrated 32k clock is accurate. */
if (val & IOSC_CLK_CALI_SRC_SEL)
return 0;
}
return parent_accuracy;
}
static const struct clk_ops ccu_iosc_32k_ops = {
.prepare = ccu_iosc_32k_prepare,
.unprepare = ccu_iosc_32k_unprepare,
.recalc_rate = ccu_iosc_32k_recalc_rate,
.recalc_accuracy = ccu_iosc_32k_recalc_accuracy,
};
static struct ccu_common iosc_32k_clk = {
.hw.init = CLK_HW_INIT_HW("iosc-32k", &iosc_clk.hw,
&ccu_iosc_32k_ops,
CLK_GET_RATE_NOCACHE),
};
static const struct clk_hw *ext_osc32k[] = { NULL }; /* updated during probe */
static SUNXI_CCU_GATE_HWS(ext_osc32k_gate_clk, "ext-osc32k-gate",
ext_osc32k, 0x0, BIT(4), 0);
static const struct clk_hw *osc32k_parents[] = {
&iosc_32k_clk.hw,
&ext_osc32k_gate_clk.common.hw
};
static struct clk_init_data osc32k_init_data = {
.name = "osc32k",
.ops = &ccu_mux_ops,
.parent_hws = osc32k_parents,
.num_parents = ARRAY_SIZE(osc32k_parents), /* updated during probe */
};
static struct ccu_mux osc32k_clk = {
.mux = _SUNXI_CCU_MUX(0, 1),
.common = {
.reg = LOSC_CTRL_REG,
.features = CCU_FEATURE_KEY_FIELD,
.hw.init = &osc32k_init_data,
},
};
/* This falls back to the global name for fwnodes without a named reference. */
static const struct clk_parent_data osc24M[] = {
{ .fw_name = "hosc", .name = "osc24M" }
};
static struct ccu_gate osc24M_32k_clk = {
.enable = BIT(16),
.common = {
.reg = LOSC_OUT_GATING_REG,
.prediv = 750,
.features = CCU_FEATURE_ALL_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS_DATA("osc24M-32k", osc24M,
&ccu_gate_ops, 0),
},
};
static const struct clk_hw *rtc_32k_parents[] = {
&osc32k_clk.common.hw,
&osc24M_32k_clk.common.hw
};
static struct clk_init_data rtc_32k_init_data = {
.name = "rtc-32k",
.ops = &ccu_mux_ops,
.parent_hws = rtc_32k_parents,
.num_parents = ARRAY_SIZE(rtc_32k_parents), /* updated during probe */
.flags = CLK_IS_CRITICAL,
};
static struct ccu_mux rtc_32k_clk = {
.mux = _SUNXI_CCU_MUX(1, 1),
.common = {
.reg = LOSC_CTRL_REG,
.features = CCU_FEATURE_KEY_FIELD,
.hw.init = &rtc_32k_init_data,
},
};
static struct clk_init_data osc32k_fanout_init_data = {
.name = "osc32k-fanout",
.ops = &ccu_mux_ops,
/* parents are set during probe */
};
static struct ccu_mux osc32k_fanout_clk = {
.enable = BIT(0),
.mux = _SUNXI_CCU_MUX(1, 2),
.common = {
.reg = LOSC_OUT_GATING_REG,
.hw.init = &osc32k_fanout_init_data,
},
};
static struct ccu_common *sun6i_rtc_ccu_clks[] = {
&iosc_clk,
&iosc_32k_clk,
&ext_osc32k_gate_clk.common,
&osc32k_clk.common,
&osc24M_32k_clk.common,
&rtc_32k_clk.common,
&osc32k_fanout_clk.common,
};
static struct clk_hw_onecell_data sun6i_rtc_ccu_hw_clks = {
.num = CLK_NUMBER,
.hws = {
[CLK_OSC32K] = &osc32k_clk.common.hw,
[CLK_OSC32K_FANOUT] = &osc32k_fanout_clk.common.hw,
[CLK_IOSC] = &iosc_clk.hw,
[CLK_IOSC_32K] = &iosc_32k_clk.hw,
[CLK_EXT_OSC32K_GATE] = &ext_osc32k_gate_clk.common.hw,
[CLK_OSC24M_32K] = &osc24M_32k_clk.common.hw,
[CLK_RTC_32K] = &rtc_32k_clk.common.hw,
},
};
static const struct sunxi_ccu_desc sun6i_rtc_ccu_desc = {
.ccu_clks = sun6i_rtc_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun6i_rtc_ccu_clks),
.hw_clks = &sun6i_rtc_ccu_hw_clks,
};
static const struct clk_parent_data sun50i_h616_osc32k_fanout_parents[] = {
{ .hw = &osc32k_clk.common.hw },
{ .fw_name = "pll-32k" },
{ .hw = &osc24M_32k_clk.common.hw }
};
static const struct clk_parent_data sun50i_r329_osc32k_fanout_parents[] = {
{ .hw = &osc32k_clk.common.hw },
{ .hw = &ext_osc32k_gate_clk.common.hw },
{ .hw = &osc24M_32k_clk.common.hw }
};
static const struct sun6i_rtc_match_data sun50i_h616_rtc_ccu_data = {
.have_iosc_calibration = true,
.rtc_32k_single_parent = true,
.osc32k_fanout_parents = sun50i_h616_osc32k_fanout_parents,
.osc32k_fanout_nparents = ARRAY_SIZE(sun50i_h616_osc32k_fanout_parents),
};
static const struct sun6i_rtc_match_data sun50i_r329_rtc_ccu_data = {
.have_ext_osc32k = true,
.osc32k_fanout_parents = sun50i_r329_osc32k_fanout_parents,
.osc32k_fanout_nparents = ARRAY_SIZE(sun50i_r329_osc32k_fanout_parents),
};
static const struct of_device_id sun6i_rtc_ccu_match[] = {
{
.compatible = "allwinner,sun50i-h616-rtc",
.data = &sun50i_h616_rtc_ccu_data,
},
{
.compatible = "allwinner,sun50i-r329-rtc",
.data = &sun50i_r329_rtc_ccu_data,
},
{},
};
int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg)
{
const struct sun6i_rtc_match_data *data;
struct clk *ext_osc32k_clk = NULL;
const struct of_device_id *match;
/* This driver is only used for newer variants of the hardware. */
match = of_match_device(sun6i_rtc_ccu_match, dev);
if (!match)
return 0;
data = match->data;
have_iosc_calibration = data->have_iosc_calibration;
if (data->have_ext_osc32k) {
const char *fw_name;
/* ext-osc32k was the only input clock in the old binding. */
fw_name = of_property_read_bool(dev->of_node, "clock-names")
? "ext-osc32k" : NULL;
ext_osc32k_clk = devm_clk_get_optional(dev, fw_name);
if (IS_ERR(ext_osc32k_clk))
return PTR_ERR(ext_osc32k_clk);
}
if (ext_osc32k_clk) {
/* Link ext-osc32k-gate to its parent. */
*ext_osc32k = __clk_get_hw(ext_osc32k_clk);
} else {
/* ext-osc32k-gate is an orphan, so do not register it. */
sun6i_rtc_ccu_hw_clks.hws[CLK_EXT_OSC32K_GATE] = NULL;
osc32k_init_data.num_parents = 1;
}
if (data->rtc_32k_single_parent)
rtc_32k_init_data.num_parents = 1;
osc32k_fanout_init_data.parent_data = data->osc32k_fanout_parents;
osc32k_fanout_init_data.num_parents = data->osc32k_fanout_nparents;
return devm_sunxi_ccu_probe(dev, reg, &sun6i_rtc_ccu_desc);
}
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun6i-rtc.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu_nkmp.h"
#include "ccu_nm.h"
#include "ccu_phase.h"
#include "ccu-sun9i-a80.h"
#define CCU_SUN9I_LOCK_REG 0x09c
/*
* The CPU PLLs are actually NP clocks, with P being /1 or /4. However
* P should only be used for output frequencies lower than 228 MHz.
* Neither mainline Linux, U-boot, nor the vendor BSPs use these.
*
* For now we can just model it as a multiplier clock, and force P to /1.
*/
#define SUN9I_A80_PLL_C0CPUX_REG 0x000
#define SUN9I_A80_PLL_C1CPUX_REG 0x004
static struct ccu_mult pll_c0cpux_clk = {
.enable = BIT(31),
.lock = BIT(0),
.mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.common = {
.reg = SUN9I_A80_PLL_C0CPUX_REG,
.lock_reg = CCU_SUN9I_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
&ccu_mult_ops,
CLK_SET_RATE_UNGATE),
},
};
static struct ccu_mult pll_c1cpux_clk = {
.enable = BIT(31),
.lock = BIT(1),
.mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.common = {
.reg = SUN9I_A80_PLL_C1CPUX_REG,
.lock_reg = CCU_SUN9I_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
&ccu_mult_ops,
CLK_SET_RATE_UNGATE),
},
};
/*
* The Audio PLL has d1, d2 dividers in addition to the usual N, M
* factors. Since we only need 2 frequencies from this PLL: 22.5792 MHz
* and 24.576 MHz, ignore them for now. Enforce d1 = 0 and d2 = 0.
*/
#define SUN9I_A80_PLL_AUDIO_REG 0x008
static struct ccu_nm pll_audio_clk = {
.enable = BIT(31),
.lock = BIT(2),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.m = _SUNXI_CCU_DIV_OFFSET(0, 6, 0),
.common = {
.reg = 0x008,
.lock_reg = CCU_SUN9I_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-audio", "osc24M",
&ccu_nm_ops, CLK_SET_RATE_UNGATE),
},
};
/* Some PLLs are input * N / div1 / div2. Model them as NKMP with no K */
static struct ccu_nkmp pll_periph0_clk = {
.enable = BIT(31),
.lock = BIT(3),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.m = _SUNXI_CCU_DIV(16, 1), /* input divider */
.p = _SUNXI_CCU_DIV(18, 1), /* output divider */
.common = {
.reg = 0x00c,
.lock_reg = CCU_SUN9I_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
static struct ccu_nkmp pll_ve_clk = {
.enable = BIT(31),
.lock = BIT(4),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.m = _SUNXI_CCU_DIV(16, 1), /* input divider */
.p = _SUNXI_CCU_DIV(18, 1), /* output divider */
.common = {
.reg = 0x010,
.lock_reg = CCU_SUN9I_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-ve", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
static struct ccu_nkmp pll_ddr_clk = {
.enable = BIT(31),
.lock = BIT(5),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.m = _SUNXI_CCU_DIV(16, 1), /* input divider */
.p = _SUNXI_CCU_DIV(18, 1), /* output divider */
.common = {
.reg = 0x014,
.lock_reg = CCU_SUN9I_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-ddr", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
static struct ccu_nm pll_video0_clk = {
.enable = BIT(31),
.lock = BIT(6),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.m = _SUNXI_CCU_DIV(16, 1), /* input divider */
.common = {
.reg = 0x018,
.lock_reg = CCU_SUN9I_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-video0", "osc24M",
&ccu_nm_ops,
CLK_SET_RATE_UNGATE),
},
};
static struct ccu_nkmp pll_video1_clk = {
.enable = BIT(31),
.lock = BIT(7),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.m = _SUNXI_CCU_DIV(16, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 2), /* external divider p */
.common = {
.reg = 0x01c,
.lock_reg = CCU_SUN9I_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-video1", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
static struct ccu_nkmp pll_gpu_clk = {
.enable = BIT(31),
.lock = BIT(8),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.m = _SUNXI_CCU_DIV(16, 1), /* input divider */
.p = _SUNXI_CCU_DIV(18, 1), /* output divider */
.common = {
.reg = 0x020,
.lock_reg = CCU_SUN9I_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
static struct ccu_nkmp pll_de_clk = {
.enable = BIT(31),
.lock = BIT(9),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.m = _SUNXI_CCU_DIV(16, 1), /* input divider */
.p = _SUNXI_CCU_DIV(18, 1), /* output divider */
.common = {
.reg = 0x024,
.lock_reg = CCU_SUN9I_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-de", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
static struct ccu_nkmp pll_isp_clk = {
.enable = BIT(31),
.lock = BIT(10),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.m = _SUNXI_CCU_DIV(16, 1), /* input divider */
.p = _SUNXI_CCU_DIV(18, 1), /* output divider */
.common = {
.reg = 0x028,
.lock_reg = CCU_SUN9I_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-isp", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
static struct ccu_nkmp pll_periph1_clk = {
.enable = BIT(31),
.lock = BIT(11),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.m = _SUNXI_CCU_DIV(16, 1), /* input divider */
.p = _SUNXI_CCU_DIV(18, 1), /* output divider */
.common = {
.reg = 0x028,
.lock_reg = CCU_SUN9I_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
static const char * const c0cpux_parents[] = { "osc24M", "pll-c0cpux" };
static SUNXI_CCU_MUX(c0cpux_clk, "c0cpux", c0cpux_parents,
0x50, 0, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
static const char * const c1cpux_parents[] = { "osc24M", "pll-c1cpux" };
static SUNXI_CCU_MUX(c1cpux_clk, "c1cpux", c1cpux_parents,
0x50, 8, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
static struct clk_div_table axi_div_table[] = {
{ .val = 0, .div = 1 },
{ .val = 1, .div = 2 },
{ .val = 2, .div = 3 },
{ .val = 3, .div = 4 },
{ .val = 4, .div = 4 },
{ .val = 5, .div = 4 },
{ .val = 6, .div = 4 },
{ .val = 7, .div = 4 },
{ /* Sentinel */ },
};
static SUNXI_CCU_M(atb0_clk, "atb0", "c0cpux", 0x054, 8, 2, 0);
static SUNXI_CCU_DIV_TABLE(axi0_clk, "axi0", "c0cpux",
0x054, 0, 3, axi_div_table, 0);
static SUNXI_CCU_M(atb1_clk, "atb1", "c1cpux", 0x058, 8, 2, 0);
static SUNXI_CCU_DIV_TABLE(axi1_clk, "axi1", "c1cpux",
0x058, 0, 3, axi_div_table, 0);
static const char * const gtbus_parents[] = { "osc24M", "pll-periph0",
"pll-periph1", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX(gtbus_clk, "gtbus", gtbus_parents,
0x05c, 0, 2, 24, 2, CLK_IS_CRITICAL);
static const char * const ahb_parents[] = { "gtbus", "pll-periph0",
"pll-periph1", "pll-periph1" };
static struct ccu_div ahb0_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0x060,
.hw.init = CLK_HW_INIT_PARENTS("ahb0",
ahb_parents,
&ccu_div_ops,
0),
},
};
static struct ccu_div ahb1_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0x064,
.hw.init = CLK_HW_INIT_PARENTS("ahb1",
ahb_parents,
&ccu_div_ops,
0),
},
};
static struct ccu_div ahb2_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0x068,
.hw.init = CLK_HW_INIT_PARENTS("ahb2",
ahb_parents,
&ccu_div_ops,
0),
},
};
static const char * const apb_parents[] = { "osc24M", "pll-periph0" };
static struct ccu_div apb0_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 1),
.common = {
.reg = 0x070,
.hw.init = CLK_HW_INIT_PARENTS("apb0",
apb_parents,
&ccu_div_ops,
0),
},
};
static struct ccu_div apb1_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 1),
.common = {
.reg = 0x074,
.hw.init = CLK_HW_INIT_PARENTS("apb1",
apb_parents,
&ccu_div_ops,
0),
},
};
static struct ccu_div cci400_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0x078,
.hw.init = CLK_HW_INIT_PARENTS("cci400",
ahb_parents,
&ccu_div_ops,
CLK_IS_CRITICAL),
},
};
static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", apb_parents,
0x080, 0, 3, 24, 2, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(trace_clk, "trace", apb_parents,
0x084, 0, 3, 24, 2, BIT(31), 0);
static const char * const out_parents[] = { "osc24M", "osc32k", "osc24M" };
static const struct ccu_mux_fixed_prediv out_prediv = {
.index = 0, .div = 750
};
static struct ccu_mp out_a_clk = {
.enable = BIT(31),
.m = _SUNXI_CCU_DIV(8, 5),
.p = _SUNXI_CCU_DIV(20, 2),
.mux = {
.shift = 24,
.width = 4,
.fixed_predivs = &out_prediv,
.n_predivs = 1,
},
.common = {
.reg = 0x180,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("out-a",
out_parents,
&ccu_mp_ops,
0),
},
};
static struct ccu_mp out_b_clk = {
.enable = BIT(31),
.m = _SUNXI_CCU_DIV(8, 5),
.p = _SUNXI_CCU_DIV(20, 2),
.mux = {
.shift = 24,
.width = 4,
.fixed_predivs = &out_prediv,
.n_predivs = 1,
},
.common = {
.reg = 0x184,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("out-b",
out_parents,
&ccu_mp_ops,
0),
},
};
static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0" };
static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_0_clk, "nand0-0", mod0_default_parents,
0x400,
0, 4, /* M */
16, 2, /* P */
24, 4, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_1_clk, "nand0-1", mod0_default_parents,
0x404,
0, 4, /* M */
16, 2, /* P */
24, 4, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_0_clk, "nand1-0", mod0_default_parents,
0x408,
0, 4, /* M */
16, 2, /* P */
24, 4, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_1_clk, "nand1-1", mod0_default_parents,
0x40c,
0, 4, /* M */
16, 2, /* P */
24, 4, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents,
0x410,
0, 4, /* M */
16, 2, /* P */
24, 4, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0-sample", "mmc0",
0x410, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0-output", "mmc0",
0x410, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents,
0x414,
0, 4, /* M */
16, 2, /* P */
24, 4, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1-sample", "mmc1",
0x414, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1-output", "mmc1",
0x414, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents,
0x418,
0, 4, /* M */
16, 2, /* P */
24, 4, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2",
0x418, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2-output", "mmc2",
0x418, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents,
0x41c,
0, 4, /* M */
16, 2, /* P */
24, 4, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3-sample", "mmc3",
0x41c, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3-output", "mmc3",
0x41c, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents,
0x428,
0, 4, /* M */
16, 2, /* P */
24, 4, /* mux */
BIT(31), /* gate */
0);
static const char * const ss_parents[] = { "osc24M", "pll-periph",
"pll-periph1" };
static const u8 ss_table[] = { 0, 1, 13 };
static struct ccu_mp ss_clk = {
.enable = BIT(31),
.m = _SUNXI_CCU_DIV(0, 4),
.p = _SUNXI_CCU_DIV(16, 2),
.mux = _SUNXI_CCU_MUX_TABLE(24, 4, ss_table),
.common = {
.reg = 0x42c,
.hw.init = CLK_HW_INIT_PARENTS("ss",
ss_parents,
&ccu_mp_ops,
0),
},
};
static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents,
0x430,
0, 4, /* M */
16, 2, /* P */
24, 4, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents,
0x434,
0, 4, /* M */
16, 2, /* P */
24, 4, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents,
0x438,
0, 4, /* M */
16, 2, /* P */
24, 4, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents,
0x43c,
0, 4, /* M */
16, 2, /* P */
24, 4, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_M_WITH_GATE(i2s0_clk, "i2s0", "pll-audio",
0x440, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(i2s1_clk, "i2s1", "pll-audio",
0x444, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
0x44c, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
static const char * const sdram_parents[] = { "pll-periph0", "pll-ddr" };
static const u8 sdram_table[] = { 0, 3 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(sdram_clk, "sdram",
sdram_parents, sdram_table,
0x484,
8, 4, /* M */
12, 4, /* mux */
0, /* no gate */
CLK_IS_CRITICAL);
static SUNXI_CCU_M_WITH_GATE(de_clk, "de", "pll-de", 0x490,
0, 4, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(edp_clk, "edp", "osc24M", 0x494, BIT(31), 0);
static const char * const mp_parents[] = { "pll-video1", "pll-gpu", "pll-de" };
static const u8 mp_table[] = { 9, 10, 11 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mp_clk, "mp", mp_parents, mp_table,
0x498,
0, 4, /* M */
24, 4, /* mux */
BIT(31), /* gate */
0);
static const char * const display_parents[] = { "pll-video0", "pll-video1" };
static const u8 display_table[] = { 8, 9 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd0_clk, "lcd0",
display_parents, display_table,
0x49c,
0, 4, /* M */
24, 4, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_NO_REPARENT |
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd1_clk, "lcd1",
display_parents, display_table,
0x4a0,
0, 4, /* M */
24, 4, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_NO_REPARENT |
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi0_clk, "mipi-dsi0",
display_parents, display_table,
0x4a8,
0, 4, /* M */
24, 4, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static const char * const mipi_dsi1_parents[] = { "osc24M", "pll-video1" };
static const u8 mipi_dsi1_table[] = { 0, 9 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi1_clk, "mipi-dsi1",
mipi_dsi1_parents, mipi_dsi1_table,
0x4ac,
0, 4, /* M */
24, 4, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(hdmi_clk, "hdmi",
display_parents, display_table,
0x4b0,
0, 4, /* M */
24, 4, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_NO_REPARENT |
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0x4b4, BIT(31), 0);
static SUNXI_CCU_M_WITH_GATE(mipi_csi_clk, "mipi-csi", "osc24M", 0x4bc,
0, 4, BIT(31), 0);
static SUNXI_CCU_M_WITH_GATE(csi_isp_clk, "csi-isp", "pll-isp", 0x4c0,
0, 4, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x4c0, BIT(16), 0);
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi0_mclk_clk, "csi0-mclk",
mipi_dsi1_parents, mipi_dsi1_table,
0x4c4,
0, 4, /* M */
24, 4, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi1_mclk_clk, "csi1-mclk",
mipi_dsi1_parents, mipi_dsi1_table,
0x4c8,
0, 4, /* M */
24, 4, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static const char * const fd_parents[] = { "pll-periph0", "pll-isp" };
static const u8 fd_table[] = { 1, 12 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(fd_clk, "fd", fd_parents, fd_table,
0x4cc,
0, 4, /* M */
24, 4, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x4d0,
16, 3, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x4d4, BIT(31), 0);
static SUNXI_CCU_M_WITH_GATE(gpu_core_clk, "gpu-core", "pll-gpu", 0x4f0,
0, 3, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(gpu_memory_clk, "gpu-memory", "pll-gpu", 0x4f4,
0, 3, BIT(31), CLK_SET_RATE_PARENT);
static const char * const gpu_axi_parents[] = { "pll-periph0", "pll-gpu" };
static const u8 gpu_axi_table[] = { 1, 10 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(gpu_axi_clk, "gpu-axi",
gpu_axi_parents, gpu_axi_table,
0x4f8,
0, 4, /* M */
24, 4, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(sata_clk, "sata", "pll-periph0", 0x500,
0, 4, BIT(31), 0);
static SUNXI_CCU_M_WITH_GATE(ac97_clk, "ac97", "pll-audio",
0x504, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_GATE(mipi_hsi_clk, "mipi-hsi",
mod0_default_parents, 0x508,
0, 4, /* M */
24, 4, /* mux */
BIT(31), /* gate */
0);
static const char * const gpadc_parents[] = { "osc24M", "pll-audio", "osc32k" };
static const u8 gpadc_table[] = { 0, 4, 7 };
static struct ccu_mp gpadc_clk = {
.enable = BIT(31),
.m = _SUNXI_CCU_DIV(0, 4),
.p = _SUNXI_CCU_DIV(16, 2),
.mux = _SUNXI_CCU_MUX_TABLE(24, 4, gpadc_table),
.common = {
.reg = 0x50c,
.hw.init = CLK_HW_INIT_PARENTS("gpadc",
gpadc_parents,
&ccu_mp_ops,
0),
},
};
static const char * const cir_tx_parents[] = { "osc24M", "osc32k" };
static const u8 cir_tx_table[] = { 0, 7 };
static struct ccu_mp cir_tx_clk = {
.enable = BIT(31),
.m = _SUNXI_CCU_DIV(0, 4),
.p = _SUNXI_CCU_DIV(16, 2),
.mux = _SUNXI_CCU_MUX_TABLE(24, 4, cir_tx_table),
.common = {
.reg = 0x510,
.hw.init = CLK_HW_INIT_PARENTS("cir-tx",
cir_tx_parents,
&ccu_mp_ops,
0),
},
};
/* AHB0 bus gates */
static SUNXI_CCU_GATE(bus_fd_clk, "bus-fd", "ahb0",
0x580, BIT(0), 0);
static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb0",
0x580, BIT(1), 0);
static SUNXI_CCU_GATE(bus_gpu_ctrl_clk, "bus-gpu-ctrl", "ahb0",
0x580, BIT(3), 0);
static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb0",
0x580, BIT(5), 0);
static SUNXI_CCU_GATE(bus_mmc_clk, "bus-mmc", "ahb0",
0x580, BIT(8), 0);
static SUNXI_CCU_GATE(bus_nand0_clk, "bus-nand0", "ahb0",
0x580, BIT(12), 0);
static SUNXI_CCU_GATE(bus_nand1_clk, "bus-nand1", "ahb0",
0x580, BIT(13), 0);
static SUNXI_CCU_GATE(bus_sdram_clk, "bus-sdram", "ahb0",
0x580, BIT(14), 0);
static SUNXI_CCU_GATE(bus_mipi_hsi_clk, "bus-mipi-hsi", "ahb0",
0x580, BIT(15), 0);
static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb0",
0x580, BIT(16), 0);
static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb0",
0x580, BIT(18), 0);
static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb0",
0x580, BIT(20), 0);
static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb0",
0x580, BIT(21), 0);
static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb0",
0x580, BIT(22), 0);
static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb0",
0x580, BIT(23), 0);
/* AHB1 bus gates */
static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
0x584, BIT(0), 0);
static SUNXI_CCU_GATE(bus_usb_clk, "bus-usb", "ahb1",
0x584, BIT(1), 0);
static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1",
0x584, BIT(17), 0);
static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
0x584, BIT(21), 0);
static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
0x584, BIT(22), 0);
static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
0x584, BIT(23), 0);
static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
0x584, BIT(24), 0);
/* AHB2 bus gates */
static SUNXI_CCU_GATE(bus_lcd0_clk, "bus-lcd0", "ahb2",
0x588, BIT(0), 0);
static SUNXI_CCU_GATE(bus_lcd1_clk, "bus-lcd1", "ahb2",
0x588, BIT(1), 0);
static SUNXI_CCU_GATE(bus_edp_clk, "bus-edp", "ahb2",
0x588, BIT(2), 0);
static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb2",
0x588, BIT(4), 0);
static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb2",
0x588, BIT(5), 0);
static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb2",
0x588, BIT(7), 0);
static SUNXI_CCU_GATE(bus_mp_clk, "bus-mp", "ahb2",
0x588, BIT(8), 0);
static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb2",
0x588, BIT(11), 0);
/* APB0 bus gates */
static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb0",
0x590, BIT(1), 0);
static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb0",
0x590, BIT(5), 0);
static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb0",
0x590, BIT(11), 0);
static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb0",
0x590, BIT(12), 0);
static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb0",
0x590, BIT(13), 0);
static SUNXI_CCU_GATE(bus_lradc_clk, "bus-lradc", "apb0",
0x590, BIT(15), 0);
static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb0",
0x590, BIT(17), 0);
static SUNXI_CCU_GATE(bus_twd_clk, "bus-twd", "apb0",
0x590, BIT(18), 0);
static SUNXI_CCU_GATE(bus_cir_tx_clk, "bus-cir-tx", "apb0",
0x590, BIT(19), 0);
/* APB1 bus gates */
static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb1",
0x594, BIT(0), 0);
static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb1",
0x594, BIT(1), 0);
static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb1",
0x594, BIT(2), 0);
static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb1",
0x594, BIT(3), 0);
static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb1",
0x594, BIT(4), 0);
static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb1",
0x594, BIT(16), 0);
static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb1",
0x594, BIT(17), 0);
static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb1",
0x594, BIT(18), 0);
static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb1",
0x594, BIT(19), 0);
static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb1",
0x594, BIT(20), 0);
static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb1",
0x594, BIT(21), 0);
static struct ccu_common *sun9i_a80_ccu_clks[] = {
&pll_c0cpux_clk.common,
&pll_c1cpux_clk.common,
&pll_audio_clk.common,
&pll_periph0_clk.common,
&pll_ve_clk.common,
&pll_ddr_clk.common,
&pll_video0_clk.common,
&pll_video1_clk.common,
&pll_gpu_clk.common,
&pll_de_clk.common,
&pll_isp_clk.common,
&pll_periph1_clk.common,
&c0cpux_clk.common,
&c1cpux_clk.common,
&atb0_clk.common,
&axi0_clk.common,
&atb1_clk.common,
&axi1_clk.common,
>bus_clk.common,
&ahb0_clk.common,
&ahb1_clk.common,
&ahb2_clk.common,
&apb0_clk.common,
&apb1_clk.common,
&cci400_clk.common,
&ats_clk.common,
&trace_clk.common,
&out_a_clk.common,
&out_b_clk.common,
/* module clocks */
&nand0_0_clk.common,
&nand0_1_clk.common,
&nand1_0_clk.common,
&nand1_1_clk.common,
&mmc0_clk.common,
&mmc0_sample_clk.common,
&mmc0_output_clk.common,
&mmc1_clk.common,
&mmc1_sample_clk.common,
&mmc1_output_clk.common,
&mmc2_clk.common,
&mmc2_sample_clk.common,
&mmc2_output_clk.common,
&mmc3_clk.common,
&mmc3_sample_clk.common,
&mmc3_output_clk.common,
&ts_clk.common,
&ss_clk.common,
&spi0_clk.common,
&spi1_clk.common,
&spi2_clk.common,
&spi3_clk.common,
&i2s0_clk.common,
&i2s1_clk.common,
&spdif_clk.common,
&sdram_clk.common,
&de_clk.common,
&edp_clk.common,
&mp_clk.common,
&lcd0_clk.common,
&lcd1_clk.common,
&mipi_dsi0_clk.common,
&mipi_dsi1_clk.common,
&hdmi_clk.common,
&hdmi_slow_clk.common,
&mipi_csi_clk.common,
&csi_isp_clk.common,
&csi_misc_clk.common,
&csi0_mclk_clk.common,
&csi1_mclk_clk.common,
&fd_clk.common,
&ve_clk.common,
&avs_clk.common,
&gpu_core_clk.common,
&gpu_memory_clk.common,
&gpu_axi_clk.common,
&sata_clk.common,
&ac97_clk.common,
&mipi_hsi_clk.common,
&gpadc_clk.common,
&cir_tx_clk.common,
/* AHB0 bus gates */
&bus_fd_clk.common,
&bus_ve_clk.common,
&bus_gpu_ctrl_clk.common,
&bus_ss_clk.common,
&bus_mmc_clk.common,
&bus_nand0_clk.common,
&bus_nand1_clk.common,
&bus_sdram_clk.common,
&bus_mipi_hsi_clk.common,
&bus_sata_clk.common,
&bus_ts_clk.common,
&bus_spi0_clk.common,
&bus_spi1_clk.common,
&bus_spi2_clk.common,
&bus_spi3_clk.common,
/* AHB1 bus gates */
&bus_otg_clk.common,
&bus_usb_clk.common,
&bus_gmac_clk.common,
&bus_msgbox_clk.common,
&bus_spinlock_clk.common,
&bus_hstimer_clk.common,
&bus_dma_clk.common,
/* AHB2 bus gates */
&bus_lcd0_clk.common,
&bus_lcd1_clk.common,
&bus_edp_clk.common,
&bus_csi_clk.common,
&bus_hdmi_clk.common,
&bus_de_clk.common,
&bus_mp_clk.common,
&bus_mipi_dsi_clk.common,
/* APB0 bus gates */
&bus_spdif_clk.common,
&bus_pio_clk.common,
&bus_ac97_clk.common,
&bus_i2s0_clk.common,
&bus_i2s1_clk.common,
&bus_lradc_clk.common,
&bus_gpadc_clk.common,
&bus_twd_clk.common,
&bus_cir_tx_clk.common,
/* APB1 bus gates */
&bus_i2c0_clk.common,
&bus_i2c1_clk.common,
&bus_i2c2_clk.common,
&bus_i2c3_clk.common,
&bus_i2c4_clk.common,
&bus_uart0_clk.common,
&bus_uart1_clk.common,
&bus_uart2_clk.common,
&bus_uart3_clk.common,
&bus_uart4_clk.common,
&bus_uart5_clk.common,
};
static struct clk_hw_onecell_data sun9i_a80_hw_clks = {
.hws = {
[CLK_PLL_C0CPUX] = &pll_c0cpux_clk.common.hw,
[CLK_PLL_C1CPUX] = &pll_c1cpux_clk.common.hw,
[CLK_PLL_AUDIO] = &pll_audio_clk.common.hw,
[CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
[CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
[CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
[CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
[CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
[CLK_PLL_DE] = &pll_de_clk.common.hw,
[CLK_PLL_ISP] = &pll_isp_clk.common.hw,
[CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
[CLK_C0CPUX] = &c0cpux_clk.common.hw,
[CLK_C1CPUX] = &c1cpux_clk.common.hw,
[CLK_ATB0] = &atb0_clk.common.hw,
[CLK_AXI0] = &axi0_clk.common.hw,
[CLK_ATB1] = &atb1_clk.common.hw,
[CLK_AXI1] = &axi1_clk.common.hw,
[CLK_GTBUS] = >bus_clk.common.hw,
[CLK_AHB0] = &ahb0_clk.common.hw,
[CLK_AHB1] = &ahb1_clk.common.hw,
[CLK_AHB2] = &ahb2_clk.common.hw,
[CLK_APB0] = &apb0_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_CCI400] = &cci400_clk.common.hw,
[CLK_ATS] = &ats_clk.common.hw,
[CLK_TRACE] = &trace_clk.common.hw,
[CLK_OUT_A] = &out_a_clk.common.hw,
[CLK_OUT_B] = &out_b_clk.common.hw,
[CLK_NAND0_0] = &nand0_0_clk.common.hw,
[CLK_NAND0_1] = &nand0_1_clk.common.hw,
[CLK_NAND1_0] = &nand1_0_clk.common.hw,
[CLK_NAND1_1] = &nand1_1_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
[CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
[CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
[CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
[CLK_MMC3] = &mmc3_clk.common.hw,
[CLK_MMC3_SAMPLE] = &mmc3_sample_clk.common.hw,
[CLK_MMC3_OUTPUT] = &mmc3_output_clk.common.hw,
[CLK_TS] = &ts_clk.common.hw,
[CLK_SS] = &ss_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI2] = &spi2_clk.common.hw,
[CLK_SPI3] = &spi3_clk.common.hw,
[CLK_I2S0] = &i2s0_clk.common.hw,
[CLK_I2S1] = &i2s1_clk.common.hw,
[CLK_SPDIF] = &spdif_clk.common.hw,
[CLK_SDRAM] = &sdram_clk.common.hw,
[CLK_DE] = &de_clk.common.hw,
[CLK_EDP] = &edp_clk.common.hw,
[CLK_MP] = &mp_clk.common.hw,
[CLK_LCD0] = &lcd0_clk.common.hw,
[CLK_LCD1] = &lcd1_clk.common.hw,
[CLK_MIPI_DSI0] = &mipi_dsi0_clk.common.hw,
[CLK_MIPI_DSI1] = &mipi_dsi1_clk.common.hw,
[CLK_HDMI] = &hdmi_clk.common.hw,
[CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw,
[CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
[CLK_CSI_ISP] = &csi_isp_clk.common.hw,
[CLK_CSI_MISC] = &csi_misc_clk.common.hw,
[CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
[CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
[CLK_FD] = &fd_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_GPU_CORE] = &gpu_core_clk.common.hw,
[CLK_GPU_MEMORY] = &gpu_memory_clk.common.hw,
[CLK_GPU_AXI] = &gpu_axi_clk.common.hw,
[CLK_SATA] = &sata_clk.common.hw,
[CLK_AC97] = &ac97_clk.common.hw,
[CLK_MIPI_HSI] = &mipi_hsi_clk.common.hw,
[CLK_GPADC] = &gpadc_clk.common.hw,
[CLK_CIR_TX] = &cir_tx_clk.common.hw,
[CLK_BUS_FD] = &bus_fd_clk.common.hw,
[CLK_BUS_VE] = &bus_ve_clk.common.hw,
[CLK_BUS_GPU_CTRL] = &bus_gpu_ctrl_clk.common.hw,
[CLK_BUS_SS] = &bus_ss_clk.common.hw,
[CLK_BUS_MMC] = &bus_mmc_clk.common.hw,
[CLK_BUS_NAND0] = &bus_nand0_clk.common.hw,
[CLK_BUS_NAND1] = &bus_nand1_clk.common.hw,
[CLK_BUS_SDRAM] = &bus_sdram_clk.common.hw,
[CLK_BUS_MIPI_HSI] = &bus_mipi_hsi_clk.common.hw,
[CLK_BUS_SATA] = &bus_sata_clk.common.hw,
[CLK_BUS_TS] = &bus_ts_clk.common.hw,
[CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
[CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
[CLK_BUS_SPI2] = &bus_spi2_clk.common.hw,
[CLK_BUS_SPI3] = &bus_spi3_clk.common.hw,
[CLK_BUS_OTG] = &bus_otg_clk.common.hw,
[CLK_BUS_USB] = &bus_usb_clk.common.hw,
[CLK_BUS_GMAC] = &bus_gmac_clk.common.hw,
[CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
[CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
[CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
[CLK_BUS_DMA] = &bus_dma_clk.common.hw,
[CLK_BUS_LCD0] = &bus_lcd0_clk.common.hw,
[CLK_BUS_LCD1] = &bus_lcd1_clk.common.hw,
[CLK_BUS_EDP] = &bus_edp_clk.common.hw,
[CLK_BUS_CSI] = &bus_csi_clk.common.hw,
[CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
[CLK_BUS_DE] = &bus_de_clk.common.hw,
[CLK_BUS_MP] = &bus_mp_clk.common.hw,
[CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
[CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
[CLK_BUS_PIO] = &bus_pio_clk.common.hw,
[CLK_BUS_AC97] = &bus_ac97_clk.common.hw,
[CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
[CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
[CLK_BUS_LRADC] = &bus_lradc_clk.common.hw,
[CLK_BUS_GPADC] = &bus_gpadc_clk.common.hw,
[CLK_BUS_TWD] = &bus_twd_clk.common.hw,
[CLK_BUS_CIR_TX] = &bus_cir_tx_clk.common.hw,
[CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
[CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
[CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
[CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
[CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw,
[CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
[CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
[CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
[CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
[CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
[CLK_BUS_UART5] = &bus_uart5_clk.common.hw,
},
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun9i_a80_ccu_resets[] = {
/* AHB0 reset controls */
[RST_BUS_FD] = { 0x5a0, BIT(0) },
[RST_BUS_VE] = { 0x5a0, BIT(1) },
[RST_BUS_GPU_CTRL] = { 0x5a0, BIT(3) },
[RST_BUS_SS] = { 0x5a0, BIT(5) },
[RST_BUS_MMC] = { 0x5a0, BIT(8) },
[RST_BUS_NAND0] = { 0x5a0, BIT(12) },
[RST_BUS_NAND1] = { 0x5a0, BIT(13) },
[RST_BUS_SDRAM] = { 0x5a0, BIT(14) },
[RST_BUS_SATA] = { 0x5a0, BIT(16) },
[RST_BUS_TS] = { 0x5a0, BIT(18) },
[RST_BUS_SPI0] = { 0x5a0, BIT(20) },
[RST_BUS_SPI1] = { 0x5a0, BIT(21) },
[RST_BUS_SPI2] = { 0x5a0, BIT(22) },
[RST_BUS_SPI3] = { 0x5a0, BIT(23) },
/* AHB1 reset controls */
[RST_BUS_OTG] = { 0x5a4, BIT(0) },
[RST_BUS_OTG_PHY] = { 0x5a4, BIT(1) },
[RST_BUS_MIPI_HSI] = { 0x5a4, BIT(9) },
[RST_BUS_GMAC] = { 0x5a4, BIT(17) },
[RST_BUS_MSGBOX] = { 0x5a4, BIT(21) },
[RST_BUS_SPINLOCK] = { 0x5a4, BIT(22) },
[RST_BUS_HSTIMER] = { 0x5a4, BIT(23) },
[RST_BUS_DMA] = { 0x5a4, BIT(24) },
/* AHB2 reset controls */
[RST_BUS_LCD0] = { 0x5a8, BIT(0) },
[RST_BUS_LCD1] = { 0x5a8, BIT(1) },
[RST_BUS_EDP] = { 0x5a8, BIT(2) },
[RST_BUS_LVDS] = { 0x5a8, BIT(3) },
[RST_BUS_CSI] = { 0x5a8, BIT(4) },
[RST_BUS_HDMI0] = { 0x5a8, BIT(5) },
[RST_BUS_HDMI1] = { 0x5a8, BIT(6) },
[RST_BUS_DE] = { 0x5a8, BIT(7) },
[RST_BUS_MP] = { 0x5a8, BIT(8) },
[RST_BUS_GPU] = { 0x5a8, BIT(9) },
[RST_BUS_MIPI_DSI] = { 0x5a8, BIT(11) },
/* APB0 reset controls */
[RST_BUS_SPDIF] = { 0x5b0, BIT(1) },
[RST_BUS_AC97] = { 0x5b0, BIT(11) },
[RST_BUS_I2S0] = { 0x5b0, BIT(12) },
[RST_BUS_I2S1] = { 0x5b0, BIT(13) },
[RST_BUS_LRADC] = { 0x5b0, BIT(15) },
[RST_BUS_GPADC] = { 0x5b0, BIT(17) },
[RST_BUS_CIR_TX] = { 0x5b0, BIT(19) },
/* APB1 reset controls */
[RST_BUS_I2C0] = { 0x5b4, BIT(0) },
[RST_BUS_I2C1] = { 0x5b4, BIT(1) },
[RST_BUS_I2C2] = { 0x5b4, BIT(2) },
[RST_BUS_I2C3] = { 0x5b4, BIT(3) },
[RST_BUS_I2C4] = { 0x5b4, BIT(4) },
[RST_BUS_UART0] = { 0x5b4, BIT(16) },
[RST_BUS_UART1] = { 0x5b4, BIT(17) },
[RST_BUS_UART2] = { 0x5b4, BIT(18) },
[RST_BUS_UART3] = { 0x5b4, BIT(19) },
[RST_BUS_UART4] = { 0x5b4, BIT(20) },
[RST_BUS_UART5] = { 0x5b4, BIT(21) },
};
static const struct sunxi_ccu_desc sun9i_a80_ccu_desc = {
.ccu_clks = sun9i_a80_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun9i_a80_ccu_clks),
.hw_clks = &sun9i_a80_hw_clks,
.resets = sun9i_a80_ccu_resets,
.num_resets = ARRAY_SIZE(sun9i_a80_ccu_resets),
};
#define SUN9I_A80_PLL_P_SHIFT 16
#define SUN9I_A80_PLL_N_SHIFT 8
#define SUN9I_A80_PLL_N_WIDTH 8
static void sun9i_a80_cpu_pll_fixup(void __iomem *reg)
{
u32 val = readl(reg);
/* bail out if P divider is not used */
if (!(val & BIT(SUN9I_A80_PLL_P_SHIFT)))
return;
/*
* If P is used, output should be less than 288 MHz. When we
* set P to 1, we should also decrease the multiplier so the
* output doesn't go out of range, but not too much such that
* the multiplier stays above 12, the minimal operation value.
*
* To keep it simple, set the multiplier to 17, the reset value.
*/
val &= ~GENMASK(SUN9I_A80_PLL_N_SHIFT + SUN9I_A80_PLL_N_WIDTH - 1,
SUN9I_A80_PLL_N_SHIFT);
val |= 17 << SUN9I_A80_PLL_N_SHIFT;
/* And clear P */
val &= ~BIT(SUN9I_A80_PLL_P_SHIFT);
writel(val, reg);
}
static int sun9i_a80_ccu_probe(struct platform_device *pdev)
{
void __iomem *reg;
u32 val;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
/* Enforce d1 = 0, d2 = 0 for Audio PLL */
val = readl(reg + SUN9I_A80_PLL_AUDIO_REG);
val &= ~(BIT(16) | BIT(18));
writel(val, reg + SUN9I_A80_PLL_AUDIO_REG);
/* Enforce P = 1 for both CPU cluster PLLs */
sun9i_a80_cpu_pll_fixup(reg + SUN9I_A80_PLL_C0CPUX_REG);
sun9i_a80_cpu_pll_fixup(reg + SUN9I_A80_PLL_C1CPUX_REG);
return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun9i_a80_ccu_desc);
}
static const struct of_device_id sun9i_a80_ccu_ids[] = {
{ .compatible = "allwinner,sun9i-a80-ccu" },
{ }
};
static struct platform_driver sun9i_a80_ccu_driver = {
.probe = sun9i_a80_ccu_probe,
.driver = {
.name = "sun9i-a80-ccu",
.suppress_bind_attrs = true,
.of_match_table = sun9i_a80_ccu_ids,
},
};
module_platform_driver(sun9i_a80_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun9i-a80.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016 Icenowy Zheng <[email protected]>
*
* Based on ccu-sun8i-h3.c, which is:
* Copyright (c) 2016 Maxime Ripard. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu_mult.h"
#include "ccu_nk.h"
#include "ccu_nkm.h"
#include "ccu_nkmp.h"
#include "ccu_nm.h"
#include "ccu_phase.h"
#include "ccu-sun8i-v3s.h"
static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
"osc24M", 0x000,
8, 5, /* N */
4, 2, /* K */
0, 2, /* M */
16, 2, /* P */
BIT(31), /* gate */
BIT(28), /* lock */
0);
/*
* The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
* the base (2x, 4x and 8x), and one variable divider (the one true
* pll audio).
*
* With sigma-delta modulation for fractional-N on the audio PLL,
* we have to use specific dividers. This means the variable divider
* can no longer be used, as the audio codec requests the exact clock
* rates we support through this mechanism. So we now hard code the
* variable divider to 1. This means the clock rates will no longer
* match the clock names.
*/
#define SUN8I_V3S_PLL_AUDIO_REG 0x008
static struct ccu_sdm_setting pll_audio_sdm_table[] = {
{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
};
static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
"osc24M", 0x008,
8, 7, /* N */
0, 5, /* M */
pll_audio_sdm_table, BIT(24),
0x284, BIT(31),
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
"osc24M", 0x0010,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
0);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
"osc24M", 0x0018,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
0);
static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
"osc24M", 0x020,
8, 5, /* N */
4, 2, /* K */
0, 2, /* M */
BIT(31), /* gate */
BIT(28), /* lock */
0);
static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
"osc24M", 0x028,
8, 5, /* N */
4, 2, /* K */
BIT(31), /* gate */
BIT(28), /* lock */
2, /* post-div */
0);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_isp_clk, "pll-isp",
"osc24M", 0x002c,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
0);
static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
"osc24M", 0x044,
8, 5, /* N */
4, 2, /* K */
BIT(31), /* gate */
BIT(28), /* lock */
2, /* post-div */
0);
static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
"osc24M", 0x04c,
8, 7, /* N */
0, 2, /* M */
BIT(31), /* gate */
BIT(28), /* lock */
0);
static const char * const cpu_parents[] = { "osc32k", "osc24M",
"pll-cpu", "pll-cpu" };
static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
0x050, 16, 2, CLK_IS_CRITICAL);
static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0);
static const char * const ahb1_parents[] = { "osc32k", "osc24M",
"axi", "pll-periph0" };
static const struct ccu_mux_var_prediv ahb1_predivs[] = {
{ .index = 3, .shift = 6, .width = 2 },
};
static struct ccu_div ahb1_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = {
.shift = 12,
.width = 2,
.var_predivs = ahb1_predivs,
.n_var_predivs = ARRAY_SIZE(ahb1_predivs),
},
.common = {
.reg = 0x054,
.features = CCU_FEATURE_VARIABLE_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("ahb1",
ahb1_parents,
&ccu_div_ops,
0),
},
};
static struct clk_div_table apb1_div_table[] = {
{ .val = 0, .div = 2 },
{ .val = 1, .div = 2 },
{ .val = 2, .div = 4 },
{ .val = 3, .div = 8 },
{ /* Sentinel */ },
};
static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
0x054, 8, 2, apb1_div_table, 0);
static const char * const apb2_parents[] = { "osc32k", "osc24M",
"pll-periph0", "pll-periph0" };
static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
0, 5, /* M */
16, 2, /* P */
24, 2, /* mux */
0);
static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
{ .index = 1, .div = 2 },
};
static struct ccu_mux ahb2_clk = {
.mux = {
.shift = 0,
.width = 1,
.fixed_predivs = ahb2_fixed_predivs,
.n_predivs = ARRAY_SIZE(ahb2_fixed_predivs),
},
.common = {
.reg = 0x05c,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("ahb2",
ahb2_parents,
&ccu_mux_ops,
0),
},
};
static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
0x060, BIT(5), 0);
static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
0x060, BIT(6), 0);
static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
0x060, BIT(8), 0);
static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
0x060, BIT(9), 0);
static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
0x060, BIT(10), 0);
static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
0x060, BIT(14), 0);
static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
0x060, BIT(17), 0);
static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
0x060, BIT(19), 0);
static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
0x060, BIT(20), 0);
static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
0x060, BIT(24), 0);
static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
0x060, BIT(26), 0);
static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
0x060, BIT(29), 0);
static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
0x064, BIT(0), 0);
static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
0x064, BIT(4), 0);
static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
0x064, BIT(8), 0);
static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
0x064, BIT(12), 0);
static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
0x068, BIT(0), 0);
static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
0x068, BIT(5), 0);
static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
0x068, BIT(12), 0);
static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
0x06c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
0x06c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
0x06c, BIT(16), 0);
static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
0x06c, BIT(17), 0);
static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
0x06c, BIT(18), 0);
static SUNXI_CCU_GATE(bus_ephy_clk, "bus-ephy", "ahb1",
0x070, BIT(0), 0);
static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
0x070, BIT(7), 0);
static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
"pll-periph1" };
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
0x088, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
0x088, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
0x08c, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
0x08c, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
0x090, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
0x090, 8, 3, 0);
static const char * const ce_parents[] = { "osc24M", "pll-periph0", };
static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
"pll-audio-2x", "pll-audio" };
static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
0x0cc, BIT(8), 0);
static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
0x0cc, BIT(16), 0);
static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1",
"pll-periph0-2x" };
static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
0x100, BIT(0), 0);
static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
0x100, BIT(1), 0);
static SUNXI_CCU_GATE(dram_ehci_clk, "dram-ehci", "dram",
0x100, BIT(17), 0);
static SUNXI_CCU_GATE(dram_ohci_clk, "dram-ohci", "dram",
0x100, BIT(18), 0);
static const char * const de_parents[] = { "pll-video", "pll-periph0" };
static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
0x104, 0, 4, 24, 2, BIT(31),
CLK_SET_RATE_PARENT);
static const char * const tcon_parents[] = { "pll-video" };
static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
0x118, 0, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
0x130, BIT(31), 0);
static const char * const csi_mclk_parents[] = { "osc24M", "pll-video",
"pll-periph0", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents,
0x130, 0, 5, 8, 3, BIT(15), 0);
static const char * const csi1_sclk_parents[] = { "pll-video", "pll-isp" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi1_sclk_clk, "csi-sclk", csi1_sclk_parents,
0x134, 16, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi-mclk", csi_mclk_parents,
0x134, 0, 5, 8, 3, BIT(15), 0);
static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
0x13c, 16, 3, BIT(31), 0);
static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
0x140, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
0x144, BIT(31), 0);
static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
"pll-ddr" };
static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
static const char * const mipi_csi_parents[] = { "pll-video", "pll-periph0",
"pll-isp" };
static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_clk, "mipi-csi", mipi_csi_parents,
0x16c, 0, 3, 24, 2, BIT(31), 0);
static struct ccu_common *sun8i_v3s_ccu_clks[] = {
&pll_cpu_clk.common,
&pll_audio_base_clk.common,
&pll_video_clk.common,
&pll_ve_clk.common,
&pll_ddr0_clk.common,
&pll_periph0_clk.common,
&pll_isp_clk.common,
&pll_periph1_clk.common,
&pll_ddr1_clk.common,
&cpu_clk.common,
&axi_clk.common,
&ahb1_clk.common,
&apb1_clk.common,
&apb2_clk.common,
&ahb2_clk.common,
&bus_ce_clk.common,
&bus_dma_clk.common,
&bus_mmc0_clk.common,
&bus_mmc1_clk.common,
&bus_mmc2_clk.common,
&bus_dram_clk.common,
&bus_emac_clk.common,
&bus_hstimer_clk.common,
&bus_spi0_clk.common,
&bus_otg_clk.common,
&bus_ehci0_clk.common,
&bus_ohci0_clk.common,
&bus_ve_clk.common,
&bus_tcon0_clk.common,
&bus_csi_clk.common,
&bus_de_clk.common,
&bus_codec_clk.common,
&bus_pio_clk.common,
&bus_i2s0_clk.common,
&bus_i2c0_clk.common,
&bus_i2c1_clk.common,
&bus_uart0_clk.common,
&bus_uart1_clk.common,
&bus_uart2_clk.common,
&bus_ephy_clk.common,
&bus_dbg_clk.common,
&mmc0_clk.common,
&mmc0_sample_clk.common,
&mmc0_output_clk.common,
&mmc1_clk.common,
&mmc1_sample_clk.common,
&mmc1_output_clk.common,
&mmc2_clk.common,
&mmc2_sample_clk.common,
&mmc2_output_clk.common,
&ce_clk.common,
&spi0_clk.common,
&i2s0_clk.common,
&usb_phy0_clk.common,
&usb_ohci0_clk.common,
&dram_clk.common,
&dram_ve_clk.common,
&dram_csi_clk.common,
&dram_ohci_clk.common,
&dram_ehci_clk.common,
&de_clk.common,
&tcon_clk.common,
&csi_misc_clk.common,
&csi0_mclk_clk.common,
&csi1_sclk_clk.common,
&csi1_mclk_clk.common,
&ve_clk.common,
&ac_dig_clk.common,
&avs_clk.common,
&mbus_clk.common,
&mipi_csi_clk.common,
};
static const struct clk_hw *clk_parent_pll_audio[] = {
&pll_audio_base_clk.common.hw
};
/* We hardcode the divider to 1 for SDM support */
static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
clk_parent_pll_audio,
1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
clk_parent_pll_audio,
2, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
clk_parent_pll_audio,
1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
clk_parent_pll_audio,
1, 2, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
&pll_periph0_clk.common.hw,
1, 2, 0);
static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
.hws = {
[CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
[CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
[CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
[CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
[CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
[CLK_PLL_ISP] = &pll_isp_clk.common.hw,
[CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
[CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
[CLK_CPU] = &cpu_clk.common.hw,
[CLK_AXI] = &axi_clk.common.hw,
[CLK_AHB1] = &ahb1_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_APB2] = &apb2_clk.common.hw,
[CLK_AHB2] = &ahb2_clk.common.hw,
[CLK_BUS_CE] = &bus_ce_clk.common.hw,
[CLK_BUS_DMA] = &bus_dma_clk.common.hw,
[CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
[CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
[CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
[CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
[CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
[CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
[CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
[CLK_BUS_OTG] = &bus_otg_clk.common.hw,
[CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
[CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
[CLK_BUS_VE] = &bus_ve_clk.common.hw,
[CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
[CLK_BUS_CSI] = &bus_csi_clk.common.hw,
[CLK_BUS_DE] = &bus_de_clk.common.hw,
[CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
[CLK_BUS_PIO] = &bus_pio_clk.common.hw,
[CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
[CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
[CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
[CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
[CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
[CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
[CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
[CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
[CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
[CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
[CLK_CE] = &ce_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
[CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
[CLK_DRAM] = &dram_clk.common.hw,
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
[CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
[CLK_DRAM_EHCI] = &dram_ehci_clk.common.hw,
[CLK_DRAM_OHCI] = &dram_ohci_clk.common.hw,
[CLK_DE] = &de_clk.common.hw,
[CLK_TCON0] = &tcon_clk.common.hw,
[CLK_CSI_MISC] = &csi_misc_clk.common.hw,
[CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
[CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw,
[CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_AC_DIG] = &ac_dig_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_MBUS] = &mbus_clk.common.hw,
[CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
},
.num = CLK_PLL_DDR1 + 1,
};
static struct clk_hw_onecell_data sun8i_v3_hw_clks = {
.hws = {
[CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
[CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
[CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
[CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
[CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
[CLK_PLL_ISP] = &pll_isp_clk.common.hw,
[CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
[CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
[CLK_CPU] = &cpu_clk.common.hw,
[CLK_AXI] = &axi_clk.common.hw,
[CLK_AHB1] = &ahb1_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_APB2] = &apb2_clk.common.hw,
[CLK_AHB2] = &ahb2_clk.common.hw,
[CLK_BUS_CE] = &bus_ce_clk.common.hw,
[CLK_BUS_DMA] = &bus_dma_clk.common.hw,
[CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
[CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
[CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
[CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
[CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
[CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
[CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
[CLK_BUS_OTG] = &bus_otg_clk.common.hw,
[CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
[CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
[CLK_BUS_VE] = &bus_ve_clk.common.hw,
[CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
[CLK_BUS_CSI] = &bus_csi_clk.common.hw,
[CLK_BUS_DE] = &bus_de_clk.common.hw,
[CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
[CLK_BUS_PIO] = &bus_pio_clk.common.hw,
[CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
[CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
[CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
[CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
[CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
[CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
[CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
[CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
[CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
[CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
[CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
[CLK_CE] = &ce_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_I2S0] = &i2s0_clk.common.hw,
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
[CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
[CLK_DRAM] = &dram_clk.common.hw,
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
[CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
[CLK_DRAM_EHCI] = &dram_ehci_clk.common.hw,
[CLK_DRAM_OHCI] = &dram_ohci_clk.common.hw,
[CLK_DE] = &de_clk.common.hw,
[CLK_TCON0] = &tcon_clk.common.hw,
[CLK_CSI_MISC] = &csi_misc_clk.common.hw,
[CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
[CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw,
[CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_AC_DIG] = &ac_dig_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_MBUS] = &mbus_clk.common.hw,
[CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
},
.num = CLK_I2S0 + 1,
};
static struct ccu_reset_map sun8i_v3s_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_MBUS] = { 0x0fc, BIT(31) },
[RST_BUS_CE] = { 0x2c0, BIT(5) },
[RST_BUS_DMA] = { 0x2c0, BIT(6) },
[RST_BUS_MMC0] = { 0x2c0, BIT(8) },
[RST_BUS_MMC1] = { 0x2c0, BIT(9) },
[RST_BUS_MMC2] = { 0x2c0, BIT(10) },
[RST_BUS_DRAM] = { 0x2c0, BIT(14) },
[RST_BUS_EMAC] = { 0x2c0, BIT(17) },
[RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
[RST_BUS_SPI0] = { 0x2c0, BIT(20) },
[RST_BUS_OTG] = { 0x2c0, BIT(24) },
[RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
[RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
[RST_BUS_VE] = { 0x2c4, BIT(0) },
[RST_BUS_TCON0] = { 0x2c4, BIT(4) },
[RST_BUS_CSI] = { 0x2c4, BIT(8) },
[RST_BUS_DE] = { 0x2c4, BIT(12) },
[RST_BUS_DBG] = { 0x2c4, BIT(31) },
[RST_BUS_EPHY] = { 0x2c8, BIT(2) },
[RST_BUS_CODEC] = { 0x2d0, BIT(0) },
[RST_BUS_I2C0] = { 0x2d8, BIT(0) },
[RST_BUS_I2C1] = { 0x2d8, BIT(1) },
[RST_BUS_UART0] = { 0x2d8, BIT(16) },
[RST_BUS_UART1] = { 0x2d8, BIT(17) },
[RST_BUS_UART2] = { 0x2d8, BIT(18) },
};
static struct ccu_reset_map sun8i_v3_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_MBUS] = { 0x0fc, BIT(31) },
[RST_BUS_CE] = { 0x2c0, BIT(5) },
[RST_BUS_DMA] = { 0x2c0, BIT(6) },
[RST_BUS_MMC0] = { 0x2c0, BIT(8) },
[RST_BUS_MMC1] = { 0x2c0, BIT(9) },
[RST_BUS_MMC2] = { 0x2c0, BIT(10) },
[RST_BUS_DRAM] = { 0x2c0, BIT(14) },
[RST_BUS_EMAC] = { 0x2c0, BIT(17) },
[RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
[RST_BUS_SPI0] = { 0x2c0, BIT(20) },
[RST_BUS_OTG] = { 0x2c0, BIT(24) },
[RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
[RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
[RST_BUS_VE] = { 0x2c4, BIT(0) },
[RST_BUS_TCON0] = { 0x2c4, BIT(4) },
[RST_BUS_CSI] = { 0x2c4, BIT(8) },
[RST_BUS_DE] = { 0x2c4, BIT(12) },
[RST_BUS_DBG] = { 0x2c4, BIT(31) },
[RST_BUS_EPHY] = { 0x2c8, BIT(2) },
[RST_BUS_CODEC] = { 0x2d0, BIT(0) },
[RST_BUS_I2S0] = { 0x2d0, BIT(12) },
[RST_BUS_I2C0] = { 0x2d8, BIT(0) },
[RST_BUS_I2C1] = { 0x2d8, BIT(1) },
[RST_BUS_UART0] = { 0x2d8, BIT(16) },
[RST_BUS_UART1] = { 0x2d8, BIT(17) },
[RST_BUS_UART2] = { 0x2d8, BIT(18) },
};
static const struct sunxi_ccu_desc sun8i_v3s_ccu_desc = {
.ccu_clks = sun8i_v3s_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_v3s_ccu_clks),
.hw_clks = &sun8i_v3s_hw_clks,
.resets = sun8i_v3s_ccu_resets,
.num_resets = ARRAY_SIZE(sun8i_v3s_ccu_resets),
};
static const struct sunxi_ccu_desc sun8i_v3_ccu_desc = {
.ccu_clks = sun8i_v3s_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_v3s_ccu_clks),
.hw_clks = &sun8i_v3_hw_clks,
.resets = sun8i_v3_ccu_resets,
.num_resets = ARRAY_SIZE(sun8i_v3_ccu_resets),
};
static int sun8i_v3s_ccu_probe(struct platform_device *pdev)
{
const struct sunxi_ccu_desc *desc;
void __iomem *reg;
u32 val;
desc = of_device_get_match_data(&pdev->dev);
if (!desc)
return -EINVAL;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
/* Force the PLL-Audio-1x divider to 1 */
val = readl(reg + SUN8I_V3S_PLL_AUDIO_REG);
val &= ~GENMASK(19, 16);
writel(val, reg + SUN8I_V3S_PLL_AUDIO_REG);
return devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
}
static const struct of_device_id sun8i_v3s_ccu_ids[] = {
{
.compatible = "allwinner,sun8i-v3-ccu",
.data = &sun8i_v3_ccu_desc,
},
{
.compatible = "allwinner,sun8i-v3s-ccu",
.data = &sun8i_v3s_ccu_desc,
},
{ }
};
static struct platform_driver sun8i_v3s_ccu_driver = {
.probe = sun8i_v3s_ccu_probe,
.driver = {
.name = "sun8i-v3s-ccu",
.suppress_bind_attrs = true,
.of_match_table = sun8i_v3s_ccu_ids,
},
};
module_platform_driver(sun8i_v3s_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun8i-v3s.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 Priit Laes <[email protected]>.
* Copyright (c) 2017 Maxime Ripard.
* Copyright (c) 2017 Jonathan Liu.
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu_mult.h"
#include "ccu_nk.h"
#include "ccu_nkm.h"
#include "ccu_nkmp.h"
#include "ccu_nm.h"
#include "ccu_phase.h"
#include "ccu_sdm.h"
#include "ccu-sun4i-a10.h"
static struct ccu_nkmp pll_core_clk = {
.enable = BIT(31),
.n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
.k = _SUNXI_CCU_MULT(4, 2),
.m = _SUNXI_CCU_DIV(0, 2),
.p = _SUNXI_CCU_DIV(16, 2),
.common = {
.reg = 0x000,
.hw.init = CLK_HW_INIT("pll-core",
"hosc",
&ccu_nkmp_ops,
0),
},
};
/*
* The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
* the base (2x, 4x and 8x), and one variable divider (the one true
* pll audio).
*
* With sigma-delta modulation for fractional-N on the audio PLL,
* we have to use specific dividers. This means the variable divider
* can no longer be used, as the audio codec requests the exact clock
* rates we support through this mechanism. So we now hard code the
* variable divider to 1. This means the clock rates will no longer
* match the clock names.
*/
#define SUN4I_PLL_AUDIO_REG 0x008
static struct ccu_sdm_setting pll_audio_sdm_table[] = {
{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
};
static struct ccu_nm pll_audio_base_clk = {
.enable = BIT(31),
.n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
.m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
.sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, 0,
0x00c, BIT(31)),
.common = {
.reg = 0x008,
.features = CCU_FEATURE_SIGMA_DELTA_MOD,
.hw.init = CLK_HW_INIT("pll-audio-base",
"hosc",
&ccu_nm_ops,
0),
},
};
static struct ccu_mult pll_video0_clk = {
.enable = BIT(31),
.mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
.frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
270000000, 297000000),
.common = {
.reg = 0x010,
.features = (CCU_FEATURE_FRACTIONAL |
CCU_FEATURE_ALL_PREDIV),
.prediv = 8,
.hw.init = CLK_HW_INIT("pll-video0",
"hosc",
&ccu_mult_ops,
0),
},
};
static struct ccu_nkmp pll_ve_sun4i_clk = {
.enable = BIT(31),
.n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
.k = _SUNXI_CCU_MULT(4, 2),
.m = _SUNXI_CCU_DIV(0, 2),
.p = _SUNXI_CCU_DIV(16, 2),
.common = {
.reg = 0x018,
.hw.init = CLK_HW_INIT("pll-ve",
"hosc",
&ccu_nkmp_ops,
0),
},
};
static struct ccu_nk pll_ve_sun7i_clk = {
.enable = BIT(31),
.n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
.k = _SUNXI_CCU_MULT(4, 2),
.common = {
.reg = 0x018,
.hw.init = CLK_HW_INIT("pll-ve",
"hosc",
&ccu_nk_ops,
0),
},
};
static struct ccu_nk pll_ddr_base_clk = {
.enable = BIT(31),
.n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
.k = _SUNXI_CCU_MULT(4, 2),
.common = {
.reg = 0x020,
.hw.init = CLK_HW_INIT("pll-ddr-base",
"hosc",
&ccu_nk_ops,
0),
},
};
static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,
CLK_IS_CRITICAL);
static struct ccu_div pll_ddr_other_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(16, 2, CLK_DIVIDER_POWER_OF_TWO),
.common = {
.reg = 0x020,
.hw.init = CLK_HW_INIT("pll-ddr-other", "pll-ddr-base",
&ccu_div_ops,
0),
},
};
static struct ccu_nk pll_periph_base_clk = {
.enable = BIT(31),
.n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
.k = _SUNXI_CCU_MULT(4, 2),
.common = {
.reg = 0x028,
.hw.init = CLK_HW_INIT("pll-periph-base",
"hosc",
&ccu_nk_ops,
0),
},
};
static CLK_FIXED_FACTOR_HW(pll_periph_clk, "pll-periph",
&pll_periph_base_clk.common.hw,
2, 1, CLK_SET_RATE_PARENT);
/* Not documented on A10 */
static struct ccu_div pll_periph_sata_clk = {
.enable = BIT(14),
.div = _SUNXI_CCU_DIV(0, 2),
.fixed_post_div = 6,
.common = {
.reg = 0x028,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-periph-sata",
"pll-periph-base",
&ccu_div_ops, 0),
},
};
static struct ccu_mult pll_video1_clk = {
.enable = BIT(31),
.mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
.frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
270000000, 297000000),
.common = {
.reg = 0x030,
.features = (CCU_FEATURE_FRACTIONAL |
CCU_FEATURE_ALL_PREDIV),
.prediv = 8,
.hw.init = CLK_HW_INIT("pll-video1",
"hosc",
&ccu_mult_ops,
0),
},
};
/* Not present on A10 */
static struct ccu_nk pll_gpu_clk = {
.enable = BIT(31),
.n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
.k = _SUNXI_CCU_MULT(4, 2),
.common = {
.reg = 0x040,
.hw.init = CLK_HW_INIT("pll-gpu",
"hosc",
&ccu_nk_ops,
0),
},
};
static SUNXI_CCU_GATE(hosc_clk, "hosc", "osc24M", 0x050, BIT(0), 0);
static const char *const cpu_parents[] = { "osc32k", "hosc",
"pll-core", "pll-periph" };
static const struct ccu_mux_fixed_prediv cpu_predivs[] = {
{ .index = 3, .div = 3, },
};
#define SUN4I_AHB_REG 0x054
static struct ccu_mux cpu_clk = {
.mux = {
.shift = 16,
.width = 2,
.fixed_predivs = cpu_predivs,
.n_predivs = ARRAY_SIZE(cpu_predivs),
},
.common = {
.reg = 0x054,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("cpu",
cpu_parents,
&ccu_mux_ops,
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
}
};
static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x054, 0, 2, 0);
static struct ccu_div ahb_sun4i_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
.common = {
.reg = 0x054,
.hw.init = CLK_HW_INIT("ahb", "axi", &ccu_div_ops, 0),
},
};
static const char *const ahb_sun7i_parents[] = { "axi", "pll-periph",
"pll-periph" };
static const struct ccu_mux_fixed_prediv ahb_sun7i_predivs[] = {
{ .index = 1, .div = 2, },
{ /* Sentinel */ },
};
static struct ccu_div ahb_sun7i_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = {
.shift = 6,
.width = 2,
.fixed_predivs = ahb_sun7i_predivs,
.n_predivs = ARRAY_SIZE(ahb_sun7i_predivs),
},
.common = {
.reg = 0x054,
.hw.init = CLK_HW_INIT_PARENTS("ahb",
ahb_sun7i_parents,
&ccu_div_ops,
0),
},
};
static struct clk_div_table apb0_div_table[] = {
{ .val = 0, .div = 2 },
{ .val = 1, .div = 2 },
{ .val = 2, .div = 4 },
{ .val = 3, .div = 8 },
{ /* Sentinel */ },
};
static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
0x054, 8, 2, apb0_div_table, 0);
static const char *const apb1_parents[] = { "hosc", "pll-periph", "osc32k" };
static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x058,
0, 5, /* M */
16, 2, /* P */
24, 2, /* mux */
0);
/* Not present on A20 */
static SUNXI_CCU_GATE(axi_dram_clk, "axi-dram", "ahb",
0x05c, BIT(31), 0);
static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
0x060, BIT(0), 0);
static SUNXI_CCU_GATE(ahb_ehci0_clk, "ahb-ehci0", "ahb",
0x060, BIT(1), 0);
static SUNXI_CCU_GATE(ahb_ohci0_clk, "ahb-ohci0", "ahb",
0x060, BIT(2), 0);
static SUNXI_CCU_GATE(ahb_ehci1_clk, "ahb-ehci1", "ahb",
0x060, BIT(3), 0);
static SUNXI_CCU_GATE(ahb_ohci1_clk, "ahb-ohci1", "ahb",
0x060, BIT(4), 0);
static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
0x060, BIT(5), 0);
static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
0x060, BIT(6), 0);
static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
0x060, BIT(7), 0);
static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
0x060, BIT(8), 0);
static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
0x060, BIT(9), 0);
static SUNXI_CCU_GATE(ahb_mmc2_clk, "ahb-mmc2", "ahb",
0x060, BIT(10), 0);
static SUNXI_CCU_GATE(ahb_mmc3_clk, "ahb-mmc3", "ahb",
0x060, BIT(11), 0);
static SUNXI_CCU_GATE(ahb_ms_clk, "ahb-ms", "ahb",
0x060, BIT(12), 0);
static SUNXI_CCU_GATE(ahb_nand_clk, "ahb-nand", "ahb",
0x060, BIT(13), 0);
static SUNXI_CCU_GATE(ahb_sdram_clk, "ahb-sdram", "ahb",
0x060, BIT(14), CLK_IS_CRITICAL);
static SUNXI_CCU_GATE(ahb_ace_clk, "ahb-ace", "ahb",
0x060, BIT(16), 0);
static SUNXI_CCU_GATE(ahb_emac_clk, "ahb-emac", "ahb",
0x060, BIT(17), 0);
static SUNXI_CCU_GATE(ahb_ts_clk, "ahb-ts", "ahb",
0x060, BIT(18), 0);
static SUNXI_CCU_GATE(ahb_spi0_clk, "ahb-spi0", "ahb",
0x060, BIT(20), 0);
static SUNXI_CCU_GATE(ahb_spi1_clk, "ahb-spi1", "ahb",
0x060, BIT(21), 0);
static SUNXI_CCU_GATE(ahb_spi2_clk, "ahb-spi2", "ahb",
0x060, BIT(22), 0);
static SUNXI_CCU_GATE(ahb_spi3_clk, "ahb-spi3", "ahb",
0x060, BIT(23), 0);
static SUNXI_CCU_GATE(ahb_pata_clk, "ahb-pata", "ahb",
0x060, BIT(24), 0);
/* Not documented on A20 */
static SUNXI_CCU_GATE(ahb_sata_clk, "ahb-sata", "ahb",
0x060, BIT(25), 0);
/* Not present on A20 */
static SUNXI_CCU_GATE(ahb_gps_clk, "ahb-gps", "ahb",
0x060, BIT(26), 0);
/* Not present on A10 */
static SUNXI_CCU_GATE(ahb_hstimer_clk, "ahb-hstimer", "ahb",
0x060, BIT(28), 0);
static SUNXI_CCU_GATE(ahb_ve_clk, "ahb-ve", "ahb",
0x064, BIT(0), 0);
static SUNXI_CCU_GATE(ahb_tvd_clk, "ahb-tvd", "ahb",
0x064, BIT(1), 0);
static SUNXI_CCU_GATE(ahb_tve0_clk, "ahb-tve0", "ahb",
0x064, BIT(2), 0);
static SUNXI_CCU_GATE(ahb_tve1_clk, "ahb-tve1", "ahb",
0x064, BIT(3), 0);
static SUNXI_CCU_GATE(ahb_lcd0_clk, "ahb-lcd0", "ahb",
0x064, BIT(4), 0);
static SUNXI_CCU_GATE(ahb_lcd1_clk, "ahb-lcd1", "ahb",
0x064, BIT(5), 0);
static SUNXI_CCU_GATE(ahb_csi0_clk, "ahb-csi0", "ahb",
0x064, BIT(8), 0);
static SUNXI_CCU_GATE(ahb_csi1_clk, "ahb-csi1", "ahb",
0x064, BIT(9), 0);
/* Not present on A10 */
static SUNXI_CCU_GATE(ahb_hdmi1_clk, "ahb-hdmi1", "ahb",
0x064, BIT(10), 0);
static SUNXI_CCU_GATE(ahb_hdmi0_clk, "ahb-hdmi0", "ahb",
0x064, BIT(11), 0);
static SUNXI_CCU_GATE(ahb_de_be0_clk, "ahb-de-be0", "ahb",
0x064, BIT(12), 0);
static SUNXI_CCU_GATE(ahb_de_be1_clk, "ahb-de-be1", "ahb",
0x064, BIT(13), 0);
static SUNXI_CCU_GATE(ahb_de_fe0_clk, "ahb-de-fe0", "ahb",
0x064, BIT(14), 0);
static SUNXI_CCU_GATE(ahb_de_fe1_clk, "ahb-de-fe1", "ahb",
0x064, BIT(15), 0);
/* Not present on A10 */
static SUNXI_CCU_GATE(ahb_gmac_clk, "ahb-gmac", "ahb",
0x064, BIT(17), 0);
static SUNXI_CCU_GATE(ahb_mp_clk, "ahb-mp", "ahb",
0x064, BIT(18), 0);
static SUNXI_CCU_GATE(ahb_gpu_clk, "ahb-gpu", "ahb",
0x064, BIT(20), 0);
static SUNXI_CCU_GATE(apb0_codec_clk, "apb0-codec", "apb0",
0x068, BIT(0), 0);
static SUNXI_CCU_GATE(apb0_spdif_clk, "apb0-spdif", "apb0",
0x068, BIT(1), 0);
static SUNXI_CCU_GATE(apb0_ac97_clk, "apb0-ac97", "apb0",
0x068, BIT(2), 0);
static SUNXI_CCU_GATE(apb0_i2s0_clk, "apb0-i2s0", "apb0",
0x068, BIT(3), 0);
/* Not present on A10 */
static SUNXI_CCU_GATE(apb0_i2s1_clk, "apb0-i2s1", "apb0",
0x068, BIT(4), 0);
static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0",
0x068, BIT(5), 0);
static SUNXI_CCU_GATE(apb0_ir0_clk, "apb0-ir0", "apb0",
0x068, BIT(6), 0);
static SUNXI_CCU_GATE(apb0_ir1_clk, "apb0-ir1", "apb0",
0x068, BIT(7), 0);
/* Not present on A10 */
static SUNXI_CCU_GATE(apb0_i2s2_clk, "apb0-i2s2", "apb0",
0x068, BIT(8), 0);
static SUNXI_CCU_GATE(apb0_keypad_clk, "apb0-keypad", "apb0",
0x068, BIT(10), 0);
static SUNXI_CCU_GATE(apb1_i2c0_clk, "apb1-i2c0", "apb1",
0x06c, BIT(0), 0);
static SUNXI_CCU_GATE(apb1_i2c1_clk, "apb1-i2c1", "apb1",
0x06c, BIT(1), 0);
static SUNXI_CCU_GATE(apb1_i2c2_clk, "apb1-i2c2", "apb1",
0x06c, BIT(2), 0);
/* Not present on A10 */
static SUNXI_CCU_GATE(apb1_i2c3_clk, "apb1-i2c3", "apb1",
0x06c, BIT(3), 0);
static SUNXI_CCU_GATE(apb1_can_clk, "apb1-can", "apb1",
0x06c, BIT(4), 0);
static SUNXI_CCU_GATE(apb1_scr_clk, "apb1-scr", "apb1",
0x06c, BIT(5), 0);
static SUNXI_CCU_GATE(apb1_ps20_clk, "apb1-ps20", "apb1",
0x06c, BIT(6), 0);
static SUNXI_CCU_GATE(apb1_ps21_clk, "apb1-ps21", "apb1",
0x06c, BIT(7), 0);
/* Not present on A10 */
static SUNXI_CCU_GATE(apb1_i2c4_clk, "apb1-i2c4", "apb1",
0x06c, BIT(15), 0);
static SUNXI_CCU_GATE(apb1_uart0_clk, "apb1-uart0", "apb1",
0x06c, BIT(16), 0);
static SUNXI_CCU_GATE(apb1_uart1_clk, "apb1-uart1", "apb1",
0x06c, BIT(17), 0);
static SUNXI_CCU_GATE(apb1_uart2_clk, "apb1-uart2", "apb1",
0x06c, BIT(18), 0);
static SUNXI_CCU_GATE(apb1_uart3_clk, "apb1-uart3", "apb1",
0x06c, BIT(19), 0);
static SUNXI_CCU_GATE(apb1_uart4_clk, "apb1-uart4", "apb1",
0x06c, BIT(20), 0);
static SUNXI_CCU_GATE(apb1_uart5_clk, "apb1-uart5", "apb1",
0x06c, BIT(21), 0);
static SUNXI_CCU_GATE(apb1_uart6_clk, "apb1-uart6", "apb1",
0x06c, BIT(22), 0);
static SUNXI_CCU_GATE(apb1_uart7_clk, "apb1-uart7", "apb1",
0x06c, BIT(23), 0);
static const char *const mod0_default_parents[] = { "hosc", "pll-periph",
"pll-ddr-other" };
static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
/* Undocumented on A10 */
static SUNXI_CCU_MP_WITH_MUX_GATE(ms_clk, "ms", mod0_default_parents, 0x084,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
/* MMC output and sample clocks are not present on A10 */
static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
0x088, 8, 3, 0);
static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
0x088, 20, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
/* MMC output and sample clocks are not present on A10 */
static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
0x08c, 8, 3, 0);
static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
0x08c, 20, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
/* MMC output and sample clocks are not present on A10 */
static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
0x090, 8, 3, 0);
static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
0x090, 20, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
/* MMC output and sample clocks are not present on A10 */
static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3_output", "mmc3",
0x094, 8, 3, 0);
static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3_sample", "mmc3",
0x094, 20, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
/* Undocumented on A10 */
static SUNXI_CCU_MP_WITH_MUX_GATE(pata_clk, "pata", mod0_default_parents, 0x0ac,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
/* TODO: Check whether A10 actually supports osc32k as 4th parent? */
static const char *const ir_parents_sun4i[] = { "hosc", "pll-periph",
"pll-ddr-other" };
static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_sun4i_clk, "ir0", ir_parents_sun4i, 0x0b0,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_sun4i_clk, "ir1", ir_parents_sun4i, 0x0b4,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static const char *const ir_parents_sun7i[] = { "hosc", "pll-periph",
"pll-ddr-other", "osc32k" };
static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_sun7i_clk, "ir0", ir_parents_sun7i, 0x0b0,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_sun7i_clk, "ir1", ir_parents_sun7i, 0x0b4,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static const char *const audio_parents[] = { "pll-audio-8x", "pll-audio-4x",
"pll-audio-2x", "pll-audio" };
static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", audio_parents,
0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", audio_parents,
0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
/* Undocumented on A10 */
static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", audio_parents,
0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static const char *const keypad_parents[] = { "hosc", "losc"};
static const u8 keypad_table[] = { 0, 2 };
static struct ccu_mp keypad_clk = {
.enable = BIT(31),
.m = _SUNXI_CCU_DIV(0, 5),
.p = _SUNXI_CCU_DIV(16, 2),
.mux = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
.common = {
.reg = 0x0c4,
.hw.init = CLK_HW_INIT_PARENTS("keypad",
keypad_parents,
&ccu_mp_ops,
0),
},
};
/*
* SATA supports external clock as parent via BIT(24) and is probably an
* optional crystal or oscillator that can be connected to the
* SATA-CLKM / SATA-CLKP pins.
*/
static const char *const sata_parents[] = {"pll-periph-sata", "sata-ext"};
static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents,
0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "pll-periph",
0x0cc, BIT(6), 0);
static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "pll-periph",
0x0cc, BIT(7), 0);
static SUNXI_CCU_GATE(usb_phy_clk, "usb-phy", "pll-periph",
0x0cc, BIT(8), 0);
/* TODO: GPS CLK 0x0d0 */
static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0d4,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
/* Not present on A10 */
static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", audio_parents,
0x0d8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
/* Not present on A10 */
static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", audio_parents,
0x0dc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
0x100, BIT(0), 0);
static SUNXI_CCU_GATE(dram_csi0_clk, "dram-csi0", "pll-ddr",
0x100, BIT(1), 0);
static SUNXI_CCU_GATE(dram_csi1_clk, "dram-csi1", "pll-ddr",
0x100, BIT(2), 0);
static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "pll-ddr",
0x100, BIT(3), 0);
static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "pll-ddr",
0x100, BIT(4), 0);
static SUNXI_CCU_GATE(dram_tve0_clk, "dram-tve0", "pll-ddr",
0x100, BIT(5), 0);
static SUNXI_CCU_GATE(dram_tve1_clk, "dram-tve1", "pll-ddr",
0x100, BIT(6), 0);
/* Clock seems to be critical only on sun4i */
static SUNXI_CCU_GATE(dram_out_clk, "dram-out", "pll-ddr",
0x100, BIT(15), CLK_IS_CRITICAL);
static SUNXI_CCU_GATE(dram_de_fe1_clk, "dram-de-fe1", "pll-ddr",
0x100, BIT(24), 0);
static SUNXI_CCU_GATE(dram_de_fe0_clk, "dram-de-fe0", "pll-ddr",
0x100, BIT(25), 0);
static SUNXI_CCU_GATE(dram_de_be0_clk, "dram-de-be0", "pll-ddr",
0x100, BIT(26), 0);
static SUNXI_CCU_GATE(dram_de_be1_clk, "dram-de-be1", "pll-ddr",
0x100, BIT(27), 0);
static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "pll-ddr",
0x100, BIT(28), 0);
static SUNXI_CCU_GATE(dram_ace_clk, "dram-ace", "pll-ddr",
0x100, BIT(29), 0);
static const char *const de_parents[] = { "pll-video0", "pll-video1",
"pll-ddr-other" };
static SUNXI_CCU_M_WITH_MUX_GATE(de_be0_clk, "de-be0", de_parents,
0x104, 0, 4, 24, 2, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(de_be1_clk, "de-be1", de_parents,
0x108, 0, 4, 24, 2, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(de_fe0_clk, "de-fe0", de_parents,
0x10c, 0, 4, 24, 2, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(de_fe1_clk, "de-fe1", de_parents,
0x110, 0, 4, 24, 2, BIT(31), 0);
/* Undocumented on A10 */
static SUNXI_CCU_M_WITH_MUX_GATE(de_mp_clk, "de-mp", de_parents,
0x114, 0, 4, 24, 2, BIT(31), 0);
static const char *const disp_parents[] = { "pll-video0", "pll-video1",
"pll-video0-2x", "pll-video1-2x" };
static SUNXI_CCU_MUX_WITH_GATE(tcon0_ch0_clk, "tcon0-ch0-sclk", disp_parents,
0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_MUX_WITH_GATE(tcon1_ch0_clk, "tcon1-ch0-sclk", disp_parents,
0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
static const char *const csi_sclk_parents[] = { "pll-video0", "pll-ve",
"pll-ddr-other", "pll-periph" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk",
csi_sclk_parents,
0x120, 0, 4, 24, 2, BIT(31), 0);
/* TVD clock setup for A10 */
static const char *const tvd_parents[] = { "pll-video0", "pll-video1" };
static SUNXI_CCU_MUX_WITH_GATE(tvd_sun4i_clk, "tvd", tvd_parents,
0x128, 24, 1, BIT(31), 0);
/* TVD clock setup for A20 */
static SUNXI_CCU_MP_WITH_MUX_GATE(tvd_sclk2_sun7i_clk,
"tvd-sclk2", tvd_parents,
0x128,
0, 4, /* M */
16, 4, /* P */
8, 1, /* mux */
BIT(15), /* gate */
0);
static SUNXI_CCU_M_WITH_GATE(tvd_sclk1_sun7i_clk, "tvd-sclk1", "tvd-sclk2",
0x128, 0, 4, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(tcon0_ch1_sclk2_clk, "tcon0-ch1-sclk2",
disp_parents,
0x12c, 0, 4, 24, 2, BIT(31),
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(tcon0_ch1_clk,
"tcon0-ch1-sclk1", "tcon0-ch1-sclk2",
0x12c, 11, 1, BIT(15),
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_ch1_sclk2_clk, "tcon1-ch1-sclk2",
disp_parents,
0x130, 0, 4, 24, 2, BIT(31),
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(tcon1_ch1_clk,
"tcon1-ch1-sclk1", "tcon1-ch1-sclk2",
0x130, 11, 1, BIT(15),
CLK_SET_RATE_PARENT);
static const char *const csi_parents[] = { "hosc", "pll-video0", "pll-video1",
"pll-video0-2x", "pll-video1-2x"};
static const u8 csi_table[] = { 0, 1, 2, 5, 6};
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi0_clk, "csi0",
csi_parents, csi_table,
0x134, 0, 5, 24, 3, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi1_clk, "csi1",
csi_parents, csi_table,
0x138, 0, 5, 24, 3, BIT(31), 0);
static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 16, 8, BIT(31), 0);
static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
0x140, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(avs_clk, "avs", "hosc", 0x144, BIT(31), 0);
static const char *const ace_parents[] = { "pll-ve", "pll-ddr-other" };
static SUNXI_CCU_M_WITH_MUX_GATE(ace_clk, "ace", ace_parents,
0x148, 0, 4, 24, 1, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", disp_parents,
0x150, 0, 4, 24, 2, BIT(31),
CLK_SET_RATE_PARENT);
static const char *const gpu_parents_sun4i[] = { "pll-video0", "pll-ve",
"pll-ddr-other",
"pll-video1" };
static SUNXI_CCU_M_WITH_MUX_GATE(gpu_sun4i_clk, "gpu", gpu_parents_sun4i,
0x154, 0, 4, 24, 2, BIT(31),
CLK_SET_RATE_PARENT);
static const char *const gpu_parents_sun7i[] = { "pll-video0", "pll-ve",
"pll-ddr-other", "pll-video1",
"pll-gpu" };
static const u8 gpu_table_sun7i[] = { 0, 1, 2, 3, 4 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(gpu_sun7i_clk, "gpu",
gpu_parents_sun7i, gpu_table_sun7i,
0x154, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
static const char *const mbus_sun4i_parents[] = { "hosc", "pll-periph",
"pll-ddr-other" };
static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_sun4i_clk, "mbus", mbus_sun4i_parents,
0x15c, 0, 4, 16, 2, 24, 2, BIT(31),
0);
static const char *const mbus_sun7i_parents[] = { "hosc", "pll-periph-base",
"pll-ddr-other" };
static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_sun7i_clk, "mbus", mbus_sun7i_parents,
0x15c, 0, 4, 16, 2, 24, 2, BIT(31),
CLK_IS_CRITICAL);
static SUNXI_CCU_GATE(hdmi1_slow_clk, "hdmi1-slow", "hosc", 0x178, BIT(31), 0);
static const char *const hdmi1_parents[] = { "pll-video0", "pll-video1" };
static const u8 hdmi1_table[] = { 0, 1};
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(hdmi1_clk, "hdmi1",
hdmi1_parents, hdmi1_table,
0x17c, 0, 4, 24, 2, BIT(31),
CLK_SET_RATE_PARENT);
static const char *const out_parents[] = { "hosc", "osc32k", "hosc" };
static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {
{ .index = 0, .div = 750, },
};
static struct ccu_mp out_a_clk = {
.enable = BIT(31),
.m = _SUNXI_CCU_DIV(8, 5),
.p = _SUNXI_CCU_DIV(20, 2),
.mux = {
.shift = 24,
.width = 2,
.fixed_predivs = clk_out_predivs,
.n_predivs = ARRAY_SIZE(clk_out_predivs),
},
.common = {
.reg = 0x1f0,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("out-a",
out_parents,
&ccu_mp_ops,
0),
},
};
static struct ccu_mp out_b_clk = {
.enable = BIT(31),
.m = _SUNXI_CCU_DIV(8, 5),
.p = _SUNXI_CCU_DIV(20, 2),
.mux = {
.shift = 24,
.width = 2,
.fixed_predivs = clk_out_predivs,
.n_predivs = ARRAY_SIZE(clk_out_predivs),
},
.common = {
.reg = 0x1f4,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("out-b",
out_parents,
&ccu_mp_ops,
0),
},
};
static struct ccu_common *sun4i_sun7i_ccu_clks[] = {
&hosc_clk.common,
&pll_core_clk.common,
&pll_audio_base_clk.common,
&pll_video0_clk.common,
&pll_ve_sun4i_clk.common,
&pll_ve_sun7i_clk.common,
&pll_ddr_base_clk.common,
&pll_ddr_clk.common,
&pll_ddr_other_clk.common,
&pll_periph_base_clk.common,
&pll_periph_sata_clk.common,
&pll_video1_clk.common,
&pll_gpu_clk.common,
&cpu_clk.common,
&axi_clk.common,
&axi_dram_clk.common,
&ahb_sun4i_clk.common,
&ahb_sun7i_clk.common,
&apb0_clk.common,
&apb1_clk.common,
&ahb_otg_clk.common,
&ahb_ehci0_clk.common,
&ahb_ohci0_clk.common,
&ahb_ehci1_clk.common,
&ahb_ohci1_clk.common,
&ahb_ss_clk.common,
&ahb_dma_clk.common,
&ahb_bist_clk.common,
&ahb_mmc0_clk.common,
&ahb_mmc1_clk.common,
&ahb_mmc2_clk.common,
&ahb_mmc3_clk.common,
&ahb_ms_clk.common,
&ahb_nand_clk.common,
&ahb_sdram_clk.common,
&ahb_ace_clk.common,
&ahb_emac_clk.common,
&ahb_ts_clk.common,
&ahb_spi0_clk.common,
&ahb_spi1_clk.common,
&ahb_spi2_clk.common,
&ahb_spi3_clk.common,
&ahb_pata_clk.common,
&ahb_sata_clk.common,
&ahb_gps_clk.common,
&ahb_hstimer_clk.common,
&ahb_ve_clk.common,
&ahb_tvd_clk.common,
&ahb_tve0_clk.common,
&ahb_tve1_clk.common,
&ahb_lcd0_clk.common,
&ahb_lcd1_clk.common,
&ahb_csi0_clk.common,
&ahb_csi1_clk.common,
&ahb_hdmi1_clk.common,
&ahb_hdmi0_clk.common,
&ahb_de_be0_clk.common,
&ahb_de_be1_clk.common,
&ahb_de_fe0_clk.common,
&ahb_de_fe1_clk.common,
&ahb_gmac_clk.common,
&ahb_mp_clk.common,
&ahb_gpu_clk.common,
&apb0_codec_clk.common,
&apb0_spdif_clk.common,
&apb0_ac97_clk.common,
&apb0_i2s0_clk.common,
&apb0_i2s1_clk.common,
&apb0_pio_clk.common,
&apb0_ir0_clk.common,
&apb0_ir1_clk.common,
&apb0_i2s2_clk.common,
&apb0_keypad_clk.common,
&apb1_i2c0_clk.common,
&apb1_i2c1_clk.common,
&apb1_i2c2_clk.common,
&apb1_i2c3_clk.common,
&apb1_can_clk.common,
&apb1_scr_clk.common,
&apb1_ps20_clk.common,
&apb1_ps21_clk.common,
&apb1_i2c4_clk.common,
&apb1_uart0_clk.common,
&apb1_uart1_clk.common,
&apb1_uart2_clk.common,
&apb1_uart3_clk.common,
&apb1_uart4_clk.common,
&apb1_uart5_clk.common,
&apb1_uart6_clk.common,
&apb1_uart7_clk.common,
&nand_clk.common,
&ms_clk.common,
&mmc0_clk.common,
&mmc0_output_clk.common,
&mmc0_sample_clk.common,
&mmc1_clk.common,
&mmc1_output_clk.common,
&mmc1_sample_clk.common,
&mmc2_clk.common,
&mmc2_output_clk.common,
&mmc2_sample_clk.common,
&mmc3_clk.common,
&mmc3_output_clk.common,
&mmc3_sample_clk.common,
&ts_clk.common,
&ss_clk.common,
&spi0_clk.common,
&spi1_clk.common,
&spi2_clk.common,
&pata_clk.common,
&ir0_sun4i_clk.common,
&ir1_sun4i_clk.common,
&ir0_sun7i_clk.common,
&ir1_sun7i_clk.common,
&i2s0_clk.common,
&ac97_clk.common,
&spdif_clk.common,
&keypad_clk.common,
&sata_clk.common,
&usb_ohci0_clk.common,
&usb_ohci1_clk.common,
&usb_phy_clk.common,
&spi3_clk.common,
&i2s1_clk.common,
&i2s2_clk.common,
&dram_ve_clk.common,
&dram_csi0_clk.common,
&dram_csi1_clk.common,
&dram_ts_clk.common,
&dram_tvd_clk.common,
&dram_tve0_clk.common,
&dram_tve1_clk.common,
&dram_out_clk.common,
&dram_de_fe1_clk.common,
&dram_de_fe0_clk.common,
&dram_de_be0_clk.common,
&dram_de_be1_clk.common,
&dram_mp_clk.common,
&dram_ace_clk.common,
&de_be0_clk.common,
&de_be1_clk.common,
&de_fe0_clk.common,
&de_fe1_clk.common,
&de_mp_clk.common,
&tcon0_ch0_clk.common,
&tcon1_ch0_clk.common,
&csi_sclk_clk.common,
&tvd_sun4i_clk.common,
&tvd_sclk1_sun7i_clk.common,
&tvd_sclk2_sun7i_clk.common,
&tcon0_ch1_sclk2_clk.common,
&tcon0_ch1_clk.common,
&tcon1_ch1_sclk2_clk.common,
&tcon1_ch1_clk.common,
&csi0_clk.common,
&csi1_clk.common,
&ve_clk.common,
&codec_clk.common,
&avs_clk.common,
&ace_clk.common,
&hdmi_clk.common,
&gpu_sun4i_clk.common,
&gpu_sun7i_clk.common,
&mbus_sun4i_clk.common,
&mbus_sun7i_clk.common,
&hdmi1_slow_clk.common,
&hdmi1_clk.common,
&out_a_clk.common,
&out_b_clk.common
};
static const struct clk_hw *clk_parent_pll_audio[] = {
&pll_audio_base_clk.common.hw
};
/* Post-divider for pll-audio is hardcoded to 1 */
static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
clk_parent_pll_audio,
1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
clk_parent_pll_audio,
2, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
clk_parent_pll_audio,
1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
clk_parent_pll_audio,
1, 2, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
&pll_video0_clk.common.hw,
1, 2, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
&pll_video1_clk.common.hw,
1, 2, CLK_SET_RATE_PARENT);
static struct clk_hw_onecell_data sun4i_a10_hw_clks = {
.hws = {
[CLK_HOSC] = &hosc_clk.common.hw,
[CLK_PLL_CORE] = &pll_core_clk.common.hw,
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
[CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
[CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
[CLK_PLL_VE] = &pll_ve_sun4i_clk.common.hw,
[CLK_PLL_DDR_BASE] = &pll_ddr_base_clk.common.hw,
[CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
[CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,
[CLK_PLL_PERIPH_BASE] = &pll_periph_base_clk.common.hw,
[CLK_PLL_PERIPH] = &pll_periph_clk.hw,
[CLK_PLL_PERIPH_SATA] = &pll_periph_sata_clk.common.hw,
[CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
[CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
[CLK_CPU] = &cpu_clk.common.hw,
[CLK_AXI] = &axi_clk.common.hw,
[CLK_AXI_DRAM] = &axi_dram_clk.common.hw,
[CLK_AHB] = &ahb_sun4i_clk.common.hw,
[CLK_APB0] = &apb0_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_AHB_OTG] = &ahb_otg_clk.common.hw,
[CLK_AHB_EHCI0] = &ahb_ehci0_clk.common.hw,
[CLK_AHB_OHCI0] = &ahb_ohci0_clk.common.hw,
[CLK_AHB_EHCI1] = &ahb_ehci1_clk.common.hw,
[CLK_AHB_OHCI1] = &ahb_ohci1_clk.common.hw,
[CLK_AHB_SS] = &ahb_ss_clk.common.hw,
[CLK_AHB_DMA] = &ahb_dma_clk.common.hw,
[CLK_AHB_BIST] = &ahb_bist_clk.common.hw,
[CLK_AHB_MMC0] = &ahb_mmc0_clk.common.hw,
[CLK_AHB_MMC1] = &ahb_mmc1_clk.common.hw,
[CLK_AHB_MMC2] = &ahb_mmc2_clk.common.hw,
[CLK_AHB_MMC3] = &ahb_mmc3_clk.common.hw,
[CLK_AHB_MS] = &ahb_ms_clk.common.hw,
[CLK_AHB_NAND] = &ahb_nand_clk.common.hw,
[CLK_AHB_SDRAM] = &ahb_sdram_clk.common.hw,
[CLK_AHB_ACE] = &ahb_ace_clk.common.hw,
[CLK_AHB_EMAC] = &ahb_emac_clk.common.hw,
[CLK_AHB_TS] = &ahb_ts_clk.common.hw,
[CLK_AHB_SPI0] = &ahb_spi0_clk.common.hw,
[CLK_AHB_SPI1] = &ahb_spi1_clk.common.hw,
[CLK_AHB_SPI2] = &ahb_spi2_clk.common.hw,
[CLK_AHB_SPI3] = &ahb_spi3_clk.common.hw,
[CLK_AHB_PATA] = &ahb_pata_clk.common.hw,
[CLK_AHB_SATA] = &ahb_sata_clk.common.hw,
[CLK_AHB_GPS] = &ahb_gps_clk.common.hw,
[CLK_AHB_VE] = &ahb_ve_clk.common.hw,
[CLK_AHB_TVD] = &ahb_tvd_clk.common.hw,
[CLK_AHB_TVE0] = &ahb_tve0_clk.common.hw,
[CLK_AHB_TVE1] = &ahb_tve1_clk.common.hw,
[CLK_AHB_LCD0] = &ahb_lcd0_clk.common.hw,
[CLK_AHB_LCD1] = &ahb_lcd1_clk.common.hw,
[CLK_AHB_CSI0] = &ahb_csi0_clk.common.hw,
[CLK_AHB_CSI1] = &ahb_csi1_clk.common.hw,
[CLK_AHB_HDMI0] = &ahb_hdmi0_clk.common.hw,
[CLK_AHB_DE_BE0] = &ahb_de_be0_clk.common.hw,
[CLK_AHB_DE_BE1] = &ahb_de_be1_clk.common.hw,
[CLK_AHB_DE_FE0] = &ahb_de_fe0_clk.common.hw,
[CLK_AHB_DE_FE1] = &ahb_de_fe1_clk.common.hw,
[CLK_AHB_MP] = &ahb_mp_clk.common.hw,
[CLK_AHB_GPU] = &ahb_gpu_clk.common.hw,
[CLK_APB0_CODEC] = &apb0_codec_clk.common.hw,
[CLK_APB0_SPDIF] = &apb0_spdif_clk.common.hw,
[CLK_APB0_AC97] = &apb0_ac97_clk.common.hw,
[CLK_APB0_I2S0] = &apb0_i2s0_clk.common.hw,
[CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
[CLK_APB0_IR0] = &apb0_ir0_clk.common.hw,
[CLK_APB0_IR1] = &apb0_ir1_clk.common.hw,
[CLK_APB0_KEYPAD] = &apb0_keypad_clk.common.hw,
[CLK_APB1_I2C0] = &apb1_i2c0_clk.common.hw,
[CLK_APB1_I2C1] = &apb1_i2c1_clk.common.hw,
[CLK_APB1_I2C2] = &apb1_i2c2_clk.common.hw,
[CLK_APB1_CAN] = &apb1_can_clk.common.hw,
[CLK_APB1_SCR] = &apb1_scr_clk.common.hw,
[CLK_APB1_PS20] = &apb1_ps20_clk.common.hw,
[CLK_APB1_PS21] = &apb1_ps21_clk.common.hw,
[CLK_APB1_UART0] = &apb1_uart0_clk.common.hw,
[CLK_APB1_UART1] = &apb1_uart1_clk.common.hw,
[CLK_APB1_UART2] = &apb1_uart2_clk.common.hw,
[CLK_APB1_UART3] = &apb1_uart3_clk.common.hw,
[CLK_APB1_UART4] = &apb1_uart4_clk.common.hw,
[CLK_APB1_UART5] = &apb1_uart5_clk.common.hw,
[CLK_APB1_UART6] = &apb1_uart6_clk.common.hw,
[CLK_APB1_UART7] = &apb1_uart7_clk.common.hw,
[CLK_NAND] = &nand_clk.common.hw,
[CLK_MS] = &ms_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_MMC3] = &mmc3_clk.common.hw,
[CLK_TS] = &ts_clk.common.hw,
[CLK_SS] = &ss_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI2] = &spi2_clk.common.hw,
[CLK_PATA] = &pata_clk.common.hw,
[CLK_IR0] = &ir0_sun4i_clk.common.hw,
[CLK_IR1] = &ir1_sun4i_clk.common.hw,
[CLK_I2S0] = &i2s0_clk.common.hw,
[CLK_AC97] = &ac97_clk.common.hw,
[CLK_SPDIF] = &spdif_clk.common.hw,
[CLK_KEYPAD] = &keypad_clk.common.hw,
[CLK_SATA] = &sata_clk.common.hw,
[CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
[CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
[CLK_USB_PHY] = &usb_phy_clk.common.hw,
/* CLK_GPS is unimplemented */
[CLK_SPI3] = &spi3_clk.common.hw,
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
[CLK_DRAM_CSI0] = &dram_csi0_clk.common.hw,
[CLK_DRAM_CSI1] = &dram_csi1_clk.common.hw,
[CLK_DRAM_TS] = &dram_ts_clk.common.hw,
[CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
[CLK_DRAM_TVE0] = &dram_tve0_clk.common.hw,
[CLK_DRAM_TVE1] = &dram_tve1_clk.common.hw,
[CLK_DRAM_OUT] = &dram_out_clk.common.hw,
[CLK_DRAM_DE_FE1] = &dram_de_fe1_clk.common.hw,
[CLK_DRAM_DE_FE0] = &dram_de_fe0_clk.common.hw,
[CLK_DRAM_DE_BE0] = &dram_de_be0_clk.common.hw,
[CLK_DRAM_DE_BE1] = &dram_de_be1_clk.common.hw,
[CLK_DRAM_MP] = &dram_mp_clk.common.hw,
[CLK_DRAM_ACE] = &dram_ace_clk.common.hw,
[CLK_DE_BE0] = &de_be0_clk.common.hw,
[CLK_DE_BE1] = &de_be1_clk.common.hw,
[CLK_DE_FE0] = &de_fe0_clk.common.hw,
[CLK_DE_FE1] = &de_fe1_clk.common.hw,
[CLK_DE_MP] = &de_mp_clk.common.hw,
[CLK_TCON0_CH0] = &tcon0_ch0_clk.common.hw,
[CLK_TCON1_CH0] = &tcon1_ch0_clk.common.hw,
[CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
[CLK_TVD] = &tvd_sun4i_clk.common.hw,
[CLK_TCON0_CH1_SCLK2] = &tcon0_ch1_sclk2_clk.common.hw,
[CLK_TCON0_CH1] = &tcon0_ch1_clk.common.hw,
[CLK_TCON1_CH1_SCLK2] = &tcon1_ch1_sclk2_clk.common.hw,
[CLK_TCON1_CH1] = &tcon1_ch1_clk.common.hw,
[CLK_CSI0] = &csi0_clk.common.hw,
[CLK_CSI1] = &csi1_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_CODEC] = &codec_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_ACE] = &ace_clk.common.hw,
[CLK_HDMI] = &hdmi_clk.common.hw,
[CLK_GPU] = &gpu_sun7i_clk.common.hw,
[CLK_MBUS] = &mbus_sun4i_clk.common.hw,
},
.num = CLK_NUMBER_SUN4I,
};
static struct clk_hw_onecell_data sun7i_a20_hw_clks = {
.hws = {
[CLK_HOSC] = &hosc_clk.common.hw,
[CLK_PLL_CORE] = &pll_core_clk.common.hw,
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
[CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
[CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
[CLK_PLL_VE] = &pll_ve_sun7i_clk.common.hw,
[CLK_PLL_DDR_BASE] = &pll_ddr_base_clk.common.hw,
[CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
[CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,
[CLK_PLL_PERIPH_BASE] = &pll_periph_base_clk.common.hw,
[CLK_PLL_PERIPH] = &pll_periph_clk.hw,
[CLK_PLL_PERIPH_SATA] = &pll_periph_sata_clk.common.hw,
[CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
[CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
[CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
[CLK_CPU] = &cpu_clk.common.hw,
[CLK_AXI] = &axi_clk.common.hw,
[CLK_AHB] = &ahb_sun7i_clk.common.hw,
[CLK_APB0] = &apb0_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_AHB_OTG] = &ahb_otg_clk.common.hw,
[CLK_AHB_EHCI0] = &ahb_ehci0_clk.common.hw,
[CLK_AHB_OHCI0] = &ahb_ohci0_clk.common.hw,
[CLK_AHB_EHCI1] = &ahb_ehci1_clk.common.hw,
[CLK_AHB_OHCI1] = &ahb_ohci1_clk.common.hw,
[CLK_AHB_SS] = &ahb_ss_clk.common.hw,
[CLK_AHB_DMA] = &ahb_dma_clk.common.hw,
[CLK_AHB_BIST] = &ahb_bist_clk.common.hw,
[CLK_AHB_MMC0] = &ahb_mmc0_clk.common.hw,
[CLK_AHB_MMC1] = &ahb_mmc1_clk.common.hw,
[CLK_AHB_MMC2] = &ahb_mmc2_clk.common.hw,
[CLK_AHB_MMC3] = &ahb_mmc3_clk.common.hw,
[CLK_AHB_MS] = &ahb_ms_clk.common.hw,
[CLK_AHB_NAND] = &ahb_nand_clk.common.hw,
[CLK_AHB_SDRAM] = &ahb_sdram_clk.common.hw,
[CLK_AHB_ACE] = &ahb_ace_clk.common.hw,
[CLK_AHB_EMAC] = &ahb_emac_clk.common.hw,
[CLK_AHB_TS] = &ahb_ts_clk.common.hw,
[CLK_AHB_SPI0] = &ahb_spi0_clk.common.hw,
[CLK_AHB_SPI1] = &ahb_spi1_clk.common.hw,
[CLK_AHB_SPI2] = &ahb_spi2_clk.common.hw,
[CLK_AHB_SPI3] = &ahb_spi3_clk.common.hw,
[CLK_AHB_PATA] = &ahb_pata_clk.common.hw,
[CLK_AHB_SATA] = &ahb_sata_clk.common.hw,
[CLK_AHB_HSTIMER] = &ahb_hstimer_clk.common.hw,
[CLK_AHB_VE] = &ahb_ve_clk.common.hw,
[CLK_AHB_TVD] = &ahb_tvd_clk.common.hw,
[CLK_AHB_TVE0] = &ahb_tve0_clk.common.hw,
[CLK_AHB_TVE1] = &ahb_tve1_clk.common.hw,
[CLK_AHB_LCD0] = &ahb_lcd0_clk.common.hw,
[CLK_AHB_LCD1] = &ahb_lcd1_clk.common.hw,
[CLK_AHB_CSI0] = &ahb_csi0_clk.common.hw,
[CLK_AHB_CSI1] = &ahb_csi1_clk.common.hw,
[CLK_AHB_HDMI1] = &ahb_hdmi1_clk.common.hw,
[CLK_AHB_HDMI0] = &ahb_hdmi0_clk.common.hw,
[CLK_AHB_DE_BE0] = &ahb_de_be0_clk.common.hw,
[CLK_AHB_DE_BE1] = &ahb_de_be1_clk.common.hw,
[CLK_AHB_DE_FE0] = &ahb_de_fe0_clk.common.hw,
[CLK_AHB_DE_FE1] = &ahb_de_fe1_clk.common.hw,
[CLK_AHB_GMAC] = &ahb_gmac_clk.common.hw,
[CLK_AHB_MP] = &ahb_mp_clk.common.hw,
[CLK_AHB_GPU] = &ahb_gpu_clk.common.hw,
[CLK_APB0_CODEC] = &apb0_codec_clk.common.hw,
[CLK_APB0_SPDIF] = &apb0_spdif_clk.common.hw,
[CLK_APB0_AC97] = &apb0_ac97_clk.common.hw,
[CLK_APB0_I2S0] = &apb0_i2s0_clk.common.hw,
[CLK_APB0_I2S1] = &apb0_i2s1_clk.common.hw,
[CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
[CLK_APB0_IR0] = &apb0_ir0_clk.common.hw,
[CLK_APB0_IR1] = &apb0_ir1_clk.common.hw,
[CLK_APB0_I2S2] = &apb0_i2s2_clk.common.hw,
[CLK_APB0_KEYPAD] = &apb0_keypad_clk.common.hw,
[CLK_APB1_I2C0] = &apb1_i2c0_clk.common.hw,
[CLK_APB1_I2C1] = &apb1_i2c1_clk.common.hw,
[CLK_APB1_I2C2] = &apb1_i2c2_clk.common.hw,
[CLK_APB1_I2C3] = &apb1_i2c3_clk.common.hw,
[CLK_APB1_CAN] = &apb1_can_clk.common.hw,
[CLK_APB1_SCR] = &apb1_scr_clk.common.hw,
[CLK_APB1_PS20] = &apb1_ps20_clk.common.hw,
[CLK_APB1_PS21] = &apb1_ps21_clk.common.hw,
[CLK_APB1_I2C4] = &apb1_i2c4_clk.common.hw,
[CLK_APB1_UART0] = &apb1_uart0_clk.common.hw,
[CLK_APB1_UART1] = &apb1_uart1_clk.common.hw,
[CLK_APB1_UART2] = &apb1_uart2_clk.common.hw,
[CLK_APB1_UART3] = &apb1_uart3_clk.common.hw,
[CLK_APB1_UART4] = &apb1_uart4_clk.common.hw,
[CLK_APB1_UART5] = &apb1_uart5_clk.common.hw,
[CLK_APB1_UART6] = &apb1_uart6_clk.common.hw,
[CLK_APB1_UART7] = &apb1_uart7_clk.common.hw,
[CLK_NAND] = &nand_clk.common.hw,
[CLK_MS] = &ms_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
[CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
[CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
[CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
[CLK_MMC3] = &mmc3_clk.common.hw,
[CLK_MMC3_OUTPUT] = &mmc3_output_clk.common.hw,
[CLK_MMC3_SAMPLE] = &mmc3_sample_clk.common.hw,
[CLK_TS] = &ts_clk.common.hw,
[CLK_SS] = &ss_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI2] = &spi2_clk.common.hw,
[CLK_PATA] = &pata_clk.common.hw,
[CLK_IR0] = &ir0_sun7i_clk.common.hw,
[CLK_IR1] = &ir1_sun7i_clk.common.hw,
[CLK_I2S0] = &i2s0_clk.common.hw,
[CLK_AC97] = &ac97_clk.common.hw,
[CLK_SPDIF] = &spdif_clk.common.hw,
[CLK_KEYPAD] = &keypad_clk.common.hw,
[CLK_SATA] = &sata_clk.common.hw,
[CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
[CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
[CLK_USB_PHY] = &usb_phy_clk.common.hw,
/* CLK_GPS is unimplemented */
[CLK_SPI3] = &spi3_clk.common.hw,
[CLK_I2S1] = &i2s1_clk.common.hw,
[CLK_I2S2] = &i2s2_clk.common.hw,
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
[CLK_DRAM_CSI0] = &dram_csi0_clk.common.hw,
[CLK_DRAM_CSI1] = &dram_csi1_clk.common.hw,
[CLK_DRAM_TS] = &dram_ts_clk.common.hw,
[CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
[CLK_DRAM_TVE0] = &dram_tve0_clk.common.hw,
[CLK_DRAM_TVE1] = &dram_tve1_clk.common.hw,
[CLK_DRAM_OUT] = &dram_out_clk.common.hw,
[CLK_DRAM_DE_FE1] = &dram_de_fe1_clk.common.hw,
[CLK_DRAM_DE_FE0] = &dram_de_fe0_clk.common.hw,
[CLK_DRAM_DE_BE0] = &dram_de_be0_clk.common.hw,
[CLK_DRAM_DE_BE1] = &dram_de_be1_clk.common.hw,
[CLK_DRAM_MP] = &dram_mp_clk.common.hw,
[CLK_DRAM_ACE] = &dram_ace_clk.common.hw,
[CLK_DE_BE0] = &de_be0_clk.common.hw,
[CLK_DE_BE1] = &de_be1_clk.common.hw,
[CLK_DE_FE0] = &de_fe0_clk.common.hw,
[CLK_DE_FE1] = &de_fe1_clk.common.hw,
[CLK_DE_MP] = &de_mp_clk.common.hw,
[CLK_TCON0_CH0] = &tcon0_ch0_clk.common.hw,
[CLK_TCON1_CH0] = &tcon1_ch0_clk.common.hw,
[CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
[CLK_TVD_SCLK2] = &tvd_sclk2_sun7i_clk.common.hw,
[CLK_TVD] = &tvd_sclk1_sun7i_clk.common.hw,
[CLK_TCON0_CH1_SCLK2] = &tcon0_ch1_sclk2_clk.common.hw,
[CLK_TCON0_CH1] = &tcon0_ch1_clk.common.hw,
[CLK_TCON1_CH1_SCLK2] = &tcon1_ch1_sclk2_clk.common.hw,
[CLK_TCON1_CH1] = &tcon1_ch1_clk.common.hw,
[CLK_CSI0] = &csi0_clk.common.hw,
[CLK_CSI1] = &csi1_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_CODEC] = &codec_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_ACE] = &ace_clk.common.hw,
[CLK_HDMI] = &hdmi_clk.common.hw,
[CLK_GPU] = &gpu_sun7i_clk.common.hw,
[CLK_MBUS] = &mbus_sun7i_clk.common.hw,
[CLK_HDMI1_SLOW] = &hdmi1_slow_clk.common.hw,
[CLK_HDMI1] = &hdmi1_clk.common.hw,
[CLK_OUT_A] = &out_a_clk.common.hw,
[CLK_OUT_B] = &out_b_clk.common.hw,
},
.num = CLK_NUMBER_SUN7I,
};
static struct ccu_reset_map sunxi_a10_a20_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_PHY2] = { 0x0cc, BIT(2) },
[RST_GPS] = { 0x0d0, BIT(0) },
[RST_DE_BE0] = { 0x104, BIT(30) },
[RST_DE_BE1] = { 0x108, BIT(30) },
[RST_DE_FE0] = { 0x10c, BIT(30) },
[RST_DE_FE1] = { 0x110, BIT(30) },
[RST_DE_MP] = { 0x114, BIT(30) },
[RST_TVE0] = { 0x118, BIT(29) },
[RST_TCON0] = { 0x118, BIT(30) },
[RST_TVE1] = { 0x11c, BIT(29) },
[RST_TCON1] = { 0x11c, BIT(30) },
[RST_CSI0] = { 0x134, BIT(30) },
[RST_CSI1] = { 0x138, BIT(30) },
[RST_VE] = { 0x13c, BIT(0) },
[RST_ACE] = { 0x148, BIT(16) },
[RST_LVDS] = { 0x14c, BIT(0) },
[RST_GPU] = { 0x154, BIT(30) },
[RST_HDMI_H] = { 0x170, BIT(0) },
[RST_HDMI_SYS] = { 0x170, BIT(1) },
[RST_HDMI_AUDIO_DMA] = { 0x170, BIT(2) },
};
static const struct sunxi_ccu_desc sun4i_a10_ccu_desc = {
.ccu_clks = sun4i_sun7i_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun4i_sun7i_ccu_clks),
.hw_clks = &sun4i_a10_hw_clks,
.resets = sunxi_a10_a20_ccu_resets,
.num_resets = ARRAY_SIZE(sunxi_a10_a20_ccu_resets),
};
static const struct sunxi_ccu_desc sun7i_a20_ccu_desc = {
.ccu_clks = sun4i_sun7i_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun4i_sun7i_ccu_clks),
.hw_clks = &sun7i_a20_hw_clks,
.resets = sunxi_a10_a20_ccu_resets,
.num_resets = ARRAY_SIZE(sunxi_a10_a20_ccu_resets),
};
static int sun4i_a10_ccu_probe(struct platform_device *pdev)
{
const struct sunxi_ccu_desc *desc;
void __iomem *reg;
u32 val;
desc = of_device_get_match_data(&pdev->dev);
if (!desc)
return -EINVAL;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
val = readl(reg + SUN4I_PLL_AUDIO_REG);
/*
* Force VCO and PLL bias current to lowest setting. Higher
* settings interfere with sigma-delta modulation and result
* in audible noise and distortions when using SPDIF or I2S.
*/
val &= ~GENMASK(25, 16);
/* Force the PLL-Audio-1x divider to 1 */
val &= ~GENMASK(29, 26);
writel(val | (1 << 26), reg + SUN4I_PLL_AUDIO_REG);
/*
* Use the peripheral PLL6 as the AHB parent, instead of CPU /
* AXI which have rate changes due to cpufreq.
*
* This is especially a big deal for the HS timer whose parent
* clock is AHB.
*
* NB! These bits are undocumented in A10 manual.
*/
val = readl(reg + SUN4I_AHB_REG);
val &= ~GENMASK(7, 6);
writel(val | (2 << 6), reg + SUN4I_AHB_REG);
return devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
}
static const struct of_device_id sun4i_a10_ccu_ids[] = {
{
.compatible = "allwinner,sun4i-a10-ccu",
.data = &sun4i_a10_ccu_desc,
},
{
.compatible = "allwinner,sun7i-a20-ccu",
.data = &sun7i_a20_ccu_desc,
},
{ }
};
static struct platform_driver sun4i_a10_ccu_driver = {
.probe = sun4i_a10_ccu_probe,
.driver = {
.name = "sun4i-a10-ccu",
.suppress_bind_attrs = true,
.of_match_table = sun4i_a10_ccu_ids,
},
};
module_platform_driver(sun4i_a10_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun4i-a10.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 Chen-Yu Tsai. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu_mux.h"
#include "ccu_nkmp.h"
#include "ccu_nm.h"
#include "ccu_phase.h"
#include "ccu-sun8i-a83t.h"
#define CCU_SUN8I_A83T_LOCK_REG 0x20c
/*
* The CPU PLLs are actually NP clocks, with P being /1 or /4. However
* P should only be used for output frequencies lower than 228 MHz.
* Neither mainline Linux, U-boot, nor the vendor BSPs use these.
*
* For now we can just model it as a multiplier clock, and force P to /1.
*/
#define SUN8I_A83T_PLL_C0CPUX_REG 0x000
#define SUN8I_A83T_PLL_C1CPUX_REG 0x004
static struct ccu_mult pll_c0cpux_clk = {
.enable = BIT(31),
.lock = BIT(0),
.mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.common = {
.reg = SUN8I_A83T_PLL_C0CPUX_REG,
.lock_reg = CCU_SUN8I_A83T_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
&ccu_mult_ops,
CLK_SET_RATE_UNGATE),
},
};
static struct ccu_mult pll_c1cpux_clk = {
.enable = BIT(31),
.lock = BIT(1),
.mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.common = {
.reg = SUN8I_A83T_PLL_C1CPUX_REG,
.lock_reg = CCU_SUN8I_A83T_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
&ccu_mult_ops,
CLK_SET_RATE_UNGATE),
},
};
/*
* The Audio PLL has d1, d2 dividers in addition to the usual N, M
* factors. Since we only need 2 frequencies from this PLL: 22.5792 MHz
* and 24.576 MHz, ignore them for now. Enforce the default for them,
* which is d1 = 0, d2 = 1.
*/
#define SUN8I_A83T_PLL_AUDIO_REG 0x008
/* clock rates doubled for post divider */
static struct ccu_sdm_setting pll_audio_sdm_table[] = {
{ .rate = 45158400, .pattern = 0xc00121ff, .m = 29, .n = 54 },
{ .rate = 49152000, .pattern = 0xc000e147, .m = 30, .n = 61 },
};
static struct ccu_nm pll_audio_clk = {
.enable = BIT(31),
.lock = BIT(2),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.m = _SUNXI_CCU_DIV(0, 6),
.fixed_post_div = 2,
.sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, BIT(24),
0x284, BIT(31)),
.common = {
.reg = SUN8I_A83T_PLL_AUDIO_REG,
.lock_reg = CCU_SUN8I_A83T_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG |
CCU_FEATURE_FIXED_POSTDIV |
CCU_FEATURE_SIGMA_DELTA_MOD,
.hw.init = CLK_HW_INIT("pll-audio", "osc24M",
&ccu_nm_ops, CLK_SET_RATE_UNGATE),
},
};
/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
static struct ccu_nkmp pll_video0_clk = {
.enable = BIT(31),
.lock = BIT(3),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.m = _SUNXI_CCU_DIV(16, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 2), /* output divider */
.max_rate = 3000000000UL,
.common = {
.reg = 0x010,
.lock_reg = CCU_SUN8I_A83T_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-video0", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
static struct ccu_nkmp pll_ve_clk = {
.enable = BIT(31),
.lock = BIT(4),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.m = _SUNXI_CCU_DIV(16, 1), /* input divider */
.p = _SUNXI_CCU_DIV(18, 1), /* output divider */
.common = {
.reg = 0x018,
.lock_reg = CCU_SUN8I_A83T_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-ve", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
static struct ccu_nkmp pll_ddr_clk = {
.enable = BIT(31),
.lock = BIT(5),
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(16, 1), /* input divider */
.p = _SUNXI_CCU_DIV(18, 1), /* output divider */
.common = {
.reg = 0x020,
.lock_reg = CCU_SUN8I_A83T_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-ddr", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
static struct ccu_nkmp pll_periph_clk = {
.enable = BIT(31),
.lock = BIT(6),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.m = _SUNXI_CCU_DIV(16, 1), /* input divider */
.p = _SUNXI_CCU_DIV(18, 1), /* output divider */
.common = {
.reg = 0x028,
.lock_reg = CCU_SUN8I_A83T_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-periph", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
static struct ccu_nkmp pll_gpu_clk = {
.enable = BIT(31),
.lock = BIT(7),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.m = _SUNXI_CCU_DIV(16, 1), /* input divider */
.p = _SUNXI_CCU_DIV(18, 1), /* output divider */
.common = {
.reg = 0x038,
.lock_reg = CCU_SUN8I_A83T_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
static struct ccu_nkmp pll_hsic_clk = {
.enable = BIT(31),
.lock = BIT(8),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.m = _SUNXI_CCU_DIV(16, 1), /* input divider */
.p = _SUNXI_CCU_DIV(18, 1), /* output divider */
.common = {
.reg = 0x044,
.lock_reg = CCU_SUN8I_A83T_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-hsic", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
static struct ccu_nkmp pll_de_clk = {
.enable = BIT(31),
.lock = BIT(9),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.m = _SUNXI_CCU_DIV(16, 1), /* input divider */
.p = _SUNXI_CCU_DIV(18, 1), /* output divider */
.common = {
.reg = 0x048,
.lock_reg = CCU_SUN8I_A83T_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-de", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
static struct ccu_nkmp pll_video1_clk = {
.enable = BIT(31),
.lock = BIT(10),
.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
.m = _SUNXI_CCU_DIV(16, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 2), /* external divider p */
.max_rate = 3000000000UL,
.common = {
.reg = 0x04c,
.lock_reg = CCU_SUN8I_A83T_LOCK_REG,
.features = CCU_FEATURE_LOCK_REG,
.hw.init = CLK_HW_INIT("pll-video1", "osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
static const char * const c0cpux_parents[] = { "osc24M", "pll-c0cpux" };
static SUNXI_CCU_MUX(c0cpux_clk, "c0cpux", c0cpux_parents,
0x50, 12, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
static const char * const c1cpux_parents[] = { "osc24M", "pll-c1cpux" };
static SUNXI_CCU_MUX(c1cpux_clk, "c1cpux", c1cpux_parents,
0x50, 28, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
static SUNXI_CCU_M(axi0_clk, "axi0", "c0cpux", 0x050, 0, 2, 0);
static SUNXI_CCU_M(axi1_clk, "axi1", "c1cpux", 0x050, 16, 2, 0);
static const char * const ahb1_parents[] = { "osc16M-d512", "osc24M",
"pll-periph",
"pll-periph" };
static const struct ccu_mux_var_prediv ahb1_predivs[] = {
{ .index = 2, .shift = 6, .width = 2 },
{ .index = 3, .shift = 6, .width = 2 },
};
static struct ccu_div ahb1_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = {
.shift = 12,
.width = 2,
.var_predivs = ahb1_predivs,
.n_var_predivs = ARRAY_SIZE(ahb1_predivs),
},
.common = {
.reg = 0x054,
.hw.init = CLK_HW_INIT_PARENTS("ahb1",
ahb1_parents,
&ccu_div_ops,
0),
},
};
static SUNXI_CCU_M(apb1_clk, "apb1", "ahb1", 0x054, 8, 2, 0);
static const char * const apb2_parents[] = { "osc16M-d512", "osc24M",
"pll-periph", "pll-periph" };
static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
0, 5, /* M */
16, 2, /* P */
24, 2, /* mux */
0);
static const char * const ahb2_parents[] = { "ahb1", "pll-periph" };
static const struct ccu_mux_fixed_prediv ahb2_prediv = {
.index = 1, .div = 2
};
static struct ccu_mux ahb2_clk = {
.mux = {
.shift = 0,
.width = 2,
.fixed_predivs = &ahb2_prediv,
.n_predivs = 1,
},
.common = {
.reg = 0x05c,
.hw.init = CLK_HW_INIT_PARENTS("ahb2",
ahb2_parents,
&ccu_mux_ops,
0),
},
};
static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
0x060, BIT(1), 0);
static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1",
0x060, BIT(5), 0);
static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
0x060, BIT(6), 0);
static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
0x060, BIT(8), 0);
static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
0x060, BIT(9), 0);
static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
0x060, BIT(10), 0);
static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
0x060, BIT(13), 0);
static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
0x060, BIT(14), 0);
static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
0x060, BIT(17), 0);
static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
0x060, BIT(19), 0);
static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
0x060, BIT(20), 0);
static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
0x060, BIT(21), 0);
static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
0x060, BIT(24), 0);
static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb2",
0x060, BIT(26), 0);
static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",
0x060, BIT(27), 0);
static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb2",
0x060, BIT(29), 0);
static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
0x064, BIT(0), 0);
static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
0x064, BIT(4), 0);
static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1",
0x064, BIT(5), 0);
static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
0x064, BIT(8), 0);
static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",
0x064, BIT(11), 0);
static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
0x064, BIT(12), 0);
static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
0x064, BIT(20), 0);
static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
0x064, BIT(21), 0);
static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
0x064, BIT(22), 0);
static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
0x068, BIT(1), 0);
static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
0x068, BIT(5), 0);
static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
0x068, BIT(12), 0);
static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
0x068, BIT(13), 0);
static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
0x068, BIT(14), 0);
static SUNXI_CCU_GATE(bus_tdm_clk, "bus-tdm", "apb1",
0x068, BIT(15), 0);
static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
0x06c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
0x06c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
0x06c, BIT(2), 0);
static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
0x06c, BIT(16), 0);
static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
0x06c, BIT(17), 0);
static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
0x06c, BIT(18), 0);
static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
0x06c, BIT(19), 0);
static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
0x06c, BIT(20), 0);
static const char * const cci400_parents[] = { "osc24M", "pll-periph",
"pll-hsic" };
static struct ccu_div cci400_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(0, 2, 0),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0x078,
.hw.init = CLK_HW_INIT_PARENTS("cci400",
cci400_parents,
&ccu_div_ops,
CLK_IS_CRITICAL),
},
};
static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents,
0x080,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents,
0x088,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0-sample", "mmc0",
0x088, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0-output", "mmc0",
0x088, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents,
0x08c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1-sample", "mmc1",
0x08c, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1-output", "mmc1",
0x08c, 8, 3, 0);
static SUNXI_CCU_MP_MMC_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents,
0x090, 0);
static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2",
0x090, 20, 3, 0);
static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2-output", "mmc2",
0x090, 8, 3, 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents,
0x09c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents,
0x0a0,
0, 4, /* M */
16, 2, /* P */
24, 4, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents,
0x0a4,
0, 4, /* M */
16, 2, /* P */
24, 4, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_M_WITH_GATE(i2s0_clk, "i2s0", "pll-audio",
0x0b0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(i2s1_clk, "i2s1", "pll-audio",
0x0b4, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(i2s2_clk, "i2s2", "pll-audio",
0x0b8, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(tdm_clk, "tdm", "pll-audio",
0x0bc, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
0x0cc, BIT(8), 0);
static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
0x0cc, BIT(9), 0);
static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
0x0cc, BIT(10), 0);
static struct ccu_gate usb_hsic_12m_clk = {
.enable = BIT(11),
.common = {
.reg = 0x0cc,
.prediv = 2,
.features = CCU_FEATURE_ALL_PREDIV,
.hw.init = CLK_HW_INIT("usb-hsic-12m", "osc24M",
&ccu_gate_ops, 0),
}
};
static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
0x0cc, BIT(16), 0);
/* TODO divider has minimum of 2 */
static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr", 0x0f4, 0, 4, CLK_IS_CRITICAL);
static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
0x100, BIT(0), 0);
static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
0x100, BIT(1), 0);
static const char * const tcon0_parents[] = { "pll-video0" };
static SUNXI_CCU_MUX_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
0x118, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
static const char * const tcon1_parents[] = { "pll-video1" };
static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_clk, "tcon1", tcon1_parents,
0x11c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x130, BIT(16), 0);
static SUNXI_CCU_GATE(mipi_csi_clk, "mipi-csi", "osc24M", 0x130, BIT(31), 0);
static const char * const csi_mclk_parents[] = { "pll-video0", "pll-de",
"osc24M" };
static const u8 csi_mclk_table[] = { 0, 3, 5 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
csi_mclk_parents, csi_mclk_table,
0x134,
0, 5, /* M */
8, 3, /* mux */
BIT(15), /* gate */
0);
static const char * const csi_sclk_parents[] = { "pll-periph", "pll-ve" };
static const u8 csi_sclk_table[] = { 0, 5 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
csi_sclk_parents, csi_sclk_table,
0x134,
16, 4, /* M */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c,
16, 3, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0);
static const char * const hdmi_parents[] = { "pll-video1" };
static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
0x150,
0, 4, /* M */
24, 2, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0x154, BIT(31), 0);
static const char * const mbus_parents[] = { "osc24M", "pll-periph",
"pll-ddr" };
static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
0x15c,
0, 3, /* M */
24, 2, /* mux */
BIT(31), /* gate */
CLK_IS_CRITICAL);
static const char * const mipi_dsi0_parents[] = { "pll-video0" };
static const u8 mipi_dsi0_table[] = { 8 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi0_clk, "mipi-dsi0",
mipi_dsi0_parents, mipi_dsi0_table,
0x168,
0, 4, /* M */
24, 4, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static const char * const mipi_dsi1_parents[] = { "osc24M", "pll-video0" };
static const u8 mipi_dsi1_table[] = { 0, 9 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi1_clk, "mipi-dsi1",
mipi_dsi1_parents, mipi_dsi1_table,
0x16c,
0, 4, /* M */
24, 4, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(gpu_core_clk, "gpu-core", "pll-gpu", 0x1a0,
0, 3, BIT(31), CLK_SET_RATE_PARENT);
static const char * const gpu_memory_parents[] = { "pll-gpu", "pll-ddr" };
static SUNXI_CCU_M_WITH_MUX_GATE(gpu_memory_clk, "gpu-memory",
gpu_memory_parents,
0x1a4,
0, 3, /* M */
24, 1, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(gpu_hyd_clk, "gpu-hyd", "pll-gpu", 0x1a8,
0, 3, BIT(31), CLK_SET_RATE_PARENT);
static struct ccu_common *sun8i_a83t_ccu_clks[] = {
&pll_c0cpux_clk.common,
&pll_c1cpux_clk.common,
&pll_audio_clk.common,
&pll_video0_clk.common,
&pll_ve_clk.common,
&pll_ddr_clk.common,
&pll_periph_clk.common,
&pll_gpu_clk.common,
&pll_hsic_clk.common,
&pll_de_clk.common,
&pll_video1_clk.common,
&c0cpux_clk.common,
&c1cpux_clk.common,
&axi0_clk.common,
&axi1_clk.common,
&ahb1_clk.common,
&ahb2_clk.common,
&apb1_clk.common,
&apb2_clk.common,
&bus_mipi_dsi_clk.common,
&bus_ss_clk.common,
&bus_dma_clk.common,
&bus_mmc0_clk.common,
&bus_mmc1_clk.common,
&bus_mmc2_clk.common,
&bus_nand_clk.common,
&bus_dram_clk.common,
&bus_emac_clk.common,
&bus_hstimer_clk.common,
&bus_spi0_clk.common,
&bus_spi1_clk.common,
&bus_otg_clk.common,
&bus_ehci0_clk.common,
&bus_ehci1_clk.common,
&bus_ohci0_clk.common,
&bus_ve_clk.common,
&bus_tcon0_clk.common,
&bus_tcon1_clk.common,
&bus_csi_clk.common,
&bus_hdmi_clk.common,
&bus_de_clk.common,
&bus_gpu_clk.common,
&bus_msgbox_clk.common,
&bus_spinlock_clk.common,
&bus_spdif_clk.common,
&bus_pio_clk.common,
&bus_i2s0_clk.common,
&bus_i2s1_clk.common,
&bus_i2s2_clk.common,
&bus_tdm_clk.common,
&bus_i2c0_clk.common,
&bus_i2c1_clk.common,
&bus_i2c2_clk.common,
&bus_uart0_clk.common,
&bus_uart1_clk.common,
&bus_uart2_clk.common,
&bus_uart3_clk.common,
&bus_uart4_clk.common,
&cci400_clk.common,
&nand_clk.common,
&mmc0_clk.common,
&mmc0_sample_clk.common,
&mmc0_output_clk.common,
&mmc1_clk.common,
&mmc1_sample_clk.common,
&mmc1_output_clk.common,
&mmc2_clk.common,
&mmc2_sample_clk.common,
&mmc2_output_clk.common,
&ss_clk.common,
&spi0_clk.common,
&spi1_clk.common,
&i2s0_clk.common,
&i2s1_clk.common,
&i2s2_clk.common,
&tdm_clk.common,
&spdif_clk.common,
&usb_phy0_clk.common,
&usb_phy1_clk.common,
&usb_hsic_clk.common,
&usb_hsic_12m_clk.common,
&usb_ohci0_clk.common,
&dram_clk.common,
&dram_ve_clk.common,
&dram_csi_clk.common,
&tcon0_clk.common,
&tcon1_clk.common,
&csi_misc_clk.common,
&mipi_csi_clk.common,
&csi_mclk_clk.common,
&csi_sclk_clk.common,
&ve_clk.common,
&avs_clk.common,
&hdmi_clk.common,
&hdmi_slow_clk.common,
&mbus_clk.common,
&mipi_dsi0_clk.common,
&mipi_dsi1_clk.common,
&gpu_core_clk.common,
&gpu_memory_clk.common,
&gpu_hyd_clk.common,
};
static struct clk_hw_onecell_data sun8i_a83t_hw_clks = {
.hws = {
[CLK_PLL_C0CPUX] = &pll_c0cpux_clk.common.hw,
[CLK_PLL_C1CPUX] = &pll_c1cpux_clk.common.hw,
[CLK_PLL_AUDIO] = &pll_audio_clk.common.hw,
[CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
[CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
[CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
[CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
[CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
[CLK_PLL_DE] = &pll_de_clk.common.hw,
[CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
[CLK_C0CPUX] = &c0cpux_clk.common.hw,
[CLK_C1CPUX] = &c1cpux_clk.common.hw,
[CLK_AXI0] = &axi0_clk.common.hw,
[CLK_AXI1] = &axi1_clk.common.hw,
[CLK_AHB1] = &ahb1_clk.common.hw,
[CLK_AHB2] = &ahb2_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_APB2] = &apb2_clk.common.hw,
[CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
[CLK_BUS_SS] = &bus_ss_clk.common.hw,
[CLK_BUS_DMA] = &bus_dma_clk.common.hw,
[CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
[CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
[CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
[CLK_BUS_NAND] = &bus_nand_clk.common.hw,
[CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
[CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
[CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
[CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
[CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
[CLK_BUS_OTG] = &bus_otg_clk.common.hw,
[CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
[CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
[CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
[CLK_BUS_VE] = &bus_ve_clk.common.hw,
[CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
[CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
[CLK_BUS_CSI] = &bus_csi_clk.common.hw,
[CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
[CLK_BUS_DE] = &bus_de_clk.common.hw,
[CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
[CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
[CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
[CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
[CLK_BUS_PIO] = &bus_pio_clk.common.hw,
[CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
[CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
[CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
[CLK_BUS_TDM] = &bus_tdm_clk.common.hw,
[CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
[CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
[CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
[CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
[CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
[CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
[CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
[CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
[CLK_CCI400] = &cci400_clk.common.hw,
[CLK_NAND] = &nand_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
[CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
[CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
[CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
[CLK_SS] = &ss_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_I2S0] = &i2s0_clk.common.hw,
[CLK_I2S1] = &i2s1_clk.common.hw,
[CLK_I2S2] = &i2s2_clk.common.hw,
[CLK_TDM] = &tdm_clk.common.hw,
[CLK_SPDIF] = &spdif_clk.common.hw,
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
[CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
[CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
[CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw,
[CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
[CLK_DRAM] = &dram_clk.common.hw,
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
[CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
[CLK_TCON0] = &tcon0_clk.common.hw,
[CLK_TCON1] = &tcon1_clk.common.hw,
[CLK_CSI_MISC] = &csi_misc_clk.common.hw,
[CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
[CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
[CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_HDMI] = &hdmi_clk.common.hw,
[CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw,
[CLK_MBUS] = &mbus_clk.common.hw,
[CLK_MIPI_DSI0] = &mipi_dsi0_clk.common.hw,
[CLK_MIPI_DSI1] = &mipi_dsi1_clk.common.hw,
[CLK_GPU_CORE] = &gpu_core_clk.common.hw,
[CLK_GPU_MEMORY] = &gpu_memory_clk.common.hw,
[CLK_GPU_HYD] = &gpu_hyd_clk.common.hw,
},
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun8i_a83t_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_HSIC] = { 0x0cc, BIT(2) },
[RST_DRAM] = { 0x0f4, BIT(31) },
[RST_MBUS] = { 0x0fc, BIT(31) },
[RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
[RST_BUS_SS] = { 0x2c0, BIT(5) },
[RST_BUS_DMA] = { 0x2c0, BIT(6) },
[RST_BUS_MMC0] = { 0x2c0, BIT(8) },
[RST_BUS_MMC1] = { 0x2c0, BIT(9) },
[RST_BUS_MMC2] = { 0x2c0, BIT(10) },
[RST_BUS_NAND] = { 0x2c0, BIT(13) },
[RST_BUS_DRAM] = { 0x2c0, BIT(14) },
[RST_BUS_EMAC] = { 0x2c0, BIT(17) },
[RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
[RST_BUS_SPI0] = { 0x2c0, BIT(20) },
[RST_BUS_SPI1] = { 0x2c0, BIT(21) },
[RST_BUS_OTG] = { 0x2c0, BIT(24) },
[RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
[RST_BUS_EHCI1] = { 0x2c0, BIT(27) },
[RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
[RST_BUS_VE] = { 0x2c4, BIT(0) },
[RST_BUS_TCON0] = { 0x2c4, BIT(4) },
[RST_BUS_TCON1] = { 0x2c4, BIT(5) },
[RST_BUS_CSI] = { 0x2c4, BIT(8) },
[RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
[RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
[RST_BUS_DE] = { 0x2c4, BIT(12) },
[RST_BUS_GPU] = { 0x2c4, BIT(20) },
[RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
[RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
[RST_BUS_LVDS] = { 0x2c8, BIT(0) },
[RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
[RST_BUS_I2S0] = { 0x2d0, BIT(12) },
[RST_BUS_I2S1] = { 0x2d0, BIT(13) },
[RST_BUS_I2S2] = { 0x2d0, BIT(14) },
[RST_BUS_TDM] = { 0x2d0, BIT(15) },
[RST_BUS_I2C0] = { 0x2d8, BIT(0) },
[RST_BUS_I2C1] = { 0x2d8, BIT(1) },
[RST_BUS_I2C2] = { 0x2d8, BIT(2) },
[RST_BUS_UART0] = { 0x2d8, BIT(16) },
[RST_BUS_UART1] = { 0x2d8, BIT(17) },
[RST_BUS_UART2] = { 0x2d8, BIT(18) },
[RST_BUS_UART3] = { 0x2d8, BIT(19) },
[RST_BUS_UART4] = { 0x2d8, BIT(20) },
};
static const struct sunxi_ccu_desc sun8i_a83t_ccu_desc = {
.ccu_clks = sun8i_a83t_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_a83t_ccu_clks),
.hw_clks = &sun8i_a83t_hw_clks,
.resets = sun8i_a83t_ccu_resets,
.num_resets = ARRAY_SIZE(sun8i_a83t_ccu_resets),
};
#define SUN8I_A83T_PLL_P_SHIFT 16
#define SUN8I_A83T_PLL_N_SHIFT 8
#define SUN8I_A83T_PLL_N_WIDTH 8
static void sun8i_a83t_cpu_pll_fixup(void __iomem *reg)
{
u32 val = readl(reg);
/* bail out if P divider is not used */
if (!(val & BIT(SUN8I_A83T_PLL_P_SHIFT)))
return;
/*
* If P is used, output should be less than 288 MHz. When we
* set P to 1, we should also decrease the multiplier so the
* output doesn't go out of range, but not too much such that
* the multiplier stays above 12, the minimal operation value.
*
* To keep it simple, set the multiplier to 17, the reset value.
*/
val &= ~GENMASK(SUN8I_A83T_PLL_N_SHIFT + SUN8I_A83T_PLL_N_WIDTH - 1,
SUN8I_A83T_PLL_N_SHIFT);
val |= 17 << SUN8I_A83T_PLL_N_SHIFT;
/* And clear P */
val &= ~BIT(SUN8I_A83T_PLL_P_SHIFT);
writel(val, reg);
}
static int sun8i_a83t_ccu_probe(struct platform_device *pdev)
{
void __iomem *reg;
u32 val;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
/* Enforce d1 = 0, d2 = 1 for Audio PLL */
val = readl(reg + SUN8I_A83T_PLL_AUDIO_REG);
val &= ~BIT(16);
val |= BIT(18);
writel(val, reg + SUN8I_A83T_PLL_AUDIO_REG);
/* Enforce P = 1 for both CPU cluster PLLs */
sun8i_a83t_cpu_pll_fixup(reg + SUN8I_A83T_PLL_C0CPUX_REG);
sun8i_a83t_cpu_pll_fixup(reg + SUN8I_A83T_PLL_C1CPUX_REG);
return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_a83t_ccu_desc);
}
static const struct of_device_id sun8i_a83t_ccu_ids[] = {
{ .compatible = "allwinner,sun8i-a83t-ccu" },
{ }
};
static struct platform_driver sun8i_a83t_ccu_driver = {
.probe = sun8i_a83t_ccu_probe,
.driver = {
.name = "sun8i-a83t-ccu",
.suppress_bind_attrs = true,
.of_match_table = sun8i_a83t_ccu_ids,
},
};
module_platform_driver(sun8i_a83t_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun8i-a83t.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Yangtao Li <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu_mult.h"
#include "ccu_nk.h"
#include "ccu_nkm.h"
#include "ccu_nkmp.h"
#include "ccu_nm.h"
#include "ccu-sun50i-a100.h"
#define SUN50I_A100_PLL_SDM_ENABLE BIT(24)
#define SUN50I_A100_PLL_OUTPUT_ENABLE BIT(27)
#define SUN50I_A100_PLL_LOCK BIT(28)
#define SUN50I_A100_PLL_LOCK_ENABLE BIT(29)
#define SUN50I_A100_PLL_ENABLE BIT(31)
#define SUN50I_A100_PLL_PERIPH1_PATTERN0 0xd1303333
/*
* The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
* P should only be used for output frequencies lower than 288 MHz.
*
* For now we can just model it as a multiplier clock, and force P to /1.
*
* The M factor is present in the register's description, but not in the
* frequency formula, and it's documented as "M is only used for backdoor
* testing", so it's not modelled and then force to 0.
*/
#define SUN50I_A100_PLL_CPUX_REG 0x000
static struct ccu_mult pll_cpux_clk = {
.enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
.lock = SUN50I_A100_PLL_LOCK,
.mult = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.common = {
.reg = 0x000,
.hw.init = CLK_HW_INIT("pll-cpux", "dcxo24M",
&ccu_mult_ops,
CLK_SET_RATE_UNGATE),
},
};
/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
#define SUN50I_A100_PLL_DDR0_REG 0x010
static struct ccu_nkmp pll_ddr0_clk = {
.enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
.lock = SUN50I_A100_PLL_LOCK,
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
.common = {
.reg = 0x010,
.hw.init = CLK_HW_INIT("pll-ddr0", "dcxo24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE |
CLK_IS_CRITICAL),
},
};
#define SUN50I_A100_PLL_PERIPH0_REG 0x020
static struct ccu_nkmp pll_periph0_clk = {
.enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
.lock = SUN50I_A100_PLL_LOCK,
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
.fixed_post_div = 2,
.common = {
.reg = 0x020,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-periph0", "dcxo24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
#define SUN50I_A100_PLL_PERIPH1_REG 0x028
static struct ccu_nkmp pll_periph1_clk = {
.enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
.lock = SUN50I_A100_PLL_LOCK,
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
.fixed_post_div = 2,
.common = {
.reg = 0x028,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-periph1", "dcxo24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
#define SUN50I_A100_PLL_PERIPH1_PATTERN0_REG 0x128
#define SUN50I_A100_PLL_GPU_REG 0x030
static struct ccu_nkmp pll_gpu_clk = {
.enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
.lock = SUN50I_A100_PLL_LOCK,
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
.common = {
.reg = 0x030,
.hw.init = CLK_HW_INIT("pll-gpu", "dcxo24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
/*
* For Video PLLs, the output divider is described as "used for testing"
* in the user manual. So it's not modelled and forced to 0.
*/
#define SUN50I_A100_PLL_VIDEO0_REG 0x040
static struct ccu_nm pll_video0_clk = {
.enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
.lock = SUN50I_A100_PLL_LOCK,
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.fixed_post_div = 4,
.common = {
.reg = 0x040,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-video0", "dcxo24M",
&ccu_nm_ops,
CLK_SET_RATE_UNGATE),
},
};
#define SUN50I_A100_PLL_VIDEO1_REG 0x048
static struct ccu_nm pll_video1_clk = {
.enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
.lock = SUN50I_A100_PLL_LOCK,
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.fixed_post_div = 4,
.common = {
.reg = 0x048,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-video1", "dcxo24M",
&ccu_nm_ops,
CLK_SET_RATE_UNGATE),
},
};
#define SUN50I_A100_PLL_VIDEO2_REG 0x050
static struct ccu_nm pll_video2_clk = {
.enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
.lock = SUN50I_A100_PLL_LOCK,
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.fixed_post_div = 4,
.common = {
.reg = 0x050,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-video2", "dcxo24M",
&ccu_nm_ops,
CLK_SET_RATE_UNGATE),
},
};
#define SUN50I_A100_PLL_VE_REG 0x058
static struct ccu_nkmp pll_ve_clk = {
.enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
.lock = SUN50I_A100_PLL_LOCK,
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
.common = {
.reg = 0x058,
.hw.init = CLK_HW_INIT("pll-ve", "dcxo24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
/*
* The COM PLL has m0 dividers in addition to the usual N, M
* factors. Since we only need 1 frequencies from this PLL: 45.1584 MHz,
* ignore it for now.
*/
#define SUN50I_A100_PLL_COM_REG 0x060
static struct ccu_sdm_setting pll_com_sdm_table[] = {
{ .rate = 451584000, .pattern = 0xc0014396, .m = 2, .n = 37 },
};
static struct ccu_nm pll_com_clk = {
.enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
.lock = SUN50I_A100_PLL_LOCK,
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(0, 1),
.sdm = _SUNXI_CCU_SDM(pll_com_sdm_table, BIT(24),
0x160, BIT(31)),
.common = {
.reg = 0x060,
.features = CCU_FEATURE_SIGMA_DELTA_MOD,
.hw.init = CLK_HW_INIT("pll-com", "dcxo24M",
&ccu_nm_ops,
CLK_SET_RATE_UNGATE),
},
};
#define SUN50I_A100_PLL_VIDEO3_REG 0x068
static struct ccu_nm pll_video3_clk = {
.enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
.lock = SUN50I_A100_PLL_LOCK,
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
.fixed_post_div = 4,
.common = {
.reg = 0x068,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-video3", "dcxo24M",
&ccu_nm_ops,
CLK_SET_RATE_UNGATE),
},
};
/*
* The Audio PLL has m0, m1 dividers in addition to the usual N, M
* factors. Since we only need 4 frequencies from this PLL: 22.5792 MHz,
* 24.576 MHz, 90.3168MHz and 98.304MHz ignore them for now.
* Enforce the default for them, which is m0 = 1, m1 = 0.
*/
#define SUN50I_A100_PLL_AUDIO_REG 0x078
static struct ccu_sdm_setting pll_audio_sdm_table[] = {
{ .rate = 45158400, .pattern = 0xc001bcd3, .m = 18, .n = 33 },
{ .rate = 49152000, .pattern = 0xc001eb85, .m = 20, .n = 40 },
{ .rate = 180633600, .pattern = 0xc001288d, .m = 3, .n = 22 },
{ .rate = 196608000, .pattern = 0xc001eb85, .m = 5, .n = 40 },
};
static struct ccu_nm pll_audio_clk = {
.enable = SUN50I_A100_PLL_OUTPUT_ENABLE,
.lock = SUN50I_A100_PLL_LOCK,
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
.m = _SUNXI_CCU_DIV(16, 6),
.fixed_post_div = 2,
.sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, BIT(24),
0x178, BIT(31)),
.common = {
.reg = 0x078,
.features = CCU_FEATURE_FIXED_POSTDIV |
CCU_FEATURE_SIGMA_DELTA_MOD,
.hw.init = CLK_HW_INIT("pll-audio", "dcxo24M",
&ccu_nm_ops,
CLK_SET_RATE_UNGATE),
},
};
static const char * const cpux_parents[] = { "dcxo24M", "osc32k",
"iosc", "pll-cpux",
"pll-periph0" };
static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x500, 0, 2, 0);
static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0);
static const char * const psi_ahb1_ahb2_parents[] = { "dcxo24M", "osc32k",
"iosc", "pll-periph0",
"pll-periph0-2x" };
static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
psi_ahb1_ahb2_parents, 0x510,
0, 2, /* M */
8, 2, /* P */
24, 3, /* mux */
0);
static const char * const ahb3_apb1_apb2_parents[] = { "dcxo24M", "osc32k",
"psi-ahb1-ahb2",
"pll-periph0",
"pll-periph0-2x" };
static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c,
0, 2, /* M */
8, 2, /* P */
24, 3, /* mux */
0);
static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520,
0, 2, /* M */
8, 2, /* P */
24, 3, /* mux */
0);
static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
0, 2, /* M */
8, 2, /* P */
24, 3, /* mux */
0);
static const char * const mbus_parents[] = { "dcxo24M", "pll-ddr0",
"pll-periph0",
"pll-periph0-2x" };
static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x540,
0, 3, /* M */
24, 2, /* mux */
BIT(31), /* gate */
CLK_IS_CRITICAL);
static const char * const de_parents[] = { "pll-com", "pll-periph0-2x" };
static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de0", de_parents, 0x600,
0, 4, /* M */
24, 1, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
0x60c, BIT(0), 0);
static const char * const g2d_parents[] = { "pll-com", "pll-periph0-2x",
"pll-video0-2x", "pll-video1-2x",
"pll-video2-2x"};
static SUNXI_CCU_M_WITH_MUX_GATE(g2d_clk, "g2d",
g2d_parents,
0x630,
0, 4, /* M */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(bus_g2d_clk, "bus-g2d", "psi-ahb1-ahb2",
0x63c, BIT(0), 0);
static const char * const gpu_parents[] = { "pll-gpu" };
static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670,
0, 2, /* M */
24, 1, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
0x67c, BIT(0), 0);
static const char * const ce_parents[] = { "dcxo24M", "pll-periph0-2x" };
static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
0, 4, /* M */
8, 2, /* P */
24, 1, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
0x68c, BIT(0), 0);
static const char * const ve_parents[] = { "pll-ve" };
static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
0, 3, /* M */
24, 1, /* mux */
BIT(31), /* gate */
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
0x69c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
0x70c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "psi-ahb1-ahb2",
0x71c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "psi-ahb1-ahb2",
0x72c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2",
0x73c, BIT(0), 0);
static SUNXI_CCU_GATE(avs_clk, "avs", "dcxo24M", 0x740, BIT(31), 0);
static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2",
0x78c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2",
0x79c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0);
static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0);
static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus",
0x804, BIT(0), 0);
static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus",
0x804, BIT(1), 0);
static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus",
0x804, BIT(2), 0);
static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus",
0x804, BIT(5), 0);
static SUNXI_CCU_GATE(mbus_csi_clk, "mbus-csi", "mbus",
0x804, BIT(8), 0);
static SUNXI_CCU_GATE(mbus_isp_clk, "mbus-isp", "mbus",
0x804, BIT(9), 0);
static SUNXI_CCU_GATE(mbus_g2d_clk, "mbus-g2d", "mbus",
0x804, BIT(10), 0);
static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2",
0x80c, BIT(0), CLK_IS_CRITICAL);
static const char * const nand_spi_parents[] = { "dcxo24M",
"pll-periph0",
"pll-periph1",
"pll-periph0-2x",
"pll-periph1-2x" };
static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", nand_spi_parents, 0x810,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", nand_spi_parents, 0x814,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0);
static const char * const mmc_parents[] = { "dcxo24M", "pll-periph0-2x",
"pll-periph1-2x" };
static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830,
0, 4, /* M */
8, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
2, /* post-div */
CLK_SET_RATE_NO_REPARENT);
static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
0, 4, /* M */
8, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
2, /* post-div */
CLK_SET_RATE_NO_REPARENT);
static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838,
0, 4, /* M */
8, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
2, /* post-div */
CLK_SET_RATE_NO_REPARENT);
static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0);
static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0);
static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0);
static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 0x90c, BIT(4), 0);
static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0);
static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", nand_spi_parents, 0x940,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", nand_spi_parents, 0x944,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", nand_spi_parents, 0x948,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb3", 0x96c, BIT(2), 0);
static SUNXI_CCU_GATE(emac_25m_clk, "emac-25m", "ahb3", 0x970,
BIT(31) | BIT(30), 0);
static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb3", 0x97c, BIT(0), 0);
static const char * const ir_parents[] = { "osc32k", "iosc",
"pll-periph0", "pll-periph1" };
static SUNXI_CCU_MP_WITH_MUX_GATE(ir_rx_clk, "ir-rx", ir_parents, 0x990,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(bus_ir_rx_clk, "bus-ir-rx", "ahb3", 0x99c, BIT(0), 0);
static SUNXI_CCU_MP_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_parents, 0x9c0,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(bus_ir_tx_clk, "bus-ir-tx", "apb1", 0x9cc, BIT(0), 0);
static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb1", 0x9ec, BIT(0), 0);
static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
static const char * const audio_parents[] = { "pll-audio", "pll-com-audio" };
static struct ccu_div i2s0_clk = {
.enable = BIT(31),
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0xa10,
.hw.init = CLK_HW_INIT_PARENTS("i2s0",
audio_parents,
&ccu_div_ops,
CLK_SET_RATE_PARENT),
},
};
static struct ccu_div i2s1_clk = {
.enable = BIT(31),
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0xa14,
.hw.init = CLK_HW_INIT_PARENTS("i2s1",
audio_parents,
&ccu_div_ops,
CLK_SET_RATE_PARENT),
},
};
static struct ccu_div i2s2_clk = {
.enable = BIT(31),
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0xa18,
.hw.init = CLK_HW_INIT_PARENTS("i2s2",
audio_parents,
&ccu_div_ops,
CLK_SET_RATE_PARENT),
},
};
static struct ccu_div i2s3_clk = {
.enable = BIT(31),
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0xa1c,
.hw.init = CLK_HW_INIT_PARENTS("i2s3",
audio_parents,
&ccu_div_ops,
CLK_SET_RATE_PARENT),
},
};
static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 0xa20, BIT(0), 0);
static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 0xa20, BIT(1), 0);
static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 0xa20, BIT(2), 0);
static SUNXI_CCU_GATE(bus_i2s3_clk, "bus-i2s3", "apb1", 0xa20, BIT(3), 0);
static struct ccu_div spdif_clk = {
.enable = BIT(31),
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0xa24,
.hw.init = CLK_HW_INIT_PARENTS("spdif",
audio_parents,
&ccu_div_ops,
0),
},
};
static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0);
static struct ccu_div dmic_clk = {
.enable = BIT(31),
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0xa40,
.hw.init = CLK_HW_INIT_PARENTS("dmic",
audio_parents,
&ccu_div_ops,
0),
},
};
static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_dac_clk, "audio-codec-dac",
audio_parents, 0xa50,
0, 4, /* M */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_adc_clk, "audio-codec-adc",
audio_parents, 0xa54,
0, 4, /* M */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_4x_clk, "audio-codec-4x",
audio_parents, 0xa58,
0, 4, /* M */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(bus_audio_codec_clk, "bus-audio-codec", "apb1", 0xa5c,
BIT(0), 0);
/*
* There are OHCI 12M clock source selection bits for 2 USB 2.0 ports.
* We will force them to 0 (12M divided from 48M).
*/
#define SUN50I_A100_USB0_CLK_REG 0xa70
#define SUN50I_A100_USB1_CLK_REG 0xa74
static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0);
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "dcxo24M", 0xa70, BIT(29), 0);
static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M", 0xa74, BIT(31), 0);
static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "dcxo24M", 0xa74, BIT(29), 0);
static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb3", 0xa8c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0);
static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb3", 0xa8c, BIT(5), 0);
static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0);
static SUNXI_CCU_GATE(bus_lradc_clk, "bus-lradc", "ahb3", 0xa9c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_dpss_top0_clk, "bus-dpss-top0", "ahb3",
0xabc, BIT(0), 0);
static SUNXI_CCU_GATE(bus_dpss_top1_clk, "bus-dpss-top1", "ahb3",
0xacc, BIT(0), 0);
static const char * const mipi_dsi_parents[] = { "dcxo24M", "pll-periph0-2x",
"pll-periph0" };
static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi",
mipi_dsi_parents,
0xb24,
0, 4, /* M */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb3",
0xb4c, BIT(0), 0);
static const char * const tcon_lcd_parents[] = { "pll-video0-4x",
"pll-video1-4x",
"pll-video2-4x",
"pll-video3-4x",
"pll-periph0-2x" };
static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_lcd_clk, "tcon-lcd0",
tcon_lcd_parents, 0xb60,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(bus_tcon_lcd_clk, "bus-tcon-lcd0", "ahb3",
0xb7c, BIT(0), 0);
static const char * const ledc_parents[] = { "dcxo24M",
"pll-periph0" };
static SUNXI_CCU_MP_WITH_MUX_GATE(ledc_clk, "ledc",
ledc_parents, 0xbf0,
0, 4, /* M */
8, 2, /* P */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(bus_ledc_clk, "bus-ledc", "ahb3", 0xbfc, BIT(0), 0);
static const char * const csi_top_parents[] = { "pll-periph0-2x",
"pll-video0-2x",
"pll-video1-2x",
"pll-video2-2x",
"pll-video3-2x" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi_top_clk, "csi-top",
csi_top_parents, 0xc04,
0, 4, /* M */
24, 3, /* mux */
BIT(31), /* gate */
0);
static const char * const csi0_mclk_parents[] = { "dcxo24M", "pll-video2",
"pll-video3", "pll-video0",
"pll-video1" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk",
csi0_mclk_parents, 0xc08,
0, 5, /* M */
24, 3, /* mux */
BIT(31), /* gate */
0);
static const char * const csi1_mclk_parents[] = { "dcxo24M", "pll-video3",
"pll-video0", "pll-video1",
"pll-video2" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk",
csi1_mclk_parents, 0xc0c,
0, 5, /* M */
24, 3, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb3", 0xc1c, BIT(0), 0);
static const char * const csi_isp_parents[] = { "pll-periph0-2x",
"pll-video0-2x",
"pll-video1-2x",
"pll-video2-2x",
"pll-video3-2x" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi_isp_clk, "csi-isp",
csi_isp_parents, 0xc20,
0, 5, /* M */
24, 3, /* mux */
BIT(31), /* gate */
0);
/* Fixed factor clocks */
static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
static CLK_FIXED_FACTOR_HW(pll_com_audio_clk, "pll-com-audio",
&pll_com_clk.common.hw,
5, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
&pll_periph0_clk.common.hw,
1, 2, 0);
static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
&pll_periph1_clk.common.hw,
1, 2, 0);
static const struct clk_hw *pll_video0_parents[] = {
&pll_video0_clk.common.hw
};
static CLK_FIXED_FACTOR_HWS(pll_video0_4x_clk, "pll-video0-4x",
pll_video0_parents,
1, 4, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_video0_2x_clk, "pll-video0-2x",
pll_video0_parents,
1, 2, CLK_SET_RATE_PARENT);
static const struct clk_hw *pll_video1_parents[] = {
&pll_video1_clk.common.hw
};
static CLK_FIXED_FACTOR_HWS(pll_video1_4x_clk, "pll-video1-4x",
pll_video1_parents,
1, 4, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_video1_2x_clk, "pll-video1-2x",
pll_video1_parents,
1, 2, CLK_SET_RATE_PARENT);
static const struct clk_hw *pll_video2_parents[] = {
&pll_video2_clk.common.hw
};
static CLK_FIXED_FACTOR_HWS(pll_video2_4x_clk, "pll-video2-4x",
pll_video2_parents,
1, 4, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_video2_2x_clk, "pll-video2-2x",
pll_video2_parents,
1, 2, CLK_SET_RATE_PARENT);
static const struct clk_hw *pll_video3_parents[] = {
&pll_video3_clk.common.hw
};
static CLK_FIXED_FACTOR_HWS(pll_video3_4x_clk, "pll-video3-4x",
pll_video3_parents,
1, 4, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_video3_2x_clk, "pll-video3-2x",
pll_video3_parents,
1, 2, CLK_SET_RATE_PARENT);
static struct ccu_common *sun50i_a100_ccu_clks[] = {
&pll_cpux_clk.common,
&pll_ddr0_clk.common,
&pll_periph0_clk.common,
&pll_periph1_clk.common,
&pll_gpu_clk.common,
&pll_video0_clk.common,
&pll_video1_clk.common,
&pll_video2_clk.common,
&pll_video3_clk.common,
&pll_ve_clk.common,
&pll_com_clk.common,
&pll_audio_clk.common,
&cpux_clk.common,
&axi_clk.common,
&cpux_apb_clk.common,
&psi_ahb1_ahb2_clk.common,
&ahb3_clk.common,
&apb1_clk.common,
&apb2_clk.common,
&mbus_clk.common,
&de_clk.common,
&bus_de_clk.common,
&g2d_clk.common,
&bus_g2d_clk.common,
&gpu_clk.common,
&bus_gpu_clk.common,
&ce_clk.common,
&bus_ce_clk.common,
&ve_clk.common,
&bus_ve_clk.common,
&bus_dma_clk.common,
&bus_msgbox_clk.common,
&bus_spinlock_clk.common,
&bus_hstimer_clk.common,
&avs_clk.common,
&bus_dbg_clk.common,
&bus_psi_clk.common,
&bus_pwm_clk.common,
&bus_iommu_clk.common,
&mbus_dma_clk.common,
&mbus_ve_clk.common,
&mbus_ce_clk.common,
&mbus_nand_clk.common,
&mbus_csi_clk.common,
&mbus_isp_clk.common,
&mbus_g2d_clk.common,
&bus_dram_clk.common,
&nand0_clk.common,
&nand1_clk.common,
&bus_nand_clk.common,
&mmc0_clk.common,
&mmc1_clk.common,
&mmc2_clk.common,
&bus_mmc0_clk.common,
&bus_mmc1_clk.common,
&bus_mmc2_clk.common,
&bus_uart0_clk.common,
&bus_uart1_clk.common,
&bus_uart2_clk.common,
&bus_uart3_clk.common,
&bus_uart4_clk.common,
&bus_i2c0_clk.common,
&bus_i2c1_clk.common,
&bus_i2c2_clk.common,
&bus_i2c3_clk.common,
&spi0_clk.common,
&spi1_clk.common,
&spi2_clk.common,
&bus_spi0_clk.common,
&bus_spi1_clk.common,
&bus_spi2_clk.common,
&emac_25m_clk.common,
&bus_emac_clk.common,
&ir_rx_clk.common,
&bus_ir_rx_clk.common,
&ir_tx_clk.common,
&bus_ir_tx_clk.common,
&bus_gpadc_clk.common,
&bus_ths_clk.common,
&i2s0_clk.common,
&i2s1_clk.common,
&i2s2_clk.common,
&i2s3_clk.common,
&bus_i2s0_clk.common,
&bus_i2s1_clk.common,
&bus_i2s2_clk.common,
&bus_i2s3_clk.common,
&spdif_clk.common,
&bus_spdif_clk.common,
&dmic_clk.common,
&bus_dmic_clk.common,
&audio_codec_dac_clk.common,
&audio_codec_adc_clk.common,
&audio_codec_4x_clk.common,
&bus_audio_codec_clk.common,
&usb_ohci0_clk.common,
&usb_phy0_clk.common,
&usb_ohci1_clk.common,
&usb_phy1_clk.common,
&bus_ohci0_clk.common,
&bus_ohci1_clk.common,
&bus_ehci0_clk.common,
&bus_ehci1_clk.common,
&bus_otg_clk.common,
&bus_lradc_clk.common,
&bus_dpss_top0_clk.common,
&bus_dpss_top1_clk.common,
&mipi_dsi_clk.common,
&bus_mipi_dsi_clk.common,
&tcon_lcd_clk.common,
&bus_tcon_lcd_clk.common,
&ledc_clk.common,
&bus_ledc_clk.common,
&csi_top_clk.common,
&csi0_mclk_clk.common,
&csi1_mclk_clk.common,
&bus_csi_clk.common,
&csi_isp_clk.common,
};
static struct clk_hw_onecell_data sun50i_a100_hw_clks = {
.hws = {
[CLK_OSC12M] = &osc12M_clk.hw,
[CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
[CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
[CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
[CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
[CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
[CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
[CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
[CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
[CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
[CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.hw,
[CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
[CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
[CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.hw,
[CLK_PLL_VIDEO2] = &pll_video2_clk.common.hw,
[CLK_PLL_VIDEO2_2X] = &pll_video2_2x_clk.hw,
[CLK_PLL_VIDEO2_4X] = &pll_video2_4x_clk.hw,
[CLK_PLL_VIDEO3] = &pll_video3_clk.common.hw,
[CLK_PLL_VIDEO3_2X] = &pll_video3_2x_clk.hw,
[CLK_PLL_VIDEO3_4X] = &pll_video3_4x_clk.hw,
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
[CLK_PLL_COM] = &pll_com_clk.common.hw,
[CLK_PLL_COM_AUDIO] = &pll_com_audio_clk.hw,
[CLK_PLL_AUDIO] = &pll_audio_clk.common.hw,
[CLK_CPUX] = &cpux_clk.common.hw,
[CLK_AXI] = &axi_clk.common.hw,
[CLK_CPUX_APB] = &cpux_apb_clk.common.hw,
[CLK_PSI_AHB1_AHB2] = &psi_ahb1_ahb2_clk.common.hw,
[CLK_AHB3] = &ahb3_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_APB2] = &apb2_clk.common.hw,
[CLK_MBUS] = &mbus_clk.common.hw,
[CLK_DE] = &de_clk.common.hw,
[CLK_BUS_DE] = &bus_de_clk.common.hw,
[CLK_G2D] = &g2d_clk.common.hw,
[CLK_BUS_G2D] = &bus_g2d_clk.common.hw,
[CLK_GPU] = &gpu_clk.common.hw,
[CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
[CLK_CE] = &ce_clk.common.hw,
[CLK_BUS_CE] = &bus_ce_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_BUS_VE] = &bus_ve_clk.common.hw,
[CLK_BUS_DMA] = &bus_dma_clk.common.hw,
[CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
[CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
[CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
[CLK_BUS_PSI] = &bus_psi_clk.common.hw,
[CLK_BUS_PWM] = &bus_pwm_clk.common.hw,
[CLK_BUS_IOMMU] = &bus_iommu_clk.common.hw,
[CLK_MBUS_DMA] = &mbus_dma_clk.common.hw,
[CLK_MBUS_VE] = &mbus_ve_clk.common.hw,
[CLK_MBUS_CE] = &mbus_ce_clk.common.hw,
[CLK_MBUS_NAND] = &mbus_nand_clk.common.hw,
[CLK_MBUS_CSI] = &mbus_csi_clk.common.hw,
[CLK_MBUS_ISP] = &mbus_isp_clk.common.hw,
[CLK_MBUS_G2D] = &mbus_g2d_clk.common.hw,
[CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
[CLK_NAND0] = &nand0_clk.common.hw,
[CLK_NAND1] = &nand1_clk.common.hw,
[CLK_BUS_NAND] = &bus_nand_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
[CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
[CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
[CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
[CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
[CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
[CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
[CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
[CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
[CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
[CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
[CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI2] = &spi2_clk.common.hw,
[CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
[CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
[CLK_BUS_SPI2] = &bus_spi2_clk.common.hw,
[CLK_EMAC_25M] = &emac_25m_clk.common.hw,
[CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
[CLK_IR_RX] = &ir_rx_clk.common.hw,
[CLK_BUS_IR_RX] = &bus_ir_rx_clk.common.hw,
[CLK_IR_TX] = &ir_tx_clk.common.hw,
[CLK_BUS_IR_TX] = &bus_ir_tx_clk.common.hw,
[CLK_BUS_GPADC] = &bus_gpadc_clk.common.hw,
[CLK_BUS_THS] = &bus_ths_clk.common.hw,
[CLK_I2S0] = &i2s0_clk.common.hw,
[CLK_I2S1] = &i2s1_clk.common.hw,
[CLK_I2S2] = &i2s2_clk.common.hw,
[CLK_I2S3] = &i2s3_clk.common.hw,
[CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
[CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
[CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
[CLK_BUS_I2S3] = &bus_i2s3_clk.common.hw,
[CLK_SPDIF] = &spdif_clk.common.hw,
[CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
[CLK_DMIC] = &dmic_clk.common.hw,
[CLK_BUS_DMIC] = &bus_dmic_clk.common.hw,
[CLK_AUDIO_DAC] = &audio_codec_dac_clk.common.hw,
[CLK_AUDIO_ADC] = &audio_codec_adc_clk.common.hw,
[CLK_AUDIO_4X] = &audio_codec_4x_clk.common.hw,
[CLK_BUS_AUDIO_CODEC] = &bus_audio_codec_clk.common.hw,
[CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
[CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
[CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
[CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
[CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
[CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
[CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
[CLK_BUS_OTG] = &bus_otg_clk.common.hw,
[CLK_BUS_LRADC] = &bus_lradc_clk.common.hw,
[CLK_BUS_DPSS_TOP0] = &bus_dpss_top0_clk.common.hw,
[CLK_BUS_DPSS_TOP1] = &bus_dpss_top1_clk.common.hw,
[CLK_MIPI_DSI] = &mipi_dsi_clk.common.hw,
[CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
[CLK_TCON_LCD] = &tcon_lcd_clk.common.hw,
[CLK_BUS_TCON_LCD] = &bus_tcon_lcd_clk.common.hw,
[CLK_LEDC] = &ledc_clk.common.hw,
[CLK_BUS_LEDC] = &bus_ledc_clk.common.hw,
[CLK_CSI_TOP] = &csi_top_clk.common.hw,
[CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
[CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
[CLK_BUS_CSI] = &bus_csi_clk.common.hw,
[CLK_CSI_ISP] = &csi_isp_clk.common.hw,
},
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun50i_a100_ccu_resets[] = {
[RST_MBUS] = { 0x540, BIT(30) },
[RST_BUS_DE] = { 0x60c, BIT(16) },
[RST_BUS_G2D] = { 0x63c, BIT(16) },
[RST_BUS_GPU] = { 0x67c, BIT(16) },
[RST_BUS_CE] = { 0x68c, BIT(16) },
[RST_BUS_VE] = { 0x69c, BIT(16) },
[RST_BUS_DMA] = { 0x70c, BIT(16) },
[RST_BUS_MSGBOX] = { 0x71c, BIT(16) },
[RST_BUS_SPINLOCK] = { 0x72c, BIT(16) },
[RST_BUS_HSTIMER] = { 0x73c, BIT(16) },
[RST_BUS_DBG] = { 0x78c, BIT(16) },
[RST_BUS_PSI] = { 0x79c, BIT(16) },
[RST_BUS_PWM] = { 0x7ac, BIT(16) },
[RST_BUS_DRAM] = { 0x80c, BIT(16) },
[RST_BUS_NAND] = { 0x82c, BIT(16) },
[RST_BUS_MMC0] = { 0x84c, BIT(16) },
[RST_BUS_MMC1] = { 0x84c, BIT(17) },
[RST_BUS_MMC2] = { 0x84c, BIT(18) },
[RST_BUS_UART0] = { 0x90c, BIT(16) },
[RST_BUS_UART1] = { 0x90c, BIT(17) },
[RST_BUS_UART2] = { 0x90c, BIT(18) },
[RST_BUS_UART3] = { 0x90c, BIT(19) },
[RST_BUS_UART4] = { 0x90c, BIT(20) },
[RST_BUS_I2C0] = { 0x91c, BIT(16) },
[RST_BUS_I2C1] = { 0x91c, BIT(17) },
[RST_BUS_I2C2] = { 0x91c, BIT(18) },
[RST_BUS_I2C3] = { 0x91c, BIT(19) },
[RST_BUS_SPI0] = { 0x96c, BIT(16) },
[RST_BUS_SPI1] = { 0x96c, BIT(17) },
[RST_BUS_SPI2] = { 0x96c, BIT(18) },
[RST_BUS_EMAC] = { 0x97c, BIT(16) },
[RST_BUS_IR_RX] = { 0x99c, BIT(16) },
[RST_BUS_IR_TX] = { 0x9cc, BIT(16) },
[RST_BUS_GPADC] = { 0x9ec, BIT(16) },
[RST_BUS_THS] = { 0x9fc, BIT(16) },
[RST_BUS_I2S0] = { 0xa20, BIT(16) },
[RST_BUS_I2S1] = { 0xa20, BIT(17) },
[RST_BUS_I2S2] = { 0xa20, BIT(18) },
[RST_BUS_I2S3] = { 0xa20, BIT(19) },
[RST_BUS_SPDIF] = { 0xa2c, BIT(16) },
[RST_BUS_DMIC] = { 0xa4c, BIT(16) },
[RST_BUS_AUDIO_CODEC] = { 0xa5c, BIT(16) },
[RST_USB_PHY0] = { 0xa70, BIT(30) },
[RST_USB_PHY1] = { 0xa74, BIT(30) },
[RST_BUS_OHCI0] = { 0xa8c, BIT(16) },
[RST_BUS_OHCI1] = { 0xa8c, BIT(17) },
[RST_BUS_EHCI0] = { 0xa8c, BIT(20) },
[RST_BUS_EHCI1] = { 0xa8c, BIT(21) },
[RST_BUS_OTG] = { 0xa8c, BIT(24) },
[RST_BUS_LRADC] = { 0xa9c, BIT(16) },
[RST_BUS_DPSS_TOP0] = { 0xabc, BIT(16) },
[RST_BUS_DPSS_TOP1] = { 0xacc, BIT(16) },
[RST_BUS_MIPI_DSI] = { 0xb4c, BIT(16) },
[RST_BUS_TCON_LCD] = { 0xb7c, BIT(16) },
[RST_BUS_LVDS] = { 0xbac, BIT(16) },
[RST_BUS_LEDC] = { 0xbfc, BIT(16) },
[RST_BUS_CSI] = { 0xc1c, BIT(16) },
[RST_BUS_CSI_ISP] = { 0xc2c, BIT(16) },
};
static const struct sunxi_ccu_desc sun50i_a100_ccu_desc = {
.ccu_clks = sun50i_a100_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun50i_a100_ccu_clks),
.hw_clks = &sun50i_a100_hw_clks,
.resets = sun50i_a100_ccu_resets,
.num_resets = ARRAY_SIZE(sun50i_a100_ccu_resets),
};
static const u32 sun50i_a100_pll_regs[] = {
SUN50I_A100_PLL_CPUX_REG,
SUN50I_A100_PLL_DDR0_REG,
SUN50I_A100_PLL_PERIPH0_REG,
SUN50I_A100_PLL_PERIPH1_REG,
SUN50I_A100_PLL_GPU_REG,
SUN50I_A100_PLL_VIDEO0_REG,
SUN50I_A100_PLL_VIDEO1_REG,
SUN50I_A100_PLL_VIDEO2_REG,
SUN50I_A100_PLL_VIDEO3_REG,
SUN50I_A100_PLL_VE_REG,
SUN50I_A100_PLL_COM_REG,
SUN50I_A100_PLL_AUDIO_REG,
};
static const u32 sun50i_a100_pll_video_regs[] = {
SUN50I_A100_PLL_VIDEO0_REG,
SUN50I_A100_PLL_VIDEO1_REG,
SUN50I_A100_PLL_VIDEO2_REG,
SUN50I_A100_PLL_VIDEO3_REG,
};
static const u32 sun50i_a100_usb2_clk_regs[] = {
SUN50I_A100_USB0_CLK_REG,
SUN50I_A100_USB1_CLK_REG,
};
static struct ccu_pll_nb sun50i_a100_pll_cpu_nb = {
.common = &pll_cpux_clk.common,
/* copy from pll_cpux_clk */
.enable = BIT(27),
.lock = BIT(28),
};
static struct ccu_mux_nb sun50i_a100_cpu_nb = {
.common = &cpux_clk.common,
.cm = &cpux_clk.mux,
.delay_us = 1,
.bypass_index = 4, /* index of pll periph0 */
};
static int sun50i_a100_ccu_probe(struct platform_device *pdev)
{
void __iomem *reg;
u32 val;
int i, ret;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
/*
* Enable lock and enable bits on all PLLs.
*
* Due to the current design, multiple PLLs share one power switch,
* so switching PLL is easy to cause stability problems.
* When initializing, we enable them by default. When disable,
* we only turn off the output of PLL.
*/
for (i = 0; i < ARRAY_SIZE(sun50i_a100_pll_regs); i++) {
val = readl(reg + sun50i_a100_pll_regs[i]);
val |= SUN50I_A100_PLL_LOCK_ENABLE | SUN50I_A100_PLL_ENABLE;
writel(val, reg + sun50i_a100_pll_regs[i]);
}
/*
* In order to pass the EMI certification, the SDM function of
* the peripheral 1 bus is enabled, and the frequency is still
* calculated using the previous division factor.
*/
writel(SUN50I_A100_PLL_PERIPH1_PATTERN0,
reg + SUN50I_A100_PLL_PERIPH1_PATTERN0_REG);
val = readl(reg + SUN50I_A100_PLL_PERIPH1_REG);
val |= SUN50I_A100_PLL_SDM_ENABLE;
writel(val, reg + SUN50I_A100_PLL_PERIPH1_REG);
/*
* Force the output divider of video PLLs to 0.
*
* See the comment before pll-video0 definition for the reason.
*/
for (i = 0; i < ARRAY_SIZE(sun50i_a100_pll_video_regs); i++) {
val = readl(reg + sun50i_a100_pll_video_regs[i]);
val &= ~BIT(0);
writel(val, reg + sun50i_a100_pll_video_regs[i]);
}
/*
* Enforce m1 = 0, m0 = 1 for Audio PLL
*
* See the comment before pll-audio definition for the reason.
*/
val = readl(reg + SUN50I_A100_PLL_AUDIO_REG);
val &= ~BIT(1);
val |= BIT(0);
writel(val, reg + SUN50I_A100_PLL_AUDIO_REG);
/*
* Force OHCI 12M clock sources to 00 (12MHz divided from 48MHz)
*
* This clock mux is still mysterious, and the code just enforces
* it to have a valid clock parent.
*/
for (i = 0; i < ARRAY_SIZE(sun50i_a100_usb2_clk_regs); i++) {
val = readl(reg + sun50i_a100_usb2_clk_regs[i]);
val &= ~GENMASK(25, 24);
writel(val, reg + sun50i_a100_usb2_clk_regs[i]);
}
ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a100_ccu_desc);
if (ret)
return ret;
/* Gate then ungate PLL CPU after any rate changes */
ccu_pll_notifier_register(&sun50i_a100_pll_cpu_nb);
/* Reparent CPU during PLL CPU rate changes */
ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
&sun50i_a100_cpu_nb);
return 0;
}
static const struct of_device_id sun50i_a100_ccu_ids[] = {
{ .compatible = "allwinner,sun50i-a100-ccu" },
{ }
};
static struct platform_driver sun50i_a100_ccu_driver = {
.probe = sun50i_a100_ccu_probe,
.driver = {
.name = "sun50i-a100-ccu",
.suppress_bind_attrs = true,
.of_match_table = sun50i_a100_ccu_ids,
},
};
module_platform_driver(sun50i_a100_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun50i-a100.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 Icenowy Zheng <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "ccu_common.h"
#include "ccu_reset.h"
#include "ccu_div.h"
#include "ccu_gate.h"
#include "ccu_mp.h"
#include "ccu_mult.h"
#include "ccu_nk.h"
#include "ccu_nkm.h"
#include "ccu_nkmp.h"
#include "ccu_nm.h"
#include "ccu_phase.h"
#include "ccu-sun8i-r40.h"
/* TODO: The result of N*K is required to be in [10, 88] range. */
static struct ccu_nkmp pll_cpu_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT(8, 5),
.k = _SUNXI_CCU_MULT(4, 2),
.m = _SUNXI_CCU_DIV(0, 2),
.p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
.common = {
.reg = 0x000,
.hw.init = CLK_HW_INIT("pll-cpu",
"osc24M",
&ccu_nkmp_ops,
CLK_SET_RATE_UNGATE),
},
};
/*
* The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
* the base (2x, 4x and 8x), and one variable divider (the one true
* pll audio).
*
* With sigma-delta modulation for fractional-N on the audio PLL,
* we have to use specific dividers. This means the variable divider
* can no longer be used, as the audio codec requests the exact clock
* rates we support through this mechanism. So we now hard code the
* variable divider to 1. This means the clock rates will no longer
* match the clock names.
*/
#define SUN8I_R40_PLL_AUDIO_REG 0x008
static struct ccu_sdm_setting pll_audio_sdm_table[] = {
{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
};
static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
"osc24M", 0x008,
8, 7, /* N */
0, 5, /* M */
pll_audio_sdm_table, BIT(24),
0x284, BIT(31),
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
"osc24M", 0x0010,
192000000, /* Minimum rate */
1008000000, /* Maximum rate */
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
/* TODO: The result of N/M is required to be in [8, 25] range. */
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
"osc24M", 0x0018,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
/* TODO: The result of N*K is required to be in [10, 77] range. */
static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
"osc24M", 0x020,
8, 5, /* N */
4, 2, /* K */
0, 2, /* M */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
/* TODO: The result of N*K is required to be in [21, 58] range. */
static struct ccu_nk pll_periph0_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT(8, 5),
.k = _SUNXI_CCU_MULT(4, 2),
.fixed_post_div = 2,
.common = {
.reg = 0x028,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
&ccu_nk_ops,
CLK_SET_RATE_UNGATE),
},
};
static struct ccu_div pll_periph0_sata_clk = {
.enable = BIT(24),
.div = _SUNXI_CCU_DIV(0, 2),
/*
* The formula of pll-periph0 (1x) is 24MHz*N*K/2, and the formula
* of pll-periph0-sata is 24MHz*N*K/M/6, so the postdiv here is
* 6/2 = 3.
*/
.fixed_post_div = 3,
.common = {
.reg = 0x028,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-periph0-sata",
"pll-periph0",
&ccu_div_ops, 0),
},
};
/* TODO: The result of N*K is required to be in [21, 58] range. */
static struct ccu_nk pll_periph1_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT(8, 5),
.k = _SUNXI_CCU_MULT(4, 2),
.fixed_post_div = 2,
.common = {
.reg = 0x02c,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
&ccu_nk_ops,
CLK_SET_RATE_UNGATE),
},
};
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
"osc24M", 0x030,
192000000, /* Minimum rate */
1008000000, /* Maximum rate */
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static struct ccu_nkm pll_sata_clk = {
.enable = BIT(31),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT(8, 5),
.k = _SUNXI_CCU_MULT(4, 2),
.m = _SUNXI_CCU_DIV(0, 2),
.fixed_post_div = 6,
.common = {
.reg = 0x034,
.features = CCU_FEATURE_FIXED_POSTDIV,
.hw.init = CLK_HW_INIT("pll-sata", "osc24M",
&ccu_nkm_ops,
CLK_SET_RATE_UNGATE),
},
};
static const char * const pll_sata_out_parents[] = { "pll-sata",
"pll-periph0-sata" };
static SUNXI_CCU_MUX_WITH_GATE(pll_sata_out_clk, "pll-sata-out",
pll_sata_out_parents, 0x034,
30, 1, /* mux */
BIT(14), /* gate */
CLK_SET_RATE_PARENT);
/* TODO: The result of N/M is required to be in [8, 25] range. */
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
"osc24M", 0x038,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
/*
* The MIPI PLL has 2 modes: "MIPI" and "HDMI".
*
* The MIPI mode is a standard NKM-style clock. The HDMI mode is an
* integer / fractional clock with switchable multipliers and dividers.
* This is not supported here. We hardcode the PLL to MIPI mode.
*
* TODO: In the MIPI mode, M/N is required to be equal or lesser than 3,
* which cannot be implemented now.
*/
#define SUN8I_R40_PLL_MIPI_REG 0x040
static const char * const pll_mipi_parents[] = { "pll-video0" };
static struct ccu_nkm pll_mipi_clk = {
.enable = BIT(31) | BIT(23) | BIT(22),
.lock = BIT(28),
.n = _SUNXI_CCU_MULT(8, 4),
.k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
.m = _SUNXI_CCU_DIV(0, 4),
.mux = _SUNXI_CCU_MUX(21, 1),
.common = {
.reg = 0x040,
.hw.init = CLK_HW_INIT_PARENTS("pll-mipi",
pll_mipi_parents,
&ccu_nkm_ops,
CLK_SET_RATE_UNGATE)
},
};
/* TODO: The result of N/M is required to be in [8, 25] range. */
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
"osc24M", 0x048,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
/* TODO: The N factor is required to be in [16, 75] range. */
static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
"osc24M", 0x04c,
8, 7, /* N */
0, 2, /* M */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static const char * const cpu_parents[] = { "osc32k", "osc24M",
"pll-cpu", "pll-cpu" };
static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0);
static const char * const ahb1_parents[] = { "osc32k", "osc24M",
"axi", "pll-periph0" };
static const struct ccu_mux_var_prediv ahb1_predivs[] = {
{ .index = 3, .shift = 6, .width = 2 },
};
static struct ccu_div ahb1_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = {
.shift = 12,
.width = 2,
.var_predivs = ahb1_predivs,
.n_var_predivs = ARRAY_SIZE(ahb1_predivs),
},
.common = {
.reg = 0x054,
.features = CCU_FEATURE_VARIABLE_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("ahb1",
ahb1_parents,
&ccu_div_ops,
0),
},
};
static struct clk_div_table apb1_div_table[] = {
{ .val = 0, .div = 2 },
{ .val = 1, .div = 2 },
{ .val = 2, .div = 4 },
{ .val = 3, .div = 8 },
{ /* Sentinel */ },
};
static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
0x054, 8, 2, apb1_div_table, 0);
static const char * const apb2_parents[] = { "osc32k", "osc24M",
"pll-periph0-2x",
"pll-periph0-2x" };
static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
0, 5, /* M */
16, 2, /* P */
24, 2, /* mux */
0);
static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
0x060, BIT(1), 0);
static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
0x060, BIT(5), 0);
static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
0x060, BIT(6), 0);
static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
0x060, BIT(8), 0);
static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
0x060, BIT(9), 0);
static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
0x060, BIT(10), 0);
static SUNXI_CCU_GATE(bus_mmc3_clk, "bus-mmc3", "ahb1",
0x060, BIT(11), 0);
static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
0x060, BIT(13), 0);
static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
0x060, BIT(14), 0);
static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb1",
0x060, BIT(17), 0);
static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
0x060, BIT(18), 0);
static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
0x060, BIT(19), 0);
static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
0x060, BIT(20), 0);
static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
0x060, BIT(21), 0);
static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb1",
0x060, BIT(22), 0);
static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb1",
0x060, BIT(23), 0);
static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb1",
0x060, BIT(24), 0);
static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
0x060, BIT(25), 0);
static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
0x060, BIT(26), 0);
static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb1",
0x060, BIT(27), 0);
static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb1",
0x060, BIT(28), 0);
static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
0x060, BIT(29), 0);
static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb1",
0x060, BIT(30), 0);
static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb1",
0x060, BIT(31), 0);
static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
0x064, BIT(0), 0);
static SUNXI_CCU_GATE(bus_mp_clk, "bus-mp", "ahb1",
0x064, BIT(2), 0);
static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
0x064, BIT(5), 0);
static SUNXI_CCU_GATE(bus_csi0_clk, "bus-csi0", "ahb1",
0x064, BIT(8), 0);
static SUNXI_CCU_GATE(bus_csi1_clk, "bus-csi1", "ahb1",
0x064, BIT(9), 0);
static SUNXI_CCU_GATE(bus_hdmi0_clk, "bus-hdmi0", "ahb1",
0x064, BIT(10), 0);
static SUNXI_CCU_GATE(bus_hdmi1_clk, "bus-hdmi1", "ahb1",
0x064, BIT(11), 0);
static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
0x064, BIT(12), 0);
static SUNXI_CCU_GATE(bus_tve0_clk, "bus-tve0", "ahb1",
0x064, BIT(13), 0);
static SUNXI_CCU_GATE(bus_tve1_clk, "bus-tve1", "ahb1",
0x064, BIT(14), 0);
static SUNXI_CCU_GATE(bus_tve_top_clk, "bus-tve-top", "ahb1",
0x064, BIT(15), 0);
static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1",
0x064, BIT(17), 0);
static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
0x064, BIT(20), 0);
static SUNXI_CCU_GATE(bus_tvd0_clk, "bus-tvd0", "ahb1",
0x064, BIT(21), 0);
static SUNXI_CCU_GATE(bus_tvd1_clk, "bus-tvd1", "ahb1",
0x064, BIT(22), 0);
static SUNXI_CCU_GATE(bus_tvd2_clk, "bus-tvd2", "ahb1",
0x064, BIT(23), 0);
static SUNXI_CCU_GATE(bus_tvd3_clk, "bus-tvd3", "ahb1",
0x064, BIT(24), 0);
static SUNXI_CCU_GATE(bus_tvd_top_clk, "bus-tvd-top", "ahb1",
0x064, BIT(25), 0);
static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb1",
0x064, BIT(26), 0);
static SUNXI_CCU_GATE(bus_tcon_lcd1_clk, "bus-tcon-lcd1", "ahb1",
0x064, BIT(27), 0);
static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb1",
0x064, BIT(28), 0);
static SUNXI_CCU_GATE(bus_tcon_tv1_clk, "bus-tcon-tv1", "ahb1",
0x064, BIT(29), 0);
static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb1",
0x064, BIT(30), 0);
static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
0x068, BIT(0), 0);
static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
0x068, BIT(1), 0);
static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb1",
0x068, BIT(2), 0);
static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
0x068, BIT(5), 0);
static SUNXI_CCU_GATE(bus_ir0_clk, "bus-ir0", "apb1",
0x068, BIT(6), 0);
static SUNXI_CCU_GATE(bus_ir1_clk, "bus-ir1", "apb1",
0x068, BIT(7), 0);
static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
0x068, BIT(8), 0);
static SUNXI_CCU_GATE(bus_keypad_clk, "bus-keypad", "apb1",
0x068, BIT(10), 0);
static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
0x068, BIT(12), 0);
static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
0x068, BIT(13), 0);
static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
0x068, BIT(14), 0);
static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
0x06c, BIT(0), 0);
static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
0x06c, BIT(1), 0);
static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
0x06c, BIT(2), 0);
static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2",
0x06c, BIT(3), 0);
/*
* In datasheet here's "Reserved", however the gate exists in BSP soucre
* code.
*/
static SUNXI_CCU_GATE(bus_can_clk, "bus-can", "apb2",
0x06c, BIT(4), 0);
static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
0x06c, BIT(5), 0);
static SUNXI_CCU_GATE(bus_ps20_clk, "bus-ps20", "apb2",
0x06c, BIT(6), 0);
static SUNXI_CCU_GATE(bus_ps21_clk, "bus-ps21", "apb2",
0x06c, BIT(7), 0);
static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb2",
0x06c, BIT(15), 0);
static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
0x06c, BIT(16), 0);
static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
0x06c, BIT(17), 0);
static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
0x06c, BIT(18), 0);
static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
0x06c, BIT(19), 0);
static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
0x06c, BIT(20), 0);
static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb2",
0x06c, BIT(21), 0);
static SUNXI_CCU_GATE(bus_uart6_clk, "bus-uart6", "apb2",
0x06c, BIT(22), 0);
static SUNXI_CCU_GATE(bus_uart7_clk, "bus-uart7", "apb2",
0x06c, BIT(23), 0);
static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
0x070, BIT(7), 0);
static const char * const ths_parents[] = { "osc24M" };
static struct ccu_div ths_clk = {
.enable = BIT(31),
.div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
.mux = _SUNXI_CCU_MUX(24, 2),
.common = {
.reg = 0x074,
.hw.init = CLK_HW_INIT_PARENTS("ths",
ths_parents,
&ccu_div_ops,
0),
},
};
static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
"pll-periph1" };
static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
0, 4, /* M */
16, 2, /* P */
24, 4, /* mux */
BIT(31), /* gate */
0);
static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x",
"pll-periph1-2x" };
static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
"pll-audio-2x", "pll-audio" };
static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", i2s_parents,
0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_parents,
0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
static const char * const keypad_parents[] = { "osc24M", "osc32k" };
static const u8 keypad_table[] = { 0, 2 };
static struct ccu_mp keypad_clk = {
.enable = BIT(31),
.m = _SUNXI_CCU_DIV(0, 5),
.p = _SUNXI_CCU_DIV(16, 2),
.mux = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
.common = {
.reg = 0x0c4,
.hw.init = CLK_HW_INIT_PARENTS("keypad",
keypad_parents,
&ccu_mp_ops,
0),
}
};
static const char * const sata_parents[] = { "pll-sata-out", "sata-ext" };
static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents,
0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
/*
* There are 3 OHCI 12M clock source selection bits in this register.
* We will force them to 0 (12M divided from 48M).
*/
#define SUN8I_R40_USB_CLK_REG 0x0cc
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
0x0cc, BIT(8), 0);
static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
0x0cc, BIT(9), 0);
static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
0x0cc, BIT(10), 0);
static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M",
0x0cc, BIT(16), 0);
static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M",
0x0cc, BIT(17), 0);
static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc12M",
0x0cc, BIT(18), 0);
static const char * const ir_parents[] = { "osc24M", "pll-periph0",
"pll-periph1", "osc32k" };
static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_clk, "ir0", ir_parents, 0x0d0,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_clk, "ir1", ir_parents, 0x0d4,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
0);
static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
0x0f4, 0, 2, 20, 2, CLK_IS_CRITICAL);
static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
0x100, BIT(0), 0);
static SUNXI_CCU_GATE(dram_csi0_clk, "dram-csi0", "dram",
0x100, BIT(1), 0);
static SUNXI_CCU_GATE(dram_csi1_clk, "dram-csi1", "dram",
0x100, BIT(2), 0);
static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
0x100, BIT(3), 0);
static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "dram",
0x100, BIT(4), 0);
static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "dram",
0x100, BIT(5), 0);
static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
0x100, BIT(6), 0);
static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
0x104, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", de_parents,
0x108, 0, 4, 24, 3, BIT(31), 0);
static const char * const tcon_parents[] = { "pll-video0", "pll-video1",
"pll-video0-2x", "pll-video1-2x",
"pll-mipi" };
static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents,
0x110, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,
0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents,
0x118, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents,
0x11c, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
static const char * const deinterlace_parents[] = { "pll-periph0",
"pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace",
deinterlace_parents, 0x124, 0, 4, 24, 3,
BIT(31), 0);
static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1",
"pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk", csi_mclk_parents,
0x130, 0, 5, 8, 3, BIT(15), 0);
static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
0x134, 16, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents,
0x134, 0, 5, 8, 3, BIT(15), 0);
static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
0x140, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
0x144, BIT(31), 0);
static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
0x150, 0, 4, 24, 2, BIT(31),
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M",
0x154, BIT(31), 0);
/*
* In the SoC's user manual, the P factor is mentioned, but not used in
* the frequency formula.
*
* Here the factor is included, according to the BSP kernel source,
* which contains the P factor of this clock.
*/
static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
"pll-ddr0" };
static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x15c,
0, 4, /* M */
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
CLK_IS_CRITICAL);
static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-video1",
"pll-periph0" };
static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents,
0x168, 0, 4, 8, 2, BIT(15), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(tve0_clk, "tve0", tcon_parents,
0x180, 0, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(tve1_clk, "tve1", tcon_parents,
0x184, 0, 4, 24, 3, BIT(31), 0);
static const char * const tvd_parents[] = { "pll-video0", "pll-video1",
"pll-video0-2x", "pll-video1-2x" };
static SUNXI_CCU_M_WITH_MUX_GATE(tvd0_clk, "tvd0", tvd_parents,
0x188, 0, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(tvd1_clk, "tvd1", tvd_parents,
0x18c, 0, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(tvd2_clk, "tvd2", tvd_parents,
0x190, 0, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_M_WITH_MUX_GATE(tvd3_clk, "tvd3", tvd_parents,
0x194, 0, 4, 24, 3, BIT(31), 0);
static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
static const char * const out_parents[] = { "osc24M", "osc32k", "osc24M" };
static const struct ccu_mux_fixed_prediv out_predivs[] = {
{ .index = 0, .div = 750, },
};
static struct ccu_mp outa_clk = {
.enable = BIT(31),
.m = _SUNXI_CCU_DIV(8, 5),
.p = _SUNXI_CCU_DIV(20, 2),
.mux = {
.shift = 24,
.width = 2,
.fixed_predivs = out_predivs,
.n_predivs = ARRAY_SIZE(out_predivs),
},
.common = {
.reg = 0x1f0,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("outa", out_parents,
&ccu_mp_ops,
CLK_SET_RATE_PARENT),
}
};
static struct ccu_mp outb_clk = {
.enable = BIT(31),
.m = _SUNXI_CCU_DIV(8, 5),
.p = _SUNXI_CCU_DIV(20, 2),
.mux = {
.shift = 24,
.width = 2,
.fixed_predivs = out_predivs,
.n_predivs = ARRAY_SIZE(out_predivs),
},
.common = {
.reg = 0x1f4,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("outb", out_parents,
&ccu_mp_ops,
CLK_SET_RATE_PARENT),
}
};
static struct ccu_common *sun8i_r40_ccu_clks[] = {
&pll_cpu_clk.common,
&pll_audio_base_clk.common,
&pll_video0_clk.common,
&pll_ve_clk.common,
&pll_ddr0_clk.common,
&pll_periph0_clk.common,
&pll_periph0_sata_clk.common,
&pll_periph1_clk.common,
&pll_video1_clk.common,
&pll_sata_clk.common,
&pll_sata_out_clk.common,
&pll_gpu_clk.common,
&pll_mipi_clk.common,
&pll_de_clk.common,
&pll_ddr1_clk.common,
&cpu_clk.common,
&axi_clk.common,
&ahb1_clk.common,
&apb1_clk.common,
&apb2_clk.common,
&bus_mipi_dsi_clk.common,
&bus_ce_clk.common,
&bus_dma_clk.common,
&bus_mmc0_clk.common,
&bus_mmc1_clk.common,
&bus_mmc2_clk.common,
&bus_mmc3_clk.common,
&bus_nand_clk.common,
&bus_dram_clk.common,
&bus_emac_clk.common,
&bus_ts_clk.common,
&bus_hstimer_clk.common,
&bus_spi0_clk.common,
&bus_spi1_clk.common,
&bus_spi2_clk.common,
&bus_spi3_clk.common,
&bus_sata_clk.common,
&bus_otg_clk.common,
&bus_ehci0_clk.common,
&bus_ehci1_clk.common,
&bus_ehci2_clk.common,
&bus_ohci0_clk.common,
&bus_ohci1_clk.common,
&bus_ohci2_clk.common,
&bus_ve_clk.common,
&bus_mp_clk.common,
&bus_deinterlace_clk.common,
&bus_csi0_clk.common,
&bus_csi1_clk.common,
&bus_hdmi0_clk.common,
&bus_hdmi1_clk.common,
&bus_de_clk.common,
&bus_tve0_clk.common,
&bus_tve1_clk.common,
&bus_tve_top_clk.common,
&bus_gmac_clk.common,
&bus_gpu_clk.common,
&bus_tvd0_clk.common,
&bus_tvd1_clk.common,
&bus_tvd2_clk.common,
&bus_tvd3_clk.common,
&bus_tvd_top_clk.common,
&bus_tcon_lcd0_clk.common,
&bus_tcon_lcd1_clk.common,
&bus_tcon_tv0_clk.common,
&bus_tcon_tv1_clk.common,
&bus_tcon_top_clk.common,
&bus_codec_clk.common,
&bus_spdif_clk.common,
&bus_ac97_clk.common,
&bus_pio_clk.common,
&bus_ir0_clk.common,
&bus_ir1_clk.common,
&bus_ths_clk.common,
&bus_keypad_clk.common,
&bus_i2s0_clk.common,
&bus_i2s1_clk.common,
&bus_i2s2_clk.common,
&bus_i2c0_clk.common,
&bus_i2c1_clk.common,
&bus_i2c2_clk.common,
&bus_i2c3_clk.common,
&bus_can_clk.common,
&bus_scr_clk.common,
&bus_ps20_clk.common,
&bus_ps21_clk.common,
&bus_i2c4_clk.common,
&bus_uart0_clk.common,
&bus_uart1_clk.common,
&bus_uart2_clk.common,
&bus_uart3_clk.common,
&bus_uart4_clk.common,
&bus_uart5_clk.common,
&bus_uart6_clk.common,
&bus_uart7_clk.common,
&bus_dbg_clk.common,
&ths_clk.common,
&nand_clk.common,
&mmc0_clk.common,
&mmc1_clk.common,
&mmc2_clk.common,
&mmc3_clk.common,
&ts_clk.common,
&ce_clk.common,
&spi0_clk.common,
&spi1_clk.common,
&spi2_clk.common,
&spi3_clk.common,
&i2s0_clk.common,
&i2s1_clk.common,
&i2s2_clk.common,
&ac97_clk.common,
&spdif_clk.common,
&keypad_clk.common,
&sata_clk.common,
&usb_phy0_clk.common,
&usb_phy1_clk.common,
&usb_phy2_clk.common,
&usb_ohci0_clk.common,
&usb_ohci1_clk.common,
&usb_ohci2_clk.common,
&ir0_clk.common,
&ir1_clk.common,
&dram_clk.common,
&dram_ve_clk.common,
&dram_csi0_clk.common,
&dram_csi1_clk.common,
&dram_ts_clk.common,
&dram_tvd_clk.common,
&dram_mp_clk.common,
&dram_deinterlace_clk.common,
&de_clk.common,
&mp_clk.common,
&tcon_lcd0_clk.common,
&tcon_lcd1_clk.common,
&tcon_tv0_clk.common,
&tcon_tv1_clk.common,
&deinterlace_clk.common,
&csi1_mclk_clk.common,
&csi_sclk_clk.common,
&csi0_mclk_clk.common,
&ve_clk.common,
&codec_clk.common,
&avs_clk.common,
&hdmi_clk.common,
&hdmi_slow_clk.common,
&mbus_clk.common,
&dsi_dphy_clk.common,
&tve0_clk.common,
&tve1_clk.common,
&tvd0_clk.common,
&tvd1_clk.common,
&tvd2_clk.common,
&tvd3_clk.common,
&gpu_clk.common,
&outa_clk.common,
&outb_clk.common,
};
/* Fixed Factor clocks */
static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
static const struct clk_hw *clk_parent_pll_audio[] = {
&pll_audio_base_clk.common.hw
};
/* We hardcode the divider to 1 for now */
static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
clk_parent_pll_audio,
1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
clk_parent_pll_audio,
2, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
clk_parent_pll_audio,
1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
clk_parent_pll_audio,
1, 2, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
&pll_periph0_clk.common.hw,
1, 2, 0);
static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
&pll_periph1_clk.common.hw,
1, 2, 0);
static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
&pll_video0_clk.common.hw,
1, 2, 0);
static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
&pll_video1_clk.common.hw,
1, 2, 0);
static struct clk_hw_onecell_data sun8i_r40_hw_clks = {
.hws = {
[CLK_OSC_12M] = &osc12M_clk.hw,
[CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
[CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
[CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
[CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
[CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
[CLK_PLL_PERIPH0_SATA] = &pll_periph0_sata_clk.common.hw,
[CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
[CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
[CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
[CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
[CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
[CLK_PLL_SATA] = &pll_sata_clk.common.hw,
[CLK_PLL_SATA_OUT] = &pll_sata_out_clk.common.hw,
[CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
[CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
[CLK_PLL_DE] = &pll_de_clk.common.hw,
[CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
[CLK_CPU] = &cpu_clk.common.hw,
[CLK_AXI] = &axi_clk.common.hw,
[CLK_AHB1] = &ahb1_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_APB2] = &apb2_clk.common.hw,
[CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
[CLK_BUS_CE] = &bus_ce_clk.common.hw,
[CLK_BUS_DMA] = &bus_dma_clk.common.hw,
[CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
[CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
[CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
[CLK_BUS_MMC3] = &bus_mmc3_clk.common.hw,
[CLK_BUS_NAND] = &bus_nand_clk.common.hw,
[CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
[CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
[CLK_BUS_TS] = &bus_ts_clk.common.hw,
[CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
[CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
[CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
[CLK_BUS_SPI2] = &bus_spi2_clk.common.hw,
[CLK_BUS_SPI3] = &bus_spi3_clk.common.hw,
[CLK_BUS_SATA] = &bus_sata_clk.common.hw,
[CLK_BUS_OTG] = &bus_otg_clk.common.hw,
[CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
[CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
[CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw,
[CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
[CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
[CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw,
[CLK_BUS_VE] = &bus_ve_clk.common.hw,
[CLK_BUS_MP] = &bus_mp_clk.common.hw,
[CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
[CLK_BUS_CSI0] = &bus_csi0_clk.common.hw,
[CLK_BUS_CSI1] = &bus_csi1_clk.common.hw,
[CLK_BUS_HDMI0] = &bus_hdmi0_clk.common.hw,
[CLK_BUS_HDMI1] = &bus_hdmi1_clk.common.hw,
[CLK_BUS_DE] = &bus_de_clk.common.hw,
[CLK_BUS_TVE0] = &bus_tve0_clk.common.hw,
[CLK_BUS_TVE1] = &bus_tve1_clk.common.hw,
[CLK_BUS_TVE_TOP] = &bus_tve_top_clk.common.hw,
[CLK_BUS_GMAC] = &bus_gmac_clk.common.hw,
[CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
[CLK_BUS_TVD0] = &bus_tvd0_clk.common.hw,
[CLK_BUS_TVD1] = &bus_tvd1_clk.common.hw,
[CLK_BUS_TVD2] = &bus_tvd2_clk.common.hw,
[CLK_BUS_TVD3] = &bus_tvd3_clk.common.hw,
[CLK_BUS_TVD_TOP] = &bus_tvd_top_clk.common.hw,
[CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw,
[CLK_BUS_TCON_LCD1] = &bus_tcon_lcd1_clk.common.hw,
[CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw,
[CLK_BUS_TCON_TV1] = &bus_tcon_tv1_clk.common.hw,
[CLK_BUS_TCON_TOP] = &bus_tcon_top_clk.common.hw,
[CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
[CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
[CLK_BUS_AC97] = &bus_ac97_clk.common.hw,
[CLK_BUS_PIO] = &bus_pio_clk.common.hw,
[CLK_BUS_IR0] = &bus_ir0_clk.common.hw,
[CLK_BUS_IR1] = &bus_ir1_clk.common.hw,
[CLK_BUS_THS] = &bus_ths_clk.common.hw,
[CLK_BUS_KEYPAD] = &bus_keypad_clk.common.hw,
[CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
[CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
[CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
[CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
[CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
[CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
[CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
[CLK_BUS_CAN] = &bus_can_clk.common.hw,
[CLK_BUS_SCR] = &bus_scr_clk.common.hw,
[CLK_BUS_PS20] = &bus_ps20_clk.common.hw,
[CLK_BUS_PS21] = &bus_ps21_clk.common.hw,
[CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw,
[CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
[CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
[CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
[CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
[CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
[CLK_BUS_UART5] = &bus_uart5_clk.common.hw,
[CLK_BUS_UART6] = &bus_uart6_clk.common.hw,
[CLK_BUS_UART7] = &bus_uart7_clk.common.hw,
[CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
[CLK_THS] = &ths_clk.common.hw,
[CLK_NAND] = &nand_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_MMC3] = &mmc3_clk.common.hw,
[CLK_TS] = &ts_clk.common.hw,
[CLK_CE] = &ce_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI2] = &spi2_clk.common.hw,
[CLK_SPI3] = &spi3_clk.common.hw,
[CLK_I2S0] = &i2s0_clk.common.hw,
[CLK_I2S1] = &i2s1_clk.common.hw,
[CLK_I2S2] = &i2s2_clk.common.hw,
[CLK_AC97] = &ac97_clk.common.hw,
[CLK_SPDIF] = &spdif_clk.common.hw,
[CLK_KEYPAD] = &keypad_clk.common.hw,
[CLK_SATA] = &sata_clk.common.hw,
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
[CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
[CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
[CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
[CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
[CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
[CLK_IR0] = &ir0_clk.common.hw,
[CLK_IR1] = &ir1_clk.common.hw,
[CLK_DRAM] = &dram_clk.common.hw,
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
[CLK_DRAM_CSI0] = &dram_csi0_clk.common.hw,
[CLK_DRAM_CSI1] = &dram_csi1_clk.common.hw,
[CLK_DRAM_TS] = &dram_ts_clk.common.hw,
[CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
[CLK_DRAM_MP] = &dram_mp_clk.common.hw,
[CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
[CLK_DE] = &de_clk.common.hw,
[CLK_MP] = &mp_clk.common.hw,
[CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw,
[CLK_TCON_LCD1] = &tcon_lcd1_clk.common.hw,
[CLK_TCON_TV0] = &tcon_tv0_clk.common.hw,
[CLK_TCON_TV1] = &tcon_tv1_clk.common.hw,
[CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
[CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
[CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
[CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_CODEC] = &codec_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_HDMI] = &hdmi_clk.common.hw,
[CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw,
[CLK_MBUS] = &mbus_clk.common.hw,
[CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
[CLK_TVE0] = &tve0_clk.common.hw,
[CLK_TVE1] = &tve1_clk.common.hw,
[CLK_TVD0] = &tvd0_clk.common.hw,
[CLK_TVD1] = &tvd1_clk.common.hw,
[CLK_TVD2] = &tvd2_clk.common.hw,
[CLK_TVD3] = &tvd3_clk.common.hw,
[CLK_GPU] = &gpu_clk.common.hw,
[CLK_OUTA] = &outa_clk.common.hw,
[CLK_OUTB] = &outb_clk.common.hw,
},
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun8i_r40_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_PHY2] = { 0x0cc, BIT(2) },
[RST_DRAM] = { 0x0f4, BIT(31) },
[RST_MBUS] = { 0x0fc, BIT(31) },
[RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
[RST_BUS_CE] = { 0x2c0, BIT(5) },
[RST_BUS_DMA] = { 0x2c0, BIT(6) },
[RST_BUS_MMC0] = { 0x2c0, BIT(8) },
[RST_BUS_MMC1] = { 0x2c0, BIT(9) },
[RST_BUS_MMC2] = { 0x2c0, BIT(10) },
[RST_BUS_MMC3] = { 0x2c0, BIT(11) },
[RST_BUS_NAND] = { 0x2c0, BIT(13) },
[RST_BUS_DRAM] = { 0x2c0, BIT(14) },
[RST_BUS_EMAC] = { 0x2c0, BIT(17) },
[RST_BUS_TS] = { 0x2c0, BIT(18) },
[RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
[RST_BUS_SPI0] = { 0x2c0, BIT(20) },
[RST_BUS_SPI1] = { 0x2c0, BIT(21) },
[RST_BUS_SPI2] = { 0x2c0, BIT(22) },
[RST_BUS_SPI3] = { 0x2c0, BIT(23) },
[RST_BUS_SATA] = { 0x2c0, BIT(24) },
[RST_BUS_OTG] = { 0x2c0, BIT(25) },
[RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
[RST_BUS_EHCI1] = { 0x2c0, BIT(27) },
[RST_BUS_EHCI2] = { 0x2c0, BIT(28) },
[RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
[RST_BUS_OHCI1] = { 0x2c0, BIT(30) },
[RST_BUS_OHCI2] = { 0x2c0, BIT(31) },
[RST_BUS_VE] = { 0x2c4, BIT(0) },
[RST_BUS_MP] = { 0x2c4, BIT(2) },
[RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
[RST_BUS_CSI0] = { 0x2c4, BIT(8) },
[RST_BUS_CSI1] = { 0x2c4, BIT(9) },
[RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
[RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
[RST_BUS_DE] = { 0x2c4, BIT(12) },
[RST_BUS_TVE0] = { 0x2c4, BIT(13) },
[RST_BUS_TVE1] = { 0x2c4, BIT(14) },
[RST_BUS_TVE_TOP] = { 0x2c4, BIT(15) },
[RST_BUS_GMAC] = { 0x2c4, BIT(17) },
[RST_BUS_GPU] = { 0x2c4, BIT(20) },
[RST_BUS_TVD0] = { 0x2c4, BIT(21) },
[RST_BUS_TVD1] = { 0x2c4, BIT(22) },
[RST_BUS_TVD2] = { 0x2c4, BIT(23) },
[RST_BUS_TVD3] = { 0x2c4, BIT(24) },
[RST_BUS_TVD_TOP] = { 0x2c4, BIT(25) },
[RST_BUS_TCON_LCD0] = { 0x2c4, BIT(26) },
[RST_BUS_TCON_LCD1] = { 0x2c4, BIT(27) },
[RST_BUS_TCON_TV0] = { 0x2c4, BIT(28) },
[RST_BUS_TCON_TV1] = { 0x2c4, BIT(29) },
[RST_BUS_TCON_TOP] = { 0x2c4, BIT(30) },
[RST_BUS_DBG] = { 0x2c4, BIT(31) },
[RST_BUS_LVDS] = { 0x2c8, BIT(0) },
[RST_BUS_CODEC] = { 0x2d0, BIT(0) },
[RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
[RST_BUS_AC97] = { 0x2d0, BIT(2) },
[RST_BUS_IR0] = { 0x2d0, BIT(6) },
[RST_BUS_IR1] = { 0x2d0, BIT(7) },
[RST_BUS_THS] = { 0x2d0, BIT(8) },
[RST_BUS_KEYPAD] = { 0x2d0, BIT(10) },
[RST_BUS_I2S0] = { 0x2d0, BIT(12) },
[RST_BUS_I2S1] = { 0x2d0, BIT(13) },
[RST_BUS_I2S2] = { 0x2d0, BIT(14) },
[RST_BUS_I2C0] = { 0x2d8, BIT(0) },
[RST_BUS_I2C1] = { 0x2d8, BIT(1) },
[RST_BUS_I2C2] = { 0x2d8, BIT(2) },
[RST_BUS_I2C3] = { 0x2d8, BIT(3) },
[RST_BUS_CAN] = { 0x2d8, BIT(4) },
[RST_BUS_SCR] = { 0x2d8, BIT(5) },
[RST_BUS_PS20] = { 0x2d8, BIT(6) },
[RST_BUS_PS21] = { 0x2d8, BIT(7) },
[RST_BUS_I2C4] = { 0x2d8, BIT(15) },
[RST_BUS_UART0] = { 0x2d8, BIT(16) },
[RST_BUS_UART1] = { 0x2d8, BIT(17) },
[RST_BUS_UART2] = { 0x2d8, BIT(18) },
[RST_BUS_UART3] = { 0x2d8, BIT(19) },
[RST_BUS_UART4] = { 0x2d8, BIT(20) },
[RST_BUS_UART5] = { 0x2d8, BIT(21) },
[RST_BUS_UART6] = { 0x2d8, BIT(22) },
[RST_BUS_UART7] = { 0x2d8, BIT(23) },
};
static const struct sunxi_ccu_desc sun8i_r40_ccu_desc = {
.ccu_clks = sun8i_r40_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun8i_r40_ccu_clks),
.hw_clks = &sun8i_r40_hw_clks,
.resets = sun8i_r40_ccu_resets,
.num_resets = ARRAY_SIZE(sun8i_r40_ccu_resets),
};
static struct ccu_pll_nb sun8i_r40_pll_cpu_nb = {
.common = &pll_cpu_clk.common,
/* copy from pll_cpu_clk */
.enable = BIT(31),
.lock = BIT(28),
};
static struct ccu_mux_nb sun8i_r40_cpu_nb = {
.common = &cpu_clk.common,
.cm = &cpu_clk.mux,
.delay_us = 1, /* > 8 clock cycles at 24 MHz */
.bypass_index = 1, /* index of 24 MHz oscillator */
};
/*
* Add a regmap for the GMAC driver (dwmac-sun8i) to access the
* GMAC configuration register.
* Only this register is allowed to be written, in order to
* prevent overriding critical clock configuration.
*/
#define SUN8I_R40_GMAC_CFG_REG 0x164
static bool sun8i_r40_ccu_regmap_accessible_reg(struct device *dev,
unsigned int reg)
{
if (reg == SUN8I_R40_GMAC_CFG_REG)
return true;
return false;
}
static struct regmap_config sun8i_r40_ccu_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = 0x320, /* PLL_LOCK_CTRL_REG */
/* other devices have no business accessing other registers */
.readable_reg = sun8i_r40_ccu_regmap_accessible_reg,
.writeable_reg = sun8i_r40_ccu_regmap_accessible_reg,
};
#define SUN8I_R40_SYS_32K_CLK_REG 0x310
#define SUN8I_R40_SYS_32K_CLK_KEY (0x16AA << 16)
static int sun8i_r40_ccu_probe(struct platform_device *pdev)
{
struct regmap *regmap;
void __iomem *reg;
u32 val;
int ret;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
/* Force the PLL-Audio-1x divider to 1 */
val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
val &= ~GENMASK(19, 16);
writel(val | (0 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
/* Force PLL-MIPI to MIPI mode */
val = readl(reg + SUN8I_R40_PLL_MIPI_REG);
val &= ~BIT(16);
writel(val, reg + SUN8I_R40_PLL_MIPI_REG);
/* Force OHCI 12M parent to 12M divided from 48M */
val = readl(reg + SUN8I_R40_USB_CLK_REG);
val &= ~GENMASK(25, 20);
writel(val, reg + SUN8I_R40_USB_CLK_REG);
/*
* Force SYS 32k (otherwise known as LOSC throughout the CCU)
* clock parent to LOSC output from RTC module instead of the
* CCU's internal RC oscillator divided output.
*/
writel(SUN8I_R40_SYS_32K_CLK_KEY | BIT(8),
reg + SUN8I_R40_SYS_32K_CLK_REG);
regmap = devm_regmap_init_mmio(&pdev->dev, reg,
&sun8i_r40_ccu_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_r40_ccu_desc);
if (ret)
return ret;
/* Gate then ungate PLL CPU after any rate changes */
ccu_pll_notifier_register(&sun8i_r40_pll_cpu_nb);
/* Reparent CPU during PLL CPU rate changes */
ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
&sun8i_r40_cpu_nb);
return 0;
}
static const struct of_device_id sun8i_r40_ccu_ids[] = {
{ .compatible = "allwinner,sun8i-r40-ccu" },
{ }
};
static struct platform_driver sun8i_r40_ccu_driver = {
.probe = sun8i_r40_ccu_probe,
.driver = {
.name = "sun8i-r40-ccu",
.suppress_bind_attrs = true,
.of_match_table = sun8i_r40_ccu_ids,
},
};
module_platform_driver(sun8i_r40_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun8i-r40.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "ccu_common.h"
#include "ccu_gate.h"
#include "ccu_reset.h"
#include "ccu-sun9i-a80-usb.h"
static const struct clk_parent_data clk_parent_hosc[] = {
{ .fw_name = "hosc" },
};
static const struct clk_parent_data clk_parent_bus[] = {
{ .fw_name = "bus" },
};
static SUNXI_CCU_GATE_DATA(bus_hci0_clk, "bus-hci0", clk_parent_bus, 0x0, BIT(1), 0);
static SUNXI_CCU_GATE_DATA(usb_ohci0_clk, "usb-ohci0", clk_parent_hosc, 0x0, BIT(2), 0);
static SUNXI_CCU_GATE_DATA(bus_hci1_clk, "bus-hci1", clk_parent_bus, 0x0, BIT(3), 0);
static SUNXI_CCU_GATE_DATA(bus_hci2_clk, "bus-hci2", clk_parent_bus, 0x0, BIT(5), 0);
static SUNXI_CCU_GATE_DATA(usb_ohci2_clk, "usb-ohci2", clk_parent_hosc, 0x0, BIT(6), 0);
static SUNXI_CCU_GATE_DATA(usb0_phy_clk, "usb0-phy", clk_parent_hosc, 0x4, BIT(1), 0);
static SUNXI_CCU_GATE_DATA(usb1_hsic_clk, "usb1-hsic", clk_parent_hosc, 0x4, BIT(2), 0);
static SUNXI_CCU_GATE_DATA(usb1_phy_clk, "usb1-phy", clk_parent_hosc, 0x4, BIT(3), 0);
static SUNXI_CCU_GATE_DATA(usb2_hsic_clk, "usb2-hsic", clk_parent_hosc, 0x4, BIT(4), 0);
static SUNXI_CCU_GATE_DATA(usb2_phy_clk, "usb2-phy", clk_parent_hosc, 0x4, BIT(5), 0);
static SUNXI_CCU_GATE_DATA(usb_hsic_clk, "usb-hsic", clk_parent_hosc, 0x4, BIT(10), 0);
static struct ccu_common *sun9i_a80_usb_clks[] = {
&bus_hci0_clk.common,
&usb_ohci0_clk.common,
&bus_hci1_clk.common,
&bus_hci2_clk.common,
&usb_ohci2_clk.common,
&usb0_phy_clk.common,
&usb1_hsic_clk.common,
&usb1_phy_clk.common,
&usb2_hsic_clk.common,
&usb2_phy_clk.common,
&usb_hsic_clk.common,
};
static struct clk_hw_onecell_data sun9i_a80_usb_hw_clks = {
.hws = {
[CLK_BUS_HCI0] = &bus_hci0_clk.common.hw,
[CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
[CLK_BUS_HCI1] = &bus_hci1_clk.common.hw,
[CLK_BUS_HCI2] = &bus_hci2_clk.common.hw,
[CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
[CLK_USB0_PHY] = &usb0_phy_clk.common.hw,
[CLK_USB1_HSIC] = &usb1_hsic_clk.common.hw,
[CLK_USB1_PHY] = &usb1_phy_clk.common.hw,
[CLK_USB2_HSIC] = &usb2_hsic_clk.common.hw,
[CLK_USB2_PHY] = &usb2_phy_clk.common.hw,
[CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
},
.num = CLK_NUMBER,
};
static struct ccu_reset_map sun9i_a80_usb_resets[] = {
[RST_USB0_HCI] = { 0x0, BIT(17) },
[RST_USB1_HCI] = { 0x0, BIT(18) },
[RST_USB2_HCI] = { 0x0, BIT(19) },
[RST_USB0_PHY] = { 0x4, BIT(17) },
[RST_USB1_HSIC] = { 0x4, BIT(18) },
[RST_USB1_PHY] = { 0x4, BIT(19) },
[RST_USB2_HSIC] = { 0x4, BIT(20) },
[RST_USB2_PHY] = { 0x4, BIT(21) },
};
static const struct sunxi_ccu_desc sun9i_a80_usb_clk_desc = {
.ccu_clks = sun9i_a80_usb_clks,
.num_ccu_clks = ARRAY_SIZE(sun9i_a80_usb_clks),
.hw_clks = &sun9i_a80_usb_hw_clks,
.resets = sun9i_a80_usb_resets,
.num_resets = ARRAY_SIZE(sun9i_a80_usb_resets),
};
static int sun9i_a80_usb_clk_probe(struct platform_device *pdev)
{
struct clk *bus_clk;
void __iomem *reg;
int ret;
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
bus_clk = devm_clk_get(&pdev->dev, "bus");
if (IS_ERR(bus_clk))
return dev_err_probe(&pdev->dev, PTR_ERR(bus_clk),
"Couldn't get bus clk\n");
/* The bus clock needs to be enabled for us to access the registers */
ret = clk_prepare_enable(bus_clk);
if (ret) {
dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret);
return ret;
}
ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun9i_a80_usb_clk_desc);
if (ret)
goto err_disable_clk;
return 0;
err_disable_clk:
clk_disable_unprepare(bus_clk);
return ret;
}
static const struct of_device_id sun9i_a80_usb_clk_ids[] = {
{ .compatible = "allwinner,sun9i-a80-usb-clks" },
{ }
};
static struct platform_driver sun9i_a80_usb_clk_driver = {
.probe = sun9i_a80_usb_clk_probe,
.driver = {
.name = "sun9i-a80-usb-clks",
.of_match_table = sun9i_a80_usb_clk_ids,
},
};
module_platform_driver(sun9i_a80_usb_clk_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022, Linaro Ltd.
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
/* Need to match the order of clocks in DT binding */
enum {
DT_BI_TCXO,
DT_SLEEP_CLK,
DT_UFS_PHY_RX_SYMBOL_0_CLK,
DT_UFS_PHY_RX_SYMBOL_1_CLK,
DT_UFS_PHY_TX_SYMBOL_0_CLK,
DT_UFS_CARD_RX_SYMBOL_0_CLK,
DT_UFS_CARD_RX_SYMBOL_1_CLK,
DT_UFS_CARD_TX_SYMBOL_0_CLK,
DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
DT_GCC_USB4_PHY_PIPEGMUX_CLK_SRC,
DT_GCC_USB4_PHY_DP_GMUX_CLK_SRC,
DT_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC,
DT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK,
DT_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
DT_QUSB4PHY_GCC_USB4_RX0_CLK,
DT_QUSB4PHY_GCC_USB4_RX1_CLK,
DT_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK,
DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,
DT_GCC_USB4_1_PHY_DP_GMUX_CLK_SRC,
DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,
DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,
DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
DT_QUSB4PHY_1_GCC_USB4_RX0_CLK,
DT_QUSB4PHY_1_GCC_USB4_RX1_CLK,
DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK,
DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK,
DT_PCIE_2A_PIPE_CLK,
DT_PCIE_2B_PIPE_CLK,
DT_PCIE_3A_PIPE_CLK,
DT_PCIE_3B_PIPE_CLK,
DT_PCIE_4_PIPE_CLK,
DT_RXC0_REF_CLK,
DT_RXC1_REF_CLK,
};
enum {
P_BI_TCXO,
P_GCC_GPLL0_OUT_EVEN,
P_GCC_GPLL0_OUT_MAIN,
P_GCC_GPLL2_OUT_MAIN,
P_GCC_GPLL4_OUT_MAIN,
P_GCC_GPLL7_OUT_MAIN,
P_GCC_GPLL8_OUT_MAIN,
P_GCC_GPLL9_OUT_MAIN,
P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC,
P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC,
P_GCC_USB4_1_PHY_DP_GMUX_CLK_SRC,
P_GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC,
P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC,
P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,
P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,
P_GCC_USB4_PHY_DP_GMUX_CLK_SRC,
P_GCC_USB4_PHY_PCIE_PIPE_CLK_SRC,
P_GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC,
P_GCC_USB4_PHY_PIPEGMUX_CLK_SRC,
P_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC,
P_QUSB4PHY_1_GCC_USB4_RX0_CLK,
P_QUSB4PHY_1_GCC_USB4_RX1_CLK,
P_QUSB4PHY_GCC_USB4_RX0_CLK,
P_QUSB4PHY_GCC_USB4_RX1_CLK,
P_RXC0_REF_CLK,
P_RXC1_REF_CLK,
P_SLEEP_CLK,
P_UFS_CARD_RX_SYMBOL_0_CLK,
P_UFS_CARD_RX_SYMBOL_1_CLK,
P_UFS_CARD_TX_SYMBOL_0_CLK,
P_UFS_PHY_RX_SYMBOL_0_CLK,
P_UFS_PHY_RX_SYMBOL_1_CLK,
P_UFS_PHY_TX_SYMBOL_0_CLK,
P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK,
P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK,
P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK,
P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,
P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
P_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK,
P_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
};
static const struct clk_parent_data gcc_parent_data_tcxo = { .index = DT_BI_TCXO };
static struct clk_alpha_pll gcc_gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x52028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll0",
.parent_data = &gcc_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
},
},
};
static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_gcc_gpll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll0_out_even",
.parent_hws = (const struct clk_hw*[]){
&gcc_gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops,
},
};
static struct clk_alpha_pll gcc_gpll2 = {
.offset = 0x2000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x52028,
.enable_mask = BIT(2),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll2",
.parent_data = &gcc_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll4 = {
.offset = 0x76000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x52028,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll4",
.parent_data = &gcc_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll7 = {
.offset = 0x1a000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x52028,
.enable_mask = BIT(7),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll7",
.parent_data = &gcc_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll8 = {
.offset = 0x1b000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x52028,
.enable_mask = BIT(8),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll8",
.parent_data = &gcc_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll9 = {
.offset = 0x1c000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x52028,
.enable_mask = BIT(9),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll9",
.parent_data = &gcc_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
},
},
};
static struct clk_rcg2 gcc_usb4_1_phy_pcie_pipe_clk_src;
static struct clk_rcg2 gcc_usb4_phy_pcie_pipe_clk_src;
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .index = DT_SLEEP_CLK },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL7_OUT_MAIN, 2 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_4[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll7.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL8_OUT_MAIN, 2 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll8.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL7_OUT_MAIN, 2 },
};
static const struct clk_parent_data gcc_parent_data_6[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll7.clkr.hw },
};
static const struct parent_map gcc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL2_OUT_MAIN, 2 },
};
static const struct clk_parent_data gcc_parent_data_7[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll2.clkr.hw },
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL7_OUT_MAIN, 2 },
{ P_RXC0_REF_CLK, 3 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_8[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll7.clkr.hw },
{ .index = DT_RXC0_REF_CLK },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_9[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL7_OUT_MAIN, 2 },
{ P_RXC1_REF_CLK, 3 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_9[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll7.clkr.hw },
{ .index = DT_RXC1_REF_CLK },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_15[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL9_OUT_MAIN, 2 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_15[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll9.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_16[] = {
{ P_UFS_CARD_RX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_16[] = {
{ .index = DT_UFS_CARD_RX_SYMBOL_0_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_17[] = {
{ P_UFS_CARD_RX_SYMBOL_1_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_17[] = {
{ .index = DT_UFS_CARD_RX_SYMBOL_1_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_18[] = {
{ P_UFS_CARD_TX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_18[] = {
{ .index = DT_UFS_CARD_TX_SYMBOL_0_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_19[] = {
{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_19[] = {
{ .index = DT_UFS_PHY_RX_SYMBOL_0_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_20[] = {
{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_20[] = {
{ .index = DT_UFS_PHY_RX_SYMBOL_1_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_21[] = {
{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_21[] = {
{ .index = DT_UFS_PHY_TX_SYMBOL_0_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_22[] = {
{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_22[] = {
{ .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_23[] = {
{ P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_23[] = {
{ .index = DT_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK },
{ .index = DT_BI_TCXO },
};
static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
.reg = 0xf060,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_22,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_prim_phy_pipe_clk_src",
.parent_data = gcc_parent_data_22,
.num_parents = ARRAY_SIZE(gcc_parent_data_22),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
.reg = 0x10060,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_23,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_sec_phy_pipe_clk_src",
.parent_data = gcc_parent_data_23,
.num_parents = ARRAY_SIZE(gcc_parent_data_23),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static const struct parent_map gcc_parent_map_24[] = {
{ P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_24[] = {
{ .index = DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_25[] = {
{ P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_25[] = {
{ .index = DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_26[] = {
{ P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 0 },
{ P_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
{ P_GCC_USB4_PHY_PIPEGMUX_CLK_SRC, 3 },
};
static const struct clk_parent_data gcc_parent_data_26[] = {
{ .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw },
{ .index = DT_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
{ .index = DT_GCC_USB4_PHY_PIPEGMUX_CLK_SRC },
};
static const struct parent_map gcc_parent_map_27[] = {
{ P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 0 },
{ P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
{ P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 3 },
};
static const struct clk_parent_data gcc_parent_data_27[] = {
{ .hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw },
{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
{ .index = DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC },
};
static const struct parent_map gcc_parent_map_28[] = {
{ P_GCC_USB4_1_PHY_DP_GMUX_CLK_SRC, 0 },
{ P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
};
static const struct clk_parent_data gcc_parent_data_28[] = {
{ .index = DT_GCC_USB4_1_PHY_DP_GMUX_CLK_SRC },
{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
};
static const struct parent_map gcc_parent_map_29[] = {
{ P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_29[] = {
{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_30[] = {
{ P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
{ P_GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC, 1 },
};
static const struct clk_parent_data gcc_parent_data_30[] = {
{ .index = DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC },
{ .hw = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr.hw },
};
static struct clk_regmap_mux gcc_usb4_1_phy_pcie_pipegmux_clk_src = {
.reg = 0xb80dc,
.shift = 0,
.width = 1,
.parent_map = gcc_parent_map_30,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_phy_pcie_pipegmux_clk_src",
.parent_data = gcc_parent_data_30,
.num_parents = ARRAY_SIZE(gcc_parent_data_30),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static const struct parent_map gcc_parent_map_31[] = {
{ P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
{ P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
};
static const struct clk_parent_data gcc_parent_data_31[] = {
{ .hw = &gcc_usb4_1_phy_pcie_pipegmux_clk_src.clkr.hw },
{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
};
static const struct parent_map gcc_parent_map_32[] = {
{ P_QUSB4PHY_1_GCC_USB4_RX0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_32[] = {
{ .index = DT_QUSB4PHY_1_GCC_USB4_RX0_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_33[] = {
{ P_QUSB4PHY_1_GCC_USB4_RX1_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_33[] = {
{ .index = DT_QUSB4PHY_1_GCC_USB4_RX1_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_34[] = {
{ P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
{ P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
};
static const struct clk_parent_data gcc_parent_data_34[] = {
{ .index = DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC },
{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
};
static const struct parent_map gcc_parent_map_35[] = {
{ P_GCC_USB4_PHY_DP_GMUX_CLK_SRC, 0 },
{ P_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
};
static const struct clk_parent_data gcc_parent_data_35[] = {
{ .index = DT_GCC_USB4_PHY_DP_GMUX_CLK_SRC },
{ .index = DT_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
};
static const struct parent_map gcc_parent_map_36[] = {
{ P_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_36[] = {
{ .index = DT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_37[] = {
{ P_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
{ P_GCC_USB4_PHY_PCIE_PIPE_CLK_SRC, 1 },
};
static const struct clk_parent_data gcc_parent_data_37[] = {
{ .index = DT_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC },
{ .hw = &gcc_usb4_phy_pcie_pipe_clk_src.clkr.hw },
};
static struct clk_regmap_mux gcc_usb4_phy_pcie_pipegmux_clk_src = {
.reg = 0x2a0dc,
.shift = 0,
.width = 1,
.parent_map = gcc_parent_map_37,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_phy_pcie_pipegmux_clk_src",
.parent_data = gcc_parent_data_37,
.num_parents = ARRAY_SIZE(gcc_parent_data_37),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static const struct parent_map gcc_parent_map_38[] = {
{ P_GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
{ P_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
};
static const struct clk_parent_data gcc_parent_data_38[] = {
{ .hw = &gcc_usb4_phy_pcie_pipegmux_clk_src.clkr.hw },
{ .index = DT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK },
};
static const struct parent_map gcc_parent_map_39[] = {
{ P_QUSB4PHY_GCC_USB4_RX0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_39[] = {
{ .index = DT_QUSB4PHY_GCC_USB4_RX0_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_40[] = {
{ P_QUSB4PHY_GCC_USB4_RX1_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_40[] = {
{ .index = DT_QUSB4PHY_GCC_USB4_RX1_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_41[] = {
{ P_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
{ P_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
};
static const struct clk_parent_data gcc_parent_data_41[] = {
{ .index = DT_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC },
{ .index = DT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK },
};
static struct clk_regmap_phy_mux gcc_pcie_2a_pipe_clk_src = {
.reg = 0x9d05c,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2a_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_2A_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_phy_mux gcc_pcie_2b_pipe_clk_src = {
.reg = 0x9e05c,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2b_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_2B_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_phy_mux gcc_pcie_3a_pipe_clk_src = {
.reg = 0xa005c,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3a_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_3A_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_phy_mux gcc_pcie_3b_pipe_clk_src = {
.reg = 0xa205c,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3b_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_3B_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_phy_mux gcc_pcie_4_pipe_clk_src = {
.reg = 0x6b05c,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_4_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_card_rx_symbol_0_clk_src = {
.reg = 0x75058,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_16,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_rx_symbol_0_clk_src",
.parent_data = gcc_parent_data_16,
.num_parents = ARRAY_SIZE(gcc_parent_data_16),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_card_rx_symbol_1_clk_src = {
.reg = 0x750c8,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_17,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_rx_symbol_1_clk_src",
.parent_data = gcc_parent_data_17,
.num_parents = ARRAY_SIZE(gcc_parent_data_17),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_card_tx_symbol_0_clk_src = {
.reg = 0x75048,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_18,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_tx_symbol_0_clk_src",
.parent_data = gcc_parent_data_18,
.num_parents = ARRAY_SIZE(gcc_parent_data_18),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
.reg = 0x77058,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_19,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
.parent_data = gcc_parent_data_19,
.num_parents = ARRAY_SIZE(gcc_parent_data_19),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
.reg = 0x770c8,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_20,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
.parent_data = gcc_parent_data_20,
.num_parents = ARRAY_SIZE(gcc_parent_data_20),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
.reg = 0x77048,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_21,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
.parent_data = gcc_parent_data_21,
.num_parents = ARRAY_SIZE(gcc_parent_data_21),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb34_prim_phy_pipe_clk_src = {
.reg = 0xf064,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_26,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb34_prim_phy_pipe_clk_src",
.parent_data = gcc_parent_data_26,
.num_parents = ARRAY_SIZE(gcc_parent_data_26),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb34_sec_phy_pipe_clk_src = {
.reg = 0x10064,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_27,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb34_sec_phy_pipe_clk_src",
.parent_data = gcc_parent_data_27,
.num_parents = ARRAY_SIZE(gcc_parent_data_27),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb3_mp_phy_pipe_0_clk_src = {
.reg = 0xab060,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_24,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_mp_phy_pipe_0_clk_src",
.parent_data = gcc_parent_data_24,
.num_parents = ARRAY_SIZE(gcc_parent_data_24),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb3_mp_phy_pipe_1_clk_src = {
.reg = 0xab068,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_25,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_mp_phy_pipe_1_clk_src",
.parent_data = gcc_parent_data_25,
.num_parents = ARRAY_SIZE(gcc_parent_data_25),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb4_1_phy_dp_clk_src = {
.reg = 0xb8050,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_28,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_phy_dp_clk_src",
.parent_data = gcc_parent_data_28,
.num_parents = ARRAY_SIZE(gcc_parent_data_28),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb4_1_phy_p2rr2p_pipe_clk_src = {
.reg = 0xb80b0,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_29,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_phy_p2rr2p_pipe_clk_src",
.parent_data = gcc_parent_data_29,
.num_parents = ARRAY_SIZE(gcc_parent_data_29),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb4_1_phy_pcie_pipe_mux_clk_src = {
.reg = 0xb80e0,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_31,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_phy_pcie_pipe_mux_clk_src",
.parent_data = gcc_parent_data_31,
.num_parents = ARRAY_SIZE(gcc_parent_data_31),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb4_1_phy_rx0_clk_src = {
.reg = 0xb8090,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_32,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_phy_rx0_clk_src",
.parent_data = gcc_parent_data_32,
.num_parents = ARRAY_SIZE(gcc_parent_data_32),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb4_1_phy_rx1_clk_src = {
.reg = 0xb809c,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_33,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_phy_rx1_clk_src",
.parent_data = gcc_parent_data_33,
.num_parents = ARRAY_SIZE(gcc_parent_data_33),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb4_1_phy_sys_clk_src = {
.reg = 0xb80c0,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_34,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_phy_sys_clk_src",
.parent_data = gcc_parent_data_34,
.num_parents = ARRAY_SIZE(gcc_parent_data_34),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb4_phy_dp_clk_src = {
.reg = 0x2a050,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_35,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_phy_dp_clk_src",
.parent_data = gcc_parent_data_35,
.num_parents = ARRAY_SIZE(gcc_parent_data_35),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb4_phy_p2rr2p_pipe_clk_src = {
.reg = 0x2a0b0,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_36,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_phy_p2rr2p_pipe_clk_src",
.parent_data = gcc_parent_data_36,
.num_parents = ARRAY_SIZE(gcc_parent_data_36),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb4_phy_pcie_pipe_mux_clk_src = {
.reg = 0x2a0e0,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_38,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_phy_pcie_pipe_mux_clk_src",
.parent_data = gcc_parent_data_38,
.num_parents = ARRAY_SIZE(gcc_parent_data_38),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb4_phy_rx0_clk_src = {
.reg = 0x2a090,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_39,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_phy_rx0_clk_src",
.parent_data = gcc_parent_data_39,
.num_parents = ARRAY_SIZE(gcc_parent_data_39),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb4_phy_rx1_clk_src = {
.reg = 0x2a09c,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_40,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_phy_rx1_clk_src",
.parent_data = gcc_parent_data_40,
.num_parents = ARRAY_SIZE(gcc_parent_data_40),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb4_phy_sys_clk_src = {
.reg = 0x2a0c0,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_41,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_phy_sys_clk_src",
.parent_data = gcc_parent_data_41,
.num_parents = ARRAY_SIZE(gcc_parent_data_41),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] = {
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
F(230400000, P_GCC_GPLL4_OUT_MAIN, 3.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_emac0_ptp_clk_src = {
.cmd_rcgr = 0xaa020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_emac0_ptp_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_ptp_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] = {
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_emac0_rgmii_clk_src = {
.cmd_rcgr = 0xaa040,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_emac0_rgmii_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_rgmii_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_emac1_ptp_clk_src = {
.cmd_rcgr = 0xba020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_emac0_ptp_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_ptp_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_emac1_rgmii_clk_src = {
.cmd_rcgr = 0xba040,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_9,
.freq_tbl = ftbl_gcc_emac0_rgmii_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_rgmii_clk_src",
.parent_data = gcc_parent_data_9,
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x64004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x65004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x66004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_gp4_clk_src = {
.cmd_rcgr = 0xc2004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp4_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_gp5_clk_src = {
.cmd_rcgr = 0xc3004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp5_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
.cmd_rcgr = 0xa4054,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
.cmd_rcgr = 0xa403c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_1_aux_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
.cmd_rcgr = 0x8d054,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
.cmd_rcgr = 0x8d03c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_2a_aux_clk_src = {
.cmd_rcgr = 0x9d064,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2a_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_2a_phy_rchng_clk_src = {
.cmd_rcgr = 0x9d044,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2a_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_2b_aux_clk_src = {
.cmd_rcgr = 0x9e064,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2b_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_2b_phy_rchng_clk_src = {
.cmd_rcgr = 0x9e044,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2b_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_3a_aux_clk_src = {
.cmd_rcgr = 0xa0064,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3a_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_3a_phy_rchng_clk_src = {
.cmd_rcgr = 0xa0044,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3a_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_3b_aux_clk_src = {
.cmd_rcgr = 0xa2064,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3b_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_3b_phy_rchng_clk_src = {
.cmd_rcgr = 0xa2044,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3b_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_4_aux_clk_src = {
.cmd_rcgr = 0x6b064,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_4_phy_rchng_clk_src = {
.cmd_rcgr = 0x6b044,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_rscc_xo_clk_src = {
.cmd_rcgr = 0xae00c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_rscc_xo_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x33010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x17148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.cmd_rcgr = 0x17278,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.cmd_rcgr = 0x173a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.cmd_rcgr = 0x174d8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.cmd_rcgr = 0x17608,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.cmd_rcgr = 0x17738,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s6_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
.name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
.cmd_rcgr = 0x17868,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
.name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
.cmd_rcgr = 0x17998,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.cmd_rcgr = 0x18148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.cmd_rcgr = 0x18278,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.cmd_rcgr = 0x183a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.cmd_rcgr = 0x184d8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.cmd_rcgr = 0x18608,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.cmd_rcgr = 0x18738,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
.name = "gcc_qupv3_wrap1_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
.cmd_rcgr = 0x18868,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
.name = "gcc_qupv3_wrap1_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
.cmd_rcgr = 0x18998,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
.name = "gcc_qupv3_wrap2_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
.cmd_rcgr = 0x1e148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
.name = "gcc_qupv3_wrap2_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
.cmd_rcgr = 0x1e278,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
.name = "gcc_qupv3_wrap2_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
.cmd_rcgr = 0x1e3a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
.name = "gcc_qupv3_wrap2_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
.cmd_rcgr = 0x1e4d8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
.name = "gcc_qupv3_wrap2_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
.cmd_rcgr = 0x1e608,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
.name = "gcc_qupv3_wrap2_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
.cmd_rcgr = 0x1e738,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
.name = "gcc_qupv3_wrap2_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
.cmd_rcgr = 0x1e868,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
.name = "gcc_qupv3_wrap2_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
.cmd_rcgr = 0x1e998,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.cmd_rcgr = 0x1400c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_15,
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_15,
.num_parents = ARRAY_SIZE(gcc_parent_data_15),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
.cmd_rcgr = 0x1600c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc4_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
.cmd_rcgr = 0x75024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_axi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
.cmd_rcgr = 0x7506c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
.cmd_rcgr = 0x750a0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
.cmd_rcgr = 0x75084,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_unipro_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.cmd_rcgr = 0x77024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_axi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.cmd_rcgr = 0x7706c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
.cmd_rcgr = 0x770a0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.cmd_rcgr = 0x77084,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_unipro_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = {
F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_mp_master_clk_src = {
.cmd_rcgr = 0xab020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_mp_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = {
.cmd_rcgr = 0xab038,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_mp_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.cmd_rcgr = 0xf020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.cmd_rcgr = 0xf038,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
.cmd_rcgr = 0x10020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_sec_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
.cmd_rcgr = 0x10038,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_sec_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = {
.cmd_rcgr = 0xab06c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_mp_phy_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.cmd_rcgr = 0xf068,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
.cmd_rcgr = 0x10068,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_sec_phy_aux_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb4_1_master_clk_src[] = {
F(85714286, P_GCC_GPLL0_OUT_EVEN, 3.5, 0, 0),
F(175000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),
F(350000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb4_1_master_clk_src = {
.cmd_rcgr = 0xb8018,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_usb4_1_master_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_master_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb4_1_phy_pcie_pipe_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb4_1_phy_pcie_pipe_clk_src = {
.cmd_rcgr = 0xb80c4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_usb4_1_phy_pcie_pipe_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_phy_pcie_pipe_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb4_1_sb_if_clk_src = {
.cmd_rcgr = 0xb8070,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_sb_if_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb4_1_tmu_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(250000000, P_GCC_GPLL2_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb4_1_tmu_clk_src = {
.cmd_rcgr = 0xb8054,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_usb4_1_tmu_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_tmu_clk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb4_master_clk_src = {
.cmd_rcgr = 0x2a018,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_usb4_1_master_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_master_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb4_phy_pcie_pipe_clk_src = {
.cmd_rcgr = 0x2a0c4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_usb4_1_phy_pcie_pipe_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_phy_pcie_pipe_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb4_sb_if_clk_src = {
.cmd_rcgr = 0x2a070,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_sb_if_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb4_tmu_clk_src = {
.cmd_rcgr = 0x2a054,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_usb4_1_tmu_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_tmu_clk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div gcc_pcie_2a_pipe_div_clk_src = {
.reg = 0x9d060,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2a_pipe_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_2a_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_pcie_2b_pipe_div_clk_src = {
.reg = 0x9e060,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2b_pipe_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_2b_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_pcie_3a_pipe_div_clk_src = {
.reg = 0xa0060,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3a_pipe_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_3a_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_pcie_3b_pipe_div_clk_src = {
.reg = 0xa2060,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3b_pipe_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_3b_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_pcie_4_pipe_div_clk_src = {
.reg = 0x6b060,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_pipe_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_4_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_qupv3_wrap0_s4_div_clk_src = {
.reg = 0x17ac8,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s4_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_qupv3_wrap1_s4_div_clk_src = {
.reg = 0x18ac8,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s4_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_qupv3_wrap2_s4_div_clk_src = {
.reg = 0x1eac8,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s4_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_usb30_mp_mock_utmi_postdiv_clk_src = {
.reg = 0xab050,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_mp_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_mp_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
.reg = 0xf050,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
.reg = 0x10050,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gcc_aggre_noc_pcie0_tunnel_axi_clk = {
.halt_reg = 0xa41a8,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0xa41a8,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(14),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_noc_pcie0_tunnel_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_noc_pcie1_tunnel_axi_clk = {
.halt_reg = 0x8d07c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x8d07c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(21),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_noc_pcie1_tunnel_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_noc_pcie_4_axi_clk = {
.halt_reg = 0x6b1b8,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x6b1b8,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(12),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_noc_pcie_4_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_noc_pcie_south_sf_axi_clk = {
.halt_reg = 0xbf13c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0xbf13c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(13),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_noc_pcie_south_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
.halt_reg = 0x750cc,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x750cc,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x750cc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_ufs_card_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
.halt_reg = 0x750cc,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x750cc,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x750cc,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
.halt_reg = 0x770cc,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x770cc,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x770cc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
.halt_reg = 0x770cc,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x770cc,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x770cc,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_mp_axi_clk = {
.halt_reg = 0xab084,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xab084,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xab084,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_usb3_mp_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_mp_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
.halt_reg = 0xf080,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xf080,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xf080,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
.halt_reg = 0x10080,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x10080,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x10080,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_usb3_sec_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb4_1_axi_clk = {
.halt_reg = 0xb80e4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xb80e4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb80e4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_usb4_1_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_1_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb4_axi_clk = {
.halt_reg = 0x2a0e4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2a0e4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2a0e4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_usb4_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb_noc_axi_clk = {
.halt_reg = 0x5d024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x5d024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5d024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_usb_noc_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb_noc_north_axi_clk = {
.halt_reg = 0x5d020,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x5d020,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5d020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_usb_noc_north_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb_noc_south_axi_clk = {
.halt_reg = 0x5d01c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x5d01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5d01c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_usb_noc_south_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ahb2phy0_clk = {
.halt_reg = 0x6a004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6a004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x6a004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ahb2phy0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ahb2phy2_clk = {
.halt_reg = 0x6a008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6a008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x6a008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ahb2phy2_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x38004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x38004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(10),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_hf_axi_clk = {
.halt_reg = 0x26010,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x26010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x26010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_camera_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_sf_axi_clk = {
.halt_reg = 0x26014,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x26014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x26014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_camera_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_throttle_nrt_axi_clk = {
.halt_reg = 0x2601c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x2601c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2601c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_camera_throttle_nrt_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_throttle_rt_axi_clk = {
.halt_reg = 0x26018,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x26018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x26018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_camera_throttle_rt_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_throttle_xo_clk = {
.halt_reg = 0x26024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x26024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_camera_throttle_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = {
.halt_reg = 0xab088,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xab088,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xab088,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cfg_noc_usb3_mp_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_mp_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.halt_reg = 0xf084,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xf084,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xf084,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
.halt_reg = 0x10084,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x10084,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x10084,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cfg_noc_usb3_sec_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cnoc_pcie0_tunnel_clk = {
.halt_reg = 0xa4074,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(8),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cnoc_pcie0_tunnel_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cnoc_pcie1_tunnel_clk = {
.halt_reg = 0x8d074,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(9),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cnoc_pcie1_tunnel_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cnoc_pcie4_qx_clk = {
.halt_reg = 0x6b084,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b084,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(10),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cnoc_pcie4_qx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ddrss_gpu_axi_clk = {
.halt_reg = 0x7115c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x7115c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7115c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ddrss_gpu_axi_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = {
.halt_reg = 0xa602c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0xa602c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(19),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ddrss_pcie_sf_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp1_hf_axi_clk = {
.halt_reg = 0xbb010,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0xbb010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xbb010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_disp1_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp1_sf_axi_clk = {
.halt_reg = 0xbb018,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0xbb018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xbb018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_disp1_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp1_throttle_nrt_axi_clk = {
.halt_reg = 0xbb024,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0xbb024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xbb024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_disp1_throttle_nrt_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp1_throttle_rt_axi_clk = {
.halt_reg = 0xbb020,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0xbb020,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xbb020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_disp1_throttle_rt_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_hf_axi_clk = {
.halt_reg = 0x27010,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x27010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x27010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_disp_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_sf_axi_clk = {
.halt_reg = 0x27018,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x27018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x27018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_disp_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_throttle_nrt_axi_clk = {
.halt_reg = 0x27024,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x27024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x27024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_disp_throttle_nrt_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_throttle_rt_axi_clk = {
.halt_reg = 0x27020,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x27020,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x27020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_disp_throttle_rt_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac0_axi_clk = {
.halt_reg = 0xaa010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xaa010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xaa010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac0_ptp_clk = {
.halt_reg = 0xaa01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xaa01c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_ptp_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_emac0_ptp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac0_rgmii_clk = {
.halt_reg = 0xaa038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xaa038,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_rgmii_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_emac0_rgmii_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac0_slv_ahb_clk = {
.halt_reg = 0xaa018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xaa018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xaa018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_slv_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac1_axi_clk = {
.halt_reg = 0xba010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xba010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xba010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac1_ptp_clk = {
.halt_reg = 0xba01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xba01c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_ptp_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_emac1_ptp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac1_rgmii_clk = {
.halt_reg = 0xba038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xba038,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_rgmii_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_emac1_rgmii_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac1_slv_ahb_clk = {
.halt_reg = 0xba018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xba018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xba018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_slv_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x64000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x64000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x65000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x65000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x66000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x66000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp4_clk = {
.halt_reg = 0xc2000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc2000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp5_clk = {
.halt_reg = 0xc3000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc3000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(15),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpu_gpll0_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_gpll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(16),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_gpll0_out_even.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_iref_en = {
.halt_reg = 0x8c014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpu_iref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
.halt_reg = 0x71010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x71010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpu_memnoc_gfx_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
.halt_reg = 0x71020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x71020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpu_snoc_dvm_gfx_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_gpu_tcu_throttle_ahb_clk = {
.halt_reg = 0x71008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x71008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpu_tcu_throttle_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_tcu_throttle_clk = {
.halt_reg = 0x71018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x71018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpu_tcu_throttle_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_phy_rchng_clk = {
.halt_reg = 0xa4038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(11),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie0_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie1_phy_rchng_clk = {
.halt_reg = 0x8d038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(23),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie1_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie2a_phy_rchng_clk = {
.halt_reg = 0x9d040,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(15),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie2a_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_2a_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie2b_phy_rchng_clk = {
.halt_reg = 0x9e040,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(22),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie2b_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_2b_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3a_phy_rchng_clk = {
.halt_reg = 0xa0040,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(29),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3a_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_3a_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3b_phy_rchng_clk = {
.halt_reg = 0xa2040,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3b_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_3b_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie4_phy_rchng_clk = {
.halt_reg = 0x6b040,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(22),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie4_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_4_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_aux_clk = {
.halt_reg = 0xa4028,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(9),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.halt_reg = 0xa4024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xa4024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(8),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.halt_reg = 0xa401c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0xa401c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(7),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_pipe_clk = {
.halt_reg = 0xa4030,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(10),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_phy_pcie_pipe_mux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.halt_reg = 0xa4014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xa4014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(6),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
.halt_reg = 0xa4010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(5),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_aux_clk = {
.halt_reg = 0x8d028,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(29),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_1_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
.halt_reg = 0x8d024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8d024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(28),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
.halt_reg = 0x8d01c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x8d01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(27),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_pipe_clk = {
.halt_reg = 0x8d030,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(30),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_axi_clk = {
.halt_reg = 0x8d014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8d014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(26),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
.halt_reg = 0x8d010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(25),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2a2b_clkref_clk = {
.halt_reg = 0x8c034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2a2b_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2a_aux_clk = {
.halt_reg = 0x9d028,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(13),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2a_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_2a_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2a_cfg_ahb_clk = {
.halt_reg = 0x9d024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9d024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(12),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2a_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2a_mstr_axi_clk = {
.halt_reg = 0x9d01c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x9d01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(11),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2a_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2a_pipe_clk = {
.halt_reg = 0x9d030,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(14),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2a_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_2a_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2a_pipediv2_clk = {
.halt_reg = 0x9d038,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(22),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2a_pipediv2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_2a_pipe_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2a_slv_axi_clk = {
.halt_reg = 0x9d014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9d014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(10),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2a_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2a_slv_q2a_axi_clk = {
.halt_reg = 0x9d010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(12),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2a_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2b_aux_clk = {
.halt_reg = 0x9e028,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(20),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2b_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_2b_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2b_cfg_ahb_clk = {
.halt_reg = 0x9e024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9e024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(19),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2b_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2b_mstr_axi_clk = {
.halt_reg = 0x9e01c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x9e01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(18),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2b_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2b_pipe_clk = {
.halt_reg = 0x9e030,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(21),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2b_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_2b_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2b_pipediv2_clk = {
.halt_reg = 0x9e038,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(23),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2b_pipediv2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_2b_pipe_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2b_slv_axi_clk = {
.halt_reg = 0x9e014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9e014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(17),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2b_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2b_slv_q2a_axi_clk = {
.halt_reg = 0x9e010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(16),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2b_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3a3b_clkref_clk = {
.halt_reg = 0x8c038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c038,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3a3b_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3a_aux_clk = {
.halt_reg = 0xa0028,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(27),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3a_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_3a_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3a_cfg_ahb_clk = {
.halt_reg = 0xa0024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xa0024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(26),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3a_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3a_mstr_axi_clk = {
.halt_reg = 0xa001c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0xa001c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(25),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3a_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3a_pipe_clk = {
.halt_reg = 0xa0030,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(28),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3a_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_3a_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3a_pipediv2_clk = {
.halt_reg = 0xa0038,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(24),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3a_pipediv2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_3a_pipe_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3a_slv_axi_clk = {
.halt_reg = 0xa0014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xa0014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(24),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3a_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3a_slv_q2a_axi_clk = {
.halt_reg = 0xa0010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(23),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3a_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3b_aux_clk = {
.halt_reg = 0xa2028,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(2),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3b_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_3b_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3b_cfg_ahb_clk = {
.halt_reg = 0xa2024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xa2024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3b_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3b_mstr_axi_clk = {
.halt_reg = 0xa201c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0xa201c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3b_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3b_pipe_clk = {
.halt_reg = 0xa2030,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(3),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3b_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_3b_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3b_pipediv2_clk = {
.halt_reg = 0xa2038,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(25),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3b_pipediv2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_3b_pipe_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3b_slv_axi_clk = {
.halt_reg = 0xa2014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xa2014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(31),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3b_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_3b_slv_q2a_axi_clk = {
.halt_reg = 0xa2010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(30),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3b_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_4_aux_clk = {
.halt_reg = 0x6b028,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(3),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_4_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_4_cfg_ahb_clk = {
.halt_reg = 0x6b024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(2),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_4_clkref_clk = {
.halt_reg = 0x8c030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_4_mstr_axi_clk = {
.halt_reg = 0x6b01c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x6b01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_4_pipe_clk = {
.halt_reg = 0x6b030,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_4_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_4_pipediv2_clk = {
.halt_reg = 0x6b038,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(16),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_pipediv2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_4_pipe_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_4_slv_axi_clk = {
.halt_reg = 0x6b014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_4_slv_q2a_axi_clk = {
.halt_reg = 0x6b010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(5),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_rscc_ahb_clk = {
.halt_reg = 0xae008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xae008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(17),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_rscc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_rscc_xo_clk = {
.halt_reg = 0xae004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(16),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_rscc_xo_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_rscc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_throttle_cfg_clk = {
.halt_reg = 0xa6028,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(15),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_throttle_cfg_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x3300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3300c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x33004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x33004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x33004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x33008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x33008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
.halt_reg = 0x26008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x26008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x26008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_camera_nrt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
.halt_reg = 0x2600c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2600c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2600c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_camera_rt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp1_ahb_clk = {
.halt_reg = 0xbb008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xbb008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xbb008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_disp1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp1_rot_ahb_clk = {
.halt_reg = 0xbb00c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xbb00c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xbb00c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_disp1_rot_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp_ahb_clk = {
.halt_reg = 0x27008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x27008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x27008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_disp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp_rot_ahb_clk = {
.halt_reg = 0x2700c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2700c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2700c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_disp_rot_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
.halt_reg = 0x28008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x28008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x28008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_video_cvp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
.halt_reg = 0x2800c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2800c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2800c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_video_vcodec_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
.halt_reg = 0x17014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(9),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_clk = {
.halt_reg = 0x1700c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(8),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_qspi0_clk = {
.halt_reg = 0x17ac4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_qspi0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.halt_reg = 0x17144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(10),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.halt_reg = 0x17274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(11),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.halt_reg = 0x173a4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(12),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.halt_reg = 0x174d4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(13),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.halt_reg = 0x17604,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(14),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s4_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.halt_reg = 0x17734,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(15),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
.halt_reg = 0x17864,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(16),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s6_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
.halt_reg = 0x17994,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(17),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s7_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
.halt_reg = 0x18014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(18),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_clk = {
.halt_reg = 0x1800c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(19),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_qspi0_clk = {
.halt_reg = 0x18ac4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(2),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_qspi0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.halt_reg = 0x18144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(22),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.halt_reg = 0x18274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(23),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.halt_reg = 0x183a4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(24),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.halt_reg = 0x184d4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(25),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.halt_reg = 0x18604,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(26),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s4_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.halt_reg = 0x18734,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(27),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
.halt_reg = 0x18864,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(27),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s6_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
.halt_reg = 0x18994,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(28),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s7_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
.halt_reg = 0x1e014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(3),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_core_clk = {
.halt_reg = 0x1e00c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_qspi0_clk = {
.halt_reg = 0x1eac4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_qspi0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
.halt_reg = 0x1e144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
.halt_reg = 0x1e274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(5),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
.halt_reg = 0x1e3a4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(6),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
.halt_reg = 0x1e4d4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(7),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
.halt_reg = 0x1e604,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(8),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s4_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
.halt_reg = 0x1e734,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(9),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
.halt_reg = 0x1e864,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(29),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s6_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s7_clk = {
.halt_reg = 0x1e994,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(30),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s7_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap2_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(6),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
.halt_reg = 0x17008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(7),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
.halt_reg = 0x18004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x18004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(20),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_1_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
.halt_reg = 0x18008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x18008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(21),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_1_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
.halt_reg = 0x1e004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1e004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(2),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_2_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
.halt_reg = 0x1e008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1e008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_2_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x14008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x14004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_ahb_clk = {
.halt_reg = 0x16008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc4_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_apps_clk = {
.halt_reg = 0x16004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc4_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_usb_axi_clk = {
.halt_reg = 0x5d000,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x5d000,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5d000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sys_noc_usb_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_1_card_clkref_clk = {
.halt_reg = 0x8c000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_1_card_clkref_clk",
.parent_data = &gcc_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_ahb_clk = {
.halt_reg = 0x75018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x75018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_axi_clk = {
.halt_reg = 0x75010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x75010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
.halt_reg = 0x75010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x75010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75010,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_clkref_clk = {
.halt_reg = 0x8c054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c054,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_clkref_clk",
.parent_data = &gcc_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_ice_core_clk = {
.halt_reg = 0x75064,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x75064,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
.halt_reg = 0x75064,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x75064,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75064,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_ice_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_phy_aux_clk = {
.halt_reg = 0x7509c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7509c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7509c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
.halt_reg = 0x7509c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7509c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7509c,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
.halt_reg = 0x75020,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x75020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_rx_symbol_0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_rx_symbol_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
.halt_reg = 0x750b8,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x750b8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_rx_symbol_1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_rx_symbol_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
.halt_reg = 0x7501c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7501c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_tx_symbol_0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_tx_symbol_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_unipro_core_clk = {
.halt_reg = 0x7505c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7505c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7505c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
.halt_reg = 0x7505c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7505c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7505c,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_card_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x77018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_clk = {
.halt_reg = 0x77010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
.halt_reg = 0x77010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77010,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.halt_reg = 0x77064,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77064,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
.halt_reg = 0x77064,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77064,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77064,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.halt_reg = 0x7709c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7709c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7709c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
.halt_reg = 0x7709c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7709c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7709c,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.halt_reg = 0x77020,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x77020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_rx_symbol_0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
.halt_reg = 0x770b8,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x770b8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_rx_symbol_1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
.halt_reg = 0x7701c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7701c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_tx_symbol_0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.halt_reg = 0x7705c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7705c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7705c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
.halt_reg = 0x7705c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7705c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7705c,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_ref_clkref_clk = {
.halt_reg = 0x8c058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c058,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_ref_clkref_clk",
.parent_data = &gcc_parent_data_tcxo,
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb2_hs0_clkref_clk = {
.halt_reg = 0x8c044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c044,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb2_hs0_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb2_hs1_clkref_clk = {
.halt_reg = 0x8c048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb2_hs1_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb2_hs2_clkref_clk = {
.halt_reg = 0x8c04c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c04c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb2_hs2_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb2_hs3_clkref_clk = {
.halt_reg = 0x8c050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c050,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb2_hs3_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_mp_master_clk = {
.halt_reg = 0xab010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xab010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_mp_master_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_mp_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_mp_mock_utmi_clk = {
.halt_reg = 0xab01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xab01c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_mp_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_mp_sleep_clk = {
.halt_reg = 0xab018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xab018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_mp_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_master_clk = {
.halt_reg = 0xf010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_master_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0xf01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf01c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_sleep_clk = {
.halt_reg = 0xf018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_master_clk = {
.halt_reg = 0x10010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_sec_master_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
.halt_reg = 0x1001c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1001c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_sec_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_sleep_clk = {
.halt_reg = 0x10018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_sec_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_mp0_clkref_clk = {
.halt_reg = 0x8c03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c03c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_mp0_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_mp1_clkref_clk = {
.halt_reg = 0x8c040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_mp1_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_mp_phy_aux_clk = {
.halt_reg = 0xab054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xab054,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_mp_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_mp_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = {
.halt_reg = 0xab058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xab058,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_mp_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_mp_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = {
.halt_reg = 0xab05c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0xab05c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_mp_phy_pipe_0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_mp_phy_pipe_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = {
.halt_reg = 0xab064,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0xab064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_mp_phy_pipe_1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_mp_phy_pipe_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
.halt_reg = 0xf054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf054,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_prim_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.halt_reg = 0xf058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf058,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_reg = 0xf05c,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0xf05c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xf05c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_prim_phy_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
.halt_reg = 0x10054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10054,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_sec_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
.halt_reg = 0x10058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x10058,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_sec_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
.halt_reg = 0x1005c,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x1005c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1005c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_sec_phy_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_cfg_ahb_clk = {
.halt_reg = 0xb808c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xb808c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb808c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_dp_clk = {
.halt_reg = 0xb8048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb8048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_dp_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_1_phy_dp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_master_clk = {
.halt_reg = 0xb8010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb8010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_master_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_1_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = {
.halt_reg = 0xb80b4,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0xb80b4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_phy_p2rr2p_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = {
.halt_reg = 0xb8038,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(19),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_phy_pcie_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_phy_rx0_clk = {
.halt_reg = 0xb8094,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb8094,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_phy_rx0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_1_phy_rx0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_phy_rx1_clk = {
.halt_reg = 0xb80a0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb80a0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_phy_rx1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_1_phy_rx1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = {
.halt_reg = 0xb8088,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0xb8088,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb8088,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_phy_usb_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_sb_if_clk = {
.halt_reg = 0xb8034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb8034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_sb_if_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_1_sb_if_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_sys_clk = {
.halt_reg = 0xb8040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb8040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_sys_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_1_phy_sys_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_1_tmu_clk = {
.halt_reg = 0xb806c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xb806c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb806c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_1_tmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_1_tmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_cfg_ahb_clk = {
.halt_reg = 0x2a08c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2a08c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2a08c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_clkref_clk = {
.halt_reg = 0x8c010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_dp_clk = {
.halt_reg = 0x2a048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2a048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_dp_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_phy_dp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_eud_clkref_clk = {
.halt_reg = 0x8c02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c02c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_eud_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_master_clk = {
.halt_reg = 0x2a010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2a010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_master_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_phy_p2rr2p_pipe_clk = {
.halt_reg = 0x2a0b4,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x2a0b4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_phy_p2rr2p_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_phy_p2rr2p_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_phy_pcie_pipe_clk = {
.halt_reg = 0x2a038,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(18),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_phy_pcie_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_phy_pcie_pipe_mux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_phy_rx0_clk = {
.halt_reg = 0x2a094,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2a094,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_phy_rx0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_phy_rx0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_phy_rx1_clk = {
.halt_reg = 0x2a0a0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2a0a0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_phy_rx1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_phy_rx1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_phy_usb_pipe_clk = {
.halt_reg = 0x2a088,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x2a088,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2a088,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_phy_usb_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_sb_if_clk = {
.halt_reg = 0x2a034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2a034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_sb_if_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_sb_if_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_sys_clk = {
.halt_reg = 0x2a040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2a040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_sys_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_phy_sys_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb4_tmu_clk = {
.halt_reg = 0x2a06c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2a06c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2a06c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb4_tmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb4_tmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi0_clk = {
.halt_reg = 0x28010,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x28010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x28010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_video_axi0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi1_clk = {
.halt_reg = 0x28018,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x28018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x28018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_video_axi1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_cvp_throttle_clk = {
.halt_reg = 0x28024,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x28024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x28024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_video_cvp_throttle_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_vcodec_throttle_clk = {
.halt_reg = 0x28020,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x28020,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x28020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_video_vcodec_throttle_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc pcie_0_tunnel_gdsc = {
.gdscr = 0xa4004,
.collapse_ctrl = 0x52128,
.collapse_mask = BIT(0),
.pd = {
.name = "pcie_0_tunnel_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc pcie_1_tunnel_gdsc = {
.gdscr = 0x8d004,
.collapse_ctrl = 0x52128,
.collapse_mask = BIT(1),
.pd = {
.name = "pcie_1_tunnel_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE | RETAIN_FF_ENABLE,
};
/*
* The Qualcomm PCIe driver does not yet implement suspend so to keep the
* PCIe power domains always-on for now.
*/
static struct gdsc pcie_2a_gdsc = {
.gdscr = 0x9d004,
.collapse_ctrl = 0x52128,
.collapse_mask = BIT(2),
.pd = {
.name = "pcie_2a_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
.flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc pcie_2b_gdsc = {
.gdscr = 0x9e004,
.collapse_ctrl = 0x52128,
.collapse_mask = BIT(3),
.pd = {
.name = "pcie_2b_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
.flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc pcie_3a_gdsc = {
.gdscr = 0xa0004,
.collapse_ctrl = 0x52128,
.collapse_mask = BIT(4),
.pd = {
.name = "pcie_3a_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
.flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc pcie_3b_gdsc = {
.gdscr = 0xa2004,
.collapse_ctrl = 0x52128,
.collapse_mask = BIT(5),
.pd = {
.name = "pcie_3b_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
.flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc pcie_4_gdsc = {
.gdscr = 0x6b004,
.collapse_ctrl = 0x52128,
.collapse_mask = BIT(6),
.pd = {
.name = "pcie_4_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
.flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc ufs_card_gdsc = {
.gdscr = 0x75004,
.pd = {
.name = "ufs_card_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc ufs_phy_gdsc = {
.gdscr = 0x77004,
.pd = {
.name = "ufs_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc usb30_mp_gdsc = {
.gdscr = 0xab004,
.pd = {
.name = "usb30_mp_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc usb30_prim_gdsc = {
.gdscr = 0xf004,
.pd = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc usb30_sec_gdsc = {
.gdscr = 0x10004,
.pd = {
.name = "usb30_sec_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc emac_0_gdsc = {
.gdscr = 0xaa004,
.pd = {
.name = "emac_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc emac_1_gdsc = {
.gdscr = 0xba004,
.pd = {
.name = "emac_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc usb4_1_gdsc = {
.gdscr = 0xb8004,
.pd = {
.name = "usb4_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc usb4_gdsc = {
.gdscr = 0x2a004,
.pd = {
.name = "usb4_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
.gdscr = 0x7d050,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
.gdscr = 0x7d058,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = {
.gdscr = 0x7d054,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc = {
.gdscr = 0x7d06c,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
.gdscr = 0x7d05c,
.pd = {
.name = "hlos1_vote_turing_mmu_tbu0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
.gdscr = 0x7d060,
.pd = {
.name = "hlos1_vote_turing_mmu_tbu1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_turing_mmu_tbu2_gdsc = {
.gdscr = 0x7d0a0,
.pd = {
.name = "hlos1_vote_turing_mmu_tbu2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_turing_mmu_tbu3_gdsc = {
.gdscr = 0x7d0a4,
.pd = {
.name = "hlos1_vote_turing_mmu_tbu3_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct clk_regmap *gcc_sc8280xp_clocks[] = {
[GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK] = &gcc_aggre_noc_pcie0_tunnel_axi_clk.clkr,
[GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK] = &gcc_aggre_noc_pcie1_tunnel_axi_clk.clkr,
[GCC_AGGRE_NOC_PCIE_4_AXI_CLK] = &gcc_aggre_noc_pcie_4_axi_clk.clkr,
[GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK] = &gcc_aggre_noc_pcie_south_sf_axi_clk.clkr,
[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
[GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_AGGRE_USB3_MP_AXI_CLK] = &gcc_aggre_usb3_mp_axi_clk.clkr,
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
[GCC_AGGRE_USB4_1_AXI_CLK] = &gcc_aggre_usb4_1_axi_clk.clkr,
[GCC_AGGRE_USB4_AXI_CLK] = &gcc_aggre_usb4_axi_clk.clkr,
[GCC_AGGRE_USB_NOC_AXI_CLK] = &gcc_aggre_usb_noc_axi_clk.clkr,
[GCC_AGGRE_USB_NOC_NORTH_AXI_CLK] = &gcc_aggre_usb_noc_north_axi_clk.clkr,
[GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK] = &gcc_aggre_usb_noc_south_axi_clk.clkr,
[GCC_AHB2PHY0_CLK] = &gcc_ahb2phy0_clk.clkr,
[GCC_AHB2PHY2_CLK] = &gcc_ahb2phy2_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
[GCC_CAMERA_THROTTLE_NRT_AXI_CLK] = &gcc_camera_throttle_nrt_axi_clk.clkr,
[GCC_CAMERA_THROTTLE_RT_AXI_CLK] = &gcc_camera_throttle_rt_axi_clk.clkr,
[GCC_CAMERA_THROTTLE_XO_CLK] = &gcc_camera_throttle_xo_clk.clkr,
[GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
[GCC_CNOC_PCIE0_TUNNEL_CLK] = &gcc_cnoc_pcie0_tunnel_clk.clkr,
[GCC_CNOC_PCIE1_TUNNEL_CLK] = &gcc_cnoc_pcie1_tunnel_clk.clkr,
[GCC_CNOC_PCIE4_QX_CLK] = &gcc_cnoc_pcie4_qx_clk.clkr,
[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
[GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr,
[GCC_DISP1_HF_AXI_CLK] = &gcc_disp1_hf_axi_clk.clkr,
[GCC_DISP1_SF_AXI_CLK] = &gcc_disp1_sf_axi_clk.clkr,
[GCC_DISP1_THROTTLE_NRT_AXI_CLK] = &gcc_disp1_throttle_nrt_axi_clk.clkr,
[GCC_DISP1_THROTTLE_RT_AXI_CLK] = &gcc_disp1_throttle_rt_axi_clk.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
[GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
[GCC_DISP_THROTTLE_NRT_AXI_CLK] = &gcc_disp_throttle_nrt_axi_clk.clkr,
[GCC_DISP_THROTTLE_RT_AXI_CLK] = &gcc_disp_throttle_rt_axi_clk.clkr,
[GCC_EMAC0_AXI_CLK] = &gcc_emac0_axi_clk.clkr,
[GCC_EMAC0_PTP_CLK] = &gcc_emac0_ptp_clk.clkr,
[GCC_EMAC0_PTP_CLK_SRC] = &gcc_emac0_ptp_clk_src.clkr,
[GCC_EMAC0_RGMII_CLK] = &gcc_emac0_rgmii_clk.clkr,
[GCC_EMAC0_RGMII_CLK_SRC] = &gcc_emac0_rgmii_clk_src.clkr,
[GCC_EMAC0_SLV_AHB_CLK] = &gcc_emac0_slv_ahb_clk.clkr,
[GCC_EMAC1_AXI_CLK] = &gcc_emac1_axi_clk.clkr,
[GCC_EMAC1_PTP_CLK] = &gcc_emac1_ptp_clk.clkr,
[GCC_EMAC1_PTP_CLK_SRC] = &gcc_emac1_ptp_clk_src.clkr,
[GCC_EMAC1_RGMII_CLK] = &gcc_emac1_rgmii_clk.clkr,
[GCC_EMAC1_RGMII_CLK_SRC] = &gcc_emac1_rgmii_clk_src.clkr,
[GCC_EMAC1_SLV_AHB_CLK] = &gcc_emac1_slv_ahb_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GP4_CLK] = &gcc_gp4_clk.clkr,
[GCC_GP4_CLK_SRC] = &gcc_gp4_clk_src.clkr,
[GCC_GP5_CLK] = &gcc_gp5_clk.clkr,
[GCC_GP5_CLK_SRC] = &gcc_gp5_clk_src.clkr,
[GCC_GPLL0] = &gcc_gpll0.clkr,
[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
[GCC_GPLL2] = &gcc_gpll2.clkr,
[GCC_GPLL4] = &gcc_gpll4.clkr,
[GCC_GPLL7] = &gcc_gpll7.clkr,
[GCC_GPLL8] = &gcc_gpll8.clkr,
[GCC_GPLL9] = &gcc_gpll9.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_GPU_TCU_THROTTLE_AHB_CLK] = &gcc_gpu_tcu_throttle_ahb_clk.clkr,
[GCC_GPU_TCU_THROTTLE_CLK] = &gcc_gpu_tcu_throttle_clk.clkr,
[GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr,
[GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr,
[GCC_PCIE2A_PHY_RCHNG_CLK] = &gcc_pcie2a_phy_rchng_clk.clkr,
[GCC_PCIE2B_PHY_RCHNG_CLK] = &gcc_pcie2b_phy_rchng_clk.clkr,
[GCC_PCIE3A_PHY_RCHNG_CLK] = &gcc_pcie3a_phy_rchng_clk.clkr,
[GCC_PCIE3B_PHY_RCHNG_CLK] = &gcc_pcie3b_phy_rchng_clk.clkr,
[GCC_PCIE4_PHY_RCHNG_CLK] = &gcc_pcie4_phy_rchng_clk.clkr,
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
[GCC_PCIE_2A2B_CLKREF_CLK] = &gcc_pcie_2a2b_clkref_clk.clkr,
[GCC_PCIE_2A_AUX_CLK] = &gcc_pcie_2a_aux_clk.clkr,
[GCC_PCIE_2A_AUX_CLK_SRC] = &gcc_pcie_2a_aux_clk_src.clkr,
[GCC_PCIE_2A_CFG_AHB_CLK] = &gcc_pcie_2a_cfg_ahb_clk.clkr,
[GCC_PCIE_2A_MSTR_AXI_CLK] = &gcc_pcie_2a_mstr_axi_clk.clkr,
[GCC_PCIE_2A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2a_phy_rchng_clk_src.clkr,
[GCC_PCIE_2A_PIPE_CLK] = &gcc_pcie_2a_pipe_clk.clkr,
[GCC_PCIE_2A_PIPE_CLK_SRC] = &gcc_pcie_2a_pipe_clk_src.clkr,
[GCC_PCIE_2A_PIPE_DIV_CLK_SRC] = &gcc_pcie_2a_pipe_div_clk_src.clkr,
[GCC_PCIE_2A_PIPEDIV2_CLK] = &gcc_pcie_2a_pipediv2_clk.clkr,
[GCC_PCIE_2A_SLV_AXI_CLK] = &gcc_pcie_2a_slv_axi_clk.clkr,
[GCC_PCIE_2A_SLV_Q2A_AXI_CLK] = &gcc_pcie_2a_slv_q2a_axi_clk.clkr,
[GCC_PCIE_2B_AUX_CLK] = &gcc_pcie_2b_aux_clk.clkr,
[GCC_PCIE_2B_AUX_CLK_SRC] = &gcc_pcie_2b_aux_clk_src.clkr,
[GCC_PCIE_2B_CFG_AHB_CLK] = &gcc_pcie_2b_cfg_ahb_clk.clkr,
[GCC_PCIE_2B_MSTR_AXI_CLK] = &gcc_pcie_2b_mstr_axi_clk.clkr,
[GCC_PCIE_2B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2b_phy_rchng_clk_src.clkr,
[GCC_PCIE_2B_PIPE_CLK] = &gcc_pcie_2b_pipe_clk.clkr,
[GCC_PCIE_2B_PIPE_CLK_SRC] = &gcc_pcie_2b_pipe_clk_src.clkr,
[GCC_PCIE_2B_PIPE_DIV_CLK_SRC] = &gcc_pcie_2b_pipe_div_clk_src.clkr,
[GCC_PCIE_2B_PIPEDIV2_CLK] = &gcc_pcie_2b_pipediv2_clk.clkr,
[GCC_PCIE_2B_SLV_AXI_CLK] = &gcc_pcie_2b_slv_axi_clk.clkr,
[GCC_PCIE_2B_SLV_Q2A_AXI_CLK] = &gcc_pcie_2b_slv_q2a_axi_clk.clkr,
[GCC_PCIE_3A3B_CLKREF_CLK] = &gcc_pcie_3a3b_clkref_clk.clkr,
[GCC_PCIE_3A_AUX_CLK] = &gcc_pcie_3a_aux_clk.clkr,
[GCC_PCIE_3A_AUX_CLK_SRC] = &gcc_pcie_3a_aux_clk_src.clkr,
[GCC_PCIE_3A_CFG_AHB_CLK] = &gcc_pcie_3a_cfg_ahb_clk.clkr,
[GCC_PCIE_3A_MSTR_AXI_CLK] = &gcc_pcie_3a_mstr_axi_clk.clkr,
[GCC_PCIE_3A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3a_phy_rchng_clk_src.clkr,
[GCC_PCIE_3A_PIPE_CLK] = &gcc_pcie_3a_pipe_clk.clkr,
[GCC_PCIE_3A_PIPE_CLK_SRC] = &gcc_pcie_3a_pipe_clk_src.clkr,
[GCC_PCIE_3A_PIPE_DIV_CLK_SRC] = &gcc_pcie_3a_pipe_div_clk_src.clkr,
[GCC_PCIE_3A_PIPEDIV2_CLK] = &gcc_pcie_3a_pipediv2_clk.clkr,
[GCC_PCIE_3A_SLV_AXI_CLK] = &gcc_pcie_3a_slv_axi_clk.clkr,
[GCC_PCIE_3A_SLV_Q2A_AXI_CLK] = &gcc_pcie_3a_slv_q2a_axi_clk.clkr,
[GCC_PCIE_3B_AUX_CLK] = &gcc_pcie_3b_aux_clk.clkr,
[GCC_PCIE_3B_AUX_CLK_SRC] = &gcc_pcie_3b_aux_clk_src.clkr,
[GCC_PCIE_3B_CFG_AHB_CLK] = &gcc_pcie_3b_cfg_ahb_clk.clkr,
[GCC_PCIE_3B_MSTR_AXI_CLK] = &gcc_pcie_3b_mstr_axi_clk.clkr,
[GCC_PCIE_3B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3b_phy_rchng_clk_src.clkr,
[GCC_PCIE_3B_PIPE_CLK] = &gcc_pcie_3b_pipe_clk.clkr,
[GCC_PCIE_3B_PIPE_CLK_SRC] = &gcc_pcie_3b_pipe_clk_src.clkr,
[GCC_PCIE_3B_PIPE_DIV_CLK_SRC] = &gcc_pcie_3b_pipe_div_clk_src.clkr,
[GCC_PCIE_3B_PIPEDIV2_CLK] = &gcc_pcie_3b_pipediv2_clk.clkr,
[GCC_PCIE_3B_SLV_AXI_CLK] = &gcc_pcie_3b_slv_axi_clk.clkr,
[GCC_PCIE_3B_SLV_Q2A_AXI_CLK] = &gcc_pcie_3b_slv_q2a_axi_clk.clkr,
[GCC_PCIE_4_AUX_CLK] = &gcc_pcie_4_aux_clk.clkr,
[GCC_PCIE_4_AUX_CLK_SRC] = &gcc_pcie_4_aux_clk_src.clkr,
[GCC_PCIE_4_CFG_AHB_CLK] = &gcc_pcie_4_cfg_ahb_clk.clkr,
[GCC_PCIE_4_CLKREF_CLK] = &gcc_pcie_4_clkref_clk.clkr,
[GCC_PCIE_4_MSTR_AXI_CLK] = &gcc_pcie_4_mstr_axi_clk.clkr,
[GCC_PCIE_4_PHY_RCHNG_CLK_SRC] = &gcc_pcie_4_phy_rchng_clk_src.clkr,
[GCC_PCIE_4_PIPE_CLK] = &gcc_pcie_4_pipe_clk.clkr,
[GCC_PCIE_4_PIPE_CLK_SRC] = &gcc_pcie_4_pipe_clk_src.clkr,
[GCC_PCIE_4_PIPE_DIV_CLK_SRC] = &gcc_pcie_4_pipe_div_clk_src.clkr,
[GCC_PCIE_4_PIPEDIV2_CLK] = &gcc_pcie_4_pipediv2_clk.clkr,
[GCC_PCIE_4_SLV_AXI_CLK] = &gcc_pcie_4_slv_axi_clk.clkr,
[GCC_PCIE_4_SLV_Q2A_AXI_CLK] = &gcc_pcie_4_slv_q2a_axi_clk.clkr,
[GCC_PCIE_RSCC_AHB_CLK] = &gcc_pcie_rscc_ahb_clk.clkr,
[GCC_PCIE_RSCC_XO_CLK] = &gcc_pcie_rscc_xo_clk.clkr,
[GCC_PCIE_RSCC_XO_CLK_SRC] = &gcc_pcie_rscc_xo_clk_src.clkr,
[GCC_PCIE_THROTTLE_CFG_CLK] = &gcc_pcie_throttle_cfg_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
[GCC_QMIP_DISP1_AHB_CLK] = &gcc_qmip_disp1_ahb_clk.clkr,
[GCC_QMIP_DISP1_ROT_AHB_CLK] = &gcc_qmip_disp1_rot_ahb_clk.clkr,
[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
[GCC_QMIP_DISP_ROT_AHB_CLK] = &gcc_qmip_disp_rot_ahb_clk.clkr,
[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
[GCC_QUPV3_WRAP0_QSPI0_CLK] = &gcc_qupv3_wrap0_qspi0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_DIV_CLK_SRC] = &gcc_qupv3_wrap0_s4_div_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
[GCC_QUPV3_WRAP1_QSPI0_CLK] = &gcc_qupv3_wrap1_qspi0_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_DIV_CLK_SRC] = &gcc_qupv3_wrap1_s4_div_clk_src.clkr,
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
[GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
[GCC_QUPV3_WRAP2_QSPI0_CLK] = &gcc_qupv3_wrap2_qspi0_clk.clkr,
[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
[GCC_QUPV3_WRAP2_S4_DIV_CLK_SRC] = &gcc_qupv3_wrap2_s4_div_clk_src.clkr,
[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
[GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
[GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
[GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr,
[GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
[GCC_SYS_NOC_USB_AXI_CLK] = &gcc_sys_noc_usb_axi_clk.clkr,
[GCC_UFS_1_CARD_CLKREF_CLK] = &gcc_ufs_1_card_clkref_clk.clkr,
[GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
[GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
[GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
[GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
[GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
[GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
[GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
[GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
[GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
[GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
[GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
[GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
[GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_rx_symbol_0_clk_src.clkr,
[GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
[GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_card_rx_symbol_1_clk_src.clkr,
[GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
[GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_tx_symbol_0_clk_src.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
[GCC_UFS_REF_CLKREF_CLK] = &gcc_ufs_ref_clkref_clk.clkr,
[GCC_USB2_HS0_CLKREF_CLK] = &gcc_usb2_hs0_clkref_clk.clkr,
[GCC_USB2_HS1_CLKREF_CLK] = &gcc_usb2_hs1_clkref_clk.clkr,
[GCC_USB2_HS2_CLKREF_CLK] = &gcc_usb2_hs2_clkref_clk.clkr,
[GCC_USB2_HS3_CLKREF_CLK] = &gcc_usb2_hs3_clkref_clk.clkr,
[GCC_USB30_MP_MASTER_CLK] = &gcc_usb30_mp_master_clk.clkr,
[GCC_USB30_MP_MASTER_CLK_SRC] = &gcc_usb30_mp_master_clk_src.clkr,
[GCC_USB30_MP_MOCK_UTMI_CLK] = &gcc_usb30_mp_mock_utmi_clk.clkr,
[GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mp_mock_utmi_clk_src.clkr,
[GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_MP_SLEEP_CLK] = &gcc_usb30_mp_sleep_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,
[GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
[GCC_USB34_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb34_prim_phy_pipe_clk_src.clkr,
[GCC_USB34_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb34_sec_phy_pipe_clk_src.clkr,
[GCC_USB3_MP0_CLKREF_CLK] = &gcc_usb3_mp0_clkref_clk.clkr,
[GCC_USB3_MP1_CLKREF_CLK] = &gcc_usb3_mp1_clkref_clk.clkr,
[GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr,
[GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr,
[GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr,
[GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr,
[GCC_USB3_MP_PHY_PIPE_0_CLK_SRC] = &gcc_usb3_mp_phy_pipe_0_clk_src.clkr,
[GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr,
[GCC_USB3_MP_PHY_PIPE_1_CLK_SRC] = &gcc_usb3_mp_phy_pipe_1_clk_src.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
[GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
[GCC_USB4_1_CFG_AHB_CLK] = &gcc_usb4_1_cfg_ahb_clk.clkr,
[GCC_USB4_1_DP_CLK] = &gcc_usb4_1_dp_clk.clkr,
[GCC_USB4_1_MASTER_CLK] = &gcc_usb4_1_master_clk.clkr,
[GCC_USB4_1_MASTER_CLK_SRC] = &gcc_usb4_1_master_clk_src.clkr,
[GCC_USB4_1_PHY_DP_CLK_SRC] = &gcc_usb4_1_phy_dp_clk_src.clkr,
[GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr,
[GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr,
[GCC_USB4_1_PHY_PCIE_PIPE_CLK] = &gcc_usb4_1_phy_pcie_pipe_clk.clkr,
[GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr,
[GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr,
[GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipegmux_clk_src.clkr,
[GCC_USB4_1_PHY_RX0_CLK] = &gcc_usb4_1_phy_rx0_clk.clkr,
[GCC_USB4_1_PHY_RX0_CLK_SRC] = &gcc_usb4_1_phy_rx0_clk_src.clkr,
[GCC_USB4_1_PHY_RX1_CLK] = &gcc_usb4_1_phy_rx1_clk.clkr,
[GCC_USB4_1_PHY_RX1_CLK_SRC] = &gcc_usb4_1_phy_rx1_clk_src.clkr,
[GCC_USB4_1_PHY_SYS_CLK_SRC] = &gcc_usb4_1_phy_sys_clk_src.clkr,
[GCC_USB4_1_PHY_USB_PIPE_CLK] = &gcc_usb4_1_phy_usb_pipe_clk.clkr,
[GCC_USB4_1_SB_IF_CLK] = &gcc_usb4_1_sb_if_clk.clkr,
[GCC_USB4_1_SB_IF_CLK_SRC] = &gcc_usb4_1_sb_if_clk_src.clkr,
[GCC_USB4_1_SYS_CLK] = &gcc_usb4_1_sys_clk.clkr,
[GCC_USB4_1_TMU_CLK] = &gcc_usb4_1_tmu_clk.clkr,
[GCC_USB4_1_TMU_CLK_SRC] = &gcc_usb4_1_tmu_clk_src.clkr,
[GCC_USB4_CFG_AHB_CLK] = &gcc_usb4_cfg_ahb_clk.clkr,
[GCC_USB4_CLKREF_CLK] = &gcc_usb4_clkref_clk.clkr,
[GCC_USB4_DP_CLK] = &gcc_usb4_dp_clk.clkr,
[GCC_USB4_EUD_CLKREF_CLK] = &gcc_usb4_eud_clkref_clk.clkr,
[GCC_USB4_MASTER_CLK] = &gcc_usb4_master_clk.clkr,
[GCC_USB4_MASTER_CLK_SRC] = &gcc_usb4_master_clk_src.clkr,
[GCC_USB4_PHY_DP_CLK_SRC] = &gcc_usb4_phy_dp_clk_src.clkr,
[GCC_USB4_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_phy_p2rr2p_pipe_clk.clkr,
[GCC_USB4_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_phy_p2rr2p_pipe_clk_src.clkr,
[GCC_USB4_PHY_PCIE_PIPE_CLK] = &gcc_usb4_phy_pcie_pipe_clk.clkr,
[GCC_USB4_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_phy_pcie_pipe_clk_src.clkr,
[GCC_USB4_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_phy_pcie_pipe_mux_clk_src.clkr,
[GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC] = &gcc_usb4_phy_pcie_pipegmux_clk_src.clkr,
[GCC_USB4_PHY_RX0_CLK] = &gcc_usb4_phy_rx0_clk.clkr,
[GCC_USB4_PHY_RX0_CLK_SRC] = &gcc_usb4_phy_rx0_clk_src.clkr,
[GCC_USB4_PHY_RX1_CLK] = &gcc_usb4_phy_rx1_clk.clkr,
[GCC_USB4_PHY_RX1_CLK_SRC] = &gcc_usb4_phy_rx1_clk_src.clkr,
[GCC_USB4_PHY_SYS_CLK_SRC] = &gcc_usb4_phy_sys_clk_src.clkr,
[GCC_USB4_PHY_USB_PIPE_CLK] = &gcc_usb4_phy_usb_pipe_clk.clkr,
[GCC_USB4_SB_IF_CLK] = &gcc_usb4_sb_if_clk.clkr,
[GCC_USB4_SB_IF_CLK_SRC] = &gcc_usb4_sb_if_clk_src.clkr,
[GCC_USB4_SYS_CLK] = &gcc_usb4_sys_clk.clkr,
[GCC_USB4_TMU_CLK] = &gcc_usb4_tmu_clk.clkr,
[GCC_USB4_TMU_CLK_SRC] = &gcc_usb4_tmu_clk_src.clkr,
[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
[GCC_VIDEO_CVP_THROTTLE_CLK] = &gcc_video_cvp_throttle_clk.clkr,
[GCC_VIDEO_VCODEC_THROTTLE_CLK] = &gcc_video_vcodec_throttle_clk.clkr,
};
static const struct qcom_reset_map gcc_sc8280xp_resets[] = {
[GCC_EMAC0_BCR] = { 0xaa000 },
[GCC_EMAC1_BCR] = { 0xba000 },
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
[GCC_PCIE_0_TUNNEL_BCR] = { 0xa4000 },
[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 },
[GCC_PCIE_1_TUNNEL_BCR] = { 0x8d000 },
[GCC_PCIE_2A_BCR] = { 0x9d000 },
[GCC_PCIE_2A_LINK_DOWN_BCR] = { 0x9d13c },
[GCC_PCIE_2A_NOCSR_COM_PHY_BCR] = { 0x9d148 },
[GCC_PCIE_2A_PHY_BCR] = { 0x9d144 },
[GCC_PCIE_2A_PHY_NOCSR_COM_PHY_BCR] = { 0x9d14c },
[GCC_PCIE_2B_BCR] = { 0x9e000 },
[GCC_PCIE_2B_LINK_DOWN_BCR] = { 0x9e084 },
[GCC_PCIE_2B_NOCSR_COM_PHY_BCR] = { 0x9e090 },
[GCC_PCIE_2B_PHY_BCR] = { 0x9e08c },
[GCC_PCIE_2B_PHY_NOCSR_COM_PHY_BCR] = { 0x9e094 },
[GCC_PCIE_3A_BCR] = { 0xa0000 },
[GCC_PCIE_3A_LINK_DOWN_BCR] = { 0xa00f0 },
[GCC_PCIE_3A_NOCSR_COM_PHY_BCR] = { 0xa00fc },
[GCC_PCIE_3A_PHY_BCR] = { 0xa00e0 },
[GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR] = { 0xa00e4 },
[GCC_PCIE_3B_BCR] = { 0xa2000 },
[GCC_PCIE_3B_LINK_DOWN_BCR] = { 0xa20e0 },
[GCC_PCIE_3B_NOCSR_COM_PHY_BCR] = { 0xa20ec },
[GCC_PCIE_3B_PHY_BCR] = { 0xa20e8 },
[GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR] = { 0xa20f0 },
[GCC_PCIE_4_BCR] = { 0x6b000 },
[GCC_PCIE_4_LINK_DOWN_BCR] = { 0x6b300 },
[GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0x6b30c },
[GCC_PCIE_4_PHY_BCR] = { 0x6b308 },
[GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0x6b310 },
[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
[GCC_PCIE_RSCC_BCR] = { 0xae000 },
[GCC_QUSB2PHY_HS0_MP_BCR] = { 0x12008 },
[GCC_QUSB2PHY_HS1_MP_BCR] = { 0x1200c },
[GCC_QUSB2PHY_HS2_MP_BCR] = { 0x12010 },
[GCC_QUSB2PHY_HS3_MP_BCR] = { 0x12014 },
[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
[GCC_SDCC2_BCR] = { 0x14000 },
[GCC_SDCC4_BCR] = { 0x16000 },
[GCC_UFS_CARD_BCR] = { 0x75000 },
[GCC_UFS_PHY_BCR] = { 0x77000 },
[GCC_USB2_PHY_PRIM_BCR] = { 0x50028 },
[GCC_USB2_PHY_SEC_BCR] = { 0x5002c },
[GCC_USB30_MP_BCR] = { 0xab000 },
[GCC_USB30_PRIM_BCR] = { 0xf000 },
[GCC_USB30_SEC_BCR] = { 0x10000 },
[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
[GCC_USB3_UNIPHY_MP0_BCR] = { 0x50018 },
[GCC_USB3_UNIPHY_MP1_BCR] = { 0x5001c },
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x50020 },
[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x50024 },
[GCC_USB4_1_BCR] = { 0xb8000 },
[GCC_USB4_1_DP_PHY_PRIM_BCR] = { 0xb9020 },
[GCC_USB4_1_DPPHY_AUX_BCR] = { 0xb9024 },
[GCC_USB4_1_PHY_PRIM_BCR] = { 0xb9018 },
[GCC_USB4_BCR] = { 0x2a000 },
[GCC_USB4_DP_PHY_PRIM_BCR] = { 0x4a008 },
[GCC_USB4_DPPHY_AUX_BCR] = { 0x4a00c },
[GCC_USB4_PHY_PRIM_BCR] = { 0x4a000 },
[GCC_USB4PHY_1_PHY_PRIM_BCR] = { 0xb901c },
[GCC_USB4PHY_PHY_PRIM_BCR] = { 0x4a004 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
[GCC_VIDEO_BCR] = { 0x28000 },
[GCC_VIDEO_AXI0_CLK_ARES] = { 0x28010, 2 },
[GCC_VIDEO_AXI1_CLK_ARES] = { 0x28018, 2 },
};
static struct gdsc *gcc_sc8280xp_gdscs[] = {
[PCIE_0_TUNNEL_GDSC] = &pcie_0_tunnel_gdsc,
[PCIE_1_TUNNEL_GDSC] = &pcie_1_tunnel_gdsc,
[PCIE_2A_GDSC] = &pcie_2a_gdsc,
[PCIE_2B_GDSC] = &pcie_2b_gdsc,
[PCIE_3A_GDSC] = &pcie_3a_gdsc,
[PCIE_3B_GDSC] = &pcie_3b_gdsc,
[PCIE_4_GDSC] = &pcie_4_gdsc,
[UFS_CARD_GDSC] = &ufs_card_gdsc,
[UFS_PHY_GDSC] = &ufs_phy_gdsc,
[USB30_MP_GDSC] = &usb30_mp_gdsc,
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
[USB30_SEC_GDSC] = &usb30_sec_gdsc,
[EMAC_0_GDSC] = &emac_0_gdsc,
[EMAC_1_GDSC] = &emac_1_gdsc,
[USB4_1_GDSC] = &usb4_1_gdsc,
[USB4_GDSC] = &usb4_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc,
[HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
[HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
[HLOS1_VOTE_TURING_MMU_TBU2_GDSC] = &hlos1_vote_turing_mmu_tbu2_gdsc,
[HLOS1_VOTE_TURING_MMU_TBU3_GDSC] = &hlos1_vote_turing_mmu_tbu3_gdsc,
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src),
};
static const struct regmap_config gcc_sc8280xp_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xc3014,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_sc8280xp_desc = {
.config = &gcc_sc8280xp_regmap_config,
.clks = gcc_sc8280xp_clocks,
.num_clks = ARRAY_SIZE(gcc_sc8280xp_clocks),
.resets = gcc_sc8280xp_resets,
.num_resets = ARRAY_SIZE(gcc_sc8280xp_resets),
.gdscs = gcc_sc8280xp_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sc8280xp_gdscs),
};
static int gcc_sc8280xp_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
regmap = qcom_cc_map(pdev, &gcc_sc8280xp_desc);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
goto err_put_rpm;
}
/*
* Keep the clocks always-ON
* GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK,
* GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK,
* GCC_VIDEO_XO_CLK, GCC_DISP1_AHB_CLK, GCC_DISP1_XO_CLK
*/
regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x26020, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x27028, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x28028, BIT(0), BIT(0));
regmap_update_bits(regmap, 0xbb004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0xbb028, BIT(0), BIT(0));
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
goto err_put_rpm;
ret = qcom_cc_really_probe(pdev, &gcc_sc8280xp_desc, regmap);
if (ret)
goto err_put_rpm;
pm_runtime_put(&pdev->dev);
return 0;
err_put_rpm:
pm_runtime_put_sync(&pdev->dev);
return ret;
}
static const struct of_device_id gcc_sc8280xp_match_table[] = {
{ .compatible = "qcom,gcc-sc8280xp" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_sc8280xp_match_table);
static struct platform_driver gcc_sc8280xp_driver = {
.probe = gcc_sc8280xp_probe,
.driver = {
.name = "gcc-sc8280xp",
.of_match_table = gcc_sc8280xp_match_table,
},
};
static int __init gcc_sc8280xp_init(void)
{
return platform_driver_register(&gcc_sc8280xp_driver);
}
subsys_initcall(gcc_sc8280xp_init);
static void __exit gcc_sc8280xp_exit(void)
{
platform_driver_unregister(&gcc_sc8280xp_driver);
}
module_exit(gcc_sc8280xp_exit);
MODULE_DESCRIPTION("Qualcomm SC8280XP GCC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/gcc-sc8280xp.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "reset.h"
enum {
DT_XO,
DT_SLEEP_CLK,
DT_PCIE_2LANE_PHY_PIPE_CLK,
DT_PCIE_2LANE_PHY_PIPE_CLK_X1,
DT_USB_PCIE_WRAPPER_PIPE_CLK,
};
enum {
P_PCIE3X2_PIPE,
P_PCIE3X1_0_PIPE,
P_PCIE3X1_1_PIPE,
P_USB3PHY_0_PIPE,
P_CORE_BI_PLL_TEST_SE,
P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC,
P_GPLL0_OUT_AUX,
P_GPLL0_OUT_MAIN,
P_GPLL2_OUT_AUX,
P_GPLL2_OUT_MAIN,
P_GPLL4_OUT_AUX,
P_GPLL4_OUT_MAIN,
P_SLEEP_CLK,
P_XO,
};
static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO };
static struct clk_alpha_pll gpll0_main = {
.offset = 0x20000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
.clkr = {
.enable_reg = 0xb000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpll0_main",
.parent_data = &gcc_parent_data_xo,
.num_parents = 1,
.ops = &clk_alpha_pll_stromer_ops,
},
},
};
static struct clk_fixed_factor gpll0_div2 = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data) {
.name = "gpll0_div2",
.parent_hws = (const struct clk_hw *[]) {
&gpll0_main.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x20000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gpll0",
.parent_hws = (const struct clk_hw *[]) {
&gpll0_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll gpll2_main = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
.clkr = {
.enable_reg = 0xb000,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gpll2",
.parent_data = &gcc_parent_data_xo,
.num_parents = 1,
.ops = &clk_alpha_pll_stromer_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll2 = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gpll2_main",
.parent_hws = (const struct clk_hw *[]) {
&gpll2_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll gpll4_main = {
.offset = 0x22000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
.clkr = {
.enable_reg = 0xb000,
.enable_mask = BIT(2),
.hw.init = &(const struct clk_init_data) {
.name = "gpll4_main",
.parent_data = &gcc_parent_data_xo,
.num_parents = 1,
.ops = &clk_alpha_pll_stromer_ops,
/*
* There are no consumers for this GPLL in kernel yet,
* (will be added soon), so the clock framework
* disables this source. But some of the clocks
* initialized by boot loaders uses this source. So we
* need to keep this clock ON. Add the
* CLK_IGNORE_UNUSED flag so the clock will not be
* disabled. Once the consumer in kernel is added, we
* can get rid of this flag.
*/
.flags = CLK_IGNORE_UNUSED,
},
},
};
static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x22000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gpll4",
.parent_hws = (const struct clk_hw *[]) {
&gpll4_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct parent_map gcc_parent_map_xo[] = {
{ P_XO, 0 },
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_div2.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL4_OUT_MAIN, 2 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
{ P_SLEEP_CLK, 6 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_div2.hw },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_XO, 0 },
{ P_GPLL4_OUT_MAIN, 1 },
{ P_GPLL0_OUT_AUX, 2 },
{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
};
static const struct clk_parent_data gcc_parent_data_4[] = {
{ .index = DT_XO },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_div2.hw },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_AUX, 2 },
{ P_SLEEP_CLK, 6 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0.clkr.hw },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL2_OUT_AUX, 2 },
{ P_GPLL4_OUT_AUX, 3 },
{ P_SLEEP_CLK, 6 },
};
static const struct clk_parent_data gcc_parent_data_6[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_parent_map_7[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL2_OUT_AUX, 2 },
};
static const struct clk_parent_data gcc_parent_data_7[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL2_OUT_MAIN, 2 },
{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
};
static const struct clk_parent_data gcc_parent_data_8[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll0_div2.hw },
};
static const struct parent_map gcc_parent_map_9[] = {
{ P_SLEEP_CLK, 6 },
};
static const struct clk_parent_data gcc_parent_data_9[] = {
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_parent_map_10[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL4_OUT_MAIN, 2 },
{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 3 },
};
static const struct clk_parent_data gcc_parent_data_10[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0_div2.hw },
};
static const struct parent_map gcc_parent_map_11[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_AUX, 2 },
{ P_SLEEP_CLK, 6 },
};
static const struct clk_parent_data gcc_parent_data_11[] = {
{ .index = DT_XO },
{ .hw = &gpll0.clkr.hw },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_parent_map_12[] = {
{ P_XO, 0 },
{ P_GPLL4_OUT_AUX, 1 },
{ P_GPLL0_OUT_MAIN, 3 },
{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
};
static const struct clk_parent_data gcc_parent_data_12[] = {
{ .index = DT_XO },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_div2.hw },
};
static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
{ }
};
static struct clk_rcg2 gcc_adss_pwm_clk_src = {
.cmd_rcgr = 0x1c004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_adss_pwm_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_adss_pwm_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_apss_axi_clk_src[] = {
F(480000000, P_GPLL4_OUT_AUX, 2.5, 0, 0),
F(533333333, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
{ }
};
static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = {
F(960000, P_XO, 1, 1, 25),
F(4800000, P_XO, 5, 0, 0),
F(9600000, P_XO, 2.5, 0, 0),
F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
F(24000000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
{ }
};
static struct clk_rcg2 gcc_blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x2004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x3004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x4004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_blsp1_uart1_apps_clk_src[] = {
F(3686400, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 144, 15625),
F(7372800, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 288, 15625),
F(14745600, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 576, 15625),
F(24000000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),
F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),
F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x202c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_uart1_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x302c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_uart2_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_uart3_apps_clk_src = {
.cmd_rcgr = 0x402c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_uart3_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x8004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x9004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_lpass_sway_clk_src[] = {
F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 gcc_lpass_sway_clk_src = {
.cmd_rcgr = 0x27004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_lpass_sway_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_lpass_sway_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_nss_ts_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_nss_ts_clk_src = {
.cmd_rcgr = 0x17088,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo,
.freq_tbl = ftbl_gcc_nss_ts_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_nss_ts_clk_src",
.parent_data = &gcc_parent_data_xo,
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie3x1_0_axi_clk_src[] = {
F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie3x1_0_axi_clk_src = {
.cmd_rcgr = 0x29018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_0_axi_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_pcie3x1_0_rchg_clk_src = {
.cmd_rcgr = 0x2907c,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_adss_pwm_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_0_rchg_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_pcie3x1_0_rchg_clk = {
.halt_reg = 0x2907c,
.clkr = {
.enable_reg = 0x2907c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pcie3x1_0_rchg_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_pcie3x1_0_rchg_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_rcg2 gcc_pcie3x1_1_axi_clk_src = {
.cmd_rcgr = 0x2a004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_1_axi_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_pcie3x1_1_rchg_clk_src = {
.cmd_rcgr = 0x2a078,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_adss_pwm_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_1_rchg_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_pcie3x1_1_rchg_clk = {
.halt_reg = 0x2a078,
.clkr = {
.enable_reg = 0x2a078,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pcie3x1_1_rchg_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_pcie3x1_1_rchg_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_pcie3x2_axi_m_clk_src[] = {
F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie3x2_axi_m_clk_src = {
.cmd_rcgr = 0x28018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie3x2_axi_m_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x2_axi_m_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_pcie3x2_axi_s_clk_src = {
.cmd_rcgr = 0x28084,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x2_axi_s_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_pcie3x2_rchg_clk_src = {
.cmd_rcgr = 0x28078,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_adss_pwm_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x2_rchg_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_pcie3x2_rchg_clk = {
.halt_reg = 0x28078,
.clkr = {
.enable_reg = 0x28078,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data) {
.name = "gcc_pcie3x2_rchg_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_pcie3x2_rchg_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] = {
F(2000000, P_XO, 12, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_aux_clk_src = {
.cmd_rcgr = 0x28004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_pcie_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_aux_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_phy_mux gcc_pcie3x2_pipe_clk_src = {
.reg = 0x28064,
.clkr = {
.hw.init = &(struct clk_init_data) {
.name = "gcc_pcie3x2_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
.index = DT_PCIE_2LANE_PHY_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = {
.reg = 0x29064,
.clkr = {
.hw.init = &(struct clk_init_data) {
.name = "gcc_pcie3x1_0_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
.index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_phy_mux gcc_pcie3x1_1_pipe_clk_src = {
.reg = 0x2a064,
.clkr = {
.hw.init = &(struct clk_init_data) {
.name = "gcc_pcie3x1_1_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
.index = DT_PCIE_2LANE_PHY_PIPE_CLK_X1,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src = {
.cmd_rcgr = 0x31004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcnoc_bfdcd_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcnoc_bfdcd_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_q6_axim_clk_src = {
.cmd_rcgr = 0x25004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_apss_axi_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_q6_axim_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_qdss_at_clk_src[] = {
F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_qdss_at_clk_src = {
.cmd_rcgr = 0x2d004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_qdss_at_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_at_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_qdss_tsctr_clk_src[] = {
F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_qdss_tsctr_clk_src = {
.cmd_rcgr = 0x2d01c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_qdss_tsctr_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_tsctr_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_fixed_factor gcc_qdss_tsctr_div2_clk_src = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data) {
.name = "gcc_qdss_tsctr_div2_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_qdss_tsctr_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_fixed_factor gcc_qdss_tsctr_div3_clk_src = {
.mult = 1,
.div = 3,
.hw.init = &(struct clk_init_data) {
.name = "gcc_qdss_tsctr_div3_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_qdss_tsctr_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_fixed_factor gcc_qdss_tsctr_div4_clk_src = {
.mult = 1,
.div = 4,
.hw.init = &(struct clk_init_data) {
.name = "gcc_qdss_tsctr_div4_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_qdss_tsctr_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_fixed_factor gcc_qdss_tsctr_div8_clk_src = {
.mult = 1,
.div = 8,
.hw.init = &(struct clk_init_data) {
.name = "gcc_qdss_tsctr_div8_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_qdss_tsctr_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_fixed_factor gcc_qdss_tsctr_div16_clk_src = {
.mult = 1,
.div = 16,
.hw.init = &(struct clk_init_data) {
.name = "gcc_qdss_tsctr_div16_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_qdss_tsctr_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static const struct freq_tbl ftbl_gcc_qpic_io_macro_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_qpic_io_macro_clk_src = {
.cmd_rcgr = 0x32004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_qpic_io_macro_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_qpic_io_macro_clk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
F(143713, P_XO, 1, 1, 167),
F(400000, P_XO, 1, 1, 60),
F(24000000, P_XO, 1, 0, 0),
F(48000000, P_GPLL2_OUT_MAIN, 12, 1, 2),
F(96000000, P_GPLL2_OUT_MAIN, 12, 0, 0),
F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(192000000, P_GPLL2_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.cmd_rcgr = 0x33004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc1_apps_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sleep_clk_src[] = {
F(32000, P_SLEEP_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sleep_clk_src = {
.cmd_rcgr = 0x3400c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_9,
.freq_tbl = ftbl_gcc_sleep_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_sleep_clk_src",
.parent_data = gcc_parent_data_9,
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_system_noc_bfdcd_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = {
.cmd_rcgr = 0x2e004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_10,
.freq_tbl = ftbl_gcc_system_noc_bfdcd_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_system_noc_bfdcd_clk_src",
.parent_data = gcc_parent_data_10,
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
.ops = &clk_rcg2_ops,
},
};
static struct clk_fixed_factor gcc_system_noc_bfdcd_div2_clk_src = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data) {
.name = "gcc_system_noc_bfdcd_div2_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_system_noc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_rcg2 gcc_uniphy_sys_clk_src = {
.cmd_rcgr = 0x16004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo,
.freq_tbl = ftbl_gcc_nss_ts_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_uniphy_sys_clk_src",
.parent_data = &gcc_parent_data_xo,
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb0_aux_clk_src = {
.cmd_rcgr = 0x2c018,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_11,
.freq_tbl = ftbl_gcc_pcie_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_aux_clk_src",
.parent_data = gcc_parent_data_11,
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb0_lfps_clk_src[] = {
F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
{ }
};
static struct clk_rcg2 gcc_usb0_lfps_clk_src = {
.cmd_rcgr = 0x2c07c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_usb0_lfps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_lfps_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb0_master_clk_src = {
.cmd_rcgr = 0x2c004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] = {
F(60000000, P_GPLL4_OUT_AUX, 10, 1, 2),
{ }
};
static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = {
.cmd_rcgr = 0x2c02c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_12,
.freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_mock_utmi_clk_src",
.parent_data = gcc_parent_data_12,
.num_parents = ARRAY_SIZE(gcc_parent_data_12),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = {
.reg = 0x2c074,
.clkr = {
.hw.init = &(struct clk_init_data) {
.name = "gcc_usb0_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
.index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_rcg2 gcc_wcss_ahb_clk_src = {
.cmd_rcgr = 0x25030,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_lpass_sway_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_wcss_ahb_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_xo_clk_src = {
.cmd_rcgr = 0x34004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo,
.freq_tbl = ftbl_gcc_nss_ts_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_xo_clk_src",
.parent_data = &gcc_parent_data_xo,
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
};
static struct clk_fixed_factor gcc_xo_div4_clk_src = {
.mult = 1,
.div = 4,
.hw.init = &(struct clk_init_data) {
.name = "gcc_xo_div4_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_xo_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap_div gcc_qdss_dap_div_clk_src = {
.reg = 0x2d028,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_dap_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qdss_tsctr_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_usb0_mock_utmi_div_clk_src = {
.reg = 0x2c040,
.shift = 0,
.width = 2,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_mock_utmi_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb0_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gcc_adss_pwm_clk = {
.halt_reg = 0x1c00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1c00c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_adss_pwm_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_adss_pwm_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ahb_clk = {
.halt_reg = 0x34024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x34024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x1008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xb004,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x2024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x2020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x3024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x3020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x4024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x4020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_sleep_clk = {
.halt_reg = 0x1010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xb004,
.enable_mask = BIT(5),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_sleep_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x2040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x3040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart3_apps_clk = {
.halt_reg = 0x4054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4054,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_blsp1_uart3_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_uart3_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce_ahb_clk = {
.halt_reg = 0x25074,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x25074,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ce_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_system_noc_bfdcd_div2_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce_axi_clk = {
.halt_reg = 0x25068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x25068,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ce_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce_pcnoc_ahb_clk = {
.halt_reg = 0x25070,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x25070,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ce_pcnoc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
.halt_reg = 0x3a004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3a004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cmn_12gpll_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cmn_12gpll_apu_clk = {
.halt_reg = 0x3a00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3a00c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cmn_12gpll_apu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cmn_12gpll_sys_clk = {
.halt_reg = 0x3a008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3a008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cmn_12gpll_sys_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_uniphy_sys_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x8018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x9018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_lpass_core_axim_clk = {
.halt_reg = 0x27018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x27018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_lpass_core_axim_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_lpass_sway_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_lpass_sway_clk = {
.halt_reg = 0x27014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x27014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_lpass_sway_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_lpass_sway_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdio_ahb_clk = {
.halt_reg = 0x12004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_mdio_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdio_slave_ahb_clk = {
.halt_reg = 0x1200c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1200c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_mdio_slave_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_ts_clk = {
.halt_reg = 0x17018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x17018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nss_ts_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_nss_ts_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nsscc_clk = {
.halt_reg = 0x17034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nsscc_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nsscfg_clk = {
.halt_reg = 0x1702c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1702c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nsscfg_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_atb_clk = {
.halt_reg = 0x17014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nssnoc_atb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qdss_at_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_nsscc_clk = {
.halt_reg = 0x17030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nssnoc_nsscc_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
.halt_reg = 0x1701c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1701c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nssnoc_qosgen_ref_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_xo_div4_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_snoc_1_clk = {
.halt_reg = 0x1707c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1707c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nssnoc_snoc_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_snoc_clk = {
.halt_reg = 0x17028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nssnoc_snoc_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
.halt_reg = 0x17020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nssnoc_timeout_ref_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_xo_div4_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_xo_dcd_clk = {
.halt_reg = 0x17074,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17074,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nssnoc_xo_dcd_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3x1_0_ahb_clk = {
.halt_reg = 0x29030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x29030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_0_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3x1_0_aux_clk = {
.halt_reg = 0x29070,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x29070,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_0_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3x1_0_axi_m_clk = {
.halt_reg = 0x29038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x29038,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_0_axi_m_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie3x1_0_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3x1_0_axi_s_bridge_clk = {
.halt_reg = 0x29048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x29048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_0_axi_s_bridge_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie3x1_0_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3x1_0_axi_s_clk = {
.halt_reg = 0x29040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x29040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_0_axi_s_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie3x1_0_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3x1_0_pipe_clk = {
.halt_reg = 0x29068,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x29068,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_0_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie3x1_0_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3x1_1_ahb_clk = {
.halt_reg = 0x2a00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2a00c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_1_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3x1_1_aux_clk = {
.halt_reg = 0x2a070,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2a070,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_1_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3x1_1_axi_m_clk = {
.halt_reg = 0x2a014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2a014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_1_axi_m_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie3x1_1_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3x1_1_axi_s_bridge_clk = {
.halt_reg = 0x2a024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2a024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_1_axi_s_bridge_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie3x1_1_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3x1_1_axi_s_clk = {
.halt_reg = 0x2a01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2a01c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_1_axi_s_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie3x1_1_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3x1_1_pipe_clk = {
.halt_reg = 0x2a068,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x2a068,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_1_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie3x1_1_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3x1_phy_ahb_clk = {
.halt_reg = 0x29078,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x29078,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_phy_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3x2_ahb_clk = {
.halt_reg = 0x28030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x28030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x2_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3x2_aux_clk = {
.halt_reg = 0x28070,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x28070,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x2_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3x2_axi_m_clk = {
.halt_reg = 0x28038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x28038,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x2_axi_m_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie3x2_axi_m_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3x2_axi_s_bridge_clk = {
.halt_reg = 0x28048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x28048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x2_axi_s_bridge_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie3x2_axi_s_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3x2_axi_s_clk = {
.halt_reg = 0x28040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x28040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x2_axi_s_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie3x2_axi_s_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3x2_phy_ahb_clk = {
.halt_reg = 0x28080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x28080,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x2_phy_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie3x2_pipe_clk = {
.halt_reg = 0x28068,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x28068,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x2_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie3x2_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcnoc_at_clk = {
.halt_reg = 0x31024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x31024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcnoc_at_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qdss_at_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcnoc_lpass_clk = {
.halt_reg = 0x31020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x31020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcnoc_lpass_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_lpass_sway_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x13024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xb004,
.enable_mask = BIT(10),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_prng_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_q6_ahb_clk = {
.halt_reg = 0x25014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x25014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_q6_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_wcss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_q6_ahb_s_clk = {
.halt_reg = 0x25018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x25018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_q6_ahb_s_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_wcss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_q6_axim_clk = {
.halt_reg = 0x2500c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x2500c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_q6_axim_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_q6_axim_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_q6_axis_clk = {
.halt_reg = 0x25010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x25010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_q6_axis_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_q6_tsctr_1to2_clk = {
.halt_reg = 0x25020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x25020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_q6_tsctr_1to2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qdss_tsctr_div2_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_q6ss_atbm_clk = {
.halt_reg = 0x2501c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x2501c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_q6ss_atbm_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qdss_at_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_q6ss_pclkdbg_clk = {
.halt_reg = 0x25024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x25024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_q6ss_pclkdbg_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qdss_dap_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_q6ss_trig_clk = {
.halt_reg = 0x250a0,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x250a0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_q6ss_trig_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qdss_dap_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_at_clk = {
.halt_reg = 0x2d038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x2d038,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_at_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qdss_at_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_cfg_ahb_clk = {
.halt_reg = 0x2d06c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x2d06c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_dap_ahb_clk = {
.halt_reg = 0x2d068,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x2d068,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_dap_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_dap_clk = {
.halt_reg = 0x2d05c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xb004,
.enable_mask = BIT(2),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_dap_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qdss_dap_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_etr_usb_clk = {
.halt_reg = 0x2d064,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x2d064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_etr_usb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
.mult = 1,
.div = 6,
.hw.init = &(struct clk_init_data) {
.name = "gcc_eud_at_div_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_qdss_at_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_branch gcc_qdss_eud_at_clk = {
.halt_reg = 0x2d070,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x2d070,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_eud_at_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_eud_at_div_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qpic_ahb_clk = {
.halt_reg = 0x32010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x32010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qpic_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qpic_clk = {
.halt_reg = 0x32014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x32014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qpic_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qpic_io_macro_clk = {
.halt_reg = 0x3200c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3200c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qpic_io_macro_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qpic_io_macro_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qpic_sleep_clk = {
.halt_reg = 0x3201c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3201c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qpic_sleep_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x33034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x33034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc1_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x3302c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3302c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_lpass_cfg_clk = {
.halt_reg = 0x2e028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2e028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_snoc_lpass_cfg_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_lpass_sway_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_nssnoc_1_clk = {
.halt_reg = 0x17090,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17090,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_snoc_nssnoc_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_nssnoc_clk = {
.halt_reg = 0x17084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17084,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_snoc_nssnoc_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_pcie3_1lane_1_m_clk = {
.halt_reg = 0x2e050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2e050,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_snoc_pcie3_1lane_1_m_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie3x1_1_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_pcie3_1lane_1_s_clk = {
.halt_reg = 0x2e0ac,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2e0ac,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_snoc_pcie3_1lane_1_s_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie3x1_1_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_pcie3_1lane_m_clk = {
.halt_reg = 0x2e080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2e080,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_snoc_pcie3_1lane_m_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie3x1_0_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_pcie3_1lane_s_clk = {
.halt_reg = 0x2e04c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2e04c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_snoc_pcie3_1lane_s_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie3x1_0_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_pcie3_2lane_m_clk = {
.halt_reg = 0x2e07c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2e07c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_snoc_pcie3_2lane_m_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie3x2_axi_m_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = {
.halt_reg = 0x2e048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2e048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_snoc_pcie3_2lane_s_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie3x2_axi_s_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_usb_clk = {
.halt_reg = 0x2e058,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x2e058,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_snoc_usb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb0_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_at_clk = {
.halt_reg = 0x2e038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x2e038,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sys_noc_at_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qdss_at_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
.halt_reg = 0x2e030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2e030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sys_noc_wcss_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_wcss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_ahb_clk = {
.halt_reg = 0x16010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_uniphy0_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_sys_clk = {
.halt_reg = 0x1600c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1600c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_uniphy0_sys_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_uniphy_sys_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy1_ahb_clk = {
.halt_reg = 0x1601c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1601c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_uniphy1_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy1_sys_clk = {
.halt_reg = 0x16018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_uniphy1_sys_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_uniphy_sys_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_aux_clk = {
.halt_reg = 0x2c050,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x2c050,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_eud_at_clk = {
.halt_reg = 0x30004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x30004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_eud_at_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_eud_at_div_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_lfps_clk = {
.halt_reg = 0x2c090,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x2c090,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_lfps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb0_lfps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_master_clk = {
.halt_reg = 0x2c048,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x2c048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_master_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb0_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_mock_utmi_clk = {
.halt_reg = 0x2c054,
.clkr = {
.enable_reg = 0x2c054,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb0_mock_utmi_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
.halt_reg = 0x2c05c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x2c05c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_phy_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_pipe_clk = {
.halt_reg = 0x2c078,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x2c078,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb0_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_sleep_clk = {
.halt_reg = 0x2c058,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x2c058,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_sleep_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_axim_clk = {
.halt_reg = 0x2505c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2505c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_wcss_axim_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_axis_clk = {
.halt_reg = 0x25060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x25060,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_wcss_axis_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = {
.halt_reg = 0x25048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x25048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_wcss_dbg_ifc_apb_bdg_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qdss_dap_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
.halt_reg = 0x25038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x25038,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_wcss_dbg_ifc_apb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qdss_dap_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = {
.halt_reg = 0x2504c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2504c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_wcss_dbg_ifc_atb_bdg_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qdss_at_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
.halt_reg = 0x2503c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2503c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_wcss_dbg_ifc_atb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qdss_at_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = {
.halt_reg = 0x25050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x25050,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_wcss_dbg_ifc_nts_bdg_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qdss_tsctr_div2_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
.halt_reg = 0x25040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x25040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_wcss_dbg_ifc_nts_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qdss_tsctr_div2_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_ecahb_clk = {
.halt_reg = 0x25058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x25058,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_wcss_ecahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_wcss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_mst_async_bdg_clk = {
.halt_reg = 0x2e0b0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2e0b0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_wcss_mst_async_bdg_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_slv_async_bdg_clk = {
.halt_reg = 0x2e0b4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2e0b4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_wcss_slv_async_bdg_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_xo_clk = {
.halt_reg = 0x34018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x34018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_xo_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_xo_div4_clk = {
.halt_reg = 0x3401c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3401c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_xo_div4_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_xo_div4_clk_src.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_im_sleep_clk = {
.halt_reg = 0x34020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x34020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_im_sleep_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {
.halt_reg = 0x17080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17080,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_nssnoc_pcnoc_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap_div gcc_snoc_qosgen_extref_div_clk_src = {
.reg = 0x2e010,
.shift = 0,
.width = 2,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_snoc_qosgen_extref_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap *gcc_ipq5332_clocks[] = {
[GPLL0_MAIN] = &gpll0_main.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL2_MAIN] = &gpll2_main.clkr,
[GPLL2] = &gpll2.clkr,
[GPLL4_MAIN] = &gpll4_main.clkr,
[GPLL4] = &gpll4.clkr,
[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
[GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr,
[GCC_AHB_CLK] = &gcc_ahb_clk.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup1_spi_apps_clk_src.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup2_spi_apps_clk_src.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup3_spi_apps_clk_src.clkr,
[GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK_SRC] = &gcc_blsp1_uart1_apps_clk_src.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK_SRC] = &gcc_blsp1_uart2_apps_clk_src.clkr,
[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
[GCC_BLSP1_UART3_APPS_CLK_SRC] = &gcc_blsp1_uart3_apps_clk_src.clkr,
[GCC_CE_AHB_CLK] = &gcc_ce_ahb_clk.clkr,
[GCC_CE_AXI_CLK] = &gcc_ce_axi_clk.clkr,
[GCC_CE_PCNOC_AHB_CLK] = &gcc_ce_pcnoc_ahb_clk.clkr,
[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
[GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr,
[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
[GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
[GCC_LPASS_SWAY_CLK_SRC] = &gcc_lpass_sway_clk_src.clkr,
[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
[GCC_MDIO_SLAVE_AHB_CLK] = &gcc_mdio_slave_ahb_clk.clkr,
[GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
[GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr,
[GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
[GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
[GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
[GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
[GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
[GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
[GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,
[GCC_PCIE3X1_0_AHB_CLK] = &gcc_pcie3x1_0_ahb_clk.clkr,
[GCC_PCIE3X1_0_AUX_CLK] = &gcc_pcie3x1_0_aux_clk.clkr,
[GCC_PCIE3X1_0_AXI_CLK_SRC] = &gcc_pcie3x1_0_axi_clk_src.clkr,
[GCC_PCIE3X1_0_AXI_M_CLK] = &gcc_pcie3x1_0_axi_m_clk.clkr,
[GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK] = &gcc_pcie3x1_0_axi_s_bridge_clk.clkr,
[GCC_PCIE3X1_0_AXI_S_CLK] = &gcc_pcie3x1_0_axi_s_clk.clkr,
[GCC_PCIE3X1_0_PIPE_CLK] = &gcc_pcie3x1_0_pipe_clk.clkr,
[GCC_PCIE3X1_0_RCHG_CLK] = &gcc_pcie3x1_0_rchg_clk.clkr,
[GCC_PCIE3X1_0_RCHG_CLK_SRC] = &gcc_pcie3x1_0_rchg_clk_src.clkr,
[GCC_PCIE3X1_1_AHB_CLK] = &gcc_pcie3x1_1_ahb_clk.clkr,
[GCC_PCIE3X1_1_AUX_CLK] = &gcc_pcie3x1_1_aux_clk.clkr,
[GCC_PCIE3X1_1_AXI_CLK_SRC] = &gcc_pcie3x1_1_axi_clk_src.clkr,
[GCC_PCIE3X1_1_AXI_M_CLK] = &gcc_pcie3x1_1_axi_m_clk.clkr,
[GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK] = &gcc_pcie3x1_1_axi_s_bridge_clk.clkr,
[GCC_PCIE3X1_1_AXI_S_CLK] = &gcc_pcie3x1_1_axi_s_clk.clkr,
[GCC_PCIE3X1_1_PIPE_CLK] = &gcc_pcie3x1_1_pipe_clk.clkr,
[GCC_PCIE3X1_1_RCHG_CLK] = &gcc_pcie3x1_1_rchg_clk.clkr,
[GCC_PCIE3X1_1_RCHG_CLK_SRC] = &gcc_pcie3x1_1_rchg_clk_src.clkr,
[GCC_PCIE3X1_PHY_AHB_CLK] = &gcc_pcie3x1_phy_ahb_clk.clkr,
[GCC_PCIE3X2_AHB_CLK] = &gcc_pcie3x2_ahb_clk.clkr,
[GCC_PCIE3X2_AUX_CLK] = &gcc_pcie3x2_aux_clk.clkr,
[GCC_PCIE3X2_AXI_M_CLK] = &gcc_pcie3x2_axi_m_clk.clkr,
[GCC_PCIE3X2_AXI_M_CLK_SRC] = &gcc_pcie3x2_axi_m_clk_src.clkr,
[GCC_PCIE3X2_AXI_S_BRIDGE_CLK] = &gcc_pcie3x2_axi_s_bridge_clk.clkr,
[GCC_PCIE3X2_AXI_S_CLK] = &gcc_pcie3x2_axi_s_clk.clkr,
[GCC_PCIE3X2_AXI_S_CLK_SRC] = &gcc_pcie3x2_axi_s_clk_src.clkr,
[GCC_PCIE3X2_PHY_AHB_CLK] = &gcc_pcie3x2_phy_ahb_clk.clkr,
[GCC_PCIE3X2_PIPE_CLK] = &gcc_pcie3x2_pipe_clk.clkr,
[GCC_PCIE3X2_RCHG_CLK] = &gcc_pcie3x2_rchg_clk.clkr,
[GCC_PCIE3X2_RCHG_CLK_SRC] = &gcc_pcie3x2_rchg_clk_src.clkr,
[GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr,
[GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr,
[GCC_PCNOC_BFDCD_CLK_SRC] = &gcc_pcnoc_bfdcd_clk_src.clkr,
[GCC_PCNOC_LPASS_CLK] = &gcc_pcnoc_lpass_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
[GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
[GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
[GCC_Q6_AXIM_CLK_SRC] = &gcc_q6_axim_clk_src.clkr,
[GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr,
[GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
[GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
[GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
[GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
[GCC_QDSS_AT_CLK_SRC] = &gcc_qdss_at_clk_src.clkr,
[GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
[GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
[GCC_QDSS_DAP_DIV_CLK_SRC] = &gcc_qdss_dap_div_clk_src.clkr,
[GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
[GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
[GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
[GCC_QPIC_IO_MACRO_CLK_SRC] = &gcc_qpic_io_macro_clk_src.clkr,
[GCC_QPIC_SLEEP_CLK] = &gcc_qpic_sleep_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
[GCC_SNOC_LPASS_CFG_CLK] = &gcc_snoc_lpass_cfg_clk.clkr,
[GCC_SNOC_NSSNOC_1_CLK] = &gcc_snoc_nssnoc_1_clk.clkr,
[GCC_SNOC_NSSNOC_CLK] = &gcc_snoc_nssnoc_clk.clkr,
[GCC_SNOC_PCIE3_1LANE_1_M_CLK] = &gcc_snoc_pcie3_1lane_1_m_clk.clkr,
[GCC_SNOC_PCIE3_1LANE_1_S_CLK] = &gcc_snoc_pcie3_1lane_1_s_clk.clkr,
[GCC_SNOC_PCIE3_1LANE_M_CLK] = &gcc_snoc_pcie3_1lane_m_clk.clkr,
[GCC_SNOC_PCIE3_1LANE_S_CLK] = &gcc_snoc_pcie3_1lane_s_clk.clkr,
[GCC_SNOC_PCIE3_2LANE_M_CLK] = &gcc_snoc_pcie3_2lane_m_clk.clkr,
[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
[GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr,
[GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr,
[GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
[GCC_SYSTEM_NOC_BFDCD_CLK_SRC] = &gcc_system_noc_bfdcd_clk_src.clkr,
[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
[GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
[GCC_UNIPHY_SYS_CLK_SRC] = &gcc_uniphy_sys_clk_src.clkr,
[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
[GCC_USB0_AUX_CLK_SRC] = &gcc_usb0_aux_clk_src.clkr,
[GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
[GCC_USB0_LFPS_CLK] = &gcc_usb0_lfps_clk.clkr,
[GCC_USB0_LFPS_CLK_SRC] = &gcc_usb0_lfps_clk_src.clkr,
[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
[GCC_USB0_MASTER_CLK_SRC] = &gcc_usb0_master_clk_src.clkr,
[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
[GCC_USB0_MOCK_UTMI_CLK_SRC] = &gcc_usb0_mock_utmi_clk_src.clkr,
[GCC_USB0_MOCK_UTMI_DIV_CLK_SRC] = &gcc_usb0_mock_utmi_div_clk_src.clkr,
[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
[GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
[GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
[GCC_WCSS_AHB_CLK_SRC] = &gcc_wcss_ahb_clk_src.clkr,
[GCC_WCSS_AXIM_CLK] = &gcc_wcss_axim_clk.clkr,
[GCC_WCSS_AXIS_CLK] = &gcc_wcss_axis_clk.clkr,
[GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr,
[GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
[GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr,
[GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
[GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr,
[GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
[GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
[GCC_WCSS_MST_ASYNC_BDG_CLK] = &gcc_wcss_mst_async_bdg_clk.clkr,
[GCC_WCSS_SLV_ASYNC_BDG_CLK] = &gcc_wcss_slv_async_bdg_clk.clkr,
[GCC_XO_CLK] = &gcc_xo_clk.clkr,
[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
[GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
[GCC_IM_SLEEP_CLK] = &gcc_im_sleep_clk.clkr,
[GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
[GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC] = &gcc_snoc_qosgen_extref_div_clk_src.clkr,
[GCC_PCIE3X2_PIPE_CLK_SRC] = &gcc_pcie3x2_pipe_clk_src.clkr,
[GCC_PCIE3X1_0_PIPE_CLK_SRC] = &gcc_pcie3x1_0_pipe_clk_src.clkr,
[GCC_PCIE3X1_1_PIPE_CLK_SRC] = &gcc_pcie3x1_1_pipe_clk_src.clkr,
[GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr,
};
static const struct qcom_reset_map gcc_ipq5332_resets[] = {
[GCC_ADSS_BCR] = { 0x1c000 },
[GCC_ADSS_PWM_CLK_ARES] = { 0x1c00c, 2 },
[GCC_AHB_CLK_ARES] = { 0x34024, 2 },
[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000 },
[GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES] = { 0x3800c, 2 },
[GCC_APSS_AHB_CLK_ARES] = { 0x24018, 2 },
[GCC_APSS_AXI_CLK_ARES] = { 0x2401c, 2 },
[GCC_BLSP1_AHB_CLK_ARES] = { 0x1008, 2 },
[GCC_BLSP1_BCR] = { 0x1000 },
[GCC_BLSP1_QUP1_BCR] = { 0x2000 },
[GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES] = { 0x2024, 2 },
[GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES] = { 0x2020, 2 },
[GCC_BLSP1_QUP2_BCR] = { 0x3000 },
[GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES] = { 0x3024, 2 },
[GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES] = { 0x3020, 2 },
[GCC_BLSP1_QUP3_BCR] = { 0x4000 },
[GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES] = { 0x4024, 2 },
[GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES] = { 0x4020, 2 },
[GCC_BLSP1_SLEEP_CLK_ARES] = { 0x1010, 2 },
[GCC_BLSP1_UART1_APPS_CLK_ARES] = { 0x2040, 2 },
[GCC_BLSP1_UART1_BCR] = { 0x2028 },
[GCC_BLSP1_UART2_APPS_CLK_ARES] = { 0x3040, 2 },
[GCC_BLSP1_UART2_BCR] = { 0x3028 },
[GCC_BLSP1_UART3_APPS_CLK_ARES] = { 0x4054, 2 },
[GCC_BLSP1_UART3_BCR] = { 0x4028 },
[GCC_CE_BCR] = { 0x18008 },
[GCC_CMN_BLK_BCR] = { 0x3a000 },
[GCC_CMN_LDO0_BCR] = { 0x1d000 },
[GCC_CMN_LDO1_BCR] = { 0x1d008 },
[GCC_DCC_BCR] = { 0x35000 },
[GCC_GP1_CLK_ARES] = { 0x8018, 2 },
[GCC_GP2_CLK_ARES] = { 0x9018, 2 },
[GCC_LPASS_BCR] = { 0x27000 },
[GCC_LPASS_CORE_AXIM_CLK_ARES] = { 0x27018, 2 },
[GCC_LPASS_SWAY_CLK_ARES] = { 0x27014, 2 },
[GCC_MDIOM_BCR] = { 0x12000 },
[GCC_MDIOS_BCR] = { 0x12008 },
[GCC_NSS_BCR] = { 0x17000 },
[GCC_NSS_TS_CLK_ARES] = { 0x17018, 2 },
[GCC_NSSCC_CLK_ARES] = { 0x17034, 2 },
[GCC_NSSCFG_CLK_ARES] = { 0x1702c, 2 },
[GCC_NSSNOC_ATB_CLK_ARES] = { 0x17014, 2 },
[GCC_NSSNOC_NSSCC_CLK_ARES] = { 0x17030, 2 },
[GCC_NSSNOC_QOSGEN_REF_CLK_ARES] = { 0x1701c, 2 },
[GCC_NSSNOC_SNOC_1_CLK_ARES] = { 0x1707c, 2 },
[GCC_NSSNOC_SNOC_CLK_ARES] = { 0x17028, 2 },
[GCC_NSSNOC_TIMEOUT_REF_CLK_ARES] = { 0x17020, 2 },
[GCC_NSSNOC_XO_DCD_CLK_ARES] = { 0x17074, 2 },
[GCC_PCIE3X1_0_AHB_CLK_ARES] = { 0x29030, 2 },
[GCC_PCIE3X1_0_AUX_CLK_ARES] = { 0x29070, 2 },
[GCC_PCIE3X1_0_AXI_M_CLK_ARES] = { 0x29038, 2 },
[GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES] = { 0x29048, 2 },
[GCC_PCIE3X1_0_AXI_S_CLK_ARES] = { 0x29040, 2 },
[GCC_PCIE3X1_0_BCR] = { 0x29000 },
[GCC_PCIE3X1_0_LINK_DOWN_BCR] = { 0x29054 },
[GCC_PCIE3X1_0_PHY_BCR] = { 0x29060 },
[GCC_PCIE3X1_0_PHY_PHY_BCR] = { 0x2905c },
[GCC_PCIE3X1_1_AHB_CLK_ARES] = { 0x2a00c, 2 },
[GCC_PCIE3X1_1_AUX_CLK_ARES] = { 0x2a070, 2 },
[GCC_PCIE3X1_1_AXI_M_CLK_ARES] = { 0x2a014, 2 },
[GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES] = { 0x2a024, 2 },
[GCC_PCIE3X1_1_AXI_S_CLK_ARES] = { 0x2a01c, 2 },
[GCC_PCIE3X1_1_BCR] = { 0x2a000 },
[GCC_PCIE3X1_1_LINK_DOWN_BCR] = { 0x2a028 },
[GCC_PCIE3X1_1_PHY_BCR] = { 0x2a030 },
[GCC_PCIE3X1_1_PHY_PHY_BCR] = { 0x2a02c },
[GCC_PCIE3X1_PHY_AHB_CLK_ARES] = { 0x29078, 2 },
[GCC_PCIE3X2_AHB_CLK_ARES] = { 0x28030, 2 },
[GCC_PCIE3X2_AUX_CLK_ARES] = { 0x28070, 2 },
[GCC_PCIE3X2_AXI_M_CLK_ARES] = { 0x28038, 2 },
[GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES] = { 0x28048, 2 },
[GCC_PCIE3X2_AXI_S_CLK_ARES] = { 0x28040, 2 },
[GCC_PCIE3X2_BCR] = { 0x28000 },
[GCC_PCIE3X2_LINK_DOWN_BCR] = { 0x28054 },
[GCC_PCIE3X2_PHY_AHB_CLK_ARES] = { 0x28080, 2 },
[GCC_PCIE3X2_PHY_BCR] = { 0x28060 },
[GCC_PCIE3X2PHY_PHY_BCR] = { 0x2805c },
[GCC_PCNOC_BCR] = { 0x31000 },
[GCC_PCNOC_LPASS_CLK_ARES] = { 0x31020, 2 },
[GCC_PRNG_AHB_CLK_ARES] = { 0x13024, 2 },
[GCC_PRNG_BCR] = { 0x13020 },
[GCC_Q6_AHB_CLK_ARES] = { 0x25014, 2 },
[GCC_Q6_AHB_S_CLK_ARES] = { 0x25018, 2 },
[GCC_Q6_AXIM_CLK_ARES] = { 0x2500c, 2 },
[GCC_Q6_AXIS_CLK_ARES] = { 0x25010, 2 },
[GCC_Q6_TSCTR_1TO2_CLK_ARES] = { 0x25020, 2 },
[GCC_Q6SS_ATBM_CLK_ARES] = { 0x2501c, 2 },
[GCC_Q6SS_PCLKDBG_CLK_ARES] = { 0x25024, 2 },
[GCC_Q6SS_TRIG_CLK_ARES] = { 0x250a0, 2 },
[GCC_QDSS_APB2JTAG_CLK_ARES] = { 0x2d060, 2 },
[GCC_QDSS_AT_CLK_ARES] = { 0x2d038, 2 },
[GCC_QDSS_BCR] = { 0x2d000 },
[GCC_QDSS_CFG_AHB_CLK_ARES] = { 0x2d06c, 2 },
[GCC_QDSS_DAP_AHB_CLK_ARES] = { 0x2d068, 2 },
[GCC_QDSS_DAP_CLK_ARES] = { 0x2d05c, 2 },
[GCC_QDSS_ETR_USB_CLK_ARES] = { 0x2d064, 2 },
[GCC_QDSS_EUD_AT_CLK_ARES] = { 0x2d070, 2 },
[GCC_QDSS_STM_CLK_ARES] = { 0x2d040, 2 },
[GCC_QDSS_TRACECLKIN_CLK_ARES] = { 0x2d044, 2 },
[GCC_QDSS_TS_CLK_ARES] = { 0x2d078, 2 },
[GCC_QDSS_TSCTR_DIV16_CLK_ARES] = { 0x2d058, 2 },
[GCC_QDSS_TSCTR_DIV2_CLK_ARES] = { 0x2d048, 2 },
[GCC_QDSS_TSCTR_DIV3_CLK_ARES] = { 0x2d04c, 2 },
[GCC_QDSS_TSCTR_DIV4_CLK_ARES] = { 0x2d050, 2 },
[GCC_QDSS_TSCTR_DIV8_CLK_ARES] = { 0x2d054, 2 },
[GCC_QPIC_AHB_CLK_ARES] = { 0x32010, 2 },
[GCC_QPIC_CLK_ARES] = { 0x32014, 2 },
[GCC_QPIC_BCR] = { 0x32000 },
[GCC_QPIC_IO_MACRO_CLK_ARES] = { 0x3200c, 2 },
[GCC_QPIC_SLEEP_CLK_ARES] = { 0x3201c, 2 },
[GCC_QUSB2_0_PHY_BCR] = { 0x2c068 },
[GCC_SDCC1_AHB_CLK_ARES] = { 0x33034, 2 },
[GCC_SDCC1_APPS_CLK_ARES] = { 0x3302c, 2 },
[GCC_SDCC_BCR] = { 0x33000 },
[GCC_SNOC_BCR] = { 0x2e000 },
[GCC_SNOC_LPASS_CFG_CLK_ARES] = { 0x2e028, 2 },
[GCC_SNOC_NSSNOC_1_CLK_ARES] = { 0x17090, 2 },
[GCC_SNOC_NSSNOC_CLK_ARES] = { 0x17084, 2 },
[GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES] = { 0x2e034, 2 },
[GCC_SYS_NOC_WCSS_AHB_CLK_ARES] = { 0x2e030, 2 },
[GCC_UNIPHY0_AHB_CLK_ARES] = { 0x16010, 2 },
[GCC_UNIPHY0_BCR] = { 0x16000 },
[GCC_UNIPHY0_SYS_CLK_ARES] = { 0x1600c, 2 },
[GCC_UNIPHY1_AHB_CLK_ARES] = { 0x1601c, 2 },
[GCC_UNIPHY1_BCR] = { 0x16014 },
[GCC_UNIPHY1_SYS_CLK_ARES] = { 0x16018, 2 },
[GCC_USB0_AUX_CLK_ARES] = { 0x2c050, 2 },
[GCC_USB0_EUD_AT_CLK_ARES] = { 0x30004, 2 },
[GCC_USB0_LFPS_CLK_ARES] = { 0x2c090, 2 },
[GCC_USB0_MASTER_CLK_ARES] = { 0x2c048, 2 },
[GCC_USB0_MOCK_UTMI_CLK_ARES] = { 0x2c054, 2 },
[GCC_USB0_PHY_BCR] = { 0x2c06c },
[GCC_USB0_PHY_CFG_AHB_CLK_ARES] = { 0x2c05c, 2 },
[GCC_USB0_SLEEP_CLK_ARES] = { 0x2c058, 2 },
[GCC_USB3PHY_0_PHY_BCR] = { 0x2c070 },
[GCC_USB_BCR] = { 0x2c000 },
[GCC_WCSS_AXIM_CLK_ARES] = { 0x2505c, 2 },
[GCC_WCSS_AXIS_CLK_ARES] = { 0x25060, 2 },
[GCC_WCSS_BCR] = { 0x18004 },
[GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES] = { 0x25048, 2 },
[GCC_WCSS_DBG_IFC_APB_CLK_ARES] = { 0x25038, 2 },
[GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES] = { 0x2504c, 2 },
[GCC_WCSS_DBG_IFC_ATB_CLK_ARES] = { 0x2503c, 2 },
[GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES] = { 0x25050, 2 },
[GCC_WCSS_DBG_IFC_NTS_CLK_ARES] = { 0x25040, 2 },
[GCC_WCSS_ECAHB_CLK_ARES] = { 0x25058, 2 },
[GCC_WCSS_MST_ASYNC_BDG_CLK_ARES] = { 0x2e0b0, 2 },
[GCC_WCSS_Q6_BCR] = { 0x18000 },
[GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES] = { 0x2e0b4, 2 },
[GCC_XO_CLK_ARES] = { 0x34018, 2 },
[GCC_XO_DIV4_CLK_ARES] = { 0x3401c, 2 },
[GCC_Q6SS_DBG_ARES] = { 0x25094 },
[GCC_WCSS_DBG_BDG_ARES] = { 0x25098, 0 },
[GCC_WCSS_DBG_ARES] = { 0x25098, 1 },
[GCC_WCSS_AXI_S_ARES] = { 0x25098, 2 },
[GCC_WCSS_AXI_M_ARES] = { 0x25098, 3 },
[GCC_WCSSAON_ARES] = { 0x2509C },
[GCC_PCIE3X2_PIPE_ARES] = { 0x28058, 0 },
[GCC_PCIE3X2_CORE_STICKY_ARES] = { 0x28058, 1 },
[GCC_PCIE3X2_AXI_S_STICKY_ARES] = { 0x28058, 2 },
[GCC_PCIE3X2_AXI_M_STICKY_ARES] = { 0x28058, 3 },
[GCC_PCIE3X1_0_PIPE_ARES] = { 0x29058, 0 },
[GCC_PCIE3X1_0_CORE_STICKY_ARES] = { 0x29058, 1 },
[GCC_PCIE3X1_0_AXI_S_STICKY_ARES] = { 0x29058, 2 },
[GCC_PCIE3X1_0_AXI_M_STICKY_ARES] = { 0x29058, 3 },
[GCC_PCIE3X1_1_PIPE_ARES] = { 0x2a058, 0 },
[GCC_PCIE3X1_1_CORE_STICKY_ARES] = { 0x2a058, 1 },
[GCC_PCIE3X1_1_AXI_S_STICKY_ARES] = { 0x2a058, 2 },
[GCC_PCIE3X1_1_AXI_M_STICKY_ARES] = { 0x2a058, 3 },
[GCC_IM_SLEEP_CLK_ARES] = { 0x34020, 2 },
[GCC_NSSNOC_PCNOC_1_CLK_ARES] = { 0x17080, 2 },
[GCC_UNIPHY0_XPCS_ARES] = { 0x16050 },
[GCC_UNIPHY1_XPCS_ARES] = { 0x16060 },
};
static const struct regmap_config gcc_ipq5332_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x3f024,
.fast_io = true,
};
static struct clk_hw *gcc_ipq5332_hws[] = {
&gpll0_div2.hw,
&gcc_xo_div4_clk_src.hw,
&gcc_system_noc_bfdcd_div2_clk_src.hw,
&gcc_qdss_tsctr_div2_clk_src.hw,
&gcc_qdss_tsctr_div3_clk_src.hw,
&gcc_qdss_tsctr_div4_clk_src.hw,
&gcc_qdss_tsctr_div8_clk_src.hw,
&gcc_qdss_tsctr_div16_clk_src.hw,
&gcc_eud_at_div_clk_src.hw,
};
static const struct qcom_cc_desc gcc_ipq5332_desc = {
.config = &gcc_ipq5332_regmap_config,
.clks = gcc_ipq5332_clocks,
.num_clks = ARRAY_SIZE(gcc_ipq5332_clocks),
.resets = gcc_ipq5332_resets,
.num_resets = ARRAY_SIZE(gcc_ipq5332_resets),
.clk_hws = gcc_ipq5332_hws,
.num_clk_hws = ARRAY_SIZE(gcc_ipq5332_hws),
};
static int gcc_ipq5332_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &gcc_ipq5332_desc);
}
static const struct of_device_id gcc_ipq5332_match_table[] = {
{ .compatible = "qcom,ipq5332-gcc" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_ipq5332_match_table);
static struct platform_driver gcc_ipq5332_driver = {
.probe = gcc_ipq5332_probe,
.driver = {
.name = "gcc-ipq5332",
.of_match_table = gcc_ipq5332_match_table,
},
};
static int __init gcc_ipq5332_init(void)
{
return platform_driver_register(&gcc_ipq5332_driver);
}
core_initcall(gcc_ipq5332_init);
static void __exit gcc_ipq5332_exit(void)
{
platform_driver_unregister(&gcc_ipq5332_driver);
}
module_exit(gcc_ipq5332_exit);
MODULE_DESCRIPTION("QTI GCC IPQ5332 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/gcc-ipq5332.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Qualcomm APCS clock controller driver
*
* Copyright (c) 2022, Linaro Limited
* Author: Dmitry Baryshkov <[email protected]>
*/
#include <linux/bits.h>
#include <linux/bitfield.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#define APCS_AUX_OFFSET 0x50
#define APCS_AUX_DIV_MASK GENMASK(17, 16)
#define APCS_AUX_DIV_2 0x1
static int qcom_apcs_msm8996_clk_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device *parent = dev->parent;
struct regmap *regmap;
struct clk_hw *hw;
unsigned int val;
int ret = -ENODEV;
regmap = dev_get_regmap(parent, NULL);
if (!regmap) {
dev_err(dev, "failed to get regmap: %d\n", ret);
return ret;
}
regmap_read(regmap, APCS_AUX_OFFSET, &val);
regmap_update_bits(regmap, APCS_AUX_OFFSET, APCS_AUX_DIV_MASK,
FIELD_PREP(APCS_AUX_DIV_MASK, APCS_AUX_DIV_2));
/*
* This clock is used during CPU cluster setup while setting up CPU PLLs.
* Add hardware mandated delay to make sure that the sys_apcs_aux clock
* is stable (after setting the divider) before continuing
* bootstrapping to keep CPUs from ending up in a weird state.
*/
udelay(5);
/*
* As this clocks is a parent of the CPU cluster clocks and is actually
* used as a parent during CPU clocks setup, we want for it to register
* as early as possible, without letting fw_devlink to delay probing of
* either of the drivers.
*
* The sys_apcs_aux is a child (divider) of gpll0, but we register it
* as a fixed rate clock instead to ease bootstrapping procedure. By
* doing this we make sure that CPU cluster clocks are able to be setup
* early during the boot process (as it is recommended by Qualcomm).
*/
hw = devm_clk_hw_register_fixed_rate(dev, "sys_apcs_aux", NULL, 0, 300000000);
if (IS_ERR(hw))
return PTR_ERR(hw);
return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
}
static struct platform_driver qcom_apcs_msm8996_clk_driver = {
.probe = qcom_apcs_msm8996_clk_probe,
.driver = {
.name = "qcom-apcs-msm8996-clk",
},
};
/* Register early enough to fix the clock to be used for other cores */
static int __init qcom_apcs_msm8996_clk_init(void)
{
return platform_driver_register(&qcom_apcs_msm8996_clk_driver);
}
postcore_initcall(qcom_apcs_msm8996_clk_init);
static void __exit qcom_apcs_msm8996_clk_exit(void)
{
platform_driver_unregister(&qcom_apcs_msm8996_clk_driver);
}
module_exit(qcom_apcs_msm8996_clk_exit);
MODULE_AUTHOR("Dmitry Baryshkov <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Qualcomm MSM8996 APCS clock driver");
| linux-master | drivers/clk/qcom/apcs-msm8996.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Danila Tikhonov <[email protected]>
* Copyright (c) 2023, David Wronek <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm7150-gcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_BI_TCXO_AO,
DT_SLEEP_CLK
};
enum {
P_BI_TCXO,
P_GPLL0_OUT_EVEN,
P_GPLL0_OUT_MAIN,
P_GPLL6_OUT_MAIN,
P_GPLL7_OUT_MAIN,
P_SLEEP_CLK,
};
static struct clk_alpha_pll gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
},
};
static const struct clk_div_table post_div_table_fabia_even[] = {
{ 0x0, 1 },
{ 0x1, 2 },
{ 0x3, 4 },
{ 0x7, 8 },
{ }
};
static struct clk_alpha_pll_postdiv gpll0_out_even = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_fabia_even,
.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_even",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_fixed_factor gcc_pll0_main_div_cdiv = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "gcc_pll0_main_div_cdiv",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_alpha_pll gpll6 = {
.offset = 0x13000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gpll6",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
},
};
static struct clk_alpha_pll gpll7 = {
.offset = 0x27000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gpll7",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct clk_parent_data gcc_parent_data_0_ao[] = {
{ .index = DT_BI_TCXO_AO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .index = DT_SLEEP_CLK },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
};
static const struct clk_parent_data gcc_parent_data_2_ao[] = {
{ .index = DT_BI_TCXO_AO },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gcc_parent_data_4[] = {
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL6_OUT_MAIN, 2 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL7_OUT_MAIN, 3 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_6[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll7.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_7[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data gcc_parent_data_8[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
};
static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
.cmd_rcgr = 0x48014,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk_src",
.parent_data = gcc_parent_data_0_ao,
.num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = {
.cmd_rcgr = 0x4815c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_rbcpr_clk_src",
.parent_data = gcc_parent_data_2_ao,
.num_parents = ARRAY_SIZE(gcc_parent_data_2_ao),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x64004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x65004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x66004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
.cmd_rcgr = 0x6b028,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
.cmd_rcgr = 0x6f014,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_phy_refgen_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x33010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x17034,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.cmd_rcgr = 0x17164,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.cmd_rcgr = 0x17294,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.cmd_rcgr = 0x173c4,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.cmd_rcgr = 0x174f4,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.cmd_rcgr = 0x17624,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
.name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
.cmd_rcgr = 0x17754,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
.name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
.cmd_rcgr = 0x17884,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.cmd_rcgr = 0x18018,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.cmd_rcgr = 0x18148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.cmd_rcgr = 0x18278,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.cmd_rcgr = 0x183a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.cmd_rcgr = 0x184d8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.cmd_rcgr = 0x18608,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
.name = "gcc_qupv3_wrap1_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
.cmd_rcgr = 0x18738,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
.name = "gcc_qupv3_wrap1_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
.cmd_rcgr = 0x18868,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
F(144000, P_BI_TCXO, 16, 3, 25),
F(400000, P_BI_TCXO, 12, 1, 4),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.cmd_rcgr = 0x12028,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x12010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(208000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.cmd_rcgr = 0x1400c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_floor_ops,
.flags = CLK_OPS_PARENT_ENABLE,
},
};
static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
.cmd_rcgr = 0x1600c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
F(105495, P_BI_TCXO, 2, 1, 91),
{ }
};
static struct clk_rcg2 gcc_tsif_ref_clk_src = {
.cmd_rcgr = 0x36010,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_tsif_ref_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ref_clk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.cmd_rcgr = 0x77020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.cmd_rcgr = 0x77048,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
.cmd_rcgr = 0x77098,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.cmd_rcgr = 0x77060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.cmd_rcgr = 0xf01c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.cmd_rcgr = 0xf034,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.cmd_rcgr = 0xf060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_vs_ctrl_clk_src = {
.cmd_rcgr = 0x7a030,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_vs_ctrl_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_vsensor_clk_src = {
.cmd_rcgr = 0x7a018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_vsensor_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_vsensor_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
.halt_reg = 0x2800c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2800c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_noc_pcie_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
.halt_reg = 0x82024,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x82024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x82024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
.halt_reg = 0x82024,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x82024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x82024,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_aggre_ufs_phy_axi_clk.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
.halt_reg = 0x8201c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_apc_vs_clk = {
.halt_reg = 0x7a050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7a050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_apc_vs_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_vsensor_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x38004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x38004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_hf_axi_clk = {
.halt_reg = 0xb020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_sf_axi_clk = {
.halt_reg = 0xb06c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb06c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_ahb_clk = {
.halt_reg = 0x4100c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x4100c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_axi_clk = {
.halt_reg = 0x41008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_clk = {
.halt_reg = 0x41004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.halt_reg = 0x502c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x502c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_ahb_clk = {
.halt_reg = 0x48000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_cpuss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_rbcpr_clk = {
.halt_reg = 0x48008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x48008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_rbcpr_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_cpuss_rbcpr_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ddrss_gpu_axi_clk = {
.halt_reg = 0x4452c,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x4452c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ddrss_gpu_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_gpll0_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_disp_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_pll0_main_div_cdiv.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_hf_axi_clk = {
.halt_reg = 0xb024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_sf_axi_clk = {
.halt_reg = 0xb070,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb070,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x64000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x64000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x65000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x65000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x66000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x66000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_pll0_main_div_cdiv.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
.halt_reg = 0x7100c,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x7100c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
.halt_reg = 0x71018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x71018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_snoc_dvm_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_vs_clk = {
.halt_reg = 0x7a04c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7a04c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_vs_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_vsensor_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_axi_clk = {
.halt_reg = 0x4d008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_cfg_ahb_clk = {
.halt_reg = 0x4d004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x4d004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4d004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_cfg_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_gpll0_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_pll0_main_div_cdiv.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_aux_clk = {
.halt_reg = 0x6b01c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.halt_reg = 0x6b018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_clkref_clk = {
.halt_reg = 0x8c008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.halt_reg = 0x6b014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_pipe_clk = {
.halt_reg = 0x6b020,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.halt_reg = 0x6b010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
.halt_reg = 0x6b00c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_phy_aux_clk = {
.halt_reg = 0x6f004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6f004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_phy_refgen_clk = {
.halt_reg = 0x6f02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6f02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_phy_refgen_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_phy_refgen_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x3300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x33004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x33004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x33004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x33008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x33008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x34004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x34004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
.halt_reg = 0x17014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_clk = {
.halt_reg = 0x1700c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.halt_reg = 0x17030,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.halt_reg = 0x17160,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.halt_reg = 0x17290,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.halt_reg = 0x173c0,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.halt_reg = 0x174f0,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.halt_reg = 0x17620,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
.halt_reg = 0x17750,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s6_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
.halt_reg = 0x17880,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s7_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
.halt_reg = 0x18004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_clk = {
.halt_reg = 0x18008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.halt_reg = 0x18014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.halt_reg = 0x18144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.halt_reg = 0x18274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.halt_reg = 0x183a4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.halt_reg = 0x184d4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.halt_reg = 0x18604,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
.halt_reg = 0x18734,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s6_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
.halt_reg = 0x18864,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(29),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s7_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
.halt_reg = 0x17008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
.halt_reg = 0x1800c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
.halt_reg = 0x18010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x18010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x12008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x1200c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0x12040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc1_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x14008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x14004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_ahb_clk = {
.halt_reg = 0x16008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_apps_clk = {
.halt_reg = 0x16004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
.halt_reg = 0x4144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_cpuss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_cpuss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ahb_clk = {
.halt_reg = 0x36004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_inactivity_timers_clk = {
.halt_reg = 0x3600c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_inactivity_timers_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ref_clk = {
.halt_reg = 0x36008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ref_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_tsif_ref_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_mem_clkref_clk = {
.halt_reg = 0x8c000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_mem_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x77014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_clk = {
.halt_reg = 0x77038,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77038,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
.halt_reg = 0x77038,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77038,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77038,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.halt_reg = 0x77090,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77090,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
.halt_reg = 0x77090,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77090,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77090,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_ice_core_clk.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.halt_reg = 0x77094,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77094,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77094,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
.halt_reg = 0x77094,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77094,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77094,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_phy_aux_clk.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.halt_reg = 0x7701c,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x7701c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
.halt_reg = 0x77018,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x77018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.halt_reg = 0x7708c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x7708c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7708c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
.halt_reg = 0x7708c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x7708c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7708c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_unipro_core_clk.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch_simple_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_master_clk = {
.halt_reg = 0xf010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0xf018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_sleep_clk = {
.halt_reg = 0xf014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_clkref_clk = {
.halt_reg = 0x8c010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
.halt_reg = 0xf050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.halt_reg = 0xf054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0xf058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
.halt_reg = 0x6a004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x6a004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x6a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_phy_cfg_ahb2phy_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vdda_vs_clk = {
.halt_reg = 0x7a00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7a00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_vdda_vs_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_vsensor_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vddcx_vs_clk = {
.halt_reg = 0x7a004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_vddcx_vs_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_vsensor_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vddmx_vs_clk = {
.halt_reg = 0x7a008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7a008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_vddmx_vs_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_vsensor_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi_clk = {
.halt_reg = 0xb01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vs_ctrl_ahb_clk = {
.halt_reg = 0x7a014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x7a014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7a014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_vs_ctrl_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vs_ctrl_clk = {
.halt_reg = 0x7a010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7a010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_vs_ctrl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_vs_ctrl_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x6b004,
.pd = {
.name = "pcie_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ufs_phy_gdsc = {
.gdscr = 0x77004,
.pd = {
.name = "ufs_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc usb30_prim_gdsc = {
.gdscr = 0xf004,
.pd = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = {
.gdscr = 0x7d030,
.pd = {
.name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = {
.gdscr = 0x7d03c,
.pd = {
.name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = {
.gdscr = 0x7d034,
.pd = {
.name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = {
.gdscr = 0x7d038,
.pd = {
.name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
.gdscr = 0x7d040,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
.gdscr = 0x7d048,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
.gdscr = 0x7d044,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct clk_hw *gcc_sm7150_hws[] = {
[GCC_GPLL0_MAIN_DIV_CDIV] = &gcc_pll0_main_div_cdiv.hw,
};
static struct clk_regmap *gcc_sm7150_clocks[] = {
[GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] =
&gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
[GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
[GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
[GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
[GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
[GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
[GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr,
[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
[GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
[GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
[GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr,
[GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
[GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
[GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
[GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
[GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
[GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
[GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr,
[GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
[GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
[GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
[GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
[GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] =
&gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
&gcc_ufs_phy_unipro_core_clk_src.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =
&gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
&gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
[GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr,
[GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr,
[GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr,
[GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
[GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr,
[GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr,
[GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr,
[GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
[GPLL6] = &gpll6.clkr,
[GPLL7] = &gpll7.clkr,
};
static const struct qcom_reset_map gcc_sm7150_resets[] = {
[GCC_PCIE_0_BCR] = { 0x6b000 },
[GCC_PCIE_PHY_BCR] = { 0x6f000 },
[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
[GCC_UFS_PHY_BCR] = { 0x77000 },
[GCC_USB30_PRIM_BCR] = { 0xf000 },
[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
[GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },
[GCC_VIDEO_AXI_CLK_BCR] = { 0xb01c, 2 },
};
static const struct clk_rcg_dfs_data gcc_sm7150_dfs_desc[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
};
static struct gdsc *gcc_sm7150_gdscs[] = {
[PCIE_0_GDSC] = &pcie_0_gdsc,
[UFS_PHY_GDSC] = &ufs_phy_gdsc,
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
[HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] =
&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc,
[HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] =
&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc,
[HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] =
&hlos1_vote_aggre_noc_mmu_tbu1_gdsc,
[HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] =
&hlos1_vote_aggre_noc_mmu_tbu2_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
};
static const struct regmap_config gcc_sm7150_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x1820b0,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_sm7150_desc = {
.config = &gcc_sm7150_regmap_config,
.clk_hws = gcc_sm7150_hws,
.num_clk_hws = ARRAY_SIZE(gcc_sm7150_hws),
.clks = gcc_sm7150_clocks,
.num_clks = ARRAY_SIZE(gcc_sm7150_clocks),
.resets = gcc_sm7150_resets,
.num_resets = ARRAY_SIZE(gcc_sm7150_resets),
.gdscs = gcc_sm7150_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sm7150_gdscs),
};
static const struct of_device_id gcc_sm7150_match_table[] = {
{ .compatible = "qcom,sm7150-gcc" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_sm7150_match_table);
static int gcc_sm7150_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sm7150_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/*
* Disable the GPLL0 active input to MM blocks, NPU
* and GPU via MISC registers.
*/
regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
/*
* Keep the critical clocks always-ON
* GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK,
* GCC_DISP_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_VIDEO_XO_CLK,
* GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK
*/
regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
ret = qcom_cc_register_rcg_dfs(regmap, gcc_sm7150_dfs_desc,
ARRAY_SIZE(gcc_sm7150_dfs_desc));
if (ret)
return ret;
return qcom_cc_really_probe(pdev, &gcc_sm7150_desc, regmap);
}
static struct platform_driver gcc_sm7150_driver = {
.probe = gcc_sm7150_probe,
.driver = {
.name = "gcc-sm7150",
.of_match_table = gcc_sm7150_match_table,
},
};
static int __init gcc_sm7150_init(void)
{
return platform_driver_register(&gcc_sm7150_driver);
}
subsys_initcall(gcc_sm7150_init);
static void __exit gcc_sm7150_exit(void)
{
platform_driver_unregister(&gcc_sm7150_driver);
}
module_exit(gcc_sm7150_exit);
MODULE_DESCRIPTION("Qualcomm SM7150 Global Clock Controller");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/gcc-sm7150.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,videocc-sm8150.h>
#include "common.h"
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_BI_TCXO,
P_VIDEO_PLL0_OUT_MAIN,
};
static struct pll_vco trion_vco[] = {
{ 249600000, 2000000000, 0 },
};
static struct alpha_pll_config video_pll0_config = {
.l = 0x14,
.alpha = 0xD555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002267,
.config_ctl_hi1_val = 0x00000024,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x000000D0,
};
static struct clk_alpha_pll video_pll0 = {
.offset = 0x42c,
.vco_table = trion_vco,
.num_vco = ARRAY_SIZE(trion_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "video_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_trion_ops,
},
},
};
static const struct parent_map video_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_PLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data video_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &video_pll0.clkr.hw },
};
static const struct freq_tbl ftbl_video_cc_iris_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
F(240000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
F(338000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
F(365000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
F(444000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
F(533000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_iris_clk_src = {
.cmd_rcgr = 0x7f0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_0,
.freq_tbl = ftbl_video_cc_iris_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "video_cc_iris_clk_src",
.parent_data = video_cc_parent_data_0,
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_branch video_cc_iris_ahb_clk = {
.halt_reg = 0x8f4,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x8f4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_iris_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_iris_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0_core_clk = {
.halt_reg = 0x890,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x890,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_mvs0_core_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_iris_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs1_core_clk = {
.halt_reg = 0x8d0,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x8d0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_mvs1_core_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_iris_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvsc_core_clk = {
.halt_reg = 0x850,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x850,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_mvsc_core_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_iris_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc venus_gdsc = {
.gdscr = 0x814,
.pd = {
.name = "venus_gdsc",
},
.flags = 0,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc vcodec0_gdsc = {
.gdscr = 0x874,
.pd = {
.name = "vcodec0_gdsc",
},
.flags = HW_CTRL,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc vcodec1_gdsc = {
.gdscr = 0x8b4,
.pd = {
.name = "vcodec1_gdsc",
},
.flags = HW_CTRL,
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *video_cc_sm8150_clocks[] = {
[VIDEO_CC_IRIS_AHB_CLK] = &video_cc_iris_ahb_clk.clkr,
[VIDEO_CC_IRIS_CLK_SRC] = &video_cc_iris_clk_src.clkr,
[VIDEO_CC_MVS0_CORE_CLK] = &video_cc_mvs0_core_clk.clkr,
[VIDEO_CC_MVS1_CORE_CLK] = &video_cc_mvs1_core_clk.clkr,
[VIDEO_CC_MVSC_CORE_CLK] = &video_cc_mvsc_core_clk.clkr,
[VIDEO_CC_PLL0] = &video_pll0.clkr,
};
static struct gdsc *video_cc_sm8150_gdscs[] = {
[VENUS_GDSC] = &venus_gdsc,
[VCODEC0_GDSC] = &vcodec0_gdsc,
[VCODEC1_GDSC] = &vcodec1_gdsc,
};
static const struct regmap_config video_cc_sm8150_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xb94,
.fast_io = true,
};
static const struct qcom_reset_map video_cc_sm8150_resets[] = {
[VIDEO_CC_MVSC_CORE_CLK_BCR] = { 0x850, 2 },
};
static const struct qcom_cc_desc video_cc_sm8150_desc = {
.config = &video_cc_sm8150_regmap_config,
.clks = video_cc_sm8150_clocks,
.num_clks = ARRAY_SIZE(video_cc_sm8150_clocks),
.resets = video_cc_sm8150_resets,
.num_resets = ARRAY_SIZE(video_cc_sm8150_resets),
.gdscs = video_cc_sm8150_gdscs,
.num_gdscs = ARRAY_SIZE(video_cc_sm8150_gdscs),
};
static const struct of_device_id video_cc_sm8150_match_table[] = {
{ .compatible = "qcom,sm8150-videocc" },
{ }
};
MODULE_DEVICE_TABLE(of, video_cc_sm8150_match_table);
static int video_cc_sm8150_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &video_cc_sm8150_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_trion_pll_configure(&video_pll0, regmap, &video_pll0_config);
/* Keep VIDEO_CC_XO_CLK ALWAYS-ON */
regmap_update_bits(regmap, 0x984, 0x1, 0x1);
return qcom_cc_really_probe(pdev, &video_cc_sm8150_desc, regmap);
}
static struct platform_driver video_cc_sm8150_driver = {
.probe = video_cc_sm8150_probe,
.driver = {
.name = "video_cc-sm8150",
.of_match_table = video_cc_sm8150_match_table,
},
};
static int __init video_cc_sm8150_init(void)
{
return platform_driver_register(&video_cc_sm8150_driver);
}
subsys_initcall(video_cc_sm8150_init);
static void __exit video_cc_sm8150_exit(void)
{
platform_driver_unregister(&video_cc_sm8150_driver);
}
module_exit(video_cc_sm8150_exit);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("QTI VIDEOCC SM8150 Driver");
| linux-master | drivers/clk/qcom/videocc-sm8150.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, The Linux Foundation. All rights reserved.
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/slab.h>
#include "clk-krait.h"
enum {
cpu0_mux = 0,
cpu1_mux,
cpu2_mux,
cpu3_mux,
l2_mux,
clks_max,
};
static unsigned int sec_mux_map[] = {
2,
0,
};
static unsigned int pri_mux_map[] = {
1,
2,
0,
};
/*
* Notifier function for switching the muxes to safe parent
* while the hfpll is getting reprogrammed.
*/
static int krait_notifier_cb(struct notifier_block *nb,
unsigned long event,
void *data)
{
int ret = 0;
struct krait_mux_clk *mux = container_of(nb, struct krait_mux_clk,
clk_nb);
/* Switch to safe parent */
if (event == PRE_RATE_CHANGE) {
mux->old_index = krait_mux_clk_ops.get_parent(&mux->hw);
ret = krait_mux_clk_ops.set_parent(&mux->hw, mux->safe_sel);
mux->reparent = false;
/*
* By the time POST_RATE_CHANGE notifier is called,
* clk framework itself would have changed the parent for the new rate.
* Only otherwise, put back to the old parent.
*/
} else if (event == POST_RATE_CHANGE) {
if (!mux->reparent)
ret = krait_mux_clk_ops.set_parent(&mux->hw,
mux->old_index);
}
return notifier_from_errno(ret);
}
static int krait_notifier_register(struct device *dev, struct clk *clk,
struct krait_mux_clk *mux)
{
int ret = 0;
mux->clk_nb.notifier_call = krait_notifier_cb;
ret = devm_clk_notifier_register(dev, clk, &mux->clk_nb);
if (ret)
dev_err(dev, "failed to register clock notifier: %d\n", ret);
return ret;
}
static struct clk_hw *
krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
{
struct krait_div2_clk *div;
static struct clk_parent_data p_data[1];
struct clk_init_data init = {
.num_parents = ARRAY_SIZE(p_data),
.ops = &krait_div2_clk_ops,
.flags = CLK_SET_RATE_PARENT,
};
struct clk_hw *clk;
char *parent_name;
int cpu, ret;
div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
if (!div)
return ERR_PTR(-ENOMEM);
div->width = 2;
div->shift = 6;
div->lpl = id >= 0;
div->offset = offset;
div->hw.init = &init;
init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
if (!init.name)
return ERR_PTR(-ENOMEM);
init.parent_data = p_data;
parent_name = kasprintf(GFP_KERNEL, "hfpll%s", s);
if (!parent_name) {
clk = ERR_PTR(-ENOMEM);
goto err_parent_name;
}
p_data[0].fw_name = parent_name;
p_data[0].name = parent_name;
ret = devm_clk_hw_register(dev, &div->hw);
if (ret) {
clk = ERR_PTR(ret);
goto err_clk;
}
clk = &div->hw;
/* clk-krait ignore any rate change if mux is not flagged as enabled */
if (id < 0)
for_each_online_cpu(cpu)
clk_prepare_enable(div->hw.clk);
else
clk_prepare_enable(div->hw.clk);
err_clk:
kfree(parent_name);
err_parent_name:
kfree(init.name);
return clk;
}
static struct clk_hw *
krait_add_sec_mux(struct device *dev, int id, const char *s,
unsigned int offset, bool unique_aux)
{
int cpu, ret;
struct krait_mux_clk *mux;
static struct clk_parent_data sec_mux_list[2] = {
{ .name = "qsb", .fw_name = "qsb" },
{},
};
struct clk_init_data init = {
.parent_data = sec_mux_list,
.num_parents = ARRAY_SIZE(sec_mux_list),
.ops = &krait_mux_clk_ops,
.flags = CLK_SET_RATE_PARENT,
};
struct clk_hw *clk;
char *parent_name;
mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
if (!mux)
return ERR_PTR(-ENOMEM);
mux->offset = offset;
mux->lpl = id >= 0;
mux->mask = 0x3;
mux->shift = 2;
mux->parent_map = sec_mux_map;
mux->hw.init = &init;
mux->safe_sel = 0;
/* Checking for qcom,krait-cc-v1 or qcom,krait-cc-v2 is not
* enough to limit this to apq/ipq8064. Directly check machine
* compatible to correctly handle this errata.
*/
if (of_machine_is_compatible("qcom,ipq8064") ||
of_machine_is_compatible("qcom,apq8064"))
mux->disable_sec_src_gating = true;
init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
if (!init.name)
return ERR_PTR(-ENOMEM);
if (unique_aux) {
parent_name = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
if (!parent_name) {
clk = ERR_PTR(-ENOMEM);
goto err_aux;
}
sec_mux_list[1].fw_name = parent_name;
sec_mux_list[1].name = parent_name;
} else {
sec_mux_list[1].name = "apu_aux";
}
ret = devm_clk_hw_register(dev, &mux->hw);
if (ret) {
clk = ERR_PTR(ret);
goto err_clk;
}
clk = &mux->hw;
ret = krait_notifier_register(dev, mux->hw.clk, mux);
if (ret) {
clk = ERR_PTR(ret);
goto err_clk;
}
/* clk-krait ignore any rate change if mux is not flagged as enabled */
if (id < 0)
for_each_online_cpu(cpu)
clk_prepare_enable(mux->hw.clk);
else
clk_prepare_enable(mux->hw.clk);
err_clk:
if (unique_aux)
kfree(parent_name);
err_aux:
kfree(init.name);
return clk;
}
static struct clk_hw *
krait_add_pri_mux(struct device *dev, struct clk_hw *hfpll_div, struct clk_hw *sec_mux,
int id, const char *s, unsigned int offset)
{
int ret;
struct krait_mux_clk *mux;
static struct clk_parent_data p_data[3];
struct clk_init_data init = {
.parent_data = p_data,
.num_parents = ARRAY_SIZE(p_data),
.ops = &krait_mux_clk_ops,
.flags = CLK_SET_RATE_PARENT,
};
struct clk_hw *clk;
char *hfpll_name;
mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
if (!mux)
return ERR_PTR(-ENOMEM);
mux->mask = 0x3;
mux->shift = 0;
mux->offset = offset;
mux->lpl = id >= 0;
mux->parent_map = pri_mux_map;
mux->hw.init = &init;
mux->safe_sel = 2;
init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
if (!init.name)
return ERR_PTR(-ENOMEM);
hfpll_name = kasprintf(GFP_KERNEL, "hfpll%s", s);
if (!hfpll_name) {
clk = ERR_PTR(-ENOMEM);
goto err_hfpll;
}
p_data[0].fw_name = hfpll_name;
p_data[0].name = hfpll_name;
p_data[1].hw = hfpll_div;
p_data[2].hw = sec_mux;
ret = devm_clk_hw_register(dev, &mux->hw);
if (ret) {
clk = ERR_PTR(ret);
goto err_clk;
}
clk = &mux->hw;
ret = krait_notifier_register(dev, mux->hw.clk, mux);
if (ret)
clk = ERR_PTR(ret);
err_clk:
kfree(hfpll_name);
err_hfpll:
kfree(init.name);
return clk;
}
/* id < 0 for L2, otherwise id == physical CPU number */
static struct clk_hw *krait_add_clks(struct device *dev, int id, bool unique_aux)
{
struct clk_hw *hfpll_div, *sec_mux, *pri_mux;
unsigned int offset;
void *p = NULL;
const char *s;
if (id >= 0) {
offset = 0x4501 + (0x1000 * id);
s = p = kasprintf(GFP_KERNEL, "%d", id);
if (!s)
return ERR_PTR(-ENOMEM);
} else {
offset = 0x500;
s = "_l2";
}
hfpll_div = krait_add_div(dev, id, s, offset);
if (IS_ERR(hfpll_div)) {
pri_mux = hfpll_div;
goto err;
}
sec_mux = krait_add_sec_mux(dev, id, s, offset, unique_aux);
if (IS_ERR(sec_mux)) {
pri_mux = sec_mux;
goto err;
}
pri_mux = krait_add_pri_mux(dev, hfpll_div, sec_mux, id, s, offset);
err:
kfree(p);
return pri_mux;
}
static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
{
unsigned int idx = clkspec->args[0];
struct clk **clks = data;
if (idx >= clks_max) {
pr_err("%s: invalid clock index %d\n", __func__, idx);
return ERR_PTR(-EINVAL);
}
return clks[idx] ? : ERR_PTR(-ENODEV);
}
static const struct of_device_id krait_cc_match_table[] = {
{ .compatible = "qcom,krait-cc-v1", (void *)1UL },
{ .compatible = "qcom,krait-cc-v2" },
{}
};
MODULE_DEVICE_TABLE(of, krait_cc_match_table);
static int krait_cc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct of_device_id *id;
unsigned long cur_rate, aux_rate;
int cpu;
struct clk_hw *mux, *l2_pri_mux;
struct clk *clk, **clks;
id = of_match_device(krait_cc_match_table, dev);
if (!id)
return -ENODEV;
/* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
if (IS_ERR(clk))
return PTR_ERR(clk);
if (!id->data) {
clk = clk_register_fixed_factor(dev, "acpu_aux",
"gpll0_vote", 0, 1, 2);
if (IS_ERR(clk))
return PTR_ERR(clk);
}
/* Krait configurations have at most 4 CPUs and one L2 */
clks = devm_kcalloc(dev, clks_max, sizeof(*clks), GFP_KERNEL);
if (!clks)
return -ENOMEM;
for_each_possible_cpu(cpu) {
mux = krait_add_clks(dev, cpu, id->data);
if (IS_ERR(mux))
return PTR_ERR(mux);
clks[cpu] = mux->clk;
}
l2_pri_mux = krait_add_clks(dev, -1, id->data);
if (IS_ERR(l2_pri_mux))
return PTR_ERR(l2_pri_mux);
clks[l2_mux] = l2_pri_mux->clk;
/*
* We don't want the CPU or L2 clocks to be turned off at late init
* if CPUFREQ or HOTPLUG configs are disabled. So, bump up the
* refcount of these clocks. Any cpufreq/hotplug manager can assume
* that the clocks have already been prepared and enabled by the time
* they take over.
*/
for_each_online_cpu(cpu) {
clk_prepare_enable(clks[l2_mux]);
WARN(clk_prepare_enable(clks[cpu]),
"Unable to turn on CPU%d clock", cpu);
}
/*
* Force reinit of HFPLLs and muxes to overwrite any potential
* incorrect configuration of HFPLLs and muxes by the bootloader.
* While at it, also make sure the cores are running at known rates
* and print the current rate.
*
* The clocks are set to aux clock rate first to make sure the
* secondary mux is not sourcing off of QSB. The rate is then set to
* two different rates to force a HFPLL reinit under all
* circumstances.
*/
cur_rate = clk_get_rate(clks[l2_mux]);
aux_rate = 384000000;
if (cur_rate < aux_rate) {
pr_info("L2 @ Undefined rate. Forcing new rate.\n");
cur_rate = aux_rate;
}
clk_set_rate(clks[l2_mux], aux_rate);
clk_set_rate(clks[l2_mux], 2);
clk_set_rate(clks[l2_mux], cur_rate);
pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
for_each_possible_cpu(cpu) {
clk = clks[cpu];
cur_rate = clk_get_rate(clk);
if (cur_rate < aux_rate) {
pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
cur_rate = aux_rate;
}
clk_set_rate(clk, aux_rate);
clk_set_rate(clk, 2);
clk_set_rate(clk, cur_rate);
pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
}
of_clk_add_provider(dev->of_node, krait_of_get, clks);
return 0;
}
static struct platform_driver krait_cc_driver = {
.probe = krait_cc_probe,
.driver = {
.name = "krait-cc",
.of_match_table = krait_cc_match_table,
},
};
module_platform_driver(krait_cc_driver);
MODULE_DESCRIPTION("Krait CPU Clock Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:krait-cc");
| linux-master | drivers/clk/qcom/krait-cc.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,qdu1000-gcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_GCC_GPLL0_OUT_EVEN,
P_GCC_GPLL0_OUT_MAIN,
P_GCC_GPLL1_OUT_MAIN,
P_GCC_GPLL2_OUT_MAIN,
P_GCC_GPLL3_OUT_MAIN,
P_GCC_GPLL4_OUT_MAIN,
P_GCC_GPLL5_OUT_MAIN,
P_GCC_GPLL6_OUT_MAIN,
P_GCC_GPLL7_OUT_MAIN,
P_GCC_GPLL8_OUT_MAIN,
P_PCIE_0_PHY_AUX_CLK,
P_PCIE_0_PIPE_CLK,
P_SLEEP_CLK,
P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
};
enum {
DT_TCXO_IDX,
DT_SLEEP_CLK_IDX,
DT_PCIE_0_PIPE_CLK_IDX,
DT_PCIE_0_PHY_AUX_CLK_IDX,
DT_USB3_PHY_WRAPPER_PIPE_CLK_IDX,
};
static struct clk_alpha_pll gcc_gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x62018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_TCXO_IDX,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
{ 0x1, 2 }
};
static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
.offset = 0x0,
.post_div_shift = 10,
.post_div_table = post_div_table_gcc_gpll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll0_out_even",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static struct clk_alpha_pll gcc_gpll1 = {
.offset = 0x1000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x62018,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll1",
.parent_data = &(const struct clk_parent_data) {
.index = DT_TCXO_IDX,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
},
};
static struct clk_alpha_pll_postdiv gcc_gpll1_out_even = {
.offset = 0x1000,
.post_div_shift = 10,
.post_div_table = post_div_table_gcc_gpll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll1_out_even",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll1.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static struct clk_alpha_pll gcc_gpll2 = {
.offset = 0x2000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x62018,
.enable_mask = BIT(2),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll2",
.parent_data = &(const struct clk_parent_data) {
.index = DT_TCXO_IDX,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
},
};
static struct clk_alpha_pll_postdiv gcc_gpll2_out_even = {
.offset = 0x2000,
.post_div_shift = 10,
.post_div_table = post_div_table_gcc_gpll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll2_out_even",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll2.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static struct clk_alpha_pll gcc_gpll3 = {
.offset = 0x3000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x62018,
.enable_mask = BIT(3),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll3",
.parent_data = &(const struct clk_parent_data) {
.index = DT_TCXO_IDX,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll4 = {
.offset = 0x4000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x62018,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll4",
.parent_data = &(const struct clk_parent_data) {
.index = DT_TCXO_IDX,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll5 = {
.offset = 0x5000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x62018,
.enable_mask = BIT(5),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll5",
.parent_data = &(const struct clk_parent_data) {
.index = DT_TCXO_IDX,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
},
};
static struct clk_alpha_pll_postdiv gcc_gpll5_out_even = {
.offset = 0x5000,
.post_div_shift = 10,
.post_div_table = post_div_table_gcc_gpll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll5_out_even",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll5.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static struct clk_alpha_pll gcc_gpll6 = {
.offset = 0x6000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x62018,
.enable_mask = BIT(6),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll6",
.parent_data = &(const struct clk_parent_data) {
.index = DT_TCXO_IDX,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll7 = {
.offset = 0x7000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x62018,
.enable_mask = BIT(7),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll7",
.parent_data = &(const struct clk_parent_data) {
.index = DT_TCXO_IDX,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll8 = {
.offset = 0x8000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x62018,
.enable_mask = BIT(8),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll8",
.parent_data = &(const struct clk_parent_data) {
.index = DT_TCXO_IDX,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .index = DT_TCXO_IDX },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .index = DT_TCXO_IDX },
{ .hw = &gcc_gpll0.clkr.hw },
{ .index = DT_SLEEP_CLK_IDX },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL5_OUT_MAIN, 3 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .index = DT_TCXO_IDX },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll5.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .index = DT_TCXO_IDX },
{ .index = DT_SLEEP_CLK_IDX },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL2_OUT_MAIN, 2 },
{ P_GCC_GPLL5_OUT_MAIN, 3 },
{ P_GCC_GPLL1_OUT_MAIN, 4 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
{ P_GCC_GPLL3_OUT_MAIN, 6 },
};
static const struct clk_parent_data gcc_parent_data_4[] = {
{ .index = DT_TCXO_IDX },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll2.clkr.hw },
{ .hw = &gcc_gpll5.clkr.hw },
{ .hw = &gcc_gpll1.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
{ .hw = &gcc_gpll3.clkr.hw },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL2_OUT_MAIN, 2 },
{ P_GCC_GPLL6_OUT_MAIN, 3 },
{ P_GCC_GPLL1_OUT_MAIN, 4 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
{ P_GCC_GPLL3_OUT_MAIN, 6 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .index = DT_TCXO_IDX },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll2.clkr.hw },
{ .hw = &gcc_gpll6.clkr.hw },
{ .hw = &gcc_gpll1.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
{ .hw = &gcc_gpll3.clkr.hw },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_PCIE_0_PHY_AUX_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_6[] = {
{ .index = DT_PCIE_0_PHY_AUX_CLK_IDX },
{ .index = DT_TCXO_IDX },
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL8_OUT_MAIN, 2 },
{ P_GCC_GPLL5_OUT_MAIN, 3 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
};
static const struct clk_parent_data gcc_parent_data_8[] = {
{ .index = DT_TCXO_IDX },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll8.clkr.hw },
{ .hw = &gcc_gpll5.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
};
static const struct parent_map gcc_parent_map_9[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL2_OUT_MAIN, 2 },
{ P_GCC_GPLL5_OUT_MAIN, 3 },
{ P_GCC_GPLL7_OUT_MAIN, 4 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
};
static const struct clk_parent_data gcc_parent_data_9[] = {
{ .index = DT_TCXO_IDX },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll2.clkr.hw },
{ .hw = &gcc_gpll5.clkr.hw },
{ .hw = &gcc_gpll7.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
};
static const struct parent_map gcc_parent_map_10[] = {
{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_10[] = {
{ .index = DT_USB3_PHY_WRAPPER_PIPE_CLK_IDX },
{ .index = DT_TCXO_IDX },
};
static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = {
.reg = 0x9d080,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_6,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_phy_aux_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
.reg = 0x9d064,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_0_PIPE_CLK_IDX,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
.reg = 0x4906c,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_10,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_prim_phy_pipe_clk_src",
.parent_data = gcc_parent_data_10,
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_dma_clk_src[] = {
F(466500000, P_GCC_GPLL5_OUT_MAIN, 2, 0, 0),
F(500000000, P_GCC_GPLL2_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_aggre_noc_ecpri_dma_clk_src = {
.cmd_rcgr = 0x92020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_aggre_noc_ecpri_dma_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_noc_ecpri_dma_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_gsi_clk_src[] = {
F(250000000, P_GCC_GPLL2_OUT_MAIN, 4, 0, 0),
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_aggre_noc_ecpri_gsi_clk_src = {
.cmd_rcgr = 0x92038,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_aggre_noc_ecpri_gsi_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_noc_ecpri_gsi_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x74004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x75004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x76004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
.cmd_rcgr = 0x9d068,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
.cmd_rcgr = 0x9d04c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x43010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x27154,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.cmd_rcgr = 0x27288,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.cmd_rcgr = 0x273bc,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.cmd_rcgr = 0x274f0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.cmd_rcgr = 0x27624,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s5_clk_src[] = {
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.cmd_rcgr = 0x27758,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
.name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
.cmd_rcgr = 0x2788c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
.name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
.cmd_rcgr = 0x279c0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.cmd_rcgr = 0x28154,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.cmd_rcgr = 0x28288,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.cmd_rcgr = 0x283bc,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.cmd_rcgr = 0x284f0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.cmd_rcgr = 0x28624,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.cmd_rcgr = 0x28758,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
.name = "gcc_qupv3_wrap1_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
.cmd_rcgr = 0x2888c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
.name = "gcc_qupv3_wrap1_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
.cmd_rcgr = 0x289c0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc5_apps_clk_src[] = {
F(144000, P_BI_TCXO, 16, 3, 25),
F(400000, P_BI_TCXO, 12, 1, 4),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(20000000, P_GCC_GPLL0_OUT_MAIN, 10, 1, 3),
F(25000000, P_GCC_GPLL0_OUT_MAIN, 12, 1, 2),
F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
F(192000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
F(384000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc5_apps_clk_src = {
.cmd_rcgr = 0x3b034,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_sdcc5_apps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc5_apps_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc5_ice_core_clk_src[] = {
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src = {
.cmd_rcgr = 0x3b01c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_sdcc5_ice_core_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc5_ice_core_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_floor_ops,
},
};
static struct clk_rcg2 gcc_sm_bus_xo_clk_src = {
.cmd_rcgr = 0x5b00c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_sm_bus_xo_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_tsc_clk_src[] = {
F(500000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_tsc_clk_src = {
.cmd_rcgr = 0x57010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_9,
.freq_tbl = ftbl_gcc_tsc_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_tsc_clk_src",
.parent_data = gcc_parent_data_9,
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.cmd_rcgr = 0x49028,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.cmd_rcgr = 0x49044,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.cmd_rcgr = 0x49070,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
.reg = 0x4905c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gcc_aggre_noc_ecpri_dma_clk = {
.halt_reg = 0x92008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x92008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x92008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_noc_ecpri_dma_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_noc_ecpri_gsi_clk = {
.halt_reg = 0x9201c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9201c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x9201c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_noc_ecpri_gsi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x48004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x48004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(10),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_ecpri_cc_ahb_clk = {
.halt_reg = 0x3e004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x3e004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3e004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cfg_noc_ecpri_cc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.halt_reg = 0x8401c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8401c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8401c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ddrss_ecpri_dma_clk = {
.halt_reg = 0x54030,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x54030,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x54030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ddrss_ecpri_dma_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_ddrss_ecpri_gsi_clk = {
.halt_reg = 0x54298,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x54298,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x54298,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ddrss_ecpri_gsi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_ecpri_ahb_clk = {
.halt_reg = 0x3a008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x3a008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3a008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ecpri_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ecpri_cc_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x62010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ecpri_cc_gpll0_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ecpri_cc_gpll1_even_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x62010,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ecpri_cc_gpll1_even_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll1_out_even.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ecpri_cc_gpll2_even_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x62010,
.enable_mask = BIT(2),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ecpri_cc_gpll2_even_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll2_out_even.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ecpri_cc_gpll3_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x62010,
.enable_mask = BIT(3),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ecpri_cc_gpll3_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll3.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ecpri_cc_gpll4_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x62010,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ecpri_cc_gpll4_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll4.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ecpri_cc_gpll5_even_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x62010,
.enable_mask = BIT(5),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ecpri_cc_gpll5_even_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll5_out_even.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ecpri_xo_clk = {
.halt_reg = 0x3a004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3a004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ecpri_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_eth_100g_c2c_hm_apb_clk = {
.halt_reg = 0x39010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_eth_100g_c2c_hm_apb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_eth_100g_fh_hm_apb_0_clk = {
.halt_reg = 0x39004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_eth_100g_fh_hm_apb_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_eth_100g_fh_hm_apb_1_clk = {
.halt_reg = 0x39008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_eth_100g_fh_hm_apb_1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_eth_100g_fh_hm_apb_2_clk = {
.halt_reg = 0x3900c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3900c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_eth_100g_fh_hm_apb_2_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_eth_dbg_c2c_hm_apb_clk = {
.halt_reg = 0x39014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_eth_dbg_c2c_hm_apb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_eth_dbg_snoc_axi_clk = {
.halt_reg = 0x3901c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x3901c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3901c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_eth_dbg_snoc_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gemnoc_pcie_qx_clk = {
.halt_reg = 0x5402c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x5402c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gemnoc_pcie_qx_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x74000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x74000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x75000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x75000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x76000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x76000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_aux_clk = {
.halt_reg = 0x9d030,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9d030,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(29),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.halt_reg = 0x9d02c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9d02c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(28),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_clkref_en = {
.halt_reg = 0x9c004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9c004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.halt_reg = 0x9d024,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x9d024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(27),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_phy_aux_clk = {
.halt_reg = 0x9d038,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9d038,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(24),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_0_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
.halt_reg = 0x9d048,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9d048,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(23),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_pipe_clk = {
.halt_reg = 0x9d040,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9d040,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(30),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_0_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.halt_reg = 0x9d01c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9d01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(26),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
.halt_reg = 0x9d018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9d018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(25),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x4300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4300c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x43004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x43004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x43004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x43008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x43008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_anoc_pcie_clk = {
.halt_reg = 0x84044,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x84044,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x84044,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_anoc_pcie_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_ecpri_dma0_clk = {
.halt_reg = 0x84038,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x84038,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x84038,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_ecpri_dma0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_ecpri_dma1_clk = {
.halt_reg = 0x8403c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8403c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8403c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_ecpri_dma1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_ecpri_gsi_clk = {
.halt_reg = 0x84040,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x84040,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x84040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_ecpri_gsi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
.halt_reg = 0x27018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(9),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_clk = {
.halt_reg = 0x2700c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(8),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.halt_reg = 0x2714c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(10),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.halt_reg = 0x27280,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(11),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.halt_reg = 0x273b4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(12),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.halt_reg = 0x274e8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(13),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.halt_reg = 0x2761c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(14),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s4_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.halt_reg = 0x27750,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(15),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s5_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
.halt_reg = 0x27884,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(16),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s6_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
.halt_reg = 0x279b8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(17),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s7_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
.halt_reg = 0x28018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(18),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_clk = {
.halt_reg = 0x2800c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(19),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.halt_reg = 0x2814c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(22),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.halt_reg = 0x28280,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(23),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.halt_reg = 0x283b4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(24),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.halt_reg = 0x284e8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(25),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.halt_reg = 0x2861c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(26),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s4_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.halt_reg = 0x28750,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(27),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s5_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
.halt_reg = 0x28884,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(28),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s6_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
.halt_reg = 0x289b8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(29),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s7_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
.halt_reg = 0x27004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x27004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(6),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
.halt_reg = 0x27008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x27008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(7),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
.halt_reg = 0x28004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x28004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(20),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_1_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
.halt_reg = 0x28008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x28008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62008,
.enable_mask = BIT(21),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_1_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc5_ahb_clk = {
.halt_reg = 0x3b00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3b00c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc5_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc5_apps_clk = {
.halt_reg = 0x3b004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3b004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc5_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc5_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc5_ice_core_clk = {
.halt_reg = 0x3b010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3b010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc5_ice_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc5_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sm_bus_ahb_clk = {
.halt_reg = 0x5b004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5b004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sm_bus_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sm_bus_xo_clk = {
.halt_reg = 0x5b008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5b008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sm_bus_xo_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sm_bus_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_qx_clk = {
.halt_reg = 0x9200c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x9200c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(11),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_snoc_cnoc_gemnoc_pcie_qx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk = {
.halt_reg = 0x92010,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x92010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(12),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_cnoc_pcie_qx_clk = {
.halt_reg = 0x84030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x84030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_snoc_cnoc_pcie_qx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_pcie_sf_center_qx_clk = {
.halt_reg = 0x92014,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x92014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(19),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_snoc_pcie_sf_center_qx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_pcie_sf_south_qx_clk = {
.halt_reg = 0x92018,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x92018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x62000,
.enable_mask = BIT(22),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_snoc_pcie_sf_south_qx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsc_cfg_ahb_clk = {
.halt_reg = 0x5700c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5700c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_tsc_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsc_cntr_clk = {
.halt_reg = 0x57004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x57004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_tsc_cntr_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_tsc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsc_etu_clk = {
.halt_reg = 0x57008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x57008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_tsc_etu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_tsc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb2_clkref_en = {
.halt_reg = 0x9c008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9c008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb2_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_master_clk = {
.halt_reg = 0x49018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x49018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_master_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0x49024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x49024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_sleep_clk = {
.halt_reg = 0x49020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x49020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
.halt_reg = 0x49060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x49060,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_prim_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.halt_reg = 0x49064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x49064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_reg = 0x49068,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x49068,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x49068,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_prim_phy_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x9d004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_pcie_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc pcie_0_phy_gdsc = {
.gdscr = 0x7c004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gcc_pcie_0_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc usb30_prim_gdsc = {
.gdscr = 0x49004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_usb30_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *gcc_qdu1000_clocks[] = {
[GCC_AGGRE_NOC_ECPRI_DMA_CLK] = &gcc_aggre_noc_ecpri_dma_clk.clkr,
[GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC] = &gcc_aggre_noc_ecpri_dma_clk_src.clkr,
[GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC] = &gcc_aggre_noc_ecpri_gsi_clk_src.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CFG_NOC_ECPRI_CC_AHB_CLK] = &gcc_cfg_noc_ecpri_cc_ahb_clk.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_DDRSS_ECPRI_DMA_CLK] = &gcc_ddrss_ecpri_dma_clk.clkr,
[GCC_ECPRI_AHB_CLK] = &gcc_ecpri_ahb_clk.clkr,
[GCC_ECPRI_CC_GPLL0_CLK_SRC] = &gcc_ecpri_cc_gpll0_clk_src.clkr,
[GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll1_even_clk_src.clkr,
[GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll2_even_clk_src.clkr,
[GCC_ECPRI_CC_GPLL3_CLK_SRC] = &gcc_ecpri_cc_gpll3_clk_src.clkr,
[GCC_ECPRI_CC_GPLL4_CLK_SRC] = &gcc_ecpri_cc_gpll4_clk_src.clkr,
[GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll5_even_clk_src.clkr,
[GCC_ECPRI_XO_CLK] = &gcc_ecpri_xo_clk.clkr,
[GCC_ETH_DBG_SNOC_AXI_CLK] = &gcc_eth_dbg_snoc_axi_clk.clkr,
[GCC_GEMNOC_PCIE_QX_CLK] = &gcc_gemnoc_pcie_qx_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPLL0] = &gcc_gpll0.clkr,
[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
[GCC_GPLL1] = &gcc_gpll1.clkr,
[GCC_GPLL2] = &gcc_gpll2.clkr,
[GCC_GPLL2_OUT_EVEN] = &gcc_gpll2_out_even.clkr,
[GCC_GPLL3] = &gcc_gpll3.clkr,
[GCC_GPLL4] = &gcc_gpll4.clkr,
[GCC_GPLL5] = &gcc_gpll5.clkr,
[GCC_GPLL5_OUT_EVEN] = &gcc_gpll5_out_even.clkr,
[GCC_GPLL6] = &gcc_gpll6.clkr,
[GCC_GPLL7] = &gcc_gpll7.clkr,
[GCC_GPLL8] = &gcc_gpll8.clkr,
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
[GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
[GCC_PCIE_0_PHY_AUX_CLK] = &gcc_pcie_0_phy_aux_clk.clkr,
[GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_QMIP_ANOC_PCIE_CLK] = &gcc_qmip_anoc_pcie_clk.clkr,
[GCC_QMIP_ECPRI_DMA0_CLK] = &gcc_qmip_ecpri_dma0_clk.clkr,
[GCC_QMIP_ECPRI_DMA1_CLK] = &gcc_qmip_ecpri_dma1_clk.clkr,
[GCC_QMIP_ECPRI_GSI_CLK] = &gcc_qmip_ecpri_gsi_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
[GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
[GCC_SDCC5_AHB_CLK] = &gcc_sdcc5_ahb_clk.clkr,
[GCC_SDCC5_APPS_CLK] = &gcc_sdcc5_apps_clk.clkr,
[GCC_SDCC5_APPS_CLK_SRC] = &gcc_sdcc5_apps_clk_src.clkr,
[GCC_SDCC5_ICE_CORE_CLK] = &gcc_sdcc5_ice_core_clk.clkr,
[GCC_SDCC5_ICE_CORE_CLK_SRC] = &gcc_sdcc5_ice_core_clk_src.clkr,
[GCC_SM_BUS_AHB_CLK] = &gcc_sm_bus_ahb_clk.clkr,
[GCC_SM_BUS_XO_CLK] = &gcc_sm_bus_xo_clk.clkr,
[GCC_SM_BUS_XO_CLK_SRC] = &gcc_sm_bus_xo_clk_src.clkr,
[GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK] = &gcc_snoc_cnoc_gemnoc_pcie_qx_clk.clkr,
[GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK] = &gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk.clkr,
[GCC_SNOC_CNOC_PCIE_QX_CLK] = &gcc_snoc_cnoc_pcie_qx_clk.clkr,
[GCC_SNOC_PCIE_SF_CENTER_QX_CLK] = &gcc_snoc_pcie_sf_center_qx_clk.clkr,
[GCC_SNOC_PCIE_SF_SOUTH_QX_CLK] = &gcc_snoc_pcie_sf_south_qx_clk.clkr,
[GCC_TSC_CFG_AHB_CLK] = &gcc_tsc_cfg_ahb_clk.clkr,
[GCC_TSC_CLK_SRC] = &gcc_tsc_clk_src.clkr,
[GCC_TSC_CNTR_CLK] = &gcc_tsc_cntr_clk.clkr,
[GCC_TSC_ETU_CLK] = &gcc_tsc_etu_clk.clkr,
[GCC_USB2_CLKREF_EN] = &gcc_usb2_clkref_en.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
[GCC_ETH_100G_C2C_HM_APB_CLK] = &gcc_eth_100g_c2c_hm_apb_clk.clkr,
[GCC_ETH_100G_FH_HM_APB_0_CLK] = &gcc_eth_100g_fh_hm_apb_0_clk.clkr,
[GCC_ETH_100G_FH_HM_APB_1_CLK] = &gcc_eth_100g_fh_hm_apb_1_clk.clkr,
[GCC_ETH_100G_FH_HM_APB_2_CLK] = &gcc_eth_100g_fh_hm_apb_2_clk.clkr,
[GCC_ETH_DBG_C2C_HM_APB_CLK] = &gcc_eth_dbg_c2c_hm_apb_clk.clkr,
[GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr,
[GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr,
[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
[GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr,
[GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr,
};
static struct gdsc *gcc_qdu1000_gdscs[] = {
[PCIE_0_GDSC] = &pcie_0_gdsc,
[PCIE_0_PHY_GDSC] = &pcie_0_phy_gdsc,
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
};
static const struct qcom_reset_map gcc_qdu1000_resets[] = {
[GCC_ECPRI_CC_BCR] = { 0x3e000 },
[GCC_ECPRI_SS_BCR] = { 0x3a000 },
[GCC_ETH_WRAPPER_BCR] = { 0x39000 },
[GCC_PCIE_0_BCR] = { 0x9d000 },
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x9e014 },
[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x9e020 },
[GCC_PCIE_0_PHY_BCR] = { 0x7c000 },
[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 },
[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c },
[GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
[GCC_PDM_BCR] = { 0x43000 },
[GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 },
[GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 },
[GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x22004 },
[GCC_SDCC5_BCR] = { 0x3b000 },
[GCC_TSC_BCR] = { 0x57000 },
[GCC_USB30_PRIM_BCR] = { 0x49000 },
[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 },
[GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 },
[GCC_USB3_PHY_PRIM_BCR] = { 0x60000 },
[GCC_USB3_PHY_SEC_BCR] = { 0x6000c },
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 },
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
};
static const struct regmap_config gcc_qdu1000_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x1f41f0,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_qdu1000_desc = {
.config = &gcc_qdu1000_regmap_config,
.clks = gcc_qdu1000_clocks,
.num_clks = ARRAY_SIZE(gcc_qdu1000_clocks),
.resets = gcc_qdu1000_resets,
.num_resets = ARRAY_SIZE(gcc_qdu1000_resets),
.gdscs = gcc_qdu1000_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_qdu1000_gdscs),
};
static const struct of_device_id gcc_qdu1000_match_table[] = {
{ .compatible = "qcom,qdu1000-gcc" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_qdu1000_match_table);
static int gcc_qdu1000_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_qdu1000_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Update FORCE_MEM_CORE_ON for gcc_pcie_0_mstr_axi_clk */
regmap_update_bits(regmap, 0x9d024, BIT(14), BIT(14));
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
ret = qcom_cc_really_probe(pdev, &gcc_qdu1000_desc, regmap);
if (ret)
return dev_err_probe(&pdev->dev, ret, "Failed to register GCC clocks\n");
return ret;
}
static struct platform_driver gcc_qdu1000_driver = {
.probe = gcc_qdu1000_probe,
.driver = {
.name = "gcc-qdu1000",
.of_match_table = gcc_qdu1000_match_table,
},
};
static int __init gcc_qdu1000_init(void)
{
return platform_driver_register(&gcc_qdu1000_driver);
}
subsys_initcall(gcc_qdu1000_init);
static void __exit gcc_qdu1000_exit(void)
{
platform_driver_unregister(&gcc_qdu1000_driver);
}
module_exit(gcc_qdu1000_exit);
MODULE_DESCRIPTION("QTI GCC QDU1000 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/gcc-qdu1000.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*/
#include <linux/export.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/platform_device.h>
#include <linux/clk-provider.h>
#include <linux/reset-controller.h>
#include <linux/of.h>
#include "common.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "reset.h"
#include "gdsc.h"
struct qcom_cc {
struct qcom_reset_controller reset;
struct clk_regmap **rclks;
size_t num_rclks;
};
const
struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
{
if (!f)
return NULL;
if (!f->freq)
return f;
for (; f->freq; f++)
if (rate <= f->freq)
return f;
/* Default to our fastest rate */
return f - 1;
}
EXPORT_SYMBOL_GPL(qcom_find_freq);
const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
unsigned long rate)
{
const struct freq_tbl *best = NULL;
for ( ; f->freq; f++) {
if (rate >= f->freq)
best = f;
else
break;
}
return best;
}
EXPORT_SYMBOL_GPL(qcom_find_freq_floor);
int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src)
{
int i, num_parents = clk_hw_get_num_parents(hw);
for (i = 0; i < num_parents; i++)
if (src == map[i].src)
return i;
return -ENOENT;
}
EXPORT_SYMBOL_GPL(qcom_find_src_index);
int qcom_find_cfg_index(struct clk_hw *hw, const struct parent_map *map, u8 cfg)
{
int i, num_parents = clk_hw_get_num_parents(hw);
for (i = 0; i < num_parents; i++)
if (cfg == map[i].cfg)
return i;
return -ENOENT;
}
EXPORT_SYMBOL_GPL(qcom_find_cfg_index);
struct regmap *
qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
{
void __iomem *base;
struct device *dev = &pdev->dev;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return ERR_CAST(base);
return devm_regmap_init_mmio(dev, base, desc->config);
}
EXPORT_SYMBOL_GPL(qcom_cc_map);
void
qcom_pll_set_fsm_mode(struct regmap *map, u32 reg, u8 bias_count, u8 lock_count)
{
u32 val;
u32 mask;
/* De-assert reset to FSM */
regmap_update_bits(map, reg, PLL_VOTE_FSM_RESET, 0);
/* Program bias count and lock count */
val = bias_count << PLL_BIAS_COUNT_SHIFT |
lock_count << PLL_LOCK_COUNT_SHIFT;
mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
regmap_update_bits(map, reg, mask, val);
/* Enable PLL FSM voting */
regmap_update_bits(map, reg, PLL_VOTE_FSM_ENA, PLL_VOTE_FSM_ENA);
}
EXPORT_SYMBOL_GPL(qcom_pll_set_fsm_mode);
static void qcom_cc_gdsc_unregister(void *data)
{
gdsc_unregister(data);
}
/*
* Backwards compatibility with old DTs. Register a pass-through factor 1/1
* clock to translate 'path' clk into 'name' clk and register the 'path'
* clk as a fixed rate clock if it isn't present.
*/
static int _qcom_cc_register_board_clk(struct device *dev, const char *path,
const char *name, unsigned long rate,
bool add_factor)
{
struct device_node *node = NULL;
struct device_node *clocks_node;
struct clk_fixed_factor *factor;
struct clk_fixed_rate *fixed;
struct clk_init_data init_data = { };
int ret;
clocks_node = of_find_node_by_path("/clocks");
if (clocks_node) {
node = of_get_child_by_name(clocks_node, path);
of_node_put(clocks_node);
}
if (!node) {
fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
if (!fixed)
return -EINVAL;
fixed->fixed_rate = rate;
fixed->hw.init = &init_data;
init_data.name = path;
init_data.ops = &clk_fixed_rate_ops;
ret = devm_clk_hw_register(dev, &fixed->hw);
if (ret)
return ret;
}
of_node_put(node);
if (add_factor) {
factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL);
if (!factor)
return -EINVAL;
factor->mult = factor->div = 1;
factor->hw.init = &init_data;
init_data.name = name;
init_data.parent_names = &path;
init_data.num_parents = 1;
init_data.flags = 0;
init_data.ops = &clk_fixed_factor_ops;
ret = devm_clk_hw_register(dev, &factor->hw);
if (ret)
return ret;
}
return 0;
}
int qcom_cc_register_board_clk(struct device *dev, const char *path,
const char *name, unsigned long rate)
{
bool add_factor = true;
/*
* TODO: The RPM clock driver currently does not support the xo clock.
* When xo is added to the RPM clock driver, we should change this
* function to skip registration of xo factor clocks.
*/
return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor);
}
EXPORT_SYMBOL_GPL(qcom_cc_register_board_clk);
int qcom_cc_register_sleep_clk(struct device *dev)
{
return _qcom_cc_register_board_clk(dev, "sleep_clk", "sleep_clk_src",
32768, true);
}
EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);
/* Drop 'protected-clocks' from the list of clocks to register */
static void qcom_cc_drop_protected(struct device *dev, struct qcom_cc *cc)
{
struct device_node *np = dev->of_node;
struct property *prop;
const __be32 *p;
u32 i;
of_property_for_each_u32(np, "protected-clocks", prop, p, i) {
if (i >= cc->num_rclks)
continue;
cc->rclks[i] = NULL;
}
}
static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec,
void *data)
{
struct qcom_cc *cc = data;
unsigned int idx = clkspec->args[0];
if (idx >= cc->num_rclks) {
pr_err("%s: invalid index %u\n", __func__, idx);
return ERR_PTR(-EINVAL);
}
return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL;
}
int qcom_cc_really_probe(struct platform_device *pdev,
const struct qcom_cc_desc *desc, struct regmap *regmap)
{
int i, ret;
struct device *dev = &pdev->dev;
struct qcom_reset_controller *reset;
struct qcom_cc *cc;
struct gdsc_desc *scd;
size_t num_clks = desc->num_clks;
struct clk_regmap **rclks = desc->clks;
size_t num_clk_hws = desc->num_clk_hws;
struct clk_hw **clk_hws = desc->clk_hws;
cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
if (!cc)
return -ENOMEM;
reset = &cc->reset;
reset->rcdev.of_node = dev->of_node;
reset->rcdev.ops = &qcom_reset_ops;
reset->rcdev.owner = dev->driver->owner;
reset->rcdev.nr_resets = desc->num_resets;
reset->regmap = regmap;
reset->reset_map = desc->resets;
ret = devm_reset_controller_register(dev, &reset->rcdev);
if (ret)
return ret;
if (desc->gdscs && desc->num_gdscs) {
scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL);
if (!scd)
return -ENOMEM;
scd->dev = dev;
scd->scs = desc->gdscs;
scd->num = desc->num_gdscs;
ret = gdsc_register(scd, &reset->rcdev, regmap);
if (ret)
return ret;
ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister,
scd);
if (ret)
return ret;
}
cc->rclks = rclks;
cc->num_rclks = num_clks;
qcom_cc_drop_protected(dev, cc);
for (i = 0; i < num_clk_hws; i++) {
ret = devm_clk_hw_register(dev, clk_hws[i]);
if (ret)
return ret;
}
for (i = 0; i < num_clks; i++) {
if (!rclks[i])
continue;
ret = devm_clk_register_regmap(dev, rclks[i]);
if (ret)
return ret;
}
ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc);
if (ret)
return ret;
return 0;
}
EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return qcom_cc_really_probe(pdev, desc, regmap);
}
EXPORT_SYMBOL_GPL(qcom_cc_probe);
int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
const struct qcom_cc_desc *desc)
{
struct regmap *regmap;
void __iomem *base;
base = devm_platform_ioremap_resource(pdev, index);
if (IS_ERR(base))
return -ENOMEM;
regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return qcom_cc_really_probe(pdev, desc, regmap);
}
EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index);
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/common.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include "clk-branch.h"
static bool clk_branch_in_hwcg_mode(const struct clk_branch *br)
{
u32 val;
if (!br->hwcg_reg)
return false;
regmap_read(br->clkr.regmap, br->hwcg_reg, &val);
return !!(val & BIT(br->hwcg_bit));
}
static bool clk_branch_check_halt(const struct clk_branch *br, bool enabling)
{
bool invert = (br->halt_check == BRANCH_HALT_ENABLE);
u32 val;
regmap_read(br->clkr.regmap, br->halt_reg, &val);
val &= BIT(br->halt_bit);
if (invert)
val = !val;
return !!val == !enabling;
}
static bool clk_branch2_check_halt(const struct clk_branch *br, bool enabling)
{
u32 val;
u32 mask;
bool invert = (br->halt_check == BRANCH_HALT_ENABLE);
mask = CBCR_NOC_FSM_STATUS;
mask |= CBCR_CLK_OFF;
regmap_read(br->clkr.regmap, br->halt_reg, &val);
if (enabling) {
val &= mask;
return (val & CBCR_CLK_OFF) == (invert ? CBCR_CLK_OFF : 0) ||
FIELD_GET(CBCR_NOC_FSM_STATUS, val) == FSM_STATUS_ON;
}
return (val & CBCR_CLK_OFF) == (invert ? 0 : CBCR_CLK_OFF);
}
static int clk_branch_wait(const struct clk_branch *br, bool enabling,
bool (check_halt)(const struct clk_branch *, bool))
{
bool voted = br->halt_check & BRANCH_VOTED;
const char *name = clk_hw_get_name(&br->clkr.hw);
/*
* Skip checking halt bit if we're explicitly ignoring the bit or the
* clock is in hardware gated mode
*/
if (br->halt_check == BRANCH_HALT_SKIP || clk_branch_in_hwcg_mode(br))
return 0;
if (br->halt_check == BRANCH_HALT_DELAY || (!enabling && voted)) {
udelay(10);
} else if (br->halt_check == BRANCH_HALT_ENABLE ||
br->halt_check == BRANCH_HALT ||
(enabling && voted)) {
int count = 200;
while (count-- > 0) {
if (check_halt(br, enabling))
return 0;
udelay(1);
}
WARN(1, "%s status stuck at 'o%s'", name,
enabling ? "ff" : "n");
return -EBUSY;
}
return 0;
}
static int clk_branch_toggle(struct clk_hw *hw, bool en,
bool (check_halt)(const struct clk_branch *, bool))
{
struct clk_branch *br = to_clk_branch(hw);
int ret;
if (en) {
ret = clk_enable_regmap(hw);
if (ret)
return ret;
} else {
clk_disable_regmap(hw);
}
return clk_branch_wait(br, en, check_halt);
}
static int clk_branch_enable(struct clk_hw *hw)
{
return clk_branch_toggle(hw, true, clk_branch_check_halt);
}
static void clk_branch_disable(struct clk_hw *hw)
{
clk_branch_toggle(hw, false, clk_branch_check_halt);
}
const struct clk_ops clk_branch_ops = {
.enable = clk_branch_enable,
.disable = clk_branch_disable,
.is_enabled = clk_is_enabled_regmap,
};
EXPORT_SYMBOL_GPL(clk_branch_ops);
static int clk_branch2_enable(struct clk_hw *hw)
{
return clk_branch_toggle(hw, true, clk_branch2_check_halt);
}
static void clk_branch2_disable(struct clk_hw *hw)
{
clk_branch_toggle(hw, false, clk_branch2_check_halt);
}
const struct clk_ops clk_branch2_ops = {
.enable = clk_branch2_enable,
.disable = clk_branch2_disable,
.is_enabled = clk_is_enabled_regmap,
};
EXPORT_SYMBOL_GPL(clk_branch2_ops);
const struct clk_ops clk_branch2_aon_ops = {
.enable = clk_branch2_enable,
.is_enabled = clk_is_enabled_regmap,
};
EXPORT_SYMBOL_GPL(clk_branch2_aon_ops);
const struct clk_ops clk_branch_simple_ops = {
.enable = clk_enable_regmap,
.disable = clk_disable_regmap,
.is_enabled = clk_is_enabled_regmap,
};
EXPORT_SYMBOL_GPL(clk_branch_simple_ops);
| linux-master | drivers/clk/qcom/clk-branch.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022, The Linux Foundation. All rights reserved.
* Copyright (c) 2022, Linaro Limited
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm6350-camcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "common.h"
#include "gdsc.h"
enum {
DT_BI_TCXO,
};
enum {
P_BI_TCXO,
P_CAMCC_PLL0_OUT_EVEN,
P_CAMCC_PLL0_OUT_MAIN,
P_CAMCC_PLL1_OUT_EVEN,
P_CAMCC_PLL1_OUT_MAIN,
P_CAMCC_PLL2_OUT_EARLY,
P_CAMCC_PLL2_OUT_MAIN,
P_CAMCC_PLL3_OUT_MAIN,
};
static struct pll_vco fabia_vco[] = {
{ 249600000, 2000000000, 0 },
};
/* 600MHz configuration */
static const struct alpha_pll_config camcc_pll0_config = {
.l = 0x1f,
.alpha = 0x4000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002067,
.test_ctl_val = 0x40000000,
.test_ctl_hi_val = 0x00000002,
.user_ctl_val = 0x00000101,
.user_ctl_hi_val = 0x00004805,
};
static struct clk_alpha_pll camcc_pll0 = {
.offset = 0x0,
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "camcc_pll0",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
};
static const struct clk_div_table post_div_table_camcc_pll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv camcc_pll0_out_even = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_camcc_pll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_camcc_pll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_pll0_out_even",
.parent_hws = (const struct clk_hw*[]){
&camcc_pll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
/* 808MHz configuration */
static const struct alpha_pll_config camcc_pll1_config = {
.l = 0x2a,
.alpha = 0x1555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002067,
.test_ctl_val = 0x40000000,
.test_ctl_hi_val = 0x00000000,
.user_ctl_val = 0x00000101,
.user_ctl_hi_val = 0x00004805,
};
static struct clk_alpha_pll camcc_pll1 = {
.offset = 0x1000,
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "camcc_pll1",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
};
static const struct clk_div_table post_div_table_camcc_pll1_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv camcc_pll1_out_even = {
.offset = 0x1000,
.post_div_shift = 8,
.post_div_table = post_div_table_camcc_pll1_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_camcc_pll1_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_pll1_out_even",
.parent_hws = (const struct clk_hw*[]){
&camcc_pll1.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
/* 1920MHz configuration */
static const struct alpha_pll_config camcc_pll2_config = {
.l = 0x64,
.alpha = 0x0,
.post_div_val = 0x3 << 8,
.post_div_mask = 0x3 << 8,
.aux_output_mask = BIT(1),
.main_output_mask = BIT(0),
.early_output_mask = BIT(3),
.config_ctl_val = 0x20000800,
.config_ctl_hi_val = 0x400003d2,
.test_ctl_val = 0x04000400,
.test_ctl_hi_val = 0x00004000,
};
static struct clk_alpha_pll camcc_pll2 = {
.offset = 0x2000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "camcc_pll2",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_agera_ops,
},
},
};
static struct clk_fixed_factor camcc_pll2_out_early = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "camcc_pll2_out_early",
.parent_hws = (const struct clk_hw*[]){
&camcc_pll2.clkr.hw,
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static const struct clk_div_table post_div_table_camcc_pll2_out_main[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv camcc_pll2_out_main = {
.offset = 0x2000,
.post_div_shift = 8,
.post_div_table = post_div_table_camcc_pll2_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_camcc_pll2_out_main),
.width = 2,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA],
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_pll2_out_main",
.parent_hws = (const struct clk_hw*[]){
&camcc_pll2.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_ops,
},
};
/* 384MHz configuration */
static const struct alpha_pll_config camcc_pll3_config = {
.l = 0x14,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002067,
.test_ctl_val = 0x40000000,
.test_ctl_hi_val = 0x00000002,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00014805,
};
static struct clk_alpha_pll camcc_pll3 = {
.offset = 0x3000,
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "camcc_pll3",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
};
static const struct parent_map camcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_CAMCC_PLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data camcc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &camcc_pll0_out_even.clkr.hw },
};
static const struct parent_map camcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_CAMCC_PLL0_OUT_MAIN, 1 },
{ P_CAMCC_PLL1_OUT_EVEN, 3 },
{ P_CAMCC_PLL2_OUT_MAIN, 4 },
};
static const struct clk_parent_data camcc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &camcc_pll0.clkr.hw },
{ .hw = &camcc_pll1_out_even.clkr.hw },
{ .hw = &camcc_pll2_out_main.clkr.hw },
};
static const struct parent_map camcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_CAMCC_PLL0_OUT_MAIN, 1 },
{ P_CAMCC_PLL3_OUT_MAIN, 5 },
};
static const struct clk_parent_data camcc_parent_data_2[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &camcc_pll0.clkr.hw },
{ .hw = &camcc_pll3.clkr.hw },
};
static const struct parent_map camcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_CAMCC_PLL2_OUT_EARLY, 3 },
};
static const struct clk_parent_data camcc_parent_data_3[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &camcc_pll2_out_early.hw },
};
static const struct parent_map camcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_CAMCC_PLL0_OUT_MAIN, 1 },
{ P_CAMCC_PLL1_OUT_EVEN, 3 },
};
static const struct clk_parent_data camcc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &camcc_pll0.clkr.hw },
{ .hw = &camcc_pll1_out_even.clkr.hw },
};
static const struct parent_map camcc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_CAMCC_PLL0_OUT_MAIN, 1 },
{ P_CAMCC_PLL1_OUT_EVEN, 3 },
{ P_CAMCC_PLL3_OUT_MAIN, 5 },
};
static const struct clk_parent_data camcc_parent_data_5[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &camcc_pll0.clkr.hw },
{ .hw = &camcc_pll1_out_even.clkr.hw },
{ .hw = &camcc_pll3.clkr.hw },
};
static const struct parent_map camcc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_CAMCC_PLL0_OUT_MAIN, 1 },
{ P_CAMCC_PLL2_OUT_MAIN, 4 },
};
static const struct clk_parent_data camcc_parent_data_6[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &camcc_pll0.clkr.hw },
{ .hw = &camcc_pll2_out_main.clkr.hw },
};
static const struct parent_map camcc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_CAMCC_PLL0_OUT_MAIN, 1 },
{ P_CAMCC_PLL1_OUT_MAIN, 2 },
{ P_CAMCC_PLL2_OUT_MAIN, 4 },
};
static const struct clk_parent_data camcc_parent_data_7[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &camcc_pll0.clkr.hw },
{ .hw = &camcc_pll1.clkr.hw },
{ .hw = &camcc_pll2_out_main.clkr.hw },
};
static const struct parent_map camcc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_CAMCC_PLL0_OUT_MAIN, 1 },
{ P_CAMCC_PLL1_OUT_MAIN, 2 },
};
static const struct clk_parent_data camcc_parent_data_8[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &camcc_pll0.clkr.hw },
{ .hw = &camcc_pll1.clkr.hw },
};
static const struct parent_map camcc_parent_map_9[] = {
{ P_BI_TCXO, 0 },
{ P_CAMCC_PLL2_OUT_MAIN, 4 },
};
static const struct clk_parent_data camcc_parent_data_9[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &camcc_pll2_out_main.clkr.hw },
};
static const struct freq_tbl ftbl_camcc_bps_clk_src[] = {
F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 camcc_bps_clk_src = {
.cmd_rcgr = 0x6010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = camcc_parent_map_1,
.freq_tbl = ftbl_camcc_bps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_bps_clk_src",
.parent_data = camcc_parent_data_1,
.num_parents = ARRAY_SIZE(camcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_camcc_cci_0_clk_src[] = {
F(37500000, P_CAMCC_PLL0_OUT_EVEN, 8, 0, 0),
F(50000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0),
{ }
};
static struct clk_rcg2 camcc_cci_0_clk_src = {
.cmd_rcgr = 0xf004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = camcc_parent_map_0,
.freq_tbl = ftbl_camcc_cci_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_cci_0_clk_src",
.parent_data = camcc_parent_data_0,
.num_parents = ARRAY_SIZE(camcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 camcc_cci_1_clk_src = {
.cmd_rcgr = 0x10004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = camcc_parent_map_0,
.freq_tbl = ftbl_camcc_cci_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_cci_1_clk_src",
.parent_data = camcc_parent_data_0,
.num_parents = ARRAY_SIZE(camcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_camcc_cphy_rx_clk_src[] = {
F(150000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0),
F(300000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
F(384000000, P_CAMCC_PLL3_OUT_MAIN, 1, 0, 0),
F(400000000, P_CAMCC_PLL0_OUT_MAIN, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 camcc_cphy_rx_clk_src = {
.cmd_rcgr = 0x9064,
.mnd_width = 0,
.hid_width = 5,
.parent_map = camcc_parent_map_2,
.freq_tbl = ftbl_camcc_cphy_rx_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_cphy_rx_clk_src",
.parent_data = camcc_parent_data_2,
.num_parents = ARRAY_SIZE(camcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_camcc_csi0phytimer_clk_src[] = {
F(300000000, P_CAMCC_PLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 camcc_csi0phytimer_clk_src = {
.cmd_rcgr = 0x5004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = camcc_parent_map_0,
.freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_csi0phytimer_clk_src",
.parent_data = camcc_parent_data_0,
.num_parents = ARRAY_SIZE(camcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 camcc_csi1phytimer_clk_src = {
.cmd_rcgr = 0x5028,
.mnd_width = 0,
.hid_width = 5,
.parent_map = camcc_parent_map_0,
.freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_csi1phytimer_clk_src",
.parent_data = camcc_parent_data_0,
.num_parents = ARRAY_SIZE(camcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 camcc_csi2phytimer_clk_src = {
.cmd_rcgr = 0x504c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = camcc_parent_map_0,
.freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_csi2phytimer_clk_src",
.parent_data = camcc_parent_data_0,
.num_parents = ARRAY_SIZE(camcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 camcc_csi3phytimer_clk_src = {
.cmd_rcgr = 0x5070,
.mnd_width = 0,
.hid_width = 5,
.parent_map = camcc_parent_map_0,
.freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_csi3phytimer_clk_src",
.parent_data = camcc_parent_data_0,
.num_parents = ARRAY_SIZE(camcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_camcc_fast_ahb_clk_src[] = {
F(100000000, P_CAMCC_PLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
F(300000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 camcc_fast_ahb_clk_src = {
.cmd_rcgr = 0x603c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = camcc_parent_map_4,
.freq_tbl = ftbl_camcc_fast_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_fast_ahb_clk_src",
.parent_data = camcc_parent_data_4,
.num_parents = ARRAY_SIZE(camcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_camcc_icp_clk_src[] = {
F(240000000, P_CAMCC_PLL0_OUT_MAIN, 2.5, 0, 0),
F(384000000, P_CAMCC_PLL3_OUT_MAIN, 1, 0, 0),
F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 camcc_icp_clk_src = {
.cmd_rcgr = 0xe014,
.mnd_width = 0,
.hid_width = 5,
.parent_map = camcc_parent_map_5,
.freq_tbl = ftbl_camcc_icp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_icp_clk_src",
.parent_data = camcc_parent_data_5,
.num_parents = ARRAY_SIZE(camcc_parent_data_5),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_camcc_ife_0_clk_src[] = {
F(240000000, P_CAMCC_PLL0_OUT_MAIN, 2.5, 0, 0),
F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 camcc_ife_0_clk_src = {
.cmd_rcgr = 0x9010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = camcc_parent_map_1,
.freq_tbl = ftbl_camcc_ife_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_ife_0_clk_src",
.parent_data = camcc_parent_data_1,
.num_parents = ARRAY_SIZE(camcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 camcc_ife_0_csid_clk_src = {
.cmd_rcgr = 0x903c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = camcc_parent_map_2,
.freq_tbl = ftbl_camcc_cphy_rx_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_ife_0_csid_clk_src",
.parent_data = camcc_parent_data_2,
.num_parents = ARRAY_SIZE(camcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 camcc_ife_1_clk_src = {
.cmd_rcgr = 0xa010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = camcc_parent_map_1,
.freq_tbl = ftbl_camcc_ife_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_ife_1_clk_src",
.parent_data = camcc_parent_data_1,
.num_parents = ARRAY_SIZE(camcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 camcc_ife_1_csid_clk_src = {
.cmd_rcgr = 0xa034,
.mnd_width = 0,
.hid_width = 5,
.parent_map = camcc_parent_map_2,
.freq_tbl = ftbl_camcc_cphy_rx_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_ife_1_csid_clk_src",
.parent_data = camcc_parent_data_2,
.num_parents = ARRAY_SIZE(camcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 camcc_ife_2_clk_src = {
.cmd_rcgr = 0xb00c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = camcc_parent_map_1,
.freq_tbl = ftbl_camcc_ife_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_ife_2_clk_src",
.parent_data = camcc_parent_data_1,
.num_parents = ARRAY_SIZE(camcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 camcc_ife_2_csid_clk_src = {
.cmd_rcgr = 0xb030,
.mnd_width = 0,
.hid_width = 5,
.parent_map = camcc_parent_map_2,
.freq_tbl = ftbl_camcc_cphy_rx_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_ife_2_csid_clk_src",
.parent_data = camcc_parent_data_2,
.num_parents = ARRAY_SIZE(camcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_camcc_ife_lite_clk_src[] = {
F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
F(400000000, P_CAMCC_PLL0_OUT_MAIN, 1.5, 0, 0),
F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 camcc_ife_lite_clk_src = {
.cmd_rcgr = 0xc004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = camcc_parent_map_6,
.freq_tbl = ftbl_camcc_ife_lite_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_ife_lite_clk_src",
.parent_data = camcc_parent_data_6,
.num_parents = ARRAY_SIZE(camcc_parent_data_6),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 camcc_ife_lite_csid_clk_src = {
.cmd_rcgr = 0xc024,
.mnd_width = 0,
.hid_width = 5,
.parent_map = camcc_parent_map_2,
.freq_tbl = ftbl_camcc_cphy_rx_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_ife_lite_csid_clk_src",
.parent_data = camcc_parent_data_2,
.num_parents = ARRAY_SIZE(camcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_camcc_ipe_0_clk_src[] = {
F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0),
F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
F(404000000, P_CAMCC_PLL1_OUT_MAIN, 2, 0, 0),
F(538666667, P_CAMCC_PLL1_OUT_MAIN, 1.5, 0, 0),
F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 camcc_ipe_0_clk_src = {
.cmd_rcgr = 0x7010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = camcc_parent_map_7,
.freq_tbl = ftbl_camcc_ipe_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_ipe_0_clk_src",
.parent_data = camcc_parent_data_7,
.num_parents = ARRAY_SIZE(camcc_parent_data_7),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_camcc_jpeg_clk_src[] = {
F(66666667, P_CAMCC_PLL0_OUT_MAIN, 9, 0, 0),
F(133333333, P_CAMCC_PLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 camcc_jpeg_clk_src = {
.cmd_rcgr = 0xd004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = camcc_parent_map_1,
.freq_tbl = ftbl_camcc_jpeg_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_jpeg_clk_src",
.parent_data = camcc_parent_data_1,
.num_parents = ARRAY_SIZE(camcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_camcc_lrme_clk_src[] = {
F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
F(269333333, P_CAMCC_PLL1_OUT_MAIN, 3, 0, 0),
F(323200000, P_CAMCC_PLL1_OUT_MAIN, 2.5, 0, 0),
F(404000000, P_CAMCC_PLL1_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 camcc_lrme_clk_src = {
.cmd_rcgr = 0x11004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = camcc_parent_map_8,
.freq_tbl = ftbl_camcc_lrme_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_lrme_clk_src",
.parent_data = camcc_parent_data_8,
.num_parents = ARRAY_SIZE(camcc_parent_data_8),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_camcc_mclk0_clk_src[] = {
F(19200000, P_CAMCC_PLL2_OUT_EARLY, 1, 1, 50),
F(24000000, P_CAMCC_PLL2_OUT_EARLY, 10, 1, 4),
F(64000000, P_CAMCC_PLL2_OUT_EARLY, 15, 0, 0),
{ }
};
static struct clk_rcg2 camcc_mclk0_clk_src = {
.cmd_rcgr = 0x4004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = camcc_parent_map_3,
.freq_tbl = ftbl_camcc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_mclk0_clk_src",
.parent_data = camcc_parent_data_3,
.num_parents = ARRAY_SIZE(camcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 camcc_mclk1_clk_src = {
.cmd_rcgr = 0x4024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = camcc_parent_map_3,
.freq_tbl = ftbl_camcc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_mclk1_clk_src",
.parent_data = camcc_parent_data_3,
.num_parents = ARRAY_SIZE(camcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 camcc_mclk2_clk_src = {
.cmd_rcgr = 0x4044,
.mnd_width = 8,
.hid_width = 5,
.parent_map = camcc_parent_map_3,
.freq_tbl = ftbl_camcc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_mclk2_clk_src",
.parent_data = camcc_parent_data_3,
.num_parents = ARRAY_SIZE(camcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 camcc_mclk3_clk_src = {
.cmd_rcgr = 0x4064,
.mnd_width = 8,
.hid_width = 5,
.parent_map = camcc_parent_map_3,
.freq_tbl = ftbl_camcc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_mclk3_clk_src",
.parent_data = camcc_parent_data_3,
.num_parents = ARRAY_SIZE(camcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 camcc_mclk4_clk_src = {
.cmd_rcgr = 0x4084,
.mnd_width = 8,
.hid_width = 5,
.parent_map = camcc_parent_map_3,
.freq_tbl = ftbl_camcc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_mclk4_clk_src",
.parent_data = camcc_parent_data_3,
.num_parents = ARRAY_SIZE(camcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_camcc_slow_ahb_clk_src[] = {
F(80000000, P_CAMCC_PLL2_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 camcc_slow_ahb_clk_src = {
.cmd_rcgr = 0x6058,
.mnd_width = 0,
.hid_width = 5,
.parent_map = camcc_parent_map_9,
.freq_tbl = ftbl_camcc_slow_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "camcc_slow_ahb_clk_src",
.parent_data = camcc_parent_data_9,
.num_parents = ARRAY_SIZE(camcc_parent_data_9),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch camcc_bps_ahb_clk = {
.halt_reg = 0x6070,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6070,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_bps_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_slow_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_bps_areg_clk = {
.halt_reg = 0x6054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_bps_areg_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_fast_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_bps_axi_clk = {
.halt_reg = 0x6038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_bps_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_bps_clk = {
.halt_reg = 0x6028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_bps_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_bps_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_camnoc_axi_clk = {
.halt_reg = 0x13004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_camnoc_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_cci_0_clk = {
.halt_reg = 0xf01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_cci_0_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_cci_0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_cci_1_clk = {
.halt_reg = 0x1001c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1001c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_cci_1_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_cci_1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_core_ahb_clk = {
.halt_reg = 0x14010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x14010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_core_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_slow_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_cpas_ahb_clk = {
.halt_reg = 0x12004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_cpas_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_slow_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_csi0phytimer_clk = {
.halt_reg = 0x501c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_csi0phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_csi0phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_csi1phytimer_clk = {
.halt_reg = 0x5040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_csi1phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_csi1phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_csi2phytimer_clk = {
.halt_reg = 0x5064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_csi2phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_csi2phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_csi3phytimer_clk = {
.halt_reg = 0x5088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_csi3phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_csi3phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_csiphy0_clk = {
.halt_reg = 0x5020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_csiphy0_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_cphy_rx_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_csiphy1_clk = {
.halt_reg = 0x5044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_csiphy1_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_cphy_rx_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_csiphy2_clk = {
.halt_reg = 0x5068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_csiphy2_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_cphy_rx_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_csiphy3_clk = {
.halt_reg = 0x508c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x508c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_csiphy3_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_cphy_rx_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_icp_clk = {
.halt_reg = 0xe02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_icp_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_icp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_icp_ts_clk = {
.halt_reg = 0xe00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_icp_ts_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ife_0_axi_clk = {
.halt_reg = 0x9080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ife_0_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ife_0_clk = {
.halt_reg = 0x9028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ife_0_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_ife_0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ife_0_cphy_rx_clk = {
.halt_reg = 0x907c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x907c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ife_0_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_cphy_rx_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ife_0_csid_clk = {
.halt_reg = 0x9054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ife_0_csid_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_ife_0_csid_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ife_0_dsp_clk = {
.halt_reg = 0x9038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ife_0_dsp_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_ife_0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ife_1_axi_clk = {
.halt_reg = 0xa058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ife_1_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ife_1_clk = {
.halt_reg = 0xa028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ife_1_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_ife_1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ife_1_cphy_rx_clk = {
.halt_reg = 0xa054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ife_1_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_cphy_rx_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ife_1_csid_clk = {
.halt_reg = 0xa04c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa04c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ife_1_csid_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_ife_1_csid_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ife_1_dsp_clk = {
.halt_reg = 0xa030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ife_1_dsp_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_ife_1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ife_2_axi_clk = {
.halt_reg = 0xb054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ife_2_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ife_2_clk = {
.halt_reg = 0xb024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ife_2_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_ife_2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ife_2_cphy_rx_clk = {
.halt_reg = 0xb050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ife_2_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_cphy_rx_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ife_2_csid_clk = {
.halt_reg = 0xb048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ife_2_csid_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_ife_2_csid_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ife_2_dsp_clk = {
.halt_reg = 0xb02c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ife_2_dsp_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_ife_2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ife_lite_clk = {
.halt_reg = 0xc01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ife_lite_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_ife_lite_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ife_lite_cphy_rx_clk = {
.halt_reg = 0xc044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ife_lite_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_cphy_rx_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ife_lite_csid_clk = {
.halt_reg = 0xc03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ife_lite_csid_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_ife_lite_csid_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ipe_0_ahb_clk = {
.halt_reg = 0x7040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ipe_0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_slow_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ipe_0_areg_clk = {
.halt_reg = 0x703c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x703c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ipe_0_areg_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_fast_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ipe_0_axi_clk = {
.halt_reg = 0x7038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ipe_0_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_ipe_0_clk = {
.halt_reg = 0x7028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_ipe_0_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_ipe_0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_jpeg_clk = {
.halt_reg = 0xd01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xd01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_jpeg_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_jpeg_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_lrme_clk = {
.halt_reg = 0x1101c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1101c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_lrme_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_lrme_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_mclk0_clk = {
.halt_reg = 0x401c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x401c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_mclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_mclk0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_mclk1_clk = {
.halt_reg = 0x403c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x403c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_mclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_mclk1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_mclk2_clk = {
.halt_reg = 0x405c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x405c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_mclk2_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_mclk2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_mclk3_clk = {
.halt_reg = 0x407c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x407c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_mclk3_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_mclk3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_mclk4_clk = {
.halt_reg = 0x409c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x409c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_mclk4_clk",
.parent_hws = (const struct clk_hw*[]){
&camcc_mclk4_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_soc_ahb_clk = {
.halt_reg = 0x1400c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1400c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_soc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camcc_sys_tmr_clk = {
.halt_reg = 0xe034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camcc_sys_tmr_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc bps_gdsc = {
.gdscr = 0x6004,
.pd = {
.name = "bps_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc ipe_0_gdsc = {
.gdscr = 0x7004,
.pd = {
.name = "ipe_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc ife_0_gdsc = {
.gdscr = 0x9004,
.pd = {
.name = "ife_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ife_1_gdsc = {
.gdscr = 0xa004,
.pd = {
.name = "ife_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ife_2_gdsc = {
.gdscr = 0xb004,
.pd = {
.name = "ife_2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc titan_top_gdsc = {
.gdscr = 0x14004,
.pd = {
.name = "titan_top_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_hw *camcc_sm6350_hws[] = {
[CAMCC_PLL2_OUT_EARLY] = &camcc_pll2_out_early.hw,
};
static struct clk_regmap *camcc_sm6350_clocks[] = {
[CAMCC_BPS_AHB_CLK] = &camcc_bps_ahb_clk.clkr,
[CAMCC_BPS_AREG_CLK] = &camcc_bps_areg_clk.clkr,
[CAMCC_BPS_AXI_CLK] = &camcc_bps_axi_clk.clkr,
[CAMCC_BPS_CLK] = &camcc_bps_clk.clkr,
[CAMCC_BPS_CLK_SRC] = &camcc_bps_clk_src.clkr,
[CAMCC_CAMNOC_AXI_CLK] = &camcc_camnoc_axi_clk.clkr,
[CAMCC_CCI_0_CLK] = &camcc_cci_0_clk.clkr,
[CAMCC_CCI_0_CLK_SRC] = &camcc_cci_0_clk_src.clkr,
[CAMCC_CCI_1_CLK] = &camcc_cci_1_clk.clkr,
[CAMCC_CCI_1_CLK_SRC] = &camcc_cci_1_clk_src.clkr,
[CAMCC_CORE_AHB_CLK] = &camcc_core_ahb_clk.clkr,
[CAMCC_CPAS_AHB_CLK] = &camcc_cpas_ahb_clk.clkr,
[CAMCC_CPHY_RX_CLK_SRC] = &camcc_cphy_rx_clk_src.clkr,
[CAMCC_CSI0PHYTIMER_CLK] = &camcc_csi0phytimer_clk.clkr,
[CAMCC_CSI0PHYTIMER_CLK_SRC] = &camcc_csi0phytimer_clk_src.clkr,
[CAMCC_CSI1PHYTIMER_CLK] = &camcc_csi1phytimer_clk.clkr,
[CAMCC_CSI1PHYTIMER_CLK_SRC] = &camcc_csi1phytimer_clk_src.clkr,
[CAMCC_CSI2PHYTIMER_CLK] = &camcc_csi2phytimer_clk.clkr,
[CAMCC_CSI2PHYTIMER_CLK_SRC] = &camcc_csi2phytimer_clk_src.clkr,
[CAMCC_CSI3PHYTIMER_CLK] = &camcc_csi3phytimer_clk.clkr,
[CAMCC_CSI3PHYTIMER_CLK_SRC] = &camcc_csi3phytimer_clk_src.clkr,
[CAMCC_CSIPHY0_CLK] = &camcc_csiphy0_clk.clkr,
[CAMCC_CSIPHY1_CLK] = &camcc_csiphy1_clk.clkr,
[CAMCC_CSIPHY2_CLK] = &camcc_csiphy2_clk.clkr,
[CAMCC_CSIPHY3_CLK] = &camcc_csiphy3_clk.clkr,
[CAMCC_FAST_AHB_CLK_SRC] = &camcc_fast_ahb_clk_src.clkr,
[CAMCC_ICP_CLK] = &camcc_icp_clk.clkr,
[CAMCC_ICP_CLK_SRC] = &camcc_icp_clk_src.clkr,
[CAMCC_ICP_TS_CLK] = &camcc_icp_ts_clk.clkr,
[CAMCC_IFE_0_AXI_CLK] = &camcc_ife_0_axi_clk.clkr,
[CAMCC_IFE_0_CLK] = &camcc_ife_0_clk.clkr,
[CAMCC_IFE_0_CLK_SRC] = &camcc_ife_0_clk_src.clkr,
[CAMCC_IFE_0_CPHY_RX_CLK] = &camcc_ife_0_cphy_rx_clk.clkr,
[CAMCC_IFE_0_CSID_CLK] = &camcc_ife_0_csid_clk.clkr,
[CAMCC_IFE_0_CSID_CLK_SRC] = &camcc_ife_0_csid_clk_src.clkr,
[CAMCC_IFE_0_DSP_CLK] = &camcc_ife_0_dsp_clk.clkr,
[CAMCC_IFE_1_AXI_CLK] = &camcc_ife_1_axi_clk.clkr,
[CAMCC_IFE_1_CLK] = &camcc_ife_1_clk.clkr,
[CAMCC_IFE_1_CLK_SRC] = &camcc_ife_1_clk_src.clkr,
[CAMCC_IFE_1_CPHY_RX_CLK] = &camcc_ife_1_cphy_rx_clk.clkr,
[CAMCC_IFE_1_CSID_CLK] = &camcc_ife_1_csid_clk.clkr,
[CAMCC_IFE_1_CSID_CLK_SRC] = &camcc_ife_1_csid_clk_src.clkr,
[CAMCC_IFE_1_DSP_CLK] = &camcc_ife_1_dsp_clk.clkr,
[CAMCC_IFE_2_AXI_CLK] = &camcc_ife_2_axi_clk.clkr,
[CAMCC_IFE_2_CLK] = &camcc_ife_2_clk.clkr,
[CAMCC_IFE_2_CLK_SRC] = &camcc_ife_2_clk_src.clkr,
[CAMCC_IFE_2_CPHY_RX_CLK] = &camcc_ife_2_cphy_rx_clk.clkr,
[CAMCC_IFE_2_CSID_CLK] = &camcc_ife_2_csid_clk.clkr,
[CAMCC_IFE_2_CSID_CLK_SRC] = &camcc_ife_2_csid_clk_src.clkr,
[CAMCC_IFE_2_DSP_CLK] = &camcc_ife_2_dsp_clk.clkr,
[CAMCC_IFE_LITE_CLK] = &camcc_ife_lite_clk.clkr,
[CAMCC_IFE_LITE_CLK_SRC] = &camcc_ife_lite_clk_src.clkr,
[CAMCC_IFE_LITE_CPHY_RX_CLK] = &camcc_ife_lite_cphy_rx_clk.clkr,
[CAMCC_IFE_LITE_CSID_CLK] = &camcc_ife_lite_csid_clk.clkr,
[CAMCC_IFE_LITE_CSID_CLK_SRC] = &camcc_ife_lite_csid_clk_src.clkr,
[CAMCC_IPE_0_AHB_CLK] = &camcc_ipe_0_ahb_clk.clkr,
[CAMCC_IPE_0_AREG_CLK] = &camcc_ipe_0_areg_clk.clkr,
[CAMCC_IPE_0_AXI_CLK] = &camcc_ipe_0_axi_clk.clkr,
[CAMCC_IPE_0_CLK] = &camcc_ipe_0_clk.clkr,
[CAMCC_IPE_0_CLK_SRC] = &camcc_ipe_0_clk_src.clkr,
[CAMCC_JPEG_CLK] = &camcc_jpeg_clk.clkr,
[CAMCC_JPEG_CLK_SRC] = &camcc_jpeg_clk_src.clkr,
[CAMCC_LRME_CLK] = &camcc_lrme_clk.clkr,
[CAMCC_LRME_CLK_SRC] = &camcc_lrme_clk_src.clkr,
[CAMCC_MCLK0_CLK] = &camcc_mclk0_clk.clkr,
[CAMCC_MCLK0_CLK_SRC] = &camcc_mclk0_clk_src.clkr,
[CAMCC_MCLK1_CLK] = &camcc_mclk1_clk.clkr,
[CAMCC_MCLK1_CLK_SRC] = &camcc_mclk1_clk_src.clkr,
[CAMCC_MCLK2_CLK] = &camcc_mclk2_clk.clkr,
[CAMCC_MCLK2_CLK_SRC] = &camcc_mclk2_clk_src.clkr,
[CAMCC_MCLK3_CLK] = &camcc_mclk3_clk.clkr,
[CAMCC_MCLK3_CLK_SRC] = &camcc_mclk3_clk_src.clkr,
[CAMCC_MCLK4_CLK] = &camcc_mclk4_clk.clkr,
[CAMCC_MCLK4_CLK_SRC] = &camcc_mclk4_clk_src.clkr,
[CAMCC_PLL0] = &camcc_pll0.clkr,
[CAMCC_PLL0_OUT_EVEN] = &camcc_pll0_out_even.clkr,
[CAMCC_PLL1] = &camcc_pll1.clkr,
[CAMCC_PLL1_OUT_EVEN] = &camcc_pll1_out_even.clkr,
[CAMCC_PLL2] = &camcc_pll2.clkr,
[CAMCC_PLL2_OUT_MAIN] = &camcc_pll2_out_main.clkr,
[CAMCC_PLL3] = &camcc_pll3.clkr,
[CAMCC_SLOW_AHB_CLK_SRC] = &camcc_slow_ahb_clk_src.clkr,
[CAMCC_SOC_AHB_CLK] = &camcc_soc_ahb_clk.clkr,
[CAMCC_SYS_TMR_CLK] = &camcc_sys_tmr_clk.clkr,
};
static struct gdsc *camcc_sm6350_gdscs[] = {
[BPS_GDSC] = &bps_gdsc,
[IPE_0_GDSC] = &ipe_0_gdsc,
[IFE_0_GDSC] = &ife_0_gdsc,
[IFE_1_GDSC] = &ife_1_gdsc,
[IFE_2_GDSC] = &ife_2_gdsc,
[TITAN_TOP_GDSC] = &titan_top_gdsc,
};
static const struct regmap_config camcc_sm6350_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x16000,
.fast_io = true,
};
static const struct qcom_cc_desc camcc_sm6350_desc = {
.config = &camcc_sm6350_regmap_config,
.clk_hws = camcc_sm6350_hws,
.num_clk_hws = ARRAY_SIZE(camcc_sm6350_hws),
.clks = camcc_sm6350_clocks,
.num_clks = ARRAY_SIZE(camcc_sm6350_clocks),
.gdscs = camcc_sm6350_gdscs,
.num_gdscs = ARRAY_SIZE(camcc_sm6350_gdscs),
};
static const struct of_device_id camcc_sm6350_match_table[] = {
{ .compatible = "qcom,sm6350-camcc" },
{ }
};
MODULE_DEVICE_TABLE(of, camcc_sm6350_match_table);
static int camcc_sm6350_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &camcc_sm6350_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_fabia_pll_configure(&camcc_pll0, regmap, &camcc_pll0_config);
clk_fabia_pll_configure(&camcc_pll1, regmap, &camcc_pll1_config);
clk_agera_pll_configure(&camcc_pll2, regmap, &camcc_pll2_config);
clk_fabia_pll_configure(&camcc_pll3, regmap, &camcc_pll3_config);
return qcom_cc_really_probe(pdev, &camcc_sm6350_desc, regmap);
}
static struct platform_driver camcc_sm6350_driver = {
.probe = camcc_sm6350_probe,
.driver = {
.name = "sm6350-camcc",
.of_match_table = camcc_sm6350_match_table,
},
};
static int __init camcc_sm6350_init(void)
{
return platform_driver_register(&camcc_sm6350_driver);
}
subsys_initcall(camcc_sm6350_init);
static void __exit camcc_sm6350_exit(void)
{
platform_driver_unregister(&camcc_sm6350_driver);
}
module_exit(camcc_sm6350_exit);
MODULE_DESCRIPTION("QTI CAMCC SM6350 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/camcc-sm6350.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm8450-gpucc.h>
#include <dt-bindings/reset/qcom,sm8450-gpucc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_GPLL0_OUT_MAIN,
DT_GPLL0_OUT_MAIN_DIV,
};
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL1_OUT_MAIN,
};
static struct pll_vco lucid_evo_vco[] = {
{ 249600000, 2000000000, 0 },
};
static struct alpha_pll_config gpu_cc_pll0_config = {
.l = 0x1d,
.alpha = 0xb000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static struct alpha_pll_config gpu_cc_pll1_config = {
.l = 0x34,
.alpha = 0x1555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct parent_map gpu_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct parent_map gpu_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gpu_cc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
};
static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_ff_clk_src = {
.cmd_rcgr = 0x9474,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_ff_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x9318,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_1,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_hub_clk_src = {
.cmd_rcgr = 0x93ec,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_2,
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_hub_clk_src",
.parent_data = gpu_cc_parent_data_2,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_xo_clk_src = {
.cmd_rcgr = 0x9010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_3,
.freq_tbl = ftbl_gpu_cc_xo_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_xo_clk_src",
.parent_data = gpu_cc_parent_data_3,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
.reg = 0x9054,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gpu_cc_demet_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
.reg = 0x9430,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gpu_cc_hub_ahb_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
.reg = 0x942c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gpu_cc_hub_cx_int_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gpu_cc_xo_div_clk_src = {
.reg = 0x9050,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gpu_cc_xo_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x911c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x911c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x9120,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9120,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_crc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_apb_clk = {
.halt_reg = 0x912c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x912c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_apb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_ff_clk = {
.halt_reg = 0x914c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x914c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_ff_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_ff_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x913c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x913c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
.halt_reg = 0x9130,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9130,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_snoc_dvm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_aon_clk = {
.halt_reg = 0x9004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_aon_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x9144,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9144,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_demet_clk = {
.halt_reg = 0x900c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x900c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_demet_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_demet_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_freq_measure_clk = {
.halt_reg = 0x9008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_freq_measure_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_ff_clk = {
.halt_reg = 0x90c0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x90c0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_ff_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_ff_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gfx3d_clk = {
.halt_reg = 0x90a8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x90a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gfx3d_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gfx3d_rdvm_clk = {
.halt_reg = 0x90c8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x90c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gfx3d_rdvm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gmu_clk = {
.halt_reg = 0x90bc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x90bc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gmu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_vsense_clk = {
.halt_reg = 0x90b0,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x90b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_vsense_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
.halt_reg = 0x7000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hub_aon_clk = {
.halt_reg = 0x93e8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x93e8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_hub_aon_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_hub_cx_int_clk = {
.halt_reg = 0x9148,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9148,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_hub_cx_int_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_memnoc_gfx_clk = {
.halt_reg = 0x9150,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9150,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
.halt_reg = 0x9288,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9288,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_mnd1x_0_gfx3d_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
.halt_reg = 0x928c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x928c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_mnd1x_1_gfx3d_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_sleep_clk = {
.halt_reg = 0x9134,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9134,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x9108,
.gds_hw_ctrl = 0x953c,
.clk_dis_wait_val = 8,
.pd = {
.name = "gpu_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x905c,
.clamp_io_ctrl = 0x9504,
.resets = (unsigned int []){ GPUCC_GPU_CC_GX_BCR,
GPUCC_GPU_CC_ACD_BCR,
GPUCC_GPU_CC_GX_ACD_IROOT_BCR },
.reset_count = 3,
.pd = {
.name = "gpu_gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
};
static struct clk_regmap *gpu_cc_sm8450_clocks[] = {
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr,
[GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_GX_FF_CLK] = &gpu_cc_gx_ff_clk.clkr,
[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
[GPU_CC_GX_GFX3D_RDVM_CLK] = &gpu_cc_gx_gfx3d_rdvm_clk.clkr,
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
[GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
[GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
[GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
[GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
[GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
[GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
[GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr,
};
static const struct qcom_reset_map gpu_cc_sm8450_resets[] = {
[GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
[GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
[GPUCC_GPU_CC_CX_BCR] = { 0x9104 },
[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
[GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },
[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
[GPUCC_GPU_CC_FF_BCR] = { 0x9470 },
[GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
[GPUCC_GPU_CC_GX_ACD_IROOT_BCR] = { 0x958c },
};
static struct gdsc *gpu_cc_sm8450_gdscs[] = {
[GPU_CX_GDSC] = &gpu_cx_gdsc,
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
static const struct regmap_config gpu_cc_sm8450_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xa000,
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_sm8450_desc = {
.config = &gpu_cc_sm8450_regmap_config,
.clks = gpu_cc_sm8450_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sm8450_clocks),
.resets = gpu_cc_sm8450_resets,
.num_resets = ARRAY_SIZE(gpu_cc_sm8450_resets),
.gdscs = gpu_cc_sm8450_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sm8450_gdscs),
};
static const struct of_device_id gpu_cc_sm8450_match_table[] = {
{ .compatible = "qcom,sm8450-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sm8450_match_table);
static int gpu_cc_sm8450_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gpu_cc_sm8450_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
return qcom_cc_really_probe(pdev, &gpu_cc_sm8450_desc, regmap);
}
static struct platform_driver gpu_cc_sm8450_driver = {
.probe = gpu_cc_sm8450_probe,
.driver = {
.name = "sm8450-gpucc",
.of_match_table = gpu_cc_sm8450_match_table,
},
};
module_platform_driver(gpu_cc_sm8450_driver);
MODULE_DESCRIPTION("QTI GPU_CC SM8450 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/gpucc-sm8450.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, Konrad Dybcio <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-sm6125.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_GPLL0_OUT_AUX2,
P_GPLL0_OUT_EARLY,
P_GPLL3_OUT_EARLY,
P_GPLL4_OUT_MAIN,
P_GPLL5_OUT_MAIN,
P_GPLL6_OUT_EARLY,
P_GPLL6_OUT_MAIN,
P_GPLL7_OUT_MAIN,
P_GPLL8_OUT_EARLY,
P_GPLL8_OUT_MAIN,
P_GPLL9_OUT_MAIN,
P_SLEEP_CLK,
};
static struct clk_alpha_pll gpll0_out_early = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_out_early",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_fixed_factor gpll0_out_aux2 = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "gpll0_out_aux2",
.parent_hws = (const struct clk_hw*[]){
&gpll0_out_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_fixed_factor gpll0_out_main = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "gpll0_out_main",
.parent_hws = (const struct clk_hw*[]){
&gpll0_out_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_alpha_pll gpll3_out_early = {
.offset = 0x3000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gpll3_out_early",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll gpll4_out_main = {
.offset = 0x4000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gpll4_out_main",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll gpll5_out_main = {
.offset = 0x5000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gpll5_out_main",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll gpll6_out_early = {
.offset = 0x6000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gpll6_out_early",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_fixed_factor gpll6_out_main = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "gpll6_out_main",
.parent_hws = (const struct clk_hw*[]){
&gpll6_out_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_alpha_pll gpll7_out_early = {
.offset = 0x7000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gpll7_out_early",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_fixed_factor gpll7_out_main = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "gpll7_out_main",
.parent_hws = (const struct clk_hw*[]){
&gpll7_out_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_alpha_pll gpll8_out_early = {
.offset = 0x8000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gpll8_out_early",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_fixed_factor gpll8_out_main = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "gpll8_out_main",
.parent_hws = (const struct clk_hw*[]){
&gpll8_out_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_alpha_pll gpll9_out_early = {
.offset = 0x9000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gpll9_out_early",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_fixed_factor gpll9_out_main = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "gpll9_out_main",
.parent_hws = (const struct clk_hw*[]){
&gpll9_out_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL0_OUT_AUX2, 2 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0_out_early.clkr.hw },
{ .hw = &gpll0_out_aux2.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL0_OUT_AUX2, 2 },
{ P_GPLL6_OUT_MAIN, 4 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0_out_early.clkr.hw },
{ .hw = &gpll0_out_aux2.hw },
{ .hw = &gpll6_out_main.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL0_OUT_AUX2, 2 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0_out_early.clkr.hw },
{ .hw = &gpll0_out_aux2.hw },
{ .fw_name = "sleep_clk" },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL5_OUT_MAIN, 3 },
{ P_GPLL4_OUT_MAIN, 5 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0_out_early.clkr.hw },
{ .hw = &gpll5_out_main.clkr.hw },
{ .hw = &gpll4_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL9_OUT_MAIN, 2 },
};
static const struct clk_parent_data gcc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0_out_early.clkr.hw },
{ .hw = &gpll9_out_main.hw },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0_out_early.clkr.hw },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL4_OUT_MAIN, 5 },
};
static const struct clk_parent_data gcc_parent_data_6[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0_out_early.clkr.hw },
{ .hw = &gpll4_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_7[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0_out_early.clkr.hw },
{ .fw_name = "sleep_clk" },
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL9_OUT_MAIN, 2 },
{ P_GPLL6_OUT_EARLY, 3 },
{ P_GPLL8_OUT_MAIN, 4 },
{ P_GPLL4_OUT_MAIN, 5 },
{ P_GPLL3_OUT_EARLY, 6 },
};
static const struct clk_parent_data gcc_parent_data_8[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0_out_early.clkr.hw },
{ .hw = &gpll9_out_main.hw },
{ .hw = &gpll6_out_early.clkr.hw },
{ .hw = &gpll8_out_main.hw },
{ .hw = &gpll4_out_main.clkr.hw },
{ .hw = &gpll3_out_early.clkr.hw },
};
static const struct parent_map gcc_parent_map_9[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL8_OUT_MAIN, 4 },
};
static const struct clk_parent_data gcc_parent_data_9[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0_out_early.clkr.hw },
{ .hw = &gpll8_out_main.hw },
};
static const struct parent_map gcc_parent_map_10[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL9_OUT_MAIN, 2 },
{ P_GPLL6_OUT_EARLY, 3 },
{ P_GPLL8_OUT_MAIN, 4 },
{ P_GPLL3_OUT_EARLY, 6 },
};
static const struct clk_parent_data gcc_parent_data_10[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0_out_early.clkr.hw },
{ .hw = &gpll9_out_main.hw },
{ .hw = &gpll6_out_early.clkr.hw },
{ .hw = &gpll8_out_main.hw },
{ .hw = &gpll3_out_early.clkr.hw },
};
static const struct parent_map gcc_parent_map_11[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL8_OUT_EARLY, 4 },
{ P_GPLL4_OUT_MAIN, 5 },
};
static const struct clk_parent_data gcc_parent_data_11[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0_out_early.clkr.hw },
{ .hw = &gpll8_out_early.clkr.hw },
{ .hw = &gpll4_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_12[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL6_OUT_EARLY, 3 },
{ P_GPLL8_OUT_EARLY, 4 },
};
static const struct clk_parent_data gcc_parent_data_12[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0_out_early.clkr.hw },
{ .hw = &gpll6_out_early.clkr.hw },
{ .hw = &gpll8_out_early.clkr.hw },
};
static const struct parent_map gcc_parent_map_13[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EARLY, 1 },
{ P_GPLL0_OUT_AUX2, 2 },
{ P_GPLL7_OUT_MAIN, 3 },
{ P_GPLL4_OUT_MAIN, 5 },
};
static const struct clk_parent_data gcc_parent_data_13[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0_out_early.clkr.hw },
{ .hw = &gpll0_out_aux2.hw },
{ .hw = &gpll7_out_main.hw },
{ .hw = &gpll4_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_14[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_14[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "sleep_clk" },
};
static const struct freq_tbl ftbl_gcc_camss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(40000000, P_GPLL8_OUT_MAIN, 12, 0, 0),
F(80000000, P_GPLL8_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_ahb_clk_src = {
.cmd_rcgr = 0x56088,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_9,
.freq_tbl = ftbl_gcc_camss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ahb_clk_src",
.parent_data = gcc_parent_data_9,
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = {
F(37500000, P_GPLL0_OUT_EARLY, 16, 0, 0),
F(50000000, P_GPLL0_OUT_EARLY, 12, 0, 0),
F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_cci_clk_src = {
.cmd_rcgr = 0x52004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_camss_cci_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_cpp_clk_src[] = {
F(120000000, P_GPLL8_OUT_MAIN, 4, 0, 0),
F(240000000, P_GPLL8_OUT_MAIN, 2, 0, 0),
F(320000000, P_GPLL8_OUT_MAIN, 1.5, 0, 0),
F(480000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_cpp_clk_src = {
.cmd_rcgr = 0x560c8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_10,
.freq_tbl = ftbl_gcc_camss_cpp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cpp_clk_src",
.parent_data = gcc_parent_data_10,
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_csi0_clk_src[] = {
F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
F(311000000, P_GPLL5_OUT_MAIN, 3, 0, 0),
F(403200000, P_GPLL4_OUT_MAIN, 2, 0, 0),
F(466500000, P_GPLL5_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_csi0_clk_src = {
.cmd_rcgr = 0x55030,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_camss_csi0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = {
F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = {
.cmd_rcgr = 0x53004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0phytimer_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_camss_csi1_clk_src = {
.cmd_rcgr = 0x5506c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_camss_csi0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = {
.cmd_rcgr = 0x53024,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1phytimer_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_camss_csi2_clk_src = {
.cmd_rcgr = 0x550a4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_camss_csi0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi2_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = {
.cmd_rcgr = 0x53044,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi2phytimer_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_camss_csi3_clk_src = {
.cmd_rcgr = 0x550e0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_camss_csi0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi3_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_csiphy_clk_src[] = {
F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0),
F(320000000, P_GPLL8_OUT_EARLY, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_csiphy_clk_src = {
.cmd_rcgr = 0x55000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_11,
.freq_tbl = ftbl_gcc_camss_csiphy_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csiphy_clk_src",
.parent_data = gcc_parent_data_11,
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_gp0_clk_src[] = {
F(50000000, P_GPLL0_OUT_EARLY, 12, 0, 0),
F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_gp0_clk_src = {
.cmd_rcgr = 0x50000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_camss_gp0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_gp0_clk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_camss_gp1_clk_src = {
.cmd_rcgr = 0x5001c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_camss_gp0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_gp1_clk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_jpeg_clk_src[] = {
F(66666667, P_GPLL0_OUT_EARLY, 9, 0, 0),
F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0),
F(219428571, P_GPLL6_OUT_EARLY, 3.5, 0, 0),
F(320000000, P_GPLL8_OUT_EARLY, 3, 0, 0),
F(480000000, P_GPLL8_OUT_EARLY, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_jpeg_clk_src = {
.cmd_rcgr = 0x52028,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_12,
.freq_tbl = ftbl_gcc_camss_jpeg_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_jpeg_clk_src",
.parent_data = gcc_parent_data_12,
.num_parents = ARRAY_SIZE(gcc_parent_data_12),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24),
F(64000000, P_GPLL9_OUT_MAIN, 1, 1, 9),
{ }
};
static struct clk_rcg2 gcc_camss_mclk0_clk_src = {
.cmd_rcgr = 0x51000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk0_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_camss_mclk1_clk_src = {
.cmd_rcgr = 0x5101c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk1_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_camss_mclk2_clk_src = {
.cmd_rcgr = 0x51038,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk2_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_camss_mclk3_clk_src = {
.cmd_rcgr = 0x51054,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk3_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_vfe0_clk_src[] = {
F(120000000, P_GPLL8_OUT_MAIN, 4, 0, 0),
F(256000000, P_GPLL6_OUT_EARLY, 3, 0, 0),
F(403200000, P_GPLL4_OUT_MAIN, 2, 0, 0),
F(480000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
F(533000000, P_GPLL3_OUT_EARLY, 2, 0, 0),
F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_vfe0_clk_src = {
.cmd_rcgr = 0x54010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_camss_vfe0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe0_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_camss_vfe1_clk_src = {
.cmd_rcgr = 0x54048,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_camss_vfe0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe1_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x4d004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x4e004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x4f004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(60000000, P_GPLL0_OUT_EARLY, 10, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x20010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625),
F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625),
F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75),
F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25),
F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75),
F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15),
F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25),
F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375),
F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75),
F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625),
F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0),
F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x1f148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.cmd_rcgr = 0x1f278,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.cmd_rcgr = 0x1f3a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.cmd_rcgr = 0x1f4d8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.cmd_rcgr = 0x1f608,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.cmd_rcgr = 0x1f738,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.cmd_rcgr = 0x39148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.cmd_rcgr = 0x39278,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.cmd_rcgr = 0x393a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.cmd_rcgr = 0x394d8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.cmd_rcgr = 0x39608,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.cmd_rcgr = 0x39738,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
F(144000, P_BI_TCXO, 16, 3, 25),
F(400000, P_BI_TCXO, 12, 1, 4),
F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3),
F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2),
F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.cmd_rcgr = 0x38028,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0),
F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
F(300000000, P_GPLL0_OUT_EARLY, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x38010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.cmd_rcgr = 0x1e00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_13,
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_13,
.num_parents = ARRAY_SIZE(gcc_parent_data_13),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.cmd_rcgr = 0x45020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0),
F(300000000, P_GPLL0_OUT_EARLY, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.cmd_rcgr = 0x45048,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
.cmd_rcgr = 0x4507c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
F(75000000, P_GPLL0_OUT_EARLY, 8, 0, 0),
F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.cmd_rcgr = 0x45060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0),
F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0),
F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.cmd_rcgr = 0x1a01c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(20000000, P_GPLL0_OUT_AUX2, 15, 0, 0),
F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0),
F(60000000, P_GPLL0_OUT_EARLY, 10, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.cmd_rcgr = 0x1a034,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.cmd_rcgr = 0x1a060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_14,
.freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parent_data_14,
.num_parents = ARRAY_SIZE(gcc_parent_data_14),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_vs_ctrl_clk_src = {
.cmd_rcgr = 0x42030,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_vs_ctrl_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(400000000, P_GPLL0_OUT_EARLY, 1.5, 0, 0),
F(600000000, P_GPLL0_OUT_EARLY, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_vsensor_clk_src = {
.cmd_rcgr = 0x42018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_vsensor_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_vsensor_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_ahb2phy_csi_clk = {
.halt_reg = 0x1d004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1d004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1d004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ahb2phy_csi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ahb2phy_usb_clk = {
.halt_reg = 0x1d008,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1d008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1d008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ahb2phy_usb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_apc_vs_clk = {
.halt_reg = 0x4204c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4204c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_apc_vs_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_vsensor_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_bimc_gpu_axi_clk = {
.halt_reg = 0x71154,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x71154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_gpu_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x23004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x23004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_ahb_clk = {
.halt_reg = 0x17008,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x17008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_xo_clk = {
.halt_reg = 0x17028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cci_ahb_clk = {
.halt_reg = 0x52020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cci_clk = {
.halt_reg = 0x5201c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_cci_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cphy_csid0_clk = {
.halt_reg = 0x5504c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5504c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cphy_csid0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csiphy_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cphy_csid1_clk = {
.halt_reg = 0x55088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x55088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cphy_csid1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csiphy_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cphy_csid2_clk = {
.halt_reg = 0x550c0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x550c0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cphy_csid2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csiphy_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cphy_csid3_clk = {
.halt_reg = 0x550fc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x550fc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cphy_csid3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csiphy_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cpp_ahb_clk = {
.halt_reg = 0x560e8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x560e8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cpp_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cpp_axi_clk = {
.halt_reg = 0x560f4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x560f4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cpp_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cpp_clk = {
.halt_reg = 0x560e0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x560e0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cpp_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_cpp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cpp_vbif_ahb_clk = {
.halt_reg = 0x560f0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x560f0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cpp_vbif_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0_ahb_clk = {
.halt_reg = 0x55050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x55050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0_clk = {
.halt_reg = 0x55048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x55048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0phytimer_clk = {
.halt_reg = 0x5301c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5301c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csi0phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0pix_clk = {
.halt_reg = 0x55060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x55060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0pix_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0rdi_clk = {
.halt_reg = 0x55058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x55058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1_ahb_clk = {
.halt_reg = 0x5508c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5508c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1_clk = {
.halt_reg = 0x55084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x55084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1phytimer_clk = {
.halt_reg = 0x5303c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5303c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csi1phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1pix_clk = {
.halt_reg = 0x5509c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5509c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1pix_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1rdi_clk = {
.halt_reg = 0x55094,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x55094,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi2_ahb_clk = {
.halt_reg = 0x550c4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x550c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi2_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi2_clk = {
.halt_reg = 0x550bc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x550bc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csi2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi2phytimer_clk = {
.halt_reg = 0x5305c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5305c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi2phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csi2phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi2pix_clk = {
.halt_reg = 0x550d4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x550d4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi2pix_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csi2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi2rdi_clk = {
.halt_reg = 0x550cc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x550cc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi2rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csi2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi3_ahb_clk = {
.halt_reg = 0x55100,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x55100,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi3_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi3_clk = {
.halt_reg = 0x550f8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x550f8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csi3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi3pix_clk = {
.halt_reg = 0x55110,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x55110,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi3pix_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csi3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi3rdi_clk = {
.halt_reg = 0x55108,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x55108,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi3rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csi3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi_vfe0_clk = {
.halt_reg = 0x54074,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x54074,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi_vfe0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_vfe0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi_vfe1_clk = {
.halt_reg = 0x54080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x54080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi_vfe1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_vfe1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csiphy0_clk = {
.halt_reg = 0x55018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x55018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csiphy0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csiphy_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csiphy1_clk = {
.halt_reg = 0x5501c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csiphy1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csiphy_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csiphy2_clk = {
.halt_reg = 0x55020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x55020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csiphy2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_csiphy_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_gp0_clk = {
.halt_reg = 0x50018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x50018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_gp0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_gp0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_gp1_clk = {
.halt_reg = 0x50034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x50034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_ispif_ahb_clk = {
.halt_reg = 0x540a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x540a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ispif_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_jpeg_ahb_clk = {
.halt_reg = 0x52048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x52048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_jpeg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_jpeg_axi_clk = {
.halt_reg = 0x5204c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5204c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_jpeg_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_jpeg_clk = {
.halt_reg = 0x52040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x52040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_jpeg_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_jpeg_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk0_clk = {
.halt_reg = 0x51018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x51018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk1_clk = {
.halt_reg = 0x51034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x51034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk2_clk = {
.halt_reg = 0x51050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x51050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_mclk2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk3_clk = {
.halt_reg = 0x5106c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5106c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_mclk3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_micro_ahb_clk = {
.halt_reg = 0x560b0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x560b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_micro_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_throttle_nrt_axi_clk = {
.halt_reg = 0x560a4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_throttle_nrt_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_throttle_rt_axi_clk = {
.halt_reg = 0x560a8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_throttle_rt_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_top_ahb_clk = {
.halt_reg = 0x560a0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x560a0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_top_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_vfe0_ahb_clk = {
.halt_reg = 0x54034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x54034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_vfe0_clk = {
.halt_reg = 0x54028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x54028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_vfe0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_vfe0_stream_clk = {
.halt_reg = 0x54030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x54030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe0_stream_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_vfe0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_vfe1_ahb_clk = {
.halt_reg = 0x5406c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5406c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_vfe1_clk = {
.halt_reg = 0x54060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x54060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_vfe1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_vfe1_stream_clk = {
.halt_reg = 0x54068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x54068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe1_stream_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_vfe1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_vfe_tsctr_clk = {
.halt_reg = 0x5409c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5409c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe_tsctr_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_vfe_vbif_ahb_clk = {
.halt_reg = 0x5408c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5408c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe_vbif_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_vfe_vbif_axi_clk = {
.halt_reg = 0x54090,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x54090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe_vbif_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_ahb_clk = {
.halt_reg = 0x2700c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2700c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_axi_clk = {
.halt_reg = 0x27008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_clk = {
.halt_reg = 0x27004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.halt_reg = 0x1a084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_gnoc_clk = {
.halt_reg = 0x2b004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2b004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_gnoc_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_ahb_clk = {
.halt_reg = 0x1700c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1700c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1700c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpll0_out_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_hf_axi_clk = {
.halt_reg = 0x17020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_throttle_core_clk = {
.halt_reg = 0x17064,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_throttle_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_xo_clk = {
.halt_reg = 0x1702c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1702c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x4d000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x4e000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x4f000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_cfg_ahb_clk = {
.halt_reg = 0x36004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x36004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x36004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_cfg_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpll0_out_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpll0_out_aux2.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
.halt_reg = 0x3600c,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x3600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
.halt_reg = 0x36018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_snoc_dvm_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_throttle_core_clk = {
.halt_reg = 0x36048,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(31),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_throttle_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_throttle_xo_clk = {
.halt_reg = 0x36044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_throttle_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_vs_clk = {
.halt_reg = 0x42048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x42048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_vs_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_vsensor_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x2000c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2000c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x20004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x20004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x20004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x20008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x21004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x21004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
.halt_reg = 0x17014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x17014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_nrt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
.halt_reg = 0x17060,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17060,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_rt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp_ahb_clk = {
.halt_reg = 0x17018,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x17018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_disp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = {
.halt_reg = 0x36040,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x36040,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_gpu_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
.halt_reg = 0x17010,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x17010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_vcodec_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
.halt_reg = 0x1f014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_clk = {
.halt_reg = 0x1f00c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.halt_reg = 0x1f144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.halt_reg = 0x1f274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.halt_reg = 0x1f3a4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.halt_reg = 0x1f4d4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.halt_reg = 0x1f604,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.halt_reg = 0x1f734,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
.halt_reg = 0x39014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_clk = {
.halt_reg = 0x3900c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.halt_reg = 0x39144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.halt_reg = 0x39274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.halt_reg = 0x393a4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.halt_reg = 0x394d4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.halt_reg = 0x39604,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.halt_reg = 0x39734,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
.halt_reg = 0x1f004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
.halt_reg = 0x1f008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1f008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
.halt_reg = 0x39004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
.halt_reg = 0x39008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x39008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x38008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x38008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x38004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x38004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0x3800c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3800c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc1_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x1e008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x1e004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_compute_sf_axi_clk = {
.halt_reg = 0x1050c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1050c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_compute_sf_axi_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
.halt_reg = 0x2b06c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_cpuss_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = {
.halt_reg = 0x45098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x45098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = {
.halt_reg = 0x1a080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_mem_clkref_clk = {
.halt_reg = 0x8c000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_mem_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x45014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x45014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x45014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_clk = {
.halt_reg = 0x45010,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x45010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x45010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.halt_reg = 0x45044,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x45044,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x45044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.halt_reg = 0x45078,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x45078,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x45078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.halt_reg = 0x4501c,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x4501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
.halt_reg = 0x45018,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x45018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.halt_reg = 0x45040,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x45040,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x45040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_master_clk = {
.halt_reg = 0x1a010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0x1a018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_sleep_clk = {
.halt_reg = 0x1a014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_clkref_clk = {
.halt_reg = 0x80278,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x80278,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.halt_reg = 0x1a054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x1a058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vdda_vs_clk = {
.halt_reg = 0x4200c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_vdda_vs_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_vsensor_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vddcx_vs_clk = {
.halt_reg = 0x42004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x42004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_vddcx_vs_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_vsensor_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vddmx_vs_clk = {
.halt_reg = 0x42008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x42008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_vddmx_vs_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_vsensor_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_ahb_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x17004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi0_clk = {
.halt_reg = 0x1701c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1701c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_throttle_core_clk = {
.halt_reg = 0x17068,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_throttle_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_xo_clk = {
.halt_reg = 0x17024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vs_ctrl_ahb_clk = {
.halt_reg = 0x42014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x42014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x42014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_vs_ctrl_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vs_ctrl_clk = {
.halt_reg = 0x42010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x42010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_vs_ctrl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_vs_ctrl_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wcss_vs_clk = {
.halt_reg = 0x42050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x42050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_wcss_vs_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_vsensor_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc usb30_prim_gdsc = {
.gdscr = 0x1a004,
.pd = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ufs_phy_gdsc = {
.gdscr = 0x45004,
.pd = {
.name = "ufs_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc camss_vfe0_gdsc = {
.gdscr = 0x54004,
.pd = {
.name = "camss_vfe0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc camss_vfe1_gdsc = {
.gdscr = 0x5403c,
.pd = {
.name = "camss_vfe1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc camss_top_gdsc = {
.gdscr = 0x5607c,
.pd = {
.name = "camss_top_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc cam_cpp_gdsc = {
.gdscr = 0x560bc,
.pd = {
.name = "cam_cpp_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
.gdscr = 0x7d060,
.pd = {
.name = "hlos1_vote_turing_mmu_tbu1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = {
.gdscr = 0x80074,
.pd = {
.name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = {
.gdscr = 0x80084,
.pd = {
.name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
.gdscr = 0x80094,
.pd = {
.name = "hlos1_vote_turing_mmu_tbu0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc *gcc_sm6125_gdscs[] = {
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
[UFS_PHY_GDSC] = &ufs_phy_gdsc,
[CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc,
[CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc,
[CAMSS_TOP_GDSC] = &camss_top_gdsc,
[CAM_CPP_GDSC] = &cam_cpp_gdsc,
[HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
[HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc,
[HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc,
[HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
};
static struct clk_hw *gcc_sm6125_hws[] = {
[GPLL0_OUT_AUX2] = &gpll0_out_aux2.hw,
[GPLL0_OUT_MAIN] = &gpll0_out_main.hw,
[GPLL6_OUT_MAIN] = &gpll6_out_main.hw,
[GPLL7_OUT_MAIN] = &gpll7_out_main.hw,
[GPLL8_OUT_MAIN] = &gpll8_out_main.hw,
[GPLL9_OUT_MAIN] = &gpll9_out_main.hw,
};
static struct clk_regmap *gcc_sm6125_clocks[] = {
[GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr,
[GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr,
[GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr,
[GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
[GCC_CAMSS_AHB_CLK_SRC] = &gcc_camss_ahb_clk_src.clkr,
[GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
[GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
[GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr,
[GCC_CAMSS_CPHY_CSID0_CLK] = &gcc_camss_cphy_csid0_clk.clkr,
[GCC_CAMSS_CPHY_CSID1_CLK] = &gcc_camss_cphy_csid1_clk.clkr,
[GCC_CAMSS_CPHY_CSID2_CLK] = &gcc_camss_cphy_csid2_clk.clkr,
[GCC_CAMSS_CPHY_CSID3_CLK] = &gcc_camss_cphy_csid3_clk.clkr,
[GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
[GCC_CAMSS_CPP_AXI_CLK] = &gcc_camss_cpp_axi_clk.clkr,
[GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
[GCC_CAMSS_CPP_CLK_SRC] = &gcc_camss_cpp_clk_src.clkr,
[GCC_CAMSS_CPP_VBIF_AHB_CLK] = &gcc_camss_cpp_vbif_ahb_clk.clkr,
[GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
[GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
[GCC_CAMSS_CSI0_CLK_SRC] = &gcc_camss_csi0_clk_src.clkr,
[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
[GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr,
[GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
[GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
[GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
[GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
[GCC_CAMSS_CSI1_CLK_SRC] = &gcc_camss_csi1_clk_src.clkr,
[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
[GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr,
[GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
[GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
[GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,
[GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,
[GCC_CAMSS_CSI2_CLK_SRC] = &gcc_camss_csi2_clk_src.clkr,
[GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr,
[GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr,
[GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,
[GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,
[GCC_CAMSS_CSI3_AHB_CLK] = &gcc_camss_csi3_ahb_clk.clkr,
[GCC_CAMSS_CSI3_CLK] = &gcc_camss_csi3_clk.clkr,
[GCC_CAMSS_CSI3_CLK_SRC] = &gcc_camss_csi3_clk_src.clkr,
[GCC_CAMSS_CSI3PIX_CLK] = &gcc_camss_csi3pix_clk.clkr,
[GCC_CAMSS_CSI3RDI_CLK] = &gcc_camss_csi3rdi_clk.clkr,
[GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
[GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr,
[GCC_CAMSS_CSIPHY0_CLK] = &gcc_camss_csiphy0_clk.clkr,
[GCC_CAMSS_CSIPHY1_CLK] = &gcc_camss_csiphy1_clk.clkr,
[GCC_CAMSS_CSIPHY2_CLK] = &gcc_camss_csiphy2_clk.clkr,
[GCC_CAMSS_CSIPHY_CLK_SRC] = &gcc_camss_csiphy_clk_src.clkr,
[GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
[GCC_CAMSS_GP0_CLK_SRC] = &gcc_camss_gp0_clk_src.clkr,
[GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
[GCC_CAMSS_GP1_CLK_SRC] = &gcc_camss_gp1_clk_src.clkr,
[GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
[GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
[GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
[GCC_CAMSS_JPEG_CLK] = &gcc_camss_jpeg_clk.clkr,
[GCC_CAMSS_JPEG_CLK_SRC] = &gcc_camss_jpeg_clk_src.clkr,
[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
[GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr,
[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
[GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr,
[GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
[GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr,
[GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr,
[GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr,
[GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
[GCC_CAMSS_THROTTLE_NRT_AXI_CLK] = &gcc_camss_throttle_nrt_axi_clk.clkr,
[GCC_CAMSS_THROTTLE_RT_AXI_CLK] = &gcc_camss_throttle_rt_axi_clk.clkr,
[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
[GCC_CAMSS_VFE0_AHB_CLK] = &gcc_camss_vfe0_ahb_clk.clkr,
[GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
[GCC_CAMSS_VFE0_CLK_SRC] = &gcc_camss_vfe0_clk_src.clkr,
[GCC_CAMSS_VFE0_STREAM_CLK] = &gcc_camss_vfe0_stream_clk.clkr,
[GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr,
[GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr,
[GCC_CAMSS_VFE1_CLK_SRC] = &gcc_camss_vfe1_clk_src.clkr,
[GCC_CAMSS_VFE1_STREAM_CLK] = &gcc_camss_vfe1_stream_clk.clkr,
[GCC_CAMSS_VFE_TSCTR_CLK] = &gcc_camss_vfe_tsctr_clk.clkr,
[GCC_CAMSS_VFE_VBIF_AHB_CLK] = &gcc_camss_vfe_vbif_ahb_clk.clkr,
[GCC_CAMSS_VFE_VBIF_AXI_CLK] = &gcc_camss_vfe_vbif_axi_clk.clkr,
[GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
[GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
[GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
[GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
[GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr,
[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr,
[GCC_GPU_THROTTLE_XO_CLK] = &gcc_gpu_throttle_xo_clk.clkr,
[GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
[GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr,
[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_SYS_NOC_COMPUTE_SF_AXI_CLK] = &gcc_sys_noc_compute_sf_axi_clk.clkr,
[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
[GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr,
[GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr,
[GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
&gcc_ufs_phy_unipro_core_clk_src.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
&gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr,
[GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr,
[GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr,
[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
[GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr,
[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
[GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr,
[GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr,
[GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr,
[GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
[GCC_WCSS_VS_CLK] = &gcc_wcss_vs_clk.clkr,
[GPLL0_OUT_EARLY] = &gpll0_out_early.clkr,
[GPLL3_OUT_EARLY] = &gpll3_out_early.clkr,
[GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
[GPLL5_OUT_MAIN] = &gpll5_out_main.clkr,
[GPLL6_OUT_EARLY] = &gpll6_out_early.clkr,
[GPLL7_OUT_EARLY] = &gpll7_out_early.clkr,
[GPLL8_OUT_EARLY] = &gpll8_out_early.clkr,
[GPLL9_OUT_EARLY] = &gpll9_out_early.clkr,
[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
};
static const struct qcom_reset_map gcc_sm6125_resets[] = {
[GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },
[GCC_UFS_PHY_BCR] = { 0x45000 },
[GCC_USB30_PRIM_BCR] = { 0x1a000 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
[GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },
[GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
[GCC_CAMSS_MICRO_BCR] = { 0x560ac },
};
static struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
};
static const struct regmap_config gcc_sm6125_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xc7000,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_sm6125_desc = {
.config = &gcc_sm6125_regmap_config,
.clks = gcc_sm6125_clocks,
.num_clks = ARRAY_SIZE(gcc_sm6125_clocks),
.clk_hws = gcc_sm6125_hws,
.num_clk_hws = ARRAY_SIZE(gcc_sm6125_hws),
.resets = gcc_sm6125_resets,
.num_resets = ARRAY_SIZE(gcc_sm6125_resets),
.gdscs = gcc_sm6125_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sm6125_gdscs),
};
static const struct of_device_id gcc_sm6125_match_table[] = {
{ .compatible = "qcom,gcc-sm6125" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_sm6125_match_table);
static int gcc_sm6125_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sm6125_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/*
* Disable the GPLL0 active input to video block via
* MISC registers.
*/
regmap_update_bits(regmap, 0x80258, 0x1, 0x1);
/*
* Enable DUAL_EDGE mode for MCLK RCGs
* This is required to enable MND divider mode
*/
regmap_update_bits(regmap, 0x51004, 0x3000, 0x2000);
regmap_update_bits(regmap, 0x51020, 0x3000, 0x2000);
regmap_update_bits(regmap, 0x5103c, 0x3000, 0x2000);
regmap_update_bits(regmap, 0x51058, 0x3000, 0x2000);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
return qcom_cc_really_probe(pdev, &gcc_sm6125_desc, regmap);
}
static struct platform_driver gcc_sm6125_driver = {
.probe = gcc_sm6125_probe,
.driver = {
.name = "gcc-sm6125",
.of_match_table = gcc_sm6125_match_table,
},
};
static int __init gcc_sm6125_init(void)
{
return platform_driver_register(&gcc_sm6125_driver);
}
subsys_initcall(gcc_sm6125_init);
static void __exit gcc_sm6125_exit(void)
{
platform_driver_unregister(&gcc_sm6125_driver);
}
module_exit(gcc_sm6125_exit);
MODULE_DESCRIPTION("QTI GCC SM6125 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gcc-sm6125.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
* Copyright (c) BayLibre, SAS.
* Author : Neil Armstrong <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-mdm9615.h>
#include <dt-bindings/reset/qcom,gcc-mdm9615.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
enum {
DT_CXO,
DT_PLL4,
};
enum {
P_CXO,
P_PLL8,
P_PLL14,
};
static const struct parent_map gcc_cxo_map[] = {
{ P_CXO, 0 },
};
static const struct clk_parent_data gcc_cxo[] = {
{ .index = DT_CXO, .name = "cxo_board" },
};
static struct clk_pll pll0 = {
.l_reg = 0x30c4,
.m_reg = 0x30c8,
.n_reg = 0x30cc,
.config_reg = 0x30d4,
.mode_reg = 0x30c0,
.status_reg = 0x30d8,
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll0",
.parent_data = gcc_cxo,
.num_parents = ARRAY_SIZE(gcc_cxo),
.ops = &clk_pll_ops,
},
};
static struct clk_regmap pll0_vote = {
.enable_reg = 0x34c0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "pll0_vote",
.parent_hws = (const struct clk_hw*[]) {
&pll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_regmap pll4_vote = {
.enable_reg = 0x34c0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pll4_vote",
.parent_data = &(const struct clk_parent_data) {
.index = DT_PLL4, .name = "pll4",
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll pll8 = {
.l_reg = 0x3144,
.m_reg = 0x3148,
.n_reg = 0x314c,
.config_reg = 0x3154,
.mode_reg = 0x3140,
.status_reg = 0x3158,
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll8",
.parent_data = gcc_cxo,
.num_parents = ARRAY_SIZE(gcc_cxo),
.ops = &clk_pll_ops,
},
};
static struct clk_regmap pll8_vote = {
.enable_reg = 0x34c0,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "pll8_vote",
.parent_hws = (const struct clk_hw*[]) {
&pll8.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll pll14 = {
.l_reg = 0x31c4,
.m_reg = 0x31c8,
.n_reg = 0x31cc,
.config_reg = 0x31d4,
.mode_reg = 0x31c0,
.status_reg = 0x31d8,
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll14",
.parent_data = gcc_cxo,
.num_parents = ARRAY_SIZE(gcc_cxo),
.ops = &clk_pll_ops,
},
};
static struct clk_regmap pll14_vote = {
.enable_reg = 0x34c0,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "pll14_vote",
.parent_hws = (const struct clk_hw*[]) {
&pll14.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static const struct parent_map gcc_cxo_pll8_map[] = {
{ P_CXO, 0 },
{ P_PLL8, 3 }
};
static const struct clk_parent_data gcc_cxo_pll8[] = {
{ .index = DT_CXO, .name = "cxo_board" },
{ .hw = &pll8_vote.hw },
};
static const struct parent_map gcc_cxo_pll14_map[] = {
{ P_CXO, 0 },
{ P_PLL14, 4 }
};
static const struct clk_parent_data gcc_cxo_pll14[] = {
{ .index = DT_CXO, .name = "cxo_board" },
{ .hw = &pll14_vote.hw },
};
static struct freq_tbl clk_tbl_gsbi_uart[] = {
{ 1843200, P_PLL8, 2, 6, 625 },
{ 3686400, P_PLL8, 2, 12, 625 },
{ 7372800, P_PLL8, 2, 24, 625 },
{ 14745600, P_PLL8, 2, 48, 625 },
{ 16000000, P_PLL8, 4, 1, 6 },
{ 24000000, P_PLL8, 4, 1, 4 },
{ 32000000, P_PLL8, 4, 1, 3 },
{ 40000000, P_PLL8, 1, 5, 48 },
{ 46400000, P_PLL8, 1, 29, 240 },
{ 48000000, P_PLL8, 4, 1, 2 },
{ 51200000, P_PLL8, 1, 2, 15 },
{ 56000000, P_PLL8, 1, 7, 48 },
{ 58982400, P_PLL8, 1, 96, 625 },
{ 64000000, P_PLL8, 2, 1, 3 },
{ }
};
static struct clk_rcg gsbi1_uart_src = {
.ns_reg = 0x29d4,
.md_reg = 0x29d0,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_cxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x29d4,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_uart_src",
.parent_data = gcc_cxo_pll8,
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi1_uart_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 10,
.clkr = {
.enable_reg = 0x29d4,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_uart_clk",
.parent_hws = (const struct clk_hw*[]) {
&gsbi1_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi2_uart_src = {
.ns_reg = 0x29f4,
.md_reg = 0x29f0,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_cxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x29f4,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_uart_src",
.parent_data = gcc_cxo_pll8,
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi2_uart_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 6,
.clkr = {
.enable_reg = 0x29f4,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_uart_clk",
.parent_hws = (const struct clk_hw*[]) {
&gsbi2_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi3_uart_src = {
.ns_reg = 0x2a14,
.md_reg = 0x2a10,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_cxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2a14,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_uart_src",
.parent_data = gcc_cxo_pll8,
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi3_uart_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 2,
.clkr = {
.enable_reg = 0x2a14,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_uart_clk",
.parent_hws = (const struct clk_hw*[]) {
&gsbi3_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi4_uart_src = {
.ns_reg = 0x2a34,
.md_reg = 0x2a30,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_cxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2a34,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_uart_src",
.parent_data = gcc_cxo_pll8,
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi4_uart_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 26,
.clkr = {
.enable_reg = 0x2a34,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_uart_clk",
.parent_hws = (const struct clk_hw*[]) {
&gsbi4_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi5_uart_src = {
.ns_reg = 0x2a54,
.md_reg = 0x2a50,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_cxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2a54,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_uart_src",
.parent_data = gcc_cxo_pll8,
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi5_uart_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 22,
.clkr = {
.enable_reg = 0x2a54,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_uart_clk",
.parent_hws = (const struct clk_hw*[]) {
&gsbi5_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct freq_tbl clk_tbl_gsbi_qup[] = {
{ 960000, P_CXO, 4, 1, 5 },
{ 4800000, P_CXO, 4, 0, 1 },
{ 9600000, P_CXO, 2, 0, 1 },
{ 15060000, P_PLL8, 1, 2, 51 },
{ 24000000, P_PLL8, 4, 1, 4 },
{ 25600000, P_PLL8, 1, 1, 15 },
{ 48000000, P_PLL8, 4, 1, 2 },
{ 51200000, P_PLL8, 1, 2, 15 },
{ }
};
static struct clk_rcg gsbi1_qup_src = {
.ns_reg = 0x29cc,
.md_reg = 0x29c8,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_cxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x29cc,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_qup_src",
.parent_data = gcc_cxo_pll8,
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi1_qup_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 9,
.clkr = {
.enable_reg = 0x29cc,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_qup_clk",
.parent_hws = (const struct clk_hw*[]) {
&gsbi1_qup_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi2_qup_src = {
.ns_reg = 0x29ec,
.md_reg = 0x29e8,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_cxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x29ec,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_qup_src",
.parent_data = gcc_cxo_pll8,
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi2_qup_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 4,
.clkr = {
.enable_reg = 0x29ec,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_qup_clk",
.parent_hws = (const struct clk_hw*[]) {
&gsbi2_qup_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi3_qup_src = {
.ns_reg = 0x2a0c,
.md_reg = 0x2a08,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_cxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2a0c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_qup_src",
.parent_data = gcc_cxo_pll8,
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi3_qup_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 0,
.clkr = {
.enable_reg = 0x2a0c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_qup_clk",
.parent_hws = (const struct clk_hw*[]) {
&gsbi3_qup_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi4_qup_src = {
.ns_reg = 0x2a2c,
.md_reg = 0x2a28,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_cxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2a2c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_qup_src",
.parent_data = gcc_cxo_pll8,
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi4_qup_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 24,
.clkr = {
.enable_reg = 0x2a2c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_qup_clk",
.parent_hws = (const struct clk_hw*[]) {
&gsbi4_qup_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi5_qup_src = {
.ns_reg = 0x2a4c,
.md_reg = 0x2a48,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_cxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2a4c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_qup_src",
.parent_data = gcc_cxo_pll8,
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi5_qup_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 20,
.clkr = {
.enable_reg = 0x2a4c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_qup_clk",
.parent_hws = (const struct clk_hw*[]) {
&gsbi5_qup_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl clk_tbl_gp[] = {
{ 9600000, P_CXO, 2, 0, 0 },
{ 19200000, P_CXO, 1, 0, 0 },
{ }
};
static struct clk_rcg gp0_src = {
.ns_reg = 0x2d24,
.md_reg = 0x2d00,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_cxo_map,
},
.freq_tbl = clk_tbl_gp,
.clkr = {
.enable_reg = 0x2d24,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp0_src",
.parent_data = gcc_cxo,
.num_parents = ARRAY_SIZE(gcc_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
}
};
static struct clk_branch gp0_clk = {
.halt_reg = 0x2fd8,
.halt_bit = 7,
.clkr = {
.enable_reg = 0x2d24,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gp0_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gp1_src = {
.ns_reg = 0x2d44,
.md_reg = 0x2d40,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_cxo_map,
},
.freq_tbl = clk_tbl_gp,
.clkr = {
.enable_reg = 0x2d44,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp1_src",
.parent_data = gcc_cxo,
.num_parents = ARRAY_SIZE(gcc_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch gp1_clk = {
.halt_reg = 0x2fd8,
.halt_bit = 6,
.clkr = {
.enable_reg = 0x2d44,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gp1_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gp2_src = {
.ns_reg = 0x2d64,
.md_reg = 0x2d60,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_cxo_map,
},
.freq_tbl = clk_tbl_gp,
.clkr = {
.enable_reg = 0x2d64,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp2_src",
.parent_data = gcc_cxo,
.num_parents = ARRAY_SIZE(gcc_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch gp2_clk = {
.halt_reg = 0x2fd8,
.halt_bit = 5,
.clkr = {
.enable_reg = 0x2d64,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gp2_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch pmem_clk = {
.hwcg_reg = 0x25a0,
.hwcg_bit = 6,
.halt_reg = 0x2fc8,
.halt_bit = 20,
.clkr = {
.enable_reg = 0x25a0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pmem_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_rcg prng_src = {
.ns_reg = 0x2e80,
.p = {
.pre_div_shift = 3,
.pre_div_width = 4,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_cxo_pll8_map,
},
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "prng_src",
.parent_data = gcc_cxo_pll8,
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
},
},
};
static struct clk_branch prng_clk = {
.halt_reg = 0x2fd8,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 10,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "prng_clk",
.parent_hws = (const struct clk_hw*[]) {
&prng_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
},
},
};
static const struct freq_tbl clk_tbl_sdc[] = {
{ 144000, P_CXO, 1, 1, 133 },
{ 400000, P_PLL8, 4, 1, 240 },
{ 16000000, P_PLL8, 4, 1, 6 },
{ 17070000, P_PLL8, 1, 2, 45 },
{ 20210000, P_PLL8, 1, 1, 19 },
{ 24000000, P_PLL8, 4, 1, 4 },
{ 38400000, P_PLL8, 2, 1, 5 },
{ 48000000, P_PLL8, 4, 1, 2 },
{ 64000000, P_PLL8, 3, 1, 2 },
{ 76800000, P_PLL8, 1, 1, 5 },
{ }
};
static struct clk_rcg sdc1_src = {
.ns_reg = 0x282c,
.md_reg = 0x2828,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_cxo_pll8_map,
},
.freq_tbl = clk_tbl_sdc,
.clkr = {
.enable_reg = 0x282c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc1_src",
.parent_data = gcc_cxo_pll8,
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
},
}
};
static struct clk_branch sdc1_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 6,
.clkr = {
.enable_reg = 0x282c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc1_clk",
.parent_hws = (const struct clk_hw*[]) {
&sdc1_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg sdc2_src = {
.ns_reg = 0x284c,
.md_reg = 0x2848,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_cxo_pll8_map,
},
.freq_tbl = clk_tbl_sdc,
.clkr = {
.enable_reg = 0x284c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc2_src",
.parent_data = gcc_cxo_pll8,
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
},
}
};
static struct clk_branch sdc2_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 5,
.clkr = {
.enable_reg = 0x284c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc2_clk",
.parent_hws = (const struct clk_hw*[]) {
&sdc2_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl clk_tbl_usb[] = {
{ 60000000, P_PLL8, 1, 5, 32 },
{ }
};
static struct clk_rcg usb_hs1_xcvr_src = {
.ns_reg = 0x290c,
.md_reg = 0x2908,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_cxo_pll8_map,
},
.freq_tbl = clk_tbl_usb,
.clkr = {
.enable_reg = 0x290c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_src",
.parent_data = gcc_cxo_pll8,
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch usb_hs1_xcvr_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 0,
.clkr = {
.enable_reg = 0x290c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_clk",
.parent_hws = (const struct clk_hw*[]) {
&usb_hs1_xcvr_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg usb_hsic_xcvr_fs_src = {
.ns_reg = 0x2928,
.md_reg = 0x2924,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_cxo_pll8_map,
},
.freq_tbl = clk_tbl_usb,
.clkr = {
.enable_reg = 0x2928,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_hsic_xcvr_fs_src",
.parent_data = gcc_cxo_pll8,
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch usb_hsic_xcvr_fs_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 9,
.clkr = {
.enable_reg = 0x2928,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_hsic_xcvr_fs_clk",
.parent_hws = (const struct clk_hw*[]) {
&usb_hsic_xcvr_fs_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl clk_tbl_usb_hs1_system[] = {
{ 60000000, P_PLL8, 1, 5, 32 },
{ }
};
static struct clk_rcg usb_hs1_system_src = {
.ns_reg = 0x36a4,
.md_reg = 0x36a0,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_cxo_pll8_map,
},
.freq_tbl = clk_tbl_usb_hs1_system,
.clkr = {
.enable_reg = 0x36a4,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_system_src",
.parent_data = gcc_cxo_pll8,
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch usb_hs1_system_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 4,
.clkr = {
.enable_reg = 0x36a4,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]) {
&usb_hs1_system_src.clkr.hw,
},
.num_parents = 1,
.name = "usb_hs1_system_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
},
};
static const struct freq_tbl clk_tbl_usb_hsic_system[] = {
{ 64000000, P_PLL8, 1, 1, 6 },
{ }
};
static struct clk_rcg usb_hsic_system_src = {
.ns_reg = 0x2b58,
.md_reg = 0x2b54,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_cxo_pll8_map,
},
.freq_tbl = clk_tbl_usb_hsic_system,
.clkr = {
.enable_reg = 0x2b58,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_hsic_system_src",
.parent_data = gcc_cxo_pll8,
.num_parents = ARRAY_SIZE(gcc_cxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch usb_hsic_system_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 7,
.clkr = {
.enable_reg = 0x2b58,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]) {
&usb_hsic_system_src.clkr.hw,
},
.num_parents = 1,
.name = "usb_hsic_system_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl clk_tbl_usb_hsic_hsic[] = {
{ 48000000, P_PLL14, 1, 0, 0 },
{ }
};
static struct clk_rcg usb_hsic_hsic_src = {
.ns_reg = 0x2b50,
.md_reg = 0x2b4c,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_cxo_pll14_map,
},
.freq_tbl = clk_tbl_usb_hsic_hsic,
.clkr = {
.enable_reg = 0x2b50,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_hsic_hsic_src",
.parent_data = gcc_cxo_pll14,
.num_parents = ARRAY_SIZE(gcc_cxo_pll14),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch usb_hsic_hsic_clk = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x2b50,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]) {
&usb_hsic_hsic_src.clkr.hw,
},
.num_parents = 1,
.name = "usb_hsic_hsic_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch usb_hsic_hsio_cal_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 8,
.clkr = {
.enable_reg = 0x2b48,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.parent_data = gcc_cxo,
.num_parents = ARRAY_SIZE(gcc_cxo),
.name = "usb_hsic_hsio_cal_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch ce1_core_clk = {
.hwcg_reg = 0x2724,
.hwcg_bit = 6,
.halt_reg = 0x2fd4,
.halt_bit = 27,
.clkr = {
.enable_reg = 0x2724,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "ce1_core_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch ce1_h_clk = {
.halt_reg = 0x2fd4,
.halt_bit = 1,
.clkr = {
.enable_reg = 0x2720,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "ce1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch dma_bam_h_clk = {
.hwcg_reg = 0x25c0,
.hwcg_bit = 6,
.halt_reg = 0x2fc8,
.halt_bit = 12,
.clkr = {
.enable_reg = 0x25c0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "dma_bam_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi1_h_clk = {
.hwcg_reg = 0x29c0,
.hwcg_bit = 6,
.halt_reg = 0x2fcc,
.halt_bit = 11,
.clkr = {
.enable_reg = 0x29c0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi2_h_clk = {
.hwcg_reg = 0x29e0,
.hwcg_bit = 6,
.halt_reg = 0x2fcc,
.halt_bit = 7,
.clkr = {
.enable_reg = 0x29e0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi3_h_clk = {
.hwcg_reg = 0x2a00,
.hwcg_bit = 6,
.halt_reg = 0x2fcc,
.halt_bit = 3,
.clkr = {
.enable_reg = 0x2a00,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi4_h_clk = {
.hwcg_reg = 0x2a20,
.hwcg_bit = 6,
.halt_reg = 0x2fd0,
.halt_bit = 27,
.clkr = {
.enable_reg = 0x2a20,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi5_h_clk = {
.hwcg_reg = 0x2a40,
.hwcg_bit = 6,
.halt_reg = 0x2fd0,
.halt_bit = 23,
.clkr = {
.enable_reg = 0x2a40,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch usb_hs1_h_clk = {
.hwcg_reg = 0x2900,
.hwcg_bit = 6,
.halt_reg = 0x2fc8,
.halt_bit = 1,
.clkr = {
.enable_reg = 0x2900,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch usb_hsic_h_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 28,
.clkr = {
.enable_reg = 0x2920,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb_hsic_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch sdc1_h_clk = {
.hwcg_reg = 0x2820,
.hwcg_bit = 6,
.halt_reg = 0x2fc8,
.halt_bit = 11,
.clkr = {
.enable_reg = 0x2820,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sdc1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch sdc2_h_clk = {
.hwcg_reg = 0x2840,
.hwcg_bit = 6,
.halt_reg = 0x2fc8,
.halt_bit = 10,
.clkr = {
.enable_reg = 0x2840,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sdc2_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch adm0_clk = {
.halt_reg = 0x2fdc,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 14,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "adm0_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch adm0_pbus_clk = {
.hwcg_reg = 0x2208,
.hwcg_bit = 6,
.halt_reg = 0x2fdc,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 13,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "adm0_pbus_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pmic_arb0_h_clk = {
.halt_reg = 0x2fd8,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 22,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "pmic_arb0_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pmic_arb1_h_clk = {
.halt_reg = 0x2fd8,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 21,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "pmic_arb1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pmic_ssbi2_clk = {
.halt_reg = 0x2fd8,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 23,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "pmic_ssbi2_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch rpm_msg_ram_h_clk = {
.hwcg_reg = 0x27e0,
.hwcg_bit = 6,
.halt_reg = 0x2fd8,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 12,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "rpm_msg_ram_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch ebi2_clk = {
.hwcg_reg = 0x2664,
.hwcg_bit = 6,
.halt_reg = 0x2fcc,
.halt_bit = 24,
.clkr = {
.enable_reg = 0x2664,
.enable_mask = BIT(6) | BIT(4),
.hw.init = &(struct clk_init_data){
.name = "ebi2_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch ebi2_aon_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 23,
.clkr = {
.enable_reg = 0x2664,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "ebi2_aon_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_regmap *gcc_mdm9615_clks[] = {
[PLL0] = &pll0.clkr,
[PLL0_VOTE] = &pll0_vote,
[PLL4_VOTE] = &pll4_vote,
[PLL8] = &pll8.clkr,
[PLL8_VOTE] = &pll8_vote,
[PLL14] = &pll14.clkr,
[PLL14_VOTE] = &pll14_vote,
[GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
[GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
[GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
[GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
[GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
[GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
[GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
[GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
[GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
[GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
[GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
[GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
[GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
[GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
[GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
[GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
[GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
[GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
[GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
[GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
[GP0_SRC] = &gp0_src.clkr,
[GP0_CLK] = &gp0_clk.clkr,
[GP1_SRC] = &gp1_src.clkr,
[GP1_CLK] = &gp1_clk.clkr,
[GP2_SRC] = &gp2_src.clkr,
[GP2_CLK] = &gp2_clk.clkr,
[PMEM_A_CLK] = &pmem_clk.clkr,
[PRNG_SRC] = &prng_src.clkr,
[PRNG_CLK] = &prng_clk.clkr,
[SDC1_SRC] = &sdc1_src.clkr,
[SDC1_CLK] = &sdc1_clk.clkr,
[SDC2_SRC] = &sdc2_src.clkr,
[SDC2_CLK] = &sdc2_clk.clkr,
[USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
[USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
[USB_HS1_SYSTEM_CLK_SRC] = &usb_hs1_system_src.clkr,
[USB_HS1_SYSTEM_CLK] = &usb_hs1_system_clk.clkr,
[USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
[USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
[USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_src.clkr,
[USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
[USB_HSIC_HSIC_CLK_SRC] = &usb_hsic_hsic_src.clkr,
[USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
[USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
[CE1_CORE_CLK] = &ce1_core_clk.clkr,
[CE1_H_CLK] = &ce1_h_clk.clkr,
[DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
[GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
[GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
[GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
[GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
[GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
[USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
[USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
[SDC1_H_CLK] = &sdc1_h_clk.clkr,
[SDC2_H_CLK] = &sdc2_h_clk.clkr,
[ADM0_CLK] = &adm0_clk.clkr,
[ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
[PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
[PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
[PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
[RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
[EBI2_CLK] = &ebi2_clk.clkr,
[EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
};
static const struct qcom_reset_map gcc_mdm9615_resets[] = {
[DMA_BAM_RESET] = { 0x25c0, 7 },
[CE1_H_RESET] = { 0x2720, 7 },
[CE1_CORE_RESET] = { 0x2724, 7 },
[SDC1_RESET] = { 0x2830 },
[SDC2_RESET] = { 0x2850 },
[ADM0_C2_RESET] = { 0x220c, 4 },
[ADM0_C1_RESET] = { 0x220c, 3 },
[ADM0_C0_RESET] = { 0x220c, 2 },
[ADM0_PBUS_RESET] = { 0x220c, 1 },
[ADM0_RESET] = { 0x220c },
[USB_HS1_RESET] = { 0x2910 },
[USB_HSIC_RESET] = { 0x2934 },
[GSBI1_RESET] = { 0x29dc },
[GSBI2_RESET] = { 0x29fc },
[GSBI3_RESET] = { 0x2a1c },
[GSBI4_RESET] = { 0x2a3c },
[GSBI5_RESET] = { 0x2a5c },
[PDM_RESET] = { 0x2CC0, 12 },
};
static const struct regmap_config gcc_mdm9615_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x3660,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_mdm9615_desc = {
.config = &gcc_mdm9615_regmap_config,
.clks = gcc_mdm9615_clks,
.num_clks = ARRAY_SIZE(gcc_mdm9615_clks),
.resets = gcc_mdm9615_resets,
.num_resets = ARRAY_SIZE(gcc_mdm9615_resets),
};
static const struct of_device_id gcc_mdm9615_match_table[] = {
{ .compatible = "qcom,gcc-mdm9615" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_mdm9615_match_table);
static int gcc_mdm9615_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gcc_mdm9615_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return qcom_cc_really_probe(pdev, &gcc_mdm9615_desc, regmap);
}
static struct platform_driver gcc_mdm9615_driver = {
.probe = gcc_mdm9615_probe,
.driver = {
.name = "gcc-mdm9615",
.of_match_table = gcc_mdm9615_match_table,
},
};
static int __init gcc_mdm9615_init(void)
{
return platform_driver_register(&gcc_mdm9615_driver);
}
core_initcall(gcc_mdm9615_init);
static void __exit gcc_mdm9615_exit(void)
{
platform_driver_unregister(&gcc_mdm9615_driver);
}
module_exit(gcc_mdm9615_exit);
MODULE_DESCRIPTION("QCOM GCC MDM9615 Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:gcc-mdm9615");
| linux-master | drivers/clk/qcom/gcc-mdm9615.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm8350-videocc.h>
#include <dt-bindings/reset/qcom,sm8350-videocc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "reset.h"
#include "gdsc.h"
enum {
DT_BI_TCXO,
DT_BI_TCXO_AO,
DT_SLEEP_CLK,
};
enum {
P_BI_TCXO,
P_BI_TCXO_AO,
P_SLEEP_CLK,
P_VIDEO_PLL0_OUT_MAIN,
P_VIDEO_PLL1_OUT_MAIN,
};
static const struct pll_vco lucid_5lpe_vco[] = {
{ 249600000, 1750000000, 0 },
};
static const struct pll_vco lucid_5lpe_vco_8280xp[] = {
{ 249600000, 1800000000, 0 },
};
static const struct alpha_pll_config video_pll0_config = {
.l = 0x25,
.alpha = 0x8000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x2a9a699c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000000,
.test_ctl_hi1_val = 0x01800000,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll video_pll0 = {
.offset = 0x42c,
.vco_table = lucid_5lpe_vco,
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "video_pll0",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_5lpe_ops,
},
},
};
static const struct alpha_pll_config video_pll1_config = {
.l = 0x2b,
.alpha = 0xc000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x2a9a699c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000000,
.test_ctl_hi1_val = 0x01800000,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll video_pll1 = {
.offset = 0x7d0,
.vco_table = lucid_5lpe_vco,
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "video_pll1",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_5lpe_ops,
},
},
};
static const struct parent_map video_cc_parent_map_0[] = {
{ P_BI_TCXO_AO, 0 },
};
static const struct clk_parent_data video_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO_AO },
};
static const struct parent_map video_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_PLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data video_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &video_pll0.clkr.hw },
};
static const struct parent_map video_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_PLL1_OUT_MAIN, 1 },
};
static const struct clk_parent_data video_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &video_pll1.clkr.hw },
};
static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_ahb_clk_src = {
.cmd_rcgr = 0xbd4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_0,
.freq_tbl = ftbl_video_cc_ahb_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_ahb_clk_src",
.parent_data = video_cc_parent_data_0,
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
F(720000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
F(1014000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_8280xp[] = {
F(720000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
F(1014000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
F(1599000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
F(1680000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs0_clk_src = {
.cmd_rcgr = 0xb94,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_1,
.freq_tbl = ftbl_video_cc_mvs0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_clk_src",
.parent_data = video_cc_parent_data_1,
.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
F(840000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
{ }
};
static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_8280xp[] = {
F(840000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
F(1600000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
F(1800000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs1_clk_src = {
.cmd_rcgr = 0xbb4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_2,
.freq_tbl = ftbl_video_cc_mvs1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1_clk_src",
.parent_data = video_cc_parent_data_2,
.num_parents = ARRAY_SIZE(video_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = {
F(32000, P_SLEEP_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_sleep_clk_src = {
.cmd_rcgr = 0xef0,
.mnd_width = 0,
.hid_width = 5,
.freq_tbl = ftbl_video_cc_sleep_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_sleep_clk_src",
.parent_data = &(const struct clk_parent_data){
.index = DT_SLEEP_CLK,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 video_cc_xo_clk_src = {
.cmd_rcgr = 0xecc,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_0,
.freq_tbl = ftbl_video_cc_ahb_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_xo_clk_src",
.parent_data = video_cc_parent_data_0,
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
.reg = 0xd54,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&video_cc_mvs0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
.reg = 0xc54,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_div2_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&video_cc_mvs0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
.reg = 0xdd4,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&video_cc_mvs1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
.reg = 0xcf4,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1c_div2_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&video_cc_mvs1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch video_cc_mvs0_clk = {
.halt_reg = 0xd34,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xd34,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xd34,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_mvs0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0c_clk = {
.halt_reg = 0xc34,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc34,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_mvs0c_div2_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs1_clk = {
.halt_reg = 0xdb4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xdb4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xdb4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_mvs1_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs1_div2_clk = {
.halt_reg = 0xdf4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xdf4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xdf4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1_div2_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_mvs1c_div2_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs1c_clk = {
.halt_reg = 0xcd4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xcd4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1c_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_mvs1c_div2_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_sleep_clk = {
.halt_reg = 0xf10,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf10,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_sleep_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc mvs0c_gdsc = {
.gdscr = 0xbf8,
.pd = {
.name = "mvs0c_gdsc",
},
.flags = RETAIN_FF_ENABLE,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc mvs1c_gdsc = {
.gdscr = 0xc98,
.pd = {
.name = "mvs1c_gdsc",
},
.flags = RETAIN_FF_ENABLE,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc mvs0_gdsc = {
.gdscr = 0xd18,
.pd = {
.name = "mvs0_gdsc",
},
.flags = HW_CTRL | RETAIN_FF_ENABLE,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc mvs1_gdsc = {
.gdscr = 0xd98,
.pd = {
.name = "mvs1_gdsc",
},
.flags = HW_CTRL | RETAIN_FF_ENABLE,
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *video_cc_sm8350_clocks[] = {
[VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr,
[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
[VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
[VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
[VIDEO_CC_MVS1_DIV2_CLK] = &video_cc_mvs1_div2_clk.clkr,
[VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
[VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
[VIDEO_CC_SLEEP_CLK] = &video_cc_sleep_clk.clkr,
[VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr,
[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr,
[VIDEO_PLL0] = &video_pll0.clkr,
[VIDEO_PLL1] = &video_pll1.clkr,
};
static const struct qcom_reset_map video_cc_sm8350_resets[] = {
[VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 },
[VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 },
[VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 },
[VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 },
[VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 },
[VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 },
[VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 },
};
static struct gdsc *video_cc_sm8350_gdscs[] = {
[MVS0C_GDSC] = &mvs0c_gdsc,
[MVS1C_GDSC] = &mvs1c_gdsc,
[MVS0_GDSC] = &mvs0_gdsc,
[MVS1_GDSC] = &mvs1_gdsc,
};
static const struct regmap_config video_cc_sm8350_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x10000,
.fast_io = true,
};
static struct qcom_cc_desc video_cc_sm8350_desc = {
.config = &video_cc_sm8350_regmap_config,
.clks = video_cc_sm8350_clocks,
.num_clks = ARRAY_SIZE(video_cc_sm8350_clocks),
.resets = video_cc_sm8350_resets,
.num_resets = ARRAY_SIZE(video_cc_sm8350_resets),
.gdscs = video_cc_sm8350_gdscs,
.num_gdscs = ARRAY_SIZE(video_cc_sm8350_gdscs),
};
static int video_cc_sm8350_probe(struct platform_device *pdev)
{
u32 video_cc_xo_clk_cbcr = 0xeec;
struct regmap *regmap;
int ret;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8280xp-videocc")) {
video_cc_sleep_clk_src.cmd_rcgr = 0xf38;
video_cc_sleep_clk.halt_reg = 0xf58;
video_cc_sleep_clk.clkr.enable_reg = 0xf58;
video_cc_xo_clk_src.cmd_rcgr = 0xf14;
video_cc_xo_clk_cbcr = 0xf34;
video_pll0.vco_table = video_pll1.vco_table = lucid_5lpe_vco_8280xp;
/* No change, but assign it for completeness */
video_pll0.num_vco = video_pll1.num_vco = ARRAY_SIZE(lucid_5lpe_vco_8280xp);
video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_8280xp;
video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_8280xp;
}
regmap = qcom_cc_map(pdev, &video_cc_sm8350_desc);
if (IS_ERR(regmap)) {
pm_runtime_put(&pdev->dev);
return PTR_ERR(regmap);
}
clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config);
clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config);
/*
* Keep clocks always enabled:
* video_cc_ahb_clk
* video_cc_xo_clk
*/
regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0));
regmap_update_bits(regmap, video_cc_xo_clk_cbcr, BIT(0), BIT(0));
ret = qcom_cc_really_probe(pdev, &video_cc_sm8350_desc, regmap);
pm_runtime_put(&pdev->dev);
return ret;
}
static const struct of_device_id video_cc_sm8350_match_table[] = {
{ .compatible = "qcom,sc8280xp-videocc" },
{ .compatible = "qcom,sm8350-videocc" },
{ }
};
MODULE_DEVICE_TABLE(of, video_cc_sm8350_match_table);
static struct platform_driver video_cc_sm8350_driver = {
.probe = video_cc_sm8350_probe,
.driver = {
.name = "sm8350-videocc",
.of_match_table = video_cc_sm8350_match_table,
},
};
module_platform_driver(video_cc_sm8350_driver);
MODULE_DESCRIPTION("QTI SM8350 VIDEOCC Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/videocc-sm8350.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,videocc-sm8250.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_BI_TCXO,
P_VIDEO_PLL0_OUT_MAIN,
P_VIDEO_PLL1_OUT_MAIN,
};
static struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
static const struct alpha_pll_config video_pll0_config = {
.l = 0x25,
.alpha = 0x8000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329A699C,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll video_pll0 = {
.offset = 0x42c,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "video_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct alpha_pll_config video_pll1_config = {
.l = 0x2B,
.alpha = 0xC000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329A699C,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll video_pll1 = {
.offset = 0x7d0,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "video_pll1",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct parent_map video_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_PLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data video_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &video_pll0.clkr.hw },
};
static const struct parent_map video_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_PLL1_OUT_MAIN, 1 },
};
static const struct clk_parent_data video_cc_parent_data_2[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &video_pll1.clkr.hw },
};
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(720000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
F(1014000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs0_clk_src = {
.cmd_rcgr = 0xb94,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_1,
.freq_tbl = ftbl_video_cc_mvs0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "video_cc_mvs0_clk_src",
.parent_data = video_cc_parent_data_1,
.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(840000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs1_clk_src = {
.cmd_rcgr = 0xbb4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_2,
.freq_tbl = ftbl_video_cc_mvs1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "video_cc_mvs1_clk_src",
.parent_data = video_cc_parent_data_2,
.num_parents = ARRAY_SIZE(video_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
.reg = 0xc54,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "video_cc_mvs0c_div2_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&video_cc_mvs0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
.reg = 0xd54,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "video_cc_mvs0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&video_cc_mvs0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
.reg = 0xcf4,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "video_cc_mvs1c_div2_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&video_cc_mvs1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch video_cc_mvs0c_clk = {
.halt_reg = 0xc34,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc34,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_mvs0c_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_mvs0c_div2_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0_clk = {
.halt_reg = 0xd34,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xd34,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_mvs0_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_mvs0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs1_div2_clk = {
.halt_reg = 0xdf4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xdf4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_mvs1_div2_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_mvs1c_div2_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs1c_clk = {
.halt_reg = 0xcd4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xcd4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_cc_mvs1c_clk",
.parent_hws = (const struct clk_hw*[]){
&video_cc_mvs1c_div2_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc mvs0c_gdsc = {
.gdscr = 0xbf8,
.pd = {
.name = "mvs0c_gdsc",
},
.flags = 0,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc mvs1c_gdsc = {
.gdscr = 0xc98,
.pd = {
.name = "mvs1c_gdsc",
},
.flags = 0,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc mvs0_gdsc = {
.gdscr = 0xd18,
.pd = {
.name = "mvs0_gdsc",
},
.flags = HW_CTRL,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc mvs1_gdsc = {
.gdscr = 0xd98,
.pd = {
.name = "mvs1_gdsc",
},
.flags = HW_CTRL,
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *video_cc_sm8250_clocks[] = {
[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
[VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
[VIDEO_CC_MVS1_DIV2_CLK] = &video_cc_mvs1_div2_clk.clkr,
[VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
[VIDEO_CC_PLL0] = &video_pll0.clkr,
[VIDEO_CC_PLL1] = &video_pll1.clkr,
};
static const struct qcom_reset_map video_cc_sm8250_resets[] = {
[VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 },
[VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 },
[VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 },
[VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 },
[VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 },
[VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 },
[VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 },
};
static struct gdsc *video_cc_sm8250_gdscs[] = {
[MVS0C_GDSC] = &mvs0c_gdsc,
[MVS1C_GDSC] = &mvs1c_gdsc,
[MVS0_GDSC] = &mvs0_gdsc,
[MVS1_GDSC] = &mvs1_gdsc,
};
static const struct regmap_config video_cc_sm8250_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xf4c,
.fast_io = true,
};
static const struct qcom_cc_desc video_cc_sm8250_desc = {
.config = &video_cc_sm8250_regmap_config,
.clks = video_cc_sm8250_clocks,
.num_clks = ARRAY_SIZE(video_cc_sm8250_clocks),
.resets = video_cc_sm8250_resets,
.num_resets = ARRAY_SIZE(video_cc_sm8250_resets),
.gdscs = video_cc_sm8250_gdscs,
.num_gdscs = ARRAY_SIZE(video_cc_sm8250_gdscs),
};
static const struct of_device_id video_cc_sm8250_match_table[] = {
{ .compatible = "qcom,sm8250-videocc" },
{ }
};
MODULE_DEVICE_TABLE(of, video_cc_sm8250_match_table);
static int video_cc_sm8250_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
regmap = qcom_cc_map(pdev, &video_cc_sm8250_desc);
if (IS_ERR(regmap)) {
pm_runtime_put(&pdev->dev);
return PTR_ERR(regmap);
}
clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config);
clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config);
/* Keep VIDEO_CC_AHB_CLK and VIDEO_CC_XO_CLK ALWAYS-ON */
regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0));
regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0));
ret = qcom_cc_really_probe(pdev, &video_cc_sm8250_desc, regmap);
pm_runtime_put(&pdev->dev);
return ret;
}
static struct platform_driver video_cc_sm8250_driver = {
.probe = video_cc_sm8250_probe,
.driver = {
.name = "sm8250-videocc",
.of_match_table = video_cc_sm8250_match_table,
},
};
static int __init video_cc_sm8250_init(void)
{
return platform_driver_register(&video_cc_sm8250_driver);
}
subsys_initcall(video_cc_sm8250_init);
static void __exit video_cc_sm8250_exit(void)
{
platform_driver_unregister(&video_cc_sm8250_driver);
}
module_exit(video_cc_sm8250_exit);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("QTI VIDEOCC SM8250 Driver");
| linux-master | drivers/clk/qcom/videocc-sm8250.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm8550-gpucc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_GPLL0_OUT_MAIN,
DT_GPLL0_OUT_MAIN_DIV,
};
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL1_OUT_MAIN,
};
static const struct pll_vco lucid_ole_vco[] = {
{ 249600000, 2300000000, 0 },
};
static const struct alpha_pll_config gpu_cc_pll0_config = {
/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
.l = 0x4444000d,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct alpha_pll_config gpu_cc_pll1_config = {
/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
.l = 0x44440016,
.alpha = 0xeaaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct parent_map gpu_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GPLL0_OUT_MAIN },
{ .index = DT_GPLL0_OUT_MAIN_DIV },
};
static const struct parent_map gpu_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gpu_cc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
};
static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_ff_clk_src = {
.cmd_rcgr = 0x9474,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_ff_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(220000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(550000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x9318,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_1,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_hub_clk_src = {
.cmd_rcgr = 0x93ec,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_2,
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_clk_src",
.parent_data = gpu_cc_parent_data_2,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_xo_clk_src = {
.cmd_rcgr = 0x9010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_3,
.freq_tbl = ftbl_gpu_cc_xo_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_xo_clk_src",
.parent_data = gpu_cc_parent_data_3,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
.reg = 0x9054,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_demet_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gpu_cc_xo_div_clk_src = {
.reg = 0x9050,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_xo_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x911c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x911c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x9120,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9120,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_crc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_ff_clk = {
.halt_reg = 0x914c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x914c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cx_ff_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_ff_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x913c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x913c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x9144,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9144,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_cxo_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_freq_measure_clk = {
.halt_reg = 0x9008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_freq_measure_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_xo_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
.halt_reg = 0x7000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hub_aon_clk = {
.halt_reg = 0x93e8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x93e8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_aon_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_hub_cx_int_clk = {
.halt_reg = 0x9148,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9148,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_cx_int_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_memnoc_gfx_clk = {
.halt_reg = 0x9150,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9150,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
.halt_reg = 0x9288,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9288,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_mnd1x_0_gfx3d_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
.halt_reg = 0x928c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x928c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_mnd1x_1_gfx3d_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_sleep_clk = {
.halt_reg = 0x9134,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9134,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cc_cx_gdsc = {
.gdscr = 0x9108,
.gds_hw_ctrl = 0x953c,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gpu_cc_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE | VOTABLE,
};
static struct gdsc gpu_cc_gx_gdsc = {
.gdscr = 0x905c,
.clamp_io_ctrl = 0x9504,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gpu_cc_gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct clk_regmap *gpu_cc_sm8550_clocks[] = {
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
[GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
[GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
[GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
[GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
[GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr,
};
static struct gdsc *gpu_cc_sm8550_gdscs[] = {
[GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc,
[GPU_CC_GX_GDSC] = &gpu_cc_gx_gdsc,
};
static const struct qcom_reset_map gpu_cc_sm8550_resets[] = {
[GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },
[GPUCC_GPU_CC_CX_BCR] = { 0x9104 },
[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
[GPUCC_GPU_CC_FF_BCR] = { 0x9470 },
[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
[GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
[GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
[GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
};
static const struct regmap_config gpu_cc_sm8550_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9988,
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_sm8550_desc = {
.config = &gpu_cc_sm8550_regmap_config,
.clks = gpu_cc_sm8550_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sm8550_clocks),
.resets = gpu_cc_sm8550_resets,
.num_resets = ARRAY_SIZE(gpu_cc_sm8550_resets),
.gdscs = gpu_cc_sm8550_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sm8550_gdscs),
};
static const struct of_device_id gpu_cc_sm8550_match_table[] = {
{ .compatible = "qcom,sm8550-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sm8550_match_table);
static int gpu_cc_sm8550_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gpu_cc_sm8550_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
/*
* Keep clocks always enabled:
* gpu_cc_cxo_aon_clk
* gpu_cc_demet_clk
*/
regmap_update_bits(regmap, 0x9004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x900c, BIT(0), BIT(0));
return qcom_cc_really_probe(pdev, &gpu_cc_sm8550_desc, regmap);
}
static struct platform_driver gpu_cc_sm8550_driver = {
.probe = gpu_cc_sm8550_probe,
.driver = {
.name = "gpu_cc-sm8550",
.of_match_table = gpu_cc_sm8550_match_table,
},
};
static int __init gpu_cc_sm8550_init(void)
{
return platform_driver_register(&gpu_cc_sm8550_driver);
}
subsys_initcall(gpu_cc_sm8550_init);
static void __exit gpu_cc_sm8550_exit(void)
{
platform_driver_unregister(&gpu_cc_sm8550_driver);
}
module_exit(gpu_cc_sm8550_exit);
MODULE_DESCRIPTION("QTI GPUCC SM8550 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/gpucc-sm8550.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Qualcomm A7 PLL driver
*
* Copyright (c) 2020, Linaro Limited
* Author: Manivannan Sadhasivam <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "clk-alpha-pll.h"
#define LUCID_PLL_OFF_L_VAL 0x04
static const struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
static struct clk_alpha_pll a7pll = {
.offset = 0x100,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "a7pll",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct alpha_pll_config a7pll_config = {
.l = 0x39,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x2261,
.config_ctl_hi1_val = 0x029A699C,
.user_ctl_val = 0x1,
.user_ctl_hi_val = 0x805,
};
static const struct regmap_config a7pll_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x1000,
.fast_io = true,
};
static int qcom_a7pll_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct regmap *regmap;
void __iomem *base;
u32 l_val;
int ret;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
regmap = devm_regmap_init_mmio(dev, base, &a7pll_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Configure PLL only if the l_val is zero */
regmap_read(regmap, a7pll.offset + LUCID_PLL_OFF_L_VAL, &l_val);
if (!l_val)
clk_lucid_pll_configure(&a7pll, regmap, &a7pll_config);
ret = devm_clk_register_regmap(dev, &a7pll.clkr);
if (ret)
return ret;
return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
&a7pll.clkr.hw);
}
static const struct of_device_id qcom_a7pll_match_table[] = {
{ .compatible = "qcom,sdx55-a7pll" },
{ }
};
MODULE_DEVICE_TABLE(of, qcom_a7pll_match_table);
static struct platform_driver qcom_a7pll_driver = {
.probe = qcom_a7pll_probe,
.driver = {
.name = "qcom-a7pll",
.of_match_table = qcom_a7pll_match_table,
},
};
module_platform_driver(qcom_a7pll_driver);
MODULE_DESCRIPTION("Qualcomm A7 PLL Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/a7-pll.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022, Linaro Ltd.
*/
#include <linux/clk-provider.h>
#include <linux/bitfield.h>
#include <linux/regmap.h>
#include <linux/export.h>
#include "clk-regmap.h"
#include "clk-regmap-phy-mux.h"
#define PHY_MUX_MASK GENMASK(1, 0)
#define PHY_MUX_PHY_SRC 0
#define PHY_MUX_REF_SRC 2
static inline struct clk_regmap_phy_mux *to_clk_regmap_phy_mux(struct clk_regmap *clkr)
{
return container_of(clkr, struct clk_regmap_phy_mux, clkr);
}
static int phy_mux_is_enabled(struct clk_hw *hw)
{
struct clk_regmap *clkr = to_clk_regmap(hw);
struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr);
unsigned int val;
regmap_read(clkr->regmap, phy_mux->reg, &val);
val = FIELD_GET(PHY_MUX_MASK, val);
WARN_ON(val != PHY_MUX_PHY_SRC && val != PHY_MUX_REF_SRC);
return val == PHY_MUX_PHY_SRC;
}
static int phy_mux_enable(struct clk_hw *hw)
{
struct clk_regmap *clkr = to_clk_regmap(hw);
struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr);
return regmap_update_bits(clkr->regmap, phy_mux->reg,
PHY_MUX_MASK,
FIELD_PREP(PHY_MUX_MASK, PHY_MUX_PHY_SRC));
}
static void phy_mux_disable(struct clk_hw *hw)
{
struct clk_regmap *clkr = to_clk_regmap(hw);
struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr);
regmap_update_bits(clkr->regmap, phy_mux->reg,
PHY_MUX_MASK,
FIELD_PREP(PHY_MUX_MASK, PHY_MUX_REF_SRC));
}
const struct clk_ops clk_regmap_phy_mux_ops = {
.enable = phy_mux_enable,
.disable = phy_mux_disable,
.is_enabled = phy_mux_is_enabled,
};
EXPORT_SYMBOL_GPL(clk_regmap_phy_mux_ops);
| linux-master | drivers/clk/qcom/clk-regmap-phy-mux.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
#include "common.h"
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_CC_PLL1_OUT_MAIN,
};
static const struct pll_vco trion_vco[] = {
{ 249600000, 2000000000, 0 },
};
static struct alpha_pll_config gpu_cc_pll1_config = {
.l = 0x1a,
.alpha = 0xaaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002267,
.config_ctl_hi1_val = 0x00000024,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000002,
.test_ctl_hi1_val = 0x00000000,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x000000d0,
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x100,
.vco_table = trion_vco,
.num_vco = ARRAY_SIZE(trion_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_trion_ops,
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .fw_name = "gcc_gpu_gpll0_clk_src" },
{ .fw_name = "gcc_gpu_gpll0_div_clk_src" },
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
{ }
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src_sc8180x[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x1120,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x1078,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x107c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x107c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_crc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_apb_clk = {
.halt_reg = 0x1088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_apb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x1098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
.halt_reg = 0x108c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x108c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_snoc_dvm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_aon_clk = {
.halt_reg = 0x1004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_aon_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x109c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x109c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gmu_clk = {
.halt_reg = 0x1064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x106c,
.gds_hw_ctrl = 0x1540,
.pd = {
.name = "gpu_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x100c,
.clamp_io_ctrl = 0x1508,
.pd = {
.name = "gpu_gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
};
static struct clk_regmap *gpu_cc_sm8150_clocks[] = {
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
};
static const struct qcom_reset_map gpu_cc_sm8150_resets[] = {
[GPUCC_GPU_CC_CX_BCR] = { 0x1068 },
[GPUCC_GPU_CC_GMU_BCR] = { 0x111c },
[GPUCC_GPU_CC_GX_BCR] = { 0x1008 },
[GPUCC_GPU_CC_SPDM_BCR] = { 0x1110 },
[GPUCC_GPU_CC_XO_BCR] = { 0x1000 },
};
static struct gdsc *gpu_cc_sm8150_gdscs[] = {
[GPU_CX_GDSC] = &gpu_cx_gdsc,
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
static const struct regmap_config gpu_cc_sm8150_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x8008,
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_sm8150_desc = {
.config = &gpu_cc_sm8150_regmap_config,
.clks = gpu_cc_sm8150_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sm8150_clocks),
.resets = gpu_cc_sm8150_resets,
.num_resets = ARRAY_SIZE(gpu_cc_sm8150_resets),
.gdscs = gpu_cc_sm8150_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sm8150_gdscs),
};
static const struct of_device_id gpu_cc_sm8150_match_table[] = {
{ .compatible = "qcom,sc8180x-gpucc" },
{ .compatible = "qcom,sm8150-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sm8150_match_table);
static int gpu_cc_sm8150_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gpu_cc_sm8150_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-gpucc"))
gpu_cc_gmu_clk_src.freq_tbl = ftbl_gpu_cc_gmu_clk_src_sc8180x;
clk_trion_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
return qcom_cc_really_probe(pdev, &gpu_cc_sm8150_desc, regmap);
}
static struct platform_driver gpu_cc_sm8150_driver = {
.probe = gpu_cc_sm8150_probe,
.driver = {
.name = "sm8150-gpucc",
.of_match_table = gpu_cc_sm8150_match_table,
},
};
static int __init gpu_cc_sm8150_init(void)
{
return platform_driver_register(&gpu_cc_sm8150_driver);
}
subsys_initcall(gpu_cc_sm8150_init);
static void __exit gpu_cc_sm8150_exit(void)
{
platform_driver_unregister(&gpu_cc_sm8150_driver);
}
module_exit(gpu_cc_sm8150_exit);
MODULE_DESCRIPTION("QTI GPUCC SM8150 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gpucc-sm8150.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Konrad Dybcio <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-sm6350.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_GPLL0_OUT_EVEN,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_ODD,
P_GPLL6_OUT_EVEN,
P_GPLL7_OUT_MAIN,
P_SLEEP_CLK,
};
static struct clk_alpha_pll gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll0_out_even = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_even",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static const struct clk_div_table post_div_table_gpll0_out_odd[] = {
{ 0x3, 3 },
{ }
};
static struct clk_alpha_pll_postdiv gpll0_out_odd = {
.offset = 0x0,
.post_div_shift = 12,
.post_div_table = post_div_table_gpll0_out_odd,
.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_odd),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_odd",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll gpll6 = {
.offset = 0x6000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gpll6",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll6_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll6_out_even = {
.offset = 0x6000,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll6_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll6_out_even",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll gpll7 = {
.offset = 0x7000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gpll7",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL6_OUT_EVEN, 2 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6_out_even.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_ODD, 2 },
};
static const struct clk_parent_data gcc_parent_data_2_ao[] = {
{ .fw_name = "bi_tcxo_ao" },
{ .hw = &gpll0_out_odd.clkr.hw },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_ODD, 2 },
};
static const struct clk_parent_data gcc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_odd.clkr.hw },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_ODD, 2 },
{ P_SLEEP_CLK, 5 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0_out_odd.clkr.hw },
{ .fw_name = "sleep_clk" },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_6[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "sleep_clk" }
};
static const struct parent_map gcc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL6_OUT_EVEN, 2 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_7[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll6_out_even.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_ODD, 2 },
{ P_GPLL7_OUT_MAIN, 3 },
};
static const struct clk_parent_data gcc_parent_data_8[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0_out_odd.clkr.hw },
{ .hw = &gpll7.clkr.hw },
};
static struct clk_regmap_div gcc_gpu_gpll0_main_div_clk_src = {
.reg = 0x4514C,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_gpu_gpll0_main_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_npu_pll0_main_div_clk_src = {
.reg = 0x4ce00,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_npu_pll0_main_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
},
};
static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
.cmd_rcgr = 0x30014,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk_src",
.parent_data = gcc_parent_data_2_ao,
.num_parents = ARRAY_SIZE(gcc_parent_data_2_ao),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x37004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x38004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x39004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x23010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
F(128000000, P_GPLL6_OUT_EVEN, 3, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x21148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.cmd_rcgr = 0x21278,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.cmd_rcgr = 0x213a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.cmd_rcgr = 0x214d8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.cmd_rcgr = 0x21608,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.cmd_rcgr = 0x21738,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.cmd_rcgr = 0x22018,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.cmd_rcgr = 0x22148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.cmd_rcgr = 0x22278,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.cmd_rcgr = 0x223a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.cmd_rcgr = 0x224d8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.cmd_rcgr = 0x22608,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
F(144000, P_BI_TCXO, 16, 3, 25),
F(400000, P_BI_TCXO, 12, 1, 4),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(192000000, P_GPLL6_OUT_EVEN, 2, 0, 0),
F(384000000, P_GPLL6_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.cmd_rcgr = 0x4b024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x4b00c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_ODD, 8, 0, 0),
F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.cmd_rcgr = 0x2000c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.flags = CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
F(25000000, P_GPLL0_OUT_ODD, 8, 0, 0),
F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.cmd_rcgr = 0x3a01c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.cmd_rcgr = 0x3a048,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
.cmd_rcgr = 0x3a0b0,
.mnd_width = 0,
.hid_width = 5,
.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.cmd_rcgr = 0x3a060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
F(66666667, P_GPLL0_OUT_ODD, 3, 0, 0),
F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.cmd_rcgr = 0x1a01c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.cmd_rcgr = 0x1a034,
.mnd_width = 0,
.hid_width = 5,
.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.cmd_rcgr = 0x1a060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
.halt_reg = 0x3e014,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x3e014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3e014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
.halt_reg = 0x3e014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x3e014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3e014,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
.halt_reg = 0x3e014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x3e014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3e014,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
.halt_reg = 0x3e010,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x3e010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3e010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x26004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x26004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_ahb_clk = {
.halt_reg = 0x17008,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x17008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_axi_clk = {
.halt_reg = 0x17018,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x17018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_throttle_nrt_axi_clk = {
.halt_reg = 0x17078,
.halt_check = BRANCH_VOTED,
.hwcg_reg = 0x17078,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_throttle_nrt_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_throttle_rt_axi_clk = {
.halt_reg = 0x17024,
.halt_check = BRANCH_VOTED,
.hwcg_reg = 0x17024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_throttle_rt_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_xo_clk = {
.halt_reg = 0x17030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_ahb_clk = {
.halt_reg = 0x2b00c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2b00c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_axi_clk = {
.halt_reg = 0x2b008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_clk = {
.halt_reg = 0x2b004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.halt_reg = 0x1101c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1101c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1101c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_ahb_clk = {
.halt_reg = 0x30000,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x30000,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_cpuss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_gnoc_clk = {
.halt_reg = 0x30004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x30004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_gnoc_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_rbcpr_clk = {
.halt_reg = 0x30008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x30008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_rbcpr_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ddrss_gpu_axi_clk = {
.halt_reg = 0x2d038,
.halt_check = BRANCH_VOTED,
.hwcg_reg = 0x2d038,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2d038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ddrss_gpu_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_ahb_clk = {
.halt_reg = 0x1700c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1700c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1700c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_axi_clk = {
.halt_reg = 0x1701c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x1701c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1701c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_cc_sleep_clk = {
.halt_reg = 0x17074,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x17074,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17074,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_cc_xo_clk = {
.halt_reg = 0x17070,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x17070,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17070,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_cc_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_gpll0_clk = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_gpll0_clk",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_throttle_axi_clk = {
.halt_reg = 0x17028,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x17028,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_throttle_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_xo_clk = {
.halt_reg = 0x17034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x37000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x37000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x38000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x38000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x39000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_cfg_ahb_clk = {
.halt_reg = 0x45004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x45004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_cfg_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_clk = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_div_clk = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gpu_gpll0_main_div_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
.halt_reg = 0x4500c,
.halt_check = BRANCH_VOTED,
.hwcg_reg = 0x4500c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
.halt_reg = 0x45014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x45014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x45014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_snoc_dvm_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_axi_clk = {
.halt_reg = 0x4c008,
.halt_check = BRANCH_VOTED,
.hwcg_reg = 0x4c008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4c008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_bwmon_axi_clk = {
.halt_reg = 0x4d004,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x4d004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4d004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_bwmon_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk = {
.halt_reg = 0x4d008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_bwmon_dma_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk = {
.halt_reg = 0x4d00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_bwmon_dsp_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_cfg_ahb_clk = {
.halt_reg = 0x4c004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x4c004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4c004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_cfg_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_dma_clk = {
.halt_reg = 0x4c140,
.halt_check = BRANCH_VOTED,
.hwcg_reg = 0x4c140,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4c140,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_dma_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_gpll0_clk = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_gpll0_clk",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_gpll0_div_clk = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_gpll0_div_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_npu_pll0_main_div_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x2300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x23004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x23004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x23004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x23008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x23008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x24004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x24004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
.halt_reg = 0x21014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_clk = {
.halt_reg = 0x2100c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.halt_reg = 0x21144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.halt_reg = 0x21274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.halt_reg = 0x213a4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.halt_reg = 0x214d4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.halt_reg = 0x21604,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.halt_reg = 0x21734,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
.halt_reg = 0x22004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_clk = {
.halt_reg = 0x22008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.halt_reg = 0x22014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.halt_reg = 0x22144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.halt_reg = 0x22274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.halt_reg = 0x223a4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.halt_reg = 0x224d4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.halt_reg = 0x22604,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
.halt_reg = 0x21004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x21004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
.halt_reg = 0x21008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x21008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
.halt_reg = 0x2200c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2200c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
.halt_reg = 0x22010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x22010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x4b004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4b004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x4b008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0x4b03c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x4b03c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4b03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc1_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x20008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x20004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
.halt_reg = 0x10140,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x10140,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_cpuss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_cpuss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_mem_clkref_clk = {
.halt_reg = 0x8c000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_mem_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x3a00c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x3a00c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3a00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_clk = {
.halt_reg = 0x3a034,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x3a034,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3a034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.halt_reg = 0x3a0a4,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x3a0a4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3a0a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
.halt_reg = 0x3a0a4,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x3a0a4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3a0a4,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.halt_reg = 0x3a0ac,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x3a0ac,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3a0ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
.halt_reg = 0x3a0ac,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x3a0ac,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3a0ac,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.halt_reg = 0x3a014,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x3a014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
.halt_reg = 0x3a018,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x3a018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
.halt_reg = 0x3a010,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x3a010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.halt_reg = 0x3a09c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x3a09c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3a09c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
.halt_reg = 0x3a09c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x3a09c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3a09c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_master_clk = {
.halt_reg = 0x1a00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0x1a018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_sleep_clk = {
.halt_reg = 0x1a014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_clkref_clk = {
.halt_reg = 0x8c010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
.halt_reg = 0x1a050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.halt_reg = 0x1a054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_reg = 0x1a058,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x1a058,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1a058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_ahb_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x17004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi_clk = {
.halt_reg = 0x17014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x17014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_throttle_axi_clk = {
.halt_reg = 0x17020,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x17020,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_throttle_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_xo_clk = {
.halt_reg = 0x1702c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1702c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc usb30_prim_gdsc = {
.gdscr = 0x1a004,
.pd = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
};
static struct gdsc ufs_phy_gdsc = {
.gdscr = 0x3a004,
.pd = {
.name = "ufs_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
.gdscr = 0xb7040,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
.gdscr = 0xb7044,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct clk_regmap *gcc_sm6350_clocks[] = {
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
[GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr,
[GCC_CAMERA_THROTTLE_NRT_AXI_CLK] =
&gcc_camera_throttle_nrt_axi_clk.clkr,
[GCC_CAMERA_THROTTLE_RT_AXI_CLK] = &gcc_camera_throttle_rt_axi_clk.clkr,
[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
[GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
[GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
[GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
[GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
[GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
[GCC_DISP_CC_SLEEP_CLK] = &gcc_disp_cc_sleep_clk.clkr,
[GCC_DISP_CC_XO_CLK] = &gcc_disp_cc_xo_clk.clkr,
[GCC_DISP_GPLL0_CLK] = &gcc_disp_gpll0_clk.clkr,
[GCC_DISP_THROTTLE_AXI_CLK] = &gcc_disp_throttle_axi_clk.clkr,
[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
[GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
[GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
[GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr,
[GCC_NPU_BWMON_DMA_CFG_AHB_CLK] = &gcc_npu_bwmon_dma_cfg_ahb_clk.clkr,
[GCC_NPU_BWMON_DSP_CFG_AHB_CLK] = &gcc_npu_bwmon_dsp_cfg_ahb_clk.clkr,
[GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
[GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr,
[GCC_NPU_GPLL0_CLK] = &gcc_npu_gpll0_clk.clkr,
[GCC_NPU_GPLL0_DIV_CLK] = &gcc_npu_gpll0_div_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
[GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
&gcc_ufs_phy_unipro_core_clk_src.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
&gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
[GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
[GCC_VIDEO_THROTTLE_AXI_CLK] = &gcc_video_throttle_axi_clk.clkr,
[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
[GPLL0_OUT_ODD] = &gpll0_out_odd.clkr,
[GPLL6] = &gpll6.clkr,
[GPLL6_OUT_EVEN] = &gpll6_out_even.clkr,
[GPLL7] = &gpll7.clkr,
[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] =
&gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =
&gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] =
&gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
[GCC_GPU_GPLL0_MAIN_DIV_CLK_SRC] = &gcc_gpu_gpll0_main_div_clk_src.clkr,
[GCC_NPU_PLL0_MAIN_DIV_CLK_SRC] = &gcc_npu_pll0_main_div_clk_src.clkr,
};
static struct gdsc *gcc_sm6350_gdscs[] = {
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
[UFS_PHY_GDSC] = &ufs_phy_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
};
static const struct qcom_reset_map gcc_sm6350_resets[] = {
[GCC_QUSB2PHY_PRIM_BCR] = { 0x1d000 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x1e000 },
[GCC_SDCC1_BCR] = { 0x4b000 },
[GCC_SDCC2_BCR] = { 0x20000 },
[GCC_UFS_PHY_BCR] = { 0x3a000 },
[GCC_USB30_PRIM_BCR] = { 0x1a000 },
[GCC_USB3_PHY_PRIM_BCR] = { 0x1c000 },
[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x1c008 },
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
};
static const struct regmap_config gcc_sm6350_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xbf030,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_sm6350_desc = {
.config = &gcc_sm6350_regmap_config,
.clks = gcc_sm6350_clocks,
.num_clks = ARRAY_SIZE(gcc_sm6350_clocks),
.resets = gcc_sm6350_resets,
.num_resets = ARRAY_SIZE(gcc_sm6350_resets),
.gdscs = gcc_sm6350_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sm6350_gdscs),
};
static const struct of_device_id gcc_sm6350_match_table[] = {
{ .compatible = "qcom,gcc-sm6350" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_sm6350_match_table);
static int gcc_sm6350_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sm6350_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Disable the GPLL0 active input to NPU and GPU via MISC registers */
regmap_update_bits(regmap, 0x4cf00, 0x3, 0x3);
regmap_update_bits(regmap, 0x45f00, 0x3, 0x3);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
return qcom_cc_really_probe(pdev, &gcc_sm6350_desc, regmap);
}
static struct platform_driver gcc_sm6350_driver = {
.probe = gcc_sm6350_probe,
.driver = {
.name = "gcc-sm6350",
.of_match_table = gcc_sm6350_match_table,
},
};
static int __init gcc_sm6350_init(void)
{
return platform_driver_register(&gcc_sm6350_driver);
}
core_initcall(gcc_sm6350_init);
static void __exit gcc_sm6350_exit(void)
{
platform_driver_unregister(&gcc_sm6350_driver);
}
module_exit(gcc_sm6350_exit);
MODULE_DESCRIPTION("QTI GCC SM6350 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gcc-sm6350.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2015 Linaro Limited
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
#include <dt-bindings/reset/qcom,gcc-msm8916.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_XO,
P_GPLL0,
P_GPLL0_AUX,
P_BIMC,
P_GPLL1,
P_GPLL1_AUX,
P_GPLL2,
P_GPLL2_AUX,
P_SLEEP_CLK,
P_DSI0_PHYPLL_BYTE,
P_DSI0_PHYPLL_DSI,
P_EXT_PRI_I2S,
P_EXT_SEC_I2S,
P_EXT_MCLK,
};
static struct clk_pll gpll0 = {
.l_reg = 0x21004,
.m_reg = 0x21008,
.n_reg = 0x2100c,
.config_reg = 0x21010,
.mode_reg = 0x21000,
.status_reg = 0x2101c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo", .name = "xo_board",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll0_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_vote",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll gpll1 = {
.l_reg = 0x20004,
.m_reg = 0x20008,
.n_reg = 0x2000c,
.config_reg = 0x20010,
.mode_reg = 0x20000,
.status_reg = 0x2001c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll1",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo", .name = "xo_board",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll1_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gpll1_vote",
.parent_hws = (const struct clk_hw*[]){
&gpll1.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll gpll2 = {
.l_reg = 0x4a004,
.m_reg = 0x4a008,
.n_reg = 0x4a00c,
.config_reg = 0x4a010,
.mode_reg = 0x4a000,
.status_reg = 0x4a01c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll2",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo", .name = "xo_board",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll2_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gpll2_vote",
.parent_hws = (const struct clk_hw*[]){
&gpll2.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll bimc_pll = {
.l_reg = 0x23004,
.m_reg = 0x23008,
.n_reg = 0x2300c,
.config_reg = 0x23010,
.mode_reg = 0x23000,
.status_reg = 0x2301c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "bimc_pll",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo", .name = "xo_board",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap bimc_pll_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "bimc_pll_vote",
.parent_hws = (const struct clk_hw*[]){
&bimc_pll.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static const struct parent_map gcc_xo_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
};
static const struct clk_parent_data gcc_xo_gpll0[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll0_vote.hw },
};
static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_BIMC, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0_bimc[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll0_vote.hw },
{ .hw = &bimc_pll_vote.hw },
};
static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = {
{ P_XO, 0 },
{ P_GPLL0_AUX, 3 },
{ P_GPLL1, 1 },
{ P_GPLL2_AUX, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0a_gpll1_gpll2a[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll1_vote.hw },
{ .hw = &gpll2_vote.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL2, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll2_vote.hw },
};
static const struct parent_map gcc_xo_gpll0a_map[] = {
{ P_XO, 0 },
{ P_GPLL0_AUX, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0a[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll0_vote.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL1_AUX, 2 },
{ P_SLEEP_CLK, 6 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll1a_sleep[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll1_vote.hw },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL1_AUX, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll1a[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll1_vote.hw },
};
static const struct parent_map gcc_xo_dsibyte_map[] = {
{ P_XO, 0, },
{ P_DSI0_PHYPLL_BYTE, 2 },
};
static const struct clk_parent_data gcc_xo_dsibyte[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
};
static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
{ P_XO, 0 },
{ P_GPLL0_AUX, 2 },
{ P_DSI0_PHYPLL_BYTE, 1 },
};
static const struct clk_parent_data gcc_xo_gpll0a_dsibyte[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll0_vote.hw },
{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
};
static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_DSI0_PHYPLL_DSI, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0_dsiphy[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll0_vote.hw },
{ .fw_name = "dsi0pll", .name = "dsi0pll" },
};
static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
{ P_XO, 0 },
{ P_GPLL0_AUX, 2 },
{ P_DSI0_PHYPLL_DSI, 1 },
};
static const struct clk_parent_data gcc_xo_gpll0a_dsiphy[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll0_vote.hw },
{ .fw_name = "dsi0pll", .name = "dsi0pll" },
};
static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = {
{ P_XO, 0 },
{ P_GPLL0_AUX, 1 },
{ P_GPLL1, 3 },
{ P_GPLL2, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0a_gpll1_gpll2[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll1_vote.hw },
{ .hw = &gpll2_vote.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL1, 2 },
{ P_SLEEP_CLK, 6 }
};
static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll1_vote.hw },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
{ P_XO, 0 },
{ P_GPLL1, 1 },
{ P_EXT_PRI_I2S, 2 },
{ P_EXT_MCLK, 3 },
{ P_SLEEP_CLK, 6 }
};
static const struct clk_parent_data gcc_xo_gpll1_epi2s_emclk_sleep[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll1_vote.hw },
{ .fw_name = "ext_pri_i2s", .name = "ext_pri_i2s" },
{ .fw_name = "ext_mclk", .name = "ext_mclk" },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
{ P_XO, 0 },
{ P_GPLL1, 1 },
{ P_EXT_SEC_I2S, 2 },
{ P_EXT_MCLK, 3 },
{ P_SLEEP_CLK, 6 }
};
static const struct clk_parent_data gcc_xo_gpll1_esi2s_emclk_sleep[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll1_vote.hw },
{ .fw_name = "ext_sec_i2s", .name = "ext_sec_i2s" },
{ .fw_name = "ext_mclk", .name = "ext_mclk" },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct parent_map gcc_xo_sleep_map[] = {
{ P_XO, 0 },
{ P_SLEEP_CLK, 6 }
};
static const struct clk_parent_data gcc_xo_sleep[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
{ P_XO, 0 },
{ P_GPLL1, 1 },
{ P_EXT_MCLK, 2 },
{ P_SLEEP_CLK, 6 }
};
static const struct clk_parent_data gcc_xo_gpll1_emclk_sleep[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll1_vote.hw },
{ .fw_name = "ext_mclk", .name = "ext_mclk" },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
.cmd_rcgr = 0x27000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_bimc_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcnoc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_bimc,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 system_noc_bfdcd_clk_src = {
.cmd_rcgr = 0x26004,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_bimc_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "system_noc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_bimc,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
F(40000000, P_GPLL0, 10, 1, 2),
F(80000000, P_GPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 camss_ahb_clk_src = {
.cmd_rcgr = 0x5a000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_camss_ahb_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_ahb_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_apss_ahb_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(133330000, P_GPLL0, 6, 0, 0),
{ }
};
static struct clk_rcg2 apss_ahb_clk_src = {
.cmd_rcgr = 0x46000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_apss_ahb_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "apss_ahb_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 csi0_clk_src = {
.cmd_rcgr = 0x4e020,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_camss_csi0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi1_clk_src = {
.cmd_rcgr = 0x4f020,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_camss_csi0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0_AUX, 16, 0, 0),
F(80000000, P_GPLL0_AUX, 10, 0, 0),
F(100000000, P_GPLL0_AUX, 8, 0, 0),
F(160000000, P_GPLL0_AUX, 5, 0, 0),
F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
F(200000000, P_GPLL0_AUX, 4, 0, 0),
F(266670000, P_GPLL0_AUX, 3, 0, 0),
F(294912000, P_GPLL1, 3, 0, 0),
F(310000000, P_GPLL2, 3, 0, 0),
F(400000000, P_GPLL0_AUX, 2, 0, 0),
{ }
};
static struct clk_rcg2 gfx3d_clk_src = {
.cmd_rcgr = 0x59000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0a_gpll1_gpll2a_map,
.freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src",
.parent_data = gcc_xo_gpll0a_gpll1_gpll2a,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0a_gpll1_gpll2a),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
F(50000000, P_GPLL0, 16, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(177780000, P_GPLL0, 4.5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
F(465000000, P_GPLL2, 2, 0, 0),
{ }
};
static struct clk_rcg2 vfe0_clk_src = {
.cmd_rcgr = 0x58000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll2_map,
.freq_tbl = ftbl_gcc_camss_vfe0_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe0_clk_src",
.parent_data = gcc_xo_gpll0_gpll2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x0200c,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
F(100000, P_XO, 16, 2, 24),
F(250000, P_XO, 16, 5, 24),
F(500000, P_XO, 8, 5, 24),
F(960000, P_XO, 10, 1, 2),
F(1000000, P_XO, 4, 5, 24),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(16000000, P_GPLL0, 10, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0, 16, 1, 2),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x02024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x03000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x03014,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x04000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x04024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x05000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x05024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
.cmd_rcgr = 0x06000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
.cmd_rcgr = 0x06024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
.cmd_rcgr = 0x07000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
.cmd_rcgr = 0x07024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
F(3686400, P_GPLL0, 1, 72, 15625),
F(7372800, P_GPLL0, 1, 144, 15625),
F(14745600, P_GPLL0, 1, 288, 15625),
F(16000000, P_GPLL0, 10, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 1, 3, 100),
F(25000000, P_GPLL0, 16, 1, 2),
F(32000000, P_GPLL0, 1, 1, 25),
F(40000000, P_GPLL0, 1, 1, 20),
F(46400000, P_GPLL0, 1, 29, 500),
F(48000000, P_GPLL0, 1, 3, 50),
F(51200000, P_GPLL0, 1, 8, 125),
F(56000000, P_GPLL0, 1, 7, 100),
F(58982400, P_GPLL0, 1, 1152, 15625),
F(60000000, P_GPLL0, 1, 3, 40),
{ }
};
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x02044,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x03034,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 cci_clk_src = {
.cmd_rcgr = 0x51000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0a_map,
.freq_tbl = ftbl_gcc_camss_cci_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "cci_clk_src",
.parent_data = gcc_xo_gpll0a,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0a),
.ops = &clk_rcg2_ops,
},
};
/*
* This is a frequency table for "General Purpose" clocks.
* These clocks can be muxed to the SoC pins and may be used by
* external devices. They're often used as PWM source.
*
* See comment at ftbl_gcc_gp1_3_clk.
*/
static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
F(10000, P_XO, 16, 1, 120),
F(100000, P_XO, 16, 1, 12),
F(500000, P_GPLL0, 16, 1, 100),
F(1000000, P_GPLL0, 16, 1, 50),
F(2500000, P_GPLL0, 16, 1, 20),
F(5000000, P_GPLL0, 16, 1, 10),
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 camss_gp0_clk_src = {
.cmd_rcgr = 0x54000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
.freq_tbl = ftbl_gcc_camss_gp0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp0_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 camss_gp1_clk_src = {
.cmd_rcgr = 0x55000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
.freq_tbl = ftbl_gcc_camss_gp0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp1_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
F(133330000, P_GPLL0, 6, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 jpeg0_clk_src = {
.cmd_rcgr = 0x57000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_camss_jpeg0_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg0_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
F(9600000, P_XO, 2, 0, 0),
F(23880000, P_GPLL0, 1, 2, 67),
F(66670000, P_GPLL0, 12, 0, 0),
{ }
};
static struct clk_rcg2 mclk0_clk_src = {
.cmd_rcgr = 0x52000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
.freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk0_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk1_clk_src = {
.cmd_rcgr = 0x53000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
.freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk1_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 csi0phytimer_clk_src = {
.cmd_rcgr = 0x4e000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1a_map,
.freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0phytimer_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi1phytimer_clk_src = {
.cmd_rcgr = 0x4f000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1a_map,
.freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1phytimer_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
F(160000000, P_GPLL0, 5, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
F(465000000, P_GPLL2, 2, 0, 0),
{ }
};
static struct clk_rcg2 cpp_clk_src = {
.cmd_rcgr = 0x58018,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll2_map,
.freq_tbl = ftbl_gcc_camss_cpp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "cpp_clk_src",
.parent_data = gcc_xo_gpll0_gpll2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
F(50000000, P_GPLL0, 16, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
{ }
};
static struct clk_rcg2 crypto_clk_src = {
.cmd_rcgr = 0x16004,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_crypto_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "crypto_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
/*
* This is a frequency table for "General Purpose" clocks.
* These clocks can be muxed to the SoC pins and may be used by
* external devices. They're often used as PWM source.
*
* Please note that MND divider must be enabled for duty-cycle
* control to be possible. (M != N) Also since D register is configured
* with a value multiplied by 2, and duty cycle is calculated as
* (2 * D) % 2^W
* DutyCycle = ----------------
* 2 * (N % 2^W)
* (where W = .mnd_width)
* N must be half or less than maximum value for the register.
* Otherwise duty-cycle control would be limited.
* (e.g. for 8-bit NMD N should be less than 128)
*/
static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
F(10000, P_XO, 16, 1, 120),
F(100000, P_XO, 16, 1, 12),
F(500000, P_GPLL0, 16, 1, 100),
F(1000000, P_GPLL0, 16, 1, 50),
F(2500000, P_GPLL0, 16, 1, 20),
F(5000000, P_GPLL0, 16, 1, 10),
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x08004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
.freq_tbl = ftbl_gcc_gp1_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp2_clk_src = {
.cmd_rcgr = 0x09004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
.freq_tbl = ftbl_gcc_gp1_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp3_clk_src = {
.cmd_rcgr = 0x0a004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
.freq_tbl = ftbl_gcc_gp1_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 byte0_clk_src = {
.cmd_rcgr = 0x4d044,
.hid_width = 5,
.parent_map = gcc_xo_gpll0a_dsibyte_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte0_clk_src",
.parent_data = gcc_xo_gpll0a_dsibyte,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_gcc_mdss_esc0_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 esc0_clk_src = {
.cmd_rcgr = 0x4d05c,
.hid_width = 5,
.parent_map = gcc_xo_dsibyte_map,
.freq_tbl = ftbl_gcc_mdss_esc0_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc0_clk_src",
.parent_data = gcc_xo_dsibyte,
.num_parents = ARRAY_SIZE(gcc_xo_dsibyte),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
F(50000000, P_GPLL0, 16, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(177780000, P_GPLL0, 4.5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 mdp_clk_src = {
.cmd_rcgr = 0x4d014,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_dsiphy_map,
.freq_tbl = ftbl_gcc_mdss_mdp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mdp_clk_src",
.parent_data = gcc_xo_gpll0_dsiphy,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_dsiphy),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 pclk0_clk_src = {
.cmd_rcgr = 0x4d000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0a_dsiphy_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk0_clk_src",
.parent_data = gcc_xo_gpll0a_dsiphy,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 vsync_clk_src = {
.cmd_rcgr = 0x4d02c,
.hid_width = 5,
.parent_map = gcc_xo_gpll0a_map,
.freq_tbl = ftbl_gcc_mdss_vsync_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vsync_clk_src",
.parent_data = gcc_xo_gpll0a,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0a),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
F(64000000, P_GPLL0, 12.5, 0, 0),
{ }
};
static struct clk_rcg2 pdm2_clk_src = {
.cmd_rcgr = 0x44010,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_pdm2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0, 10, 1, 4),
F(25000000, P_GPLL0, 16, 1, 2),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(177770000, P_GPLL0, 4.5, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x42004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_sdcc1_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0, 10, 1, 4),
F(25000000, P_GPLL0, 16, 1, 2),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 sdcc2_apps_clk_src = {
.cmd_rcgr = 0x43004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_sdcc2_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
F(155000000, P_GPLL2, 6, 0, 0),
F(310000000, P_GPLL2, 3, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 apss_tcu_clk_src = {
.cmd_rcgr = 0x1207c,
.hid_width = 5,
.parent_map = gcc_xo_gpll0a_gpll1_gpll2_map,
.freq_tbl = ftbl_gcc_apss_tcu_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "apss_tcu_clk_src",
.parent_data = gcc_xo_gpll0a_gpll1_gpll2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0a_gpll1_gpll2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266500000, P_BIMC, 4, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
F(533000000, P_BIMC, 2, 0, 0),
{ }
};
static struct clk_rcg2 bimc_gpu_clk_src = {
.cmd_rcgr = 0x31028,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_bimc_map,
.freq_tbl = ftbl_gcc_bimc_gpu_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "bimc_gpu_clk_src",
.parent_data = gcc_xo_gpll0_bimc,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
.flags = CLK_GET_RATE_NOCACHE,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
F(80000000, P_GPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 usb_hs_system_clk_src = {
.cmd_rcgr = 0x41010,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_usb_hs_system_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hs_system_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = {
F(3200000, P_XO, 6, 0, 0),
F(6400000, P_XO, 3, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(19200000, P_XO, 1, 0, 0),
F(40000000, P_GPLL0, 10, 1, 2),
F(66670000, P_GPLL0, 12, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
.cmd_rcgr = 0x1c010,
.hid_width = 5,
.mnd_width = 8,
.parent_map = gcc_xo_gpll0_gpll1_sleep_map,
.freq_tbl = ftbl_gcc_ultaudio_ahb_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_ahbfabric_clk_src",
.parent_data = gcc_xo_gpll0_gpll1_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
.halt_reg = 0x1c028,
.clkr = {
.enable_reg = 0x1c028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
.parent_hws = (const struct clk_hw*[]){
&ultaudio_ahbfabric_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
.halt_reg = 0x1c024,
.clkr = {
.enable_reg = 0x1c024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
.parent_hws = (const struct clk_hw*[]){
&ultaudio_ahbfabric_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = {
F(128000, P_XO, 10, 1, 15),
F(256000, P_XO, 5, 1, 15),
F(384000, P_XO, 5, 1, 10),
F(512000, P_XO, 5, 2, 15),
F(576000, P_XO, 5, 3, 20),
F(705600, P_GPLL1, 16, 1, 80),
F(768000, P_XO, 5, 1, 5),
F(800000, P_XO, 5, 5, 24),
F(1024000, P_XO, 5, 4, 15),
F(1152000, P_XO, 1, 3, 50),
F(1411200, P_GPLL1, 16, 1, 40),
F(1536000, P_XO, 1, 2, 25),
F(1600000, P_XO, 12, 0, 0),
F(1728000, P_XO, 5, 9, 20),
F(2048000, P_XO, 5, 8, 15),
F(2304000, P_XO, 5, 3, 5),
F(2400000, P_XO, 8, 0, 0),
F(2822400, P_GPLL1, 16, 1, 20),
F(3072000, P_XO, 5, 4, 5),
F(4096000, P_GPLL1, 9, 2, 49),
F(4800000, P_XO, 4, 0, 0),
F(5644800, P_GPLL1, 16, 1, 10),
F(6144000, P_GPLL1, 7, 1, 21),
F(8192000, P_GPLL1, 9, 4, 49),
F(9600000, P_XO, 2, 0, 0),
F(11289600, P_GPLL1, 16, 1, 5),
F(12288000, P_GPLL1, 7, 2, 21),
{ }
};
static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
.cmd_rcgr = 0x1c054,
.hid_width = 5,
.mnd_width = 8,
.parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map,
.freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_lpaif_pri_i2s_clk_src",
.parent_data = gcc_xo_gpll1_epi2s_emclk_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll1_epi2s_emclk_sleep),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = {
.halt_reg = 0x1c068,
.clkr = {
.enable_reg = 0x1c068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_lpaif_pri_i2s_clk",
.parent_hws = (const struct clk_hw*[]){
&ultaudio_lpaif_pri_i2s_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
.cmd_rcgr = 0x1c06c,
.hid_width = 5,
.mnd_width = 8,
.parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map,
.freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_lpaif_sec_i2s_clk_src",
.parent_data = gcc_xo_gpll1_esi2s_emclk_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = {
.halt_reg = 0x1c080,
.clkr = {
.enable_reg = 0x1c080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_lpaif_sec_i2s_clk",
.parent_hws = (const struct clk_hw*[]){
&ultaudio_lpaif_sec_i2s_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
.cmd_rcgr = 0x1c084,
.hid_width = 5,
.mnd_width = 8,
.parent_map = gcc_xo_gpll1_emclk_sleep_map,
.freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_lpaif_aux_i2s_clk_src",
.parent_data = gcc_xo_gpll1_esi2s_emclk_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = {
.halt_reg = 0x1c098,
.clkr = {
.enable_reg = 0x1c098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_lpaif_aux_i2s_clk",
.parent_hws = (const struct clk_hw*[]){
&ultaudio_lpaif_aux_i2s_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 ultaudio_xo_clk_src = {
.cmd_rcgr = 0x1c034,
.hid_width = 5,
.parent_map = gcc_xo_sleep_map,
.freq_tbl = ftbl_gcc_ultaudio_xo_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_xo_clk_src",
.parent_data = gcc_xo_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_sleep),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_ultaudio_avsync_xo_clk = {
.halt_reg = 0x1c04c,
.clkr = {
.enable_reg = 0x1c04c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_avsync_xo_clk",
.parent_hws = (const struct clk_hw*[]){
&ultaudio_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ultaudio_stc_xo_clk = {
.halt_reg = 0x1c050,
.clkr = {
.enable_reg = 0x1c050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_stc_xo_clk",
.parent_hws = (const struct clk_hw*[]){
&ultaudio_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_codec_clk[] = {
F(9600000, P_XO, 2, 0, 0),
F(12288000, P_XO, 1, 16, 25),
F(19200000, P_XO, 1, 0, 0),
F(11289600, P_EXT_MCLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 codec_digcodec_clk_src = {
.cmd_rcgr = 0x1c09c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll1_emclk_sleep_map,
.freq_tbl = ftbl_codec_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "codec_digcodec_clk_src",
.parent_data = gcc_xo_gpll1_emclk_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll1_emclk_sleep),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_codec_digcodec_clk = {
.halt_reg = 0x1c0b0,
.clkr = {
.enable_reg = 0x1c0b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_codec_digcodec_clk",
.parent_hws = (const struct clk_hw*[]){
&codec_digcodec_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = {
.halt_reg = 0x1c000,
.clkr = {
.enable_reg = 0x1c000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_pcnoc_mport_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
.halt_reg = 0x1c004,
.clkr = {
.enable_reg = 0x1c004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_pcnoc_sway_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(228570000, P_GPLL0, 3.5, 0, 0),
{ }
};
static struct clk_rcg2 vcodec0_clk_src = {
.cmd_rcgr = 0x4C000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vcodec0_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x01008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_sleep_clk = {
.halt_reg = 0x01004,
.clkr = {
.enable_reg = 0x01004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_sleep_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep_clk", .name = "sleep_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x02008,
.clkr = {
.enable_reg = 0x02008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x02004,
.clkr = {
.enable_reg = 0x02004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x03010,
.clkr = {
.enable_reg = 0x03010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x0300c,
.clkr = {
.enable_reg = 0x0300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x04020,
.clkr = {
.enable_reg = 0x04020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x0401c,
.clkr = {
.enable_reg = 0x0401c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.halt_reg = 0x05020,
.clkr = {
.enable_reg = 0x05020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.halt_reg = 0x0501c,
.clkr = {
.enable_reg = 0x0501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
.halt_reg = 0x06020,
.clkr = {
.enable_reg = 0x06020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup5_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
.halt_reg = 0x0601c,
.clkr = {
.enable_reg = 0x0601c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup5_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
.halt_reg = 0x07020,
.clkr = {
.enable_reg = 0x07020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup6_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
.halt_reg = 0x0701c,
.clkr = {
.enable_reg = 0x0701c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup6_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x0203c,
.clkr = {
.enable_reg = 0x0203c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x0302c,
.clkr = {
.enable_reg = 0x0302c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x1300c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cci_ahb_clk = {
.halt_reg = 0x5101c,
.clkr = {
.enable_reg = 0x5101c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cci_clk = {
.halt_reg = 0x51018,
.clkr = {
.enable_reg = 0x51018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_clk",
.parent_hws = (const struct clk_hw*[]){
&cci_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0_ahb_clk = {
.halt_reg = 0x4e040,
.clkr = {
.enable_reg = 0x4e040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0_clk = {
.halt_reg = 0x4e03c,
.clkr = {
.enable_reg = 0x4e03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0phy_clk = {
.halt_reg = 0x4e048,
.clkr = {
.enable_reg = 0x4e048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0pix_clk = {
.halt_reg = 0x4e058,
.clkr = {
.enable_reg = 0x4e058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0rdi_clk = {
.halt_reg = 0x4e050,
.clkr = {
.enable_reg = 0x4e050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1_ahb_clk = {
.halt_reg = 0x4f040,
.clkr = {
.enable_reg = 0x4f040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1_clk = {
.halt_reg = 0x4f03c,
.clkr = {
.enable_reg = 0x4f03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1phy_clk = {
.halt_reg = 0x4f048,
.clkr = {
.enable_reg = 0x4f048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1pix_clk = {
.halt_reg = 0x4f058,
.clkr = {
.enable_reg = 0x4f058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1rdi_clk = {
.halt_reg = 0x4f050,
.clkr = {
.enable_reg = 0x4f050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi_vfe0_clk = {
.halt_reg = 0x58050,
.clkr = {
.enable_reg = 0x58050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi_vfe0_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_gp0_clk = {
.halt_reg = 0x54018,
.clkr = {
.enable_reg = 0x54018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_gp0_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_gp0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_gp1_clk = {
.halt_reg = 0x55018,
.clkr = {
.enable_reg = 0x55018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_ispif_ahb_clk = {
.halt_reg = 0x50004,
.clkr = {
.enable_reg = 0x50004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ispif_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_jpeg0_clk = {
.halt_reg = 0x57020,
.clkr = {
.enable_reg = 0x57020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_jpeg0_clk",
.parent_hws = (const struct clk_hw*[]){
&jpeg0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_jpeg_ahb_clk = {
.halt_reg = 0x57024,
.clkr = {
.enable_reg = 0x57024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_jpeg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_jpeg_axi_clk = {
.halt_reg = 0x57028,
.clkr = {
.enable_reg = 0x57028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_jpeg_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk0_clk = {
.halt_reg = 0x52018,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk1_clk = {
.halt_reg = 0x53018,
.clkr = {
.enable_reg = 0x53018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_micro_ahb_clk = {
.halt_reg = 0x5600c,
.clkr = {
.enable_reg = 0x5600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_micro_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0phytimer_clk = {
.halt_reg = 0x4e01c,
.clkr = {
.enable_reg = 0x4e01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1phytimer_clk = {
.halt_reg = 0x4f01c,
.clkr = {
.enable_reg = 0x4f01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_ahb_clk = {
.halt_reg = 0x5a014,
.clkr = {
.enable_reg = 0x5a014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_top_ahb_clk = {
.halt_reg = 0x56004,
.clkr = {
.enable_reg = 0x56004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_top_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cpp_ahb_clk = {
.halt_reg = 0x58040,
.clkr = {
.enable_reg = 0x58040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cpp_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cpp_clk = {
.halt_reg = 0x5803c,
.clkr = {
.enable_reg = 0x5803c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cpp_clk",
.parent_hws = (const struct clk_hw*[]){
&cpp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_vfe0_clk = {
.halt_reg = 0x58038,
.clkr = {
.enable_reg = 0x58038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe0_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_vfe_ahb_clk = {
.halt_reg = 0x58044,
.clkr = {
.enable_reg = 0x58044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_vfe_axi_clk = {
.halt_reg = 0x58048,
.clkr = {
.enable_reg = 0x58048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_ahb_clk = {
.halt_reg = 0x16024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_axi_clk = {
.halt_reg = 0x16020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_clk = {
.halt_reg = 0x1601c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_clk",
.parent_hws = (const struct clk_hw*[]){
&crypto_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_oxili_gmem_clk = {
.halt_reg = 0x59024,
.clkr = {
.enable_reg = 0x59024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_oxili_gmem_clk",
.parent_hws = (const struct clk_hw*[]){
&gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x08000,
.clkr = {
.enable_reg = 0x08000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x09000,
.clkr = {
.enable_reg = 0x09000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]){
&gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x0a000,
.clkr = {
.enable_reg = 0x0a000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]){
&gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_ahb_clk = {
.halt_reg = 0x4d07c,
.clkr = {
.enable_reg = 0x4d07c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_axi_clk = {
.halt_reg = 0x4d080,
.clkr = {
.enable_reg = 0x4d080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_byte0_clk = {
.halt_reg = 0x4d094,
.clkr = {
.enable_reg = 0x4d094,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]){
&byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_esc0_clk = {
.halt_reg = 0x4d098,
.clkr = {
.enable_reg = 0x4d098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]){
&esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_mdp_clk = {
.halt_reg = 0x4D088,
.clkr = {
.enable_reg = 0x4D088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_pclk0_clk = {
.halt_reg = 0x4d084,
.clkr = {
.enable_reg = 0x4d084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_vsync_clk = {
.halt_reg = 0x4d090,
.clkr = {
.enable_reg = 0x4d090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_cfg_ahb_clk = {
.halt_reg = 0x49000,
.clkr = {
.enable_reg = 0x49000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_oxili_ahb_clk = {
.halt_reg = 0x59028,
.clkr = {
.enable_reg = 0x59028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_oxili_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_oxili_gfx3d_clk = {
.halt_reg = 0x59020,
.clkr = {
.enable_reg = 0x59020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_oxili_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]){
&gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x4400c,
.clkr = {
.enable_reg = 0x4400c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]){
&pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x44004,
.clkr = {
.enable_reg = 0x44004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x13004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x4201c,
.clkr = {
.enable_reg = 0x4201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x42018,
.clkr = {
.enable_reg = 0x42018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x4301c,
.clkr = {
.enable_reg = 0x4301c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x43018,
.clkr = {
.enable_reg = 0x43018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_rcg2 bimc_ddr_clk_src = {
.cmd_rcgr = 0x32004,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_bimc_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "bimc_ddr_clk_src",
.parent_data = gcc_xo_gpll0_bimc,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
.ops = &clk_rcg2_ops,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.halt_reg = 0x49004,
.clkr = {
.enable_reg = 0x49004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_q6_bimc_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&bimc_ddr_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_apss_tcu_clk = {
.halt_reg = 0x12018,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_tcu_clk",
.parent_hws = (const struct clk_hw*[]){
&bimc_ddr_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gfx_tcu_clk = {
.halt_reg = 0x12020,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_gfx_tcu_clk",
.parent_hws = (const struct clk_hw*[]){
&bimc_ddr_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gtcu_ahb_clk = {
.halt_reg = 0x12044,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_gtcu_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_bimc_gfx_clk = {
.halt_reg = 0x31024,
.clkr = {
.enable_reg = 0x31024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_gfx_clk",
.parent_hws = (const struct clk_hw*[]){
&bimc_gpu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_bimc_gpu_clk = {
.halt_reg = 0x31040,
.clkr = {
.enable_reg = 0x31040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_gpu_clk",
.parent_hws = (const struct clk_hw*[]){
&bimc_gpu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_jpeg_tbu_clk = {
.halt_reg = 0x12034,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_jpeg_tbu_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdp_tbu_clk = {
.halt_reg = 0x1201c,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdp_tbu_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_smmu_cfg_clk = {
.halt_reg = 0x12038,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_smmu_cfg_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus_tbu_clk = {
.halt_reg = 0x12014,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus_tbu_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vfe_tbu_clk = {
.halt_reg = 0x1203c,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_vfe_tbu_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb2a_phy_sleep_clk = {
.halt_reg = 0x4102c,
.clkr = {
.enable_reg = 0x4102c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb2a_phy_sleep_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep_clk", .name = "sleep_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_ahb_clk = {
.halt_reg = 0x41008,
.clkr = {
.enable_reg = 0x41008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_system_clk = {
.halt_reg = 0x41004,
.clkr = {
.enable_reg = 0x41004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_system_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_hs_system_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus0_ahb_clk = {
.halt_reg = 0x4c020,
.clkr = {
.enable_reg = 0x4c020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus0_axi_clk = {
.halt_reg = 0x4c024,
.clkr = {
.enable_reg = 0x4c024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus0_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus0_vcodec0_clk = {
.halt_reg = 0x4c01c,
.clkr = {
.enable_reg = 0x4c01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus0_vcodec0_clk",
.parent_hws = (const struct clk_hw*[]){
&vcodec0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc venus_gdsc = {
.gdscr = 0x4c018,
.pd = {
.name = "venus",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x4d078,
.pd = {
.name = "mdss",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc jpeg_gdsc = {
.gdscr = 0x5701c,
.pd = {
.name = "jpeg",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc vfe_gdsc = {
.gdscr = 0x58034,
.pd = {
.name = "vfe",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc oxili_gdsc = {
.gdscr = 0x5901c,
.pd = {
.name = "oxili",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *gcc_msm8916_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL0_VOTE] = &gpll0_vote,
[BIMC_PLL] = &bimc_pll.clkr,
[BIMC_PLL_VOTE] = &bimc_pll_vote,
[GPLL1] = &gpll1.clkr,
[GPLL1_VOTE] = &gpll1_vote,
[GPLL2] = &gpll2.clkr,
[GPLL2_VOTE] = &gpll2_vote,
[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
[CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[CCI_CLK_SRC] = &cci_clk_src.clkr,
[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
[CPP_CLK_SRC] = &cpp_clk_src.clkr,
[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
[MDP_CLK_SRC] = &mdp_clk_src.clkr,
[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
[APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
[VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
[GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
[GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
[GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
[GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
[GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
[GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
[GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
[GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
[GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
[GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
[GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
[GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
[GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
[GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
[GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
[GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
[GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
[GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
[GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
[GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
[GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
[GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
[GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
[GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
[GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
[GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
[GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
[GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
[GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
[GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
[GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
[GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
[GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
[GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
[GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
[GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
[GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
[GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
[GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
[GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
[GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
[GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
[BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
[GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
[GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
[BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,
[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
[GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
[ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr,
[ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr,
[ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr,
[ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr,
[ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr,
[CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr,
[GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr,
[GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr,
[GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr,
[GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr,
[GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr,
[GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr,
[GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr,
[GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr,
[GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr,
[GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr,
[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
};
static struct gdsc *gcc_msm8916_gdscs[] = {
[VENUS_GDSC] = &venus_gdsc,
[MDSS_GDSC] = &mdss_gdsc,
[JPEG_GDSC] = &jpeg_gdsc,
[VFE_GDSC] = &vfe_gdsc,
[OXILI_GDSC] = &oxili_gdsc,
};
static const struct qcom_reset_map gcc_msm8916_resets[] = {
[GCC_BLSP1_BCR] = { 0x01000 },
[GCC_BLSP1_QUP1_BCR] = { 0x02000 },
[GCC_BLSP1_UART1_BCR] = { 0x02038 },
[GCC_BLSP1_QUP2_BCR] = { 0x03008 },
[GCC_BLSP1_UART2_BCR] = { 0x03028 },
[GCC_BLSP1_QUP3_BCR] = { 0x04018 },
[GCC_BLSP1_QUP4_BCR] = { 0x05018 },
[GCC_BLSP1_QUP5_BCR] = { 0x06018 },
[GCC_BLSP1_QUP6_BCR] = { 0x07018 },
[GCC_IMEM_BCR] = { 0x0e000 },
[GCC_SMMU_BCR] = { 0x12000 },
[GCC_APSS_TCU_BCR] = { 0x12050 },
[GCC_SMMU_XPU_BCR] = { 0x12054 },
[GCC_PCNOC_TBU_BCR] = { 0x12058 },
[GCC_PRNG_BCR] = { 0x13000 },
[GCC_BOOT_ROM_BCR] = { 0x13008 },
[GCC_CRYPTO_BCR] = { 0x16000 },
[GCC_SEC_CTRL_BCR] = { 0x1a000 },
[GCC_AUDIO_CORE_BCR] = { 0x1c008 },
[GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
[GCC_DEHR_BCR] = { 0x1f000 },
[GCC_SYSTEM_NOC_BCR] = { 0x26000 },
[GCC_PCNOC_BCR] = { 0x27018 },
[GCC_TCSR_BCR] = { 0x28000 },
[GCC_QDSS_BCR] = { 0x29000 },
[GCC_DCD_BCR] = { 0x2a000 },
[GCC_MSG_RAM_BCR] = { 0x2b000 },
[GCC_MPM_BCR] = { 0x2c000 },
[GCC_SPMI_BCR] = { 0x2e000 },
[GCC_SPDM_BCR] = { 0x2f000 },
[GCC_MM_SPDM_BCR] = { 0x2f024 },
[GCC_BIMC_BCR] = { 0x31000 },
[GCC_RBCPR_BCR] = { 0x33000 },
[GCC_TLMM_BCR] = { 0x34000 },
[GCC_USB_HS_BCR] = { 0x41000 },
[GCC_USB2A_PHY_BCR] = { 0x41028 },
[GCC_SDCC1_BCR] = { 0x42000 },
[GCC_SDCC2_BCR] = { 0x43000 },
[GCC_PDM_BCR] = { 0x44000 },
[GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
[GCC_MMSS_BCR] = { 0x4b000 },
[GCC_VENUS0_BCR] = { 0x4c014 },
[GCC_MDSS_BCR] = { 0x4d074 },
[GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
[GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
[GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
[GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
[GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
[GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
[GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
[GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
[GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
[GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
[GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
[GCC_CAMSS_CCI_BCR] = { 0x51014 },
[GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
[GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
[GCC_CAMSS_GP0_BCR] = { 0x54014 },
[GCC_CAMSS_GP1_BCR] = { 0x55014 },
[GCC_CAMSS_TOP_BCR] = { 0x56000 },
[GCC_CAMSS_MICRO_BCR] = { 0x56008 },
[GCC_CAMSS_JPEG_BCR] = { 0x57018 },
[GCC_CAMSS_VFE_BCR] = { 0x58030 },
[GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
[GCC_OXILI_BCR] = { 0x59018 },
[GCC_GMEM_BCR] = { 0x5902c },
[GCC_CAMSS_AHB_BCR] = { 0x5a018 },
[GCC_MDP_TBU_BCR] = { 0x62000 },
[GCC_GFX_TBU_BCR] = { 0x63000 },
[GCC_GFX_TCU_BCR] = { 0x64000 },
[GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
[GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
[GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
[GCC_GTCU_AHB_BCR] = { 0x68000 },
[GCC_SMMU_CFG_BCR] = { 0x69000 },
[GCC_VFE_TBU_BCR] = { 0x6a000 },
[GCC_VENUS_TBU_BCR] = { 0x6b000 },
[GCC_JPEG_TBU_BCR] = { 0x6c000 },
[GCC_PRONTO_TBU_BCR] = { 0x6d000 },
[GCC_SMMU_CATS_BCR] = { 0x7c000 },
};
static const struct regmap_config gcc_msm8916_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x80000,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_msm8916_desc = {
.config = &gcc_msm8916_regmap_config,
.clks = gcc_msm8916_clocks,
.num_clks = ARRAY_SIZE(gcc_msm8916_clocks),
.resets = gcc_msm8916_resets,
.num_resets = ARRAY_SIZE(gcc_msm8916_resets),
.gdscs = gcc_msm8916_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_msm8916_gdscs),
};
static const struct of_device_id gcc_msm8916_match_table[] = {
{ .compatible = "qcom,gcc-msm8916" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_msm8916_match_table);
static int gcc_msm8916_probe(struct platform_device *pdev)
{
int ret;
struct device *dev = &pdev->dev;
ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
if (ret)
return ret;
ret = qcom_cc_register_sleep_clk(dev);
if (ret)
return ret;
return qcom_cc_probe(pdev, &gcc_msm8916_desc);
}
static struct platform_driver gcc_msm8916_driver = {
.probe = gcc_msm8916_probe,
.driver = {
.name = "gcc-msm8916",
.of_match_table = gcc_msm8916_match_table,
},
};
static int __init gcc_msm8916_init(void)
{
return platform_driver_register(&gcc_msm8916_driver);
}
core_initcall(gcc_msm8916_init);
static void __exit gcc_msm8916_exit(void)
{
platform_driver_unregister(&gcc_msm8916_driver);
}
module_exit(gcc_msm8916_exit);
MODULE_DESCRIPTION("Qualcomm GCC MSM8916 Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:gcc-msm8916");
| linux-master | drivers/clk/qcom/gcc-msm8916.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/regmap.h>
#include <linux/export.h>
#include "clk-regmap-divider.h"
static inline struct clk_regmap_div *to_clk_regmap_div(struct clk_hw *hw)
{
return container_of(to_clk_regmap(hw), struct clk_regmap_div, clkr);
}
static long div_round_ro_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_regmap_div *divider = to_clk_regmap_div(hw);
struct clk_regmap *clkr = ÷r->clkr;
u32 val;
regmap_read(clkr->regmap, divider->reg, &val);
val >>= divider->shift;
val &= BIT(divider->width) - 1;
return divider_ro_round_rate(hw, rate, prate, NULL, divider->width,
CLK_DIVIDER_ROUND_CLOSEST, val);
}
static long div_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_regmap_div *divider = to_clk_regmap_div(hw);
return divider_round_rate(hw, rate, prate, NULL, divider->width,
CLK_DIVIDER_ROUND_CLOSEST);
}
static int div_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_regmap_div *divider = to_clk_regmap_div(hw);
struct clk_regmap *clkr = ÷r->clkr;
u32 div;
div = divider_get_val(rate, parent_rate, NULL, divider->width,
CLK_DIVIDER_ROUND_CLOSEST);
return regmap_update_bits(clkr->regmap, divider->reg,
(BIT(divider->width) - 1) << divider->shift,
div << divider->shift);
}
static unsigned long div_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_regmap_div *divider = to_clk_regmap_div(hw);
struct clk_regmap *clkr = ÷r->clkr;
u32 div;
regmap_read(clkr->regmap, divider->reg, &div);
div >>= divider->shift;
div &= BIT(divider->width) - 1;
return divider_recalc_rate(hw, parent_rate, div, NULL,
CLK_DIVIDER_ROUND_CLOSEST, divider->width);
}
const struct clk_ops clk_regmap_div_ops = {
.round_rate = div_round_rate,
.set_rate = div_set_rate,
.recalc_rate = div_recalc_rate,
};
EXPORT_SYMBOL_GPL(clk_regmap_div_ops);
const struct clk_ops clk_regmap_div_ro_ops = {
.round_rate = div_round_ro_rate,
.recalc_rate = div_recalc_rate,
};
EXPORT_SYMBOL_GPL(clk_regmap_div_ro_ops);
| linux-master | drivers/clk/qcom/clk-regmap-divider.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2020 Linaro Limited
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-msm8939.h>
#include <dt-bindings/reset/qcom,gcc-msm8939.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_XO,
P_GPLL0,
P_GPLL0_AUX,
P_BIMC,
P_GPLL1,
P_GPLL1_AUX,
P_GPLL2,
P_GPLL2_AUX,
P_GPLL3,
P_GPLL3_AUX,
P_GPLL4,
P_GPLL5,
P_GPLL5_AUX,
P_GPLL5_EARLY,
P_GPLL6,
P_GPLL6_AUX,
P_SLEEP_CLK,
P_DSI0_PHYPLL_BYTE,
P_DSI0_PHYPLL_DSI,
P_EXT_PRI_I2S,
P_EXT_SEC_I2S,
P_EXT_MCLK,
};
static struct clk_pll gpll0 = {
.l_reg = 0x21004,
.m_reg = 0x21008,
.n_reg = 0x2100c,
.config_reg = 0x21010,
.mode_reg = 0x21000,
.status_reg = 0x2101c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll0_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_vote",
.parent_hws = (const struct clk_hw*[]) {
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll gpll1 = {
.l_reg = 0x20004,
.m_reg = 0x20008,
.n_reg = 0x2000c,
.config_reg = 0x20010,
.mode_reg = 0x20000,
.status_reg = 0x2001c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll1",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll1_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gpll1_vote",
.parent_hws = (const struct clk_hw*[]) {
&gpll1.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll gpll2 = {
.l_reg = 0x4a004,
.m_reg = 0x4a008,
.n_reg = 0x4a00c,
.config_reg = 0x4a010,
.mode_reg = 0x4a000,
.status_reg = 0x4a01c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll2",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll2_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gpll2_vote",
.parent_hws = (const struct clk_hw*[]) {
&gpll2.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll bimc_pll = {
.l_reg = 0x23004,
.m_reg = 0x23008,
.n_reg = 0x2300c,
.config_reg = 0x23010,
.mode_reg = 0x23000,
.status_reg = 0x2301c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "bimc_pll",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap bimc_pll_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "bimc_pll_vote",
.parent_hws = (const struct clk_hw*[]) {
&bimc_pll.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll gpll3 = {
.l_reg = 0x22004,
.m_reg = 0x22008,
.n_reg = 0x2200c,
.config_reg = 0x22010,
.mode_reg = 0x22000,
.status_reg = 0x2201c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll3",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll3_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gpll3_vote",
.parent_hws = (const struct clk_hw*[]) {
&gpll3.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
/* GPLL3 at 1100 MHz, main output enabled. */
static const struct pll_config gpll3_config = {
.l = 57,
.m = 7,
.n = 24,
.vco_val = 0x0,
.vco_mask = BIT(20),
.pre_div_val = 0x0,
.pre_div_mask = BIT(12),
.post_div_val = 0x0,
.post_div_mask = BIT(9) | BIT(8),
.mn_ena_mask = BIT(24),
.main_output_mask = BIT(0),
.aux_output_mask = BIT(1),
};
static struct clk_pll gpll4 = {
.l_reg = 0x24004,
.m_reg = 0x24008,
.n_reg = 0x2400c,
.config_reg = 0x24010,
.mode_reg = 0x24000,
.status_reg = 0x2401c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll4_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gpll4_vote",
.parent_hws = (const struct clk_hw*[]) {
&gpll4.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
/* GPLL4 at 1200 MHz, main output enabled. */
static struct pll_config gpll4_config = {
.l = 62,
.m = 1,
.n = 2,
.vco_val = 0x0,
.vco_mask = BIT(20),
.pre_div_val = 0x0,
.pre_div_mask = BIT(12),
.post_div_val = 0x0,
.post_div_mask = BIT(9) | BIT(8),
.mn_ena_mask = BIT(24),
.main_output_mask = BIT(0),
};
static struct clk_pll gpll5 = {
.l_reg = 0x25004,
.m_reg = 0x25008,
.n_reg = 0x2500c,
.config_reg = 0x25010,
.mode_reg = 0x25000,
.status_reg = 0x2501c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll5",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll5_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gpll5_vote",
.parent_hws = (const struct clk_hw*[]) {
&gpll5.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll gpll6 = {
.l_reg = 0x37004,
.m_reg = 0x37008,
.n_reg = 0x3700c,
.config_reg = 0x37010,
.mode_reg = 0x37000,
.status_reg = 0x3701c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll6",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll6_vote = {
.enable_reg = 0x45000,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gpll6_vote",
.parent_hws = (const struct clk_hw*[]) {
&gpll6.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static const struct parent_map gcc_xo_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
};
static const struct clk_parent_data gcc_xo_gpll0_parent_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
};
static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_BIMC, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0_bimc_parent_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
{ .hw = &bimc_pll_vote.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll6a_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6_AUX, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll6a_parent_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll6_vote.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL2_AUX, 4 },
{ P_GPLL3, 2 },
{ P_GPLL6_AUX, 3 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll2_vote.hw },
{ .hw = &gpll3_vote.hw },
{ .hw = &gpll6_vote.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL2, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll2_parent_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll2_vote.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL2, 3 },
{ P_GPLL4, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_parent_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll2_vote.hw },
{ .hw = &gpll4_vote.hw },
};
static const struct parent_map gcc_xo_gpll0a_map[] = {
{ P_XO, 0 },
{ P_GPLL0_AUX, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0a_parent_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL1_AUX, 2 },
{ P_SLEEP_CLK, 6 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll1a_sleep_parent_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll1_vote.hw },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct parent_map gcc_xo_gpll0_gpll1a_gpll6_sleep_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL1_AUX, 2 },
{ P_GPLL6, 2 },
{ P_SLEEP_CLK, 6 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll1_vote.hw },
{ .hw = &gpll6_vote.hw },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL1_AUX, 2 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll1a_parent_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll1_vote.hw },
};
static const struct parent_map gcc_xo_dsibyte_map[] = {
{ P_XO, 0, },
{ P_DSI0_PHYPLL_BYTE, 2 },
};
static const struct clk_parent_data gcc_xo_dsibyte_parent_data[] = {
{ .fw_name = "xo" },
{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
};
static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
{ P_XO, 0 },
{ P_GPLL0_AUX, 2 },
{ P_DSI0_PHYPLL_BYTE, 1 },
};
static const struct clk_parent_data gcc_xo_gpll0a_dsibyte_parent_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
};
static const struct parent_map gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map[] = {
{ P_XO, 0 },
{ P_GPLL1, 1 },
{ P_DSI0_PHYPLL_DSI, 2 },
{ P_GPLL6, 3 },
{ P_GPLL3_AUX, 4 },
{ P_GPLL0_AUX, 5 },
};
static const struct clk_parent_data gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll1_vote.hw },
{ .fw_name = "dsi0pll", .name = "dsi0pll" },
{ .hw = &gpll6_vote.hw },
{ .hw = &gpll3_vote.hw },
{ .hw = &gpll0_vote.hw },
};
static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
{ P_XO, 0 },
{ P_GPLL0_AUX, 2 },
{ P_DSI0_PHYPLL_DSI, 1 },
};
static const struct clk_parent_data gcc_xo_gpll0a_dsiphy_parent_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
{ .fw_name = "dsi0pll", .name = "dsi0pll" },
};
static const struct parent_map gcc_xo_gpll0_gpll5a_gpll6_bimc_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL5_AUX, 3 },
{ P_GPLL6, 2 },
{ P_BIMC, 4 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll5_vote.hw },
{ .hw = &gpll6_vote.hw },
{ .hw = &bimc_pll_vote.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL1, 2 },
{ P_SLEEP_CLK, 6 }
};
static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep_parent_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll1_vote.hw },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
{ P_XO, 0 },
{ P_GPLL1, 1 },
{ P_EXT_PRI_I2S, 2 },
{ P_EXT_MCLK, 3 },
{ P_SLEEP_CLK, 6 }
};
static const struct clk_parent_data gcc_xo_gpll1_epi2s_emclk_sleep_parent_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_vote.hw },
{ .fw_name = "ext_pri_i2s", .name = "ext_pri_i2s" },
{ .fw_name = "ext_mclk", .name = "ext_mclk" },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
{ P_XO, 0 },
{ P_GPLL1, 1 },
{ P_EXT_SEC_I2S, 2 },
{ P_EXT_MCLK, 3 },
{ P_SLEEP_CLK, 6 }
};
static const struct clk_parent_data gcc_xo_gpll1_esi2s_emclk_sleep_parent_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll1_vote.hw },
{ .fw_name = "ext_sec_i2s", .name = "ext_sec_i2s" },
{ .fw_name = "ext_mclk", .name = "ext_mclk" },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct parent_map gcc_xo_sleep_map[] = {
{ P_XO, 0 },
{ P_SLEEP_CLK, 6 }
};
static const struct clk_parent_data gcc_xo_sleep_parent_data[] = {
{ .fw_name = "xo" },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
{ P_XO, 0 },
{ P_GPLL1, 1 },
{ P_EXT_MCLK, 2 },
{ P_SLEEP_CLK, 6 }
};
static const struct clk_parent_data gcc_xo_gpll1_emclk_sleep_parent_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll1_vote.hw },
{ .fw_name = "ext_mclk", .name = "ext_mclk" },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct clk_parent_data gcc_xo_gpll6_gpll0_parent_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll6_vote.hw },
{ .hw = &gpll0_vote.hw },
};
static const struct clk_parent_data gcc_xo_gpll6_gpll0a_parent_data[] = {
{ .fw_name = "xo" },
{ .hw = &gpll6_vote.hw },
{ .hw = &gpll0_vote.hw },
};
static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
.cmd_rcgr = 0x27000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcnoc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 system_noc_bfdcd_clk_src = {
.cmd_rcgr = 0x26004,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll6a_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "system_noc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_gpll6a_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6a_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 bimc_ddr_clk_src = {
.cmd_rcgr = 0x32024,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_bimc_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "bimc_ddr_clk_src",
.parent_data = gcc_xo_gpll0_bimc_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc_parent_data),
.ops = &clk_rcg2_ops,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_rcg2 system_mm_noc_bfdcd_clk_src = {
.cmd_rcgr = 0x2600c,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll6a_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "system_mm_noc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_gpll6a_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6a_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
F(40000000, P_GPLL0, 10, 1, 2),
F(80000000, P_GPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 camss_ahb_clk_src = {
.cmd_rcgr = 0x5a000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_camss_ahb_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_ahb_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_apss_ahb_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(133330000, P_GPLL0, 6, 0, 0),
{ }
};
static struct clk_rcg2 apss_ahb_clk_src = {
.cmd_rcgr = 0x46000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_apss_ahb_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "apss_ahb_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 csi0_clk_src = {
.cmd_rcgr = 0x4e020,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_camss_csi0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi1_clk_src = {
.cmd_rcgr = 0x4f020,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_camss_csi0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(220000000, P_GPLL3, 5, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(310000000, P_GPLL2_AUX, 3, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
F(465000000, P_GPLL2_AUX, 2, 0, 0),
F(550000000, P_GPLL3, 2, 0, 0),
{ }
};
static struct clk_rcg2 gfx3d_clk_src = {
.cmd_rcgr = 0x59000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map,
.freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src",
.parent_data = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
F(50000000, P_GPLL0, 16, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(177780000, P_GPLL0, 4.5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
F(465000000, P_GPLL2, 2, 0, 0),
F(480000000, P_GPLL4, 2.5, 0, 0),
F(600000000, P_GPLL4, 2, 0, 0),
{ }
};
static struct clk_rcg2 vfe0_clk_src = {
.cmd_rcgr = 0x58000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll2_gpll4_map,
.freq_tbl = ftbl_gcc_camss_vfe0_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe0_clk_src",
.parent_data = gcc_xo_gpll0_gpll2_gpll4_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x0200c,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(16000000, P_GPLL0, 10, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0, 16, 1, 2),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x02024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x03000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x03014,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x04000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x04024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x05000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x05024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
.cmd_rcgr = 0x06000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
.cmd_rcgr = 0x06024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
.cmd_rcgr = 0x07000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
.cmd_rcgr = 0x07024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
F(3686400, P_GPLL0, 1, 72, 15625),
F(7372800, P_GPLL0, 1, 144, 15625),
F(14745600, P_GPLL0, 1, 288, 15625),
F(16000000, P_GPLL0, 10, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 1, 3, 100),
F(25000000, P_GPLL0, 16, 1, 2),
F(32000000, P_GPLL0, 1, 1, 25),
F(40000000, P_GPLL0, 1, 1, 20),
F(46400000, P_GPLL0, 1, 29, 500),
F(48000000, P_GPLL0, 1, 3, 50),
F(51200000, P_GPLL0, 1, 8, 125),
F(56000000, P_GPLL0, 1, 7, 100),
F(58982400, P_GPLL0, 1, 1152, 15625),
F(60000000, P_GPLL0, 1, 3, 40),
{ }
};
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x02044,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x03034,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(37500000, P_GPLL0, 1, 3, 64),
{ }
};
static struct clk_rcg2 cci_clk_src = {
.cmd_rcgr = 0x51000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0a_map,
.freq_tbl = ftbl_gcc_camss_cci_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "cci_clk_src",
.parent_data = gcc_xo_gpll0a_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0a_parent_data),
.ops = &clk_rcg2_ops,
},
};
/*
* This is a frequency table for "General Purpose" clocks.
* These clocks can be muxed to the SoC pins and may be used by
* external devices. They're often used as PWM source.
*
* See comment at ftbl_gcc_gp1_3_clk.
*/
static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
F(10000, P_XO, 16, 1, 120),
F(100000, P_XO, 16, 1, 12),
F(500000, P_GPLL0, 16, 1, 100),
F(1000000, P_GPLL0, 16, 1, 50),
F(2500000, P_GPLL0, 16, 1, 20),
F(5000000, P_GPLL0, 16, 1, 10),
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 camss_gp0_clk_src = {
.cmd_rcgr = 0x54000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
.freq_tbl = ftbl_gcc_camss_gp0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp0_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 camss_gp1_clk_src = {
.cmd_rcgr = 0x55000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
.freq_tbl = ftbl_gcc_camss_gp0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp1_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
F(133330000, P_GPLL0, 6, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 jpeg0_clk_src = {
.cmd_rcgr = 0x57000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_camss_jpeg0_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg0_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
F(24000000, P_GPLL0, 1, 1, 45),
F(66670000, P_GPLL0, 12, 0, 0),
{ }
};
static struct clk_rcg2 mclk0_clk_src = {
.cmd_rcgr = 0x52000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map,
.freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk0_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk1_clk_src = {
.cmd_rcgr = 0x53000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map,
.freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk1_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 csi0phytimer_clk_src = {
.cmd_rcgr = 0x4e000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1a_map,
.freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0phytimer_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi1phytimer_clk_src = {
.cmd_rcgr = 0x4f000,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1a_map,
.freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1phytimer_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
F(160000000, P_GPLL0, 5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(228570000, P_GPLL0, 3.5, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
F(465000000, P_GPLL2, 2, 0, 0),
{ }
};
static struct clk_rcg2 cpp_clk_src = {
.cmd_rcgr = 0x58018,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll2_map,
.freq_tbl = ftbl_gcc_camss_cpp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "cpp_clk_src",
.parent_data = gcc_xo_gpll0_gpll2_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
F(50000000, P_GPLL0, 16, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
{ }
};
/* This is not in the documentation but is in the downstream driver */
static struct clk_rcg2 crypto_clk_src = {
.cmd_rcgr = 0x16004,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_crypto_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "crypto_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
/*
* This is a frequency table for "General Purpose" clocks.
* These clocks can be muxed to the SoC pins and may be used by
* external devices. They're often used as PWM source.
*
* Please note that MND divider must be enabled for duty-cycle
* control to be possible. (M != N) Also since D register is configured
* with a value multiplied by 2, and duty cycle is calculated as
* (2 * D) % 2^W
* DutyCycle = ----------------
* 2 * (N % 2^W)
* (where W = .mnd_width)
* N must be half or less than maximum value for the register.
* Otherwise duty-cycle control would be limited.
* (e.g. for 8-bit NMD N should be less than 128)
*/
static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
F(10000, P_XO, 16, 1, 120),
F(100000, P_XO, 16, 1, 12),
F(500000, P_GPLL0, 16, 1, 100),
F(1000000, P_GPLL0, 16, 1, 50),
F(2500000, P_GPLL0, 16, 1, 20),
F(5000000, P_GPLL0, 16, 1, 10),
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x08004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
.freq_tbl = ftbl_gcc_gp1_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp2_clk_src = {
.cmd_rcgr = 0x09004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
.freq_tbl = ftbl_gcc_gp1_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp3_clk_src = {
.cmd_rcgr = 0x0a004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
.freq_tbl = ftbl_gcc_gp1_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 byte0_clk_src = {
.cmd_rcgr = 0x4d044,
.hid_width = 5,
.parent_map = gcc_xo_gpll0a_dsibyte_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte0_clk_src",
.parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte_parent_data),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_rcg2 byte1_clk_src = {
.cmd_rcgr = 0x4d0b0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0a_dsibyte_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte1_clk_src",
.parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte_parent_data),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_gcc_mdss_esc_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 esc0_clk_src = {
.cmd_rcgr = 0x4d060,
.hid_width = 5,
.parent_map = gcc_xo_dsibyte_map,
.freq_tbl = ftbl_gcc_mdss_esc_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc0_clk_src",
.parent_data = gcc_xo_dsibyte_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_dsibyte_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 esc1_clk_src = {
.cmd_rcgr = 0x4d0a8,
.hid_width = 5,
.parent_map = gcc_xo_dsibyte_map,
.freq_tbl = ftbl_gcc_mdss_esc_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc1_clk_src",
.parent_data = gcc_xo_dsibyte_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_dsibyte_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
F(50000000, P_GPLL0_AUX, 16, 0, 0),
F(80000000, P_GPLL0_AUX, 10, 0, 0),
F(100000000, P_GPLL0_AUX, 8, 0, 0),
F(145500000, P_GPLL0_AUX, 5.5, 0, 0),
F(153600000, P_GPLL0, 4, 0, 0),
F(160000000, P_GPLL0_AUX, 5, 0, 0),
F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
F(200000000, P_GPLL0_AUX, 4, 0, 0),
F(266670000, P_GPLL0_AUX, 3, 0, 0),
F(307200000, P_GPLL1, 2, 0, 0),
F(366670000, P_GPLL3_AUX, 3, 0, 0),
{ }
};
static struct clk_rcg2 mdp_clk_src = {
.cmd_rcgr = 0x4d014,
.hid_width = 5,
.parent_map = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map,
.freq_tbl = ftbl_gcc_mdss_mdp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mdp_clk_src",
.parent_data = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 pclk0_clk_src = {
.cmd_rcgr = 0x4d000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0a_dsiphy_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk0_clk_src",
.parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy_parent_data),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_rcg2 pclk1_clk_src = {
.cmd_rcgr = 0x4d0b8,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0a_dsiphy_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk1_clk_src",
.parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy_parent_data),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 vsync_clk_src = {
.cmd_rcgr = 0x4d02c,
.hid_width = 5,
.parent_map = gcc_xo_gpll0a_map,
.freq_tbl = ftbl_gcc_mdss_vsync_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vsync_clk_src",
.parent_data = gcc_xo_gpll0a_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0a_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
F(64000000, P_GPLL0, 12.5, 0, 0),
{ }
};
/* This is not in the documentation but is in the downstream driver */
static struct clk_rcg2 pdm2_clk_src = {
.cmd_rcgr = 0x44010,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_pdm2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc_apps_clk[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0, 10, 1, 4),
F(25000000, P_GPLL0, 16, 1, 2),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(177770000, P_GPLL0, 4.5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x42004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_sdcc_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_floor_ops,
},
};
static struct clk_rcg2 sdcc2_apps_clk_src = {
.cmd_rcgr = 0x43004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_sdcc_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
F(154285000, P_GPLL6, 7, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 apss_tcu_clk_src = {
.cmd_rcgr = 0x1207c,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map,
.freq_tbl = ftbl_gcc_apss_tcu_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "apss_tcu_clk_src",
.parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266500000, P_BIMC, 4, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
F(533000000, P_BIMC, 2, 0, 0),
{ }
};
static struct clk_rcg2 bimc_gpu_clk_src = {
.cmd_rcgr = 0x31028,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map,
.freq_tbl = ftbl_gcc_bimc_gpu_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "bimc_gpu_clk_src",
.parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data),
.flags = CLK_GET_RATE_NOCACHE,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
F(57140000, P_GPLL0, 14, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 usb_hs_system_clk_src = {
.cmd_rcgr = 0x41010,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_usb_hs_system_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hs_system_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb_fs_system_clk[] = {
F(64000000, P_GPLL0, 12.5, 0, 0),
{ }
};
static struct clk_rcg2 usb_fs_system_clk_src = {
.cmd_rcgr = 0x3f010,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_usb_fs_system_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_fs_system_clk_src",
.parent_data = gcc_xo_gpll6_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb_fs_ic_clk[] = {
F(60000000, P_GPLL6, 1, 1, 18),
{ }
};
static struct clk_rcg2 usb_fs_ic_clk_src = {
.cmd_rcgr = 0x3f034,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_usb_fs_ic_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_fs_ic_clk_src",
.parent_data = gcc_xo_gpll6_gpll0a_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0a_parent_data),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = {
F(3200000, P_XO, 6, 0, 0),
F(6400000, P_XO, 3, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(19200000, P_XO, 1, 0, 0),
F(40000000, P_GPLL0, 10, 1, 2),
F(66670000, P_GPLL0, 12, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
.cmd_rcgr = 0x1c010,
.hid_width = 5,
.mnd_width = 8,
.parent_map = gcc_xo_gpll0_gpll1_sleep_map,
.freq_tbl = ftbl_gcc_ultaudio_ahb_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_ahbfabric_clk_src",
.parent_data = gcc_xo_gpll0_gpll1_sleep_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
.halt_reg = 0x1c028,
.clkr = {
.enable_reg = 0x1c028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
.parent_hws = (const struct clk_hw*[]){
&ultaudio_ahbfabric_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
.halt_reg = 0x1c024,
.clkr = {
.enable_reg = 0x1c024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
.parent_hws = (const struct clk_hw*[]){
&ultaudio_ahbfabric_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = {
F(128000, P_XO, 10, 1, 15),
F(256000, P_XO, 5, 1, 15),
F(384000, P_XO, 5, 1, 10),
F(512000, P_XO, 5, 2, 15),
F(576000, P_XO, 5, 3, 20),
F(705600, P_GPLL1, 16, 1, 80),
F(768000, P_XO, 5, 1, 5),
F(800000, P_XO, 5, 5, 24),
F(1024000, P_XO, 5, 4, 15),
F(1152000, P_XO, 1, 3, 50),
F(1411200, P_GPLL1, 16, 1, 40),
F(1536000, P_XO, 1, 2, 25),
F(1600000, P_XO, 12, 0, 0),
F(1728000, P_XO, 5, 9, 20),
F(2048000, P_XO, 5, 8, 15),
F(2304000, P_XO, 5, 3, 5),
F(2400000, P_XO, 8, 0, 0),
F(2822400, P_GPLL1, 16, 1, 20),
F(3072000, P_XO, 5, 4, 5),
F(4096000, P_GPLL1, 9, 2, 49),
F(4800000, P_XO, 4, 0, 0),
F(5644800, P_GPLL1, 16, 1, 10),
F(6144000, P_GPLL1, 7, 1, 21),
F(8192000, P_GPLL1, 9, 4, 49),
F(9600000, P_XO, 2, 0, 0),
F(11289600, P_GPLL1, 16, 1, 5),
F(12288000, P_GPLL1, 7, 2, 21),
{ }
};
static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
.cmd_rcgr = 0x1c054,
.hid_width = 5,
.mnd_width = 8,
.parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map,
.freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_lpaif_pri_i2s_clk_src",
.parent_data = gcc_xo_gpll1_epi2s_emclk_sleep_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll1_epi2s_emclk_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = {
.halt_reg = 0x1c068,
.clkr = {
.enable_reg = 0x1c068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_lpaif_pri_i2s_clk",
.parent_hws = (const struct clk_hw*[]){
&ultaudio_lpaif_pri_i2s_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
.cmd_rcgr = 0x1c06c,
.hid_width = 5,
.mnd_width = 8,
.parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map,
.freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_lpaif_sec_i2s_clk_src",
.parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = {
.halt_reg = 0x1c080,
.clkr = {
.enable_reg = 0x1c080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_lpaif_sec_i2s_clk",
.parent_hws = (const struct clk_hw*[]){
&ultaudio_lpaif_sec_i2s_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
.cmd_rcgr = 0x1c084,
.hid_width = 5,
.mnd_width = 8,
.parent_map = gcc_xo_gpll1_emclk_sleep_map,
.freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_lpaif_aux_i2s_clk_src",
.parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = {
.halt_reg = 0x1c098,
.clkr = {
.enable_reg = 0x1c098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_lpaif_aux_i2s_clk",
.parent_hws = (const struct clk_hw*[]){
&ultaudio_lpaif_aux_i2s_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 ultaudio_xo_clk_src = {
.cmd_rcgr = 0x1c034,
.hid_width = 5,
.parent_map = gcc_xo_sleep_map,
.freq_tbl = ftbl_gcc_ultaudio_xo_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_xo_clk_src",
.parent_data = gcc_xo_sleep_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_ultaudio_avsync_xo_clk = {
.halt_reg = 0x1c04c,
.clkr = {
.enable_reg = 0x1c04c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_avsync_xo_clk",
.parent_hws = (const struct clk_hw*[]){
&ultaudio_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ultaudio_stc_xo_clk = {
.halt_reg = 0x1c050,
.clkr = {
.enable_reg = 0x1c050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_stc_xo_clk",
.parent_hws = (const struct clk_hw*[]){
&ultaudio_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_codec_clk[] = {
F(9600000, P_XO, 2, 0, 0),
F(12288000, P_XO, 1, 16, 25),
F(19200000, P_XO, 1, 0, 0),
F(11289600, P_EXT_MCLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 codec_digcodec_clk_src = {
.cmd_rcgr = 0x1c09c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll1_emclk_sleep_map,
.freq_tbl = ftbl_codec_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "codec_digcodec_clk_src",
.parent_data = gcc_xo_gpll1_emclk_sleep_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll1_emclk_sleep_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_codec_digcodec_clk = {
.halt_reg = 0x1c0b0,
.clkr = {
.enable_reg = 0x1c0b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_codec_digcodec_clk",
.parent_hws = (const struct clk_hw*[]){
&codec_digcodec_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = {
.halt_reg = 0x1c000,
.clkr = {
.enable_reg = 0x1c000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_pcnoc_mport_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
.halt_reg = 0x1c004,
.clkr = {
.enable_reg = 0x1c004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_pcnoc_sway_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
F(133330000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266670000, P_GPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 vcodec0_clk_src = {
.cmd_rcgr = 0x4C000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vcodec0_clk_src",
.parent_data = gcc_xo_gpll0_parent_data,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x01008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_sleep_clk = {
.halt_reg = 0x01004,
.clkr = {
.enable_reg = 0x01004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x02008,
.clkr = {
.enable_reg = 0x02008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x02004,
.clkr = {
.enable_reg = 0x02004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x03010,
.clkr = {
.enable_reg = 0x03010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x0300c,
.clkr = {
.enable_reg = 0x0300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x04020,
.clkr = {
.enable_reg = 0x04020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x0401c,
.clkr = {
.enable_reg = 0x0401c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.halt_reg = 0x05020,
.clkr = {
.enable_reg = 0x05020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.halt_reg = 0x0501c,
.clkr = {
.enable_reg = 0x0501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
.halt_reg = 0x06020,
.clkr = {
.enable_reg = 0x06020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup5_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
.halt_reg = 0x0601c,
.clkr = {
.enable_reg = 0x0601c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup5_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
.halt_reg = 0x07020,
.clkr = {
.enable_reg = 0x07020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup6_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
.halt_reg = 0x0701c,
.clkr = {
.enable_reg = 0x0701c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup6_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x0203c,
.clkr = {
.enable_reg = 0x0203c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x0302c,
.clkr = {
.enable_reg = 0x0302c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x1300c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cci_ahb_clk = {
.halt_reg = 0x5101c,
.clkr = {
.enable_reg = 0x5101c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cci_clk = {
.halt_reg = 0x51018,
.clkr = {
.enable_reg = 0x51018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_clk",
.parent_hws = (const struct clk_hw*[]){
&cci_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0_ahb_clk = {
.halt_reg = 0x4e040,
.clkr = {
.enable_reg = 0x4e040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0_clk = {
.halt_reg = 0x4e03c,
.clkr = {
.enable_reg = 0x4e03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0phy_clk = {
.halt_reg = 0x4e048,
.clkr = {
.enable_reg = 0x4e048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0pix_clk = {
.halt_reg = 0x4e058,
.clkr = {
.enable_reg = 0x4e058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0rdi_clk = {
.halt_reg = 0x4e050,
.clkr = {
.enable_reg = 0x4e050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1_ahb_clk = {
.halt_reg = 0x4f040,
.clkr = {
.enable_reg = 0x4f040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1_clk = {
.halt_reg = 0x4f03c,
.clkr = {
.enable_reg = 0x4f03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1phy_clk = {
.halt_reg = 0x4f048,
.clkr = {
.enable_reg = 0x4f048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1pix_clk = {
.halt_reg = 0x4f058,
.clkr = {
.enable_reg = 0x4f058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1rdi_clk = {
.halt_reg = 0x4f050,
.clkr = {
.enable_reg = 0x4f050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi_vfe0_clk = {
.halt_reg = 0x58050,
.clkr = {
.enable_reg = 0x58050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi_vfe0_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_gp0_clk = {
.halt_reg = 0x54018,
.clkr = {
.enable_reg = 0x54018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_gp0_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_gp0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_gp1_clk = {
.halt_reg = 0x55018,
.clkr = {
.enable_reg = 0x55018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_ispif_ahb_clk = {
.halt_reg = 0x50004,
.clkr = {
.enable_reg = 0x50004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ispif_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_jpeg0_clk = {
.halt_reg = 0x57020,
.clkr = {
.enable_reg = 0x57020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_jpeg0_clk",
.parent_hws = (const struct clk_hw*[]){
&jpeg0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_jpeg_ahb_clk = {
.halt_reg = 0x57024,
.clkr = {
.enable_reg = 0x57024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_jpeg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_jpeg_axi_clk = {
.halt_reg = 0x57028,
.clkr = {
.enable_reg = 0x57028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_jpeg_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_mm_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk0_clk = {
.halt_reg = 0x52018,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk1_clk = {
.halt_reg = 0x53018,
.clkr = {
.enable_reg = 0x53018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_micro_ahb_clk = {
.halt_reg = 0x5600c,
.clkr = {
.enable_reg = 0x5600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_micro_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0phytimer_clk = {
.halt_reg = 0x4e01c,
.clkr = {
.enable_reg = 0x4e01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1phytimer_clk = {
.halt_reg = 0x4f01c,
.clkr = {
.enable_reg = 0x4f01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_ahb_clk = {
.halt_reg = 0x5a014,
.clkr = {
.enable_reg = 0x5a014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_top_ahb_clk = {
.halt_reg = 0x56004,
.clkr = {
.enable_reg = 0x56004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_top_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cpp_ahb_clk = {
.halt_reg = 0x58040,
.clkr = {
.enable_reg = 0x58040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cpp_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cpp_clk = {
.halt_reg = 0x5803c,
.clkr = {
.enable_reg = 0x5803c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cpp_clk",
.parent_hws = (const struct clk_hw*[]){
&cpp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_vfe0_clk = {
.halt_reg = 0x58038,
.clkr = {
.enable_reg = 0x58038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe0_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_vfe_ahb_clk = {
.halt_reg = 0x58044,
.clkr = {
.enable_reg = 0x58044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_vfe_axi_clk = {
.halt_reg = 0x58048,
.clkr = {
.enable_reg = 0x58048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_mm_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_ahb_clk = {
.halt_reg = 0x16024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_axi_clk = {
.halt_reg = 0x16020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_clk = {
.halt_reg = 0x1601c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_clk",
.parent_hws = (const struct clk_hw*[]){
&crypto_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_oxili_gmem_clk = {
.halt_reg = 0x59024,
.clkr = {
.enable_reg = 0x59024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_oxili_gmem_clk",
.parent_hws = (const struct clk_hw*[]){
&gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x08000,
.clkr = {
.enable_reg = 0x08000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x09000,
.clkr = {
.enable_reg = 0x09000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]){
&gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x0a000,
.clkr = {
.enable_reg = 0x0a000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]){
&gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_ahb_clk = {
.halt_reg = 0x4d07c,
.clkr = {
.enable_reg = 0x4d07c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_axi_clk = {
.halt_reg = 0x4d080,
.clkr = {
.enable_reg = 0x4d080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_mm_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_byte0_clk = {
.halt_reg = 0x4d094,
.clkr = {
.enable_reg = 0x4d094,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]){
&byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_byte1_clk = {
.halt_reg = 0x4d0a0,
.clkr = {
.enable_reg = 0x4d0a0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_byte1_clk",
.parent_hws = (const struct clk_hw*[]){
&byte1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_esc0_clk = {
.halt_reg = 0x4d098,
.clkr = {
.enable_reg = 0x4d098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]){
&esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_esc1_clk = {
.halt_reg = 0x4d09c,
.clkr = {
.enable_reg = 0x4d09c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_esc1_clk",
.parent_hws = (const struct clk_hw*[]){
&esc1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_mdp_clk = {
.halt_reg = 0x4D088,
.clkr = {
.enable_reg = 0x4D088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_pclk0_clk = {
.halt_reg = 0x4d084,
.clkr = {
.enable_reg = 0x4d084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_pclk1_clk = {
.halt_reg = 0x4d0a4,
.clkr = {
.enable_reg = 0x4d0a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_pclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&pclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdss_vsync_clk = {
.halt_reg = 0x4d090,
.clkr = {
.enable_reg = 0x4d090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_cfg_ahb_clk = {
.halt_reg = 0x49000,
.clkr = {
.enable_reg = 0x49000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.halt_reg = 0x49004,
.clkr = {
.enable_reg = 0x49004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_q6_bimc_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&bimc_ddr_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_oxili_ahb_clk = {
.halt_reg = 0x59028,
.clkr = {
.enable_reg = 0x59028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_oxili_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_oxili_gfx3d_clk = {
.halt_reg = 0x59020,
.clkr = {
.enable_reg = 0x59020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_oxili_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]){
&gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x4400c,
.clkr = {
.enable_reg = 0x4400c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]){
&pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x44004,
.clkr = {
.enable_reg = 0x44004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x13004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x45004,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x4201c,
.clkr = {
.enable_reg = 0x4201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x42018,
.clkr = {
.enable_reg = 0x42018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x4301c,
.clkr = {
.enable_reg = 0x4301c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x43018,
.clkr = {
.enable_reg = 0x43018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_apss_tcu_clk = {
.halt_reg = 0x12018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_tcu_clk",
.parent_hws = (const struct clk_hw*[]){
&bimc_ddr_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gfx_tcu_clk = {
.halt_reg = 0x12020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_gfx_tcu_clk",
.parent_hws = (const struct clk_hw*[]){
&bimc_ddr_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gfx_tbu_clk = {
.halt_reg = 0x12010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_gfx_tbu_clk",
.parent_hws = (const struct clk_hw*[]){
&bimc_ddr_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdp_tbu_clk = {
.halt_reg = 0x1201c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdp_tbu_clk",
.parent_hws = (const struct clk_hw*[]){
&system_mm_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus_tbu_clk = {
.halt_reg = 0x12014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus_tbu_clk",
.parent_hws = (const struct clk_hw*[]){
&system_mm_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vfe_tbu_clk = {
.halt_reg = 0x1203c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_vfe_tbu_clk",
.parent_hws = (const struct clk_hw*[]){
&system_mm_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_jpeg_tbu_clk = {
.halt_reg = 0x12034,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_jpeg_tbu_clk",
.parent_hws = (const struct clk_hw*[]){
&system_mm_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_smmu_cfg_clk = {
.halt_reg = 0x12038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_smmu_cfg_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gtcu_ahb_clk = {
.halt_reg = 0x12044,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_gtcu_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpp_tbu_clk = {
.halt_reg = 0x12040,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpp_tbu_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdp_rt_tbu_clk = {
.halt_reg = 0x1201c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4500c,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdp_rt_tbu_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_bimc_gfx_clk = {
.halt_reg = 0x31024,
.clkr = {
.enable_reg = 0x31024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_gfx_clk",
.parent_hws = (const struct clk_hw*[]){
&bimc_gpu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_bimc_gpu_clk = {
.halt_reg = 0x31040,
.clkr = {
.enable_reg = 0x31040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_gpu_clk",
.parent_hws = (const struct clk_hw*[]){
&bimc_gpu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb2a_phy_sleep_clk = {
.halt_reg = 0x4102c,
.clkr = {
.enable_reg = 0x4102c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb2a_phy_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_fs_ahb_clk = {
.halt_reg = 0x3f008,
.clkr = {
.enable_reg = 0x3f008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_fs_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_fs_ic_clk = {
.halt_reg = 0x3f030,
.clkr = {
.enable_reg = 0x3f030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_fs_ic_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_fs_ic_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_fs_system_clk = {
.halt_reg = 0x3f004,
.clkr = {
.enable_reg = 0x3f004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_fs_system_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_fs_system_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_ahb_clk = {
.halt_reg = 0x41008,
.clkr = {
.enable_reg = 0x41008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_system_clk = {
.halt_reg = 0x41004,
.clkr = {
.enable_reg = 0x41004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_system_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_hs_system_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus0_ahb_clk = {
.halt_reg = 0x4c020,
.clkr = {
.enable_reg = 0x4c020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus0_axi_clk = {
.halt_reg = 0x4c024,
.clkr = {
.enable_reg = 0x4c024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus0_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_mm_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus0_vcodec0_clk = {
.halt_reg = 0x4c01c,
.clkr = {
.enable_reg = 0x4c01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus0_vcodec0_clk",
.parent_hws = (const struct clk_hw*[]){
&vcodec0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
.halt_reg = 0x4c02c,
.clkr = {
.enable_reg = 0x4c02c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus0_core0_vcodec0_clk",
.parent_hws = (const struct clk_hw*[]){
&vcodec0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus0_core1_vcodec0_clk = {
.halt_reg = 0x4c034,
.clkr = {
.enable_reg = 0x4c034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus0_core1_vcodec0_clk",
.parent_hws = (const struct clk_hw*[]){
&vcodec0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_oxili_timer_clk = {
.halt_reg = 0x59040,
.clkr = {
.enable_reg = 0x59040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_oxili_timer_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc venus_gdsc = {
.gdscr = 0x4c018,
.pd = {
.name = "venus",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x4d078,
.pd = {
.name = "mdss",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc jpeg_gdsc = {
.gdscr = 0x5701c,
.pd = {
.name = "jpeg",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc vfe_gdsc = {
.gdscr = 0x58034,
.pd = {
.name = "vfe",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc oxili_gdsc = {
.gdscr = 0x5901c,
.pd = {
.name = "oxili",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc venus_core0_gdsc = {
.gdscr = 0x4c028,
.pd = {
.name = "venus_core0",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc venus_core1_gdsc = {
.gdscr = 0x4c030,
.pd = {
.name = "venus_core1",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *gcc_msm8939_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL0_VOTE] = &gpll0_vote,
[BIMC_PLL] = &bimc_pll.clkr,
[BIMC_PLL_VOTE] = &bimc_pll_vote,
[GPLL1] = &gpll1.clkr,
[GPLL1_VOTE] = &gpll1_vote,
[GPLL2] = &gpll2.clkr,
[GPLL2_VOTE] = &gpll2_vote,
[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
[SYSTEM_MM_NOC_BFDCD_CLK_SRC] = &system_mm_noc_bfdcd_clk_src.clkr,
[CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[CCI_CLK_SRC] = &cci_clk_src.clkr,
[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
[CPP_CLK_SRC] = &cpp_clk_src.clkr,
[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
[MDP_CLK_SRC] = &mdp_clk_src.clkr,
[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
[APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
[VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
[GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
[GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
[GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
[GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
[GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
[GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
[GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
[GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
[GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
[GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
[GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
[GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
[GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
[GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
[GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
[GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
[GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
[GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
[GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
[GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
[GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
[GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
[GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
[GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
[GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
[GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
[GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
[GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
[GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
[GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
[GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
[GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
[GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
[GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
[GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
[GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
[GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
[GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
[GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
[GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
[GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
[GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
[BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
[GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
[GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
[BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,
[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
[GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
[ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr,
[ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr,
[ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr,
[ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr,
[ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr,
[CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr,
[GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr,
[GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr,
[GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr,
[GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr,
[GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr,
[GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr,
[GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr,
[GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr,
[GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr,
[GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr,
[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
[GPLL3] = &gpll3.clkr,
[GPLL3_VOTE] = &gpll3_vote,
[GPLL4] = &gpll4.clkr,
[GPLL4_VOTE] = &gpll4_vote,
[GPLL5] = &gpll5.clkr,
[GPLL5_VOTE] = &gpll5_vote,
[GPLL6] = &gpll6.clkr,
[GPLL6_VOTE] = &gpll6_vote,
[BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
[GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr,
[ESC1_CLK_SRC] = &esc1_clk_src.clkr,
[GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr,
[PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
[GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr,
[GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
[GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
[GCC_MDP_RT_TBU_CLK] = &gcc_mdp_rt_tbu_clk.clkr,
[USB_FS_SYSTEM_CLK_SRC] = &usb_fs_system_clk_src.clkr,
[USB_FS_IC_CLK_SRC] = &usb_fs_ic_clk_src.clkr,
[GCC_USB_FS_AHB_CLK] = &gcc_usb_fs_ahb_clk.clkr,
[GCC_USB_FS_IC_CLK] = &gcc_usb_fs_ic_clk.clkr,
[GCC_USB_FS_SYSTEM_CLK] = &gcc_usb_fs_system_clk.clkr,
[GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
[GCC_VENUS0_CORE1_VCODEC0_CLK] = &gcc_venus0_core1_vcodec0_clk.clkr,
[GCC_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr,
};
static struct gdsc *gcc_msm8939_gdscs[] = {
[VENUS_GDSC] = &venus_gdsc,
[MDSS_GDSC] = &mdss_gdsc,
[JPEG_GDSC] = &jpeg_gdsc,
[VFE_GDSC] = &vfe_gdsc,
[OXILI_GDSC] = &oxili_gdsc,
[VENUS_CORE0_GDSC] = &venus_core0_gdsc,
[VENUS_CORE1_GDSC] = &venus_core1_gdsc,
};
static const struct qcom_reset_map gcc_msm8939_resets[] = {
[GCC_BLSP1_BCR] = { 0x01000 },
[GCC_BLSP1_QUP1_BCR] = { 0x02000 },
[GCC_BLSP1_UART1_BCR] = { 0x02038 },
[GCC_BLSP1_QUP2_BCR] = { 0x03008 },
[GCC_BLSP1_UART2_BCR] = { 0x03028 },
[GCC_BLSP1_QUP3_BCR] = { 0x04018 },
[GCC_BLSP1_UART3_BCR] = { 0x04038 },
[GCC_BLSP1_QUP4_BCR] = { 0x05018 },
[GCC_BLSP1_QUP5_BCR] = { 0x06018 },
[GCC_BLSP1_QUP6_BCR] = { 0x07018 },
[GCC_IMEM_BCR] = { 0x0e000 },
[GCC_SMMU_BCR] = { 0x12000 },
[GCC_APSS_TCU_BCR] = { 0x12050 },
[GCC_SMMU_XPU_BCR] = { 0x12054 },
[GCC_PCNOC_TBU_BCR] = { 0x12058 },
[GCC_PRNG_BCR] = { 0x13000 },
[GCC_BOOT_ROM_BCR] = { 0x13008 },
[GCC_CRYPTO_BCR] = { 0x16000 },
[GCC_SEC_CTRL_BCR] = { 0x1a000 },
[GCC_AUDIO_CORE_BCR] = { 0x1c008 },
[GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
[GCC_DEHR_BCR] = { 0x1f000 },
[GCC_SYSTEM_NOC_BCR] = { 0x26000 },
[GCC_PCNOC_BCR] = { 0x27018 },
[GCC_TCSR_BCR] = { 0x28000 },
[GCC_QDSS_BCR] = { 0x29000 },
[GCC_DCD_BCR] = { 0x2a000 },
[GCC_MSG_RAM_BCR] = { 0x2b000 },
[GCC_MPM_BCR] = { 0x2c000 },
[GCC_SPMI_BCR] = { 0x2e000 },
[GCC_SPDM_BCR] = { 0x2f000 },
[GCC_MM_SPDM_BCR] = { 0x2f024 },
[GCC_BIMC_BCR] = { 0x31000 },
[GCC_RBCPR_BCR] = { 0x33000 },
[GCC_TLMM_BCR] = { 0x34000 },
[GCC_CAMSS_CSI2_BCR] = { 0x3c038 },
[GCC_CAMSS_CSI2PHY_BCR] = { 0x3c044 },
[GCC_CAMSS_CSI2RDI_BCR] = { 0x3c04c },
[GCC_CAMSS_CSI2PIX_BCR] = { 0x3c054 },
[GCC_USB_FS_BCR] = { 0x3f000 },
[GCC_USB_HS_BCR] = { 0x41000 },
[GCC_USB2A_PHY_BCR] = { 0x41028 },
[GCC_SDCC1_BCR] = { 0x42000 },
[GCC_SDCC2_BCR] = { 0x43000 },
[GCC_PDM_BCR] = { 0x44000 },
[GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
[GCC_MMSS_BCR] = { 0x4b000 },
[GCC_VENUS0_BCR] = { 0x4c014 },
[GCC_MDSS_BCR] = { 0x4d074 },
[GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
[GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
[GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
[GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
[GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
[GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
[GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
[GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
[GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
[GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
[GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
[GCC_BLSP1_QUP4_SPI_APPS_CBCR] = { 0x0501c },
[GCC_CAMSS_CCI_BCR] = { 0x51014 },
[GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
[GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
[GCC_CAMSS_GP0_BCR] = { 0x54014 },
[GCC_CAMSS_GP1_BCR] = { 0x55014 },
[GCC_CAMSS_TOP_BCR] = { 0x56000 },
[GCC_CAMSS_MICRO_BCR] = { 0x56008 },
[GCC_CAMSS_JPEG_BCR] = { 0x57018 },
[GCC_CAMSS_VFE_BCR] = { 0x58030 },
[GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
[GCC_OXILI_BCR] = { 0x59018 },
[GCC_GMEM_BCR] = { 0x5902c },
[GCC_CAMSS_AHB_BCR] = { 0x5a018 },
[GCC_CAMSS_MCLK2_BCR] = { 0x5c014 },
[GCC_MDP_TBU_BCR] = { 0x62000 },
[GCC_GFX_TBU_BCR] = { 0x63000 },
[GCC_GFX_TCU_BCR] = { 0x64000 },
[GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
[GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
[GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
[GCC_GTCU_AHB_BCR] = { 0x68000 },
[GCC_SMMU_CFG_BCR] = { 0x69000 },
[GCC_VFE_TBU_BCR] = { 0x6a000 },
[GCC_VENUS_TBU_BCR] = { 0x6b000 },
[GCC_JPEG_TBU_BCR] = { 0x6c000 },
[GCC_PRONTO_TBU_BCR] = { 0x6d000 },
[GCC_CPP_TBU_BCR] = { 0x6e000 },
[GCC_MDP_RT_TBU_BCR] = { 0x6f000 },
[GCC_SMMU_CATS_BCR] = { 0x7c000 },
};
static const struct regmap_config gcc_msm8939_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x80000,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_msm8939_desc = {
.config = &gcc_msm8939_regmap_config,
.clks = gcc_msm8939_clocks,
.num_clks = ARRAY_SIZE(gcc_msm8939_clocks),
.resets = gcc_msm8939_resets,
.num_resets = ARRAY_SIZE(gcc_msm8939_resets),
.gdscs = gcc_msm8939_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_msm8939_gdscs),
};
static const struct of_device_id gcc_msm8939_match_table[] = {
{ .compatible = "qcom,gcc-msm8939" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_msm8939_match_table);
static int gcc_msm8939_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gcc_msm8939_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_pll_configure_sr_hpm_lp(&gpll3, regmap, &gpll3_config, true);
clk_pll_configure_sr_hpm_lp(&gpll4, regmap, &gpll4_config, true);
return qcom_cc_really_probe(pdev, &gcc_msm8939_desc, regmap);
}
static struct platform_driver gcc_msm8939_driver = {
.probe = gcc_msm8939_probe,
.driver = {
.name = "gcc-msm8939",
.of_match_table = gcc_msm8939_match_table,
},
};
static int __init gcc_msm8939_init(void)
{
return platform_driver_register(&gcc_msm8939_driver);
}
core_initcall(gcc_msm8939_init);
static void __exit gcc_msm8939_exit(void)
{
platform_driver_unregister(&gcc_msm8939_driver);
}
module_exit(gcc_msm8939_exit);
MODULE_DESCRIPTION("Qualcomm GCC MSM8939 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gcc-msm8939.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022, Konrad Dybcio <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm6375-gcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_BI_TCXO_AO,
DT_SLEEP_CLK
};
enum {
P_BI_TCXO,
P_GPLL0_OUT_EVEN,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_ODD,
P_GPLL10_OUT_EVEN,
P_GPLL11_OUT_EVEN,
P_GPLL11_OUT_ODD,
P_GPLL3_OUT_EVEN,
P_GPLL3_OUT_MAIN,
P_GPLL4_OUT_EVEN,
P_GPLL5_OUT_EVEN,
P_GPLL6_OUT_EVEN,
P_GPLL6_OUT_MAIN,
P_GPLL7_OUT_EVEN,
P_GPLL8_OUT_EVEN,
P_GPLL8_OUT_MAIN,
P_GPLL9_OUT_EARLY,
P_GPLL9_OUT_MAIN,
P_SLEEP_CLK,
};
static struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
static struct pll_vco zonda_vco[] = {
{ 595200000, 3600000000UL, 0 },
};
static struct clk_alpha_pll gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll0_out_even = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_even",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
static const struct clk_div_table post_div_table_gpll0_out_odd[] = {
{ 0x3, 3 },
{ }
};
static struct clk_alpha_pll_postdiv gpll0_out_odd = {
.offset = 0x0,
.post_div_shift = 12,
.post_div_table = post_div_table_gpll0_out_odd,
.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_odd),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_odd",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
static struct clk_alpha_pll gpll1 = {
.offset = 0x1000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gpll1",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
/* 1152MHz Configuration */
static const struct alpha_pll_config gpll10_config = {
.l = 0x3c,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329a299c,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll gpll10 = {
.offset = 0xa000,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.flags = SUPPORTS_FSM_LEGACY_MODE,
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gpll10",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ops,
},
},
};
/* 532MHz Configuration */
static const struct alpha_pll_config gpll11_config = {
.l = 0x1b,
.alpha = 0xb555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329a299c,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll gpll11 = {
.offset = 0xb000,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.flags = SUPPORTS_FSM_LEGACY_MODE,
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gpll11",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static struct clk_alpha_pll gpll3 = {
.offset = 0x3000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gpll3",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll3_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll3_out_even = {
.offset = 0x3000,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll3_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gpll3_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll3_out_even",
.parent_hws = (const struct clk_hw*[]){
&gpll3.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
static struct clk_alpha_pll gpll4 = {
.offset = 0x4000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ops,
},
},
};
static struct clk_alpha_pll gpll5 = {
.offset = 0x5000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gpll5",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ops,
},
},
};
static struct clk_alpha_pll gpll6 = {
.offset = 0x6000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gpll6",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll6_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll6_out_even = {
.offset = 0x6000,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll6_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll6_out_even",
.parent_hws = (const struct clk_hw*[]){
&gpll6.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
static struct clk_alpha_pll gpll7 = {
.offset = 0x7000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gpll7",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ops,
},
},
};
/* 400MHz Configuration */
static const struct alpha_pll_config gpll8_config = {
.l = 0x14,
.alpha = 0xd555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329a299c,
.user_ctl_val = 0x00000101,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll gpll8 = {
.offset = 0x8000,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.flags = SUPPORTS_FSM_LEGACY_MODE,
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gpll8",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll8_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll8_out_even = {
.offset = 0x8000,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll8_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll8_out_even",
.parent_hws = (const struct clk_hw*[]){
&gpll8.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
/* 1440MHz Configuration */
static const struct alpha_pll_config gpll9_config = {
.l = 0x4b,
.alpha = 0x0,
.config_ctl_val = 0x08200800,
.config_ctl_hi_val = 0x05022011,
.config_ctl_hi1_val = 0x08000000,
.user_ctl_val = 0x00000301,
};
static struct clk_alpha_pll gpll9 = {
.offset = 0x9000,
.vco_table = zonda_vco,
.num_vco = ARRAY_SIZE(zonda_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
.clkr = {
.enable_reg = 0x79000,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gpll9",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_zonda_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll9_out_main[] = {
{ 0x3, 4 },
{ }
};
static struct clk_alpha_pll_postdiv gpll9_out_main = {
.offset = 0x9000,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll9_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main),
.width = 2,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll9_out_main",
.parent_hws = (const struct clk_hw*[]){
&gpll9.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_zonda_ops,
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 2 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 2 },
{ P_GPLL6_OUT_EVEN, 4 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
{ .hw = &gpll6_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 2 },
{ P_GPLL0_OUT_ODD, 4 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
{ .hw = &gpll0_out_odd.clkr.hw },
};
static const struct clk_parent_data gcc_parent_data_2_ao[] = {
{ .index = DT_BI_TCXO_AO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
{ .hw = &gpll0_out_odd.clkr.hw },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL9_OUT_EARLY, 2 },
{ P_GPLL10_OUT_EVEN, 3 },
{ P_GPLL9_OUT_MAIN, 4 },
{ P_GPLL3_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll9.clkr.hw },
{ .hw = &gpll10.clkr.hw },
{ .hw = &gpll9_out_main.clkr.hw },
{ .hw = &gpll3_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 2 },
{ P_GPLL0_OUT_ODD, 4 },
{ P_GPLL4_OUT_EVEN, 5 },
{ P_GPLL3_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_4[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
{ .hw = &gpll0_out_odd.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll3_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL8_OUT_MAIN, 2 },
{ P_GPLL10_OUT_EVEN, 3 },
{ P_GPLL9_OUT_MAIN, 4 },
{ P_GPLL8_OUT_EVEN, 5 },
{ P_GPLL3_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll8.clkr.hw },
{ .hw = &gpll10.clkr.hw },
{ .hw = &gpll9_out_main.clkr.hw },
{ .hw = &gpll8_out_even.clkr.hw },
{ .hw = &gpll3_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL8_OUT_MAIN, 2 },
{ P_GPLL5_OUT_EVEN, 3 },
{ P_GPLL9_OUT_MAIN, 4 },
{ P_GPLL8_OUT_EVEN, 5 },
{ P_GPLL3_OUT_MAIN, 6 },
};
static const struct clk_parent_data gcc_parent_data_6[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll8.clkr.hw },
{ .hw = &gpll5.clkr.hw },
{ .hw = &gpll9_out_main.clkr.hw },
{ .hw = &gpll8_out_even.clkr.hw },
{ .hw = &gpll3.clkr.hw },
};
static const struct parent_map gcc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 2 },
{ P_GPLL0_OUT_ODD, 4 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_7[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
{ .hw = &gpll0_out_odd.clkr.hw },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 2 },
{ P_GPLL10_OUT_EVEN, 3 },
{ P_GPLL4_OUT_EVEN, 5 },
{ P_GPLL3_OUT_MAIN, 6 },
};
static const struct clk_parent_data gcc_parent_data_8[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
{ .hw = &gpll10.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll3.clkr.hw },
};
static const struct parent_map gcc_parent_map_9[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 2 },
{ P_GPLL10_OUT_EVEN, 3 },
{ P_GPLL9_OUT_MAIN, 4 },
{ P_GPLL8_OUT_EVEN, 5 },
{ P_GPLL3_OUT_MAIN, 6 },
};
static const struct clk_parent_data gcc_parent_data_9[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
{ .hw = &gpll10.clkr.hw },
{ .hw = &gpll9_out_main.clkr.hw },
{ .hw = &gpll8_out_even.clkr.hw },
{ .hw = &gpll3.clkr.hw },
};
static const struct parent_map gcc_parent_map_10[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL8_OUT_MAIN, 2 },
{ P_GPLL10_OUT_EVEN, 3 },
{ P_GPLL9_OUT_MAIN, 4 },
{ P_GPLL8_OUT_EVEN, 5 },
{ P_GPLL3_OUT_MAIN, 6 },
};
static const struct clk_parent_data gcc_parent_data_10[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll8.clkr.hw },
{ .hw = &gpll10.clkr.hw },
{ .hw = &gpll9_out_main.clkr.hw },
{ .hw = &gpll8_out_even.clkr.hw },
{ .hw = &gpll3.clkr.hw },
};
static const struct parent_map gcc_parent_map_11[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL8_OUT_MAIN, 2 },
{ P_GPLL10_OUT_EVEN, 3 },
{ P_GPLL6_OUT_MAIN, 4 },
{ P_GPLL3_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_11[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll8.clkr.hw },
{ .hw = &gpll10.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll3_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_12[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 2 },
{ P_GPLL7_OUT_EVEN, 3 },
{ P_GPLL4_OUT_EVEN, 5 },
};
static const struct clk_parent_data gcc_parent_data_12[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
{ .hw = &gpll7.clkr.hw },
{ .hw = &gpll4.clkr.hw },
};
static const struct parent_map gcc_parent_map_13[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_13[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_parent_map_14[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL11_OUT_ODD, 2 },
{ P_GPLL11_OUT_EVEN, 3 },
};
static const struct clk_parent_data gcc_parent_data_14[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll11.clkr.hw },
{ .hw = &gpll11.clkr.hw },
};
static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_axi_clk_src = {
.cmd_rcgr = 0x5802c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_camss_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_axi_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_cci_0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_cci_0_clk_src = {
.cmd_rcgr = 0x56000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_9,
.freq_tbl = ftbl_gcc_camss_cci_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_0_clk_src",
.parent_data = gcc_parent_data_9,
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_cci_1_clk_src = {
.cmd_rcgr = 0x5c000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_9,
.freq_tbl = ftbl_gcc_camss_cci_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_1_clk_src",
.parent_data = gcc_parent_data_9,
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = {
.cmd_rcgr = 0x59000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0phytimer_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = {
.cmd_rcgr = 0x5901c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1phytimer_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = {
.cmd_rcgr = 0x59038,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi2phytimer_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_csi3phytimer_clk_src = {
.cmd_rcgr = 0x59054,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi3phytimer_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 15),
F(65454545, P_GPLL9_OUT_EARLY, 11, 1, 2),
{ }
};
static struct clk_rcg2 gcc_camss_mclk0_clk_src = {
.cmd_rcgr = 0x51000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk0_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_mclk1_clk_src = {
.cmd_rcgr = 0x5101c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk1_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_mclk2_clk_src = {
.cmd_rcgr = 0x51038,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk2_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_mclk3_clk_src = {
.cmd_rcgr = 0x51054,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk3_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_mclk4_clk_src = {
.cmd_rcgr = 0x51070,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk4_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = {
.cmd_rcgr = 0x55024,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_10,
.freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ope_ahb_clk_src",
.parent_data = gcc_parent_data_10,
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_GPLL8_OUT_EVEN, 1, 0, 0),
F(266600000, P_GPLL8_OUT_EVEN, 1, 0, 0),
F(480000000, P_GPLL8_OUT_EVEN, 1, 0, 0),
F(580000000, P_GPLL8_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_ope_clk_src = {
.cmd_rcgr = 0x55004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_10,
.freq_tbl = ftbl_gcc_camss_ope_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ope_clk_src",
.parent_data = gcc_parent_data_10,
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(144000000, P_GPLL9_OUT_MAIN, 2.5, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
F(180000000, P_GPLL9_OUT_MAIN, 2, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
F(329142857, P_GPLL10_OUT_EVEN, 3.5, 0, 0),
F(384000000, P_GPLL10_OUT_EVEN, 3, 0, 0),
F(460800000, P_GPLL10_OUT_EVEN, 2.5, 0, 0),
F(576000000, P_GPLL10_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_tfe_0_clk_src = {
.cmd_rcgr = 0x52004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
F(266571429, P_GPLL5_OUT_EVEN, 3.5, 0, 0),
F(426400000, P_GPLL3_OUT_MAIN, 2.5, 0, 0),
F(466500000, P_GPLL5_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = {
.cmd_rcgr = 0x52094,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_csid_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_tfe_1_clk_src = {
.cmd_rcgr = 0x52024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = {
.cmd_rcgr = 0x520b4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_csid_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_tfe_2_clk_src = {
.cmd_rcgr = 0x52044,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_2_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_camss_tfe_2_csid_clk_src = {
.cmd_rcgr = 0x520d4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_2_csid_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(256000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
F(384000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = {
.cmd_rcgr = 0x52064,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_11,
.freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_cphy_rx_clk_src",
.parent_data = gcc_parent_data_11,
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
F(80000000, P_GPLL0_OUT_MAIN, 7.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_camss_top_ahb_clk_src = {
.cmd_rcgr = 0x58010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_camss_top_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_camss_top_ahb_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
.cmd_rcgr = 0x2b13c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk_src",
.parent_data = gcc_parent_data_2_ao,
.num_parents = ARRAY_SIZE(gcc_parent_data_2_ao),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x4d004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x4e004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x4f004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x20010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
F(128000000, P_GPLL6_OUT_EVEN, 3, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x1f148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.cmd_rcgr = 0x1f278,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.cmd_rcgr = 0x1f3a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.cmd_rcgr = 0x1f4d8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.cmd_rcgr = 0x1f608,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.cmd_rcgr = 0x1f738,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.cmd_rcgr = 0x5301c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.cmd_rcgr = 0x5314c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.cmd_rcgr = 0x5327c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.cmd_rcgr = 0x533ac,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.cmd_rcgr = 0x534dc,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.cmd_rcgr = 0x5360c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
F(144000, P_BI_TCXO, 16, 3, 25),
F(400000, P_BI_TCXO, 12, 1, 4),
F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(192000000, P_GPLL6_OUT_EVEN, 2, 0, 0),
F(384000000, P_GPLL6_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.cmd_rcgr = 0x38028,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x38010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(202000000, P_GPLL7_OUT_EVEN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.cmd_rcgr = 0x1e00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_12,
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_12,
.num_parents = ARRAY_SIZE(gcc_parent_data_12),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.cmd_rcgr = 0x45020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.cmd_rcgr = 0x45048,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
.cmd_rcgr = 0x4507c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.cmd_rcgr = 0x45060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.cmd_rcgr = 0x1a01c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.cmd_rcgr = 0x1a034,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.cmd_rcgr = 0x1a060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_13,
.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parent_data_13,
.num_parents = ARRAY_SIZE(gcc_parent_data_13),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = {
F(133000000, P_GPLL11_OUT_EVEN, 4, 0, 0),
F(240000000, P_GPLL11_OUT_EVEN, 2.5, 0, 0),
F(300000000, P_GPLL11_OUT_EVEN, 2, 0, 0),
F(384000000, P_GPLL11_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_video_venus_clk_src = {
.cmd_rcgr = 0x58060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_14,
.freq_tbl = ftbl_gcc_video_venus_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_video_venus_clk_src",
.parent_data = gcc_parent_data_14,
.num_parents = ARRAY_SIZE(gcc_parent_data_14),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = {
.reg = 0x2b154,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_cpuss_ahb_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_cpuss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
.reg = 0x1a04c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gcc_ahb2phy_csi_clk = {
.halt_reg = 0x1d004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1d004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1d004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ahb2phy_csi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ahb2phy_usb_clk = {
.halt_reg = 0x1d008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1d008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1d008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ahb2phy_usb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_bimc_gpu_axi_clk = {
.halt_reg = 0x71154,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x71154,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_gpu_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x23004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x23004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cam_throttle_nrt_clk = {
.halt_reg = 0x17070,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17070,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_cam_throttle_nrt_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cam_throttle_rt_clk = {
.halt_reg = 0x1706c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1706c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_cam_throttle_rt_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_ahb_clk = {
.halt_reg = 0x17008,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x17008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_axi_clk = {
.halt_reg = 0x58044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cci_0_clk = {
.halt_reg = 0x56018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x56018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_cci_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cci_1_clk = {
.halt_reg = 0x5c018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5c018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_cci_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cphy_0_clk = {
.halt_reg = 0x52088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x52088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cphy_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cphy_1_clk = {
.halt_reg = 0x5208c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5208c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cphy_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cphy_2_clk = {
.halt_reg = 0x52090,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x52090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cphy_2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_cphy_3_clk = {
.halt_reg = 0x520f8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x520f8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cphy_3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi0phytimer_clk = {
.halt_reg = 0x59018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_csi0phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi1phytimer_clk = {
.halt_reg = 0x59034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_csi1phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi2phytimer_clk = {
.halt_reg = 0x59050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x59050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi2phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_csi2phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_csi3phytimer_clk = {
.halt_reg = 0x5906c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5906c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi3phytimer_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_csi3phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk0_clk = {
.halt_reg = 0x51018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x51018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk1_clk = {
.halt_reg = 0x51034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x51034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk2_clk = {
.halt_reg = 0x51050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x51050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_mclk2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk3_clk = {
.halt_reg = 0x5106c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5106c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_mclk3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_mclk4_clk = {
.halt_reg = 0x51088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x51088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk4_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_mclk4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_nrt_axi_clk = {
.halt_reg = 0x58054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_nrt_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_ope_ahb_clk = {
.halt_reg = 0x5503c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5503c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ope_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_ope_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_ope_clk = {
.halt_reg = 0x5501c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ope_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_ope_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_rt_axi_clk = {
.halt_reg = 0x5805c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5805c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_rt_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_0_clk = {
.halt_reg = 0x5201c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = {
.halt_reg = 0x5207c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5207c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_0_csid_clk = {
.halt_reg = 0x520ac,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x520ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_csid_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_0_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_1_clk = {
.halt_reg = 0x5203c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5203c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = {
.halt_reg = 0x52080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x52080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_1_csid_clk = {
.halt_reg = 0x520cc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x520cc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_csid_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_1_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_2_clk = {
.halt_reg = 0x5205c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5205c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_2_cphy_rx_clk = {
.halt_reg = 0x52084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x52084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_2_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_tfe_2_csid_clk = {
.halt_reg = 0x520ec,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x520ec,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_2_csid_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_2_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camss_top_ahb_clk = {
.halt_reg = 0x58028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x58028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_top_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.halt_reg = 0x1a084,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1a084,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1a084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_ahb_clk = {
.halt_reg = 0x1700c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1700c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1700c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap_div gcc_disp_gpll0_clk_src = {
.reg = 0x17058,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_disp_gpll0_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
};
static struct clk_branch gcc_disp_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_disp_gpll0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_hf_axi_clk = {
.halt_reg = 0x17020,
.halt_check = BRANCH_VOTED,
.hwcg_reg = 0x17020,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_sleep_clk = {
.halt_reg = 0x17074,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17074,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17074,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_throttle_core_clk = {
.halt_reg = 0x17064,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17064,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_throttle_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x4d000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x4e000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4e000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x4f000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4f000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_cfg_ahb_clk = {
.halt_reg = 0x36004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x36004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x36004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_cfg_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gpll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gpll0_out_even.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
.halt_reg = 0x3600c,
.halt_check = BRANCH_VOTED,
.hwcg_reg = 0x3600c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
.halt_reg = 0x36018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x36018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_snoc_dvm_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_throttle_core_clk = {
.halt_reg = 0x36048,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x36048,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(31),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_throttle_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x2000c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2000c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x20004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x20004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x20004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x20008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x21004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x21004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
.halt_reg = 0x17014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_nrt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
.halt_reg = 0x17060,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17060,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_rt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp_ahb_clk = {
.halt_reg = 0x17018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_disp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = {
.halt_reg = 0x36040,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x36040,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_gpu_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
.halt_reg = 0x17010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_vcodec_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
.halt_reg = 0x1f014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_clk = {
.halt_reg = 0x1f00c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.halt_reg = 0x1f144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.halt_reg = 0x1f274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.halt_reg = 0x1f3a4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.halt_reg = 0x1f4d4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.halt_reg = 0x1f604,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.halt_reg = 0x1f734,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
.halt_reg = 0x53014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_clk = {
.halt_reg = 0x5300c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.halt_reg = 0x53018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.halt_reg = 0x53148,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.halt_reg = 0x53278,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.halt_reg = 0x533a8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.halt_reg = 0x534d8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.halt_reg = 0x53608,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
.halt_reg = 0x1f004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1f004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
.halt_reg = 0x1f008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1f008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
.halt_reg = 0x53004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x53004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
.halt_reg = 0x53008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x53008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7900c,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x38008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x38008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x38004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x38004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0x3800c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x3800c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3800c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc1_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x1e008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x1e004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
.halt_reg = 0x2b06c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2b06c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_cpuss_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = {
.halt_reg = 0x45098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x45098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = {
.halt_reg = 0x1a080,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1a080,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1a080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x45014,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x45014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x45014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_clk = {
.halt_reg = 0x45010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x45010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x45010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.halt_reg = 0x45044,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x45044,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x45044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.halt_reg = 0x45078,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x45078,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x45078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.halt_reg = 0x4501c,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x4501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
.halt_reg = 0x45018,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x45018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.halt_reg = 0x45040,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x45040,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x45040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_master_clk = {
.halt_reg = 0x1a010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0x1a018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_sleep_clk = {
.halt_reg = 0x1a014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_mem_clkref_clk = {
.halt_reg = 0x8c000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_mem_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_rx5_pcie_clkref_en_clk = {
.halt_reg = 0x8c00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_rx5_pcie_clkref_en_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_clkref_clk = {
.halt_reg = 0x8c010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.halt_reg = 0x1a054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_reg = 0x1a058,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x1a058,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1a058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_vcodec0_axi_clk = {
.halt_reg = 0x6e008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6e008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_vcodec0_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus_ahb_clk = {
.halt_reg = 0x6e010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6e010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_venus_ctl_axi_clk = {
.halt_reg = 0x6e004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus_ctl_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_ahb_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x17004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi0_clk = {
.halt_reg = 0x1701c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x1701c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1701c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_throttle_core_clk = {
.halt_reg = 0x17068,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17068,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x79004,
.enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_throttle_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_vcodec0_sys_clk = {
.halt_reg = 0x580a4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x580a4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x580a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_vcodec0_sys_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_video_venus_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_venus_ctl_clk = {
.halt_reg = 0x5808c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5808c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_venus_ctl_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_video_venus_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_xo_clk = {
.halt_reg = 0x17024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_xo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc usb30_prim_gdsc = {
.gdscr = 0x1a004,
.pd = {
.name = "usb30_prim_gdsc",
},
/* TODO: Change to OFF_ON when USB drivers get proper suspend support */
.pwrsts = PWRSTS_RET_ON,
};
static struct gdsc ufs_phy_gdsc = {
.gdscr = 0x45004,
.pd = {
.name = "ufs_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc camss_top_gdsc = {
.gdscr = 0x58004,
.pd = {
.name = "camss_top_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc venus_gdsc = {
.gdscr = 0x5807c,
.pd = {
.name = "venus_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc vcodec0_gdsc = {
.gdscr = 0x58098,
.pd = {
.name = "vcodec0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL,
};
static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = {
.gdscr = 0x7d074,
.pd = {
.name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = {
.gdscr = 0x7d078,
.pd = {
.name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
.gdscr = 0x7d060,
.pd = {
.name = "hlos1_vote_turing_mmu_tbu1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
.gdscr = 0x7d07c,
.pd = {
.name = "hlos1_vote_turing_mmu_tbu0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct clk_regmap *gcc_sm6375_clocks[] = {
[GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr,
[GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr,
[GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr,
[GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr,
[GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
[GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr,
[GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr,
[GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr,
[GCC_CAMSS_CCI_0_CLK_SRC] = &gcc_camss_cci_0_clk_src.clkr,
[GCC_CAMSS_CCI_1_CLK] = &gcc_camss_cci_1_clk.clkr,
[GCC_CAMSS_CCI_1_CLK_SRC] = &gcc_camss_cci_1_clk_src.clkr,
[GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr,
[GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr,
[GCC_CAMSS_CPHY_2_CLK] = &gcc_camss_cphy_2_clk.clkr,
[GCC_CAMSS_CPHY_3_CLK] = &gcc_camss_cphy_3_clk.clkr,
[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
[GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr,
[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
[GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr,
[GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr,
[GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr,
[GCC_CAMSS_CSI3PHYTIMER_CLK] = &gcc_camss_csi3phytimer_clk.clkr,
[GCC_CAMSS_CSI3PHYTIMER_CLK_SRC] = &gcc_camss_csi3phytimer_clk_src.clkr,
[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
[GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr,
[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
[GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr,
[GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
[GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr,
[GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr,
[GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr,
[GCC_CAMSS_MCLK4_CLK] = &gcc_camss_mclk4_clk.clkr,
[GCC_CAMSS_MCLK4_CLK_SRC] = &gcc_camss_mclk4_clk_src.clkr,
[GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr,
[GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr,
[GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr,
[GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr,
[GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr,
[GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr,
[GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr,
[GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr,
[GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr,
[GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr,
[GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr,
[GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr,
[GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr,
[GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr,
[GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr,
[GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr,
[GCC_CAMSS_TFE_2_CLK] = &gcc_camss_tfe_2_clk.clkr,
[GCC_CAMSS_TFE_2_CLK_SRC] = &gcc_camss_tfe_2_clk_src.clkr,
[GCC_CAMSS_TFE_2_CPHY_RX_CLK] = &gcc_camss_tfe_2_cphy_rx_clk.clkr,
[GCC_CAMSS_TFE_2_CSID_CLK] = &gcc_camss_tfe_2_csid_clk.clkr,
[GCC_CAMSS_TFE_2_CSID_CLK_SRC] = &gcc_camss_tfe_2_csid_clk_src.clkr,
[GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr,
[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
[GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
[GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr,
[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
[GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
[GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
[GCC_DISP_SLEEP_CLK] = &gcc_disp_sleep_clk.clkr,
[GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
[GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr,
[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
[GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr,
[GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr,
[GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr,
[GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr,
[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
[GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr,
[GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr,
[GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr,
[GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr,
[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
[GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
[GCC_RX5_PCIE_CLKREF_EN_CLK] = &gcc_rx5_pcie_clkref_en_clk.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
[GPLL0_OUT_ODD] = &gpll0_out_odd.clkr,
[GPLL1] = &gpll1.clkr,
[GPLL10] = &gpll10.clkr,
[GPLL11] = &gpll11.clkr,
[GPLL3] = &gpll3.clkr,
[GPLL3_OUT_EVEN] = &gpll3_out_even.clkr,
[GPLL4] = &gpll4.clkr,
[GPLL5] = &gpll5.clkr,
[GPLL6] = &gpll6.clkr,
[GPLL6_OUT_EVEN] = &gpll6_out_even.clkr,
[GPLL7] = &gpll7.clkr,
[GPLL8] = &gpll8.clkr,
[GPLL8_OUT_EVEN] = &gpll8_out_even.clkr,
[GPLL9] = &gpll9.clkr,
[GPLL9_OUT_MAIN] = &gpll9_out_main.clkr,
};
static const struct qcom_reset_map gcc_sm6375_resets[] = {
[GCC_MMSS_BCR] = { 0x17000 },
[GCC_USB30_PRIM_BCR] = { 0x1a000 },
[GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x1b020 },
[GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
[GCC_SDCC2_BCR] = { 0x1e000 },
[GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 },
[GCC_PDM_BCR] = { 0x20000 },
[GCC_GPU_BCR] = { 0x36000 },
[GCC_SDCC1_BCR] = { 0x38000 },
[GCC_UFS_PHY_BCR] = { 0x45000 },
[GCC_CAMSS_TFE_BCR] = { 0x52000 },
[GCC_QUPV3_WRAPPER_1_BCR] = { 0x53000 },
[GCC_CAMSS_OPE_BCR] = { 0x55000 },
[GCC_CAMSS_TOP_BCR] = { 0x58000 },
[GCC_VENUS_BCR] = { 0x58078 },
[GCC_VCODEC0_BCR] = { 0x58094 },
[GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 },
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
};
static struct gdsc *gcc_sm6375_gdscs[] = {
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
[UFS_PHY_GDSC] = &ufs_phy_gdsc,
[CAMSS_TOP_GDSC] = &camss_top_gdsc,
[VENUS_GDSC] = &venus_gdsc,
[VCODEC0_GDSC] = &vcodec0_gdsc,
[HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc,
[HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc,
[HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
[HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
};
static const struct regmap_config gcc_sm6375_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xc7000,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_sm6375_desc = {
.config = &gcc_sm6375_regmap_config,
.clks = gcc_sm6375_clocks,
.num_clks = ARRAY_SIZE(gcc_sm6375_clocks),
.resets = gcc_sm6375_resets,
.num_resets = ARRAY_SIZE(gcc_sm6375_resets),
.gdscs = gcc_sm6375_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sm6375_gdscs),
};
static const struct of_device_id gcc_sm6375_match_table[] = {
{ .compatible = "qcom,sm6375-gcc" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_sm6375_match_table);
static int gcc_sm6375_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sm6375_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
/*
* Keep the following clocks always on:
* GCC_CAMERA_XO_CLK, GCC_CPUSS_GNOC_CLK, GCC_DISP_XO_CLK
*/
regmap_update_bits(regmap, 0x17028, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x2b004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x1702c, BIT(0), BIT(0));
clk_lucid_pll_configure(&gpll10, regmap, &gpll10_config);
clk_lucid_pll_configure(&gpll11, regmap, &gpll11_config);
clk_lucid_pll_configure(&gpll8, regmap, &gpll8_config);
clk_zonda_pll_configure(&gpll9, regmap, &gpll9_config);
return qcom_cc_really_probe(pdev, &gcc_sm6375_desc, regmap);
}
static struct platform_driver gcc_sm6375_driver = {
.probe = gcc_sm6375_probe,
.driver = {
.name = "gcc-sm6375",
.of_match_table = gcc_sm6375_match_table,
},
};
static int __init gcc_sm6375_init(void)
{
return platform_driver_register(&gcc_sm6375_driver);
}
subsys_initcall(gcc_sm6375_init);
static void __exit gcc_sm6375_exit(void)
{
platform_driver_unregister(&gcc_sm6375_driver);
}
module_exit(gcc_sm6375_exit);
MODULE_DESCRIPTION("QTI GCC SM6375 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/gcc-sm6375.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,lpass-sc7280.h>
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_LPASS_AON_CC_PLL_OUT_EVEN,
P_LPASS_AON_CC_PLL_OUT_MAIN,
P_LPASS_AON_CC_PLL_OUT_MAIN_CDIV_DIV_CLK_SRC,
P_LPASS_AON_CC_PLL_OUT_ODD,
P_LPASS_AUDIO_CC_PLL_OUT_AUX,
P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC,
P_LPASS_AUDIO_CC_PLL_MAIN_DIV_CLK,
};
static const struct pll_vco zonda_vco[] = {
{ 595200000UL, 3600000000UL, 0 },
};
static struct clk_branch lpass_q6ss_ahbm_clk = {
.halt_reg = 0x901c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x901c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_q6ss_ahbm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_q6ss_ahbs_clk = {
.halt_reg = 0x9020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "lpass_q6ss_ahbs_clk",
.ops = &clk_branch2_ops,
},
},
};
/* 1128.96MHz configuration */
static const struct alpha_pll_config lpass_audio_cc_pll_config = {
.l = 0x3a,
.alpha = 0xcccc,
.config_ctl_val = 0x08200920,
.config_ctl_hi_val = 0x05002001,
.config_ctl_hi1_val = 0x00000000,
.user_ctl_val = 0x03000101,
};
static struct clk_alpha_pll lpass_audio_cc_pll = {
.offset = 0x0,
.vco_table = zonda_vco,
.num_vco = ARRAY_SIZE(zonda_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "lpass_audio_cc_pll",
.parent_data = &(const struct clk_parent_data){
.index = 0,
},
.num_parents = 1,
.ops = &clk_alpha_pll_zonda_ops,
},
},
};
static const struct clk_div_table post_div_table_lpass_audio_cc_pll_out_aux2[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv lpass_audio_cc_pll_out_aux2 = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_lpass_audio_cc_pll_out_aux2,
.num_post_div = ARRAY_SIZE(post_div_table_lpass_audio_cc_pll_out_aux2),
.width = 2,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
.clkr.hw.init = &(const struct clk_init_data){
.name = "lpass_audio_cc_pll_out_aux2",
.parent_hws = (const struct clk_hw*[]){
&lpass_audio_cc_pll.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_zonda_ops,
},
};
static const struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
/* 614.4 MHz configuration */
static const struct alpha_pll_config lpass_aon_cc_pll_config = {
.l = 0x20,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329A299C,
.user_ctl_val = 0x00005100,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll lpass_aon_cc_pll = {
.offset = 0x0,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "lpass_aon_cc_pll",
.parent_data = &(const struct clk_parent_data){
.index = 0,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct clk_div_table post_div_table_lpass_aon_cc_pll_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv lpass_aon_cc_pll_out_even = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_lpass_aon_cc_pll_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_lpass_aon_cc_pll_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(const struct clk_init_data){
.name = "lpass_aon_cc_pll_out_even",
.parent_hws = (const struct clk_hw*[]){
&lpass_aon_cc_pll.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
static const struct clk_div_table post_div_table_lpass_aon_cc_pll_out_odd[] = {
{ 0x5, 5 },
{ }
};
static struct clk_alpha_pll_postdiv lpass_aon_cc_pll_out_odd = {
.offset = 0x0,
.post_div_shift = 12,
.post_div_table = post_div_table_lpass_aon_cc_pll_out_odd,
.num_post_div = ARRAY_SIZE(post_div_table_lpass_aon_cc_pll_out_odd),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(const struct clk_init_data){
.name = "lpass_aon_cc_pll_out_odd",
.parent_hws = (const struct clk_hw*[]){
&lpass_aon_cc_pll.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
static const struct parent_map lpass_audio_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_LPASS_AUDIO_CC_PLL_OUT_AUX, 3 },
{ P_LPASS_AON_CC_PLL_OUT_ODD, 5 },
{ P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 6 },
};
static struct clk_regmap_div lpass_audio_cc_pll_out_aux2_div_clk_src;
static struct clk_regmap_div lpass_audio_cc_pll_out_main_div_clk_src;
static const struct clk_parent_data lpass_audio_cc_parent_data_0[] = {
{ .index = 0 },
{ .hw = &lpass_audio_cc_pll.clkr.hw },
{ .hw = &lpass_aon_cc_pll_out_odd.clkr.hw },
{ .hw = &lpass_audio_cc_pll_out_aux2_div_clk_src.clkr.hw },
};
static const struct parent_map lpass_aon_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_LPASS_AON_CC_PLL_OUT_EVEN, 4 },
};
static const struct clk_parent_data lpass_aon_cc_parent_data_0[] = {
{ .index = 0 },
{ .hw = &lpass_aon_cc_pll_out_even.clkr.hw },
};
static const struct parent_map lpass_aon_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_LPASS_AON_CC_PLL_OUT_ODD, 1 },
{ P_LPASS_AUDIO_CC_PLL_MAIN_DIV_CLK, 6 },
};
static const struct clk_parent_data lpass_aon_cc_parent_data_1[] = {
{ .index = 0 },
{ .hw = &lpass_aon_cc_pll_out_odd.clkr.hw },
{ .hw = &lpass_audio_cc_pll_out_main_div_clk_src.clkr.hw },
};
static const struct freq_tbl ftbl_lpass_aon_cc_main_rcg_clk_src[] = {
F(38400000, P_LPASS_AON_CC_PLL_OUT_EVEN, 8, 0, 0),
F(76800000, P_LPASS_AON_CC_PLL_OUT_EVEN, 4, 0, 0),
F(153600000, P_LPASS_AON_CC_PLL_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 lpass_aon_cc_main_rcg_clk_src = {
.cmd_rcgr = 0x1000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = lpass_aon_cc_parent_map_0,
.freq_tbl = ftbl_lpass_aon_cc_main_rcg_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "lpass_aon_cc_main_rcg_clk_src",
.parent_data = lpass_aon_cc_parent_data_0,
.num_parents = ARRAY_SIZE(lpass_aon_cc_parent_data_0),
.flags = CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_lpass_aon_cc_tx_mclk_rcg_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24576000, P_LPASS_AON_CC_PLL_OUT_ODD, 5, 0, 0),
{ }
};
static struct clk_rcg2 lpass_aon_cc_tx_mclk_rcg_clk_src = {
.cmd_rcgr = 0x13004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = lpass_aon_cc_parent_map_1,
.freq_tbl = ftbl_lpass_aon_cc_tx_mclk_rcg_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "lpass_aon_cc_tx_mclk_rcg_clk_src",
.parent_data = lpass_aon_cc_parent_data_1,
.num_parents = ARRAY_SIZE(lpass_aon_cc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div lpass_audio_cc_pll_out_aux2_div_clk_src = {
.reg = 0x48,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "lpass_audio_cc_pll_out_aux2_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&lpass_audio_cc_pll_out_aux2.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div lpass_audio_cc_pll_out_main_div_clk_src = {
.reg = 0x3c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "lpass_audio_cc_pll_out_main_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&lpass_audio_cc_pll.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div lpass_aon_cc_cdiv_tx_mclk_div_clk_src = {
.reg = 0x13010,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "lpass_aon_cc_cdiv_tx_mclk_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&lpass_aon_cc_tx_mclk_rcg_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div lpass_aon_cc_pll_out_main_cdiv_div_clk_src = {
.reg = 0x80,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "lpass_aon_cc_pll_out_main_cdiv_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&lpass_aon_cc_pll.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static const struct freq_tbl ftbl_lpass_audio_cc_ext_mclk0_clk_src[] = {
F(256000, P_LPASS_AON_CC_PLL_OUT_ODD, 15, 1, 32),
F(352800, P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 10, 1, 32),
F(512000, P_LPASS_AON_CC_PLL_OUT_ODD, 15, 1, 16),
F(705600, P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 10, 1, 16),
F(768000, P_LPASS_AON_CC_PLL_OUT_ODD, 10, 1, 16),
F(1024000, P_LPASS_AON_CC_PLL_OUT_ODD, 15, 1, 8),
F(1411200, P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 10, 1, 8),
F(1536000, P_LPASS_AON_CC_PLL_OUT_ODD, 10, 1, 8),
F(2048000, P_LPASS_AON_CC_PLL_OUT_ODD, 15, 1, 4),
F(2822400, P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 10, 1, 4),
F(3072000, P_LPASS_AON_CC_PLL_OUT_ODD, 10, 1, 4),
F(4096000, P_LPASS_AON_CC_PLL_OUT_ODD, 15, 1, 2),
F(5644800, P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 10, 1, 2),
F(6144000, P_LPASS_AON_CC_PLL_OUT_ODD, 10, 1, 2),
F(8192000, P_LPASS_AON_CC_PLL_OUT_ODD, 15, 0, 0),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(11289600, P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 10, 0, 0),
F(12288000, P_LPASS_AON_CC_PLL_OUT_ODD, 10, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(22579200, P_LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC, 5, 0, 0),
F(24576000, P_LPASS_AON_CC_PLL_OUT_ODD, 5, 0, 0),
{ }
};
static struct clk_rcg2 lpass_audio_cc_ext_mclk0_clk_src = {
.cmd_rcgr = 0x20004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = lpass_audio_cc_parent_map_0,
.freq_tbl = ftbl_lpass_audio_cc_ext_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "lpass_audio_cc_ext_mclk0_clk_src",
.parent_data = lpass_audio_cc_parent_data_0,
.num_parents = ARRAY_SIZE(lpass_audio_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 lpass_audio_cc_ext_mclk1_clk_src = {
.cmd_rcgr = 0x21004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = lpass_audio_cc_parent_map_0,
.freq_tbl = ftbl_lpass_audio_cc_ext_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "lpass_audio_cc_ext_mclk1_clk_src",
.parent_data = lpass_audio_cc_parent_data_0,
.num_parents = ARRAY_SIZE(lpass_audio_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 lpass_audio_cc_rx_mclk_clk_src = {
.cmd_rcgr = 0x24004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = lpass_audio_cc_parent_map_0,
.freq_tbl = ftbl_lpass_audio_cc_ext_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "lpass_audio_cc_rx_mclk_clk_src",
.parent_data = lpass_audio_cc_parent_data_0,
.num_parents = ARRAY_SIZE(lpass_audio_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div lpass_audio_cc_cdiv_rx_mclk_div_clk_src = {
.reg = 0x240d0,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "lpass_audio_cc_cdiv_rx_mclk_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&lpass_audio_cc_rx_mclk_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch lpass_aon_cc_audio_hm_h_clk;
static struct clk_branch lpass_audio_cc_codec_mem0_clk = {
.halt_reg = 0x1e004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "lpass_audio_cc_codec_mem0_clk",
.parent_hws = (const struct clk_hw*[]){
&lpass_aon_cc_audio_hm_h_clk.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_audio_cc_codec_mem1_clk = {
.halt_reg = 0x1e008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "lpass_audio_cc_codec_mem1_clk",
.parent_hws = (const struct clk_hw*[]){
&lpass_aon_cc_audio_hm_h_clk.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_audio_cc_codec_mem2_clk = {
.halt_reg = 0x1e00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e00c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "lpass_audio_cc_codec_mem2_clk",
.parent_hws = (const struct clk_hw*[]){
&lpass_aon_cc_audio_hm_h_clk.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_audio_cc_codec_mem_clk = {
.halt_reg = 0x1e000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "lpass_audio_cc_codec_mem_clk",
.parent_hws = (const struct clk_hw*[]){
&lpass_aon_cc_audio_hm_h_clk.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_audio_cc_ext_mclk0_clk = {
.halt_reg = 0x20018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "lpass_audio_cc_ext_mclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&lpass_audio_cc_ext_mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_audio_cc_ext_mclk1_clk = {
.halt_reg = 0x21018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x21018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "lpass_audio_cc_ext_mclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&lpass_audio_cc_ext_mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_audio_cc_rx_mclk_2x_clk = {
.halt_reg = 0x240cc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x240cc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "lpass_audio_cc_rx_mclk_2x_clk",
.parent_hws = (const struct clk_hw*[]){
&lpass_audio_cc_rx_mclk_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_audio_cc_rx_mclk_clk = {
.halt_reg = 0x240d4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x240d4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "lpass_audio_cc_rx_mclk_clk",
.parent_hws = (const struct clk_hw*[]){
&lpass_audio_cc_cdiv_rx_mclk_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_aon_cc_audio_hm_h_clk = {
.halt_reg = 0x9014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "lpass_aon_cc_audio_hm_h_clk",
.parent_hws = (const struct clk_hw*[]){
&lpass_aon_cc_main_rcg_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch lpass_aon_cc_va_mem0_clk = {
.halt_reg = 0x9028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "lpass_aon_cc_va_mem0_clk",
.parent_hws = (const struct clk_hw*[]){
&lpass_aon_cc_main_rcg_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_aon_cc_tx_mclk_2x_clk = {
.halt_reg = 0x1300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1300c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "lpass_aon_cc_tx_mclk_2x_clk",
.parent_hws = (const struct clk_hw*[]){
&lpass_aon_cc_tx_mclk_rcg_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch lpass_aon_cc_tx_mclk_clk = {
.halt_reg = 0x13014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x13014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "lpass_aon_cc_tx_mclk_clk",
.parent_hws = (const struct clk_hw*[]){
&lpass_aon_cc_cdiv_tx_mclk_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc lpass_aon_cc_lpass_audio_hm_gdsc = {
.gdscr = 0x9090,
.pd = {
.name = "lpass_aon_cc_lpass_audio_hm_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct clk_regmap *lpass_cc_sc7280_clocks[] = {
[LPASS_Q6SS_AHBM_CLK] = &lpass_q6ss_ahbm_clk.clkr,
[LPASS_Q6SS_AHBS_CLK] = &lpass_q6ss_ahbs_clk.clkr,
};
static struct clk_regmap *lpass_aon_cc_sc7280_clocks[] = {
[LPASS_AON_CC_AUDIO_HM_H_CLK] = &lpass_aon_cc_audio_hm_h_clk.clkr,
[LPASS_AON_CC_VA_MEM0_CLK] = &lpass_aon_cc_va_mem0_clk.clkr,
[LPASS_AON_CC_CDIV_TX_MCLK_DIV_CLK_SRC] = &lpass_aon_cc_cdiv_tx_mclk_div_clk_src.clkr,
[LPASS_AON_CC_MAIN_RCG_CLK_SRC] = &lpass_aon_cc_main_rcg_clk_src.clkr,
[LPASS_AON_CC_PLL] = &lpass_aon_cc_pll.clkr,
[LPASS_AON_CC_PLL_OUT_EVEN] = &lpass_aon_cc_pll_out_even.clkr,
[LPASS_AON_CC_PLL_OUT_MAIN_CDIV_DIV_CLK_SRC] =
&lpass_aon_cc_pll_out_main_cdiv_div_clk_src.clkr,
[LPASS_AON_CC_PLL_OUT_ODD] = &lpass_aon_cc_pll_out_odd.clkr,
[LPASS_AON_CC_TX_MCLK_2X_CLK] = &lpass_aon_cc_tx_mclk_2x_clk.clkr,
[LPASS_AON_CC_TX_MCLK_CLK] = &lpass_aon_cc_tx_mclk_clk.clkr,
[LPASS_AON_CC_TX_MCLK_RCG_CLK_SRC] = &lpass_aon_cc_tx_mclk_rcg_clk_src.clkr,
};
static struct gdsc *lpass_aon_cc_sc7280_gdscs[] = {
[LPASS_AON_CC_LPASS_AUDIO_HM_GDSC] = &lpass_aon_cc_lpass_audio_hm_gdsc,
};
static struct clk_regmap *lpass_audio_cc_sc7280_clocks[] = {
[LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC] = &lpass_audio_cc_cdiv_rx_mclk_div_clk_src.clkr,
[LPASS_AUDIO_CC_CODEC_MEM0_CLK] = &lpass_audio_cc_codec_mem0_clk.clkr,
[LPASS_AUDIO_CC_CODEC_MEM1_CLK] = &lpass_audio_cc_codec_mem1_clk.clkr,
[LPASS_AUDIO_CC_CODEC_MEM2_CLK] = &lpass_audio_cc_codec_mem2_clk.clkr,
[LPASS_AUDIO_CC_CODEC_MEM_CLK] = &lpass_audio_cc_codec_mem_clk.clkr,
[LPASS_AUDIO_CC_EXT_MCLK0_CLK] = &lpass_audio_cc_ext_mclk0_clk.clkr,
[LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC] = &lpass_audio_cc_ext_mclk0_clk_src.clkr,
[LPASS_AUDIO_CC_EXT_MCLK1_CLK] = &lpass_audio_cc_ext_mclk1_clk.clkr,
[LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC] = &lpass_audio_cc_ext_mclk1_clk_src.clkr,
[LPASS_AUDIO_CC_PLL] = &lpass_audio_cc_pll.clkr,
[LPASS_AUDIO_CC_PLL_OUT_AUX2] = &lpass_audio_cc_pll_out_aux2.clkr,
[LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC] = &lpass_audio_cc_pll_out_aux2_div_clk_src.clkr,
[LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC] = &lpass_audio_cc_pll_out_main_div_clk_src.clkr,
[LPASS_AUDIO_CC_RX_MCLK_2X_CLK] = &lpass_audio_cc_rx_mclk_2x_clk.clkr,
[LPASS_AUDIO_CC_RX_MCLK_CLK] = &lpass_audio_cc_rx_mclk_clk.clkr,
[LPASS_AUDIO_CC_RX_MCLK_CLK_SRC] = &lpass_audio_cc_rx_mclk_clk_src.clkr,
};
static struct regmap_config lpass_audio_cc_sc7280_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.fast_io = true,
};
static const struct qcom_cc_desc lpass_cc_sc7280_desc = {
.config = &lpass_audio_cc_sc7280_regmap_config,
.clks = lpass_cc_sc7280_clocks,
.num_clks = ARRAY_SIZE(lpass_cc_sc7280_clocks),
.gdscs = lpass_aon_cc_sc7280_gdscs,
.num_gdscs = ARRAY_SIZE(lpass_aon_cc_sc7280_gdscs),
};
static const struct qcom_cc_desc lpass_audio_cc_sc7280_desc = {
.config = &lpass_audio_cc_sc7280_regmap_config,
.clks = lpass_audio_cc_sc7280_clocks,
.num_clks = ARRAY_SIZE(lpass_audio_cc_sc7280_clocks),
};
static const struct qcom_reset_map lpass_audio_cc_sc7280_resets[] = {
[LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
[LPASS_AUDIO_SWR_TX_CGCR] = { 0xa8, 1 },
[LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
};
static const struct qcom_cc_desc lpass_audio_cc_reset_sc7280_desc = {
.config = &lpass_audio_cc_sc7280_regmap_config,
.resets = lpass_audio_cc_sc7280_resets,
.num_resets = ARRAY_SIZE(lpass_audio_cc_sc7280_resets),
};
static const struct of_device_id lpass_audio_cc_sc7280_match_table[] = {
{ .compatible = "qcom,sc7280-lpassaudiocc" },
{ }
};
MODULE_DEVICE_TABLE(of, lpass_audio_cc_sc7280_match_table);
static int lpass_audio_setup_runtime_pm(struct platform_device *pdev)
{
int ret;
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = devm_pm_clk_create(&pdev->dev);
if (ret)
return ret;
ret = pm_clk_add(&pdev->dev, "iface");
if (ret < 0)
dev_err(&pdev->dev, "failed to acquire iface clock\n");
return pm_runtime_resume_and_get(&pdev->dev);
}
static int lpass_audio_cc_sc7280_probe(struct platform_device *pdev)
{
const struct qcom_cc_desc *desc;
struct regmap *regmap;
int ret;
ret = lpass_audio_setup_runtime_pm(pdev);
if (ret)
return ret;
lpass_audio_cc_sc7280_regmap_config.name = "lpassaudio_cc";
lpass_audio_cc_sc7280_regmap_config.max_register = 0x2f000;
desc = &lpass_audio_cc_sc7280_desc;
regmap = qcom_cc_map(pdev, desc);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
goto exit;
}
clk_zonda_pll_configure(&lpass_audio_cc_pll, regmap, &lpass_audio_cc_pll_config);
/* PLL settings */
regmap_write(regmap, 0x4, 0x3b);
regmap_write(regmap, 0x8, 0xff05);
ret = qcom_cc_really_probe(pdev, &lpass_audio_cc_sc7280_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC clocks\n");
goto exit;
}
ret = qcom_cc_probe_by_index(pdev, 1, &lpass_audio_cc_reset_sc7280_desc);
if (ret) {
dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC Resets\n");
goto exit;
}
pm_runtime_mark_last_busy(&pdev->dev);
exit:
pm_runtime_put_autosuspend(&pdev->dev);
return ret;
}
static const struct dev_pm_ops lpass_audio_cc_pm_ops = {
SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
};
static struct platform_driver lpass_audio_cc_sc7280_driver = {
.probe = lpass_audio_cc_sc7280_probe,
.driver = {
.name = "lpass_audio_cc-sc7280",
.of_match_table = lpass_audio_cc_sc7280_match_table,
.pm = &lpass_audio_cc_pm_ops,
},
};
static const struct qcom_cc_desc lpass_aon_cc_sc7280_desc = {
.config = &lpass_audio_cc_sc7280_regmap_config,
.clks = lpass_aon_cc_sc7280_clocks,
.num_clks = ARRAY_SIZE(lpass_aon_cc_sc7280_clocks),
.gdscs = lpass_aon_cc_sc7280_gdscs,
.num_gdscs = ARRAY_SIZE(lpass_aon_cc_sc7280_gdscs),
};
static const struct of_device_id lpass_aon_cc_sc7280_match_table[] = {
{ .compatible = "qcom,sc7280-lpassaoncc" },
{ }
};
MODULE_DEVICE_TABLE(of, lpass_aon_cc_sc7280_match_table);
static int lpass_aon_cc_sc7280_probe(struct platform_device *pdev)
{
const struct qcom_cc_desc *desc;
struct regmap *regmap;
int ret;
ret = lpass_audio_setup_runtime_pm(pdev);
if (ret)
return ret;
if (of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) {
lpass_audio_cc_sc7280_regmap_config.name = "cc";
desc = &lpass_cc_sc7280_desc;
ret = qcom_cc_probe(pdev, desc);
goto exit;
}
lpass_audio_cc_sc7280_regmap_config.name = "lpasscc_aon";
lpass_audio_cc_sc7280_regmap_config.max_register = 0xa0008;
desc = &lpass_aon_cc_sc7280_desc;
regmap = qcom_cc_map(pdev, desc);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
goto exit;
}
clk_lucid_pll_configure(&lpass_aon_cc_pll, regmap, &lpass_aon_cc_pll_config);
ret = qcom_cc_really_probe(pdev, &lpass_aon_cc_sc7280_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register LPASS AON CC clocks\n");
goto exit;
}
pm_runtime_mark_last_busy(&pdev->dev);
exit:
pm_runtime_put_autosuspend(&pdev->dev);
return ret;
}
static struct platform_driver lpass_aon_cc_sc7280_driver = {
.probe = lpass_aon_cc_sc7280_probe,
.driver = {
.name = "lpass_aon_cc-sc7280",
.of_match_table = lpass_aon_cc_sc7280_match_table,
.pm = &lpass_audio_cc_pm_ops,
},
};
static int __init lpass_audio_cc_sc7280_init(void)
{
int ret;
ret = platform_driver_register(&lpass_aon_cc_sc7280_driver);
if (ret)
return ret;
return platform_driver_register(&lpass_audio_cc_sc7280_driver);
}
subsys_initcall(lpass_audio_cc_sc7280_init);
static void __exit lpass_audio_cc_sc7280_exit(void)
{
platform_driver_unregister(&lpass_audio_cc_sc7280_driver);
platform_driver_unregister(&lpass_aon_cc_sc7280_driver);
}
module_exit(lpass_audio_cc_sc7280_exit);
MODULE_DESCRIPTION("QTI LPASS_AUDIO_CC SC7280 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/lpassaudiocc-sc7280.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*/
#include <linux/device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/export.h>
#include "clk-regmap.h"
/**
* clk_is_enabled_regmap - standard is_enabled() for regmap users
*
* @hw: clk to operate on
*
* Clocks that use regmap for their register I/O can set the
* enable_reg and enable_mask fields in their struct clk_regmap and then use
* this as their is_enabled operation, saving some code.
*/
int clk_is_enabled_regmap(struct clk_hw *hw)
{
struct clk_regmap *rclk = to_clk_regmap(hw);
unsigned int val;
int ret;
ret = regmap_read(rclk->regmap, rclk->enable_reg, &val);
if (ret != 0)
return ret;
if (rclk->enable_is_inverted)
return (val & rclk->enable_mask) == 0;
else
return (val & rclk->enable_mask) != 0;
}
EXPORT_SYMBOL_GPL(clk_is_enabled_regmap);
/**
* clk_enable_regmap - standard enable() for regmap users
*
* @hw: clk to operate on
*
* Clocks that use regmap for their register I/O can set the
* enable_reg and enable_mask fields in their struct clk_regmap and then use
* this as their enable() operation, saving some code.
*/
int clk_enable_regmap(struct clk_hw *hw)
{
struct clk_regmap *rclk = to_clk_regmap(hw);
unsigned int val;
if (rclk->enable_is_inverted)
val = 0;
else
val = rclk->enable_mask;
return regmap_update_bits(rclk->regmap, rclk->enable_reg,
rclk->enable_mask, val);
}
EXPORT_SYMBOL_GPL(clk_enable_regmap);
/**
* clk_disable_regmap - standard disable() for regmap users
*
* @hw: clk to operate on
*
* Clocks that use regmap for their register I/O can set the
* enable_reg and enable_mask fields in their struct clk_regmap and then use
* this as their disable() operation, saving some code.
*/
void clk_disable_regmap(struct clk_hw *hw)
{
struct clk_regmap *rclk = to_clk_regmap(hw);
unsigned int val;
if (rclk->enable_is_inverted)
val = rclk->enable_mask;
else
val = 0;
regmap_update_bits(rclk->regmap, rclk->enable_reg, rclk->enable_mask,
val);
}
EXPORT_SYMBOL_GPL(clk_disable_regmap);
/**
* devm_clk_register_regmap - register a clk_regmap clock
*
* @dev: reference to the caller's device
* @rclk: clk to operate on
*
* Clocks that use regmap for their register I/O should register their
* clk_regmap struct via this function so that the regmap is initialized
* and so that the clock is registered with the common clock framework.
*/
int devm_clk_register_regmap(struct device *dev, struct clk_regmap *rclk)
{
if (dev && dev_get_regmap(dev, NULL))
rclk->regmap = dev_get_regmap(dev, NULL);
else if (dev && dev->parent)
rclk->regmap = dev_get_regmap(dev->parent, NULL);
return devm_clk_hw_register(dev, &rclk->hw);
}
EXPORT_SYMBOL_GPL(devm_clk_register_regmap);
| linux-master | drivers/clk/qcom/clk-regmap.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,mss-sc7180.h>
#include "clk-regmap.h"
#include "clk-branch.h"
#include "common.h"
static struct clk_branch mss_axi_nav_clk = {
.halt_reg = 0x20bc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20bc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mss_axi_nav_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "gcc_mss_nav_axi",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mss_axi_crypto_clk = {
.halt_reg = 0x20cc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20cc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mss_axi_crypto_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "gcc_mss_mfab_axis",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static const struct regmap_config mss_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.fast_io = true,
.max_register = 0x41aa0cc,
};
static struct clk_regmap *mss_sc7180_clocks[] = {
[MSS_AXI_CRYPTO_CLK] = &mss_axi_crypto_clk.clkr,
[MSS_AXI_NAV_CLK] = &mss_axi_nav_clk.clkr,
};
static const struct qcom_cc_desc mss_sc7180_desc = {
.config = &mss_regmap_config,
.clks = mss_sc7180_clocks,
.num_clks = ARRAY_SIZE(mss_sc7180_clocks),
};
static int mss_sc7180_probe(struct platform_device *pdev)
{
int ret;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = devm_pm_clk_create(&pdev->dev);
if (ret)
return ret;
ret = pm_clk_add(&pdev->dev, "cfg_ahb");
if (ret < 0) {
dev_err(&pdev->dev, "failed to acquire iface clock\n");
return ret;
}
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
ret = qcom_cc_probe(pdev, &mss_sc7180_desc);
if (ret < 0)
goto err_put_rpm;
pm_runtime_put(&pdev->dev);
return 0;
err_put_rpm:
pm_runtime_put_sync(&pdev->dev);
return ret;
}
static const struct dev_pm_ops mss_sc7180_pm_ops = {
SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
};
static const struct of_device_id mss_sc7180_match_table[] = {
{ .compatible = "qcom,sc7180-mss" },
{ }
};
MODULE_DEVICE_TABLE(of, mss_sc7180_match_table);
static struct platform_driver mss_sc7180_driver = {
.probe = mss_sc7180_probe,
.driver = {
.name = "sc7180-mss",
.of_match_table = mss_sc7180_match_table,
.pm = &mss_sc7180_pm_ops,
},
};
static int __init mss_sc7180_init(void)
{
return platform_driver_register(&mss_sc7180_driver);
}
subsys_initcall(mss_sc7180_init);
static void __exit mss_sc7180_exit(void)
{
platform_driver_unregister(&mss_sc7180_driver);
}
module_exit(mss_sc7180_exit);
MODULE_DESCRIPTION("QTI MSS SC7180 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/mss-sc7180.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gpucc-sm8250.h>
#include "common.h"
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "reset.h"
#include "gdsc.h"
#define CX_GMU_CBCR_SLEEP_MASK 0xf
#define CX_GMU_CBCR_SLEEP_SHIFT 4
#define CX_GMU_CBCR_WAKE_MASK 0xf
#define CX_GMU_CBCR_WAKE_SHIFT 8
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL1_OUT_MAIN,
};
static struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
static const struct alpha_pll_config gpu_cc_pll1_config = {
.l = 0x1a,
.alpha = 0xaaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x029a699c,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x100,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .fw_name = "gcc_gpu_gpll0_clk_src" },
{ .fw_name = "gcc_gpu_gpll0_div_clk_src" },
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x1120,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x1078,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x107c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x107c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_crc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_apb_clk = {
.halt_reg = 0x1088,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_apb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x1098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
.halt_reg = 0x108c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x108c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_snoc_dvm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_aon_clk = {
.halt_reg = 0x1004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_aon_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x109c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x109c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gmu_clk = {
.halt_reg = 0x1064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
.halt_reg = 0x5000,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x5000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x106c,
.gds_hw_ctrl = 0x1540,
.pd = {
.name = "gpu_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x100c,
.clamp_io_ctrl = 0x1508,
.pd = {
.name = "gpu_gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
};
static struct clk_regmap *gpu_cc_sm8250_clocks[] = {
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
};
static const struct qcom_reset_map gpu_cc_sm8250_resets[] = {
[GPUCC_GPU_CC_ACD_BCR] = { 0x1160 },
[GPUCC_GPU_CC_CX_BCR] = { 0x1068 },
[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 },
[GPUCC_GPU_CC_GMU_BCR] = { 0x111c },
[GPUCC_GPU_CC_GX_BCR] = { 0x1008 },
[GPUCC_GPU_CC_XO_BCR] = { 0x1000 },
};
static struct gdsc *gpu_cc_sm8250_gdscs[] = {
[GPU_CX_GDSC] = &gpu_cx_gdsc,
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
static const struct regmap_config gpu_cc_sm8250_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x8008,
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_sm8250_desc = {
.config = &gpu_cc_sm8250_regmap_config,
.clks = gpu_cc_sm8250_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sm8250_clocks),
.resets = gpu_cc_sm8250_resets,
.num_resets = ARRAY_SIZE(gpu_cc_sm8250_resets),
.gdscs = gpu_cc_sm8250_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sm8250_gdscs),
};
static const struct of_device_id gpu_cc_sm8250_match_table[] = {
{ .compatible = "qcom,sm8250-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sm8250_match_table);
static int gpu_cc_sm8250_probe(struct platform_device *pdev)
{
struct regmap *regmap;
unsigned int value, mask;
regmap = qcom_cc_map(pdev, &gpu_cc_sm8250_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
/*
* Configure gpu_cc_cx_gmu_clk with recommended
* wakeup/sleep settings
*/
mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
regmap_update_bits(regmap, 0x1098, mask, value);
return qcom_cc_really_probe(pdev, &gpu_cc_sm8250_desc, regmap);
}
static struct platform_driver gpu_cc_sm8250_driver = {
.probe = gpu_cc_sm8250_probe,
.driver = {
.name = "sm8250-gpucc",
.of_match_table = gpu_cc_sm8250_match_table,
},
};
static int __init gpu_cc_sm8250_init(void)
{
return platform_driver_register(&gpu_cc_sm8250_driver);
}
subsys_initcall(gpu_cc_sm8250_init);
static void __exit gpu_cc_sm8250_exit(void)
{
platform_driver_unregister(&gpu_cc_sm8250_driver);
}
module_exit(gpu_cc_sm8250_exit);
MODULE_DESCRIPTION("QTI GPU_CC SM8250 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gpucc-sm8250.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-ipq6018.h>
#include <dt-bindings/reset/qcom,gcc-ipq6018.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "clk-alpha-pll.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "reset.h"
enum {
P_XO,
P_BIAS_PLL,
P_UNIPHY0_RX,
P_UNIPHY0_TX,
P_UNIPHY1_RX,
P_BIAS_PLL_NSS_NOC,
P_UNIPHY1_TX,
P_PCIE20_PHY0_PIPE,
P_USB3PHY_0_PIPE,
P_GPLL0,
P_GPLL0_DIV2,
P_GPLL2,
P_GPLL4,
P_GPLL6,
P_SLEEP_CLK,
P_UBI32_PLL,
P_NSS_CRYPTO_PLL,
P_PI_SLEEP,
};
static struct clk_alpha_pll gpll0_main = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_main",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_fixed_factor gpll0_out_main_div2 = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "gpll0_out_main_div2",
.parent_hws = (const struct clk_hw *[]){
&gpll0_main.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_hws = (const struct clk_hw *[]){
&gpll0_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw},
{ .hw = &gpll0_out_main_div2.hw},
};
static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL0_DIV2, 4 },
};
static struct clk_alpha_pll ubi32_pll_main = {
.offset = 0x25000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "ubi32_pll_main",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_huayra_ops,
},
},
};
static struct clk_alpha_pll_postdiv ubi32_pll = {
.offset = 0x25000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
.width = 2,
.clkr.hw.init = &(struct clk_init_data){
.name = "ubi32_pll",
.parent_hws = (const struct clk_hw *[]){
&ubi32_pll_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll gpll6_main = {
.offset = 0x37000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gpll6_main",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll6 = {
.offset = 0x37000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
.width = 2,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll6",
.parent_hws = (const struct clk_hw *[]){
&gpll6_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll gpll4_main = {
.offset = 0x24000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gpll4_main",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x24000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_hws = (const struct clk_hw *[]){
&gpll4_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
.cmd_rcgr = 0x27000,
.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcnoc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static struct clk_alpha_pll gpll2_main = {
.offset = 0x4a000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gpll2_main",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll2 = {
.offset = 0x4a000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll2",
.parent_hws = (const struct clk_hw *[]){
&gpll2_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_alpha_pll nss_crypto_pll_main = {
.offset = 0x22000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "nss_crypto_pll_main",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll_postdiv nss_crypto_pll = {
.offset = 0x22000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_crypto_pll",
.parent_hws = (const struct clk_hw *[]){
&nss_crypto_pll_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
F(320000000, P_GPLL0, 2.5, 0, 0),
F(600000000, P_GPLL4, 2, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll6_gpll0_div2[] = {
{ .fw_name = "xo" },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
};
static const struct parent_map gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map[] = {
{ P_XO, 0 },
{ P_GPLL4, 1 },
{ P_GPLL0, 2 },
{ P_GPLL6, 3 },
{ P_GPLL0_DIV2, 4 },
};
static struct clk_rcg2 qdss_tsctr_clk_src = {
.cmd_rcgr = 0x29064,
.freq_tbl = ftbl_qdss_tsctr_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "qdss_tsctr_clk_src",
.parent_data = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2,
.num_parents = 5,
.ops = &clk_rcg2_ops,
},
};
static struct clk_fixed_factor qdss_dap_sync_clk_src = {
.mult = 1,
.div = 4,
.hw.init = &(struct clk_init_data){
.name = "qdss_dap_sync_clk_src",
.parent_hws = (const struct clk_hw *[]){
&qdss_tsctr_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
F(66670000, P_GPLL0_DIV2, 6, 0, 0),
F(240000000, P_GPLL4, 5, 0, 0),
{ }
};
static struct clk_rcg2 qdss_at_clk_src = {
.cmd_rcgr = 0x2900c,
.freq_tbl = ftbl_qdss_at_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "qdss_at_clk_src",
.parent_data = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2,
.num_parents = 5,
.ops = &clk_rcg2_ops,
},
};
static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "qdss_tsctr_div2_clk_src",
.parent_hws = (const struct clk_hw *[]){
&qdss_tsctr_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_fixed_factor_ops,
},
};
static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(300000000, P_BIAS_PLL, 1, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
{ .fw_name = "xo" },
{ .fw_name = "bias_pll_cc_clk" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &nss_crypto_pll.clkr.hw },
{ .hw = &ubi32_pll.clkr.hw },
};
static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
{ P_XO, 0 },
{ P_BIAS_PLL, 1 },
{ P_GPLL0, 2 },
{ P_GPLL4, 3 },
{ P_NSS_CRYPTO_PLL, 4 },
{ P_UBI32_PLL, 5 },
};
static struct clk_rcg2 nss_ppe_clk_src = {
.cmd_rcgr = 0x68080,
.freq_tbl = ftbl_nss_ppe_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_ppe_clk_src",
.parent_data = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
.num_parents = 6,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_xo_clk_src = {
.halt_reg = 0x30018,
.clkr = {
.enable_reg = 0x30018,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_xo_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_nss_ce_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_gpll0[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
};
static struct clk_rcg2 nss_ce_clk_src = {
.cmd_rcgr = 0x68098,
.freq_tbl = ftbl_nss_ce_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_ce_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_sleep_clk_src = {
.halt_reg = 0x30000,
.clkr = {
.enable_reg = 0x30000,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_sleep_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep_clk",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_snoc_nssnoc_bfdcd_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0_DIV2, 8, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(133333333, P_GPLL0, 6, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266666667, P_GPLL0, 3, 0, 0),
{ }
};
static const struct clk_parent_data
gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 2 },
{ P_GPLL0_DIV2, 3 },
};
static struct clk_rcg2 snoc_nssnoc_bfdcd_clk_src = {
.cmd_rcgr = 0x76054,
.freq_tbl = ftbl_snoc_nssnoc_bfdcd_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "snoc_nssnoc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
.num_parents = 4,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0_DIV2, 16, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 apss_ahb_clk_src = {
.cmd_rcgr = 0x46000,
.freq_tbl = ftbl_apss_ahb_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "apss_ahb_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
F(25000000, P_UNIPHY0_RX, 5, 0, 0),
F(78125000, P_UNIPHY1_RX, 4, 0, 0),
F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
F(125000000, P_UNIPHY0_RX, 1, 0, 0),
F(156250000, P_UNIPHY1_RX, 2, 0, 0),
F(312500000, P_UNIPHY1_RX, 1, 0, 0),
{ }
};
static const struct clk_parent_data
gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
{ .fw_name = "xo" },
{ .fw_name = "uniphy0_gcc_rx_clk" },
{ .fw_name = "uniphy0_gcc_tx_clk" },
{ .fw_name = "uniphy1_gcc_rx_clk" },
{ .fw_name = "uniphy1_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
{ .fw_name = "bias_pll_cc_clk" },
};
static const struct parent_map
gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
{ P_XO, 0 },
{ P_UNIPHY0_RX, 1 },
{ P_UNIPHY0_TX, 2 },
{ P_UNIPHY1_RX, 3 },
{ P_UNIPHY1_TX, 4 },
{ P_UBI32_PLL, 5 },
{ P_BIAS_PLL, 6 },
};
static struct clk_rcg2 nss_port5_rx_clk_src = {
.cmd_rcgr = 0x68060,
.freq_tbl = ftbl_nss_port5_rx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port5_rx_clk_src",
.parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
.num_parents = 7,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
F(25000000, P_UNIPHY0_TX, 5, 0, 0),
F(78125000, P_UNIPHY1_TX, 4, 0, 0),
F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
F(125000000, P_UNIPHY0_TX, 1, 0, 0),
F(156250000, P_UNIPHY1_TX, 2, 0, 0),
F(312500000, P_UNIPHY1_TX, 1, 0, 0),
{ }
};
static const struct clk_parent_data
gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
{ .fw_name = "xo" },
{ .fw_name = "uniphy0_gcc_tx_clk" },
{ .fw_name = "uniphy0_gcc_rx_clk" },
{ .fw_name = "uniphy1_gcc_tx_clk" },
{ .fw_name = "uniphy1_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
{ .fw_name = "bias_pll_cc_clk" },
};
static const struct parent_map
gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
{ P_XO, 0 },
{ P_UNIPHY0_TX, 1 },
{ P_UNIPHY0_RX, 2 },
{ P_UNIPHY1_TX, 3 },
{ P_UNIPHY1_RX, 4 },
{ P_UBI32_PLL, 5 },
{ P_BIAS_PLL, 6 },
};
static struct clk_rcg2 nss_port5_tx_clk_src = {
.cmd_rcgr = 0x68068,
.freq_tbl = ftbl_nss_port5_tx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port5_tx_clk_src",
.parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
.num_parents = 7,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(240000000, P_GPLL4, 5, 0, 0),
{ }
};
static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 2 },
};
static struct clk_rcg2 pcie0_axi_clk_src = {
.cmd_rcgr = 0x75054,
.freq_tbl = ftbl_pcie_axi_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie0_axi_clk_src",
.parent_data = gcc_xo_gpll0_gpll4,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb0_master_clk_src[] = {
F(80000000, P_GPLL0_DIV2, 5, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(133330000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0_out_main_div2.hw },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0_DIV2, 2 },
{ P_GPLL0, 1 },
};
static struct clk_rcg2 usb0_master_clk_src = {
.cmd_rcgr = 0x3e00c,
.freq_tbl = ftbl_usb0_master_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb0_master_clk_src",
.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div apss_ahb_postdiv_clk_src = {
.reg = 0x46018,
.shift = 4,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "apss_ahb_postdiv_clk_src",
.parent_hws = (const struct clk_hw *[]){
&apss_ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
},
};
static struct clk_fixed_factor gcc_xo_div4_clk_src = {
.mult = 1,
.div = 4,
.hw.init = &(struct clk_init_data){
.name = "gcc_xo_div4_clk_src",
.parent_hws = (const struct clk_hw *[]){
&gcc_xo_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(25000000, P_UNIPHY0_RX, 5, 0, 0),
F(125000000, P_UNIPHY0_RX, 1, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
{ .fw_name = "xo" },
{ .fw_name = "uniphy0_gcc_rx_clk" },
{ .fw_name = "uniphy0_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
{ .fw_name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
{ P_XO, 0 },
{ P_UNIPHY0_RX, 1 },
{ P_UNIPHY0_TX, 2 },
{ P_UBI32_PLL, 5 },
{ P_BIAS_PLL, 6 },
};
static struct clk_rcg2 nss_port1_rx_clk_src = {
.cmd_rcgr = 0x68020,
.freq_tbl = ftbl_nss_port1_rx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port1_rx_clk_src",
.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
.num_parents = 5,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(25000000, P_UNIPHY0_TX, 5, 0, 0),
F(125000000, P_UNIPHY0_TX, 1, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
{ .fw_name = "xo" },
{ .fw_name = "uniphy0_gcc_tx_clk" },
{ .fw_name = "uniphy0_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
{ .fw_name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
{ P_XO, 0 },
{ P_UNIPHY0_TX, 1 },
{ P_UNIPHY0_RX, 2 },
{ P_UBI32_PLL, 5 },
{ P_BIAS_PLL, 6 },
};
static struct clk_rcg2 nss_port1_tx_clk_src = {
.cmd_rcgr = 0x68028,
.freq_tbl = ftbl_nss_port1_tx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port1_tx_clk_src",
.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
.num_parents = 5,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 nss_port2_rx_clk_src = {
.cmd_rcgr = 0x68030,
.freq_tbl = ftbl_nss_port1_rx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port2_rx_clk_src",
.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
.num_parents = 5,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 nss_port2_tx_clk_src = {
.cmd_rcgr = 0x68038,
.freq_tbl = ftbl_nss_port1_tx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port2_tx_clk_src",
.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
.num_parents = 5,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 nss_port3_rx_clk_src = {
.cmd_rcgr = 0x68040,
.freq_tbl = ftbl_nss_port1_rx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port3_rx_clk_src",
.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
.num_parents = 5,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 nss_port3_tx_clk_src = {
.cmd_rcgr = 0x68048,
.freq_tbl = ftbl_nss_port1_tx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port3_tx_clk_src",
.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
.num_parents = 5,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 nss_port4_rx_clk_src = {
.cmd_rcgr = 0x68050,
.freq_tbl = ftbl_nss_port1_rx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port4_rx_clk_src",
.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
.num_parents = 5,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 nss_port4_tx_clk_src = {
.cmd_rcgr = 0x68058,
.freq_tbl = ftbl_nss_port1_tx_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port4_tx_clk_src",
.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
.num_parents = 5,
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div nss_port5_rx_div_clk_src = {
.reg = 0x68440,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port5_rx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port5_rx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_regmap_div nss_port5_tx_div_clk_src = {
.reg = 0x68444,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port5_tx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port5_tx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0_DIV2, 4, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(308570000, P_GPLL6, 3.5, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
F(533000000, P_GPLL0, 1.5, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_gpll0_gpll6_ubi32_gpll0_div2[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &ubi32_pll.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
};
static const struct parent_map
gcc_xo_gpll0_gpll6_ubi32_gpll0_div2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 2 },
{ P_UBI32_PLL, 3 },
{ P_GPLL0_DIV2, 6 },
};
static struct clk_rcg2 apss_axi_clk_src = {
.cmd_rcgr = 0x38048,
.freq_tbl = ftbl_apss_axi_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll6_ubi32_gpll0_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "apss_axi_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_ubi32_gpll0_div2,
.num_parents = 5,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_nss_crypto_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(300000000, P_NSS_CRYPTO_PLL, 2, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_nss_crypto_pll_gpll0[] = {
{ .fw_name = "xo" },
{ .hw = &nss_crypto_pll.clkr.hw },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
{ P_XO, 0 },
{ P_NSS_CRYPTO_PLL, 1 },
{ P_GPLL0, 2 },
};
static struct clk_rcg2 nss_crypto_clk_src = {
.cmd_rcgr = 0x68144,
.freq_tbl = ftbl_nss_crypto_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_crypto_clk_src",
.parent_data = gcc_xo_nss_crypto_pll_gpll0,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div nss_port1_rx_div_clk_src = {
.reg = 0x68400,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port1_rx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port1_rx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_regmap_div nss_port1_tx_div_clk_src = {
.reg = 0x68404,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port1_tx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port1_tx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_regmap_div nss_port2_rx_div_clk_src = {
.reg = 0x68410,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port2_rx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port2_rx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_regmap_div nss_port2_tx_div_clk_src = {
.reg = 0x68414,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port2_tx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port2_tx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_regmap_div nss_port3_rx_div_clk_src = {
.reg = 0x68420,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port3_rx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port3_rx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_regmap_div nss_port3_tx_div_clk_src = {
.reg = 0x68424,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port3_tx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port3_tx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_regmap_div nss_port4_rx_div_clk_src = {
.reg = 0x68430,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port4_rx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port4_rx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_regmap_div nss_port4_tx_div_clk_src = {
.reg = 0x68434,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port4_tx_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_port4_tx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_nss_ubi_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(149760000, P_UBI32_PLL, 10, 0, 0),
F(187200000, P_UBI32_PLL, 8, 0, 0),
F(249600000, P_UBI32_PLL, 6, 0, 0),
F(374400000, P_UBI32_PLL, 4, 0, 0),
F(748800000, P_UBI32_PLL, 2, 0, 0),
F(1497600000, P_UBI32_PLL, 1, 0, 0),
{ }
};
static const struct clk_parent_data
gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
{ .fw_name = "xo" },
{ .hw = &ubi32_pll.clkr.hw },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll6.clkr.hw },
};
static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
{ P_XO, 0 },
{ P_UBI32_PLL, 1 },
{ P_GPLL0, 2 },
{ P_GPLL2, 3 },
{ P_GPLL4, 4 },
{ P_GPLL6, 5 },
};
static struct clk_rcg2 nss_ubi0_clk_src = {
.cmd_rcgr = 0x68104,
.freq_tbl = ftbl_nss_ubi_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_ubi0_clk_src",
.parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
.num_parents = 6,
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 adss_pwm_clk_src = {
.cmd_rcgr = 0x1c008,
.freq_tbl = ftbl_adss_pwm_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "adss_pwm_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0_DIV2, 16, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x0200c,
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 2, 5),
F(4800000, P_XO, 5, 0, 0),
F(9600000, P_XO, 2, 4, 5),
F(12500000, P_GPLL0_DIV2, 16, 1, 2),
F(16000000, P_GPLL0, 10, 1, 5),
F(24000000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0, 16, 1, 2),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x02024,
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x03000,
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x03014,
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x04000,
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x04014,
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x05000,
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x05014,
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
.cmd_rcgr = 0x06000,
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
.cmd_rcgr = 0x06014,
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
.cmd_rcgr = 0x07000,
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
.cmd_rcgr = 0x07014,
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
F(16000000, P_GPLL0_DIV2, 5, 1, 5),
F(24000000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 1, 3, 100),
F(25000000, P_GPLL0, 16, 1, 2),
F(32000000, P_GPLL0, 1, 1, 25),
F(40000000, P_GPLL0, 1, 1, 20),
F(46400000, P_GPLL0, 1, 29, 500),
F(48000000, P_GPLL0, 1, 3, 50),
F(51200000, P_GPLL0, 1, 8, 125),
F(56000000, P_GPLL0, 1, 7, 100),
F(58982400, P_GPLL0, 1, 1152, 15625),
F(60000000, P_GPLL0, 1, 3, 40),
F(64000000, P_GPLL0, 12.5, 1, 1),
{ }
};
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x02044,
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x03034,
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
.cmd_rcgr = 0x04034,
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart3_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
.cmd_rcgr = 0x05034,
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart4_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
.cmd_rcgr = 0x06034,
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart5_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
.cmd_rcgr = 0x07034,
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart6_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_crypto_clk_src[] = {
F(40000000, P_GPLL0_DIV2, 10, 0, 0),
F(80000000, P_GPLL0, 10, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
{ }
};
static struct clk_rcg2 crypto_clk_src = {
.cmd_rcgr = 0x16004,
.freq_tbl = ftbl_crypto_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "crypto_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gp_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0_DIV2, 8, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266666666, P_GPLL0, 3, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
{ .fw_name = "sleep_clk" },
};
static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 2 },
{ P_GPLL0_DIV2, 4 },
{ P_SLEEP_CLK, 6 },
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x08004,
.freq_tbl = ftbl_gp_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
.num_parents = 5,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp2_clk_src = {
.cmd_rcgr = 0x09004,
.freq_tbl = ftbl_gp_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
.num_parents = 5,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp3_clk_src = {
.cmd_rcgr = 0x0a004,
.freq_tbl = ftbl_gp_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
.num_parents = 5,
.ops = &clk_rcg2_ops,
},
};
static struct clk_fixed_factor nss_ppe_cdiv_clk_src = {
.mult = 1,
.div = 4,
.hw.init = &(struct clk_init_data){
.name = "nss_ppe_cdiv_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap_div nss_ubi0_div_clk_src = {
.reg = 0x68118,
.shift = 0,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_ubi0_div_clk_src",
.parent_hws = (const struct clk_hw *[]){
&nss_ubi0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
};
static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .fw_name = "sleep_clk" },
};
static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 2 },
{ P_PI_SLEEP, 6 },
};
static struct clk_rcg2 pcie0_aux_clk_src = {
.cmd_rcgr = 0x75024,
.freq_tbl = ftbl_pcie_aux_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie0_aux_clk_src",
.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
{ .fw_name = "pcie20_phy0_pipe_clk" },
{ .fw_name = "xo" },
};
static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
{ P_PCIE20_PHY0_PIPE, 0 },
{ P_XO, 2 },
};
static struct clk_regmap_mux pcie0_pipe_clk_src = {
.reg = 0x7501c,
.shift = 8,
.width = 2,
.parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "pcie0_pipe_clk_src",
.parent_data = gcc_pcie20_phy0_pipe_clk_xo,
.num_parents = 2,
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
F(144000, P_XO, 16, 12, 125),
F(400000, P_XO, 12, 1, 5),
F(24000000, P_GPLL2, 12, 1, 4),
F(48000000, P_GPLL2, 12, 1, 2),
F(96000000, P_GPLL2, 12, 0, 0),
F(177777778, P_GPLL0, 4.5, 0, 0),
F(192000000, P_GPLL2, 6, 0, 0),
F(384000000, P_GPLL2, 3, 0, 0),
{ }
};
static const struct clk_parent_data
gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL2, 2 },
{ P_GPLL0_DIV2, 4 },
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x42004,
.freq_tbl = ftbl_sdcc_apps_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
.num_parents = 4,
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 usb0_aux_clk_src = {
.cmd_rcgr = 0x3e05c,
.freq_tbl = ftbl_usb_aux_clk_src,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb0_aux_clk_src",
.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(60000000, P_GPLL6, 6, 1, 3),
{ }
};
static const struct clk_parent_data
gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
{ .fw_name = "xo" },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
};
static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
{ P_XO, 0 },
{ P_GPLL6, 1 },
{ P_GPLL0, 3 },
{ P_GPLL0_DIV2, 4 },
};
static struct clk_rcg2 usb0_mock_utmi_clk_src = {
.cmd_rcgr = 0x3e020,
.freq_tbl = ftbl_usb_mock_utmi_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb0_mock_utmi_clk_src",
.parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
.num_parents = 4,
.ops = &clk_rcg2_ops,
},
};
static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
{ .fw_name = "usb3phy_0_cc_pipe_clk" },
{ .fw_name = "xo" },
};
static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
{ P_USB3PHY_0_PIPE, 0 },
{ P_XO, 2 },
};
static struct clk_regmap_mux usb0_pipe_clk_src = {
.reg = 0x3e048,
.shift = 8,
.width = 2,
.parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "usb0_pipe_clk_src",
.parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
.num_parents = 2,
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
F(80000000, P_GPLL0_DIV2, 5, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(216000000, P_GPLL6, 5, 0, 0),
F(308570000, P_GPLL6, 3.5, 0, 0),
};
static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {
{ .fw_name = "xo"},
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL6, 2 },
{ P_GPLL0_DIV2, 4 },
};
static struct clk_rcg2 sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x5d000,
.freq_tbl = ftbl_sdcc_ice_core_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_ice_core_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_gpll0_div2,
.num_parents = 4,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0_DIV2, 8, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 qdss_stm_clk_src = {
.cmd_rcgr = 0x2902C,
.freq_tbl = ftbl_qdss_stm_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "qdss_stm_clk_src",
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
F(80000000, P_GPLL0_DIV2, 5, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(300000000, P_GPLL4, 4, 0, 0),
{ }
};
static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_div2[] = {
{ .fw_name = "xo" },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_main_div2.hw },
};
static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_div2_map[] = {
{ P_XO, 0 },
{ P_GPLL4, 1 },
{ P_GPLL0, 2 },
{ P_GPLL0_DIV2, 4 },
};
static struct clk_rcg2 qdss_traceclkin_clk_src = {
.cmd_rcgr = 0x29048,
.freq_tbl = ftbl_qdss_traceclkin_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "qdss_traceclkin_clk_src",
.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
.num_parents = 4,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 usb1_mock_utmi_clk_src = {
.cmd_rcgr = 0x3f020,
.freq_tbl = ftbl_usb_mock_utmi_clk_src,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb1_mock_utmi_clk_src",
.parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
.num_parents = 4,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_adss_pwm_clk = {
.halt_reg = 0x1c020,
.clkr = {
.enable_reg = 0x1c020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_adss_pwm_clk",
.parent_hws = (const struct clk_hw *[]){
&adss_pwm_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_apss_ahb_clk = {
.halt_reg = 0x4601c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x0b004,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&apss_ahb_postdiv_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0_DIV2, 8, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
F(133333333, P_GPLL0, 6, 0, 0),
F(160000000, P_GPLL0, 5, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
F(266666667, P_GPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 system_noc_bfdcd_clk_src = {
.cmd_rcgr = 0x26004,
.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "system_noc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
.num_parents = 4,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_ubi32_mem_noc_bfdcd_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(307670000, P_BIAS_PLL_NSS_NOC, 1.5, 0, 0),
F(533333333, P_GPLL0, 1.5, 0, 0),
{ }
};
static const struct clk_parent_data
gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .fw_name = "bias_pll_nss_noc_clk" },
};
static const struct parent_map gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL2, 3 },
{ P_BIAS_PLL_NSS_NOC, 4 },
};
static struct clk_rcg2 ubi32_mem_noc_bfdcd_clk_src = {
.cmd_rcgr = 0x68088,
.freq_tbl = ftbl_ubi32_mem_noc_bfdcd_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "ubi32_mem_noc_bfdcd_clk_src",
.parent_data = gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk,
.num_parents = 4,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_apss_axi_clk = {
.halt_reg = 0x46020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x0b004,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&apss_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x01008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x0b004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x02008,
.clkr = {
.enable_reg = 0x02008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup1_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x02004,
.clkr = {
.enable_reg = 0x02004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup1_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x03010,
.clkr = {
.enable_reg = 0x03010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup2_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x0300c,
.clkr = {
.enable_reg = 0x0300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup2_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x04010,
.clkr = {
.enable_reg = 0x04010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup3_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x0400c,
.clkr = {
.enable_reg = 0x0400c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup3_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.halt_reg = 0x05010,
.clkr = {
.enable_reg = 0x05010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup4_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.halt_reg = 0x0500c,
.clkr = {
.enable_reg = 0x0500c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup4_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
.halt_reg = 0x06010,
.clkr = {
.enable_reg = 0x06010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup5_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
.halt_reg = 0x0600c,
.clkr = {
.enable_reg = 0x0600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup5_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
.halt_reg = 0x0700c,
.clkr = {
.enable_reg = 0x0700c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup6_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x0203c,
.clkr = {
.enable_reg = 0x0203c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_uart1_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x0302c,
.clkr = {
.enable_reg = 0x0302c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_uart2_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart3_apps_clk = {
.halt_reg = 0x0402c,
.clkr = {
.enable_reg = 0x0402c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_uart3_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart4_apps_clk = {
.halt_reg = 0x0502c,
.clkr = {
.enable_reg = 0x0502c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart4_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_uart4_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart5_apps_clk = {
.halt_reg = 0x0602c,
.clkr = {
.enable_reg = 0x0602c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart5_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_uart5_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart6_apps_clk = {
.halt_reg = 0x0702c,
.clkr = {
.enable_reg = 0x0702c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart6_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_uart6_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_ahb_clk = {
.halt_reg = 0x16024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x0b004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_axi_clk = {
.halt_reg = 0x16020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x0b004,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_clk = {
.halt_reg = 0x1601c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x0b004,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_clk",
.parent_hws = (const struct clk_hw *[]){
&crypto_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_fixed_factor gpll6_out_main_div2 = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "gpll6_out_main_div2",
.parent_hws = (const struct clk_hw *[]){
&gpll6_main.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_branch gcc_xo_clk = {
.halt_reg = 0x30030,
.clkr = {
.enable_reg = 0x30030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_xo_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_xo_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x08000,
.clkr = {
.enable_reg = 0x08000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw *[]){
&gp1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x09000,
.clkr = {
.enable_reg = 0x09000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw *[]){
&gp2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x0a000,
.clkr = {
.enable_reg = 0x0a000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw *[]){
&gp3_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mdio_ahb_clk = {
.halt_reg = 0x58004,
.clkr = {
.enable_reg = 0x58004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdio_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_ppe_clk = {
.halt_reg = 0x68310,
.clkr = {
.enable_reg = 0x68310,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_ppe_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_ce_apb_clk = {
.halt_reg = 0x68174,
.clkr = {
.enable_reg = 0x68174,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ce_apb_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_ce_axi_clk = {
.halt_reg = 0x68170,
.clkr = {
.enable_reg = 0x68170,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ce_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_cfg_clk = {
.halt_reg = 0x68160,
.clkr = {
.enable_reg = 0x68160,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_cfg_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_crypto_clk = {
.halt_reg = 0x68164,
.clkr = {
.enable_reg = 0x68164,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_crypto_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_crypto_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_csr_clk = {
.halt_reg = 0x68318,
.clkr = {
.enable_reg = 0x68318,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_csr_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_edma_cfg_clk = {
.halt_reg = 0x6819C,
.clkr = {
.enable_reg = 0x6819C,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_edma_cfg_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_edma_clk = {
.halt_reg = 0x68198,
.clkr = {
.enable_reg = 0x68198,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_edma_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_noc_clk = {
.halt_reg = 0x68168,
.clkr = {
.enable_reg = 0x68168,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_noc_clk",
.parent_hws = (const struct clk_hw *[]){
&snoc_nssnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ubi0_utcm_clk = {
.halt_reg = 0x2606c,
.clkr = {
.enable_reg = 0x2606c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_utcm_clk",
.parent_hws = (const struct clk_hw *[]){
&snoc_nssnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_nssnoc_clk = {
.halt_reg = 0x26070,
.clkr = {
.enable_reg = 0x26070,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_snoc_nssnoc_clk",
.parent_hws = (const struct clk_hw *[]){
&snoc_nssnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(133333333, P_GPLL0, 6, 0, 0),
{ }
};
static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 wcss_ahb_clk_src = {
.cmd_rcgr = 0x59020,
.freq_tbl = ftbl_wcss_ahb_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "wcss_ahb_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_gpll6[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll6.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_gpll6_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL2, 2 },
{ P_GPLL4, 3 },
{ P_GPLL6, 4 },
};
static struct clk_rcg2 q6_axi_clk_src = {
.cmd_rcgr = 0x59120,
.freq_tbl = ftbl_q6_axi_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll2_gpll4_gpll6_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "q6_axi_clk_src",
.parent_data = gcc_xo_gpll0_gpll2_gpll4_gpll6,
.num_parents = 5,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_lpass_core_axim_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 lpass_core_axim_clk_src = {
.cmd_rcgr = 0x1F020,
.freq_tbl = ftbl_lpass_core_axim_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "lpass_core_axim_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_lpass_snoc_cfg_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(266666667, P_GPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 lpass_snoc_cfg_clk_src = {
.cmd_rcgr = 0x1F040,
.freq_tbl = ftbl_lpass_snoc_cfg_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "lpass_snoc_cfg_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_lpass_q6_axim_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(400000000, P_GPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 lpass_q6_axim_clk_src = {
.cmd_rcgr = 0x1F008,
.freq_tbl = ftbl_lpass_q6_axim_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "lpass_q6_axim_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_rbcpr_wcss_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 16, 0, 0),
{ }
};
static struct clk_rcg2 rbcpr_wcss_clk_src = {
.cmd_rcgr = 0x3a00c,
.freq_tbl = ftbl_rbcpr_wcss_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "rbcpr_wcss_clk_src",
.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
.num_parents = 3,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_lpass_core_axim_clk = {
.halt_reg = 0x1F028,
.clkr = {
.enable_reg = 0x1F028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_lpass_core_axim_clk",
.parent_hws = (const struct clk_hw *[]){
&lpass_core_axim_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_lpass_snoc_cfg_clk = {
.halt_reg = 0x1F048,
.clkr = {
.enable_reg = 0x1F048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_lpass_snoc_cfg_clk",
.parent_hws = (const struct clk_hw *[]){
&lpass_snoc_cfg_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_lpass_q6_axim_clk = {
.halt_reg = 0x1F010,
.clkr = {
.enable_reg = 0x1F010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_lpass_q6_axim_clk",
.parent_hws = (const struct clk_hw *[]){
&lpass_q6_axim_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_lpass_q6_atbm_at_clk = {
.halt_reg = 0x1F018,
.clkr = {
.enable_reg = 0x1F018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_lpass_q6_atbm_at_clk",
.parent_hws = (const struct clk_hw *[]){
&qdss_at_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_lpass_q6_pclkdbg_clk = {
.halt_reg = 0x1F01C,
.clkr = {
.enable_reg = 0x1F01C,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_lpass_q6_pclkdbg_clk",
.parent_hws = (const struct clk_hw *[]){
&qdss_dap_sync_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_lpass_q6ss_tsctr_1to2_clk = {
.halt_reg = 0x1F014,
.clkr = {
.enable_reg = 0x1F014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_lpass_q6ss_tsctr_1to2_clk",
.parent_hws = (const struct clk_hw *[]){
&qdss_tsctr_div2_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_lpass_q6ss_trig_clk = {
.halt_reg = 0x1F038,
.clkr = {
.enable_reg = 0x1F038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_lpass_q6ss_trig_clk",
.parent_hws = (const struct clk_hw *[]){
&qdss_dap_sync_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_lpass_tbu_clk = {
.halt_reg = 0x12094,
.clkr = {
.enable_reg = 0xb00c,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_lpass_tbu_clk",
.parent_hws = (const struct clk_hw *[]){
&lpass_q6_axim_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcnoc_lpass_clk = {
.halt_reg = 0x27020,
.clkr = {
.enable_reg = 0x27020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcnoc_lpass_clk",
.parent_hws = (const struct clk_hw *[]){
&lpass_core_axim_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mem_noc_lpass_clk = {
.halt_reg = 0x1D044,
.clkr = {
.enable_reg = 0x1D044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mem_noc_lpass_clk",
.parent_hws = (const struct clk_hw *[]){
&lpass_q6_axim_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_lpass_cfg_clk = {
.halt_reg = 0x26074,
.clkr = {
.enable_reg = 0x26074,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_snoc_lpass_cfg_clk",
.parent_hws = (const struct clk_hw *[]){
&lpass_snoc_cfg_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mem_noc_ubi32_clk = {
.halt_reg = 0x1D03C,
.clkr = {
.enable_reg = 0x1D03C,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mem_noc_ubi32_clk",
.parent_hws = (const struct clk_hw *[]){
&ubi32_mem_noc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port1_rx_clk = {
.halt_reg = 0x68240,
.clkr = {
.enable_reg = 0x68240,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port1_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port1_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port1_tx_clk = {
.halt_reg = 0x68244,
.clkr = {
.enable_reg = 0x68244,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port1_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port1_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port2_rx_clk = {
.halt_reg = 0x68248,
.clkr = {
.enable_reg = 0x68248,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port2_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port2_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port2_tx_clk = {
.halt_reg = 0x6824c,
.clkr = {
.enable_reg = 0x6824c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port2_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port2_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port3_rx_clk = {
.halt_reg = 0x68250,
.clkr = {
.enable_reg = 0x68250,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port3_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port3_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port3_tx_clk = {
.halt_reg = 0x68254,
.clkr = {
.enable_reg = 0x68254,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port3_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port3_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port4_rx_clk = {
.halt_reg = 0x68258,
.clkr = {
.enable_reg = 0x68258,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port4_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port4_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port4_tx_clk = {
.halt_reg = 0x6825c,
.clkr = {
.enable_reg = 0x6825c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port4_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port4_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port5_rx_clk = {
.halt_reg = 0x68260,
.clkr = {
.enable_reg = 0x68260,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port5_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port5_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_port5_tx_clk = {
.halt_reg = 0x68264,
.clkr = {
.enable_reg = 0x68264,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port5_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port5_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_ppe_cfg_clk = {
.halt_reg = 0x68194,
.clkr = {
.enable_reg = 0x68194,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ppe_cfg_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_ppe_clk = {
.halt_reg = 0x68190,
.clkr = {
.enable_reg = 0x68190,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ppe_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_ppe_ipe_clk = {
.halt_reg = 0x68338,
.clkr = {
.enable_reg = 0x68338,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ppe_ipe_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nss_ptp_ref_clk = {
.halt_reg = 0x6816C,
.clkr = {
.enable_reg = 0x6816C,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ptp_ref_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_cdiv_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_ce_apb_clk = {
.halt_reg = 0x6830C,
.clkr = {
.enable_reg = 0x6830C,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ce_apb_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_ce_axi_clk = {
.halt_reg = 0x68308,
.clkr = {
.enable_reg = 0x68308,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ce_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_crypto_clk = {
.halt_reg = 0x68314,
.clkr = {
.enable_reg = 0x68314,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_crypto_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_crypto_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_ppe_cfg_clk = {
.halt_reg = 0x68304,
.clkr = {
.enable_reg = 0x68304,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ppe_cfg_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_ppe_clk = {
.halt_reg = 0x68300,
.clkr = {
.enable_reg = 0x68300,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ppe_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
.halt_reg = 0x68180,
.clkr = {
.enable_reg = 0x68180,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_qosgen_ref_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_xo_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_snoc_clk = {
.halt_reg = 0x68188,
.clkr = {
.enable_reg = 0x68188,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_snoc_clk",
.parent_hws = (const struct clk_hw *[]){
&system_noc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
.halt_reg = 0x68184,
.clkr = {
.enable_reg = 0x68184,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_timeout_ref_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_xo_div4_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = {
.halt_reg = 0x68270,
.clkr = {
.enable_reg = 0x68270,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ubi0_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_port1_mac_clk = {
.halt_reg = 0x68320,
.clkr = {
.enable_reg = 0x68320,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port1_mac_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_port2_mac_clk = {
.halt_reg = 0x68324,
.clkr = {
.enable_reg = 0x68324,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port2_mac_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_port3_mac_clk = {
.halt_reg = 0x68328,
.clkr = {
.enable_reg = 0x68328,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port3_mac_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_port4_mac_clk = {
.halt_reg = 0x6832c,
.clkr = {
.enable_reg = 0x6832c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port4_mac_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_port5_mac_clk = {
.halt_reg = 0x68330,
.clkr = {
.enable_reg = 0x68330,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port5_mac_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ubi0_ahb_clk = {
.halt_reg = 0x6820C,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x6820C,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ubi0_axi_clk = {
.halt_reg = 0x68200,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x68200,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&ubi32_mem_noc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ubi0_nc_axi_clk = {
.halt_reg = 0x68204,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x68204,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_nc_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&snoc_nssnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ubi0_core_clk = {
.halt_reg = 0x68210,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x68210,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_core_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_ubi0_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_ahb_clk = {
.halt_reg = 0x75010,
.clkr = {
.enable_reg = 0x75010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_aux_clk = {
.halt_reg = 0x75014,
.clkr = {
.enable_reg = 0x75014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&pcie0_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_axi_m_clk = {
.halt_reg = 0x75008,
.clkr = {
.enable_reg = 0x75008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_axi_m_clk",
.parent_hws = (const struct clk_hw *[]){
&pcie0_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_axi_s_clk = {
.halt_reg = 0x7500c,
.clkr = {
.enable_reg = 0x7500c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_axi_s_clk",
.parent_hws = (const struct clk_hw *[]){
&pcie0_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
.halt_reg = 0x26048,
.clkr = {
.enable_reg = 0x26048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_pcie0_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&pcie0_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_pipe_clk = {
.halt_reg = 0x75018,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x75018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_pipe_clk",
.parent_hws = (const struct clk_hw *[]){
&pcie0_pipe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x13004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x0b004,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qdss_dap_clk = {
.halt_reg = 0x29084,
.clkr = {
.enable_reg = 0x29084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qdss_dap_clk",
.parent_hws = (const struct clk_hw *[]){
&qdss_dap_sync_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qpic_ahb_clk = {
.halt_reg = 0x57024,
.clkr = {
.enable_reg = 0x57024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qpic_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qpic_clk = {
.halt_reg = 0x57020,
.clkr = {
.enable_reg = 0x57020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qpic_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x4201c,
.clkr = {
.enable_reg = 0x4201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x42018,
.clkr = {
.enable_reg = 0x42018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&sdcc1_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_ahb_clk = {
.halt_reg = 0x56008,
.clkr = {
.enable_reg = 0x56008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_port1_rx_clk = {
.halt_reg = 0x56010,
.clkr = {
.enable_reg = 0x56010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port1_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port1_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_port1_tx_clk = {
.halt_reg = 0x56014,
.clkr = {
.enable_reg = 0x56014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port1_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port1_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_port2_rx_clk = {
.halt_reg = 0x56018,
.clkr = {
.enable_reg = 0x56018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port2_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port2_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_port2_tx_clk = {
.halt_reg = 0x5601c,
.clkr = {
.enable_reg = 0x5601c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port2_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port2_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_port3_rx_clk = {
.halt_reg = 0x56020,
.clkr = {
.enable_reg = 0x56020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port3_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port3_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_port3_tx_clk = {
.halt_reg = 0x56024,
.clkr = {
.enable_reg = 0x56024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port3_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port3_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_port4_rx_clk = {
.halt_reg = 0x56028,
.clkr = {
.enable_reg = 0x56028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port4_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port4_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_port4_tx_clk = {
.halt_reg = 0x5602c,
.clkr = {
.enable_reg = 0x5602c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port4_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port4_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_port5_rx_clk = {
.halt_reg = 0x56030,
.clkr = {
.enable_reg = 0x56030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port5_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port5_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_port5_tx_clk = {
.halt_reg = 0x56034,
.clkr = {
.enable_reg = 0x56034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port5_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port5_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy0_sys_clk = {
.halt_reg = 0x5600C,
.clkr = {
.enable_reg = 0x5600C,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_sys_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_xo_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy1_ahb_clk = {
.halt_reg = 0x56108,
.clkr = {
.enable_reg = 0x56108,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy1_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy1_port5_rx_clk = {
.halt_reg = 0x56110,
.clkr = {
.enable_reg = 0x56110,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy1_port5_rx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port5_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy1_port5_tx_clk = {
.halt_reg = 0x56114,
.clkr = {
.enable_reg = 0x56114,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy1_port5_tx_clk",
.parent_hws = (const struct clk_hw *[]){
&nss_port5_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_uniphy1_sys_clk = {
.halt_reg = 0x5610C,
.clkr = {
.enable_reg = 0x5610C,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy1_sys_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_xo_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_aux_clk = {
.halt_reg = 0x3e044,
.clkr = {
.enable_reg = 0x3e044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_aux_clk",
.parent_hws = (const struct clk_hw *[]){
&usb0_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_master_clk = {
.halt_reg = 0x3e000,
.clkr = {
.enable_reg = 0x3e000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_master_clk",
.parent_hws = (const struct clk_hw *[]){
&usb0_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_snoc_bus_timeout2_ahb_clk = {
.halt_reg = 0x47014,
.clkr = {
.enable_reg = 0x47014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_snoc_bus_timeout2_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&usb0_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_rcg2 pcie0_rchng_clk_src = {
.cmd_rcgr = 0x75070,
.freq_tbl = ftbl_pcie_rchng_clk_src,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie0_rchng_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_pcie0_rchng_clk = {
.halt_reg = 0x75070,
.clkr = {
.enable_reg = 0x75070,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_rchng_clk",
.parent_hws = (const struct clk_hw *[]){
&pcie0_rchng_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
.halt_reg = 0x75048,
.clkr = {
.enable_reg = 0x75048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_axi_s_bridge_clk",
.parent_hws = (const struct clk_hw *[]){
&pcie0_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
.halt_reg = 0x26040,
.clkr = {
.enable_reg = 0x26040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb0_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&usb0_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_mock_utmi_clk = {
.halt_reg = 0x3e008,
.clkr = {
.enable_reg = 0x3e008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_mock_utmi_clk",
.parent_hws = (const struct clk_hw *[]){
&usb0_mock_utmi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
.halt_reg = 0x3e080,
.clkr = {
.enable_reg = 0x3e080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_phy_cfg_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_pipe_clk = {
.halt_reg = 0x3e040,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x3e040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_pipe_clk",
.parent_hws = (const struct clk_hw *[]){
&usb0_pipe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb0_sleep_clk = {
.halt_reg = 0x3e004,
.clkr = {
.enable_reg = 0x3e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_sleep_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_sleep_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb1_master_clk = {
.halt_reg = 0x3f000,
.clkr = {
.enable_reg = 0x3f000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_master_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb1_mock_utmi_clk = {
.halt_reg = 0x3f008,
.clkr = {
.enable_reg = 0x3f008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_mock_utmi_clk",
.parent_hws = (const struct clk_hw *[]){
&usb1_mock_utmi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
.halt_reg = 0x3f080,
.clkr = {
.enable_reg = 0x3f080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_phy_cfg_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb1_sleep_clk = {
.halt_reg = 0x3f004,
.clkr = {
.enable_reg = 0x3f004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_sleep_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_sleep_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
.halt_reg = 0x56308,
.clkr = {
.enable_reg = 0x56308,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cmn_12gpll_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cmn_12gpll_sys_clk = {
.halt_reg = 0x5630c,
.clkr = {
.enable_reg = 0x5630c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cmn_12gpll_sys_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_xo_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0x5d014,
.clkr = {
.enable_reg = 0x5d014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
.parent_hws = (const struct clk_hw *[]){
&sdcc1_ice_core_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_dcc_clk = {
.halt_reg = 0x77004,
.clkr = {
.enable_reg = 0x77004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_dcc_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct alpha_pll_config ubi32_pll_config = {
.l = 0x3e,
.alpha = 0x6667,
.config_ctl_val = 0x240d4828,
.config_ctl_hi_val = 0x6,
.main_output_mask = BIT(0),
.aux_output_mask = BIT(1),
.pre_div_val = 0x0,
.pre_div_mask = BIT(12),
.post_div_val = 0x0,
.post_div_mask = GENMASK(9, 8),
.alpha_en_mask = BIT(24),
.test_ctl_val = 0x1C0000C0,
.test_ctl_hi_val = 0x4000,
};
static const struct alpha_pll_config nss_crypto_pll_config = {
.l = 0x32,
.alpha = 0x0,
.alpha_hi = 0x0,
.config_ctl_val = 0x4001055b,
.main_output_mask = BIT(0),
.pre_div_val = 0x0,
.pre_div_mask = GENMASK(14, 12),
.post_div_val = 0x1 << 8,
.post_div_mask = GENMASK(11, 8),
.vco_mask = GENMASK(21, 20),
.vco_val = 0x0,
.alpha_en_mask = BIT(24),
};
static struct clk_hw *gcc_ipq6018_hws[] = {
&gpll0_out_main_div2.hw,
&gcc_xo_div4_clk_src.hw,
&nss_ppe_cdiv_clk_src.hw,
&gpll6_out_main_div2.hw,
&qdss_dap_sync_clk_src.hw,
&qdss_tsctr_div2_clk_src.hw,
};
static struct clk_regmap *gcc_ipq6018_clks[] = {
[GPLL0_MAIN] = &gpll0_main.clkr,
[GPLL0] = &gpll0.clkr,
[UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
[UBI32_PLL] = &ubi32_pll.clkr,
[GPLL6_MAIN] = &gpll6_main.clkr,
[GPLL6] = &gpll6.clkr,
[GPLL4_MAIN] = &gpll4_main.clkr,
[GPLL4] = &gpll4.clkr,
[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
[GPLL2_MAIN] = &gpll2_main.clkr,
[GPLL2] = &gpll2.clkr,
[NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
[NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
[QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
[QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
[NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
[SNOC_NSSNOC_BFDCD_CLK_SRC] = &snoc_nssnoc_bfdcd_clk_src.clkr,
[NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
[NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
[NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
[UBI32_MEM_NOC_BFDCD_CLK_SRC] = &ubi32_mem_noc_bfdcd_clk_src.clkr,
[PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
[USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
[APSS_AHB_POSTDIV_CLK_SRC] = &apss_ahb_postdiv_clk_src.clkr,
[NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
[NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
[NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
[NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
[NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
[NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
[NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
[NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
[NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
[NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
[APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr,
[NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
[NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
[NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
[NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
[NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
[NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
[NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
[NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
[NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
[NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
[ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
[NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
[PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
[USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
[USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
[GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
[GCC_XO_CLK] = &gcc_xo_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
[GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
[GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
[GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
[GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
[GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
[GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
[GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
[GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
[GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
[GCC_UBI0_UTCM_CLK] = &gcc_ubi0_utcm_clk.clkr,
[GCC_SNOC_NSSNOC_CLK] = &gcc_snoc_nssnoc_clk.clkr,
[GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
[GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
[GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
[GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
[GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
[GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
[GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
[GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
[GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
[GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
[GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
[GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
[GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
[GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
[GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
[GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
[GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
[GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
[GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
[GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
[GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
[GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
[GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
[GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
[GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
[GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
[GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
[GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
[GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
[GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
[GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
[GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
[GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
[GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
[GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
[GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
[GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
[GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
[GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
[GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
[GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
[GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
[GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
[GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
[GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
[GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
[GCC_SNOC_BUS_TIMEOUT2_AHB_CLK] = &gcc_snoc_bus_timeout2_ahb_clk.clkr,
[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
[GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
[GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
[GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
[GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
[GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
[GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
[PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
[PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
[WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
[Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
[RBCPR_WCSS_CLK_SRC] = &rbcpr_wcss_clk_src.clkr,
[GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
[LPASS_CORE_AXIM_CLK_SRC] = &lpass_core_axim_clk_src.clkr,
[GCC_LPASS_SNOC_CFG_CLK] = &gcc_lpass_snoc_cfg_clk.clkr,
[LPASS_SNOC_CFG_CLK_SRC] = &lpass_snoc_cfg_clk_src.clkr,
[GCC_LPASS_Q6_AXIM_CLK] = &gcc_lpass_q6_axim_clk.clkr,
[LPASS_Q6_AXIM_CLK_SRC] = &lpass_q6_axim_clk_src.clkr,
[GCC_LPASS_Q6_ATBM_AT_CLK] = &gcc_lpass_q6_atbm_at_clk.clkr,
[GCC_LPASS_Q6_PCLKDBG_CLK] = &gcc_lpass_q6_pclkdbg_clk.clkr,
[GCC_LPASS_Q6SS_TSCTR_1TO2_CLK] = &gcc_lpass_q6ss_tsctr_1to2_clk.clkr,
[GCC_LPASS_Q6SS_TRIG_CLK] = &gcc_lpass_q6ss_trig_clk.clkr,
[GCC_LPASS_TBU_CLK] = &gcc_lpass_tbu_clk.clkr,
[GCC_PCNOC_LPASS_CLK] = &gcc_pcnoc_lpass_clk.clkr,
[GCC_MEM_NOC_UBI32_CLK] = &gcc_mem_noc_ubi32_clk.clkr,
[GCC_MEM_NOC_LPASS_CLK] = &gcc_mem_noc_lpass_clk.clkr,
[GCC_SNOC_LPASS_CFG_CLK] = &gcc_snoc_lpass_cfg_clk.clkr,
[QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
[QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
};
static const struct qcom_reset_map gcc_ipq6018_resets[] = {
[GCC_BLSP1_BCR] = { 0x01000, 0 },
[GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
[GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
[GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
[GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
[GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
[GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
[GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
[GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
[GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
[GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
[GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
[GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
[GCC_IMEM_BCR] = { 0x0e000, 0 },
[GCC_SMMU_BCR] = { 0x12000, 0 },
[GCC_APSS_TCU_BCR] = { 0x12050, 0 },
[GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
[GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
[GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
[GCC_PRNG_BCR] = { 0x13000, 0 },
[GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
[GCC_CRYPTO_BCR] = { 0x16000, 0 },
[GCC_WCSS_BCR] = { 0x18000, 0 },
[GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
[GCC_NSS_BCR] = { 0x19000, 0 },
[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
[GCC_ADSS_BCR] = { 0x1c000, 0 },
[GCC_DDRSS_BCR] = { 0x1e000, 0 },
[GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
[GCC_PCNOC_BCR] = { 0x27018, 0 },
[GCC_TCSR_BCR] = { 0x28000, 0 },
[GCC_QDSS_BCR] = { 0x29000, 0 },
[GCC_DCD_BCR] = { 0x2a000, 0 },
[GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
[GCC_MPM_BCR] = { 0x2c000, 0 },
[GCC_SPDM_BCR] = { 0x2f000, 0 },
[GCC_RBCPR_BCR] = { 0x33000, 0 },
[GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
[GCC_TLMM_BCR] = { 0x34000, 0 },
[GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
[GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
[GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
[GCC_USB0_BCR] = { 0x3e070, 0 },
[GCC_USB1_BCR] = { 0x3f070, 0 },
[GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
[GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
[GCC_SDCC1_BCR] = { 0x42000, 0 },
[GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
[GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x47008, 0 },
[GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47010, 0 },
[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
[GCC_UNIPHY0_BCR] = { 0x56000, 0 },
[GCC_UNIPHY1_BCR] = { 0x56100, 0 },
[GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
[GCC_QPIC_BCR] = { 0x57018, 0 },
[GCC_MDIO_BCR] = { 0x58000, 0 },
[GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
[GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
[GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
[GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
[GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
[GCC_PCIE0_BCR] = { 0x75004, 0 },
[GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
[GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
[GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
[GCC_DCC_BCR] = { 0x77000, 0 },
[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
[GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
[GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
[GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
[GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
[GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
[GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
[GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
[GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
[GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
[GCC_NSS_CFG_ARES] = { 0x68010, 16 },
[GCC_NSS_NOC_ARES] = { 0x68010, 18 },
[GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
[GCC_NSS_CSR_ARES] = { 0x68010, 20 },
[GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
[GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
[GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
[GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
[GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
[GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
[GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
[GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
[GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
[GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
[GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
[GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
[GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
[GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
[GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
[GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
[GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
[GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
[GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = 0xf0000 },
[GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = 0x3ff2 },
[GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
[GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = 0x32 },
[GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
[GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = 0x300000 },
[GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = 0x1000003 },
[GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = 0x200000c },
[GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = 0x4000030 },
[GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = 0x8000300 },
[GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = 0x10000c00 },
[GCC_UNIPHY0_PORT1_ARES] = { .reg = 0x56004, .bitmask = 0x30 },
[GCC_UNIPHY0_PORT2_ARES] = { .reg = 0x56004, .bitmask = 0xc0 },
[GCC_UNIPHY0_PORT3_ARES] = { .reg = 0x56004, .bitmask = 0x300 },
[GCC_UNIPHY0_PORT4_ARES] = { .reg = 0x56004, .bitmask = 0xc00 },
[GCC_UNIPHY0_PORT5_ARES] = { .reg = 0x56004, .bitmask = 0x3000 },
[GCC_UNIPHY0_PORT_4_5_RESET] = { .reg = 0x56004, .bitmask = 0x3c02 },
[GCC_UNIPHY0_PORT_4_RESET] = { .reg = 0x56004, .bitmask = 0xc02 },
[GCC_LPASS_BCR] = {0x1F000, 0},
[GCC_UBI32_TBU_BCR] = {0x65000, 0},
[GCC_LPASS_TBU_BCR] = {0x6C000, 0},
[GCC_WCSSAON_RESET] = {0x59010, 0},
[GCC_LPASS_Q6_AXIM_ARES] = {0x1F004, 0},
[GCC_LPASS_Q6SS_TSCTR_1TO2_ARES] = {0x1F004, 1},
[GCC_LPASS_Q6SS_TRIG_ARES] = {0x1F004, 2},
[GCC_LPASS_Q6_ATBM_AT_ARES] = {0x1F004, 3},
[GCC_LPASS_Q6_PCLKDBG_ARES] = {0x1F004, 4},
[GCC_LPASS_CORE_AXIM_ARES] = {0x1F004, 5},
[GCC_LPASS_SNOC_CFG_ARES] = {0x1F004, 6},
[GCC_WCSS_DBG_ARES] = {0x59008, 0},
[GCC_WCSS_ECAHB_ARES] = {0x59008, 1},
[GCC_WCSS_ACMT_ARES] = {0x59008, 2},
[GCC_WCSS_DBG_BDG_ARES] = {0x59008, 3},
[GCC_WCSS_AHB_S_ARES] = {0x59008, 4},
[GCC_WCSS_AXI_M_ARES] = {0x59008, 5},
[GCC_Q6SS_DBG_ARES] = {0x59110, 0},
[GCC_Q6_AHB_S_ARES] = {0x59110, 1},
[GCC_Q6_AHB_ARES] = {0x59110, 2},
[GCC_Q6_AXIM2_ARES] = {0x59110, 3},
[GCC_Q6_AXIM_ARES] = {0x59110, 4},
};
static const struct of_device_id gcc_ipq6018_match_table[] = {
{ .compatible = "qcom,gcc-ipq6018" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_ipq6018_match_table);
static const struct regmap_config gcc_ipq6018_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x7fffc,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_ipq6018_desc = {
.config = &gcc_ipq6018_regmap_config,
.clks = gcc_ipq6018_clks,
.num_clks = ARRAY_SIZE(gcc_ipq6018_clks),
.resets = gcc_ipq6018_resets,
.num_resets = ARRAY_SIZE(gcc_ipq6018_resets),
.clk_hws = gcc_ipq6018_hws,
.num_clk_hws = ARRAY_SIZE(gcc_ipq6018_hws),
};
static int gcc_ipq6018_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gcc_ipq6018_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Disable SW_COLLAPSE for USB0 GDSCR */
regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0);
/* Enable SW_OVERRIDE for USB0 GDSCR */
regmap_update_bits(regmap, 0x3e078, BIT(2), BIT(2));
/* Disable SW_COLLAPSE for USB1 GDSCR */
regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0);
/* Enable SW_OVERRIDE for USB1 GDSCR */
regmap_update_bits(regmap, 0x3f078, BIT(2), BIT(2));
/* SW Workaround for UBI Huyara PLL */
regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
&nss_crypto_pll_config);
return qcom_cc_really_probe(pdev, &gcc_ipq6018_desc, regmap);
}
static struct platform_driver gcc_ipq6018_driver = {
.probe = gcc_ipq6018_probe,
.driver = {
.name = "qcom,gcc-ipq6018",
.of_match_table = gcc_ipq6018_match_table,
},
};
static int __init gcc_ipq6018_init(void)
{
return platform_driver_register(&gcc_ipq6018_driver);
}
core_initcall(gcc_ipq6018_init);
static void __exit gcc_ipq6018_exit(void)
{
platform_driver_unregister(&gcc_ipq6018_driver);
}
module_exit(gcc_ipq6018_exit);
MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ6018 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gcc-ipq6018.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm6115-gpucc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_GCC_GPU_GPLL0_CLK_SRC,
DT_GCC_GPU_GPLL0_DIV_CLK_SRC,
};
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_CC_PLL0_OUT_AUX2,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL1_OUT_AUX,
P_GPU_CC_PLL1_OUT_MAIN,
};
static struct pll_vco default_vco[] = {
{ 1000000000, 2000000000, 0 },
};
static struct pll_vco pll1_vco[] = {
{ 500000000, 1000000000, 2 },
};
static const struct alpha_pll_config gpu_cc_pll0_config = {
.l = 0x3e,
.alpha = 0,
.alpha_hi = 0x80,
.vco_val = 0x0 << 20,
.vco_mask = GENMASK(21, 20),
.alpha_en_mask = BIT(24),
.main_output_mask = BIT(0),
.aux_output_mask = BIT(1),
.aux2_output_mask = BIT(2),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
};
/* 1200MHz configuration */
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
.vco_table = default_vco,
.num_vco = ARRAY_SIZE(default_vco),
.flags = SUPPORTS_DYNAMIC_UPDATE,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct clk_div_table post_div_table_gpu_cc_pll0_out_aux2[] = {
{ 0x0, 1 },
{ }
};
static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_aux2 = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_gpu_cc_pll0_out_aux2,
.num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_aux2),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll0_out_aux2",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_pll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_ops,
},
};
/* 640MHz configuration */
static const struct alpha_pll_config gpu_cc_pll1_config = {
.l = 0x21,
.alpha = 0x55555555,
.alpha_hi = 0x55,
.alpha_en_mask = BIT(24),
.vco_val = 0x2 << 20,
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.aux_output_mask = BIT(1),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x100,
.vco_table = pll1_vco,
.num_vco = ARRAY_SIZE(pll1_vco),
.flags = SUPPORTS_DYNAMIC_UPDATE,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct clk_div_table post_div_table_gpu_cc_pll1_out_aux[] = {
{ 0x0, 1 },
{ }
};
static struct clk_alpha_pll_postdiv gpu_cc_pll1_out_aux = {
.offset = 0x100,
.post_div_shift = 15,
.post_div_table = post_div_table_gpu_cc_pll1_out_aux,
.num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll1_out_aux),
.width = 3,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1_out_aux",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_pll1.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_ops,
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .index = P_BI_TCXO },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_AUX2, 2 },
{ P_GPU_CC_PLL1_OUT_AUX, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
{ .index = P_BI_TCXO },
{ .hw = &gpu_cc_pll0_out_aux2.clkr.hw },
{ .hw = &gpu_cc_pll1_out_aux.clkr.hw },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x1120,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
F(320000000, P_GPU_CC_PLL1_OUT_AUX, 2, 0, 0),
F(465000000, P_GPU_CC_PLL1_OUT_AUX, 2, 0, 0),
F(600000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(745000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(820000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(900000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(950000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(980000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
.cmd_rcgr = 0x101c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_1,
.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gfx3d_clk_src",
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x1078,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x107c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x107c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_crc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gfx3d_clk = {
.halt_reg = 0x10a4,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x10a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_gfx3d_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x1098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_gmu_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
.halt_reg = 0x108c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x108c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_snoc_dvm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_aon_clk = {
.halt_reg = 0x1004,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_aon_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x109c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x109c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_cxo_clk = {
.halt_reg = 0x1060,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_cxo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gfx3d_clk = {
.halt_reg = 0x1054,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x1054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gfx3d_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_sleep_clk = {
.halt_reg = 0x1090,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
.halt_reg = 0x5000,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x5000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x106c,
.gds_hw_ctrl = 0x1540,
.pd = {
.name = "gpu_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x100c,
.clamp_io_ctrl = 0x1508,
.resets = (unsigned int []){ GPU_GX_BCR },
.reset_count = 1,
.pd = {
.name = "gpu_gx_gdsc",
},
.parent = &gpu_cx_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | SW_RESET | VOTABLE,
};
static struct clk_regmap *gpu_cc_sm6115_clocks[] = {
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr,
[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
[GPU_CC_PLL0_OUT_AUX2] = &gpu_cc_pll0_out_aux2.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
[GPU_CC_PLL1_OUT_AUX] = &gpu_cc_pll1_out_aux.clkr,
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
};
static const struct qcom_reset_map gpu_cc_sm6115_resets[] = {
[GPU_GX_BCR] = { 0x1008 },
};
static struct gdsc *gpu_cc_sm6115_gdscs[] = {
[GPU_CX_GDSC] = &gpu_cx_gdsc,
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
static const struct regmap_config gpu_cc_sm6115_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9000,
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_sm6115_desc = {
.config = &gpu_cc_sm6115_regmap_config,
.clks = gpu_cc_sm6115_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sm6115_clocks),
.resets = gpu_cc_sm6115_resets,
.num_resets = ARRAY_SIZE(gpu_cc_sm6115_resets),
.gdscs = gpu_cc_sm6115_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sm6115_gdscs),
};
static const struct of_device_id gpu_cc_sm6115_match_table[] = {
{ .compatible = "qcom,sm6115-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sm6115_match_table);
static int gpu_cc_sm6115_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gpu_cc_sm6115_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_alpha_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_alpha_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
/* Set recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
qcom_branch_set_wakeup(regmap, gpu_cc_cx_gmu_clk, 0xf);
qcom_branch_set_sleep(regmap, gpu_cc_cx_gmu_clk, 0xf);
qcom_branch_set_force_mem_core(regmap, gpu_cc_gx_gfx3d_clk, true);
qcom_branch_set_force_periph_on(regmap, gpu_cc_gx_gfx3d_clk, true);
return qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap);
}
static struct platform_driver gpu_cc_sm6115_driver = {
.probe = gpu_cc_sm6115_probe,
.driver = {
.name = "sm6115-gpucc",
.of_match_table = gpu_cc_sm6115_match_table,
},
};
module_platform_driver(gpu_cc_sm6115_driver);
MODULE_DESCRIPTION("QTI GPU_CC SM6115 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/gpucc-sm6115.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm8450-videocc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
};
enum {
P_BI_TCXO,
P_VIDEO_CC_PLL0_OUT_MAIN,
P_VIDEO_CC_PLL1_OUT_MAIN,
};
static const struct pll_vco lucid_ole_vco[] = {
{ 249600000, 2300000000, 0 },
};
static const struct alpha_pll_config video_cc_pll0_config = {
/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
.l = 0x44440025,
.alpha = 0x8000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll video_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct alpha_pll_config video_cc_pll1_config = {
/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
.l = 0x44440036,
.alpha = 0xb000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000003,
.test_ctl_hi1_val = 0x00009000,
.test_ctl_hi2_val = 0x00000034,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll video_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_pll1",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct parent_map video_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data video_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .hw = &video_cc_pll0.clkr.hw },
};
static const struct parent_map video_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_CC_PLL1_OUT_MAIN, 1 },
};
static const struct clk_parent_data video_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &video_cc_pll1.clkr.hw },
};
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs0_clk_src = {
.cmd_rcgr = 0x8000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_0,
.freq_tbl = ftbl_video_cc_mvs0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_clk_src",
.parent_data = video_cc_parent_data_0,
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs1_clk_src = {
.cmd_rcgr = 0x8018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_1,
.freq_tbl = ftbl_video_cc_mvs1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1_clk_src",
.parent_data = video_cc_parent_data_1,
.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
.reg = 0x80c4,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
.reg = 0x8070,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_div2_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
.reg = 0x80ec,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
.reg = 0x809c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1c_div2_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch video_cc_mvs0_clk = {
.halt_reg = 0x80b8,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x80b8,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x80b8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0c_clk = {
.halt_reg = 0x8064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0c_div2_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs1_clk = {
.halt_reg = 0x80e0,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x80e0,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x80e0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs1_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs1c_clk = {
.halt_reg = 0x8090,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8090,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1c_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs1c_div2_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc video_cc_mvs0c_gdsc = {
.gdscr = 0x804c,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x6,
.pd = {
.name = "video_cc_mvs0c_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc video_cc_mvs0_gdsc = {
.gdscr = 0x80a4,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x6,
.pd = {
.name = "video_cc_mvs0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &video_cc_mvs0c_gdsc.pd,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL,
};
static struct gdsc video_cc_mvs1c_gdsc = {
.gdscr = 0x8078,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x6,
.pd = {
.name = "video_cc_mvs1c_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc video_cc_mvs1_gdsc = {
.gdscr = 0x80cc,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x6,
.pd = {
.name = "video_cc_mvs1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &video_cc_mvs1c_gdsc.pd,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL,
};
static struct clk_regmap *video_cc_sm8550_clocks[] = {
[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
[VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
[VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
[VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
[VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
[VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
[VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
};
static struct gdsc *video_cc_sm8550_gdscs[] = {
[VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,
[VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,
[VIDEO_CC_MVS1C_GDSC] = &video_cc_mvs1c_gdsc,
[VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc,
};
static const struct qcom_reset_map video_cc_sm8550_resets[] = {
[CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80f0 },
[CVP_VIDEO_CC_MVS0_BCR] = { 0x80a0 },
[CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
[CVP_VIDEO_CC_MVS1_BCR] = { 0x80c8 },
[CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 },
[VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
[VIDEO_CC_MVS1C_CLK_ARES] = { 0x8090, 2 },
};
static const struct regmap_config video_cc_sm8550_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9f4c,
.fast_io = true,
};
static struct qcom_cc_desc video_cc_sm8550_desc = {
.config = &video_cc_sm8550_regmap_config,
.clks = video_cc_sm8550_clocks,
.num_clks = ARRAY_SIZE(video_cc_sm8550_clocks),
.resets = video_cc_sm8550_resets,
.num_resets = ARRAY_SIZE(video_cc_sm8550_resets),
.gdscs = video_cc_sm8550_gdscs,
.num_gdscs = ARRAY_SIZE(video_cc_sm8550_gdscs),
};
static const struct of_device_id video_cc_sm8550_match_table[] = {
{ .compatible = "qcom,sm8550-videocc" },
{ }
};
MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table);
static int video_cc_sm8550_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
regmap = qcom_cc_map(pdev, &video_cc_sm8550_desc);
if (IS_ERR(regmap)) {
pm_runtime_put(&pdev->dev);
return PTR_ERR(regmap);
}
clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
/*
* Keep clocks always enabled:
* video_cc_ahb_clk
* video_cc_sleep_clk
* video_cc_xo_clk
*/
regmap_update_bits(regmap, 0x80f4, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x8140, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x8124, BIT(0), BIT(0));
ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap);
pm_runtime_put(&pdev->dev);
return ret;
}
static struct platform_driver video_cc_sm8550_driver = {
.probe = video_cc_sm8550_probe,
.driver = {
.name = "video_cc-sm8550",
.of_match_table = video_cc_sm8550_match_table,
},
};
static int __init video_cc_sm8550_init(void)
{
return platform_driver_register(&video_cc_sm8550_driver);
}
subsys_initcall(video_cc_sm8550_init);
static void __exit video_cc_sm8550_exit(void)
{
platform_driver_unregister(&video_cc_sm8550_driver);
}
module_exit(video_cc_sm8550_exit);
MODULE_DESCRIPTION("QTI VIDEOCC SM8550 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/videocc-sm8550.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm8450-videocc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
};
enum {
P_BI_TCXO,
P_VIDEO_CC_PLL0_OUT_MAIN,
P_VIDEO_CC_PLL1_OUT_MAIN,
};
static const struct pll_vco lucid_evo_vco[] = {
{ 249600000, 2020000000, 0 },
};
static const struct alpha_pll_config video_cc_pll0_config = {
/* .l includes CAL_L_VAL, L_VAL fields */
.l = 0x0044001e,
.alpha = 0x0,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll video_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct alpha_pll_config video_cc_pll1_config = {
/* .l includes CAL_L_VAL, L_VAL fields */
.l = 0x0044002b,
.alpha = 0xc000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
};
static struct clk_alpha_pll video_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_pll1",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct parent_map video_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data video_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .hw = &video_cc_pll0.clkr.hw },
};
static const struct parent_map video_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_VIDEO_CC_PLL1_OUT_MAIN, 1 },
};
static const struct clk_parent_data video_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &video_cc_pll1.clkr.hw },
};
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
F(576000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs0_clk_src = {
.cmd_rcgr = 0x8000,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_0,
.freq_tbl = ftbl_video_cc_mvs0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_clk_src",
.parent_data = video_cc_parent_data_0,
.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs1_clk_src = {
.cmd_rcgr = 0x8018,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_1,
.freq_tbl = ftbl_video_cc_mvs1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1_clk_src",
.parent_data = video_cc_parent_data_1,
.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
.reg = 0x80b8,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
.reg = 0x806c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_div2_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
.reg = 0x80dc,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
.reg = 0x8094,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1c_div2_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch video_cc_mvs0_clk = {
.halt_reg = 0x80b0,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x80b0,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x80b0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0c_clk = {
.halt_reg = 0x8064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs0c_div2_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs1_clk = {
.halt_reg = 0x80d4,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x80d4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x80d4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs1_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs1c_clk = {
.halt_reg = 0x808c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x808c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1c_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_mvs1c_div2_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc video_cc_mvs0c_gdsc = {
.gdscr = 0x804c,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x6,
.pd = {
.name = "video_cc_mvs0c_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc video_cc_mvs0_gdsc = {
.gdscr = 0x809c,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x6,
.pd = {
.name = "video_cc_mvs0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &video_cc_mvs0c_gdsc.pd,
.flags = RETAIN_FF_ENABLE | HW_CTRL,
};
static struct gdsc video_cc_mvs1c_gdsc = {
.gdscr = 0x8074,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x6,
.pd = {
.name = "video_cc_mvs1c_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc video_cc_mvs1_gdsc = {
.gdscr = 0x80c0,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x6,
.pd = {
.name = "video_cc_mvs1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &video_cc_mvs1c_gdsc.pd,
.flags = RETAIN_FF_ENABLE | HW_CTRL,
};
static struct clk_regmap *video_cc_sm8450_clocks[] = {
[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
[VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
[VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
[VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
[VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
[VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
[VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
};
static struct gdsc *video_cc_sm8450_gdscs[] = {
[VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,
[VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,
[VIDEO_CC_MVS1C_GDSC] = &video_cc_mvs1c_gdsc,
[VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc,
};
static const struct qcom_reset_map video_cc_sm8450_resets[] = {
[CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80e0 },
[CVP_VIDEO_CC_MVS0_BCR] = { 0x8098 },
[CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
[CVP_VIDEO_CC_MVS1_BCR] = { 0x80bc },
[CVP_VIDEO_CC_MVS1C_BCR] = { 0x8070 },
[VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
[VIDEO_CC_MVS1C_CLK_ARES] = { 0x808c, 2 },
};
static const struct regmap_config video_cc_sm8450_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9f4c,
.fast_io = true,
};
static struct qcom_cc_desc video_cc_sm8450_desc = {
.config = &video_cc_sm8450_regmap_config,
.clks = video_cc_sm8450_clocks,
.num_clks = ARRAY_SIZE(video_cc_sm8450_clocks),
.resets = video_cc_sm8450_resets,
.num_resets = ARRAY_SIZE(video_cc_sm8450_resets),
.gdscs = video_cc_sm8450_gdscs,
.num_gdscs = ARRAY_SIZE(video_cc_sm8450_gdscs),
};
static const struct of_device_id video_cc_sm8450_match_table[] = {
{ .compatible = "qcom,sm8450-videocc" },
{ }
};
MODULE_DEVICE_TABLE(of, video_cc_sm8450_match_table);
static int video_cc_sm8450_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
regmap = qcom_cc_map(pdev, &video_cc_sm8450_desc);
if (IS_ERR(regmap)) {
pm_runtime_put(&pdev->dev);
return PTR_ERR(regmap);
}
clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
/*
* Keep clocks always enabled:
* video_cc_ahb_clk
* video_cc_sleep_clk
* video_cc_xo_clk
*/
regmap_update_bits(regmap, 0x80e4, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x8130, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x8114, BIT(0), BIT(0));
ret = qcom_cc_really_probe(pdev, &video_cc_sm8450_desc, regmap);
pm_runtime_put(&pdev->dev);
return ret;
}
static struct platform_driver video_cc_sm8450_driver = {
.probe = video_cc_sm8450_probe,
.driver = {
.name = "video_cc-sm8450",
.of_match_table = video_cc_sm8450_match_table,
},
};
static int __init video_cc_sm8450_init(void)
{
return platform_driver_register(&video_cc_sm8450_driver);
}
subsys_initcall(video_cc_sm8450_init);
static void __exit video_cc_sm8450_exit(void)
{
platform_driver_unregister(&video_cc_sm8450_driver);
}
module_exit(video_cc_sm8450_exit);
MODULE_DESCRIPTION("QTI VIDEOCC SM8450 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/videocc-sm8450.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_DISP_CC_PLL0_OUT_MAIN,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
P_DSI1_PHY_PLL_OUT_BYTECLK,
P_DSI1_PHY_PLL_OUT_DSICLK,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_DP_PHY_PLL_LINK_CLK,
P_DP_PHY_PLL_VCO_DIV_CLK,
};
static struct clk_alpha_pll disp_cc_pll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "disp_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo", .name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
};
static const struct parent_map disp_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
{ P_DSI1_PHY_PLL_OUT_BYTECLK, 2 },
};
static const struct clk_parent_data disp_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .fw_name = "dsi0_phy_pll_out_byteclk", .name = "dsi0_phy_pll_out_byteclk" },
{ .fw_name = "dsi1_phy_pll_out_byteclk", .name = "dsi1_phy_pll_out_byteclk" },
};
static const struct parent_map disp_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_DP_PHY_PLL_LINK_CLK, 1 },
{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
};
static const struct clk_parent_data disp_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .fw_name = "dp_link_clk_divsel_ten", .name = "dp_link_clk_divsel_ten" },
{ .fw_name = "dp_vco_divided_clk_src_mux", .name = "dp_vco_divided_clk_src_mux" },
};
static const struct parent_map disp_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_2[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
};
static const struct parent_map disp_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_MAIN, 4 },
{ P_GPLL0_OUT_MAIN_DIV, 5 },
};
static const struct clk_parent_data disp_cc_parent_data_3[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &disp_cc_pll0.clkr.hw },
{ .fw_name = "gcc_disp_gpll0_clk_src", .name = "gcc_disp_gpll0_clk_src" },
{ .fw_name = "gcc_disp_gpll0_div_clk_src", .name = "gcc_disp_gpll0_div_clk_src" },
};
static const struct parent_map disp_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
{ P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
};
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .fw_name = "dsi0_phy_pll_out_dsiclk", .name = "dsi0_phy_pll_out_dsiclk" },
{ .fw_name = "dsi1_phy_pll_out_dsiclk", .name = "dsi1_phy_pll_out_dsiclk" },
};
/* Return the HW recalc rate for idle use case */
static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
.cmd_rcgr = 0x20d0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
/* Return the HW recalc rate for idle use case */
static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
.cmd_rcgr = 0x20ec,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte1_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
.cmd_rcgr = 0x219c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_aux_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
.cmd_rcgr = 0x2154,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_crypto_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
.cmd_rcgr = 0x2138,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
.cmd_rcgr = 0x2184,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel1_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
.cmd_rcgr = 0x216c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.cmd_rcgr = 0x2108,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
.cmd_rcgr = 0x2120,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc1_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(85714286, P_GPLL0_OUT_MAIN, 7, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
F(344000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
F(430000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.cmd_rcgr = 0x2088,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
/* Return the HW recalc rate for idle use case */
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.cmd_rcgr = 0x2058,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
};
/* Return the HW recalc rate for idle use case */
static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
.cmd_rcgr = 0x2070,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk1_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
F(344000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
F(430000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
.cmd_rcgr = 0x20a0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
.cmd_rcgr = 0x20b8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch disp_cc_mdss_ahb_clk = {
.halt_reg = 0x4004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_axi_clk = {
.halt_reg = 0x4008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
/* Return the HW recalc rate for idle use case */
static struct clk_branch disp_cc_mdss_byte0_clk = {
.halt_reg = 0x2028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* Return the HW recalc rate for idle use case */
static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
.reg = 0x20e8,
.shift = 0,
.width = 2,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
},
};
/* Return the HW recalc rate for idle use case */
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
.halt_reg = 0x202c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x202c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* Return the HW recalc rate for idle use case */
static struct clk_branch disp_cc_mdss_byte1_clk = {
.halt_reg = 0x2030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* Return the HW recalc rate for idle use case */
static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
.reg = 0x2104,
.shift = 0,
.width = 2,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte1_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
},
};
/* Return the HW recalc rate for idle use case */
static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
.halt_reg = 0x2034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte1_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte1_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_aux_clk = {
.halt_reg = 0x2054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
.halt_reg = 0x2048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_crypto_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_link_clk = {
.halt_reg = 0x2040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 (div 4) */
static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
.halt_reg = 0x2044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_pixel1_clk = {
.halt_reg = 0x2050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_pixel1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
.halt_reg = 0x204c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x204c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_esc0_clk = {
.halt_reg = 0x2038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_esc1_clk = {
.halt_reg = 0x203c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x203c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_esc1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_clk = {
.halt_reg = 0x200c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
.halt_reg = 0x201c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_lut_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
/* Return the HW recalc rate for idle use case */
static struct clk_branch disp_cc_mdss_pclk0_clk = {
.halt_reg = 0x2004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* Return the HW recalc rate for idle use case */
static struct clk_branch disp_cc_mdss_pclk1_clk = {
.halt_reg = 0x2008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_pclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rot_clk = {
.halt_reg = 0x2014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_rot_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
.halt_reg = 0x5004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rscc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
.halt_reg = 0x5008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rscc_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_vsync_clk = {
.halt_reg = 0x2024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x3000,
.pd = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL | POLL_CFG_GDSCR,
};
static struct clk_regmap *disp_cc_sdm845_clocks[] = {
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
[DISP_CC_MDSS_AXI_CLK] = &disp_cc_mdss_axi_clk.clkr,
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] =
&disp_cc_mdss_byte0_div_clk_src.clkr,
[DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
[DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
[DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] =
&disp_cc_mdss_byte1_div_clk_src.clkr,
[DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
[DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
[DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
[DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] =
&disp_cc_mdss_dp_crypto_clk_src.clkr,
[DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
[DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
[DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
[DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr,
[DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] =
&disp_cc_mdss_dp_pixel1_clk_src.clkr,
[DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
[DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
[DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
[DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
[DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
[DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
};
static const struct qcom_reset_map disp_cc_sdm845_resets[] = {
[DISP_CC_MDSS_RSCC_BCR] = { 0x5000 },
};
static struct gdsc *disp_cc_sdm845_gdscs[] = {
[MDSS_GDSC] = &mdss_gdsc,
};
static const struct regmap_config disp_cc_sdm845_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x10000,
.fast_io = true,
};
static const struct qcom_cc_desc disp_cc_sdm845_desc = {
.config = &disp_cc_sdm845_regmap_config,
.clks = disp_cc_sdm845_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sdm845_clocks),
.resets = disp_cc_sdm845_resets,
.num_resets = ARRAY_SIZE(disp_cc_sdm845_resets),
.gdscs = disp_cc_sdm845_gdscs,
.num_gdscs = ARRAY_SIZE(disp_cc_sdm845_gdscs),
};
static const struct of_device_id disp_cc_sdm845_match_table[] = {
{ .compatible = "qcom,sdm845-dispcc" },
{ }
};
MODULE_DEVICE_TABLE(of, disp_cc_sdm845_match_table);
static int disp_cc_sdm845_probe(struct platform_device *pdev)
{
struct regmap *regmap;
struct alpha_pll_config disp_cc_pll0_config = {};
regmap = qcom_cc_map(pdev, &disp_cc_sdm845_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
disp_cc_pll0_config.l = 0x2c;
disp_cc_pll0_config.alpha = 0xcaaa;
clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
/* Enable hardware clock gating for DSI and MDP clocks */
regmap_update_bits(regmap, 0x8000, 0x7f0, 0x7f0);
return qcom_cc_really_probe(pdev, &disp_cc_sdm845_desc, regmap);
}
static struct platform_driver disp_cc_sdm845_driver = {
.probe = disp_cc_sdm845_probe,
.driver = {
.name = "disp_cc-sdm845",
.of_match_table = disp_cc_sdm845_match_table,
},
};
static int __init disp_cc_sdm845_init(void)
{
return platform_driver_register(&disp_cc_sdm845_driver);
}
subsys_initcall(disp_cc_sdm845_init);
static void __exit disp_cc_sdm845_exit(void)
{
platform_driver_unregister(&disp_cc_sdm845_driver);
}
module_exit(disp_cc_sdm845_exit);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("QTI DISPCC SDM845 Driver");
| linux-master | drivers/clk/qcom/dispcc-sdm845.c |
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/ctype.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-msm8994.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-alpha-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_XO,
P_GPLL0,
P_GPLL4,
};
static struct clk_alpha_pll gpll0_early = {
.offset = 0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x1480,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_early",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_hws = (const struct clk_hw*[]){
&gpll0_early.clkr.hw
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
},
};
static struct clk_alpha_pll gpll4_early = {
.offset = 0x1dc0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x1480,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gpll4_early",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x1dc0,
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_hws = (const struct clk_hw*[]){
&gpll4_early.clkr.hw
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
},
};
static const struct parent_map gcc_xo_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
};
static const struct clk_parent_data gcc_xo_gpll0[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 5 },
};
static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
};
static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(171430000, P_GPLL0, 3.5, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(240000000, P_GPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 ufs_axi_clk_src = {
.cmd_rcgr = 0x1d68,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_ufs_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "ufs_axi_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_usb30_master_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(125000000, P_GPLL0, 1, 5, 24),
{ }
};
static struct clk_rcg2 usb30_master_clk_src = {
.cmd_rcgr = 0x03d4,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_usb30_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_master_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x0660,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(15000000, P_GPLL0, 10, 1, 4),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 12.5, 1, 2),
F(25000000, P_GPLL0, 12, 1, 2),
F(48000000, P_GPLL0, 12.5, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
{ }
};
static struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src_8992[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(15000000, P_GPLL0, 10, 1, 4),
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0, 12, 1, 2),
F(50000000, P_GPLL0, 12, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x064c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x06e0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(15000000, P_GPLL0, 10, 1, 4),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 12.5, 1, 2),
F(25000000, P_GPLL0, 12, 1, 2),
F(42860000, P_GPLL0, 14, 0, 0),
F(46150000, P_GPLL0, 13, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x06cc,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x0760,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_blsp1_qup3_4_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(15000000, P_GPLL0, 10, 1, 4),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 12.5, 1, 2),
F(25000000, P_GPLL0, 12, 1, 2),
F(42860000, P_GPLL0, 14, 0, 0),
F(44440000, P_GPLL0, 13.5, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x074c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x07e0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x07cc,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
.cmd_rcgr = 0x0860,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(15000000, P_GPLL0, 10, 1, 4),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 12.5, 1, 2),
F(25000000, P_GPLL0, 12, 1, 2),
F(40000000, P_GPLL0, 15, 0, 0),
F(42860000, P_GPLL0, 14, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
.cmd_rcgr = 0x084c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup5_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
.cmd_rcgr = 0x08e0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(15000000, P_GPLL0, 10, 1, 4),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 12.5, 1, 2),
F(27906976, P_GPLL0, 1, 2, 43),
F(41380000, P_GPLL0, 15, 0, 0),
F(42860000, P_GPLL0, 14, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
.cmd_rcgr = 0x08cc,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp1_qup6_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
F(3686400, P_GPLL0, 1, 96, 15625),
F(7372800, P_GPLL0, 1, 192, 15625),
F(14745600, P_GPLL0, 1, 384, 15625),
F(16000000, P_GPLL0, 5, 2, 15),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 5, 1, 5),
F(32000000, P_GPLL0, 1, 4, 75),
F(40000000, P_GPLL0, 15, 0, 0),
F(46400000, P_GPLL0, 1, 29, 375),
F(48000000, P_GPLL0, 12.5, 0, 0),
F(51200000, P_GPLL0, 1, 32, 375),
F(56000000, P_GPLL0, 1, 7, 75),
F(58982400, P_GPLL0, 1, 1536, 15625),
F(60000000, P_GPLL0, 10, 0, 0),
F(63160000, P_GPLL0, 9.5, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x068c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x070c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
.cmd_rcgr = 0x078c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart3_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
.cmd_rcgr = 0x080c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart4_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
.cmd_rcgr = 0x088c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart5_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
.cmd_rcgr = 0x090c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart6_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x09a0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_blsp2_qup1_2_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(15000000, P_GPLL0, 10, 1, 4),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 12.5, 1, 2),
F(25000000, P_GPLL0, 12, 1, 2),
F(42860000, P_GPLL0, 14, 0, 0),
F(44440000, P_GPLL0, 13.5, 0, 0),
{ }
};
static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x098c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x0a20,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x0a0c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_blsp2_qup3_4_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(15000000, P_GPLL0, 10, 1, 4),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 12.5, 1, 2),
F(25000000, P_GPLL0, 12, 1, 2),
F(42860000, P_GPLL0, 14, 0, 0),
F(48000000, P_GPLL0, 12.5, 0, 0),
{ }
};
static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x0aa0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x0a8c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x0b20,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x0b0c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
.cmd_rcgr = 0x0ba0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup5_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
.cmd_rcgr = 0x0b8c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
/* BLSP1 QUP1 and BLSP2 QUP5 use the same freqs */
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup5_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
.cmd_rcgr = 0x0c20,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup6_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(15000000, P_GPLL0, 10, 1, 4),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 12.5, 1, 2),
F(25000000, P_GPLL0, 12, 1, 2),
F(44440000, P_GPLL0, 13.5, 0, 0),
F(48000000, P_GPLL0, 12.5, 0, 0),
{ }
};
static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
.cmd_rcgr = 0x0c0c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp2_qup6_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup6_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
.cmd_rcgr = 0x09cc,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
.cmd_rcgr = 0x0a4c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
.cmd_rcgr = 0x0acc,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart3_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
.cmd_rcgr = 0x0b4c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart4_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
.cmd_rcgr = 0x0bcc,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart5_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
.cmd_rcgr = 0x0c4c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart6_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_gp1_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x1904,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_gp2_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 gp2_clk_src = {
.cmd_rcgr = 0x1944,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gp2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_gp3_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 gp3_clk_src = {
.cmd_rcgr = 0x1984,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gp3_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
F(1011000, P_XO, 1, 1, 19),
{ }
};
static struct clk_rcg2 pcie_0_aux_clk_src = {
.cmd_rcgr = 0x1b00,
.mnd_width = 8,
.hid_width = 5,
.freq_tbl = ftbl_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_0_aux_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
F(125000000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 pcie_0_pipe_clk_src = {
.cmd_rcgr = 0x1adc,
.hid_width = 5,
.freq_tbl = ftbl_pcie_pipe_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_0_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
F(1011000, P_XO, 1, 1, 19),
{ }
};
static struct clk_rcg2 pcie_1_aux_clk_src = {
.cmd_rcgr = 0x1b80,
.mnd_width = 8,
.hid_width = 5,
.freq_tbl = ftbl_pcie_1_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_1_aux_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 pcie_1_pipe_clk_src = {
.cmd_rcgr = 0x1b5c,
.hid_width = 5,
.freq_tbl = ftbl_pcie_pipe_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_1_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_pdm2_clk_src[] = {
F(60000000, P_GPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 pdm2_clk_src = {
.cmd_rcgr = 0x0cd0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0, 15, 1, 2),
F(25000000, P_GPLL0, 12, 1, 2),
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(192000000, P_GPLL4, 2, 0, 0),
F(384000000, P_GPLL4, 1, 0, 0),
{ }
};
static struct freq_tbl ftbl_sdcc1_apps_clk_src_8992[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0, 15, 1, 2),
F(25000000, P_GPLL0, 12, 1, 2),
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(172000000, P_GPLL4, 2, 0, 0),
F(344000000, P_GPLL4, 1, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x04d0,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_map,
.freq_tbl = ftbl_sdcc1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_xo_gpll0_gpll4,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
.ops = &clk_rcg2_floor_ops,
},
};
static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0, 15, 1, 2),
F(25000000, P_GPLL0, 12, 1, 2),
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 sdcc2_apps_clk_src = {
.cmd_rcgr = 0x0510,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_sdcc2_4_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
};
static struct clk_rcg2 sdcc3_apps_clk_src = {
.cmd_rcgr = 0x0550,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_sdcc2_4_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc3_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
};
static struct clk_rcg2 sdcc4_apps_clk_src = {
.cmd_rcgr = 0x0590,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_sdcc2_4_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc4_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
};
static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
F(105500, P_XO, 1, 1, 182),
{ }
};
static struct clk_rcg2 tsif_ref_clk_src = {
.cmd_rcgr = 0x0d90,
.mnd_width = 8,
.hid_width = 5,
.freq_tbl = ftbl_tsif_ref_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "tsif_ref_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(60000000, P_GPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 usb30_mock_utmi_clk_src = {
.cmd_rcgr = 0x03e8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_mock_utmi_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
F(1200000, P_XO, 16, 0, 0),
{ }
};
static struct clk_rcg2 usb3_phy_aux_clk_src = {
.cmd_rcgr = 0x1414,
.hid_width = 5,
.freq_tbl = ftbl_usb3_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb3_phy_aux_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
F(75000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 usb_hs_system_clk_src = {
.cmd_rcgr = 0x0490,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_usb_hs_system_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hs_system_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x05c4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x0648,
.clkr = {
.enable_reg = 0x0648,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x0644,
.clkr = {
.enable_reg = 0x0644,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x06c8,
.clkr = {
.enable_reg = 0x06c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x06c4,
.clkr = {
.enable_reg = 0x06c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x0748,
.clkr = {
.enable_reg = 0x0748,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x0744,
.clkr = {
.enable_reg = 0x0744,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.halt_reg = 0x07c8,
.clkr = {
.enable_reg = 0x07c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.halt_reg = 0x07c4,
.clkr = {
.enable_reg = 0x07c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
.halt_reg = 0x0848,
.clkr = {
.enable_reg = 0x0848,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
.halt_reg = 0x0844,
.clkr = {
.enable_reg = 0x0844,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
.halt_reg = 0x08c8,
.clkr = {
.enable_reg = 0x08c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
.halt_reg = 0x08c4,
.clkr = {
.enable_reg = 0x08c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x0684,
.clkr = {
.enable_reg = 0x0684,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x0704,
.clkr = {
.enable_reg = 0x0704,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart3_apps_clk = {
.halt_reg = 0x0784,
.clkr = {
.enable_reg = 0x0784,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart4_apps_clk = {
.halt_reg = 0x0804,
.clkr = {
.enable_reg = 0x0804,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart4_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart5_apps_clk = {
.halt_reg = 0x0884,
.clkr = {
.enable_reg = 0x0884,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart5_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart6_apps_clk = {
.halt_reg = 0x0904,
.clkr = {
.enable_reg = 0x0904,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart6_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_ahb_clk = {
.halt_reg = 0x0944,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
.halt_reg = 0x0988,
.clkr = {
.enable_reg = 0x0988,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
.halt_reg = 0x0984,
.clkr = {
.enable_reg = 0x0984,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
.halt_reg = 0x0a08,
.clkr = {
.enable_reg = 0x0a08,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
.halt_reg = 0x0a04,
.clkr = {
.enable_reg = 0x0a04,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
.halt_reg = 0x0a88,
.clkr = {
.enable_reg = 0x0a88,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
.halt_reg = 0x0a84,
.clkr = {
.enable_reg = 0x0a84,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
.halt_reg = 0x0b08,
.clkr = {
.enable_reg = 0x0b08,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
.halt_reg = 0x0b04,
.clkr = {
.enable_reg = 0x0b04,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
.halt_reg = 0x0b88,
.clkr = {
.enable_reg = 0x0b88,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup5_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
.halt_reg = 0x0b84,
.clkr = {
.enable_reg = 0x0b84,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup5_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
.halt_reg = 0x0c08,
.clkr = {
.enable_reg = 0x0c08,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup6_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
.halt_reg = 0x0c04,
.clkr = {
.enable_reg = 0x0c04,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup6_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart1_apps_clk = {
.halt_reg = 0x09c4,
.clkr = {
.enable_reg = 0x09c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart1_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp2_uart1_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart2_apps_clk = {
.halt_reg = 0x0a44,
.clkr = {
.enable_reg = 0x0a44,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart2_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp2_uart2_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart3_apps_clk = {
.halt_reg = 0x0ac4,
.clkr = {
.enable_reg = 0x0ac4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart3_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp2_uart3_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart4_apps_clk = {
.halt_reg = 0x0b44,
.clkr = {
.enable_reg = 0x0b44,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart4_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp2_uart4_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart5_apps_clk = {
.halt_reg = 0x0bc4,
.clkr = {
.enable_reg = 0x0bc4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart5_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp2_uart5_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart6_apps_clk = {
.halt_reg = 0x0c44,
.clkr = {
.enable_reg = 0x0c44,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart6_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &blsp2_uart6_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x1900,
.clkr = {
.enable_reg = 0x1900,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x1940,
.clkr = {
.enable_reg = 0x1940,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x1980,
.clkr = {
.enable_reg = 0x1980,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_lpass_q6_axi_clk = {
.halt_reg = 0x0280,
.clkr = {
.enable_reg = 0x0280,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_lpass_q6_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.halt_reg = 0x0284,
.clkr = {
.enable_reg = 0x0284,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_q6_bimc_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_aux_clk = {
.halt_reg = 0x1ad4,
.clkr = {
.enable_reg = 0x1ad4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk",
.parent_hws = (const struct clk_hw *[]){ &pcie_0_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.halt_reg = 0x1ad0,
.clkr = {
.enable_reg = 0x1ad0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.halt_reg = 0x1acc,
.clkr = {
.enable_reg = 0x1acc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_pipe_clk = {
.halt_reg = 0x1ad8,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1ad8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
.parent_hws = (const struct clk_hw *[]){ &pcie_0_pipe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.halt_reg = 0x1ac8,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1ac8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_aux_clk = {
.halt_reg = 0x1b54,
.clkr = {
.enable_reg = 0x1b54,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk",
.parent_hws = (const struct clk_hw *[]){ &pcie_1_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
.halt_reg = 0x1b54,
.clkr = {
.enable_reg = 0x1b54,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
.halt_reg = 0x1b50,
.clkr = {
.enable_reg = 0x1b50,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_pipe_clk = {
.halt_reg = 0x1b58,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1b58,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk",
.parent_hws = (const struct clk_hw *[]){ &pcie_1_pipe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_axi_clk = {
.halt_reg = 0x1b48,
.clkr = {
.enable_reg = 0x1b48,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x0ccc,
.clkr = {
.enable_reg = 0x0ccc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x0cc4,
.clkr = {
.enable_reg = 0x0cc4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x04c4,
.clkr = {
.enable_reg = 0x04c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x04c8,
.clkr = {
.enable_reg = 0x04c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x0508,
.clkr = {
.enable_reg = 0x0508,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x0504,
.clkr = {
.enable_reg = 0x0504,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc3_ahb_clk = {
.halt_reg = 0x0548,
.clkr = {
.enable_reg = 0x0548,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc3_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc3_apps_clk = {
.halt_reg = 0x0544,
.clkr = {
.enable_reg = 0x0544,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc3_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &sdcc3_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_ahb_clk = {
.halt_reg = 0x0588,
.clkr = {
.enable_reg = 0x0588,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_apps_clk = {
.halt_reg = 0x0584,
.clkr = {
.enable_reg = 0x0584,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk",
.parent_hws = (const struct clk_hw *[]){ &sdcc4_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
.halt_reg = 0x1d7c,
.clkr = {
.enable_reg = 0x1d7c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_ufs_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
.halt_reg = 0x03fc,
.clkr = {
.enable_reg = 0x03fc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb3_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ahb_clk = {
.halt_reg = 0x0d84,
.clkr = {
.enable_reg = 0x0d84,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ref_clk = {
.halt_reg = 0x0d88,
.clkr = {
.enable_reg = 0x0d88,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ref_clk",
.parent_hws = (const struct clk_hw *[]){ &tsif_ref_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_ahb_clk = {
.halt_reg = 0x1d4c,
.clkr = {
.enable_reg = 0x1d4c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_axi_clk = {
.halt_reg = 0x1d48,
.clkr = {
.enable_reg = 0x1d48,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_rx_cfg_clk = {
.halt_reg = 0x1d54,
.clkr = {
.enable_reg = 0x1d54,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_cfg_clk",
.parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
.halt_reg = 0x1d60,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1d60,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
.halt_reg = 0x1d64,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1d64,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_symbol_1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_tx_cfg_clk = {
.halt_reg = 0x1d50,
.clkr = {
.enable_reg = 0x1d50,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_cfg_clk",
.parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
.halt_reg = 0x1d58,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1d58,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
.halt_reg = 0x1d5c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1d5c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_symbol_1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb2_hs_phy_sleep_clk = {
.halt_reg = 0x04ac,
.clkr = {
.enable_reg = 0x04ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb2_hs_phy_sleep_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep",
.name = "sleep"
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_master_clk = {
.halt_reg = 0x03c8,
.clkr = {
.enable_reg = 0x03c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_master_clk",
.parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_mock_utmi_clk = {
.halt_reg = 0x03d0,
.clkr = {
.enable_reg = 0x03d0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mock_utmi_clk",
.parent_hws = (const struct clk_hw *[]){ &usb30_mock_utmi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sleep_clk = {
.halt_reg = 0x03cc,
.clkr = {
.enable_reg = 0x03cc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sleep_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep",
.name = "sleep"
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_phy_aux_clk = {
.halt_reg = 0x1408,
.clkr = {
.enable_reg = 0x1408,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_aux_clk",
.parent_hws = (const struct clk_hw *[]){ &usb3_phy_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_phy_pipe_clk = {
.halt_reg = 0x140c,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x140c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_ahb_clk = {
.halt_reg = 0x0488,
.clkr = {
.enable_reg = 0x0488,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_system_clk = {
.halt_reg = 0x0484,
.clkr = {
.enable_reg = 0x0484,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_system_clk",
.parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
.halt_reg = 0x1a84,
.clkr = {
.enable_reg = 0x1a84,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_phy_cfg_ahb2phy_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpll0_out_mmsscc = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gpll0_out_mmsscc",
.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpll0_out_msscc = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gpll0_out_msscc",
.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch pcie_0_phy_ldo = {
.halt_reg = 0x1e00,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x1E00,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "pcie_0_phy_ldo",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch pcie_1_phy_ldo = {
.halt_reg = 0x1e04,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x1E04,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "pcie_1_phy_ldo",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch ufs_phy_ldo = {
.halt_reg = 0x1e0c,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x1E0C,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "ufs_phy_ldo",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch usb_ss_phy_ldo = {
.halt_reg = 0x1e08,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x1E08,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "usb_ss_phy_ldo",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x0e04,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x0e04,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x0d04,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x1ac4,
.pd = {
.name = "pcie_0",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc pcie_1_gdsc = {
.gdscr = 0x1b44,
.pd = {
.name = "pcie_1",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc usb30_gdsc = {
.gdscr = 0x3c4,
.pd = {
.name = "usb30",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc ufs_gdsc = {
.gdscr = 0x1d44,
.pd = {
.name = "ufs",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *gcc_msm8994_clocks[] = {
[GPLL0_EARLY] = &gpll0_early.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL4_EARLY] = &gpll4_early.clkr,
[GPLL4] = &gpll4.clkr,
[UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
[BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
[BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
[BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
[BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
[BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
[BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
[BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
[BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
[BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
[BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
[BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
[BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
[BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
[BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
[BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
[BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
[BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
[BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
[PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
[PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
[PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
[PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
[SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
[SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
[TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
[USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
[USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
[GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
[GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
[GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
[GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
[GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
[GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
[GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
[GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
[GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
[GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
[GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
[GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
[GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
[GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
[GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
[GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
[GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
[GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
[GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
[GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
[GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
[GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
[GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr,
[GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr,
[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
[GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
[GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
[GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
[GPLL0_OUT_MMSSCC] = &gpll0_out_mmsscc.clkr,
[GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr,
[PCIE_0_PHY_LDO] = &pcie_0_phy_ldo.clkr,
[PCIE_1_PHY_LDO] = &pcie_1_phy_ldo.clkr,
[UFS_PHY_LDO] = &ufs_phy_ldo.clkr,
[USB_SS_PHY_LDO] = &usb_ss_phy_ldo.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
/*
* The following clocks should NOT be managed by this driver, but they once were
* mistakengly added. Now they are only here to indicate that they are not defined
* on purpose, even though the names will stay in the header file (for ABI sanity).
*/
[CONFIG_NOC_CLK_SRC] = NULL,
[PERIPH_NOC_CLK_SRC] = NULL,
[SYSTEM_NOC_CLK_SRC] = NULL,
};
static struct gdsc *gcc_msm8994_gdscs[] = {
/* This GDSC does not exist, but ABI has to remain intact */
[PCIE_GDSC] = NULL,
[PCIE_0_GDSC] = &pcie_0_gdsc,
[PCIE_1_GDSC] = &pcie_1_gdsc,
[USB30_GDSC] = &usb30_gdsc,
[UFS_GDSC] = &ufs_gdsc,
};
static const struct qcom_reset_map gcc_msm8994_resets[] = {
[USB3_PHY_RESET] = { 0x1400 },
[USB3PHY_PHY_RESET] = { 0x1404 },
[MSS_RESET] = { 0x1680 },
[PCIE_PHY_0_RESET] = { 0x1b18 },
[PCIE_PHY_1_RESET] = { 0x1b98 },
[QUSB2_PHY_RESET] = { 0x04b8 },
};
static const struct regmap_config gcc_msm8994_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x2000,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_msm8994_desc = {
.config = &gcc_msm8994_regmap_config,
.clks = gcc_msm8994_clocks,
.num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
.resets = gcc_msm8994_resets,
.num_resets = ARRAY_SIZE(gcc_msm8994_resets),
.gdscs = gcc_msm8994_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs),
};
static const struct of_device_id gcc_msm8994_match_table[] = {
{ .compatible = "qcom,gcc-msm8992" },
{ .compatible = "qcom,gcc-msm8994" }, /* V2 and V2.1 */
{}
};
MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
static int gcc_msm8994_probe(struct platform_device *pdev)
{
if (of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-msm8992")) {
/* MSM8992 features less clocks and some have different freq tables */
gcc_msm8994_desc.clks[UFS_AXI_CLK_SRC] = NULL;
gcc_msm8994_desc.clks[GCC_LPASS_Q6_AXI_CLK] = NULL;
gcc_msm8994_desc.clks[UFS_PHY_LDO] = NULL;
gcc_msm8994_desc.clks[GCC_UFS_AHB_CLK] = NULL;
gcc_msm8994_desc.clks[GCC_UFS_AXI_CLK] = NULL;
gcc_msm8994_desc.clks[GCC_UFS_RX_CFG_CLK] = NULL;
gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_0_CLK] = NULL;
gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_1_CLK] = NULL;
gcc_msm8994_desc.clks[GCC_UFS_TX_CFG_CLK] = NULL;
gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_0_CLK] = NULL;
gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_1_CLK] = NULL;
sdcc1_apps_clk_src.freq_tbl = ftbl_sdcc1_apps_clk_src_8992;
blsp1_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
blsp1_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
blsp1_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
blsp1_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
blsp1_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
blsp1_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
blsp2_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
blsp2_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
blsp2_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
blsp2_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
blsp2_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
blsp2_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
/*
* Some 8992 boards might *possibly* use
* PCIe1 clocks and controller, but it's not
* standard and they should be disabled otherwise.
*/
gcc_msm8994_desc.clks[PCIE_1_AUX_CLK_SRC] = NULL;
gcc_msm8994_desc.clks[PCIE_1_PIPE_CLK_SRC] = NULL;
gcc_msm8994_desc.clks[PCIE_1_PHY_LDO] = NULL;
gcc_msm8994_desc.clks[GCC_PCIE_1_AUX_CLK] = NULL;
gcc_msm8994_desc.clks[GCC_PCIE_1_CFG_AHB_CLK] = NULL;
gcc_msm8994_desc.clks[GCC_PCIE_1_MSTR_AXI_CLK] = NULL;
gcc_msm8994_desc.clks[GCC_PCIE_1_PIPE_CLK] = NULL;
gcc_msm8994_desc.clks[GCC_PCIE_1_SLV_AXI_CLK] = NULL;
gcc_msm8994_desc.clks[GCC_SYS_NOC_UFS_AXI_CLK] = NULL;
}
return qcom_cc_probe(pdev, &gcc_msm8994_desc);
}
static struct platform_driver gcc_msm8994_driver = {
.probe = gcc_msm8994_probe,
.driver = {
.name = "gcc-msm8994",
.of_match_table = gcc_msm8994_match_table,
},
};
static int __init gcc_msm8994_init(void)
{
return platform_driver_register(&gcc_msm8994_driver);
}
core_initcall(gcc_msm8994_init);
static void __exit gcc_msm8994_exit(void)
{
platform_driver_unregister(&gcc_msm8994_driver);
}
module_exit(gcc_msm8994_exit);
MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:gcc-msm8994");
| linux-master | drivers/clk/qcom/gcc-msm8994.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2022, Linaro Limited
*/
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gpucc-sm8350.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "common.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-divider.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL1_OUT_MAIN,
};
static struct pll_vco lucid_5lpe_vco[] = {
{ 249600000, 1750000000, 0 },
};
static const struct alpha_pll_config gpu_cc_pll0_config = {
.l = 0x18,
.alpha = 0x6000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x2a9a699c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000000,
.test_ctl_hi1_val = 0x01800000,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static const struct clk_parent_data gpu_cc_parent = {
.fw_name = "bi_tcxo",
};
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_5lpe_vco,
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_pll0",
.parent_data = &gpu_cc_parent,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_5lpe_ops,
},
},
};
static const struct alpha_pll_config gpu_cc_pll1_config = {
.l = 0x1a,
.alpha = 0xaaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x2a9a699c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000000,
.test_ctl_hi1_val = 0x01800000,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x100,
.vco_table = lucid_5lpe_vco,
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &gpu_cc_parent,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_5lpe_ops,
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .fw_name = "gcc_gpu_gpll0_clk_src" },
{ .fw_name = "gcc_gpu_gpll0_div_clk_src" },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .fw_name = "gcc_gpu_gpll0_clk_src" },
{ .fw_name = "gcc_gpu_gpll0_div_clk_src" },
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x1120,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_hub_clk_src = {
.cmd_rcgr = 0x117c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_1,
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_hub_clk_src",
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
.reg = 0x11c0,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gpu_cc_hub_ahb_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
.reg = 0x11bc,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gpu_cc_hub_cx_int_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x1078,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cb_clk = {
.halt_reg = 0x1170,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1170,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x107c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x107c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_crc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_apb_clk = {
.halt_reg = 0x1088,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_apb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x1098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_cx_qdss_at_clk = {
.halt_reg = 0x1080,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_qdss_at_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_qdss_trig_clk = {
.halt_reg = 0x1094,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1094,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_qdss_trig_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_qdss_tsctr_clk = {
.halt_reg = 0x1084,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_qdss_tsctr_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
.halt_reg = 0x108c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x108c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_snoc_dvm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_aon_clk = {
.halt_reg = 0x1004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_aon_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x109c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x109c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_freq_measure_clk = {
.halt_reg = 0x120c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x120c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_freq_measure_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gmu_clk = {
.halt_reg = 0x1064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_qdss_tsctr_clk = {
.halt_reg = 0x105c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x105c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_qdss_tsctr_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_vsense_clk = {
.halt_reg = 0x1058,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_vsense_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
.halt_reg = 0x5000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hub_aon_clk = {
.halt_reg = 0x1178,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1178,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_hub_aon_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_hub_cx_int_clk = {
.halt_reg = 0x1204,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1204,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_hub_cx_int_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
.halt_reg = 0x802c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x802c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_mnd1x_0_gfx3d_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
.halt_reg = 0x8030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_mnd1x_1_gfx3d_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_sleep_clk = {
.halt_reg = 0x1090,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x106c,
.gds_hw_ctrl = 0x1540,
.pd = {
.name = "gpu_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x100c,
.clamp_io_ctrl = 0x1508,
.pd = {
.name = "gpu_gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
};
static struct clk_regmap *gpu_cc_sm8350_clocks[] = {
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CX_QDSS_AT_CLK] = &gpu_cc_cx_qdss_at_clk.clkr,
[GPU_CC_CX_QDSS_TRIG_CLK] = &gpu_cc_cx_qdss_trig_clk.clkr,
[GPU_CC_CX_QDSS_TSCTR_CLK] = &gpu_cc_cx_qdss_tsctr_clk.clkr,
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
[GPU_CC_GX_QDSS_TSCTR_CLK] = &gpu_cc_gx_qdss_tsctr_clk.clkr,
[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
[GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
[GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
[GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
[GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
};
static const struct qcom_reset_map gpu_cc_sm8350_resets[] = {
[GPUCC_GPU_CC_ACD_BCR] = { 0x1160 },
[GPUCC_GPU_CC_CB_BCR] = { 0x116c },
[GPUCC_GPU_CC_CX_BCR] = { 0x1068 },
[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x1174 },
[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 },
[GPUCC_GPU_CC_GMU_BCR] = { 0x111c },
[GPUCC_GPU_CC_GX_BCR] = { 0x1008 },
[GPUCC_GPU_CC_XO_BCR] = { 0x1000 },
};
static struct gdsc *gpu_cc_sm8350_gdscs[] = {
[GPU_CX_GDSC] = &gpu_cx_gdsc,
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
static const struct regmap_config gpu_cc_sm8350_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x8030,
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_sm8350_desc = {
.config = &gpu_cc_sm8350_regmap_config,
.clks = gpu_cc_sm8350_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sm8350_clocks),
.resets = gpu_cc_sm8350_resets,
.num_resets = ARRAY_SIZE(gpu_cc_sm8350_resets),
.gdscs = gpu_cc_sm8350_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sm8350_gdscs),
};
static int gpu_cc_sm8350_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gpu_cc_sm8350_desc);
if (IS_ERR(regmap)) {
dev_err(&pdev->dev, "Failed to map gpu cc registers\n");
return PTR_ERR(regmap);
}
clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
return qcom_cc_really_probe(pdev, &gpu_cc_sm8350_desc, regmap);
}
static const struct of_device_id gpu_cc_sm8350_match_table[] = {
{ .compatible = "qcom,sm8350-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sm8350_match_table);
static struct platform_driver gpu_cc_sm8350_driver = {
.probe = gpu_cc_sm8350_probe,
.driver = {
.name = "sm8350-gpucc",
.of_match_table = gpu_cc_sm8350_match_table,
},
};
static int __init gpu_cc_sm8350_init(void)
{
return platform_driver_register(&gpu_cc_sm8350_driver);
}
subsys_initcall(gpu_cc_sm8350_init);
static void __exit gpu_cc_sm8350_exit(void)
{
platform_driver_unregister(&gpu_cc_sm8350_driver);
}
module_exit(gpu_cc_sm8350_exit);
MODULE_DESCRIPTION("QTI GPU_CC SM8350 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gpucc-sm8350.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <linux/math64.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
#include "clk-regmap-divider.h"
#define to_clk_regmap_div(_hw) container_of(to_clk_regmap(_hw),\
struct clk_regmap_div, clkr)
#define to_clk_fepll(_hw) container_of(to_clk_regmap_div(_hw),\
struct clk_fepll, cdiv)
enum {
P_XO,
P_FEPLL200,
P_FEPLL500,
P_DDRPLL,
P_FEPLLWCSS2G,
P_FEPLLWCSS5G,
P_FEPLL125DLY,
P_DDRPLLAPSS,
};
/*
* struct clk_fepll_vco - vco feedback divider corresponds for FEPLL clocks
* @fdbkdiv_shift: lowest bit for FDBKDIV
* @fdbkdiv_width: number of bits in FDBKDIV
* @refclkdiv_shift: lowest bit for REFCLKDIV
* @refclkdiv_width: number of bits in REFCLKDIV
* @reg: PLL_DIV register address
*/
struct clk_fepll_vco {
u32 fdbkdiv_shift;
u32 fdbkdiv_width;
u32 refclkdiv_shift;
u32 refclkdiv_width;
u32 reg;
};
/*
* struct clk_fepll - clk divider corresponds to FEPLL clocks
* @fixed_div: fixed divider value if divider is fixed
* @parent_map: map from software's parent index to hardware's src_sel field
* @cdiv: divider values for PLL_DIV
* @pll_vco: vco feedback divider
* @div_table: mapping for actual divider value to register divider value
* in case of non fixed divider
* @freq_tbl: frequency table
*/
struct clk_fepll {
u32 fixed_div;
const u8 *parent_map;
struct clk_regmap_div cdiv;
const struct clk_fepll_vco *pll_vco;
const struct clk_div_table *div_table;
const struct freq_tbl *freq_tbl;
};
/*
* Contains index for safe clock during APSS freq change.
* fepll500 is being used as safe clock so initialize it
* with its index in parents list gcc_xo_ddr_500_200.
*/
static const int gcc_ipq4019_cpu_safe_parent = 2;
/* Calculates the VCO rate for FEPLL. */
static u64 clk_fepll_vco_calc_rate(struct clk_fepll *pll_div,
unsigned long parent_rate)
{
const struct clk_fepll_vco *pll_vco = pll_div->pll_vco;
u32 fdbkdiv, refclkdiv, cdiv;
u64 vco;
regmap_read(pll_div->cdiv.clkr.regmap, pll_vco->reg, &cdiv);
refclkdiv = (cdiv >> pll_vco->refclkdiv_shift) &
(BIT(pll_vco->refclkdiv_width) - 1);
fdbkdiv = (cdiv >> pll_vco->fdbkdiv_shift) &
(BIT(pll_vco->fdbkdiv_width) - 1);
vco = parent_rate / refclkdiv;
vco *= 2;
vco *= fdbkdiv;
return vco;
}
static const struct clk_fepll_vco gcc_apss_ddrpll_vco = {
.fdbkdiv_shift = 16,
.fdbkdiv_width = 8,
.refclkdiv_shift = 24,
.refclkdiv_width = 5,
.reg = 0x2e020,
};
static const struct clk_fepll_vco gcc_fepll_vco = {
.fdbkdiv_shift = 16,
.fdbkdiv_width = 8,
.refclkdiv_shift = 24,
.refclkdiv_width = 5,
.reg = 0x2f020,
};
/*
* Round rate function for APSS CPU PLL Clock divider.
* It looks up the frequency table and returns the next higher frequency
* supported in hardware.
*/
static long clk_cpu_div_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *p_rate)
{
struct clk_fepll *pll = to_clk_fepll(hw);
struct clk_hw *p_hw;
const struct freq_tbl *f;
f = qcom_find_freq(pll->freq_tbl, rate);
if (!f)
return -EINVAL;
p_hw = clk_hw_get_parent_by_index(hw, f->src);
*p_rate = clk_hw_get_rate(p_hw);
return f->freq;
};
/*
* Clock set rate function for APSS CPU PLL Clock divider.
* It looks up the frequency table and updates the PLL divider to corresponding
* divider value.
*/
static int clk_cpu_div_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_fepll *pll = to_clk_fepll(hw);
const struct freq_tbl *f;
u32 mask;
f = qcom_find_freq(pll->freq_tbl, rate);
if (!f)
return -EINVAL;
mask = (BIT(pll->cdiv.width) - 1) << pll->cdiv.shift;
regmap_update_bits(pll->cdiv.clkr.regmap,
pll->cdiv.reg, mask,
f->pre_div << pll->cdiv.shift);
/*
* There is no status bit which can be checked for successful CPU
* divider update operation so using delay for the same.
*/
udelay(1);
return 0;
};
/*
* Clock frequency calculation function for APSS CPU PLL Clock divider.
* This clock divider is nonlinear so this function calculates the actual
* divider and returns the output frequency by dividing VCO Frequency
* with this actual divider value.
*/
static unsigned long
clk_cpu_div_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_fepll *pll = to_clk_fepll(hw);
u32 cdiv, pre_div;
u64 rate;
regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv);
cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1);
/*
* Some dividers have value in 0.5 fraction so multiply both VCO
* frequency(parent_rate) and pre_div with 2 to make integer
* calculation.
*/
if (cdiv > 10)
pre_div = (cdiv + 1) * 2;
else
pre_div = cdiv + 12;
rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
do_div(rate, pre_div);
return rate;
};
static const struct clk_ops clk_regmap_cpu_div_ops = {
.round_rate = clk_cpu_div_round_rate,
.set_rate = clk_cpu_div_set_rate,
.recalc_rate = clk_cpu_div_recalc_rate,
};
static const struct freq_tbl ftbl_apss_ddr_pll[] = {
{ 384000000, P_XO, 0xd, 0, 0 },
{ 413000000, P_XO, 0xc, 0, 0 },
{ 448000000, P_XO, 0xb, 0, 0 },
{ 488000000, P_XO, 0xa, 0, 0 },
{ 512000000, P_XO, 0x9, 0, 0 },
{ 537000000, P_XO, 0x8, 0, 0 },
{ 565000000, P_XO, 0x7, 0, 0 },
{ 597000000, P_XO, 0x6, 0, 0 },
{ 632000000, P_XO, 0x5, 0, 0 },
{ 672000000, P_XO, 0x4, 0, 0 },
{ 716000000, P_XO, 0x3, 0, 0 },
{ 768000000, P_XO, 0x2, 0, 0 },
{ 823000000, P_XO, 0x1, 0, 0 },
{ 896000000, P_XO, 0x0, 0, 0 },
{ }
};
static struct clk_fepll gcc_apss_cpu_plldiv_clk = {
.cdiv.reg = 0x2e020,
.cdiv.shift = 4,
.cdiv.width = 4,
.cdiv.clkr = {
.enable_reg = 0x2e000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "ddrpllapss",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_regmap_cpu_div_ops,
},
},
.freq_tbl = ftbl_apss_ddr_pll,
.pll_vco = &gcc_apss_ddrpll_vco,
};
/* Calculates the rate for PLL divider.
* If the divider value is not fixed then it gets the actual divider value
* from divider table. Then, it calculate the clock rate by dividing the
* parent rate with actual divider value.
*/
static unsigned long
clk_regmap_clk_div_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_fepll *pll = to_clk_fepll(hw);
u32 cdiv, pre_div = 1;
u64 rate;
const struct clk_div_table *clkt;
if (pll->fixed_div) {
pre_div = pll->fixed_div;
} else {
regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv);
cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1);
for (clkt = pll->div_table; clkt->div; clkt++) {
if (clkt->val == cdiv)
pre_div = clkt->div;
}
}
rate = clk_fepll_vco_calc_rate(pll, parent_rate);
do_div(rate, pre_div);
return rate;
};
static const struct clk_ops clk_fepll_div_ops = {
.recalc_rate = clk_regmap_clk_div_recalc_rate,
};
static struct clk_fepll gcc_apss_sdcc_clk = {
.fixed_div = 28,
.cdiv.clkr = {
.hw.init = &(struct clk_init_data){
.name = "ddrpllsdcc",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_fepll_div_ops,
},
},
.pll_vco = &gcc_apss_ddrpll_vco,
};
static struct clk_fepll gcc_fepll125_clk = {
.fixed_div = 32,
.cdiv.clkr = {
.hw.init = &(struct clk_init_data){
.name = "fepll125",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_fepll_div_ops,
},
},
.pll_vco = &gcc_fepll_vco,
};
static struct clk_fepll gcc_fepll125dly_clk = {
.fixed_div = 32,
.cdiv.clkr = {
.hw.init = &(struct clk_init_data){
.name = "fepll125dly",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_fepll_div_ops,
},
},
.pll_vco = &gcc_fepll_vco,
};
static struct clk_fepll gcc_fepll200_clk = {
.fixed_div = 20,
.cdiv.clkr = {
.hw.init = &(struct clk_init_data){
.name = "fepll200",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_fepll_div_ops,
},
},
.pll_vco = &gcc_fepll_vco,
};
static struct clk_fepll gcc_fepll500_clk = {
.fixed_div = 8,
.cdiv.clkr = {
.hw.init = &(struct clk_init_data){
.name = "fepll500",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_fepll_div_ops,
},
},
.pll_vco = &gcc_fepll_vco,
};
static const struct clk_div_table fepllwcss_clk_div_table[] = {
{ 0, 15 },
{ 1, 16 },
{ 2, 18 },
{ 3, 20 },
{ },
};
static struct clk_fepll gcc_fepllwcss2g_clk = {
.cdiv.reg = 0x2f020,
.cdiv.shift = 8,
.cdiv.width = 2,
.cdiv.clkr = {
.hw.init = &(struct clk_init_data){
.name = "fepllwcss2g",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_fepll_div_ops,
},
},
.div_table = fepllwcss_clk_div_table,
.pll_vco = &gcc_fepll_vco,
};
static struct clk_fepll gcc_fepllwcss5g_clk = {
.cdiv.reg = 0x2f020,
.cdiv.shift = 12,
.cdiv.width = 2,
.cdiv.clkr = {
.hw.init = &(struct clk_init_data){
.name = "fepllwcss5g",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_fepll_div_ops,
},
},
.div_table = fepllwcss_clk_div_table,
.pll_vco = &gcc_fepll_vco,
};
static struct parent_map gcc_xo_200_500_map[] = {
{ P_XO, 0 },
{ P_FEPLL200, 1 },
{ P_FEPLL500, 2 },
};
static const struct clk_parent_data gcc_xo_200_500[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &gcc_fepll200_clk.cdiv.clkr.hw },
{ .hw = &gcc_fepll500_clk.cdiv.clkr.hw },
};
static const struct freq_tbl ftbl_gcc_pcnoc_ahb_clk[] = {
F(48000000, P_XO, 1, 0, 0),
F(100000000, P_FEPLL200, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcnoc_ahb_clk_src = {
.cmd_rcgr = 0x21024,
.hid_width = 5,
.parent_map = gcc_xo_200_500_map,
.freq_tbl = ftbl_gcc_pcnoc_ahb_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcnoc_ahb_clk_src",
.parent_data = gcc_xo_200_500,
.num_parents = ARRAY_SIZE(gcc_xo_200_500),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch pcnoc_clk_src = {
.halt_reg = 0x21030,
.clkr = {
.enable_reg = 0x21030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "pcnoc_clk_src",
.parent_hws = (const struct clk_hw *[]){
&gcc_pcnoc_ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT |
CLK_IS_CRITICAL,
},
},
};
static struct parent_map gcc_xo_200_map[] = {
{ P_XO, 0 },
{ P_FEPLL200, 1 },
};
static const struct clk_parent_data gcc_xo_200[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &gcc_fepll200_clk.cdiv.clkr.hw },
};
static const struct freq_tbl ftbl_gcc_audio_pwm_clk[] = {
F(48000000, P_XO, 1, 0, 0),
F(200000000, P_FEPLL200, 1, 0, 0),
{ }
};
static struct clk_rcg2 audio_clk_src = {
.cmd_rcgr = 0x1b000,
.hid_width = 5,
.parent_map = gcc_xo_200_map,
.freq_tbl = ftbl_gcc_audio_pwm_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "audio_clk_src",
.parent_data = gcc_xo_200,
.num_parents = ARRAY_SIZE(gcc_xo_200),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_audio_ahb_clk = {
.halt_reg = 0x1b010,
.clkr = {
.enable_reg = 0x1b010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_audio_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.clkr.hw },
.flags = CLK_SET_RATE_PARENT,
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_audio_pwm_clk = {
.halt_reg = 0x1b00C,
.clkr = {
.enable_reg = 0x1b00C,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_audio_pwm_clk",
.parent_hws = (const struct clk_hw *[]){
&audio_clk_src.clkr.hw },
.flags = CLK_SET_RATE_PARENT,
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_blsp1_qup1_2_i2c_apps_clk[] = {
F(19050000, P_FEPLL200, 10.5, 1, 1),
{ }
};
static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x200c,
.hid_width = 5,
.parent_map = gcc_xo_200_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_2_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_200,
.num_parents = ARRAY_SIZE(gcc_xo_200),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x2008,
.clkr = {
.enable_reg = 0x2008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup1_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x3000,
.hid_width = 5,
.parent_map = gcc_xo_200_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_2_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_200,
.num_parents = ARRAY_SIZE(gcc_xo_200),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x3010,
.clkr = {
.enable_reg = 0x3010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup2_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct parent_map gcc_xo_200_spi_map[] = {
{ P_XO, 0 },
{ P_FEPLL200, 2 },
};
static const struct clk_parent_data gcc_xo_200_spi[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &gcc_fepll200_clk.cdiv.clkr.hw },
};
static const struct freq_tbl ftbl_gcc_blsp1_qup1_2_spi_apps_clk[] = {
F(960000, P_XO, 12, 1, 4),
F(4800000, P_XO, 1, 1, 10),
F(9600000, P_XO, 1, 1, 5),
F(15000000, P_XO, 1, 1, 3),
F(19200000, P_XO, 1, 2, 5),
F(24000000, P_XO, 1, 1, 2),
F(48000000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x2024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_200_spi_map,
.freq_tbl = ftbl_gcc_blsp1_qup1_2_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_200_spi,
.num_parents = ARRAY_SIZE(gcc_xo_200_spi),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x2004,
.clkr = {
.enable_reg = 0x2004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup1_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x3014,
.mnd_width = 8,
.hid_width = 5,
.freq_tbl = ftbl_gcc_blsp1_qup1_2_spi_apps_clk,
.parent_map = gcc_xo_200_spi_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_200_spi,
.num_parents = ARRAY_SIZE(gcc_xo_200_spi),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x300c,
.clkr = {
.enable_reg = 0x300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_qup2_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_gcc_blsp1_uart1_2_apps_clk[] = {
F(1843200, P_FEPLL200, 1, 144, 15625),
F(3686400, P_FEPLL200, 1, 288, 15625),
F(7372800, P_FEPLL200, 1, 576, 15625),
F(14745600, P_FEPLL200, 1, 1152, 15625),
F(16000000, P_FEPLL200, 1, 2, 25),
F(24000000, P_XO, 1, 1, 2),
F(32000000, P_FEPLL200, 1, 4, 25),
F(40000000, P_FEPLL200, 1, 1, 5),
F(46400000, P_FEPLL200, 1, 29, 125),
F(48000000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x2044,
.mnd_width = 16,
.hid_width = 5,
.freq_tbl = ftbl_gcc_blsp1_uart1_2_apps_clk,
.parent_map = gcc_xo_200_spi_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
.parent_data = gcc_xo_200_spi,
.num_parents = ARRAY_SIZE(gcc_xo_200_spi),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x203c,
.clkr = {
.enable_reg = 0x203c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_uart1_apps_clk_src.clkr.hw },
.flags = CLK_SET_RATE_PARENT,
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x3034,
.mnd_width = 16,
.hid_width = 5,
.freq_tbl = ftbl_gcc_blsp1_uart1_2_apps_clk,
.parent_map = gcc_xo_200_spi_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
.parent_data = gcc_xo_200_spi,
.num_parents = ARRAY_SIZE(gcc_xo_200_spi),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x302c,
.clkr = {
.enable_reg = 0x302c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&blsp1_uart2_apps_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl ftbl_gcc_gp_clk[] = {
F(1250000, P_FEPLL200, 1, 16, 0),
F(2500000, P_FEPLL200, 1, 8, 0),
F(5000000, P_FEPLL200, 1, 4, 0),
{ }
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x8004,
.mnd_width = 8,
.hid_width = 5,
.freq_tbl = ftbl_gcc_gp_clk,
.parent_map = gcc_xo_200_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.parent_data = gcc_xo_200,
.num_parents = ARRAY_SIZE(gcc_xo_200),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x8000,
.clkr = {
.enable_reg = 0x8000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw *[]){
&gp1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg2 gp2_clk_src = {
.cmd_rcgr = 0x9004,
.mnd_width = 8,
.hid_width = 5,
.freq_tbl = ftbl_gcc_gp_clk,
.parent_map = gcc_xo_200_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.parent_data = gcc_xo_200,
.num_parents = ARRAY_SIZE(gcc_xo_200),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x9000,
.clkr = {
.enable_reg = 0x9000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw *[]){
&gp2_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg2 gp3_clk_src = {
.cmd_rcgr = 0xa004,
.mnd_width = 8,
.hid_width = 5,
.freq_tbl = ftbl_gcc_gp_clk,
.parent_map = gcc_xo_200_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.parent_data = gcc_xo_200,
.num_parents = ARRAY_SIZE(gcc_xo_200),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0xa000,
.clkr = {
.enable_reg = 0xa000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw *[]){
&gp3_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct parent_map gcc_xo_sdcc1_500_map[] = {
{ P_XO, 0 },
{ P_DDRPLL, 1 },
{ P_FEPLL500, 2 },
};
static const struct clk_parent_data gcc_xo_sdcc1_500[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &gcc_apss_sdcc_clk.cdiv.clkr.hw },
{ .hw = &gcc_fepll500_clk.cdiv.clkr.hw },
};
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
F(144000, P_XO, 1, 3, 240),
F(400000, P_XO, 1, 1, 0),
F(20000000, P_FEPLL500, 1, 1, 25),
F(25000000, P_FEPLL500, 1, 1, 20),
F(50000000, P_FEPLL500, 1, 1, 10),
F(100000000, P_FEPLL500, 1, 1, 5),
F(192000000, P_DDRPLL, 1, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x18004,
.hid_width = 5,
.freq_tbl = ftbl_gcc_sdcc1_apps_clk,
.parent_map = gcc_xo_sdcc1_500_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_xo_sdcc1_500,
.num_parents = ARRAY_SIZE(gcc_xo_sdcc1_500),
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_gcc_apps_clk[] = {
F(48000000, P_XO, 1, 0, 0),
F(200000000, P_FEPLL200, 1, 0, 0),
F(384000000, P_DDRPLLAPSS, 1, 0, 0),
F(413000000, P_DDRPLLAPSS, 1, 0, 0),
F(448000000, P_DDRPLLAPSS, 1, 0, 0),
F(488000000, P_DDRPLLAPSS, 1, 0, 0),
F(500000000, P_FEPLL500, 1, 0, 0),
F(512000000, P_DDRPLLAPSS, 1, 0, 0),
F(537000000, P_DDRPLLAPSS, 1, 0, 0),
F(565000000, P_DDRPLLAPSS, 1, 0, 0),
F(597000000, P_DDRPLLAPSS, 1, 0, 0),
F(632000000, P_DDRPLLAPSS, 1, 0, 0),
F(672000000, P_DDRPLLAPSS, 1, 0, 0),
F(716000000, P_DDRPLLAPSS, 1, 0, 0),
{ }
};
static struct parent_map gcc_xo_ddr_500_200_map[] = {
{ P_XO, 0 },
{ P_FEPLL200, 3 },
{ P_FEPLL500, 2 },
{ P_DDRPLLAPSS, 1 },
};
static const struct clk_parent_data gcc_xo_ddr_500_200[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &gcc_fepll200_clk.cdiv.clkr.hw },
{ .hw = &gcc_fepll500_clk.cdiv.clkr.hw },
{ .hw = &gcc_apss_cpu_plldiv_clk.cdiv.clkr.hw },
};
static struct clk_rcg2 apps_clk_src = {
.cmd_rcgr = 0x1900c,
.hid_width = 5,
.freq_tbl = ftbl_gcc_apps_clk,
.parent_map = gcc_xo_ddr_500_200_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "apps_clk_src",
.parent_data = gcc_xo_ddr_500_200,
.num_parents = ARRAY_SIZE(gcc_xo_ddr_500_200),
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_gcc_apps_ahb_clk[] = {
F(48000000, P_XO, 1, 0, 0),
F(100000000, P_FEPLL200, 2, 0, 0),
{ }
};
static struct clk_rcg2 apps_ahb_clk_src = {
.cmd_rcgr = 0x19014,
.hid_width = 5,
.parent_map = gcc_xo_200_500_map,
.freq_tbl = ftbl_gcc_apps_ahb_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "apps_ahb_clk_src",
.parent_data = gcc_xo_200_500,
.num_parents = ARRAY_SIZE(gcc_xo_200_500),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_apss_ahb_clk = {
.halt_reg = 0x19004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x6000,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&apps_ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x1008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x6000,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_dcd_xo_clk = {
.halt_reg = 0x2103c,
.clkr = {
.enable_reg = 0x2103c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_dcd_xo_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x1300c,
.clkr = {
.enable_reg = 0x1300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_crypto_ahb_clk = {
.halt_reg = 0x16024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x6000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_axi_clk = {
.halt_reg = 0x16020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x6000,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_fepll125_clk.cdiv.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_crypto_clk = {
.halt_reg = 0x1601c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x6000,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_fepll125_clk.cdiv.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct parent_map gcc_xo_125_dly_map[] = {
{ P_XO, 0 },
{ P_FEPLL125DLY, 1 },
};
static const struct clk_parent_data gcc_xo_125_dly[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &gcc_fepll125dly_clk.cdiv.clkr.hw },
};
static const struct freq_tbl ftbl_gcc_fephy_dly_clk[] = {
F(125000000, P_FEPLL125DLY, 1, 0, 0),
{ }
};
static struct clk_rcg2 fephy_125m_dly_clk_src = {
.cmd_rcgr = 0x12000,
.hid_width = 5,
.parent_map = gcc_xo_125_dly_map,
.freq_tbl = ftbl_gcc_fephy_dly_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "fephy_125m_dly_clk_src",
.parent_data = gcc_xo_125_dly,
.num_parents = ARRAY_SIZE(gcc_xo_125_dly),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_ess_clk = {
.halt_reg = 0x12010,
.clkr = {
.enable_reg = 0x12010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ess_clk",
.parent_hws = (const struct clk_hw *[]){
&fephy_125m_dly_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_imem_axi_clk = {
.halt_reg = 0xe004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x6000,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_imem_axi_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_fepll200_clk.cdiv.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_imem_cfg_ahb_clk = {
.halt_reg = 0xe008,
.clkr = {
.enable_reg = 0xe008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_imem_cfg_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_ahb_clk = {
.halt_reg = 0x1d00c,
.clkr = {
.enable_reg = 0x1d00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_axi_m_clk = {
.halt_reg = 0x1d004,
.clkr = {
.enable_reg = 0x1d004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_axi_m_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_fepll200_clk.cdiv.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_axi_s_clk = {
.halt_reg = 0x1d008,
.clkr = {
.enable_reg = 0x1d008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_axi_s_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_fepll200_clk.cdiv.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x13004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x6000,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qpic_ahb_clk = {
.halt_reg = 0x1c008,
.clkr = {
.enable_reg = 0x1c008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qpic_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qpic_clk = {
.halt_reg = 0x1c004,
.clkr = {
.enable_reg = 0x1c004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qpic_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x18010,
.clkr = {
.enable_reg = 0x18010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x1800c,
.clkr = {
.enable_reg = 0x1800c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw *[]){
&sdcc1_apps_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_tlmm_ahb_clk = {
.halt_reg = 0x5004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x6000,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_tlmm_ahb_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb2_master_clk = {
.halt_reg = 0x1e00c,
.clkr = {
.enable_reg = 0x1e00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb2_master_clk",
.parent_hws = (const struct clk_hw *[]){
&pcnoc_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb2_sleep_clk = {
.halt_reg = 0x1e010,
.clkr = {
.enable_reg = 0x1e010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb2_sleep_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep_clk",
.name = "gcc_sleep_clk_src",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
F(2000000, P_FEPLL200, 10, 0, 0),
{ }
};
static struct clk_rcg2 usb30_mock_utmi_clk_src = {
.cmd_rcgr = 0x1e000,
.hid_width = 5,
.parent_map = gcc_xo_200_map,
.freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_mock_utmi_clk_src",
.parent_data = gcc_xo_200,
.num_parents = ARRAY_SIZE(gcc_xo_200),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_usb2_mock_utmi_clk = {
.halt_reg = 0x1e014,
.clkr = {
.enable_reg = 0x1e014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb2_mock_utmi_clk",
.parent_hws = (const struct clk_hw *[]){
&usb30_mock_utmi_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_usb3_master_clk = {
.halt_reg = 0x1e028,
.clkr = {
.enable_reg = 0x1e028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_master_clk",
.parent_hws = (const struct clk_hw *[]){
&gcc_fepll125_clk.cdiv.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sleep_clk = {
.halt_reg = 0x1e02C,
.clkr = {
.enable_reg = 0x1e02C,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sleep_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep_clk",
.name = "gcc_sleep_clk_src",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_mock_utmi_clk = {
.halt_reg = 0x1e030,
.clkr = {
.enable_reg = 0x1e030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_mock_utmi_clk",
.parent_hws = (const struct clk_hw *[]){
&usb30_mock_utmi_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct parent_map gcc_xo_wcss2g_map[] = {
{ P_XO, 0 },
{ P_FEPLLWCSS2G, 1 },
};
static const struct clk_parent_data gcc_xo_wcss2g[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &gcc_fepllwcss2g_clk.cdiv.clkr.hw },
};
static const struct freq_tbl ftbl_gcc_wcss2g_clk[] = {
F(48000000, P_XO, 1, 0, 0),
F(250000000, P_FEPLLWCSS2G, 1, 0, 0),
{ }
};
static struct clk_rcg2 wcss2g_clk_src = {
.cmd_rcgr = 0x1f000,
.hid_width = 5,
.freq_tbl = ftbl_gcc_wcss2g_clk,
.parent_map = gcc_xo_wcss2g_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "wcss2g_clk_src",
.parent_data = gcc_xo_wcss2g,
.num_parents = ARRAY_SIZE(gcc_xo_wcss2g),
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_branch gcc_wcss2g_clk = {
.halt_reg = 0x1f00C,
.clkr = {
.enable_reg = 0x1f00C,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_wcss2g_clk",
.parent_hws = (const struct clk_hw *[]){
&wcss2g_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_wcss2g_ref_clk = {
.halt_reg = 0x1f00C,
.clkr = {
.enable_reg = 0x1f00C,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_wcss2g_ref_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_wcss2g_rtc_clk = {
.halt_reg = 0x1f010,
.clkr = {
.enable_reg = 0x1f010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_wcss2g_rtc_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep_clk",
.name = "gcc_sleep_clk_src",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct parent_map gcc_xo_wcss5g_map[] = {
{ P_XO, 0 },
{ P_FEPLLWCSS5G, 1 },
};
static const struct clk_parent_data gcc_xo_wcss5g[] = {
{ .fw_name = "xo", .name = "xo" },
{ .hw = &gcc_fepllwcss5g_clk.cdiv.clkr.hw },
};
static const struct freq_tbl ftbl_gcc_wcss5g_clk[] = {
F(48000000, P_XO, 1, 0, 0),
F(250000000, P_FEPLLWCSS5G, 1, 0, 0),
{ }
};
static struct clk_rcg2 wcss5g_clk_src = {
.cmd_rcgr = 0x20000,
.hid_width = 5,
.parent_map = gcc_xo_wcss5g_map,
.freq_tbl = ftbl_gcc_wcss5g_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "wcss5g_clk_src",
.parent_data = gcc_xo_wcss5g,
.num_parents = ARRAY_SIZE(gcc_xo_wcss5g),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_wcss5g_clk = {
.halt_reg = 0x2000c,
.clkr = {
.enable_reg = 0x2000c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_wcss5g_clk",
.parent_hws = (const struct clk_hw *[]){
&wcss5g_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_wcss5g_ref_clk = {
.halt_reg = 0x2000c,
.clkr = {
.enable_reg = 0x2000c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_wcss5g_ref_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
.name = "xo",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch gcc_wcss5g_rtc_clk = {
.halt_reg = 0x20010,
.clkr = {
.enable_reg = 0x20010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_wcss5g_rtc_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep_clk",
.name = "gcc_sleep_clk_src",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_regmap *gcc_ipq4019_clocks[] = {
[AUDIO_CLK_SRC] = &audio_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[GCC_USB3_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
[GCC_APPS_CLK_SRC] = &apps_clk_src.clkr,
[GCC_APPS_AHB_CLK_SRC] = &apps_ahb_clk_src.clkr,
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[FEPHY_125M_DLY_CLK_SRC] = &fephy_125m_dly_clk_src.clkr,
[WCSS2G_CLK_SRC] = &wcss2g_clk_src.clkr,
[WCSS5G_CLK_SRC] = &wcss5g_clk_src.clkr,
[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
[GCC_AUDIO_AHB_CLK] = &gcc_audio_ahb_clk.clkr,
[GCC_AUDIO_PWM_CLK] = &gcc_audio_pwm_clk.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_DCD_XO_CLK] = &gcc_dcd_xo_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
[GCC_ESS_CLK] = &gcc_ess_clk.clkr,
[GCC_IMEM_AXI_CLK] = &gcc_imem_axi_clk.clkr,
[GCC_IMEM_CFG_AHB_CLK] = &gcc_imem_cfg_ahb_clk.clkr,
[GCC_PCIE_AHB_CLK] = &gcc_pcie_ahb_clk.clkr,
[GCC_PCIE_AXI_M_CLK] = &gcc_pcie_axi_m_clk.clkr,
[GCC_PCIE_AXI_S_CLK] = &gcc_pcie_axi_s_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_TLMM_AHB_CLK] = &gcc_tlmm_ahb_clk.clkr,
[GCC_USB2_MASTER_CLK] = &gcc_usb2_master_clk.clkr,
[GCC_USB2_SLEEP_CLK] = &gcc_usb2_sleep_clk.clkr,
[GCC_USB2_MOCK_UTMI_CLK] = &gcc_usb2_mock_utmi_clk.clkr,
[GCC_USB3_MASTER_CLK] = &gcc_usb3_master_clk.clkr,
[GCC_USB3_SLEEP_CLK] = &gcc_usb3_sleep_clk.clkr,
[GCC_USB3_MOCK_UTMI_CLK] = &gcc_usb3_mock_utmi_clk.clkr,
[GCC_WCSS2G_CLK] = &gcc_wcss2g_clk.clkr,
[GCC_WCSS2G_REF_CLK] = &gcc_wcss2g_ref_clk.clkr,
[GCC_WCSS2G_RTC_CLK] = &gcc_wcss2g_rtc_clk.clkr,
[GCC_WCSS5G_CLK] = &gcc_wcss5g_clk.clkr,
[GCC_WCSS5G_REF_CLK] = &gcc_wcss5g_ref_clk.clkr,
[GCC_WCSS5G_RTC_CLK] = &gcc_wcss5g_rtc_clk.clkr,
[GCC_SDCC_PLLDIV_CLK] = &gcc_apss_sdcc_clk.cdiv.clkr,
[GCC_FEPLL125_CLK] = &gcc_fepll125_clk.cdiv.clkr,
[GCC_FEPLL125DLY_CLK] = &gcc_fepll125dly_clk.cdiv.clkr,
[GCC_FEPLL200_CLK] = &gcc_fepll200_clk.cdiv.clkr,
[GCC_FEPLL500_CLK] = &gcc_fepll500_clk.cdiv.clkr,
[GCC_FEPLL_WCSS2G_CLK] = &gcc_fepllwcss2g_clk.cdiv.clkr,
[GCC_FEPLL_WCSS5G_CLK] = &gcc_fepllwcss5g_clk.cdiv.clkr,
[GCC_APSS_CPU_PLLDIV_CLK] = &gcc_apss_cpu_plldiv_clk.cdiv.clkr,
[GCC_PCNOC_AHB_CLK_SRC] = &gcc_pcnoc_ahb_clk_src.clkr,
[GCC_PCNOC_AHB_CLK] = &pcnoc_clk_src.clkr,
};
static const struct qcom_reset_map gcc_ipq4019_resets[] = {
[WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
[WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
[WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
[WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
[WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
[WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
[WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
[WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
[WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
[WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
[WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
[WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
[USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
[USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
[USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
[USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
[USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
[PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
[PCIE_AHB_ARES] = { 0x1d010, 10 },
[PCIE_PWR_ARES] = { 0x1d010, 9 },
[PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
[PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
[PCIE_PHY_ARES] = { 0x1d010, 6 },
[PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
[PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
[PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
[PCIE_PIPE_ARES] = { 0x1d010, 2 },
[PCIE_AXI_S_ARES] = { 0x1d010, 1 },
[PCIE_AXI_M_ARES] = { 0x1d010, 0 },
[ESS_RESET] = { 0x12008, 0},
[GCC_BLSP1_BCR] = {0x01000, 0},
[GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
[GCC_BLSP1_UART1_BCR] = {0x02038, 0},
[GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
[GCC_BLSP1_UART2_BCR] = {0x03028, 0},
[GCC_BIMC_BCR] = {0x04000, 0},
[GCC_TLMM_BCR] = {0x05000, 0},
[GCC_IMEM_BCR] = {0x0E000, 0},
[GCC_ESS_BCR] = {0x12008, 0},
[GCC_PRNG_BCR] = {0x13000, 0},
[GCC_BOOT_ROM_BCR] = {0x13008, 0},
[GCC_CRYPTO_BCR] = {0x16000, 0},
[GCC_SDCC1_BCR] = {0x18000, 0},
[GCC_SEC_CTRL_BCR] = {0x1A000, 0},
[GCC_AUDIO_BCR] = {0x1B008, 0},
[GCC_QPIC_BCR] = {0x1C000, 0},
[GCC_PCIE_BCR] = {0x1D000, 0},
[GCC_USB2_BCR] = {0x1E008, 0},
[GCC_USB2_PHY_BCR] = {0x1E018, 0},
[GCC_USB3_BCR] = {0x1E024, 0},
[GCC_USB3_PHY_BCR] = {0x1E034, 0},
[GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
[GCC_PCNOC_BCR] = {0x2102C, 0},
[GCC_DCD_BCR] = {0x21038, 0},
[GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
[GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
[GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
[GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
[GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
[GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
[GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
[GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
[GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
[GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
[GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
[GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
[GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
[GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
[GCC_TCSR_BCR] = {0x22000, 0},
[GCC_MPM_BCR] = {0x24000, 0},
[GCC_SPDM_BCR] = {0x25000, 0},
[ESS_MAC1_ARES] = {0x1200C, 0},
[ESS_MAC2_ARES] = {0x1200C, 1},
[ESS_MAC3_ARES] = {0x1200C, 2},
[ESS_MAC4_ARES] = {0x1200C, 3},
[ESS_MAC5_ARES] = {0x1200C, 4},
[ESS_PSGMII_ARES] = {0x1200C, 5},
};
static const struct regmap_config gcc_ipq4019_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x2ffff,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_ipq4019_desc = {
.config = &gcc_ipq4019_regmap_config,
.clks = gcc_ipq4019_clocks,
.num_clks = ARRAY_SIZE(gcc_ipq4019_clocks),
.resets = gcc_ipq4019_resets,
.num_resets = ARRAY_SIZE(gcc_ipq4019_resets),
};
static const struct of_device_id gcc_ipq4019_match_table[] = {
{ .compatible = "qcom,gcc-ipq4019" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_ipq4019_match_table);
static int
gcc_ipq4019_cpu_clk_notifier_fn(struct notifier_block *nb,
unsigned long action, void *data)
{
int err = 0;
if (action == PRE_RATE_CHANGE)
err = clk_rcg2_ops.set_parent(&apps_clk_src.clkr.hw,
gcc_ipq4019_cpu_safe_parent);
return notifier_from_errno(err);
}
static struct notifier_block gcc_ipq4019_cpu_clk_notifier = {
.notifier_call = gcc_ipq4019_cpu_clk_notifier_fn,
};
static int gcc_ipq4019_probe(struct platform_device *pdev)
{
int err;
err = qcom_cc_probe(pdev, &gcc_ipq4019_desc);
if (err)
return err;
return devm_clk_notifier_register(&pdev->dev, apps_clk_src.clkr.hw.clk,
&gcc_ipq4019_cpu_clk_notifier);
}
static struct platform_driver gcc_ipq4019_driver = {
.probe = gcc_ipq4019_probe,
.driver = {
.name = "qcom,gcc-ipq4019",
.of_match_table = gcc_ipq4019_match_table,
},
};
static int __init gcc_ipq4019_init(void)
{
return platform_driver_register(&gcc_ipq4019_driver);
}
core_initcall(gcc_ipq4019_init);
static void __exit gcc_ipq4019_exit(void)
{
platform_driver_unregister(&gcc_ipq4019_driver);
}
module_exit(gcc_ipq4019_exit);
MODULE_ALIAS("platform:gcc-ipq4019");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("QCOM GCC IPQ4019 driver");
| linux-master | drivers/clk/qcom/gcc-ipq4019.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Linaro Ltd.
*/
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_BI_TCXO_AO,
P_DISP_CC_PLL0_OUT_MAIN,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
P_GPLL0_OUT_DIV,
P_GPLL0_OUT_MAIN,
P_SLEEP_CLK,
};
static const struct pll_vco spark_vco[] = {
{ 500000000, 1000000000, 2 },
};
/* 768MHz configuration */
static const struct alpha_pll_config disp_cc_pll0_config = {
.l = 0x28,
.alpha = 0x0,
.alpha_en_mask = BIT(24),
.vco_val = 0x2 << 20,
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055B,
};
static struct clk_alpha_pll disp_cc_pll0 = {
.offset = 0x0,
.vco_table = spark_vco,
.num_vco = ARRAY_SIZE(spark_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "disp_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct parent_map disp_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
};
static const struct clk_parent_data disp_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dsi0_phy_pll_out_byteclk" },
};
static const struct parent_map disp_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map disp_cc_parent_map_2[] = {
{ P_BI_TCXO_AO, 0 },
{ P_GPLL0_OUT_DIV, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_2[] = {
{ .fw_name = "bi_tcxo_ao" },
{ .fw_name = "gcc_disp_gpll0_div_clk_src" },
};
static const struct parent_map disp_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_MAIN, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_3[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &disp_cc_pll0.clkr.hw },
{ .fw_name = "gcc_disp_gpll0_clk_src" },
};
static const struct parent_map disp_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
};
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dsi0_phy_pll_out_dsiclk" },
};
static const struct parent_map disp_cc_parent_map_5[] = {
{ P_SLEEP_CLK, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_5[] = {
{ .fw_name = "sleep_clk" },
};
static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
.cmd_rcgr = 0x20a4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
/* For set_rate and set_parent to succeed, parent(s) must be enabled */
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_byte2_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
.reg = 0x20bc,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO_AO, 1, 0, 0),
F(37500000, P_GPLL0_OUT_DIV, 8, 0, 0),
F(75000000, P_GPLL0_OUT_DIV, 4, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
.cmd_rcgr = 0x2154,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.cmd_rcgr = 0x20c0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
F(384000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.cmd_rcgr = 0x2074,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.cmd_rcgr = 0x205c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
/* For set_rate and set_parent to succeed, parent(s) must be enabled */
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_pixel_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
.cmd_rcgr = 0x208c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
F(32764, P_SLEEP_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_sleep_clk_src = {
.cmd_rcgr = 0x6050,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.freq_tbl = ftbl_disp_cc_sleep_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_sleep_clk_src",
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch disp_cc_mdss_ahb_clk = {
.halt_reg = 0x2044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_clk = {
.halt_reg = 0x201c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
.halt_reg = 0x2020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_esc0_clk = {
.halt_reg = 0x2024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_clk = {
.halt_reg = 0x2008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
.halt_reg = 0x2010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x2010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_lut_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
.halt_reg = 0x4004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_pclk0_clk = {
.halt_reg = 0x2004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_vsync_clk = {
.halt_reg = 0x2018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_sleep_clk = {
.halt_reg = 0x6068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_sleep_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct qcom_reset_map disp_cc_qcm2290_resets[] = {
[DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x3000,
.pd = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL,
};
static struct gdsc *disp_cc_qcm2290_gdscs[] = {
[MDSS_GDSC] = &mdss_gdsc,
};
static struct clk_regmap *disp_cc_qcm2290_clocks[] = {
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
[DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
};
static const struct regmap_config disp_cc_qcm2290_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x10000,
.fast_io = true,
};
static const struct qcom_cc_desc disp_cc_qcm2290_desc = {
.config = &disp_cc_qcm2290_regmap_config,
.clks = disp_cc_qcm2290_clocks,
.num_clks = ARRAY_SIZE(disp_cc_qcm2290_clocks),
.gdscs = disp_cc_qcm2290_gdscs,
.num_gdscs = ARRAY_SIZE(disp_cc_qcm2290_gdscs),
.resets = disp_cc_qcm2290_resets,
.num_resets = ARRAY_SIZE(disp_cc_qcm2290_resets),
};
static const struct of_device_id disp_cc_qcm2290_match_table[] = {
{ .compatible = "qcom,qcm2290-dispcc" },
{ }
};
MODULE_DEVICE_TABLE(of, disp_cc_qcm2290_match_table);
static int disp_cc_qcm2290_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &disp_cc_qcm2290_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
/* Keep DISP_CC_XO_CLK always-ON */
regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0));
ret = qcom_cc_really_probe(pdev, &disp_cc_qcm2290_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register DISP CC clocks\n");
return ret;
}
return ret;
}
static struct platform_driver disp_cc_qcm2290_driver = {
.probe = disp_cc_qcm2290_probe,
.driver = {
.name = "dispcc-qcm2290",
.of_match_table = disp_cc_qcm2290_match_table,
},
};
static int __init disp_cc_qcm2290_init(void)
{
return platform_driver_register(&disp_cc_qcm2290_driver);
}
subsys_initcall(disp_cc_qcm2290_init);
static void __exit disp_cc_qcm2290_exit(void)
{
platform_driver_unregister(&disp_cc_qcm2290_driver);
}
module_exit(disp_cc_qcm2290_exit);
MODULE_DESCRIPTION("QTI DISP_CC qcm2290 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/dispcc-qcm2290.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,mmcc-apq8084.h>
#include <dt-bindings/reset/qcom,mmcc-apq8084.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_XO,
P_MMPLL0,
P_EDPLINK,
P_MMPLL1,
P_HDMIPLL,
P_GPLL0,
P_EDPVCO,
P_MMPLL4,
P_DSI0PLL,
P_DSI0PLL_BYTE,
P_MMPLL2,
P_MMPLL3,
P_GPLL1,
P_DSI1PLL,
P_DSI1PLL_BYTE,
P_MMSLEEP,
};
static struct clk_pll mmpll0 = {
.l_reg = 0x0004,
.m_reg = 0x0008,
.n_reg = 0x000c,
.config_reg = 0x0014,
.mode_reg = 0x0000,
.status_reg = 0x001c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll0",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap mmpll0_vote = {
.enable_reg = 0x0100,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmpll0_vote",
.parent_hws = (const struct clk_hw*[]){
&mmpll0.clkr.hw
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll mmpll1 = {
.l_reg = 0x0044,
.m_reg = 0x0048,
.n_reg = 0x004c,
.config_reg = 0x0050,
.mode_reg = 0x0040,
.status_reg = 0x005c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll1",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap mmpll1_vote = {
.enable_reg = 0x0100,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "mmpll1_vote",
.parent_hws = (const struct clk_hw*[]){
&mmpll1.clkr.hw
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll mmpll2 = {
.l_reg = 0x4104,
.m_reg = 0x4108,
.n_reg = 0x410c,
.config_reg = 0x4110,
.mode_reg = 0x4100,
.status_reg = 0x411c,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll2",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_pll mmpll3 = {
.l_reg = 0x0084,
.m_reg = 0x0088,
.n_reg = 0x008c,
.config_reg = 0x0090,
.mode_reg = 0x0080,
.status_reg = 0x009c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll3",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_pll mmpll4 = {
.l_reg = 0x00a4,
.m_reg = 0x00a8,
.n_reg = 0x00ac,
.config_reg = 0x00b0,
.mode_reg = 0x0080,
.status_reg = 0x00bc,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll4",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_GPLL0, 5 }
};
static const struct clk_parent_data mmcc_xo_mmpll0_mmpll1_gpll0[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &mmpll0_vote.hw },
{ .hw = &mmpll1_vote.hw },
{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
};
static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_HDMIPLL, 4 },
{ P_GPLL0, 5 },
{ P_DSI0PLL, 2 },
{ P_DSI1PLL, 3 }
};
static const struct clk_parent_data mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &mmpll0_vote.hw },
{ .fw_name = "hdmipll", .name = "hdmipll" },
{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
{ .fw_name = "dsi0pll", .name = "dsi0pll" },
{ .fw_name = "dsi1pll", .name = "dsi1pll" },
};
static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_GPLL0, 5 },
{ P_MMPLL2, 3 }
};
static const struct clk_parent_data mmcc_xo_mmpll0_1_2_gpll0[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &mmpll0_vote.hw },
{ .hw = &mmpll1_vote.hw },
{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
{ .hw = &mmpll2.clkr.hw },
};
static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_GPLL0, 5 },
{ P_MMPLL3, 3 }
};
static const struct clk_parent_data mmcc_xo_mmpll0_1_3_gpll0[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &mmpll0_vote.hw },
{ .hw = &mmpll1_vote.hw },
{ .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
{ .hw = &mmpll3.clkr.hw },
};
static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
{ P_XO, 0 },
{ P_EDPLINK, 4 },
{ P_HDMIPLL, 3 },
{ P_EDPVCO, 5 },
{ P_DSI0PLL, 1 },
{ P_DSI1PLL, 2 }
};
static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
{ .fw_name = "hdmipll", .name = "hdmipll" },
{ .fw_name = "edp_vco_div", .name = "edp_vco_div" },
{ .fw_name = "dsi0pll", .name = "dsi0pll" },
{ .fw_name = "dsi1pll", .name = "dsi1pll" },
};
static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
{ P_XO, 0 },
{ P_EDPLINK, 4 },
{ P_HDMIPLL, 3 },
{ P_GPLL0, 5 },
{ P_DSI0PLL, 1 },
{ P_DSI1PLL, 2 }
};
static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp_gpll0[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
{ .fw_name = "hdmipll", .name = "hdmipll" },
{ .fw_name = "gpll0_vote", .name = "gpll0_vote" },
{ .fw_name = "dsi0pll", .name = "dsi0pll" },
{ .fw_name = "dsi1pll", .name = "dsi1pll" },
};
static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
{ P_XO, 0 },
{ P_EDPLINK, 4 },
{ P_HDMIPLL, 3 },
{ P_GPLL0, 5 },
{ P_DSI0PLL_BYTE, 1 },
{ P_DSI1PLL_BYTE, 2 }
};
static const struct clk_parent_data mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .fw_name = "edp_link_clk", .name = "edp_link_clk" },
{ .fw_name = "hdmipll", .name = "hdmipll" },
{ .fw_name = "gpll0_vote", .name = "gpll0_vote" },
{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
{ .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
};
static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_GPLL0, 5 },
{ P_MMPLL4, 3 }
};
static const struct clk_parent_data mmcc_xo_mmpll0_1_4_gpll0[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &mmpll0.clkr.hw },
{ .hw = &mmpll1.clkr.hw },
{ .hw = &mmpll4.clkr.hw },
{ .fw_name = "gpll0", .name = "gpll0" },
};
static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_MMPLL4, 3 },
{ P_GPLL0, 5 },
{ P_GPLL1, 4 }
};
static const struct clk_parent_data mmcc_xo_mmpll0_1_4_gpll1_0[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &mmpll0.clkr.hw },
{ .hw = &mmpll1.clkr.hw },
{ .hw = &mmpll4.clkr.hw },
{ .fw_name = "gpll1", .name = "gpll1" },
{ .fw_name = "gpll0", .name = "gpll0" },
};
static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
{ P_MMPLL1, 2 },
{ P_MMPLL4, 3 },
{ P_GPLL0, 5 },
{ P_GPLL1, 4 },
{ P_MMSLEEP, 6 }
};
static const struct clk_parent_data mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &mmpll0.clkr.hw },
{ .hw = &mmpll1.clkr.hw },
{ .hw = &mmpll4.clkr.hw },
{ .fw_name = "gpll1", .name = "gpll1" },
{ .fw_name = "gpll0", .name = "gpll0" },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static struct clk_rcg2 mmss_ahb_clk_src = {
.cmd_rcgr = 0x5000,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmss_ahb_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_mmss_axi_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(37500000, P_GPLL0, 16, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(333430000, P_MMPLL1, 3.5, 0, 0),
F(400000000, P_MMPLL0, 2, 0, 0),
F(466800000, P_MMPLL1, 2.5, 0, 0),
};
static struct clk_rcg2 mmss_axi_clk_src = {
.cmd_rcgr = 0x5040,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_mmss_axi_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmss_axi_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_ocmemnoc_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(37500000, P_GPLL0, 16, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
F(109090000, P_GPLL0, 5.5, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(228570000, P_MMPLL0, 3.5, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
};
static struct clk_rcg2 ocmemnoc_clk_src = {
.cmd_rcgr = 0x5090,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_ocmemnoc_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ocmemnoc_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 csi0_clk_src = {
.cmd_rcgr = 0x3090,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
.freq_tbl = ftbl_camss_csi0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0_clk_src",
.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi1_clk_src = {
.cmd_rcgr = 0x3100,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
.freq_tbl = ftbl_camss_csi0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1_clk_src",
.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi2_clk_src = {
.cmd_rcgr = 0x3160,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
.freq_tbl = ftbl_camss_csi0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi2_clk_src",
.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi3_clk_src = {
.cmd_rcgr = 0x31c0,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
.freq_tbl = ftbl_camss_csi0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi3_clk_src",
.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
F(37500000, P_GPLL0, 16, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
F(60000000, P_GPLL0, 10, 0, 0),
F(80000000, P_GPLL0, 7.5, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(109090000, P_GPLL0, 5.5, 0, 0),
F(133330000, P_GPLL0, 4.5, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(228570000, P_MMPLL0, 3.5, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(465000000, P_MMPLL4, 2, 0, 0),
F(600000000, P_GPLL0, 1, 0, 0),
{ }
};
static struct clk_rcg2 vfe0_clk_src = {
.cmd_rcgr = 0x3600,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
.freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe0_clk_src",
.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 vfe1_clk_src = {
.cmd_rcgr = 0x3620,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
.freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe1_clk_src",
.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_mdss_mdp_clk[] = {
F(37500000, P_GPLL0, 16, 0, 0),
F(60000000, P_GPLL0, 10, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
F(85710000, P_GPLL0, 7, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(160000000, P_MMPLL0, 5, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
F(228570000, P_MMPLL0, 3.5, 0, 0),
F(300000000, P_GPLL0, 2, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 mdp_clk_src = {
.cmd_rcgr = 0x2040,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
.freq_tbl = ftbl_mdss_mdp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mdp_clk_src",
.parent_data = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gfx3d_clk_src = {
.cmd_rcgr = 0x4000,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src",
.parent_data = mmcc_xo_mmpll0_1_2_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_2_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
F(75000000, P_GPLL0, 8, 0, 0),
F(133330000, P_GPLL0, 4.5, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(228570000, P_MMPLL0, 3.5, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 jpeg0_clk_src = {
.cmd_rcgr = 0x3500,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg0_clk_src",
.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 jpeg1_clk_src = {
.cmd_rcgr = 0x3520,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg1_clk_src",
.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 jpeg2_clk_src = {
.cmd_rcgr = 0x3540,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg2_clk_src",
.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 pclk0_clk_src = {
.cmd_rcgr = 0x2000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk0_clk_src",
.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_rcg2 pclk1_clk_src = {
.cmd_rcgr = 0x2020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk1_clk_src",
.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(133330000, P_GPLL0, 4.5, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
F(465000000, P_MMPLL3, 2, 0, 0),
{ }
};
static struct clk_rcg2 vcodec0_clk_src = {
.cmd_rcgr = 0x1000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
.freq_tbl = ftbl_venus0_vcodec0_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vcodec0_clk_src",
.parent_data = mmcc_xo_mmpll0_1_3_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_avsync_vp_clk[] = {
F(150000000, P_GPLL0, 4, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 vp_clk_src = {
.cmd_rcgr = 0x2430,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_avsync_vp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vp_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 cci_clk_src = {
.cmd_rcgr = 0x3300,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
.freq_tbl = ftbl_camss_cci_cci_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "cci_clk_src",
.parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
F(10000, P_XO, 16, 1, 120),
F(24000, P_XO, 16, 1, 50),
F(6000000, P_GPLL0, 10, 1, 10),
F(12000000, P_GPLL0, 10, 1, 5),
F(13000000, P_GPLL0, 4, 13, 150),
F(24000000, P_GPLL0, 5, 1, 5),
{ }
};
static struct clk_rcg2 camss_gp0_clk_src = {
.cmd_rcgr = 0x3420,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
.freq_tbl = ftbl_camss_gp0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp0_clk_src",
.parent_data = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0_sleep),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 camss_gp1_clk_src = {
.cmd_rcgr = 0x3450,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
.freq_tbl = ftbl_camss_gp0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp1_clk_src",
.parent_data = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0_sleep),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
F(4800000, P_XO, 4, 0, 0),
F(6000000, P_GPLL0, 10, 1, 10),
F(8000000, P_GPLL0, 15, 1, 5),
F(9600000, P_XO, 2, 0, 0),
F(16000000, P_MMPLL0, 10, 1, 5),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 5, 1, 5),
F(32000000, P_MMPLL0, 5, 1, 5),
F(48000000, P_GPLL0, 12.5, 0, 0),
F(64000000, P_MMPLL0, 12.5, 0, 0),
{ }
};
static struct clk_rcg2 mclk0_clk_src = {
.cmd_rcgr = 0x3360,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
.freq_tbl = ftbl_camss_mclk0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk0_clk_src",
.parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk1_clk_src = {
.cmd_rcgr = 0x3390,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
.freq_tbl = ftbl_camss_mclk0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk1_clk_src",
.parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk2_clk_src = {
.cmd_rcgr = 0x33c0,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
.freq_tbl = ftbl_camss_mclk0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk2_clk_src",
.parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk3_clk_src = {
.cmd_rcgr = 0x33f0,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
.freq_tbl = ftbl_camss_mclk0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk3_clk_src",
.parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 csi0phytimer_clk_src = {
.cmd_rcgr = 0x3000,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0phytimer_clk_src",
.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi1phytimer_clk_src = {
.cmd_rcgr = 0x3030,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1phytimer_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi2phytimer_clk_src = {
.cmd_rcgr = 0x3060,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi2phytimer_clk_src",
.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
F(133330000, P_GPLL0, 4.5, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(372000000, P_MMPLL4, 2.5, 0, 0),
F(465000000, P_MMPLL4, 2, 0, 0),
F(600000000, P_GPLL0, 1, 0, 0),
{ }
};
static struct clk_rcg2 cpp_clk_src = {
.cmd_rcgr = 0x3640,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
.freq_tbl = ftbl_camss_vfe_cpp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "cpp_clk_src",
.parent_data = mmcc_xo_mmpll0_1_4_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 byte0_clk_src = {
.cmd_rcgr = 0x2120,
.hid_width = 5,
.parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte0_clk_src",
.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_rcg2 byte1_clk_src = {
.cmd_rcgr = 0x2140,
.hid_width = 5,
.parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte1_clk_src",
.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 edpaux_clk_src = {
.cmd_rcgr = 0x20e0,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_mdss_edpaux_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "edpaux_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_mdss_edplink_clk[] = {
F(135000000, P_EDPLINK, 2, 0, 0),
F(270000000, P_EDPLINK, 11, 0, 0),
{ }
};
static struct clk_rcg2 edplink_clk_src = {
.cmd_rcgr = 0x20c0,
.hid_width = 5,
.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
.freq_tbl = ftbl_mdss_edplink_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "edplink_clk_src",
.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct freq_tbl edp_pixel_freq_tbl[] = {
{ .src = P_EDPVCO },
{ }
};
static struct clk_rcg2 edppixel_clk_src = {
.cmd_rcgr = 0x20a0,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmcc_xo_dsi_hdmi_edp_map,
.freq_tbl = edp_pixel_freq_tbl,
.clkr.hw.init = &(struct clk_init_data){
.name = "edppixel_clk_src",
.parent_data = mmcc_xo_dsi_hdmi_edp,
.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp),
.ops = &clk_edp_pixel_ops,
},
};
static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 esc0_clk_src = {
.cmd_rcgr = 0x2160,
.hid_width = 5,
.parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
.freq_tbl = ftbl_mdss_esc0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc0_clk_src",
.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 esc1_clk_src = {
.cmd_rcgr = 0x2180,
.hid_width = 5,
.parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
.freq_tbl = ftbl_mdss_esc0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc1_clk_src",
.parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl extpclk_freq_tbl[] = {
{ .src = P_HDMIPLL },
{ }
};
static struct clk_rcg2 extpclk_clk_src = {
.cmd_rcgr = 0x2060,
.hid_width = 5,
.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
.freq_tbl = extpclk_freq_tbl,
.clkr.hw.init = &(struct clk_init_data){
.name = "extpclk_clk_src",
.parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
.ops = &clk_byte_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 hdmi_clk_src = {
.cmd_rcgr = 0x2100,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_mdss_hdmi_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "hdmi_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_mdss_vsync_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 vsync_clk_src = {
.cmd_rcgr = 0x2080,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_mdss_vsync_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vsync_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_mmss_rbcpr_clk[] = {
F(50000000, P_GPLL0, 12, 0, 0),
{ }
};
static struct clk_rcg2 rbcpr_clk_src = {
.cmd_rcgr = 0x4060,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_mmss_rbcpr_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "rbcpr_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 rbbmtimer_clk_src = {
.cmd_rcgr = 0x4090,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_oxili_rbbmtimer_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "rbbmtimer_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_vpu_maple_clk[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(133330000, P_GPLL0, 4.5, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
F(465000000, P_MMPLL3, 2, 0, 0),
{ }
};
static struct clk_rcg2 maple_clk_src = {
.cmd_rcgr = 0x1320,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_vpu_maple_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "maple_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_vpu_vdp_clk[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
F(400000000, P_MMPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 vdp_clk_src = {
.cmd_rcgr = 0x1300,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_vpu_vdp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vdp_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct freq_tbl ftbl_vpu_bus_clk[] = {
F(40000000, P_GPLL0, 15, 0, 0),
F(80000000, P_MMPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 vpu_bus_clk_src = {
.cmd_rcgr = 0x1340,
.hid_width = 5,
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.freq_tbl = ftbl_vpu_bus_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vpu_bus_clk_src",
.parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
.num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch mmss_cxo_clk = {
.halt_reg = 0x5104,
.clkr = {
.enable_reg = 0x5104,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_cxo_clk",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmss_sleepclk_clk = {
.halt_reg = 0x5100,
.clkr = {
.enable_reg = 0x5100,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_sleepclk_clk",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch avsync_ahb_clk = {
.halt_reg = 0x2414,
.clkr = {
.enable_reg = 0x2414,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "avsync_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch avsync_edppixel_clk = {
.halt_reg = 0x2418,
.clkr = {
.enable_reg = 0x2418,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "avsync_edppixel_clk",
.parent_hws = (const struct clk_hw*[]){
&edppixel_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch avsync_extpclk_clk = {
.halt_reg = 0x2410,
.clkr = {
.enable_reg = 0x2410,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "avsync_extpclk_clk",
.parent_hws = (const struct clk_hw*[]){
&extpclk_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch avsync_pclk0_clk = {
.halt_reg = 0x241c,
.clkr = {
.enable_reg = 0x241c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "avsync_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&pclk0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch avsync_pclk1_clk = {
.halt_reg = 0x2420,
.clkr = {
.enable_reg = 0x2420,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "avsync_pclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&pclk1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch avsync_vp_clk = {
.halt_reg = 0x2404,
.clkr = {
.enable_reg = 0x2404,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "avsync_vp_clk",
.parent_hws = (const struct clk_hw*[]){
&vp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_ahb_clk = {
.halt_reg = 0x348c,
.clkr = {
.enable_reg = 0x348c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cci_cci_ahb_clk = {
.halt_reg = 0x3348,
.clkr = {
.enable_reg = 0x3348,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cci_cci_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cci_cci_clk = {
.halt_reg = 0x3344,
.clkr = {
.enable_reg = 0x3344,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cci_cci_clk",
.parent_hws = (const struct clk_hw*[]){
&cci_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0_ahb_clk = {
.halt_reg = 0x30bc,
.clkr = {
.enable_reg = 0x30bc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0_clk = {
.halt_reg = 0x30b4,
.clkr = {
.enable_reg = 0x30b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0phy_clk = {
.halt_reg = 0x30c4,
.clkr = {
.enable_reg = 0x30c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0pix_clk = {
.halt_reg = 0x30e4,
.clkr = {
.enable_reg = 0x30e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi0rdi_clk = {
.halt_reg = 0x30d4,
.clkr = {
.enable_reg = 0x30d4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1_ahb_clk = {
.halt_reg = 0x3128,
.clkr = {
.enable_reg = 0x3128,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1_clk = {
.halt_reg = 0x3124,
.clkr = {
.enable_reg = 0x3124,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1phy_clk = {
.halt_reg = 0x3134,
.clkr = {
.enable_reg = 0x3134,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1pix_clk = {
.halt_reg = 0x3154,
.clkr = {
.enable_reg = 0x3154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi1rdi_clk = {
.halt_reg = 0x3144,
.clkr = {
.enable_reg = 0x3144,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2_ahb_clk = {
.halt_reg = 0x3188,
.clkr = {
.enable_reg = 0x3188,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2_clk = {
.halt_reg = 0x3184,
.clkr = {
.enable_reg = 0x3184,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2phy_clk = {
.halt_reg = 0x3194,
.clkr = {
.enable_reg = 0x3194,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2pix_clk = {
.halt_reg = 0x31b4,
.clkr = {
.enable_reg = 0x31b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi2rdi_clk = {
.halt_reg = 0x31a4,
.clkr = {
.enable_reg = 0x31a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3_ahb_clk = {
.halt_reg = 0x31e8,
.clkr = {
.enable_reg = 0x31e8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3_clk = {
.halt_reg = 0x31e4,
.clkr = {
.enable_reg = 0x31e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3_clk",
.parent_hws = (const struct clk_hw*[]){
&csi3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3phy_clk = {
.halt_reg = 0x31f4,
.clkr = {
.enable_reg = 0x31f4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3phy_clk",
.parent_hws = (const struct clk_hw*[]){
&csi3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3pix_clk = {
.halt_reg = 0x3214,
.clkr = {
.enable_reg = 0x3214,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3pix_clk",
.parent_hws = (const struct clk_hw*[]){
&csi3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi3rdi_clk = {
.halt_reg = 0x3204,
.clkr = {
.enable_reg = 0x3204,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3rdi_clk",
.parent_hws = (const struct clk_hw*[]){
&csi3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi_vfe0_clk = {
.halt_reg = 0x3704,
.clkr = {
.enable_reg = 0x3704,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi_vfe0_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_csi_vfe1_clk = {
.halt_reg = 0x3714,
.clkr = {
.enable_reg = 0x3714,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi_vfe1_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_gp0_clk = {
.halt_reg = 0x3444,
.clkr = {
.enable_reg = 0x3444,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_gp0_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_gp0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_gp1_clk = {
.halt_reg = 0x3474,
.clkr = {
.enable_reg = 0x3474,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&camss_gp1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_ispif_ahb_clk = {
.halt_reg = 0x3224,
.clkr = {
.enable_reg = 0x3224,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_ispif_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_jpeg0_clk = {
.halt_reg = 0x35a8,
.clkr = {
.enable_reg = 0x35a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg0_clk",
.parent_hws = (const struct clk_hw*[]){
&jpeg0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_jpeg1_clk = {
.halt_reg = 0x35ac,
.clkr = {
.enable_reg = 0x35ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg1_clk",
.parent_hws = (const struct clk_hw*[]){
&jpeg1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_jpeg2_clk = {
.halt_reg = 0x35b0,
.clkr = {
.enable_reg = 0x35b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg2_clk",
.parent_hws = (const struct clk_hw*[]){
&jpeg2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
.halt_reg = 0x35b4,
.clkr = {
.enable_reg = 0x35b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_jpeg_jpeg_axi_clk = {
.halt_reg = 0x35b8,
.clkr = {
.enable_reg = 0x35b8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_mclk0_clk = {
.halt_reg = 0x3384,
.clkr = {
.enable_reg = 0x3384,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_mclk1_clk = {
.halt_reg = 0x33b4,
.clkr = {
.enable_reg = 0x33b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_mclk2_clk = {
.halt_reg = 0x33e4,
.clkr = {
.enable_reg = 0x33e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk2_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_mclk3_clk = {
.halt_reg = 0x3414,
.clkr = {
.enable_reg = 0x3414,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk3_clk",
.parent_hws = (const struct clk_hw*[]){
&mclk3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_micro_ahb_clk = {
.halt_reg = 0x3494,
.clkr = {
.enable_reg = 0x3494,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_micro_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_phy0_csi0phytimer_clk = {
.halt_reg = 0x3024,
.clkr = {
.enable_reg = 0x3024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_phy0_csi0phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&csi0phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_phy1_csi1phytimer_clk = {
.halt_reg = 0x3054,
.clkr = {
.enable_reg = 0x3054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_phy1_csi1phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&csi1phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_phy2_csi2phytimer_clk = {
.halt_reg = 0x3084,
.clkr = {
.enable_reg = 0x3084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_phy2_csi2phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&csi2phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_top_ahb_clk = {
.halt_reg = 0x3484,
.clkr = {
.enable_reg = 0x3484,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_top_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_cpp_ahb_clk = {
.halt_reg = 0x36b4,
.clkr = {
.enable_reg = 0x36b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_cpp_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_cpp_clk = {
.halt_reg = 0x36b0,
.clkr = {
.enable_reg = 0x36b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_cpp_clk",
.parent_hws = (const struct clk_hw*[]){
&cpp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_vfe0_clk = {
.halt_reg = 0x36a8,
.clkr = {
.enable_reg = 0x36a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vfe0_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_vfe1_clk = {
.halt_reg = 0x36ac,
.clkr = {
.enable_reg = 0x36ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vfe1_clk",
.parent_hws = (const struct clk_hw*[]){
&vfe1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_vfe_ahb_clk = {
.halt_reg = 0x36b8,
.clkr = {
.enable_reg = 0x36b8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vfe_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe_vfe_axi_clk = {
.halt_reg = 0x36bc,
.clkr = {
.enable_reg = 0x36bc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vfe_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_ahb_clk = {
.halt_reg = 0x2308,
.clkr = {
.enable_reg = 0x2308,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_axi_clk = {
.halt_reg = 0x2310,
.clkr = {
.enable_reg = 0x2310,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_byte0_clk = {
.halt_reg = 0x233c,
.clkr = {
.enable_reg = 0x233c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]){
&byte0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_byte1_clk = {
.halt_reg = 0x2340,
.clkr = {
.enable_reg = 0x2340,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_byte1_clk",
.parent_hws = (const struct clk_hw*[]){
&byte1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_edpaux_clk = {
.halt_reg = 0x2334,
.clkr = {
.enable_reg = 0x2334,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_edpaux_clk",
.parent_hws = (const struct clk_hw*[]){
&edpaux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_edplink_clk = {
.halt_reg = 0x2330,
.clkr = {
.enable_reg = 0x2330,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_edplink_clk",
.parent_hws = (const struct clk_hw*[]){
&edplink_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_edppixel_clk = {
.halt_reg = 0x232c,
.clkr = {
.enable_reg = 0x232c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_edppixel_clk",
.parent_hws = (const struct clk_hw*[]){
&edppixel_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_esc0_clk = {
.halt_reg = 0x2344,
.clkr = {
.enable_reg = 0x2344,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]){
&esc0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_esc1_clk = {
.halt_reg = 0x2348,
.clkr = {
.enable_reg = 0x2348,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_esc1_clk",
.parent_hws = (const struct clk_hw*[]){
&esc1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_extpclk_clk = {
.halt_reg = 0x2324,
.clkr = {
.enable_reg = 0x2324,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_extpclk_clk",
.parent_hws = (const struct clk_hw*[]){
&extpclk_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_hdmi_ahb_clk = {
.halt_reg = 0x230c,
.clkr = {
.enable_reg = 0x230c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_hdmi_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_hdmi_clk = {
.halt_reg = 0x2338,
.clkr = {
.enable_reg = 0x2338,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_hdmi_clk",
.parent_hws = (const struct clk_hw*[]){
&hdmi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_mdp_clk = {
.halt_reg = 0x231c,
.clkr = {
.enable_reg = 0x231c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&mdp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_mdp_lut_clk = {
.halt_reg = 0x2320,
.clkr = {
.enable_reg = 0x2320,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_mdp_lut_clk",
.parent_hws = (const struct clk_hw*[]){
&mdp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_pclk0_clk = {
.halt_reg = 0x2314,
.clkr = {
.enable_reg = 0x2314,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&pclk0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_pclk1_clk = {
.halt_reg = 0x2318,
.clkr = {
.enable_reg = 0x2318,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_pclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&pclk1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_vsync_clk = {
.halt_reg = 0x2328,
.clkr = {
.enable_reg = 0x2328,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&vsync_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmss_rbcpr_ahb_clk = {
.halt_reg = 0x4088,
.clkr = {
.enable_reg = 0x4088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_rbcpr_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmss_rbcpr_clk = {
.halt_reg = 0x4084,
.clkr = {
.enable_reg = 0x4084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_rbcpr_clk",
.parent_hws = (const struct clk_hw*[]){
&rbcpr_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmss_misc_ahb_clk = {
.halt_reg = 0x502c,
.clkr = {
.enable_reg = 0x502c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_misc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmss_mmssnoc_ahb_clk = {
.halt_reg = 0x5024,
.clkr = {
.enable_reg = 0x5024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_mmssnoc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
},
};
static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
.halt_reg = 0x5028,
.clkr = {
.enable_reg = 0x5028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_mmssnoc_bto_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
},
};
static struct clk_branch mmss_mmssnoc_axi_clk = {
.halt_reg = 0x506c,
.clkr = {
.enable_reg = 0x506c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_mmssnoc_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mmss_s0_axi_clk = {
.halt_reg = 0x5064,
.clkr = {
.enable_reg = 0x5064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_s0_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
},
};
static struct clk_branch ocmemcx_ahb_clk = {
.halt_reg = 0x405c,
.clkr = {
.enable_reg = 0x405c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "ocmemcx_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch ocmemcx_ocmemnoc_clk = {
.halt_reg = 0x4058,
.clkr = {
.enable_reg = 0x4058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "ocmemcx_ocmemnoc_clk",
.parent_hws = (const struct clk_hw*[]){
&ocmemnoc_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch oxili_ocmemgx_clk = {
.halt_reg = 0x402c,
.clkr = {
.enable_reg = 0x402c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "oxili_ocmemgx_clk",
.parent_hws = (const struct clk_hw*[]){
&gfx3d_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch oxili_gfx3d_clk = {
.halt_reg = 0x4028,
.clkr = {
.enable_reg = 0x4028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "oxili_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]){
&gfx3d_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch oxili_rbbmtimer_clk = {
.halt_reg = 0x40b0,
.clkr = {
.enable_reg = 0x40b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "oxili_rbbmtimer_clk",
.parent_hws = (const struct clk_hw*[]){
&rbbmtimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch oxilicx_ahb_clk = {
.halt_reg = 0x403c,
.clkr = {
.enable_reg = 0x403c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "oxilicx_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch venus0_ahb_clk = {
.halt_reg = 0x1030,
.clkr = {
.enable_reg = 0x1030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch venus0_axi_clk = {
.halt_reg = 0x1034,
.clkr = {
.enable_reg = 0x1034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch venus0_core0_vcodec_clk = {
.halt_reg = 0x1048,
.clkr = {
.enable_reg = 0x1048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_core0_vcodec_clk",
.parent_hws = (const struct clk_hw*[]){
&vcodec0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch venus0_core1_vcodec_clk = {
.halt_reg = 0x104c,
.clkr = {
.enable_reg = 0x104c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_core1_vcodec_clk",
.parent_hws = (const struct clk_hw*[]){
&vcodec0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch venus0_ocmemnoc_clk = {
.halt_reg = 0x1038,
.clkr = {
.enable_reg = 0x1038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_ocmemnoc_clk",
.parent_hws = (const struct clk_hw*[]){
&ocmemnoc_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch venus0_vcodec0_clk = {
.halt_reg = 0x1028,
.clkr = {
.enable_reg = 0x1028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_vcodec0_clk",
.parent_hws = (const struct clk_hw*[]){
&vcodec0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch vpu_ahb_clk = {
.halt_reg = 0x1430,
.clkr = {
.enable_reg = 0x1430,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpu_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch vpu_axi_clk = {
.halt_reg = 0x143c,
.clkr = {
.enable_reg = 0x143c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpu_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch vpu_bus_clk = {
.halt_reg = 0x1440,
.clkr = {
.enable_reg = 0x1440,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpu_bus_clk",
.parent_hws = (const struct clk_hw*[]){
&vpu_bus_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch vpu_cxo_clk = {
.halt_reg = 0x1434,
.clkr = {
.enable_reg = 0x1434,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpu_cxo_clk",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch vpu_maple_clk = {
.halt_reg = 0x142c,
.clkr = {
.enable_reg = 0x142c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpu_maple_clk",
.parent_hws = (const struct clk_hw*[]){
&maple_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch vpu_sleep_clk = {
.halt_reg = 0x1438,
.clkr = {
.enable_reg = 0x1438,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpu_sleep_clk",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch vpu_vdp_clk = {
.halt_reg = 0x1428,
.clkr = {
.enable_reg = 0x1428,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpu_vdp_clk",
.parent_hws = (const struct clk_hw*[]){
&vdp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct pll_config mmpll1_config = {
.l = 60,
.m = 25,
.n = 32,
.vco_val = 0x0,
.vco_mask = 0x3 << 20,
.pre_div_val = 0x0,
.pre_div_mask = 0x7 << 12,
.post_div_val = 0x0,
.post_div_mask = 0x3 << 8,
.mn_ena_mask = BIT(24),
.main_output_mask = BIT(0),
};
static const struct pll_config mmpll3_config = {
.l = 48,
.m = 7,
.n = 16,
.vco_val = 0x0,
.vco_mask = 0x3 << 20,
.pre_div_val = 0x0,
.pre_div_mask = 0x7 << 12,
.post_div_val = 0x0,
.post_div_mask = 0x3 << 8,
.mn_ena_mask = BIT(24),
.main_output_mask = BIT(0),
.aux_output_mask = BIT(1),
};
static struct gdsc venus0_gdsc = {
.gdscr = 0x1024,
.pd = {
.name = "venus0",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc venus0_core0_gdsc = {
.gdscr = 0x1040,
.pd = {
.name = "venus0_core0",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc venus0_core1_gdsc = {
.gdscr = 0x1044,
.pd = {
.name = "venus0_core1",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x2304,
.cxcs = (unsigned int []){ 0x231c, 0x2320 },
.cxc_count = 2,
.pd = {
.name = "mdss",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc camss_jpeg_gdsc = {
.gdscr = 0x35a4,
.pd = {
.name = "camss_jpeg",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc camss_vfe_gdsc = {
.gdscr = 0x36a4,
.cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x36b0 },
.cxc_count = 3,
.pd = {
.name = "camss_vfe",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc oxili_gdsc = {
.gdscr = 0x4024,
.cxcs = (unsigned int []){ 0x4028 },
.cxc_count = 1,
.pd = {
.name = "oxili",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc oxilicx_gdsc = {
.gdscr = 0x4034,
.pd = {
.name = "oxilicx",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *mmcc_apq8084_clocks[] = {
[MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
[MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
[MMPLL0] = &mmpll0.clkr,
[MMPLL0_VOTE] = &mmpll0_vote,
[MMPLL1] = &mmpll1.clkr,
[MMPLL1_VOTE] = &mmpll1_vote,
[MMPLL2] = &mmpll2.clkr,
[MMPLL3] = &mmpll3.clkr,
[MMPLL4] = &mmpll4.clkr,
[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
[CSI3_CLK_SRC] = &csi3_clk_src.clkr,
[VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
[VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
[MDP_CLK_SRC] = &mdp_clk_src.clkr,
[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
[PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
[OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
[JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
[JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
[EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
[EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
[VP_CLK_SRC] = &vp_clk_src.clkr,
[CCI_CLK_SRC] = &cci_clk_src.clkr,
[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
[MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
[MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
[CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
[CPP_CLK_SRC] = &cpp_clk_src.clkr,
[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
[BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
[EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
[EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
[ESC1_CLK_SRC] = &esc1_clk_src.clkr,
[HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
[MMSS_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
[RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
[MAPLE_CLK_SRC] = &maple_clk_src.clkr,
[VDP_CLK_SRC] = &vdp_clk_src.clkr,
[VPU_BUS_CLK_SRC] = &vpu_bus_clk_src.clkr,
[MMSS_CXO_CLK] = &mmss_cxo_clk.clkr,
[MMSS_SLEEPCLK_CLK] = &mmss_sleepclk_clk.clkr,
[AVSYNC_AHB_CLK] = &avsync_ahb_clk.clkr,
[AVSYNC_EDPPIXEL_CLK] = &avsync_edppixel_clk.clkr,
[AVSYNC_EXTPCLK_CLK] = &avsync_extpclk_clk.clkr,
[AVSYNC_PCLK0_CLK] = &avsync_pclk0_clk.clkr,
[AVSYNC_PCLK1_CLK] = &avsync_pclk1_clk.clkr,
[AVSYNC_VP_CLK] = &avsync_vp_clk.clkr,
[CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
[CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
[CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
[CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
[CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
[CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
[CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
[CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
[CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
[CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
[CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
[CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
[CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
[CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
[CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
[CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
[CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
[CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
[CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
[CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
[CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
[CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
[CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
[CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
[CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
[CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
[CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
[CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
[CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
[CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
[CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
[CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
[CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
[CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
[CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
[CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
[CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
[CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
[CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
[CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
[CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
[CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
[CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
[CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
[CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
[CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
[CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
[CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
[MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
[MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
[MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
[MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
[MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
[MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
[MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
[MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
[MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
[MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
[MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
[MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
[MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
[MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
[MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
[MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
[MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
[MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
[MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
[MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
[MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
[MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
[MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
[OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
[OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
[OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
[OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr,
[OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
[VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
[VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
[VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr,
[VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr,
[VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
[VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
[VPU_AHB_CLK] = &vpu_ahb_clk.clkr,
[VPU_AXI_CLK] = &vpu_axi_clk.clkr,
[VPU_BUS_CLK] = &vpu_bus_clk.clkr,
[VPU_CXO_CLK] = &vpu_cxo_clk.clkr,
[VPU_MAPLE_CLK] = &vpu_maple_clk.clkr,
[VPU_SLEEP_CLK] = &vpu_sleep_clk.clkr,
[VPU_VDP_CLK] = &vpu_vdp_clk.clkr,
};
static const struct qcom_reset_map mmcc_apq8084_resets[] = {
[MMSS_SPDM_RESET] = { 0x0200 },
[MMSS_SPDM_RM_RESET] = { 0x0300 },
[VENUS0_RESET] = { 0x1020 },
[VPU_RESET] = { 0x1400 },
[MDSS_RESET] = { 0x2300 },
[AVSYNC_RESET] = { 0x2400 },
[CAMSS_PHY0_RESET] = { 0x3020 },
[CAMSS_PHY1_RESET] = { 0x3050 },
[CAMSS_PHY2_RESET] = { 0x3080 },
[CAMSS_CSI0_RESET] = { 0x30b0 },
[CAMSS_CSI0PHY_RESET] = { 0x30c0 },
[CAMSS_CSI0RDI_RESET] = { 0x30d0 },
[CAMSS_CSI0PIX_RESET] = { 0x30e0 },
[CAMSS_CSI1_RESET] = { 0x3120 },
[CAMSS_CSI1PHY_RESET] = { 0x3130 },
[CAMSS_CSI1RDI_RESET] = { 0x3140 },
[CAMSS_CSI1PIX_RESET] = { 0x3150 },
[CAMSS_CSI2_RESET] = { 0x3180 },
[CAMSS_CSI2PHY_RESET] = { 0x3190 },
[CAMSS_CSI2RDI_RESET] = { 0x31a0 },
[CAMSS_CSI2PIX_RESET] = { 0x31b0 },
[CAMSS_CSI3_RESET] = { 0x31e0 },
[CAMSS_CSI3PHY_RESET] = { 0x31f0 },
[CAMSS_CSI3RDI_RESET] = { 0x3200 },
[CAMSS_CSI3PIX_RESET] = { 0x3210 },
[CAMSS_ISPIF_RESET] = { 0x3220 },
[CAMSS_CCI_RESET] = { 0x3340 },
[CAMSS_MCLK0_RESET] = { 0x3380 },
[CAMSS_MCLK1_RESET] = { 0x33b0 },
[CAMSS_MCLK2_RESET] = { 0x33e0 },
[CAMSS_MCLK3_RESET] = { 0x3410 },
[CAMSS_GP0_RESET] = { 0x3440 },
[CAMSS_GP1_RESET] = { 0x3470 },
[CAMSS_TOP_RESET] = { 0x3480 },
[CAMSS_AHB_RESET] = { 0x3488 },
[CAMSS_MICRO_RESET] = { 0x3490 },
[CAMSS_JPEG_RESET] = { 0x35a0 },
[CAMSS_VFE_RESET] = { 0x36a0 },
[CAMSS_CSI_VFE0_RESET] = { 0x3700 },
[CAMSS_CSI_VFE1_RESET] = { 0x3710 },
[OXILI_RESET] = { 0x4020 },
[OXILICX_RESET] = { 0x4030 },
[OCMEMCX_RESET] = { 0x4050 },
[MMSS_RBCRP_RESET] = { 0x4080 },
[MMSSNOCAHB_RESET] = { 0x5020 },
[MMSSNOCAXI_RESET] = { 0x5060 },
};
static struct gdsc *mmcc_apq8084_gdscs[] = {
[VENUS0_GDSC] = &venus0_gdsc,
[VENUS0_CORE0_GDSC] = &venus0_core0_gdsc,
[VENUS0_CORE1_GDSC] = &venus0_core1_gdsc,
[MDSS_GDSC] = &mdss_gdsc,
[CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
[CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
[OXILI_GDSC] = &oxili_gdsc,
[OXILICX_GDSC] = &oxilicx_gdsc,
};
static const struct regmap_config mmcc_apq8084_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x5104,
.fast_io = true,
};
static const struct qcom_cc_desc mmcc_apq8084_desc = {
.config = &mmcc_apq8084_regmap_config,
.clks = mmcc_apq8084_clocks,
.num_clks = ARRAY_SIZE(mmcc_apq8084_clocks),
.resets = mmcc_apq8084_resets,
.num_resets = ARRAY_SIZE(mmcc_apq8084_resets),
.gdscs = mmcc_apq8084_gdscs,
.num_gdscs = ARRAY_SIZE(mmcc_apq8084_gdscs),
};
static const struct of_device_id mmcc_apq8084_match_table[] = {
{ .compatible = "qcom,mmcc-apq8084" },
{ }
};
MODULE_DEVICE_TABLE(of, mmcc_apq8084_match_table);
static int mmcc_apq8084_probe(struct platform_device *pdev)
{
int ret;
struct regmap *regmap;
ret = qcom_cc_probe(pdev, &mmcc_apq8084_desc);
if (ret)
return ret;
regmap = dev_get_regmap(&pdev->dev, NULL);
clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
return 0;
}
static struct platform_driver mmcc_apq8084_driver = {
.probe = mmcc_apq8084_probe,
.driver = {
.name = "mmcc-apq8084",
.of_match_table = mmcc_apq8084_match_table,
},
};
module_platform_driver(mmcc_apq8084_driver);
MODULE_DESCRIPTION("QCOM MMCC APQ8084 Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:mmcc-apq8084");
| linux-master | drivers/clk/qcom/mmcc-apq8084.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, The Linux Foundation. All rights reserved.
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include "clk-regmap.h"
#include "clk-hfpll.h"
static const struct hfpll_data hdata = {
.mode_reg = 0x00,
.l_reg = 0x04,
.m_reg = 0x08,
.n_reg = 0x0c,
.user_reg = 0x10,
.config_reg = 0x14,
.config_val = 0x430405d,
.status_reg = 0x1c,
.lock_bit = 16,
.user_val = 0x8,
.user_vco_mask = 0x100000,
.low_vco_max_rate = 1248000000,
.min_rate = 537600000UL,
.max_rate = 2900000000UL,
};
static const struct of_device_id qcom_hfpll_match_table[] = {
{ .compatible = "qcom,hfpll" },
{ }
};
MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
static const struct regmap_config hfpll_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x30,
.fast_io = true,
};
static int qcom_hfpll_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
void __iomem *base;
struct regmap *regmap;
struct clk_hfpll *h;
struct clk_init_data init = {
.num_parents = 1,
.ops = &clk_ops_hfpll,
/*
* rather than marking the clock critical and forcing the clock
* to be always enabled, we make sure that the clock is not
* disabled: the firmware remains responsible of enabling this
* clock (for more info check the commit log)
*/
.flags = CLK_IGNORE_UNUSED,
};
int ret;
struct clk_parent_data pdata = { .index = 0 };
h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
if (!h)
return -ENOMEM;
base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
if (IS_ERR(base))
return PTR_ERR(base);
regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
if (of_property_read_string_index(dev->of_node, "clock-output-names",
0, &init.name))
return -ENODEV;
init.parent_data = &pdata;
h->d = &hdata;
h->clkr.hw.init = &init;
spin_lock_init(&h->lock);
ret = devm_clk_register_regmap(dev, &h->clkr);
if (ret) {
dev_err(dev, "failed to register regmap clock: %d\n", ret);
return ret;
}
return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
&h->clkr.hw);
}
static struct platform_driver qcom_hfpll_driver = {
.probe = qcom_hfpll_probe,
.driver = {
.name = "qcom-hfpll",
.of_match_table = qcom_hfpll_match_table,
},
};
module_platform_driver(qcom_hfpll_driver);
MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:qcom-hfpll");
| linux-master | drivers/clk/qcom/hfpll.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_GCC_GPLL0_OUT_EVEN,
P_GCC_GPLL0_OUT_MAIN,
P_GCC_GPLL0_OUT_ODD,
P_GCC_GPLL10_OUT_MAIN,
P_GCC_GPLL4_OUT_MAIN,
P_GCC_GPLL9_OUT_MAIN,
P_PCIE_0_PIPE_CLK,
P_PCIE_1_PIPE_CLK,
P_SLEEP_CLK,
P_UFS_PHY_RX_SYMBOL_0_CLK,
P_UFS_PHY_RX_SYMBOL_1_CLK,
P_UFS_PHY_TX_SYMBOL_0_CLK,
P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
P_GCC_MSS_GPLL0_MAIN_DIV_CLK,
};
static struct clk_alpha_pll gcc_gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ops,
},
},
};
static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_gcc_gpll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gpll0_out_even",
.parent_hws = (const struct clk_hw*[]){
&gcc_gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
static const struct clk_div_table post_div_table_gcc_gpll0_out_odd[] = {
{ 0x3, 3 },
{ }
};
static struct clk_alpha_pll_postdiv gcc_gpll0_out_odd = {
.offset = 0x0,
.post_div_shift = 12,
.post_div_table = post_div_table_gcc_gpll0_out_odd,
.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_odd),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gpll0_out_odd",
.parent_hws = (const struct clk_hw*[]){
&gcc_gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_ops,
},
};
static struct clk_alpha_pll gcc_gpll1 = {
.offset = 0x1000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpll1",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll10 = {
.offset = 0x1e000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpll10",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll4 = {
.offset = 0x76000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpll4",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll9 = {
.offset = 0x1c000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpll9",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ops,
},
},
};
static struct clk_branch gcc_mss_gpll0_main_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_gpll0_main_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_gpll0_out_even.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL0_OUT_ODD, 3 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll0_out_odd.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "sleep_clk" },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL0_OUT_ODD, 3 },
{ P_SLEEP_CLK, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll0_out_odd.clkr.hw },
{ .fw_name = "sleep_clk" },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL0_OUT_ODD, 3 },
{ P_GCC_GPLL10_OUT_MAIN, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_8[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll0_out_odd.clkr.hw },
{ .hw = &gcc_gpll10.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_9[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL9_OUT_MAIN, 2 },
{ P_GCC_GPLL0_OUT_ODD, 3 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_9[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll9.clkr.hw },
{ .hw = &gcc_gpll0_out_odd.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_10[] = {
{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_10[] = {
{ .fw_name = "ufs_phy_rx_symbol_0_clk" },
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_11[] = {
{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_11[] = {
{ .fw_name = "ufs_phy_rx_symbol_1_clk" },
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_12[] = {
{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_12[] = {
{ .fw_name = "ufs_phy_tx_symbol_0_clk" },
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_13[] = {
{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_13[] = {
{ .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_14[] = {
{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_14[] = {
{ .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_15[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_MSS_GPLL0_MAIN_DIV_CLK, 1 },
};
static const struct clk_parent_data gcc_parent_data_15[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gcc_mss_gpll0_main_div_clk_src.clkr.hw },
};
static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
.reg = 0x6b054,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "pcie_0_pipe_clk",
.name = "pcie_0_pipe_clk",
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
.reg = 0x8d054,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "pcie_1_pipe_clk",
.name = "pcie_1_pipe_clk",
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
.reg = 0x77058,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_10,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
.parent_data = gcc_parent_data_10,
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
.reg = 0x770c8,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_11,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
.parent_data = gcc_parent_data_11,
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
.reg = 0x77048,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_12,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
.parent_data = gcc_parent_data_12,
.num_parents = ARRAY_SIZE(gcc_parent_data_12),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
.reg = 0xf060,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_13,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk_src",
.parent_data = gcc_parent_data_13,
.num_parents = ARRAY_SIZE(gcc_parent_data_13),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
.reg = 0x9e060,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_14,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_pipe_clk_src",
.parent_data = gcc_parent_data_14,
.num_parents = ARRAY_SIZE(gcc_parent_data_14),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x64004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x65004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x66004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
.cmd_rcgr = 0x6b058,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
.cmd_rcgr = 0x6b03c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
.cmd_rcgr = 0x8d058,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
.cmd_rcgr = 0x8d03c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x33010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_qspi_core_clk_src = {
.cmd_rcgr = 0x4b00c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qspi_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x17010,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.cmd_rcgr = 0x17140,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(52174000, P_GCC_GPLL0_OUT_MAIN, 1, 2, 23),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.cmd_rcgr = 0x17270,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.cmd_rcgr = 0x173a0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.cmd_rcgr = 0x174d0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.cmd_rcgr = 0x17600,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
.name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
.cmd_rcgr = 0x17730,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
.name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
.cmd_rcgr = 0x17860,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.cmd_rcgr = 0x18010,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.cmd_rcgr = 0x18140,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.cmd_rcgr = 0x18270,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.cmd_rcgr = 0x183a0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.cmd_rcgr = 0x184d0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.cmd_rcgr = 0x18600,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
.name = "gcc_qupv3_wrap1_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
.cmd_rcgr = 0x18730,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
.name = "gcc_qupv3_wrap1_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
.cmd_rcgr = 0x18860,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
F(144000, P_BI_TCXO, 16, 3, 25),
F(400000, P_BI_TCXO, 12, 1, 4),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3),
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
F(192000000, P_GCC_GPLL10_OUT_MAIN, 2, 0, 0),
F(384000000, P_GCC_GPLL10_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.cmd_rcgr = 0x7500c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_8,
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x7502c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.cmd_rcgr = 0x1400c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_9,
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_9,
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
.flags = CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
.cmd_rcgr = 0x1600c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.cmd_rcgr = 0x77024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.cmd_rcgr = 0x7706c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
.cmd_rcgr = 0x770a0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.cmd_rcgr = 0x77084,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0),
F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.cmd_rcgr = 0xf020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.cmd_rcgr = 0xf038,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk_src[] = {
F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),
F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
.cmd_rcgr = 0x9e020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_usb30_sec_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_master_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
.cmd_rcgr = 0x9e038,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_mock_utmi_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.cmd_rcgr = 0xf064,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
.cmd_rcgr = 0x9e064,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_aux_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = {
F(4800000, P_BI_TCXO, 4, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sec_ctrl_clk_src = {
.cmd_rcgr = 0x3d02c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_sec_ctrl_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sec_ctrl_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
.reg = 0xf050,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
.reg = 0x9e050,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gcc_pcie_clkref_en = {
.halt_reg = 0x8c004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_edp_clkref_en = {
.halt_reg = 0x8c008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_edp_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = {
.halt_reg = 0x6b080,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x6b080,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_noc_pcie_0_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = {
.halt_reg = 0x8d084,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x8d084,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_noc_pcie_1_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
.halt_reg = 0x90010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x90010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_noc_pcie_tbu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_noc_pcie_center_sf_axi_clk = {
.halt_reg = 0x8d088,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8d088,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_noc_pcie_center_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
.halt_reg = 0x770cc,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x770cc,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x770cc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
.halt_reg = 0xf080,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xf080,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xf080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
.halt_reg = 0x9e080,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9e080,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x9e080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_sec_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_hf_axi_clk = {
.halt_reg = 0x26010,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x26010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x26010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_sf_axi_clk = {
.halt_reg = 0x2601c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x2601c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2601c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.halt_reg = 0xf07c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xf07c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xf07c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
.halt_reg = 0x9e07c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x9e07c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x9e07c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_sec_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ddrss_gpu_axi_clk = {
.halt_reg = 0x71154,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x71154,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ddrss_gpu_axi_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_ddrss_pcie_sf_clk = {
.halt_reg = 0x8d080,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x8d080,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_ddrss_pcie_sf_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_gpll0_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_gpll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_hf_axi_clk = {
.halt_reg = 0x2700c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x2700c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2700c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_sf_axi_clk = {
.halt_reg = 0x27014,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x27014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x27014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x64000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x64000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x65000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x65000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x66000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x66000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_gpll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_gpll0_out_even.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_iref_en = {
.halt_reg = 0x8c014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_iref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
.halt_reg = 0x7100c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7100c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7100c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_memnoc_gfx_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
.halt_reg = 0x71018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x71018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_snoc_dvm_gfx_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_pcie0_phy_rchng_clk = {
.halt_reg = 0x6b038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie1_phy_rchng_clk = {
.halt_reg = 0x8d038,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_aux_clk = {
.halt_reg = 0x6b028,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.halt_reg = 0x6b024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.halt_reg = 0x6b01c,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_pipe_clk = {
.halt_reg = 0x6b030,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_0_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.halt_reg = 0x6b014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
.halt_reg = 0x6b010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_aux_clk = {
.halt_reg = 0x8d028,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(29),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_1_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
.halt_reg = 0x8d024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8d024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
.halt_reg = 0x8d01c,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_pipe_clk = {
.halt_reg = 0x8d030,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(30),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pcie_1_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_axi_clk = {
.halt_reg = 0x8d014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
.halt_reg = 0x8d010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_throttle_core_clk = {
.halt_reg = 0x90018,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x90018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_throttle_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x3300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x33004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x33004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x33004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x33008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x33008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
.halt_reg = 0x26008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x26008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x26008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_nrt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
.halt_reg = 0x2600c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2600c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_camera_rt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_disp_ahb_clk = {
.halt_reg = 0x27008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x27008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_disp_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
.halt_reg = 0x28008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x28008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x28008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qmip_video_vcodec_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
.halt_reg = 0x4b004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x4b004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4b004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_cnoc_periph_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qspi_core_clk = {
.halt_reg = 0x4b008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qspi_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
.halt_reg = 0x23008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_clk = {
.halt_reg = 0x23000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.halt_reg = 0x1700c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.halt_reg = 0x1713c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.halt_reg = 0x1726c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.halt_reg = 0x1739c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.halt_reg = 0x174cc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.halt_reg = 0x175fc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
.halt_reg = 0x1772c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s6_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
.halt_reg = 0x1785c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s7_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
.halt_reg = 0x23140,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_clk = {
.halt_reg = 0x23138,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.halt_reg = 0x1800c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.halt_reg = 0x1813c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.halt_reg = 0x1826c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.halt_reg = 0x1839c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.halt_reg = 0x184cc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.halt_reg = 0x185fc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
.halt_reg = 0x1872c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s6_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
.halt_reg = 0x1885c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s7_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
.halt_reg = 0x17008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
.halt_reg = 0x18004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x18004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
.halt_reg = 0x18008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x18008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x75004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x75004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x75008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x75008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0x75024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x75024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc1_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x14008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x14004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_ahb_clk = {
.halt_reg = 0x16008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_apps_clk = {
.halt_reg = 0x16004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_throttle_pcie_ahb_clk = {
.halt_reg = 0x9001c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9001c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_throttle_pcie_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_titan_nrt_throttle_core_clk = {
.halt_reg = 0x26024,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x26024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x26024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_titan_nrt_throttle_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_titan_rt_throttle_core_clk = {
.halt_reg = 0x26018,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x26018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x26018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_titan_rt_throttle_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_1_clkref_en = {
.halt_reg = 0x8c000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_1_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x77018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_clk = {
.halt_reg = 0x77010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.halt_reg = 0x77064,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77064,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.halt_reg = 0x7709c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7709c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7709c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.halt_reg = 0x77020,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x77020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
.halt_reg = 0x770b8,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x770b8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
.halt_reg = 0x7701c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7701c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.halt_reg = 0x7705c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7705c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7705c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_master_clk = {
.halt_reg = 0xf010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0xf01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_sleep_clk = {
.halt_reg = 0xf018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_master_clk = {
.halt_reg = 0x9e010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9e010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_master_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_sec_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
.halt_reg = 0x9e01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9e01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sec_sleep_clk = {
.halt_reg = 0x9e018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9e018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
.halt_reg = 0xf054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.halt_reg = 0xf058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_reg = 0xf05c,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0xf05c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xf05c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_lpass_clk = {
.halt_reg = 0x47020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x47020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_lpass_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_mss_cfg_ahb_clk = {
.halt_reg = 0x8a000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8a000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_offline_axi_clk = {
.halt_reg = 0x8a004,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x8a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_offline_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_snoc_axi_clk = {
.halt_reg = 0x8a154,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x8a154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_snoc_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
.halt_reg = 0x8a158,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8a158,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_q6_memnoc_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap_mux gcc_mss_q6ss_boot_clk_src = {
.reg = 0x8a2a4,
.shift = 0,
.width = 1,
.parent_map = gcc_parent_map_15,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_q6ss_boot_clk_src",
.parent_data = gcc_parent_data_15,
.num_parents = ARRAY_SIZE(gcc_parent_data_15),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
.halt_reg = 0x9e054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9e054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
.halt_reg = 0x9e058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9e058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
.halt_reg = 0x9e05c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x9e05c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x9e05c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_pipe_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi0_clk = {
.halt_reg = 0x2800c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x2800c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2800c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_mvp_throttle_core_clk = {
.halt_reg = 0x28010,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x28010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x28010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_mvp_throttle_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wpss_ahb_clk = {
.halt_reg = 0x9d154,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9d154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_wpss_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wpss_ahb_bdg_mst_clk = {
.halt_reg = 0x9d158,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9d158,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_wpss_ahb_bdg_mst_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_wpss_rscp_clk = {
.halt_reg = 0x9d16c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9d16c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_wpss_rscp_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gcc_pcie_0_gdsc = {
.gdscr = 0x6b004,
.pd = {
.name = "gcc_pcie_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc gcc_pcie_1_gdsc = {
.gdscr = 0x8d004,
.pd = {
.name = "gcc_pcie_1_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
.flags = VOTABLE,
};
static struct gdsc gcc_ufs_phy_gdsc = {
.gdscr = 0x77004,
.pd = {
.name = "gcc_ufs_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc gcc_usb30_prim_gdsc = {
.gdscr = 0xf004,
.pd = {
.name = "gcc_usb30_prim_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
.flags = VOTABLE,
};
static struct gdsc gcc_usb30_sec_gdsc = {
.gdscr = 0x9e004,
.pd = {
.name = "gcc_usb30_sec_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
.gdscr = 0x7d050,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
.gdscr = 0x7d058,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = {
.gdscr = 0x7d054,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
.gdscr = 0x7d05c,
.pd = {
.name = "hlos1_vote_turing_mmu_tbu0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
.gdscr = 0x7d060,
.pd = {
.name = "hlos1_vote_turing_mmu_tbu1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct clk_regmap *gcc_sc7280_clocks[] = {
[GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr,
[GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
[GCC_DDRSS_PCIE_SF_CLK] = &gcc_ddrss_pcie_sf_clk.clkr,
[GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
[GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPLL0] = &gcc_gpll0.clkr,
[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
[GCC_GPLL0_OUT_ODD] = &gcc_gpll0_out_odd.clkr,
[GCC_GPLL1] = &gcc_gpll1.clkr,
[GCC_GPLL10] = &gcc_gpll10.clkr,
[GCC_GPLL4] = &gcc_gpll4.clkr,
[GCC_GPLL9] = &gcc_gpll9.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr,
[GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr,
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
[GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
[GCC_PCIE_THROTTLE_CORE_CLK] = &gcc_pcie_throttle_core_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
[GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
[GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
[GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
[GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
[GCC_THROTTLE_PCIE_AHB_CLK] = &gcc_throttle_pcie_ahb_clk.clkr,
[GCC_TITAN_NRT_THROTTLE_CORE_CLK] =
&gcc_titan_nrt_throttle_core_clk.clkr,
[GCC_TITAN_RT_THROTTLE_CORE_CLK] = &gcc_titan_rt_throttle_core_clk.clkr,
[GCC_UFS_1_CLKREF_EN] = &gcc_ufs_1_clkref_en.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] =
&gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] =
&gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] =
&gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
&gcc_ufs_phy_unipro_core_clk_src.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
&gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] =
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
&gcc_usb30_sec_mock_utmi_clk_src.clkr,
[GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] =
&gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
[GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
[GCC_VIDEO_MVP_THROTTLE_CORE_CLK] =
&gcc_video_mvp_throttle_core_clk.clkr,
[GCC_CFG_NOC_LPASS_CLK] = &gcc_cfg_noc_lpass_clk.clkr,
[GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC] = &gcc_mss_gpll0_main_div_clk_src.clkr,
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
[GCC_MSS_OFFLINE_AXI_CLK] = &gcc_mss_offline_axi_clk.clkr,
[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
[GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
[GCC_MSS_Q6SS_BOOT_CLK_SRC] = &gcc_mss_q6ss_boot_clk_src.clkr,
[GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
[GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK] =
&gcc_aggre_noc_pcie_center_sf_axi_clk.clkr,
[GCC_PCIE_CLKREF_EN] = &gcc_pcie_clkref_en.clkr,
[GCC_EDP_CLKREF_EN] = &gcc_edp_clkref_en.clkr,
[GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr,
[GCC_WPSS_AHB_CLK] = &gcc_wpss_ahb_clk.clkr,
[GCC_WPSS_AHB_BDG_MST_CLK] = &gcc_wpss_ahb_bdg_mst_clk.clkr,
[GCC_WPSS_RSCP_CLK] = &gcc_wpss_rscp_clk.clkr,
};
static struct gdsc *gcc_sc7280_gdscs[] = {
[GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc,
[GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc,
[GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,
[GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
[GCC_USB30_SEC_GDSC] = &gcc_usb30_sec_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc,
[HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
[HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
};
static const struct qcom_reset_map gcc_sc7280_resets[] = {
[GCC_PCIE_0_BCR] = { 0x6b000 },
[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
[GCC_PCIE_1_BCR] = { 0x8d000 },
[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
[GCC_SDCC1_BCR] = { 0x75000 },
[GCC_SDCC2_BCR] = { 0x14000 },
[GCC_SDCC4_BCR] = { 0x16000 },
[GCC_UFS_PHY_BCR] = { 0x77000 },
[GCC_USB30_PRIM_BCR] = { 0xf000 },
[GCC_USB30_SEC_BCR] = { 0x9e000 },
[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
};
static const struct regmap_config gcc_sc7280_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9f128,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_sc7280_desc = {
.config = &gcc_sc7280_regmap_config,
.clks = gcc_sc7280_clocks,
.num_clks = ARRAY_SIZE(gcc_sc7280_clocks),
.resets = gcc_sc7280_resets,
.num_resets = ARRAY_SIZE(gcc_sc7280_resets),
.gdscs = gcc_sc7280_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sc7280_gdscs),
};
static const struct of_device_id gcc_sc7280_match_table[] = {
{ .compatible = "qcom,gcc-sc7280" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_sc7280_match_table);
static int gcc_sc7280_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sc7280_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/*
* Keep the clocks always-ON
* GCC_CAMERA_AHB_CLK/XO_CLK, GCC_DISP_AHB_CLK/XO_CLK
* GCC_VIDEO_AHB_CLK/XO_CLK, GCC_GPU_CFG_AHB_CLK
*/
regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x2701C, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x28014, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13));
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
return qcom_cc_really_probe(pdev, &gcc_sc7280_desc, regmap);
}
static struct platform_driver gcc_sc7280_driver = {
.probe = gcc_sc7280_probe,
.driver = {
.name = "gcc-sc7280",
.of_match_table = gcc_sc7280_match_table,
},
};
static int __init gcc_sc7280_init(void)
{
return platform_driver_register(&gcc_sc7280_driver);
}
subsys_initcall(gcc_sc7280_init);
static void __exit gcc_sc7280_exit(void)
{
platform_driver_unregister(&gcc_sc7280_driver);
}
module_exit(gcc_sc7280_exit);
MODULE_DESCRIPTION("QTI GCC SC7280 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gcc-sc7280.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
#include <dt-bindings/reset/qcom,gcc-msm8960.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "clk-hfpll.h"
#include "reset.h"
static struct clk_pll pll3 = {
.l_reg = 0x3164,
.m_reg = 0x3168,
.n_reg = 0x316c,
.config_reg = 0x3174,
.mode_reg = 0x3160,
.status_reg = 0x3178,
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll3",
.parent_data = &(const struct clk_parent_data){
.fw_name = "pxo", .name = "pxo_board",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap pll4_vote = {
.enable_reg = 0x34c0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pll4_vote",
.parent_data = &(const struct clk_parent_data){
.fw_name = "pll4", .name = "pll4",
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll pll8 = {
.l_reg = 0x3144,
.m_reg = 0x3148,
.n_reg = 0x314c,
.config_reg = 0x3154,
.mode_reg = 0x3140,
.status_reg = 0x3158,
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll8",
.parent_data = &(const struct clk_parent_data){
.fw_name = "pxo", .name = "pxo_board",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap pll8_vote = {
.enable_reg = 0x34c0,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "pll8_vote",
.parent_hws = (const struct clk_hw*[]){
&pll8.clkr.hw
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct hfpll_data hfpll0_data = {
.mode_reg = 0x3200,
.l_reg = 0x3208,
.m_reg = 0x320c,
.n_reg = 0x3210,
.config_reg = 0x3204,
.status_reg = 0x321c,
.config_val = 0x7845c665,
.droop_reg = 0x3214,
.droop_val = 0x0108c000,
.min_rate = 600000000UL,
.max_rate = 1800000000UL,
};
static struct clk_hfpll hfpll0 = {
.d = &hfpll0_data,
.clkr.hw.init = &(struct clk_init_data){
.parent_data = &(const struct clk_parent_data){
.fw_name = "pxo", .name = "pxo_board",
},
.num_parents = 1,
.name = "hfpll0",
.ops = &clk_ops_hfpll,
.flags = CLK_IGNORE_UNUSED,
},
.lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
};
static struct hfpll_data hfpll1_8064_data = {
.mode_reg = 0x3240,
.l_reg = 0x3248,
.m_reg = 0x324c,
.n_reg = 0x3250,
.config_reg = 0x3244,
.status_reg = 0x325c,
.config_val = 0x7845c665,
.droop_reg = 0x3254,
.droop_val = 0x0108c000,
.min_rate = 600000000UL,
.max_rate = 1800000000UL,
};
static struct hfpll_data hfpll1_data = {
.mode_reg = 0x3300,
.l_reg = 0x3308,
.m_reg = 0x330c,
.n_reg = 0x3310,
.config_reg = 0x3304,
.status_reg = 0x331c,
.config_val = 0x7845c665,
.droop_reg = 0x3314,
.droop_val = 0x0108c000,
.min_rate = 600000000UL,
.max_rate = 1800000000UL,
};
static struct clk_hfpll hfpll1 = {
.d = &hfpll1_data,
.clkr.hw.init = &(struct clk_init_data){
.parent_data = &(const struct clk_parent_data){
.fw_name = "pxo", .name = "pxo_board",
},
.num_parents = 1,
.name = "hfpll1",
.ops = &clk_ops_hfpll,
.flags = CLK_IGNORE_UNUSED,
},
.lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
};
static struct hfpll_data hfpll2_data = {
.mode_reg = 0x3280,
.l_reg = 0x3288,
.m_reg = 0x328c,
.n_reg = 0x3290,
.config_reg = 0x3284,
.status_reg = 0x329c,
.config_val = 0x7845c665,
.droop_reg = 0x3294,
.droop_val = 0x0108c000,
.min_rate = 600000000UL,
.max_rate = 1800000000UL,
};
static struct clk_hfpll hfpll2 = {
.d = &hfpll2_data,
.clkr.hw.init = &(struct clk_init_data){
.parent_data = &(const struct clk_parent_data){
.fw_name = "pxo", .name = "pxo_board",
},
.num_parents = 1,
.name = "hfpll2",
.ops = &clk_ops_hfpll,
.flags = CLK_IGNORE_UNUSED,
},
.lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock),
};
static struct hfpll_data hfpll3_data = {
.mode_reg = 0x32c0,
.l_reg = 0x32c8,
.m_reg = 0x32cc,
.n_reg = 0x32d0,
.config_reg = 0x32c4,
.status_reg = 0x32dc,
.config_val = 0x7845c665,
.droop_reg = 0x32d4,
.droop_val = 0x0108c000,
.min_rate = 600000000UL,
.max_rate = 1800000000UL,
};
static struct clk_hfpll hfpll3 = {
.d = &hfpll3_data,
.clkr.hw.init = &(struct clk_init_data){
.parent_data = &(const struct clk_parent_data){
.fw_name = "pxo", .name = "pxo_board",
},
.num_parents = 1,
.name = "hfpll3",
.ops = &clk_ops_hfpll,
.flags = CLK_IGNORE_UNUSED,
},
.lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock),
};
static struct hfpll_data hfpll_l2_8064_data = {
.mode_reg = 0x3300,
.l_reg = 0x3308,
.m_reg = 0x330c,
.n_reg = 0x3310,
.config_reg = 0x3304,
.status_reg = 0x331c,
.config_val = 0x7845c665,
.droop_reg = 0x3314,
.droop_val = 0x0108c000,
.min_rate = 600000000UL,
.max_rate = 1800000000UL,
};
static struct hfpll_data hfpll_l2_data = {
.mode_reg = 0x3400,
.l_reg = 0x3408,
.m_reg = 0x340c,
.n_reg = 0x3410,
.config_reg = 0x3404,
.status_reg = 0x341c,
.config_val = 0x7845c665,
.droop_reg = 0x3414,
.droop_val = 0x0108c000,
.min_rate = 600000000UL,
.max_rate = 1800000000UL,
};
static struct clk_hfpll hfpll_l2 = {
.d = &hfpll_l2_data,
.clkr.hw.init = &(struct clk_init_data){
.parent_data = &(const struct clk_parent_data){
.fw_name = "pxo", .name = "pxo_board",
},
.num_parents = 1,
.name = "hfpll_l2",
.ops = &clk_ops_hfpll,
.flags = CLK_IGNORE_UNUSED,
},
.lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
};
static struct clk_pll pll14 = {
.l_reg = 0x31c4,
.m_reg = 0x31c8,
.n_reg = 0x31cc,
.config_reg = 0x31d4,
.mode_reg = 0x31c0,
.status_reg = 0x31d8,
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll14",
.parent_data = &(const struct clk_parent_data){
.fw_name = "pxo", .name = "pxo_board",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap pll14_vote = {
.enable_reg = 0x34c0,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "pll14_vote",
.parent_hws = (const struct clk_hw*[]){
&pll14.clkr.hw
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
enum {
P_PXO,
P_PLL8,
P_PLL3,
P_CXO,
};
static const struct parent_map gcc_pxo_pll8_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 3 }
};
static const struct clk_parent_data gcc_pxo_pll8[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .hw = &pll8_vote.hw },
};
static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 3 },
{ P_CXO, 5 }
};
static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .hw = &pll8_vote.hw },
{ .fw_name = "cxo", .name = "cxo_board" },
};
static const struct parent_map gcc_pxo_pll8_pll3_map[] = {
{ P_PXO, 0 },
{ P_PLL8, 3 },
{ P_PLL3, 6 }
};
static const struct clk_parent_data gcc_pxo_pll8_pll3[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .hw = &pll8_vote.hw },
{ .hw = &pll3.clkr.hw },
};
static struct freq_tbl clk_tbl_gsbi_uart[] = {
{ 1843200, P_PLL8, 2, 6, 625 },
{ 3686400, P_PLL8, 2, 12, 625 },
{ 7372800, P_PLL8, 2, 24, 625 },
{ 14745600, P_PLL8, 2, 48, 625 },
{ 16000000, P_PLL8, 4, 1, 6 },
{ 24000000, P_PLL8, 4, 1, 4 },
{ 32000000, P_PLL8, 4, 1, 3 },
{ 40000000, P_PLL8, 1, 5, 48 },
{ 46400000, P_PLL8, 1, 29, 240 },
{ 48000000, P_PLL8, 4, 1, 2 },
{ 51200000, P_PLL8, 1, 2, 15 },
{ 56000000, P_PLL8, 1, 7, 48 },
{ 58982400, P_PLL8, 1, 96, 625 },
{ 64000000, P_PLL8, 2, 1, 3 },
{ }
};
static struct clk_rcg gsbi1_uart_src = {
.ns_reg = 0x29d4,
.md_reg = 0x29d0,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x29d4,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi1_uart_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 10,
.clkr = {
.enable_reg = 0x29d4,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi1_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi2_uart_src = {
.ns_reg = 0x29f4,
.md_reg = 0x29f0,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x29f4,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi2_uart_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 6,
.clkr = {
.enable_reg = 0x29f4,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi2_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi3_uart_src = {
.ns_reg = 0x2a14,
.md_reg = 0x2a10,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2a14,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi3_uart_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 2,
.clkr = {
.enable_reg = 0x2a14,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi3_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi4_uart_src = {
.ns_reg = 0x2a34,
.md_reg = 0x2a30,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2a34,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi4_uart_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 26,
.clkr = {
.enable_reg = 0x2a34,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi4_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi5_uart_src = {
.ns_reg = 0x2a54,
.md_reg = 0x2a50,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2a54,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi5_uart_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 22,
.clkr = {
.enable_reg = 0x2a54,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi5_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi6_uart_src = {
.ns_reg = 0x2a74,
.md_reg = 0x2a70,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2a74,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi6_uart_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 18,
.clkr = {
.enable_reg = 0x2a74,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi6_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi7_uart_src = {
.ns_reg = 0x2a94,
.md_reg = 0x2a90,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2a94,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi7_uart_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 14,
.clkr = {
.enable_reg = 0x2a94,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi7_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi8_uart_src = {
.ns_reg = 0x2ab4,
.md_reg = 0x2ab0,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2ab4,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi8_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi8_uart_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 10,
.clkr = {
.enable_reg = 0x2ab4,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi8_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi8_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi9_uart_src = {
.ns_reg = 0x2ad4,
.md_reg = 0x2ad0,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2ad4,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi9_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi9_uart_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 6,
.clkr = {
.enable_reg = 0x2ad4,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi9_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi9_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi10_uart_src = {
.ns_reg = 0x2af4,
.md_reg = 0x2af0,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2af4,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi10_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi10_uart_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 2,
.clkr = {
.enable_reg = 0x2af4,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi10_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi10_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi11_uart_src = {
.ns_reg = 0x2b14,
.md_reg = 0x2b10,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2b14,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi11_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi11_uart_clk = {
.halt_reg = 0x2fd4,
.halt_bit = 17,
.clkr = {
.enable_reg = 0x2b14,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi11_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi11_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi12_uart_src = {
.ns_reg = 0x2b34,
.md_reg = 0x2b30,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_uart,
.clkr = {
.enable_reg = 0x2b34,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi12_uart_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi12_uart_clk = {
.halt_reg = 0x2fd4,
.halt_bit = 13,
.clkr = {
.enable_reg = 0x2b34,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi12_uart_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi12_uart_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct freq_tbl clk_tbl_gsbi_qup[] = {
{ 1100000, P_PXO, 1, 2, 49 },
{ 5400000, P_PXO, 1, 1, 5 },
{ 10800000, P_PXO, 1, 2, 5 },
{ 15060000, P_PLL8, 1, 2, 51 },
{ 24000000, P_PLL8, 4, 1, 4 },
{ 25600000, P_PLL8, 1, 1, 15 },
{ 27000000, P_PXO, 1, 0, 0 },
{ 48000000, P_PLL8, 4, 1, 2 },
{ 51200000, P_PLL8, 1, 2, 15 },
{ }
};
static struct clk_rcg gsbi1_qup_src = {
.ns_reg = 0x29cc,
.md_reg = 0x29c8,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x29cc,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi1_qup_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 9,
.clkr = {
.enable_reg = 0x29cc,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi1_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi2_qup_src = {
.ns_reg = 0x29ec,
.md_reg = 0x29e8,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x29ec,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi2_qup_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 4,
.clkr = {
.enable_reg = 0x29ec,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi2_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi3_qup_src = {
.ns_reg = 0x2a0c,
.md_reg = 0x2a08,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2a0c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi3_qup_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 0,
.clkr = {
.enable_reg = 0x2a0c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi3_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi4_qup_src = {
.ns_reg = 0x2a2c,
.md_reg = 0x2a28,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2a2c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi4_qup_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 24,
.clkr = {
.enable_reg = 0x2a2c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi4_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi5_qup_src = {
.ns_reg = 0x2a4c,
.md_reg = 0x2a48,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2a4c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi5_qup_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 20,
.clkr = {
.enable_reg = 0x2a4c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi5_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi6_qup_src = {
.ns_reg = 0x2a6c,
.md_reg = 0x2a68,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2a6c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi6_qup_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 16,
.clkr = {
.enable_reg = 0x2a6c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi6_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi7_qup_src = {
.ns_reg = 0x2a8c,
.md_reg = 0x2a88,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2a8c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi7_qup_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 12,
.clkr = {
.enable_reg = 0x2a8c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi7_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi8_qup_src = {
.ns_reg = 0x2aac,
.md_reg = 0x2aa8,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2aac,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi8_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi8_qup_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 8,
.clkr = {
.enable_reg = 0x2aac,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi8_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi8_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi9_qup_src = {
.ns_reg = 0x2acc,
.md_reg = 0x2ac8,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2acc,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi9_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi9_qup_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 4,
.clkr = {
.enable_reg = 0x2acc,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi9_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi9_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi10_qup_src = {
.ns_reg = 0x2aec,
.md_reg = 0x2ae8,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2aec,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi10_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi10_qup_clk = {
.halt_reg = 0x2fd0,
.halt_bit = 0,
.clkr = {
.enable_reg = 0x2aec,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi10_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi10_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi11_qup_src = {
.ns_reg = 0x2b0c,
.md_reg = 0x2b08,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2b0c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi11_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi11_qup_clk = {
.halt_reg = 0x2fd4,
.halt_bit = 15,
.clkr = {
.enable_reg = 0x2b0c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi11_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi11_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gsbi12_qup_src = {
.ns_reg = 0x2b2c,
.md_reg = 0x2b28,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_gsbi_qup,
.clkr = {
.enable_reg = 0x2b2c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi12_qup_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
},
};
static struct clk_branch gsbi12_qup_clk = {
.halt_reg = 0x2fd4,
.halt_bit = 11,
.clkr = {
.enable_reg = 0x2b2c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi12_qup_clk",
.parent_hws = (const struct clk_hw*[]){
&gsbi12_qup_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl clk_tbl_gp[] = {
{ 9600000, P_CXO, 2, 0, 0 },
{ 13500000, P_PXO, 2, 0, 0 },
{ 19200000, P_CXO, 1, 0, 0 },
{ 27000000, P_PXO, 1, 0, 0 },
{ 64000000, P_PLL8, 2, 1, 3 },
{ 76800000, P_PLL8, 1, 1, 5 },
{ 96000000, P_PLL8, 4, 0, 0 },
{ 128000000, P_PLL8, 3, 0, 0 },
{ 192000000, P_PLL8, 2, 0, 0 },
{ }
};
static struct clk_rcg gp0_src = {
.ns_reg = 0x2d24,
.md_reg = 0x2d00,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_cxo_map,
},
.freq_tbl = clk_tbl_gp,
.clkr = {
.enable_reg = 0x2d24,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp0_src",
.parent_data = gcc_pxo_pll8_cxo,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
}
};
static struct clk_branch gp0_clk = {
.halt_reg = 0x2fd8,
.halt_bit = 7,
.clkr = {
.enable_reg = 0x2d24,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp0_clk",
.parent_hws = (const struct clk_hw*[]){
&gp0_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gp1_src = {
.ns_reg = 0x2d44,
.md_reg = 0x2d40,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_cxo_map,
},
.freq_tbl = clk_tbl_gp,
.clkr = {
.enable_reg = 0x2d44,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp1_src",
.parent_data = gcc_pxo_pll8_cxo,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch gp1_clk = {
.halt_reg = 0x2fd8,
.halt_bit = 6,
.clkr = {
.enable_reg = 0x2d44,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&gp1_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg gp2_src = {
.ns_reg = 0x2d64,
.md_reg = 0x2d60,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_cxo_map,
},
.freq_tbl = clk_tbl_gp,
.clkr = {
.enable_reg = 0x2d64,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp2_src",
.parent_data = gcc_pxo_pll8_cxo,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch gp2_clk = {
.halt_reg = 0x2fd8,
.halt_bit = 5,
.clkr = {
.enable_reg = 0x2d64,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp2_clk",
.parent_hws = (const struct clk_hw*[]){
&gp2_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch pmem_clk = {
.hwcg_reg = 0x25a0,
.hwcg_bit = 6,
.halt_reg = 0x2fc8,
.halt_bit = 20,
.clkr = {
.enable_reg = 0x25a0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pmem_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_rcg prng_src = {
.ns_reg = 0x2e80,
.p = {
.pre_div_shift = 3,
.pre_div_width = 4,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "prng_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
},
};
static struct clk_branch prng_clk = {
.halt_reg = 0x2fd8,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 10,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "prng_clk",
.parent_hws = (const struct clk_hw*[]){
&prng_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
},
},
};
static const struct freq_tbl clk_tbl_sdc[] = {
{ 144000, P_PXO, 3, 2, 125 },
{ 400000, P_PLL8, 4, 1, 240 },
{ 16000000, P_PLL8, 4, 1, 6 },
{ 17070000, P_PLL8, 1, 2, 45 },
{ 20210000, P_PLL8, 1, 1, 19 },
{ 24000000, P_PLL8, 4, 1, 4 },
{ 48000000, P_PLL8, 4, 1, 2 },
{ 64000000, P_PLL8, 3, 1, 2 },
{ 96000000, P_PLL8, 4, 0, 0 },
{ 192000000, P_PLL8, 2, 0, 0 },
{ }
};
static struct clk_rcg sdc1_src = {
.ns_reg = 0x282c,
.md_reg = 0x2828,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_sdc,
.clkr = {
.enable_reg = 0x282c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc1_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
};
static struct clk_branch sdc1_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 6,
.clkr = {
.enable_reg = 0x282c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc1_clk",
.parent_hws = (const struct clk_hw*[]){
&sdc1_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg sdc2_src = {
.ns_reg = 0x284c,
.md_reg = 0x2848,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_sdc,
.clkr = {
.enable_reg = 0x284c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc2_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
};
static struct clk_branch sdc2_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 5,
.clkr = {
.enable_reg = 0x284c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc2_clk",
.parent_hws = (const struct clk_hw*[]){
&sdc2_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg sdc3_src = {
.ns_reg = 0x286c,
.md_reg = 0x2868,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_sdc,
.clkr = {
.enable_reg = 0x286c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc3_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
};
static struct clk_branch sdc3_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 4,
.clkr = {
.enable_reg = 0x286c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc3_clk",
.parent_hws = (const struct clk_hw*[]){
&sdc3_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg sdc4_src = {
.ns_reg = 0x288c,
.md_reg = 0x2888,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_sdc,
.clkr = {
.enable_reg = 0x288c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc4_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
};
static struct clk_branch sdc4_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 3,
.clkr = {
.enable_reg = 0x288c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc4_clk",
.parent_hws = (const struct clk_hw*[]){
&sdc4_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg sdc5_src = {
.ns_reg = 0x28ac,
.md_reg = 0x28a8,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_sdc,
.clkr = {
.enable_reg = 0x28ac,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc5_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
};
static struct clk_branch sdc5_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 2,
.clkr = {
.enable_reg = 0x28ac,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc5_clk",
.parent_hws = (const struct clk_hw*[]){
&sdc5_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl clk_tbl_tsif_ref[] = {
{ 105000, P_PXO, 1, 1, 256 },
{ }
};
static struct clk_rcg tsif_ref_src = {
.ns_reg = 0x2710,
.md_reg = 0x270c,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_tsif_ref,
.clkr = {
.enable_reg = 0x2710,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "tsif_ref_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch tsif_ref_clk = {
.halt_reg = 0x2fd4,
.halt_bit = 5,
.clkr = {
.enable_reg = 0x2710,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "tsif_ref_clk",
.parent_hws = (const struct clk_hw*[]){
&tsif_ref_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl clk_tbl_usb[] = {
{ 60000000, P_PLL8, 1, 5, 32 },
{ }
};
static struct clk_rcg usb_hs1_xcvr_src = {
.ns_reg = 0x290c,
.md_reg = 0x2908,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_usb,
.clkr = {
.enable_reg = 0x290c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch usb_hs1_xcvr_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 0,
.clkr = {
.enable_reg = 0x290c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_hs1_xcvr_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg usb_hs3_xcvr_src = {
.ns_reg = 0x370c,
.md_reg = 0x3708,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_usb,
.clkr = {
.enable_reg = 0x370c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_hs3_xcvr_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch usb_hs3_xcvr_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 30,
.clkr = {
.enable_reg = 0x370c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_hs3_xcvr_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_hs3_xcvr_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg usb_hs4_xcvr_src = {
.ns_reg = 0x372c,
.md_reg = 0x3728,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_usb,
.clkr = {
.enable_reg = 0x372c,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_hs4_xcvr_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch usb_hs4_xcvr_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 2,
.clkr = {
.enable_reg = 0x372c,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_hs4_xcvr_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_hs4_xcvr_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg usb_hsic_xcvr_fs_src = {
.ns_reg = 0x2928,
.md_reg = 0x2924,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_usb,
.clkr = {
.enable_reg = 0x2928,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_hsic_xcvr_fs_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch usb_hsic_xcvr_fs_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 2,
.clkr = {
.enable_reg = 0x2928,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_hsic_xcvr_fs_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_hsic_xcvr_fs_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch usb_hsic_system_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 24,
.clkr = {
.enable_reg = 0x292c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]){
&usb_hsic_xcvr_fs_src.clkr.hw,
},
.num_parents = 1,
.name = "usb_hsic_system_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch usb_hsic_hsic_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 19,
.clkr = {
.enable_reg = 0x2b44,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]){
&pll14_vote.hw
},
.num_parents = 1,
.name = "usb_hsic_hsic_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch usb_hsic_hsio_cal_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 23,
.clkr = {
.enable_reg = 0x2b48,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "usb_hsic_hsio_cal_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_rcg usb_fs1_xcvr_fs_src = {
.ns_reg = 0x2968,
.md_reg = 0x2964,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_usb,
.clkr = {
.enable_reg = 0x2968,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_xcvr_fs_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch usb_fs1_xcvr_fs_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 15,
.clkr = {
.enable_reg = 0x2968,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_xcvr_fs_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_fs1_xcvr_fs_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch usb_fs1_system_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 16,
.clkr = {
.enable_reg = 0x296c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.parent_hws = (const struct clk_hw*[]){
&usb_fs1_xcvr_fs_src.clkr.hw,
},
.num_parents = 1,
.name = "usb_fs1_system_clk",
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_rcg usb_fs2_xcvr_fs_src = {
.ns_reg = 0x2988,
.md_reg = 0x2984,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_map,
},
.freq_tbl = clk_tbl_usb,
.clkr = {
.enable_reg = 0x2988,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_fs2_xcvr_fs_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
}
};
static struct clk_branch usb_fs2_xcvr_fs_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 12,
.clkr = {
.enable_reg = 0x2988,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_fs2_xcvr_fs_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_fs2_xcvr_fs_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch usb_fs2_system_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 13,
.clkr = {
.enable_reg = 0x298c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb_fs2_system_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_fs2_xcvr_fs_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch ce1_core_clk = {
.hwcg_reg = 0x2724,
.hwcg_bit = 6,
.halt_reg = 0x2fd4,
.halt_bit = 27,
.clkr = {
.enable_reg = 0x2724,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "ce1_core_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch ce1_h_clk = {
.halt_reg = 0x2fd4,
.halt_bit = 1,
.clkr = {
.enable_reg = 0x2720,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "ce1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch dma_bam_h_clk = {
.hwcg_reg = 0x25c0,
.hwcg_bit = 6,
.halt_reg = 0x2fc8,
.halt_bit = 12,
.clkr = {
.enable_reg = 0x25c0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "dma_bam_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi1_h_clk = {
.hwcg_reg = 0x29c0,
.hwcg_bit = 6,
.halt_reg = 0x2fcc,
.halt_bit = 11,
.clkr = {
.enable_reg = 0x29c0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi2_h_clk = {
.hwcg_reg = 0x29e0,
.hwcg_bit = 6,
.halt_reg = 0x2fcc,
.halt_bit = 7,
.clkr = {
.enable_reg = 0x29e0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi3_h_clk = {
.hwcg_reg = 0x2a00,
.hwcg_bit = 6,
.halt_reg = 0x2fcc,
.halt_bit = 3,
.clkr = {
.enable_reg = 0x2a00,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi3_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi4_h_clk = {
.hwcg_reg = 0x2a20,
.hwcg_bit = 6,
.halt_reg = 0x2fd0,
.halt_bit = 27,
.clkr = {
.enable_reg = 0x2a20,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi5_h_clk = {
.hwcg_reg = 0x2a40,
.hwcg_bit = 6,
.halt_reg = 0x2fd0,
.halt_bit = 23,
.clkr = {
.enable_reg = 0x2a40,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi6_h_clk = {
.hwcg_reg = 0x2a60,
.hwcg_bit = 6,
.halt_reg = 0x2fd0,
.halt_bit = 19,
.clkr = {
.enable_reg = 0x2a60,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi7_h_clk = {
.hwcg_reg = 0x2a80,
.hwcg_bit = 6,
.halt_reg = 0x2fd0,
.halt_bit = 15,
.clkr = {
.enable_reg = 0x2a80,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi8_h_clk = {
.hwcg_reg = 0x2aa0,
.hwcg_bit = 6,
.halt_reg = 0x2fd0,
.halt_bit = 11,
.clkr = {
.enable_reg = 0x2aa0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi8_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi9_h_clk = {
.hwcg_reg = 0x2ac0,
.hwcg_bit = 6,
.halt_reg = 0x2fd0,
.halt_bit = 7,
.clkr = {
.enable_reg = 0x2ac0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi9_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi10_h_clk = {
.hwcg_reg = 0x2ae0,
.hwcg_bit = 6,
.halt_reg = 0x2fd0,
.halt_bit = 3,
.clkr = {
.enable_reg = 0x2ae0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi10_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi11_h_clk = {
.hwcg_reg = 0x2b00,
.hwcg_bit = 6,
.halt_reg = 0x2fd4,
.halt_bit = 18,
.clkr = {
.enable_reg = 0x2b00,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi11_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch gsbi12_h_clk = {
.hwcg_reg = 0x2b20,
.hwcg_bit = 6,
.halt_reg = 0x2fd4,
.halt_bit = 14,
.clkr = {
.enable_reg = 0x2b20,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gsbi12_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch tsif_h_clk = {
.hwcg_reg = 0x2700,
.hwcg_bit = 6,
.halt_reg = 0x2fd4,
.halt_bit = 7,
.clkr = {
.enable_reg = 0x2700,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "tsif_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch usb_fs1_h_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 17,
.clkr = {
.enable_reg = 0x2960,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch usb_fs2_h_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 14,
.clkr = {
.enable_reg = 0x2980,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb_fs2_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch usb_hs1_h_clk = {
.hwcg_reg = 0x2900,
.hwcg_bit = 6,
.halt_reg = 0x2fc8,
.halt_bit = 1,
.clkr = {
.enable_reg = 0x2900,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch usb_hs3_h_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 31,
.clkr = {
.enable_reg = 0x3700,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb_hs3_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch usb_hs4_h_clk = {
.halt_reg = 0x2fc8,
.halt_bit = 7,
.clkr = {
.enable_reg = 0x3720,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb_hs4_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch usb_hsic_h_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 28,
.clkr = {
.enable_reg = 0x2920,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb_hsic_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch sdc1_h_clk = {
.hwcg_reg = 0x2820,
.hwcg_bit = 6,
.halt_reg = 0x2fc8,
.halt_bit = 11,
.clkr = {
.enable_reg = 0x2820,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sdc1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch sdc2_h_clk = {
.hwcg_reg = 0x2840,
.hwcg_bit = 6,
.halt_reg = 0x2fc8,
.halt_bit = 10,
.clkr = {
.enable_reg = 0x2840,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sdc2_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch sdc3_h_clk = {
.hwcg_reg = 0x2860,
.hwcg_bit = 6,
.halt_reg = 0x2fc8,
.halt_bit = 9,
.clkr = {
.enable_reg = 0x2860,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sdc3_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch sdc4_h_clk = {
.hwcg_reg = 0x2880,
.hwcg_bit = 6,
.halt_reg = 0x2fc8,
.halt_bit = 8,
.clkr = {
.enable_reg = 0x2880,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sdc4_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch sdc5_h_clk = {
.hwcg_reg = 0x28a0,
.hwcg_bit = 6,
.halt_reg = 0x2fc8,
.halt_bit = 7,
.clkr = {
.enable_reg = 0x28a0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sdc5_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch adm0_clk = {
.halt_reg = 0x2fdc,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 14,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "adm0_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch adm0_pbus_clk = {
.hwcg_reg = 0x2208,
.hwcg_bit = 6,
.halt_reg = 0x2fdc,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 13,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "adm0_pbus_clk",
.ops = &clk_branch_ops,
},
},
};
static struct freq_tbl clk_tbl_ce3[] = {
{ 48000000, P_PLL8, 8 },
{ 100000000, P_PLL3, 12 },
{ 120000000, P_PLL3, 10 },
{ }
};
static struct clk_rcg ce3_src = {
.ns_reg = 0x36c0,
.p = {
.pre_div_shift = 3,
.pre_div_width = 4,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll3_map,
},
.freq_tbl = clk_tbl_ce3,
.clkr = {
.enable_reg = 0x36c0,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "ce3_src",
.parent_data = gcc_pxo_pll8_pll3,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll3),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
},
};
static struct clk_branch ce3_core_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 5,
.clkr = {
.enable_reg = 0x36cc,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "ce3_core_clk",
.parent_hws = (const struct clk_hw*[]){
&ce3_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch ce3_h_clk = {
.halt_reg = 0x2fc4,
.halt_bit = 16,
.clkr = {
.enable_reg = 0x36c4,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "ce3_h_clk",
.parent_hws = (const struct clk_hw*[]){
&ce3_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct freq_tbl clk_tbl_sata_ref[] = {
{ 48000000, P_PLL8, 8, 0, 0 },
{ 100000000, P_PLL3, 12, 0, 0 },
{ }
};
static struct clk_rcg sata_clk_src = {
.ns_reg = 0x2c08,
.p = {
.pre_div_shift = 3,
.pre_div_width = 4,
},
.s = {
.src_sel_shift = 0,
.parent_map = gcc_pxo_pll8_pll3_map,
},
.freq_tbl = clk_tbl_sata_ref,
.clkr = {
.enable_reg = 0x2c08,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "sata_clk_src",
.parent_data = gcc_pxo_pll8_pll3,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll3),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
},
};
static struct clk_branch sata_rxoob_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 26,
.clkr = {
.enable_reg = 0x2c0c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sata_rxoob_clk",
.parent_hws = (const struct clk_hw*[]){
&sata_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch sata_pmalive_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 25,
.clkr = {
.enable_reg = 0x2c10,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sata_pmalive_clk",
.parent_hws = (const struct clk_hw*[]){
&sata_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch sata_phy_ref_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 24,
.clkr = {
.enable_reg = 0x2c14,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sata_phy_ref_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "pxo", .name = "pxo_board",
},
.num_parents = 1,
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch sata_a_clk = {
.halt_reg = 0x2fc0,
.halt_bit = 12,
.clkr = {
.enable_reg = 0x2c20,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sata_a_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch sata_h_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 27,
.clkr = {
.enable_reg = 0x2c00,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sata_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch sfab_sata_s_h_clk = {
.halt_reg = 0x2fc4,
.halt_bit = 14,
.clkr = {
.enable_reg = 0x2480,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sfab_sata_s_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch sata_phy_cfg_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 12,
.clkr = {
.enable_reg = 0x2c40,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sata_phy_cfg_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pcie_phy_ref_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 29,
.clkr = {
.enable_reg = 0x22d0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pcie_phy_ref_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pcie_h_clk = {
.halt_reg = 0x2fd4,
.halt_bit = 8,
.clkr = {
.enable_reg = 0x22cc,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pcie_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pcie_a_clk = {
.halt_reg = 0x2fc0,
.halt_bit = 13,
.clkr = {
.enable_reg = 0x22c0,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pcie_a_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pmic_arb0_h_clk = {
.halt_reg = 0x2fd8,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 22,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "pmic_arb0_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pmic_arb1_h_clk = {
.halt_reg = 0x2fd8,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 21,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "pmic_arb1_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch pmic_ssbi2_clk = {
.halt_reg = 0x2fd8,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 23,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "pmic_ssbi2_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_branch rpm_msg_ram_h_clk = {
.hwcg_reg = 0x27e0,
.hwcg_bit = 6,
.halt_reg = 0x2fd8,
.halt_check = BRANCH_HALT_VOTED,
.halt_bit = 12,
.clkr = {
.enable_reg = 0x3080,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "rpm_msg_ram_h_clk",
.ops = &clk_branch_ops,
},
},
};
static struct clk_regmap *gcc_msm8960_clks[] = {
[PLL3] = &pll3.clkr,
[PLL4_VOTE] = &pll4_vote,
[PLL8] = &pll8.clkr,
[PLL8_VOTE] = &pll8_vote,
[PLL14] = &pll14.clkr,
[PLL14_VOTE] = &pll14_vote,
[GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
[GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
[GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
[GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
[GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
[GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
[GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
[GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
[GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
[GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
[GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
[GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
[GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
[GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
[GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
[GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
[GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
[GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
[GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
[GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
[GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
[GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
[GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
[GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
[GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
[GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
[GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
[GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
[GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
[GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
[GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
[GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
[GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
[GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
[GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
[GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
[GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
[GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
[GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
[GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
[GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
[GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
[GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
[GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
[GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
[GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
[GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
[GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
[GP0_SRC] = &gp0_src.clkr,
[GP0_CLK] = &gp0_clk.clkr,
[GP1_SRC] = &gp1_src.clkr,
[GP1_CLK] = &gp1_clk.clkr,
[GP2_SRC] = &gp2_src.clkr,
[GP2_CLK] = &gp2_clk.clkr,
[PMEM_A_CLK] = &pmem_clk.clkr,
[PRNG_SRC] = &prng_src.clkr,
[PRNG_CLK] = &prng_clk.clkr,
[SDC1_SRC] = &sdc1_src.clkr,
[SDC1_CLK] = &sdc1_clk.clkr,
[SDC2_SRC] = &sdc2_src.clkr,
[SDC2_CLK] = &sdc2_clk.clkr,
[SDC3_SRC] = &sdc3_src.clkr,
[SDC3_CLK] = &sdc3_clk.clkr,
[SDC4_SRC] = &sdc4_src.clkr,
[SDC4_CLK] = &sdc4_clk.clkr,
[SDC5_SRC] = &sdc5_src.clkr,
[SDC5_CLK] = &sdc5_clk.clkr,
[TSIF_REF_SRC] = &tsif_ref_src.clkr,
[TSIF_REF_CLK] = &tsif_ref_clk.clkr,
[USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
[USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
[USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
[USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
[USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
[USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
[USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
[USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
[USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
[USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
[USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
[USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
[USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
[CE1_CORE_CLK] = &ce1_core_clk.clkr,
[CE1_H_CLK] = &ce1_h_clk.clkr,
[DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
[GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
[GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
[GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
[GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
[GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
[GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
[GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
[GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
[GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
[GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
[GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
[GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
[TSIF_H_CLK] = &tsif_h_clk.clkr,
[USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
[USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
[USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
[USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
[SDC1_H_CLK] = &sdc1_h_clk.clkr,
[SDC2_H_CLK] = &sdc2_h_clk.clkr,
[SDC3_H_CLK] = &sdc3_h_clk.clkr,
[SDC4_H_CLK] = &sdc4_h_clk.clkr,
[SDC5_H_CLK] = &sdc5_h_clk.clkr,
[ADM0_CLK] = &adm0_clk.clkr,
[ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
[PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
[PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
[PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
[RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
[PLL9] = &hfpll0.clkr,
[PLL10] = &hfpll1.clkr,
[PLL12] = &hfpll_l2.clkr,
};
static const struct qcom_reset_map gcc_msm8960_resets[] = {
[SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 },
[SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 },
[QDSS_STM_RESET] = { 0x2060, 6 },
[AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
[AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
[AFAB_SMPSS_M0_RESET] = { 0x20b8 },
[AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
[AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
[SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
[SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
[SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
[ADM0_C2_RESET] = { 0x220c, 4},
[ADM0_C1_RESET] = { 0x220c, 3},
[ADM0_C0_RESET] = { 0x220c, 2},
[ADM0_PBUS_RESET] = { 0x220c, 1 },
[ADM0_RESET] = { 0x220c },
[QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
[QDSS_POR_RESET] = { 0x2260, 4 },
[QDSS_TSCTR_RESET] = { 0x2260, 3 },
[QDSS_HRESET_RESET] = { 0x2260, 2 },
[QDSS_AXI_RESET] = { 0x2260, 1 },
[QDSS_DBG_RESET] = { 0x2260 },
[PCIE_A_RESET] = { 0x22c0, 7 },
[PCIE_AUX_RESET] = { 0x22c8, 7 },
[PCIE_H_RESET] = { 0x22d0, 7 },
[SFAB_PCIE_M_RESET] = { 0x22d4, 1 },
[SFAB_PCIE_S_RESET] = { 0x22d4 },
[SFAB_MSS_M_RESET] = { 0x2340, 7 },
[SFAB_USB3_M_RESET] = { 0x2360, 7 },
[SFAB_RIVA_M_RESET] = { 0x2380, 7 },
[SFAB_LPASS_RESET] = { 0x23a0, 7 },
[SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
[AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
[AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
[SFAB_SATA_S_RESET] = { 0x2480, 7 },
[SFAB_DFAB_M_RESET] = { 0x2500, 7 },
[DFAB_SFAB_M_RESET] = { 0x2520, 7 },
[DFAB_SWAY0_RESET] = { 0x2540, 7 },
[DFAB_SWAY1_RESET] = { 0x2544, 7 },
[DFAB_ARB0_RESET] = { 0x2560, 7 },
[DFAB_ARB1_RESET] = { 0x2564, 7 },
[PPSS_PROC_RESET] = { 0x2594, 1 },
[PPSS_RESET] = { 0x2594},
[DMA_BAM_RESET] = { 0x25c0, 7 },
[SPS_TIC_H_RESET] = { 0x2600, 7 },
[SLIMBUS_H_RESET] = { 0x2620, 7 },
[SFAB_CFPB_M_RESET] = { 0x2680, 7 },
[SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
[TSIF_H_RESET] = { 0x2700, 7 },
[CE1_H_RESET] = { 0x2720, 7 },
[CE1_CORE_RESET] = { 0x2724, 7 },
[CE1_SLEEP_RESET] = { 0x2728, 7 },
[CE2_H_RESET] = { 0x2740, 7 },
[CE2_CORE_RESET] = { 0x2744, 7 },
[SFAB_SFPB_M_RESET] = { 0x2780, 7 },
[SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
[RPM_PROC_RESET] = { 0x27c0, 7 },
[PMIC_SSBI2_RESET] = { 0x280c, 12 },
[SDC1_RESET] = { 0x2830 },
[SDC2_RESET] = { 0x2850 },
[SDC3_RESET] = { 0x2870 },
[SDC4_RESET] = { 0x2890 },
[SDC5_RESET] = { 0x28b0 },
[DFAB_A2_RESET] = { 0x28c0, 7 },
[USB_HS1_RESET] = { 0x2910 },
[USB_HSIC_RESET] = { 0x2934 },
[USB_FS1_XCVR_RESET] = { 0x2974, 1 },
[USB_FS1_RESET] = { 0x2974 },
[USB_FS2_XCVR_RESET] = { 0x2994, 1 },
[USB_FS2_RESET] = { 0x2994 },
[GSBI1_RESET] = { 0x29dc },
[GSBI2_RESET] = { 0x29fc },
[GSBI3_RESET] = { 0x2a1c },
[GSBI4_RESET] = { 0x2a3c },
[GSBI5_RESET] = { 0x2a5c },
[GSBI6_RESET] = { 0x2a7c },
[GSBI7_RESET] = { 0x2a9c },
[GSBI8_RESET] = { 0x2abc },
[GSBI9_RESET] = { 0x2adc },
[GSBI10_RESET] = { 0x2afc },
[GSBI11_RESET] = { 0x2b1c },
[GSBI12_RESET] = { 0x2b3c },
[SPDM_RESET] = { 0x2b6c },
[TLMM_H_RESET] = { 0x2ba0, 7 },
[SFAB_MSS_S_RESET] = { 0x2c00, 7 },
[MSS_SLP_RESET] = { 0x2c60, 7 },
[MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 },
[MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 },
[MSS_RESET] = { 0x2c64 },
[SATA_H_RESET] = { 0x2c80, 7 },
[SATA_RXOOB_RESE] = { 0x2c8c, 7 },
[SATA_PMALIVE_RESET] = { 0x2c90, 7 },
[SATA_SFAB_M_RESET] = { 0x2c98, 7 },
[TSSC_RESET] = { 0x2ca0, 7 },
[PDM_RESET] = { 0x2cc0, 12 },
[MPM_H_RESET] = { 0x2da0, 7 },
[MPM_RESET] = { 0x2da4 },
[SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
[PRNG_RESET] = { 0x2e80, 12 },
[RIVA_RESET] = { 0x35e0 },
};
static struct clk_regmap *gcc_apq8064_clks[] = {
[PLL3] = &pll3.clkr,
[PLL4_VOTE] = &pll4_vote,
[PLL8] = &pll8.clkr,
[PLL8_VOTE] = &pll8_vote,
[PLL14] = &pll14.clkr,
[PLL14_VOTE] = &pll14_vote,
[GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
[GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
[GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
[GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
[GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
[GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
[GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
[GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
[GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
[GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
[GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
[GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
[GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
[GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
[GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
[GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
[GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
[GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
[GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
[GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
[GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
[GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
[GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
[GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
[GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
[GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
[GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
[GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
[GP0_SRC] = &gp0_src.clkr,
[GP0_CLK] = &gp0_clk.clkr,
[GP1_SRC] = &gp1_src.clkr,
[GP1_CLK] = &gp1_clk.clkr,
[GP2_SRC] = &gp2_src.clkr,
[GP2_CLK] = &gp2_clk.clkr,
[PMEM_A_CLK] = &pmem_clk.clkr,
[PRNG_SRC] = &prng_src.clkr,
[PRNG_CLK] = &prng_clk.clkr,
[SDC1_SRC] = &sdc1_src.clkr,
[SDC1_CLK] = &sdc1_clk.clkr,
[SDC2_SRC] = &sdc2_src.clkr,
[SDC2_CLK] = &sdc2_clk.clkr,
[SDC3_SRC] = &sdc3_src.clkr,
[SDC3_CLK] = &sdc3_clk.clkr,
[SDC4_SRC] = &sdc4_src.clkr,
[SDC4_CLK] = &sdc4_clk.clkr,
[TSIF_REF_SRC] = &tsif_ref_src.clkr,
[TSIF_REF_CLK] = &tsif_ref_clk.clkr,
[USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
[USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
[USB_HS3_XCVR_SRC] = &usb_hs3_xcvr_src.clkr,
[USB_HS3_XCVR_CLK] = &usb_hs3_xcvr_clk.clkr,
[USB_HS4_XCVR_SRC] = &usb_hs4_xcvr_src.clkr,
[USB_HS4_XCVR_CLK] = &usb_hs4_xcvr_clk.clkr,
[USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
[USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
[USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
[USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
[USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
[USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
[USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
[USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
[SATA_H_CLK] = &sata_h_clk.clkr,
[SATA_CLK_SRC] = &sata_clk_src.clkr,
[SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
[SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
[SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
[SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
[SATA_A_CLK] = &sata_a_clk.clkr,
[SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
[CE3_SRC] = &ce3_src.clkr,
[CE3_CORE_CLK] = &ce3_core_clk.clkr,
[CE3_H_CLK] = &ce3_h_clk.clkr,
[DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
[GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
[GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
[GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
[GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
[GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
[GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
[GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
[TSIF_H_CLK] = &tsif_h_clk.clkr,
[USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
[USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
[USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
[USB_HS3_H_CLK] = &usb_hs3_h_clk.clkr,
[USB_HS4_H_CLK] = &usb_hs4_h_clk.clkr,
[SDC1_H_CLK] = &sdc1_h_clk.clkr,
[SDC2_H_CLK] = &sdc2_h_clk.clkr,
[SDC3_H_CLK] = &sdc3_h_clk.clkr,
[SDC4_H_CLK] = &sdc4_h_clk.clkr,
[ADM0_CLK] = &adm0_clk.clkr,
[ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
[PCIE_A_CLK] = &pcie_a_clk.clkr,
[PCIE_PHY_REF_CLK] = &pcie_phy_ref_clk.clkr,
[PCIE_H_CLK] = &pcie_h_clk.clkr,
[PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
[PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
[PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
[RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
[PLL9] = &hfpll0.clkr,
[PLL10] = &hfpll1.clkr,
[PLL12] = &hfpll_l2.clkr,
[PLL16] = &hfpll2.clkr,
[PLL17] = &hfpll3.clkr,
};
static const struct qcom_reset_map gcc_apq8064_resets[] = {
[QDSS_STM_RESET] = { 0x2060, 6 },
[AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
[AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
[AFAB_SMPSS_M0_RESET] = { 0x20b8 },
[AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
[AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
[SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
[SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
[SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
[ADM0_C2_RESET] = { 0x220c, 4},
[ADM0_C1_RESET] = { 0x220c, 3},
[ADM0_C0_RESET] = { 0x220c, 2},
[ADM0_PBUS_RESET] = { 0x220c, 1 },
[ADM0_RESET] = { 0x220c },
[QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
[QDSS_POR_RESET] = { 0x2260, 4 },
[QDSS_TSCTR_RESET] = { 0x2260, 3 },
[QDSS_HRESET_RESET] = { 0x2260, 2 },
[QDSS_AXI_RESET] = { 0x2260, 1 },
[QDSS_DBG_RESET] = { 0x2260 },
[SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
[SFAB_PCIE_S_RESET] = { 0x22d8 },
[PCIE_EXT_PCI_RESET] = { 0x22dc, 6 },
[PCIE_PHY_RESET] = { 0x22dc, 5 },
[PCIE_PCI_RESET] = { 0x22dc, 4 },
[PCIE_POR_RESET] = { 0x22dc, 3 },
[PCIE_HCLK_RESET] = { 0x22dc, 2 },
[PCIE_ACLK_RESET] = { 0x22dc },
[SFAB_USB3_M_RESET] = { 0x2360, 7 },
[SFAB_RIVA_M_RESET] = { 0x2380, 7 },
[SFAB_LPASS_RESET] = { 0x23a0, 7 },
[SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
[AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
[AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
[SFAB_SATA_S_RESET] = { 0x2480, 7 },
[SFAB_DFAB_M_RESET] = { 0x2500, 7 },
[DFAB_SFAB_M_RESET] = { 0x2520, 7 },
[DFAB_SWAY0_RESET] = { 0x2540, 7 },
[DFAB_SWAY1_RESET] = { 0x2544, 7 },
[DFAB_ARB0_RESET] = { 0x2560, 7 },
[DFAB_ARB1_RESET] = { 0x2564, 7 },
[PPSS_PROC_RESET] = { 0x2594, 1 },
[PPSS_RESET] = { 0x2594},
[DMA_BAM_RESET] = { 0x25c0, 7 },
[SPS_TIC_H_RESET] = { 0x2600, 7 },
[SFAB_CFPB_M_RESET] = { 0x2680, 7 },
[SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
[TSIF_H_RESET] = { 0x2700, 7 },
[CE1_H_RESET] = { 0x2720, 7 },
[CE1_CORE_RESET] = { 0x2724, 7 },
[CE1_SLEEP_RESET] = { 0x2728, 7 },
[CE2_H_RESET] = { 0x2740, 7 },
[CE2_CORE_RESET] = { 0x2744, 7 },
[SFAB_SFPB_M_RESET] = { 0x2780, 7 },
[SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
[RPM_PROC_RESET] = { 0x27c0, 7 },
[PMIC_SSBI2_RESET] = { 0x280c, 12 },
[SDC1_RESET] = { 0x2830 },
[SDC2_RESET] = { 0x2850 },
[SDC3_RESET] = { 0x2870 },
[SDC4_RESET] = { 0x2890 },
[USB_HS1_RESET] = { 0x2910 },
[USB_HSIC_RESET] = { 0x2934 },
[USB_FS1_XCVR_RESET] = { 0x2974, 1 },
[USB_FS1_RESET] = { 0x2974 },
[GSBI1_RESET] = { 0x29dc },
[GSBI2_RESET] = { 0x29fc },
[GSBI3_RESET] = { 0x2a1c },
[GSBI4_RESET] = { 0x2a3c },
[GSBI5_RESET] = { 0x2a5c },
[GSBI6_RESET] = { 0x2a7c },
[GSBI7_RESET] = { 0x2a9c },
[SPDM_RESET] = { 0x2b6c },
[TLMM_H_RESET] = { 0x2ba0, 7 },
[SATA_SFAB_M_RESET] = { 0x2c18 },
[SATA_RESET] = { 0x2c1c },
[GSS_SLP_RESET] = { 0x2c60, 7 },
[GSS_RESET] = { 0x2c64 },
[TSSC_RESET] = { 0x2ca0, 7 },
[PDM_RESET] = { 0x2cc0, 12 },
[MPM_H_RESET] = { 0x2da0, 7 },
[MPM_RESET] = { 0x2da4 },
[SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
[PRNG_RESET] = { 0x2e80, 12 },
[RIVA_RESET] = { 0x35e0 },
[CE3_H_RESET] = { 0x36c4, 7 },
[SFAB_CE3_M_RESET] = { 0x36c8, 1 },
[SFAB_CE3_S_RESET] = { 0x36c8 },
[CE3_RESET] = { 0x36cc, 7 },
[CE3_SLEEP_RESET] = { 0x36d0, 7 },
[USB_HS3_RESET] = { 0x3710 },
[USB_HS4_RESET] = { 0x3730 },
};
static const struct regmap_config gcc_msm8960_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x3660,
.fast_io = true,
};
static const struct regmap_config gcc_apq8064_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x3880,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_msm8960_desc = {
.config = &gcc_msm8960_regmap_config,
.clks = gcc_msm8960_clks,
.num_clks = ARRAY_SIZE(gcc_msm8960_clks),
.resets = gcc_msm8960_resets,
.num_resets = ARRAY_SIZE(gcc_msm8960_resets),
};
static const struct qcom_cc_desc gcc_apq8064_desc = {
.config = &gcc_apq8064_regmap_config,
.clks = gcc_apq8064_clks,
.num_clks = ARRAY_SIZE(gcc_apq8064_clks),
.resets = gcc_apq8064_resets,
.num_resets = ARRAY_SIZE(gcc_apq8064_resets),
};
static const struct of_device_id gcc_msm8960_match_table[] = {
{ .compatible = "qcom,gcc-msm8960", .data = &gcc_msm8960_desc },
{ .compatible = "qcom,gcc-apq8064", .data = &gcc_apq8064_desc },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table);
static int gcc_msm8960_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct of_device_id *match;
struct platform_device *tsens;
int ret;
match = of_match_device(gcc_msm8960_match_table, &pdev->dev);
if (!match)
return -EINVAL;
ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
if (ret)
return ret;
ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
if (ret)
return ret;
ret = qcom_cc_probe(pdev, match->data);
if (ret)
return ret;
if (match->data == &gcc_apq8064_desc) {
hfpll1.d = &hfpll1_8064_data;
hfpll_l2.d = &hfpll_l2_8064_data;
}
if (of_get_available_child_count(pdev->dev.of_node) != 0)
return devm_of_platform_populate(&pdev->dev);
tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1,
NULL, 0);
if (IS_ERR(tsens))
return PTR_ERR(tsens);
platform_set_drvdata(pdev, tsens);
return 0;
}
static void gcc_msm8960_remove(struct platform_device *pdev)
{
struct platform_device *tsens = platform_get_drvdata(pdev);
if (tsens)
platform_device_unregister(tsens);
}
static struct platform_driver gcc_msm8960_driver = {
.probe = gcc_msm8960_probe,
.remove_new = gcc_msm8960_remove,
.driver = {
.name = "gcc-msm8960",
.of_match_table = gcc_msm8960_match_table,
},
};
static int __init gcc_msm8960_init(void)
{
return platform_driver_register(&gcc_msm8960_driver);
}
core_initcall(gcc_msm8960_init);
static void __exit gcc_msm8960_exit(void)
{
platform_driver_unregister(&gcc_msm8960_driver);
}
module_exit(gcc_msm8960_exit);
MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:gcc-msm8960");
| linux-master | drivers/clk/qcom/gcc-msm8960.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
#include "common.h"
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "gdsc.h"
#define CX_GMU_CBCR_SLEEP_MASK 0xf
#define CX_GMU_CBCR_SLEEP_SHIFT 4
#define CX_GMU_CBCR_WAKE_MASK 0xf
#define CX_GMU_CBCR_WAKE_SHIFT 8
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_CC_PLL1_OUT_MAIN,
};
static const struct alpha_pll_config gpu_cc_pll1_config = {
.l = 0x1a,
.alpha = 0xaab,
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x100,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo", .name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .fw_name = "gcc_gpu_gpll0_clk_src", .name = "gcc_gpu_gpll0_clk_src" },
{ .fw_name = "gcc_gpu_gpll0_div_clk_src", .name = "gcc_gpu_gpll0_div_clk_src" },
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x1120,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x1098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x109c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x109c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x106c,
.gds_hw_ctrl = 0x1540,
.clk_dis_wait_val = 0x8,
.pd = {
.name = "gpu_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x100c,
.clamp_io_ctrl = 0x1508,
.pd = {
.name = "gpu_gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
};
static struct clk_regmap *gpu_cc_sdm845_clocks[] = {
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
};
static struct gdsc *gpu_cc_sdm845_gdscs[] = {
[GPU_CX_GDSC] = &gpu_cx_gdsc,
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
static const struct regmap_config gpu_cc_sdm845_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x8008,
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_sdm845_desc = {
.config = &gpu_cc_sdm845_regmap_config,
.clks = gpu_cc_sdm845_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sdm845_clocks),
.gdscs = gpu_cc_sdm845_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sdm845_gdscs),
};
static const struct of_device_id gpu_cc_sdm845_match_table[] = {
{ .compatible = "qcom,sdm845-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sdm845_match_table);
static int gpu_cc_sdm845_probe(struct platform_device *pdev)
{
struct regmap *regmap;
unsigned int value, mask;
regmap = qcom_cc_map(pdev, &gpu_cc_sdm845_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
/*
* Configure gpu_cc_cx_gmu_clk with recommended
* wakeup/sleep settings
*/
mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
regmap_update_bits(regmap, 0x1098, mask, value);
return qcom_cc_really_probe(pdev, &gpu_cc_sdm845_desc, regmap);
}
static struct platform_driver gpu_cc_sdm845_driver = {
.probe = gpu_cc_sdm845_probe,
.driver = {
.name = "sdm845-gpucc",
.of_match_table = gpu_cc_sdm845_match_table,
},
};
static int __init gpu_cc_sdm845_init(void)
{
return platform_driver_register(&gpu_cc_sdm845_driver);
}
subsys_initcall(gpu_cc_sdm845_init);
static void __exit gpu_cc_sdm845_exit(void)
{
platform_driver_unregister(&gpu_cc_sdm845_driver);
}
module_exit(gpu_cc_sdm845_exit);
MODULE_DESCRIPTION("QTI GPUCC SDM845 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gpucc-sdm845.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Based on dispcc-qcm2290.c
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Linaro Ltd.
*/
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm6115-dispcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
enum {
DT_BI_TCXO,
DT_SLEEP_CLK,
DT_DSI0_PHY_PLL_OUT_BYTECLK,
DT_DSI0_PHY_PLL_OUT_DSICLK,
DT_GPLL0_DISP_DIV,
};
enum {
P_BI_TCXO,
P_DISP_CC_PLL0_OUT_MAIN,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
P_GPLL0_OUT_MAIN,
P_SLEEP_CLK,
};
static const struct clk_parent_data parent_data_tcxo = { .index = DT_BI_TCXO };
static const struct pll_vco spark_vco[] = {
{ 500000000, 1000000000, 2 },
};
/* 768MHz configuration */
static const struct alpha_pll_config disp_cc_pll0_config = {
.l = 0x28,
.alpha = 0x0,
.alpha_en_mask = BIT(24),
.vco_val = 0x2 << 20,
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055B,
};
static struct clk_alpha_pll disp_cc_pll0 = {
.offset = 0x0,
.vco_table = spark_vco,
.num_vco = ARRAY_SIZE(spark_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "disp_cc_pll0",
.parent_data = &parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct clk_div_table post_div_table_disp_cc_pll0_out_main[] = {
{ 0x0, 1 },
{ }
};
static struct clk_alpha_pll_postdiv disp_cc_pll0_out_main = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_disp_cc_pll0_out_main,
.num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll0_out_main),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_pll0_out_main",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_pll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_ops,
},
};
static const struct parent_map disp_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
};
static const struct clk_parent_data disp_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
};
static const struct parent_map disp_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
};
static const struct parent_map disp_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_GPLL0_DISP_DIV },
};
static const struct parent_map disp_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data disp_cc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
{ .hw = &disp_cc_pll0_out_main.clkr.hw },
};
static const struct parent_map disp_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
};
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
};
static const struct parent_map disp_cc_parent_map_5[] = {
{ P_SLEEP_CLK, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_5[] = {
{ .index = DT_SLEEP_CLK, },
};
static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
.cmd_rcgr = 0x20bc,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
/* For set_rate and set_parent to succeed, parent(s) must be enabled */
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE | CLK_GET_RATE_NOCACHE,
.ops = &clk_byte2_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
.reg = 0x20d4,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
.cmd_rcgr = 0x2154,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.cmd_rcgr = 0x20d8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
F(384000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.cmd_rcgr = 0x2074,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.cmd_rcgr = 0x205c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
/* For set_rate and set_parent to succeed, parent(s) must be enabled */
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE | CLK_GET_RATE_NOCACHE,
.ops = &clk_pixel_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
.cmd_rcgr = 0x208c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
.cmd_rcgr = 0x20a4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
F(32764, P_SLEEP_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_sleep_clk_src = {
.cmd_rcgr = 0x6050,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.freq_tbl = ftbl_disp_cc_sleep_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_sleep_clk_src",
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch disp_cc_mdss_ahb_clk = {
.halt_reg = 0x2044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_clk = {
.halt_reg = 0x2024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
.halt_reg = 0x2028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_esc0_clk = {
.halt_reg = 0x202c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x202c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_clk = {
.halt_reg = 0x2008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
.halt_reg = 0x2018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x2018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_lut_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
.halt_reg = 0x4004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_pclk0_clk = {
.halt_reg = 0x2004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rot_clk = {
.halt_reg = 0x2010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_rot_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_vsync_clk = {
.halt_reg = 0x2020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_sleep_clk = {
.halt_reg = 0x6068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_sleep_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x3000,
.pd = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL,
};
static struct gdsc *disp_cc_sm6115_gdscs[] = {
[MDSS_GDSC] = &mdss_gdsc,
};
static struct clk_regmap *disp_cc_sm6115_clocks[] = {
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
[DISP_CC_PLL0_OUT_MAIN] = &disp_cc_pll0_out_main.clkr,
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
[DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
};
static const struct regmap_config disp_cc_sm6115_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x10000,
.fast_io = true,
};
static const struct qcom_cc_desc disp_cc_sm6115_desc = {
.config = &disp_cc_sm6115_regmap_config,
.clks = disp_cc_sm6115_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sm6115_clocks),
.gdscs = disp_cc_sm6115_gdscs,
.num_gdscs = ARRAY_SIZE(disp_cc_sm6115_gdscs),
};
static const struct of_device_id disp_cc_sm6115_match_table[] = {
{ .compatible = "qcom,sm6115-dispcc" },
{ }
};
MODULE_DEVICE_TABLE(of, disp_cc_sm6115_match_table);
static int disp_cc_sm6115_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &disp_cc_sm6115_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
/* Keep DISP_CC_XO_CLK always-ON */
regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0));
ret = qcom_cc_really_probe(pdev, &disp_cc_sm6115_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register DISP CC clocks\n");
return ret;
}
return ret;
}
static struct platform_driver disp_cc_sm6115_driver = {
.probe = disp_cc_sm6115_probe,
.driver = {
.name = "dispcc-sm6115",
.of_match_table = disp_cc_sm6115_match_table,
},
};
module_platform_driver(disp_cc_sm6115_driver);
MODULE_DESCRIPTION("Qualcomm SM6115 Display Clock controller");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/dispcc-sm6115.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018-2020, 2022, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_DISP_CC_PLL0_OUT_MAIN,
P_DISP_CC_PLL1_OUT_EVEN,
P_DISP_CC_PLL1_OUT_MAIN,
P_DP_PHY_PLL_LINK_CLK,
P_DP_PHY_PLL_VCO_DIV_CLK,
P_DPTX1_PHY_PLL_LINK_CLK,
P_DPTX1_PHY_PLL_VCO_DIV_CLK,
P_DPTX2_PHY_PLL_LINK_CLK,
P_DPTX2_PHY_PLL_VCO_DIV_CLK,
P_EDP_PHY_PLL_LINK_CLK,
P_EDP_PHY_PLL_VCO_DIV_CLK,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
P_DSI1_PHY_PLL_OUT_BYTECLK,
P_DSI1_PHY_PLL_OUT_DSICLK,
};
static struct pll_vco vco_table[] = {
{ 249600000, 2000000000, 0 },
};
static struct pll_vco lucid_5lpe_vco[] = {
{ 249600000, 1750000000, 0 },
};
static struct alpha_pll_config disp_cc_pll0_config = {
.l = 0x47,
.alpha = 0xE000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329A699C,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_init_data disp_cc_pll0_init = {
.name = "disp_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
};
static struct clk_alpha_pll disp_cc_pll0 = {
.offset = 0x0,
.vco_table = vco_table,
.num_vco = ARRAY_SIZE(vco_table),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &disp_cc_pll0_init
};
static struct alpha_pll_config disp_cc_pll1_config = {
.l = 0x1F,
.alpha = 0x4000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329A699C,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_init_data disp_cc_pll1_init = {
.name = "disp_cc_pll1",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
};
static struct clk_alpha_pll disp_cc_pll1 = {
.offset = 0x1000,
.vco_table = vco_table,
.num_vco = ARRAY_SIZE(vco_table),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &disp_cc_pll1_init
};
static const struct parent_map disp_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_DP_PHY_PLL_LINK_CLK, 1 },
{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
{ P_DPTX1_PHY_PLL_LINK_CLK, 3 },
{ P_DPTX1_PHY_PLL_VCO_DIV_CLK, 4 },
{ P_DPTX2_PHY_PLL_LINK_CLK, 5 },
{ P_DPTX2_PHY_PLL_VCO_DIV_CLK, 6 },
};
static const struct clk_parent_data disp_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dp_phy_pll_link_clk" },
{ .fw_name = "dp_phy_pll_vco_div_clk" },
{ .fw_name = "dptx1_phy_pll_link_clk" },
{ .fw_name = "dptx1_phy_pll_vco_div_clk" },
{ .fw_name = "dptx2_phy_pll_link_clk" },
{ .fw_name = "dptx2_phy_pll_vco_div_clk" },
};
static const struct parent_map disp_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map disp_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
{ P_DSI1_PHY_PLL_OUT_BYTECLK, 2 },
};
static const struct clk_parent_data disp_cc_parent_data_2[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dsi0_phy_pll_out_byteclk" },
{ .fw_name = "dsi1_phy_pll_out_byteclk" },
};
static const struct parent_map disp_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_3[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &disp_cc_pll1.clkr.hw },
};
static const struct parent_map disp_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_EDP_PHY_PLL_LINK_CLK, 1 },
{ P_EDP_PHY_PLL_VCO_DIV_CLK, 2},
};
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "edp_phy_pll_link_clk" },
{ .fw_name = "edp_phy_pll_vco_div_clk" },
};
static const struct parent_map disp_cc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_5[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &disp_cc_pll0.clkr.hw },
{ .hw = &disp_cc_pll1.clkr.hw },
};
static const struct parent_map disp_cc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
{ P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
};
static const struct clk_parent_data disp_cc_parent_data_6[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dsi0_phy_pll_out_dsiclk" },
{ .fw_name = "dsi1_phy_pll_out_dsiclk" },
};
static const struct parent_map disp_cc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
/* { P_DISP_CC_PLL1_OUT_EVEN, 5 }, */
};
static const struct clk_parent_data disp_cc_parent_data_7[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &disp_cc_pll1.clkr.hw },
/* { .hw = &disp_cc_pll1_out_even.clkr.hw }, */
};
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
.cmd_rcgr = 0x22bc,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
.cmd_rcgr = 0x2110,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
.cmd_rcgr = 0x212c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte1_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = {
.cmd_rcgr = 0x2240,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_aux1_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
.cmd_rcgr = 0x21dc,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_aux_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = {
.cmd_rcgr = 0x220c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link1_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
.cmd_rcgr = 0x2178,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
.cmd_rcgr = 0x21c4,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel1_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = {
.cmd_rcgr = 0x21f4,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel2_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
.cmd_rcgr = 0x21ac,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = {
.cmd_rcgr = 0x228c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_aux_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_edp_gtc_clk_src = {
.cmd_rcgr = 0x22a4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_7,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_gtc_clk_src",
.parent_data = disp_cc_parent_data_7,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = {
.cmd_rcgr = 0x2270,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_link_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = {
.cmd_rcgr = 0x2258,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_pixel_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.ops = &clk_dp_ops,
},
};
static struct clk_branch disp_cc_mdss_edp_aux_clk = {
.halt_reg = 0x2078,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_edp_gtc_clk = {
.halt_reg = 0x207c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x207c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_gtc_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_gtc_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_edp_link_clk = {
.halt_reg = 0x2070,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2070,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_link_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap_div disp_cc_mdss_edp_link_div_clk_src = {
.reg = 0x2288,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_edp_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_link_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch disp_cc_mdss_edp_link_intf_clk = {
.halt_reg = 0x2074,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2074,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_edp_pixel_clk = {
.halt_reg = 0x206c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x206c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_pixel_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_pixel_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.cmd_rcgr = 0x2148,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
.cmd_rcgr = 0x2160,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc1_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(85714286, P_DISP_CC_PLL1_OUT_MAIN, 7, 0, 0),
F(100000000, P_DISP_CC_PLL1_OUT_MAIN, 6, 0, 0),
F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0),
F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.cmd_rcgr = 0x20c8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk_src",
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.cmd_rcgr = 0x2098,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_6,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_6,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
.cmd_rcgr = 0x20b0,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_6,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk1_clk_src",
.parent_data = disp_cc_parent_data_6,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
.cmd_rcgr = 0x20e0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk_src",
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
.cmd_rcgr = 0x20f8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
.reg = 0x2128,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
.reg = 0x2144,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte1_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src = {
.reg = 0x2224,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dp_link1_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
.reg = 0x2190,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dp_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch disp_cc_mdss_ahb_clk = {
.halt_reg = 0x2080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_clk = {
.halt_reg = 0x2028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
.halt_reg = 0x202c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x202c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte1_clk = {
.halt_reg = 0x2030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
.halt_reg = 0x2034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte1_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte1_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_aux1_clk = {
.halt_reg = 0x2068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_aux1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_aux1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_aux_clk = {
.halt_reg = 0x2054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_link1_clk = {
.halt_reg = 0x205c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x205c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_link1_intf_clk = {
.halt_reg = 0x2060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link1_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link1_div_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_link_clk = {
.halt_reg = 0x2040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
.halt_reg = 0x2044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_pixel1_clk = {
.halt_reg = 0x2050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_pixel1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_pixel2_clk = {
.halt_reg = 0x2058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel2_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_pixel2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
.halt_reg = 0x204c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x204c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_esc0_clk = {
.halt_reg = 0x2038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_esc1_clk = {
.halt_reg = 0x203c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x203c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_esc1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_clk = {
.halt_reg = 0x200c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
.halt_reg = 0x201c,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_lut_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
.halt_reg = 0x4004,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x4004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_pclk0_clk = {
.halt_reg = 0x2004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_pclk1_clk = {
.halt_reg = 0x2008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_pclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rot_clk = {
.halt_reg = 0x2014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_rot_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
.halt_reg = 0x400c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x400c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rscc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
.halt_reg = 0x4008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rscc_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_vsync_clk = {
.halt_reg = 0x2024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x3000,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL | RETAIN_FF_ENABLE,
};
static struct clk_regmap *disp_cc_sm8250_clocks[] = {
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
[DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
[DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,
[DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
[DISP_CC_MDSS_DP_AUX1_CLK] = &disp_cc_mdss_dp_aux1_clk.clkr,
[DISP_CC_MDSS_DP_AUX1_CLK_SRC] = &disp_cc_mdss_dp_aux1_clk_src.clkr,
[DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
[DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
[DISP_CC_MDSS_DP_LINK1_CLK] = &disp_cc_mdss_dp_link1_clk.clkr,
[DISP_CC_MDSS_DP_LINK1_CLK_SRC] = &disp_cc_mdss_dp_link1_clk_src.clkr,
[DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = &disp_cc_mdss_dp_link1_div_clk_src.clkr,
[DISP_CC_MDSS_DP_LINK1_INTF_CLK] = &disp_cc_mdss_dp_link1_intf_clk.clkr,
[DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
[DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dp_link_div_clk_src.clkr,
[DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
[DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr,
[DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = &disp_cc_mdss_dp_pixel1_clk_src.clkr,
[DISP_CC_MDSS_DP_PIXEL2_CLK] = &disp_cc_mdss_dp_pixel2_clk.clkr,
[DISP_CC_MDSS_DP_PIXEL2_CLK_SRC] = &disp_cc_mdss_dp_pixel2_clk_src.clkr,
[DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
[DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
[DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr,
[DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr,
[DISP_CC_MDSS_EDP_GTC_CLK] = &disp_cc_mdss_edp_gtc_clk.clkr,
[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = &disp_cc_mdss_edp_gtc_clk_src.clkr,
[DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr,
[DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr,
[DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_edp_link_div_clk_src.clkr,
[DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr,
[DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr,
[DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr,
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
[DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
[DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
[DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
[DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
[DISP_CC_PLL1] = &disp_cc_pll1.clkr,
};
static const struct qcom_reset_map disp_cc_sm8250_resets[] = {
[DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
[DISP_CC_MDSS_RSCC_BCR] = { 0x4000 },
};
static struct gdsc *disp_cc_sm8250_gdscs[] = {
[MDSS_GDSC] = &mdss_gdsc,
};
static const struct regmap_config disp_cc_sm8250_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x10000,
.fast_io = true,
};
static const struct qcom_cc_desc disp_cc_sm8250_desc = {
.config = &disp_cc_sm8250_regmap_config,
.clks = disp_cc_sm8250_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sm8250_clocks),
.resets = disp_cc_sm8250_resets,
.num_resets = ARRAY_SIZE(disp_cc_sm8250_resets),
.gdscs = disp_cc_sm8250_gdscs,
.num_gdscs = ARRAY_SIZE(disp_cc_sm8250_gdscs),
};
static const struct of_device_id disp_cc_sm8250_match_table[] = {
{ .compatible = "qcom,sc8180x-dispcc" },
{ .compatible = "qcom,sm8150-dispcc" },
{ .compatible = "qcom,sm8250-dispcc" },
{ .compatible = "qcom,sm8350-dispcc" },
{ }
};
MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table);
static int disp_cc_sm8250_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
regmap = qcom_cc_map(pdev, &disp_cc_sm8250_desc);
if (IS_ERR(regmap)) {
pm_runtime_put(&pdev->dev);
return PTR_ERR(regmap);
}
/* Apply differences for SM8150 and SM8350 */
BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") ||
of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
disp_cc_pll0_config.config_ctl_hi_val = 0x00002267;
disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024;
disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0;
disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops;
disp_cc_pll1_config.config_ctl_hi_val = 0x00002267;
disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
disp_cc_mdss_dp_link_intf_clk.clkr.hw.init->parent_hws[0] =
&disp_cc_mdss_dp_link_clk_src.clkr.hw;
disp_cc_mdss_dp_link1_intf_clk.clkr.hw.init->parent_hws[0] =
&disp_cc_mdss_dp_link1_clk_src.clkr.hw;
disp_cc_mdss_edp_link_intf_clk.clkr.hw.init->parent_hws[0] =
&disp_cc_mdss_edp_link_clk_src.clkr.hw;
disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = NULL;
disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = NULL;
disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = NULL;
} else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
static struct clk_rcg2 * const rcgs[] = {
&disp_cc_mdss_byte0_clk_src,
&disp_cc_mdss_byte1_clk_src,
&disp_cc_mdss_dp_aux1_clk_src,
&disp_cc_mdss_dp_aux_clk_src,
&disp_cc_mdss_dp_link1_clk_src,
&disp_cc_mdss_dp_link_clk_src,
&disp_cc_mdss_dp_pixel1_clk_src,
&disp_cc_mdss_dp_pixel2_clk_src,
&disp_cc_mdss_dp_pixel_clk_src,
&disp_cc_mdss_edp_aux_clk_src,
&disp_cc_mdss_edp_link_clk_src,
&disp_cc_mdss_edp_pixel_clk_src,
&disp_cc_mdss_esc0_clk_src,
&disp_cc_mdss_esc1_clk_src,
&disp_cc_mdss_mdp_clk_src,
&disp_cc_mdss_pclk0_clk_src,
&disp_cc_mdss_pclk1_clk_src,
&disp_cc_mdss_rot_clk_src,
&disp_cc_mdss_vsync_clk_src,
};
static struct clk_regmap_div * const divs[] = {
&disp_cc_mdss_byte0_div_clk_src,
&disp_cc_mdss_byte1_div_clk_src,
&disp_cc_mdss_dp_link1_div_clk_src,
&disp_cc_mdss_dp_link_div_clk_src,
&disp_cc_mdss_edp_link_div_clk_src,
};
unsigned int i;
static bool offset_applied;
/*
* note: trion == lucid, except for the prepare() op
* only apply the offsets once (in case of deferred probe)
*/
if (!offset_applied) {
for (i = 0; i < ARRAY_SIZE(rcgs); i++)
rcgs[i]->cmd_rcgr -= 4;
for (i = 0; i < ARRAY_SIZE(divs); i++) {
divs[i]->reg -= 4;
divs[i]->width = 4;
}
disp_cc_mdss_ahb_clk.halt_reg -= 4;
disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4;
offset_applied = true;
}
disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0;
disp_cc_pll0_config.config_ctl_hi1_val = 0x2a9a699c;
disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000;
disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
disp_cc_pll0.vco_table = lucid_5lpe_vco;
disp_cc_pll1_config.config_ctl_hi1_val = 0x2a9a699c;
disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000;
disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
disp_cc_pll1.vco_table = lucid_5lpe_vco;
disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK] = NULL;
disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = NULL;
}
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
/* Enable clock gating for MDP clocks */
regmap_update_bits(regmap, 0x8000, 0x10, 0x10);
/* DISP_CC_XO_CLK always-on */
regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0));
ret = qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap);
pm_runtime_put(&pdev->dev);
return ret;
}
static struct platform_driver disp_cc_sm8250_driver = {
.probe = disp_cc_sm8250_probe,
.driver = {
.name = "disp_cc-sm8250",
.of_match_table = disp_cc_sm8250_match_table,
},
};
static int __init disp_cc_sm8250_init(void)
{
return platform_driver_register(&disp_cc_sm8250_driver);
}
subsys_initcall(disp_cc_sm8250_init);
static void __exit disp_cc_sm8250_exit(void)
{
platform_driver_unregister(&disp_cc_sm8250_driver);
}
module_exit(disp_cc_sm8250_exit);
MODULE_DESCRIPTION("QTI DISPCC SM8250 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/dispcc-sm8250.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "reset.h"
static struct clk_pll pll4 = {
.l_reg = 0x4,
.m_reg = 0x8,
.n_reg = 0xc,
.config_reg = 0x14,
.mode_reg = 0x0,
.status_reg = 0x18,
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll4",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "pxo", .name = "pxo_board",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static const struct pll_config pll4_config = {
.l = 0xf,
.m = 0x91,
.n = 0xc7,
.vco_val = 0x0,
.vco_mask = BIT(17) | BIT(16),
.pre_div_val = 0x0,
.pre_div_mask = BIT(19),
.post_div_val = 0x0,
.post_div_mask = BIT(21) | BIT(20),
.mn_ena_mask = BIT(22),
.main_output_mask = BIT(23),
};
enum {
P_PXO,
P_PLL4,
};
static const struct parent_map lcc_pxo_pll4_map[] = {
{ P_PXO, 0 },
{ P_PLL4, 2 }
};
static const struct clk_parent_data lcc_pxo_pll4[] = {
{ .fw_name = "pxo", .name = "pxo_board" },
{ .fw_name = "pll4_vote", .name = "pll4_vote" },
};
static struct freq_tbl clk_tbl_aif_mi2s[] = {
{ 1024000, P_PLL4, 4, 1, 96 },
{ 1411200, P_PLL4, 4, 2, 139 },
{ 1536000, P_PLL4, 4, 1, 64 },
{ 2048000, P_PLL4, 4, 1, 48 },
{ 2116800, P_PLL4, 4, 2, 93 },
{ 2304000, P_PLL4, 4, 2, 85 },
{ 2822400, P_PLL4, 4, 6, 209 },
{ 3072000, P_PLL4, 4, 1, 32 },
{ 3175200, P_PLL4, 4, 1, 31 },
{ 4096000, P_PLL4, 4, 1, 24 },
{ 4233600, P_PLL4, 4, 9, 209 },
{ 4608000, P_PLL4, 4, 3, 64 },
{ 5644800, P_PLL4, 4, 12, 209 },
{ 6144000, P_PLL4, 4, 1, 16 },
{ 6350400, P_PLL4, 4, 2, 31 },
{ 8192000, P_PLL4, 4, 1, 12 },
{ 8467200, P_PLL4, 4, 18, 209 },
{ 9216000, P_PLL4, 4, 3, 32 },
{ 11289600, P_PLL4, 4, 24, 209 },
{ 12288000, P_PLL4, 4, 1, 8 },
{ 12700800, P_PLL4, 4, 27, 209 },
{ 13824000, P_PLL4, 4, 9, 64 },
{ 16384000, P_PLL4, 4, 1, 6 },
{ 16934400, P_PLL4, 4, 41, 238 },
{ 18432000, P_PLL4, 4, 3, 16 },
{ 22579200, P_PLL4, 2, 24, 209 },
{ 24576000, P_PLL4, 4, 1, 4 },
{ 27648000, P_PLL4, 4, 9, 32 },
{ 33868800, P_PLL4, 4, 41, 119 },
{ 36864000, P_PLL4, 4, 3, 8 },
{ 45158400, P_PLL4, 1, 24, 209 },
{ 49152000, P_PLL4, 4, 1, 2 },
{ 50803200, P_PLL4, 1, 27, 209 },
{ }
};
static struct clk_rcg mi2s_osr_src = {
.ns_reg = 0x48,
.md_reg = 0x4c,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 24,
.m_val_shift = 8,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = lcc_pxo_pll4_map,
},
.freq_tbl = clk_tbl_aif_mi2s,
.clkr = {
.enable_reg = 0x48,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "mi2s_osr_src",
.parent_data = lcc_pxo_pll4,
.num_parents = ARRAY_SIZE(lcc_pxo_pll4),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
},
};
static struct clk_branch mi2s_osr_clk = {
.halt_reg = 0x50,
.halt_bit = 1,
.halt_check = BRANCH_HALT_ENABLE,
.clkr = {
.enable_reg = 0x48,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "mi2s_osr_clk",
.parent_hws = (const struct clk_hw*[]) {
&mi2s_osr_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_regmap_div mi2s_div_clk = {
.reg = 0x48,
.shift = 10,
.width = 4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "mi2s_div_clk",
.parent_hws = (const struct clk_hw*[]) {
&mi2s_osr_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
},
};
static struct clk_branch mi2s_bit_div_clk = {
.halt_reg = 0x50,
.halt_bit = 0,
.halt_check = BRANCH_HALT_ENABLE,
.clkr = {
.enable_reg = 0x48,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "mi2s_bit_div_clk",
.parent_hws = (const struct clk_hw*[]) {
&mi2s_div_clk.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = {
{ .hw = &mi2s_bit_div_clk.clkr.hw, },
{ .fw_name = "mi2s_codec", .name = "mi2s_codec_clk" },
};
static struct clk_regmap_mux mi2s_bit_clk = {
.reg = 0x48,
.shift = 14,
.width = 1,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "mi2s_bit_clk",
.parent_data = lcc_mi2s_bit_div_codec_clk,
.num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk),
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct freq_tbl clk_tbl_pcm[] = {
{ 64000, P_PLL4, 4, 1, 1536 },
{ 128000, P_PLL4, 4, 1, 768 },
{ 256000, P_PLL4, 4, 1, 384 },
{ 512000, P_PLL4, 4, 1, 192 },
{ 1024000, P_PLL4, 4, 1, 96 },
{ 2048000, P_PLL4, 4, 1, 48 },
{ },
};
static struct clk_rcg pcm_src = {
.ns_reg = 0x54,
.md_reg = 0x58,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 16,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = lcc_pxo_pll4_map,
},
.freq_tbl = clk_tbl_pcm,
.clkr = {
.enable_reg = 0x54,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "pcm_src",
.parent_data = lcc_pxo_pll4,
.num_parents = ARRAY_SIZE(lcc_pxo_pll4),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
},
};
static struct clk_branch pcm_clk_out = {
.halt_reg = 0x5c,
.halt_bit = 0,
.halt_check = BRANCH_HALT_ENABLE,
.clkr = {
.enable_reg = 0x54,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "pcm_clk_out",
.parent_hws = (const struct clk_hw*[]) {
&pcm_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = {
{ .hw = &pcm_clk_out.clkr.hw, },
{ .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" },
};
static struct clk_regmap_mux pcm_clk = {
.reg = 0x54,
.shift = 10,
.width = 1,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "pcm_clk",
.parent_data = lcc_pcm_clk_out_codec_clk,
.num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk),
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct freq_tbl clk_tbl_aif_osr[] = {
{ 2822400, P_PLL4, 1, 147, 20480 },
{ 4096000, P_PLL4, 1, 1, 96 },
{ 5644800, P_PLL4, 1, 147, 10240 },
{ 6144000, P_PLL4, 1, 1, 64 },
{ 11289600, P_PLL4, 1, 147, 5120 },
{ 12288000, P_PLL4, 1, 1, 32 },
{ 22579200, P_PLL4, 1, 147, 2560 },
{ 24576000, P_PLL4, 1, 1, 16 },
{ },
};
static struct clk_rcg spdif_src = {
.ns_reg = 0xcc,
.md_reg = 0xd0,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 16,
.m_val_shift = 16,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = lcc_pxo_pll4_map,
},
.freq_tbl = clk_tbl_aif_osr,
.clkr = {
.enable_reg = 0xcc,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "spdif_src",
.parent_data = lcc_pxo_pll4,
.num_parents = ARRAY_SIZE(lcc_pxo_pll4),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
},
};
static struct clk_branch spdif_clk = {
.halt_reg = 0xd4,
.halt_bit = 1,
.halt_check = BRANCH_HALT_ENABLE,
.clkr = {
.enable_reg = 0xcc,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "spdif_clk",
.parent_hws = (const struct clk_hw*[]) {
&spdif_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct freq_tbl clk_tbl_ahbix[] = {
{ 131072000, P_PLL4, 1, 1, 3 },
{ },
};
static struct clk_rcg ahbix_clk = {
.ns_reg = 0x38,
.md_reg = 0x3c,
.mn = {
.mnctr_en_bit = 8,
.mnctr_reset_bit = 7,
.mnctr_mode_shift = 5,
.n_val_shift = 24,
.m_val_shift = 8,
.width = 8,
},
.p = {
.pre_div_shift = 3,
.pre_div_width = 2,
},
.s = {
.src_sel_shift = 0,
.parent_map = lcc_pxo_pll4_map,
},
.freq_tbl = clk_tbl_ahbix,
.clkr = {
.enable_reg = 0x38,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "ahbix",
.parent_data = lcc_pxo_pll4,
.num_parents = ARRAY_SIZE(lcc_pxo_pll4),
.ops = &clk_rcg_lcc_ops,
},
},
};
static struct clk_regmap *lcc_ipq806x_clks[] = {
[PLL4] = &pll4.clkr,
[MI2S_OSR_SRC] = &mi2s_osr_src.clkr,
[MI2S_OSR_CLK] = &mi2s_osr_clk.clkr,
[MI2S_DIV_CLK] = &mi2s_div_clk.clkr,
[MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr,
[MI2S_BIT_CLK] = &mi2s_bit_clk.clkr,
[PCM_SRC] = &pcm_src.clkr,
[PCM_CLK_OUT] = &pcm_clk_out.clkr,
[PCM_CLK] = &pcm_clk.clkr,
[SPDIF_SRC] = &spdif_src.clkr,
[SPDIF_CLK] = &spdif_clk.clkr,
[AHBIX_CLK] = &ahbix_clk.clkr,
};
static const struct qcom_reset_map lcc_ipq806x_resets[] = {
[LCC_PCM_RESET] = { 0x54, 13 },
};
static const struct regmap_config lcc_ipq806x_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xfc,
.fast_io = true,
};
static const struct qcom_cc_desc lcc_ipq806x_desc = {
.config = &lcc_ipq806x_regmap_config,
.clks = lcc_ipq806x_clks,
.num_clks = ARRAY_SIZE(lcc_ipq806x_clks),
.resets = lcc_ipq806x_resets,
.num_resets = ARRAY_SIZE(lcc_ipq806x_resets),
};
static const struct of_device_id lcc_ipq806x_match_table[] = {
{ .compatible = "qcom,lcc-ipq8064" },
{ }
};
MODULE_DEVICE_TABLE(of, lcc_ipq806x_match_table);
static int lcc_ipq806x_probe(struct platform_device *pdev)
{
u32 val;
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &lcc_ipq806x_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Configure the rate of PLL4 if the bootloader hasn't already */
regmap_read(regmap, 0x0, &val);
if (!val)
clk_pll_configure_sr(&pll4, regmap, &pll4_config, true);
/* Enable PLL4 source on the LPASS Primary PLL Mux */
regmap_write(regmap, 0xc4, 0x1);
return qcom_cc_really_probe(pdev, &lcc_ipq806x_desc, regmap);
}
static struct platform_driver lcc_ipq806x_driver = {
.probe = lcc_ipq806x_probe,
.driver = {
.name = "lcc-ipq806x",
.of_match_table = lcc_ipq806x_match_table,
},
};
module_platform_driver(lcc_ipq806x_driver);
MODULE_DESCRIPTION("QCOM LCC IPQ806x Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:lcc-ipq806x");
| linux-master | drivers/clk/qcom/lcc-ipq806x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "reset.h"
#include "gdsc.h"
/* Need to match the order of clocks in DT binding */
enum {
DT_BI_TCXO,
DT_GCC_GPU_GPLL0_CLK_SRC,
DT_GCC_GPU_GPLL0_DIV_CLK_SRC,
};
enum {
P_BI_TCXO,
P_GCC_GPU_GPLL0_CLK_SRC,
P_GCC_GPU_GPLL0_DIV_CLK_SRC,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL1_OUT_MAIN,
};
static const struct clk_parent_data parent_data_tcxo = { .index = DT_BI_TCXO };
static const struct pll_vco lucid_5lpe_vco[] = {
{ 249600000, 1800000000, 0 },
};
static struct alpha_pll_config gpu_cc_pll0_config = {
.l = 0x1c,
.alpha = 0xa555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x2a9a699c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000000,
.test_ctl_hi1_val = 0x01800000,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_5lpe_vco,
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_pll0",
.parent_data = &parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_5lpe_ops,
},
},
};
static struct alpha_pll_config gpu_cc_pll1_config = {
.l = 0x1A,
.alpha = 0xaaa,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x2a9a699c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000000,
.test_ctl_hi1_val = 0x01800000,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x100,
.vco_table = lucid_5lpe_vco,
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_5lpe_ops,
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GCC_GPU_GPLL0_CLK_SRC, 5 },
{ P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GCC_GPU_GPLL0_CLK_SRC, 5 },
{ P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_GCC_GPU_GPLL0_DIV_CLK_SRC, 1.5, 0, 0),
F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x1120,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
F(200000000, P_GCC_GPU_GPLL0_CLK_SRC, 3, 0, 0),
F(300000000, P_GCC_GPU_GPLL0_CLK_SRC, 2, 0, 0),
F(400000000, P_GCC_GPU_GPLL0_CLK_SRC, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_hub_clk_src = {
.cmd_rcgr = 0x117c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_1,
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hub_clk_src",
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
.reg = 0x11c0,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_ahb_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
.reg = 0x11bc,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_cx_int_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x1078,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1078,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x107c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x107c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_crc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x1098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1098,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
.halt_reg = 0x108c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x108c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cx_snoc_dvm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_aon_clk = {
.halt_reg = 0x1004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cxo_aon_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gmu_clk = {
.halt_reg = 0x1064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_gx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
.halt_reg = 0x5000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x5000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hub_aon_clk = {
.halt_reg = 0x1178,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1178,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hub_aon_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_hub_cx_int_clk = {
.halt_reg = 0x1204,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1204,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hub_cx_int_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_sleep_clk = {
.halt_reg = 0x1090,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1090,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *gpu_cc_sc8280xp_clocks[] = {
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
[GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
[GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
};
static struct gdsc cx_gdsc = {
.gdscr = 0x106c,
.gds_hw_ctrl = 0x1540,
.pd = {
.name = "cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc gx_gdsc = {
.gdscr = 0x100c,
.clamp_io_ctrl = 0x1508,
.pd = {
.name = "gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | RETAIN_FF_ENABLE,
};
static struct gdsc *gpu_cc_sc8280xp_gdscs[] = {
[GPU_CC_CX_GDSC] = &cx_gdsc,
[GPU_CC_GX_GDSC] = &gx_gdsc,
};
static const struct regmap_config gpu_cc_sc8280xp_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x8030,
.fast_io = true,
};
static struct qcom_cc_desc gpu_cc_sc8280xp_desc = {
.config = &gpu_cc_sc8280xp_regmap_config,
.clks = gpu_cc_sc8280xp_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sc8280xp_clocks),
.gdscs = gpu_cc_sc8280xp_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sc8280xp_gdscs),
};
static int gpu_cc_sc8280xp_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
regmap = qcom_cc_map(pdev, &gpu_cc_sc8280xp_desc);
if (IS_ERR(regmap)) {
pm_runtime_put(&pdev->dev);
return PTR_ERR(regmap);
}
clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
/*
* Keep the clocks always-ON
* GPU_CC_CB_CLK, GPU_CC_CXO_CLK
*/
regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x109c, BIT(0), BIT(0));
ret = qcom_cc_really_probe(pdev, &gpu_cc_sc8280xp_desc, regmap);
pm_runtime_put(&pdev->dev);
return ret;
}
static const struct of_device_id gpu_cc_sc8280xp_match_table[] = {
{ .compatible = "qcom,sc8280xp-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sc8280xp_match_table);
static struct platform_driver gpu_cc_sc8280xp_driver = {
.probe = gpu_cc_sc8280xp_probe,
.driver = {
.name = "gpu_cc-sc8280xp",
.of_match_table = gpu_cc_sc8280xp_match_table,
},
};
module_platform_driver(gpu_cc_sc8280xp_driver);
MODULE_DESCRIPTION("Qualcomm SC8280XP GPU clock controller");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/gpucc-sc8280xp.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_GPLL0_OUT_EVEN,
P_GPLL0_OUT_MAIN,
P_GPLL1_OUT_MAIN,
P_GPLL4_OUT_MAIN,
P_GPLL6_OUT_MAIN,
P_GPLL7_OUT_MAIN,
P_SLEEP_CLK,
};
static struct clk_alpha_pll gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
.name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll0_out_even = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_gpll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_even",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_fixed_factor gcc_pll0_main_div_cdiv = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "gcc_pll0_main_div_cdiv",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_alpha_pll gpll1 = {
.offset = 0x01000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gpll1",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
.name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
},
};
static struct clk_alpha_pll gpll4 = {
.offset = 0x76000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
.name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
},
};
static struct clk_alpha_pll gpll6 = {
.offset = 0x13000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gpll6",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
.name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
},
};
static struct clk_alpha_pll gpll7 = {
.offset = 0x27000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gpll7",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
.name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct clk_parent_data gcc_parent_data_0_ao[] = {
{ .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL6_OUT_MAIN, 2 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL1_OUT_MAIN, 4 },
{ P_GPLL4_OUT_MAIN, 5 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll1.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_4[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL7_OUT_MAIN, 3 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll7.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_6[] = {
{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
.cmd_rcgr = 0x48014,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk_src",
.parent_data = gcc_parent_data_0_ao,
.num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x64004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x65004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x66004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x33010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_qspi_core_clk_src = {
.cmd_rcgr = 0x4b00c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_qspi_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_core_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
F(51200000, P_GPLL6_OUT_MAIN, 7.5, 0, 0),
F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x17034,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.cmd_rcgr = 0x17164,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.cmd_rcgr = 0x17294,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.cmd_rcgr = 0x173c4,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.cmd_rcgr = 0x174f4,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.cmd_rcgr = 0x17624,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.cmd_rcgr = 0x18018,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.cmd_rcgr = 0x18148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.cmd_rcgr = 0x18278,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.cmd_rcgr = 0x183a8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.cmd_rcgr = 0x184d8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.cmd_rcgr = 0x18608,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
F(144000, P_BI_TCXO, 16, 3, 25),
F(400000, P_BI_TCXO, 12, 1, 4),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.cmd_rcgr = 0x12028,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x12010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.cmd_rcgr = 0x1400c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.flags = CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.cmd_rcgr = 0x77020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.cmd_rcgr = 0x77048,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
.cmd_rcgr = 0x77098,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.cmd_rcgr = 0x77060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.cmd_rcgr = 0xf01c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.cmd_rcgr = 0xf034,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.cmd_rcgr = 0xf060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = {
F(4800000, P_BI_TCXO, 4, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sec_ctrl_clk_src = {
.cmd_rcgr = 0x3d030,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_sec_ctrl_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sec_ctrl_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
.halt_reg = 0x82024,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x82024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x82024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
.halt_reg = 0x8201c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8201c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x38004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x38004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_hf_axi_clk = {
.halt_reg = 0xb020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_throttle_hf_axi_clk = {
.halt_reg = 0xb080,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xb080,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camera_throttle_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_ahb_clk = {
.halt_reg = 0x4100c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x4100c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_axi_clk = {
.halt_reg = 0x41008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_clk = {
.halt_reg = 0x41004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.halt_reg = 0x502c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x502c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* For CPUSS functionality the AHB clock needs to be left enabled */
static struct clk_branch gcc_cpuss_ahb_clk = {
.halt_reg = 0x48000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_cpuss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cpuss_rbcpr_clk = {
.halt_reg = 0x48008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x48008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_rbcpr_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ddrss_gpu_axi_clk = {
.halt_reg = 0x4452c,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x4452c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ddrss_gpu_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_gpll0_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_disp_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_pll0_main_div_cdiv.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_hf_axi_clk = {
.halt_reg = 0xb024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_throttle_hf_axi_clk = {
.halt_reg = 0xb084,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xb084,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_throttle_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x64000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x64000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x65000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x65000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x66000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x66000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_pll0_main_div_cdiv.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
.halt_reg = 0x7100c,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x7100c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_memnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
.halt_reg = 0x71018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x71018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_snoc_dvm_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_axi_clk = {
.halt_reg = 0x4d008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_bwmon_axi_clk = {
.halt_reg = 0x73008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x73008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_bwmon_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk = {
.halt_reg = 0x73018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x73018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_bwmon_dma_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk = {
.halt_reg = 0x7301c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7301c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_bwmon_dsp_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_cfg_ahb_clk = {
.halt_reg = 0x4d004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x4d004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4d004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_dma_clk = {
.halt_reg = 0x4d1a0,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x4d1a0,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4d1a0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_dma_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_gpll0_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_gpll0_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_npu_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_npu_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_pll0_main_div_cdiv.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x3300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x33004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x33004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x33004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x33008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x33008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x34004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x34004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
.halt_reg = 0x4b004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x4b004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x4b004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_cnoc_periph_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qspi_core_clk = {
.halt_reg = 0x4b008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4b008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qspi_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
.halt_reg = 0x17014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_clk = {
.halt_reg = 0x1700c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.halt_reg = 0x17030,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.halt_reg = 0x17160,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.halt_reg = 0x17290,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.halt_reg = 0x173c0,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.halt_reg = 0x174f0,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.halt_reg = 0x17620,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
.halt_reg = 0x18004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_clk = {
.halt_reg = 0x18008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.halt_reg = 0x18014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.halt_reg = 0x18144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.halt_reg = 0x18274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.halt_reg = 0x183a4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.halt_reg = 0x184d4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.halt_reg = 0x18604,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
.halt_reg = 0x17008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x17008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
.halt_reg = 0x1800c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
.halt_reg = 0x18010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x18010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap_1_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x12008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x1200c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0x12040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x12040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc1_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x14008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x14004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
/* For CPUSS functionality the SYS NOC clock needs to be left enabled */
static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
.halt_reg = 0x4144,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_cpuss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_cpuss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_mem_clkref_clk = {
.halt_reg = 0x8c000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_mem_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x77014,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_clk = {
.halt_reg = 0x77038,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77038,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.halt_reg = 0x77090,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77090,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.halt_reg = 0x77094,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x77094,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77094,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.halt_reg = 0x7701c,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x7701c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
.halt_reg = 0x77018,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x77018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.halt_reg = 0x7708c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x7708c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7708c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_master_clk = {
.halt_reg = 0xf010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0xf018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_sleep_clk = {
.halt_reg = 0xf014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_clkref_clk = {
.halt_reg = 0x8c010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8c010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
.halt_reg = 0xf050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.halt_reg = 0xf054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_reg = 0xf058,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0xf058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
.halt_reg = 0x6a004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x6a004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x6a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_phy_cfg_ahb2phy_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi_clk = {
.halt_reg = 0xb01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_gpll0_div_clk_src = {
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_gpll0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gcc_pll0_main_div_cdiv.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_throttle_axi_clk = {
.halt_reg = 0xb07c,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0xb07c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb07c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_throttle_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_cfg_ahb_clk = {
.halt_reg = 0x8a000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8a000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_mfab_axis_clk = {
.halt_reg = 0x8a004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x8a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_mfab_axis_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_nav_axi_clk = {
.halt_reg = 0x8a00c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x8a00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_nav_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_snoc_axi_clk = {
.halt_reg = 0x8a150,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8a150,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_snoc_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
.halt_reg = 0x8a154,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8a154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_q6_memnoc_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_lpass_cfg_noc_sway_clk = {
.halt_reg = 0x47018,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x47018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_lpass_cfg_noc_sway_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc ufs_phy_gdsc = {
.gdscr = 0x77004,
.pd = {
.name = "ufs_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc usb30_prim_gdsc = {
.gdscr = 0x0f004,
.pd = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_RET_ON,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
.gdscr = 0x7d040,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
.gdscr = 0x7d044,
.pd = {
.name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc *gcc_sc7180_gdscs[] = {
[UFS_PHY_GDSC] = &ufs_phy_gdsc,
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
[HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] =
&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
};
static struct clk_hw *gcc_sc7180_hws[] = {
[GCC_GPLL0_MAIN_DIV_CDIV] = &gcc_pll0_main_div_cdiv.hw,
};
static struct clk_regmap *gcc_sc7180_clocks[] = {
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
[GCC_CAMERA_THROTTLE_HF_AXI_CLK] = &gcc_camera_throttle_hf_axi_clk.clkr,
[GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
[GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
[GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
[GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
[GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
[GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
[GCC_DISP_THROTTLE_HF_AXI_CLK] = &gcc_disp_throttle_hf_axi_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
[GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr,
[GCC_NPU_BWMON_DMA_CFG_AHB_CLK] = &gcc_npu_bwmon_dma_cfg_ahb_clk.clkr,
[GCC_NPU_BWMON_DSP_CFG_AHB_CLK] = &gcc_npu_bwmon_dsp_cfg_ahb_clk.clkr,
[GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
[GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr,
[GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
[GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
[GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
[GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
[GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
&gcc_ufs_phy_unipro_core_clk_src.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
&gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
[GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
[GCC_VIDEO_GPLL0_DIV_CLK_SRC] = &gcc_video_gpll0_div_clk_src.clkr,
[GCC_VIDEO_THROTTLE_AXI_CLK] = &gcc_video_throttle_axi_clk.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
[GPLL6] = &gpll6.clkr,
[GPLL7] = &gpll7.clkr,
[GPLL4] = &gpll4.clkr,
[GPLL1] = &gpll1.clkr,
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
[GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
[GCC_MSS_NAV_AXI_CLK] = &gcc_mss_nav_axi_clk.clkr,
[GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
[GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr,
[GCC_LPASS_CFG_NOC_SWAY_CLK] = &gcc_lpass_cfg_noc_sway_clk.clkr,
};
static const struct qcom_reset_map gcc_sc7180_resets[] = {
[GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x26004 },
[GCC_UFS_PHY_BCR] = { 0x77000 },
[GCC_USB30_PRIM_BCR] = { 0xf000 },
[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
};
static struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
};
static const struct regmap_config gcc_sc7180_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x18208c,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_sc7180_desc = {
.config = &gcc_sc7180_regmap_config,
.clk_hws = gcc_sc7180_hws,
.num_clk_hws = ARRAY_SIZE(gcc_sc7180_hws),
.clks = gcc_sc7180_clocks,
.num_clks = ARRAY_SIZE(gcc_sc7180_clocks),
.resets = gcc_sc7180_resets,
.num_resets = ARRAY_SIZE(gcc_sc7180_resets),
.gdscs = gcc_sc7180_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sc7180_gdscs),
};
static const struct of_device_id gcc_sc7180_match_table[] = {
{ .compatible = "qcom,gcc-sc7180" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_sc7180_match_table);
static int gcc_sc7180_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sc7180_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/*
* Disable the GPLL0 active input to MM blocks, NPU
* and GPU via MISC registers.
*/
regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
/*
* Keep the clocks always-ON
* GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK,
* GCC_DISP_AHB_CLK, GCC_GPU_CFG_AHB_CLK
*/
regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
return qcom_cc_really_probe(pdev, &gcc_sc7180_desc, regmap);
}
static struct platform_driver gcc_sc7180_driver = {
.probe = gcc_sc7180_probe,
.driver = {
.name = "gcc-sc7180",
.of_match_table = gcc_sc7180_match_table,
},
};
static int __init gcc_sc7180_init(void)
{
return platform_driver_register(&gcc_sc7180_driver);
}
core_initcall(gcc_sc7180_init);
static void __exit gcc_sc7180_exit(void)
{
platform_driver_unregister(&gcc_sc7180_driver);
}
module_exit(gcc_sc7180_exit);
MODULE_DESCRIPTION("QTI GCC SC7180 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gcc-sc7180.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022, Linaro Ltd.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
/* Need to match the order of clocks in DT binding */
enum {
DT_IFACE,
DT_BI_TCXO,
DT_SLEEP_CLK,
DT_DP0_PHY_PLL_LINK_CLK,
DT_DP0_PHY_PLL_VCO_DIV_CLK,
DT_DP1_PHY_PLL_LINK_CLK,
DT_DP1_PHY_PLL_VCO_DIV_CLK,
DT_DP2_PHY_PLL_LINK_CLK,
DT_DP2_PHY_PLL_VCO_DIV_CLK,
DT_DP3_PHY_PLL_LINK_CLK,
DT_DP3_PHY_PLL_VCO_DIV_CLK,
DT_DSI0_PHY_PLL_OUT_BYTECLK,
DT_DSI0_PHY_PLL_OUT_DSICLK,
DT_DSI1_PHY_PLL_OUT_BYTECLK,
DT_DSI1_PHY_PLL_OUT_DSICLK,
};
enum {
P_BI_TCXO,
P_DP0_PHY_PLL_LINK_CLK,
P_DP0_PHY_PLL_VCO_DIV_CLK,
P_DP1_PHY_PLL_LINK_CLK,
P_DP1_PHY_PLL_VCO_DIV_CLK,
P_DP2_PHY_PLL_LINK_CLK,
P_DP2_PHY_PLL_VCO_DIV_CLK,
P_DP3_PHY_PLL_LINK_CLK,
P_DP3_PHY_PLL_VCO_DIV_CLK,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
P_DSI1_PHY_PLL_OUT_BYTECLK,
P_DSI1_PHY_PLL_OUT_DSICLK,
P_DISPn_CC_PLL0_OUT_MAIN,
P_DISPn_CC_PLL1_OUT_EVEN,
P_DISPn_CC_PLL1_OUT_MAIN,
P_DISPn_CC_PLL2_OUT_MAIN,
P_SLEEP_CLK,
};
static const struct clk_parent_data parent_data_tcxo = { .index = DT_BI_TCXO };
static const struct pll_vco lucid_5lpe_vco[] = {
{ 249600000, 1800000000, 0 },
};
static const struct alpha_pll_config disp_cc_pll0_config = {
.l = 0x4e,
.alpha = 0x2000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x2a9a699c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000000,
.test_ctl_hi1_val = 0x01800000,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll disp0_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_5lpe_vco,
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_pll0",
.parent_data = &parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_5lpe_ops,
},
},
};
static struct clk_alpha_pll disp1_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_5lpe_vco,
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_pll0",
.parent_data = &parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_5lpe_ops,
},
},
};
static const struct alpha_pll_config disp_cc_pll1_config = {
.l = 0x1f,
.alpha = 0x4000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x2a9a699c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000000,
.test_ctl_hi1_val = 0x01800000,
.user_ctl_val = 0x00000100,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll disp0_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_5lpe_vco,
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_pll1",
.parent_data = &parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_5lpe_ops,
},
},
};
static struct clk_alpha_pll disp1_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_5lpe_vco,
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_pll1",
.parent_data = &parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_5lpe_ops,
},
},
};
static const struct clk_div_table post_div_table_disp_cc_pll1_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv disp0_cc_pll1_out_even = {
.offset = 0x1000,
.post_div_shift = 8,
.post_div_table = post_div_table_disp_cc_pll1_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll1_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_pll1_out_even",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_pll1.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops,
},
};
static struct clk_alpha_pll_postdiv disp1_cc_pll1_out_even = {
.offset = 0x1000,
.post_div_shift = 8,
.post_div_table = post_div_table_disp_cc_pll1_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll1_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_pll1_out_even",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_pll1.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops,
},
};
static const struct alpha_pll_config disp_cc_pll2_config = {
.l = 0x46,
.alpha = 0x5000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x2a9a699c,
.test_ctl_val = 0x00000000,
.test_ctl_hi_val = 0x00000000,
.test_ctl_hi1_val = 0x01800000,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll disp0_cc_pll2 = {
.offset = 0x9000,
.vco_table = lucid_5lpe_vco,
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_pll2",
.parent_data = &parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_5lpe_ops,
},
},
};
static struct clk_alpha_pll disp1_cc_pll2 = {
.offset = 0x9000,
.vco_table = lucid_5lpe_vco,
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_pll2",
.parent_data = &parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_5lpe_ops,
},
},
};
static const struct parent_map disp_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_DP0_PHY_PLL_LINK_CLK, 1 },
{ P_DP1_PHY_PLL_LINK_CLK, 2 },
{ P_DP2_PHY_PLL_LINK_CLK, 3 },
{ P_DP3_PHY_PLL_LINK_CLK, 4 },
{ P_DISPn_CC_PLL2_OUT_MAIN, 5 },
};
static const struct clk_parent_data disp0_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DP0_PHY_PLL_LINK_CLK },
{ .index = DT_DP1_PHY_PLL_LINK_CLK },
{ .index = DT_DP2_PHY_PLL_LINK_CLK },
{ .index = DT_DP3_PHY_PLL_LINK_CLK },
{ .hw = &disp0_cc_pll2.clkr.hw },
};
static const struct clk_parent_data disp1_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DP0_PHY_PLL_LINK_CLK },
{ .index = DT_DP1_PHY_PLL_LINK_CLK },
{ .index = DT_DP2_PHY_PLL_LINK_CLK },
{ .index = DT_DP3_PHY_PLL_LINK_CLK },
{ .hw = &disp1_cc_pll2.clkr.hw },
};
static const struct parent_map disp_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_DP0_PHY_PLL_LINK_CLK, 1 },
{ P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },
{ P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
{ P_DISPn_CC_PLL2_OUT_MAIN, 5 },
{ P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
};
static const struct clk_parent_data disp0_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DP0_PHY_PLL_LINK_CLK },
{ .index = DT_DP0_PHY_PLL_VCO_DIV_CLK },
{ .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
{ .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
{ .hw = &disp0_cc_pll2.clkr.hw },
{ .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
};
static const struct clk_parent_data disp1_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DP0_PHY_PLL_LINK_CLK },
{ .index = DT_DP0_PHY_PLL_VCO_DIV_CLK },
{ .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
{ .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
{ .hw = &disp1_cc_pll2.clkr.hw },
{ .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
};
static const struct parent_map disp_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
};
static const struct parent_map disp_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
{ P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
{ .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
{ .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
};
static const struct parent_map disp_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
{ .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
};
static const struct parent_map disp_cc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_DISPn_CC_PLL0_OUT_MAIN, 1 },
{ P_DISPn_CC_PLL1_OUT_MAIN, 4 },
{ P_DISPn_CC_PLL2_OUT_MAIN, 5 },
{ P_DISPn_CC_PLL1_OUT_EVEN, 6 },
};
static const struct clk_parent_data disp0_cc_parent_data_5[] = {
{ .index = DT_BI_TCXO },
{ .hw = &disp0_cc_pll0.clkr.hw },
{ .hw = &disp0_cc_pll1.clkr.hw },
{ .hw = &disp0_cc_pll2.clkr.hw },
{ .hw = &disp0_cc_pll1_out_even.clkr.hw },
};
static const struct clk_parent_data disp1_cc_parent_data_5[] = {
{ .index = DT_BI_TCXO },
{ .hw = &disp1_cc_pll0.clkr.hw },
{ .hw = &disp1_cc_pll1.clkr.hw },
{ .hw = &disp1_cc_pll2.clkr.hw },
{ .hw = &disp1_cc_pll1_out_even.clkr.hw },
};
static const struct parent_map disp_cc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_DISPn_CC_PLL1_OUT_MAIN, 4 },
{ P_DISPn_CC_PLL1_OUT_EVEN, 6 },
};
static const struct clk_parent_data disp0_cc_parent_data_6[] = {
{ .index = DT_BI_TCXO },
{ .hw = &disp0_cc_pll1.clkr.hw },
{ .hw = &disp0_cc_pll1_out_even.clkr.hw },
};
static const struct clk_parent_data disp1_cc_parent_data_6[] = {
{ .index = DT_BI_TCXO },
{ .hw = &disp1_cc_pll1.clkr.hw },
{ .hw = &disp1_cc_pll1_out_even.clkr.hw },
};
static const struct parent_map disp_cc_parent_map_7[] = {
{ P_SLEEP_CLK, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_7[] = {
{ .index = DT_SLEEP_CLK },
};
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_DISPn_CC_PLL1_OUT_EVEN, 8, 0, 0),
F(75000000, P_DISPn_CC_PLL1_OUT_MAIN, 8, 0, 0),
{ }
};
static struct clk_rcg2 disp0_cc_mdss_ahb_clk_src = {
.cmd_rcgr = 0x2364,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_6,
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_ahb_clk_src",
.parent_data = disp0_cc_parent_data_6,
.num_parents = ARRAY_SIZE(disp0_cc_parent_data_6),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_ahb_clk_src = {
.cmd_rcgr = 0x2364,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_6,
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_ahb_clk_src",
.parent_data = disp1_cc_parent_data_6,
.num_parents = ARRAY_SIZE(disp1_cc_parent_data_6),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp0_cc_mdss_byte0_clk_src = {
.cmd_rcgr = 0x213c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_byte0_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_byte0_clk_src = {
.cmd_rcgr = 0x213c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_byte0_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp0_cc_mdss_byte1_clk_src = {
.cmd_rcgr = 0x2158,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_byte1_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_byte1_clk_src = {
.cmd_rcgr = 0x2158,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_byte1_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp0_cc_mdss_dptx0_aux_clk_src = {
.cmd_rcgr = 0x2238,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx0_aux_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_dptx0_aux_clk_src = {
.cmd_rcgr = 0x2238,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx0_aux_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp0_cc_mdss_dptx0_link_clk_src = {
.cmd_rcgr = 0x21a4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx0_link_clk_src",
.parent_data = disp0_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp0_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_dptx0_link_clk_src = {
.cmd_rcgr = 0x21a4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx0_link_clk_src",
.parent_data = disp1_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp1_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp0_cc_mdss_dptx0_pixel0_clk_src = {
.cmd_rcgr = 0x21d8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx0_pixel0_clk_src",
.parent_data = disp0_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp0_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_dptx0_pixel0_clk_src = {
.cmd_rcgr = 0x21d8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx0_pixel0_clk_src",
.parent_data = disp1_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp1_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp0_cc_mdss_dptx0_pixel1_clk_src = {
.cmd_rcgr = 0x21f0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx0_pixel1_clk_src",
.parent_data = disp0_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp0_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_dptx0_pixel1_clk_src = {
.cmd_rcgr = 0x21f0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx0_pixel1_clk_src",
.parent_data = disp1_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp1_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp0_cc_mdss_dptx1_aux_clk_src = {
.cmd_rcgr = 0x22d0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx1_aux_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_dptx1_aux_clk_src = {
.cmd_rcgr = 0x22d0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx1_aux_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp0_cc_mdss_dptx1_link_clk_src = {
.cmd_rcgr = 0x2268,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx1_link_clk_src",
.parent_data = disp0_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp0_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_dptx1_link_clk_src = {
.cmd_rcgr = 0x2268,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx1_link_clk_src",
.parent_data = disp1_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp1_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp0_cc_mdss_dptx1_pixel0_clk_src = {
.cmd_rcgr = 0x2250,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx1_pixel0_clk_src",
.parent_data = disp0_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp0_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_dptx1_pixel0_clk_src = {
.cmd_rcgr = 0x2250,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx1_pixel0_clk_src",
.parent_data = disp1_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp1_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp0_cc_mdss_dptx1_pixel1_clk_src = {
.cmd_rcgr = 0x2370,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx1_pixel1_clk_src",
.parent_data = disp0_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp0_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_dptx1_pixel1_clk_src = {
.cmd_rcgr = 0x2370,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx1_pixel1_clk_src",
.parent_data = disp1_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp1_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp0_cc_mdss_dptx2_aux_clk_src = {
.cmd_rcgr = 0x22e8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx2_aux_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_dptx2_aux_clk_src = {
.cmd_rcgr = 0x22e8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx2_aux_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp0_cc_mdss_dptx2_link_clk_src = {
.cmd_rcgr = 0x2284,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx2_link_clk_src",
.parent_data = disp0_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp0_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_dptx2_link_clk_src = {
.cmd_rcgr = 0x2284,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx2_link_clk_src",
.parent_data = disp1_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp1_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp0_cc_mdss_dptx2_pixel0_clk_src = {
.cmd_rcgr = 0x2208,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx2_pixel0_clk_src",
.parent_data = disp0_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp0_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_dptx2_pixel0_clk_src = {
.cmd_rcgr = 0x2208,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx2_pixel0_clk_src",
.parent_data = disp1_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp1_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp0_cc_mdss_dptx2_pixel1_clk_src = {
.cmd_rcgr = 0x2220,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx2_pixel1_clk_src",
.parent_data = disp0_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp0_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_dptx2_pixel1_clk_src = {
.cmd_rcgr = 0x2220,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx2_pixel1_clk_src",
.parent_data = disp1_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp1_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp0_cc_mdss_dptx3_aux_clk_src = {
.cmd_rcgr = 0x234c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx3_aux_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_dptx3_aux_clk_src = {
.cmd_rcgr = 0x234c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx3_aux_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp0_cc_mdss_dptx3_link_clk_src = {
.cmd_rcgr = 0x2318,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx3_link_clk_src",
.parent_data = disp0_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp0_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_dptx3_link_clk_src = {
.cmd_rcgr = 0x2318,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx3_link_clk_src",
.parent_data = disp1_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp1_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp0_cc_mdss_dptx3_pixel0_clk_src = {
.cmd_rcgr = 0x2300,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx3_pixel0_clk_src",
.parent_data = disp0_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp0_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_dptx3_pixel0_clk_src = {
.cmd_rcgr = 0x2300,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx3_pixel0_clk_src",
.parent_data = disp1_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp1_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp0_cc_mdss_esc0_clk_src = {
.cmd_rcgr = 0x2174,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_esc0_clk_src = {
.cmd_rcgr = 0x2174,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp0_cc_mdss_esc1_clk_src = {
.cmd_rcgr = 0x218c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_esc1_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_esc1_clk_src = {
.cmd_rcgr = 0x218c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_esc1_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(85714286, P_DISPn_CC_PLL1_OUT_MAIN, 7, 0, 0),
F(100000000, P_DISPn_CC_PLL1_OUT_MAIN, 6, 0, 0),
F(150000000, P_DISPn_CC_PLL1_OUT_MAIN, 4, 0, 0),
F(200000000, P_DISPn_CC_PLL1_OUT_MAIN, 3, 0, 0),
F(300000000, P_DISPn_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(375000000, P_DISPn_CC_PLL0_OUT_MAIN, 4, 0, 0),
F(500000000, P_DISPn_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(600000000, P_DISPn_CC_PLL1_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp0_cc_mdss_mdp_clk_src = {
.cmd_rcgr = 0x20f4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_mdp_clk_src",
.parent_data = disp0_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp0_cc_parent_data_5),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_mdp_clk_src = {
.cmd_rcgr = 0x20f4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_mdp_clk_src",
.parent_data = disp1_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp1_cc_parent_data_5),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp0_cc_mdss_pclk0_clk_src = {
.cmd_rcgr = 0x20c4,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_pclk0_clk_src = {
.cmd_rcgr = 0x20c4,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
};
static struct clk_rcg2 disp0_cc_mdss_pclk1_clk_src = {
.cmd_rcgr = 0x20dc,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_pclk1_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_pclk1_clk_src = {
.cmd_rcgr = 0x20dc,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_pclk1_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(200000000, P_DISPn_CC_PLL1_OUT_MAIN, 3, 0, 0),
F(300000000, P_DISPn_CC_PLL1_OUT_MAIN, 2, 0, 0),
F(375000000, P_DISPn_CC_PLL0_OUT_MAIN, 4, 0, 0),
F(500000000, P_DISPn_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(600000000, P_DISPn_CC_PLL1_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp0_cc_mdss_rot_clk_src = {
.cmd_rcgr = 0x210c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_rot_clk_src",
.parent_data = disp0_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp0_cc_parent_data_5),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_rot_clk_src = {
.cmd_rcgr = 0x210c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_rot_clk_src",
.parent_data = disp1_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp1_cc_parent_data_5),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp0_cc_mdss_vsync_clk_src = {
.cmd_rcgr = 0x2124,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp1_cc_mdss_vsync_clk_src = {
.cmd_rcgr = 0x2124,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
F(32000, P_SLEEP_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp0_cc_sleep_clk_src = {
.cmd_rcgr = 0x6060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_7,
.freq_tbl = ftbl_disp_cc_sleep_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_sleep_clk_src",
.parent_data = disp_cc_parent_data_7,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp1_cc_sleep_clk_src = {
.cmd_rcgr = 0x6060,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_7,
.freq_tbl = ftbl_disp_cc_sleep_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_sleep_clk_src",
.parent_data = disp_cc_parent_data_7,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div disp0_cc_mdss_byte0_div_clk_src = {
.reg = 0x2154,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_byte0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ops,
},
};
static struct clk_regmap_div disp1_cc_mdss_byte0_div_clk_src = {
.reg = 0x2154,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_byte0_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ops,
},
};
static struct clk_regmap_div disp0_cc_mdss_byte1_div_clk_src = {
.reg = 0x2170,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_byte1_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_byte1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ops,
},
};
static struct clk_regmap_div disp1_cc_mdss_byte1_div_clk_src = {
.reg = 0x2170,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_byte1_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_byte1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ops,
},
};
static struct clk_regmap_div disp0_cc_mdss_dptx0_link_div_clk_src = {
.reg = 0x21bc,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx0_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx0_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div disp1_cc_mdss_dptx0_link_div_clk_src = {
.reg = 0x21bc,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx0_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx0_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div disp0_cc_mdss_dptx1_link_div_clk_src = {
.reg = 0x2280,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx1_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx1_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div disp1_cc_mdss_dptx1_link_div_clk_src = {
.reg = 0x2280,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx1_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx1_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div disp0_cc_mdss_dptx2_link_div_clk_src = {
.reg = 0x229c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx2_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx2_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div disp1_cc_mdss_dptx2_link_div_clk_src = {
.reg = 0x229c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx2_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx2_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div disp0_cc_mdss_dptx3_link_div_clk_src = {
.reg = 0x2330,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx3_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx3_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div disp1_cc_mdss_dptx3_link_div_clk_src = {
.reg = 0x2330,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx3_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx3_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch disp0_cc_mdss_ahb1_clk = {
.halt_reg = 0x20c0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20c0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_ahb1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_ahb1_clk = {
.halt_reg = 0x20c0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20c0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_ahb1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_ahb_clk = {
.halt_reg = 0x20bc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20bc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_ahb_clk = {
.halt_reg = 0x20bc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20bc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_byte0_clk = {
.halt_reg = 0x2044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2044,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_byte0_clk = {
.halt_reg = 0x2044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2044,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_byte0_intf_clk = {
.halt_reg = 0x2048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_byte0_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_byte0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_byte0_intf_clk = {
.halt_reg = 0x2048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2048,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_byte0_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_byte0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_byte1_clk = {
.halt_reg = 0x204c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x204c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_byte1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_byte1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_byte1_clk = {
.halt_reg = 0x204c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x204c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_byte1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_byte1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_byte1_intf_clk = {
.halt_reg = 0x2050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2050,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_byte1_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_byte1_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_byte1_intf_clk = {
.halt_reg = 0x2050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2050,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_byte1_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_byte1_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_dptx0_aux_clk = {
.halt_reg = 0x206c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x206c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx0_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_dptx0_aux_clk = {
.halt_reg = 0x206c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x206c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx0_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_dptx0_link_clk = {
.halt_reg = 0x205c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x205c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx0_link_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx0_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_dptx0_link_clk = {
.halt_reg = 0x205c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x205c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx0_link_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx0_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_dptx0_link_intf_clk = {
.halt_reg = 0x2060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2060,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx0_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_dptx0_link_intf_clk = {
.halt_reg = 0x2060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2060,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx0_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_dptx0_pixel0_clk = {
.halt_reg = 0x2070,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2070,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx0_pixel0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_dptx0_pixel0_clk = {
.halt_reg = 0x2070,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2070,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx0_pixel0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_dptx0_pixel1_clk = {
.halt_reg = 0x2074,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2074,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx0_pixel1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_dptx0_pixel1_clk = {
.halt_reg = 0x2074,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2074,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx0_pixel1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_dptx0_usb_router_link_intf_clk = {
.halt_reg = 0x2064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx0_usb_router_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_dptx0_usb_router_link_intf_clk = {
.halt_reg = 0x2064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx0_usb_router_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_dptx1_aux_clk = {
.halt_reg = 0x20a0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20a0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx1_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx1_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_dptx1_aux_clk = {
.halt_reg = 0x20a0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20a0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx1_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx1_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_dptx1_link_clk = {
.halt_reg = 0x2084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2084,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx1_link_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx1_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_dptx1_link_clk = {
.halt_reg = 0x2084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2084,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx1_link_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx1_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_dptx1_link_intf_clk = {
.halt_reg = 0x2088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2088,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx1_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_dptx1_link_intf_clk = {
.halt_reg = 0x2088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2088,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx1_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_dptx1_pixel0_clk = {
.halt_reg = 0x2078,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2078,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx1_pixel0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_dptx1_pixel0_clk = {
.halt_reg = 0x2078,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2078,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx1_pixel0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_dptx1_pixel1_clk = {
.halt_reg = 0x236c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x236c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx1_pixel1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_dptx1_pixel1_clk = {
.halt_reg = 0x236c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x236c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx1_pixel1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_dptx1_usb_router_link_intf_clk = {
.halt_reg = 0x208c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x208c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx1_usb_router_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_dptx1_usb_router_link_intf_clk = {
.halt_reg = 0x208c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x208c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx1_usb_router_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_dptx2_aux_clk = {
.halt_reg = 0x20a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx2_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx2_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_dptx2_aux_clk = {
.halt_reg = 0x20a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx2_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx2_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_dptx2_link_clk = {
.halt_reg = 0x2090,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2090,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx2_link_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx2_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_dptx2_link_clk = {
.halt_reg = 0x2090,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2090,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx2_link_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx2_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_dptx2_link_intf_clk = {
.halt_reg = 0x2094,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2094,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx2_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx2_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_dptx2_link_intf_clk = {
.halt_reg = 0x2094,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2094,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx2_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx2_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_dptx2_pixel0_clk = {
.halt_reg = 0x207c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x207c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx2_pixel0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_dptx2_pixel0_clk = {
.halt_reg = 0x207c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x207c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx2_pixel0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_dptx2_pixel1_clk = {
.halt_reg = 0x2080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2080,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx2_pixel1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_dptx2_pixel1_clk = {
.halt_reg = 0x2080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2080,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx2_pixel1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_dptx3_aux_clk = {
.halt_reg = 0x20b8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20b8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx3_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx3_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_dptx3_aux_clk = {
.halt_reg = 0x20b8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20b8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx3_aux_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx3_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_dptx3_link_clk = {
.halt_reg = 0x20ac,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20ac,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx3_link_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx3_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_dptx3_link_clk = {
.halt_reg = 0x20ac,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20ac,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx3_link_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx3_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_dptx3_link_intf_clk = {
.halt_reg = 0x20b0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20b0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx3_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx3_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_dptx3_link_intf_clk = {
.halt_reg = 0x20b0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20b0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx3_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx3_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_dptx3_pixel0_clk = {
.halt_reg = 0x20a8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20a8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_dptx3_pixel0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_dptx3_pixel0_clk = {
.halt_reg = 0x20a8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20a8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_dptx3_pixel0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_esc0_clk = {
.halt_reg = 0x2054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2054,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_esc0_clk = {
.halt_reg = 0x2054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2054,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_esc1_clk = {
.halt_reg = 0x2058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2058,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_esc1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_esc1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_esc1_clk = {
.halt_reg = 0x2058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2058,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_esc1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_esc1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_mdp1_clk = {
.halt_reg = 0x2014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_mdp1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_mdp1_clk = {
.halt_reg = 0x2014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_mdp1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_mdp_clk = {
.halt_reg = 0x200c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x200c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_mdp_clk = {
.halt_reg = 0x200c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x200c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_mdp_lut1_clk = {
.halt_reg = 0x2034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_mdp_lut1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_mdp_lut1_clk = {
.halt_reg = 0x2034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_mdp_lut1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_mdp_lut_clk = {
.halt_reg = 0x202c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x202c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_mdp_lut_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_mdp_lut_clk = {
.halt_reg = 0x202c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x202c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_mdp_lut_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_non_gdsc_ahb_clk = {
.halt_reg = 0x4004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_non_gdsc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_non_gdsc_ahb_clk = {
.halt_reg = 0x4004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x4004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_non_gdsc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_pclk0_clk = {
.halt_reg = 0x2004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_pclk0_clk = {
.halt_reg = 0x2004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_pclk1_clk = {
.halt_reg = 0x2008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_pclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_pclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_pclk1_clk = {
.halt_reg = 0x2008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_pclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_pclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_rot1_clk = {
.halt_reg = 0x2024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_rot1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_rot_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_rot1_clk = {
.halt_reg = 0x2024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_rot1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_rot_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_rot_clk = {
.halt_reg = 0x201c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x201c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_rot_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_rot_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_rot_clk = {
.halt_reg = 0x201c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x201c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_rot_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_rot_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_rscc_ahb_clk = {
.halt_reg = 0x400c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x400c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_rscc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_rscc_ahb_clk = {
.halt_reg = 0x400c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x400c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_rscc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_rscc_vsync_clk = {
.halt_reg = 0x4008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_rscc_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_rscc_vsync_clk = {
.halt_reg = 0x4008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_rscc_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_vsync1_clk = {
.halt_reg = 0x2040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_vsync1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_vsync1_clk = {
.halt_reg = 0x2040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2040,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_vsync1_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_mdss_vsync_clk = {
.halt_reg = 0x203c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x203c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_mdss_vsync_clk = {
.halt_reg = 0x203c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x203c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp0_cc_sleep_clk = {
.halt_reg = 0x6078,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6078,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp0_cc_sleep_clk",
.parent_hws = (const struct clk_hw*[]){
&disp0_cc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp1_cc_sleep_clk = {
.halt_reg = 0x6078,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6078,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "disp1_cc_sleep_clk",
.parent_hws = (const struct clk_hw*[]){
&disp1_cc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *disp0_cc_sc8280xp_clocks[] = {
[DISP_CC_MDSS_AHB1_CLK] = &disp0_cc_mdss_ahb1_clk.clkr,
[DISP_CC_MDSS_AHB_CLK] = &disp0_cc_mdss_ahb_clk.clkr,
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp0_cc_mdss_ahb_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_CLK] = &disp0_cc_mdss_byte0_clk.clkr,
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp0_cc_mdss_byte0_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp0_cc_mdss_byte0_div_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp0_cc_mdss_byte0_intf_clk.clkr,
[DISP_CC_MDSS_BYTE1_CLK] = &disp0_cc_mdss_byte1_clk.clkr,
[DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp0_cc_mdss_byte1_clk_src.clkr,
[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp0_cc_mdss_byte1_div_clk_src.clkr,
[DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp0_cc_mdss_byte1_intf_clk.clkr,
[DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp0_cc_mdss_dptx0_aux_clk.clkr,
[DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp0_cc_mdss_dptx0_aux_clk_src.clkr,
[DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp0_cc_mdss_dptx0_link_clk.clkr,
[DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp0_cc_mdss_dptx0_link_clk_src.clkr,
[DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp0_cc_mdss_dptx0_link_div_clk_src.clkr,
[DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp0_cc_mdss_dptx0_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp0_cc_mdss_dptx0_pixel0_clk.clkr,
[DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp0_cc_mdss_dptx0_pixel0_clk_src.clkr,
[DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp0_cc_mdss_dptx0_pixel1_clk.clkr,
[DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp0_cc_mdss_dptx0_pixel1_clk_src.clkr,
[DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = &disp0_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp0_cc_mdss_dptx1_aux_clk.clkr,
[DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp0_cc_mdss_dptx1_aux_clk_src.clkr,
[DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp0_cc_mdss_dptx1_link_clk.clkr,
[DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp0_cc_mdss_dptx1_link_clk_src.clkr,
[DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp0_cc_mdss_dptx1_link_div_clk_src.clkr,
[DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp0_cc_mdss_dptx1_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp0_cc_mdss_dptx1_pixel0_clk.clkr,
[DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp0_cc_mdss_dptx1_pixel0_clk_src.clkr,
[DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp0_cc_mdss_dptx1_pixel1_clk.clkr,
[DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp0_cc_mdss_dptx1_pixel1_clk_src.clkr,
[DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = &disp0_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp0_cc_mdss_dptx2_aux_clk.clkr,
[DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp0_cc_mdss_dptx2_aux_clk_src.clkr,
[DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp0_cc_mdss_dptx2_link_clk.clkr,
[DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp0_cc_mdss_dptx2_link_clk_src.clkr,
[DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp0_cc_mdss_dptx2_link_div_clk_src.clkr,
[DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp0_cc_mdss_dptx2_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp0_cc_mdss_dptx2_pixel0_clk.clkr,
[DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp0_cc_mdss_dptx2_pixel0_clk_src.clkr,
[DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp0_cc_mdss_dptx2_pixel1_clk.clkr,
[DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp0_cc_mdss_dptx2_pixel1_clk_src.clkr,
[DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp0_cc_mdss_dptx3_aux_clk.clkr,
[DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp0_cc_mdss_dptx3_aux_clk_src.clkr,
[DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp0_cc_mdss_dptx3_link_clk.clkr,
[DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp0_cc_mdss_dptx3_link_clk_src.clkr,
[DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp0_cc_mdss_dptx3_link_div_clk_src.clkr,
[DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp0_cc_mdss_dptx3_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp0_cc_mdss_dptx3_pixel0_clk.clkr,
[DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp0_cc_mdss_dptx3_pixel0_clk_src.clkr,
[DISP_CC_MDSS_ESC0_CLK] = &disp0_cc_mdss_esc0_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp0_cc_mdss_esc0_clk_src.clkr,
[DISP_CC_MDSS_ESC1_CLK] = &disp0_cc_mdss_esc1_clk.clkr,
[DISP_CC_MDSS_ESC1_CLK_SRC] = &disp0_cc_mdss_esc1_clk_src.clkr,
[DISP_CC_MDSS_MDP1_CLK] = &disp0_cc_mdss_mdp1_clk.clkr,
[DISP_CC_MDSS_MDP_CLK] = &disp0_cc_mdss_mdp_clk.clkr,
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp0_cc_mdss_mdp_clk_src.clkr,
[DISP_CC_MDSS_MDP_LUT1_CLK] = &disp0_cc_mdss_mdp_lut1_clk.clkr,
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp0_cc_mdss_mdp_lut_clk.clkr,
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp0_cc_mdss_non_gdsc_ahb_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK] = &disp0_cc_mdss_pclk0_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp0_cc_mdss_pclk0_clk_src.clkr,
[DISP_CC_MDSS_PCLK1_CLK] = &disp0_cc_mdss_pclk1_clk.clkr,
[DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp0_cc_mdss_pclk1_clk_src.clkr,
[DISP_CC_MDSS_ROT1_CLK] = &disp0_cc_mdss_rot1_clk.clkr,
[DISP_CC_MDSS_ROT_CLK] = &disp0_cc_mdss_rot_clk.clkr,
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp0_cc_mdss_rot_clk_src.clkr,
[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp0_cc_mdss_rscc_ahb_clk.clkr,
[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp0_cc_mdss_rscc_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC1_CLK] = &disp0_cc_mdss_vsync1_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK] = &disp0_cc_mdss_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp0_cc_mdss_vsync_clk_src.clkr,
[DISP_CC_PLL0] = &disp0_cc_pll0.clkr,
[DISP_CC_PLL1] = &disp0_cc_pll1.clkr,
[DISP_CC_PLL1_OUT_EVEN] = &disp0_cc_pll1_out_even.clkr,
[DISP_CC_PLL2] = &disp0_cc_pll2.clkr,
[DISP_CC_SLEEP_CLK] = &disp0_cc_sleep_clk.clkr,
[DISP_CC_SLEEP_CLK_SRC] = &disp0_cc_sleep_clk_src.clkr,
};
static struct clk_regmap *disp1_cc_sc8280xp_clocks[] = {
[DISP_CC_MDSS_AHB1_CLK] = &disp1_cc_mdss_ahb1_clk.clkr,
[DISP_CC_MDSS_AHB_CLK] = &disp1_cc_mdss_ahb_clk.clkr,
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp1_cc_mdss_ahb_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_CLK] = &disp1_cc_mdss_byte0_clk.clkr,
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp1_cc_mdss_byte0_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp1_cc_mdss_byte0_div_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp1_cc_mdss_byte0_intf_clk.clkr,
[DISP_CC_MDSS_BYTE1_CLK] = &disp1_cc_mdss_byte1_clk.clkr,
[DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp1_cc_mdss_byte1_clk_src.clkr,
[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp1_cc_mdss_byte1_div_clk_src.clkr,
[DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp1_cc_mdss_byte1_intf_clk.clkr,
[DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp1_cc_mdss_dptx0_aux_clk.clkr,
[DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp1_cc_mdss_dptx0_aux_clk_src.clkr,
[DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp1_cc_mdss_dptx0_link_clk.clkr,
[DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp1_cc_mdss_dptx0_link_clk_src.clkr,
[DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp1_cc_mdss_dptx0_link_div_clk_src.clkr,
[DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp1_cc_mdss_dptx0_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp1_cc_mdss_dptx0_pixel0_clk.clkr,
[DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp1_cc_mdss_dptx0_pixel0_clk_src.clkr,
[DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp1_cc_mdss_dptx0_pixel1_clk.clkr,
[DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp1_cc_mdss_dptx0_pixel1_clk_src.clkr,
[DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = &disp1_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp1_cc_mdss_dptx1_aux_clk.clkr,
[DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp1_cc_mdss_dptx1_aux_clk_src.clkr,
[DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp1_cc_mdss_dptx1_link_clk.clkr,
[DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp1_cc_mdss_dptx1_link_clk_src.clkr,
[DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp1_cc_mdss_dptx1_link_div_clk_src.clkr,
[DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp1_cc_mdss_dptx1_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp1_cc_mdss_dptx1_pixel0_clk.clkr,
[DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp1_cc_mdss_dptx1_pixel0_clk_src.clkr,
[DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp1_cc_mdss_dptx1_pixel1_clk.clkr,
[DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp1_cc_mdss_dptx1_pixel1_clk_src.clkr,
[DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = &disp1_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp1_cc_mdss_dptx2_aux_clk.clkr,
[DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp1_cc_mdss_dptx2_aux_clk_src.clkr,
[DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp1_cc_mdss_dptx2_link_clk.clkr,
[DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp1_cc_mdss_dptx2_link_clk_src.clkr,
[DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp1_cc_mdss_dptx2_link_div_clk_src.clkr,
[DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp1_cc_mdss_dptx2_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp1_cc_mdss_dptx2_pixel0_clk.clkr,
[DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp1_cc_mdss_dptx2_pixel0_clk_src.clkr,
[DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp1_cc_mdss_dptx2_pixel1_clk.clkr,
[DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp1_cc_mdss_dptx2_pixel1_clk_src.clkr,
[DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp1_cc_mdss_dptx3_aux_clk.clkr,
[DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp1_cc_mdss_dptx3_aux_clk_src.clkr,
[DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp1_cc_mdss_dptx3_link_clk.clkr,
[DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp1_cc_mdss_dptx3_link_clk_src.clkr,
[DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp1_cc_mdss_dptx3_link_div_clk_src.clkr,
[DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp1_cc_mdss_dptx3_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp1_cc_mdss_dptx3_pixel0_clk.clkr,
[DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp1_cc_mdss_dptx3_pixel0_clk_src.clkr,
[DISP_CC_MDSS_ESC0_CLK] = &disp1_cc_mdss_esc0_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp1_cc_mdss_esc0_clk_src.clkr,
[DISP_CC_MDSS_ESC1_CLK] = &disp1_cc_mdss_esc1_clk.clkr,
[DISP_CC_MDSS_ESC1_CLK_SRC] = &disp1_cc_mdss_esc1_clk_src.clkr,
[DISP_CC_MDSS_MDP1_CLK] = &disp1_cc_mdss_mdp1_clk.clkr,
[DISP_CC_MDSS_MDP_CLK] = &disp1_cc_mdss_mdp_clk.clkr,
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp1_cc_mdss_mdp_clk_src.clkr,
[DISP_CC_MDSS_MDP_LUT1_CLK] = &disp1_cc_mdss_mdp_lut1_clk.clkr,
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp1_cc_mdss_mdp_lut_clk.clkr,
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp1_cc_mdss_non_gdsc_ahb_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK] = &disp1_cc_mdss_pclk0_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp1_cc_mdss_pclk0_clk_src.clkr,
[DISP_CC_MDSS_PCLK1_CLK] = &disp1_cc_mdss_pclk1_clk.clkr,
[DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp1_cc_mdss_pclk1_clk_src.clkr,
[DISP_CC_MDSS_ROT1_CLK] = &disp1_cc_mdss_rot1_clk.clkr,
[DISP_CC_MDSS_ROT_CLK] = &disp1_cc_mdss_rot_clk.clkr,
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp1_cc_mdss_rot_clk_src.clkr,
[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp1_cc_mdss_rscc_ahb_clk.clkr,
[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp1_cc_mdss_rscc_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC1_CLK] = &disp1_cc_mdss_vsync1_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK] = &disp1_cc_mdss_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp1_cc_mdss_vsync_clk_src.clkr,
[DISP_CC_PLL0] = &disp1_cc_pll0.clkr,
[DISP_CC_PLL1] = &disp1_cc_pll1.clkr,
[DISP_CC_PLL1_OUT_EVEN] = &disp1_cc_pll1_out_even.clkr,
[DISP_CC_PLL2] = &disp1_cc_pll2.clkr,
[DISP_CC_SLEEP_CLK] = &disp1_cc_sleep_clk.clkr,
[DISP_CC_SLEEP_CLK_SRC] = &disp1_cc_sleep_clk_src.clkr,
};
static const struct qcom_reset_map disp_cc_sc8280xp_resets[] = {
[DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
[DISP_CC_MDSS_RSCC_BCR] = { 0x4000 },
};
static struct gdsc disp0_mdss_gdsc = {
.gdscr = 0x3000,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "disp0_mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL | RETAIN_FF_ENABLE,
};
static struct gdsc disp1_mdss_gdsc = {
.gdscr = 0x3000,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "disp1_mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL | RETAIN_FF_ENABLE,
};
static struct gdsc disp0_mdss_int2_gdsc = {
.gdscr = 0xa000,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "disp0_mdss_int2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL | RETAIN_FF_ENABLE,
};
static struct gdsc disp1_mdss_int2_gdsc = {
.gdscr = 0xa000,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "disp1_mdss_int2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL | RETAIN_FF_ENABLE,
};
static struct gdsc *disp0_cc_sc8280xp_gdscs[] = {
[MDSS_GDSC] = &disp0_mdss_gdsc,
[MDSS_INT2_GDSC] = &disp0_mdss_int2_gdsc,
};
static struct gdsc *disp1_cc_sc8280xp_gdscs[] = {
[MDSS_GDSC] = &disp1_mdss_gdsc,
[MDSS_INT2_GDSC] = &disp1_mdss_int2_gdsc,
};
static const struct regmap_config disp_cc_sc8280xp_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x10000,
.fast_io = true,
};
static struct qcom_cc_desc disp0_cc_sc8280xp_desc = {
.config = &disp_cc_sc8280xp_regmap_config,
.clks = disp0_cc_sc8280xp_clocks,
.num_clks = ARRAY_SIZE(disp0_cc_sc8280xp_clocks),
.resets = disp_cc_sc8280xp_resets,
.num_resets = ARRAY_SIZE(disp_cc_sc8280xp_resets),
.gdscs = disp0_cc_sc8280xp_gdscs,
.num_gdscs = ARRAY_SIZE(disp0_cc_sc8280xp_gdscs),
};
static struct qcom_cc_desc disp1_cc_sc8280xp_desc = {
.config = &disp_cc_sc8280xp_regmap_config,
.clks = disp1_cc_sc8280xp_clocks,
.num_clks = ARRAY_SIZE(disp1_cc_sc8280xp_clocks),
.resets = disp_cc_sc8280xp_resets,
.num_resets = ARRAY_SIZE(disp_cc_sc8280xp_resets),
.gdscs = disp1_cc_sc8280xp_gdscs,
.num_gdscs = ARRAY_SIZE(disp1_cc_sc8280xp_gdscs),
};
#define clkr_to_alpha_clk_pll(_clkr) container_of(_clkr, struct clk_alpha_pll, clkr)
static int disp_cc_sc8280xp_probe(struct platform_device *pdev)
{
const struct qcom_cc_desc *desc;
struct regmap *regmap;
int ret;
desc = device_get_match_data(&pdev->dev);
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = devm_pm_clk_create(&pdev->dev);
if (ret)
return ret;
ret = pm_clk_add(&pdev->dev, NULL);
if (ret < 0) {
dev_err(&pdev->dev, "failed to acquire ahb clock\n");
return ret;
}
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
regmap = qcom_cc_map(pdev, desc);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
goto out_pm_runtime_put;
}
clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL0]), regmap, &disp_cc_pll0_config);
clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL1]), regmap, &disp_cc_pll1_config);
clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL2]), regmap, &disp_cc_pll2_config);
ret = qcom_cc_really_probe(pdev, desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register display clock controller\n");
goto out_pm_runtime_put;
}
/* DISP_CC_XO_CLK always-on */
regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0));
out_pm_runtime_put:
pm_runtime_put_sync(&pdev->dev);
return ret;
}
static const struct of_device_id disp_cc_sc8280xp_match_table[] = {
{ .compatible = "qcom,sc8280xp-dispcc0", .data = &disp0_cc_sc8280xp_desc },
{ .compatible = "qcom,sc8280xp-dispcc1", .data = &disp1_cc_sc8280xp_desc },
{ }
};
MODULE_DEVICE_TABLE(of, disp_cc_sc8280xp_match_table);
static struct platform_driver disp_cc_sc8280xp_driver = {
.probe = disp_cc_sc8280xp_probe,
.driver = {
.name = "disp_cc-sc8280xp",
.of_match_table = disp_cc_sc8280xp_match_table,
},
};
static int __init disp_cc_sc8280xp_init(void)
{
return platform_driver_register(&disp_cc_sc8280xp_driver);
}
subsys_initcall(disp_cc_sc8280xp_init);
static void __exit disp_cc_sc8280xp_exit(void)
{
platform_driver_unregister(&disp_cc_sc8280xp_driver);
}
module_exit(disp_cc_sc8280xp_exit);
MODULE_DESCRIPTION("Qualcomm SC8280XP dispcc driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/dispcc-sc8280xp.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sdx75-gcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_SLEEP_CLK,
DT_EMAC0_SGMIIPHY_MAC_RCLK,
DT_EMAC0_SGMIIPHY_MAC_TCLK,
DT_EMAC0_SGMIIPHY_RCLK,
DT_EMAC0_SGMIIPHY_TCLK,
DT_EMAC1_SGMIIPHY_MAC_RCLK,
DT_EMAC1_SGMIIPHY_MAC_TCLK,
DT_EMAC1_SGMIIPHY_RCLK,
DT_EMAC1_SGMIIPHY_TCLK,
DT_PCIE20_PHY_AUX_CLK,
DT_PCIE_1_PIPE_CLK,
DT_PCIE_2_PIPE_CLK,
DT_PCIE_PIPE_CLK,
DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
};
enum {
P_BI_TCXO,
P_EMAC0_SGMIIPHY_MAC_RCLK,
P_EMAC0_SGMIIPHY_MAC_TCLK,
P_EMAC0_SGMIIPHY_RCLK,
P_EMAC0_SGMIIPHY_TCLK,
P_EMAC1_SGMIIPHY_MAC_RCLK,
P_EMAC1_SGMIIPHY_MAC_TCLK,
P_EMAC1_SGMIIPHY_RCLK,
P_EMAC1_SGMIIPHY_TCLK,
P_GPLL0_OUT_EVEN,
P_GPLL0_OUT_MAIN,
P_GPLL4_OUT_MAIN,
P_GPLL5_OUT_MAIN,
P_GPLL6_OUT_MAIN,
P_GPLL8_OUT_MAIN,
P_PCIE20_PHY_AUX_CLK,
P_PCIE_1_PIPE_CLK,
P_PCIE_2_PIPE_CLK,
P_PCIE_PIPE_CLK,
P_SLEEP_CLK,
P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
};
static struct clk_alpha_pll gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.enable_reg = 0x7d000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gpll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll0_out_even = {
.offset = 0x0,
.post_div_shift = 10,
.post_div_table = post_div_table_gpll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpll0_out_even",
.parent_hws = (const struct clk_hw*[]) {
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
},
};
static struct clk_alpha_pll gpll4 = {
.offset = 0x4000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.enable_reg = 0x7d000,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data) {
.name = "gpll4",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
},
},
};
static struct clk_alpha_pll gpll5 = {
.offset = 0x5000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.enable_reg = 0x7d000,
.enable_mask = BIT(5),
.hw.init = &(const struct clk_init_data) {
.name = "gpll5",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
},
},
};
static struct clk_alpha_pll gpll6 = {
.offset = 0x6000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.enable_reg = 0x7d000,
.enable_mask = BIT(6),
.hw.init = &(const struct clk_init_data) {
.name = "gpll6",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
},
},
};
static struct clk_alpha_pll gpll8 = {
.offset = 0x8000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.enable_reg = 0x7d000,
.enable_mask = BIT(8),
.hw.init = &(const struct clk_init_data) {
.name = "gpll8",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
},
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL4_OUT_MAIN, 2 },
{ P_GPLL5_OUT_MAIN, 5 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll5.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .index = DT_SLEEP_CLK },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_4[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_EMAC0_SGMIIPHY_RCLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .index = DT_EMAC0_SGMIIPHY_RCLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_EMAC0_SGMIIPHY_TCLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_6[] = {
{ .index = DT_EMAC0_SGMIIPHY_TCLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_7[] = {
{ P_EMAC0_SGMIIPHY_MAC_RCLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_7[] = {
{ .index = DT_EMAC0_SGMIIPHY_MAC_RCLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_EMAC0_SGMIIPHY_MAC_TCLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_8[] = {
{ .index = DT_EMAC0_SGMIIPHY_MAC_TCLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_9[] = {
{ P_EMAC1_SGMIIPHY_RCLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_9[] = {
{ .index = DT_EMAC1_SGMIIPHY_RCLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_10[] = {
{ P_EMAC1_SGMIIPHY_TCLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_10[] = {
{ .index = DT_EMAC1_SGMIIPHY_TCLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_11[] = {
{ P_EMAC1_SGMIIPHY_MAC_RCLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_11[] = {
{ .index = DT_EMAC1_SGMIIPHY_MAC_RCLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_12[] = {
{ P_EMAC1_SGMIIPHY_MAC_TCLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_12[] = {
{ .index = DT_EMAC1_SGMIIPHY_MAC_TCLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_15[] = {
{ P_PCIE20_PHY_AUX_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_15[] = {
{ .index = DT_PCIE20_PHY_AUX_CLK },
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_17[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL6_OUT_MAIN, 2 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_17[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll6.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_18[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL8_OUT_MAIN, 2 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_18[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll8.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_19[] = {
{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_19[] = {
{ .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK },
{ .index = DT_BI_TCXO },
};
static struct clk_regmap_mux gcc_emac0_cc_sgmiiphy_rx_clk_src = {
.reg = 0x71060,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_5,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_cc_sgmiiphy_rx_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_emac0_cc_sgmiiphy_tx_clk_src = {
.reg = 0x71058,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_6,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_cc_sgmiiphy_tx_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_emac0_sgmiiphy_mac_rclk_src = {
.reg = 0x71098,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_7,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_sgmiiphy_mac_rclk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_emac0_sgmiiphy_mac_tclk_src = {
.reg = 0x71094,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_8,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_sgmiiphy_mac_tclk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_emac1_cc_sgmiiphy_rx_clk_src = {
.reg = 0x72060,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_9,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_cc_sgmiiphy_rx_clk_src",
.parent_data = gcc_parent_data_9,
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_emac1_cc_sgmiiphy_tx_clk_src = {
.reg = 0x72058,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_10,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_cc_sgmiiphy_tx_clk_src",
.parent_data = gcc_parent_data_10,
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_emac1_sgmiiphy_mac_rclk_src = {
.reg = 0x72098,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_11,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_sgmiiphy_mac_rclk_src",
.parent_data = gcc_parent_data_11,
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_emac1_sgmiiphy_mac_tclk_src = {
.reg = 0x72094,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_12,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_sgmiiphy_mac_tclk_src",
.parent_data = gcc_parent_data_12,
.num_parents = ARRAY_SIZE(gcc_parent_data_12),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
.reg = 0x67084,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
.index = DT_PCIE_1_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_phy_mux gcc_pcie_2_pipe_clk_src = {
.reg = 0x68050,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
.index = DT_PCIE_2_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux gcc_pcie_aux_clk_src = {
.reg = 0x53074,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_15,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_aux_clk_src",
.parent_data = gcc_parent_data_15,
.num_parents = ARRAY_SIZE(gcc_parent_data_15),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_phy_mux gcc_pcie_pipe_clk_src = {
.reg = 0x53058,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
.index = DT_PCIE_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux gcc_usb3_phy_pipe_clk_src = {
.reg = 0x27070,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_19,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_phy_pipe_clk_src",
.parent_data = gcc_parent_data_19,
.num_parents = ARRAY_SIZE(gcc_parent_data_19),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_eee_emac0_clk_src[] = {
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_eee_emac0_clk_src = {
.cmd_rcgr = 0x710b0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_eee_emac0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_eee_emac0_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_eee_emac1_clk_src = {
.cmd_rcgr = 0x720b0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_eee_emac0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_eee_emac1_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_emac0_phy_aux_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_emac0_phy_aux_clk_src = {
.cmd_rcgr = 0x7102c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_phy_aux_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] = {
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(125000000, P_GPLL4_OUT_MAIN, 4, 0, 0),
F(230400000, P_GPLL5_OUT_MAIN, 3.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_emac0_ptp_clk_src = {
.cmd_rcgr = 0x7107c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_emac0_ptp_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_ptp_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] = {
F(5000000, P_GPLL0_OUT_EVEN, 10, 1, 6),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(125000000, P_GPLL4_OUT_MAIN, 4, 0, 0),
F(250000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_emac0_rgmii_clk_src = {
.cmd_rcgr = 0x71064,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_emac0_rgmii_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_rgmii_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_emac1_phy_aux_clk_src = {
.cmd_rcgr = 0x7202c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_phy_aux_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_emac1_ptp_clk_src = {
.cmd_rcgr = 0x7207c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_emac0_ptp_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_ptp_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_emac1_rgmii_clk_src = {
.cmd_rcgr = 0x72064,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_emac0_rgmii_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_rgmii_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x47004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x48004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x49004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_1_aux_phy_clk_src = {
.cmd_rcgr = 0x67044,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_aux_phy_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_1_phy_rchng_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
.cmd_rcgr = 0x6706c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_1_phy_rchng_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_phy_rchng_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_2_aux_phy_clk_src = {
.cmd_rcgr = 0x68064,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2_aux_phy_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src = {
.cmd_rcgr = 0x68038,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_1_phy_rchng_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2_phy_rchng_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_aux_phy_clk_src = {
.cmd_rcgr = 0x5305c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_aux_phy_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_rchng_phy_clk_src = {
.cmd_rcgr = 0x53078,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_1_phy_rchng_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_rchng_phy_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x34010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.cmd_rcgr = 0x6c010,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.cmd_rcgr = 0x6c148,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.cmd_rcgr = 0x6c280,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.cmd_rcgr = 0x6c3b8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.cmd_rcgr = 0x6c4f0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.cmd_rcgr = 0x6c628,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
.name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
.cmd_rcgr = 0x6c760,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
.name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
.cmd_rcgr = 0x6c898,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap0_s8_clk_src_init = {
.name = "gcc_qupv3_wrap0_s8_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap0_s8_clk_src = {
.cmd_rcgr = 0x6c9d0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
.clkr.hw.init = &gcc_qupv3_wrap0_s8_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
F(144000, P_BI_TCXO, 16, 3, 25),
F(400000, P_BI_TCXO, 12, 1, 4),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.cmd_rcgr = 0x6b014,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_17,
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc1_apps_clk_src",
.parent_data = gcc_parent_data_17,
.num_parents = ARRAY_SIZE(gcc_parent_data_17),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
F(202000000, P_GPLL8_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.cmd_rcgr = 0x6a018,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_18,
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_18,
.num_parents = ARRAY_SIZE(gcc_parent_data_18),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_master_clk_src[] = {
F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_master_clk_src = {
.cmd_rcgr = 0x27034,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_master_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb30_mock_utmi_clk_src = {
.cmd_rcgr = 0x2704c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb3_phy_aux_clk_src[] = {
F(1000000, P_BI_TCXO, 1, 5, 96),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb3_phy_aux_clk_src = {
.cmd_rcgr = 0x27074,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_usb3_phy_aux_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div gcc_pcie_1_pipe_div2_clk_src = {
.reg = 0x67088,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_pipe_div2_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_1_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_pcie_2_pipe_div2_clk_src = {
.reg = 0x68088,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2_pipe_div2_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_2_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_usb30_mock_utmi_postdiv_clk_src = {
.reg = 0x27064,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x37004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x37004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7d008,
.enable_mask = BIT(26),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_eee_emac0_clk = {
.halt_reg = 0x710ac,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x710ac,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_eee_emac0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_eee_emac0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_eee_emac1_clk = {
.halt_reg = 0x720ac,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x720ac,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_eee_emac1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_eee_emac1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac0_axi_clk = {
.halt_reg = 0x71018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x71018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac0_cc_sgmiiphy_rx_clk = {
.halt_reg = 0x7105c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7105c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_cc_sgmiiphy_rx_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_emac0_cc_sgmiiphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac0_cc_sgmiiphy_tx_clk = {
.halt_reg = 0x71054,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x71054,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_cc_sgmiiphy_tx_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_emac0_cc_sgmiiphy_tx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac0_phy_aux_clk = {
.halt_reg = 0x71028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x71028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_emac0_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac0_ptp_clk = {
.halt_reg = 0x71044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x71044,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_ptp_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_emac0_ptp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac0_rgmii_clk = {
.halt_reg = 0x71050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x71050,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_rgmii_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_emac0_rgmii_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac0_rpcs_rx_clk = {
.halt_reg = 0x710a0,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x710a0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_rpcs_rx_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_emac0_sgmiiphy_mac_rclk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac0_rpcs_tx_clk = {
.halt_reg = 0x7109c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7109c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_rpcs_tx_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_emac0_sgmiiphy_mac_tclk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac0_slv_ahb_clk = {
.halt_reg = 0x71024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x71024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_slv_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac0_xgxs_rx_clk = {
.halt_reg = 0x710a8,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x710a8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_xgxs_rx_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_emac0_sgmiiphy_mac_rclk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac0_xgxs_tx_clk = {
.halt_reg = 0x710a4,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x710a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac0_xgxs_tx_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_emac0_sgmiiphy_mac_tclk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac1_axi_clk = {
.halt_reg = 0x72018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x72018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x72018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac1_cc_sgmiiphy_rx_clk = {
.halt_reg = 0x7205c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7205c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_cc_sgmiiphy_rx_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_emac1_cc_sgmiiphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac1_cc_sgmiiphy_tx_clk = {
.halt_reg = 0x72054,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x72054,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_cc_sgmiiphy_tx_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_emac1_cc_sgmiiphy_tx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac1_phy_aux_clk = {
.halt_reg = 0x72028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x72028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_emac1_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac1_ptp_clk = {
.halt_reg = 0x72044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x72044,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_ptp_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_emac1_ptp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac1_rgmii_clk = {
.halt_reg = 0x72050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x72050,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_rgmii_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_emac1_rgmii_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac1_rpcs_rx_clk = {
.halt_reg = 0x720a0,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x720a0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_rpcs_rx_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_emac1_sgmiiphy_mac_rclk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac1_rpcs_tx_clk = {
.halt_reg = 0x7209c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7209c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_rpcs_tx_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_emac1_sgmiiphy_mac_tclk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac1_slv_ahb_clk = {
.halt_reg = 0x72024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x72024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x72024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_slv_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac1_xgxs_rx_clk = {
.halt_reg = 0x720a8,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x720a8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_xgxs_rx_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_emac1_sgmiiphy_mac_rclk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac1_xgxs_tx_clk = {
.halt_reg = 0x720a4,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x720a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac1_xgxs_tx_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_emac1_sgmiiphy_mac_tclk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac_0_clkref_en = {
.halt_reg = 0x98108,
.halt_check = BRANCH_HALT_ENABLE,
.clkr = {
.enable_reg = 0x98108,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac_0_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_emac_1_clkref_en = {
.halt_reg = 0x9810c,
.halt_check = BRANCH_HALT_ENABLE,
.clkr = {
.enable_reg = 0x9810c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_emac_1_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x47000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x47000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x48000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x48000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x49000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x49000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_clkref_en = {
.halt_reg = 0x98004,
.halt_check = BRANCH_HALT_ENABLE,
.clkr = {
.enable_reg = 0x98004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_aux_clk = {
.halt_reg = 0x67038,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(22),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_1_aux_phy_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
.halt_reg = 0x67034,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x67034,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(21),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_clkref_en = {
.halt_reg = 0x98114,
.halt_check = BRANCH_HALT_ENABLE,
.clkr = {
.enable_reg = 0x98114,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
.halt_reg = 0x67028,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(20),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
.halt_reg = 0x67068,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(24),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_pipe_clk = {
.halt_reg = 0x6705c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(23),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_1_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_pipe_div2_clk = {
.halt_reg = 0x6708c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7d020,
.enable_mask = BIT(3),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_pipe_div2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_1_pipe_div2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_axi_clk = {
.halt_reg = 0x6701c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(19),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
.halt_reg = 0x67018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(18),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_aux_clk = {
.halt_reg = 0x68058,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(29),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_2_aux_phy_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
.halt_reg = 0x68034,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x68034,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(28),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_clkref_en = {
.halt_reg = 0x98110,
.halt_check = BRANCH_HALT_ENABLE,
.clkr = {
.enable_reg = 0x98110,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
.halt_reg = 0x68028,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d008,
.enable_mask = BIT(8),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_phy_rchng_clk = {
.halt_reg = 0x68098,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(31),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_2_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_pipe_clk = {
.halt_reg = 0x6807c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(30),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_2_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_pipe_div2_clk = {
.halt_reg = 0x6808c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7d020,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2_pipe_div2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_2_pipe_div2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_slv_axi_clk = {
.halt_reg = 0x6801c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(26),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = {
.halt_reg = 0x68018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(25),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_aux_clk = {
.halt_reg = 0x5303c,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x5303c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(15),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_cfg_ahb_clk = {
.halt_reg = 0x53034,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x53034,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(13),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_mstr_axi_clk = {
.halt_reg = 0x53028,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x53028,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(12),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_pipe_clk = {
.halt_reg = 0x5304c,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x5304c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(17),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_rchng_phy_clk = {
.halt_reg = 0x53038,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x53038,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(14),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_rchng_phy_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_rchng_phy_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_sleep_clk = {
.halt_reg = 0x53048,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x53048,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(16),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_sleep_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_aux_phy_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_slv_axi_clk = {
.halt_reg = 0x5301c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(11),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_slv_q2a_axi_clk = {
.halt_reg = 0x53018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x53018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7d010,
.enable_mask = BIT(10),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x3400c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3400c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x34004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x34004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x34008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x34008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
.halt_reg = 0x2d018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d008,
.enable_mask = BIT(15),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_core_clk = {
.halt_reg = 0x2d008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d008,
.enable_mask = BIT(14),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.halt_reg = 0x6c004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d008,
.enable_mask = BIT(16),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.halt_reg = 0x6c13c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d008,
.enable_mask = BIT(17),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.halt_reg = 0x6c274,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d008,
.enable_mask = BIT(18),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.halt_reg = 0x6c3ac,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d008,
.enable_mask = BIT(19),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.halt_reg = 0x6c4e4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d008,
.enable_mask = BIT(20),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s4_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.halt_reg = 0x6c61c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d008,
.enable_mask = BIT(21),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s5_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
.halt_reg = 0x6c754,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d008,
.enable_mask = BIT(22),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s6_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
.halt_reg = 0x6c88c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d008,
.enable_mask = BIT(23),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s7_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap0_s8_clk = {
.halt_reg = 0x6c9c4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d020,
.enable_mask = BIT(7),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap0_s8_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s8_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
.halt_reg = 0x2d000,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2d000,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7d008,
.enable_mask = BIT(12),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
.halt_reg = 0x2d004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2d004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7d008,
.enable_mask = BIT(13),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x6b004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6b004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x6b008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6b008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x6a010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6a010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x6a004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6a004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb2_clkref_en = {
.halt_reg = 0x98008,
.halt_check = BRANCH_HALT_ENABLE,
.clkr = {
.enable_reg = 0x98008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb2_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_master_clk = {
.halt_reg = 0x27018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x27018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_master_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_mock_utmi_clk = {
.halt_reg = 0x27030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x27030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_mstr_axi_clk = {
.halt_reg = 0x27024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x27024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sleep_clk = {
.halt_reg = 0x2702c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2702c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_slv_ahb_clk = {
.halt_reg = 0x27028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x27028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_slv_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_phy_aux_clk = {
.halt_reg = 0x27068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x27068,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_phy_pipe_clk = {
.halt_reg = 0x2706c,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x2706c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2706c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_phy_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_phy_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_clkref_en = {
.halt_reg = 0x98000,
.halt_check = BRANCH_HALT_ENABLE,
.clkr = {
.enable_reg = 0x98000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_prim_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
.halt_reg = 0x29004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x29004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x29004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb_phy_cfg_ahb2phy_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct gdsc gcc_emac0_gdsc = {
.gdscr = 0x71004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_emac0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc gcc_emac1_gdsc = {
.gdscr = 0x72004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_emac1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc gcc_pcie_1_gdsc = {
.gdscr = 0x67004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_pcie_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc gcc_pcie_1_phy_gdsc = {
.gdscr = 0x56004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gcc_pcie_1_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc gcc_pcie_2_gdsc = {
.gdscr = 0x68004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_pcie_2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc gcc_pcie_2_phy_gdsc = {
.gdscr = 0x6e004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gcc_pcie_2_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc gcc_pcie_gdsc = {
.gdscr = 0x53004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_pcie_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc gcc_pcie_phy_gdsc = {
.gdscr = 0x54004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gcc_pcie_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc gcc_usb30_gdsc = {
.gdscr = 0x27004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_usb30_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct gdsc gcc_usb3_phy_gdsc = {
.gdscr = 0x28008,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gcc_usb3_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = RETAIN_FF_ENABLE,
};
static struct clk_regmap *gcc_sdx75_clocks[] = {
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_EEE_EMAC0_CLK] = &gcc_eee_emac0_clk.clkr,
[GCC_EEE_EMAC0_CLK_SRC] = &gcc_eee_emac0_clk_src.clkr,
[GCC_EEE_EMAC1_CLK] = &gcc_eee_emac1_clk.clkr,
[GCC_EEE_EMAC1_CLK_SRC] = &gcc_eee_emac1_clk_src.clkr,
[GCC_EMAC0_AXI_CLK] = &gcc_emac0_axi_clk.clkr,
[GCC_EMAC0_CC_SGMIIPHY_RX_CLK] = &gcc_emac0_cc_sgmiiphy_rx_clk.clkr,
[GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC] = &gcc_emac0_cc_sgmiiphy_rx_clk_src.clkr,
[GCC_EMAC0_CC_SGMIIPHY_TX_CLK] = &gcc_emac0_cc_sgmiiphy_tx_clk.clkr,
[GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC] = &gcc_emac0_cc_sgmiiphy_tx_clk_src.clkr,
[GCC_EMAC0_PHY_AUX_CLK] = &gcc_emac0_phy_aux_clk.clkr,
[GCC_EMAC0_PHY_AUX_CLK_SRC] = &gcc_emac0_phy_aux_clk_src.clkr,
[GCC_EMAC0_PTP_CLK] = &gcc_emac0_ptp_clk.clkr,
[GCC_EMAC0_PTP_CLK_SRC] = &gcc_emac0_ptp_clk_src.clkr,
[GCC_EMAC0_RGMII_CLK] = &gcc_emac0_rgmii_clk.clkr,
[GCC_EMAC0_RGMII_CLK_SRC] = &gcc_emac0_rgmii_clk_src.clkr,
[GCC_EMAC0_RPCS_RX_CLK] = &gcc_emac0_rpcs_rx_clk.clkr,
[GCC_EMAC0_RPCS_TX_CLK] = &gcc_emac0_rpcs_tx_clk.clkr,
[GCC_EMAC0_SGMIIPHY_MAC_RCLK_SRC] = &gcc_emac0_sgmiiphy_mac_rclk_src.clkr,
[GCC_EMAC0_SGMIIPHY_MAC_TCLK_SRC] = &gcc_emac0_sgmiiphy_mac_tclk_src.clkr,
[GCC_EMAC0_SLV_AHB_CLK] = &gcc_emac0_slv_ahb_clk.clkr,
[GCC_EMAC0_XGXS_RX_CLK] = &gcc_emac0_xgxs_rx_clk.clkr,
[GCC_EMAC0_XGXS_TX_CLK] = &gcc_emac0_xgxs_tx_clk.clkr,
[GCC_EMAC1_AXI_CLK] = &gcc_emac1_axi_clk.clkr,
[GCC_EMAC1_CC_SGMIIPHY_RX_CLK] = &gcc_emac1_cc_sgmiiphy_rx_clk.clkr,
[GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC] = &gcc_emac1_cc_sgmiiphy_rx_clk_src.clkr,
[GCC_EMAC1_CC_SGMIIPHY_TX_CLK] = &gcc_emac1_cc_sgmiiphy_tx_clk.clkr,
[GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC] = &gcc_emac1_cc_sgmiiphy_tx_clk_src.clkr,
[GCC_EMAC1_PHY_AUX_CLK] = &gcc_emac1_phy_aux_clk.clkr,
[GCC_EMAC1_PHY_AUX_CLK_SRC] = &gcc_emac1_phy_aux_clk_src.clkr,
[GCC_EMAC1_PTP_CLK] = &gcc_emac1_ptp_clk.clkr,
[GCC_EMAC1_PTP_CLK_SRC] = &gcc_emac1_ptp_clk_src.clkr,
[GCC_EMAC1_RGMII_CLK] = &gcc_emac1_rgmii_clk.clkr,
[GCC_EMAC1_RGMII_CLK_SRC] = &gcc_emac1_rgmii_clk_src.clkr,
[GCC_EMAC1_RPCS_RX_CLK] = &gcc_emac1_rpcs_rx_clk.clkr,
[GCC_EMAC1_RPCS_TX_CLK] = &gcc_emac1_rpcs_tx_clk.clkr,
[GCC_EMAC1_SGMIIPHY_MAC_RCLK_SRC] = &gcc_emac1_sgmiiphy_mac_rclk_src.clkr,
[GCC_EMAC1_SGMIIPHY_MAC_TCLK_SRC] = &gcc_emac1_sgmiiphy_mac_tclk_src.clkr,
[GCC_EMAC1_SLV_AHB_CLK] = &gcc_emac1_slv_ahb_clk.clkr,
[GCC_EMAC1_XGXS_RX_CLK] = &gcc_emac1_xgxs_rx_clk.clkr,
[GCC_EMAC1_XGXS_TX_CLK] = &gcc_emac1_xgxs_tx_clk.clkr,
[GCC_EMAC_0_CLKREF_EN] = &gcc_emac_0_clkref_en.clkr,
[GCC_EMAC_1_CLKREF_EN] = &gcc_emac_1_clkref_en.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
[GCC_PCIE_1_AUX_PHY_CLK_SRC] = &gcc_pcie_1_aux_phy_clk_src.clkr,
[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
[GCC_PCIE_1_CLKREF_EN] = &gcc_pcie_1_clkref_en.clkr,
[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
[GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
[GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
[GCC_PCIE_1_PIPE_DIV2_CLK] = &gcc_pcie_1_pipe_div2_clk.clkr,
[GCC_PCIE_1_PIPE_DIV2_CLK_SRC] = &gcc_pcie_1_pipe_div2_clk_src.clkr,
[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
[GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
[GCC_PCIE_2_AUX_PHY_CLK_SRC] = &gcc_pcie_2_aux_phy_clk_src.clkr,
[GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
[GCC_PCIE_2_CLKREF_EN] = &gcc_pcie_2_clkref_en.clkr,
[GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
[GCC_PCIE_2_PHY_RCHNG_CLK] = &gcc_pcie_2_phy_rchng_clk.clkr,
[GCC_PCIE_2_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2_phy_rchng_clk_src.clkr,
[GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
[GCC_PCIE_2_PIPE_CLK_SRC] = &gcc_pcie_2_pipe_clk_src.clkr,
[GCC_PCIE_2_PIPE_DIV2_CLK] = &gcc_pcie_2_pipe_div2_clk.clkr,
[GCC_PCIE_2_PIPE_DIV2_CLK_SRC] = &gcc_pcie_2_pipe_div2_clk_src.clkr,
[GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
[GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr,
[GCC_PCIE_AUX_CLK] = &gcc_pcie_aux_clk.clkr,
[GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr,
[GCC_PCIE_AUX_PHY_CLK_SRC] = &gcc_pcie_aux_phy_clk_src.clkr,
[GCC_PCIE_CFG_AHB_CLK] = &gcc_pcie_cfg_ahb_clk.clkr,
[GCC_PCIE_MSTR_AXI_CLK] = &gcc_pcie_mstr_axi_clk.clkr,
[GCC_PCIE_PIPE_CLK] = &gcc_pcie_pipe_clk.clkr,
[GCC_PCIE_PIPE_CLK_SRC] = &gcc_pcie_pipe_clk_src.clkr,
[GCC_PCIE_RCHNG_PHY_CLK] = &gcc_pcie_rchng_phy_clk.clkr,
[GCC_PCIE_RCHNG_PHY_CLK_SRC] = &gcc_pcie_rchng_phy_clk_src.clkr,
[GCC_PCIE_SLEEP_CLK] = &gcc_pcie_sleep_clk.clkr,
[GCC_PCIE_SLV_AXI_CLK] = &gcc_pcie_slv_axi_clk.clkr,
[GCC_PCIE_SLV_Q2A_AXI_CLK] = &gcc_pcie_slv_q2a_axi_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
[GCC_QUPV3_WRAP0_S8_CLK] = &gcc_qupv3_wrap0_s8_clk.clkr,
[GCC_QUPV3_WRAP0_S8_CLK_SRC] = &gcc_qupv3_wrap0_s8_clk_src.clkr,
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_USB2_CLKREF_EN] = &gcc_usb2_clkref_en.clkr,
[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
[GCC_USB30_MASTER_CLK_SRC] = &gcc_usb30_master_clk_src.clkr,
[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
[GCC_USB30_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mock_utmi_clk_src.clkr,
[GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_MSTR_AXI_CLK] = &gcc_usb30_mstr_axi_clk.clkr,
[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
[GCC_USB30_SLV_AHB_CLK] = &gcc_usb30_slv_ahb_clk.clkr,
[GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
[GCC_USB3_PHY_AUX_CLK_SRC] = &gcc_usb3_phy_aux_clk_src.clkr,
[GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
[GCC_USB3_PHY_PIPE_CLK_SRC] = &gcc_usb3_phy_pipe_clk_src.clkr,
[GCC_USB3_PRIM_CLKREF_EN] = &gcc_usb3_prim_clkref_en.clkr,
[GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
[GPLL4] = &gpll4.clkr,
[GPLL5] = &gpll5.clkr,
[GPLL6] = &gpll6.clkr,
[GPLL8] = &gpll8.clkr,
};
static struct gdsc *gcc_sdx75_gdscs[] = {
[GCC_EMAC0_GDSC] = &gcc_emac0_gdsc,
[GCC_EMAC1_GDSC] = &gcc_emac1_gdsc,
[GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc,
[GCC_PCIE_1_PHY_GDSC] = &gcc_pcie_1_phy_gdsc,
[GCC_PCIE_2_GDSC] = &gcc_pcie_2_gdsc,
[GCC_PCIE_2_PHY_GDSC] = &gcc_pcie_2_phy_gdsc,
[GCC_PCIE_GDSC] = &gcc_pcie_gdsc,
[GCC_PCIE_PHY_GDSC] = &gcc_pcie_phy_gdsc,
[GCC_USB30_GDSC] = &gcc_usb30_gdsc,
[GCC_USB3_PHY_GDSC] = &gcc_usb3_phy_gdsc,
};
static const struct qcom_reset_map gcc_sdx75_resets[] = {
[GCC_EMAC0_BCR] = { 0x71000 },
[GCC_EMAC0_RGMII_CLK_ARES] = { 0x71050, 2 },
[GCC_EMAC1_BCR] = { 0x72000 },
[GCC_EMMC_BCR] = { 0x6b000 },
[GCC_PCIE_1_BCR] = { 0x67000 },
[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x9e700 },
[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x56120 },
[GCC_PCIE_1_PHY_BCR] = { 0x56000 },
[GCC_PCIE_2_BCR] = { 0x68000 },
[GCC_PCIE_2_LINK_DOWN_BCR] = { 0x9f700 },
[GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x6e130 },
[GCC_PCIE_2_PHY_BCR] = { 0x6e000 },
[GCC_PCIE_BCR] = { 0x53000 },
[GCC_PCIE_LINK_DOWN_BCR] = { 0x87000 },
[GCC_PCIE_NOCSR_COM_PHY_BCR] = { 0x88008 },
[GCC_PCIE_PHY_BCR] = { 0x54000 },
[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x88000 },
[GCC_PCIE_PHY_COM_BCR] = { 0x88004 },
[GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x8800c },
[GCC_QUSB2PHY_BCR] = { 0x2a000 },
[GCC_TCSR_PCIE_BCR] = { 0x84000 },
[GCC_USB30_BCR] = { 0x27000 },
[GCC_USB3_PHY_BCR] = { 0x28000 },
[GCC_USB3PHY_PHY_BCR] = { 0x28004 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x29000 },
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s8_clk_src),
};
static const struct regmap_config gcc_sdx75_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x1f41f0,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_sdx75_desc = {
.config = &gcc_sdx75_regmap_config,
.clks = gcc_sdx75_clocks,
.num_clks = ARRAY_SIZE(gcc_sdx75_clocks),
.resets = gcc_sdx75_resets,
.num_resets = ARRAY_SIZE(gcc_sdx75_resets),
.gdscs = gcc_sdx75_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sdx75_gdscs),
};
static const struct of_device_id gcc_sdx75_match_table[] = {
{ .compatible = "qcom,sdx75-gcc" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_sdx75_match_table);
static int gcc_sdx75_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
regmap = qcom_cc_map(pdev, &gcc_sdx75_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
return ret;
/*
* Keep clocks always enabled:
* gcc_ahb_pcie_link_clk
* gcc_xo_pcie_link_clk
*/
regmap_update_bits(regmap, 0x3e004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x3e008, BIT(0), BIT(0));
return qcom_cc_really_probe(pdev, &gcc_sdx75_desc, regmap);
}
static struct platform_driver gcc_sdx75_driver = {
.probe = gcc_sdx75_probe,
.driver = {
.name = "gcc-sdx75",
.of_match_table = gcc_sdx75_match_table,
},
};
static int __init gcc_sdx75_init(void)
{
return platform_driver_register(&gcc_sdx75_driver);
}
subsys_initcall(gcc_sdx75_init);
static void __exit gcc_sdx75_exit(void)
{
platform_driver_unregister(&gcc_sdx75_driver);
}
module_exit(gcc_sdx75_exit);
MODULE_DESCRIPTION("QTI GCC SDX75 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/gcc-sdx75.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Ltd.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/pm_runtime.h>
#include <dt-bindings/clock/qcom,sm8550-dispcc.h>
#include "common.h"
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "reset.h"
#include "gdsc.h"
/* Need to match the order of clocks in DT binding */
enum {
DT_BI_TCXO,
DT_BI_TCXO_AO,
DT_AHB_CLK,
DT_SLEEP_CLK,
DT_DSI0_PHY_PLL_OUT_BYTECLK,
DT_DSI0_PHY_PLL_OUT_DSICLK,
DT_DSI1_PHY_PLL_OUT_BYTECLK,
DT_DSI1_PHY_PLL_OUT_DSICLK,
DT_DP0_PHY_PLL_LINK_CLK,
DT_DP0_PHY_PLL_VCO_DIV_CLK,
DT_DP1_PHY_PLL_LINK_CLK,
DT_DP1_PHY_PLL_VCO_DIV_CLK,
DT_DP2_PHY_PLL_LINK_CLK,
DT_DP2_PHY_PLL_VCO_DIV_CLK,
DT_DP3_PHY_PLL_LINK_CLK,
DT_DP3_PHY_PLL_VCO_DIV_CLK,
};
#define DISP_CC_MISC_CMD 0xF000
enum {
P_BI_TCXO,
P_DISP_CC_PLL0_OUT_MAIN,
P_DISP_CC_PLL1_OUT_EVEN,
P_DISP_CC_PLL1_OUT_MAIN,
P_DP0_PHY_PLL_LINK_CLK,
P_DP0_PHY_PLL_VCO_DIV_CLK,
P_DP1_PHY_PLL_LINK_CLK,
P_DP1_PHY_PLL_VCO_DIV_CLK,
P_DP2_PHY_PLL_LINK_CLK,
P_DP2_PHY_PLL_VCO_DIV_CLK,
P_DP3_PHY_PLL_LINK_CLK,
P_DP3_PHY_PLL_VCO_DIV_CLK,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
P_DSI1_PHY_PLL_OUT_BYTECLK,
P_DSI1_PHY_PLL_OUT_DSICLK,
P_SLEEP_CLK,
};
static struct pll_vco lucid_ole_vco[] = {
{ 249600000, 2000000000, 0 },
};
static const struct alpha_pll_config disp_cc_pll0_config = {
.l = 0xd,
.alpha = 0x6492,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll disp_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_reset_lucid_ole_ops,
},
},
};
static const struct alpha_pll_config disp_cc_pll1_config = {
.l = 0x1f,
.alpha = 0x4000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x82aa299c,
.user_ctl_val = 0x00000000,
.user_ctl_hi_val = 0x00000005,
};
static struct clk_alpha_pll disp_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_ole_vco,
.num_vco = ARRAY_SIZE(lucid_ole_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_pll1",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_reset_lucid_ole_ops,
},
},
};
static const struct parent_map disp_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
};
static const struct clk_parent_data disp_cc_parent_data_0_ao[] = {
{ .index = DT_BI_TCXO_AO },
};
static const struct parent_map disp_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
{ P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
};
static const struct clk_parent_data disp_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
{ .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
{ .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
};
static const struct parent_map disp_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
{ P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
{ .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
{ .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
};
static const struct parent_map disp_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_DP1_PHY_PLL_LINK_CLK, 2 },
{ P_DP2_PHY_PLL_LINK_CLK, 3 },
{ P_DP3_PHY_PLL_LINK_CLK, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DP1_PHY_PLL_LINK_CLK },
{ .index = DT_DP2_PHY_PLL_LINK_CLK },
{ .index = DT_DP3_PHY_PLL_LINK_CLK },
};
static const struct parent_map disp_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_DP0_PHY_PLL_LINK_CLK, 1 },
{ P_DP1_PHY_PLL_VCO_DIV_CLK, 2 },
{ P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
{ P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
};
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DP0_PHY_PLL_LINK_CLK },
{ .index = DT_DP0_PHY_PLL_VCO_DIV_CLK },
{ .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
{ .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
{ .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
};
static const struct parent_map disp_cc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 4 },
{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_5[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
{ .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
};
static const struct parent_map disp_cc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
{ P_DISP_CC_PLL1_OUT_EVEN, 6 },
};
static const struct clk_parent_data disp_cc_parent_data_6[] = {
{ .index = DT_BI_TCXO },
{ .hw = &disp_cc_pll1.clkr.hw },
{ .hw = &disp_cc_pll1.clkr.hw },
};
static const struct parent_map disp_cc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_DP0_PHY_PLL_LINK_CLK, 1 },
{ P_DP1_PHY_PLL_LINK_CLK, 2 },
{ P_DP2_PHY_PLL_LINK_CLK, 3 },
{ P_DP3_PHY_PLL_LINK_CLK, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_7[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DP0_PHY_PLL_LINK_CLK },
{ .index = DT_DP1_PHY_PLL_LINK_CLK },
{ .index = DT_DP2_PHY_PLL_LINK_CLK },
{ .index = DT_DP3_PHY_PLL_LINK_CLK },
};
static const struct parent_map disp_cc_parent_map_8[] = {
{ P_BI_TCXO, 0 },
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
{ P_DISP_CC_PLL1_OUT_EVEN, 6 },
};
static const struct clk_parent_data disp_cc_parent_data_8[] = {
{ .index = DT_BI_TCXO },
{ .hw = &disp_cc_pll0.clkr.hw },
{ .hw = &disp_cc_pll1.clkr.hw },
{ .hw = &disp_cc_pll1.clkr.hw },
};
static const struct parent_map disp_cc_parent_map_9[] = {
{ P_SLEEP_CLK, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_9[] = {
{ .index = DT_SLEEP_CLK },
};
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
.cmd_rcgr = 0x82e8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_6,
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_ahb_clk_src",
.parent_data = disp_cc_parent_data_6,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
.cmd_rcgr = 0x8108,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte0_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
.cmd_rcgr = 0x8124,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte1_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {
.cmd_rcgr = 0x81bc,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_aux_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = {
F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
.cmd_rcgr = 0x8170,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_7,
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_link_clk_src",
.parent_data = disp_cc_parent_data_7,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = {
.cmd_rcgr = 0x818c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_pixel0_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = {
.cmd_rcgr = 0x81a4,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_pixel1_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = {
.cmd_rcgr = 0x8220,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_aux_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {
.cmd_rcgr = 0x8204,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = {
.cmd_rcgr = 0x81d4,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_pixel0_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = {
.cmd_rcgr = 0x81ec,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_pixel1_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = {
.cmd_rcgr = 0x8284,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_aux_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {
.cmd_rcgr = 0x8238,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = {
.cmd_rcgr = 0x8254,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_pixel0_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = {
.cmd_rcgr = 0x826c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_pixel1_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = {
.cmd_rcgr = 0x82d0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_aux_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {
.cmd_rcgr = 0x82b4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_link_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = {
.cmd_rcgr = 0x829c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_pixel0_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.cmd_rcgr = 0x8140,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
.cmd_rcgr = 0x8158,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_5,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_esc1_clk_src",
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(172000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(375000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.cmd_rcgr = 0x80d8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_8,
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_mdp_clk_src",
.parent_data = disp_cc_parent_data_8,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_8),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.cmd_rcgr = 0x80a8,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
.cmd_rcgr = 0x80c0,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_pclk1_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
.cmd_rcgr = 0x80f0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
F(32000, P_SLEEP_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_sleep_clk_src = {
.cmd_rcgr = 0xe05c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_9,
.freq_tbl = ftbl_disp_cc_sleep_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_sleep_clk_src",
.parent_data = disp_cc_parent_data_9,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_9),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 disp_cc_xo_clk_src = {
.cmd_rcgr = 0xe03c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_xo_clk_src",
.parent_data = disp_cc_parent_data_0_ao,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
.reg = 0x8120,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte0_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
.reg = 0x813c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte1_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte1_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = {
.reg = 0x8188,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = {
.reg = 0x821c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = {
.reg = 0x8250,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = {
.reg = 0x82cc,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch disp_cc_mdss_accu_clk = {
.halt_reg = 0xe058,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xe058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_accu_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_ahb1_clk = {
.halt_reg = 0xa020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_ahb1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_ahb_clk = {
.halt_reg = 0x80a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x80a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_clk = {
.halt_reg = 0x8028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
.halt_reg = 0x802c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x802c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte0_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte1_clk = {
.halt_reg = 0x8030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
.halt_reg = 0x8034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte1_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_byte1_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx0_aux_clk = {
.halt_reg = 0x8058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = {
.halt_reg = 0x804c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x804c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_crypto_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx0_link_clk = {
.halt_reg = 0x8040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_link_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = {
.halt_reg = 0x8048,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_link_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = {
.halt_reg = 0x8050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8050,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_pixel0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = {
.halt_reg = 0x8054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_pixel1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = {
.halt_reg = 0x8044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx1_aux_clk = {
.halt_reg = 0x8074,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8074,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = {
.halt_reg = 0x8070,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8070,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_crypto_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx1_link_clk = {
.halt_reg = 0x8064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_link_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = {
.halt_reg = 0x806c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x806c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_link_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = {
.halt_reg = 0x805c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x805c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_pixel0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = {
.halt_reg = 0x8060,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_pixel1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = {
.halt_reg = 0x8068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx2_aux_clk = {
.halt_reg = 0x808c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x808c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx2_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = {
.halt_reg = 0x8088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_crypto_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx2_link_clk = {
.halt_reg = 0x8080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_link_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = {
.halt_reg = 0x8084,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_link_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = {
.halt_reg = 0x8078,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_pixel0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = {
.halt_reg = 0x807c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x807c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx2_pixel1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx3_aux_clk = {
.halt_reg = 0x809c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x809c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx3_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = {
.halt_reg = 0x80a0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x80a0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_crypto_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx3_link_clk = {
.halt_reg = 0x8094,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8094,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_link_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = {
.halt_reg = 0x8098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_link_intf_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = {
.halt_reg = 0x8090,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_dptx3_pixel0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_esc0_clk = {
.halt_reg = 0x8038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_esc1_clk = {
.halt_reg = 0x803c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x803c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_esc1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_esc1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp1_clk = {
.halt_reg = 0xa004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_mdp1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_clk = {
.halt_reg = 0x800c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x800c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_lut1_clk = {
.halt_reg = 0xa010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_mdp_lut1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
.halt_reg = 0x8018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x8018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_mdp_lut_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
.halt_reg = 0xc004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0xc004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_pclk0_clk = {
.halt_reg = 0x8004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_pclk1_clk = {
.halt_reg = 0x8008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_pclk1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_pclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
.halt_reg = 0xc00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_rscc_ahb_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
.halt_reg = 0xc008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xc008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_rscc_vsync_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_vsync1_clk = {
.halt_reg = 0xa01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_vsync1_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_vsync_clk = {
.halt_reg = 0x8024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_sleep_clk = {
.halt_reg = 0xe074,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xe074,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "disp_cc_sleep_clk",
.parent_hws = (const struct clk_hw*[]) {
&disp_cc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x9000,
.pd = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL | RETAIN_FF_ENABLE,
};
static struct gdsc mdss_int2_gdsc = {
.gdscr = 0xb000,
.pd = {
.name = "mdss_int2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL | RETAIN_FF_ENABLE,
};
static struct clk_regmap *disp_cc_sm8550_clocks[] = {
[DISP_CC_MDSS_ACCU_CLK] = &disp_cc_mdss_accu_clk.clkr,
[DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr,
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
[DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
[DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,
[DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
[DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr,
[DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr,
[DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr,
[DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr,
[DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr,
[DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr,
[DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr,
[DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr,
[DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr,
[DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr,
[DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =
&disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr,
[DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr,
[DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr,
[DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr,
[DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr,
[DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr,
[DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr,
[DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr,
[DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr,
[DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr,
[DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =
&disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr,
[DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr,
[DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr,
[DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr,
[DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr,
[DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr,
[DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr,
[DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr,
[DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr,
[DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr,
[DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr,
[DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr,
[DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr,
[DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr,
[DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr,
[DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr,
[DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr,
[DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr,
[DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr,
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
[DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
[DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
[DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr,
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
[DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr,
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
[DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
[DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
[DISP_CC_PLL1] = &disp_cc_pll1.clkr,
[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
[DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
[DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr,
};
static const struct qcom_reset_map disp_cc_sm8550_resets[] = {
[DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
[DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
[DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
};
static struct gdsc *disp_cc_sm8550_gdscs[] = {
[MDSS_GDSC] = &mdss_gdsc,
[MDSS_INT2_GDSC] = &mdss_int2_gdsc,
};
static const struct regmap_config disp_cc_sm8550_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x11008,
.fast_io = true,
};
static struct qcom_cc_desc disp_cc_sm8550_desc = {
.config = &disp_cc_sm8550_regmap_config,
.clks = disp_cc_sm8550_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sm8550_clocks),
.resets = disp_cc_sm8550_resets,
.num_resets = ARRAY_SIZE(disp_cc_sm8550_resets),
.gdscs = disp_cc_sm8550_gdscs,
.num_gdscs = ARRAY_SIZE(disp_cc_sm8550_gdscs),
};
static const struct of_device_id disp_cc_sm8550_match_table[] = {
{ .compatible = "qcom,sm8550-dispcc" },
{ }
};
MODULE_DEVICE_TABLE(of, disp_cc_sm8550_match_table);
static int disp_cc_sm8550_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
regmap = qcom_cc_map(pdev, &disp_cc_sm8550_desc);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
goto err_put_rpm;
}
clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
/* Enable clock gating for MDP clocks */
regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
/*
* Keep clocks always enabled:
* disp_cc_xo_clk
*/
regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0));
ret = qcom_cc_really_probe(pdev, &disp_cc_sm8550_desc, regmap);
if (ret)
goto err_put_rpm;
pm_runtime_put(&pdev->dev);
return 0;
err_put_rpm:
pm_runtime_put_sync(&pdev->dev);
return ret;
}
static struct platform_driver disp_cc_sm8550_driver = {
.probe = disp_cc_sm8550_probe,
.driver = {
.name = "disp_cc-sm8550",
.of_match_table = disp_cc_sm8550_match_table,
},
};
static int __init disp_cc_sm8550_init(void)
{
return platform_driver_register(&disp_cc_sm8550_driver);
}
subsys_initcall(disp_cc_sm8550_init);
static void __exit disp_cc_sm8550_exit(void)
{
platform_driver_unregister(&disp_cc_sm8550_driver);
}
module_exit(disp_cc_sm8550_exit);
MODULE_DESCRIPTION("QTI DISPCC SM8550 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/qcom/dispcc-sm8550.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
* Copyright (c) 2018, Craig Tatlor.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-sdm660.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-alpha-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_XO,
P_SLEEP_CLK,
P_GPLL0,
P_GPLL1,
P_GPLL4,
P_GPLL0_EARLY_DIV,
P_GPLL1_EARLY_DIV,
};
static struct clk_fixed_factor xo = {
.mult = 1,
.div = 1,
.hw.init = &(struct clk_init_data){
.name = "xo",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xo"
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_alpha_pll gpll0_early = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_early",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_fixed_factor gpll0_early_div = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "gpll0_early_div",
.parent_hws = (const struct clk_hw*[]){
&gpll0_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x00000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_hws = (const struct clk_hw*[]){
&gpll0_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
},
};
static struct clk_alpha_pll gpll1_early = {
.offset = 0x1000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gpll1_early",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_fixed_factor gpll1_early_div = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "gpll1_early_div",
.parent_hws = (const struct clk_hw*[]){
&gpll1_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static struct clk_alpha_pll_postdiv gpll1 = {
.offset = 0x1000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll1",
.parent_hws = (const struct clk_hw*[]){
&gpll1_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
},
};
static struct clk_alpha_pll gpll4_early = {
.offset = 0x77000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gpll4_early",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x77000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data)
{
.name = "gpll4",
.parent_hws = (const struct clk_hw*[]){
&gpll4_early.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ops,
},
};
static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL0_EARLY_DIV, 6 },
};
static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};
static const struct parent_map gcc_parent_map_xo_gpll0[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
};
static const struct clk_parent_data gcc_parent_data_xo_gpll0[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
};
static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_SLEEP_CLK, 5 },
{ P_GPLL0_EARLY_DIV, 6 },
};
static const struct clk_parent_data gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .fw_name = "sleep_clk" },
{ .hw = &gpll0_early_div.hw },
};
static const struct parent_map gcc_parent_map_xo_sleep_clk[] = {
{ P_XO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_xo_sleep_clk[] = {
{ .fw_name = "xo" },
{ .fw_name = "sleep_clk" },
};
static const struct parent_map gcc_parent_map_xo_gpll4[] = {
{ P_XO, 0 },
{ P_GPLL4, 5 },
};
static const struct clk_parent_data gcc_parent_data_xo_gpll4[] = {
{ .fw_name = "xo" },
{ .hw = &gpll4.clkr.hw },
};
static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL0_EARLY_DIV, 3 },
{ P_GPLL1, 4 },
{ P_GPLL4, 5 },
{ P_GPLL1_EARLY_DIV, 6 },
};
static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_early_div.hw },
{ .hw = &gpll1.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll1_early_div.hw },
};
static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 5 },
{ P_GPLL0_EARLY_DIV, 6 },
};
static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &gpll0_early_div.hw },
};
static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL0_EARLY_DIV, 2 },
{ P_GPLL4, 5 },
};
static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_early_div.hw },
{ .hw = &gpll4.clkr.hw },
};
static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x19020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(15000000, P_GPLL0, 10, 1, 4),
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0, 12, 1, 2),
F(50000000, P_GPLL0, 12, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x1900c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x1b020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x1b00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x1d020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x1d00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x1f020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x1f00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
F(3686400, P_GPLL0, 1, 96, 15625),
F(7372800, P_GPLL0, 1, 192, 15625),
F(14745600, P_GPLL0, 1, 384, 15625),
F(16000000, P_GPLL0, 5, 2, 15),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 5, 1, 5),
F(32000000, P_GPLL0, 1, 4, 75),
F(40000000, P_GPLL0, 15, 0, 0),
F(46400000, P_GPLL0, 1, 29, 375),
F(48000000, P_GPLL0, 12.5, 0, 0),
F(51200000, P_GPLL0, 1, 32, 375),
F(56000000, P_GPLL0, 1, 7, 75),
F(58982400, P_GPLL0, 1, 1536, 15625),
F(60000000, P_GPLL0, 10, 0, 0),
F(63157895, P_GPLL0, 9.5, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x1a00c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x1c00c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x26020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_i2c_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x2600c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_spi_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x28020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_i2c_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x2800c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_spi_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x2a020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_i2c_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x2a00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_spi_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x2c020,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_i2c_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x2c00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_spi_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
.cmd_rcgr = 0x2700c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart1_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
.cmd_rcgr = 0x2900c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart2_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gp1_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x64004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
.freq_tbl = ftbl_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp2_clk_src = {
.cmd_rcgr = 0x65004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
.freq_tbl = ftbl_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp3_clk_src = {
.cmd_rcgr = 0x66004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
.freq_tbl = ftbl_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {
F(300000000, P_GPLL0, 2, 0, 0),
F(600000000, P_GPLL0, 1, 0, 0),
{ }
};
static struct clk_rcg2 hmss_gpll0_clk_src = {
.cmd_rcgr = 0x4805c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_hmss_gpll0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "hmss_gpll0_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] = {
F(384000000, P_GPLL4, 4, 0, 0),
F(768000000, P_GPLL4, 2, 0, 0),
F(1536000000, P_GPLL4, 1, 0, 0),
{ }
};
static struct clk_rcg2 hmss_gpll4_clk_src = {
.cmd_rcgr = 0x48074,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll4,
.freq_tbl = ftbl_hmss_gpll4_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "hmss_gpll4_clk_src",
.parent_data = gcc_parent_data_xo_gpll4,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll4),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 hmss_rbcpr_clk_src = {
.cmd_rcgr = 0x48044,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0,
.freq_tbl = ftbl_hmss_rbcpr_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "hmss_rbcpr_clk_src",
.parent_data = gcc_parent_data_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_pdm2_clk_src[] = {
F(60000000, P_GPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 pdm2_clk_src = {
.cmd_rcgr = 0x33010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(80200000, P_GPLL1_EARLY_DIV, 5, 0, 0),
F(160400000, P_GPLL1, 5, 0, 0),
F(267333333, P_GPLL1, 3, 0, 0),
{ }
};
static struct clk_rcg2 qspi_ser_clk_src = {
.cmd_rcgr = 0x4d00c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
.freq_tbl = ftbl_qspi_ser_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "qspi_ser_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(192000000, P_GPLL4, 8, 0, 0),
F(384000000, P_GPLL4, 4, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x1602c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div,
.freq_tbl = ftbl_sdcc1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(300000000, P_GPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x16010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_sdcc1_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_ice_core_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(192000000, P_GPLL4, 8, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
{ }
};
static struct clk_rcg2 sdcc2_apps_clk_src = {
.cmd_rcgr = 0x14010,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4,
.freq_tbl = ftbl_sdcc2_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(240000000, P_GPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 ufs_axi_clk_src = {
.cmd_rcgr = 0x75018,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_ufs_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "ufs_axi_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(300000000, P_GPLL0, 2, 0, 0),
{ }
};
static struct clk_rcg2 ufs_ice_core_clk_src = {
.cmd_rcgr = 0x76010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_ufs_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "ufs_ice_core_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 ufs_phy_aux_clk_src = {
.cmd_rcgr = 0x76044,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_sleep_clk,
.freq_tbl = ftbl_hmss_rbcpr_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "ufs_phy_aux_clk_src",
.parent_data = gcc_parent_data_xo_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = {
F(37500000, P_GPLL0_EARLY_DIV, 8, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 ufs_unipro_core_clk_src = {
.cmd_rcgr = 0x76028,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_ufs_unipro_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "ufs_unipro_core_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(60000000, P_GPLL0, 10, 0, 0),
F(120000000, P_GPLL0, 5, 0, 0),
{ }
};
static struct clk_rcg2 usb20_master_clk_src = {
.cmd_rcgr = 0x2f010,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_usb20_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb20_master_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(60000000, P_GPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 usb20_mock_utmi_clk_src = {
.cmd_rcgr = 0x2f024,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_usb20_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb20_mock_utmi_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(66666667, P_GPLL0_EARLY_DIV, 4.5, 0, 0),
F(120000000, P_GPLL0, 5, 0, 0),
F(133333333, P_GPLL0, 4.5, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(240000000, P_GPLL0, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 usb30_master_clk_src = {
.cmd_rcgr = 0xf014,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_usb30_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_master_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(40000000, P_GPLL0_EARLY_DIV, 7.5, 0, 0),
F(60000000, P_GPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 usb30_mock_utmi_clk_src = {
.cmd_rcgr = 0xf028,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_mock_utmi_clk_src",
.parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
F(1200000, P_XO, 16, 0, 0),
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 usb3_phy_aux_clk_src = {
.cmd_rcgr = 0x5000c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_xo_sleep_clk,
.freq_tbl = ftbl_usb3_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb3_phy_aux_clk_src",
.parent_data = gcc_parent_data_xo_sleep_clk,
.num_parents = ARRAY_SIZE(gcc_parent_data_xo_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_aggre2_ufs_axi_clk = {
.halt_reg = 0x75034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x75034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre2_ufs_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&ufs_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre2_usb3_axi_clk = {
.halt_reg = 0xf03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_aggre2_usb3_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_bimc_gfx_clk = {
.halt_reg = 0x7106c,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x7106c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_bimc_hmss_axi_clk = {
.halt_reg = 0x48004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_hmss_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
.halt_reg = 0x4401c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4401c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_mss_q6_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x17004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x19008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x19008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x19004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x19004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x1b008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1b008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x1b004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1b004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x1d008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1d008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x1d004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1d004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.halt_reg = 0x1f008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1f008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.halt_reg = 0x1f004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1f004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x1a004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x1c004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1c004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp1_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_ahb_clk = {
.halt_reg = 0x25004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
.halt_reg = 0x26008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x26008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp2_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
.halt_reg = 0x26004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x26004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp2_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
.halt_reg = 0x28008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x28008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp2_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
.halt_reg = 0x28004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x28004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp2_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
.halt_reg = 0x2a008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2a008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp2_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
.halt_reg = 0x2a004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp2_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
.halt_reg = 0x2c008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2c008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp2_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
.halt_reg = 0x2c004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2c004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp2_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart1_apps_clk = {
.halt_reg = 0x27004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x27004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart1_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp2_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart2_apps_clk = {
.halt_reg = 0x29004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x29004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart2_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&blsp2_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x38004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb2_axi_clk = {
.halt_reg = 0x5058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb2_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&usb20_master_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
.halt_reg = 0x5018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_dcc_ahb_clk = {
.halt_reg = 0x84004,
.clkr = {
.enable_reg = 0x84004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_dcc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x64000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x64000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x65000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x65000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x66000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x66000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_bimc_gfx_clk = {
.halt_reg = 0x71010,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x71010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_bimc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_cfg_ahb_clk = {
.halt_reg = 0x71004,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x71004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_cfg_ahb_clk",
.ops = &clk_branch2_ops,
.flags = CLK_IS_CRITICAL,
},
},
};
static struct clk_branch gcc_gpu_gpll0_clk = {
.halt_reg = 0x5200c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_div_clk = {
.halt_reg = 0x5200c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpll0_early_div.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_hmss_dvm_bus_clk = {
.halt_reg = 0x4808c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4808c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_hmss_dvm_bus_clk",
.ops = &clk_branch2_ops,
.flags = CLK_IGNORE_UNUSED,
},
},
};
static struct clk_branch gcc_hmss_rbcpr_clk = {
.halt_reg = 0x48008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x48008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_hmss_rbcpr_clk",
.parent_hws = (const struct clk_hw*[]) {
&hmss_rbcpr_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mmss_gpll0_clk = {
.halt_reg = 0x5200c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_mmss_gpll0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mmss_gpll0_div_clk = {
.halt_reg = 0x5200c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mmss_gpll0_div_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpll0_early_div.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
.halt_reg = 0x9004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mmss_noc_cfg_ahb_clk",
.ops = &clk_branch2_ops,
/*
* Any access to mmss depends on this clock.
* Gating this clock has been shown to crash the system
* when mmssnoc_axi_rpm_clk is inited in rpmcc.
*/
.flags = CLK_IS_CRITICAL,
},
},
};
static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
.halt_reg = 0x9000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mmss_sys_noc_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_cfg_ahb_clk = {
.halt_reg = 0x8a000,
.clkr = {
.enable_reg = 0x8a000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
.halt_reg = 0x8a004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x8a004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_mnoc_bimc_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.halt_reg = 0x8a040,
.clkr = {
.enable_reg = 0x8a040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_q6_bimc_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_snoc_axi_clk = {
.halt_reg = 0x8a03c,
.clkr = {
.enable_reg = 0x8a03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_snoc_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x3300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3300c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]) {
&pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x33004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x33004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x34004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qspi_ahb_clk = {
.halt_reg = 0x4d004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qspi_ser_clk = {
.halt_reg = 0x4d008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4d008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_ser_clk",
.parent_hws = (const struct clk_hw*[]) {
&qspi_ser_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_rx0_usb2_clkref_clk = {
.halt_reg = 0x88018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x88018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_rx0_usb2_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_rx1_usb2_clkref_clk = {
.halt_reg = 0x88014,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x88014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_rx1_usb2_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x16008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x16004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x16004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0x1600c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&sdcc1_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x14008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x14004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_ahb_clk = {
.halt_reg = 0x7500c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7500c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_axi_clk = {
.halt_reg = 0x75008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x75008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&ufs_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_clkref_clk = {
.halt_reg = 0x88008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x88008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_ice_core_clk = {
.halt_reg = 0x7600c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7600c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_ice_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&ufs_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_aux_clk = {
.halt_reg = 0x76040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x76040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&ufs_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
.halt_reg = 0x75014,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x75014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
.halt_reg = 0x7605c,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x7605c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_symbol_1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
.halt_reg = 0x75010,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x75010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_unipro_core_clk = {
.halt_reg = 0x76008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x76008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&ufs_unipro_core_clk_src.clkr.hw,
},
.flags = CLK_SET_RATE_PARENT,
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb20_master_clk = {
.halt_reg = 0x2f004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2f004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb20_master_clk",
.parent_hws = (const struct clk_hw*[]) {
&usb20_master_clk_src.clkr.hw,
},
.flags = CLK_SET_RATE_PARENT,
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb20_mock_utmi_clk = {
.halt_reg = 0x2f00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2f00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb20_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&usb20_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb20_sleep_clk = {
.halt_reg = 0x2f008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2f008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb20_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_master_clk = {
.halt_reg = 0xf008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_master_clk",
.parent_hws = (const struct clk_hw*[]) {
&usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_mock_utmi_clk = {
.halt_reg = 0xf010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&usb30_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sleep_clk = {
.halt_reg = 0xf00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xf00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_clkref_clk = {
.halt_reg = 0x8800c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x8800c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_clkref_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_phy_aux_clk = {
.halt_reg = 0x50000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x50000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&usb3_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_phy_pipe_clk = {
.halt_reg = 0x50004,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x50004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
.halt_reg = 0x6a004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_phy_cfg_ahb2phy_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc ufs_gdsc = {
.gdscr = 0x75004,
.gds_hw_ctrl = 0x0,
.pd = {
.name = "ufs_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc usb_30_gdsc = {
.gdscr = 0xf004,
.gds_hw_ctrl = 0x0,
.pd = {
.name = "usb_30_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x6b004,
.gds_hw_ctrl = 0x0,
.pd = {
.name = "pcie_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct clk_hw *gcc_sdm660_hws[] = {
&xo.hw,
&gpll0_early_div.hw,
&gpll1_early_div.hw,
};
static struct clk_regmap *gcc_sdm660_clocks[] = {
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
[BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
[BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
[BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
[BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
[BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
[BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
[BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
[BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
[BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
[GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
[GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
[GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
[GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
[GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
[GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
[GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
[GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
[GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
[GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CFG_NOC_USB2_AXI_CLK] = &gcc_cfg_noc_usb2_axi_clk.clkr,
[GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
[GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
[GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
[GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
[GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
[GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
[GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
[GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
[GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
[GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
[GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
[GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
[GCC_RX0_USB2_CLKREF_CLK] = &gcc_rx0_usb2_clkref_clk.clkr,
[GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
[GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
[GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
[GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
[GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
[GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
[GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
[GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
[GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
[GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
[GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
[GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
[GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
[GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
[GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
[GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL0_EARLY] = &gpll0_early.clkr,
[GPLL1] = &gpll1.clkr,
[GPLL1_EARLY] = &gpll1_early.clkr,
[GPLL4] = &gpll4.clkr,
[GPLL4_EARLY] = &gpll4_early.clkr,
[HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
[HMSS_GPLL4_CLK_SRC] = &hmss_gpll4_clk_src.clkr,
[HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
[QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
[UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
[UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
[UFS_PHY_AUX_CLK_SRC] = &ufs_phy_aux_clk_src.clkr,
[UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr,
[USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
[USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
[USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
[USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
};
static struct gdsc *gcc_sdm660_gdscs[] = {
[UFS_GDSC] = &ufs_gdsc,
[USB_30_GDSC] = &usb_30_gdsc,
[PCIE_0_GDSC] = &pcie_0_gdsc,
};
static const struct qcom_reset_map gcc_sdm660_resets[] = {
[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
[GCC_UFS_BCR] = { 0x75000 },
[GCC_USB3_DP_PHY_BCR] = { 0x50028 },
[GCC_USB3_PHY_BCR] = { 0x50020 },
[GCC_USB3PHY_PHY_BCR] = { 0x50024 },
[GCC_USB_20_BCR] = { 0x2f000 },
[GCC_USB_30_BCR] = { 0xf000 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
[GCC_MSS_RESTART] = { 0x79000 },
};
static const struct regmap_config gcc_sdm660_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x94000,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_sdm660_desc = {
.config = &gcc_sdm660_regmap_config,
.clks = gcc_sdm660_clocks,
.num_clks = ARRAY_SIZE(gcc_sdm660_clocks),
.resets = gcc_sdm660_resets,
.num_resets = ARRAY_SIZE(gcc_sdm660_resets),
.gdscs = gcc_sdm660_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sdm660_gdscs),
.clk_hws = gcc_sdm660_hws,
.num_clk_hws = ARRAY_SIZE(gcc_sdm660_hws),
};
static const struct of_device_id gcc_sdm660_match_table[] = {
{ .compatible = "qcom,gcc-sdm630" },
{ .compatible = "qcom,gcc-sdm660" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_sdm660_match_table);
static int gcc_sdm660_probe(struct platform_device *pdev)
{
int ret;
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gcc_sdm660_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/*
* Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
* turned off by hardware during certain apps low power modes.
*/
ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
if (ret)
return ret;
return qcom_cc_really_probe(pdev, &gcc_sdm660_desc, regmap);
}
static struct platform_driver gcc_sdm660_driver = {
.probe = gcc_sdm660_probe,
.driver = {
.name = "gcc-sdm660",
.of_match_table = gcc_sdm660_match_table,
},
};
static int __init gcc_sdm660_init(void)
{
return platform_driver_register(&gcc_sdm660_driver);
}
core_initcall_sync(gcc_sdm660_init);
static void __exit gcc_sdm660_exit(void)
{
platform_driver_unregister(&gcc_sdm660_driver);
}
module_exit(gcc_sdm660_exit);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("QCOM GCC sdm660 Driver");
| linux-master | drivers/clk/qcom/gcc-sdm660.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,camcc-sc7180.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_CAM_CC_PLL0_OUT_EVEN,
P_CAM_CC_PLL1_OUT_EVEN,
P_CAM_CC_PLL2_OUT_AUX,
P_CAM_CC_PLL2_OUT_EARLY,
P_CAM_CC_PLL3_OUT_MAIN,
};
static const struct pll_vco agera_vco[] = {
{ 600000000, 3300000000UL, 0 },
};
static const struct pll_vco fabia_vco[] = {
{ 249600000, 2000000000UL, 0 },
};
/* 600MHz configuration */
static const struct alpha_pll_config cam_cc_pll0_config = {
.l = 0x1f,
.alpha = 0x4000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002067,
.test_ctl_val = 0x40000000,
.user_ctl_hi_val = 0x00004805,
.user_ctl_val = 0x00000001,
};
static struct clk_alpha_pll cam_cc_pll0 = {
.offset = 0x0,
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
};
/* 860MHz configuration */
static const struct alpha_pll_config cam_cc_pll1_config = {
.l = 0x2a,
.alpha = 0x1555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002067,
.test_ctl_val = 0x40000000,
.user_ctl_hi_val = 0x00004805,
};
static struct clk_alpha_pll cam_cc_pll1 = {
.offset = 0x1000,
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll1",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
};
/* 1920MHz configuration */
static const struct alpha_pll_config cam_cc_pll2_config = {
.l = 0x64,
.config_ctl_val = 0x20000800,
.config_ctl_hi_val = 0x400003D2,
.test_ctl_val = 0x04000400,
.test_ctl_hi_val = 0x00004000,
.user_ctl_val = 0x0000030F,
};
static struct clk_alpha_pll cam_cc_pll2 = {
.offset = 0x2000,
.vco_table = agera_vco,
.num_vco = ARRAY_SIZE(agera_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll2",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_agera_ops,
},
},
};
static struct clk_fixed_factor cam_cc_pll2_out_early = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll2_out_early",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_pll2.clkr.hw,
},
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
};
static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux[] = {
{ 0x3, 4 },
{ }
};
static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = {
.offset = 0x2000,
.post_div_shift = 8,
.post_div_table = post_div_table_cam_cc_pll2_out_aux,
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux),
.width = 2,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll2_out_aux",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_pll2.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_ops,
},
};
/* 1080MHz configuration */
static const struct alpha_pll_config cam_cc_pll3_config = {
.l = 0x38,
.alpha = 0x4000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002067,
.test_ctl_val = 0x40000000,
.user_ctl_hi_val = 0x00004805,
};
static struct clk_alpha_pll cam_cc_pll3 = {
.offset = 0x3000,
.vco_table = fabia_vco,
.num_vco = ARRAY_SIZE(fabia_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll3",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
};
static const struct parent_map cam_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll1.clkr.hw },
{ .hw = &cam_cc_pll0.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL2_OUT_AUX, 1 },
};
static const struct clk_parent_data cam_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll2_out_aux.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL2_OUT_EARLY, 4 },
{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_2[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll2_out_early.hw },
{ .hw = &cam_cc_pll3.clkr.hw },
{ .hw = &cam_cc_pll0.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
{ P_CAM_CC_PLL2_OUT_EARLY, 4 },
{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_3[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll1.clkr.hw },
{ .hw = &cam_cc_pll2_out_early.hw },
{ .hw = &cam_cc_pll3.clkr.hw },
{ .hw = &cam_cc_pll0.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll3.clkr.hw },
{ .hw = &cam_cc_pll0.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_5[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll0.clkr.hw },
};
static const struct parent_map cam_cc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data cam_cc_parent_data_6[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &cam_cc_pll1.clkr.hw },
{ .hw = &cam_cc_pll3.clkr.hw },
{ .hw = &cam_cc_pll0.clkr.hw },
};
static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_bps_clk_src = {
.cmd_rcgr = 0x6010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_2,
.freq_tbl = ftbl_cam_cc_bps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_clk_src",
.parent_data = cam_cc_parent_data_2,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_cci_0_clk_src = {
.cmd_rcgr = 0xb0d8,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_5,
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_0_clk_src",
.parent_data = cam_cc_parent_data_5,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_cci_1_clk_src = {
.cmd_rcgr = 0xb14c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_5,
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_1_clk_src",
.parent_data = cam_cc_parent_data_5,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0),
F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
.cmd_rcgr = 0x9064,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_3,
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_cphy_rx_clk_src",
.parent_data = cam_cc_parent_data_3,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
.cmd_rcgr = 0x5004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi0phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
.cmd_rcgr = 0x5028,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi1phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
.cmd_rcgr = 0x504c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi2phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
.cmd_rcgr = 0x5070,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi3phytimer_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
.cmd_rcgr = 0x603c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_fast_ahb_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_icp_clk_src = {
.cmd_rcgr = 0xb088,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_2,
.freq_tbl = ftbl_cam_cc_icp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_icp_clk_src",
.parent_data = cam_cc_parent_data_2,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_0_clk_src = {
.cmd_rcgr = 0x9010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_4,
.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_clk_src",
.parent_data = cam_cc_parent_data_4,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = {
F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0),
F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
.cmd_rcgr = 0x903c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_3,
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_csid_clk_src",
.parent_data = cam_cc_parent_data_3,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_ife_1_clk_src = {
.cmd_rcgr = 0xa010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_4,
.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_clk_src",
.parent_data = cam_cc_parent_data_4,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
.cmd_rcgr = 0xa034,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_3,
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_csid_clk_src",
.parent_data = cam_cc_parent_data_3,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
.cmd_rcgr = 0xb004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_4,
.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_clk_src",
.parent_data = cam_cc_parent_data_4,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
.cmd_rcgr = 0xb024,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_3,
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_csid_clk_src",
.parent_data = cam_cc_parent_data_3,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = {
F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
.cmd_rcgr = 0x7010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_2,
.freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_clk_src",
.parent_data = cam_cc_parent_data_2,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = {
F(66666667, P_CAM_CC_PLL0_OUT_EVEN, 9, 0, 0),
F(133333333, P_CAM_CC_PLL0_OUT_EVEN, 4.5, 0, 0),
F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0),
F(320000000, P_CAM_CC_PLL2_OUT_EARLY, 3, 0, 0),
F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_jpeg_clk_src = {
.cmd_rcgr = 0xb04c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_2,
.freq_tbl = ftbl_cam_cc_jpeg_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_jpeg_clk_src",
.parent_data = cam_cc_parent_data_2,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = {
F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0),
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_lrme_clk_src = {
.cmd_rcgr = 0xb0f8,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_6,
.freq_tbl = ftbl_cam_cc_lrme_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_lrme_clk_src",
.parent_data = cam_cc_parent_data_6,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24000000, P_CAM_CC_PLL2_OUT_AUX, 10, 1, 2),
F(64000000, P_CAM_CC_PLL2_OUT_AUX, 7.5, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_mclk0_clk_src = {
.cmd_rcgr = 0x4004,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk0_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_mclk1_clk_src = {
.cmd_rcgr = 0x4024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk1_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_mclk2_clk_src = {
.cmd_rcgr = 0x4044,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk2_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_mclk3_clk_src = {
.cmd_rcgr = 0x4064,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk3_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_cc_mclk4_clk_src = {
.cmd_rcgr = 0x4084,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_cc_parent_map_1,
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk4_clk_src",
.parent_data = cam_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
{ }
};
static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
.cmd_rcgr = 0x6058,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_cc_parent_map_0,
.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_slow_ahb_clk_src",
.parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_branch cam_cc_bps_ahb_clk = {
.halt_reg = 0x6070,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6070,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_bps_areg_clk = {
.halt_reg = 0x6054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_areg_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_bps_axi_clk = {
.halt_reg = 0x6038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_bps_clk = {
.halt_reg = 0x6028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x6028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_bps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_camnoc_axi_clk = {
.halt_reg = 0xb124,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb124,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_camnoc_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cci_0_clk = {
.halt_reg = 0xb0f0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb0f0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_0_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cci_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cci_1_clk = {
.halt_reg = 0xb164,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb164,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_1_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cci_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_core_ahb_clk = {
.halt_reg = 0xb144,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0xb144,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_core_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_cpas_ahb_clk = {
.halt_reg = 0xb11c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb11c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_cpas_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi0phytimer_clk = {
.halt_reg = 0x501c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x501c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi0phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_csi0phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi1phytimer_clk = {
.halt_reg = 0x5040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi1phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_csi1phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi2phytimer_clk = {
.halt_reg = 0x5064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi2phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_csi2phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csi3phytimer_clk = {
.halt_reg = 0x5088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi3phytimer_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_csi3phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy0_clk = {
.halt_reg = 0x5020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy0_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy1_clk = {
.halt_reg = 0x5044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy1_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy2_clk = {
.halt_reg = 0x5068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy2_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_csiphy3_clk = {
.halt_reg = 0x508c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x508c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy3_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_icp_clk = {
.halt_reg = 0xb0a0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb0a0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_icp_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_icp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_axi_clk = {
.halt_reg = 0x9080,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9080,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_clk = {
.halt_reg = 0x9028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
.halt_reg = 0x907c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x907c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_csid_clk = {
.halt_reg = 0x9054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_csid_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_0_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_0_dsp_clk = {
.halt_reg = 0x9038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_dsp_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_axi_clk = {
.halt_reg = 0xa058,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_clk = {
.halt_reg = 0xa028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
.halt_reg = 0xa054,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_csid_clk = {
.halt_reg = 0xa04c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa04c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_csid_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_1_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_1_dsp_clk = {
.halt_reg = 0xa030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_dsp_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_clk = {
.halt_reg = 0xb01c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb01c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_lite_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
.halt_reg = 0xb044,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb044,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_cphy_rx_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ife_lite_csid_clk = {
.halt_reg = 0xb03c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb03c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_csid_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ife_lite_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_0_ahb_clk = {
.halt_reg = 0x7040,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7040,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_0_areg_clk = {
.halt_reg = 0x703c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x703c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_areg_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_0_axi_clk = {
.halt_reg = 0x7038,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_ipe_0_clk = {
.halt_reg = 0x7028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x7028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_ipe_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_jpeg_clk = {
.halt_reg = 0xb064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_jpeg_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_jpeg_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_lrme_clk = {
.halt_reg = 0xb110,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb110,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_lrme_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_lrme_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk0_clk = {
.halt_reg = 0x401c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x401c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk1_clk = {
.halt_reg = 0x403c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x403c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk1_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk2_clk = {
.halt_reg = 0x405c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x405c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk2_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_mclk2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk3_clk = {
.halt_reg = 0x407c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x407c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk3_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_mclk3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_mclk4_clk = {
.halt_reg = 0x409c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x409c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk4_clk",
.parent_hws = (const struct clk_hw*[]){
&cam_cc_mclk4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_soc_ahb_clk = {
.halt_reg = 0xb140,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb140,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_soc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_cc_sys_tmr_clk = {
.halt_reg = 0xb0a8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xb0a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_sys_tmr_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc titan_top_gdsc = {
.gdscr = 0xb134,
.pd = {
.name = "titan_top_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc bps_gdsc = {
.gdscr = 0x6004,
.pd = {
.name = "bps_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &titan_top_gdsc.pd,
.flags = HW_CTRL,
};
static struct gdsc ife_0_gdsc = {
.gdscr = 0x9004,
.pd = {
.name = "ife_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &titan_top_gdsc.pd,
};
static struct gdsc ife_1_gdsc = {
.gdscr = 0xa004,
.pd = {
.name = "ife_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.parent = &titan_top_gdsc.pd,
};
static struct gdsc ipe_0_gdsc = {
.gdscr = 0x7004,
.pd = {
.name = "ipe_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL,
.parent = &titan_top_gdsc.pd,
};
static struct clk_hw *cam_cc_sc7180_hws[] = {
[CAM_CC_PLL2_OUT_EARLY] = &cam_cc_pll2_out_early.hw,
};
static struct clk_regmap *cam_cc_sc7180_clocks[] = {
[CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
[CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr,
[CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr,
[CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
[CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
[CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
[CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
[CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
[CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
[CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
[CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr,
[CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
[CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
[CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr,
[CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr,
[CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr,
[CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
[CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr,
[CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
[CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
[CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr,
[CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr,
[CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr,
[CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
[CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
[CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
[CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
[CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
[CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
[CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr,
[CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr,
[CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr,
[CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr,
[CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr,
[CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
[CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
[CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr,
[CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr,
[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
[CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
[CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
[CAM_CC_PLL1] = &cam_cc_pll1.clkr,
[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
[CAM_CC_PLL2_OUT_AUX] = &cam_cc_pll2_out_aux.clkr,
[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
[CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr,
[CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr,
};
static struct gdsc *cam_cc_sc7180_gdscs[] = {
[BPS_GDSC] = &bps_gdsc,
[IFE_0_GDSC] = &ife_0_gdsc,
[IFE_1_GDSC] = &ife_1_gdsc,
[IPE_0_GDSC] = &ipe_0_gdsc,
[TITAN_TOP_GDSC] = &titan_top_gdsc,
};
static const struct regmap_config cam_cc_sc7180_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xd028,
.fast_io = true,
};
static const struct qcom_cc_desc cam_cc_sc7180_desc = {
.config = &cam_cc_sc7180_regmap_config,
.clk_hws = cam_cc_sc7180_hws,
.num_clk_hws = ARRAY_SIZE(cam_cc_sc7180_hws),
.clks = cam_cc_sc7180_clocks,
.num_clks = ARRAY_SIZE(cam_cc_sc7180_clocks),
.gdscs = cam_cc_sc7180_gdscs,
.num_gdscs = ARRAY_SIZE(cam_cc_sc7180_gdscs),
};
static const struct of_device_id cam_cc_sc7180_match_table[] = {
{ .compatible = "qcom,sc7180-camcc" },
{ }
};
MODULE_DEVICE_TABLE(of, cam_cc_sc7180_match_table);
static int cam_cc_sc7180_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret < 0)
return ret;
ret = devm_pm_clk_create(&pdev->dev);
if (ret < 0)
return ret;
ret = pm_clk_add(&pdev->dev, "xo");
if (ret < 0) {
dev_err(&pdev->dev, "Failed to acquire XO clock\n");
return ret;
}
ret = pm_clk_add(&pdev->dev, "iface");
if (ret < 0) {
dev_err(&pdev->dev, "Failed to acquire iface clock\n");
return ret;
}
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
regmap = qcom_cc_map(pdev, &cam_cc_sc7180_desc);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
pm_runtime_put(&pdev->dev);
return ret;
}
clk_fabia_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
clk_fabia_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
clk_agera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
ret = qcom_cc_really_probe(pdev, &cam_cc_sc7180_desc, regmap);
pm_runtime_put(&pdev->dev);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to register CAM CC clocks\n");
return ret;
}
return 0;
}
static const struct dev_pm_ops cam_cc_pm_ops = {
SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
};
static struct platform_driver cam_cc_sc7180_driver = {
.probe = cam_cc_sc7180_probe,
.driver = {
.name = "cam_cc-sc7180",
.of_match_table = cam_cc_sc7180_match_table,
.pm = &cam_cc_pm_ops,
},
};
static int __init cam_cc_sc7180_init(void)
{
return platform_driver_register(&cam_cc_sc7180_driver);
}
subsys_initcall(cam_cc_sc7180_init);
static void __exit cam_cc_sc7180_exit(void)
{
platform_driver_unregister(&cam_cc_sc7180_driver);
}
module_exit(cam_cc_sc7180_exit);
MODULE_DESCRIPTION("QTI CAM_CC SC7180 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/camcc-sc7180.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved.
*/
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/ktime.h>
#include <linux/pm_domain.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include "gdsc.h"
#define PWR_ON_MASK BIT(31)
#define EN_REST_WAIT_MASK GENMASK_ULL(23, 20)
#define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16)
#define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12)
#define SW_OVERRIDE_MASK BIT(2)
#define HW_CONTROL_MASK BIT(1)
#define SW_COLLAPSE_MASK BIT(0)
#define GMEM_CLAMP_IO_MASK BIT(0)
#define GMEM_RESET_MASK BIT(4)
/* CFG_GDSCR */
#define GDSC_POWER_UP_COMPLETE BIT(16)
#define GDSC_POWER_DOWN_COMPLETE BIT(15)
#define GDSC_RETAIN_FF_ENABLE BIT(11)
#define CFG_GDSCR_OFFSET 0x4
/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
#define EN_REST_WAIT_VAL 0x2
#define EN_FEW_WAIT_VAL 0x8
#define CLK_DIS_WAIT_VAL 0x2
/* Transition delay shifts */
#define EN_REST_WAIT_SHIFT 20
#define EN_FEW_WAIT_SHIFT 16
#define CLK_DIS_WAIT_SHIFT 12
#define RETAIN_MEM BIT(14)
#define RETAIN_PERIPH BIT(13)
#define STATUS_POLL_TIMEOUT_US 1500
#define TIMEOUT_US 500
#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
enum gdsc_status {
GDSC_OFF,
GDSC_ON
};
/* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
{
unsigned int reg;
u32 val;
int ret;
if (sc->flags & POLL_CFG_GDSCR)
reg = sc->gdscr + CFG_GDSCR_OFFSET;
else if (sc->gds_hw_ctrl)
reg = sc->gds_hw_ctrl;
else
reg = sc->gdscr;
ret = regmap_read(sc->regmap, reg, &val);
if (ret)
return ret;
if (sc->flags & POLL_CFG_GDSCR) {
switch (status) {
case GDSC_ON:
return !!(val & GDSC_POWER_UP_COMPLETE);
case GDSC_OFF:
return !!(val & GDSC_POWER_DOWN_COMPLETE);
}
}
switch (status) {
case GDSC_ON:
return !!(val & PWR_ON_MASK);
case GDSC_OFF:
return !(val & PWR_ON_MASK);
}
return -EINVAL;
}
static int gdsc_hwctrl(struct gdsc *sc, bool en)
{
u32 val = en ? HW_CONTROL_MASK : 0;
return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
}
static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
{
ktime_t start;
start = ktime_get();
do {
if (gdsc_check_status(sc, status))
return 0;
} while (ktime_us_delta(ktime_get(), start) < STATUS_POLL_TIMEOUT_US);
if (gdsc_check_status(sc, status))
return 0;
return -ETIMEDOUT;
}
static int gdsc_update_collapse_bit(struct gdsc *sc, bool val)
{
u32 reg, mask;
int ret;
if (sc->collapse_mask) {
reg = sc->collapse_ctrl;
mask = sc->collapse_mask;
} else {
reg = sc->gdscr;
mask = SW_COLLAPSE_MASK;
}
ret = regmap_update_bits(sc->regmap, reg, mask, val ? mask : 0);
if (ret)
return ret;
return 0;
}
static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status,
bool wait)
{
int ret;
if (status == GDSC_ON && sc->rsupply) {
ret = regulator_enable(sc->rsupply);
if (ret < 0)
return ret;
}
ret = gdsc_update_collapse_bit(sc, status == GDSC_OFF);
/* If disabling votable gdscs, don't poll on status */
if ((sc->flags & VOTABLE) && status == GDSC_OFF && !wait) {
/*
* Add a short delay here to ensure that an enable
* right after it was disabled does not put it in an
* unknown state
*/
udelay(TIMEOUT_US);
return 0;
}
if (sc->gds_hw_ctrl) {
/*
* The gds hw controller asserts/de-asserts the status bit soon
* after it receives a power on/off request from a master.
* The controller then takes around 8 xo cycles to start its
* internal state machine and update the status bit. During
* this time, the status bit does not reflect the true status
* of the core.
* Add a delay of 1 us between writing to the SW_COLLAPSE bit
* and polling the status bit.
*/
udelay(1);
}
ret = gdsc_poll_status(sc, status);
WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n");
if (!ret && status == GDSC_OFF && sc->rsupply) {
ret = regulator_disable(sc->rsupply);
if (ret < 0)
return ret;
}
return ret;
}
static inline int gdsc_deassert_reset(struct gdsc *sc)
{
int i;
for (i = 0; i < sc->reset_count; i++)
sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
return 0;
}
static inline int gdsc_assert_reset(struct gdsc *sc)
{
int i;
for (i = 0; i < sc->reset_count; i++)
sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
return 0;
}
static inline void gdsc_force_mem_on(struct gdsc *sc)
{
int i;
u32 mask = RETAIN_MEM;
if (!(sc->flags & NO_RET_PERIPH))
mask |= RETAIN_PERIPH;
for (i = 0; i < sc->cxc_count; i++)
regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
}
static inline void gdsc_clear_mem_on(struct gdsc *sc)
{
int i;
u32 mask = RETAIN_MEM;
if (!(sc->flags & NO_RET_PERIPH))
mask |= RETAIN_PERIPH;
for (i = 0; i < sc->cxc_count; i++)
regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
}
static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
{
regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
GMEM_CLAMP_IO_MASK, 0);
}
static inline void gdsc_assert_clamp_io(struct gdsc *sc)
{
regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
GMEM_CLAMP_IO_MASK, 1);
}
static inline void gdsc_assert_reset_aon(struct gdsc *sc)
{
regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
GMEM_RESET_MASK, 1);
udelay(1);
regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
GMEM_RESET_MASK, 0);
}
static void gdsc_retain_ff_on(struct gdsc *sc)
{
u32 mask = GDSC_RETAIN_FF_ENABLE;
regmap_update_bits(sc->regmap, sc->gdscr, mask, mask);
}
static int gdsc_enable(struct generic_pm_domain *domain)
{
struct gdsc *sc = domain_to_gdsc(domain);
int ret;
if (sc->pwrsts == PWRSTS_ON)
return gdsc_deassert_reset(sc);
if (sc->flags & SW_RESET) {
gdsc_assert_reset(sc);
udelay(1);
gdsc_deassert_reset(sc);
}
if (sc->flags & CLAMP_IO) {
if (sc->flags & AON_RESET)
gdsc_assert_reset_aon(sc);
gdsc_deassert_clamp_io(sc);
}
ret = gdsc_toggle_logic(sc, GDSC_ON, false);
if (ret)
return ret;
if (sc->pwrsts & PWRSTS_OFF)
gdsc_force_mem_on(sc);
/*
* If clocks to this power domain were already on, they will take an
* additional 4 clock cycles to re-enable after the power domain is
* enabled. Delay to account for this. A delay is also needed to ensure
* clocks are not enabled within 400ns of enabling power to the
* memories.
*/
udelay(1);
/* Turn on HW trigger mode if supported */
if (sc->flags & HW_CTRL) {
ret = gdsc_hwctrl(sc, true);
if (ret)
return ret;
/*
* Wait for the GDSC to go through a power down and
* up cycle. In case a firmware ends up polling status
* bits for the gdsc, it might read an 'on' status before
* the GDSC can finish the power cycle.
* We wait 1us before returning to ensure the firmware
* can't immediately poll the status bits.
*/
udelay(1);
}
if (sc->flags & RETAIN_FF_ENABLE)
gdsc_retain_ff_on(sc);
return 0;
}
static int gdsc_disable(struct generic_pm_domain *domain)
{
struct gdsc *sc = domain_to_gdsc(domain);
int ret;
if (sc->pwrsts == PWRSTS_ON)
return gdsc_assert_reset(sc);
/* Turn off HW trigger mode if supported */
if (sc->flags & HW_CTRL) {
ret = gdsc_hwctrl(sc, false);
if (ret < 0)
return ret;
/*
* Wait for the GDSC to go through a power down and
* up cycle. In case we end up polling status
* bits for the gdsc before the power cycle is completed
* it might read an 'on' status wrongly.
*/
udelay(1);
ret = gdsc_poll_status(sc, GDSC_ON);
if (ret)
return ret;
}
if (sc->pwrsts & PWRSTS_OFF)
gdsc_clear_mem_on(sc);
/*
* If the GDSC supports only a Retention state, apart from ON,
* leave it in ON state.
* There is no SW control to transition the GDSC into
* Retention state. This happens in HW when the parent
* domain goes down to a Low power state
*/
if (sc->pwrsts == PWRSTS_RET_ON)
return 0;
ret = gdsc_toggle_logic(sc, GDSC_OFF, domain->synced_poweroff);
if (ret)
return ret;
if (sc->flags & CLAMP_IO)
gdsc_assert_clamp_io(sc);
return 0;
}
static int gdsc_init(struct gdsc *sc)
{
u32 mask, val;
int on, ret;
/*
* Disable HW trigger: collapse/restore occur based on registers writes.
* Disable SW override: Use hardware state-machine for sequencing.
* Configure wait time between states.
*/
mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
if (!sc->en_rest_wait_val)
sc->en_rest_wait_val = EN_REST_WAIT_VAL;
if (!sc->en_few_wait_val)
sc->en_few_wait_val = EN_FEW_WAIT_VAL;
if (!sc->clk_dis_wait_val)
sc->clk_dis_wait_val = CLK_DIS_WAIT_VAL;
val = sc->en_rest_wait_val << EN_REST_WAIT_SHIFT |
sc->en_few_wait_val << EN_FEW_WAIT_SHIFT |
sc->clk_dis_wait_val << CLK_DIS_WAIT_SHIFT;
ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
if (ret)
return ret;
/* Force gdsc ON if only ON state is supported */
if (sc->pwrsts == PWRSTS_ON) {
ret = gdsc_toggle_logic(sc, GDSC_ON, false);
if (ret)
return ret;
}
on = gdsc_check_status(sc, GDSC_ON);
if (on < 0)
return on;
if (on) {
/* The regulator must be on, sync the kernel state */
if (sc->rsupply) {
ret = regulator_enable(sc->rsupply);
if (ret < 0)
return ret;
}
/*
* Votable GDSCs can be ON due to Vote from other masters.
* If a Votable GDSC is ON, make sure we have a Vote.
*/
if (sc->flags & VOTABLE) {
ret = gdsc_update_collapse_bit(sc, false);
if (ret)
goto err_disable_supply;
}
/* Turn on HW trigger mode if supported */
if (sc->flags & HW_CTRL) {
ret = gdsc_hwctrl(sc, true);
if (ret < 0)
goto err_disable_supply;
}
/*
* Make sure the retain bit is set if the GDSC is already on,
* otherwise we end up turning off the GDSC and destroying all
* the register contents that we thought we were saving.
*/
if (sc->flags & RETAIN_FF_ENABLE)
gdsc_retain_ff_on(sc);
} else if (sc->flags & ALWAYS_ON) {
/* If ALWAYS_ON GDSCs are not ON, turn them ON */
gdsc_enable(&sc->pd);
on = true;
}
if (on || (sc->pwrsts & PWRSTS_RET))
gdsc_force_mem_on(sc);
else
gdsc_clear_mem_on(sc);
if (sc->flags & ALWAYS_ON)
sc->pd.flags |= GENPD_FLAG_ALWAYS_ON;
if (!sc->pd.power_off)
sc->pd.power_off = gdsc_disable;
if (!sc->pd.power_on)
sc->pd.power_on = gdsc_enable;
ret = pm_genpd_init(&sc->pd, NULL, !on);
if (ret)
goto err_disable_supply;
return 0;
err_disable_supply:
if (on && sc->rsupply)
regulator_disable(sc->rsupply);
return ret;
}
int gdsc_register(struct gdsc_desc *desc,
struct reset_controller_dev *rcdev, struct regmap *regmap)
{
int i, ret;
struct genpd_onecell_data *data;
struct device *dev = desc->dev;
struct gdsc **scs = desc->scs;
size_t num = desc->num;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
GFP_KERNEL);
if (!data->domains)
return -ENOMEM;
for (i = 0; i < num; i++) {
if (!scs[i] || !scs[i]->supply)
continue;
scs[i]->rsupply = devm_regulator_get(dev, scs[i]->supply);
if (IS_ERR(scs[i]->rsupply))
return PTR_ERR(scs[i]->rsupply);
}
data->num_domains = num;
for (i = 0; i < num; i++) {
if (!scs[i])
continue;
scs[i]->regmap = regmap;
scs[i]->rcdev = rcdev;
ret = gdsc_init(scs[i]);
if (ret)
return ret;
data->domains[i] = &scs[i]->pd;
}
/* Add subdomains */
for (i = 0; i < num; i++) {
if (!scs[i])
continue;
if (scs[i]->parent)
pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
else if (!IS_ERR_OR_NULL(dev->pm_domain))
pm_genpd_add_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd);
}
return of_genpd_add_provider_onecell(dev->of_node, data);
}
void gdsc_unregister(struct gdsc_desc *desc)
{
int i;
struct device *dev = desc->dev;
struct gdsc **scs = desc->scs;
size_t num = desc->num;
/* Remove subdomains */
for (i = 0; i < num; i++) {
if (!scs[i])
continue;
if (scs[i]->parent)
pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
else if (!IS_ERR_OR_NULL(dev->pm_domain))
pm_genpd_remove_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd);
}
of_genpd_del_provider(dev->of_node);
}
/*
* On SDM845+ the GPU GX domain is *almost* entirely controlled by the GMU
* running in the CX domain so the CPU doesn't need to know anything about the
* GX domain EXCEPT....
*
* Hardware constraints dictate that the GX be powered down before the CX. If
* the GMU crashes it could leave the GX on. In order to successfully bring back
* the device the CPU needs to disable the GX headswitch. There being no sane
* way to reach in and touch that register from deep inside the GPU driver we
* need to set up the infrastructure to be able to ensure that the GPU can
* ensure that the GX is off during this super special case. We do this by
* defining a GX gdsc with a dummy enable function and a "default" disable
* function.
*
* This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU
* driver. During power up, nothing will happen from the CPU (and the GMU will
* power up normally but during power down this will ensure that the GX domain
* is *really* off - this gives us a semi standard way of doing what we need.
*/
int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain)
{
/* Do nothing but give genpd the impression that we were successful */
return 0;
}
EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable);
| linux-master | drivers/clk/qcom/gdsc.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,gcc-sdx65.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_GPLL0_OUT_EVEN,
P_GPLL0_OUT_MAIN,
P_PCIE_PIPE_CLK,
P_SLEEP_CLK,
P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
};
static struct clk_alpha_pll gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.enable_reg = 0x6d000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
},
},
};
static const struct clk_div_table post_div_table_gpll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gpll0_out_even = {
.offset = 0x0,
.post_div_shift = 10,
.post_div_table = post_div_table_gpll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_even",
.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct clk_parent_data gcc_parent_data_0_ao[] = {
{ .fw_name = "bi_tcxo_ao" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 },
{ P_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .fw_name = "sleep_clk" },
{ .hw = &gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "sleep_clk" },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 2 },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_PCIE_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .fw_name = "pcie_pipe_clk"},
{ .fw_name = "bi_tcxo"},
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_6[] = {
{ .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk"},
{ .fw_name = "bi_tcxo"},
};
static struct clk_regmap_mux gcc_pcie_aux_clk_src = {
.reg = 0x43060,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_aux_clk_src",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_pcie_pipe_clk_src = {
.reg = 0x43044,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_5,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_pipe_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = 2,
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static struct clk_regmap_mux gcc_usb3_phy_pipe_clk_src = {
.reg = 0x1706c,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_6,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_pipe_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = 2,
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_blsp1_qup1_i2c_apps_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
{ }
};
static struct clk_rcg2 gcc_blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x1c024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = {
F(960000, P_BI_TCXO, 10, 1, 2),
F(4800000, P_BI_TCXO, 4, 0, 0),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(15000000, P_GPLL0_OUT_EVEN, 5, 1, 4),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24000000, P_GPLL0_OUT_MAIN, 12.5, 1, 2),
F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
{ }
};
static struct clk_rcg2 gcc_blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x1c00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x1e024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x1e00c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x20024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x2000c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x22024,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x2200c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_blsp1_uart1_apps_clk_src[] = {
F(3686400, P_GPLL0_OUT_EVEN, 1, 192, 15625),
F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
F(9600000, P_BI_TCXO, 2, 0, 0),
F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
F(16000000, P_GPLL0_OUT_EVEN, 1, 4, 75),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(19354839, P_GPLL0_OUT_MAIN, 15.5, 1, 2),
F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
F(20689655, P_GPLL0_OUT_MAIN, 14.5, 1, 2),
F(21428571, P_GPLL0_OUT_MAIN, 14, 1, 2),
F(22222222, P_GPLL0_OUT_MAIN, 13.5, 1, 2),
F(23076923, P_GPLL0_OUT_MAIN, 13, 1, 2),
F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5),
F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
F(26086957, P_GPLL0_OUT_MAIN, 11.5, 1, 2),
F(27272727, P_GPLL0_OUT_MAIN, 11, 1, 2),
F(28571429, P_GPLL0_OUT_MAIN, 10.5, 1, 2),
F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75),
F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375),
F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375),
F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75),
F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625),
F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x1d00c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x1f00c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_uart3_apps_clk_src = {
.cmd_rcgr = 0x2100c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_blsp1_uart4_apps_clk_src = {
.cmd_rcgr = 0x2300c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart4_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
.cmd_rcgr = 0x3000c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk_src",
.parent_data = gcc_parent_data_0_ao,
.num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x37004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = 4,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x38004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = 4,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x39004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = 4,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_aux_phy_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_aux_phy_clk_src = {
.cmd_rcgr = 0x43048,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_pcie_aux_phy_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_aux_phy_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_rchng_phy_clk_src[] = {
F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_rchng_phy_clk_src = {
.cmd_rcgr = 0x43064,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_pcie_rchng_phy_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_rchng_phy_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = 4,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x24010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.cmd_rcgr = 0x1a010,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_master_clk_src[] = {
F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_master_clk_src = {
.cmd_rcgr = 0x17030,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gcc_usb30_mock_utmi_clk_src = {
.cmd_rcgr = 0x17048,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_aux_phy_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb3_phy_aux_clk_src[] = {
F(1000000, P_BI_TCXO, 1, 5, 96),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb3_phy_aux_clk_src = {
.cmd_rcgr = 0x17070,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_usb3_phy_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = {
.reg = 0x30024,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_cpuss_ahb_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_cpuss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_usb30_mock_utmi_postdiv_clk_src = {
.reg = 0x17060,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_usb30_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gcc_ahb_pcie_link_clk = {
.halt_reg = 0x2e004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ahb_pcie_link_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x1b004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x6d008,
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x1c008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1c008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x1c004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1c004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x1e008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x1e004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1e004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x20008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x20004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x20004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.halt_reg = 0x22008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x22008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.halt_reg = 0x22004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x22004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_sleep_clk = {
.halt_reg = 0x1b00c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x6d008,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x1d004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1d004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x1f004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1f004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart3_apps_clk = {
.halt_reg = 0x21004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x21004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_uart3_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart4_apps_clk = {
.halt_reg = 0x23004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x23004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart4_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_blsp1_uart4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x27004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x27004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x6d008,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x37000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x37000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x38000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x38000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x39000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_clkref_en = {
.halt_reg = 0x88004,
/*
* The clock controller does not handle the status bit for
* the clocks with gdscs(powerdomains) in hw controlled mode
* and hence avoid checking for the status bit of those clocks
* by setting the BRANCH_HALT_DELAY flag
*/
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x88004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_aux_clk = {
.halt_reg = 0x43034,
/*
* The clock controller does not handle the status bit for
* the clocks with gdscs(powerdomains) in hw controlled mode
* and hence avoid checking for the status bit of those clocks
* by setting the BRANCH_HALT_DELAY flag
*/
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x43034,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x6d010,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_cfg_ahb_clk = {
.halt_reg = 0x4302c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x4302c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x6d010,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_mstr_axi_clk = {
.halt_reg = 0x43024,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x43024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x6d010,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_pipe_clk = {
.halt_reg = 0x4303c,
/*
* The clock controller does not handle the status bit for
* the clocks with gdscs(powerdomains) in hw controlled mode
* and hence avoid checking for the status bit of those clocks
* by setting the BRANCH_HALT_DELAY flag
*/
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x4303c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x6d010,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_rchng_phy_clk = {
.halt_reg = 0x43030,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x43030,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x6d010,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_rchng_phy_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_rchng_phy_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_sleep_clk = {
.halt_reg = 0x43038,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x43038,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x6d010,
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_sleep_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_aux_phy_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_slv_axi_clk = {
.halt_reg = 0x4301c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x4301c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x6d010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_slv_q2a_axi_clk = {
.halt_reg = 0x43018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x43018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x6d010,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x2400c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2400c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x24004,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x24004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x24004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x24008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x24008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_rx1_usb2_clkref_en = {
.halt_reg = 0x88008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x88008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_rx1_usb2_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x1a00c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a00c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x1a004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1a004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_master_clk = {
.halt_reg = 0x17018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_master_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_mock_utmi_clk = {
.halt_reg = 0x1702c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1702c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_mstr_axi_clk = {
.halt_reg = 0x17020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sleep_clk = {
.halt_reg = 0x17028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_slv_ahb_clk = {
.halt_reg = 0x17024,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_slv_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_phy_aux_clk = {
.halt_reg = 0x17064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x17064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc usb30_gdsc = {
.gdscr = 0x17004,
.pd = {
.name = "usb30_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc pcie_gdsc = {
.gdscr = 0x43004,
.pd = {
.name = "pcie_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_branch gcc_usb3_phy_pipe_clk = {
.halt_reg = 0x17068,
/*
* The clock controller does not handle the status bit for
* the clocks with gdscs(powerdomains) in hw controlled mode
* and hence avoid checking for the status bit of those clocks
* by setting the BRANCH_HALT_DELAY flag
*/
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x17068,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x17068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_phy_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_clkref_en = {
.halt_reg = 0x88000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x88000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_clkref_en",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
.halt_reg = 0x19008,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x19008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x19008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_phy_cfg_ahb2phy_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_xo_div4_clk = {
.halt_reg = 0x2e010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2e010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_xo_div4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_xo_pcie_link_clk = {
.halt_reg = 0x2e008,
.halt_check = BRANCH_HALT,
.hwcg_reg = 0x2e008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2e008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_xo_pcie_link_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *gcc_sdx65_clocks[] = {
[GCC_AHB_PCIE_LINK_CLK] = &gcc_ahb_pcie_link_clk.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC] = &gcc_blsp1_qup1_i2c_apps_clk_src.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup1_spi_apps_clk_src.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC] = &gcc_blsp1_qup2_i2c_apps_clk_src.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup2_spi_apps_clk_src.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC] = &gcc_blsp1_qup3_i2c_apps_clk_src.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup3_spi_apps_clk_src.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC] = &gcc_blsp1_qup4_i2c_apps_clk_src.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup4_spi_apps_clk_src.clkr,
[GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK_SRC] = &gcc_blsp1_uart1_apps_clk_src.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK_SRC] = &gcc_blsp1_uart2_apps_clk_src.clkr,
[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
[GCC_BLSP1_UART3_APPS_CLK_SRC] = &gcc_blsp1_uart3_apps_clk_src.clkr,
[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
[GCC_BLSP1_UART4_APPS_CLK_SRC] = &gcc_blsp1_uart4_apps_clk_src.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
[GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
[GCC_PCIE_AUX_CLK] = &gcc_pcie_aux_clk.clkr,
[GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr,
[GCC_PCIE_AUX_PHY_CLK_SRC] = &gcc_pcie_aux_phy_clk_src.clkr,
[GCC_PCIE_CFG_AHB_CLK] = &gcc_pcie_cfg_ahb_clk.clkr,
[GCC_PCIE_MSTR_AXI_CLK] = &gcc_pcie_mstr_axi_clk.clkr,
[GCC_PCIE_PIPE_CLK] = &gcc_pcie_pipe_clk.clkr,
[GCC_PCIE_PIPE_CLK_SRC] = &gcc_pcie_pipe_clk_src.clkr,
[GCC_PCIE_RCHNG_PHY_CLK] = &gcc_pcie_rchng_phy_clk.clkr,
[GCC_PCIE_RCHNG_PHY_CLK_SRC] = &gcc_pcie_rchng_phy_clk_src.clkr,
[GCC_PCIE_SLEEP_CLK] = &gcc_pcie_sleep_clk.clkr,
[GCC_PCIE_SLV_AXI_CLK] = &gcc_pcie_slv_axi_clk.clkr,
[GCC_PCIE_SLV_Q2A_AXI_CLK] = &gcc_pcie_slv_q2a_axi_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_RX1_USB2_CLKREF_EN] = &gcc_rx1_usb2_clkref_en.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
[GCC_USB30_MASTER_CLK_SRC] = &gcc_usb30_master_clk_src.clkr,
[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
[GCC_USB30_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mock_utmi_clk_src.clkr,
[GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_MSTR_AXI_CLK] = &gcc_usb30_mstr_axi_clk.clkr,
[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
[GCC_USB30_SLV_AHB_CLK] = &gcc_usb30_slv_ahb_clk.clkr,
[GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
[GCC_USB3_PHY_AUX_CLK_SRC] = &gcc_usb3_phy_aux_clk_src.clkr,
[GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
[GCC_USB3_PHY_PIPE_CLK_SRC] = &gcc_usb3_phy_pipe_clk_src.clkr,
[GCC_USB3_PRIM_CLKREF_EN] = &gcc_usb3_prim_clkref_en.clkr,
[GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
[GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
[GCC_XO_PCIE_LINK_CLK] = &gcc_xo_pcie_link_clk.clkr,
[GPLL0] = &gpll0.clkr,
[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
};
static const struct qcom_reset_map gcc_sdx65_resets[] = {
[GCC_BLSP1_QUP1_BCR] = { 0x1c000 },
[GCC_BLSP1_QUP2_BCR] = { 0x1e000 },
[GCC_BLSP1_QUP3_BCR] = { 0x20000 },
[GCC_BLSP1_QUP4_BCR] = { 0x22000 },
[GCC_BLSP1_UART1_BCR] = { 0x1d000 },
[GCC_BLSP1_UART2_BCR] = { 0x1f000 },
[GCC_BLSP1_UART3_BCR] = { 0x21000 },
[GCC_BLSP1_UART4_BCR] = { 0x23000 },
[GCC_PCIE_BCR] = { 0x43000 },
[GCC_PCIE_LINK_DOWN_BCR] = { 0x77000 },
[GCC_PCIE_NOCSR_COM_PHY_BCR] = { 0x78008 },
[GCC_PCIE_PHY_BCR] = { 0x44000 },
[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x78000 },
[GCC_PCIE_PHY_COM_BCR] = { 0x78004 },
[GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x7800c },
[GCC_PDM_BCR] = { 0x24000 },
[GCC_QUSB2PHY_BCR] = { 0x19000 },
[GCC_SDCC1_BCR] = { 0x1a000 },
[GCC_TCSR_PCIE_BCR] = { 0x57000 },
[GCC_USB30_BCR] = { 0x17000 },
[GCC_USB3_PHY_BCR] = { 0x18000 },
[GCC_USB3PHY_PHY_BCR] = { 0x18004 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x19004 },
};
static struct gdsc *gcc_sdx65_gdscs[] = {
[USB30_GDSC] = &usb30_gdsc,
[PCIE_GDSC] = &pcie_gdsc,
};
static const struct regmap_config gcc_sdx65_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x1f101c,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_sdx65_desc = {
.config = &gcc_sdx65_regmap_config,
.clks = gcc_sdx65_clocks,
.num_clks = ARRAY_SIZE(gcc_sdx65_clocks),
.resets = gcc_sdx65_resets,
.num_resets = ARRAY_SIZE(gcc_sdx65_resets),
.gdscs = gcc_sdx65_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sdx65_gdscs),
};
static const struct of_device_id gcc_sdx65_match_table[] = {
{ .compatible = "qcom,gcc-sdx65" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_sdx65_match_table);
static int gcc_sdx65_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gcc_sdx65_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/*
* Keep the clocks always-ON as they are critical to the functioning
* of the system:
* GCC_SYS_NOC_CPUSS_AHB_CLK, GCC_CPUSS_AHB_CLK, GCC_CPUSS_GNOC_CLK
*/
regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21));
regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22));
return qcom_cc_really_probe(pdev, &gcc_sdx65_desc, regmap);
}
static struct platform_driver gcc_sdx65_driver = {
.probe = gcc_sdx65_probe,
.driver = {
.name = "gcc-sdx65",
.of_match_table = gcc_sdx65_match_table,
},
};
static int __init gcc_sdx65_init(void)
{
return platform_driver_register(&gcc_sdx65_driver);
}
subsys_initcall(gcc_sdx65_init);
static void __exit gcc_sdx65_exit(void)
{
platform_driver_unregister(&gcc_sdx65_driver);
}
module_exit(gcc_sdx65_exit);
MODULE_DESCRIPTION("QTI GCC SDX65 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/gcc-sdx65.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2017, Linaro Limited
* Author: Georgi Djakov <[email protected]>
*/
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/regmap.h>
#include "clk-regmap-mux-div.h"
#define CMD_RCGR 0x0
#define CMD_RCGR_UPDATE BIT(0)
#define CMD_RCGR_DIRTY_CFG BIT(4)
#define CMD_RCGR_ROOT_OFF BIT(31)
#define CFG_RCGR 0x4
#define to_clk_regmap_mux_div(_hw) \
container_of(to_clk_regmap(_hw), struct clk_regmap_mux_div, clkr)
int mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div)
{
int ret, count;
u32 val, mask;
const char *name = clk_hw_get_name(&md->clkr.hw);
val = (div << md->hid_shift) | (src << md->src_shift);
mask = ((BIT(md->hid_width) - 1) << md->hid_shift) |
((BIT(md->src_width) - 1) << md->src_shift);
ret = regmap_update_bits(md->clkr.regmap, CFG_RCGR + md->reg_offset,
mask, val);
if (ret)
return ret;
ret = regmap_update_bits(md->clkr.regmap, CMD_RCGR + md->reg_offset,
CMD_RCGR_UPDATE, CMD_RCGR_UPDATE);
if (ret)
return ret;
/* Wait for update to take effect */
for (count = 500; count > 0; count--) {
ret = regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset,
&val);
if (ret)
return ret;
if (!(val & CMD_RCGR_UPDATE))
return 0;
udelay(1);
}
pr_err("%s: RCG did not update its configuration", name);
return -EBUSY;
}
EXPORT_SYMBOL_GPL(mux_div_set_src_div);
static void mux_div_get_src_div(struct clk_regmap_mux_div *md, u32 *src,
u32 *div)
{
u32 val, d, s;
const char *name = clk_hw_get_name(&md->clkr.hw);
regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset, &val);
if (val & CMD_RCGR_DIRTY_CFG) {
pr_err("%s: RCG configuration is pending\n", name);
return;
}
regmap_read(md->clkr.regmap, CFG_RCGR + md->reg_offset, &val);
s = (val >> md->src_shift);
s &= BIT(md->src_width) - 1;
*src = s;
d = (val >> md->hid_shift);
d &= BIT(md->hid_width) - 1;
*div = d;
}
static inline bool is_better_rate(unsigned long req, unsigned long best,
unsigned long new)
{
return (req <= new && new < best) || (best < req && best < new);
}
static int mux_div_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
unsigned int i, div, max_div;
unsigned long actual_rate, best_rate = 0;
unsigned long req_rate = req->rate;
for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
unsigned long parent_rate = clk_hw_get_rate(parent);
max_div = BIT(md->hid_width) - 1;
for (div = 1; div < max_div; div++) {
parent_rate = mult_frac(req_rate, div, 2);
parent_rate = clk_hw_round_rate(parent, parent_rate);
actual_rate = mult_frac(parent_rate, 2, div);
if (is_better_rate(req_rate, best_rate, actual_rate)) {
best_rate = actual_rate;
req->rate = best_rate;
req->best_parent_rate = parent_rate;
req->best_parent_hw = parent;
}
if (actual_rate < req_rate || best_rate <= req_rate)
break;
}
}
if (!best_rate)
return -EINVAL;
return 0;
}
static int __mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
unsigned long prate, u32 src)
{
struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
int ret;
u32 div, max_div, best_src = 0, best_div = 0;
unsigned int i;
unsigned long actual_rate, best_rate = 0;
for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
unsigned long parent_rate = clk_hw_get_rate(parent);
max_div = BIT(md->hid_width) - 1;
for (div = 1; div < max_div; div++) {
parent_rate = mult_frac(rate, div, 2);
parent_rate = clk_hw_round_rate(parent, parent_rate);
actual_rate = mult_frac(parent_rate, 2, div);
if (is_better_rate(rate, best_rate, actual_rate)) {
best_rate = actual_rate;
best_src = md->parent_map[i];
best_div = div - 1;
}
if (actual_rate < rate || best_rate <= rate)
break;
}
}
ret = mux_div_set_src_div(md, best_src, best_div);
if (!ret) {
md->div = best_div;
md->src = best_src;
}
return ret;
}
static u8 mux_div_get_parent(struct clk_hw *hw)
{
struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
const char *name = clk_hw_get_name(hw);
u32 i, div, src = 0;
mux_div_get_src_div(md, &src, &div);
for (i = 0; i < clk_hw_get_num_parents(hw); i++)
if (src == md->parent_map[i])
return i;
pr_err("%s: Can't find parent with src %d\n", name, src);
return 0;
}
static int mux_div_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
return mux_div_set_src_div(md, md->parent_map[index], md->div);
}
static int mux_div_set_rate(struct clk_hw *hw,
unsigned long rate, unsigned long prate)
{
struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
return __mux_div_set_rate_and_parent(hw, rate, prate, md->src);
}
static int mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
unsigned long prate, u8 index)
{
struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
return __mux_div_set_rate_and_parent(hw, rate, prate,
md->parent_map[index]);
}
static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate)
{
struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
u32 div, src;
int i, num_parents = clk_hw_get_num_parents(hw);
const char *name = clk_hw_get_name(hw);
mux_div_get_src_div(md, &src, &div);
for (i = 0; i < num_parents; i++)
if (src == md->parent_map[i]) {
struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
unsigned long parent_rate = clk_hw_get_rate(p);
return mult_frac(parent_rate, 2, div + 1);
}
pr_err("%s: Can't find parent %d\n", name, src);
return 0;
}
const struct clk_ops clk_regmap_mux_div_ops = {
.get_parent = mux_div_get_parent,
.set_parent = mux_div_set_parent,
.set_rate = mux_div_set_rate,
.set_rate_and_parent = mux_div_set_rate_and_parent,
.determine_rate = mux_div_determine_rate,
.recalc_rate = mux_div_recalc_rate,
};
EXPORT_SYMBOL_GPL(clk_regmap_mux_div_ops);
| linux-master | drivers/clk/qcom/clk-regmap-mux-div.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,mmcc-msm8998.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-alpha-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_XO,
P_GPLL0,
P_GPLL0_DIV,
P_MMPLL0_OUT_EVEN,
P_MMPLL1_OUT_EVEN,
P_MMPLL3_OUT_EVEN,
P_MMPLL4_OUT_EVEN,
P_MMPLL5_OUT_EVEN,
P_MMPLL6_OUT_EVEN,
P_MMPLL7_OUT_EVEN,
P_MMPLL10_OUT_EVEN,
P_DSI0PLL,
P_DSI1PLL,
P_DSI0PLL_BYTE,
P_DSI1PLL_BYTE,
P_HDMIPLL,
P_DPVCO,
P_DPLINK,
};
static const struct clk_div_table post_div_table_fabia_even[] = {
{ 0x0, 1 },
{ 0x1, 2 },
{ 0x3, 4 },
{ 0x7, 8 },
{ }
};
static struct clk_alpha_pll mmpll0 = {
.offset = 0xc000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.enable_reg = 0x1e0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmpll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo"
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
},
};
static struct clk_alpha_pll_postdiv mmpll0_out_even = {
.offset = 0xc000,
.post_div_shift = 8,
.post_div_table = post_div_table_fabia_even,
.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll0_out_even",
.parent_hws = (const struct clk_hw *[]){ &mmpll0.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll mmpll1 = {
.offset = 0xc050,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.enable_reg = 0x1e0,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "mmpll1",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo"
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
},
};
static struct clk_alpha_pll_postdiv mmpll1_out_even = {
.offset = 0xc050,
.post_div_shift = 8,
.post_div_table = post_div_table_fabia_even,
.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll1_out_even",
.parent_hws = (const struct clk_hw *[]){ &mmpll1.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll mmpll3 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll3",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo"
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv mmpll3_out_even = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_fabia_even,
.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll3_out_even",
.parent_hws = (const struct clk_hw *[]){ &mmpll3.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll mmpll4 = {
.offset = 0x50,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll4",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo"
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv mmpll4_out_even = {
.offset = 0x50,
.post_div_shift = 8,
.post_div_table = post_div_table_fabia_even,
.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll4_out_even",
.parent_hws = (const struct clk_hw *[]){ &mmpll4.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll mmpll5 = {
.offset = 0xa0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll5",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo"
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv mmpll5_out_even = {
.offset = 0xa0,
.post_div_shift = 8,
.post_div_table = post_div_table_fabia_even,
.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll5_out_even",
.parent_hws = (const struct clk_hw *[]){ &mmpll5.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll mmpll6 = {
.offset = 0xf0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll6",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo"
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv mmpll6_out_even = {
.offset = 0xf0,
.post_div_shift = 8,
.post_div_table = post_div_table_fabia_even,
.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll6_out_even",
.parent_hws = (const struct clk_hw *[]){ &mmpll6.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll mmpll7 = {
.offset = 0x140,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll7",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo"
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv mmpll7_out_even = {
.offset = 0x140,
.post_div_shift = 8,
.post_div_table = post_div_table_fabia_even,
.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll7_out_even",
.parent_hws = (const struct clk_hw *[]){ &mmpll7.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static struct clk_alpha_pll mmpll10 = {
.offset = 0x190,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll10",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo"
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
},
};
static struct clk_alpha_pll_postdiv mmpll10_out_even = {
.offset = 0x190,
.post_div_shift = 8,
.post_div_table = post_div_table_fabia_even,
.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll10_out_even",
.parent_hws = (const struct clk_hw *[]){ &mmpll10.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops,
},
};
static const struct parent_map mmss_xo_hdmi_map[] = {
{ P_XO, 0 },
{ P_HDMIPLL, 1 },
};
static const struct clk_parent_data mmss_xo_hdmi[] = {
{ .fw_name = "xo" },
{ .fw_name = "hdmipll" },
};
static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL, 1 },
{ P_DSI1PLL, 2 },
};
static const struct clk_parent_data mmss_xo_dsi0pll_dsi1pll[] = {
{ .fw_name = "xo" },
{ .fw_name = "dsi0dsi" },
{ .fw_name = "dsi1dsi" },
};
static const struct parent_map mmss_xo_dsibyte_map[] = {
{ P_XO, 0 },
{ P_DSI0PLL_BYTE, 1 },
{ P_DSI1PLL_BYTE, 2 },
};
static const struct clk_parent_data mmss_xo_dsibyte[] = {
{ .fw_name = "xo" },
{ .fw_name = "dsi0byte" },
{ .fw_name = "dsi1byte" },
};
static const struct parent_map mmss_xo_dp_map[] = {
{ P_XO, 0 },
{ P_DPLINK, 1 },
{ P_DPVCO, 2 },
};
static const struct clk_parent_data mmss_xo_dp[] = {
{ .fw_name = "xo" },
{ .fw_name = "dplink" },
{ .fw_name = "dpvco" },
};
static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 },
};
static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = {
{ .fw_name = "xo" },
{ .fw_name = "gpll0" },
{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
};
static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_MMPLL0_OUT_EVEN, 1 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 },
};
static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = {
{ .fw_name = "xo" },
{ .hw = &mmpll0_out_even.clkr.hw },
{ .fw_name = "gpll0" },
{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
};
static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_MMPLL0_OUT_EVEN, 1 },
{ P_MMPLL1_OUT_EVEN, 2 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 },
};
static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
{ .fw_name = "xo" },
{ .hw = &mmpll0_out_even.clkr.hw },
{ .hw = &mmpll1_out_even.clkr.hw },
{ .fw_name = "gpll0" },
{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
};
static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_MMPLL0_OUT_EVEN, 1 },
{ P_MMPLL5_OUT_EVEN, 2 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 },
};
static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
{ .fw_name = "xo" },
{ .hw = &mmpll0_out_even.clkr.hw },
{ .hw = &mmpll5_out_even.clkr.hw },
{ .fw_name = "gpll0" },
{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
};
static const struct parent_map mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_MMPLL0_OUT_EVEN, 1 },
{ P_MMPLL3_OUT_EVEN, 3 },
{ P_MMPLL6_OUT_EVEN, 4 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 },
};
static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div[] = {
{ .fw_name = "xo" },
{ .hw = &mmpll0_out_even.clkr.hw },
{ .hw = &mmpll3_out_even.clkr.hw },
{ .hw = &mmpll6_out_even.clkr.hw },
{ .fw_name = "gpll0" },
{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
};
static const struct parent_map mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_MMPLL4_OUT_EVEN, 1 },
{ P_MMPLL7_OUT_EVEN, 2 },
{ P_MMPLL10_OUT_EVEN, 3 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 },
};
static const struct clk_parent_data mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
{ .fw_name = "xo" },
{ .hw = &mmpll4_out_even.clkr.hw },
{ .hw = &mmpll7_out_even.clkr.hw },
{ .hw = &mmpll10_out_even.clkr.hw },
{ .fw_name = "gpll0" },
{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
};
static const struct parent_map mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_MMPLL0_OUT_EVEN, 1 },
{ P_MMPLL7_OUT_EVEN, 2 },
{ P_MMPLL10_OUT_EVEN, 3 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 },
};
static const struct clk_parent_data mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div[] = {
{ .fw_name = "xo" },
{ .hw = &mmpll0_out_even.clkr.hw },
{ .hw = &mmpll7_out_even.clkr.hw },
{ .hw = &mmpll10_out_even.clkr.hw },
{ .fw_name = "gpll0" },
{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
};
static const struct parent_map mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
{ P_XO, 0 },
{ P_MMPLL0_OUT_EVEN, 1 },
{ P_MMPLL4_OUT_EVEN, 2 },
{ P_MMPLL7_OUT_EVEN, 3 },
{ P_MMPLL10_OUT_EVEN, 4 },
{ P_GPLL0, 5 },
{ P_GPLL0_DIV, 6 },
};
static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
{ .fw_name = "xo" },
{ .hw = &mmpll0_out_even.clkr.hw },
{ .hw = &mmpll4_out_even.clkr.hw },
{ .hw = &mmpll7_out_even.clkr.hw },
{ .hw = &mmpll10_out_even.clkr.hw },
{ .fw_name = "gpll0" },
{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
};
static struct clk_rcg2 byte0_clk_src = {
.cmd_rcgr = 0x2120,
.hid_width = 5,
.parent_map = mmss_xo_dsibyte_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte0_clk_src",
.parent_data = mmss_xo_dsibyte,
.num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_rcg2 byte1_clk_src = {
.cmd_rcgr = 0x2140,
.hid_width = 5,
.parent_map = mmss_xo_dsibyte_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte1_clk_src",
.parent_data = mmss_xo_dsibyte,
.num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_cci_clk_src[] = {
F(37500000, P_GPLL0, 16, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
{ }
};
static struct clk_rcg2 cci_clk_src = {
.cmd_rcgr = 0x3300,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_cci_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cci_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_cpp_clk_src[] = {
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
F(600000000, P_GPLL0, 1, 0, 0),
{ }
};
static struct clk_rcg2 cpp_clk_src = {
.cmd_rcgr = 0x3640,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_cpp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "cpp_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_csi_clk_src[] = {
F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
F(300000000, P_GPLL0, 2, 0, 0),
F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 csi0_clk_src = {
.cmd_rcgr = 0x3090,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi1_clk_src = {
.cmd_rcgr = 0x3100,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi2_clk_src = {
.cmd_rcgr = 0x3160,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi2_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi3_clk_src = {
.cmd_rcgr = 0x31c0,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi3_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_csiphy_clk_src[] = {
F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
F(300000000, P_GPLL0, 2, 0, 0),
F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 csiphy_clk_src = {
.cmd_rcgr = 0x3800,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csiphy_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csiphy_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_csiphytimer_clk_src[] = {
F(200000000, P_GPLL0, 3, 0, 0),
F(269333333, P_MMPLL0_OUT_EVEN, 3, 0, 0),
{ }
};
static struct clk_rcg2 csi0phytimer_clk_src = {
.cmd_rcgr = 0x3000,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csiphytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0phytimer_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi1phytimer_clk_src = {
.cmd_rcgr = 0x3030,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csiphytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1phytimer_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 csi2phytimer_clk_src = {
.cmd_rcgr = 0x3060,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_csiphytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi2phytimer_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_dp_aux_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 dp_aux_clk_src = {
.cmd_rcgr = 0x2260,
.hid_width = 5,
.parent_map = mmss_xo_gpll0_gpll0_div_map,
.freq_tbl = ftbl_dp_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "dp_aux_clk_src",
.parent_data = mmss_xo_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_dp_crypto_clk_src[] = {
F(101250, P_DPLINK, 1, 5, 16),
F(168750, P_DPLINK, 1, 5, 16),
F(337500, P_DPLINK, 1, 5, 16),
{ }
};
static struct clk_rcg2 dp_crypto_clk_src = {
.cmd_rcgr = 0x2220,
.hid_width = 5,
.parent_map = mmss_xo_dp_map,
.freq_tbl = ftbl_dp_crypto_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "dp_crypto_clk_src",
.parent_data = mmss_xo_dp,
.num_parents = ARRAY_SIZE(mmss_xo_dp),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_dp_link_clk_src[] = {
F(162000, P_DPLINK, 2, 0, 0),
F(270000, P_DPLINK, 2, 0, 0),
F(540000, P_DPLINK, 2, 0, 0),
{ }
};
static struct clk_rcg2 dp_link_clk_src = {
.cmd_rcgr = 0x2200,
.hid_width = 5,
.parent_map = mmss_xo_dp_map,
.freq_tbl = ftbl_dp_link_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "dp_link_clk_src",
.parent_data = mmss_xo_dp,
.num_parents = ARRAY_SIZE(mmss_xo_dp),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_dp_pixel_clk_src[] = {
F(154000000, P_DPVCO, 1, 0, 0),
F(337500000, P_DPVCO, 2, 0, 0),
F(675000000, P_DPVCO, 2, 0, 0),
{ }
};
static struct clk_rcg2 dp_pixel_clk_src = {
.cmd_rcgr = 0x2240,
.hid_width = 5,
.parent_map = mmss_xo_dp_map,
.freq_tbl = ftbl_dp_pixel_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "dp_pixel_clk_src",
.parent_data = mmss_xo_dp,
.num_parents = ARRAY_SIZE(mmss_xo_dp),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_esc_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 esc0_clk_src = {
.cmd_rcgr = 0x2160,
.hid_width = 5,
.parent_map = mmss_xo_dsibyte_map,
.freq_tbl = ftbl_esc_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc0_clk_src",
.parent_data = mmss_xo_dsibyte,
.num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 esc1_clk_src = {
.cmd_rcgr = 0x2180,
.hid_width = 5,
.parent_map = mmss_xo_dsibyte_map,
.freq_tbl = ftbl_esc_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc1_clk_src",
.parent_data = mmss_xo_dsibyte,
.num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_extpclk_clk_src[] = {
{ .src = P_HDMIPLL },
{ }
};
static struct clk_rcg2 extpclk_clk_src = {
.cmd_rcgr = 0x2060,
.hid_width = 5,
.parent_map = mmss_xo_hdmi_map,
.freq_tbl = ftbl_extpclk_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "extpclk_clk_src",
.parent_data = mmss_xo_hdmi,
.num_parents = ARRAY_SIZE(mmss_xo_hdmi),
.ops = &clk_byte_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_fd_core_clk_src[] = {
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 fd_core_clk_src = {
.cmd_rcgr = 0x3b00,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_fd_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "fd_core_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_hdmi_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 hdmi_clk_src = {
.cmd_rcgr = 0x2100,
.hid_width = 5,
.parent_map = mmss_xo_gpll0_gpll0_div_map,
.freq_tbl = ftbl_hdmi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "hdmi_clk_src",
.parent_data = mmss_xo_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
F(75000000, P_GPLL0, 8, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 jpeg0_clk_src = {
.cmd_rcgr = 0x3500,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_jpeg0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg0_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_maxi_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(75000000, P_GPLL0_DIV, 4, 0, 0),
F(171428571, P_GPLL0, 3.5, 0, 0),
F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
F(406000000, P_MMPLL1_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 maxi_clk_src = {
.cmd_rcgr = 0xf020,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
.freq_tbl = ftbl_maxi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "maxi_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_mclk_clk_src[] = {
F(4800000, P_XO, 4, 0, 0),
F(6000000, P_GPLL0_DIV, 10, 1, 5),
F(8000000, P_GPLL0_DIV, 1, 2, 75),
F(9600000, P_XO, 2, 0, 0),
F(16666667, P_GPLL0_DIV, 2, 1, 9),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0_DIV, 1, 2, 25),
F(33333333, P_GPLL0_DIV, 1, 2, 9),
F(48000000, P_GPLL0, 1, 2, 25),
F(66666667, P_GPLL0, 1, 2, 9),
{ }
};
static struct clk_rcg2 mclk0_clk_src = {
.cmd_rcgr = 0x3360,
.hid_width = 5,
.parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_mclk_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk0_clk_src",
.parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk1_clk_src = {
.cmd_rcgr = 0x3390,
.hid_width = 5,
.parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_mclk_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk1_clk_src",
.parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk2_clk_src = {
.cmd_rcgr = 0x33c0,
.hid_width = 5,
.parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_mclk_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk2_clk_src",
.parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 mclk3_clk_src = {
.cmd_rcgr = 0x33f0,
.hid_width = 5,
.parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_mclk_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk3_clk_src",
.parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_mdp_clk_src[] = {
F(85714286, P_GPLL0, 7, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
F(171428571, P_GPLL0, 3.5, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
F(300000000, P_GPLL0, 2, 0, 0),
F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 mdp_clk_src = {
.cmd_rcgr = 0x2040,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
.freq_tbl = ftbl_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mdp_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_vsync_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static struct clk_rcg2 vsync_clk_src = {
.cmd_rcgr = 0x2080,
.hid_width = 5,
.parent_map = mmss_xo_gpll0_gpll0_div_map,
.freq_tbl = ftbl_vsync_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "vsync_clk_src",
.parent_data = mmss_xo_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_ahb_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(40000000, P_GPLL0, 15, 0, 0),
F(80800000, P_MMPLL0_OUT_EVEN, 10, 0, 0),
{ }
};
static struct clk_rcg2 ahb_clk_src = {
.cmd_rcgr = 0x5000,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
.freq_tbl = ftbl_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "ahb_clk_src",
.parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_axi_clk_src[] = {
F(75000000, P_GPLL0, 8, 0, 0),
F(171428571, P_GPLL0, 3.5, 0, 0),
F(240000000, P_GPLL0, 2.5, 0, 0),
F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
F(406000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
{ }
};
/* RO to linux */
static struct clk_rcg2 axi_clk_src = {
.cmd_rcgr = 0xd000,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
.freq_tbl = ftbl_axi_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "axi_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 pclk0_clk_src = {
.cmd_rcgr = 0x2000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmss_xo_dsi0pll_dsi1pll_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk0_clk_src",
.parent_data = mmss_xo_dsi0pll_dsi1pll,
.num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_rcg2 pclk1_clk_src = {
.cmd_rcgr = 0x2020,
.mnd_width = 8,
.hid_width = 5,
.parent_map = mmss_xo_dsi0pll_dsi1pll_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk1_clk_src",
.parent_data = mmss_xo_dsi0pll_dsi1pll,
.num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct freq_tbl ftbl_rot_clk_src[] = {
F(171428571, P_GPLL0, 3.5, 0, 0),
F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 rot_clk_src = {
.cmd_rcgr = 0x21a0,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
.freq_tbl = ftbl_rot_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "rot_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_video_core_clk_src[] = {
F(200000000, P_GPLL0, 3, 0, 0),
F(269330000, P_MMPLL0_OUT_EVEN, 3, 0, 0),
F(355200000, P_MMPLL6_OUT_EVEN, 2.5, 0, 0),
F(444000000, P_MMPLL6_OUT_EVEN, 2, 0, 0),
F(533000000, P_MMPLL3_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 video_core_clk_src = {
.cmd_rcgr = 0x1000,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
.freq_tbl = ftbl_video_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "video_core_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 video_subcore0_clk_src = {
.cmd_rcgr = 0x1060,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
.freq_tbl = ftbl_video_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "video_subcore0_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 video_subcore1_clk_src = {
.cmd_rcgr = 0x1080,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
.freq_tbl = ftbl_video_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "video_subcore1_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_vfe_clk_src[] = {
F(200000000, P_GPLL0, 3, 0, 0),
F(300000000, P_GPLL0, 2, 0, 0),
F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
F(600000000, P_GPLL0, 1, 0, 0),
{ }
};
static struct clk_rcg2 vfe0_clk_src = {
.cmd_rcgr = 0x3600,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_vfe_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe0_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 vfe1_clk_src = {
.cmd_rcgr = 0x3620,
.hid_width = 5,
.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
.freq_tbl = ftbl_vfe_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe1_clk_src",
.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch misc_ahb_clk = {
.halt_reg = 0x328,
.hwcg_reg = 0x328,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x328,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "misc_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch video_core_clk = {
.halt_reg = 0x1028,
.clkr = {
.enable_reg = 0x1028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_core_clk",
.parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch video_ahb_clk = {
.halt_reg = 0x1030,
.hwcg_reg = 0x1030,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x1030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch video_axi_clk = {
.halt_reg = 0x1034,
.clkr = {
.enable_reg = 0x1034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_maxi_clk = {
.halt_reg = 0x1038,
.clkr = {
.enable_reg = 0x1038,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_maxi_clk",
.parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch video_subcore0_clk = {
.halt_reg = 0x1048,
.clkr = {
.enable_reg = 0x1048,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_subcore0_clk",
.parent_hws = (const struct clk_hw *[]){ &video_subcore0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch video_subcore1_clk = {
.halt_reg = 0x104c,
.clkr = {
.enable_reg = 0x104c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "video_subcore1_clk",
.parent_hws = (const struct clk_hw *[]){ &video_subcore1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdss_ahb_clk = {
.halt_reg = 0x2308,
.hwcg_reg = 0x2308,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2308,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdss_hdmi_dp_ahb_clk = {
.halt_reg = 0x230c,
.clkr = {
.enable_reg = 0x230c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_hdmi_dp_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdss_axi_clk = {
.halt_reg = 0x2310,
.clkr = {
.enable_reg = 0x2310,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mdss_pclk0_clk = {
.halt_reg = 0x2314,
.clkr = {
.enable_reg = 0x2314,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_pclk0_clk",
.parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdss_pclk1_clk = {
.halt_reg = 0x2318,
.clkr = {
.enable_reg = 0x2318,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_pclk1_clk",
.parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdss_mdp_clk = {
.halt_reg = 0x231c,
.clkr = {
.enable_reg = 0x231c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_mdp_clk",
.parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdss_mdp_lut_clk = {
.halt_reg = 0x2320,
.clkr = {
.enable_reg = 0x2320,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_mdp_lut_clk",
.parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdss_extpclk_clk = {
.halt_reg = 0x2324,
.clkr = {
.enable_reg = 0x2324,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_extpclk_clk",
.parent_hws = (const struct clk_hw *[]){ &extpclk_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdss_vsync_clk = {
.halt_reg = 0x2328,
.clkr = {
.enable_reg = 0x2328,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_vsync_clk",
.parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdss_hdmi_clk = {
.halt_reg = 0x2338,
.clkr = {
.enable_reg = 0x2338,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_hdmi_clk",
.parent_hws = (const struct clk_hw *[]){ &hdmi_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdss_byte0_clk = {
.halt_reg = 0x233c,
.clkr = {
.enable_reg = 0x233c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_byte0_clk",
.parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdss_byte1_clk = {
.halt_reg = 0x2340,
.clkr = {
.enable_reg = 0x2340,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_byte1_clk",
.parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdss_esc0_clk = {
.halt_reg = 0x2344,
.clkr = {
.enable_reg = 0x2344,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_esc0_clk",
.parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdss_esc1_clk = {
.halt_reg = 0x2348,
.clkr = {
.enable_reg = 0x2348,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_esc1_clk",
.parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdss_rot_clk = {
.halt_reg = 0x2350,
.clkr = {
.enable_reg = 0x2350,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_rot_clk",
.parent_hws = (const struct clk_hw *[]){ &rot_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdss_dp_link_clk = {
.halt_reg = 0x2354,
.clkr = {
.enable_reg = 0x2354,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_dp_link_clk",
.parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdss_dp_link_intf_clk = {
.halt_reg = 0x2358,
.clkr = {
.enable_reg = 0x2358,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_dp_link_intf_clk",
.parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdss_dp_crypto_clk = {
.halt_reg = 0x235c,
.clkr = {
.enable_reg = 0x235c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_dp_crypto_clk",
.parent_hws = (const struct clk_hw *[]){ &dp_crypto_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdss_dp_pixel_clk = {
.halt_reg = 0x2360,
.clkr = {
.enable_reg = 0x2360,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_dp_pixel_clk",
.parent_hws = (const struct clk_hw *[]){ &dp_pixel_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdss_dp_aux_clk = {
.halt_reg = 0x2364,
.clkr = {
.enable_reg = 0x2364,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_dp_aux_clk",
.parent_hws = (const struct clk_hw *[]){ &dp_aux_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdss_byte0_intf_clk = {
.halt_reg = 0x2374,
.clkr = {
.enable_reg = 0x2374,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_byte0_intf_clk",
.parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mdss_byte1_intf_clk = {
.halt_reg = 0x2378,
.clkr = {
.enable_reg = 0x2378,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_byte1_intf_clk",
.parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csi0phytimer_clk = {
.halt_reg = 0x3024,
.clkr = {
.enable_reg = 0x3024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0phytimer_clk",
.parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csi1phytimer_clk = {
.halt_reg = 0x3054,
.clkr = {
.enable_reg = 0x3054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1phytimer_clk",
.parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csi2phytimer_clk = {
.halt_reg = 0x3084,
.clkr = {
.enable_reg = 0x3084,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2phytimer_clk",
.parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csi0_clk = {
.halt_reg = 0x30b4,
.clkr = {
.enable_reg = 0x30b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0_clk",
.parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csi0_ahb_clk = {
.halt_reg = 0x30bc,
.clkr = {
.enable_reg = 0x30bc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csi0rdi_clk = {
.halt_reg = 0x30d4,
.clkr = {
.enable_reg = 0x30d4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0rdi_clk",
.parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csi0pix_clk = {
.halt_reg = 0x30e4,
.clkr = {
.enable_reg = 0x30e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0pix_clk",
.parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csi1_clk = {
.halt_reg = 0x3124,
.clkr = {
.enable_reg = 0x3124,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1_clk",
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csi1_ahb_clk = {
.halt_reg = 0x3128,
.clkr = {
.enable_reg = 0x3128,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csi1rdi_clk = {
.halt_reg = 0x3144,
.clkr = {
.enable_reg = 0x3144,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1rdi_clk",
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csi1pix_clk = {
.halt_reg = 0x3154,
.clkr = {
.enable_reg = 0x3154,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1pix_clk",
.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csi2_clk = {
.halt_reg = 0x3184,
.clkr = {
.enable_reg = 0x3184,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2_clk",
.parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csi2_ahb_clk = {
.halt_reg = 0x3188,
.clkr = {
.enable_reg = 0x3188,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csi2rdi_clk = {
.halt_reg = 0x31a4,
.clkr = {
.enable_reg = 0x31a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2rdi_clk",
.parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csi2pix_clk = {
.halt_reg = 0x31b4,
.clkr = {
.enable_reg = 0x31b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2pix_clk",
.parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csi3_clk = {
.halt_reg = 0x31e4,
.clkr = {
.enable_reg = 0x31e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3_clk",
.parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csi3_ahb_clk = {
.halt_reg = 0x31e8,
.clkr = {
.enable_reg = 0x31e8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csi3rdi_clk = {
.halt_reg = 0x3204,
.clkr = {
.enable_reg = 0x3204,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3rdi_clk",
.parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csi3pix_clk = {
.halt_reg = 0x3214,
.clkr = {
.enable_reg = 0x3214,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3pix_clk",
.parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_ispif_ahb_clk = {
.halt_reg = 0x3224,
.clkr = {
.enable_reg = 0x3224,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_ispif_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_cci_clk = {
.halt_reg = 0x3344,
.clkr = {
.enable_reg = 0x3344,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cci_clk",
.parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_cci_ahb_clk = {
.halt_reg = 0x3348,
.clkr = {
.enable_reg = 0x3348,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cci_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_mclk0_clk = {
.halt_reg = 0x3384,
.clkr = {
.enable_reg = 0x3384,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk0_clk",
.parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_mclk1_clk = {
.halt_reg = 0x33b4,
.clkr = {
.enable_reg = 0x33b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk1_clk",
.parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_mclk2_clk = {
.halt_reg = 0x33e4,
.clkr = {
.enable_reg = 0x33e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk2_clk",
.parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_mclk3_clk = {
.halt_reg = 0x3414,
.clkr = {
.enable_reg = 0x3414,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk3_clk",
.parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_top_ahb_clk = {
.halt_reg = 0x3484,
.clkr = {
.enable_reg = 0x3484,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_top_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_ahb_clk = {
.halt_reg = 0x348c,
.clkr = {
.enable_reg = 0x348c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_micro_ahb_clk = {
.halt_reg = 0x3494,
.clkr = {
.enable_reg = 0x3494,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_micro_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_jpeg0_clk = {
.halt_reg = 0x35a8,
.clkr = {
.enable_reg = 0x35a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg0_clk",
.parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_jpeg_ahb_clk = {
.halt_reg = 0x35b4,
.clkr = {
.enable_reg = 0x35b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_jpeg_axi_clk = {
.halt_reg = 0x35b8,
.clkr = {
.enable_reg = 0x35b8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_vfe0_ahb_clk = {
.halt_reg = 0x3668,
.clkr = {
.enable_reg = 0x3668,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe0_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_vfe1_ahb_clk = {
.halt_reg = 0x3678,
.clkr = {
.enable_reg = 0x3678,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe1_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_vfe0_clk = {
.halt_reg = 0x36a8,
.clkr = {
.enable_reg = 0x36a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe0_clk",
.parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_vfe1_clk = {
.halt_reg = 0x36ac,
.clkr = {
.enable_reg = 0x36ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe1_clk",
.parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_cpp_clk = {
.halt_reg = 0x36b0,
.clkr = {
.enable_reg = 0x36b0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cpp_clk",
.parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_cpp_ahb_clk = {
.halt_reg = 0x36b4,
.clkr = {
.enable_reg = 0x36b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cpp_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_vfe_vbif_ahb_clk = {
.halt_reg = 0x36b8,
.clkr = {
.enable_reg = 0x36b8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vbif_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_vfe_vbif_axi_clk = {
.halt_reg = 0x36bc,
.clkr = {
.enable_reg = 0x36bc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vbif_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cpp_axi_clk = {
.halt_reg = 0x36c4,
.clkr = {
.enable_reg = 0x36c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cpp_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch camss_cpp_vbif_ahb_clk = {
.halt_reg = 0x36c8,
.clkr = {
.enable_reg = 0x36c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cpp_vbif_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csi_vfe0_clk = {
.halt_reg = 0x3704,
.clkr = {
.enable_reg = 0x3704,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi_vfe0_clk",
.parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csi_vfe1_clk = {
.halt_reg = 0x3714,
.clkr = {
.enable_reg = 0x3714,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi_vfe1_clk",
.parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_vfe0_stream_clk = {
.halt_reg = 0x3720,
.clkr = {
.enable_reg = 0x3720,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe0_stream_clk",
.parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_vfe1_stream_clk = {
.halt_reg = 0x3724,
.clkr = {
.enable_reg = 0x3724,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe1_stream_clk",
.parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_cphy_csid0_clk = {
.halt_reg = 0x3730,
.clkr = {
.enable_reg = 0x3730,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cphy_csid0_clk",
.parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_cphy_csid1_clk = {
.halt_reg = 0x3734,
.clkr = {
.enable_reg = 0x3734,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cphy_csid1_clk",
.parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_cphy_csid2_clk = {
.halt_reg = 0x3738,
.clkr = {
.enable_reg = 0x3738,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cphy_csid2_clk",
.parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_cphy_csid3_clk = {
.halt_reg = 0x373c,
.clkr = {
.enable_reg = 0x373c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cphy_csid3_clk",
.parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csiphy0_clk = {
.halt_reg = 0x3740,
.clkr = {
.enable_reg = 0x3740,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csiphy0_clk",
.parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csiphy1_clk = {
.halt_reg = 0x3744,
.clkr = {
.enable_reg = 0x3744,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csiphy1_clk",
.parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch camss_csiphy2_clk = {
.halt_reg = 0x3748,
.clkr = {
.enable_reg = 0x3748,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csiphy2_clk",
.parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch fd_core_clk = {
.halt_reg = 0x3b68,
.clkr = {
.enable_reg = 0x3b68,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "fd_core_clk",
.parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch fd_core_uar_clk = {
.halt_reg = 0x3b6c,
.clkr = {
.enable_reg = 0x3b6c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "fd_core_uar_clk",
.parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch fd_ahb_clk = {
.halt_reg = 0x3b74,
.clkr = {
.enable_reg = 0x3b74,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "fd_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch mnoc_ahb_clk = {
.halt_reg = 0x5024,
.clkr = {
.enable_reg = 0x5024,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mnoc_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch bimc_smmu_ahb_clk = {
.halt_reg = 0xe004,
.hwcg_reg = 0xe004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xe004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "bimc_smmu_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch bimc_smmu_axi_clk = {
.halt_reg = 0xe008,
.hwcg_reg = 0xe008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xe008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "bimc_smmu_axi_clk",
.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch mnoc_maxi_clk = {
.halt_reg = 0xf004,
.clkr = {
.enable_reg = 0xf004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mnoc_maxi_clk",
.parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch vmem_maxi_clk = {
.halt_reg = 0xf064,
.clkr = {
.enable_reg = 0xf064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vmem_maxi_clk",
.parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct clk_branch vmem_ahb_clk = {
.halt_reg = 0xf068,
.clkr = {
.enable_reg = 0xf068,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vmem_ahb_clk",
.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_SET_RATE_PARENT,
},
},
};
static struct gdsc video_top_gdsc = {
.gdscr = 0x1024,
.pd = {
.name = "video_top",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc video_subcore0_gdsc = {
.gdscr = 0x1040,
.pd = {
.name = "video_subcore0",
},
.parent = &video_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc video_subcore1_gdsc = {
.gdscr = 0x1044,
.pd = {
.name = "video_subcore1",
},
.parent = &video_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x2304,
.cxcs = (unsigned int []){ 0x2310, 0x2350, 0x231c, 0x2320 },
.cxc_count = 4,
.pd = {
.name = "mdss",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc camss_top_gdsc = {
.gdscr = 0x34a0,
.cxcs = (unsigned int []){ 0x35b8, 0x36c4, 0x3704, 0x3714, 0x3494,
0x35a8, 0x3868 },
.cxc_count = 7,
.pd = {
.name = "camss_top",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc camss_vfe0_gdsc = {
.gdscr = 0x3664,
.pd = {
.name = "camss_vfe0",
},
.parent = &camss_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc camss_vfe1_gdsc = {
.gdscr = 0x3674,
.pd = {
.name = "camss_vfe1_gdsc",
},
.parent = &camss_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc camss_cpp_gdsc = {
.gdscr = 0x36d4,
.pd = {
.name = "camss_cpp",
},
.parent = &camss_top_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc bimc_smmu_gdsc = {
.gdscr = 0xe020,
.gds_hw_ctrl = 0xe024,
.pd = {
.name = "bimc_smmu",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL | ALWAYS_ON,
};
static struct clk_regmap *mmcc_msm8998_clocks[] = {
[MMPLL0] = &mmpll0.clkr,
[MMPLL0_OUT_EVEN] = &mmpll0_out_even.clkr,
[MMPLL1] = &mmpll1.clkr,
[MMPLL1_OUT_EVEN] = &mmpll1_out_even.clkr,
[MMPLL3] = &mmpll3.clkr,
[MMPLL3_OUT_EVEN] = &mmpll3_out_even.clkr,
[MMPLL4] = &mmpll4.clkr,
[MMPLL4_OUT_EVEN] = &mmpll4_out_even.clkr,
[MMPLL5] = &mmpll5.clkr,
[MMPLL5_OUT_EVEN] = &mmpll5_out_even.clkr,
[MMPLL6] = &mmpll6.clkr,
[MMPLL6_OUT_EVEN] = &mmpll6_out_even.clkr,
[MMPLL7] = &mmpll7.clkr,
[MMPLL7_OUT_EVEN] = &mmpll7_out_even.clkr,
[MMPLL10] = &mmpll10.clkr,
[MMPLL10_OUT_EVEN] = &mmpll10_out_even.clkr,
[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
[BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
[CCI_CLK_SRC] = &cci_clk_src.clkr,
[CPP_CLK_SRC] = &cpp_clk_src.clkr,
[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
[CSI3_CLK_SRC] = &csi3_clk_src.clkr,
[CSIPHY_CLK_SRC] = &csiphy_clk_src.clkr,
[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
[CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
[DP_AUX_CLK_SRC] = &dp_aux_clk_src.clkr,
[DP_CRYPTO_CLK_SRC] = &dp_crypto_clk_src.clkr,
[DP_LINK_CLK_SRC] = &dp_link_clk_src.clkr,
[DP_PIXEL_CLK_SRC] = &dp_pixel_clk_src.clkr,
[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
[ESC1_CLK_SRC] = &esc1_clk_src.clkr,
[EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
[FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
[HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
[MAXI_CLK_SRC] = &maxi_clk_src.clkr,
[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
[MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
[MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
[MDP_CLK_SRC] = &mdp_clk_src.clkr,
[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
[AHB_CLK_SRC] = &ahb_clk_src.clkr,
[AXI_CLK_SRC] = &axi_clk_src.clkr,
[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
[PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
[ROT_CLK_SRC] = &rot_clk_src.clkr,
[VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
[VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr,
[VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr,
[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
[VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
[MISC_AHB_CLK] = &misc_ahb_clk.clkr,
[VIDEO_CORE_CLK] = &video_core_clk.clkr,
[VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
[VIDEO_AXI_CLK] = &video_axi_clk.clkr,
[VIDEO_MAXI_CLK] = &video_maxi_clk.clkr,
[VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
[VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr,
[MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
[MDSS_HDMI_DP_AHB_CLK] = &mdss_hdmi_dp_ahb_clk.clkr,
[MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
[MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
[MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
[MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
[MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
[MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
[MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
[MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
[MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
[MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
[MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
[MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
[MDSS_ROT_CLK] = &mdss_rot_clk.clkr,
[MDSS_DP_LINK_CLK] = &mdss_dp_link_clk.clkr,
[MDSS_DP_LINK_INTF_CLK] = &mdss_dp_link_intf_clk.clkr,
[MDSS_DP_CRYPTO_CLK] = &mdss_dp_crypto_clk.clkr,
[MDSS_DP_PIXEL_CLK] = &mdss_dp_pixel_clk.clkr,
[MDSS_DP_AUX_CLK] = &mdss_dp_aux_clk.clkr,
[MDSS_BYTE0_INTF_CLK] = &mdss_byte0_intf_clk.clkr,
[MDSS_BYTE1_INTF_CLK] = &mdss_byte1_intf_clk.clkr,
[CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
[CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
[CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
[CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
[CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
[CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
[CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
[CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
[CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
[CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
[CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
[CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
[CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
[CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
[CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
[CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
[CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
[CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
[CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
[CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
[CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
[CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
[CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
[CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
[CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
[CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
[CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
[CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
[CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
[CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
[CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
[CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
[CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
[CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
[CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
[CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
[CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
[CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
[CAMSS_VFE_VBIF_AHB_CLK] = &camss_vfe_vbif_ahb_clk.clkr,
[CAMSS_VFE_VBIF_AXI_CLK] = &camss_vfe_vbif_axi_clk.clkr,
[CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
[CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
[CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
[CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
[CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
[CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
[CAMSS_CPHY_CSID0_CLK] = &camss_cphy_csid0_clk.clkr,
[CAMSS_CPHY_CSID1_CLK] = &camss_cphy_csid1_clk.clkr,
[CAMSS_CPHY_CSID2_CLK] = &camss_cphy_csid2_clk.clkr,
[CAMSS_CPHY_CSID3_CLK] = &camss_cphy_csid3_clk.clkr,
[CAMSS_CSIPHY0_CLK] = &camss_csiphy0_clk.clkr,
[CAMSS_CSIPHY1_CLK] = &camss_csiphy1_clk.clkr,
[CAMSS_CSIPHY2_CLK] = &camss_csiphy2_clk.clkr,
[FD_CORE_CLK] = &fd_core_clk.clkr,
[FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
[FD_AHB_CLK] = &fd_ahb_clk.clkr,
[MNOC_AHB_CLK] = &mnoc_ahb_clk.clkr,
[BIMC_SMMU_AHB_CLK] = &bimc_smmu_ahb_clk.clkr,
[BIMC_SMMU_AXI_CLK] = &bimc_smmu_axi_clk.clkr,
[MNOC_MAXI_CLK] = &mnoc_maxi_clk.clkr,
[VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr,
[VMEM_AHB_CLK] = &vmem_ahb_clk.clkr,
};
static struct gdsc *mmcc_msm8998_gdscs[] = {
[VIDEO_TOP_GDSC] = &video_top_gdsc,
[VIDEO_SUBCORE0_GDSC] = &video_subcore0_gdsc,
[VIDEO_SUBCORE1_GDSC] = &video_subcore1_gdsc,
[MDSS_GDSC] = &mdss_gdsc,
[CAMSS_TOP_GDSC] = &camss_top_gdsc,
[CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc,
[CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc,
[CAMSS_CPP_GDSC] = &camss_cpp_gdsc,
[BIMC_SMMU_GDSC] = &bimc_smmu_gdsc,
};
static const struct qcom_reset_map mmcc_msm8998_resets[] = {
[SPDM_BCR] = { 0x200 },
[SPDM_RM_BCR] = { 0x300 },
[MISC_BCR] = { 0x320 },
[VIDEO_TOP_BCR] = { 0x1020 },
[THROTTLE_VIDEO_BCR] = { 0x1180 },
[MDSS_BCR] = { 0x2300 },
[THROTTLE_MDSS_BCR] = { 0x2460 },
[CAMSS_PHY0_BCR] = { 0x3020 },
[CAMSS_PHY1_BCR] = { 0x3050 },
[CAMSS_PHY2_BCR] = { 0x3080 },
[CAMSS_CSI0_BCR] = { 0x30b0 },
[CAMSS_CSI0RDI_BCR] = { 0x30d0 },
[CAMSS_CSI0PIX_BCR] = { 0x30e0 },
[CAMSS_CSI1_BCR] = { 0x3120 },
[CAMSS_CSI1RDI_BCR] = { 0x3140 },
[CAMSS_CSI1PIX_BCR] = { 0x3150 },
[CAMSS_CSI2_BCR] = { 0x3180 },
[CAMSS_CSI2RDI_BCR] = { 0x31a0 },
[CAMSS_CSI2PIX_BCR] = { 0x31b0 },
[CAMSS_CSI3_BCR] = { 0x31e0 },
[CAMSS_CSI3RDI_BCR] = { 0x3200 },
[CAMSS_CSI3PIX_BCR] = { 0x3210 },
[CAMSS_ISPIF_BCR] = { 0x3220 },
[CAMSS_CCI_BCR] = { 0x3340 },
[CAMSS_TOP_BCR] = { 0x3480 },
[CAMSS_AHB_BCR] = { 0x3488 },
[CAMSS_MICRO_BCR] = { 0x3490 },
[CAMSS_JPEG_BCR] = { 0x35a0 },
[CAMSS_VFE0_BCR] = { 0x3660 },
[CAMSS_VFE1_BCR] = { 0x3670 },
[CAMSS_VFE_VBIF_BCR] = { 0x36a0 },
[CAMSS_CPP_TOP_BCR] = { 0x36c0 },
[CAMSS_CPP_BCR] = { 0x36d0 },
[CAMSS_CSI_VFE0_BCR] = { 0x3700 },
[CAMSS_CSI_VFE1_BCR] = { 0x3710 },
[CAMSS_FD_BCR] = { 0x3b60 },
[THROTTLE_CAMSS_BCR] = { 0x3c30 },
[MNOCAHB_BCR] = { 0x5020 },
[MNOCAXI_BCR] = { 0xd020 },
[BMIC_SMMU_BCR] = { 0xe000 },
[MNOC_MAXI_BCR] = { 0xf000 },
[VMEM_BCR] = { 0xf060 },
[BTO_BCR] = { 0x10004 },
};
static const struct regmap_config mmcc_msm8998_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x10004,
.fast_io = true,
};
static const struct qcom_cc_desc mmcc_msm8998_desc = {
.config = &mmcc_msm8998_regmap_config,
.clks = mmcc_msm8998_clocks,
.num_clks = ARRAY_SIZE(mmcc_msm8998_clocks),
.resets = mmcc_msm8998_resets,
.num_resets = ARRAY_SIZE(mmcc_msm8998_resets),
.gdscs = mmcc_msm8998_gdscs,
.num_gdscs = ARRAY_SIZE(mmcc_msm8998_gdscs),
};
static const struct of_device_id mmcc_msm8998_match_table[] = {
{ .compatible = "qcom,mmcc-msm8998" },
{ }
};
MODULE_DEVICE_TABLE(of, mmcc_msm8998_match_table);
static int mmcc_msm8998_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &mmcc_msm8998_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return qcom_cc_really_probe(pdev, &mmcc_msm8998_desc, regmap);
}
static struct platform_driver mmcc_msm8998_driver = {
.probe = mmcc_msm8998_probe,
.driver = {
.name = "mmcc-msm8998",
.of_match_table = mmcc_msm8998_match_table,
},
};
module_platform_driver(mmcc_msm8998_driver);
MODULE_DESCRIPTION("QCOM MMCC MSM8998 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/qcom/mmcc-msm8998.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include <dt-bindings/reset/qcom,gcc-msm8974.h>
#include "common.h"
#include "clk-regmap.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-branch.h"
#include "reset.h"
#include "gdsc.h"
enum {
P_XO,
P_GPLL0,
P_GPLL1,
P_GPLL4,
};
static struct clk_pll gpll0 = {
.l_reg = 0x0004,
.m_reg = 0x0008,
.n_reg = 0x000c,
.config_reg = 0x0014,
.mode_reg = 0x0000,
.status_reg = 0x001c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo", .name = "xo_board",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll0_vote = {
.enable_reg = 0x1480,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_vote",
.parent_hws = (const struct clk_hw*[]){
&gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static struct clk_pll gpll4 = {
.l_reg = 0x1dc4,
.m_reg = 0x1dc8,
.n_reg = 0x1dcc,
.config_reg = 0x1dd4,
.mode_reg = 0x1dc0,
.status_reg = 0x1ddc,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo", .name = "xo_board",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll4_vote = {
.enable_reg = 0x1480,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gpll4_vote",
.parent_hws = (const struct clk_hw*[]){
&gpll4.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static const struct parent_map gcc_xo_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 }
};
static const struct clk_parent_data gcc_xo_gpll0[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll0_vote.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
{ P_GPLL4, 5 }
};
static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll0_vote.hw },
{ .hw = &gpll4_vote.hw },
};
static struct clk_rcg2 config_noc_clk_src = {
.cmd_rcgr = 0x0150,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "config_noc_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 periph_noc_clk_src = {
.cmd_rcgr = 0x0190,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "periph_noc_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 system_noc_clk_src = {
.cmd_rcgr = 0x0120,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "system_noc_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_pll gpll1 = {
.l_reg = 0x0044,
.m_reg = 0x0048,
.n_reg = 0x004c,
.config_reg = 0x0054,
.mode_reg = 0x0040,
.status_reg = 0x005c,
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll1",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo", .name = "xo_board",
},
.num_parents = 1,
.ops = &clk_pll_ops,
},
};
static struct clk_regmap gpll1_vote = {
.enable_reg = 0x1480,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gpll1_vote",
.parent_hws = (const struct clk_hw*[]){
&gpll1.clkr.hw,
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
F(125000000, P_GPLL0, 1, 5, 24),
{ }
};
static struct clk_rcg2 usb30_master_clk_src = {
.cmd_rcgr = 0x03d4,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_usb30_master_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_master_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(37500000, P_GPLL0, 16, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x0660,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
F(15000000, P_GPLL0, 10, 1, 4),
F(19200000, P_XO, 1, 0, 0),
F(25000000, P_GPLL0, 12, 1, 2),
F(50000000, P_GPLL0, 12, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x064c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x06e0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x06cc,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x0760,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x074c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x07e0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x07cc,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
.cmd_rcgr = 0x0860,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
.cmd_rcgr = 0x084c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
.cmd_rcgr = 0x08e0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
.cmd_rcgr = 0x08cc,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = {
F(3686400, P_GPLL0, 1, 96, 15625),
F(7372800, P_GPLL0, 1, 192, 15625),
F(14745600, P_GPLL0, 1, 384, 15625),
F(16000000, P_GPLL0, 5, 2, 15),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 5, 1, 5),
F(32000000, P_GPLL0, 1, 4, 75),
F(40000000, P_GPLL0, 15, 0, 0),
F(46400000, P_GPLL0, 1, 29, 375),
F(48000000, P_GPLL0, 12.5, 0, 0),
F(51200000, P_GPLL0, 1, 32, 375),
F(56000000, P_GPLL0, 1, 7, 75),
F(58982400, P_GPLL0, 1, 1536, 15625),
F(60000000, P_GPLL0, 10, 0, 0),
F(63160000, P_GPLL0, 9.5, 0, 0),
{ }
};
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.cmd_rcgr = 0x068c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.cmd_rcgr = 0x070c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
.cmd_rcgr = 0x078c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart3_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
.cmd_rcgr = 0x080c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart4_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
.cmd_rcgr = 0x088c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart5_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
.cmd_rcgr = 0x090c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart6_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
.cmd_rcgr = 0x09a0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x098c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
.cmd_rcgr = 0x0a20,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x0a0c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x0aa0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x0a8c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
.cmd_rcgr = 0x0b20,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
.cmd_rcgr = 0x0b0c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
.cmd_rcgr = 0x0ba0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup5_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
.cmd_rcgr = 0x0b8c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup5_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
.cmd_rcgr = 0x0c20,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup6_i2c_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
.cmd_rcgr = 0x0c0c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup6_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
.cmd_rcgr = 0x09cc,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart1_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
.cmd_rcgr = 0x0a4c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart2_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
.cmd_rcgr = 0x0acc,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart3_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
.cmd_rcgr = 0x0b4c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart4_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
.cmd_rcgr = 0x0bcc,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart5_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
.cmd_rcgr = 0x0c4c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart6_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ce1_clk_msm8226[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
{ }
};
static const struct freq_tbl ftbl_gcc_ce1_clk[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 ce1_clk_src = {
.cmd_rcgr = 0x1050,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_ce1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ce1_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_ce2_clk[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(150000000, P_GPLL0, 4, 0, 0),
{ }
};
static struct clk_rcg2 ce2_clk_src = {
.cmd_rcgr = 0x1090,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_ce2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ce2_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_gp_clk_msm8226[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
static const struct freq_tbl ftbl_gcc_gp_clk[] = {
F(4800000, P_XO, 4, 0, 0),
F(6000000, P_GPLL0, 10, 1, 10),
F(6750000, P_GPLL0, 1, 1, 89),
F(8000000, P_GPLL0, 15, 1, 5),
F(9600000, P_XO, 2, 0, 0),
F(16000000, P_GPLL0, 1, 2, 75),
F(19200000, P_XO, 1, 0, 0),
F(24000000, P_GPLL0, 5, 1, 5),
{ }
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x1904,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_gp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp2_clk_src = {
.cmd_rcgr = 0x1944,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_gp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_rcg2 gp3_clk_src = {
.cmd_rcgr = 0x1984,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_gp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
F(60000000, P_GPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 pdm2_clk_src = {
.cmd_rcgr = 0x0cd0,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_pdm2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0, 15, 1, 2),
F(25000000, P_GPLL0, 12, 1, 2),
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
{ }
};
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_pro[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
F(20000000, P_GPLL0, 15, 1, 2),
F(25000000, P_GPLL0, 12, 1, 2),
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(192000000, P_GPLL4, 4, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
F(384000000, P_GPLL4, 2, 0, 0),
{ }
};
static struct clk_init_data sdcc1_apps_clk_src_init = {
.name = "sdcc1_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x04d0,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
.clkr.hw.init = &sdcc1_apps_clk_src_init,
};
static struct clk_rcg2 sdcc2_apps_clk_src = {
.cmd_rcgr = 0x0510,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
};
static struct clk_rcg2 sdcc3_apps_clk_src = {
.cmd_rcgr = 0x0550,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc3_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
};
static struct clk_rcg2 sdcc4_apps_clk_src = {
.cmd_rcgr = 0x0590,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc4_apps_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = {
F(105000, P_XO, 2, 1, 91),
{ }
};
static struct clk_rcg2 tsif_ref_clk_src = {
.cmd_rcgr = 0x0d90,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_tsif_ref_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "tsif_ref_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
F(60000000, P_GPLL0, 10, 0, 0),
{ }
};
static struct clk_rcg2 usb30_mock_utmi_clk_src = {
.cmd_rcgr = 0x03e8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_mock_utmi_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
F(60000000, P_GPLL0, 10, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 usb_hs_system_clk_src = {
.cmd_rcgr = 0x0490,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_usb_hs_system_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hs_system_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
F(480000000, P_GPLL1, 1, 0, 0),
{ }
};
static const struct parent_map usb_hsic_clk_src_map[] = {
{ P_XO, 0 },
{ P_GPLL1, 4 }
};
static struct clk_rcg2 usb_hsic_clk_src = {
.cmd_rcgr = 0x0440,
.hid_width = 5,
.parent_map = usb_hsic_clk_src_map,
.freq_tbl = ftbl_gcc_usb_hsic_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hsic_clk_src",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" },
{ .hw = &gpll1_vote.hw },
},
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
F(9600000, P_XO, 2, 0, 0),
{ }
};
static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
.cmd_rcgr = 0x0458,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hsic_io_cal_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
F(60000000, P_GPLL0, 10, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
{ }
};
static struct clk_rcg2 usb_hsic_system_clk_src = {
.cmd_rcgr = 0x041c,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gcc_usb_hsic_system_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hsic_system_clk_src",
.parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap gcc_mmss_gpll0_clk_src = {
.enable_reg = 0x1484,
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "mmss_gpll0_vote",
.parent_hws = (const struct clk_hw*[]){
&gpll0_vote.hw,
},
.num_parents = 1,
.ops = &clk_branch_simple_ops,
},
};
static struct clk_branch gcc_bam_dma_ahb_clk = {
.halt_reg = 0x0d44,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_bam_dma_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x05c4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.halt_reg = 0x0648,
.clkr = {
.enable_reg = 0x0648,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.halt_reg = 0x0644,
.clkr = {
.enable_reg = 0x0644,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.halt_reg = 0x06c8,
.clkr = {
.enable_reg = 0x06c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.halt_reg = 0x06c4,
.clkr = {
.enable_reg = 0x06c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.halt_reg = 0x0748,
.clkr = {
.enable_reg = 0x0748,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.halt_reg = 0x0744,
.clkr = {
.enable_reg = 0x0744,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.halt_reg = 0x07c8,
.clkr = {
.enable_reg = 0x07c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.halt_reg = 0x07c4,
.clkr = {
.enable_reg = 0x07c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
.halt_reg = 0x0848,
.clkr = {
.enable_reg = 0x0848,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup5_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
.halt_reg = 0x0844,
.clkr = {
.enable_reg = 0x0844,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup5_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
.halt_reg = 0x08c8,
.clkr = {
.enable_reg = 0x08c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup6_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
.halt_reg = 0x08c4,
.clkr = {
.enable_reg = 0x08c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_qup6_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.halt_reg = 0x0684,
.clkr = {
.enable_reg = 0x0684,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.halt_reg = 0x0704,
.clkr = {
.enable_reg = 0x0704,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart3_apps_clk = {
.halt_reg = 0x0784,
.clkr = {
.enable_reg = 0x0784,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart3_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart4_apps_clk = {
.halt_reg = 0x0804,
.clkr = {
.enable_reg = 0x0804,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart4_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart5_apps_clk = {
.halt_reg = 0x0884,
.clkr = {
.enable_reg = 0x0884,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart5_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart5_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp1_uart6_apps_clk = {
.halt_reg = 0x0904,
.clkr = {
.enable_reg = 0x0904,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart6_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp1_uart6_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_ahb_clk = {
.halt_reg = 0x0944,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
.halt_reg = 0x0988,
.clkr = {
.enable_reg = 0x0988,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup1_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
.halt_reg = 0x0984,
.clkr = {
.enable_reg = 0x0984,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup1_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
.halt_reg = 0x0a08,
.clkr = {
.enable_reg = 0x0a08,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup2_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
.halt_reg = 0x0a04,
.clkr = {
.enable_reg = 0x0a04,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup2_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
.halt_reg = 0x0a88,
.clkr = {
.enable_reg = 0x0a88,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup3_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
.halt_reg = 0x0a84,
.clkr = {
.enable_reg = 0x0a84,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup3_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
.halt_reg = 0x0b08,
.clkr = {
.enable_reg = 0x0b08,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup4_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
.halt_reg = 0x0b04,
.clkr = {
.enable_reg = 0x0b04,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup4_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
.halt_reg = 0x0b88,
.clkr = {
.enable_reg = 0x0b88,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup5_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup5_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
.halt_reg = 0x0b84,
.clkr = {
.enable_reg = 0x0b84,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup5_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup5_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
.halt_reg = 0x0c08,
.clkr = {
.enable_reg = 0x0c08,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup6_i2c_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup6_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
.halt_reg = 0x0c04,
.clkr = {
.enable_reg = 0x0c04,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup6_spi_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_qup6_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart1_apps_clk = {
.halt_reg = 0x09c4,
.clkr = {
.enable_reg = 0x09c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart2_apps_clk = {
.halt_reg = 0x0a44,
.clkr = {
.enable_reg = 0x0a44,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart3_apps_clk = {
.halt_reg = 0x0ac4,
.clkr = {
.enable_reg = 0x0ac4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart3_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart3_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart4_apps_clk = {
.halt_reg = 0x0b44,
.clkr = {
.enable_reg = 0x0b44,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart4_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart5_apps_clk = {
.halt_reg = 0x0bc4,
.clkr = {
.enable_reg = 0x0bc4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart5_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart5_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_blsp2_uart6_apps_clk = {
.halt_reg = 0x0c44,
.clkr = {
.enable_reg = 0x0c44,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart6_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&blsp2_uart6_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x0e04,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_ahb_clk = {
.halt_reg = 0x104c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_axi_clk = {
.halt_reg = 0x1048,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce1_clk = {
.halt_reg = 0x1050,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce1_clk",
.parent_hws = (const struct clk_hw*[]){
&ce1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce2_ahb_clk = {
.halt_reg = 0x108c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce2_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce2_axi_clk = {
.halt_reg = 0x1088,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce2_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ce2_clk = {
.halt_reg = 0x1090,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_ce2_clk",
.parent_hws = (const struct clk_hw*[]){
&ce2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x1900,
.clkr = {
.enable_reg = 0x1900,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]){
&gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x1940,
.clkr = {
.enable_reg = 0x1940,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]){
&gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x1980,
.clkr = {
.enable_reg = 0x1980,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]){
&gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_lpass_q6_axi_clk = {
.halt_reg = 0x11c0,
.clkr = {
.enable_reg = 0x11c0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_lpass_q6_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
.halt_reg = 0x024c,
.clkr = {
.enable_reg = 0x024c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mmss_noc_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
.flags = CLK_IGNORE_UNUSED,
},
},
};
static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
.halt_reg = 0x0248,
.clkr = {
.enable_reg = 0x0248,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ocmem_noc_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_cfg_ahb_clk = {
.halt_reg = 0x0280,
.clkr = {
.enable_reg = 0x0280,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_cfg_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&config_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.halt_reg = 0x0284,
.clkr = {
.enable_reg = 0x0284,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_q6_bimc_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&system_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x0ccc,
.clkr = {
.enable_reg = 0x0ccc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]){
&pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x0cc4,
.clkr = {
.enable_reg = 0x0cc4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x0cc8,
.clkr = {
.enable_reg = 0x0cc8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_xo4_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "xo", .name = "xo_board",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x0d04,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0x04c8,
.clkr = {
.enable_reg = 0x04c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0x04c4,
.clkr = {
.enable_reg = 0x04c4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_cdccal_ff_clk = {
.halt_reg = 0x04e8,
.clkr = {
.enable_reg = 0x04e8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_cdccal_ff_clk",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "xo", .name = "xo_board" }
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = {
.halt_reg = 0x04e4,
.clkr = {
.enable_reg = 0x04e4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_cdccal_sleep_clk",
.parent_data = (const struct clk_parent_data[]){
{ .fw_name = "sleep_clk", .name = "sleep_clk" }
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x0508,
.clkr = {
.enable_reg = 0x0508,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x0504,
.clkr = {
.enable_reg = 0x0504,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc3_ahb_clk = {
.halt_reg = 0x0548,
.clkr = {
.enable_reg = 0x0548,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc3_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc3_apps_clk = {
.halt_reg = 0x0544,
.clkr = {
.enable_reg = 0x0544,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc3_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc3_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_ahb_clk = {
.halt_reg = 0x0588,
.clkr = {
.enable_reg = 0x0588,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc4_apps_clk = {
.halt_reg = 0x0584,
.clkr = {
.enable_reg = 0x0584,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk",
.parent_hws = (const struct clk_hw*[]){
&sdcc4_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
.halt_reg = 0x0108,
.clkr = {
.enable_reg = 0x0108,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb3_axi_clk",
.parent_hws = (const struct clk_hw*[]){
&usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ahb_clk = {
.halt_reg = 0x0d84,
.clkr = {
.enable_reg = 0x0d84,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_tsif_ref_clk = {
.halt_reg = 0x0d88,
.clkr = {
.enable_reg = 0x0d88,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ref_clk",
.parent_hws = (const struct clk_hw*[]){
&tsif_ref_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb2a_phy_sleep_clk = {
.halt_reg = 0x04ac,
.clkr = {
.enable_reg = 0x04ac,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb2a_phy_sleep_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep_clk", .name = "sleep_clk",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb2b_phy_sleep_clk = {
.halt_reg = 0x04b4,
.clkr = {
.enable_reg = 0x04b4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb2b_phy_sleep_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep_clk", .name = "sleep_clk",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_master_clk = {
.halt_reg = 0x03c8,
.clkr = {
.enable_reg = 0x03c8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_master_clk",
.parent_hws = (const struct clk_hw*[]){
&usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_mock_utmi_clk = {
.halt_reg = 0x03d0,
.clkr = {
.enable_reg = 0x03d0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]){
&usb30_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_sleep_clk = {
.halt_reg = 0x03cc,
.clkr = {
.enable_reg = 0x03cc,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sleep_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep_clk", .name = "sleep_clk",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_ahb_clk = {
.halt_reg = 0x0488,
.clkr = {
.enable_reg = 0x0488,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hs_system_clk = {
.halt_reg = 0x0484,
.clkr = {
.enable_reg = 0x0484,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_system_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_hs_system_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hsic_ahb_clk = {
.halt_reg = 0x0408,
.clkr = {
.enable_reg = 0x0408,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hsic_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&periph_noc_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hsic_clk = {
.halt_reg = 0x0410,
.clkr = {
.enable_reg = 0x0410,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hsic_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_hsic_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hsic_io_cal_clk = {
.halt_reg = 0x0414,
.clkr = {
.enable_reg = 0x0414,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hsic_io_cal_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_hsic_io_cal_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
.halt_reg = 0x0418,
.clkr = {
.enable_reg = 0x0418,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hsic_io_cal_sleep_clk",
.parent_data = &(const struct clk_parent_data){
.fw_name = "sleep_clk", .name = "sleep_clk",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb_hsic_system_clk = {
.halt_reg = 0x040c,
.clkr = {
.enable_reg = 0x040c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hsic_system_clk",
.parent_hws = (const struct clk_hw*[]){
&usb_hsic_system_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc usb_hs_hsic_gdsc = {
.gdscr = 0x404,
.pd = {
.name = "usb_hs_hsic",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *gcc_msm8226_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL0_VOTE] = &gpll0_vote,
[GPLL1] = &gpll1.clkr,
[GPLL1_VOTE] = &gpll1_vote,
[CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
[PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
[SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
[CE1_CLK_SRC] = &ce1_clk_src.clkr,
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
[SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
[USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
[USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
[USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
[GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
[GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
[GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
[GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
[GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
[GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
[GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
[GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
};
static const struct qcom_reset_map gcc_msm8226_resets[] = {
[GCC_USB_HS_HSIC_BCR] = { 0x0400 },
[GCC_USB_HS_BCR] = { 0x0480 },
[GCC_USB2A_PHY_BCR] = { 0x04a8 },
};
static struct gdsc *gcc_msm8226_gdscs[] = {
[USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc,
};
static const struct regmap_config gcc_msm8226_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x1a80,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_msm8226_desc = {
.config = &gcc_msm8226_regmap_config,
.clks = gcc_msm8226_clocks,
.num_clks = ARRAY_SIZE(gcc_msm8226_clocks),
.resets = gcc_msm8226_resets,
.num_resets = ARRAY_SIZE(gcc_msm8226_resets),
.gdscs = gcc_msm8226_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_msm8226_gdscs),
};
static struct clk_regmap *gcc_msm8974_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL0_VOTE] = &gpll0_vote,
[CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
[PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
[SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
[GPLL1] = &gpll1.clkr,
[GPLL1_VOTE] = &gpll1_vote,
[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
[BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
[BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
[BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
[BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
[BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
[BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
[BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
[BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
[BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
[BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
[BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
[BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
[BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
[BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
[BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
[BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
[BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
[BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
[CE1_CLK_SRC] = &ce1_clk_src.clkr,
[CE2_CLK_SRC] = &ce2_clk_src.clkr,
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
[SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
[SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
[TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
[USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
[USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
[USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
[USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
[GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
[GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
[GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
[GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
[GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
[GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
[GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
[GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
[GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
[GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
[GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
[GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
[GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
[GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
[GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
[GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
[GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr,
[GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr,
[GCC_CE2_CLK] = &gcc_ce2_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
[GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
[GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr,
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
[GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
[GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
[GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr,
[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
[GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
[GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
[GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
[GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
[GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
[GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src,
[GPLL4] = NULL,
[GPLL4_VOTE] = NULL,
[GCC_SDCC1_CDCCAL_SLEEP_CLK] = NULL,
[GCC_SDCC1_CDCCAL_FF_CLK] = NULL,
};
static const struct qcom_reset_map gcc_msm8974_resets[] = {
[GCC_SYSTEM_NOC_BCR] = { 0x0100 },
[GCC_CONFIG_NOC_BCR] = { 0x0140 },
[GCC_PERIPH_NOC_BCR] = { 0x0180 },
[GCC_IMEM_BCR] = { 0x0200 },
[GCC_MMSS_BCR] = { 0x0240 },
[GCC_QDSS_BCR] = { 0x0300 },
[GCC_USB_30_BCR] = { 0x03c0 },
[GCC_USB3_PHY_BCR] = { 0x03fc },
[GCC_USB_HS_HSIC_BCR] = { 0x0400 },
[GCC_USB_HS_BCR] = { 0x0480 },
[GCC_USB2A_PHY_BCR] = { 0x04a8 },
[GCC_USB2B_PHY_BCR] = { 0x04b0 },
[GCC_SDCC1_BCR] = { 0x04c0 },
[GCC_SDCC2_BCR] = { 0x0500 },
[GCC_SDCC3_BCR] = { 0x0540 },
[GCC_SDCC4_BCR] = { 0x0580 },
[GCC_BLSP1_BCR] = { 0x05c0 },
[GCC_BLSP1_QUP1_BCR] = { 0x0640 },
[GCC_BLSP1_UART1_BCR] = { 0x0680 },
[GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
[GCC_BLSP1_UART2_BCR] = { 0x0700 },
[GCC_BLSP1_QUP3_BCR] = { 0x0740 },
[GCC_BLSP1_UART3_BCR] = { 0x0780 },
[GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
[GCC_BLSP1_UART4_BCR] = { 0x0800 },
[GCC_BLSP1_QUP5_BCR] = { 0x0840 },
[GCC_BLSP1_UART5_BCR] = { 0x0880 },
[GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
[GCC_BLSP1_UART6_BCR] = { 0x0900 },
[GCC_BLSP2_BCR] = { 0x0940 },
[GCC_BLSP2_QUP1_BCR] = { 0x0980 },
[GCC_BLSP2_UART1_BCR] = { 0x09c0 },
[GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
[GCC_BLSP2_UART2_BCR] = { 0x0a40 },
[GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
[GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
[GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
[GCC_BLSP2_UART4_BCR] = { 0x0b40 },
[GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
[GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
[GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
[GCC_BLSP2_UART6_BCR] = { 0x0c40 },
[GCC_PDM_BCR] = { 0x0cc0 },
[GCC_BAM_DMA_BCR] = { 0x0d40 },
[GCC_TSIF_BCR] = { 0x0d80 },
[GCC_TCSR_BCR] = { 0x0dc0 },
[GCC_BOOT_ROM_BCR] = { 0x0e00 },
[GCC_MSG_RAM_BCR] = { 0x0e40 },
[GCC_TLMM_BCR] = { 0x0e80 },
[GCC_MPM_BCR] = { 0x0ec0 },
[GCC_SEC_CTRL_BCR] = { 0x0f40 },
[GCC_SPMI_BCR] = { 0x0fc0 },
[GCC_SPDM_BCR] = { 0x1000 },
[GCC_CE1_BCR] = { 0x1040 },
[GCC_CE2_BCR] = { 0x1080 },
[GCC_BIMC_BCR] = { 0x1100 },
[GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
[GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
[GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
[GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
[GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
[GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
[GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
[GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
[GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
[GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
[GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
[GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
[GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
[GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
[GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
[GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
[GCC_DEHR_BCR] = { 0x1300 },
[GCC_RBCPR_BCR] = { 0x1380 },
[GCC_MSS_RESTART] = { 0x1680 },
[GCC_LPASS_RESTART] = { 0x16c0 },
[GCC_WCSS_RESTART] = { 0x1700 },
[GCC_VENUS_RESTART] = { 0x1740 },
};
static struct gdsc *gcc_msm8974_gdscs[] = {
[USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc,
};
static const struct regmap_config gcc_msm8974_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x1fc0,
.fast_io = true,
};
static const struct qcom_cc_desc gcc_msm8974_desc = {
.config = &gcc_msm8974_regmap_config,
.clks = gcc_msm8974_clocks,
.num_clks = ARRAY_SIZE(gcc_msm8974_clocks),
.resets = gcc_msm8974_resets,
.num_resets = ARRAY_SIZE(gcc_msm8974_resets),
.gdscs = gcc_msm8974_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_msm8974_gdscs),
};
static const struct of_device_id gcc_msm8974_match_table[] = {
{ .compatible = "qcom,gcc-msm8226", .data = &gcc_msm8226_desc },
{ .compatible = "qcom,gcc-msm8974", .data = &gcc_msm8974_desc },
{ .compatible = "qcom,gcc-msm8974pro", .data = &gcc_msm8974_desc },
{ .compatible = "qcom,gcc-msm8974pro-ac", .data = &gcc_msm8974_desc },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table);
static void msm8226_clock_override(void)
{
ce1_clk_src.freq_tbl = ftbl_gcc_ce1_clk_msm8226;
gp1_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226;
gp2_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226;
gp3_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226;
}
static void msm8974_pro_clock_override(void)
{
sdcc1_apps_clk_src_init.parent_data = gcc_xo_gpll0_gpll4;
sdcc1_apps_clk_src_init.num_parents = 3;
sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_pro;
sdcc1_apps_clk_src.parent_map = gcc_xo_gpll0_gpll4_map;
gcc_msm8974_clocks[GPLL4] = &gpll4.clkr;
gcc_msm8974_clocks[GPLL4_VOTE] = &gpll4_vote;
gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_SLEEP_CLK] =
&gcc_sdcc1_cdccal_sleep_clk.clkr;
gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_FF_CLK] =
&gcc_sdcc1_cdccal_ff_clk.clkr;
}
static int gcc_msm8974_probe(struct platform_device *pdev)
{
int ret;
struct device *dev = &pdev->dev;
const struct of_device_id *id;
id = of_match_device(gcc_msm8974_match_table, dev);
if (!id)
return -ENODEV;
if (!of_device_is_compatible(dev->of_node, "qcom,gcc-msm8974")) {
if (id->data == &gcc_msm8226_desc)
msm8226_clock_override();
else
msm8974_pro_clock_override();
}
ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
if (ret)
return ret;
ret = qcom_cc_register_sleep_clk(dev);
if (ret)
return ret;
return qcom_cc_probe(pdev, &gcc_msm8974_desc);
}
static struct platform_driver gcc_msm8974_driver = {
.probe = gcc_msm8974_probe,
.driver = {
.name = "gcc-msm8974",
.of_match_table = gcc_msm8974_match_table,
},
};
static int __init gcc_msm8974_init(void)
{
return platform_driver_register(&gcc_msm8974_driver);
}
core_initcall(gcc_msm8974_init);
static void __exit gcc_msm8974_exit(void)
{
platform_driver_unregister(&gcc_msm8974_driver);
}
module_exit(gcc_msm8974_exit);
MODULE_DESCRIPTION("QCOM GCC MSM8974 Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:gcc-msm8974");
| linux-master | drivers/clk/qcom/gcc-msm8974.c |
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