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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
* Author: Elaine Zhang <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rk3568-cru.h>
#include "clk.h"
#define RK3568_GRF_SOC_STATUS0 0x580
enum rk3568_pmu_plls {
ppll, hpll,
};
enum rk3568_plls {
apll, dpll, gpll, cpll, npll, vpll,
};
static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
RK3036_PLL_RATE(297000000, 2, 99, 4, 1, 1, 0),
RK3036_PLL_RATE(241500000, 2, 161, 4, 2, 1, 0),
RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),
RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),
RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),
RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0),
RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),
RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
{ /* sentinel */ },
};
#define RK3568_DIV_ATCLK_CORE_MASK 0x1f
#define RK3568_DIV_ATCLK_CORE_SHIFT 0
#define RK3568_DIV_GICCLK_CORE_MASK 0x1f
#define RK3568_DIV_GICCLK_CORE_SHIFT 8
#define RK3568_DIV_PCLK_CORE_MASK 0x1f
#define RK3568_DIV_PCLK_CORE_SHIFT 0
#define RK3568_DIV_PERIPHCLK_CORE_MASK 0x1f
#define RK3568_DIV_PERIPHCLK_CORE_SHIFT 8
#define RK3568_DIV_ACLK_CORE_MASK 0x1f
#define RK3568_DIV_ACLK_CORE_SHIFT 8
#define RK3568_DIV_SCLK_CORE_MASK 0xf
#define RK3568_DIV_SCLK_CORE_SHIFT 0
#define RK3568_MUX_SCLK_CORE_MASK 0x3
#define RK3568_MUX_SCLK_CORE_SHIFT 8
#define RK3568_MUX_SCLK_CORE_NPLL_MASK 0x1
#define RK3568_MUX_SCLK_CORE_NPLL_SHIFT 15
#define RK3568_MUX_CLK_CORE_APLL_MASK 0x1
#define RK3568_MUX_CLK_CORE_APLL_SHIFT 7
#define RK3568_MUX_CLK_PVTPLL_MASK 0x1
#define RK3568_MUX_CLK_PVTPLL_SHIFT 15
#define RK3568_CLKSEL1(_sclk_core) \
{ \
.reg = RK3568_CLKSEL_CON(2), \
.val = HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_NPLL_MASK, \
RK3568_MUX_SCLK_CORE_NPLL_SHIFT) | \
HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_MASK, \
RK3568_MUX_SCLK_CORE_SHIFT) | \
HIWORD_UPDATE(1, RK3568_DIV_SCLK_CORE_MASK, \
RK3568_DIV_SCLK_CORE_SHIFT), \
}
#define RK3568_CLKSEL2(_aclk_core) \
{ \
.reg = RK3568_CLKSEL_CON(5), \
.val = HIWORD_UPDATE(_aclk_core, RK3568_DIV_ACLK_CORE_MASK, \
RK3568_DIV_ACLK_CORE_SHIFT), \
}
#define RK3568_CLKSEL3(_atclk_core, _gic_core) \
{ \
.reg = RK3568_CLKSEL_CON(3), \
.val = HIWORD_UPDATE(_atclk_core, RK3568_DIV_ATCLK_CORE_MASK, \
RK3568_DIV_ATCLK_CORE_SHIFT) | \
HIWORD_UPDATE(_gic_core, RK3568_DIV_GICCLK_CORE_MASK, \
RK3568_DIV_GICCLK_CORE_SHIFT), \
}
#define RK3568_CLKSEL4(_pclk_core, _periph_core) \
{ \
.reg = RK3568_CLKSEL_CON(4), \
.val = HIWORD_UPDATE(_pclk_core, RK3568_DIV_PCLK_CORE_MASK, \
RK3568_DIV_PCLK_CORE_SHIFT) | \
HIWORD_UPDATE(_periph_core, RK3568_DIV_PERIPHCLK_CORE_MASK, \
RK3568_DIV_PERIPHCLK_CORE_SHIFT), \
}
#define RK3568_CPUCLK_RATE(_prate, _sclk, _acore, _atcore, _gicclk, _pclk, _periph) \
{ \
.prate = _prate##U, \
.divs = { \
RK3568_CLKSEL1(_sclk), \
RK3568_CLKSEL2(_acore), \
RK3568_CLKSEL3(_atcore, _gicclk), \
RK3568_CLKSEL4(_pclk, _periph), \
}, \
}
static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = {
RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7),
RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7),
RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1584000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1560000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1536000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1512000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1488000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1464000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1440000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1416000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1392000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1368000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1344000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1320000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1296000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1272000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1248000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1224000000, 0, 1, 5, 5, 5, 5),
RK3568_CPUCLK_RATE(1200000000, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(1104000000, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(1008000000, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(912000000, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(816000000, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(696000000, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(600000000, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(408000000, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(312000000, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(216000000, 0, 1, 3, 3, 3, 3),
RK3568_CPUCLK_RATE(96000000, 0, 1, 3, 3, 3, 3),
};
static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = {
.core_reg[0] = RK3568_CLKSEL_CON(0),
.div_core_shift[0] = 0,
.div_core_mask[0] = 0x1f,
.core_reg[1] = RK3568_CLKSEL_CON(0),
.div_core_shift[1] = 8,
.div_core_mask[1] = 0x1f,
.core_reg[2] = RK3568_CLKSEL_CON(1),
.div_core_shift[2] = 0,
.div_core_mask[2] = 0x1f,
.core_reg[3] = RK3568_CLKSEL_CON(1),
.div_core_shift[3] = 8,
.div_core_mask[3] = 0x1f,
.num_cores = 4,
.mux_core_alt = 1,
.mux_core_main = 0,
.mux_core_shift = 6,
.mux_core_mask = 0x1,
};
PNAME(mux_pll_p) = { "xin24m" };
PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" };
PNAME(mux_armclk_p) = { "apll", "gpll" };
PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" };
PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" };
PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin_osc0_half" };
PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin_osc0_half" };
PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin_osc0_half "};
PNAME(clk_i2s3_2ch_tx_p) = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac", "i2s3_mclkin", "xin_osc0_half" };
PNAME(clk_i2s3_2ch_rx_p) = { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac", "i2s3_mclkin", "xin_osc0_half" };
PNAME(mclk_spdif_8ch_p) = { "mclk_spdif_8ch_src", "mclk_spdif_8ch_frac" };
PNAME(sclk_audpwm_p) = { "sclk_audpwm_src", "sclk_audpwm_frac" };
PNAME(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
PNAME(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
PNAME(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
PNAME(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
PNAME(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
PNAME(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
PNAME(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
PNAME(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
PNAME(sclk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" };
PNAME(sclk_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
PNAME(clk_rtc32k_pmu_p) = { "clk_32k_pvtm", "xin32k", "clk_rtc32k_frac" };
PNAME(mpll_gpll_cpll_npll_p) = { "mpll", "gpll", "cpll", "npll" };
PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll" };
PNAME(npll_gpll_p) = { "npll", "gpll" };
PNAME(cpll_gpll_p) = { "cpll", "gpll" };
PNAME(gpll_cpll_p) = { "gpll", "cpll" };
PNAME(gpll_cpll_npll_vpll_p) = { "gpll", "cpll", "npll", "vpll" };
PNAME(apll_gpll_npll_p) = { "apll", "gpll", "npll" };
PNAME(sclk_core_pre_p) = { "sclk_core_src", "npll" };
PNAME(gpll150_gpll100_gpll75_xin24m_p) = { "gpll_150m", "gpll_100m", "gpll_75m", "xin24m" };
PNAME(clk_gpu_pre_mux_p) = { "clk_gpu_src", "gpu_pvtpll_out" };
PNAME(clk_npu_pre_ndft_p) = { "clk_npu_src", "dummy"};
PNAME(clk_npu_p) = { "clk_npu_pre_ndft", "npu_pvtpll_out" };
PNAME(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" };
PNAME(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" };
PNAME(gpll200_gpll150_gpll100_xin24m_p) = { "gpll_200m", "gpll_150m", "gpll_100m", "xin24m" };
PNAME(gpll100_gpll75_gpll50_p) = { "gpll_100m", "gpll_75m", "cpll_50m" };
PNAME(i2s0_mclkout_tx_p) = { "clk_i2s0_8ch_tx", "xin_osc0_half" };
PNAME(i2s0_mclkout_rx_p) = { "clk_i2s0_8ch_rx", "xin_osc0_half" };
PNAME(i2s1_mclkout_tx_p) = { "clk_i2s1_8ch_tx", "xin_osc0_half" };
PNAME(i2s1_mclkout_rx_p) = { "clk_i2s1_8ch_rx", "xin_osc0_half" };
PNAME(i2s2_mclkout_p) = { "clk_i2s2_2ch", "xin_osc0_half" };
PNAME(i2s3_mclkout_tx_p) = { "clk_i2s3_2ch_tx", "xin_osc0_half" };
PNAME(i2s3_mclkout_rx_p) = { "clk_i2s3_2ch_rx", "xin_osc0_half" };
PNAME(mclk_pdm_p) = { "gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m" };
PNAME(clk_i2c_p) = { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" };
PNAME(gpll200_gpll150_gpll100_p) = { "gpll_200m", "gpll_150m", "gpll_100m" };
PNAME(gpll300_gpll200_gpll100_p) = { "gpll_300m", "gpll_200m", "gpll_100m" };
PNAME(clk_nandc_p) = { "gpll_200m", "gpll_150m", "cpll_100m", "xin24m" };
PNAME(sclk_sfc_p) = { "xin24m", "cpll_50m", "gpll_75m", "gpll_100m", "cpll_125m", "gpll_150m" };
PNAME(gpll200_gpll150_cpll125_p) = { "gpll_200m", "gpll_150m", "cpll_125m" };
PNAME(cclk_emmc_p) = { "xin24m", "gpll_200m", "gpll_150m", "cpll_100m", "cpll_50m", "clk_osc0_div_375k" };
PNAME(aclk_pipe_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" };
PNAME(gpll200_cpll125_p) = { "gpll_200m", "cpll_125m" };
PNAME(gpll300_gpll200_gpll100_xin24m_p) = { "gpll_300m", "gpll_200m", "gpll_100m", "xin24m" };
PNAME(clk_sdmmc_p) = { "xin24m", "gpll_400m", "gpll_300m", "cpll_100m", "cpll_50m", "clk_osc0_div_750k" };
PNAME(cpll125_cpll50_cpll25_xin24m_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "xin24m" };
PNAME(clk_gmac_ptp_p) = { "cpll_62p5", "gpll_100m", "cpll_50m", "xin24m" };
PNAME(cpll333_gpll300_gpll200_p) = { "cpll_333m", "gpll_300m", "gpll_200m" };
PNAME(cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" };
PNAME(gpll_usb480m_xin24m_p) = { "gpll", "usb480m", "xin24m", "xin24m" };
PNAME(gpll300_cpll250_gpll100_xin24m_p) = { "gpll_300m", "cpll_250m", "gpll_100m", "xin24m" };
PNAME(cpll_gpll_hpll_vpll_p) = { "cpll", "gpll", "hpll", "vpll" };
PNAME(hpll_vpll_gpll_cpll_p) = { "hpll", "vpll", "gpll", "cpll" };
PNAME(gpll400_cpll333_gpll200_p) = { "gpll_400m", "cpll_333m", "gpll_200m" };
PNAME(gpll100_gpll75_cpll50_xin24m_p) = { "gpll_100m", "gpll_75m", "cpll_50m", "xin24m" };
PNAME(xin24m_gpll100_cpll100_p) = { "xin24m", "gpll_100m", "cpll_100m" };
PNAME(gpll_cpll_usb480m_p) = { "gpll", "cpll", "usb480m" };
PNAME(gpll100_xin24m_cpll100_p) = { "gpll_100m", "xin24m", "cpll_100m" };
PNAME(gpll200_xin24m_cpll100_p) = { "gpll_200m", "xin24m", "cpll_100m" };
PNAME(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" };
PNAME(cpll500_gpll400_gpll300_xin24m_p) = { "cpll_500m", "gpll_400m", "gpll_300m", "xin24m" };
PNAME(gpll400_gpll300_gpll200_xin24m_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" };
PNAME(xin24m_cpll100_p) = { "xin24m", "cpll_100m" };
PNAME(ppll_usb480m_cpll_gpll_p) = { "ppll", "usb480m", "cpll", "gpll"};
PNAME(clk_usbphy0_ref_p) = { "clk_ref24m", "xin_osc0_usbphy0_g" };
PNAME(clk_usbphy1_ref_p) = { "clk_ref24m", "xin_osc0_usbphy1_g" };
PNAME(clk_mipidsiphy0_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy0_g" };
PNAME(clk_mipidsiphy1_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy1_g" };
PNAME(clk_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" };
PNAME(clk_pciephy0_ref_p) = { "clk_pciephy0_osc0", "clk_pciephy0_div" };
PNAME(clk_pciephy1_ref_p) = { "clk_pciephy1_osc0", "clk_pciephy1_div" };
PNAME(clk_pciephy2_ref_p) = { "clk_pciephy2_osc0", "clk_pciephy2_div" };
PNAME(mux_gmac0_p) = { "clk_mac0_2top", "gmac0_clkin" };
PNAME(mux_gmac0_rgmii_speed_p) = { "clk_gmac0", "clk_gmac0", "clk_gmac0_tx_div50", "clk_gmac0_tx_div5" };
PNAME(mux_gmac0_rmii_speed_p) = { "clk_gmac0_rx_div20", "clk_gmac0_rx_div2" };
PNAME(mux_gmac0_rx_tx_p) = { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed", "clk_gmac0_xpcs_mii" };
PNAME(mux_gmac1_p) = { "clk_mac1_2top", "gmac1_clkin" };
PNAME(mux_gmac1_rgmii_speed_p) = { "clk_gmac1", "clk_gmac1", "clk_gmac1_tx_div50", "clk_gmac1_tx_div5" };
PNAME(mux_gmac1_rmii_speed_p) = { "clk_gmac1_rx_div20", "clk_gmac1_rx_div2" };
PNAME(mux_gmac1_rx_tx_p) = { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed", "clk_gmac1_xpcs_mii" };
PNAME(clk_hdmi_ref_p) = { "hpll", "hpll_ph0" };
PNAME(clk_pdpmu_p) = { "ppll", "gpll" };
PNAME(clk_mac_2top_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" };
PNAME(clk_pwm0_p) = { "xin24m", "clk_pdpmu" };
PNAME(aclk_rkvdec_pre_p) = { "gpll", "cpll" };
PNAME(clk_rkvdec_core_p) = { "gpll", "cpll", "dummy_npll", "dummy_vpll" };
static struct rockchip_pll_clock rk3568_pmu_pll_clks[] __initdata = {
[ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p,
0, RK3568_PMU_PLL_CON(0),
RK3568_PMU_MODE_CON0, 0, 4, 0, rk3568_pll_rates),
[hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p,
0, RK3568_PMU_PLL_CON(16),
RK3568_PMU_MODE_CON0, 2, 7, 0, rk3568_pll_rates),
};
static struct rockchip_pll_clock rk3568_pll_clks[] __initdata = {
[apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
0, RK3568_PLL_CON(0),
RK3568_MODE_CON0, 0, 0, 0, rk3568_pll_rates),
[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
0, RK3568_PLL_CON(8),
RK3568_MODE_CON0, 2, 1, 0, NULL),
[cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
0, RK3568_PLL_CON(24),
RK3568_MODE_CON0, 4, 2, 0, rk3568_pll_rates),
[gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
0, RK3568_PLL_CON(16),
RK3568_MODE_CON0, 6, 3, 0, rk3568_pll_rates),
[npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
0, RK3568_PLL_CON(32),
RK3568_MODE_CON0, 10, 5, 0, rk3568_pll_rates),
[vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p,
0, RK3568_PLL_CON(40),
RK3568_MODE_CON0, 12, 6, 0, rk3568_pll_rates),
};
#define MFLAGS CLK_MUX_HIWORD_MASK
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
static struct rockchip_clk_branch rk3568_i2s0_8ch_tx_fracmux __initdata =
MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(11), 10, 2, MFLAGS);
static struct rockchip_clk_branch rk3568_i2s0_8ch_rx_fracmux __initdata =
MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(13), 10, 2, MFLAGS);
static struct rockchip_clk_branch rk3568_i2s1_8ch_tx_fracmux __initdata =
MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(15), 10, 2, MFLAGS);
static struct rockchip_clk_branch rk3568_i2s1_8ch_rx_fracmux __initdata =
MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(17), 10, 2, MFLAGS);
static struct rockchip_clk_branch rk3568_i2s2_2ch_fracmux __initdata =
MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(19), 10, 2, MFLAGS);
static struct rockchip_clk_branch rk3568_i2s3_2ch_tx_fracmux __initdata =
MUX(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(21), 10, 2, MFLAGS);
static struct rockchip_clk_branch rk3568_i2s3_2ch_rx_fracmux __initdata =
MUX(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(83), 10, 2, MFLAGS);
static struct rockchip_clk_branch rk3568_spdif_8ch_fracmux __initdata =
MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(23), 15, 1, MFLAGS);
static struct rockchip_clk_branch rk3568_audpwm_fracmux __initdata =
MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(25), 15, 1, MFLAGS);
static struct rockchip_clk_branch rk3568_uart1_fracmux __initdata =
MUX(0, "sclk_uart1_mux", sclk_uart1_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(52), 12, 2, MFLAGS);
static struct rockchip_clk_branch rk3568_uart2_fracmux __initdata =
MUX(0, "sclk_uart2_mux", sclk_uart2_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(54), 12, 2, MFLAGS);
static struct rockchip_clk_branch rk3568_uart3_fracmux __initdata =
MUX(0, "sclk_uart3_mux", sclk_uart3_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(56), 12, 2, MFLAGS);
static struct rockchip_clk_branch rk3568_uart4_fracmux __initdata =
MUX(0, "sclk_uart4_mux", sclk_uart4_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(58), 12, 2, MFLAGS);
static struct rockchip_clk_branch rk3568_uart5_fracmux __initdata =
MUX(0, "sclk_uart5_mux", sclk_uart5_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(60), 12, 2, MFLAGS);
static struct rockchip_clk_branch rk3568_uart6_fracmux __initdata =
MUX(0, "sclk_uart6_mux", sclk_uart6_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(62), 12, 2, MFLAGS);
static struct rockchip_clk_branch rk3568_uart7_fracmux __initdata =
MUX(0, "sclk_uart7_mux", sclk_uart7_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(64), 12, 2, MFLAGS);
static struct rockchip_clk_branch rk3568_uart8_fracmux __initdata =
MUX(0, "sclk_uart8_mux", sclk_uart8_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(66), 12, 2, MFLAGS);
static struct rockchip_clk_branch rk3568_uart9_fracmux __initdata =
MUX(0, "sclk_uart9_mux", sclk_uart9_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(68), 12, 2, MFLAGS);
static struct rockchip_clk_branch rk3568_uart0_fracmux __initdata =
MUX(0, "sclk_uart0_mux", sclk_uart0_p, CLK_SET_RATE_PARENT,
RK3568_PMU_CLKSEL_CON(4), 10, 2, MFLAGS);
static struct rockchip_clk_branch rk3568_rtc32k_pmu_fracmux __initdata =
MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3568_PMU_CLKSEL_CON(0), 6, 2, MFLAGS);
static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
/*
* Clock-Architecture Diagram 1
*/
/* SRC_CLK */
COMPOSITE_NOMUX(0, "gpll_400m", "gpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(75), 0, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 0, GFLAGS),
COMPOSITE_NOMUX(0, "gpll_300m", "gpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(75), 8, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 1, GFLAGS),
COMPOSITE_NOMUX(0, "gpll_200m", "gpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(76), 0, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 2, GFLAGS),
COMPOSITE_NOMUX(0, "gpll_150m", "gpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(76), 8, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 3, GFLAGS),
COMPOSITE_NOMUX(0, "gpll_100m", "gpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(77), 0, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 4, GFLAGS),
COMPOSITE_NOMUX(0, "gpll_75m", "gpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(77), 8, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 5, GFLAGS),
COMPOSITE_NOMUX(0, "gpll_20m", "gpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(78), 0, 6, DFLAGS,
RK3568_CLKGATE_CON(35), 6, GFLAGS),
COMPOSITE_NOMUX(CPLL_500M, "cpll_500m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(78), 8, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 7, GFLAGS),
COMPOSITE_NOMUX(CPLL_333M, "cpll_333m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(79), 0, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 8, GFLAGS),
COMPOSITE_NOMUX(CPLL_250M, "cpll_250m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(79), 8, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 9, GFLAGS),
COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(80), 0, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 10, GFLAGS),
COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(82), 0, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 11, GFLAGS),
COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(80), 8, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 12, GFLAGS),
COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(81), 0, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 13, GFLAGS),
COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(81), 8, 6, DFLAGS,
RK3568_CLKGATE_CON(35), 14, GFLAGS),
COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(82), 8, 6, DFLAGS,
RK3568_CLKGATE_CON(35), 15, GFLAGS),
FACTOR(0, "clk_osc0_div_375k", "clk_osc0_div_750k", 0, 1, 2),
FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2),
MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
RK3568_MODE_CON0, 14, 2, MFLAGS),
/* PD_CORE */
COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3568_CLKGATE_CON(0), 5, GFLAGS),
COMPOSITE_NODIV(0, "sclk_core", sclk_core_pre_p, CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(2), 15, 1, MFLAGS,
RK3568_CLKGATE_CON(0), 7, GFLAGS),
COMPOSITE_NOMUX(0, "atclk_core", "armclk", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3568_CLKGATE_CON(0), 8, GFLAGS),
COMPOSITE_NOMUX(0, "gicclk_core", "armclk", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3568_CLKGATE_CON(0), 9, GFLAGS),
COMPOSITE_NOMUX(0, "pclk_core_pre", "armclk", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(4), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3568_CLKGATE_CON(0), 10, GFLAGS),
COMPOSITE_NOMUX(0, "periphclk_core_pre", "armclk", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(4), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3568_CLKGATE_CON(0), 11, GFLAGS),
COMPOSITE_NOMUX(0, "tsclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(5), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3568_CLKGATE_CON(0), 14, GFLAGS),
COMPOSITE_NOMUX(0, "cntclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(5), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3568_CLKGATE_CON(0), 15, GFLAGS),
COMPOSITE_NOMUX(0, "aclk_core", "sclk_core", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(5), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3568_CLKGATE_CON(1), 0, GFLAGS),
COMPOSITE_NODIV(ACLK_CORE_NIU2BUS, "aclk_core_niu2bus", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(5), 14, 2, MFLAGS,
RK3568_CLKGATE_CON(1), 2, GFLAGS),
GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 0,
RK3568_CLKGATE_CON(1), 10, GFLAGS),
GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 0,
RK3568_CLKGATE_CON(1), 11, GFLAGS),
GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", CLK_IGNORE_UNUSED,
RK3568_CLKGATE_CON(1), 12, GFLAGS),
GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 0,
RK3568_CLKGATE_CON(1), 9, GFLAGS),
/* PD_GPU */
COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", mpll_gpll_cpll_npll_p, 0,
RK3568_CLKSEL_CON(6), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3568_CLKGATE_CON(2), 0, GFLAGS),
MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux", clk_gpu_pre_mux_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(6), 11, 1, MFLAGS | CLK_MUX_READ_ONLY),
DIV(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre_mux", 0,
RK3568_CLKSEL_CON(6), 8, 2, DFLAGS),
DIV(PCLK_GPU_PRE, "pclk_gpu_pre", "clk_gpu_pre_mux", 0,
RK3568_CLKSEL_CON(6), 12, 4, DFLAGS),
GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_mux", 0,
RK3568_CLKGATE_CON(2), 3, GFLAGS),
GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 0,
RK3568_CLKGATE_CON(2), 6, GFLAGS),
GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0,
RK3568_CLKGATE_CON(2), 7, GFLAGS),
GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 0,
RK3568_CLKGATE_CON(2), 8, GFLAGS),
GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", CLK_IGNORE_UNUSED,
RK3568_CLKGATE_CON(2), 9, GFLAGS),
/* PD_NPU */
COMPOSITE(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 0,
RK3568_CLKSEL_CON(7), 6, 1, MFLAGS, 0, 4, DFLAGS,
RK3568_CLKGATE_CON(3), 0, GFLAGS),
MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
RK3568_CLKSEL_CON(7), 8, 1, MFLAGS),
MUX(CLK_NPU, "clk_npu", clk_npu_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(7), 15, 1, MFLAGS),
COMPOSITE_NOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu", 0,
RK3568_CLKSEL_CON(8), 0, 4, DFLAGS,
RK3568_CLKGATE_CON(3), 2, GFLAGS),
COMPOSITE_NOMUX(PCLK_NPU_PRE, "pclk_npu_pre", "clk_npu", 0,
RK3568_CLKSEL_CON(8), 4, 4, DFLAGS,
RK3568_CLKGATE_CON(3), 3, GFLAGS),
GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 0,
RK3568_CLKGATE_CON(3), 4, GFLAGS),
GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 0,
RK3568_CLKGATE_CON(3), 7, GFLAGS),
GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 0,
RK3568_CLKGATE_CON(3), 8, GFLAGS),
GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 0,
RK3568_CLKGATE_CON(3), 9, GFLAGS),
GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0,
RK3568_CLKGATE_CON(3), 10, GFLAGS),
GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft", 0,
RK3568_CLKGATE_CON(3), 11, GFLAGS),
GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", CLK_IGNORE_UNUSED,
RK3568_CLKGATE_CON(3), 12, GFLAGS),
/* PD_DDR */
COMPOSITE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", dpll_gpll_cpll_p, CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3568_CLKGATE_CON(4), 0, GFLAGS),
MUXGRF(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(9), 15, 1, MFLAGS),
COMPOSITE_NOMUX(CLK_MSCH, "clk_msch", "clk_ddr1x", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(10), 0, 2, DFLAGS,
RK3568_CLKGATE_CON(4), 2, GFLAGS),
GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
RK3568_CLKGATE_CON(4), 15, GFLAGS),
/* PD_GIC_AUDIO */
COMPOSITE_NODIV(ACLK_GIC_AUDIO, "aclk_gic_audio", gpll200_gpll150_gpll100_xin24m_p, CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(10), 8, 2, MFLAGS,
RK3568_CLKGATE_CON(5), 0, GFLAGS),
COMPOSITE_NODIV(HCLK_GIC_AUDIO, "hclk_gic_audio", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(10), 10, 2, MFLAGS,
RK3568_CLKGATE_CON(5), 1, GFLAGS),
GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 0,
RK3568_CLKGATE_CON(5), 8, GFLAGS),
COMPOSITE_NODIV(DCLK_SDMMC_BUFFER, "dclk_sdmmc_buffer", gpll100_gpll75_gpll50_p, 0,
RK3568_CLKSEL_CON(10), 12, 2, MFLAGS,
RK3568_CLKGATE_CON(5), 9, GFLAGS),
GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", CLK_IGNORE_UNUSED,
RK3568_CLKGATE_CON(5), 4, GFLAGS),
GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", CLK_IGNORE_UNUSED,
RK3568_CLKGATE_CON(5), 7, GFLAGS),
GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 0,
RK3568_CLKGATE_CON(5), 10, GFLAGS),
GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 0,
RK3568_CLKGATE_CON(5), 11, GFLAGS),
GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 0,
RK3568_CLKGATE_CON(5), 12, GFLAGS),
GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 0,
RK3568_CLKGATE_CON(5), 13, GFLAGS),
COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_cpll_npll_p, 0,
RK3568_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3568_CLKGATE_CON(6), 0, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(12), 0,
RK3568_CLKGATE_CON(6), 1, GFLAGS,
&rk3568_i2s0_8ch_tx_fracmux),
GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0,
RK3568_CLKGATE_CON(6), 2, GFLAGS),
COMPOSITE_NODIV(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", i2s0_mclkout_tx_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(11), 15, 1, MFLAGS,
RK3568_CLKGATE_CON(6), 3, GFLAGS),
COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_cpll_npll_p, 0,
RK3568_CLKSEL_CON(13), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3568_CLKGATE_CON(6), 4, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(14), 0,
RK3568_CLKGATE_CON(6), 5, GFLAGS,
&rk3568_i2s0_8ch_rx_fracmux),
GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0,
RK3568_CLKGATE_CON(6), 6, GFLAGS),
COMPOSITE_NODIV(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", i2s0_mclkout_rx_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(13), 15, 1, MFLAGS,
RK3568_CLKGATE_CON(6), 7, GFLAGS),
COMPOSITE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", gpll_cpll_npll_p, 0,
RK3568_CLKSEL_CON(15), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3568_CLKGATE_CON(6), 8, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(16), 0,
RK3568_CLKGATE_CON(6), 9, GFLAGS,
&rk3568_i2s1_8ch_tx_fracmux),
GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0,
RK3568_CLKGATE_CON(6), 10, GFLAGS),
COMPOSITE_NODIV(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", i2s1_mclkout_tx_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(15), 15, 1, MFLAGS,
RK3568_CLKGATE_CON(6), 11, GFLAGS),
COMPOSITE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", gpll_cpll_npll_p, 0,
RK3568_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3568_CLKGATE_CON(6), 12, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(18), 0,
RK3568_CLKGATE_CON(6), 13, GFLAGS,
&rk3568_i2s1_8ch_rx_fracmux),
GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0,
RK3568_CLKGATE_CON(6), 14, GFLAGS),
COMPOSITE_NODIV(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", i2s1_mclkout_rx_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(17), 15, 1, MFLAGS,
RK3568_CLKGATE_CON(6), 15, GFLAGS),
COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_cpll_npll_p, 0,
RK3568_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3568_CLKGATE_CON(7), 0, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(20), 0,
RK3568_CLKGATE_CON(7), 1, GFLAGS,
&rk3568_i2s2_2ch_fracmux),
GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0,
RK3568_CLKGATE_CON(7), 2, GFLAGS),
COMPOSITE_NODIV(I2S2_MCLKOUT, "i2s2_mclkout", i2s2_mclkout_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(19), 15, 1, MFLAGS,
RK3568_CLKGATE_CON(7), 3, GFLAGS),
COMPOSITE(CLK_I2S3_2CH_TX_SRC, "clk_i2s3_2ch_tx_src", gpll_cpll_npll_p, 0,
RK3568_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3568_CLKGATE_CON(7), 4, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", "clk_i2s3_2ch_tx_src", CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(22), 0,
RK3568_CLKGATE_CON(7), 5, GFLAGS,
&rk3568_i2s3_2ch_tx_fracmux),
GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 0,
RK3568_CLKGATE_CON(7), 6, GFLAGS),
COMPOSITE_NODIV(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", i2s3_mclkout_tx_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(21), 15, 1, MFLAGS,
RK3568_CLKGATE_CON(7), 7, GFLAGS),
COMPOSITE(CLK_I2S3_2CH_RX_SRC, "clk_i2s3_2ch_rx_src", gpll_cpll_npll_p, 0,
RK3568_CLKSEL_CON(83), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3568_CLKGATE_CON(7), 8, GFLAGS),
COMPOSITE_FRACMUX(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", "clk_i2s3_2ch_rx_src", CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(84), 0,
RK3568_CLKGATE_CON(7), 9, GFLAGS,
&rk3568_i2s3_2ch_rx_fracmux),
GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 0,
RK3568_CLKGATE_CON(7), 10, GFLAGS),
COMPOSITE_NODIV(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", i2s3_mclkout_rx_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(83), 15, 1, MFLAGS,
RK3568_CLKGATE_CON(7), 11, GFLAGS),
GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 0,
RK3568_CLKGATE_CON(5), 14, GFLAGS),
COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 0,
RK3568_CLKSEL_CON(23), 8, 2, MFLAGS,
RK3568_CLKGATE_CON(5), 15, GFLAGS),
GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 0,
RK3568_CLKGATE_CON(7), 12, GFLAGS),
GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 0,
RK3568_CLKGATE_CON(7), 13, GFLAGS),
COMPOSITE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", cpll_gpll_p, 0,
RK3568_CLKSEL_CON(23), 14, 1, MFLAGS, 0, 7, DFLAGS,
RK3568_CLKGATE_CON(7), 14, GFLAGS),
COMPOSITE_FRACMUX(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", "mclk_spdif_8ch_src", CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(24), 0,
RK3568_CLKGATE_CON(7), 15, GFLAGS,
&rk3568_spdif_8ch_fracmux),
GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 0,
RK3568_CLKGATE_CON(8), 0, GFLAGS),
COMPOSITE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", gpll_cpll_p, 0,
RK3568_CLKSEL_CON(25), 14, 1, MFLAGS, 0, 6, DFLAGS,
RK3568_CLKGATE_CON(8), 1, GFLAGS),
COMPOSITE_FRACMUX(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_src", CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(26), 0,
RK3568_CLKGATE_CON(8), 2, GFLAGS,
&rk3568_audpwm_fracmux),
GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 0,
RK3568_CLKGATE_CON(8), 3, GFLAGS),
COMPOSITE_NODIV(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", clk_i2c_p, 0,
RK3568_CLKSEL_CON(23), 10, 2, MFLAGS,
RK3568_CLKGATE_CON(8), 4, GFLAGS),
GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 0,
RK3568_CLKGATE_CON(8), 5, GFLAGS),
GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 0,
RK3568_CLKGATE_CON(8), 6, GFLAGS),
/* PD_SECURE_FLASH */
COMPOSITE_NODIV(ACLK_SECURE_FLASH, "aclk_secure_flash", gpll200_gpll150_gpll100_xin24m_p, 0,
RK3568_CLKSEL_CON(27), 0, 2, MFLAGS,
RK3568_CLKGATE_CON(8), 7, GFLAGS),
COMPOSITE_NODIV(HCLK_SECURE_FLASH, "hclk_secure_flash", gpll150_gpll100_gpll75_xin24m_p, 0,
RK3568_CLKSEL_CON(27), 2, 2, MFLAGS,
RK3568_CLKGATE_CON(8), 8, GFLAGS),
GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 0,
RK3568_CLKGATE_CON(8), 11, GFLAGS),
GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 0,
RK3568_CLKGATE_CON(8), 12, GFLAGS),
COMPOSITE_NODIV(CLK_CRYPTO_NS_CORE, "clk_crypto_ns_core", gpll200_gpll150_gpll100_p, 0,
RK3568_CLKSEL_CON(27), 4, 2, MFLAGS,
RK3568_CLKGATE_CON(8), 13, GFLAGS),
COMPOSITE_NODIV(CLK_CRYPTO_NS_PKA, "clk_crypto_ns_pka", gpll300_gpll200_gpll100_p, 0,
RK3568_CLKSEL_CON(27), 6, 2, MFLAGS,
RK3568_CLKGATE_CON(8), 14, GFLAGS),
GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", 0,
RK3568_CLKGATE_CON(8), 15, GFLAGS),
GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED,
RK3568_CLKGATE_CON(9), 10, GFLAGS),
GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED,
RK3568_CLKGATE_CON(9), 11, GFLAGS),
GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 0,
RK3568_CLKGATE_CON(26), 9, GFLAGS),
GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 0,
RK3568_CLKGATE_CON(26), 10, GFLAGS),
GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 0,
RK3568_CLKGATE_CON(26), 11, GFLAGS),
GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 0,
RK3568_CLKGATE_CON(9), 0, GFLAGS),
COMPOSITE_NODIV(NCLK_NANDC, "nclk_nandc", clk_nandc_p, 0,
RK3568_CLKSEL_CON(28), 0, 2, MFLAGS,
RK3568_CLKGATE_CON(9), 1, GFLAGS),
GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 0,
RK3568_CLKGATE_CON(9), 2, GFLAGS),
GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 0,
RK3568_CLKGATE_CON(9), 3, GFLAGS),
COMPOSITE_NODIV(SCLK_SFC, "sclk_sfc", sclk_sfc_p, 0,
RK3568_CLKSEL_CON(28), 4, 3, MFLAGS,
RK3568_CLKGATE_CON(9), 4, GFLAGS),
GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 0,
RK3568_CLKGATE_CON(9), 5, GFLAGS),
GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 0,
RK3568_CLKGATE_CON(9), 6, GFLAGS),
COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", gpll200_gpll150_cpll125_p, 0,
RK3568_CLKSEL_CON(28), 8, 2, MFLAGS,
RK3568_CLKGATE_CON(9), 7, GFLAGS),
COMPOSITE_NODIV(CCLK_EMMC, "cclk_emmc", cclk_emmc_p, 0,
RK3568_CLKSEL_CON(28), 12, 3, MFLAGS,
RK3568_CLKGATE_CON(9), 8, GFLAGS),
GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0,
RK3568_CLKGATE_CON(9), 9, GFLAGS),
MMC(SCLK_EMMC_DRV, "emmc_drv", "cclk_emmc", RK3568_EMMC_CON0, 1),
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "cclk_emmc", RK3568_EMMC_CON1, 1),
/* PD_PIPE */
COMPOSITE_NODIV(ACLK_PIPE, "aclk_pipe", aclk_pipe_p, 0,
RK3568_CLKSEL_CON(29), 0, 2, MFLAGS,
RK3568_CLKGATE_CON(10), 0, GFLAGS),
COMPOSITE_NOMUX(PCLK_PIPE, "pclk_pipe", "aclk_pipe", 0,
RK3568_CLKSEL_CON(29), 4, 4, DFLAGS,
RK3568_CLKGATE_CON(10), 1, GFLAGS),
GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 0,
RK3568_CLKGATE_CON(12), 0, GFLAGS),
GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 0,
RK3568_CLKGATE_CON(12), 1, GFLAGS),
GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 0,
RK3568_CLKGATE_CON(12), 2, GFLAGS),
GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 0,
RK3568_CLKGATE_CON(12), 3, GFLAGS),
GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0,
RK3568_CLKGATE_CON(12), 4, GFLAGS),
GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0,
RK3568_CLKGATE_CON(12), 8, GFLAGS),
GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0,
RK3568_CLKGATE_CON(12), 9, GFLAGS),
GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 0,
RK3568_CLKGATE_CON(12), 10, GFLAGS),
GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 0,
RK3568_CLKGATE_CON(12), 11, GFLAGS),
GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0,
RK3568_CLKGATE_CON(12), 12, GFLAGS),
GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0,
RK3568_CLKGATE_CON(13), 0, GFLAGS),
GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0,
RK3568_CLKGATE_CON(13), 1, GFLAGS),
GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 0,
RK3568_CLKGATE_CON(13), 2, GFLAGS),
GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 0,
RK3568_CLKGATE_CON(13), 3, GFLAGS),
GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0,
RK3568_CLKGATE_CON(13), 4, GFLAGS),
GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0,
RK3568_CLKGATE_CON(11), 0, GFLAGS),
GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0,
RK3568_CLKGATE_CON(11), 1, GFLAGS),
GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "cpll_50m", 0,
RK3568_CLKGATE_CON(11), 2, GFLAGS),
GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 0,
RK3568_CLKGATE_CON(11), 4, GFLAGS),
GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "gpll_20m", 0,
RK3568_CLKGATE_CON(11), 5, GFLAGS),
GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "cpll_50m", 0,
RK3568_CLKGATE_CON(11), 6, GFLAGS),
GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 0,
RK3568_CLKGATE_CON(11), 8, GFLAGS),
GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "gpll_20m", 0,
RK3568_CLKGATE_CON(11), 9, GFLAGS),
GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "cpll_50m", 0,
RK3568_CLKGATE_CON(11), 10, GFLAGS),
GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 0,
RK3568_CLKGATE_CON(10), 8, GFLAGS),
GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
RK3568_CLKGATE_CON(10), 9, GFLAGS),
COMPOSITE_NODIV(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", xin24m_32k_p, 0,
RK3568_CLKSEL_CON(29), 8, 1, MFLAGS,
RK3568_CLKGATE_CON(10), 10, GFLAGS),
GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 0,
RK3568_CLKGATE_CON(10), 12, GFLAGS),
GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0,
RK3568_CLKGATE_CON(10), 13, GFLAGS),
COMPOSITE_NODIV(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", xin24m_32k_p, 0,
RK3568_CLKSEL_CON(29), 9, 1, MFLAGS,
RK3568_CLKGATE_CON(10), 14, GFLAGS),
COMPOSITE_NODIV(CLK_XPCS_EEE, "clk_xpcs_eee", gpll200_cpll125_p, 0,
RK3568_CLKSEL_CON(29), 13, 1, MFLAGS,
RK3568_CLKGATE_CON(10), 4, GFLAGS),
GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 0,
RK3568_CLKGATE_CON(13), 6, GFLAGS),
/* PD_PHP */
COMPOSITE_NODIV(ACLK_PHP, "aclk_php", gpll300_gpll200_gpll100_xin24m_p, 0,
RK3568_CLKSEL_CON(30), 0, 2, MFLAGS,
RK3568_CLKGATE_CON(14), 8, GFLAGS),
COMPOSITE_NODIV(HCLK_PHP, "hclk_php", gpll150_gpll100_gpll75_xin24m_p, 0,
RK3568_CLKSEL_CON(30), 2, 2, MFLAGS,
RK3568_CLKGATE_CON(14), 9, GFLAGS),
COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", 0,
RK3568_CLKSEL_CON(30), 4, 4, DFLAGS,
RK3568_CLKGATE_CON(14), 10, GFLAGS),
GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 0,
RK3568_CLKGATE_CON(15), 0, GFLAGS),
COMPOSITE_NODIV(CLK_SDMMC0, "clk_sdmmc0", clk_sdmmc_p, 0,
RK3568_CLKSEL_CON(30), 8, 3, MFLAGS,
RK3568_CLKGATE_CON(15), 1, GFLAGS),
MMC(SCLK_SDMMC0_DRV, "sdmmc0_drv", "clk_sdmmc0", RK3568_SDMMC0_CON0, 1),
MMC(SCLK_SDMMC0_SAMPLE, "sdmmc0_sample", "clk_sdmmc0", RK3568_SDMMC0_CON1, 1),
GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 0,
RK3568_CLKGATE_CON(15), 2, GFLAGS),
COMPOSITE_NODIV(CLK_SDMMC1, "clk_sdmmc1", clk_sdmmc_p, 0,
RK3568_CLKSEL_CON(30), 12, 3, MFLAGS,
RK3568_CLKGATE_CON(15), 3, GFLAGS),
MMC(SCLK_SDMMC1_DRV, "sdmmc1_drv", "clk_sdmmc1", RK3568_SDMMC1_CON0, 1),
MMC(SCLK_SDMMC1_SAMPLE, "sdmmc1_sample", "clk_sdmmc1", RK3568_SDMMC1_CON1, 1),
GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php", 0,
RK3568_CLKGATE_CON(15), 5, GFLAGS),
GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php", 0,
RK3568_CLKGATE_CON(15), 6, GFLAGS),
COMPOSITE_NODIV(CLK_MAC0_2TOP, "clk_mac0_2top", clk_mac_2top_p, 0,
RK3568_CLKSEL_CON(31), 8, 2, MFLAGS,
RK3568_CLKGATE_CON(15), 7, GFLAGS),
COMPOSITE_NODIV(CLK_MAC0_OUT, "clk_mac0_out", cpll125_cpll50_cpll25_xin24m_p, 0,
RK3568_CLKSEL_CON(31), 14, 2, MFLAGS,
RK3568_CLKGATE_CON(15), 8, GFLAGS),
GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 0,
RK3568_CLKGATE_CON(15), 12, GFLAGS),
COMPOSITE_NODIV(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac_ptp_p, 0,
RK3568_CLKSEL_CON(31), 12, 2, MFLAGS,
RK3568_CLKGATE_CON(15), 4, GFLAGS),
MUX(SCLK_GMAC0, "clk_gmac0", mux_gmac0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3568_CLKSEL_CON(31), 2, 1, MFLAGS),
FACTOR(0, "clk_gmac0_tx_div5", "clk_gmac0", 0, 1, 5),
FACTOR(0, "clk_gmac0_tx_div50", "clk_gmac0", 0, 1, 50),
FACTOR(0, "clk_gmac0_rx_div2", "clk_gmac0", 0, 1, 2),
FACTOR(0, "clk_gmac0_rx_div20", "clk_gmac0", 0, 1, 20),
MUX(SCLK_GMAC0_RGMII_SPEED, "clk_gmac0_rgmii_speed", mux_gmac0_rgmii_speed_p, 0,
RK3568_CLKSEL_CON(31), 4, 2, MFLAGS),
MUX(SCLK_GMAC0_RMII_SPEED, "clk_gmac0_rmii_speed", mux_gmac0_rmii_speed_p, 0,
RK3568_CLKSEL_CON(31), 3, 1, MFLAGS),
MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(31), 0, 2, MFLAGS),
/* PD_USB */
COMPOSITE_NODIV(ACLK_USB, "aclk_usb", gpll300_gpll200_gpll100_xin24m_p, 0,
RK3568_CLKSEL_CON(32), 0, 2, MFLAGS,
RK3568_CLKGATE_CON(16), 0, GFLAGS),
COMPOSITE_NODIV(HCLK_USB, "hclk_usb", gpll150_gpll100_gpll75_xin24m_p, 0,
RK3568_CLKSEL_CON(32), 2, 2, MFLAGS,
RK3568_CLKGATE_CON(16), 1, GFLAGS),
COMPOSITE_NOMUX(PCLK_USB, "pclk_usb", "aclk_usb", 0,
RK3568_CLKSEL_CON(32), 4, 4, DFLAGS,
RK3568_CLKGATE_CON(16), 2, GFLAGS),
GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 0,
RK3568_CLKGATE_CON(16), 12, GFLAGS),
GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 0,
RK3568_CLKGATE_CON(16), 13, GFLAGS),
GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 0,
RK3568_CLKGATE_CON(16), 14, GFLAGS),
GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 0,
RK3568_CLKGATE_CON(16), 15, GFLAGS),
GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 0,
RK3568_CLKGATE_CON(17), 0, GFLAGS),
COMPOSITE_NODIV(CLK_SDMMC2, "clk_sdmmc2", clk_sdmmc_p, 0,
RK3568_CLKSEL_CON(32), 8, 3, MFLAGS,
RK3568_CLKGATE_CON(17), 1, GFLAGS),
MMC(SCLK_SDMMC2_DRV, "sdmmc2_drv", "clk_sdmmc2", RK3568_SDMMC2_CON0, 1),
MMC(SCLK_SDMMC2_SAMPLE, "sdmmc2_sample", "clk_sdmmc2", RK3568_SDMMC2_CON1, 1),
GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 0,
RK3568_CLKGATE_CON(17), 3, GFLAGS),
GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 0,
RK3568_CLKGATE_CON(17), 4, GFLAGS),
COMPOSITE_NODIV(CLK_MAC1_2TOP, "clk_mac1_2top", clk_mac_2top_p, 0,
RK3568_CLKSEL_CON(33), 8, 2, MFLAGS,
RK3568_CLKGATE_CON(17), 5, GFLAGS),
COMPOSITE_NODIV(CLK_MAC1_OUT, "clk_mac1_out", cpll125_cpll50_cpll25_xin24m_p, 0,
RK3568_CLKSEL_CON(33), 14, 2, MFLAGS,
RK3568_CLKGATE_CON(17), 6, GFLAGS),
GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 0,
RK3568_CLKGATE_CON(17), 10, GFLAGS),
COMPOSITE_NODIV(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac_ptp_p, 0,
RK3568_CLKSEL_CON(33), 12, 2, MFLAGS,
RK3568_CLKGATE_CON(17), 2, GFLAGS),
MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3568_CLKSEL_CON(33), 2, 1, MFLAGS),
FACTOR(0, "clk_gmac1_tx_div5", "clk_gmac1", 0, 1, 5),
FACTOR(0, "clk_gmac1_tx_div50", "clk_gmac1", 0, 1, 50),
FACTOR(0, "clk_gmac1_rx_div2", "clk_gmac1", 0, 1, 2),
FACTOR(0, "clk_gmac1_rx_div20", "clk_gmac1", 0, 1, 20),
MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed", mux_gmac1_rgmii_speed_p, 0,
RK3568_CLKSEL_CON(33), 4, 2, MFLAGS),
MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed", mux_gmac1_rmii_speed_p, 0,
RK3568_CLKSEL_CON(33), 3, 1, MFLAGS),
MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p, CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(33), 0, 2, MFLAGS),
/* PD_PERI */
COMPOSITE_NODIV(ACLK_PERIMID, "aclk_perimid", gpll300_gpll200_gpll100_xin24m_p, CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(10), 4, 2, MFLAGS,
RK3568_CLKGATE_CON(14), 0, GFLAGS),
COMPOSITE_NODIV(HCLK_PERIMID, "hclk_perimid", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(10), 6, 2, MFLAGS,
RK3568_CLKGATE_CON(14), 1, GFLAGS),
/* PD_VI */
COMPOSITE_NODIV(ACLK_VI, "aclk_vi", gpll400_gpll300_gpll200_xin24m_p, 0,
RK3568_CLKSEL_CON(34), 0, 2, MFLAGS,
RK3568_CLKGATE_CON(18), 0, GFLAGS),
COMPOSITE_NOMUX(HCLK_VI, "hclk_vi", "aclk_vi", 0,
RK3568_CLKSEL_CON(34), 4, 4, DFLAGS,
RK3568_CLKGATE_CON(18), 1, GFLAGS),
COMPOSITE_NOMUX(PCLK_VI, "pclk_vi", "aclk_vi", 0,
RK3568_CLKSEL_CON(34), 8, 4, DFLAGS,
RK3568_CLKGATE_CON(18), 2, GFLAGS),
GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 0,
RK3568_CLKGATE_CON(18), 9, GFLAGS),
GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0,
RK3568_CLKGATE_CON(18), 10, GFLAGS),
COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", cpll333_gpll300_gpll200_p, 0,
RK3568_CLKSEL_CON(34), 14, 2, MFLAGS,
RK3568_CLKGATE_CON(18), 11, GFLAGS),
GATE(ICLK_VICAP_G, "iclk_vicap_g", "iclk_vicap", 0,
RK3568_CLKGATE_CON(18), 13, GFLAGS),
GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 0,
RK3568_CLKGATE_CON(19), 0, GFLAGS),
GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0,
RK3568_CLKGATE_CON(19), 1, GFLAGS),
COMPOSITE(CLK_ISP, "clk_isp", cpll_gpll_hpll_p, 0,
RK3568_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3568_CLKGATE_CON(19), 2, GFLAGS),
GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 0,
RK3568_CLKGATE_CON(19), 4, GFLAGS),
COMPOSITE(CLK_CIF_OUT, "clk_cif_out", gpll_usb480m_xin24m_p, 0,
RK3568_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 6, DFLAGS,
RK3568_CLKGATE_CON(19), 8, GFLAGS),
COMPOSITE(CLK_CAM0_OUT, "clk_cam0_out", gpll_usb480m_xin24m_p, 0,
RK3568_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3568_CLKGATE_CON(19), 9, GFLAGS),
COMPOSITE(CLK_CAM1_OUT, "clk_cam1_out", gpll_usb480m_xin24m_p, 0,
RK3568_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 6, DFLAGS,
RK3568_CLKGATE_CON(19), 10, GFLAGS),
/* PD_VO */
COMPOSITE_NODIV(ACLK_VO, "aclk_vo", gpll300_cpll250_gpll100_xin24m_p, 0,
RK3568_CLKSEL_CON(37), 0, 2, MFLAGS,
RK3568_CLKGATE_CON(20), 0, GFLAGS),
COMPOSITE_NOMUX(HCLK_VO, "hclk_vo", "aclk_vo", 0,
RK3568_CLKSEL_CON(37), 8, 4, DFLAGS,
RK3568_CLKGATE_CON(20), 1, GFLAGS),
COMPOSITE_NOMUX(PCLK_VO, "pclk_vo", "aclk_vo", 0,
RK3568_CLKSEL_CON(37), 12, 4, DFLAGS,
RK3568_CLKGATE_CON(20), 2, GFLAGS),
COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", cpll_gpll_hpll_vpll_p, 0,
RK3568_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3568_CLKGATE_CON(20), 6, GFLAGS),
GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0,
RK3568_CLKGATE_CON(20), 8, GFLAGS),
GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0,
RK3568_CLKGATE_CON(20), 9, GFLAGS),
COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS,
RK3568_CLKGATE_CON(20), 10, GFLAGS),
COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS,
RK3568_CLKGATE_CON(20), 11, GFLAGS),
COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS,
RK3568_CLKGATE_CON(20), 12, GFLAGS),
GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0,
RK3568_CLKGATE_CON(20), 13, GFLAGS),
GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 0,
RK3568_CLKGATE_CON(21), 0, GFLAGS),
GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 0,
RK3568_CLKGATE_CON(21), 1, GFLAGS),
GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 0,
RK3568_CLKGATE_CON(21), 2, GFLAGS),
GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 0,
RK3568_CLKGATE_CON(21), 3, GFLAGS),
GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0,
RK3568_CLKGATE_CON(21), 4, GFLAGS),
GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 0,
RK3568_CLKGATE_CON(21), 5, GFLAGS),
GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 0,
RK3568_CLKGATE_CON(21), 6, GFLAGS),
GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 0,
RK3568_CLKGATE_CON(21), 7, GFLAGS),
GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 0,
RK3568_CLKGATE_CON(21), 8, GFLAGS),
COMPOSITE_NODIV(CLK_EDP_200M, "clk_edp_200m", gpll200_gpll150_cpll125_p, 0,
RK3568_CLKSEL_CON(38), 8, 2, MFLAGS,
RK3568_CLKGATE_CON(21), 9, GFLAGS),
/* PD_VPU */
COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", gpll_cpll_p, 0,
RK3568_CLKSEL_CON(42), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3568_CLKGATE_CON(22), 0, GFLAGS),
COMPOSITE_NOMUX(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0,
RK3568_CLKSEL_CON(42), 8, 4, DFLAGS,
RK3568_CLKGATE_CON(22), 1, GFLAGS),
GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0,
RK3568_CLKGATE_CON(22), 4, GFLAGS),
GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0,
RK3568_CLKGATE_CON(22), 5, GFLAGS),
/* PD_RGA */
COMPOSITE_NODIV(ACLK_RGA_PRE, "aclk_rga_pre", gpll300_cpll250_gpll100_xin24m_p, 0,
RK3568_CLKSEL_CON(43), 0, 2, MFLAGS,
RK3568_CLKGATE_CON(23), 0, GFLAGS),
COMPOSITE_NOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_pre", 0,
RK3568_CLKSEL_CON(43), 8, 4, DFLAGS,
RK3568_CLKGATE_CON(23), 1, GFLAGS),
COMPOSITE_NOMUX(PCLK_RGA_PRE, "pclk_rga_pre", "aclk_rga_pre", 0,
RK3568_CLKSEL_CON(43), 12, 4, DFLAGS,
RK3568_CLKGATE_CON(22), 12, GFLAGS),
GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
RK3568_CLKGATE_CON(23), 4, GFLAGS),
GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
RK3568_CLKGATE_CON(23), 5, GFLAGS),
COMPOSITE_NODIV(CLK_RGA_CORE, "clk_rga_core", gpll300_gpll200_gpll100_p, 0,
RK3568_CLKSEL_CON(43), 2, 2, MFLAGS,
RK3568_CLKGATE_CON(23), 6, GFLAGS),
GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 0,
RK3568_CLKGATE_CON(23), 7, GFLAGS),
GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 0,
RK3568_CLKGATE_CON(23), 8, GFLAGS),
COMPOSITE_NODIV(CLK_IEP_CORE, "clk_iep_core", gpll300_gpll200_gpll100_p, 0,
RK3568_CLKSEL_CON(43), 4, 2, MFLAGS,
RK3568_CLKGATE_CON(23), 9, GFLAGS),
GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 10, GFLAGS),
COMPOSITE_NODIV(DCLK_EBC, "dclk_ebc", gpll400_cpll333_gpll200_p, 0,
RK3568_CLKSEL_CON(43), 6, 2, MFLAGS,
RK3568_CLKGATE_CON(23), 11, GFLAGS),
GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 0,
RK3568_CLKGATE_CON(23), 12, GFLAGS),
GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0,
RK3568_CLKGATE_CON(23), 13, GFLAGS),
GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 0,
RK3568_CLKGATE_CON(23), 14, GFLAGS),
GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 0,
RK3568_CLKGATE_CON(23), 15, GFLAGS),
GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 0,
RK3568_CLKGATE_CON(22), 14, GFLAGS),
GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 0,
RK3568_CLKGATE_CON(22), 15, GFLAGS),
/* PD_RKVENC */
COMPOSITE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", gpll_cpll_npll_p, 0,
RK3568_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3568_CLKGATE_CON(24), 0, GFLAGS),
COMPOSITE_NOMUX(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0,
RK3568_CLKSEL_CON(44), 8, 4, DFLAGS,
RK3568_CLKGATE_CON(24), 1, GFLAGS),
GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0,
RK3568_CLKGATE_CON(24), 6, GFLAGS),
GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0,
RK3568_CLKGATE_CON(24), 7, GFLAGS),
COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_npll_vpll_p, 0,
RK3568_CLKSEL_CON(45), 14, 2, MFLAGS, 0, 5, DFLAGS,
RK3568_CLKGATE_CON(24), 8, GFLAGS),
COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", aclk_rkvdec_pre_p, CLK_SET_RATE_NO_REPARENT,
RK3568_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3568_CLKGATE_CON(25), 0, GFLAGS),
COMPOSITE_NOMUX(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0,
RK3568_CLKSEL_CON(47), 8, 4, DFLAGS,
RK3568_CLKGATE_CON(25), 1, GFLAGS),
GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0,
RK3568_CLKGATE_CON(25), 4, GFLAGS),
GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0,
RK3568_CLKGATE_CON(25), 5, GFLAGS),
COMPOSITE(CLK_RKVDEC_CA, "clk_rkvdec_ca", gpll_cpll_npll_vpll_p, 0,
RK3568_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3568_CLKGATE_CON(25), 6, GFLAGS),
COMPOSITE(CLK_RKVDEC_CORE, "clk_rkvdec_core", clk_rkvdec_core_p, CLK_SET_RATE_NO_REPARENT,
RK3568_CLKSEL_CON(49), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3568_CLKGATE_CON(25), 7, GFLAGS),
COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_npll_vpll_p, 0,
RK3568_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3568_CLKGATE_CON(25), 8, GFLAGS),
/* PD_BUS */
COMPOSITE_NODIV(ACLK_BUS, "aclk_bus", gpll200_gpll150_gpll100_xin24m_p, 0,
RK3568_CLKSEL_CON(50), 0, 2, MFLAGS,
RK3568_CLKGATE_CON(26), 0, GFLAGS),
COMPOSITE_NODIV(PCLK_BUS, "pclk_bus", gpll100_gpll75_cpll50_xin24m_p, 0,
RK3568_CLKSEL_CON(50), 4, 2, MFLAGS,
RK3568_CLKGATE_CON(26), 1, GFLAGS),
GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0,
RK3568_CLKGATE_CON(26), 4, GFLAGS),
COMPOSITE(CLK_TSADC_TSEN, "clk_tsadc_tsen", xin24m_gpll100_cpll100_p, 0,
RK3568_CLKSEL_CON(51), 4, 2, MFLAGS, 0, 3, DFLAGS,
RK3568_CLKGATE_CON(26), 5, GFLAGS),
COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "clk_tsadc_tsen", 0,
RK3568_CLKSEL_CON(51), 8, 7, DFLAGS,
RK3568_CLKGATE_CON(26), 6, GFLAGS),
GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0,
RK3568_CLKGATE_CON(26), 7, GFLAGS),
GATE(CLK_SARADC, "clk_saradc", "xin24m", 0,
RK3568_CLKGATE_CON(26), 8, GFLAGS),
GATE(PCLK_SCR, "pclk_scr", "pclk_bus", CLK_IGNORE_UNUSED,
RK3568_CLKGATE_CON(26), 12, GFLAGS),
GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 0,
RK3568_CLKGATE_CON(26), 13, GFLAGS),
GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
RK3568_CLKGATE_CON(26), 14, GFLAGS),
GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", CLK_IGNORE_UNUSED,
RK3568_CLKGATE_CON(32), 13, GFLAGS),
GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", CLK_IGNORE_UNUSED,
RK3568_CLKGATE_CON(32), 14, GFLAGS),
GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0,
RK3568_CLKGATE_CON(32), 15, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0,
RK3568_CLKGATE_CON(27), 12, GFLAGS),
COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_usb480m_p, 0,
RK3568_CLKSEL_CON(52), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3568_CLKGATE_CON(27), 13, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(53), 0,
RK3568_CLKGATE_CON(27), 14, GFLAGS,
&rk3568_uart1_fracmux),
GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
RK3568_CLKGATE_CON(27), 15, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0,
RK3568_CLKGATE_CON(28), 0, GFLAGS),
COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_usb480m_p, 0,
RK3568_CLKSEL_CON(54), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3568_CLKGATE_CON(28), 1, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(55), 0,
RK3568_CLKGATE_CON(28), 2, GFLAGS,
&rk3568_uart2_fracmux),
GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0,
RK3568_CLKGATE_CON(28), 3, GFLAGS),
GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0,
RK3568_CLKGATE_CON(28), 4, GFLAGS),
COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_usb480m_p, 0,
RK3568_CLKSEL_CON(56), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3568_CLKGATE_CON(28), 5, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(57), 0,
RK3568_CLKGATE_CON(28), 6, GFLAGS,
&rk3568_uart3_fracmux),
GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
RK3568_CLKGATE_CON(28), 7, GFLAGS),
GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 0,
RK3568_CLKGATE_CON(28), 8, GFLAGS),
COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_usb480m_p, 0,
RK3568_CLKSEL_CON(58), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3568_CLKGATE_CON(28), 9, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(59), 0,
RK3568_CLKGATE_CON(28), 10, GFLAGS,
&rk3568_uart4_fracmux),
GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
RK3568_CLKGATE_CON(28), 11, GFLAGS),
GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 0,
RK3568_CLKGATE_CON(28), 12, GFLAGS),
COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_usb480m_p, 0,
RK3568_CLKSEL_CON(60), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3568_CLKGATE_CON(28), 13, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(61), 0,
RK3568_CLKGATE_CON(28), 14, GFLAGS,
&rk3568_uart5_fracmux),
GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
RK3568_CLKGATE_CON(28), 15, GFLAGS),
GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 0,
RK3568_CLKGATE_CON(29), 0, GFLAGS),
COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_usb480m_p, 0,
RK3568_CLKSEL_CON(62), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3568_CLKGATE_CON(29), 1, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(63), 0,
RK3568_CLKGATE_CON(29), 2, GFLAGS,
&rk3568_uart6_fracmux),
GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_mux", 0,
RK3568_CLKGATE_CON(29), 3, GFLAGS),
GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 0,
RK3568_CLKGATE_CON(29), 4, GFLAGS),
COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_usb480m_p, 0,
RK3568_CLKSEL_CON(64), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3568_CLKGATE_CON(29), 5, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(65), 0,
RK3568_CLKGATE_CON(29), 6, GFLAGS,
&rk3568_uart7_fracmux),
GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_mux", 0,
RK3568_CLKGATE_CON(29), 7, GFLAGS),
GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 0,
RK3568_CLKGATE_CON(29), 8, GFLAGS),
COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_usb480m_p, 0,
RK3568_CLKSEL_CON(66), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3568_CLKGATE_CON(29), 9, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(67), 0,
RK3568_CLKGATE_CON(29), 10, GFLAGS,
&rk3568_uart8_fracmux),
GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_mux", 0,
RK3568_CLKGATE_CON(29), 11, GFLAGS),
GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 0,
RK3568_CLKGATE_CON(29), 12, GFLAGS),
COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_usb480m_p, 0,
RK3568_CLKSEL_CON(68), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3568_CLKGATE_CON(29), 13, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT,
RK3568_CLKSEL_CON(69), 0,
RK3568_CLKGATE_CON(29), 14, GFLAGS,
&rk3568_uart9_fracmux),
GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_mux", 0,
RK3568_CLKGATE_CON(29), 15, GFLAGS),
GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 0,
RK3568_CLKGATE_CON(27), 5, GFLAGS),
COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0,
RK3568_CLKSEL_CON(70), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3568_CLKGATE_CON(27), 6, GFLAGS),
GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 0,
RK3568_CLKGATE_CON(27), 7, GFLAGS),
COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0,
RK3568_CLKSEL_CON(70), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3568_CLKGATE_CON(27), 8, GFLAGS),
GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 0,
RK3568_CLKGATE_CON(27), 9, GFLAGS),
COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0,
RK3568_CLKSEL_CON(71), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3568_CLKGATE_CON(27), 10, GFLAGS),
COMPOSITE_NODIV(CLK_I2C, "clk_i2c", clk_i2c_p, 0,
RK3568_CLKSEL_CON(71), 8, 2, MFLAGS,
RK3568_CLKGATE_CON(32), 10, GFLAGS),
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0,
RK3568_CLKGATE_CON(30), 0, GFLAGS),
GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0,
RK3568_CLKGATE_CON(30), 1, GFLAGS),
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0,
RK3568_CLKGATE_CON(30), 2, GFLAGS),
GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0,
RK3568_CLKGATE_CON(30), 3, GFLAGS),
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0,
RK3568_CLKGATE_CON(30), 4, GFLAGS),
GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0,
RK3568_CLKGATE_CON(30), 5, GFLAGS),
GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0,
RK3568_CLKGATE_CON(30), 6, GFLAGS),
GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0,
RK3568_CLKGATE_CON(30), 7, GFLAGS),
GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0,
RK3568_CLKGATE_CON(30), 8, GFLAGS),
GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0,
RK3568_CLKGATE_CON(30), 9, GFLAGS),
GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0,
RK3568_CLKGATE_CON(30), 10, GFLAGS),
COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", gpll200_xin24m_cpll100_p, 0,
RK3568_CLKSEL_CON(72), 0, 1, MFLAGS,
RK3568_CLKGATE_CON(30), 11, GFLAGS),
GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0,
RK3568_CLKGATE_CON(30), 12, GFLAGS),
COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", gpll200_xin24m_cpll100_p, 0,
RK3568_CLKSEL_CON(72), 2, 1, MFLAGS,
RK3568_CLKGATE_CON(30), 13, GFLAGS),
GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0,
RK3568_CLKGATE_CON(30), 14, GFLAGS),
COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", gpll200_xin24m_cpll100_p, 0,
RK3568_CLKSEL_CON(72), 4, 1, MFLAGS,
RK3568_CLKGATE_CON(30), 15, GFLAGS),
GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 0,
RK3568_CLKGATE_CON(31), 0, GFLAGS),
COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", gpll200_xin24m_cpll100_p, 0,
RK3568_CLKSEL_CON(72), 6, 1, MFLAGS, RK3568_CLKGATE_CON(31), 1, GFLAGS),
GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 10, GFLAGS),
COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 0,
RK3568_CLKSEL_CON(72), 8, 1, MFLAGS,
RK3568_CLKGATE_CON(31), 11, GFLAGS),
GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0,
RK3568_CLKGATE_CON(31), 12, GFLAGS),
GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 0,
RK3568_CLKGATE_CON(31), 13, GFLAGS),
COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", gpll100_xin24m_cpll100_p, 0,
RK3568_CLKSEL_CON(72), 10, 1, MFLAGS,
RK3568_CLKGATE_CON(31), 14, GFLAGS),
GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0,
RK3568_CLKGATE_CON(31), 15, GFLAGS),
GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 0,
RK3568_CLKGATE_CON(32), 0, GFLAGS),
COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", gpll100_xin24m_cpll100_p, 0,
RK3568_CLKSEL_CON(72), 12, 1, MFLAGS,
RK3568_CLKGATE_CON(32), 1, GFLAGS),
GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0,
RK3568_CLKGATE_CON(32), 2, GFLAGS),
COMPOSITE_NODIV(DBCLK_GPIO, "dbclk_gpio", xin24m_32k_p, 0,
RK3568_CLKSEL_CON(72), 14, 1, MFLAGS,
RK3568_CLKGATE_CON(32), 11, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0,
RK3568_CLKGATE_CON(31), 2, GFLAGS),
GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 0,
RK3568_CLKGATE_CON(31), 3, GFLAGS),
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0,
RK3568_CLKGATE_CON(31), 4, GFLAGS),
GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 0,
RK3568_CLKGATE_CON(31), 5, GFLAGS),
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0,
RK3568_CLKGATE_CON(31), 6, GFLAGS),
GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 0,
RK3568_CLKGATE_CON(31), 7, GFLAGS),
GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 0,
RK3568_CLKGATE_CON(31), 8, GFLAGS),
GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 0,
RK3568_CLKGATE_CON(31), 9, GFLAGS),
GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0,
RK3568_CLKGATE_CON(32), 3, GFLAGS),
GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
RK3568_CLKGATE_CON(32), 4, GFLAGS),
GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
RK3568_CLKGATE_CON(32), 5, GFLAGS),
GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
RK3568_CLKGATE_CON(32), 6, GFLAGS),
GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
RK3568_CLKGATE_CON(32), 7, GFLAGS),
GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
RK3568_CLKGATE_CON(32), 8, GFLAGS),
GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
RK3568_CLKGATE_CON(32), 9, GFLAGS),
/* PD_TOP */
COMPOSITE_NODIV(ACLK_TOP_HIGH, "aclk_top_high", cpll500_gpll400_gpll300_xin24m_p, 0,
RK3568_CLKSEL_CON(73), 0, 2, MFLAGS,
RK3568_CLKGATE_CON(33), 0, GFLAGS),
COMPOSITE_NODIV(ACLK_TOP_LOW, "aclk_top_low", gpll400_gpll300_gpll200_xin24m_p, 0,
RK3568_CLKSEL_CON(73), 4, 2, MFLAGS,
RK3568_CLKGATE_CON(33), 1, GFLAGS),
COMPOSITE_NODIV(HCLK_TOP, "hclk_top", gpll150_gpll100_gpll75_xin24m_p, 0,
RK3568_CLKSEL_CON(73), 8, 2, MFLAGS,
RK3568_CLKGATE_CON(33), 2, GFLAGS),
COMPOSITE_NODIV(PCLK_TOP, "pclk_top", gpll100_gpll75_cpll50_xin24m_p, 0,
RK3568_CLKSEL_CON(73), 12, 2, MFLAGS,
RK3568_CLKGATE_CON(33), 3, GFLAGS),
GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 0,
RK3568_CLKGATE_CON(33), 8, GFLAGS),
COMPOSITE_NODIV(CLK_OPTC_ARB, "clk_optc_arb", xin24m_cpll100_p, 0,
RK3568_CLKSEL_CON(73), 15, 1, MFLAGS,
RK3568_CLKGATE_CON(33), 9, GFLAGS),
GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 0,
RK3568_CLKGATE_CON(33), 13, GFLAGS),
GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 0,
RK3568_CLKGATE_CON(33), 14, GFLAGS),
GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 0,
RK3568_CLKGATE_CON(33), 15, GFLAGS),
GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 0,
RK3568_CLKGATE_CON(34), 4, GFLAGS),
GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 0,
RK3568_CLKGATE_CON(34), 5, GFLAGS),
GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 0,
RK3568_CLKGATE_CON(34), 6, GFLAGS),
GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 0,
RK3568_CLKGATE_CON(34), 11, GFLAGS),
GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 0,
RK3568_CLKGATE_CON(34), 12, GFLAGS),
GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 0,
RK3568_CLKGATE_CON(34), 13, GFLAGS),
GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 0,
RK3568_CLKGATE_CON(34), 14, GFLAGS),
};
static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = {
/* PD_PMU */
FACTOR(0, "ppll_ph0", "ppll", 0, 1, 2),
FACTOR(0, "ppll_ph180", "ppll", 0, 1, 2),
FACTOR(0, "hpll_ph0", "hpll", 0, 1, 2),
MUX(CLK_PDPMU, "clk_pdpmu", clk_pdpmu_p, 0,
RK3568_PMU_CLKSEL_CON(2), 15, 1, MFLAGS),
COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "clk_pdpmu", 0,
RK3568_PMU_CLKSEL_CON(2), 0, 5, DFLAGS,
RK3568_PMU_CLKGATE_CON(0), 2, GFLAGS),
GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", 0,
RK3568_PMU_CLKGATE_CON(0), 6, GFLAGS),
GATE(CLK_PMU, "clk_pmu", "xin24m", 0,
RK3568_PMU_CLKGATE_CON(0), 7, GFLAGS),
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0,
RK3568_PMU_CLKGATE_CON(1), 0, GFLAGS),
COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "clk_pdpmu", 0,
RK3568_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
RK3568_PMU_CLKGATE_CON(1), 1, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 0,
RK3568_PMU_CLKGATE_CON(1), 2, GFLAGS),
COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
RK3568_PMU_CLKSEL_CON(1), 0,
RK3568_PMU_CLKGATE_CON(0), 1, GFLAGS,
&rk3568_rtc32k_pmu_fracmux),
COMPOSITE_NOMUX(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IGNORE_UNUSED,
RK3568_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,
RK3568_PMU_CLKGATE_CON(0), 0, GFLAGS),
COMPOSITE(CLK_UART0_DIV, "sclk_uart0_div", ppll_usb480m_cpll_gpll_p, 0,
RK3568_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3568_PMU_CLKGATE_CON(1), 3, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT,
RK3568_PMU_CLKSEL_CON(5), 0,
RK3568_PMU_CLKGATE_CON(1), 4, GFLAGS,
&rk3568_uart0_fracmux),
GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0,
RK3568_PMU_CLKGATE_CON(1), 5, GFLAGS),
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0,
RK3568_PMU_CLKGATE_CON(1), 9, GFLAGS),
COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", xin24m_32k_p, 0,
RK3568_PMU_CLKSEL_CON(6), 15, 1, MFLAGS,
RK3568_PMU_CLKGATE_CON(1), 10, GFLAGS),
GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,
RK3568_PMU_CLKGATE_CON(1), 6, GFLAGS),
COMPOSITE(CLK_PWM0, "clk_pwm0", clk_pwm0_p, 0,
RK3568_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3568_PMU_CLKGATE_CON(1), 7, GFLAGS),
GATE(CLK_CAPTURE_PWM0_NDFT, "clk_capture_pwm0_ndft", "xin24m", 0,
RK3568_PMU_CLKGATE_CON(1), 8, GFLAGS),
GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0,
RK3568_PMU_CLKGATE_CON(1), 11, GFLAGS),
GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0,
RK3568_PMU_CLKGATE_CON(1), 12, GFLAGS),
GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0,
RK3568_PMU_CLKGATE_CON(1), 13, GFLAGS),
COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "clk_pdpmu", 0,
RK3568_PMU_CLKSEL_CON(7), 0, 6, DFLAGS,
RK3568_PMU_CLKGATE_CON(2), 0, GFLAGS),
GATE(XIN_OSC0_USBPHY0_G, "xin_osc0_usbphy0_g", "xin24m", 0,
RK3568_PMU_CLKGATE_CON(2), 1, GFLAGS),
MUX(CLK_USBPHY0_REF, "clk_usbphy0_ref", clk_usbphy0_ref_p, 0,
RK3568_PMU_CLKSEL_CON(8), 0, 1, MFLAGS),
GATE(XIN_OSC0_USBPHY1_G, "xin_osc0_usbphy1_g", "xin24m", 0,
RK3568_PMU_CLKGATE_CON(2), 2, GFLAGS),
MUX(CLK_USBPHY1_REF, "clk_usbphy1_ref", clk_usbphy1_ref_p, 0,
RK3568_PMU_CLKSEL_CON(8), 1, 1, MFLAGS),
GATE(XIN_OSC0_MIPIDSIPHY0_G, "xin_osc0_mipidsiphy0_g", "xin24m", 0,
RK3568_PMU_CLKGATE_CON(2), 3, GFLAGS),
MUX(CLK_MIPIDSIPHY0_REF, "clk_mipidsiphy0_ref", clk_mipidsiphy0_ref_p, 0,
RK3568_PMU_CLKSEL_CON(8), 2, 1, MFLAGS),
GATE(XIN_OSC0_MIPIDSIPHY1_G, "xin_osc0_mipidsiphy1_g", "xin24m", 0,
RK3568_PMU_CLKGATE_CON(2), 4, GFLAGS),
MUX(CLK_MIPIDSIPHY1_REF, "clk_mipidsiphy1_ref", clk_mipidsiphy1_ref_p, 0,
RK3568_PMU_CLKSEL_CON(8), 3, 1, MFLAGS),
COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "clk_pdpmu", 0,
RK3568_PMU_CLKSEL_CON(8), 8, 6, DFLAGS,
RK3568_PMU_CLKGATE_CON(2), 5, GFLAGS),
GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0,
RK3568_PMU_CLKGATE_CON(2), 6, GFLAGS),
MUX(CLK_WIFI, "clk_wifi", clk_wifi_p, CLK_SET_RATE_PARENT,
RK3568_PMU_CLKSEL_CON(8), 15, 1, MFLAGS),
COMPOSITE_NOMUX(CLK_PCIEPHY0_DIV, "clk_pciephy0_div", "ppll_ph0", 0,
RK3568_PMU_CLKSEL_CON(9), 0, 3, DFLAGS,
RK3568_PMU_CLKGATE_CON(2), 7, GFLAGS),
GATE(CLK_PCIEPHY0_OSC0, "clk_pciephy0_osc0", "xin24m", 0,
RK3568_PMU_CLKGATE_CON(2), 8, GFLAGS),
MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref", clk_pciephy0_ref_p, CLK_SET_RATE_PARENT,
RK3568_PMU_CLKSEL_CON(9), 3, 1, MFLAGS),
COMPOSITE_NOMUX(CLK_PCIEPHY1_DIV, "clk_pciephy1_div", "ppll_ph0", 0,
RK3568_PMU_CLKSEL_CON(9), 4, 3, DFLAGS,
RK3568_PMU_CLKGATE_CON(2), 9, GFLAGS),
GATE(CLK_PCIEPHY1_OSC0, "clk_pciephy1_osc0", "xin24m", 0,
RK3568_PMU_CLKGATE_CON(2), 10, GFLAGS),
MUX(CLK_PCIEPHY1_REF, "clk_pciephy1_ref", clk_pciephy1_ref_p, CLK_SET_RATE_PARENT,
RK3568_PMU_CLKSEL_CON(9), 7, 1, MFLAGS),
COMPOSITE_NOMUX(CLK_PCIEPHY2_DIV, "clk_pciephy2_div", "ppll_ph0", 0,
RK3568_PMU_CLKSEL_CON(9), 8, 3, DFLAGS,
RK3568_PMU_CLKGATE_CON(2), 11, GFLAGS),
GATE(CLK_PCIEPHY2_OSC0, "clk_pciephy2_osc0", "xin24m", 0,
RK3568_PMU_CLKGATE_CON(2), 12, GFLAGS),
MUX(CLK_PCIEPHY2_REF, "clk_pciephy2_ref", clk_pciephy2_ref_p, CLK_SET_RATE_PARENT,
RK3568_PMU_CLKSEL_CON(9), 11, 1, MFLAGS),
GATE(CLK_PCIE30PHY_REF_M, "clk_pcie30phy_ref_m", "ppll_ph0", 0,
RK3568_PMU_CLKGATE_CON(2), 13, GFLAGS),
GATE(CLK_PCIE30PHY_REF_N, "clk_pcie30phy_ref_n", "ppll_ph180", 0,
RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS),
GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0,
RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS),
MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, CLK_SET_RATE_PARENT,
RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS),
};
static const char *const rk3568_cru_critical_clocks[] __initconst = {
"armclk",
"pclk_core_pre",
"aclk_bus",
"pclk_bus",
"aclk_top_high",
"aclk_top_low",
"hclk_top",
"pclk_top",
"aclk_perimid",
"hclk_perimid",
"aclk_secure_flash",
"hclk_secure_flash",
"aclk_core_niu2bus",
"npll",
"clk_optc_arb",
"hclk_php",
"pclk_php",
"hclk_usb",
"hclk_vo",
};
static const char *const rk3568_pmucru_critical_clocks[] __initconst = {
"pclk_pdpmu",
"pclk_pmu",
"clk_pmu",
};
static void __init rk3568_pmu_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru pmu region\n", __func__);
return;
}
ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
if (IS_ERR(ctx)) {
pr_err("%s: rockchip pmu clk init failed\n", __func__);
return;
}
rockchip_clk_register_plls(ctx, rk3568_pmu_pll_clks,
ARRAY_SIZE(rk3568_pmu_pll_clks),
RK3568_GRF_SOC_STATUS0);
rockchip_clk_register_branches(ctx, rk3568_clk_pmu_branches,
ARRAY_SIZE(rk3568_clk_pmu_branches));
rockchip_register_softrst(np, 1, reg_base + RK3568_PMU_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
rockchip_clk_protect_critical(rk3568_pmucru_critical_clocks,
ARRAY_SIZE(rk3568_pmucru_critical_clocks));
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rk3568_cru_pmu, "rockchip,rk3568-pmucru", rk3568_pmu_clk_init);
static void __init rk3568_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru region\n", __func__);
return;
}
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
if (IS_ERR(ctx)) {
pr_err("%s: rockchip clk init failed\n", __func__);
iounmap(reg_base);
return;
}
rockchip_clk_register_plls(ctx, rk3568_pll_clks,
ARRAY_SIZE(rk3568_pll_clks),
RK3568_GRF_SOC_STATUS0);
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
&rk3568_cpuclk_data, rk3568_cpuclk_rates,
ARRAY_SIZE(rk3568_cpuclk_rates));
rockchip_clk_register_branches(ctx, rk3568_clk_branches,
ARRAY_SIZE(rk3568_clk_branches));
rockchip_register_softrst(np, 30, reg_base + RK3568_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
rockchip_register_restart_notifier(ctx, RK3568_GLB_SRST_FST, NULL);
rockchip_clk_protect_critical(rk3568_cru_critical_clocks,
ARRAY_SIZE(rk3568_cru_critical_clocks));
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rk3568_cru, "rockchip,rk3568-cru", rk3568_clk_init);
struct clk_rk3568_inits {
void (*inits)(struct device_node *np);
};
static const struct clk_rk3568_inits clk_rk3568_pmucru_init = {
.inits = rk3568_pmu_clk_init,
};
static const struct clk_rk3568_inits clk_3568_cru_init = {
.inits = rk3568_clk_init,
};
static const struct of_device_id clk_rk3568_match_table[] = {
{
.compatible = "rockchip,rk3568-cru",
.data = &clk_3568_cru_init,
}, {
.compatible = "rockchip,rk3568-pmucru",
.data = &clk_rk3568_pmucru_init,
},
{ }
};
static int __init clk_rk3568_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
const struct clk_rk3568_inits *init_data;
init_data = (struct clk_rk3568_inits *)of_device_get_match_data(&pdev->dev);
if (!init_data)
return -EINVAL;
if (init_data->inits)
init_data->inits(np);
return 0;
}
static struct platform_driver clk_rk3568_driver = {
.driver = {
.name = "clk-rk3568",
.of_match_table = clk_rk3568_match_table,
.suppress_bind_attrs = true,
},
};
builtin_platform_driver_probe(clk_rk3568_driver, clk_rk3568_probe);
| linux-master | drivers/clk/rockchip/clk-rk3568.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2015 Rockchip Electronics Co. Ltd.
* Author: Xing Zheng <[email protected]>
* Jeffy Chen <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include "clk.h"
#define RK3228_GRF_SOC_STATUS0 0x480
enum rk3228_plls {
apll, dpll, cpll, gpll,
};
static struct rockchip_pll_rate_table rk3228_pll_rates[] = {
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
{ /* sentinel */ },
};
#define RK3228_DIV_CPU_MASK 0x1f
#define RK3228_DIV_CPU_SHIFT 8
#define RK3228_DIV_PERI_MASK 0xf
#define RK3228_DIV_PERI_SHIFT 0
#define RK3228_DIV_ACLK_MASK 0x7
#define RK3228_DIV_ACLK_SHIFT 4
#define RK3228_DIV_HCLK_MASK 0x3
#define RK3228_DIV_HCLK_SHIFT 8
#define RK3228_DIV_PCLK_MASK 0x7
#define RK3228_DIV_PCLK_SHIFT 12
#define RK3228_CLKSEL1(_core_aclk_div, _core_peri_div) \
{ \
.reg = RK2928_CLKSEL_CON(1), \
.val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \
RK3228_DIV_PERI_SHIFT) | \
HIWORD_UPDATE(_core_aclk_div, RK3228_DIV_ACLK_MASK, \
RK3228_DIV_ACLK_SHIFT), \
}
#define RK3228_CPUCLK_RATE(_prate, _core_aclk_div, _core_peri_div) \
{ \
.prate = _prate, \
.divs = { \
RK3228_CLKSEL1(_core_aclk_div, _core_peri_div), \
}, \
}
static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = {
RK3228_CPUCLK_RATE(1800000000, 1, 7),
RK3228_CPUCLK_RATE(1704000000, 1, 7),
RK3228_CPUCLK_RATE(1608000000, 1, 7),
RK3228_CPUCLK_RATE(1512000000, 1, 7),
RK3228_CPUCLK_RATE(1488000000, 1, 5),
RK3228_CPUCLK_RATE(1464000000, 1, 5),
RK3228_CPUCLK_RATE(1416000000, 1, 5),
RK3228_CPUCLK_RATE(1392000000, 1, 5),
RK3228_CPUCLK_RATE(1296000000, 1, 5),
RK3228_CPUCLK_RATE(1200000000, 1, 5),
RK3228_CPUCLK_RATE(1104000000, 1, 5),
RK3228_CPUCLK_RATE(1008000000, 1, 5),
RK3228_CPUCLK_RATE(912000000, 1, 5),
RK3228_CPUCLK_RATE(816000000, 1, 3),
RK3228_CPUCLK_RATE(696000000, 1, 3),
RK3228_CPUCLK_RATE(600000000, 1, 3),
RK3228_CPUCLK_RATE(408000000, 1, 1),
RK3228_CPUCLK_RATE(312000000, 1, 1),
RK3228_CPUCLK_RATE(216000000, 1, 1),
RK3228_CPUCLK_RATE(96000000, 1, 1),
};
static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = {
.core_reg[0] = RK2928_CLKSEL_CON(0),
.div_core_shift[0] = 0,
.div_core_mask[0] = 0x1f,
.num_cores = 1,
.mux_core_alt = 1,
.mux_core_main = 0,
.mux_core_shift = 6,
.mux_core_mask = 0x1,
};
PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" };
PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" };
PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" };
PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" };
PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy", "usb480m" };
PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" };
PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" };
PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" };
PNAME(mux_aclk_peri_src_p) = { "cpll_peri", "gpll_peri", "hdmiphy_peri" };
PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" };
PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" };
PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" };
PNAME(mux_sclk_vop_src_p) = { "gpll_vop", "cpll_vop" };
PNAME(mux_dclk_vop_p) = { "hdmiphy", "sclk_vop_pre" };
PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" };
PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" };
PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" };
PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" };
PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
PNAME(mux_sclk_mac_extclk_p) = { "ext_gmac", "phy_50m_out" };
PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_mac_extclk" };
PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" };
static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = {
[apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
RK2928_MODE_CON, 0, 7, 0, rk3228_pll_rates),
[dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3),
RK2928_MODE_CON, 4, 6, 0, NULL),
[cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
RK2928_MODE_CON, 8, 8, 0, NULL),
[gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9),
RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates),
};
#define MFLAGS CLK_MUX_HIWORD_MASK
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
static struct rockchip_clk_branch rk3228_i2s0_fracmux __initdata =
MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(9), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3228_i2s1_fracmux __initdata =
MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3228_i2s2_fracmux __initdata =
MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(16), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3228_spdif_fracmux __initdata =
MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(6), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3228_uart0_fracmux __initdata =
MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3228_uart1_fracmux __initdata =
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3228_uart2_fracmux __initdata =
MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
/*
* Clock-Architecture Diagram 1
*/
DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
/* PD_DDR */
GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 2, GFLAGS),
GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 2, GFLAGS),
GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 2, GFLAGS),
COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK2928_CLKGATE_CON(7), 1, GFLAGS),
GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(8), 5, GFLAGS),
FACTOR_GATE(0, "ddrphy", "ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
RK2928_CLKGATE_CON(7), 0, GFLAGS),
/* PD_CORE */
GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 6, GFLAGS),
GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 6, GFLAGS),
GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 6, GFLAGS),
COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK2928_CLKGATE_CON(4), 1, GFLAGS),
COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK2928_CLKGATE_CON(4), 0, GFLAGS),
/* PD_MISC */
MUX(SCLK_HDMI_PHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
RK2928_MISC_CON, 13, 1, MFLAGS),
MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,
RK2928_MISC_CON, 14, 1, MFLAGS),
MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
RK2928_MISC_CON, 15, 1, MFLAGS),
/* PD_BUS */
GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 1, GFLAGS),
GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 1, GFLAGS),
GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 1, GFLAGS),
COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS),
GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0,
RK2928_CLKGATE_CON(6), 0, GFLAGS),
COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", 0,
RK2928_CLKSEL_CON(1), 8, 2, DFLAGS,
RK2928_CLKGATE_CON(6), 1, GFLAGS),
COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0,
RK2928_CLKSEL_CON(1), 12, 3, DFLAGS,
RK2928_CLKGATE_CON(6), 2, GFLAGS),
GATE(PCLK_CPU, "pclk_cpu", "pclk_bus_src", 0,
RK2928_CLKGATE_CON(6), 3, GFLAGS),
GATE(0, "pclk_phy_pre", "pclk_bus_src", 0,
RK2928_CLKGATE_CON(6), 4, GFLAGS),
GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0,
RK2928_CLKGATE_CON(6), 13, GFLAGS),
/* PD_VIDEO */
COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 11, GFLAGS),
FACTOR_GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4,
RK2928_CLKGATE_CON(4), 4, GFLAGS),
COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 2, GFLAGS),
FACTOR_GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4,
RK2928_CLKGATE_CON(4), 5, GFLAGS),
COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 3, GFLAGS),
COMPOSITE(SCLK_VDEC_CORE, "sclk_vdec_core", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 4, GFLAGS),
/* PD_VIO */
COMPOSITE(ACLK_IEP_PRE, "aclk_iep_pre", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 0, GFLAGS),
DIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_iep_pre", 0,
RK2928_CLKSEL_CON(2), 0, 5, DFLAGS),
COMPOSITE(ACLK_HDCP_PRE, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(1), 4, GFLAGS),
MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(33), 13, 2, MFLAGS),
COMPOSITE_NOMUX(ACLK_RGA_PRE, "aclk_rga_pre", "sclk_rga_src", 0,
RK2928_CLKSEL_CON(33), 8, 5, DFLAGS,
RK2928_CLKGATE_CON(1), 2, GFLAGS),
COMPOSITE(SCLK_RGA, "sclk_rga", mux_sclk_rga_p, 0,
RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 6, GFLAGS),
COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(1), 1, GFLAGS),
COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 6, DFLAGS,
RK2928_CLKGATE_CON(3), 5, GFLAGS),
GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
RK2928_CLKGATE_CON(3), 7, GFLAGS),
COMPOSITE(SCLK_HDMI_CEC, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0,
RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, 0, 14, DFLAGS,
RK2928_CLKGATE_CON(3), 8, GFLAGS),
/* PD_PERI */
GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(2), 0, GFLAGS),
GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(2), 0, GFLAGS),
GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(2), 0, GFLAGS),
COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0,
RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS),
COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
RK2928_CLKSEL_CON(10), 12, 3, DFLAGS,
RK2928_CLKGATE_CON(5), 2, GFLAGS),
COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
RK2928_CLKSEL_CON(10), 8, 2, DFLAGS,
RK2928_CLKGATE_CON(5), 1, GFLAGS),
GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
RK2928_CLKGATE_CON(5), 0, GFLAGS),
GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
RK2928_CLKGATE_CON(6), 5, GFLAGS),
GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
RK2928_CLKGATE_CON(6), 6, GFLAGS),
GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
RK2928_CLKGATE_CON(6), 7, GFLAGS),
GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
RK2928_CLKGATE_CON(6), 8, GFLAGS),
GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
RK2928_CLKGATE_CON(6), 9, GFLAGS),
GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
RK2928_CLKGATE_CON(6), 10, GFLAGS),
COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_2plls_p, 0,
RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(2), 7, GFLAGS),
COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_2plls_p, 0,
RK2928_CLKSEL_CON(22), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(2), 6, GFLAGS),
GATE(SCLK_HSADC, "sclk_hsadc", "ext_hsadc", 0,
RK2928_CLKGATE_CON(10), 12, GFLAGS),
COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
RK2928_CLKGATE_CON(2), 15, GFLAGS),
COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK2928_CLKGATE_CON(2), 11, GFLAGS),
COMPOSITE_NODIV(SCLK_SDIO_SRC, "sclk_sdio_src", mux_mmc_src_p, 0,
RK2928_CLKSEL_CON(11), 10, 2, MFLAGS,
RK2928_CLKGATE_CON(2), 13, GFLAGS),
DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
RK2928_CLKSEL_CON(12), 0, 8, DFLAGS),
COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0,
RK2928_CLKSEL_CON(11), 12, 2, MFLAGS,
RK2928_CLKGATE_CON(2), 14, GFLAGS),
DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0,
RK2928_CLKSEL_CON(12), 8, 8, DFLAGS),
/*
* Clock-Architecture Diagram 2
*/
GATE(0, "gpll_vop", "gpll", 0,
RK2928_CLKGATE_CON(3), 1, GFLAGS),
GATE(0, "cpll_vop", "cpll", 0,
RK2928_CLKGATE_CON(3), 1, GFLAGS),
MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0,
RK2928_CLKSEL_CON(27), 0, 1, MFLAGS),
DIV(DCLK_HDMI_PHY, "dclk_hdmiphy", "sclk_vop_src", 0,
RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),
MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0,
RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,
RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 3, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(8), 0,
RK2928_CLKGATE_CON(0), 4, GFLAGS,
&rk3228_i2s0_fracmux),
GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
RK2928_CLKGATE_CON(0), 5, GFLAGS),
COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0,
RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 10, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(7), 0,
RK2928_CLKGATE_CON(0), 11, GFLAGS,
&rk3228_i2s1_fracmux),
GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
RK2928_CLKGATE_CON(0), 14, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
RK2928_CLKGATE_CON(0), 13, GFLAGS),
COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0,
RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 7, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(30), 0,
RK2928_CLKGATE_CON(0), 8, GFLAGS,
&rk3228_i2s2_fracmux),
GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
RK2928_CLKGATE_CON(0), 9, GFLAGS),
COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0,
RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(2), 10, GFLAGS),
COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(20), 0,
RK2928_CLKGATE_CON(2), 12, GFLAGS,
&rk3228_spdif_fracmux),
GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 3, GFLAGS),
GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 0,
RK2928_CLKGATE_CON(1), 5, GFLAGS),
GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", 0,
RK2928_CLKGATE_CON(1), 6, GFLAGS),
COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,
RK2928_CLKSEL_CON(24), 6, 10, DFLAGS,
RK2928_CLKGATE_CON(2), 8, GFLAGS),
COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 13, GFLAGS),
COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0,
RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(2), 9, GFLAGS),
/* PD_UART */
COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb480m_p, 0,
RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 8, GFLAGS),
COMPOSITE(0, "uart1_src", mux_pll_src_cpll_gpll_usb480m_p, 0,
RK2928_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 10, GFLAGS),
COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p,
0, RK2928_CLKSEL_CON(15), 12, 2,
MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS),
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(17), 0,
RK2928_CLKGATE_CON(1), 9, GFLAGS,
&rk3228_uart0_fracmux),
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(18), 0,
RK2928_CLKGATE_CON(1), 11, GFLAGS,
&rk3228_uart1_fracmux),
COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(19), 0,
RK2928_CLKGATE_CON(1), 13, GFLAGS,
&rk3228_uart2_fracmux),
COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(1), 0, GFLAGS),
COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_2plls_p, 0,
RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(1), 7, GFLAGS),
MUX(SCLK_MAC_EXTCLK, "sclk_mac_extclk", mux_sclk_mac_extclk_p, 0,
RK2928_CLKSEL_CON(29), 10, 1, MFLAGS),
MUX(SCLK_MAC, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0,
RK2928_CLKSEL_CON(5), 5, 1, MFLAGS),
GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_gmac_pre", 0,
RK2928_CLKGATE_CON(5), 4, GFLAGS),
GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_gmac_pre", 0,
RK2928_CLKGATE_CON(5), 3, GFLAGS),
GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_gmac_pre", 0,
RK2928_CLKGATE_CON(5), 5, GFLAGS),
GATE(SCLK_MAC_TX, "sclk_mac_tx", "sclk_gmac_pre", 0,
RK2928_CLKGATE_CON(5), 6, GFLAGS),
COMPOSITE(SCLK_MAC_PHY, "sclk_macphy", mux_sclk_macphy_p, 0,
RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, 8, 2, DFLAGS,
RK2928_CLKGATE_CON(5), 7, GFLAGS),
COMPOSITE(SCLK_MAC_OUT, "sclk_gmac_out", mux_pll_src_2plls_p, 0,
RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(2), 2, GFLAGS),
/*
* Clock-Architecture Diagram 3
*/
/* PD_VOP */
GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),
GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 11, GFLAGS),
GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),
GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS),
GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),
GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS),
GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(13), 10, GFLAGS),
GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),
GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),
GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS),
GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS),
GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS),
GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),
GATE(HCLK_HDCP_MMU, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),
GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),
GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),
GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),
/* PD_PERI */
GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 0, GFLAGS),
GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(11), 4, GFLAGS),
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 0, GFLAGS),
GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 1, GFLAGS),
GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS),
GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS),
GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS),
GATE(0, "hclk_host0_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 7, GFLAGS),
GATE(HCLK_HOST1, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS),
GATE(0, "hclk_host1_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 9, GFLAGS),
GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS),
GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS),
GATE(0, "hclk_otg_pmu", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 13, GFLAGS),
GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS),
GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS),
GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS),
GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS),
/* PD_GPU */
GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
/* PD_BUS */
GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
GATE(0, "aclk_initmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
GATE(0, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
GATE(HCLK_TSP, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS),
GATE(HCLK_M_CRYPTO, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
GATE(HCLK_S_CRYPTO, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS),
GATE(PCLK_EFUSE_1024, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
GATE(PCLK_EFUSE_256, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS),
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 4, GFLAGS),
GATE(0, "pclk_stimer", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 9, GFLAGS),
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 10, GFLAGS),
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 11, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 13, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 14, GFLAGS),
GATE(PCLK_TSADC, "pclk_tsadc", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 15, GFLAGS),
GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 0, GFLAGS),
GATE(0, "pclk_cru", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),
GATE(0, "pclk_sim", "pclk_cpu", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),
GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),
GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS),
GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 4, GFLAGS),
GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS),
GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 6, GFLAGS),
GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),
GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 5, GFLAGS),
GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS),
GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 7, GFLAGS),
/* PD_MMC */
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0),
MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1),
MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 0),
MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1),
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 0),
};
static const char *const rk3228_critical_clocks[] __initconst = {
"aclk_cpu",
"pclk_cpu",
"hclk_cpu",
"aclk_peri",
"hclk_peri",
"pclk_peri",
"aclk_rga_noc",
"aclk_iep_noc",
"aclk_vop_noc",
"aclk_hdcp_noc",
"hclk_vio_ahb_arbi",
"hclk_vio_noc",
"hclk_vop_noc",
"hclk_host0_arb",
"hclk_host1_arb",
"hclk_host2_arb",
"hclk_otg_pmu",
"aclk_gpu_noc",
"sclk_initmem_mbist",
"aclk_initmem",
"hclk_rom",
"pclk_ddrupctl",
"pclk_ddrmon",
"pclk_msch_noc",
"pclk_stimer",
"pclk_ddrphy",
"pclk_acodecphy",
"pclk_phy_noc",
"aclk_vpu_noc",
"aclk_rkvdec_noc",
"hclk_vpu_noc",
"hclk_rkvdec_noc",
};
static void __init rk3228_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru region\n", __func__);
return;
}
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
if (IS_ERR(ctx)) {
pr_err("%s: rockchip clk init failed\n", __func__);
iounmap(reg_base);
return;
}
rockchip_clk_register_plls(ctx, rk3228_pll_clks,
ARRAY_SIZE(rk3228_pll_clks),
RK3228_GRF_SOC_STATUS0);
rockchip_clk_register_branches(ctx, rk3228_clk_branches,
ARRAY_SIZE(rk3228_clk_branches));
rockchip_clk_protect_critical(rk3228_critical_clocks,
ARRAY_SIZE(rk3228_critical_clocks));
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
&rk3228_cpuclk_data, rk3228_cpuclk_rates,
ARRAY_SIZE(rk3228_cpuclk_rates));
rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
rockchip_register_restart_notifier(ctx, RK3228_GLB_SRST_FST, NULL);
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init);
| linux-master | drivers/clk/rockchip/clk-rk3228.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
* Author: Elaine <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rk3328-cru.h>
#include "clk.h"
#define RK3328_GRF_SOC_CON4 0x410
#define RK3328_GRF_SOC_STATUS0 0x480
#define RK3328_GRF_MAC_CON1 0x904
#define RK3328_GRF_MAC_CON2 0x908
enum rk3328_plls {
apll, dpll, cpll, gpll, npll,
};
static struct rockchip_pll_rate_table rk3328_pll_rates[] = {
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
{ /* sentinel */ },
};
static struct rockchip_pll_rate_table rk3328_pll_frac_rates[] = {
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134218),
/* vco = 1016064000 */
RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671089),
/* vco = 983040000 */
RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671089),
/* vco = 983040000 */
RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671089),
/* vco = 860156000 */
RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797895),
/* vco = 903168000 */
RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066330),
/* vco = 819200000 */
{ /* sentinel */ },
};
#define RK3328_DIV_ACLKM_MASK 0x7
#define RK3328_DIV_ACLKM_SHIFT 4
#define RK3328_DIV_PCLK_DBG_MASK 0xf
#define RK3328_DIV_PCLK_DBG_SHIFT 0
#define RK3328_CLKSEL1(_aclk_core, _pclk_dbg) \
{ \
.reg = RK3328_CLKSEL_CON(1), \
.val = HIWORD_UPDATE(_aclk_core, RK3328_DIV_ACLKM_MASK, \
RK3328_DIV_ACLKM_SHIFT) | \
HIWORD_UPDATE(_pclk_dbg, RK3328_DIV_PCLK_DBG_MASK, \
RK3328_DIV_PCLK_DBG_SHIFT), \
}
#define RK3328_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
{ \
.prate = _prate, \
.divs = { \
RK3328_CLKSEL1(_aclk_core, _pclk_dbg), \
}, \
}
static struct rockchip_cpuclk_rate_table rk3328_cpuclk_rates[] __initdata = {
RK3328_CPUCLK_RATE(1800000000, 1, 7),
RK3328_CPUCLK_RATE(1704000000, 1, 7),
RK3328_CPUCLK_RATE(1608000000, 1, 7),
RK3328_CPUCLK_RATE(1512000000, 1, 7),
RK3328_CPUCLK_RATE(1488000000, 1, 5),
RK3328_CPUCLK_RATE(1416000000, 1, 5),
RK3328_CPUCLK_RATE(1392000000, 1, 5),
RK3328_CPUCLK_RATE(1296000000, 1, 5),
RK3328_CPUCLK_RATE(1200000000, 1, 5),
RK3328_CPUCLK_RATE(1104000000, 1, 5),
RK3328_CPUCLK_RATE(1008000000, 1, 5),
RK3328_CPUCLK_RATE(912000000, 1, 5),
RK3328_CPUCLK_RATE(816000000, 1, 3),
RK3328_CPUCLK_RATE(696000000, 1, 3),
RK3328_CPUCLK_RATE(600000000, 1, 3),
RK3328_CPUCLK_RATE(408000000, 1, 1),
RK3328_CPUCLK_RATE(312000000, 1, 1),
RK3328_CPUCLK_RATE(216000000, 1, 1),
RK3328_CPUCLK_RATE(96000000, 1, 1),
};
static const struct rockchip_cpuclk_reg_data rk3328_cpuclk_data = {
.core_reg[0] = RK3328_CLKSEL_CON(0),
.div_core_shift[0] = 0,
.div_core_mask[0] = 0x1f,
.num_cores = 1,
.mux_core_alt = 1,
.mux_core_main = 3,
.mux_core_shift = 6,
.mux_core_mask = 0x3,
};
PNAME(mux_pll_p) = { "xin24m" };
PNAME(mux_2plls_p) = { "cpll", "gpll" };
PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
PNAME(mux_cpll_gpll_apll_p) = { "cpll", "gpll", "apll" };
PNAME(mux_2plls_xin24m_p) = { "cpll", "gpll", "xin24m" };
PNAME(mux_2plls_hdmiphy_p) = { "cpll", "gpll",
"dummy_hdmiphy" };
PNAME(mux_4plls_p) = { "cpll", "gpll",
"dummy_hdmiphy",
"usb480m" };
PNAME(mux_2plls_u480m_p) = { "cpll", "gpll",
"usb480m" };
PNAME(mux_2plls_24m_u480m_p) = { "cpll", "gpll",
"xin24m", "usb480m" };
PNAME(mux_ddrphy_p) = { "dpll", "apll", "cpll" };
PNAME(mux_armclk_p) = { "apll_core",
"gpll_core",
"dpll_core",
"npll_core"};
PNAME(mux_hdmiphy_p) = { "hdmi_phy", "xin24m" };
PNAME(mux_usb480m_p) = { "usb480m_phy",
"xin24m" };
PNAME(mux_i2s0_p) = { "clk_i2s0_div",
"clk_i2s0_frac",
"xin12m",
"xin12m" };
PNAME(mux_i2s1_p) = { "clk_i2s1_div",
"clk_i2s1_frac",
"clkin_i2s1",
"xin12m" };
PNAME(mux_i2s2_p) = { "clk_i2s2_div",
"clk_i2s2_frac",
"clkin_i2s2",
"xin12m" };
PNAME(mux_i2s1out_p) = { "clk_i2s1", "xin12m"};
PNAME(mux_i2s2out_p) = { "clk_i2s2", "xin12m" };
PNAME(mux_spdif_p) = { "clk_spdif_div",
"clk_spdif_frac",
"xin12m",
"xin12m" };
PNAME(mux_uart0_p) = { "clk_uart0_div",
"clk_uart0_frac",
"xin24m" };
PNAME(mux_uart1_p) = { "clk_uart1_div",
"clk_uart1_frac",
"xin24m" };
PNAME(mux_uart2_p) = { "clk_uart2_div",
"clk_uart2_frac",
"xin24m" };
PNAME(mux_sclk_cif_p) = { "clk_cif_src",
"xin24m" };
PNAME(mux_dclk_lcdc_p) = { "hdmiphy",
"dclk_lcdc_src" };
PNAME(mux_aclk_peri_pre_p) = { "cpll_peri",
"gpll_peri",
"hdmiphy_peri" };
PNAME(mux_ref_usb3otg_src_p) = { "xin24m",
"clk_usb3otg_ref" };
PNAME(mux_xin24m_32k_p) = { "xin24m",
"clk_rtc32k" };
PNAME(mux_mac2io_src_p) = { "clk_mac2io_src",
"gmac_clkin" };
PNAME(mux_mac2phy_src_p) = { "clk_mac2phy_src",
"phy_50m_out" };
PNAME(mux_mac2io_ext_p) = { "clk_mac2io",
"gmac_clkin" };
static struct rockchip_pll_clock rk3328_pll_clks[] __initdata = {
[apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
0, RK3328_PLL_CON(0),
RK3328_MODE_CON, 0, 4, 0, rk3328_pll_frac_rates),
[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
0, RK3328_PLL_CON(8),
RK3328_MODE_CON, 4, 3, 0, NULL),
[cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
0, RK3328_PLL_CON(16),
RK3328_MODE_CON, 8, 2, 0, rk3328_pll_rates),
[gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
0, RK3328_PLL_CON(24),
RK3328_MODE_CON, 12, 1, 0, rk3328_pll_frac_rates),
[npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
0, RK3328_PLL_CON(40),
RK3328_MODE_CON, 1, 0, 0, rk3328_pll_rates),
};
#define MFLAGS CLK_MUX_HIWORD_MASK
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
static struct rockchip_clk_branch rk3328_i2s0_fracmux __initdata =
MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(6), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3328_i2s1_fracmux __initdata =
MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(8), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3328_i2s2_fracmux __initdata =
MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(10), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3328_spdif_fracmux __initdata =
MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(12), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3328_uart0_fracmux __initdata =
MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(14), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3328_uart1_fracmux __initdata =
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(16), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3328_uart2_fracmux __initdata =
MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(18), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
/*
* Clock-Architecture Diagram 1
*/
DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
RK3328_CLKSEL_CON(2), 8, 5, DFLAGS),
COMPOSITE(SCLK_RTC32K, "clk_rtc32k", mux_2plls_xin24m_p, 0,
RK3328_CLKSEL_CON(38), 14, 2, MFLAGS, 0, 14, DFLAGS,
RK3328_CLKGATE_CON(0), 11, GFLAGS),
/* PD_MISC */
MUX(HDMIPHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
RK3328_MISC_CON, 13, 1, MFLAGS),
MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
RK3328_MISC_CON, 15, 1, MFLAGS),
/*
* Clock-Architecture Diagram 2
*/
/* PD_CORE */
GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(0), 0, GFLAGS),
GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(0), 2, GFLAGS),
GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(0), 1, GFLAGS),
GATE(0, "npll_core", "npll", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(0), 12, GFLAGS),
COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
RK3328_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3328_CLKGATE_CON(7), 0, GFLAGS),
COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
RK3328_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3328_CLKGATE_CON(7), 1, GFLAGS),
GATE(0, "aclk_core_niu", "aclk_core", 0,
RK3328_CLKGATE_CON(13), 0, GFLAGS),
GATE(0, "aclk_gic400", "aclk_core", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(13), 1, GFLAGS),
GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(7), 2, GFLAGS),
/* PD_GPU */
COMPOSITE(0, "aclk_gpu_pre", mux_4plls_p, 0,
RK3328_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3328_CLKGATE_CON(6), 6, GFLAGS),
GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", CLK_SET_RATE_PARENT,
RK3328_CLKGATE_CON(14), 0, GFLAGS),
GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", 0,
RK3328_CLKGATE_CON(14), 1, GFLAGS),
/* PD_DDR */
COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED,
RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK3328_CLKGATE_CON(0), 4, GFLAGS),
GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(18), 6, GFLAGS),
GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(18), 5, GFLAGS),
GATE(0, "aclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(18), 4, GFLAGS),
GATE(0, "clk_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(0), 6, GFLAGS),
COMPOSITE(PCLK_DDR, "pclk_ddr", mux_2plls_hdmiphy_p, 0,
RK3328_CLKSEL_CON(4), 13, 2, MFLAGS, 8, 3, DFLAGS,
RK3328_CLKGATE_CON(7), 4, GFLAGS),
GATE(0, "pclk_ddrupctl", "pclk_ddr", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(18), 1, GFLAGS),
GATE(0, "pclk_ddr_msch", "pclk_ddr", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(18), 2, GFLAGS),
GATE(0, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(18), 3, GFLAGS),
GATE(0, "pclk_ddrstdby", "pclk_ddr", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(18), 7, GFLAGS),
GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(18), 9, GFLAGS),
/*
* Clock-Architecture Diagram 3
*/
/* PD_BUS */
COMPOSITE(ACLK_BUS_PRE, "aclk_bus_pre", mux_2plls_hdmiphy_p, 0,
RK3328_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS,
RK3328_CLKGATE_CON(8), 0, GFLAGS),
COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_pre", 0,
RK3328_CLKSEL_CON(1), 8, 2, DFLAGS,
RK3328_CLKGATE_CON(8), 1, GFLAGS),
COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", 0,
RK3328_CLKSEL_CON(1), 12, 3, DFLAGS,
RK3328_CLKGATE_CON(8), 2, GFLAGS),
GATE(0, "pclk_bus", "pclk_bus_pre", 0,
RK3328_CLKGATE_CON(8), 3, GFLAGS),
GATE(0, "pclk_phy_pre", "pclk_bus_pre", 0,
RK3328_CLKGATE_CON(8), 4, GFLAGS),
COMPOSITE(SCLK_TSP, "clk_tsp", mux_2plls_p, 0,
RK3328_CLKSEL_CON(21), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3328_CLKGATE_CON(2), 5, GFLAGS),
GATE(0, "clk_hsadc_tsp", "ext_gpio3a2", 0,
RK3328_CLKGATE_CON(17), 13, GFLAGS),
/* PD_I2S */
COMPOSITE(0, "clk_i2s0_div", mux_2plls_p, 0,
RK3328_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK3328_CLKGATE_CON(1), 1, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(7), 0,
RK3328_CLKGATE_CON(1), 2, GFLAGS,
&rk3328_i2s0_fracmux),
GATE(SCLK_I2S0, "clk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
RK3328_CLKGATE_CON(1), 3, GFLAGS),
COMPOSITE(0, "clk_i2s1_div", mux_2plls_p, 0,
RK3328_CLKSEL_CON(8), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK3328_CLKGATE_CON(1), 4, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(9), 0,
RK3328_CLKGATE_CON(1), 5, GFLAGS,
&rk3328_i2s1_fracmux),
GATE(SCLK_I2S1, "clk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
RK3328_CLKGATE_CON(1), 6, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S1_OUT, "i2s1_out", mux_i2s1out_p, 0,
RK3328_CLKSEL_CON(8), 12, 1, MFLAGS,
RK3328_CLKGATE_CON(1), 7, GFLAGS),
COMPOSITE(0, "clk_i2s2_div", mux_2plls_p, 0,
RK3328_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK3328_CLKGATE_CON(1), 8, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(11), 0,
RK3328_CLKGATE_CON(1), 9, GFLAGS,
&rk3328_i2s2_fracmux),
GATE(SCLK_I2S2, "clk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
RK3328_CLKGATE_CON(1), 10, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S2_OUT, "i2s2_out", mux_i2s2out_p, 0,
RK3328_CLKSEL_CON(10), 12, 1, MFLAGS,
RK3328_CLKGATE_CON(1), 11, GFLAGS),
COMPOSITE(0, "clk_spdif_div", mux_2plls_p, 0,
RK3328_CLKSEL_CON(12), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK3328_CLKGATE_CON(1), 12, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(13), 0,
RK3328_CLKGATE_CON(1), 13, GFLAGS,
&rk3328_spdif_fracmux),
/* PD_UART */
COMPOSITE(0, "clk_uart0_div", mux_2plls_u480m_p, 0,
RK3328_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
RK3328_CLKGATE_CON(1), 14, GFLAGS),
COMPOSITE(0, "clk_uart1_div", mux_2plls_u480m_p, 0,
RK3328_CLKSEL_CON(16), 12, 2, MFLAGS, 0, 7, DFLAGS,
RK3328_CLKGATE_CON(2), 0, GFLAGS),
COMPOSITE(0, "clk_uart2_div", mux_2plls_u480m_p, 0,
RK3328_CLKSEL_CON(18), 12, 2, MFLAGS, 0, 7, DFLAGS,
RK3328_CLKGATE_CON(2), 2, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(15), 0,
RK3328_CLKGATE_CON(1), 15, GFLAGS,
&rk3328_uart0_fracmux),
COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(17), 0,
RK3328_CLKGATE_CON(2), 1, GFLAGS,
&rk3328_uart1_fracmux),
COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(19), 0,
RK3328_CLKGATE_CON(2), 3, GFLAGS,
&rk3328_uart2_fracmux),
/*
* Clock-Architecture Diagram 4
*/
COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_2plls_p, 0,
RK3328_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3328_CLKGATE_CON(2), 9, GFLAGS),
COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_2plls_p, 0,
RK3328_CLKSEL_CON(34), 15, 1, MFLAGS, 8, 7, DFLAGS,
RK3328_CLKGATE_CON(2), 10, GFLAGS),
COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_2plls_p, 0,
RK3328_CLKSEL_CON(35), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3328_CLKGATE_CON(2), 11, GFLAGS),
COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_2plls_p, 0,
RK3328_CLKSEL_CON(35), 15, 1, MFLAGS, 8, 7, DFLAGS,
RK3328_CLKGATE_CON(2), 12, GFLAGS),
COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_2plls_p, 0,
RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3328_CLKGATE_CON(2), 4, GFLAGS),
COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "clk_24m", 0,
RK3328_CLKSEL_CON(22), 0, 10, DFLAGS,
RK3328_CLKGATE_CON(2), 6, GFLAGS),
COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "clk_24m", 0,
RK3328_CLKSEL_CON(23), 0, 10, DFLAGS,
RK3328_CLKGATE_CON(2), 14, GFLAGS),
COMPOSITE(SCLK_SPI, "clk_spi", mux_2plls_p, 0,
RK3328_CLKSEL_CON(24), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3328_CLKGATE_CON(2), 7, GFLAGS),
COMPOSITE(SCLK_PWM, "clk_pwm", mux_2plls_p, 0,
RK3328_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 7, DFLAGS,
RK3328_CLKGATE_CON(2), 8, GFLAGS),
COMPOSITE(SCLK_OTP, "clk_otp", mux_2plls_xin24m_p, 0,
RK3328_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3328_CLKGATE_CON(3), 8, GFLAGS),
COMPOSITE(SCLK_EFUSE, "clk_efuse", mux_2plls_xin24m_p, 0,
RK3328_CLKSEL_CON(5), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3328_CLKGATE_CON(2), 13, GFLAGS),
COMPOSITE(SCLK_PDM, "clk_pdm", mux_cpll_gpll_apll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3328_CLKGATE_CON(2), 15, GFLAGS),
GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
RK3328_CLKGATE_CON(8), 5, GFLAGS),
GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
RK3328_CLKGATE_CON(8), 6, GFLAGS),
GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
RK3328_CLKGATE_CON(8), 7, GFLAGS),
GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
RK3328_CLKGATE_CON(8), 8, GFLAGS),
GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
RK3328_CLKGATE_CON(8), 9, GFLAGS),
GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
RK3328_CLKGATE_CON(8), 10, GFLAGS),
COMPOSITE(SCLK_WIFI, "clk_wifi", mux_2plls_u480m_p, 0,
RK3328_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3328_CLKGATE_CON(0), 10, GFLAGS),
/*
* Clock-Architecture Diagram 5
*/
/* PD_VIDEO */
COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", mux_4plls_p, 0,
RK3328_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3328_CLKGATE_CON(6), 0, GFLAGS),
FACTOR_GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4,
RK3328_CLKGATE_CON(11), 0, GFLAGS),
GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", CLK_SET_RATE_PARENT,
RK3328_CLKGATE_CON(24), 0, GFLAGS),
GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", CLK_SET_RATE_PARENT,
RK3328_CLKGATE_CON(24), 1, GFLAGS),
GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", 0,
RK3328_CLKGATE_CON(24), 2, GFLAGS),
GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", 0,
RK3328_CLKGATE_CON(24), 3, GFLAGS),
COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_4plls_p, 0,
RK3328_CLKSEL_CON(48), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3328_CLKGATE_CON(6), 1, GFLAGS),
COMPOSITE(SCLK_VDEC_CORE, "sclk_vdec_core", mux_4plls_p, 0,
RK3328_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3328_CLKGATE_CON(6), 2, GFLAGS),
COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", mux_4plls_p, 0,
RK3328_CLKSEL_CON(50), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3328_CLKGATE_CON(6), 5, GFLAGS),
FACTOR_GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4,
RK3328_CLKGATE_CON(11), 8, GFLAGS),
GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", CLK_SET_RATE_PARENT,
RK3328_CLKGATE_CON(23), 0, GFLAGS),
GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", CLK_SET_RATE_PARENT,
RK3328_CLKGATE_CON(23), 1, GFLAGS),
GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", 0,
RK3328_CLKGATE_CON(23), 2, GFLAGS),
GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", 0,
RK3328_CLKGATE_CON(23), 3, GFLAGS),
COMPOSITE(ACLK_RKVENC, "aclk_rkvenc", mux_4plls_p, 0,
RK3328_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3328_CLKGATE_CON(6), 3, GFLAGS),
FACTOR_GATE(HCLK_RKVENC, "hclk_rkvenc", "aclk_rkvenc", 0, 1, 4,
RK3328_CLKGATE_CON(11), 4, GFLAGS),
GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc", 0,
RK3328_CLKGATE_CON(25), 0, GFLAGS),
GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 0,
RK3328_CLKGATE_CON(25), 1, GFLAGS),
GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0,
RK3328_CLKGATE_CON(25), 2, GFLAGS),
GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 0,
RK3328_CLKGATE_CON(25), 3, GFLAGS),
GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 0,
RK3328_CLKGATE_CON(25), 4, GFLAGS),
GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 0,
RK3328_CLKGATE_CON(25), 5, GFLAGS),
GATE(ACLK_AXISRAM, "aclk_axisram", "aclk_rkvenc", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(25), 6, GFLAGS),
COMPOSITE(SCLK_VENC_CORE, "sclk_venc_core", mux_4plls_p, 0,
RK3328_CLKSEL_CON(51), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3328_CLKGATE_CON(6), 4, GFLAGS),
COMPOSITE(SCLK_VENC_DSP, "sclk_venc_dsp", mux_4plls_p, 0,
RK3328_CLKSEL_CON(52), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3328_CLKGATE_CON(6), 7, GFLAGS),
/*
* Clock-Architecture Diagram 6
*/
/* PD_VIO */
COMPOSITE(ACLK_VIO_PRE, "aclk_vio_pre", mux_4plls_p, 0,
RK3328_CLKSEL_CON(37), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3328_CLKGATE_CON(5), 2, GFLAGS),
DIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_vio_pre", 0,
RK3328_CLKSEL_CON(37), 8, 5, DFLAGS),
COMPOSITE(ACLK_RGA_PRE, "aclk_rga_pre", mux_4plls_p, 0,
RK3328_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3328_CLKGATE_CON(5), 0, GFLAGS),
COMPOSITE(SCLK_RGA, "clk_rga", mux_4plls_p, 0,
RK3328_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3328_CLKGATE_CON(5), 1, GFLAGS),
COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_4plls_p, 0,
RK3328_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3328_CLKGATE_CON(5), 5, GFLAGS),
GATE(SCLK_HDMI_SFC, "sclk_hdmi_sfc", "xin24m", 0,
RK3328_CLKGATE_CON(5), 4, GFLAGS),
COMPOSITE_NODIV(0, "clk_cif_src", mux_2plls_p, 0,
RK3328_CLKSEL_CON(42), 7, 1, MFLAGS,
RK3328_CLKGATE_CON(5), 3, GFLAGS),
COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cif_out", mux_sclk_cif_p, CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(42), 5, 1, MFLAGS, 0, 5, DFLAGS),
COMPOSITE(DCLK_LCDC_SRC, "dclk_lcdc_src", mux_gpll_cpll_p, 0,
RK3328_CLKSEL_CON(40), 0, 1, MFLAGS, 8, 8, DFLAGS,
RK3328_CLKGATE_CON(5), 6, GFLAGS),
DIV(DCLK_HDMIPHY, "dclk_hdmiphy", "dclk_lcdc_src", 0,
RK3328_CLKSEL_CON(40), 3, 3, DFLAGS),
MUX(DCLK_LCDC, "dclk_lcdc", mux_dclk_lcdc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3328_CLKSEL_CON(40), 1, 1, MFLAGS),
/*
* Clock-Architecture Diagram 7
*/
/* PD_PERI */
GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(4), 0, GFLAGS),
GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(4), 1, GFLAGS),
GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(4), 2, GFLAGS),
COMPOSITE_NOGATE(ACLK_PERI_PRE, "aclk_peri_pre", mux_aclk_peri_pre_p, 0,
RK3328_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS),
COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED,
RK3328_CLKSEL_CON(29), 0, 2, DFLAGS,
RK3328_CLKGATE_CON(10), 2, GFLAGS),
COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED,
RK3328_CLKSEL_CON(29), 4, 3, DFLAGS,
RK3328_CLKGATE_CON(10), 1, GFLAGS),
GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT,
RK3328_CLKGATE_CON(10), 0, GFLAGS),
COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_2plls_24m_u480m_p, 0,
RK3328_CLKSEL_CON(30), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3328_CLKGATE_CON(4), 3, GFLAGS),
COMPOSITE(SCLK_SDIO, "clk_sdio", mux_2plls_24m_u480m_p, 0,
RK3328_CLKSEL_CON(31), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3328_CLKGATE_CON(4), 4, GFLAGS),
COMPOSITE(SCLK_EMMC, "clk_emmc", mux_2plls_24m_u480m_p, 0,
RK3328_CLKSEL_CON(32), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3328_CLKGATE_CON(4), 5, GFLAGS),
COMPOSITE(SCLK_SDMMC_EXT, "clk_sdmmc_ext", mux_2plls_24m_u480m_p, 0,
RK3328_CLKSEL_CON(43), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3328_CLKGATE_CON(4), 10, GFLAGS),
COMPOSITE(SCLK_REF_USB3OTG_SRC, "clk_ref_usb3otg_src", mux_2plls_p, 0,
RK3328_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3328_CLKGATE_CON(4), 9, GFLAGS),
MUX(SCLK_REF_USB3OTG, "clk_ref_usb3otg", mux_ref_usb3otg_src_p, CLK_SET_RATE_PARENT,
RK3328_CLKSEL_CON(45), 8, 1, MFLAGS),
GATE(SCLK_USB3OTG_REF, "clk_usb3otg_ref", "xin24m", 0,
RK3328_CLKGATE_CON(4), 7, GFLAGS),
COMPOSITE(SCLK_USB3OTG_SUSPEND, "clk_usb3otg_suspend", mux_xin24m_32k_p, 0,
RK3328_CLKSEL_CON(33), 15, 1, MFLAGS, 0, 10, DFLAGS,
RK3328_CLKGATE_CON(4), 8, GFLAGS),
/*
* Clock-Architecture Diagram 8
*/
/* PD_GMAC */
COMPOSITE(ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_p, 0,
RK3328_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3328_CLKGATE_CON(3), 2, GFLAGS),
COMPOSITE_NOMUX(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 0,
RK3328_CLKSEL_CON(25), 8, 3, DFLAGS,
RK3328_CLKGATE_CON(9), 0, GFLAGS),
COMPOSITE(SCLK_MAC2IO_SRC, "clk_mac2io_src", mux_2plls_p, 0,
RK3328_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3328_CLKGATE_CON(3), 1, GFLAGS),
GATE(SCLK_MAC2IO_REF, "clk_mac2io_ref", "clk_mac2io", 0,
RK3328_CLKGATE_CON(9), 7, GFLAGS),
GATE(SCLK_MAC2IO_RX, "clk_mac2io_rx", "clk_mac2io", 0,
RK3328_CLKGATE_CON(9), 4, GFLAGS),
GATE(SCLK_MAC2IO_TX, "clk_mac2io_tx", "clk_mac2io", 0,
RK3328_CLKGATE_CON(9), 5, GFLAGS),
GATE(SCLK_MAC2IO_REFOUT, "clk_mac2io_refout", "clk_mac2io", 0,
RK3328_CLKGATE_CON(9), 6, GFLAGS),
COMPOSITE(SCLK_MAC2IO_OUT, "clk_mac2io_out", mux_2plls_p, 0,
RK3328_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3328_CLKGATE_CON(3), 5, GFLAGS),
MUXGRF(SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_p, CLK_SET_RATE_NO_REPARENT,
RK3328_GRF_MAC_CON1, 10, 1, MFLAGS),
MUXGRF(SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_p, CLK_SET_RATE_NO_REPARENT,
RK3328_GRF_SOC_CON4, 14, 1, MFLAGS),
COMPOSITE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", mux_2plls_p, 0,
RK3328_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3328_CLKGATE_CON(3), 0, GFLAGS),
GATE(SCLK_MAC2PHY_REF, "clk_mac2phy_ref", "clk_mac2phy", 0,
RK3328_CLKGATE_CON(9), 3, GFLAGS),
GATE(SCLK_MAC2PHY_RXTX, "clk_mac2phy_rxtx", "clk_mac2phy", 0,
RK3328_CLKGATE_CON(9), 1, GFLAGS),
COMPOSITE_NOMUX(SCLK_MAC2PHY_OUT, "clk_mac2phy_out", "clk_mac2phy", 0,
RK3328_CLKSEL_CON(26), 8, 2, DFLAGS,
RK3328_CLKGATE_CON(9), 2, GFLAGS),
MUXGRF(SCLK_MAC2PHY, "clk_mac2phy", mux_mac2phy_src_p, CLK_SET_RATE_NO_REPARENT,
RK3328_GRF_MAC_CON2, 10, 1, MFLAGS),
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
/*
* Clock-Architecture Diagram 9
*/
/* PD_VOP */
GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3328_CLKGATE_CON(21), 10, GFLAGS),
GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0, RK3328_CLKGATE_CON(22), 3, GFLAGS),
GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK3328_CLKGATE_CON(21), 2, GFLAGS),
GATE(0, "aclk_vop_niu", "aclk_vop_pre", 0, RK3328_CLKGATE_CON(21), 4, GFLAGS),
GATE(ACLK_IEP, "aclk_iep", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 6, GFLAGS),
GATE(ACLK_CIF, "aclk_cif", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 8, GFLAGS),
GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 15, GFLAGS),
GATE(0, "aclk_vio_niu", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 2, GFLAGS),
GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 3, GFLAGS),
GATE(0, "hclk_vop_niu", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 5, GFLAGS),
GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 7, GFLAGS),
GATE(HCLK_CIF, "hclk_cif", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 9, GFLAGS),
GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 11, GFLAGS),
GATE(0, "hclk_ahb1tom", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 12, GFLAGS),
GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 13, GFLAGS),
GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 14, GFLAGS),
GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 0, GFLAGS),
GATE(0, "hclk_vio_niu", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 1, GFLAGS),
GATE(PCLK_HDMI, "pclk_hdmi", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 4, GFLAGS),
GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 5, GFLAGS),
/* PD_PERI */
GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 11, GFLAGS),
GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 14, GFLAGS),
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 0, GFLAGS),
GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 1, GFLAGS),
GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 2, GFLAGS),
GATE(HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 15, GFLAGS),
GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 6, GFLAGS),
GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 7, GFLAGS),
GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 8, GFLAGS),
GATE(HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 9, GFLAGS),
GATE(0, "hclk_peri_niu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 12, GFLAGS),
GATE(0, "pclk_peri_niu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 13, GFLAGS),
/* PD_GMAC */
GATE(ACLK_MAC2PHY, "aclk_mac2phy", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 0, GFLAGS),
GATE(ACLK_MAC2IO, "aclk_mac2io", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 2, GFLAGS),
GATE(0, "aclk_gmac_niu", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 4, GFLAGS),
GATE(PCLK_MAC2PHY, "pclk_mac2phy", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 1, GFLAGS),
GATE(PCLK_MAC2IO, "pclk_mac2io", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 3, GFLAGS),
GATE(0, "pclk_gmac_niu", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 5, GFLAGS),
/* PD_BUS */
GATE(0, "aclk_bus_niu", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 12, GFLAGS),
GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 11, GFLAGS),
GATE(ACLK_TSP, "aclk_tsp", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 12, GFLAGS),
GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 0, GFLAGS),
GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 1, GFLAGS),
GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 2, GFLAGS),
GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 3, GFLAGS),
GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 4, GFLAGS),
GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 5, GFLAGS),
GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 6, GFLAGS),
GATE(HCLK_TSP, "hclk_tsp", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 11, GFLAGS),
GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 7, GFLAGS),
GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 8, GFLAGS),
GATE(0, "hclk_bus_niu", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 13, GFLAGS),
GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(28), 0, GFLAGS),
GATE(0, "pclk_bus_niu", "pclk_bus", 0, RK3328_CLKGATE_CON(15), 14, GFLAGS),
GATE(0, "pclk_efuse", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 9, GFLAGS),
GATE(0, "pclk_otp", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 4, GFLAGS),
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3328_CLKGATE_CON(15), 10, GFLAGS),
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 0, GFLAGS),
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 1, GFLAGS),
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 2, GFLAGS),
GATE(PCLK_TIMER, "pclk_timer0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 3, GFLAGS),
GATE(0, "pclk_stimer", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 4, GFLAGS),
GATE(PCLK_SPI, "pclk_spi", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 5, GFLAGS),
GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 6, GFLAGS),
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 7, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 8, GFLAGS),
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 9, GFLAGS),
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 10, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 11, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 12, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 13, GFLAGS),
GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 14, GFLAGS),
GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 15, GFLAGS),
GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 0, GFLAGS),
GATE(0, "pclk_cru", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 4, GFLAGS),
GATE(0, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 6, GFLAGS),
GATE(0, "pclk_sim", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 10, GFLAGS),
GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3328_CLKGATE_CON(17), 15, GFLAGS),
GATE(0, "pclk_pmu", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 3, GFLAGS),
/* Watchdog pclk is controlled from the secure GRF */
SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_bus"),
GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 1, GFLAGS),
GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 2, GFLAGS),
GATE(PCLK_USB3_GRF, "pclk_usb3_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 2, GFLAGS),
GATE(PCLK_USB2_GRF, "pclk_usb2_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 14, GFLAGS),
GATE(0, "pclk_ddrphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 13, GFLAGS),
GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(17), 5, GFLAGS),
GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 7, GFLAGS),
GATE(0, "pclk_vdacphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 8, GFLAGS),
GATE(0, "pclk_phy_niu", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(15), 15, GFLAGS),
/* PD_MMC */
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc",
RK3328_SDMMC_CON0, 1),
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc",
RK3328_SDMMC_CON1, 1),
MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio",
RK3328_SDIO_CON0, 1),
MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio",
RK3328_SDIO_CON1, 1),
MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc",
RK3328_EMMC_CON0, 1),
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc",
RK3328_EMMC_CON1, 1),
MMC(SCLK_SDMMC_EXT_DRV, "sdmmc_ext_drv", "clk_sdmmc_ext",
RK3328_SDMMC_EXT_CON0, 1),
MMC(SCLK_SDMMC_EXT_SAMPLE, "sdmmc_ext_sample", "clk_sdmmc_ext",
RK3328_SDMMC_EXT_CON1, 1),
};
static const char *const rk3328_critical_clocks[] __initconst = {
"aclk_bus",
"aclk_bus_niu",
"pclk_bus",
"pclk_bus_niu",
"hclk_bus",
"hclk_bus_niu",
"aclk_peri",
"hclk_peri",
"hclk_peri_niu",
"pclk_peri",
"pclk_peri_niu",
"pclk_dbg",
"aclk_core_niu",
"aclk_gic400",
"aclk_intmem",
"hclk_rom",
"pclk_grf",
"pclk_cru",
"pclk_sgrf",
"pclk_timer0",
"clk_timer0",
"pclk_ddr_msch",
"pclk_ddr_mon",
"pclk_ddr_grf",
"clk_ddrupctl",
"clk_ddrmsch",
"hclk_ahb1tom",
"clk_jtag",
"pclk_ddrphy",
"pclk_pmu",
"hclk_otg_pmu",
"aclk_rga_niu",
"pclk_vio_h2p",
"hclk_vio_h2p",
"aclk_vio_niu",
"hclk_vio_niu",
"aclk_vop_niu",
"hclk_vop_niu",
"aclk_gpu_niu",
"aclk_rkvdec_niu",
"hclk_rkvdec_niu",
"aclk_vpu_niu",
"hclk_vpu_niu",
"aclk_rkvenc_niu",
"hclk_rkvenc_niu",
"aclk_gmac_niu",
"pclk_gmac_niu",
"pclk_phy_niu",
};
static void __init rk3328_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru region\n", __func__);
return;
}
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
if (IS_ERR(ctx)) {
pr_err("%s: rockchip clk init failed\n", __func__);
iounmap(reg_base);
return;
}
rockchip_clk_register_plls(ctx, rk3328_pll_clks,
ARRAY_SIZE(rk3328_pll_clks),
RK3328_GRF_SOC_STATUS0);
rockchip_clk_register_branches(ctx, rk3328_clk_branches,
ARRAY_SIZE(rk3328_clk_branches));
rockchip_clk_protect_critical(rk3328_critical_clocks,
ARRAY_SIZE(rk3328_critical_clocks));
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
&rk3328_cpuclk_data, rk3328_cpuclk_rates,
ARRAY_SIZE(rk3328_cpuclk_rates));
rockchip_register_softrst(np, 12, reg_base + RK3328_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
rockchip_register_restart_notifier(ctx, RK3328_GLB_SRST_FST, NULL);
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rk3328_cru, "rockchip,rk3328-cru", rk3328_clk_init);
| linux-master | drivers/clk/rockchip/clk-rk3328.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2017 Rockchip Electronics Co. Ltd.
* Author: Elaine <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rk3128-cru.h>
#include "clk.h"
#define RK3128_GRF_SOC_STATUS0 0x14c
enum rk3128_plls {
apll, dpll, cpll, gpll,
};
static struct rockchip_pll_rate_table rk3128_pll_rates[] = {
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
{ /* sentinel */ },
};
#define RK3128_DIV_CPU_MASK 0x1f
#define RK3128_DIV_CPU_SHIFT 8
#define RK3128_DIV_PERI_MASK 0xf
#define RK3128_DIV_PERI_SHIFT 0
#define RK3128_DIV_ACLK_MASK 0x7
#define RK3128_DIV_ACLK_SHIFT 4
#define RK3128_DIV_HCLK_MASK 0x3
#define RK3128_DIV_HCLK_SHIFT 8
#define RK3128_DIV_PCLK_MASK 0x7
#define RK3128_DIV_PCLK_SHIFT 12
#define RK3128_CLKSEL1(_core_aclk_div, _pclk_dbg_div) \
{ \
.reg = RK2928_CLKSEL_CON(1), \
.val = HIWORD_UPDATE(_pclk_dbg_div, RK3128_DIV_PERI_MASK, \
RK3128_DIV_PERI_SHIFT) | \
HIWORD_UPDATE(_core_aclk_div, RK3128_DIV_ACLK_MASK, \
RK3128_DIV_ACLK_SHIFT), \
}
#define RK3128_CPUCLK_RATE(_prate, _core_aclk_div, _pclk_dbg_div) \
{ \
.prate = _prate, \
.divs = { \
RK3128_CLKSEL1(_core_aclk_div, _pclk_dbg_div), \
}, \
}
static struct rockchip_cpuclk_rate_table rk3128_cpuclk_rates[] __initdata = {
RK3128_CPUCLK_RATE(1800000000, 1, 7),
RK3128_CPUCLK_RATE(1704000000, 1, 7),
RK3128_CPUCLK_RATE(1608000000, 1, 7),
RK3128_CPUCLK_RATE(1512000000, 1, 7),
RK3128_CPUCLK_RATE(1488000000, 1, 5),
RK3128_CPUCLK_RATE(1416000000, 1, 5),
RK3128_CPUCLK_RATE(1392000000, 1, 5),
RK3128_CPUCLK_RATE(1296000000, 1, 5),
RK3128_CPUCLK_RATE(1200000000, 1, 5),
RK3128_CPUCLK_RATE(1104000000, 1, 5),
RK3128_CPUCLK_RATE(1008000000, 1, 5),
RK3128_CPUCLK_RATE(912000000, 1, 5),
RK3128_CPUCLK_RATE(816000000, 1, 3),
RK3128_CPUCLK_RATE(696000000, 1, 3),
RK3128_CPUCLK_RATE(600000000, 1, 3),
RK3128_CPUCLK_RATE(408000000, 1, 1),
RK3128_CPUCLK_RATE(312000000, 1, 1),
RK3128_CPUCLK_RATE(216000000, 1, 1),
RK3128_CPUCLK_RATE(96000000, 1, 1),
};
static const struct rockchip_cpuclk_reg_data rk3128_cpuclk_data = {
.core_reg[0] = RK2928_CLKSEL_CON(0),
.div_core_shift[0] = 0,
.div_core_mask[0] = 0x1f,
.num_cores = 1,
.mux_core_alt = 1,
.mux_core_main = 0,
.mux_core_shift = 7,
.mux_core_mask = 0x1,
};
PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_div2_ddr" };
PNAME(mux_armclk_p) = { "apll_core", "gpll_div2_core" };
PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
PNAME(mux_aclk_cpu_src_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3" };
PNAME(mux_pll_src_5plls_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3", "usb480m" };
PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "gpll_div2", "usb480m" };
PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "gpll_div2" };
PNAME(mux_aclk_peri_src_p) = { "gpll_peri", "cpll_peri", "gpll_div2_peri", "gpll_div3_peri" };
PNAME(mux_mmc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" };
PNAME(mux_clk_cif_out_src_p) = { "clk_cif_src", "xin24m" };
PNAME(mux_sclk_vop_src_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3" };
PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" };
PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" };
PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" };
PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
PNAME(mux_sclk_gmac_p) = { "sclk_gmac_src", "gmac_clkin" };
PNAME(mux_sclk_sfc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" };
static struct rockchip_pll_clock rk3128_pll_clks[] __initdata = {
[apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
RK2928_MODE_CON, 0, 1, 0, rk3128_pll_rates),
[dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
RK2928_MODE_CON, 4, 0, 0, NULL),
[cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
RK2928_MODE_CON, 8, 2, 0, rk3128_pll_rates),
[gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
RK2928_MODE_CON, 12, 3, ROCKCHIP_PLL_SYNC_RATE, rk3128_pll_rates),
};
#define MFLAGS CLK_MUX_HIWORD_MASK
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
static struct rockchip_clk_branch rk3128_i2s0_fracmux __initdata =
MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(9), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3128_i2s1_fracmux __initdata =
MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3128_spdif_fracmux __initdata =
MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(6), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3128_uart0_fracmux __initdata =
MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3128_uart1_fracmux __initdata =
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3128_uart2_fracmux __initdata =
MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
static struct rockchip_clk_branch common_clk_branches[] __initdata = {
/*
* Clock-Architecture Diagram 1
*/
FACTOR(PLL_GPLL_DIV2, "gpll_div2", "gpll", 0, 1, 2),
FACTOR(PLL_GPLL_DIV3, "gpll_div3", "gpll", 0, 1, 3),
DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
/* PD_DDR */
GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 2, GFLAGS),
GATE(0, "gpll_div2_ddr", "gpll_div2", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 2, GFLAGS),
COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
FACTOR(SCLK_DDRC, "clk_ddrc", "ddrphy2x", 0, 1, 2),
FACTOR(0, "clk_ddrphy", "ddrphy2x", 0, 1, 2),
/* PD_CORE */
GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 6, GFLAGS),
GATE(0, "gpll_div2_core", "gpll_div2", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 6, GFLAGS),
COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK2928_CLKGATE_CON(0), 0, GFLAGS),
COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK2928_CLKGATE_CON(0), 7, GFLAGS),
/* PD_MISC */
MUX(SCLK_USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
RK2928_MISC_CON, 15, 1, MFLAGS),
/* PD_CPU */
COMPOSITE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(0), 1, GFLAGS),
GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0,
RK2928_CLKGATE_CON(0), 3, GFLAGS),
COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", 0,
RK2928_CLKSEL_CON(1), 8, 2, DFLAGS,
RK2928_CLKGATE_CON(0), 4, GFLAGS),
COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_src", 0,
RK2928_CLKSEL_CON(1), 12, 2, DFLAGS,
RK2928_CLKGATE_CON(0), 5, GFLAGS),
COMPOSITE_NOMUX(SCLK_CRYPTO, "clk_crypto", "aclk_cpu_src", 0,
RK2928_CLKSEL_CON(24), 0, 2, DFLAGS,
RK2928_CLKGATE_CON(0), 12, GFLAGS),
/* PD_VIDEO */
COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_5plls_p, 0,
RK2928_CLKSEL_CON(32), 5, 3, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 9, GFLAGS),
FACTOR(HCLK_VEPU, "hclk_vepu", "aclk_vepu", 0, 1, 4),
COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_5plls_p, 0,
RK2928_CLKSEL_CON(32), 13, 3, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 11, GFLAGS),
FACTOR_GATE(HCLK_VDPU, "hclk_vdpu", "aclk_vdpu", 0, 1, 4,
RK2928_CLKGATE_CON(3), 12, GFLAGS),
COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_5plls_p, 0,
RK2928_CLKSEL_CON(34), 13, 3, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 10, GFLAGS),
/* PD_VIO */
COMPOSITE(ACLK_VIO0, "aclk_vio0", mux_pll_src_5plls_p, 0,
RK2928_CLKSEL_CON(31), 5, 3, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 0, GFLAGS),
COMPOSITE(ACLK_VIO1, "aclk_vio1", mux_pll_src_5plls_p, 0,
RK2928_CLKSEL_CON(31), 13, 3, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(1), 4, GFLAGS),
COMPOSITE(HCLK_VIO, "hclk_vio", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(0), 11, GFLAGS),
/* PD_PERI */
GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(2), 0, GFLAGS),
GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(2), 0, GFLAGS),
GATE(0, "gpll_div2_peri", "gpll_div2", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(2), 0, GFLAGS),
GATE(0, "gpll_div3_peri", "gpll_div3", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(2), 0, GFLAGS),
COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0,
RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS),
COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK2928_CLKGATE_CON(2), 3, GFLAGS),
COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK2928_CLKGATE_CON(2), 2, GFLAGS),
GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
RK2928_CLKGATE_CON(2), 1, GFLAGS),
GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
RK2928_CLKGATE_CON(10), 3, GFLAGS),
GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
RK2928_CLKGATE_CON(10), 4, GFLAGS),
GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
RK2928_CLKGATE_CON(10), 5, GFLAGS),
GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
RK2928_CLKGATE_CON(10), 6, GFLAGS),
GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
RK2928_CLKGATE_CON(10), 7, GFLAGS),
GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
RK2928_CLKGATE_CON(10), 8, GFLAGS),
GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
RK2928_CLKGATE_CON(10), 0, GFLAGS),
GATE(SCLK_PVTM_GPU, "clk_pvtm_gpu", "xin24m", 0,
RK2928_CLKGATE_CON(10), 1, GFLAGS),
GATE(SCLK_PVTM_FUNC, "clk_pvtm_func", "xin24m", 0,
RK2928_CLKGATE_CON(10), 2, GFLAGS),
GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(2), 15, GFLAGS),
COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
RK2928_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK2928_CLKGATE_CON(2), 11, GFLAGS),
COMPOSITE(SCLK_SDIO, "sclk_sdio", mux_mmc_src_p, 0,
RK2928_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK2928_CLKGATE_CON(2), 13, GFLAGS),
COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
RK2928_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
RK2928_CLKGATE_CON(2), 14, GFLAGS),
DIV(SCLK_PVTM, "clk_pvtm", "clk_pvtm_func", 0,
RK2928_CLKSEL_CON(2), 0, 7, DFLAGS),
/*
* Clock-Architecture Diagram 2
*/
COMPOSITE(DCLK_VOP, "dclk_vop", mux_sclk_vop_src_p, 0,
RK2928_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
RK2928_CLKGATE_CON(3), 1, GFLAGS),
COMPOSITE(SCLK_VOP, "sclk_vop", mux_sclk_vop_src_p, 0,
RK2928_CLKSEL_CON(28), 0, 2, MFLAGS, 8, 8, DFLAGS,
RK2928_CLKGATE_CON(3), 2, GFLAGS),
COMPOSITE(DCLK_EBC, "dclk_ebc", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(23), 0, 2, MFLAGS, 8, 8, DFLAGS,
RK2928_CLKGATE_CON(3), 4, GFLAGS),
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
COMPOSITE_NODIV(SCLK_CIF_SRC, "sclk_cif_src", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(29), 0, 2, MFLAGS,
RK2928_CLKGATE_CON(3), 7, GFLAGS),
MUX(SCLK_CIF_OUT_SRC, "sclk_cif_out_src", mux_clk_cif_out_src_p, 0,
RK2928_CLKSEL_CON(13), 14, 2, MFLAGS),
DIV(SCLK_CIF_OUT, "sclk_cif_out", "sclk_cif_out_src", 0,
RK2928_CLKSEL_CON(29), 2, 5, DFLAGS),
COMPOSITE(0, "i2s0_src", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(9), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(4), 4, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(8), 0,
RK2928_CLKGATE_CON(4), 5, GFLAGS,
&rk3128_i2s0_fracmux),
GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
RK2928_CLKGATE_CON(4), 6, GFLAGS),
COMPOSITE(0, "i2s1_src", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 9, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(7), 0,
RK2928_CLKGATE_CON(0), 10, GFLAGS,
&rk3128_i2s1_fracmux),
GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
RK2928_CLKGATE_CON(0), 14, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
RK2928_CLKGATE_CON(0), 13, GFLAGS),
COMPOSITE(0, "sclk_spdif_src", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(6), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(2), 10, GFLAGS),
COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(20), 0,
RK2928_CLKGATE_CON(2), 12, GFLAGS,
&rk3128_spdif_fracmux),
GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 3, GFLAGS),
GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", 0,
RK2928_CLKGATE_CON(1), 5, GFLAGS),
GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin12m", 0,
RK2928_CLKGATE_CON(1), 6, GFLAGS),
COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
RK2928_CLKSEL_CON(24), 8, 8, DFLAGS,
RK2928_CLKGATE_CON(2), 8, GFLAGS),
COMPOSITE(ACLK_GPU, "aclk_gpu", mux_pll_src_5plls_p, 0,
RK2928_CLKSEL_CON(34), 5, 3, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 13, GFLAGS),
COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(2), 9, GFLAGS),
/* PD_UART */
COMPOSITE(0, "uart0_src", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 8, GFLAGS),
MUX(0, "uart12_src", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(13), 14, 2, MFLAGS),
COMPOSITE_NOMUX(0, "uart1_src", "uart12_src", 0,
RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 10, GFLAGS),
COMPOSITE_NOMUX(0, "uart2_src", "uart12_src", 0,
RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 13, GFLAGS),
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(17), 0,
RK2928_CLKGATE_CON(1), 9, GFLAGS,
&rk3128_uart0_fracmux),
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(18), 0,
RK2928_CLKGATE_CON(1), 11, GFLAGS,
&rk3128_uart1_fracmux),
COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(19), 0,
RK2928_CLKGATE_CON(1), 13, GFLAGS,
&rk3128_uart2_fracmux),
COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(1), 7, GFLAGS),
MUX(SCLK_MAC, "sclk_gmac", mux_sclk_gmac_p, 0,
RK2928_CLKSEL_CON(5), 15, 1, MFLAGS),
GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_gmac", 0,
RK2928_CLKGATE_CON(2), 5, GFLAGS),
GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_gmac", 0,
RK2928_CLKGATE_CON(2), 4, GFLAGS),
GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_gmac", 0,
RK2928_CLKGATE_CON(2), 6, GFLAGS),
GATE(SCLK_MAC_TX, "sclk_mac_tx", "sclk_gmac", 0,
RK2928_CLKGATE_CON(2), 7, GFLAGS),
COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(1), 14, GFLAGS),
COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(2), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(10), 15, GFLAGS),
COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "cpll", 0,
RK2928_CLKSEL_CON(29), 8, 6, DFLAGS,
RK2928_CLKGATE_CON(1), 0, GFLAGS),
/*
* Clock-Architecture Diagram 3
*/
/* PD_VOP */
GATE(ACLK_LCDC0, "aclk_lcdc0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 0, GFLAGS),
GATE(ACLK_CIF, "aclk_cif", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 5, GFLAGS),
GATE(ACLK_RGA, "aclk_rga", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS),
GATE(0, "aclk_vio0_niu", "aclk_vio0", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 13, GFLAGS),
GATE(ACLK_IEP, "aclk_iep", "aclk_vio1", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS),
GATE(0, "aclk_vio1_niu", "aclk_vio1", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 10, GFLAGS),
GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
GATE(PCLK_MIPI, "pclk_mipi", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS),
GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),
GATE(0, "hclk_vio_niu", "hclk_vio", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 12, GFLAGS),
GATE(HCLK_CIF, "hclk_cif", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS),
GATE(HCLK_EBC, "hclk_ebc", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 9, GFLAGS),
/* PD_PERI */
GATE(0, "aclk_peri_axi", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(10), 10, GFLAGS),
GATE(ACLK_DMAC, "aclk_dmac", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 15, GFLAGS),
GATE(0, "aclk_cpu_to_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
GATE(HCLK_I2S_2CH, "hclk_i2s_2ch", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 13, GFLAGS),
GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 13, GFLAGS),
GATE(0, "hclk_peri_ahb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 14, GFLAGS),
GATE(HCLK_SPDIF, "hclk_spdif", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 12, GFLAGS),
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS),
GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
GATE(0, "hclk_emmc_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 6, GFLAGS),
GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 14, GFLAGS),
GATE(PCLK_SIM_CARD, "pclk_sim_card", "pclk_peri", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS),
GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS),
GATE(0, "pclk_peri_axi", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
GATE(PCLK_PWM, "pclk_pwm", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS),
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
GATE(PCLK_EFUSE, "pclk_efuse", "pclk_peri", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS),
GATE(PCLK_TIMER, "pclk_timer", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 7, GFLAGS),
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
/* PD_BUS */
GATE(0, "aclk_initmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
GATE(0, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS),
GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
GATE(0, "pclk_ddrupctl", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 7, GFLAGS),
GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
GATE(0, "pclk_mipiphy", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 0, GFLAGS),
GATE(0, "pclk_pmu", "pclk_pmu_pre", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 3, GFLAGS),
/* PD_MMC */
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0),
MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1),
MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 0),
MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1),
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 0),
};
static struct rockchip_clk_branch rk3126_clk_branches[] __initdata = {
GATE(0, "pclk_stimer", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 15, GFLAGS),
GATE(0, "pclk_s_efuse", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS),
GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 8, GFLAGS),
};
static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
COMPOSITE(SCLK_SFC, "sclk_sfc", mux_sclk_sfc_src_p, 0,
RK2928_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 15, GFLAGS),
GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
};
static const char *const rk3128_critical_clocks[] __initconst = {
"aclk_cpu",
"hclk_cpu",
"pclk_cpu",
"aclk_peri",
"hclk_peri",
"pclk_peri",
"pclk_pmu",
"sclk_timer5",
};
static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru region\n", __func__);
return ERR_PTR(-ENOMEM);
}
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
if (IS_ERR(ctx)) {
pr_err("%s: rockchip clk init failed\n", __func__);
iounmap(reg_base);
return ERR_PTR(-ENOMEM);
}
rockchip_clk_register_plls(ctx, rk3128_pll_clks,
ARRAY_SIZE(rk3128_pll_clks),
RK3128_GRF_SOC_STATUS0);
rockchip_clk_register_branches(ctx, common_clk_branches,
ARRAY_SIZE(common_clk_branches));
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
&rk3128_cpuclk_data, rk3128_cpuclk_rates,
ARRAY_SIZE(rk3128_cpuclk_rates));
rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);
return ctx;
}
static void __init rk3126_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
ctx = rk3128_common_clk_init(np);
if (IS_ERR(ctx))
return;
rockchip_clk_register_branches(ctx, rk3126_clk_branches,
ARRAY_SIZE(rk3126_clk_branches));
rockchip_clk_protect_critical(rk3128_critical_clocks,
ARRAY_SIZE(rk3128_critical_clocks));
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rk3126_cru, "rockchip,rk3126-cru", rk3126_clk_init);
static void __init rk3128_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
ctx = rk3128_common_clk_init(np);
if (IS_ERR(ctx))
return;
rockchip_clk_register_branches(ctx, rk3128_clk_branches,
ARRAY_SIZE(rk3128_clk_branches));
rockchip_clk_protect_critical(rk3128_critical_clocks,
ARRAY_SIZE(rk3128_critical_clocks));
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rk3128_cru, "rockchip,rk3128-cru", rk3128_clk_init);
| linux-master | drivers/clk/rockchip/clk-rk3128.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2015 Heiko Stuebner <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/rk3368-cru.h>
#include "clk.h"
#define RK3368_GRF_SOC_STATUS0 0x480
enum rk3368_plls {
apllb, aplll, dpll, cpll, gpll, npll,
};
static struct rockchip_pll_rate_table rk3368_pll_rates[] = {
RK3066_PLL_RATE(2208000000, 1, 92, 1),
RK3066_PLL_RATE(2184000000, 1, 91, 1),
RK3066_PLL_RATE(2160000000, 1, 90, 1),
RK3066_PLL_RATE(2136000000, 1, 89, 1),
RK3066_PLL_RATE(2112000000, 1, 88, 1),
RK3066_PLL_RATE(2088000000, 1, 87, 1),
RK3066_PLL_RATE(2064000000, 1, 86, 1),
RK3066_PLL_RATE(2040000000, 1, 85, 1),
RK3066_PLL_RATE(2016000000, 1, 84, 1),
RK3066_PLL_RATE(1992000000, 1, 83, 1),
RK3066_PLL_RATE(1968000000, 1, 82, 1),
RK3066_PLL_RATE(1944000000, 1, 81, 1),
RK3066_PLL_RATE(1920000000, 1, 80, 1),
RK3066_PLL_RATE(1896000000, 1, 79, 1),
RK3066_PLL_RATE(1872000000, 1, 78, 1),
RK3066_PLL_RATE(1848000000, 1, 77, 1),
RK3066_PLL_RATE(1824000000, 1, 76, 1),
RK3066_PLL_RATE(1800000000, 1, 75, 1),
RK3066_PLL_RATE(1776000000, 1, 74, 1),
RK3066_PLL_RATE(1752000000, 1, 73, 1),
RK3066_PLL_RATE(1728000000, 1, 72, 1),
RK3066_PLL_RATE(1704000000, 1, 71, 1),
RK3066_PLL_RATE(1680000000, 1, 70, 1),
RK3066_PLL_RATE(1656000000, 1, 69, 1),
RK3066_PLL_RATE(1632000000, 1, 68, 1),
RK3066_PLL_RATE(1608000000, 1, 67, 1),
RK3066_PLL_RATE(1560000000, 1, 65, 1),
RK3066_PLL_RATE(1512000000, 1, 63, 1),
RK3066_PLL_RATE(1488000000, 1, 62, 1),
RK3066_PLL_RATE(1464000000, 1, 61, 1),
RK3066_PLL_RATE(1440000000, 1, 60, 1),
RK3066_PLL_RATE(1416000000, 1, 59, 1),
RK3066_PLL_RATE(1392000000, 1, 58, 1),
RK3066_PLL_RATE(1368000000, 1, 57, 1),
RK3066_PLL_RATE(1344000000, 1, 56, 1),
RK3066_PLL_RATE(1320000000, 1, 55, 1),
RK3066_PLL_RATE(1296000000, 1, 54, 1),
RK3066_PLL_RATE(1272000000, 1, 53, 1),
RK3066_PLL_RATE(1248000000, 1, 52, 1),
RK3066_PLL_RATE(1224000000, 1, 51, 1),
RK3066_PLL_RATE(1200000000, 1, 50, 1),
RK3066_PLL_RATE(1176000000, 1, 49, 1),
RK3066_PLL_RATE(1128000000, 1, 47, 1),
RK3066_PLL_RATE(1104000000, 1, 46, 1),
RK3066_PLL_RATE(1008000000, 1, 84, 2),
RK3066_PLL_RATE( 912000000, 1, 76, 2),
RK3066_PLL_RATE( 888000000, 1, 74, 2),
RK3066_PLL_RATE( 816000000, 1, 68, 2),
RK3066_PLL_RATE( 792000000, 1, 66, 2),
RK3066_PLL_RATE( 696000000, 1, 58, 2),
RK3066_PLL_RATE( 672000000, 1, 56, 2),
RK3066_PLL_RATE( 648000000, 1, 54, 2),
RK3066_PLL_RATE( 624000000, 1, 52, 2),
RK3066_PLL_RATE( 600000000, 1, 50, 2),
RK3066_PLL_RATE( 576000000, 1, 48, 2),
RK3066_PLL_RATE( 552000000, 1, 46, 2),
RK3066_PLL_RATE( 528000000, 1, 88, 4),
RK3066_PLL_RATE( 504000000, 1, 84, 4),
RK3066_PLL_RATE( 480000000, 1, 80, 4),
RK3066_PLL_RATE( 456000000, 1, 76, 4),
RK3066_PLL_RATE( 408000000, 1, 68, 4),
RK3066_PLL_RATE( 312000000, 1, 52, 4),
RK3066_PLL_RATE( 252000000, 1, 84, 8),
RK3066_PLL_RATE( 216000000, 1, 72, 8),
RK3066_PLL_RATE( 126000000, 2, 84, 8),
RK3066_PLL_RATE( 48000000, 2, 32, 8),
{ /* sentinel */ },
};
PNAME(mux_pll_p) = { "xin24m", "xin32k" };
PNAME(mux_armclkb_p) = { "apllb_core", "gpllb_core" };
PNAME(mux_armclkl_p) = { "aplll_core", "gplll_core" };
PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
PNAME(mux_cs_src_p) = { "apllb_cs", "aplll_cs", "gpll_cs"};
PNAME(mux_aclk_bus_src_p) = { "cpll_aclk_bus", "gpll_aclk_bus" };
PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
PNAME(mux_pll_src_cpll_gpll_usb_p) = { "cpll", "gpll", "usbphy_480m" };
PNAME(mux_pll_src_cpll_gpll_usb_usb_p) = { "cpll", "gpll", "usbphy_480m",
"usbphy_480m" };
PNAME(mux_pll_src_cpll_gpll_usb_npll_p) = { "cpll", "gpll", "usbphy_480m",
"npll" };
PNAME(mux_pll_src_cpll_gpll_npll_npll_p) = { "cpll", "gpll", "npll", "npll" };
PNAME(mux_pll_src_cpll_gpll_npll_usb_p) = { "cpll", "gpll", "npll",
"usbphy_480m" };
PNAME(mux_i2s_8ch_pre_p) = { "i2s_8ch_src", "i2s_8ch_frac",
"ext_i2s", "xin12m" };
PNAME(mux_i2s_8ch_clkout_p) = { "i2s_8ch_pre", "xin12m" };
PNAME(mux_i2s_2ch_p) = { "i2s_2ch_src", "i2s_2ch_frac",
"dummy", "xin12m" };
PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac",
"ext_i2s", "xin12m" };
PNAME(mux_edp_24m_p) = { "xin24m", "dummy" };
PNAME(mux_vip_out_p) = { "vip_src", "xin24m" };
PNAME(mux_usbphy480m_p) = { "usbotg_out", "xin24m" };
PNAME(mux_hsic_usbphy480m_p) = { "usbotg_out", "dummy" };
PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy_480m" };
PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
PNAME(mux_uart2_p) = { "uart2_src", "xin24m" };
PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m" };
PNAME(mux_uart4_p) = { "uart4_src", "uart4_frac", "xin24m" };
PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" };
PNAME(mux_mmc_src_p) = { "cpll", "gpll", "usbphy_480m", "xin24m" };
static struct rockchip_pll_clock rk3368_pll_clks[] __initdata = {
[apllb] = PLL(pll_rk3066, PLL_APLLB, "apllb", mux_pll_p, 0, RK3368_PLL_CON(0),
RK3368_PLL_CON(3), 8, 1, 0, rk3368_pll_rates),
[aplll] = PLL(pll_rk3066, PLL_APLLL, "aplll", mux_pll_p, 0, RK3368_PLL_CON(4),
RK3368_PLL_CON(7), 8, 0, 0, rk3368_pll_rates),
[dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8),
RK3368_PLL_CON(11), 8, 2, 0, NULL),
[cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
RK3368_PLL_CON(15), 8, 3, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16),
RK3368_PLL_CON(19), 8, 4, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
[npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3368_PLL_CON(20),
RK3368_PLL_CON(23), 8, 5, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
};
static struct clk_div_table div_ddrphy_t[] = {
{ .val = 0, .div = 1 },
{ .val = 1, .div = 2 },
{ .val = 3, .div = 4 },
{ /* sentinel */ },
};
#define MFLAGS CLK_MUX_HIWORD_MASK
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
static const struct rockchip_cpuclk_reg_data rk3368_cpuclkb_data = {
.core_reg[0] = RK3368_CLKSEL_CON(0),
.div_core_shift[0] = 0,
.div_core_mask[0] = 0x1f,
.num_cores = 1,
.mux_core_alt = 1,
.mux_core_main = 0,
.mux_core_shift = 7,
.mux_core_mask = 0x1,
};
static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
.core_reg[0] = RK3368_CLKSEL_CON(2),
.div_core_shift[0] = 0,
.mux_core_alt = 1,
.num_cores = 1,
.mux_core_main = 0,
.div_core_mask[0] = 0x1f,
.mux_core_shift = 7,
.mux_core_mask = 0x1,
};
#define RK3368_DIV_ACLKM_MASK 0x1f
#define RK3368_DIV_ACLKM_SHIFT 8
#define RK3368_DIV_ATCLK_MASK 0x1f
#define RK3368_DIV_ATCLK_SHIFT 0
#define RK3368_DIV_PCLK_DBG_MASK 0x1f
#define RK3368_DIV_PCLK_DBG_SHIFT 8
#define RK3368_CLKSEL0(_offs, _aclkm) \
{ \
.reg = RK3368_CLKSEL_CON(0 + _offs), \
.val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK, \
RK3368_DIV_ACLKM_SHIFT), \
}
#define RK3368_CLKSEL1(_offs, _atclk, _pdbg) \
{ \
.reg = RK3368_CLKSEL_CON(1 + _offs), \
.val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK, \
RK3368_DIV_ATCLK_SHIFT) | \
HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK, \
RK3368_DIV_PCLK_DBG_SHIFT), \
}
/* cluster_b: aclkm in clksel0, rest in clksel1 */
#define RK3368_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \
{ \
.prate = _prate, \
.divs = { \
RK3368_CLKSEL0(0, _aclkm), \
RK3368_CLKSEL1(0, _atclk, _pdbg), \
}, \
}
/* cluster_l: aclkm in clksel2, rest in clksel3 */
#define RK3368_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \
{ \
.prate = _prate, \
.divs = { \
RK3368_CLKSEL0(2, _aclkm), \
RK3368_CLKSEL1(2, _atclk, _pdbg), \
}, \
}
static struct rockchip_cpuclk_rate_table rk3368_cpuclkb_rates[] __initdata = {
RK3368_CPUCLKB_RATE(1512000000, 1, 5, 5),
RK3368_CPUCLKB_RATE(1488000000, 1, 4, 4),
RK3368_CPUCLKB_RATE(1416000000, 1, 4, 4),
RK3368_CPUCLKB_RATE(1200000000, 1, 3, 3),
RK3368_CPUCLKB_RATE(1008000000, 1, 3, 3),
RK3368_CPUCLKB_RATE( 816000000, 1, 2, 2),
RK3368_CPUCLKB_RATE( 696000000, 1, 2, 2),
RK3368_CPUCLKB_RATE( 600000000, 1, 1, 1),
RK3368_CPUCLKB_RATE( 408000000, 1, 1, 1),
RK3368_CPUCLKB_RATE( 312000000, 1, 1, 1),
};
static struct rockchip_cpuclk_rate_table rk3368_cpuclkl_rates[] __initdata = {
RK3368_CPUCLKL_RATE(1512000000, 1, 6, 6),
RK3368_CPUCLKL_RATE(1488000000, 1, 5, 5),
RK3368_CPUCLKL_RATE(1416000000, 1, 5, 5),
RK3368_CPUCLKL_RATE(1200000000, 1, 4, 4),
RK3368_CPUCLKL_RATE(1008000000, 1, 4, 4),
RK3368_CPUCLKL_RATE( 816000000, 1, 3, 3),
RK3368_CPUCLKL_RATE( 696000000, 1, 2, 2),
RK3368_CPUCLKL_RATE( 600000000, 1, 2, 2),
RK3368_CPUCLKL_RATE( 408000000, 1, 1, 1),
RK3368_CPUCLKL_RATE( 312000000, 1, 1, 1),
};
static struct rockchip_clk_branch rk3368_i2s_8ch_fracmux __initdata =
MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(27), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3368_spdif_8ch_fracmux __initdata =
MUX(0, "spdif_8ch_pre", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(31), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3368_i2s_2ch_fracmux __initdata =
MUX(0, "i2s_2ch_pre", mux_i2s_2ch_p, CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(53), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3368_uart0_fracmux __initdata =
MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(33), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3368_uart1_fracmux __initdata =
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(35), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3368_uart3_fracmux __initdata =
MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(39), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3368_uart4_fracmux __initdata =
MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(41), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
/*
* Clock-Architecture Diagram 2
*/
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
MUX(SCLK_USBPHY480M, "usbphy_480m", mux_usbphy480m_p, CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(13), 8, 1, MFLAGS),
GATE(0, "apllb_core", "apllb", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(0), 0, GFLAGS),
GATE(0, "gpllb_core", "gpll", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(0), 1, GFLAGS),
GATE(0, "aplll_core", "aplll", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(0), 4, GFLAGS),
GATE(0, "gplll_core", "gpll", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(0), 5, GFLAGS),
DIV(0, "aclkm_core_b", "armclkb", 0,
RK3368_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
DIV(0, "atclk_core_b", "armclkb", 0,
RK3368_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
DIV(0, "pclk_dbg_b", "armclkb", 0,
RK3368_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
DIV(0, "aclkm_core_l", "armclkl", 0,
RK3368_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
DIV(0, "atclk_core_l", "armclkl", 0,
RK3368_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
DIV(0, "pclk_dbg_l", "armclkl", 0,
RK3368_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
GATE(0, "apllb_cs", "apllb", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(0), 9, GFLAGS),
GATE(0, "aplll_cs", "aplll", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(0), 10, GFLAGS),
GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(0), 8, GFLAGS),
COMPOSITE_NOGATE(0, "sclk_cs_pre", mux_cs_src_p, CLK_IGNORE_UNUSED,
RK3368_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
COMPOSITE_NOMUX(0, "clkin_trace", "sclk_cs_pre", CLK_IGNORE_UNUSED,
RK3368_CLKSEL_CON(4), 8, 5, DFLAGS,
RK3368_CLKGATE_CON(0), 13, GFLAGS),
COMPOSITE(0, "aclk_cci_pre", mux_pll_src_cpll_gpll_usb_npll_p, CLK_IGNORE_UNUSED,
RK3368_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 7, DFLAGS,
RK3368_CLKGATE_CON(0), 12, GFLAGS),
GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3368_CLKGATE_CON(7), 10, GFLAGS),
GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(1), 8, GFLAGS),
GATE(0, "gpll_ddr", "gpll", 0,
RK3368_CLKGATE_CON(1), 9, GFLAGS),
COMPOSITE_NOGATE_DIVTBL(0, "ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
RK3368_CLKSEL_CON(13), 4, 1, MFLAGS, 0, 2, DFLAGS, div_ddrphy_t),
FACTOR_GATE(0, "sclk_ddr", "ddrphy_src", CLK_IGNORE_UNUSED, 1, 4,
RK3368_CLKGATE_CON(6), 14, GFLAGS),
GATE(0, "sclk_ddr4x", "ddrphy_src", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(6), 15, GFLAGS),
GATE(0, "gpll_aclk_bus", "gpll", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(1), 10, GFLAGS),
GATE(0, "cpll_aclk_bus", "cpll", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(1), 11, GFLAGS),
COMPOSITE_NOGATE(0, "aclk_bus_src", mux_aclk_bus_src_p, CLK_IGNORE_UNUSED,
RK3368_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 5, DFLAGS),
GATE(ACLK_BUS, "aclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(1), 0, GFLAGS),
COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
RK3368_CLKSEL_CON(8), 12, 3, DFLAGS,
RK3368_CLKGATE_CON(1), 2, GFLAGS),
COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
RK3368_CLKSEL_CON(8), 8, 2, DFLAGS,
RK3368_CLKGATE_CON(1), 1, GFLAGS),
COMPOSITE_NOMUX(0, "sclk_crypto", "aclk_bus_src", 0,
RK3368_CLKSEL_CON(10), 14, 2, DFLAGS,
RK3368_CLKGATE_CON(7), 2, GFLAGS),
COMPOSITE(0, "fclk_mcu_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
RK3368_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3368_CLKGATE_CON(1), 3, GFLAGS),
/*
* stclk_mcu is listed as child of fclk_mcu_src in diagram 5,
* but stclk_mcu has an additional own divider in diagram 2
*/
COMPOSITE_NOMUX(0, "stclk_mcu", "fclk_mcu_src", 0,
RK3368_CLKSEL_CON(12), 8, 3, DFLAGS,
RK3368_CLKGATE_CON(13), 13, GFLAGS),
COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(27), 12, 1, MFLAGS, 0, 7, DFLAGS,
RK3368_CLKGATE_CON(6), 1, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(28), 0,
RK3368_CLKGATE_CON(6), 2, GFLAGS,
&rk3368_i2s_8ch_fracmux),
COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0,
RK3368_CLKSEL_CON(27), 15, 1, MFLAGS,
RK3368_CLKGATE_CON(6), 0, GFLAGS),
GATE(SCLK_I2S_8CH, "sclk_i2s_8ch", "i2s_8ch_pre", CLK_SET_RATE_PARENT,
RK3368_CLKGATE_CON(6), 3, GFLAGS),
COMPOSITE(0, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(31), 12, 1, MFLAGS, 0, 7, DFLAGS,
RK3368_CLKGATE_CON(6), 4, GFLAGS),
COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(32), 0,
RK3368_CLKGATE_CON(6), 5, GFLAGS,
&rk3368_spdif_8ch_fracmux),
GATE(SCLK_SPDIF_8CH, "sclk_spdif_8ch", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
RK3368_CLKGATE_CON(6), 6, GFLAGS),
COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(53), 12, 1, MFLAGS, 0, 7, DFLAGS,
RK3368_CLKGATE_CON(5), 13, GFLAGS),
COMPOSITE_FRACMUX(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(54), 0,
RK3368_CLKGATE_CON(5), 14, GFLAGS,
&rk3368_i2s_2ch_fracmux),
GATE(SCLK_I2S_2CH, "sclk_i2s_2ch", "i2s_2ch_pre", CLK_SET_RATE_PARENT,
RK3368_CLKGATE_CON(5), 15, GFLAGS),
COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
RK3368_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3368_CLKGATE_CON(6), 12, GFLAGS),
GATE(0, "sclk_hsadc_tsp", "ext_hsadc_tsp", 0,
RK3368_CLKGATE_CON(13), 7, GFLAGS),
MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(35), 12, 1, MFLAGS),
COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
RK3368_CLKSEL_CON(37), 0, 7, DFLAGS,
RK3368_CLKGATE_CON(2), 4, GFLAGS),
MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(37), 8, 1, MFLAGS),
/*
* Clock-Architecture Diagram 3
*/
COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_npll_usb_p, 0,
RK3368_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3368_CLKGATE_CON(4), 6, GFLAGS),
COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_npll_usb_p, 0,
RK3368_CLKSEL_CON(15), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3368_CLKGATE_CON(4), 7, GFLAGS),
/*
* We use aclk_vdpu by default ---GRF_SOC_CON0[7] setting in system,
* so we ignore the mux and make clocks nodes as following,
*/
FACTOR_GATE(0, "hclk_video_pre", "aclk_vdpu", 0, 1, 4,
RK3368_CLKGATE_CON(4), 8, GFLAGS),
COMPOSITE(0, "sclk_hevc_cabac_src", mux_pll_src_cpll_gpll_npll_usb_p, 0,
RK3368_CLKSEL_CON(17), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3368_CLKGATE_CON(5), 1, GFLAGS),
COMPOSITE(0, "sclk_hevc_core_src", mux_pll_src_cpll_gpll_npll_usb_p, 0,
RK3368_CLKSEL_CON(17), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3368_CLKGATE_CON(5), 2, GFLAGS),
COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb_p, CLK_IGNORE_UNUSED,
RK3368_CLKSEL_CON(19), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3368_CLKGATE_CON(4), 0, GFLAGS),
DIV(0, "hclk_vio", "aclk_vio0", 0,
RK3368_CLKSEL_CON(21), 0, 5, DFLAGS),
COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb_p, 0,
RK3368_CLKSEL_CON(18), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3368_CLKGATE_CON(4), 3, GFLAGS),
COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb_p, 0,
RK3368_CLKSEL_CON(18), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3368_CLKGATE_CON(4), 4, GFLAGS),
COMPOSITE(DCLK_VOP, "dclk_vop", mux_pll_src_cpll_gpll_npll_p, 0,
RK3368_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3368_CLKGATE_CON(4), 1, GFLAGS),
GATE(SCLK_VOP0_PWM, "sclk_vop0_pwm", "xin24m", 0,
RK3368_CLKGATE_CON(4), 2, GFLAGS),
COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_npll_p, 0,
RK3368_CLKSEL_CON(22), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3368_CLKGATE_CON(4), 9, GFLAGS),
GATE(0, "pclk_isp_in", "ext_isp", 0,
RK3368_CLKGATE_CON(17), 2, GFLAGS),
INVERTER(PCLK_ISP, "pclk_isp", "pclk_isp_in",
RK3368_CLKSEL_CON(21), 6, IFLAGS),
GATE(0, "pclk_vip_in", "ext_vip", 0,
RK3368_CLKGATE_CON(16), 13, GFLAGS),
INVERTER(PCLK_VIP, "pclk_vip", "pclk_vip_in",
RK3368_CLKSEL_CON(21), 13, IFLAGS),
GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
RK3368_CLKGATE_CON(4), 13, GFLAGS),
GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
RK3368_CLKGATE_CON(4), 12, GFLAGS),
COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,
RK3368_CLKGATE_CON(4), 5, GFLAGS),
COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
RK3368_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS),
COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
RK3368_CLKSEL_CON(23), 8, 1, MFLAGS,
RK3368_CLKGATE_CON(5), 4, GFLAGS),
COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_npll_p, 0,
RK3368_CLKSEL_CON(23), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3368_CLKGATE_CON(5), 3, GFLAGS),
COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_cpll_gpll_npll_npll_p, 0,
RK3368_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3368_CLKGATE_CON(5), 5, GFLAGS),
DIV(0, "pclk_pd_alive", "gpll", 0,
RK3368_CLKSEL_CON(10), 8, 5, DFLAGS),
/* sclk_timer has a gate in the sgrf */
COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,
RK3368_CLKSEL_CON(10), 0, 5, DFLAGS,
RK3368_CLKGATE_CON(7), 9, GFLAGS),
GATE(SCLK_PVTM_PMU, "sclk_pvtm_pmu", "xin24m", 0,
RK3368_CLKGATE_CON(7), 3, GFLAGS),
COMPOSITE(0, "sclk_gpu_core_src", mux_pll_src_cpll_gpll_usb_npll_p, 0,
RK3368_CLKSEL_CON(14), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3368_CLKGATE_CON(4), 11, GFLAGS),
MUX(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(14), 14, 1, MFLAGS),
COMPOSITE_NOMUX(0, "aclk_gpu_mem_pre", "aclk_gpu_src", 0,
RK3368_CLKSEL_CON(14), 8, 5, DFLAGS,
RK3368_CLKGATE_CON(5), 8, GFLAGS),
COMPOSITE_NOMUX(0, "aclk_gpu_cfg_pre", "aclk_gpu_src", 0,
RK3368_CLKSEL_CON(16), 8, 5, DFLAGS,
RK3368_CLKGATE_CON(5), 9, GFLAGS),
GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0,
RK3368_CLKGATE_CON(7), 11, GFLAGS),
COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
RK3368_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3368_CLKGATE_CON(3), 0, GFLAGS),
COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
RK3368_CLKSEL_CON(9), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK3368_CLKGATE_CON(3), 3, GFLAGS),
COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
RK3368_CLKSEL_CON(9), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK3368_CLKGATE_CON(3), 2, GFLAGS),
GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(3), 1, GFLAGS),
GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3368_CLKGATE_CON(4), 14, GFLAGS),
/*
* Clock-Architecture Diagram 4
*/
COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3368_CLKGATE_CON(3), 7, GFLAGS),
COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(45), 15, 1, MFLAGS, 8, 7, DFLAGS,
RK3368_CLKGATE_CON(3), 8, GFLAGS),
COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(46), 15, 1, MFLAGS, 8, 7, DFLAGS,
RK3368_CLKGATE_CON(3), 9, GFLAGS),
COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
RK3368_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3368_CLKGATE_CON(7), 12, GFLAGS),
COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
RK3368_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3368_CLKGATE_CON(7), 13, GFLAGS),
COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
RK3368_CLKSEL_CON(51), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK3368_CLKGATE_CON(7), 15, GFLAGS),
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3368_SDMMC_CON0, 1),
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3368_SDMMC_CON1, 0),
MMC(SCLK_SDIO0_DRV, "sdio0_drv", "sclk_sdio0", RK3368_SDIO0_CON0, 1),
MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3368_SDIO0_CON1, 0),
MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3368_EMMC_CON0, 1),
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3368_EMMC_CON1, 0),
GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(8), 1, GFLAGS),
/* pmu_grf_soc_con0[6] allows to select between xin32k and pvtm_pmu */
GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(8), 4, GFLAGS),
/* pmu_grf_soc_con0[6] allows to select between xin32k and pvtm_pmu */
COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,
RK3368_CLKSEL_CON(25), 0, 6, DFLAGS,
RK3368_CLKGATE_CON(3), 5, GFLAGS),
COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
RK3368_CLKSEL_CON(25), 8, 8, DFLAGS,
RK3368_CLKGATE_CON(3), 6, GFLAGS),
COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3368_CLKGATE_CON(7), 8, GFLAGS),
COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3368_CLKGATE_CON(6), 7, GFLAGS),
COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb_usb_p, 0,
RK3368_CLKSEL_CON(33), 12, 2, MFLAGS, 0, 7, DFLAGS,
RK3368_CLKGATE_CON(2), 0, GFLAGS),
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(34), 0,
RK3368_CLKGATE_CON(2), 1, GFLAGS,
&rk3368_uart0_fracmux),
COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
RK3368_CLKSEL_CON(35), 0, 7, DFLAGS,
RK3368_CLKGATE_CON(2), 2, GFLAGS),
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(36), 0,
RK3368_CLKGATE_CON(2), 3, GFLAGS,
&rk3368_uart1_fracmux),
COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
RK3368_CLKSEL_CON(39), 0, 7, DFLAGS,
RK3368_CLKGATE_CON(2), 6, GFLAGS),
COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(40), 0,
RK3368_CLKGATE_CON(2), 7, GFLAGS,
&rk3368_uart3_fracmux),
COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
RK3368_CLKSEL_CON(41), 0, 7, DFLAGS,
RK3368_CLKGATE_CON(2), 8, GFLAGS),
COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(42), 0,
RK3368_CLKGATE_CON(2), 9, GFLAGS,
&rk3368_uart4_fracmux),
COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3368_CLKGATE_CON(3), 4, GFLAGS),
MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(43), 8, 1, MFLAGS),
GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0,
RK3368_CLKGATE_CON(7), 7, GFLAGS),
GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0,
RK3368_CLKGATE_CON(7), 6, GFLAGS),
GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0,
RK3368_CLKGATE_CON(7), 4, GFLAGS),
GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
RK3368_CLKGATE_CON(7), 5, GFLAGS),
GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(7), 0, GFLAGS),
COMPOSITE_NODIV(0, "hsic_usbphy_480m", mux_hsic_usbphy480m_p, 0,
RK3368_CLKSEL_CON(26), 8, 2, MFLAGS,
RK3368_CLKGATE_CON(8), 0, GFLAGS),
COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
RK3368_CLKSEL_CON(26), 12, 2, MFLAGS,
RK3368_CLKGATE_CON(8), 7, GFLAGS),
GATE(SCLK_HSICPHY12M, "sclk_hsicphy12m", "xin12m", 0,
RK3368_CLKGATE_CON(8), 6, GFLAGS),
/*
* Clock-Architecture Diagram 5
*/
/* aclk_cci_pre gates */
GATE(0, "aclk_core_niu_cpup", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 4, GFLAGS),
GATE(0, "aclk_core_niu_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 3, GFLAGS),
GATE(0, "aclk_cci400", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 2, GFLAGS),
GATE(0, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 1, GFLAGS),
GATE(0, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 0, GFLAGS),
/* aclkm_core_* gates */
GATE(0, "aclk_adb400s_pd_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(10), 0, GFLAGS),
GATE(0, "aclk_adb400s_pd_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 0, GFLAGS),
/* armclk* gates */
GATE(0, "sclk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(10), 1, GFLAGS),
GATE(0, "sclk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 1, GFLAGS),
/* sclk_cs_pre gates */
GATE(0, "sclk_dbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 7, GFLAGS),
GATE(0, "pclk_core_niu_sdbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 6, GFLAGS),
GATE(0, "hclk_core_niu_dbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 5, GFLAGS),
/* aclk_bus gates */
GATE(0, "aclk_strc_sys", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 12, GFLAGS),
GATE(ACLK_DMAC_BUS, "aclk_dmac_bus", "aclk_bus", 0, RK3368_CLKGATE_CON(12), 11, GFLAGS),
GATE(0, "sclk_intmem1", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 6, GFLAGS),
GATE(0, "sclk_intmem0", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 5, GFLAGS),
GATE(0, "aclk_intmem", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 4, GFLAGS),
GATE(0, "aclk_gic400", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 9, GFLAGS),
/* sclk_ddr gates */
GATE(0, "nclk_ddrupctl", "sclk_ddr", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 2, GFLAGS),
/* clk_hsadc_tsp is part of diagram2 */
/* fclk_mcu_src gates */
GATE(0, "hclk_noc_mcu", "fclk_mcu_src", 0, RK3368_CLKGATE_CON(13), 14, GFLAGS),
GATE(0, "fclk_mcu", "fclk_mcu_src", 0, RK3368_CLKGATE_CON(13), 12, GFLAGS),
GATE(0, "hclk_mcu", "fclk_mcu_src", 0, RK3368_CLKGATE_CON(13), 11, GFLAGS),
/* hclk_cpu gates */
GATE(HCLK_SPDIF, "hclk_spdif", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 10, GFLAGS),
GATE(HCLK_ROM, "hclk_rom", "hclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 9, GFLAGS),
GATE(HCLK_I2S_2CH, "hclk_i2s_2ch", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 8, GFLAGS),
GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 7, GFLAGS),
GATE(HCLK_TSP, "hclk_tsp", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 10, GFLAGS),
GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 4, GFLAGS),
GATE(MCLK_CRYPTO, "mclk_crypto", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 3, GFLAGS),
/* pclk_cpu gates */
GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 14, GFLAGS),
GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 13, GFLAGS),
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 3, GFLAGS),
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 2, GFLAGS),
GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 1, GFLAGS),
GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 0, GFLAGS),
GATE(PCLK_SIM, "pclk_sim", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 8, GFLAGS),
GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),
GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
GATE(0, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
/*
* video clk gates
* aclk_video(_pre) can actually select between parents of aclk_vdpu
* and aclk_vepu by setting bit GRF_SOC_CON0[7].
*/
GATE(ACLK_VIDEO, "aclk_video", "aclk_vdpu", 0, RK3368_CLKGATE_CON(15), 0, GFLAGS),
GATE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", "sclk_hevc_cabac_src", 0, RK3368_CLKGATE_CON(15), 3, GFLAGS),
GATE(SCLK_HEVC_CORE, "sclk_hevc_core", "sclk_hevc_core_src", 0, RK3368_CLKGATE_CON(15), 2, GFLAGS),
GATE(HCLK_VIDEO, "hclk_video", "hclk_video_pre", 0, RK3368_CLKGATE_CON(15), 1, GFLAGS),
/* aclk_rga_pre gates */
GATE(ACLK_VIO1_NOC, "aclk_vio1_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 10, GFLAGS),
GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(16), 0, GFLAGS),
GATE(ACLK_HDCP, "aclk_hdcp", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(17), 10, GFLAGS),
/* aclk_vio0 gates */
GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 11, GFLAGS),
GATE(ACLK_VIO0_NOC, "aclk_vio0_noc", "aclk_vio0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 9, GFLAGS),
GATE(ACLK_VOP, "aclk_vop", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 5, GFLAGS),
GATE(ACLK_VOP_IEP, "aclk_vop_iep", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 4, GFLAGS),
GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 2, GFLAGS),
/* sclk_isp gates */
GATE(HCLK_ISP, "hclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(16), 14, GFLAGS),
GATE(ACLK_ISP, "aclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(17), 0, GFLAGS),
/* hclk_vio gates */
GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 12, GFLAGS),
GATE(HCLK_VIO_NOC, "hclk_vio_noc", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 8, GFLAGS),
GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 7, GFLAGS),
GATE(HCLK_VOP, "hclk_vop", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 6, GFLAGS),
GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 3, GFLAGS),
GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 1, GFLAGS),
GATE(HCLK_VIO_HDCPMMU, "hclk_hdcpmmu", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 12, GFLAGS),
GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 7, GFLAGS),
/*
* pclk_vio gates
* pclk_vio comes from the exactly same source as hclk_vio
*/
GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 11, GFLAGS),
GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 9, GFLAGS),
GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 8, GFLAGS),
GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 6, GFLAGS),
GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 4, GFLAGS),
GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 3, GFLAGS),
/* ext_vip gates in diagram3 */
/* gpu gates */
GATE(SCLK_GPU_CORE, "sclk_gpu_core", "sclk_gpu_core_src", 0, RK3368_CLKGATE_CON(18), 2, GFLAGS),
GATE(ACLK_GPU_MEM, "aclk_gpu_mem", "aclk_gpu_mem_pre", 0, RK3368_CLKGATE_CON(18), 1, GFLAGS),
GATE(ACLK_GPU_CFG, "aclk_gpu_cfg", "aclk_gpu_cfg_pre", 0, RK3368_CLKGATE_CON(18), 0, GFLAGS),
/* aclk_peri gates */
GATE(ACLK_DMAC_PERI, "aclk_dmac_peri", "aclk_peri", 0, RK3368_CLKGATE_CON(19), 3, GFLAGS),
GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 2, GFLAGS),
GATE(HCLK_SFC, "hclk_sfc", "aclk_peri", 0, RK3368_CLKGATE_CON(20), 15, GFLAGS),
GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3368_CLKGATE_CON(20), 13, GFLAGS),
GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 8, GFLAGS),
GATE(ACLK_PERI_MMU, "aclk_peri_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(21), 4, GFLAGS),
/* hclk_peri gates */
GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 0, GFLAGS),
GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 11, GFLAGS),
GATE(0, "hclk_mmc_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 10, GFLAGS),
GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 9, GFLAGS),
GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 7, GFLAGS),
GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 6, GFLAGS),
GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 5, GFLAGS),
GATE(HCLK_HOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 4, GFLAGS),
GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 3, GFLAGS),
GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 2, GFLAGS),
GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 1, GFLAGS),
GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 3, GFLAGS),
GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 2, GFLAGS),
GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 1, GFLAGS),
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 0, GFLAGS),
/* pclk_peri gates */
GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 15, GFLAGS),
GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 14, GFLAGS),
GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 13, GFLAGS),
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 12, GFLAGS),
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 11, GFLAGS),
GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 10, GFLAGS),
GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 9, GFLAGS),
GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 8, GFLAGS),
GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 7, GFLAGS),
GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 6, GFLAGS),
GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 5, GFLAGS),
GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 4, GFLAGS),
GATE(0, "pclk_peri_axi_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 1, GFLAGS),
GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK3368_CLKGATE_CON(20), 14, GFLAGS),
GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3368_CLKGATE_CON(20), 0, GFLAGS),
/* pclk_pd_alive gates */
GATE(PCLK_TIMER1, "pclk_timer1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 13, GFLAGS),
GATE(PCLK_TIMER0, "pclk_timer0", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 12, GFLAGS),
GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 9, GFLAGS),
GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 8, GFLAGS),
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 3, GFLAGS),
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 2, GFLAGS),
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 1, GFLAGS),
/* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"),
/*
* pclk_vio gates
* pclk_vio comes from the exactly same source as hclk_vio
*/
GATE(PCLK_DPHYRX, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 11, GFLAGS),
GATE(PCLK_DPHYTX0, "pclk_dphytx0", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 10, GFLAGS),
/* pclk_pd_pmu gates */
GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 5, GFLAGS),
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3368_CLKGATE_CON(23), 4, GFLAGS),
GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 3, GFLAGS),
GATE(0, "pclk_pmu_noc", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 2, GFLAGS),
GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 1, GFLAGS),
GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 0, GFLAGS),
/* timer gates */
GATE(SCLK_TIMER15, "sclk_timer15", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 11, GFLAGS),
GATE(SCLK_TIMER14, "sclk_timer14", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 10, GFLAGS),
GATE(SCLK_TIMER13, "sclk_timer13", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 9, GFLAGS),
GATE(SCLK_TIMER12, "sclk_timer12", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 8, GFLAGS),
GATE(SCLK_TIMER11, "sclk_timer11", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 7, GFLAGS),
GATE(SCLK_TIMER10, "sclk_timer10", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 6, GFLAGS),
GATE(SCLK_TIMER05, "sclk_timer05", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 5, GFLAGS),
GATE(SCLK_TIMER04, "sclk_timer04", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 4, GFLAGS),
GATE(SCLK_TIMER03, "sclk_timer03", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 3, GFLAGS),
GATE(SCLK_TIMER02, "sclk_timer02", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 2, GFLAGS),
GATE(SCLK_TIMER01, "sclk_timer01", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 1, GFLAGS),
GATE(SCLK_TIMER00, "sclk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 0, GFLAGS),
};
static const char *const rk3368_critical_clocks[] __initconst = {
"aclk_bus",
"aclk_peri",
/*
* pwm1 supplies vdd_logic on a lot of boards, is currently unhandled
* but needs to stay enabled there (including its parents) at all times.
*/
"pclk_pwm1",
"pclk_pd_pmu",
"pclk_pd_alive",
"pclk_peri",
"hclk_peri",
"pclk_ddrphy",
"pclk_ddrupctl",
"pmu_hclk_otg0",
};
static void __init rk3368_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
reg_base = of_iomap(np, 0);
if (!reg_base) {
pr_err("%s: could not map cru region\n", __func__);
return;
}
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
if (IS_ERR(ctx)) {
pr_err("%s: rockchip clk init failed\n", __func__);
iounmap(reg_base);
return;
}
rockchip_clk_register_plls(ctx, rk3368_pll_clks,
ARRAY_SIZE(rk3368_pll_clks),
RK3368_GRF_SOC_STATUS0);
rockchip_clk_register_branches(ctx, rk3368_clk_branches,
ARRAY_SIZE(rk3368_clk_branches));
rockchip_clk_protect_critical(rk3368_critical_clocks,
ARRAY_SIZE(rk3368_critical_clocks));
rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
&rk3368_cpuclkb_data, rk3368_cpuclkb_rates,
ARRAY_SIZE(rk3368_cpuclkb_rates));
rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
&rk3368_cpuclkl_data, rk3368_cpuclkl_rates,
ARRAY_SIZE(rk3368_cpuclkl_rates));
rockchip_register_softrst(np, 15, reg_base + RK3368_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
rockchip_register_restart_notifier(ctx, RK3368_GLB_SRST_FST, NULL);
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rk3368_cru, "rockchip,rk3368-cru", rk3368_clk_init);
| linux-master | drivers/clk/rockchip/clk-rk3368.c |
// SPDX-License-Identifier: GPL-2.0
/*
* StarFive JH7110 System-Top-Group Clock Driver
*
* Copyright (C) 2022 Emil Renner Berthing <[email protected]>
* Copyright (C) 2022 StarFive Technology Co., Ltd.
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/starfive,jh7110-crg.h>
#include "clk-starfive-jh7110.h"
/* external clocks */
#define JH7110_STGCLK_OSC (JH7110_STGCLK_END + 0)
#define JH7110_STGCLK_HIFI4_CORE (JH7110_STGCLK_END + 1)
#define JH7110_STGCLK_STG_AXIAHB (JH7110_STGCLK_END + 2)
#define JH7110_STGCLK_USB_125M (JH7110_STGCLK_END + 3)
#define JH7110_STGCLK_CPU_BUS (JH7110_STGCLK_END + 4)
#define JH7110_STGCLK_HIFI4_AXI (JH7110_STGCLK_END + 5)
#define JH7110_STGCLK_NOCSTG_BUS (JH7110_STGCLK_END + 6)
#define JH7110_STGCLK_APB_BUS (JH7110_STGCLK_END + 7)
#define JH7110_STGCLK_EXT_END (JH7110_STGCLK_END + 8)
static const struct jh71x0_clk_data jh7110_stgclk_data[] = {
/* hifi4 */
JH71X0_GATE(JH7110_STGCLK_HIFI4_CLK_CORE, "hifi4_clk_core", 0,
JH7110_STGCLK_HIFI4_CORE),
/* usb */
JH71X0_GATE(JH7110_STGCLK_USB0_APB, "usb0_apb", 0, JH7110_STGCLK_APB_BUS),
JH71X0_GATE(JH7110_STGCLK_USB0_UTMI_APB, "usb0_utmi_apb", 0, JH7110_STGCLK_APB_BUS),
JH71X0_GATE(JH7110_STGCLK_USB0_AXI, "usb0_axi", 0, JH7110_STGCLK_STG_AXIAHB),
JH71X0_GDIV(JH7110_STGCLK_USB0_LPM, "usb0_lpm", 0, 2, JH7110_STGCLK_OSC),
JH71X0_GDIV(JH7110_STGCLK_USB0_STB, "usb0_stb", 0, 4, JH7110_STGCLK_OSC),
JH71X0_GATE(JH7110_STGCLK_USB0_APP_125, "usb0_app_125", 0, JH7110_STGCLK_USB_125M),
JH71X0__DIV(JH7110_STGCLK_USB0_REFCLK, "usb0_refclk", 2, JH7110_STGCLK_OSC),
/* pci-e */
JH71X0_GATE(JH7110_STGCLK_PCIE0_AXI_MST0, "pcie0_axi_mst0", 0,
JH7110_STGCLK_STG_AXIAHB),
JH71X0_GATE(JH7110_STGCLK_PCIE0_APB, "pcie0_apb", 0, JH7110_STGCLK_APB_BUS),
JH71X0_GATE(JH7110_STGCLK_PCIE0_TL, "pcie0_tl", 0, JH7110_STGCLK_STG_AXIAHB),
JH71X0_GATE(JH7110_STGCLK_PCIE1_AXI_MST0, "pcie1_axi_mst0", 0,
JH7110_STGCLK_STG_AXIAHB),
JH71X0_GATE(JH7110_STGCLK_PCIE1_APB, "pcie1_apb", 0, JH7110_STGCLK_APB_BUS),
JH71X0_GATE(JH7110_STGCLK_PCIE1_TL, "pcie1_tl", 0, JH7110_STGCLK_STG_AXIAHB),
JH71X0_GATE(JH7110_STGCLK_PCIE_SLV_MAIN, "pcie_slv_main", CLK_IS_CRITICAL,
JH7110_STGCLK_STG_AXIAHB),
/* security */
JH71X0_GATE(JH7110_STGCLK_SEC_AHB, "sec_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
JH71X0_GATE(JH7110_STGCLK_SEC_MISC_AHB, "sec_misc_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
/* stg mtrx */
JH71X0_GATE(JH7110_STGCLK_GRP0_MAIN, "mtrx_grp0_main", CLK_IS_CRITICAL,
JH7110_STGCLK_CPU_BUS),
JH71X0_GATE(JH7110_STGCLK_GRP0_BUS, "mtrx_grp0_bus", CLK_IS_CRITICAL,
JH7110_STGCLK_NOCSTG_BUS),
JH71X0_GATE(JH7110_STGCLK_GRP0_STG, "mtrx_grp0_stg", CLK_IS_CRITICAL,
JH7110_STGCLK_STG_AXIAHB),
JH71X0_GATE(JH7110_STGCLK_GRP1_MAIN, "mtrx_grp1_main", CLK_IS_CRITICAL,
JH7110_STGCLK_CPU_BUS),
JH71X0_GATE(JH7110_STGCLK_GRP1_BUS, "mtrx_grp1_bus", CLK_IS_CRITICAL,
JH7110_STGCLK_NOCSTG_BUS),
JH71X0_GATE(JH7110_STGCLK_GRP1_STG, "mtrx_grp1_stg", CLK_IS_CRITICAL,
JH7110_STGCLK_STG_AXIAHB),
JH71X0_GATE(JH7110_STGCLK_GRP1_HIFI, "mtrx_grp1_hifi", CLK_IS_CRITICAL,
JH7110_STGCLK_HIFI4_AXI),
/* e24_rvpi */
JH71X0_GDIV(JH7110_STGCLK_E2_RTC, "e2_rtc", 0, 24, JH7110_STGCLK_OSC),
JH71X0_GATE(JH7110_STGCLK_E2_CORE, "e2_core", 0, JH7110_STGCLK_STG_AXIAHB),
JH71X0_GATE(JH7110_STGCLK_E2_DBG, "e2_dbg", 0, JH7110_STGCLK_STG_AXIAHB),
/* dw_sgdma1p */
JH71X0_GATE(JH7110_STGCLK_DMA1P_AXI, "dma1p_axi", 0, JH7110_STGCLK_STG_AXIAHB),
JH71X0_GATE(JH7110_STGCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
};
static struct clk_hw *jh7110_stgclk_get(struct of_phandle_args *clkspec, void *data)
{
struct jh71x0_clk_priv *priv = data;
unsigned int idx = clkspec->args[0];
if (idx < JH7110_STGCLK_END)
return &priv->reg[idx].hw;
return ERR_PTR(-EINVAL);
}
static int jh7110_stgcrg_probe(struct platform_device *pdev)
{
struct jh71x0_clk_priv *priv;
unsigned int idx;
int ret;
priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7110_STGCLK_END),
GFP_KERNEL);
if (!priv)
return -ENOMEM;
spin_lock_init(&priv->rmw_lock);
priv->dev = &pdev->dev;
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
for (idx = 0; idx < JH7110_STGCLK_END; idx++) {
u32 max = jh7110_stgclk_data[idx].max;
struct clk_parent_data parents[4] = {};
struct clk_init_data init = {
.name = jh7110_stgclk_data[idx].name,
.ops = starfive_jh71x0_clk_ops(max),
.parent_data = parents,
.num_parents =
((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
.flags = jh7110_stgclk_data[idx].flags,
};
struct jh71x0_clk *clk = &priv->reg[idx];
const char *fw_name[JH7110_STGCLK_EXT_END - JH7110_STGCLK_END] = {
"osc",
"hifi4_core",
"stg_axiahb",
"usb_125m",
"cpu_bus",
"hifi4_axi",
"nocstg_bus",
"apb_bus"
};
unsigned int i;
for (i = 0; i < init.num_parents; i++) {
unsigned int pidx = jh7110_stgclk_data[idx].parents[i];
if (pidx < JH7110_STGCLK_END)
parents[i].hw = &priv->reg[pidx].hw;
else if (pidx < JH7110_STGCLK_EXT_END)
parents[i].fw_name = fw_name[pidx - JH7110_STGCLK_END];
}
clk->hw.init = &init;
clk->idx = idx;
clk->max_div = max & JH71X0_CLK_DIV_MASK;
ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
if (ret)
return ret;
}
ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_stgclk_get, priv);
if (ret)
return ret;
return jh7110_reset_controller_register(priv, "rst-stg", 2);
}
static const struct of_device_id jh7110_stgcrg_match[] = {
{ .compatible = "starfive,jh7110-stgcrg" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, jh7110_stgcrg_match);
static struct platform_driver jh7110_stgcrg_driver = {
.probe = jh7110_stgcrg_probe,
.driver = {
.name = "clk-starfive-jh7110-stg",
.of_match_table = jh7110_stgcrg_match,
},
};
module_platform_driver(jh7110_stgcrg_driver);
MODULE_AUTHOR("Xingyu Wu <[email protected]>");
MODULE_AUTHOR("Emil Renner Berthing <[email protected]>");
MODULE_DESCRIPTION("StarFive JH7110 System-Top-Group clock driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/starfive/clk-starfive-jh7110-stg.c |
// SPDX-License-Identifier: GPL-2.0
/*
* StarFive JH7110 System Clock Driver
*
* Copyright (C) 2022 Emil Renner Berthing <[email protected]>
* Copyright (C) 2022 StarFive Technology Co., Ltd.
*/
#include <linux/auxiliary_bus.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <soc/starfive/reset-starfive-jh71x0.h>
#include <dt-bindings/clock/starfive,jh7110-crg.h>
#include "clk-starfive-jh7110.h"
/* external clocks */
#define JH7110_SYSCLK_OSC (JH7110_SYSCLK_END + 0)
#define JH7110_SYSCLK_GMAC1_RMII_REFIN (JH7110_SYSCLK_END + 1)
#define JH7110_SYSCLK_GMAC1_RGMII_RXIN (JH7110_SYSCLK_END + 2)
#define JH7110_SYSCLK_I2STX_BCLK_EXT (JH7110_SYSCLK_END + 3)
#define JH7110_SYSCLK_I2STX_LRCK_EXT (JH7110_SYSCLK_END + 4)
#define JH7110_SYSCLK_I2SRX_BCLK_EXT (JH7110_SYSCLK_END + 5)
#define JH7110_SYSCLK_I2SRX_LRCK_EXT (JH7110_SYSCLK_END + 6)
#define JH7110_SYSCLK_TDM_EXT (JH7110_SYSCLK_END + 7)
#define JH7110_SYSCLK_MCLK_EXT (JH7110_SYSCLK_END + 8)
#define JH7110_SYSCLK_PLL0_OUT (JH7110_SYSCLK_END + 9)
#define JH7110_SYSCLK_PLL1_OUT (JH7110_SYSCLK_END + 10)
#define JH7110_SYSCLK_PLL2_OUT (JH7110_SYSCLK_END + 11)
static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
/* root */
JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2,
JH7110_SYSCLK_OSC,
JH7110_SYSCLK_PLL0_OUT),
JH71X0__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, JH7110_SYSCLK_CPU_ROOT),
JH71X0__DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2, JH7110_SYSCLK_CPU_CORE),
JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2,
JH7110_SYSCLK_PLL2_OUT,
JH7110_SYSCLK_PLL1_OUT),
JH71X0_MDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, 2,
JH7110_SYSCLK_PLL0_OUT,
JH7110_SYSCLK_PLL2_OUT),
JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2,
JH7110_SYSCLK_OSC,
JH7110_SYSCLK_PLL2_OUT),
JH71X0__DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3, JH7110_SYSCLK_BUS_ROOT),
JH71X0__DIV(JH7110_SYSCLK_AXI_CFG0, "axi_cfg0", 3, JH7110_SYSCLK_BUS_ROOT),
JH71X0__DIV(JH7110_SYSCLK_STG_AXIAHB, "stg_axiahb", 2, JH7110_SYSCLK_AXI_CFG0),
JH71X0_GATE(JH7110_SYSCLK_AHB0, "ahb0", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
JH71X0_GATE(JH7110_SYSCLK_AHB1, "ahb1", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
JH71X0__DIV(JH7110_SYSCLK_APB_BUS, "apb_bus", 8, JH7110_SYSCLK_STG_AXIAHB),
JH71X0_GATE(JH7110_SYSCLK_APB0, "apb0", CLK_IS_CRITICAL, JH7110_SYSCLK_APB_BUS),
JH71X0__DIV(JH7110_SYSCLK_PLL0_DIV2, "pll0_div2", 2, JH7110_SYSCLK_PLL0_OUT),
JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV2, "pll1_div2", 2, JH7110_SYSCLK_PLL1_OUT),
JH71X0__DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2, JH7110_SYSCLK_PLL2_OUT),
JH71X0__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, JH7110_SYSCLK_PLL2_OUT),
JH71X0__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, JH7110_SYSCLK_AUDIO_ROOT),
JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 2,
JH7110_SYSCLK_MCLK_INNER,
JH7110_SYSCLK_MCLK_EXT),
JH71X0_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", 0, JH7110_SYSCLK_MCLK_INNER),
JH71X0_MDIV(JH7110_SYSCLK_ISP_2X, "isp_2x", 8, 2,
JH7110_SYSCLK_PLL2_OUT,
JH7110_SYSCLK_PLL1_OUT),
JH71X0__DIV(JH7110_SYSCLK_ISP_AXI, "isp_axi", 4, JH7110_SYSCLK_ISP_2X),
JH71X0_GDIV(JH7110_SYSCLK_GCLK0, "gclk0", 0, 62, JH7110_SYSCLK_PLL0_DIV2),
JH71X0_GDIV(JH7110_SYSCLK_GCLK1, "gclk1", 0, 62, JH7110_SYSCLK_PLL1_DIV2),
JH71X0_GDIV(JH7110_SYSCLK_GCLK2, "gclk2", 0, 62, JH7110_SYSCLK_PLL2_DIV2),
/* cores */
JH71X0_GATE(JH7110_SYSCLK_CORE, "core", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
JH71X0_GATE(JH7110_SYSCLK_CORE1, "core1", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
JH71X0_GATE(JH7110_SYSCLK_CORE2, "core2", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
JH71X0_GATE(JH7110_SYSCLK_CORE3, "core3", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
JH71X0_GATE(JH7110_SYSCLK_CORE4, "core4", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
JH71X0_GATE(JH7110_SYSCLK_DEBUG, "debug", 0, JH7110_SYSCLK_CPU_BUS),
JH71X0__DIV(JH7110_SYSCLK_RTC_TOGGLE, "rtc_toggle", 6, JH7110_SYSCLK_OSC),
JH71X0_GATE(JH7110_SYSCLK_TRACE0, "trace0", 0, JH7110_SYSCLK_CPU_CORE),
JH71X0_GATE(JH7110_SYSCLK_TRACE1, "trace1", 0, JH7110_SYSCLK_CPU_CORE),
JH71X0_GATE(JH7110_SYSCLK_TRACE2, "trace2", 0, JH7110_SYSCLK_CPU_CORE),
JH71X0_GATE(JH7110_SYSCLK_TRACE3, "trace3", 0, JH7110_SYSCLK_CPU_CORE),
JH71X0_GATE(JH7110_SYSCLK_TRACE4, "trace4", 0, JH7110_SYSCLK_CPU_CORE),
JH71X0_GATE(JH7110_SYSCLK_TRACE_COM, "trace_com", 0, JH7110_SYSCLK_CPU_BUS),
/* noc */
JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_CPU_AXI, "noc_bus_cpu_axi", CLK_IS_CRITICAL,
JH7110_SYSCLK_CPU_BUS),
JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI, "noc_bus_axicfg0_axi", CLK_IS_CRITICAL,
JH7110_SYSCLK_AXI_CFG0),
/* ddr */
JH71X0__DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2, JH7110_SYSCLK_OSC),
JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2, JH7110_SYSCLK_PLL1_DIV2),
JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2, JH7110_SYSCLK_PLL1_DIV4),
JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4,
JH7110_SYSCLK_OSC_DIV2,
JH7110_SYSCLK_PLL1_DIV2,
JH7110_SYSCLK_PLL1_DIV4,
JH7110_SYSCLK_PLL1_DIV8),
JH71X0_GATE(JH7110_SYSCLK_DDR_AXI, "ddr_axi", CLK_IS_CRITICAL, JH7110_SYSCLK_DDR_BUS),
/* gpu */
JH71X0__DIV(JH7110_SYSCLK_GPU_CORE, "gpu_core", 7, JH7110_SYSCLK_GPU_ROOT),
JH71X0_GATE(JH7110_SYSCLK_GPU_CORE_CLK, "gpu_core_clk", 0, JH7110_SYSCLK_GPU_CORE),
JH71X0_GATE(JH7110_SYSCLK_GPU_SYS_CLK, "gpu_sys_clk", 0, JH7110_SYSCLK_ISP_AXI),
JH71X0_GATE(JH7110_SYSCLK_GPU_APB, "gpu_apb", 0, JH7110_SYSCLK_APB_BUS),
JH71X0_GDIV(JH7110_SYSCLK_GPU_RTC_TOGGLE, "gpu_rtc_toggle", 0, 12, JH7110_SYSCLK_OSC),
JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_GPU_AXI, "noc_bus_gpu_axi", 0, JH7110_SYSCLK_GPU_CORE),
/* isp */
JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_CORE, "isp_top_core", 0, JH7110_SYSCLK_ISP_2X),
JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_AXI, "isp_top_axi", 0, JH7110_SYSCLK_ISP_AXI),
JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_ISP_AXI, "noc_bus_isp_axi", CLK_IS_CRITICAL,
JH7110_SYSCLK_ISP_AXI),
/* hifi4 */
JH71X0__DIV(JH7110_SYSCLK_HIFI4_CORE, "hifi4_core", 15, JH7110_SYSCLK_BUS_ROOT),
JH71X0__DIV(JH7110_SYSCLK_HIFI4_AXI, "hifi4_axi", 2, JH7110_SYSCLK_HIFI4_CORE),
/* axi_cfg1 */
JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_MAIN, "axi_cfg1_main", CLK_IS_CRITICAL,
JH7110_SYSCLK_ISP_AXI),
JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_AHB, "axi_cfg1_ahb", CLK_IS_CRITICAL,
JH7110_SYSCLK_AHB0),
/* vout */
JH71X0_GATE(JH7110_SYSCLK_VOUT_SRC, "vout_src", 0, JH7110_SYSCLK_PLL2_OUT),
JH71X0__DIV(JH7110_SYSCLK_VOUT_AXI, "vout_axi", 7, JH7110_SYSCLK_PLL2_OUT),
JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_DISP_AXI, "noc_bus_disp_axi", 0, JH7110_SYSCLK_VOUT_AXI),
JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AHB, "vout_top_ahb", 0, JH7110_SYSCLK_AHB1),
JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AXI, "vout_top_axi", 0, JH7110_SYSCLK_VOUT_AXI),
JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK, "vout_top_hdmitx0_mclk", 0,
JH7110_SYSCLK_MCLK),
JH71X0__DIV(JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF, "vout_top_mipiphy_ref", 2,
JH7110_SYSCLK_OSC),
/* jpegc */
JH71X0__DIV(JH7110_SYSCLK_JPEGC_AXI, "jpegc_axi", 16, JH7110_SYSCLK_PLL2_OUT),
JH71X0_GATE(JH7110_SYSCLK_CODAJ12_AXI, "codaj12_axi", 0, JH7110_SYSCLK_JPEGC_AXI),
JH71X0_GDIV(JH7110_SYSCLK_CODAJ12_CORE, "codaj12_core", 0, 16, JH7110_SYSCLK_PLL2_OUT),
JH71X0_GATE(JH7110_SYSCLK_CODAJ12_APB, "codaj12_apb", 0, JH7110_SYSCLK_APB_BUS),
/* vdec */
JH71X0__DIV(JH7110_SYSCLK_VDEC_AXI, "vdec_axi", 7, JH7110_SYSCLK_BUS_ROOT),
JH71X0_GATE(JH7110_SYSCLK_WAVE511_AXI, "wave511_axi", 0, JH7110_SYSCLK_VDEC_AXI),
JH71X0_GDIV(JH7110_SYSCLK_WAVE511_BPU, "wave511_bpu", 0, 7, JH7110_SYSCLK_BUS_ROOT),
JH71X0_GDIV(JH7110_SYSCLK_WAVE511_VCE, "wave511_vce", 0, 7, JH7110_SYSCLK_PLL0_OUT),
JH71X0_GATE(JH7110_SYSCLK_WAVE511_APB, "wave511_apb", 0, JH7110_SYSCLK_APB_BUS),
JH71X0_GATE(JH7110_SYSCLK_VDEC_JPG, "vdec_jpg", 0, JH7110_SYSCLK_JPEGC_AXI),
JH71X0_GATE(JH7110_SYSCLK_VDEC_MAIN, "vdec_main", 0, JH7110_SYSCLK_VDEC_AXI),
JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VDEC_AXI, "noc_bus_vdec_axi", 0, JH7110_SYSCLK_VDEC_AXI),
/* venc */
JH71X0__DIV(JH7110_SYSCLK_VENC_AXI, "venc_axi", 15, JH7110_SYSCLK_PLL2_OUT),
JH71X0_GATE(JH7110_SYSCLK_WAVE420L_AXI, "wave420l_axi", 0, JH7110_SYSCLK_VENC_AXI),
JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_BPU, "wave420l_bpu", 0, 15, JH7110_SYSCLK_PLL2_OUT),
JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_VCE, "wave420l_vce", 0, 15, JH7110_SYSCLK_PLL2_OUT),
JH71X0_GATE(JH7110_SYSCLK_WAVE420L_APB, "wave420l_apb", 0, JH7110_SYSCLK_APB_BUS),
JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VENC_AXI, "noc_bus_venc_axi", 0, JH7110_SYSCLK_VENC_AXI),
/* axi_cfg0 */
JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN_DIV, "axi_cfg0_main_div", CLK_IS_CRITICAL,
JH7110_SYSCLK_AHB1),
JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN, "axi_cfg0_main", CLK_IS_CRITICAL,
JH7110_SYSCLK_AXI_CFG0),
JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_HIFI4, "axi_cfg0_hifi4", CLK_IS_CRITICAL,
JH7110_SYSCLK_HIFI4_AXI),
/* intmem */
JH71X0_GATE(JH7110_SYSCLK_AXIMEM2_AXI, "aximem2_axi", 0, JH7110_SYSCLK_AXI_CFG0),
/* qspi */
JH71X0_GATE(JH7110_SYSCLK_QSPI_AHB, "qspi_ahb", 0, JH7110_SYSCLK_AHB1),
JH71X0_GATE(JH7110_SYSCLK_QSPI_APB, "qspi_apb", 0, JH7110_SYSCLK_APB_BUS),
JH71X0__DIV(JH7110_SYSCLK_QSPI_REF_SRC, "qspi_ref_src", 16, JH7110_SYSCLK_PLL0_OUT),
JH71X0_GMUX(JH7110_SYSCLK_QSPI_REF, "qspi_ref", 0, 2,
JH7110_SYSCLK_OSC,
JH7110_SYSCLK_QSPI_REF_SRC),
/* sdio */
JH71X0_GATE(JH7110_SYSCLK_SDIO0_AHB, "sdio0_ahb", 0, JH7110_SYSCLK_AHB0),
JH71X0_GATE(JH7110_SYSCLK_SDIO1_AHB, "sdio1_ahb", 0, JH7110_SYSCLK_AHB0),
JH71X0_GDIV(JH7110_SYSCLK_SDIO0_SDCARD, "sdio0_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0),
JH71X0_GDIV(JH7110_SYSCLK_SDIO1_SDCARD, "sdio1_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0),
/* stg */
JH71X0__DIV(JH7110_SYSCLK_USB_125M, "usb_125m", 15, JH7110_SYSCLK_PLL0_OUT),
JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_STG_AXI, "noc_bus_stg_axi", CLK_IS_CRITICAL,
JH7110_SYSCLK_NOCSTG_BUS),
/* gmac1 */
JH71X0_GATE(JH7110_SYSCLK_GMAC1_AHB, "gmac1_ahb", 0, JH7110_SYSCLK_AHB0),
JH71X0_GATE(JH7110_SYSCLK_GMAC1_AXI, "gmac1_axi", 0, JH7110_SYSCLK_STG_AXIAHB),
JH71X0__DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", 7, JH7110_SYSCLK_PLL0_OUT),
JH71X0__DIV(JH7110_SYSCLK_GMAC1_GTXCLK, "gmac1_gtxclk", 15, JH7110_SYSCLK_PLL0_OUT),
JH71X0__DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30,
JH7110_SYSCLK_GMAC1_RMII_REFIN),
JH71X0_GDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2,
JH7110_SYSCLK_GMAC1_RGMII_RXIN,
JH7110_SYSCLK_GMAC1_RMII_RTX),
JH71X0__INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", JH7110_SYSCLK_GMAC1_RX),
JH71X0_GMUX(JH7110_SYSCLK_GMAC1_TX, "gmac1_tx",
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2,
JH7110_SYSCLK_GMAC1_GTXCLK,
JH7110_SYSCLK_GMAC1_RMII_RTX),
JH71X0__INV(JH7110_SYSCLK_GMAC1_TX_INV, "gmac1_tx_inv", JH7110_SYSCLK_GMAC1_TX),
JH71X0_GATE(JH7110_SYSCLK_GMAC1_GTXC, "gmac1_gtxc", 0, JH7110_SYSCLK_GMAC1_GTXCLK),
/* gmac0 */
JH71X0_GDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk", 0, 15, JH7110_SYSCLK_PLL0_OUT),
JH71X0_GDIV(JH7110_SYSCLK_GMAC0_PTP, "gmac0_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
JH71X0_GDIV(JH7110_SYSCLK_GMAC_PHY, "gmac_phy", 0, 31, JH7110_SYSCLK_GMAC_SRC),
JH71X0_GATE(JH7110_SYSCLK_GMAC0_GTXC, "gmac0_gtxc", 0, JH7110_SYSCLK_GMAC0_GTXCLK),
/* apb misc */
JH71X0_GATE(JH7110_SYSCLK_IOMUX_APB, "iomux_apb", 0, JH7110_SYSCLK_APB_BUS),
JH71X0_GATE(JH7110_SYSCLK_MAILBOX_APB, "mailbox_apb", 0, JH7110_SYSCLK_APB_BUS),
JH71X0_GATE(JH7110_SYSCLK_INT_CTRL_APB, "int_ctrl_apb", 0, JH7110_SYSCLK_APB_BUS),
/* can0 */
JH71X0_GATE(JH7110_SYSCLK_CAN0_APB, "can0_apb", 0, JH7110_SYSCLK_APB_BUS),
JH71X0_GDIV(JH7110_SYSCLK_CAN0_TIMER, "can0_timer", 0, 24, JH7110_SYSCLK_OSC),
JH71X0_GDIV(JH7110_SYSCLK_CAN0_CAN, "can0_can", 0, 63, JH7110_SYSCLK_PERH_ROOT),
/* can1 */
JH71X0_GATE(JH7110_SYSCLK_CAN1_APB, "can1_apb", 0, JH7110_SYSCLK_APB_BUS),
JH71X0_GDIV(JH7110_SYSCLK_CAN1_TIMER, "can1_timer", 0, 24, JH7110_SYSCLK_OSC),
JH71X0_GDIV(JH7110_SYSCLK_CAN1_CAN, "can1_can", 0, 63, JH7110_SYSCLK_PERH_ROOT),
/* pwm */
JH71X0_GATE(JH7110_SYSCLK_PWM_APB, "pwm_apb", 0, JH7110_SYSCLK_APB_BUS),
/* wdt */
JH71X0_GATE(JH7110_SYSCLK_WDT_APB, "wdt_apb", 0, JH7110_SYSCLK_APB_BUS),
JH71X0_GATE(JH7110_SYSCLK_WDT_CORE, "wdt_core", 0, JH7110_SYSCLK_OSC),
/* timer */
JH71X0_GATE(JH7110_SYSCLK_TIMER_APB, "timer_apb", 0, JH7110_SYSCLK_APB_BUS),
JH71X0_GATE(JH7110_SYSCLK_TIMER0, "timer0", 0, JH7110_SYSCLK_OSC),
JH71X0_GATE(JH7110_SYSCLK_TIMER1, "timer1", 0, JH7110_SYSCLK_OSC),
JH71X0_GATE(JH7110_SYSCLK_TIMER2, "timer2", 0, JH7110_SYSCLK_OSC),
JH71X0_GATE(JH7110_SYSCLK_TIMER3, "timer3", 0, JH7110_SYSCLK_OSC),
/* temp sensor */
JH71X0_GATE(JH7110_SYSCLK_TEMP_APB, "temp_apb", 0, JH7110_SYSCLK_APB_BUS),
JH71X0_GDIV(JH7110_SYSCLK_TEMP_CORE, "temp_core", 0, 24, JH7110_SYSCLK_OSC),
/* spi */
JH71X0_GATE(JH7110_SYSCLK_SPI0_APB, "spi0_apb", 0, JH7110_SYSCLK_APB0),
JH71X0_GATE(JH7110_SYSCLK_SPI1_APB, "spi1_apb", 0, JH7110_SYSCLK_APB0),
JH71X0_GATE(JH7110_SYSCLK_SPI2_APB, "spi2_apb", 0, JH7110_SYSCLK_APB0),
JH71X0_GATE(JH7110_SYSCLK_SPI3_APB, "spi3_apb", 0, JH7110_SYSCLK_APB_BUS),
JH71X0_GATE(JH7110_SYSCLK_SPI4_APB, "spi4_apb", 0, JH7110_SYSCLK_APB_BUS),
JH71X0_GATE(JH7110_SYSCLK_SPI5_APB, "spi5_apb", 0, JH7110_SYSCLK_APB_BUS),
JH71X0_GATE(JH7110_SYSCLK_SPI6_APB, "spi6_apb", 0, JH7110_SYSCLK_APB_BUS),
/* i2c */
JH71X0_GATE(JH7110_SYSCLK_I2C0_APB, "i2c0_apb", 0, JH7110_SYSCLK_APB0),
JH71X0_GATE(JH7110_SYSCLK_I2C1_APB, "i2c1_apb", 0, JH7110_SYSCLK_APB0),
JH71X0_GATE(JH7110_SYSCLK_I2C2_APB, "i2c2_apb", 0, JH7110_SYSCLK_APB0),
JH71X0_GATE(JH7110_SYSCLK_I2C3_APB, "i2c3_apb", 0, JH7110_SYSCLK_APB_BUS),
JH71X0_GATE(JH7110_SYSCLK_I2C4_APB, "i2c4_apb", 0, JH7110_SYSCLK_APB_BUS),
JH71X0_GATE(JH7110_SYSCLK_I2C5_APB, "i2c5_apb", 0, JH7110_SYSCLK_APB_BUS),
JH71X0_GATE(JH7110_SYSCLK_I2C6_APB, "i2c6_apb", 0, JH7110_SYSCLK_APB_BUS),
/* uart */
JH71X0_GATE(JH7110_SYSCLK_UART0_APB, "uart0_apb", 0, JH7110_SYSCLK_APB0),
JH71X0_GATE(JH7110_SYSCLK_UART0_CORE, "uart0_core", 0, JH7110_SYSCLK_OSC),
JH71X0_GATE(JH7110_SYSCLK_UART1_APB, "uart1_apb", 0, JH7110_SYSCLK_APB0),
JH71X0_GATE(JH7110_SYSCLK_UART1_CORE, "uart1_core", 0, JH7110_SYSCLK_OSC),
JH71X0_GATE(JH7110_SYSCLK_UART2_APB, "uart2_apb", 0, JH7110_SYSCLK_APB0),
JH71X0_GATE(JH7110_SYSCLK_UART2_CORE, "uart2_core", 0, JH7110_SYSCLK_OSC),
JH71X0_GATE(JH7110_SYSCLK_UART3_APB, "uart3_apb", 0, JH7110_SYSCLK_APB0),
JH71X0_GDIV(JH7110_SYSCLK_UART3_CORE, "uart3_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
JH71X0_GATE(JH7110_SYSCLK_UART4_APB, "uart4_apb", 0, JH7110_SYSCLK_APB0),
JH71X0_GDIV(JH7110_SYSCLK_UART4_CORE, "uart4_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
JH71X0_GATE(JH7110_SYSCLK_UART5_APB, "uart5_apb", 0, JH7110_SYSCLK_APB0),
JH71X0_GDIV(JH7110_SYSCLK_UART5_CORE, "uart5_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
/* pwmdac */
JH71X0_GATE(JH7110_SYSCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7110_SYSCLK_APB0),
JH71X0_GDIV(JH7110_SYSCLK_PWMDAC_CORE, "pwmdac_core", 0, 256, JH7110_SYSCLK_AUDIO_ROOT),
/* spdif */
JH71X0_GATE(JH7110_SYSCLK_SPDIF_APB, "spdif_apb", 0, JH7110_SYSCLK_APB0),
JH71X0_GATE(JH7110_SYSCLK_SPDIF_CORE, "spdif_core", 0, JH7110_SYSCLK_MCLK),
/* i2stx0 */
JH71X0_GATE(JH7110_SYSCLK_I2STX0_APB, "i2stx0_apb", 0, JH7110_SYSCLK_APB0),
JH71X0_GDIV(JH7110_SYSCLK_I2STX0_BCLK_MST, "i2stx0_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_MST_INV, "i2stx0_bclk_mst_inv",
JH7110_SYSCLK_I2STX0_BCLK_MST),
JH71X0_MDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, 2,
JH7110_SYSCLK_I2STX0_BCLK_MST_INV,
JH7110_SYSCLK_I2STX0_BCLK_MST),
JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 2,
JH7110_SYSCLK_I2STX0_BCLK_MST,
JH7110_SYSCLK_I2STX_BCLK_EXT),
JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv", JH7110_SYSCLK_I2STX0_BCLK),
JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2,
JH7110_SYSCLK_I2STX0_LRCK_MST,
JH7110_SYSCLK_I2STX_LRCK_EXT),
/* i2stx1 */
JH71X0_GATE(JH7110_SYSCLK_I2STX1_APB, "i2stx1_apb", 0, JH7110_SYSCLK_APB0),
JH71X0_GDIV(JH7110_SYSCLK_I2STX1_BCLK_MST, "i2stx1_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_MST_INV, "i2stx1_bclk_mst_inv",
JH7110_SYSCLK_I2STX1_BCLK_MST),
JH71X0_MDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, 2,
JH7110_SYSCLK_I2STX1_BCLK_MST_INV,
JH7110_SYSCLK_I2STX1_BCLK_MST),
JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2,
JH7110_SYSCLK_I2STX1_BCLK_MST,
JH7110_SYSCLK_I2STX_BCLK_EXT),
JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv", JH7110_SYSCLK_I2STX1_BCLK),
JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2,
JH7110_SYSCLK_I2STX1_LRCK_MST,
JH7110_SYSCLK_I2STX_LRCK_EXT),
/* i2srx */
JH71X0_GATE(JH7110_SYSCLK_I2SRX_APB, "i2srx_apb", 0, JH7110_SYSCLK_APB0),
JH71X0_GDIV(JH7110_SYSCLK_I2SRX_BCLK_MST, "i2srx_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_MST_INV, "i2srx_bclk_mst_inv",
JH7110_SYSCLK_I2SRX_BCLK_MST),
JH71X0_MDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, 2,
JH7110_SYSCLK_I2SRX_BCLK_MST_INV,
JH7110_SYSCLK_I2SRX_BCLK_MST),
JH71X0__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 2,
JH7110_SYSCLK_I2SRX_BCLK_MST,
JH7110_SYSCLK_I2SRX_BCLK_EXT),
JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv", JH7110_SYSCLK_I2SRX_BCLK),
JH71X0__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 2,
JH7110_SYSCLK_I2SRX_LRCK_MST,
JH7110_SYSCLK_I2SRX_LRCK_EXT),
/* pdm */
JH71X0_GDIV(JH7110_SYSCLK_PDM_DMIC, "pdm_dmic", 0, 64, JH7110_SYSCLK_MCLK),
JH71X0_GATE(JH7110_SYSCLK_PDM_APB, "pdm_apb", 0, JH7110_SYSCLK_APB0),
/* tdm */
JH71X0_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0, JH7110_SYSCLK_AHB0),
JH71X0_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0, JH7110_SYSCLK_APB0),
JH71X0_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64, JH7110_SYSCLK_MCLK),
JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 2,
JH7110_SYSCLK_TDM_INTERNAL,
JH7110_SYSCLK_TDM_EXT),
JH71X0__INV(JH7110_SYSCLK_TDM_TDM_INV, "tdm_tdm_inv", JH7110_SYSCLK_TDM_TDM),
/* jtag */
JH71X0__DIV(JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG, "jtag_certification_trng", 4,
JH7110_SYSCLK_OSC),
};
static struct clk_hw *jh7110_sysclk_get(struct of_phandle_args *clkspec, void *data)
{
struct jh71x0_clk_priv *priv = data;
unsigned int idx = clkspec->args[0];
if (idx < JH7110_SYSCLK_END)
return &priv->reg[idx].hw;
return ERR_PTR(-EINVAL);
}
static void jh7110_reset_unregister_adev(void *_adev)
{
struct auxiliary_device *adev = _adev;
auxiliary_device_delete(adev);
auxiliary_device_uninit(adev);
}
static void jh7110_reset_adev_release(struct device *dev)
{
struct auxiliary_device *adev = to_auxiliary_dev(dev);
struct jh71x0_reset_adev *rdev = to_jh71x0_reset_adev(adev);
kfree(rdev);
}
int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
const char *adev_name,
u32 adev_id)
{
struct jh71x0_reset_adev *rdev;
struct auxiliary_device *adev;
int ret;
rdev = kzalloc(sizeof(*rdev), GFP_KERNEL);
if (!rdev)
return -ENOMEM;
rdev->base = priv->base;
adev = &rdev->adev;
adev->name = adev_name;
adev->dev.parent = priv->dev;
adev->dev.release = jh7110_reset_adev_release;
adev->id = adev_id;
ret = auxiliary_device_init(adev);
if (ret)
return ret;
ret = auxiliary_device_add(adev);
if (ret) {
auxiliary_device_uninit(adev);
return ret;
}
return devm_add_action_or_reset(priv->dev,
jh7110_reset_unregister_adev, adev);
}
EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
static int __init jh7110_syscrg_probe(struct platform_device *pdev)
{
struct jh71x0_clk_priv *priv;
unsigned int idx;
int ret;
struct clk *pllclk;
priv = devm_kzalloc(&pdev->dev,
struct_size(priv, reg, JH7110_SYSCLK_END),
GFP_KERNEL);
if (!priv)
return -ENOMEM;
spin_lock_init(&priv->rmw_lock);
priv->dev = &pdev->dev;
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
/* Use fixed factor clocks if can not get the PLL clocks from DTS */
pllclk = clk_get(priv->dev, "pll0_out");
if (IS_ERR(pllclk)) {
/* 24MHz -> 1000.0MHz */
priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
"osc", 0, 125, 3);
if (IS_ERR(priv->pll[0]))
return PTR_ERR(priv->pll[0]);
} else {
clk_put(pllclk);
priv->pll[0] = NULL;
}
pllclk = clk_get(priv->dev, "pll1_out");
if (IS_ERR(pllclk)) {
/* 24MHz -> 1066.0MHz */
priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
"osc", 0, 533, 12);
if (IS_ERR(priv->pll[1]))
return PTR_ERR(priv->pll[1]);
} else {
clk_put(pllclk);
priv->pll[1] = NULL;
}
pllclk = clk_get(priv->dev, "pll2_out");
if (IS_ERR(pllclk)) {
/* 24MHz -> 1188.0MHz */
priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
"osc", 0, 99, 2);
if (IS_ERR(priv->pll[2]))
return PTR_ERR(priv->pll[2]);
} else {
clk_put(pllclk);
priv->pll[2] = NULL;
}
for (idx = 0; idx < JH7110_SYSCLK_END; idx++) {
u32 max = jh7110_sysclk_data[idx].max;
struct clk_parent_data parents[4] = {};
struct clk_init_data init = {
.name = jh7110_sysclk_data[idx].name,
.ops = starfive_jh71x0_clk_ops(max),
.parent_data = parents,
.num_parents =
((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
.flags = jh7110_sysclk_data[idx].flags,
};
struct jh71x0_clk *clk = &priv->reg[idx];
unsigned int i;
for (i = 0; i < init.num_parents; i++) {
unsigned int pidx = jh7110_sysclk_data[idx].parents[i];
if (pidx < JH7110_SYSCLK_END)
parents[i].hw = &priv->reg[pidx].hw;
else if (pidx == JH7110_SYSCLK_OSC)
parents[i].fw_name = "osc";
else if (pidx == JH7110_SYSCLK_GMAC1_RMII_REFIN)
parents[i].fw_name = "gmac1_rmii_refin";
else if (pidx == JH7110_SYSCLK_GMAC1_RGMII_RXIN)
parents[i].fw_name = "gmac1_rgmii_rxin";
else if (pidx == JH7110_SYSCLK_I2STX_BCLK_EXT)
parents[i].fw_name = "i2stx_bclk_ext";
else if (pidx == JH7110_SYSCLK_I2STX_LRCK_EXT)
parents[i].fw_name = "i2stx_lrck_ext";
else if (pidx == JH7110_SYSCLK_I2SRX_BCLK_EXT)
parents[i].fw_name = "i2srx_bclk_ext";
else if (pidx == JH7110_SYSCLK_I2SRX_LRCK_EXT)
parents[i].fw_name = "i2srx_lrck_ext";
else if (pidx == JH7110_SYSCLK_TDM_EXT)
parents[i].fw_name = "tdm_ext";
else if (pidx == JH7110_SYSCLK_MCLK_EXT)
parents[i].fw_name = "mclk_ext";
else if (pidx == JH7110_SYSCLK_PLL0_OUT && !priv->pll[0])
parents[i].fw_name = "pll0_out";
else if (pidx == JH7110_SYSCLK_PLL1_OUT && !priv->pll[1])
parents[i].fw_name = "pll1_out";
else if (pidx == JH7110_SYSCLK_PLL2_OUT && !priv->pll[2])
parents[i].fw_name = "pll2_out";
else
parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT];
}
clk->hw.init = &init;
clk->idx = idx;
clk->max_div = max & JH71X0_CLK_DIV_MASK;
ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
if (ret)
return ret;
}
ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_sysclk_get, priv);
if (ret)
return ret;
return jh7110_reset_controller_register(priv, "rst-sys", 0);
}
static const struct of_device_id jh7110_syscrg_match[] = {
{ .compatible = "starfive,jh7110-syscrg" },
{ /* sentinel */ }
};
static struct platform_driver jh7110_syscrg_driver = {
.driver = {
.name = "clk-starfive-jh7110-sys",
.of_match_table = jh7110_syscrg_match,
.suppress_bind_attrs = true,
},
};
builtin_platform_driver_probe(jh7110_syscrg_driver, jh7110_syscrg_probe);
| linux-master | drivers/clk/starfive/clk-starfive-jh7110-sys.c |
// SPDX-License-Identifier: GPL-2.0
/*
* StarFive JH7110 Video-Output Clock Driver
*
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <dt-bindings/clock/starfive,jh7110-crg.h>
#include "clk-starfive-jh7110.h"
/* external clocks */
#define JH7110_VOUTCLK_VOUT_SRC (JH7110_VOUTCLK_END + 0)
#define JH7110_VOUTCLK_VOUT_TOP_AHB (JH7110_VOUTCLK_END + 1)
#define JH7110_VOUTCLK_VOUT_TOP_AXI (JH7110_VOUTCLK_END + 2)
#define JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK (JH7110_VOUTCLK_END + 3)
#define JH7110_VOUTCLK_I2STX0_BCLK (JH7110_VOUTCLK_END + 4)
#define JH7110_VOUTCLK_HDMITX0_PIXELCLK (JH7110_VOUTCLK_END + 5)
#define JH7110_VOUTCLK_EXT_END (JH7110_VOUTCLK_END + 6)
static struct clk_bulk_data jh7110_vout_top_clks[] = {
{ .id = "vout_src" },
{ .id = "vout_top_ahb" }
};
static const struct jh71x0_clk_data jh7110_voutclk_data[] = {
/* divider */
JH71X0__DIV(JH7110_VOUTCLK_APB, "apb", 8, JH7110_VOUTCLK_VOUT_TOP_AHB),
JH71X0__DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, JH7110_VOUTCLK_VOUT_SRC),
JH71X0__DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, JH7110_VOUTCLK_VOUT_SRC),
JH71X0__DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, JH7110_VOUTCLK_VOUT_TOP_AHB),
/* dc8200 */
JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB),
JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2,
JH7110_VOUTCLK_DC8200_PIX,
JH7110_VOUTCLK_HDMITX0_PIXELCLK),
JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2,
JH7110_VOUTCLK_DC8200_PIX,
JH7110_VOUTCLK_HDMITX0_PIXELCLK),
/* LCD */
JH71X0_GMUX(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", 0, 2,
JH7110_VOUTCLK_DC8200_PIX0,
JH7110_VOUTCLK_DC8200_PIX1),
/* dsiTx */
JH71X0_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", 0, JH7110_VOUTCLK_DSI_SYS),
JH71X0_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", 0, JH7110_VOUTCLK_DSI_SYS),
JH71X0_GMUX(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", 0, 2,
JH7110_VOUTCLK_DC8200_PIX,
JH7110_VOUTCLK_HDMITX0_PIXELCLK),
JH71X0_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", 0, JH7110_VOUTCLK_TX_ESC),
/* mipitx DPHY */
JH71X0_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", 0,
JH7110_VOUTCLK_TX_ESC),
/* hdmi */
JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", 0,
JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK),
JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", 0,
JH7110_VOUTCLK_I2STX0_BCLK),
JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", 0, JH7110_VOUTCLK_APB),
};
static int jh7110_vout_top_rst_init(struct jh71x0_clk_priv *priv)
{
struct reset_control *top_rst;
/* The reset should be shared and other Vout modules will use its. */
top_rst = devm_reset_control_get_shared(priv->dev, NULL);
if (IS_ERR(top_rst))
return dev_err_probe(priv->dev, PTR_ERR(top_rst), "failed to get top reset\n");
return reset_control_deassert(top_rst);
}
static struct clk_hw *jh7110_voutclk_get(struct of_phandle_args *clkspec, void *data)
{
struct jh71x0_clk_priv *priv = data;
unsigned int idx = clkspec->args[0];
if (idx < JH7110_VOUTCLK_END)
return &priv->reg[idx].hw;
return ERR_PTR(-EINVAL);
}
#ifdef CONFIG_PM
static int jh7110_voutcrg_suspend(struct device *dev)
{
struct jh7110_top_sysclk *top = dev_get_drvdata(dev);
clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks);
return 0;
}
static int jh7110_voutcrg_resume(struct device *dev)
{
struct jh7110_top_sysclk *top = dev_get_drvdata(dev);
return clk_bulk_prepare_enable(top->top_clks_num, top->top_clks);
}
static const struct dev_pm_ops jh7110_voutcrg_pm_ops = {
RUNTIME_PM_OPS(jh7110_voutcrg_suspend, jh7110_voutcrg_resume, NULL)
};
#endif
static int jh7110_voutcrg_probe(struct platform_device *pdev)
{
struct jh71x0_clk_priv *priv;
struct jh7110_top_sysclk *top;
unsigned int idx;
int ret;
priv = devm_kzalloc(&pdev->dev,
struct_size(priv, reg, JH7110_VOUTCLK_END),
GFP_KERNEL);
if (!priv)
return -ENOMEM;
top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL);
if (!top)
return -ENOMEM;
spin_lock_init(&priv->rmw_lock);
priv->dev = &pdev->dev;
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
top->top_clks = jh7110_vout_top_clks;
top->top_clks_num = ARRAY_SIZE(jh7110_vout_top_clks);
ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks);
if (ret)
return dev_err_probe(priv->dev, ret, "failed to get top clocks\n");
dev_set_drvdata(priv->dev, top);
/* enable power domain and clocks */
pm_runtime_enable(priv->dev);
ret = pm_runtime_get_sync(priv->dev);
if (ret < 0)
return dev_err_probe(priv->dev, ret, "failed to turn on power\n");
ret = jh7110_vout_top_rst_init(priv);
if (ret)
goto err_exit;
for (idx = 0; idx < JH7110_VOUTCLK_END; idx++) {
u32 max = jh7110_voutclk_data[idx].max;
struct clk_parent_data parents[4] = {};
struct clk_init_data init = {
.name = jh7110_voutclk_data[idx].name,
.ops = starfive_jh71x0_clk_ops(max),
.parent_data = parents,
.num_parents =
((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
.flags = jh7110_voutclk_data[idx].flags,
};
struct jh71x0_clk *clk = &priv->reg[idx];
unsigned int i;
const char *fw_name[JH7110_VOUTCLK_EXT_END - JH7110_VOUTCLK_END] = {
"vout_src",
"vout_top_ahb",
"vout_top_axi",
"vout_top_hdmitx0_mclk",
"i2stx0_bclk",
"hdmitx0_pixelclk"
};
for (i = 0; i < init.num_parents; i++) {
unsigned int pidx = jh7110_voutclk_data[idx].parents[i];
if (pidx < JH7110_VOUTCLK_END)
parents[i].hw = &priv->reg[pidx].hw;
else if (pidx < JH7110_VOUTCLK_EXT_END)
parents[i].fw_name = fw_name[pidx - JH7110_VOUTCLK_END];
}
clk->hw.init = &init;
clk->idx = idx;
clk->max_div = max & JH71X0_CLK_DIV_MASK;
ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
if (ret)
goto err_exit;
}
ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_voutclk_get, priv);
if (ret)
goto err_exit;
ret = jh7110_reset_controller_register(priv, "rst-vo", 4);
if (ret)
goto err_exit;
return 0;
err_exit:
pm_runtime_put_sync(priv->dev);
pm_runtime_disable(priv->dev);
return ret;
}
static int jh7110_voutcrg_remove(struct platform_device *pdev)
{
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
return 0;
}
static const struct of_device_id jh7110_voutcrg_match[] = {
{ .compatible = "starfive,jh7110-voutcrg" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, jh7110_voutcrg_match);
static struct platform_driver jh7110_voutcrg_driver = {
.probe = jh7110_voutcrg_probe,
.remove = jh7110_voutcrg_remove,
.driver = {
.name = "clk-starfive-jh7110-vout",
.of_match_table = jh7110_voutcrg_match,
.pm = pm_ptr(&jh7110_voutcrg_pm_ops),
},
};
module_platform_driver(jh7110_voutcrg_driver);
MODULE_AUTHOR("Xingyu Wu <[email protected]>");
MODULE_DESCRIPTION("StarFive JH7110 Video-Output clock driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/starfive/clk-starfive-jh7110-vout.c |
// SPDX-License-Identifier: GPL-2.0
/*
* StarFive JH7100 Audio Clock Driver
*
* Copyright (C) 2021 Emil Renner Berthing <[email protected]>
*/
#include <linux/bits.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/starfive-jh7100-audio.h>
#include "clk-starfive-jh71x0.h"
/* external clocks */
#define JH7100_AUDCLK_AUDIO_SRC (JH7100_AUDCLK_END + 0)
#define JH7100_AUDCLK_AUDIO_12288 (JH7100_AUDCLK_END + 1)
#define JH7100_AUDCLK_DOM7AHB_BUS (JH7100_AUDCLK_END + 2)
#define JH7100_AUDCLK_I2SADC_BCLK_IOPAD (JH7100_AUDCLK_END + 3)
#define JH7100_AUDCLK_I2SADC_LRCLK_IOPAD (JH7100_AUDCLK_END + 4)
#define JH7100_AUDCLK_I2SDAC_BCLK_IOPAD (JH7100_AUDCLK_END + 5)
#define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD (JH7100_AUDCLK_END + 6)
#define JH7100_AUDCLK_VAD_INTMEM (JH7100_AUDCLK_END + 7)
static const struct jh71x0_clk_data jh7100_audclk_data[] = {
JH71X0__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
JH7100_AUDCLK_AUDIO_SRC,
JH7100_AUDCLK_AUDIO_12288),
JH71X0__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
JH7100_AUDCLK_AUDIO_SRC,
JH7100_AUDCLK_AUDIO_12288),
JH71X0_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
JH71X0_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
JH7100_AUDCLK_ADC_MCLK,
JH7100_AUDCLK_I2SADC_BCLK_IOPAD),
JH71X0__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
JH71X0_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
JH7100_AUDCLK_I2SADC_BCLK_N,
JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,
JH7100_AUDCLK_I2SADC_BCLK),
JH71X0_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
JH71X0__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
JH7100_AUDCLK_AUDIO_SRC,
JH7100_AUDCLK_AUDIO_12288),
JH71X0_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
JH71X0__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
JH7100_AUDCLK_AUDIO_SRC,
JH7100_AUDCLK_AUDIO_12288),
JH71X0_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
JH71X0_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
JH71X0__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
JH7100_AUDCLK_AUDIO_SRC,
JH7100_AUDCLK_AUDIO_12288),
JH71X0_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
JH7100_AUDCLK_DAC_MCLK,
JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
JH71X0__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
JH7100_AUDCLK_I2S1_MCLK,
JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
JH71X0_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
JH71X0_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
JH7100_AUDCLK_I2S1_MCLK,
JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
JH71X0__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
JH71X0_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
JH7100_AUDCLK_I2S1_BCLK_N,
JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),
JH71X0_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
JH71X0__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
JH71X0_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
JH71X0_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
JH71X0_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
JH71X0_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
JH71X0__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
JH7100_AUDCLK_VAD_INTMEM,
JH7100_AUDCLK_AUDIO_12288),
};
static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data)
{
struct jh71x0_clk_priv *priv = data;
unsigned int idx = clkspec->args[0];
if (idx < JH7100_AUDCLK_END)
return &priv->reg[idx].hw;
return ERR_PTR(-EINVAL);
}
static int jh7100_audclk_probe(struct platform_device *pdev)
{
struct jh71x0_clk_priv *priv;
unsigned int idx;
int ret;
priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7100_AUDCLK_END), GFP_KERNEL);
if (!priv)
return -ENOMEM;
spin_lock_init(&priv->rmw_lock);
priv->dev = &pdev->dev;
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
for (idx = 0; idx < JH7100_AUDCLK_END; idx++) {
u32 max = jh7100_audclk_data[idx].max;
struct clk_parent_data parents[4] = {};
struct clk_init_data init = {
.name = jh7100_audclk_data[idx].name,
.ops = starfive_jh71x0_clk_ops(max),
.parent_data = parents,
.num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
.flags = jh7100_audclk_data[idx].flags,
};
struct jh71x0_clk *clk = &priv->reg[idx];
unsigned int i;
for (i = 0; i < init.num_parents; i++) {
unsigned int pidx = jh7100_audclk_data[idx].parents[i];
if (pidx < JH7100_AUDCLK_END)
parents[i].hw = &priv->reg[pidx].hw;
else if (pidx == JH7100_AUDCLK_AUDIO_SRC)
parents[i].fw_name = "audio_src";
else if (pidx == JH7100_AUDCLK_AUDIO_12288)
parents[i].fw_name = "audio_12288";
else if (pidx == JH7100_AUDCLK_DOM7AHB_BUS)
parents[i].fw_name = "dom7ahb_bus";
}
clk->hw.init = &init;
clk->idx = idx;
clk->max_div = max & JH71X0_CLK_DIV_MASK;
ret = devm_clk_hw_register(priv->dev, &clk->hw);
if (ret)
return ret;
}
return devm_of_clk_add_hw_provider(priv->dev, jh7100_audclk_get, priv);
}
static const struct of_device_id jh7100_audclk_match[] = {
{ .compatible = "starfive,jh7100-audclk" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, jh7100_audclk_match);
static struct platform_driver jh7100_audclk_driver = {
.probe = jh7100_audclk_probe,
.driver = {
.name = "clk-starfive-jh7100-audio",
.of_match_table = jh7100_audclk_match,
},
};
module_platform_driver(jh7100_audclk_driver);
MODULE_AUTHOR("Emil Renner Berthing");
MODULE_DESCRIPTION("StarFive JH7100 audio clock driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/clk/starfive/clk-starfive-jh7100-audio.c |
// SPDX-License-Identifier: GPL-2.0
/*
* StarFive JH71X0 Clock Generator Driver
*
* Copyright (C) 2021-2022 Emil Renner Berthing <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/io.h>
#include "clk-starfive-jh71x0.h"
static struct jh71x0_clk *jh71x0_clk_from(struct clk_hw *hw)
{
return container_of(hw, struct jh71x0_clk, hw);
}
static struct jh71x0_clk_priv *jh71x0_priv_from(struct jh71x0_clk *clk)
{
return container_of(clk, struct jh71x0_clk_priv, reg[clk->idx]);
}
static u32 jh71x0_clk_reg_get(struct jh71x0_clk *clk)
{
struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
void __iomem *reg = priv->base + 4 * clk->idx;
return readl_relaxed(reg);
}
static void jh71x0_clk_reg_rmw(struct jh71x0_clk *clk, u32 mask, u32 value)
{
struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
void __iomem *reg = priv->base + 4 * clk->idx;
unsigned long flags;
spin_lock_irqsave(&priv->rmw_lock, flags);
value |= readl_relaxed(reg) & ~mask;
writel_relaxed(value, reg);
spin_unlock_irqrestore(&priv->rmw_lock, flags);
}
static int jh71x0_clk_enable(struct clk_hw *hw)
{
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, JH71X0_CLK_ENABLE);
return 0;
}
static void jh71x0_clk_disable(struct clk_hw *hw)
{
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, 0);
}
static int jh71x0_clk_is_enabled(struct clk_hw *hw)
{
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
return !!(jh71x0_clk_reg_get(clk) & JH71X0_CLK_ENABLE);
}
static unsigned long jh71x0_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
u32 div = jh71x0_clk_reg_get(clk) & JH71X0_CLK_DIV_MASK;
return div ? parent_rate / div : 0;
}
static int jh71x0_clk_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
unsigned long parent = req->best_parent_rate;
unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div);
unsigned long result = parent / div;
/*
* we want the result clamped by min_rate and max_rate if possible:
* case 1: div hits the max divider value, which means it's less than
* parent / rate, so the result is greater than rate and min_rate in
* particular. we can't do anything about result > max_rate because the
* divider doesn't go any further.
* case 2: div = DIV_ROUND_UP(parent, rate) which means the result is
* always lower or equal to rate and max_rate. however the result may
* turn out lower than min_rate, but then the next higher rate is fine:
* div - 1 = ceil(parent / rate) - 1 < parent / rate
* and thus
* min_rate <= rate < parent / (div - 1)
*/
if (result < req->min_rate && div > 1)
result = parent / (div - 1);
req->rate = result;
return 0;
}
static int jh71x0_clk_set_rate(struct clk_hw *hw,
unsigned long rate,
unsigned long parent_rate)
{
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
1UL, (unsigned long)clk->max_div);
jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, div);
return 0;
}
static unsigned long jh71x0_clk_frac_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
u32 reg = jh71x0_clk_reg_get(clk);
unsigned long div100 = 100 * (reg & JH71X0_CLK_INT_MASK) +
((reg & JH71X0_CLK_FRAC_MASK) >> JH71X0_CLK_FRAC_SHIFT);
return (div100 >= JH71X0_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
}
static int jh71x0_clk_frac_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
unsigned long parent100 = 100 * req->best_parent_rate;
unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate),
JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX);
unsigned long result = parent100 / div100;
/* clamp the result as in jh71x0_clk_determine_rate() above */
if (result > req->max_rate && div100 < JH71X0_CLK_FRAC_MAX)
result = parent100 / (div100 + 1);
if (result < req->min_rate && div100 > JH71X0_CLK_FRAC_MIN)
result = parent100 / (div100 - 1);
req->rate = result;
return 0;
}
static int jh71x0_clk_frac_set_rate(struct clk_hw *hw,
unsigned long rate,
unsigned long parent_rate)
{
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate),
JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX);
u32 value = ((div100 % 100) << JH71X0_CLK_FRAC_SHIFT) | (div100 / 100);
jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, value);
return 0;
}
static u8 jh71x0_clk_get_parent(struct clk_hw *hw)
{
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
u32 value = jh71x0_clk_reg_get(clk);
return (value & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT;
}
static int jh71x0_clk_set_parent(struct clk_hw *hw, u8 index)
{
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
u32 value = (u32)index << JH71X0_CLK_MUX_SHIFT;
jh71x0_clk_reg_rmw(clk, JH71X0_CLK_MUX_MASK, value);
return 0;
}
static int jh71x0_clk_get_phase(struct clk_hw *hw)
{
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
u32 value = jh71x0_clk_reg_get(clk);
return (value & JH71X0_CLK_INVERT) ? 180 : 0;
}
static int jh71x0_clk_set_phase(struct clk_hw *hw, int degrees)
{
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
u32 value;
if (degrees == 0)
value = 0;
else if (degrees == 180)
value = JH71X0_CLK_INVERT;
else
return -EINVAL;
jh71x0_clk_reg_rmw(clk, JH71X0_CLK_INVERT, value);
return 0;
}
#ifdef CONFIG_DEBUG_FS
static void jh71x0_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
{
static const struct debugfs_reg32 jh71x0_clk_reg = {
.name = "CTRL",
.offset = 0,
};
struct jh71x0_clk *clk = jh71x0_clk_from(hw);
struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
struct debugfs_regset32 *regset;
regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
if (!regset)
return;
regset->regs = &jh71x0_clk_reg;
regset->nregs = 1;
regset->base = priv->base + 4 * clk->idx;
debugfs_create_regset32("registers", 0400, dentry, regset);
}
#else
#define jh71x0_clk_debug_init NULL
#endif
static const struct clk_ops jh71x0_clk_gate_ops = {
.enable = jh71x0_clk_enable,
.disable = jh71x0_clk_disable,
.is_enabled = jh71x0_clk_is_enabled,
.debug_init = jh71x0_clk_debug_init,
};
static const struct clk_ops jh71x0_clk_div_ops = {
.recalc_rate = jh71x0_clk_recalc_rate,
.determine_rate = jh71x0_clk_determine_rate,
.set_rate = jh71x0_clk_set_rate,
.debug_init = jh71x0_clk_debug_init,
};
static const struct clk_ops jh71x0_clk_fdiv_ops = {
.recalc_rate = jh71x0_clk_frac_recalc_rate,
.determine_rate = jh71x0_clk_frac_determine_rate,
.set_rate = jh71x0_clk_frac_set_rate,
.debug_init = jh71x0_clk_debug_init,
};
static const struct clk_ops jh71x0_clk_gdiv_ops = {
.enable = jh71x0_clk_enable,
.disable = jh71x0_clk_disable,
.is_enabled = jh71x0_clk_is_enabled,
.recalc_rate = jh71x0_clk_recalc_rate,
.determine_rate = jh71x0_clk_determine_rate,
.set_rate = jh71x0_clk_set_rate,
.debug_init = jh71x0_clk_debug_init,
};
static const struct clk_ops jh71x0_clk_mux_ops = {
.determine_rate = __clk_mux_determine_rate,
.set_parent = jh71x0_clk_set_parent,
.get_parent = jh71x0_clk_get_parent,
.debug_init = jh71x0_clk_debug_init,
};
static const struct clk_ops jh71x0_clk_gmux_ops = {
.enable = jh71x0_clk_enable,
.disable = jh71x0_clk_disable,
.is_enabled = jh71x0_clk_is_enabled,
.determine_rate = __clk_mux_determine_rate,
.set_parent = jh71x0_clk_set_parent,
.get_parent = jh71x0_clk_get_parent,
.debug_init = jh71x0_clk_debug_init,
};
static const struct clk_ops jh71x0_clk_mdiv_ops = {
.recalc_rate = jh71x0_clk_recalc_rate,
.determine_rate = jh71x0_clk_determine_rate,
.get_parent = jh71x0_clk_get_parent,
.set_parent = jh71x0_clk_set_parent,
.set_rate = jh71x0_clk_set_rate,
.debug_init = jh71x0_clk_debug_init,
};
static const struct clk_ops jh71x0_clk_gmd_ops = {
.enable = jh71x0_clk_enable,
.disable = jh71x0_clk_disable,
.is_enabled = jh71x0_clk_is_enabled,
.recalc_rate = jh71x0_clk_recalc_rate,
.determine_rate = jh71x0_clk_determine_rate,
.get_parent = jh71x0_clk_get_parent,
.set_parent = jh71x0_clk_set_parent,
.set_rate = jh71x0_clk_set_rate,
.debug_init = jh71x0_clk_debug_init,
};
static const struct clk_ops jh71x0_clk_inv_ops = {
.get_phase = jh71x0_clk_get_phase,
.set_phase = jh71x0_clk_set_phase,
.debug_init = jh71x0_clk_debug_init,
};
const struct clk_ops *starfive_jh71x0_clk_ops(u32 max)
{
if (max & JH71X0_CLK_DIV_MASK) {
if (max & JH71X0_CLK_MUX_MASK) {
if (max & JH71X0_CLK_ENABLE)
return &jh71x0_clk_gmd_ops;
return &jh71x0_clk_mdiv_ops;
}
if (max & JH71X0_CLK_ENABLE)
return &jh71x0_clk_gdiv_ops;
if (max == JH71X0_CLK_FRAC_MAX)
return &jh71x0_clk_fdiv_ops;
return &jh71x0_clk_div_ops;
}
if (max & JH71X0_CLK_MUX_MASK) {
if (max & JH71X0_CLK_ENABLE)
return &jh71x0_clk_gmux_ops;
return &jh71x0_clk_mux_ops;
}
if (max & JH71X0_CLK_ENABLE)
return &jh71x0_clk_gate_ops;
return &jh71x0_clk_inv_ops;
}
EXPORT_SYMBOL_GPL(starfive_jh71x0_clk_ops);
| linux-master | drivers/clk/starfive/clk-starfive-jh71x0.c |
// SPDX-License-Identifier: GPL-2.0
/*
* StarFive JH7100 Clock Generator Driver
*
* Copyright 2021 Ahmad Fatoum, Pengutronix
* Copyright (C) 2021 Glider bv
* Copyright (C) 2021 Emil Renner Berthing <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/starfive-jh7100.h>
#include "clk-starfive-jh71x0.h"
/* external clocks */
#define JH7100_CLK_OSC_SYS (JH7100_CLK_END + 0)
#define JH7100_CLK_OSC_AUD (JH7100_CLK_END + 1)
#define JH7100_CLK_GMAC_RMII_REF (JH7100_CLK_END + 2)
#define JH7100_CLK_GMAC_GR_MII_RX (JH7100_CLK_END + 3)
static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
JH7100_CLK_OSC_SYS,
JH7100_CLK_PLL0_OUT,
JH7100_CLK_PLL1_OUT,
JH7100_CLK_PLL2_OUT),
JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
JH7100_CLK_OSC_SYS,
JH7100_CLK_PLL1_OUT,
JH7100_CLK_PLL2_OUT),
JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
JH7100_CLK_OSC_SYS,
JH7100_CLK_PLL0_OUT,
JH7100_CLK_PLL1_OUT,
JH7100_CLK_PLL2_OUT),
JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
JH7100_CLK_OSC_SYS,
JH7100_CLK_PLL0_OUT,
JH7100_CLK_PLL2_OUT),
JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
JH7100_CLK_OSC_SYS,
JH7100_CLK_PLL0_OUT),
JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
JH7100_CLK_OSC_SYS,
JH7100_CLK_PLL2_OUT),
JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
JH7100_CLK_OSC_SYS,
JH7100_CLK_PLL1_OUT,
JH7100_CLK_PLL2_OUT),
JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
JH7100_CLK_OSC_AUD,
JH7100_CLK_PLL0_OUT,
JH7100_CLK_PLL2_OUT),
JH71X0_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
JH7100_CLK_OSC_SYS,
JH7100_CLK_PLL1_OUT,
JH7100_CLK_PLL2_OUT),
JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
JH7100_CLK_OSC_SYS,
JH7100_CLK_PLL0_OUT,
JH7100_CLK_PLL1_OUT),
JH71X0__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
JH7100_CLK_OSC_AUD,
JH7100_CLK_PLL0_OUT,
JH7100_CLK_PLL2_OUT),
JH71X0__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
JH71X0__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
JH71X0__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
JH71X0__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
JH71X0_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
JH71X0_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
JH71X0_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
JH71X0__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
JH7100_CLK_OSC_SYS,
JH7100_CLK_OSC_AUD),
JH71X0__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
JH71X0__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
JH71X0__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
JH71X0__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
JH71X0__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
JH71X0_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
JH71X0_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
JH71X0_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
JH71X0_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
JH71X0_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
JH71X0_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS),
JH71X0_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
JH71X0_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
JH71X0_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
JH71X0__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
JH71X0_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
JH71X0_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
JH71X0_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
JH71X0_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
JH71X0__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
JH71X0_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
JH71X0__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
JH71X0__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
JH71X0_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
JH71X0_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
JH71X0_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
JH71X0_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
JH71X0_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
JH71X0_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
JH71X0_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
JH71X0_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
JH71X0_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
JH71X0_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
JH71X0__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
JH71X0_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
JH71X0_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
JH71X0__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
JH71X0_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
JH71X0_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
JH71X0_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
JH71X0_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
JH71X0_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT),
JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2,
JH7100_CLK_DDRPLL_DIV2),
JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2,
JH7100_CLK_DDRPLL_DIV4),
JH71X0_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS),
JH71X0_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
JH7100_CLK_DDROSC_DIV2,
JH7100_CLK_DDRPLL_DIV2,
JH7100_CLK_DDRPLL_DIV4,
JH7100_CLK_DDRPLL_DIV8),
JH71X0_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
JH7100_CLK_DDROSC_DIV2,
JH7100_CLK_DDRPLL_DIV2,
JH7100_CLK_DDRPLL_DIV4,
JH7100_CLK_DDRPLL_DIV8),
JH71X0_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
JH71X0__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
JH71X0__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
JH71X0_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
JH71X0__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
JH71X0__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
JH7100_CLK_CPU_AXI,
JH7100_CLK_NNEBUS_SRC1),
JH71X0_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
JH71X0_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
JH71X0_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
JH71X0_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
JH71X0__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
JH71X0__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
JH71X0_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
JH71X0__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
JH71X0_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
JH71X0_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
JH71X0__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
JH71X0_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
JH71X0_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
JH71X0_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
JH71X0__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
JH71X0_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
JH71X0_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
JH71X0__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
JH71X0_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
JH71X0_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32,
JH7100_CLK_USBPHY_ROOTDIV),
JH71X0__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
JH7100_CLK_OSC_SYS,
JH7100_CLK_USBPHY_PLLDIV25M),
JH71X0_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
JH71X0_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
JH71X0_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
JH71X0_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
JH71X0__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
JH71X0_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
JH71X0_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
JH71X0_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
JH71X0__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
JH71X0_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
JH71X0_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
JH71X0__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
JH71X0_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
JH71X0_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
JH71X0_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
JH71X0__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
JH71X0__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
JH71X0_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
JH71X0_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
JH71X0_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
JH71X0_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
JH71X0__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
JH71X0_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
JH71X0_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
JH71X0__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
JH71X0_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
JH71X0__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
JH71X0_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
JH71X0_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
JH71X0_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
JH71X0_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
JH7100_CLK_GMAC_GTX,
JH7100_CLK_GMAC_TX_INV,
JH7100_CLK_GMAC_RMII_TX),
JH71X0__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
JH71X0__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
JH7100_CLK_GMAC_GR_MII_RX,
JH7100_CLK_GMAC_RMII_RX),
JH71X0__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
JH71X0_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
JH71X0_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
JH71X0_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
JH71X0_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
JH71X0_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
JH71X0_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
JH71X0_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
JH71X0_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
JH71X0_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
JH71X0_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
JH71X0_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
JH71X0_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
JH71X0_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
JH71X0_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
JH71X0_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
JH71X0_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
JH71X0_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
JH71X0_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
JH71X0_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
JH71X0_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
JH71X0_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
JH71X0_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
JH71X0_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
JH71X0_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
JH71X0_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
JH71X0_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
JH71X0_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
JH71X0_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
JH71X0_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
JH71X0_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
JH71X0_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
JH71X0_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
JH71X0_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
JH71X0_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
JH71X0_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
JH71X0_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
JH71X0_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
JH71X0_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
JH71X0_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
JH71X0_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
JH71X0_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
JH71X0_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
JH71X0_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
JH71X0_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
JH71X0_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
JH71X0_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
JH71X0_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
JH71X0_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
JH71X0_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
JH71X0_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
JH71X0_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
JH71X0_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
JH71X0_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
JH71X0_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
JH71X0_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
JH71X0_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
};
static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data)
{
struct jh71x0_clk_priv *priv = data;
unsigned int idx = clkspec->args[0];
if (idx < JH7100_CLK_PLL0_OUT)
return &priv->reg[idx].hw;
if (idx < JH7100_CLK_END)
return priv->pll[idx - JH7100_CLK_PLL0_OUT];
return ERR_PTR(-EINVAL);
}
static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
{
struct jh71x0_clk_priv *priv;
unsigned int idx;
int ret;
priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7100_CLK_PLL0_OUT), GFP_KERNEL);
if (!priv)
return -ENOMEM;
spin_lock_init(&priv->rmw_lock);
priv->dev = &pdev->dev;
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
"osc_sys", 0, 40, 1);
if (IS_ERR(priv->pll[0]))
return PTR_ERR(priv->pll[0]);
priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
"osc_sys", 0, 64, 1);
if (IS_ERR(priv->pll[1]))
return PTR_ERR(priv->pll[1]);
priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
"pll2_refclk", 0, 55, 1);
if (IS_ERR(priv->pll[2]))
return PTR_ERR(priv->pll[2]);
for (idx = 0; idx < JH7100_CLK_PLL0_OUT; idx++) {
u32 max = jh7100_clk_data[idx].max;
struct clk_parent_data parents[4] = {};
struct clk_init_data init = {
.name = jh7100_clk_data[idx].name,
.ops = starfive_jh71x0_clk_ops(max),
.parent_data = parents,
.num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
.flags = jh7100_clk_data[idx].flags,
};
struct jh71x0_clk *clk = &priv->reg[idx];
unsigned int i;
for (i = 0; i < init.num_parents; i++) {
unsigned int pidx = jh7100_clk_data[idx].parents[i];
if (pidx < JH7100_CLK_PLL0_OUT)
parents[i].hw = &priv->reg[pidx].hw;
else if (pidx < JH7100_CLK_END)
parents[i].hw = priv->pll[pidx - JH7100_CLK_PLL0_OUT];
else if (pidx == JH7100_CLK_OSC_SYS)
parents[i].fw_name = "osc_sys";
else if (pidx == JH7100_CLK_OSC_AUD)
parents[i].fw_name = "osc_aud";
else if (pidx == JH7100_CLK_GMAC_RMII_REF)
parents[i].fw_name = "gmac_rmii_ref";
else if (pidx == JH7100_CLK_GMAC_GR_MII_RX)
parents[i].fw_name = "gmac_gr_mii_rxclk";
}
clk->hw.init = &init;
clk->idx = idx;
clk->max_div = max & JH71X0_CLK_DIV_MASK;
ret = devm_clk_hw_register(priv->dev, &clk->hw);
if (ret)
return ret;
}
return devm_of_clk_add_hw_provider(priv->dev, jh7100_clk_get, priv);
}
static const struct of_device_id clk_starfive_jh7100_match[] = {
{ .compatible = "starfive,jh7100-clkgen" },
{ /* sentinel */ }
};
static struct platform_driver clk_starfive_jh7100_driver = {
.driver = {
.name = "clk-starfive-jh7100",
.of_match_table = clk_starfive_jh7100_match,
.suppress_bind_attrs = true,
},
};
builtin_platform_driver_probe(clk_starfive_jh7100_driver, clk_starfive_jh7100_probe);
| linux-master | drivers/clk/starfive/clk-starfive-jh7100.c |
// SPDX-License-Identifier: GPL-2.0
/*
* StarFive JH7110 Always-On Clock Driver
*
* Copyright (C) 2022 Emil Renner Berthing <[email protected]>
* Copyright (C) 2022 StarFive Technology Co., Ltd.
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/starfive,jh7110-crg.h>
#include "clk-starfive-jh7110.h"
/* external clocks */
#define JH7110_AONCLK_OSC (JH7110_AONCLK_END + 0)
#define JH7110_AONCLK_GMAC0_RMII_REFIN (JH7110_AONCLK_END + 1)
#define JH7110_AONCLK_GMAC0_RGMII_RXIN (JH7110_AONCLK_END + 2)
#define JH7110_AONCLK_STG_AXIAHB (JH7110_AONCLK_END + 3)
#define JH7110_AONCLK_APB_BUS (JH7110_AONCLK_END + 4)
#define JH7110_AONCLK_GMAC0_GTXCLK (JH7110_AONCLK_END + 5)
#define JH7110_AONCLK_RTC_OSC (JH7110_AONCLK_END + 6)
static const struct jh71x0_clk_data jh7110_aonclk_data[] = {
/* source */
JH71X0__DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4, JH7110_AONCLK_OSC),
JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 2,
JH7110_AONCLK_OSC_DIV4,
JH7110_AONCLK_OSC),
/* gmac0 */
JH71X0_GATE(JH7110_AONCLK_GMAC0_AHB, "gmac0_ahb", 0, JH7110_AONCLK_STG_AXIAHB),
JH71X0_GATE(JH7110_AONCLK_GMAC0_AXI, "gmac0_axi", 0, JH7110_AONCLK_STG_AXIAHB),
JH71X0__DIV(JH7110_AONCLK_GMAC0_RMII_RTX, "gmac0_rmii_rtx", 30,
JH7110_AONCLK_GMAC0_RMII_REFIN),
JH71X0_GMUX(JH7110_AONCLK_GMAC0_TX, "gmac0_tx",
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2,
JH7110_AONCLK_GMAC0_GTXCLK,
JH7110_AONCLK_GMAC0_RMII_RTX),
JH71X0__INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", JH7110_AONCLK_GMAC0_TX),
JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2,
JH7110_AONCLK_GMAC0_RGMII_RXIN,
JH7110_AONCLK_GMAC0_RMII_RTX),
JH71X0__INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv", JH7110_AONCLK_GMAC0_RX),
/* otpc */
JH71X0_GATE(JH7110_AONCLK_OTPC_APB, "otpc_apb", 0, JH7110_AONCLK_APB_BUS),
/* rtc */
JH71X0_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", 0, JH7110_AONCLK_APB_BUS),
JH71X0__DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022, JH7110_AONCLK_OSC),
JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2,
JH7110_AONCLK_RTC_OSC,
JH7110_AONCLK_RTC_INTERNAL),
JH71X0_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", 0, JH7110_AONCLK_OSC),
};
static struct clk_hw *jh7110_aonclk_get(struct of_phandle_args *clkspec, void *data)
{
struct jh71x0_clk_priv *priv = data;
unsigned int idx = clkspec->args[0];
if (idx < JH7110_AONCLK_END)
return &priv->reg[idx].hw;
return ERR_PTR(-EINVAL);
}
static int jh7110_aoncrg_probe(struct platform_device *pdev)
{
struct jh71x0_clk_priv *priv;
unsigned int idx;
int ret;
priv = devm_kzalloc(&pdev->dev,
struct_size(priv, reg, JH7110_AONCLK_END),
GFP_KERNEL);
if (!priv)
return -ENOMEM;
spin_lock_init(&priv->rmw_lock);
priv->dev = &pdev->dev;
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
for (idx = 0; idx < JH7110_AONCLK_END; idx++) {
u32 max = jh7110_aonclk_data[idx].max;
struct clk_parent_data parents[4] = {};
struct clk_init_data init = {
.name = jh7110_aonclk_data[idx].name,
.ops = starfive_jh71x0_clk_ops(max),
.parent_data = parents,
.num_parents =
((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
.flags = jh7110_aonclk_data[idx].flags,
};
struct jh71x0_clk *clk = &priv->reg[idx];
unsigned int i;
for (i = 0; i < init.num_parents; i++) {
unsigned int pidx = jh7110_aonclk_data[idx].parents[i];
if (pidx < JH7110_AONCLK_END)
parents[i].hw = &priv->reg[pidx].hw;
else if (pidx == JH7110_AONCLK_OSC)
parents[i].fw_name = "osc";
else if (pidx == JH7110_AONCLK_GMAC0_RMII_REFIN)
parents[i].fw_name = "gmac0_rmii_refin";
else if (pidx == JH7110_AONCLK_GMAC0_RGMII_RXIN)
parents[i].fw_name = "gmac0_rgmii_rxin";
else if (pidx == JH7110_AONCLK_STG_AXIAHB)
parents[i].fw_name = "stg_axiahb";
else if (pidx == JH7110_AONCLK_APB_BUS)
parents[i].fw_name = "apb_bus";
else if (pidx == JH7110_AONCLK_GMAC0_GTXCLK)
parents[i].fw_name = "gmac0_gtxclk";
else if (pidx == JH7110_AONCLK_RTC_OSC)
parents[i].fw_name = "rtc_osc";
}
clk->hw.init = &init;
clk->idx = idx;
clk->max_div = max & JH71X0_CLK_DIV_MASK;
ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
if (ret)
return ret;
}
ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_aonclk_get, priv);
if (ret)
return ret;
return jh7110_reset_controller_register(priv, "rst-aon", 1);
}
static const struct of_device_id jh7110_aoncrg_match[] = {
{ .compatible = "starfive,jh7110-aoncrg" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, jh7110_aoncrg_match);
static struct platform_driver jh7110_aoncrg_driver = {
.probe = jh7110_aoncrg_probe,
.driver = {
.name = "clk-starfive-jh7110-aon",
.of_match_table = jh7110_aoncrg_match,
},
};
module_platform_driver(jh7110_aoncrg_driver);
MODULE_AUTHOR("Emil Renner Berthing");
MODULE_DESCRIPTION("StarFive JH7110 always-on clock driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/starfive/clk-starfive-jh7110-aon.c |
// SPDX-License-Identifier: GPL-2.0
/*
* StarFive JH7110 Image-Signal-Process Clock Driver
*
* Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <dt-bindings/clock/starfive,jh7110-crg.h>
#include "clk-starfive-jh7110.h"
/* external clocks */
#define JH7110_ISPCLK_ISP_TOP_CORE (JH7110_ISPCLK_END + 0)
#define JH7110_ISPCLK_ISP_TOP_AXI (JH7110_ISPCLK_END + 1)
#define JH7110_ISPCLK_NOC_BUS_ISP_AXI (JH7110_ISPCLK_END + 2)
#define JH7110_ISPCLK_DVP_CLK (JH7110_ISPCLK_END + 3)
#define JH7110_ISPCLK_EXT_END (JH7110_ISPCLK_END + 4)
static struct clk_bulk_data jh7110_isp_top_clks[] = {
{ .id = "isp_top_core" },
{ .id = "isp_top_axi" }
};
static const struct jh71x0_clk_data jh7110_ispclk_data[] = {
/* syscon */
JH71X0__DIV(JH7110_ISPCLK_DOM4_APB_FUNC, "dom4_apb_func", 15,
JH7110_ISPCLK_ISP_TOP_AXI),
JH71X0__DIV(JH7110_ISPCLK_MIPI_RX0_PXL, "mipi_rx0_pxl", 8,
JH7110_ISPCLK_ISP_TOP_CORE),
JH71X0__INV(JH7110_ISPCLK_DVP_INV, "dvp_inv", JH7110_ISPCLK_DVP_CLK),
/* vin */
JH71X0__DIV(JH7110_ISPCLK_M31DPHY_CFG_IN, "m31dphy_cfg_in", 16,
JH7110_ISPCLK_ISP_TOP_CORE),
JH71X0__DIV(JH7110_ISPCLK_M31DPHY_REF_IN, "m31dphy_ref_in", 16,
JH7110_ISPCLK_ISP_TOP_CORE),
JH71X0__DIV(JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0, "m31dphy_tx_esc_lan0", 60,
JH7110_ISPCLK_ISP_TOP_CORE),
JH71X0_GATE(JH7110_ISPCLK_VIN_APB, "vin_apb", 0,
JH7110_ISPCLK_DOM4_APB_FUNC),
JH71X0__DIV(JH7110_ISPCLK_VIN_SYS, "vin_sys", 8, JH7110_ISPCLK_ISP_TOP_CORE),
JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF0, "vin_pixel_if0", 0,
JH7110_ISPCLK_MIPI_RX0_PXL),
JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF1, "vin_pixel_if1", 0,
JH7110_ISPCLK_MIPI_RX0_PXL),
JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF2, "vin_pixel_if2", 0,
JH7110_ISPCLK_MIPI_RX0_PXL),
JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF3, "vin_pixel_if3", 0,
JH7110_ISPCLK_MIPI_RX0_PXL),
JH71X0__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 2,
JH7110_ISPCLK_MIPI_RX0_PXL,
JH7110_ISPCLK_DVP_INV),
/* ispv2_top_wrapper */
JH71X0_GMUX(JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C, "ispv2_top_wrapper_c", 0, 2,
JH7110_ISPCLK_MIPI_RX0_PXL,
JH7110_ISPCLK_DVP_INV),
};
static inline int jh7110_isp_top_rst_init(struct jh71x0_clk_priv *priv)
{
struct reset_control *top_rsts;
/* The resets should be shared and other ISP modules will use its. */
top_rsts = devm_reset_control_array_get_shared(priv->dev);
if (IS_ERR(top_rsts))
return dev_err_probe(priv->dev, PTR_ERR(top_rsts),
"failed to get top resets\n");
return reset_control_deassert(top_rsts);
}
static struct clk_hw *jh7110_ispclk_get(struct of_phandle_args *clkspec, void *data)
{
struct jh71x0_clk_priv *priv = data;
unsigned int idx = clkspec->args[0];
if (idx < JH7110_ISPCLK_END)
return &priv->reg[idx].hw;
return ERR_PTR(-EINVAL);
}
#ifdef CONFIG_PM
static int jh7110_ispcrg_suspend(struct device *dev)
{
struct jh7110_top_sysclk *top = dev_get_drvdata(dev);
clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks);
return 0;
}
static int jh7110_ispcrg_resume(struct device *dev)
{
struct jh7110_top_sysclk *top = dev_get_drvdata(dev);
return clk_bulk_prepare_enable(top->top_clks_num, top->top_clks);
}
static const struct dev_pm_ops jh7110_ispcrg_pm_ops = {
RUNTIME_PM_OPS(jh7110_ispcrg_suspend, jh7110_ispcrg_resume, NULL)
};
#endif
static int jh7110_ispcrg_probe(struct platform_device *pdev)
{
struct jh71x0_clk_priv *priv;
struct jh7110_top_sysclk *top;
unsigned int idx;
int ret;
priv = devm_kzalloc(&pdev->dev,
struct_size(priv, reg, JH7110_ISPCLK_END),
GFP_KERNEL);
if (!priv)
return -ENOMEM;
top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL);
if (!top)
return -ENOMEM;
spin_lock_init(&priv->rmw_lock);
priv->dev = &pdev->dev;
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
top->top_clks = jh7110_isp_top_clks;
top->top_clks_num = ARRAY_SIZE(jh7110_isp_top_clks);
ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks);
if (ret)
return dev_err_probe(priv->dev, ret, "failed to get main clocks\n");
dev_set_drvdata(priv->dev, top);
/* enable power domain and clocks */
pm_runtime_enable(priv->dev);
ret = pm_runtime_get_sync(priv->dev);
if (ret < 0)
return dev_err_probe(priv->dev, ret, "failed to turn on power\n");
ret = jh7110_isp_top_rst_init(priv);
if (ret)
goto err_exit;
for (idx = 0; idx < JH7110_ISPCLK_END; idx++) {
u32 max = jh7110_ispclk_data[idx].max;
struct clk_parent_data parents[4] = {};
struct clk_init_data init = {
.name = jh7110_ispclk_data[idx].name,
.ops = starfive_jh71x0_clk_ops(max),
.parent_data = parents,
.num_parents =
((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
.flags = jh7110_ispclk_data[idx].flags,
};
struct jh71x0_clk *clk = &priv->reg[idx];
unsigned int i;
const char *fw_name[JH7110_ISPCLK_EXT_END - JH7110_ISPCLK_END] = {
"isp_top_core",
"isp_top_axi",
"noc_bus_isp_axi",
"dvp_clk"
};
for (i = 0; i < init.num_parents; i++) {
unsigned int pidx = jh7110_ispclk_data[idx].parents[i];
if (pidx < JH7110_ISPCLK_END)
parents[i].hw = &priv->reg[pidx].hw;
else
parents[i].fw_name = fw_name[pidx - JH7110_ISPCLK_END];
}
clk->hw.init = &init;
clk->idx = idx;
clk->max_div = max & JH71X0_CLK_DIV_MASK;
ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
if (ret)
goto err_exit;
}
ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_ispclk_get, priv);
if (ret)
goto err_exit;
ret = jh7110_reset_controller_register(priv, "rst-isp", 3);
if (ret)
goto err_exit;
return 0;
err_exit:
pm_runtime_put_sync(priv->dev);
pm_runtime_disable(priv->dev);
return ret;
}
static int jh7110_ispcrg_remove(struct platform_device *pdev)
{
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
return 0;
}
static const struct of_device_id jh7110_ispcrg_match[] = {
{ .compatible = "starfive,jh7110-ispcrg" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, jh7110_ispcrg_match);
static struct platform_driver jh7110_ispcrg_driver = {
.probe = jh7110_ispcrg_probe,
.remove = jh7110_ispcrg_remove,
.driver = {
.name = "clk-starfive-jh7110-isp",
.of_match_table = jh7110_ispcrg_match,
.pm = pm_ptr(&jh7110_ispcrg_pm_ops),
},
};
module_platform_driver(jh7110_ispcrg_driver);
MODULE_AUTHOR("Xingyu Wu <[email protected]>");
MODULE_DESCRIPTION("StarFive JH7110 Image-Signal-Process clock driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/starfive/clk-starfive-jh7110-isp.c |
// SPDX-License-Identifier: GPL-2.0
/*
* StarFive JH7110 PLL Clock Generator Driver
*
* Copyright (C) 2023 StarFive Technology Co., Ltd.
* Copyright (C) 2023 Emil Renner Berthing <[email protected]>
*
* This driver is about to register JH7110 PLL clock generator and support ops.
* The JH7110 have three PLL clock, PLL0, PLL1 and PLL2.
* Each PLL clocks work in integer mode or fraction mode by some dividers,
* and the configuration registers and dividers are set in several syscon registers.
* The formula for calculating frequency is:
* Fvco = Fref * (NI + NF) / M / Q1
* Fref: OSC source clock rate
* NI: integer frequency dividing ratio of feedback divider, set by fbdiv[11:0].
* NF: fractional frequency dividing ratio, set by frac[23:0]. NF = frac[23:0] / 2^24 = 0 ~ 0.999.
* M: frequency dividing ratio of pre-divider, set by prediv[5:0].
* Q1: frequency dividing ratio of post divider, set by 2^postdiv1[1:0], eg. 1, 2, 4 or 8.
*/
#include <linux/bits.h>
#include <linux/clk-provider.h>
#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/starfive,jh7110-crg.h>
/* this driver expects a 24MHz input frequency from the oscillator */
#define JH7110_PLL_OSC_RATE 24000000UL
#define JH7110_PLL0_PD_OFFSET 0x18
#define JH7110_PLL0_DACPD_SHIFT 24
#define JH7110_PLL0_DACPD_MASK BIT(24)
#define JH7110_PLL0_DSMPD_SHIFT 25
#define JH7110_PLL0_DSMPD_MASK BIT(25)
#define JH7110_PLL0_FBDIV_OFFSET 0x1c
#define JH7110_PLL0_FBDIV_SHIFT 0
#define JH7110_PLL0_FBDIV_MASK GENMASK(11, 0)
#define JH7110_PLL0_FRAC_OFFSET 0x20
#define JH7110_PLL0_PREDIV_OFFSET 0x24
#define JH7110_PLL1_PD_OFFSET 0x24
#define JH7110_PLL1_DACPD_SHIFT 15
#define JH7110_PLL1_DACPD_MASK BIT(15)
#define JH7110_PLL1_DSMPD_SHIFT 16
#define JH7110_PLL1_DSMPD_MASK BIT(16)
#define JH7110_PLL1_FBDIV_OFFSET 0x24
#define JH7110_PLL1_FBDIV_SHIFT 17
#define JH7110_PLL1_FBDIV_MASK GENMASK(28, 17)
#define JH7110_PLL1_FRAC_OFFSET 0x28
#define JH7110_PLL1_PREDIV_OFFSET 0x2c
#define JH7110_PLL2_PD_OFFSET 0x2c
#define JH7110_PLL2_DACPD_SHIFT 15
#define JH7110_PLL2_DACPD_MASK BIT(15)
#define JH7110_PLL2_DSMPD_SHIFT 16
#define JH7110_PLL2_DSMPD_MASK BIT(16)
#define JH7110_PLL2_FBDIV_OFFSET 0x2c
#define JH7110_PLL2_FBDIV_SHIFT 17
#define JH7110_PLL2_FBDIV_MASK GENMASK(28, 17)
#define JH7110_PLL2_FRAC_OFFSET 0x30
#define JH7110_PLL2_PREDIV_OFFSET 0x34
#define JH7110_PLL_FRAC_SHIFT 0
#define JH7110_PLL_FRAC_MASK GENMASK(23, 0)
#define JH7110_PLL_POSTDIV1_SHIFT 28
#define JH7110_PLL_POSTDIV1_MASK GENMASK(29, 28)
#define JH7110_PLL_PREDIV_SHIFT 0
#define JH7110_PLL_PREDIV_MASK GENMASK(5, 0)
enum jh7110_pll_mode {
JH7110_PLL_MODE_FRACTION,
JH7110_PLL_MODE_INTEGER,
};
struct jh7110_pll_preset {
unsigned long freq;
u32 frac; /* frac value should be decimals multiplied by 2^24 */
unsigned fbdiv : 12; /* fbdiv value should be 8 to 4095 */
unsigned prediv : 6;
unsigned postdiv1 : 2;
unsigned mode : 1;
};
struct jh7110_pll_info {
char *name;
const struct jh7110_pll_preset *presets;
unsigned int npresets;
struct {
unsigned int pd;
unsigned int fbdiv;
unsigned int frac;
unsigned int prediv;
} offsets;
struct {
u32 dacpd;
u32 dsmpd;
u32 fbdiv;
} masks;
struct {
char dacpd;
char dsmpd;
char fbdiv;
} shifts;
};
#define _JH7110_PLL(_idx, _name, _presets) \
[_idx] = { \
.name = _name, \
.presets = _presets, \
.npresets = ARRAY_SIZE(_presets), \
.offsets = { \
.pd = JH7110_PLL##_idx##_PD_OFFSET, \
.fbdiv = JH7110_PLL##_idx##_FBDIV_OFFSET, \
.frac = JH7110_PLL##_idx##_FRAC_OFFSET, \
.prediv = JH7110_PLL##_idx##_PREDIV_OFFSET, \
}, \
.masks = { \
.dacpd = JH7110_PLL##_idx##_DACPD_MASK, \
.dsmpd = JH7110_PLL##_idx##_DSMPD_MASK, \
.fbdiv = JH7110_PLL##_idx##_FBDIV_MASK, \
}, \
.shifts = { \
.dacpd = JH7110_PLL##_idx##_DACPD_SHIFT, \
.dsmpd = JH7110_PLL##_idx##_DSMPD_SHIFT, \
.fbdiv = JH7110_PLL##_idx##_FBDIV_SHIFT, \
}, \
}
#define JH7110_PLL(idx, name, presets) _JH7110_PLL(idx, name, presets)
struct jh7110_pll_data {
struct clk_hw hw;
unsigned int idx;
};
struct jh7110_pll_priv {
struct device *dev;
struct regmap *regmap;
struct jh7110_pll_data pll[JH7110_PLLCLK_END];
};
struct jh7110_pll_regvals {
u32 dacpd;
u32 dsmpd;
u32 fbdiv;
u32 frac;
u32 postdiv1;
u32 prediv;
};
/*
* Because the pll frequency is relatively fixed,
* it cannot be set arbitrarily, so it needs a specific configuration.
* PLL0 frequency should be multiple of 125MHz (USB frequency).
*/
static const struct jh7110_pll_preset jh7110_pll0_presets[] = {
{
.freq = 375000000,
.fbdiv = 125,
.prediv = 8,
.postdiv1 = 0,
.mode = JH7110_PLL_MODE_INTEGER,
}, {
.freq = 500000000,
.fbdiv = 125,
.prediv = 6,
.postdiv1 = 0,
.mode = JH7110_PLL_MODE_INTEGER,
}, {
.freq = 625000000,
.fbdiv = 625,
.prediv = 24,
.postdiv1 = 0,
.mode = JH7110_PLL_MODE_INTEGER,
}, {
.freq = 750000000,
.fbdiv = 125,
.prediv = 4,
.postdiv1 = 0,
.mode = JH7110_PLL_MODE_INTEGER,
}, {
.freq = 875000000,
.fbdiv = 875,
.prediv = 24,
.postdiv1 = 0,
.mode = JH7110_PLL_MODE_INTEGER,
}, {
.freq = 1000000000,
.fbdiv = 125,
.prediv = 3,
.postdiv1 = 0,
.mode = JH7110_PLL_MODE_INTEGER,
}, {
.freq = 1250000000,
.fbdiv = 625,
.prediv = 12,
.postdiv1 = 0,
.mode = JH7110_PLL_MODE_INTEGER,
}, {
.freq = 1375000000,
.fbdiv = 1375,
.prediv = 24,
.postdiv1 = 0,
.mode = JH7110_PLL_MODE_INTEGER,
}, {
.freq = 1500000000,
.fbdiv = 125,
.prediv = 2,
.postdiv1 = 0,
.mode = JH7110_PLL_MODE_INTEGER,
},
};
static const struct jh7110_pll_preset jh7110_pll1_presets[] = {
{
.freq = 1066000000,
.fbdiv = 533,
.prediv = 12,
.postdiv1 = 0,
.mode = JH7110_PLL_MODE_INTEGER,
}, {
.freq = 1200000000,
.fbdiv = 50,
.prediv = 1,
.postdiv1 = 0,
.mode = JH7110_PLL_MODE_INTEGER,
}, {
.freq = 1400000000,
.fbdiv = 350,
.prediv = 6,
.postdiv1 = 0,
.mode = JH7110_PLL_MODE_INTEGER,
}, {
.freq = 1600000000,
.fbdiv = 200,
.prediv = 3,
.postdiv1 = 0,
.mode = JH7110_PLL_MODE_INTEGER,
},
};
static const struct jh7110_pll_preset jh7110_pll2_presets[] = {
{
.freq = 1188000000,
.fbdiv = 99,
.prediv = 2,
.postdiv1 = 0,
.mode = JH7110_PLL_MODE_INTEGER,
}, {
.freq = 1228800000,
.fbdiv = 256,
.prediv = 5,
.postdiv1 = 0,
.mode = JH7110_PLL_MODE_INTEGER,
},
};
static const struct jh7110_pll_info jh7110_plls[JH7110_PLLCLK_END] = {
JH7110_PLL(JH7110_PLLCLK_PLL0_OUT, "pll0_out", jh7110_pll0_presets),
JH7110_PLL(JH7110_PLLCLK_PLL1_OUT, "pll1_out", jh7110_pll1_presets),
JH7110_PLL(JH7110_PLLCLK_PLL2_OUT, "pll2_out", jh7110_pll2_presets),
};
static struct jh7110_pll_data *jh7110_pll_data_from(struct clk_hw *hw)
{
return container_of(hw, struct jh7110_pll_data, hw);
}
static struct jh7110_pll_priv *jh7110_pll_priv_from(struct jh7110_pll_data *pll)
{
return container_of(pll, struct jh7110_pll_priv, pll[pll->idx]);
}
static void jh7110_pll_regvals_get(struct regmap *regmap,
const struct jh7110_pll_info *info,
struct jh7110_pll_regvals *ret)
{
u32 val;
regmap_read(regmap, info->offsets.pd, &val);
ret->dacpd = (val & info->masks.dacpd) >> info->shifts.dacpd;
ret->dsmpd = (val & info->masks.dsmpd) >> info->shifts.dsmpd;
regmap_read(regmap, info->offsets.fbdiv, &val);
ret->fbdiv = (val & info->masks.fbdiv) >> info->shifts.fbdiv;
regmap_read(regmap, info->offsets.frac, &val);
ret->frac = (val & JH7110_PLL_FRAC_MASK) >> JH7110_PLL_FRAC_SHIFT;
ret->postdiv1 = (val & JH7110_PLL_POSTDIV1_MASK) >> JH7110_PLL_POSTDIV1_SHIFT;
regmap_read(regmap, info->offsets.prediv, &val);
ret->prediv = (val & JH7110_PLL_PREDIV_MASK) >> JH7110_PLL_PREDIV_SHIFT;
}
static unsigned long jh7110_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll);
struct jh7110_pll_regvals val;
unsigned long rate;
jh7110_pll_regvals_get(priv->regmap, &jh7110_plls[pll->idx], &val);
/*
* dacpd = dsmpd = 0: fraction mode
* dacpd = dsmpd = 1: integer mode, frac value ignored
*
* rate = parent * (fbdiv + frac/2^24) / prediv / 2^postdiv1
* = (parent * fbdiv + parent * frac / 2^24) / (prediv * 2^postdiv1)
*/
if (val.dacpd == 0 && val.dsmpd == 0)
rate = parent_rate * val.frac / (1UL << 24);
else if (val.dacpd == 1 && val.dsmpd == 1)
rate = 0;
else
return 0;
rate += parent_rate * val.fbdiv;
rate /= val.prediv << val.postdiv1;
return rate;
}
static int jh7110_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{
struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
const struct jh7110_pll_info *info = &jh7110_plls[pll->idx];
const struct jh7110_pll_preset *selected = &info->presets[0];
unsigned int idx;
/* if the parent rate doesn't match our expectations the presets won't work */
if (req->best_parent_rate != JH7110_PLL_OSC_RATE) {
req->rate = jh7110_pll_recalc_rate(hw, req->best_parent_rate);
return 0;
}
/* find highest rate lower or equal to the requested rate */
for (idx = 1; idx < info->npresets; idx++) {
const struct jh7110_pll_preset *val = &info->presets[idx];
if (req->rate < val->freq)
break;
selected = val;
}
req->rate = selected->freq;
return 0;
}
static int jh7110_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll);
const struct jh7110_pll_info *info = &jh7110_plls[pll->idx];
const struct jh7110_pll_preset *val;
unsigned int idx;
/* if the parent rate doesn't match our expectations the presets won't work */
if (parent_rate != JH7110_PLL_OSC_RATE)
return -EINVAL;
for (idx = 0, val = &info->presets[0]; idx < info->npresets; idx++, val++) {
if (val->freq == rate)
goto found;
}
return -EINVAL;
found:
if (val->mode == JH7110_PLL_MODE_FRACTION)
regmap_update_bits(priv->regmap, info->offsets.frac, JH7110_PLL_FRAC_MASK,
val->frac << JH7110_PLL_FRAC_SHIFT);
regmap_update_bits(priv->regmap, info->offsets.pd, info->masks.dacpd,
(u32)val->mode << info->shifts.dacpd);
regmap_update_bits(priv->regmap, info->offsets.pd, info->masks.dsmpd,
(u32)val->mode << info->shifts.dsmpd);
regmap_update_bits(priv->regmap, info->offsets.prediv, JH7110_PLL_PREDIV_MASK,
(u32)val->prediv << JH7110_PLL_PREDIV_SHIFT);
regmap_update_bits(priv->regmap, info->offsets.fbdiv, info->masks.fbdiv,
val->fbdiv << info->shifts.fbdiv);
regmap_update_bits(priv->regmap, info->offsets.frac, JH7110_PLL_POSTDIV1_MASK,
(u32)val->postdiv1 << JH7110_PLL_POSTDIV1_SHIFT);
return 0;
}
#ifdef CONFIG_DEBUG_FS
static int jh7110_pll_registers_read(struct seq_file *s, void *unused)
{
struct jh7110_pll_data *pll = s->private;
struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll);
struct jh7110_pll_regvals val;
jh7110_pll_regvals_get(priv->regmap, &jh7110_plls[pll->idx], &val);
seq_printf(s, "fbdiv=%u\n"
"frac=%u\n"
"prediv=%u\n"
"postdiv1=%u\n"
"dacpd=%u\n"
"dsmpd=%u\n",
val.fbdiv, val.frac, val.prediv, val.postdiv1,
val.dacpd, val.dsmpd);
return 0;
}
static int jh7110_pll_registers_open(struct inode *inode, struct file *f)
{
return single_open(f, jh7110_pll_registers_read, inode->i_private);
}
static const struct file_operations jh7110_pll_registers_ops = {
.owner = THIS_MODULE,
.open = jh7110_pll_registers_open,
.release = single_release,
.read = seq_read,
.llseek = seq_lseek
};
static void jh7110_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
{
struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
debugfs_create_file("registers", 0400, dentry, pll,
&jh7110_pll_registers_ops);
}
#else
#define jh7110_pll_debug_init NULL
#endif
static const struct clk_ops jh7110_pll_ops = {
.recalc_rate = jh7110_pll_recalc_rate,
.determine_rate = jh7110_pll_determine_rate,
.set_rate = jh7110_pll_set_rate,
.debug_init = jh7110_pll_debug_init,
};
static struct clk_hw *jh7110_pll_get(struct of_phandle_args *clkspec, void *data)
{
struct jh7110_pll_priv *priv = data;
unsigned int idx = clkspec->args[0];
if (idx < JH7110_PLLCLK_END)
return &priv->pll[idx].hw;
return ERR_PTR(-EINVAL);
}
static int jh7110_pll_probe(struct platform_device *pdev)
{
struct jh7110_pll_priv *priv;
unsigned int idx;
int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = &pdev->dev;
priv->regmap = syscon_node_to_regmap(priv->dev->of_node->parent);
if (IS_ERR(priv->regmap))
return PTR_ERR(priv->regmap);
for (idx = 0; idx < JH7110_PLLCLK_END; idx++) {
struct clk_parent_data parents = {
.index = 0,
};
struct clk_init_data init = {
.name = jh7110_plls[idx].name,
.ops = &jh7110_pll_ops,
.parent_data = &parents,
.num_parents = 1,
.flags = 0,
};
struct jh7110_pll_data *pll = &priv->pll[idx];
pll->hw.init = &init;
pll->idx = idx;
ret = devm_clk_hw_register(&pdev->dev, &pll->hw);
if (ret)
return ret;
}
return devm_of_clk_add_hw_provider(&pdev->dev, jh7110_pll_get, priv);
}
static const struct of_device_id jh7110_pll_match[] = {
{ .compatible = "starfive,jh7110-pll" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, jh7110_pll_match);
static struct platform_driver jh7110_pll_driver = {
.driver = {
.name = "clk-starfive-jh7110-pll",
.of_match_table = jh7110_pll_match,
},
};
builtin_platform_driver_probe(jh7110_pll_driver, jh7110_pll_probe);
| linux-master | drivers/clk/starfive/clk-starfive-jh7110-pll.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2018 Samsung Electronics Co., Ltd.
// Author: Marek Szyprowski <[email protected]>
// Common Clock Framework support for Exynos5 power-domain dependent clocks
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
#include "clk.h"
#include "clk-exynos5-subcmu.h"
static struct samsung_clk_provider *ctx;
static const struct exynos5_subcmu_info **cmu;
static int nr_cmus;
static void exynos5_subcmu_clk_save(void __iomem *base,
struct exynos5_subcmu_reg_dump *rd,
unsigned int num_regs)
{
for (; num_regs > 0; --num_regs, ++rd) {
rd->save = readl(base + rd->offset);
writel((rd->save & ~rd->mask) | rd->value, base + rd->offset);
rd->save &= rd->mask;
}
};
static void exynos5_subcmu_clk_restore(void __iomem *base,
struct exynos5_subcmu_reg_dump *rd,
unsigned int num_regs)
{
for (; num_regs > 0; --num_regs, ++rd)
writel((readl(base + rd->offset) & ~rd->mask) | rd->save,
base + rd->offset);
}
static void exynos5_subcmu_defer_gate(struct samsung_clk_provider *ctx,
const struct samsung_gate_clock *list, int nr_clk)
{
while (nr_clk--)
samsung_clk_add_lookup(ctx, ERR_PTR(-EPROBE_DEFER), list++->id);
}
/*
* Pass the needed clock provider context and register sub-CMU clocks
*
* NOTE: This function has to be called from the main, CLK_OF_DECLARE-
* initialized clock provider driver. This happens very early during boot
* process. Then this driver, during core_initcall registers two platform
* drivers: one which binds to the same device-tree node as CLK_OF_DECLARE
* driver and second, for handling its per-domain child-devices. Those
* platform drivers are bound to their devices a bit later in arch_initcall,
* when OF-core populates all device-tree nodes.
*/
void exynos5_subcmus_init(struct samsung_clk_provider *_ctx, int _nr_cmus,
const struct exynos5_subcmu_info **_cmu)
{
ctx = _ctx;
cmu = _cmu;
nr_cmus = _nr_cmus;
for (; _nr_cmus--; _cmu++) {
exynos5_subcmu_defer_gate(ctx, (*_cmu)->gate_clks,
(*_cmu)->nr_gate_clks);
exynos5_subcmu_clk_save(ctx->reg_base, (*_cmu)->suspend_regs,
(*_cmu)->nr_suspend_regs);
}
}
static int __maybe_unused exynos5_subcmu_suspend(struct device *dev)
{
struct exynos5_subcmu_info *info = dev_get_drvdata(dev);
unsigned long flags;
spin_lock_irqsave(&ctx->lock, flags);
exynos5_subcmu_clk_save(ctx->reg_base, info->suspend_regs,
info->nr_suspend_regs);
spin_unlock_irqrestore(&ctx->lock, flags);
return 0;
}
static int __maybe_unused exynos5_subcmu_resume(struct device *dev)
{
struct exynos5_subcmu_info *info = dev_get_drvdata(dev);
unsigned long flags;
spin_lock_irqsave(&ctx->lock, flags);
exynos5_subcmu_clk_restore(ctx->reg_base, info->suspend_regs,
info->nr_suspend_regs);
spin_unlock_irqrestore(&ctx->lock, flags);
return 0;
}
static int __init exynos5_subcmu_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct exynos5_subcmu_info *info = dev_get_drvdata(dev);
pm_runtime_set_suspended(dev);
pm_runtime_enable(dev);
pm_runtime_get(dev);
ctx->dev = dev;
samsung_clk_register_div(ctx, info->div_clks, info->nr_div_clks);
samsung_clk_register_gate(ctx, info->gate_clks, info->nr_gate_clks);
ctx->dev = NULL;
pm_runtime_put_sync(dev);
return 0;
}
static const struct dev_pm_ops exynos5_subcmu_pm_ops = {
SET_RUNTIME_PM_OPS(exynos5_subcmu_suspend,
exynos5_subcmu_resume, NULL)
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver exynos5_subcmu_driver __refdata = {
.driver = {
.name = "exynos5-subcmu",
.suppress_bind_attrs = true,
.pm = &exynos5_subcmu_pm_ops,
},
.probe = exynos5_subcmu_probe,
};
static int __init exynos5_clk_register_subcmu(struct device *parent,
const struct exynos5_subcmu_info *info,
struct device_node *pd_node)
{
struct of_phandle_args genpdspec = { .np = pd_node };
struct platform_device *pdev;
int ret;
pdev = platform_device_alloc("exynos5-subcmu", PLATFORM_DEVID_AUTO);
if (!pdev)
return -ENOMEM;
pdev->dev.parent = parent;
platform_set_drvdata(pdev, (void *)info);
of_genpd_add_device(&genpdspec, &pdev->dev);
ret = platform_device_add(pdev);
if (ret)
platform_device_put(pdev);
return ret;
}
static int __init exynos5_clk_probe(struct platform_device *pdev)
{
struct device_node *np;
const char *name;
int i;
for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
if (of_property_read_string(np, "label", &name) < 0)
continue;
for (i = 0; i < nr_cmus; i++)
if (strcmp(cmu[i]->pd_name, name) == 0)
exynos5_clk_register_subcmu(&pdev->dev,
cmu[i], np);
}
return 0;
}
static const struct of_device_id exynos5_clk_of_match[] = {
{ .compatible = "samsung,exynos5250-clock", },
{ .compatible = "samsung,exynos5420-clock", },
{ .compatible = "samsung,exynos5800-clock", },
{ },
};
static struct platform_driver exynos5_clk_driver __refdata = {
.driver = {
.name = "exynos5-clock",
.of_match_table = exynos5_clk_of_match,
.suppress_bind_attrs = true,
},
.probe = exynos5_clk_probe,
};
static int __init exynos5_clk_drv_init(void)
{
platform_driver_register(&exynos5_clk_driver);
platform_driver_register(&exynos5_subcmu_driver);
return 0;
}
core_initcall(exynos5_clk_drv_init);
| linux-master | drivers/clk/samsung/clk-exynos5-subcmu.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Mateusz Krawczuk <[email protected]>
*
* Based on clock drivers for S3C64xx and Exynos4 SoCs.
*
* Common Clock Framework support for all S5PC110/S5PV210 SoCs.
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "clk.h"
#include "clk-pll.h"
#include <dt-bindings/clock/s5pv210.h>
/* S5PC110/S5PV210 clock controller register offsets */
#define APLL_LOCK 0x0000
#define MPLL_LOCK 0x0008
#define EPLL_LOCK 0x0010
#define VPLL_LOCK 0x0020
#define APLL_CON0 0x0100
#define APLL_CON1 0x0104
#define MPLL_CON 0x0108
#define EPLL_CON0 0x0110
#define EPLL_CON1 0x0114
#define VPLL_CON 0x0120
#define CLK_SRC0 0x0200
#define CLK_SRC1 0x0204
#define CLK_SRC2 0x0208
#define CLK_SRC3 0x020c
#define CLK_SRC4 0x0210
#define CLK_SRC5 0x0214
#define CLK_SRC6 0x0218
#define CLK_SRC_MASK0 0x0280
#define CLK_SRC_MASK1 0x0284
#define CLK_DIV0 0x0300
#define CLK_DIV1 0x0304
#define CLK_DIV2 0x0308
#define CLK_DIV3 0x030c
#define CLK_DIV4 0x0310
#define CLK_DIV5 0x0314
#define CLK_DIV6 0x0318
#define CLK_DIV7 0x031c
#define CLK_GATE_MAIN0 0x0400
#define CLK_GATE_MAIN1 0x0404
#define CLK_GATE_MAIN2 0x0408
#define CLK_GATE_PERI0 0x0420
#define CLK_GATE_PERI1 0x0424
#define CLK_GATE_SCLK0 0x0440
#define CLK_GATE_SCLK1 0x0444
#define CLK_GATE_IP0 0x0460
#define CLK_GATE_IP1 0x0464
#define CLK_GATE_IP2 0x0468
#define CLK_GATE_IP3 0x046c
#define CLK_GATE_IP4 0x0470
#define CLK_GATE_BLOCK 0x0480
#define CLK_GATE_IP5 0x0484
#define CLK_OUT 0x0500
#define MISC 0xe000
#define OM_STAT 0xe100
/* IDs of PLLs available on S5PV210/S5P6442 SoCs */
enum {
apll,
mpll,
epll,
vpll,
};
/* IDs of external clocks (used for legacy boards) */
enum {
xxti,
xusbxti,
};
static void __iomem *reg_base;
/* List of registers that need to be preserved across suspend/resume. */
static unsigned long s5pv210_clk_regs[] __initdata = {
CLK_SRC0,
CLK_SRC1,
CLK_SRC2,
CLK_SRC3,
CLK_SRC4,
CLK_SRC5,
CLK_SRC6,
CLK_SRC_MASK0,
CLK_SRC_MASK1,
CLK_DIV0,
CLK_DIV1,
CLK_DIV2,
CLK_DIV3,
CLK_DIV4,
CLK_DIV5,
CLK_DIV6,
CLK_DIV7,
CLK_GATE_MAIN0,
CLK_GATE_MAIN1,
CLK_GATE_MAIN2,
CLK_GATE_PERI0,
CLK_GATE_PERI1,
CLK_GATE_SCLK0,
CLK_GATE_SCLK1,
CLK_GATE_IP0,
CLK_GATE_IP1,
CLK_GATE_IP2,
CLK_GATE_IP3,
CLK_GATE_IP4,
CLK_GATE_IP5,
CLK_GATE_BLOCK,
APLL_LOCK,
MPLL_LOCK,
EPLL_LOCK,
VPLL_LOCK,
APLL_CON0,
APLL_CON1,
MPLL_CON,
EPLL_CON0,
EPLL_CON1,
VPLL_CON,
CLK_OUT,
};
/* Mux parent lists. */
static const char *const fin_pll_p[] __initconst = {
"xxti",
"xusbxti"
};
static const char *const mout_apll_p[] __initconst = {
"fin_pll",
"fout_apll"
};
static const char *const mout_mpll_p[] __initconst = {
"fin_pll",
"fout_mpll"
};
static const char *const mout_epll_p[] __initconst = {
"fin_pll",
"fout_epll"
};
static const char *const mout_vpllsrc_p[] __initconst = {
"fin_pll",
"sclk_hdmi27m"
};
static const char *const mout_vpll_p[] __initconst = {
"mout_vpllsrc",
"fout_vpll"
};
static const char *const mout_group1_p[] __initconst = {
"dout_a2m",
"mout_mpll",
"mout_epll",
"mout_vpll"
};
static const char *const mout_group2_p[] __initconst = {
"xxti",
"xusbxti",
"sclk_hdmi27m",
"sclk_usbphy0",
"sclk_usbphy1",
"sclk_hdmiphy",
"mout_mpll",
"mout_epll",
"mout_vpll",
};
static const char *const mout_audio0_p[] __initconst = {
"xxti",
"pcmcdclk0",
"sclk_hdmi27m",
"sclk_usbphy0",
"sclk_usbphy1",
"sclk_hdmiphy",
"mout_mpll",
"mout_epll",
"mout_vpll",
};
static const char *const mout_audio1_p[] __initconst = {
"i2scdclk1",
"pcmcdclk1",
"sclk_hdmi27m",
"sclk_usbphy0",
"sclk_usbphy1",
"sclk_hdmiphy",
"mout_mpll",
"mout_epll",
"mout_vpll",
};
static const char *const mout_audio2_p[] __initconst = {
"i2scdclk2",
"pcmcdclk2",
"sclk_hdmi27m",
"sclk_usbphy0",
"sclk_usbphy1",
"sclk_hdmiphy",
"mout_mpll",
"mout_epll",
"mout_vpll",
};
static const char *const mout_spdif_p[] __initconst = {
"dout_audio0",
"dout_audio1",
"dout_audio3",
};
static const char *const mout_group3_p[] __initconst = {
"mout_apll",
"mout_mpll"
};
static const char *const mout_group4_p[] __initconst = {
"mout_mpll",
"dout_a2m"
};
static const char *const mout_flash_p[] __initconst = {
"dout_hclkd",
"dout_hclkp"
};
static const char *const mout_dac_p[] __initconst = {
"mout_vpll",
"sclk_hdmiphy"
};
static const char *const mout_hdmi_p[] __initconst = {
"sclk_hdmiphy",
"dout_tblk"
};
static const char *const mout_mixer_p[] __initconst = {
"mout_dac",
"mout_hdmi"
};
static const char *const mout_vpll_6442_p[] __initconst = {
"fin_pll",
"fout_vpll"
};
static const char *const mout_mixer_6442_p[] __initconst = {
"mout_vpll",
"dout_mixer"
};
static const char *const mout_d0sync_6442_p[] __initconst = {
"mout_dsys",
"div_apll"
};
static const char *const mout_d1sync_6442_p[] __initconst = {
"mout_psys",
"div_apll"
};
static const char *const mout_group2_6442_p[] __initconst = {
"fin_pll",
"none",
"none",
"sclk_usbphy0",
"none",
"none",
"mout_mpll",
"mout_epll",
"mout_vpll",
};
static const char *const mout_audio0_6442_p[] __initconst = {
"fin_pll",
"pcmcdclk0",
"none",
"sclk_usbphy0",
"none",
"none",
"mout_mpll",
"mout_epll",
"mout_vpll",
};
static const char *const mout_audio1_6442_p[] __initconst = {
"i2scdclk1",
"pcmcdclk1",
"none",
"sclk_usbphy0",
"none",
"none",
"mout_mpll",
"mout_epll",
"mout_vpll",
"fin_pll",
};
static const char *const mout_clksel_p[] __initconst = {
"fout_apll_clkout",
"fout_mpll_clkout",
"fout_epll",
"fout_vpll",
"sclk_usbphy0",
"sclk_usbphy1",
"sclk_hdmiphy",
"rtc",
"rtc_tick",
"dout_hclkm",
"dout_pclkm",
"dout_hclkd",
"dout_pclkd",
"dout_hclkp",
"dout_pclkp",
"dout_apll_clkout",
"dout_hpm",
"xxti",
"xusbxti",
"div_dclk"
};
static const char *const mout_clksel_6442_p[] __initconst = {
"fout_apll_clkout",
"fout_mpll_clkout",
"fout_epll",
"fout_vpll",
"sclk_usbphy0",
"none",
"none",
"rtc",
"rtc_tick",
"none",
"none",
"dout_hclkd",
"dout_pclkd",
"dout_hclkp",
"dout_pclkp",
"dout_apll_clkout",
"none",
"fin_pll",
"none",
"div_dclk"
};
static const char *const mout_clkout_p[] __initconst = {
"dout_clkout",
"none",
"xxti",
"xusbxti"
};
/* Common fixed factor clocks. */
static const struct samsung_fixed_factor_clock ffactor_clks[] __initconst = {
FFACTOR(FOUT_APLL_CLKOUT, "fout_apll_clkout", "fout_apll", 1, 4, 0),
FFACTOR(FOUT_MPLL_CLKOUT, "fout_mpll_clkout", "fout_mpll", 1, 2, 0),
FFACTOR(DOUT_APLL_CLKOUT, "dout_apll_clkout", "dout_apll", 1, 4, 0),
};
/* PLL input mux (fin_pll), which needs to be registered before PLLs. */
static const struct samsung_mux_clock early_mux_clks[] __initconst = {
MUX_F(FIN_PLL, "fin_pll", fin_pll_p, OM_STAT, 0, 1,
CLK_MUX_READ_ONLY, 0),
};
/* Common clock muxes. */
static const struct samsung_mux_clock mux_clks[] __initconst = {
MUX(MOUT_FLASH, "mout_flash", mout_flash_p, CLK_SRC0, 28, 1),
MUX(MOUT_PSYS, "mout_psys", mout_group4_p, CLK_SRC0, 24, 1),
MUX(MOUT_DSYS, "mout_dsys", mout_group4_p, CLK_SRC0, 20, 1),
MUX(MOUT_MSYS, "mout_msys", mout_group3_p, CLK_SRC0, 16, 1),
MUX(MOUT_EPLL, "mout_epll", mout_epll_p, CLK_SRC0, 8, 1),
MUX(MOUT_MPLL, "mout_mpll", mout_mpll_p, CLK_SRC0, 4, 1),
MUX(MOUT_APLL, "mout_apll", mout_apll_p, CLK_SRC0, 0, 1),
MUX(MOUT_CLKOUT, "mout_clkout", mout_clkout_p, MISC, 8, 2),
};
/* S5PV210-specific clock muxes. */
static const struct samsung_mux_clock s5pv210_mux_clks[] __initconst = {
MUX(MOUT_VPLL, "mout_vpll", mout_vpll_p, CLK_SRC0, 12, 1),
MUX(MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, CLK_SRC1, 28, 1),
MUX(MOUT_CSIS, "mout_csis", mout_group2_p, CLK_SRC1, 24, 4),
MUX(MOUT_FIMD, "mout_fimd", mout_group2_p, CLK_SRC1, 20, 4),
MUX(MOUT_CAM1, "mout_cam1", mout_group2_p, CLK_SRC1, 16, 4),
MUX(MOUT_CAM0, "mout_cam0", mout_group2_p, CLK_SRC1, 12, 4),
MUX(MOUT_DAC, "mout_dac", mout_dac_p, CLK_SRC1, 8, 1),
MUX(MOUT_MIXER, "mout_mixer", mout_mixer_p, CLK_SRC1, 4, 1),
MUX(MOUT_HDMI, "mout_hdmi", mout_hdmi_p, CLK_SRC1, 0, 1),
MUX(MOUT_G2D, "mout_g2d", mout_group1_p, CLK_SRC2, 8, 2),
MUX(MOUT_MFC, "mout_mfc", mout_group1_p, CLK_SRC2, 4, 2),
MUX(MOUT_G3D, "mout_g3d", mout_group1_p, CLK_SRC2, 0, 2),
MUX(MOUT_FIMC2, "mout_fimc2", mout_group2_p, CLK_SRC3, 20, 4),
MUX(MOUT_FIMC1, "mout_fimc1", mout_group2_p, CLK_SRC3, 16, 4),
MUX(MOUT_FIMC0, "mout_fimc0", mout_group2_p, CLK_SRC3, 12, 4),
MUX(MOUT_UART3, "mout_uart3", mout_group2_p, CLK_SRC4, 28, 4),
MUX(MOUT_UART2, "mout_uart2", mout_group2_p, CLK_SRC4, 24, 4),
MUX(MOUT_UART1, "mout_uart1", mout_group2_p, CLK_SRC4, 20, 4),
MUX(MOUT_UART0, "mout_uart0", mout_group2_p, CLK_SRC4, 16, 4),
MUX(MOUT_MMC3, "mout_mmc3", mout_group2_p, CLK_SRC4, 12, 4),
MUX(MOUT_MMC2, "mout_mmc2", mout_group2_p, CLK_SRC4, 8, 4),
MUX(MOUT_MMC1, "mout_mmc1", mout_group2_p, CLK_SRC4, 4, 4),
MUX(MOUT_MMC0, "mout_mmc0", mout_group2_p, CLK_SRC4, 0, 4),
MUX(MOUT_PWM, "mout_pwm", mout_group2_p, CLK_SRC5, 12, 4),
MUX(MOUT_SPI1, "mout_spi1", mout_group2_p, CLK_SRC5, 4, 4),
MUX(MOUT_SPI0, "mout_spi0", mout_group2_p, CLK_SRC5, 0, 4),
MUX(MOUT_DMC0, "mout_dmc0", mout_group1_p, CLK_SRC6, 24, 2),
MUX(MOUT_PWI, "mout_pwi", mout_group2_p, CLK_SRC6, 20, 4),
MUX(MOUT_HPM, "mout_hpm", mout_group3_p, CLK_SRC6, 16, 1),
MUX(MOUT_SPDIF, "mout_spdif", mout_spdif_p, CLK_SRC6, 12, 2),
MUX(MOUT_AUDIO2, "mout_audio2", mout_audio2_p, CLK_SRC6, 8, 4),
MUX(MOUT_AUDIO1, "mout_audio1", mout_audio1_p, CLK_SRC6, 4, 4),
MUX(MOUT_AUDIO0, "mout_audio0", mout_audio0_p, CLK_SRC6, 0, 4),
MUX(MOUT_CLKSEL, "mout_clksel", mout_clksel_p, CLK_OUT, 12, 5),
};
/* S5P6442-specific clock muxes. */
static const struct samsung_mux_clock s5p6442_mux_clks[] __initconst = {
MUX(MOUT_VPLL, "mout_vpll", mout_vpll_6442_p, CLK_SRC0, 12, 1),
MUX(MOUT_FIMD, "mout_fimd", mout_group2_6442_p, CLK_SRC1, 20, 4),
MUX(MOUT_CAM1, "mout_cam1", mout_group2_6442_p, CLK_SRC1, 16, 4),
MUX(MOUT_CAM0, "mout_cam0", mout_group2_6442_p, CLK_SRC1, 12, 4),
MUX(MOUT_MIXER, "mout_mixer", mout_mixer_6442_p, CLK_SRC1, 4, 1),
MUX(MOUT_D0SYNC, "mout_d0sync", mout_d0sync_6442_p, CLK_SRC2, 28, 1),
MUX(MOUT_D1SYNC, "mout_d1sync", mout_d1sync_6442_p, CLK_SRC2, 24, 1),
MUX(MOUT_FIMC2, "mout_fimc2", mout_group2_6442_p, CLK_SRC3, 20, 4),
MUX(MOUT_FIMC1, "mout_fimc1", mout_group2_6442_p, CLK_SRC3, 16, 4),
MUX(MOUT_FIMC0, "mout_fimc0", mout_group2_6442_p, CLK_SRC3, 12, 4),
MUX(MOUT_UART2, "mout_uart2", mout_group2_6442_p, CLK_SRC4, 24, 4),
MUX(MOUT_UART1, "mout_uart1", mout_group2_6442_p, CLK_SRC4, 20, 4),
MUX(MOUT_UART0, "mout_uart0", mout_group2_6442_p, CLK_SRC4, 16, 4),
MUX(MOUT_MMC2, "mout_mmc2", mout_group2_6442_p, CLK_SRC4, 8, 4),
MUX(MOUT_MMC1, "mout_mmc1", mout_group2_6442_p, CLK_SRC4, 4, 4),
MUX(MOUT_MMC0, "mout_mmc0", mout_group2_6442_p, CLK_SRC4, 0, 4),
MUX(MOUT_PWM, "mout_pwm", mout_group2_6442_p, CLK_SRC5, 12, 4),
MUX(MOUT_SPI0, "mout_spi0", mout_group2_6442_p, CLK_SRC5, 0, 4),
MUX(MOUT_AUDIO1, "mout_audio1", mout_audio1_6442_p, CLK_SRC6, 4, 4),
MUX(MOUT_AUDIO0, "mout_audio0", mout_audio0_6442_p, CLK_SRC6, 0, 4),
MUX(MOUT_CLKSEL, "mout_clksel", mout_clksel_6442_p, CLK_OUT, 12, 5),
};
/* S5PV210-specific fixed rate clocks generated inside the SoC. */
static const struct samsung_fixed_rate_clock s5pv210_frate_clks[] __initconst = {
FRATE(SCLK_HDMI27M, "sclk_hdmi27m", NULL, 0, 27000000),
FRATE(SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 27000000),
FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, 0, 48000000),
FRATE(SCLK_USBPHY1, "sclk_usbphy1", NULL, 0, 48000000),
};
/* S5P6442-specific fixed rate clocks generated inside the SoC. */
static const struct samsung_fixed_rate_clock s5p6442_frate_clks[] __initconst = {
FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, 0, 30000000),
};
/* Common clock dividers. */
static const struct samsung_div_clock div_clks[] __initconst = {
DIV(DOUT_PCLKP, "dout_pclkp", "dout_hclkp", CLK_DIV0, 28, 3),
DIV(DOUT_PCLKD, "dout_pclkd", "dout_hclkd", CLK_DIV0, 20, 3),
DIV(DOUT_A2M, "dout_a2m", "mout_apll", CLK_DIV0, 4, 3),
DIV(DOUT_APLL, "dout_apll", "mout_msys", CLK_DIV0, 0, 3),
DIV(DOUT_FIMD, "dout_fimd", "mout_fimd", CLK_DIV1, 20, 4),
DIV(DOUT_CAM1, "dout_cam1", "mout_cam1", CLK_DIV1, 16, 4),
DIV(DOUT_CAM0, "dout_cam0", "mout_cam0", CLK_DIV1, 12, 4),
DIV(DOUT_FIMC2, "dout_fimc2", "mout_fimc2", CLK_DIV3, 20, 4),
DIV(DOUT_FIMC1, "dout_fimc1", "mout_fimc1", CLK_DIV3, 16, 4),
DIV(DOUT_FIMC0, "dout_fimc0", "mout_fimc0", CLK_DIV3, 12, 4),
DIV(DOUT_UART2, "dout_uart2", "mout_uart2", CLK_DIV4, 24, 4),
DIV(DOUT_UART1, "dout_uart1", "mout_uart1", CLK_DIV4, 20, 4),
DIV(DOUT_UART0, "dout_uart0", "mout_uart0", CLK_DIV4, 16, 4),
DIV(DOUT_MMC2, "dout_mmc2", "mout_mmc2", CLK_DIV4, 8, 4),
DIV(DOUT_MMC1, "dout_mmc1", "mout_mmc1", CLK_DIV4, 4, 4),
DIV(DOUT_MMC0, "dout_mmc0", "mout_mmc0", CLK_DIV4, 0, 4),
DIV(DOUT_PWM, "dout_pwm", "mout_pwm", CLK_DIV5, 12, 4),
DIV(DOUT_SPI0, "dout_spi0", "mout_spi0", CLK_DIV5, 0, 4),
DIV(DOUT_FLASH, "dout_flash", "mout_flash", CLK_DIV6, 12, 3),
DIV(DOUT_AUDIO1, "dout_audio1", "mout_audio1", CLK_DIV6, 4, 4),
DIV(DOUT_AUDIO0, "dout_audio0", "mout_audio0", CLK_DIV6, 0, 4),
DIV(DOUT_CLKOUT, "dout_clkout", "mout_clksel", CLK_OUT, 20, 4),
};
/* S5PV210-specific clock dividers. */
static const struct samsung_div_clock s5pv210_div_clks[] __initconst = {
DIV(DOUT_HCLKP, "dout_hclkp", "mout_psys", CLK_DIV0, 24, 4),
DIV(DOUT_HCLKD, "dout_hclkd", "mout_dsys", CLK_DIV0, 16, 4),
DIV(DOUT_PCLKM, "dout_pclkm", "dout_hclkm", CLK_DIV0, 12, 3),
DIV(DOUT_HCLKM, "dout_hclkm", "dout_apll", CLK_DIV0, 8, 3),
DIV(DOUT_CSIS, "dout_csis", "mout_csis", CLK_DIV1, 28, 4),
DIV(DOUT_TBLK, "dout_tblk", "mout_vpll", CLK_DIV1, 0, 4),
DIV(DOUT_G2D, "dout_g2d", "mout_g2d", CLK_DIV2, 8, 4),
DIV(DOUT_MFC, "dout_mfc", "mout_mfc", CLK_DIV2, 4, 4),
DIV(DOUT_G3D, "dout_g3d", "mout_g3d", CLK_DIV2, 0, 4),
DIV(DOUT_UART3, "dout_uart3", "mout_uart3", CLK_DIV4, 28, 4),
DIV(DOUT_MMC3, "dout_mmc3", "mout_mmc3", CLK_DIV4, 12, 4),
DIV(DOUT_SPI1, "dout_spi1", "mout_spi1", CLK_DIV5, 4, 4),
DIV(DOUT_DMC0, "dout_dmc0", "mout_dmc0", CLK_DIV6, 28, 4),
DIV(DOUT_PWI, "dout_pwi", "mout_pwi", CLK_DIV6, 24, 4),
DIV(DOUT_HPM, "dout_hpm", "dout_copy", CLK_DIV6, 20, 3),
DIV(DOUT_COPY, "dout_copy", "mout_hpm", CLK_DIV6, 16, 3),
DIV(DOUT_AUDIO2, "dout_audio2", "mout_audio2", CLK_DIV6, 8, 4),
DIV(DOUT_DPM, "dout_dpm", "dout_pclkp", CLK_DIV7, 8, 7),
DIV(DOUT_DVSEM, "dout_dvsem", "dout_pclkp", CLK_DIV7, 0, 7),
};
/* S5P6442-specific clock dividers. */
static const struct samsung_div_clock s5p6442_div_clks[] __initconst = {
DIV(DOUT_HCLKP, "dout_hclkp", "mout_d1sync", CLK_DIV0, 24, 4),
DIV(DOUT_HCLKD, "dout_hclkd", "mout_d0sync", CLK_DIV0, 16, 4),
DIV(DOUT_MIXER, "dout_mixer", "mout_vpll", CLK_DIV1, 0, 4),
};
/* Common clock gates. */
static const struct samsung_gate_clock gate_clks[] __initconst = {
GATE(CLK_ROTATOR, "rotator", "dout_hclkd", CLK_GATE_IP0, 29, 0, 0),
GATE(CLK_FIMC2, "fimc2", "dout_hclkd", CLK_GATE_IP0, 26, 0, 0),
GATE(CLK_FIMC1, "fimc1", "dout_hclkd", CLK_GATE_IP0, 25, 0, 0),
GATE(CLK_FIMC0, "fimc0", "dout_hclkd", CLK_GATE_IP0, 24, 0, 0),
GATE(CLK_PDMA0, "pdma0", "dout_hclkp", CLK_GATE_IP0, 3, 0, 0),
GATE(CLK_MDMA, "mdma", "dout_hclkd", CLK_GATE_IP0, 2, 0, 0),
GATE(CLK_SROMC, "sromc", "dout_hclkp", CLK_GATE_IP1, 26, 0, 0),
GATE(CLK_NANDXL, "nandxl", "dout_hclkp", CLK_GATE_IP1, 24, 0, 0),
GATE(CLK_USB_OTG, "usb_otg", "dout_hclkp", CLK_GATE_IP1, 16, 0, 0),
GATE(CLK_TVENC, "tvenc", "dout_hclkd", CLK_GATE_IP1, 10, 0, 0),
GATE(CLK_MIXER, "mixer", "dout_hclkd", CLK_GATE_IP1, 9, 0, 0),
GATE(CLK_VP, "vp", "dout_hclkd", CLK_GATE_IP1, 8, 0, 0),
GATE(CLK_FIMD, "fimd", "dout_hclkd", CLK_GATE_IP1, 0, 0, 0),
GATE(CLK_HSMMC2, "hsmmc2", "dout_hclkp", CLK_GATE_IP2, 18, 0, 0),
GATE(CLK_HSMMC1, "hsmmc1", "dout_hclkp", CLK_GATE_IP2, 17, 0, 0),
GATE(CLK_HSMMC0, "hsmmc0", "dout_hclkp", CLK_GATE_IP2, 16, 0, 0),
GATE(CLK_MODEMIF, "modemif", "dout_hclkp", CLK_GATE_IP2, 9, 0, 0),
GATE(CLK_SECSS, "secss", "dout_hclkp", CLK_GATE_IP2, 0, 0, 0),
GATE(CLK_PCM1, "pcm1", "dout_pclkp", CLK_GATE_IP3, 29, 0, 0),
GATE(CLK_PCM0, "pcm0", "dout_pclkp", CLK_GATE_IP3, 28, 0, 0),
GATE(CLK_TSADC, "tsadc", "dout_pclkp", CLK_GATE_IP3, 24, 0, 0),
GATE(CLK_PWM, "pwm", "dout_pclkp", CLK_GATE_IP3, 23, 0, 0),
GATE(CLK_WDT, "watchdog", "dout_pclkp", CLK_GATE_IP3, 22, 0, 0),
GATE(CLK_KEYIF, "keyif", "dout_pclkp", CLK_GATE_IP3, 21, 0, 0),
GATE(CLK_UART2, "uart2", "dout_pclkp", CLK_GATE_IP3, 19, 0, 0),
GATE(CLK_UART1, "uart1", "dout_pclkp", CLK_GATE_IP3, 18, 0, 0),
GATE(CLK_UART0, "uart0", "dout_pclkp", CLK_GATE_IP3, 17, 0, 0),
GATE(CLK_SYSTIMER, "systimer", "dout_pclkp", CLK_GATE_IP3, 16, 0, 0),
GATE(CLK_RTC, "rtc", "dout_pclkp", CLK_GATE_IP3, 15, 0, 0),
GATE(CLK_SPI0, "spi0", "dout_pclkp", CLK_GATE_IP3, 12, 0, 0),
GATE(CLK_I2C2, "i2c2", "dout_pclkp", CLK_GATE_IP3, 9, 0, 0),
GATE(CLK_I2C0, "i2c0", "dout_pclkp", CLK_GATE_IP3, 7, 0, 0),
GATE(CLK_I2S1, "i2s1", "dout_pclkp", CLK_GATE_IP3, 5, 0, 0),
GATE(CLK_I2S0, "i2s0", "dout_pclkp", CLK_GATE_IP3, 4, 0, 0),
GATE(CLK_SECKEY, "seckey", "dout_pclkp", CLK_GATE_IP4, 3, 0, 0),
GATE(CLK_CHIPID, "chipid", "dout_pclkp", CLK_GATE_IP4, 0, 0, 0),
GATE(SCLK_AUDIO1, "sclk_audio1", "dout_audio1", CLK_SRC_MASK0, 25,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_AUDIO0, "sclk_audio0", "dout_audio0", CLK_SRC_MASK0, 24,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_PWM, "sclk_pwm", "dout_pwm", CLK_SRC_MASK0, 19,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_SPI0, "sclk_spi0", "dout_spi0", CLK_SRC_MASK0, 16,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_UART2, "sclk_uart2", "dout_uart2", CLK_SRC_MASK0, 14,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_UART1, "sclk_uart1", "dout_uart1", CLK_SRC_MASK0, 13,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_UART0, "sclk_uart0", "dout_uart0", CLK_SRC_MASK0, 12,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_MMC2, "sclk_mmc2", "dout_mmc2", CLK_SRC_MASK0, 10,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_MMC1, "sclk_mmc1", "dout_mmc1", CLK_SRC_MASK0, 9,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_MMC0, "sclk_mmc0", "dout_mmc0", CLK_SRC_MASK0, 8,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_FIMD, "sclk_fimd", "dout_fimd", CLK_SRC_MASK0, 5,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_CAM1, "sclk_cam1", "dout_cam1", CLK_SRC_MASK0, 4,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_CAM0, "sclk_cam0", "dout_cam0", CLK_SRC_MASK0, 3,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_MIXER, "sclk_mixer", "mout_mixer", CLK_SRC_MASK0, 1,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_FIMC2, "sclk_fimc2", "dout_fimc2", CLK_SRC_MASK1, 4,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_FIMC1, "sclk_fimc1", "dout_fimc1", CLK_SRC_MASK1, 3,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_FIMC0, "sclk_fimc0", "dout_fimc0", CLK_SRC_MASK1, 2,
CLK_SET_RATE_PARENT, 0),
};
/* S5PV210-specific clock gates. */
static const struct samsung_gate_clock s5pv210_gate_clks[] __initconst = {
GATE(CLK_CSIS, "clk_csis", "dout_hclkd", CLK_GATE_IP0, 31, 0, 0),
GATE(CLK_MFC, "mfc", "dout_hclkm", CLK_GATE_IP0, 16, 0, 0),
GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0),
GATE(CLK_G3D, "g3d", "dout_hclkm", CLK_GATE_IP0, 8, 0, 0),
GATE(CLK_IMEM, "imem", "dout_hclkm", CLK_GATE_IP0, 5, 0, 0),
GATE(CLK_PDMA1, "pdma1", "dout_hclkp", CLK_GATE_IP0, 4, 0, 0),
GATE(CLK_NFCON, "nfcon", "dout_hclkp", CLK_GATE_IP1, 28, 0, 0),
GATE(CLK_CFCON, "cfcon", "dout_hclkp", CLK_GATE_IP1, 25, 0, 0),
GATE(CLK_USB_HOST, "usb_host", "dout_hclkp", CLK_GATE_IP1, 17, 0, 0),
GATE(CLK_HDMI, "hdmi", "dout_hclkd", CLK_GATE_IP1, 11, 0, 0),
GATE(CLK_DSIM, "dsim", "dout_pclkd", CLK_GATE_IP1, 2, 0, 0),
GATE(CLK_TZIC3, "tzic3", "dout_hclkm", CLK_GATE_IP2, 31, 0, 0),
GATE(CLK_TZIC2, "tzic2", "dout_hclkm", CLK_GATE_IP2, 30, 0, 0),
GATE(CLK_TZIC1, "tzic1", "dout_hclkm", CLK_GATE_IP2, 29, 0, 0),
GATE(CLK_TZIC0, "tzic0", "dout_hclkm", CLK_GATE_IP2, 28, 0, 0),
GATE(CLK_TSI, "tsi", "dout_hclkd", CLK_GATE_IP2, 20, 0, 0),
GATE(CLK_HSMMC3, "hsmmc3", "dout_hclkp", CLK_GATE_IP2, 19, 0, 0),
GATE(CLK_JTAG, "jtag", "dout_hclkp", CLK_GATE_IP2, 11, 0, 0),
GATE(CLK_CORESIGHT, "coresight", "dout_pclkp", CLK_GATE_IP2, 8, 0, 0),
GATE(CLK_SDM, "sdm", "dout_pclkm", CLK_GATE_IP2, 1, 0, 0),
GATE(CLK_PCM2, "pcm2", "dout_pclkp", CLK_GATE_IP3, 30, 0, 0),
GATE(CLK_UART3, "uart3", "dout_pclkp", CLK_GATE_IP3, 20, 0, 0),
GATE(CLK_SPI1, "spi1", "dout_pclkp", CLK_GATE_IP3, 13, 0, 0),
GATE(CLK_I2C_HDMI_PHY, "i2c_hdmi_phy", "dout_pclkd",
CLK_GATE_IP3, 11, 0, 0),
GATE(CLK_I2C1, "i2c1", "dout_pclkd", CLK_GATE_IP3, 10, 0, 0),
GATE(CLK_I2S2, "i2s2", "dout_pclkp", CLK_GATE_IP3, 6, 0, 0),
GATE(CLK_AC97, "ac97", "dout_pclkp", CLK_GATE_IP3, 1, 0, 0),
GATE(CLK_SPDIF, "spdif", "dout_pclkp", CLK_GATE_IP3, 0, 0, 0),
GATE(CLK_TZPC3, "tzpc.3", "dout_pclkd", CLK_GATE_IP4, 8, 0, 0),
GATE(CLK_TZPC2, "tzpc.2", "dout_pclkd", CLK_GATE_IP4, 7, 0, 0),
GATE(CLK_TZPC1, "tzpc.1", "dout_pclkp", CLK_GATE_IP4, 6, 0, 0),
GATE(CLK_TZPC0, "tzpc.0", "dout_pclkm", CLK_GATE_IP4, 5, 0, 0),
GATE(CLK_IEM_APC, "iem_apc", "dout_pclkp", CLK_GATE_IP4, 2, 0, 0),
GATE(CLK_IEM_IEC, "iem_iec", "dout_pclkp", CLK_GATE_IP4, 1, 0, 0),
GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP5, 29, 0, 0),
GATE(SCLK_SPDIF, "sclk_spdif", "mout_spdif", CLK_SRC_MASK0, 27,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_AUDIO2, "sclk_audio2", "dout_audio2", CLK_SRC_MASK0, 26,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_SPI1, "sclk_spi1", "dout_spi1", CLK_SRC_MASK0, 17,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_UART3, "sclk_uart3", "dout_uart3", CLK_SRC_MASK0, 15,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_MMC3, "sclk_mmc3", "dout_mmc3", CLK_SRC_MASK0, 11,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_CSIS, "sclk_csis", "dout_csis", CLK_SRC_MASK0, 6,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_DAC, "sclk_dac", "mout_dac", CLK_SRC_MASK0, 2,
CLK_SET_RATE_PARENT, 0),
GATE(SCLK_HDMI, "sclk_hdmi", "mout_hdmi", CLK_SRC_MASK0, 0,
CLK_SET_RATE_PARENT, 0),
};
/* S5P6442-specific clock gates. */
static const struct samsung_gate_clock s5p6442_gate_clks[] __initconst = {
GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP0, 28, 0, 0),
GATE(CLK_MFC, "mfc", "dout_hclkd", CLK_GATE_IP0, 16, 0, 0),
GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0),
GATE(CLK_G3D, "g3d", "dout_hclkd", CLK_GATE_IP0, 8, 0, 0),
GATE(CLK_IMEM, "imem", "dout_hclkd", CLK_GATE_IP0, 5, 0, 0),
GATE(CLK_ETB, "etb", "dout_hclkd", CLK_GATE_IP1, 31, 0, 0),
GATE(CLK_ETM, "etm", "dout_hclkd", CLK_GATE_IP1, 30, 0, 0),
GATE(CLK_I2C1, "i2c1", "dout_pclkp", CLK_GATE_IP3, 8, 0, 0),
GATE(SCLK_DAC, "sclk_dac", "mout_vpll", CLK_SRC_MASK0, 2,
CLK_SET_RATE_PARENT, 0),
};
/*
* Clock aliases for legacy clkdev look-up.
* NOTE: Needed only to support legacy board files.
*/
static const struct samsung_clock_alias s5pv210_aliases[] __initconst = {
ALIAS(DOUT_APLL, NULL, "armclk"),
ALIAS(DOUT_HCLKM, NULL, "hclk_msys"),
ALIAS(MOUT_DMC0, NULL, "sclk_dmc0"),
};
/* S5PV210-specific PLLs. */
static const struct samsung_pll_clock s5pv210_pll_clks[] __initconst = {
[apll] = PLL(pll_4508, FOUT_APLL, "fout_apll", "fin_pll",
APLL_LOCK, APLL_CON0, NULL),
[mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
MPLL_LOCK, MPLL_CON, NULL),
[epll] = PLL(pll_4600, FOUT_EPLL, "fout_epll", "fin_pll",
EPLL_LOCK, EPLL_CON0, NULL),
[vpll] = PLL(pll_4502, FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
VPLL_LOCK, VPLL_CON, NULL),
};
/* S5P6442-specific PLLs. */
static const struct samsung_pll_clock s5p6442_pll_clks[] __initconst = {
[apll] = PLL(pll_4502, FOUT_APLL, "fout_apll", "fin_pll",
APLL_LOCK, APLL_CON0, NULL),
[mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
MPLL_LOCK, MPLL_CON, NULL),
[epll] = PLL(pll_4500, FOUT_EPLL, "fout_epll", "fin_pll",
EPLL_LOCK, EPLL_CON0, NULL),
[vpll] = PLL(pll_4500, FOUT_VPLL, "fout_vpll", "fin_pll",
VPLL_LOCK, VPLL_CON, NULL),
};
static void __init __s5pv210_clk_init(struct device_node *np,
unsigned long xxti_f,
unsigned long xusbxti_f,
bool is_s5p6442)
{
struct samsung_clk_provider *ctx;
struct clk_hw **hws;
ctx = samsung_clk_init(NULL, reg_base, NR_CLKS);
hws = ctx->clk_data.hws;
samsung_clk_register_mux(ctx, early_mux_clks,
ARRAY_SIZE(early_mux_clks));
if (is_s5p6442) {
samsung_clk_register_fixed_rate(ctx, s5p6442_frate_clks,
ARRAY_SIZE(s5p6442_frate_clks));
samsung_clk_register_pll(ctx, s5p6442_pll_clks,
ARRAY_SIZE(s5p6442_pll_clks));
samsung_clk_register_mux(ctx, s5p6442_mux_clks,
ARRAY_SIZE(s5p6442_mux_clks));
samsung_clk_register_div(ctx, s5p6442_div_clks,
ARRAY_SIZE(s5p6442_div_clks));
samsung_clk_register_gate(ctx, s5p6442_gate_clks,
ARRAY_SIZE(s5p6442_gate_clks));
} else {
samsung_clk_register_fixed_rate(ctx, s5pv210_frate_clks,
ARRAY_SIZE(s5pv210_frate_clks));
samsung_clk_register_pll(ctx, s5pv210_pll_clks,
ARRAY_SIZE(s5pv210_pll_clks));
samsung_clk_register_mux(ctx, s5pv210_mux_clks,
ARRAY_SIZE(s5pv210_mux_clks));
samsung_clk_register_div(ctx, s5pv210_div_clks,
ARRAY_SIZE(s5pv210_div_clks));
samsung_clk_register_gate(ctx, s5pv210_gate_clks,
ARRAY_SIZE(s5pv210_gate_clks));
}
samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks));
samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));
samsung_clk_register_fixed_factor(ctx, ffactor_clks,
ARRAY_SIZE(ffactor_clks));
samsung_clk_register_alias(ctx, s5pv210_aliases,
ARRAY_SIZE(s5pv210_aliases));
samsung_clk_sleep_init(reg_base, s5pv210_clk_regs,
ARRAY_SIZE(s5pv210_clk_regs));
samsung_clk_of_add_provider(np, ctx);
pr_info("%s clocks: mout_apll = %ld, mout_mpll = %ld\n"
"\tmout_epll = %ld, mout_vpll = %ld\n",
is_s5p6442 ? "S5P6442" : "S5PV210",
clk_hw_get_rate(hws[MOUT_APLL]),
clk_hw_get_rate(hws[MOUT_MPLL]),
clk_hw_get_rate(hws[MOUT_EPLL]),
clk_hw_get_rate(hws[MOUT_VPLL]));
}
static void __init s5pv210_clk_dt_init(struct device_node *np)
{
reg_base = of_iomap(np, 0);
if (!reg_base)
panic("%s: failed to map registers\n", __func__);
__s5pv210_clk_init(np, 0, 0, false);
}
CLK_OF_DECLARE(s5pv210_clk, "samsung,s5pv210-clock", s5pv210_clk_dt_init);
static void __init s5p6442_clk_dt_init(struct device_node *np)
{
reg_base = of_iomap(np, 0);
if (!reg_base)
panic("%s: failed to map registers\n", __func__);
__s5pv210_clk_init(np, 0, 0, true);
}
CLK_OF_DECLARE(s5p6442_clk, "samsung,s5p6442-clock", s5p6442_clk_dt_init);
| linux-master | drivers/clk/samsung/clk-s5pv210.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
* https://www.samsung.com
* Copyright (c) 2017-2022 Tesla, Inc.
* https://www.tesla.com
*
* Common Clock Framework support for FSD SoC.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/fsd-clk.h>
#include "clk.h"
#include "clk-exynos-arm64.h"
/* Register Offset definitions for CMU_CMU (0x11c10000) */
#define PLL_LOCKTIME_PLL_SHARED0 0x0
#define PLL_LOCKTIME_PLL_SHARED1 0x4
#define PLL_LOCKTIME_PLL_SHARED2 0x8
#define PLL_LOCKTIME_PLL_SHARED3 0xc
#define PLL_CON0_PLL_SHARED0 0x100
#define PLL_CON0_PLL_SHARED1 0x120
#define PLL_CON0_PLL_SHARED2 0x140
#define PLL_CON0_PLL_SHARED3 0x160
#define MUX_CMU_CIS0_CLKMUX 0x1000
#define MUX_CMU_CIS1_CLKMUX 0x1004
#define MUX_CMU_CIS2_CLKMUX 0x1008
#define MUX_CMU_CPUCL_SWITCHMUX 0x100c
#define MUX_CMU_FSYS1_ACLK_MUX 0x1014
#define MUX_PLL_SHARED0_MUX 0x1020
#define MUX_PLL_SHARED1_MUX 0x1024
#define DIV_CMU_CIS0_CLK 0x1800
#define DIV_CMU_CIS1_CLK 0x1804
#define DIV_CMU_CIS2_CLK 0x1808
#define DIV_CMU_CMU_ACLK 0x180c
#define DIV_CMU_CPUCL_SWITCH 0x1810
#define DIV_CMU_FSYS0_SHARED0DIV4 0x181c
#define DIV_CMU_FSYS0_SHARED1DIV3 0x1820
#define DIV_CMU_FSYS0_SHARED1DIV4 0x1824
#define DIV_CMU_FSYS1_SHARED0DIV4 0x1828
#define DIV_CMU_FSYS1_SHARED0DIV8 0x182c
#define DIV_CMU_IMEM_ACLK 0x1834
#define DIV_CMU_IMEM_DMACLK 0x1838
#define DIV_CMU_IMEM_TCUCLK 0x183c
#define DIV_CMU_PERIC_SHARED0DIV20 0x1844
#define DIV_CMU_PERIC_SHARED0DIV3_TBUCLK 0x1848
#define DIV_CMU_PERIC_SHARED1DIV36 0x184c
#define DIV_CMU_PERIC_SHARED1DIV4_DMACLK 0x1850
#define DIV_PLL_SHARED0_DIV2 0x1858
#define DIV_PLL_SHARED0_DIV3 0x185c
#define DIV_PLL_SHARED0_DIV4 0x1860
#define DIV_PLL_SHARED0_DIV6 0x1864
#define DIV_PLL_SHARED1_DIV3 0x1868
#define DIV_PLL_SHARED1_DIV36 0x186c
#define DIV_PLL_SHARED1_DIV4 0x1870
#define DIV_PLL_SHARED1_DIV9 0x1874
#define GAT_CMU_CIS0_CLKGATE 0x2000
#define GAT_CMU_CIS1_CLKGATE 0x2004
#define GAT_CMU_CIS2_CLKGATE 0x2008
#define GAT_CMU_CPUCL_SWITCH_GATE 0x200c
#define GAT_CMU_FSYS0_SHARED0DIV4_GATE 0x2018
#define GAT_CMU_FSYS0_SHARED1DIV4_CLK 0x201c
#define GAT_CMU_FSYS0_SHARED1DIV4_GATE 0x2020
#define GAT_CMU_FSYS1_SHARED0DIV4_GATE 0x2024
#define GAT_CMU_FSYS1_SHARED1DIV4_GATE 0x2028
#define GAT_CMU_IMEM_ACLK_GATE 0x2030
#define GAT_CMU_IMEM_DMACLK_GATE 0x2034
#define GAT_CMU_IMEM_TCUCLK_GATE 0x2038
#define GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE 0x2040
#define GAT_CMU_PERIC_SHARED0DIVE4_GATE 0x2044
#define GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE 0x2048
#define GAT_CMU_PERIC_SHARED1DIVE4_GATE 0x204c
#define GAT_CMU_CMU_CMU_IPCLKPORT_PCLK 0x2054
#define GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK 0x2058
#define GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU 0x205c
#define GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK 0x2060
static const unsigned long cmu_clk_regs[] __initconst = {
PLL_LOCKTIME_PLL_SHARED0,
PLL_LOCKTIME_PLL_SHARED1,
PLL_LOCKTIME_PLL_SHARED2,
PLL_LOCKTIME_PLL_SHARED3,
PLL_CON0_PLL_SHARED0,
PLL_CON0_PLL_SHARED1,
PLL_CON0_PLL_SHARED2,
PLL_CON0_PLL_SHARED3,
MUX_CMU_CIS0_CLKMUX,
MUX_CMU_CIS1_CLKMUX,
MUX_CMU_CIS2_CLKMUX,
MUX_CMU_CPUCL_SWITCHMUX,
MUX_CMU_FSYS1_ACLK_MUX,
MUX_PLL_SHARED0_MUX,
MUX_PLL_SHARED1_MUX,
DIV_CMU_CIS0_CLK,
DIV_CMU_CIS1_CLK,
DIV_CMU_CIS2_CLK,
DIV_CMU_CMU_ACLK,
DIV_CMU_CPUCL_SWITCH,
DIV_CMU_FSYS0_SHARED0DIV4,
DIV_CMU_FSYS0_SHARED1DIV3,
DIV_CMU_FSYS0_SHARED1DIV4,
DIV_CMU_FSYS1_SHARED0DIV4,
DIV_CMU_FSYS1_SHARED0DIV8,
DIV_CMU_IMEM_ACLK,
DIV_CMU_IMEM_DMACLK,
DIV_CMU_IMEM_TCUCLK,
DIV_CMU_PERIC_SHARED0DIV20,
DIV_CMU_PERIC_SHARED0DIV3_TBUCLK,
DIV_CMU_PERIC_SHARED1DIV36,
DIV_CMU_PERIC_SHARED1DIV4_DMACLK,
DIV_PLL_SHARED0_DIV2,
DIV_PLL_SHARED0_DIV3,
DIV_PLL_SHARED0_DIV4,
DIV_PLL_SHARED0_DIV6,
DIV_PLL_SHARED1_DIV3,
DIV_PLL_SHARED1_DIV36,
DIV_PLL_SHARED1_DIV4,
DIV_PLL_SHARED1_DIV9,
GAT_CMU_CIS0_CLKGATE,
GAT_CMU_CIS1_CLKGATE,
GAT_CMU_CIS2_CLKGATE,
GAT_CMU_CPUCL_SWITCH_GATE,
GAT_CMU_FSYS0_SHARED0DIV4_GATE,
GAT_CMU_FSYS0_SHARED1DIV4_CLK,
GAT_CMU_FSYS0_SHARED1DIV4_GATE,
GAT_CMU_FSYS1_SHARED0DIV4_GATE,
GAT_CMU_FSYS1_SHARED1DIV4_GATE,
GAT_CMU_IMEM_ACLK_GATE,
GAT_CMU_IMEM_DMACLK_GATE,
GAT_CMU_IMEM_TCUCLK_GATE,
GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE,
GAT_CMU_PERIC_SHARED0DIVE4_GATE,
GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE,
GAT_CMU_PERIC_SHARED1DIVE4_GATE,
GAT_CMU_CMU_CMU_IPCLKPORT_PCLK,
GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK,
GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU,
GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK,
};
static const struct samsung_pll_rate_table pll_shared0_rate_table[] __initconst = {
PLL_35XX_RATE(24 * MHZ, 2000000000U, 250, 3, 0),
};
static const struct samsung_pll_rate_table pll_shared1_rate_table[] __initconst = {
PLL_35XX_RATE(24 * MHZ, 2400000000U, 200, 2, 0),
};
static const struct samsung_pll_rate_table pll_shared2_rate_table[] __initconst = {
PLL_35XX_RATE(24 * MHZ, 2400000000U, 200, 2, 0),
};
static const struct samsung_pll_rate_table pll_shared3_rate_table[] __initconst = {
PLL_35XX_RATE(24 * MHZ, 1800000000U, 150, 2, 0),
};
static const struct samsung_pll_clock cmu_pll_clks[] __initconst = {
PLL(pll_142xx, 0, "fout_pll_shared0", "fin_pll", PLL_LOCKTIME_PLL_SHARED0,
PLL_CON0_PLL_SHARED0, pll_shared0_rate_table),
PLL(pll_142xx, 0, "fout_pll_shared1", "fin_pll", PLL_LOCKTIME_PLL_SHARED1,
PLL_CON0_PLL_SHARED1, pll_shared1_rate_table),
PLL(pll_142xx, 0, "fout_pll_shared2", "fin_pll", PLL_LOCKTIME_PLL_SHARED2,
PLL_CON0_PLL_SHARED2, pll_shared2_rate_table),
PLL(pll_142xx, 0, "fout_pll_shared3", "fin_pll", PLL_LOCKTIME_PLL_SHARED3,
PLL_CON0_PLL_SHARED3, pll_shared3_rate_table),
};
/* List of parent clocks for Muxes in CMU_CMU */
PNAME(mout_cmu_shared0_pll_p) = { "fin_pll", "fout_pll_shared0" };
PNAME(mout_cmu_shared1_pll_p) = { "fin_pll", "fout_pll_shared1" };
PNAME(mout_cmu_shared2_pll_p) = { "fin_pll", "fout_pll_shared2" };
PNAME(mout_cmu_shared3_pll_p) = { "fin_pll", "fout_pll_shared3" };
PNAME(mout_cmu_cis0_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
PNAME(mout_cmu_cis1_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
PNAME(mout_cmu_cis2_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
PNAME(mout_cmu_cpucl_switchmux_p) = { "mout_cmu_pll_shared2", "mout_cmu_pll_shared0_mux" };
PNAME(mout_cmu_fsys1_aclk_mux_p) = { "dout_cmu_pll_shared0_div4", "fin_pll" };
PNAME(mout_cmu_pll_shared0_mux_p) = { "fin_pll", "mout_cmu_pll_shared0" };
PNAME(mout_cmu_pll_shared1_mux_p) = { "fin_pll", "mout_cmu_pll_shared1" };
static const struct samsung_mux_clock cmu_mux_clks[] __initconst = {
MUX(0, "mout_cmu_pll_shared0", mout_cmu_shared0_pll_p, PLL_CON0_PLL_SHARED0, 4, 1),
MUX(0, "mout_cmu_pll_shared1", mout_cmu_shared1_pll_p, PLL_CON0_PLL_SHARED1, 4, 1),
MUX(0, "mout_cmu_pll_shared2", mout_cmu_shared2_pll_p, PLL_CON0_PLL_SHARED2, 4, 1),
MUX(0, "mout_cmu_pll_shared3", mout_cmu_shared3_pll_p, PLL_CON0_PLL_SHARED3, 4, 1),
MUX(0, "mout_cmu_cis0_clkmux", mout_cmu_cis0_clkmux_p, MUX_CMU_CIS0_CLKMUX, 0, 1),
MUX(0, "mout_cmu_cis1_clkmux", mout_cmu_cis1_clkmux_p, MUX_CMU_CIS1_CLKMUX, 0, 1),
MUX(0, "mout_cmu_cis2_clkmux", mout_cmu_cis2_clkmux_p, MUX_CMU_CIS2_CLKMUX, 0, 1),
MUX(0, "mout_cmu_cpucl_switchmux", mout_cmu_cpucl_switchmux_p,
MUX_CMU_CPUCL_SWITCHMUX, 0, 1),
MUX(0, "mout_cmu_fsys1_aclk_mux", mout_cmu_fsys1_aclk_mux_p, MUX_CMU_FSYS1_ACLK_MUX, 0, 1),
MUX(0, "mout_cmu_pll_shared0_mux", mout_cmu_pll_shared0_mux_p, MUX_PLL_SHARED0_MUX, 0, 1),
MUX(0, "mout_cmu_pll_shared1_mux", mout_cmu_pll_shared1_mux_p, MUX_PLL_SHARED1_MUX, 0, 1),
};
static const struct samsung_div_clock cmu_div_clks[] __initconst = {
DIV(0, "dout_cmu_cis0_clk", "cmu_cis0_clkgate", DIV_CMU_CIS0_CLK, 0, 4),
DIV(0, "dout_cmu_cis1_clk", "cmu_cis1_clkgate", DIV_CMU_CIS1_CLK, 0, 4),
DIV(0, "dout_cmu_cis2_clk", "cmu_cis2_clkgate", DIV_CMU_CIS2_CLK, 0, 4),
DIV(0, "dout_cmu_cmu_aclk", "dout_cmu_pll_shared1_div9", DIV_CMU_CMU_ACLK, 0, 4),
DIV(0, "dout_cmu_cpucl_switch", "cmu_cpucl_switch_gate", DIV_CMU_CPUCL_SWITCH, 0, 4),
DIV(DOUT_CMU_FSYS0_SHARED0DIV4, "dout_cmu_fsys0_shared0div4", "cmu_fsys0_shared0div4_gate",
DIV_CMU_FSYS0_SHARED0DIV4, 0, 4),
DIV(0, "dout_cmu_fsys0_shared1div3", "cmu_fsys0_shared1div4_clk",
DIV_CMU_FSYS0_SHARED1DIV3, 0, 4),
DIV(DOUT_CMU_FSYS0_SHARED1DIV4, "dout_cmu_fsys0_shared1div4", "cmu_fsys0_shared1div4_gate",
DIV_CMU_FSYS0_SHARED1DIV4, 0, 4),
DIV(DOUT_CMU_FSYS1_SHARED0DIV4, "dout_cmu_fsys1_shared0div4", "cmu_fsys1_shared0div4_gate",
DIV_CMU_FSYS1_SHARED0DIV4, 0, 4),
DIV(DOUT_CMU_FSYS1_SHARED0DIV8, "dout_cmu_fsys1_shared0div8", "cmu_fsys1_shared1div4_gate",
DIV_CMU_FSYS1_SHARED0DIV8, 0, 4),
DIV(DOUT_CMU_IMEM_ACLK, "dout_cmu_imem_aclk", "cmu_imem_aclk_gate",
DIV_CMU_IMEM_ACLK, 0, 4),
DIV(DOUT_CMU_IMEM_DMACLK, "dout_cmu_imem_dmaclk", "cmu_imem_dmaclk_gate",
DIV_CMU_IMEM_DMACLK, 0, 4),
DIV(DOUT_CMU_IMEM_TCUCLK, "dout_cmu_imem_tcuclk", "cmu_imem_tcuclk_gate",
DIV_CMU_IMEM_TCUCLK, 0, 4),
DIV(DOUT_CMU_PERIC_SHARED0DIV20, "dout_cmu_peric_shared0div20",
"cmu_peric_shared0dive4_gate", DIV_CMU_PERIC_SHARED0DIV20, 0, 4),
DIV(DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK, "dout_cmu_peric_shared0div3_tbuclk",
"cmu_peric_shared0dive3_tbuclk_gate", DIV_CMU_PERIC_SHARED0DIV3_TBUCLK, 0, 4),
DIV(DOUT_CMU_PERIC_SHARED1DIV36, "dout_cmu_peric_shared1div36",
"cmu_peric_shared1dive4_gate", DIV_CMU_PERIC_SHARED1DIV36, 0, 4),
DIV(DOUT_CMU_PERIC_SHARED1DIV4_DMACLK, "dout_cmu_peric_shared1div4_dmaclk",
"cmu_peric_shared1div4_dmaclk_gate", DIV_CMU_PERIC_SHARED1DIV4_DMACLK, 0, 4),
DIV(0, "dout_cmu_pll_shared0_div2", "mout_cmu_pll_shared0_mux",
DIV_PLL_SHARED0_DIV2, 0, 4),
DIV(0, "dout_cmu_pll_shared0_div3", "mout_cmu_pll_shared0_mux",
DIV_PLL_SHARED0_DIV3, 0, 4),
DIV(DOUT_CMU_PLL_SHARED0_DIV4, "dout_cmu_pll_shared0_div4", "dout_cmu_pll_shared0_div2",
DIV_PLL_SHARED0_DIV4, 0, 4),
DIV(DOUT_CMU_PLL_SHARED0_DIV6, "dout_cmu_pll_shared0_div6", "dout_cmu_pll_shared0_div3",
DIV_PLL_SHARED0_DIV6, 0, 4),
DIV(0, "dout_cmu_pll_shared1_div3", "mout_cmu_pll_shared1_mux",
DIV_PLL_SHARED1_DIV3, 0, 4),
DIV(0, "dout_cmu_pll_shared1_div36", "dout_cmu_pll_shared1_div9",
DIV_PLL_SHARED1_DIV36, 0, 4),
DIV(0, "dout_cmu_pll_shared1_div4", "mout_cmu_pll_shared1_mux",
DIV_PLL_SHARED1_DIV4, 0, 4),
DIV(0, "dout_cmu_pll_shared1_div9", "dout_cmu_pll_shared1_div3",
DIV_PLL_SHARED1_DIV9, 0, 4),
};
static const struct samsung_gate_clock cmu_gate_clks[] __initconst = {
GATE(0, "cmu_cis0_clkgate", "mout_cmu_cis0_clkmux", GAT_CMU_CIS0_CLKGATE, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "cmu_cis1_clkgate", "mout_cmu_cis1_clkmux", GAT_CMU_CIS1_CLKGATE, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "cmu_cis2_clkgate", "mout_cmu_cis2_clkmux", GAT_CMU_CIS2_CLKGATE, 21,
CLK_IGNORE_UNUSED, 0),
GATE(CMU_CPUCL_SWITCH_GATE, "cmu_cpucl_switch_gate", "mout_cmu_cpucl_switchmux",
GAT_CMU_CPUCL_SWITCH_GATE, 21, CLK_IGNORE_UNUSED, 0),
GATE(GAT_CMU_FSYS0_SHARED0DIV4, "cmu_fsys0_shared0div4_gate", "dout_cmu_pll_shared0_div4",
GAT_CMU_FSYS0_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cmu_fsys0_shared1div4_clk", "dout_cmu_pll_shared1_div3",
GAT_CMU_FSYS0_SHARED1DIV4_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cmu_fsys0_shared1div4_gate", "dout_cmu_pll_shared1_div4",
GAT_CMU_FSYS0_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cmu_fsys1_shared0div4_gate", "mout_cmu_fsys1_aclk_mux",
GAT_CMU_FSYS1_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cmu_fsys1_shared1div4_gate", "dout_cmu_fsys1_shared0div4",
GAT_CMU_FSYS1_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cmu_imem_aclk_gate", "dout_cmu_pll_shared1_div9", GAT_CMU_IMEM_ACLK_GATE, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "cmu_imem_dmaclk_gate", "mout_cmu_pll_shared1_mux", GAT_CMU_IMEM_DMACLK_GATE, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "cmu_imem_tcuclk_gate", "dout_cmu_pll_shared0_div3", GAT_CMU_IMEM_TCUCLK_GATE, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "cmu_peric_shared0dive3_tbuclk_gate", "dout_cmu_pll_shared0_div3",
GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cmu_peric_shared0dive4_gate", "dout_cmu_pll_shared0_div4",
GAT_CMU_PERIC_SHARED0DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cmu_peric_shared1div4_dmaclk_gate", "dout_cmu_pll_shared1_div4",
GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cmu_peric_shared1dive4_gate", "dout_cmu_pll_shared1_div36",
GAT_CMU_PERIC_SHARED1DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cmu_uid_cmu_cmu_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk",
GAT_CMU_CMU_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cmu_uid_axi2apb_cmu_ipclkport_aclk", "dout_cmu_cmu_aclk",
GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cmu_uid_ns_brdg_cmu_ipclkport_clk__psoc_cmu__clk_cmu", "dout_cmu_cmu_aclk",
GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cmu_uid_sysreg_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk",
GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_cmu_info cmu_cmu_info __initconst = {
.pll_clks = cmu_pll_clks,
.nr_pll_clks = ARRAY_SIZE(cmu_pll_clks),
.mux_clks = cmu_mux_clks,
.nr_mux_clks = ARRAY_SIZE(cmu_mux_clks),
.div_clks = cmu_div_clks,
.nr_div_clks = ARRAY_SIZE(cmu_div_clks),
.gate_clks = cmu_gate_clks,
.nr_gate_clks = ARRAY_SIZE(cmu_gate_clks),
.nr_clk_ids = CMU_NR_CLK,
.clk_regs = cmu_clk_regs,
.nr_clk_regs = ARRAY_SIZE(cmu_clk_regs),
};
static void __init fsd_clk_cmu_init(struct device_node *np)
{
samsung_cmu_register_one(np, &cmu_cmu_info);
}
CLK_OF_DECLARE(fsd_clk_cmu, "tesla,fsd-clock-cmu", fsd_clk_cmu_init);
/* Register Offset definitions for CMU_PERIC (0x14010000) */
#define PLL_CON0_PERIC_DMACLK_MUX 0x100
#define PLL_CON0_PERIC_EQOS_BUSCLK_MUX 0x120
#define PLL_CON0_PERIC_PCLK_MUX 0x140
#define PLL_CON0_PERIC_TBUCLK_MUX 0x160
#define PLL_CON0_SPI_CLK 0x180
#define PLL_CON0_SPI_PCLK 0x1a0
#define PLL_CON0_UART_CLK 0x1c0
#define PLL_CON0_UART_PCLK 0x1e0
#define MUX_PERIC_EQOS_PHYRXCLK 0x1000
#define DIV_EQOS_BUSCLK 0x1800
#define DIV_PERIC_MCAN_CLK 0x1804
#define DIV_RGMII_CLK 0x1808
#define DIV_RII_CLK 0x180c
#define DIV_RMII_CLK 0x1810
#define DIV_SPI_CLK 0x1814
#define DIV_UART_CLK 0x1818
#define GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 0x2000
#define GAT_GPIO_PERIC_IPCLKPORT_OSCCLK 0x2004
#define GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK 0x2008
#define GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK 0x200c
#define GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK 0x2010
#define GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK 0x2014
#define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM 0x2018
#define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS 0x201c
#define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM 0x2020
#define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS 0x2024
#define GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK 0x2028
#define GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK 0x202c
#define GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK 0x2030
#define GAT_BUS_D_PERIC_IPCLKPORT_DMACLK 0x2034
#define GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK 0x2038
#define GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK 0x203c
#define GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK 0x2040
#define GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK 0x2044
#define GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK 0x2048
#define GAT_EQOS_TOP_IPCLKPORT_ACLK_I 0x204c
#define GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I 0x2050
#define GAT_EQOS_TOP_IPCLKPORT_HCLK_I 0x2054
#define GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 0x2058
#define GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I 0x205c
#define GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I 0x2060
#define GAT_GPIO_PERIC_IPCLKPORT_PCLK 0x2064
#define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D 0x2068
#define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P 0x206c
#define GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0 0x2070
#define GAT_PERIC_DMA0_IPCLKPORT_ACLK 0x2074
#define GAT_PERIC_DMA1_IPCLKPORT_ACLK 0x2078
#define GAT_PERIC_I2C0_IPCLKPORT_I_PCLK 0x207c
#define GAT_PERIC_I2C1_IPCLKPORT_I_PCLK 0x2080
#define GAT_PERIC_I2C2_IPCLKPORT_I_PCLK 0x2084
#define GAT_PERIC_I2C3_IPCLKPORT_I_PCLK 0x2088
#define GAT_PERIC_I2C4_IPCLKPORT_I_PCLK 0x208c
#define GAT_PERIC_I2C5_IPCLKPORT_I_PCLK 0x2090
#define GAT_PERIC_I2C6_IPCLKPORT_I_PCLK 0x2094
#define GAT_PERIC_I2C7_IPCLKPORT_I_PCLK 0x2098
#define GAT_PERIC_MCAN0_IPCLKPORT_CCLK 0x209c
#define GAT_PERIC_MCAN0_IPCLKPORT_PCLK 0x20a0
#define GAT_PERIC_MCAN1_IPCLKPORT_CCLK 0x20a4
#define GAT_PERIC_MCAN1_IPCLKPORT_PCLK 0x20a8
#define GAT_PERIC_MCAN2_IPCLKPORT_CCLK 0x20ac
#define GAT_PERIC_MCAN2_IPCLKPORT_PCLK 0x20b0
#define GAT_PERIC_MCAN3_IPCLKPORT_CCLK 0x20b4
#define GAT_PERIC_MCAN3_IPCLKPORT_PCLK 0x20b8
#define GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0 0x20bc
#define GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0 0x20c0
#define GAT_PERIC_SMMU_IPCLKPORT_CCLK 0x20c4
#define GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK 0x20c8
#define GAT_PERIC_SPI0_IPCLKPORT_I_PCLK 0x20cc
#define GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI 0x20d0
#define GAT_PERIC_SPI1_IPCLKPORT_I_PCLK 0x20d4
#define GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI 0x20d8
#define GAT_PERIC_SPI2_IPCLKPORT_I_PCLK 0x20dc
#define GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI 0x20e0
#define GAT_PERIC_TDM0_IPCLKPORT_HCLK_M 0x20e4
#define GAT_PERIC_TDM0_IPCLKPORT_PCLK 0x20e8
#define GAT_PERIC_TDM1_IPCLKPORT_HCLK_M 0x20ec
#define GAT_PERIC_TDM1_IPCLKPORT_PCLK 0x20f0
#define GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART 0x20f4
#define GAT_PERIC_UART0_IPCLKPORT_PCLK 0x20f8
#define GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART 0x20fc
#define GAT_PERIC_UART1_IPCLKPORT_PCLK 0x2100
#define GAT_SYSREG_PERI_IPCLKPORT_PCLK 0x2104
static const unsigned long peric_clk_regs[] __initconst = {
PLL_CON0_PERIC_DMACLK_MUX,
PLL_CON0_PERIC_EQOS_BUSCLK_MUX,
PLL_CON0_PERIC_PCLK_MUX,
PLL_CON0_PERIC_TBUCLK_MUX,
PLL_CON0_SPI_CLK,
PLL_CON0_SPI_PCLK,
PLL_CON0_UART_CLK,
PLL_CON0_UART_PCLK,
MUX_PERIC_EQOS_PHYRXCLK,
DIV_EQOS_BUSCLK,
DIV_PERIC_MCAN_CLK,
DIV_RGMII_CLK,
DIV_RII_CLK,
DIV_RMII_CLK,
DIV_SPI_CLK,
DIV_UART_CLK,
GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I,
GAT_GPIO_PERIC_IPCLKPORT_OSCCLK,
GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK,
GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK,
GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK,
GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK,
GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM,
GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS,
GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM,
GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS,
GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK,
GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK,
GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK,
GAT_BUS_D_PERIC_IPCLKPORT_DMACLK,
GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK,
GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK,
GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK,
GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK,
GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK,
GAT_EQOS_TOP_IPCLKPORT_ACLK_I,
GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I,
GAT_EQOS_TOP_IPCLKPORT_HCLK_I,
GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I,
GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I,
GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I,
GAT_GPIO_PERIC_IPCLKPORT_PCLK,
GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D,
GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P,
GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0,
GAT_PERIC_DMA0_IPCLKPORT_ACLK,
GAT_PERIC_DMA1_IPCLKPORT_ACLK,
GAT_PERIC_I2C0_IPCLKPORT_I_PCLK,
GAT_PERIC_I2C1_IPCLKPORT_I_PCLK,
GAT_PERIC_I2C2_IPCLKPORT_I_PCLK,
GAT_PERIC_I2C3_IPCLKPORT_I_PCLK,
GAT_PERIC_I2C4_IPCLKPORT_I_PCLK,
GAT_PERIC_I2C5_IPCLKPORT_I_PCLK,
GAT_PERIC_I2C6_IPCLKPORT_I_PCLK,
GAT_PERIC_I2C7_IPCLKPORT_I_PCLK,
GAT_PERIC_MCAN0_IPCLKPORT_CCLK,
GAT_PERIC_MCAN0_IPCLKPORT_PCLK,
GAT_PERIC_MCAN1_IPCLKPORT_CCLK,
GAT_PERIC_MCAN1_IPCLKPORT_PCLK,
GAT_PERIC_MCAN2_IPCLKPORT_CCLK,
GAT_PERIC_MCAN2_IPCLKPORT_PCLK,
GAT_PERIC_MCAN3_IPCLKPORT_CCLK,
GAT_PERIC_MCAN3_IPCLKPORT_PCLK,
GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0,
GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0,
GAT_PERIC_SMMU_IPCLKPORT_CCLK,
GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK,
GAT_PERIC_SPI0_IPCLKPORT_I_PCLK,
GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI,
GAT_PERIC_SPI1_IPCLKPORT_I_PCLK,
GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI,
GAT_PERIC_SPI2_IPCLKPORT_I_PCLK,
GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI,
GAT_PERIC_TDM0_IPCLKPORT_HCLK_M,
GAT_PERIC_TDM0_IPCLKPORT_PCLK,
GAT_PERIC_TDM1_IPCLKPORT_HCLK_M,
GAT_PERIC_TDM1_IPCLKPORT_PCLK,
GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART,
GAT_PERIC_UART0_IPCLKPORT_PCLK,
GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART,
GAT_PERIC_UART1_IPCLKPORT_PCLK,
GAT_SYSREG_PERI_IPCLKPORT_PCLK,
};
static const struct samsung_fixed_rate_clock peric_fixed_clks[] __initconst = {
FRATE(PERIC_EQOS_PHYRXCLK, "eqos_phyrxclk", NULL, 0, 125000000),
};
/* List of parent clocks for Muxes in CMU_PERIC */
PNAME(mout_peric_dmaclk_p) = { "fin_pll", "cmu_peric_shared1div4_dmaclk_gate" };
PNAME(mout_peric_eqos_busclk_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
PNAME(mout_peric_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" };
PNAME(mout_peric_tbuclk_p) = { "fin_pll", "dout_cmu_peric_shared0div3_tbuclk" };
PNAME(mout_peric_spi_clk_p) = { "fin_pll", "dout_cmu_peric_shared0div20" };
PNAME(mout_peric_spi_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" };
PNAME(mout_peric_uart_clk_p) = { "fin_pll", "dout_cmu_peric_shared1div4_dmaclk" };
PNAME(mout_peric_uart_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" };
PNAME(mout_peric_eqos_phyrxclk_p) = { "dout_peric_rgmii_clk", "eqos_phyrxclk" };
static const struct samsung_mux_clock peric_mux_clks[] __initconst = {
MUX(0, "mout_peric_dmaclk", mout_peric_dmaclk_p, PLL_CON0_PERIC_DMACLK_MUX, 4, 1),
MUX(0, "mout_peric_eqos_busclk", mout_peric_eqos_busclk_p,
PLL_CON0_PERIC_EQOS_BUSCLK_MUX, 4, 1),
MUX(0, "mout_peric_pclk", mout_peric_pclk_p, PLL_CON0_PERIC_PCLK_MUX, 4, 1),
MUX(0, "mout_peric_tbuclk", mout_peric_tbuclk_p, PLL_CON0_PERIC_TBUCLK_MUX, 4, 1),
MUX(0, "mout_peric_spi_clk", mout_peric_spi_clk_p, PLL_CON0_SPI_CLK, 4, 1),
MUX(0, "mout_peric_spi_pclk", mout_peric_spi_pclk_p, PLL_CON0_SPI_PCLK, 4, 1),
MUX(0, "mout_peric_uart_clk", mout_peric_uart_clk_p, PLL_CON0_UART_CLK, 4, 1),
MUX(0, "mout_peric_uart_pclk", mout_peric_uart_pclk_p, PLL_CON0_UART_PCLK, 4, 1),
MUX(PERIC_EQOS_PHYRXCLK_MUX, "mout_peric_eqos_phyrxclk", mout_peric_eqos_phyrxclk_p,
MUX_PERIC_EQOS_PHYRXCLK, 0, 1),
};
static const struct samsung_div_clock peric_div_clks[] __initconst = {
DIV(0, "dout_peric_eqos_busclk", "mout_peric_eqos_busclk", DIV_EQOS_BUSCLK, 0, 4),
DIV(0, "dout_peric_mcan_clk", "mout_peric_dmaclk", DIV_PERIC_MCAN_CLK, 0, 4),
DIV(PERIC_DOUT_RGMII_CLK, "dout_peric_rgmii_clk", "mout_peric_eqos_busclk",
DIV_RGMII_CLK, 0, 4),
DIV(0, "dout_peric_rii_clk", "dout_peric_rmii_clk", DIV_RII_CLK, 0, 4),
DIV(0, "dout_peric_rmii_clk", "dout_peric_rgmii_clk", DIV_RMII_CLK, 0, 4),
DIV(0, "dout_peric_spi_clk", "mout_peric_spi_clk", DIV_SPI_CLK, 0, 6),
DIV(0, "dout_peric_uart_clk", "mout_peric_uart_clk", DIV_UART_CLK, 0, 6),
};
static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, "peric_eqos_top_ipclkport_clk_ptp_ref_i",
"fin_pll", GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_gpio_peric_ipclkport_oscclk", "fin_pll", GAT_GPIO_PERIC_IPCLKPORT_OSCCLK,
21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_PCLK_ADCIF, "peric_adc0_ipclkport_i_oscclk", "fin_pll",
GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_cmu_peric_ipclkport_pclk", "mout_peric_pclk",
GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_pwm0_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_pwm1_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_async_apb_dma0_ipclkport_pclkm", "mout_peric_dmaclk",
GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_async_apb_dma0_ipclkport_pclks", "mout_peric_pclk",
GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_async_apb_dma1_ipclkport_pclkm", "mout_peric_dmaclk",
GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_async_apb_dma1_ipclkport_pclks", "mout_peric_pclk",
GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_axi2apb_peric0_ipclkport_aclk", "mout_peric_pclk",
GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_axi2apb_peric1_ipclkport_aclk", "mout_peric_pclk",
GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_axi2apb_peric2_ipclkport_aclk", "mout_peric_pclk",
GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_bus_d_peric_ipclkport_dmaclk", "mout_peric_dmaclk",
GAT_BUS_D_PERIC_IPCLKPORT_DMACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_d_peric_ipclkport_eqosclk",
"dout_peric_eqos_busclk", GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_bus_d_peric_ipclkport_mainclk", "mout_peric_tbuclk",
GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_p_peric_ipclkport_eqosclk",
"dout_peric_eqos_busclk", GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_bus_p_peric_ipclkport_mainclk", "mout_peric_pclk",
GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_bus_p_peric_ipclkport_smmuclk", "mout_peric_tbuclk",
GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_EQOS_TOP_IPCLKPORT_ACLK_I, "peric_eqos_top_ipclkport_aclk_i",
"dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_ACLK_I, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I, "peric_eqos_top_ipclkport_clk_rx_i",
"mout_peric_eqos_phyrxclk", GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_EQOS_TOP_IPCLKPORT_HCLK_I, "peric_eqos_top_ipclkport_hclk_i",
"dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_HCLK_I, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, "peric_eqos_top_ipclkport_rgmii_clk_i",
"dout_peric_rgmii_clk", GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_eqos_top_ipclkport_rii_clk_i", "dout_peric_rii_clk",
GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_eqos_top_ipclkport_rmii_clk_i", "dout_peric_rmii_clk",
GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_gpio_peric_ipclkport_pclk", "mout_peric_pclk",
GAT_GPIO_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_d", "mout_peric_tbuclk",
GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_p", "mout_peric_pclk",
GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_adc0_ipclkport_pclk_s0", "mout_peric_pclk",
GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_DMA0_IPCLKPORT_ACLK, "peric_dma0_ipclkport_aclk", "mout_peric_dmaclk",
GAT_PERIC_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_DMA1_IPCLKPORT_ACLK, "peric_dma1_ipclkport_aclk", "mout_peric_dmaclk",
GAT_PERIC_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_PCLK_HSI2C0, "peric_i2c0_ipclkport_i_pclk", "mout_peric_pclk",
GAT_PERIC_I2C0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_PCLK_HSI2C1, "peric_i2c1_ipclkport_i_pclk", "mout_peric_pclk",
GAT_PERIC_I2C1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_PCLK_HSI2C2, "peric_i2c2_ipclkport_i_pclk", "mout_peric_pclk",
GAT_PERIC_I2C2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_PCLK_HSI2C3, "peric_i2c3_ipclkport_i_pclk", "mout_peric_pclk",
GAT_PERIC_I2C3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_PCLK_HSI2C4, "peric_i2c4_ipclkport_i_pclk", "mout_peric_pclk",
GAT_PERIC_I2C4_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_PCLK_HSI2C5, "peric_i2c5_ipclkport_i_pclk", "mout_peric_pclk",
GAT_PERIC_I2C5_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_PCLK_HSI2C6, "peric_i2c6_ipclkport_i_pclk", "mout_peric_pclk",
GAT_PERIC_I2C6_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_PCLK_HSI2C7, "peric_i2c7_ipclkport_i_pclk", "mout_peric_pclk",
GAT_PERIC_I2C7_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_MCAN0_IPCLKPORT_CCLK, "peric_mcan0_ipclkport_cclk", "dout_peric_mcan_clk",
GAT_PERIC_MCAN0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_MCAN0_IPCLKPORT_PCLK, "peric_mcan0_ipclkport_pclk", "mout_peric_pclk",
GAT_PERIC_MCAN0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_MCAN1_IPCLKPORT_CCLK, "peric_mcan1_ipclkport_cclk", "dout_peric_mcan_clk",
GAT_PERIC_MCAN1_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_MCAN1_IPCLKPORT_PCLK, "peric_mcan1_ipclkport_pclk", "mout_peric_pclk",
GAT_PERIC_MCAN1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_MCAN2_IPCLKPORT_CCLK, "peric_mcan2_ipclkport_cclk", "dout_peric_mcan_clk",
GAT_PERIC_MCAN2_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_MCAN2_IPCLKPORT_PCLK, "peric_mcan2_ipclkport_pclk", "mout_peric_pclk",
GAT_PERIC_MCAN2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_MCAN3_IPCLKPORT_CCLK, "peric_mcan3_ipclkport_cclk", "dout_peric_mcan_clk",
GAT_PERIC_MCAN3_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_MCAN3_IPCLKPORT_PCLK, "peric_mcan3_ipclkport_pclk", "mout_peric_pclk",
GAT_PERIC_MCAN3_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_PWM0_IPCLKPORT_I_PCLK_S0, "peric_pwm0_ipclkport_i_pclk_s0", "mout_peric_pclk",
GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_PWM1_IPCLKPORT_I_PCLK_S0, "peric_pwm1_ipclkport_i_pclk_s0", "mout_peric_pclk",
GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_smmu_ipclkport_cclk", "mout_peric_tbuclk",
GAT_PERIC_SMMU_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_smmu_ipclkport_peric_bclk", "mout_peric_tbuclk",
GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_PCLK_SPI0, "peric_spi0_ipclkport_i_pclk", "mout_peric_spi_pclk",
GAT_PERIC_SPI0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_SCLK_SPI0, "peric_spi0_ipclkport_i_sclk_spi", "dout_peric_spi_clk",
GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_PCLK_SPI1, "peric_spi1_ipclkport_i_pclk", "mout_peric_spi_pclk",
GAT_PERIC_SPI1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_SCLK_SPI1, "peric_spi1_ipclkport_i_sclk_spi", "dout_peric_spi_clk",
GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_PCLK_SPI2, "peric_spi2_ipclkport_i_pclk", "mout_peric_spi_pclk",
GAT_PERIC_SPI2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_SCLK_SPI2, "peric_spi2_ipclkport_i_sclk_spi", "dout_peric_spi_clk",
GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_HCLK_TDM0, "peric_tdm0_ipclkport_hclk_m", "mout_peric_pclk",
GAT_PERIC_TDM0_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_PCLK_TDM0, "peric_tdm0_ipclkport_pclk", "mout_peric_pclk",
GAT_PERIC_TDM0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_HCLK_TDM1, "peric_tdm1_ipclkport_hclk_m", "mout_peric_pclk",
GAT_PERIC_TDM1_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_PCLK_TDM1, "peric_tdm1_ipclkport_pclk", "mout_peric_pclk",
GAT_PERIC_TDM1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_SCLK_UART0, "peric_uart0_ipclkport_i_sclk_uart", "dout_peric_uart_clk",
GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_PCLK_UART0, "peric_uart0_ipclkport_pclk", "mout_peric_uart_pclk",
GAT_PERIC_UART0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_SCLK_UART1, "peric_uart1_ipclkport_i_sclk_uart", "dout_peric_uart_clk",
GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0),
GATE(PERIC_PCLK_UART1, "peric_uart1_ipclkport_pclk", "mout_peric_uart_pclk",
GAT_PERIC_UART1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "peric_sysreg_peri_ipclkport_pclk", "mout_peric_pclk",
GAT_SYSREG_PERI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_cmu_info peric_cmu_info __initconst = {
.mux_clks = peric_mux_clks,
.nr_mux_clks = ARRAY_SIZE(peric_mux_clks),
.div_clks = peric_div_clks,
.nr_div_clks = ARRAY_SIZE(peric_div_clks),
.gate_clks = peric_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
.fixed_clks = peric_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(peric_fixed_clks),
.nr_clk_ids = PERIC_NR_CLK,
.clk_regs = peric_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
.clk_name = "dout_cmu_pll_shared0_div4",
};
/* Register Offset definitions for CMU_FSYS0 (0x15010000) */
#define PLL_CON0_CLKCMU_FSYS0_UNIPRO 0x100
#define PLL_CON0_CLK_FSYS0_SLAVEBUSCLK 0x140
#define PLL_CON0_EQOS_RGMII_125_MUX1 0x160
#define DIV_CLK_UNIPRO 0x1800
#define DIV_EQS_RGMII_CLK_125 0x1804
#define DIV_PERIBUS_GRP 0x1808
#define DIV_EQOS_RII_CLK2O5 0x180c
#define DIV_EQOS_RMIICLK_25 0x1810
#define DIV_PCIE_PHY_OSCCLK 0x1814
#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 0x2004
#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 0x2008
#define GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x200c
#define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK 0x2010
#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO 0x2014
#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK 0x2018
#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC 0x201c
#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 0x2020
#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 0x2024
#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 0x2028
#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 0x202c
#define GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK 0x2038
#define GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK 0x203c
#define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK 0x2040
#define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK 0x2044
#define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK 0x2048
#define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK 0x204c
#define GAT_FSYS0_CPE425_IPCLKPORT_ACLK 0x2050
#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 0x2054
#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 0x2058
#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 0x205c
#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I 0x2060
#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I 0x2064
#define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK 0x2068
#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D 0x206c
#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1 0x2070
#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P 0x2074
#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S 0x2078
#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK 0x207c
#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL 0x2080
#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0 0x2084
#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC 0x2088
#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x208c
#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC 0x2090
#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC 0x2094
#define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK 0x2098
#define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK 0x209c
#define GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK 0x20a0
#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS 0x20a4
#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK 0x20a8
#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO 0x20ac
#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK 0x20b0
#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS 0x20b4
#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK 0x20b8
#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO 0x20bc
#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK 0x20c0
#define GAT_FSYS0_RII_CLK_DIVGATE 0x20d4
static const unsigned long fsys0_clk_regs[] __initconst = {
PLL_CON0_CLKCMU_FSYS0_UNIPRO,
PLL_CON0_CLK_FSYS0_SLAVEBUSCLK,
PLL_CON0_EQOS_RGMII_125_MUX1,
DIV_CLK_UNIPRO,
DIV_EQS_RGMII_CLK_125,
DIV_PERIBUS_GRP,
DIV_EQOS_RII_CLK2O5,
DIV_EQOS_RMIICLK_25,
DIV_PCIE_PHY_OSCCLK,
GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I,
GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I,
GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK,
GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO,
GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK,
GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC,
GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24,
GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26,
GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24,
GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26,
GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK,
GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK,
GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK,
GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK,
GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK,
GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK,
GAT_FSYS0_CPE425_IPCLKPORT_ACLK,
GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I,
GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I,
GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I,
GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I,
GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I,
GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK,
GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D,
GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1,
GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P,
GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S,
GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK,
GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL,
GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0,
GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC,
GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC,
GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC,
GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK,
GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK,
GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK,
GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS,
GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK,
GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO,
GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK,
GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS,
GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK,
GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO,
GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK,
GAT_FSYS0_RII_CLK_DIVGATE,
};
static const struct samsung_fixed_rate_clock fsys0_fixed_clks[] __initconst = {
FRATE(0, "pad_eqos0_phyrxclk", NULL, 0, 125000000),
FRATE(0, "i_mphy_refclk_ixtal26", NULL, 0, 26000000),
FRATE(0, "xtal_clk_pcie_phy", NULL, 0, 100000000),
};
/* List of parent clocks for Muxes in CMU_FSYS0 */
PNAME(mout_fsys0_clkcmu_fsys0_unipro_p) = { "fin_pll", "dout_cmu_pll_shared0_div6" };
PNAME(mout_fsys0_clk_fsys0_slavebusclk_p) = { "fin_pll", "dout_cmu_fsys0_shared1div4" };
PNAME(mout_fsys0_eqos_rgmii_125_mux1_p) = { "fin_pll", "dout_cmu_fsys0_shared0div4" };
static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
MUX(0, "mout_fsys0_clkcmu_fsys0_unipro", mout_fsys0_clkcmu_fsys0_unipro_p,
PLL_CON0_CLKCMU_FSYS0_UNIPRO, 4, 1),
MUX(0, "mout_fsys0_clk_fsys0_slavebusclk", mout_fsys0_clk_fsys0_slavebusclk_p,
PLL_CON0_CLK_FSYS0_SLAVEBUSCLK, 4, 1),
MUX(0, "mout_fsys0_eqos_rgmii_125_mux1", mout_fsys0_eqos_rgmii_125_mux1_p,
PLL_CON0_EQOS_RGMII_125_MUX1, 4, 1),
};
static const struct samsung_div_clock fsys0_div_clks[] __initconst = {
DIV(0, "dout_fsys0_clk_unipro", "mout_fsys0_clkcmu_fsys0_unipro", DIV_CLK_UNIPRO, 0, 4),
DIV(0, "dout_fsys0_eqs_rgmii_clk_125", "mout_fsys0_eqos_rgmii_125_mux1",
DIV_EQS_RGMII_CLK_125, 0, 4),
DIV(FSYS0_DOUT_FSYS0_PERIBUS_GRP, "dout_fsys0_peribus_grp",
"mout_fsys0_clk_fsys0_slavebusclk", DIV_PERIBUS_GRP, 0, 4),
DIV(0, "dout_fsys0_eqos_rii_clk2o5", "fsys0_rii_clk_divgate", DIV_EQOS_RII_CLK2O5, 0, 4),
DIV(0, "dout_fsys0_eqos_rmiiclk_25", "mout_fsys0_eqos_rgmii_125_mux1",
DIV_EQOS_RMIICLK_25, 0, 5),
DIV(0, "dout_fsys0_pcie_phy_oscclk", "mout_fsys0_eqos_rgmii_125_mux1",
DIV_PCIE_PHY_OSCCLK, 0, 4),
};
static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
GATE(FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, "fsys0_eqos_top0_ipclkport_clk_rx_i",
"pad_eqos0_phyrxclk", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, 21,
CLK_IGNORE_UNUSED, 0),
GATE(PCIE_SUBCTRL_INST0_AUX_CLK_SOC,
"fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_aux_clk_soc", "fin_pll",
GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_fsys0_cmu_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp",
GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0,
"fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_pll_refclk_from_xo",
"xtal_clk_pcie_phy",
GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO, 21,
CLK_IGNORE_UNUSED, 0),
GATE(UFS0_MPHY_REFCLK_IXTAL24, "fsys0_ufs_top0_ipclkport_i_mphy_refclk_ixtal24",
"i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 21,
CLK_IGNORE_UNUSED, 0),
GATE(UFS0_MPHY_REFCLK_IXTAL26, "fsys0_ufs_top0_ipclkport_i_mphy_refclk_ixtal26",
"i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 21,
CLK_IGNORE_UNUSED, 0),
GATE(UFS1_MPHY_REFCLK_IXTAL24, "fsys0_ufs_top1_ipclkport_i_mphy_refclk_ixtal24",
"i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 21,
CLK_IGNORE_UNUSED, 0),
GATE(UFS1_MPHY_REFCLK_IXTAL26, "fsys0_ufs_top1_ipclkport_i_mphy_refclk_ixtal26",
"i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_ahbbr_fsys0_ipclkport_hclk", "dout_fsys0_peribus_grp",
GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_axi2apb_fsys0_ipclkport_aclk", "dout_fsys0_peribus_grp",
GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_bus_d_fsys0_ipclkport_mainclk", "mout_fsys0_clk_fsys0_slavebusclk",
GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_bus_d_fsys0_ipclkport_periclk", "dout_fsys0_peribus_grp",
GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_bus_p_fsys0_ipclkport_mainclk", "dout_fsys0_peribus_grp",
GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_bus_p_fsys0_ipclkport_tcuclk", "mout_fsys0_eqos_rgmii_125_mux1",
GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_cpe425_ipclkport_aclk", "mout_fsys0_clk_fsys0_slavebusclk",
GAT_FSYS0_CPE425_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, "fsys0_eqos_top0_ipclkport_aclk_i",
"dout_fsys0_peribus_grp", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, 21,
CLK_IGNORE_UNUSED, 0),
GATE(FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, "fsys0_eqos_top0_ipclkport_hclk_i",
"dout_fsys0_peribus_grp", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, 21,
CLK_IGNORE_UNUSED, 0),
GATE(FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, "fsys0_eqos_top0_ipclkport_rgmii_clk_i",
"dout_fsys0_eqs_rgmii_clk_125", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_eqos_top0_ipclkport_rii_clk_i", "dout_fsys0_eqos_rii_clk2o5",
GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_eqos_top0_ipclkport_rmii_clk_i", "dout_fsys0_eqos_rmiiclk_25",
GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_gpio_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp",
GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_gpio_fsys0_ipclkport_oscclk", "fin_pll",
GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d",
"mout_fsys0_clk_fsys0_slavebusclk",
GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d1",
"mout_fsys0_eqos_rgmii_125_mux1",
GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_p",
"dout_fsys0_peribus_grp",
GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_s",
"mout_fsys0_clk_fsys0_slavebusclk",
GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_i_apb_pclk",
"dout_fsys0_peribus_grp",
GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0,
"fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_pll_refclk_from_syspll",
"dout_fsys0_pcie_phy_oscclk",
GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL,
21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_apb_pclk_0", "dout_fsys0_peribus_grp",
GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_immortal_clk", "fin_pll",
GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PCIE_SUBCTRL_INST0_DBI_ACLK_SOC,
"fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_dbi_aclk_soc",
"dout_fsys0_peribus_grp",
GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_i_driver_apb_clk",
"dout_fsys0_peribus_grp",
GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 21,
CLK_IGNORE_UNUSED, 0),
GATE(PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC,
"fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_mstr_aclk_soc",
"mout_fsys0_clk_fsys0_slavebusclk",
GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC, 21,
CLK_IGNORE_UNUSED, 0),
GATE(PCIE_SUBCTRL_INST0_SLV_ACLK_SOC,
"fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_slv_aclk_soc",
"mout_fsys0_clk_fsys0_slavebusclk",
GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_smmu_fsys0_ipclkport_cclk", "mout_fsys0_eqos_rgmii_125_mux1",
GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_smmu_fsys0_ipclkport_fsys0_bclk", "mout_fsys0_clk_fsys0_slavebusclk",
GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_sysreg_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp",
GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(UFS0_TOP0_HCLK_BUS, "fsys0_ufs_top0_ipclkport_hclk_bus", "dout_fsys0_peribus_grp",
GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0),
GATE(UFS0_TOP0_ACLK, "fsys0_ufs_top0_ipclkport_i_aclk", "dout_fsys0_peribus_grp",
GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(UFS0_TOP0_CLK_UNIPRO, "fsys0_ufs_top0_ipclkport_i_clk_unipro", "dout_fsys0_clk_unipro",
GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0),
GATE(UFS0_TOP0_FMP_CLK, "fsys0_ufs_top0_ipclkport_i_fmp_clk", "dout_fsys0_peribus_grp",
GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(UFS1_TOP1_HCLK_BUS, "fsys0_ufs_top1_ipclkport_hclk_bus", "dout_fsys0_peribus_grp",
GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0),
GATE(UFS1_TOP1_ACLK, "fsys0_ufs_top1_ipclkport_i_aclk", "dout_fsys0_peribus_grp",
GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(UFS1_TOP1_CLK_UNIPRO, "fsys0_ufs_top1_ipclkport_i_clk_unipro", "dout_fsys0_clk_unipro",
GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0),
GATE(UFS1_TOP1_FMP_CLK, "fsys0_ufs_top1_ipclkport_i_fmp_clk", "dout_fsys0_peribus_grp",
GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys0_rii_clk_divgate", "dout_fsys0_eqos_rmiiclk_25", GAT_FSYS0_RII_CLK_DIVGATE,
21, CLK_IGNORE_UNUSED, 0),
GATE(FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, "fsys0_eqos_top0_ipclkport_clk_ptp_ref_i",
"fin_pll", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
.mux_clks = fsys0_mux_clks,
.nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
.div_clks = fsys0_div_clks,
.nr_div_clks = ARRAY_SIZE(fsys0_div_clks),
.gate_clks = fsys0_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
.fixed_clks = fsys0_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(fsys0_fixed_clks),
.nr_clk_ids = FSYS0_NR_CLK,
.clk_regs = fsys0_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
.clk_name = "dout_cmu_fsys0_shared1div4",
};
/* Register Offset definitions for CMU_FSYS1 (0x16810000) */
#define PLL_CON0_ACLK_FSYS1_BUSP_MUX 0x100
#define PLL_CON0_PCLKL_FSYS1_BUSP_MUX 0x180
#define DIV_CLK_FSYS1_PHY0_OSCCLK 0x1800
#define DIV_CLK_FSYS1_PHY1_OSCCLK 0x1804
#define GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2000
#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK 0x2004
#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK 0x2008
#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK 0x200c
#define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL 0x202c
#define GAT_FSYS1_PHY0_OSCCLLK 0x2034
#define GAT_FSYS1_PHY1_OSCCLK 0x2038
#define GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK 0x203c
#define GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK 0x2040
#define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK 0x2048
#define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK 0x204c
#define GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK 0x2054
#define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0 0x205c
#define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0 0x2064
#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK 0x206c
#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK 0x2070
#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK 0x2074
#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK 0x2078
#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK 0x207c
#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK 0x2080
#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK 0x2084
#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK 0x2088
#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK 0x208c
#define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK 0x20a4
#define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL 0x20a8
#define GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK 0x20b4
#define GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK 0x20b8
static const unsigned long fsys1_clk_regs[] __initconst = {
PLL_CON0_ACLK_FSYS1_BUSP_MUX,
PLL_CON0_PCLKL_FSYS1_BUSP_MUX,
DIV_CLK_FSYS1_PHY0_OSCCLK,
DIV_CLK_FSYS1_PHY1_OSCCLK,
GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK,
GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK,
GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK,
GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL,
GAT_FSYS1_PHY0_OSCCLLK,
GAT_FSYS1_PHY1_OSCCLK,
GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK,
GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK,
GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK,
GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK,
GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK,
GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0,
GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0,
GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK,
GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK,
GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK,
GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK,
GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK,
GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK,
GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK,
GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK,
GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK,
GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK,
GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL,
GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK,
GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK,
};
static const struct samsung_fixed_rate_clock fsys1_fixed_clks[] __initconst = {
FRATE(0, "clk_fsys1_phy0_ref", NULL, 0, 100000000),
FRATE(0, "clk_fsys1_phy1_ref", NULL, 0, 100000000),
};
/* List of parent clocks for Muxes in CMU_FSYS1 */
PNAME(mout_fsys1_pclkl_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div8" };
PNAME(mout_fsys1_aclk_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div4" };
static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
MUX(0, "mout_fsys1_pclkl_fsys1_busp_mux", mout_fsys1_pclkl_fsys1_busp_mux_p,
PLL_CON0_PCLKL_FSYS1_BUSP_MUX, 4, 1),
MUX(0, "mout_fsys1_aclk_fsys1_busp_mux", mout_fsys1_aclk_fsys1_busp_mux_p,
PLL_CON0_ACLK_FSYS1_BUSP_MUX, 4, 1),
};
static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
DIV(0, "dout_fsys1_clk_fsys1_phy0_oscclk", "fsys1_phy0_osccllk",
DIV_CLK_FSYS1_PHY0_OSCCLK, 0, 4),
DIV(0, "dout_fsys1_clk_fsys1_phy1_oscclk", "fsys1_phy1_oscclk",
DIV_CLK_FSYS1_PHY1_OSCCLK, 0, 4),
};
static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
GATE(0, "fsys1_cmu_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux",
GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_xtal", "clk_fsys1_phy0_ref",
GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys1_phy0_osccllk", "mout_fsys1_aclk_fsys1_busp_mux",
GAT_FSYS1_PHY0_OSCCLLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys1_phy1_oscclk", "mout_fsys1_aclk_fsys1_busp_mux",
GAT_FSYS1_PHY1_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys1_axi2apb_fsys1_ipclkport_aclk", "mout_fsys1_pclkl_fsys1_busp_mux",
GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys1_bus_d0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux",
GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys1_bus_s0_fsys1_ipclkport_m250clk", "mout_fsys1_pclkl_fsys1_busp_mux",
GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys1_bus_s0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux",
GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys1_cpe425_0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux",
GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_d0",
"mout_fsys1_aclk_fsys1_busp_mux",
GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_s0",
"mout_fsys1_aclk_fsys1_busp_mux",
GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0, 21,
CLK_IGNORE_UNUSED, 0),
GATE(PCIE_LINK0_IPCLKPORT_DBI_ACLK, "fsys1_pcie_link0_ipclkport_dbi_aclk",
"mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys1_pcie_link0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys1_pcie_link0_ipclkport_i_soc_ref_clk", "fin_pll",
GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys1_pcie_link0_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PCIE_LINK0_IPCLKPORT_MSTR_ACLK, "fsys1_pcie_link0_ipclkport_mstr_aclk",
"mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK, 21,
CLK_IGNORE_UNUSED, 0),
GATE(PCIE_LINK0_IPCLKPORT_SLV_ACLK, "fsys1_pcie_link0_ipclkport_slv_aclk",
"mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK, 21,
CLK_IGNORE_UNUSED, 0),
GATE(PCIE_LINK1_IPCLKPORT_DBI_ACLK, "fsys1_pcie_link1_ipclkport_dbi_aclk",
"mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys1_pcie_link1_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PCIE_LINK1_IPCLKPORT_MSTR_ACLK, "fsys1_pcie_link1_ipclkport_mstr_aclk",
"mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK, 21,
CLK_IGNORE_UNUSED, 0),
GATE(PCIE_LINK1_IPCLKPORT_SLV_ACLK, "fsys1_pcie_link1_ipclkport_slv_aclk",
"mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys1_pcie_phy0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PCIE_LINK0_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link0_ipclkport_auxclk", "fin_pll",
GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(PCIE_LINK1_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link1_ipclkport_auxclk", "fin_pll",
GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_soc_pll", "dout_fsys1_clk_fsys1_phy0_oscclk",
GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys1_sysreg_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux",
GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "fsys1_tbu0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux",
GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
.mux_clks = fsys1_mux_clks,
.nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
.div_clks = fsys1_div_clks,
.nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
.gate_clks = fsys1_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
.fixed_clks = fsys1_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(fsys1_fixed_clks),
.nr_clk_ids = FSYS1_NR_CLK,
.clk_regs = fsys1_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
.clk_name = "dout_cmu_fsys1_shared0div4",
};
/* Register Offset definitions for CMU_IMEM (0x10010000) */
#define PLL_CON0_CLK_IMEM_ACLK 0x100
#define PLL_CON0_CLK_IMEM_INTMEMCLK 0x120
#define PLL_CON0_CLK_IMEM_TCUCLK 0x140
#define DIV_OSCCLK_IMEM_TMUTSCLK 0x1800
#define GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK 0x2000
#define GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO 0x2004
#define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x2008
#define GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK 0x200c
#define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK 0x2010
#define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 0x2014
#define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK 0x2018
#define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 0x201c
#define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK 0x2020
#define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 0x2024
#define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK 0x2028
#define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 0x202c
#define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK 0x2030
#define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 0x2034
#define GAT_IMEM_WDT0_IPCLKPORT_CLK 0x2038
#define GAT_IMEM_WDT1_IPCLKPORT_CLK 0x203c
#define GAT_IMEM_WDT2_IPCLKPORT_CLK 0x2040
#define GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM 0x2044
#define GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM 0x2048
#define GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM 0x204c
#define GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS 0x2050
#define GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS 0x2054
#define GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS 0x2058
#define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM 0x205c
#define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS 0x2060
#define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM 0x2064
#define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS 0x2068
#define GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK 0x206c
#define GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK 0x2070
#define GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK 0x2074
#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK 0x2078
#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK 0x207c
#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK 0x2080
#define GAT_IMEM_DMA0_IPCLKPORT_ACLK 0x2084
#define GAT_IMEM_DMA1_IPCLKPORT_ACLK 0x2088
#define GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK 0x208c
#define GAT_IMEM_GIC_IPCLKPORT_CLK 0x2090
#define GAT_IMEM_INTMEM_IPCLKPORT_ACLK 0x2094
#define GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK 0x2098
#define GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK 0x209c
#define GAT_IMEM_MCT_IPCLKPORT_PCLK 0x20a0
#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D 0x20a4
#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU 0x20a8
#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P 0x20ac
#define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK 0x20b0
#define GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK 0x20b4
#define GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK 0x20b8
#define GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK 0x20bc
#define GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK 0x20c0
#define GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK 0x20c4
#define GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK 0x20c8
#define GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK 0x20cc
#define GAT_IMEM_TCU_IPCLKPORT_ACLK 0x20d0
#define GAT_IMEM_WDT0_IPCLKPORT_PCLK 0x20d4
#define GAT_IMEM_WDT1_IPCLKPORT_PCLK 0x20d8
#define GAT_IMEM_WDT2_IPCLKPORT_PCLK 0x20dc
static const unsigned long imem_clk_regs[] __initconst = {
PLL_CON0_CLK_IMEM_ACLK,
PLL_CON0_CLK_IMEM_INTMEMCLK,
PLL_CON0_CLK_IMEM_TCUCLK,
DIV_OSCCLK_IMEM_TMUTSCLK,
GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK,
GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO,
GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK,
GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK,
GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS,
GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK,
GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS,
GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK,
GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS,
GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK,
GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS,
GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK,
GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS,
GAT_IMEM_WDT0_IPCLKPORT_CLK,
GAT_IMEM_WDT1_IPCLKPORT_CLK,
GAT_IMEM_WDT2_IPCLKPORT_CLK,
GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM,
GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM,
GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM,
GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS,
GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS,
GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS,
GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM,
GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS,
GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM,
GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS,
GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK,
GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK,
GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK,
GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK,
GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK,
GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK,
GAT_IMEM_DMA0_IPCLKPORT_ACLK,
GAT_IMEM_DMA1_IPCLKPORT_ACLK,
GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK,
GAT_IMEM_GIC_IPCLKPORT_CLK,
GAT_IMEM_INTMEM_IPCLKPORT_ACLK,
GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK,
GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK,
GAT_IMEM_MCT_IPCLKPORT_PCLK,
GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D,
GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU,
GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P,
GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK,
GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK,
GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK,
GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK,
GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK,
GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK,
GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK,
GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK,
GAT_IMEM_TCU_IPCLKPORT_ACLK,
GAT_IMEM_WDT0_IPCLKPORT_PCLK,
GAT_IMEM_WDT1_IPCLKPORT_PCLK,
GAT_IMEM_WDT2_IPCLKPORT_PCLK,
};
PNAME(mout_imem_clk_imem_tcuclk_p) = { "fin_pll", "dout_cmu_imem_tcuclk" };
PNAME(mout_imem_clk_imem_aclk_p) = { "fin_pll", "dout_cmu_imem_aclk" };
PNAME(mout_imem_clk_imem_intmemclk_p) = { "fin_pll", "dout_cmu_imem_dmaclk" };
static const struct samsung_mux_clock imem_mux_clks[] __initconst = {
MUX(0, "mout_imem_clk_imem_tcuclk", mout_imem_clk_imem_tcuclk_p,
PLL_CON0_CLK_IMEM_TCUCLK, 4, 1),
MUX(0, "mout_imem_clk_imem_aclk", mout_imem_clk_imem_aclk_p, PLL_CON0_CLK_IMEM_ACLK, 4, 1),
MUX(0, "mout_imem_clk_imem_intmemclk", mout_imem_clk_imem_intmemclk_p,
PLL_CON0_CLK_IMEM_INTMEMCLK, 4, 1),
};
static const struct samsung_div_clock imem_div_clks[] __initconst = {
DIV(0, "dout_imem_oscclk_imem_tmutsclk", "fin_pll", DIV_OSCCLK_IMEM_TMUTSCLK, 0, 4),
};
static const struct samsung_gate_clock imem_gate_clks[] __initconst = {
GATE(0, "imem_imem_cmu_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_otp_con_top_ipclkport_i_oscclk", "fin_pll",
GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_tmu_top_ipclkport_i_clk", "fin_pll",
GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_tmu_gt_ipclkport_i_clk", "fin_pll",
GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_tmu_cpu0_ipclkport_i_clk", "fin_pll",
GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_tmu_gpu_ipclkport_i_clk", "fin_pll",
GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_mct_ipclkport_oscclk__alo", "fin_pll",
GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_wdt0_ipclkport_clk", "fin_pll",
GAT_IMEM_WDT0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_wdt1_ipclkport_clk", "fin_pll",
GAT_IMEM_WDT1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_wdt2_ipclkport_clk", "fin_pll",
GAT_IMEM_WDT2_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu0_ipclkport_i_clk_ts",
"dout_imem_oscclk_imem_tmutsclk",
GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
GATE(IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu2_ipclkport_i_clk_ts",
"dout_imem_oscclk_imem_tmutsclk",
GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
GATE(IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, "imem_tmu_gpu_ipclkport_i_clk_ts",
"dout_imem_oscclk_imem_tmutsclk",
GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
GATE(IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, "imem_tmu_gt_ipclkport_i_clk_ts",
"dout_imem_oscclk_imem_tmutsclk",
GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
GATE(IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, "imem_tmu_top_ipclkport_i_clk_ts",
"dout_imem_oscclk_imem_tmutsclk",
GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_adm_axi4st_i0_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",
GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_adm_axi4st_i1_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",
GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_adm_axi4st_i2_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",
GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_ads_axi4st_i0_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",
GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_ads_axi4st_i1_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",
GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_ads_axi4st_i2_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",
GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_async_dma0_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk",
GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_async_dma0_ipclkport_pclks", "mout_imem_clk_imem_aclk",
GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_async_dma1_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk",
GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_async_dma1_ipclkport_pclks", "mout_imem_clk_imem_aclk",
GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_axi2apb_imemp0_ipclkport_aclk", "mout_imem_clk_imem_aclk",
GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_axi2apb_imemp1_ipclkport_aclk", "mout_imem_clk_imem_aclk",
GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_bus_d_imem_ipclkport_mainclk", "mout_imem_clk_imem_tcuclk",
GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_bus_p_imem_ipclkport_mainclk", "mout_imem_clk_imem_aclk",
GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_bus_p_imem_ipclkport_pericclk", "mout_imem_clk_imem_aclk",
GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_bus_p_imem_ipclkport_tcuclk", "mout_imem_clk_imem_tcuclk",
GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(IMEM_DMA0_IPCLKPORT_ACLK, "imem_dma0_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
GAT_IMEM_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0),
GATE(IMEM_DMA1_IPCLKPORT_ACLK, "imem_dma1_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
GAT_IMEM_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0),
GATE(0, "imem_gic500_input_sync_ipclkport_clk", "mout_imem_clk_imem_aclk",
GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_gic_ipclkport_clk", "mout_imem_clk_imem_aclk",
GAT_IMEM_GIC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_intmem_ipclkport_aclk", "mout_imem_clk_imem_intmemclk",
GAT_IMEM_INTMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_mailbox_scs_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk",
GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_mailbox_sms_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk",
GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(IMEM_MCT_PCLK, "imem_mct_ipclkport_pclk", "mout_imem_clk_imem_aclk",
GAT_IMEM_MCT_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_d",
"mout_imem_clk_imem_tcuclk",
GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_tcu",
"mout_imem_clk_imem_tcuclk",
GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psoc_imem__clk_imem_p", "mout_imem_clk_imem_aclk",
GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_otp_con_top_ipclkport_pclk", "mout_imem_clk_imem_aclk",
GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_rstnsync_aclk_ipclkport_clk", "mout_imem_clk_imem_aclk",
GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_rstnsync_oscclk_ipclkport_clk", "fin_pll",
GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_rstnsync_intmemclk_ipclkport_clk", "mout_imem_clk_imem_intmemclk",
GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_rstnsync_tcuclk_ipclkport_clk", "mout_imem_clk_imem_tcuclk",
GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_sfrif_tmu0_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_sfrif_tmu1_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_tmu_cpu2_ipclkport_i_clk", "fin_pll",
GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_sysreg_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_tbu_imem_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "imem_tcu_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
GAT_IMEM_TCU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(IMEM_WDT0_IPCLKPORT_PCLK, "imem_wdt0_ipclkport_pclk", "mout_imem_clk_imem_aclk",
GAT_IMEM_WDT0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(IMEM_WDT1_IPCLKPORT_PCLK, "imem_wdt1_ipclkport_pclk", "mout_imem_clk_imem_aclk",
GAT_IMEM_WDT1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(IMEM_WDT2_IPCLKPORT_PCLK, "imem_wdt2_ipclkport_pclk", "mout_imem_clk_imem_aclk",
GAT_IMEM_WDT2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_cmu_info imem_cmu_info __initconst = {
.mux_clks = imem_mux_clks,
.nr_mux_clks = ARRAY_SIZE(imem_mux_clks),
.div_clks = imem_div_clks,
.nr_div_clks = ARRAY_SIZE(imem_div_clks),
.gate_clks = imem_gate_clks,
.nr_gate_clks = ARRAY_SIZE(imem_gate_clks),
.nr_clk_ids = IMEM_NR_CLK,
.clk_regs = imem_clk_regs,
.nr_clk_regs = ARRAY_SIZE(imem_clk_regs),
};
static void __init fsd_clk_imem_init(struct device_node *np)
{
samsung_cmu_register_one(np, &imem_cmu_info);
}
CLK_OF_DECLARE(fsd_clk_imem, "tesla,fsd-clock-imem", fsd_clk_imem_init);
/* Register Offset definitions for CMU_MFC (0x12810000) */
#define PLL_LOCKTIME_PLL_MFC 0x0
#define PLL_CON0_PLL_MFC 0x100
#define MUX_MFC_BUSD 0x1000
#define MUX_MFC_BUSP 0x1008
#define DIV_MFC_BUSD_DIV4 0x1800
#define GAT_MFC_CMU_MFC_IPCLKPORT_PCLK 0x2000
#define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM 0x2004
#define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS 0x2008
#define GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK 0x200c
#define GAT_MFC_MFC_IPCLKPORT_ACLK 0x2010
#define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D 0x2018
#define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P 0x201c
#define GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK 0x2028
#define GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK 0x202c
#define GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK 0x2030
#define GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK 0x2034
#define GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK 0x2038
#define GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK 0x203c
#define GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK 0x2040
#define GAT_MFC_BUSD_DIV4_GATE 0x2044
#define GAT_MFC_BUSD_GATE 0x2048
static const unsigned long mfc_clk_regs[] __initconst = {
PLL_LOCKTIME_PLL_MFC,
PLL_CON0_PLL_MFC,
MUX_MFC_BUSD,
MUX_MFC_BUSP,
DIV_MFC_BUSD_DIV4,
GAT_MFC_CMU_MFC_IPCLKPORT_PCLK,
GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM,
GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS,
GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK,
GAT_MFC_MFC_IPCLKPORT_ACLK,
GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D,
GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P,
GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK,
GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK,
GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK,
GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK,
GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK,
GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK,
GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK,
GAT_MFC_BUSD_DIV4_GATE,
GAT_MFC_BUSD_GATE,
};
static const struct samsung_pll_rate_table pll_mfc_rate_table[] __initconst = {
PLL_35XX_RATE(24 * MHZ, 666000000U, 111, 4, 0),
};
static const struct samsung_pll_clock mfc_pll_clks[] __initconst = {
PLL(pll_142xx, 0, "fout_pll_mfc", "fin_pll",
PLL_LOCKTIME_PLL_MFC, PLL_CON0_PLL_MFC, pll_mfc_rate_table),
};
PNAME(mout_mfc_pll_p) = { "fin_pll", "fout_pll_mfc" };
PNAME(mout_mfc_busp_p) = { "fin_pll", "dout_mfc_busd_div4" };
PNAME(mout_mfc_busd_p) = { "fin_pll", "mfc_busd_gate" };
static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
MUX(0, "mout_mfc_pll", mout_mfc_pll_p, PLL_CON0_PLL_MFC, 4, 1),
MUX(0, "mout_mfc_busp", mout_mfc_busp_p, MUX_MFC_BUSP, 0, 1),
MUX(0, "mout_mfc_busd", mout_mfc_busd_p, MUX_MFC_BUSD, 0, 1),
};
static const struct samsung_div_clock mfc_div_clks[] __initconst = {
DIV(0, "dout_mfc_busd_div4", "mfc_busd_div4_gate", DIV_MFC_BUSD_DIV4, 0, 4),
};
static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
GATE(0, "mfc_cmu_mfc_ipclkport_pclk", "mout_mfc_busp",
GAT_MFC_CMU_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_as_p_mfc_ipclkport_pclkm", "mout_mfc_busd",
GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_as_p_mfc_ipclkport_pclks", "mout_mfc_busp",
GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_axi2apb_mfc_ipclkport_aclk", "mout_mfc_busp",
GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(MFC_MFC_IPCLKPORT_ACLK, "mfc_mfc_ipclkport_aclk", "mout_mfc_busd",
GAT_MFC_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_d", "mout_mfc_busd",
GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_p", "mout_mfc_busp",
GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_ppmu_mfcd0_ipclkport_aclk", "mout_mfc_busd",
GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_ppmu_mfcd0_ipclkport_pclk", "mout_mfc_busp",
GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_ppmu_mfcd1_ipclkport_aclk", "mout_mfc_busd",
GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_ppmu_mfcd1_ipclkport_pclk", "mout_mfc_busp",
GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_sysreg_mfc_ipclkport_pclk", "mout_mfc_busp",
GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_tbu_mfcd0_ipclkport_clk", "mout_mfc_busd",
GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_tbu_mfcd1_ipclkport_clk", "mout_mfc_busd",
GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_busd_div4_gate", "mout_mfc_pll",
GAT_MFC_BUSD_DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "mfc_busd_gate", "mout_mfc_pll", GAT_MFC_BUSD_GATE, 21, CLK_IS_CRITICAL, 0),
};
static const struct samsung_cmu_info mfc_cmu_info __initconst = {
.pll_clks = mfc_pll_clks,
.nr_pll_clks = ARRAY_SIZE(mfc_pll_clks),
.mux_clks = mfc_mux_clks,
.nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
.div_clks = mfc_div_clks,
.nr_div_clks = ARRAY_SIZE(mfc_div_clks),
.gate_clks = mfc_gate_clks,
.nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
.nr_clk_ids = MFC_NR_CLK,
.clk_regs = mfc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
};
/* Register Offset definitions for CMU_CAM_CSI (0x12610000) */
#define PLL_LOCKTIME_PLL_CAM_CSI 0x0
#define PLL_CON0_PLL_CAM_CSI 0x100
#define DIV_CAM_CSI0_ACLK 0x1800
#define DIV_CAM_CSI1_ACLK 0x1804
#define DIV_CAM_CSI2_ACLK 0x1808
#define DIV_CAM_CSI_BUSD 0x180c
#define DIV_CAM_CSI_BUSP 0x1810
#define GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK 0x2000
#define GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK 0x2004
#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0 0x2008
#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1 0x200c
#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2 0x2010
#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC 0x2014
#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC 0x2018
#define GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK 0x201c
#define GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK 0x2020
#define GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK 0x2024
#define GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK 0x2028
#define GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK 0x202c
#define GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK 0x2030
#define GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK 0x2034
#define GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK 0x2038
#define GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK 0x203c
#define GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK 0x2040
#define GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK 0x2044
#define GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK 0x2048
#define GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK 0x204c
#define GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK 0x2050
#define GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK 0x2054
#define GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK 0x2058
#define GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK 0x205c
#define GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK 0x2060
#define GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK 0x2064
#define GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK 0x2068
#define GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK 0x206c
#define GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK 0x2070
#define GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK 0x2074
#define GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK 0x2078
#define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D 0x207c
#define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P 0x2080
#define GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK 0x2084
#define GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK 0x2088
static const unsigned long cam_csi_clk_regs[] __initconst = {
PLL_LOCKTIME_PLL_CAM_CSI,
PLL_CON0_PLL_CAM_CSI,
DIV_CAM_CSI0_ACLK,
DIV_CAM_CSI1_ACLK,
DIV_CAM_CSI2_ACLK,
DIV_CAM_CSI_BUSD,
DIV_CAM_CSI_BUSP,
GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK,
GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK,
GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0,
GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1,
GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2,
GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC,
GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC,
GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK,
GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK,
GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK,
GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK,
GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK,
GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK,
GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK,
GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK,
GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK,
GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK,
GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK,
GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK,
GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK,
GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK,
GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK,
GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK,
GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK,
GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK,
GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK,
GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK,
GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK,
GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK,
GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK,
GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK,
GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D,
GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P,
GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK,
GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK,
};
static const struct samsung_pll_rate_table pll_cam_csi_rate_table[] __initconst = {
PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 12, 0),
};
static const struct samsung_pll_clock cam_csi_pll_clks[] __initconst = {
PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll",
PLL_LOCKTIME_PLL_CAM_CSI, PLL_CON0_PLL_CAM_CSI, pll_cam_csi_rate_table),
};
PNAME(mout_cam_csi_pll_p) = { "fin_pll", "fout_pll_cam_csi" };
static const struct samsung_mux_clock cam_csi_mux_clks[] __initconst = {
MUX(0, "mout_cam_csi_pll", mout_cam_csi_pll_p, PLL_CON0_PLL_CAM_CSI, 4, 1),
};
static const struct samsung_div_clock cam_csi_div_clks[] __initconst = {
DIV(0, "dout_cam_csi0_aclk", "mout_cam_csi_pll", DIV_CAM_CSI0_ACLK, 0, 4),
DIV(0, "dout_cam_csi1_aclk", "mout_cam_csi_pll", DIV_CAM_CSI1_ACLK, 0, 4),
DIV(0, "dout_cam_csi2_aclk", "mout_cam_csi_pll", DIV_CAM_CSI2_ACLK, 0, 4),
DIV(0, "dout_cam_csi_busd", "mout_cam_csi_pll", DIV_CAM_CSI_BUSD, 0, 4),
DIV(0, "dout_cam_csi_busp", "mout_cam_csi_pll", DIV_CAM_CSI_BUSP, 0, 4),
};
static const struct samsung_gate_clock cam_csi_gate_clks[] __initconst = {
GATE(0, "cam_csi_cmu_cam_csi_ipclkport_pclk", "dout_cam_csi_busp",
GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_axi2apb_cam_csi_ipclkport_aclk", "dout_cam_csi_busp",
GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi0", "dout_cam_csi0_aclk",
GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi1", "dout_cam_csi1_aclk",
GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi2", "dout_cam_csi2_aclk",
GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_soc_noc", "dout_cam_csi_busd",
GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__noc", "dout_cam_csi_busd",
GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 21, CLK_IGNORE_UNUSED, 0),
GATE(CAM_CSI0_0_IPCLKPORT_I_ACLK, "cam_csi0_0_ipclkport_i_aclk", "dout_cam_csi0_aclk",
GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp",
GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CAM_CSI0_1_IPCLKPORT_I_ACLK, "cam_csi0_1_ipclkport_i_aclk", "dout_cam_csi0_aclk",
GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp",
GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CAM_CSI0_2_IPCLKPORT_I_ACLK, "cam_csi0_2_ipclkport_i_aclk", "dout_cam_csi0_aclk",
GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp",
GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CAM_CSI0_3_IPCLKPORT_I_ACLK, "cam_csi0_3_ipclkport_i_aclk", "dout_cam_csi0_aclk",
GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp",
GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CAM_CSI1_0_IPCLKPORT_I_ACLK, "cam_csi1_0_ipclkport_i_aclk", "dout_cam_csi1_aclk",
GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp",
GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CAM_CSI1_1_IPCLKPORT_I_ACLK, "cam_csi1_1_ipclkport_i_aclk", "dout_cam_csi1_aclk",
GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp",
GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CAM_CSI1_2_IPCLKPORT_I_ACLK, "cam_csi1_2_ipclkport_i_aclk", "dout_cam_csi1_aclk",
GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp",
GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CAM_CSI1_3_IPCLKPORT_I_ACLK, "cam_csi1_3_ipclkport_i_aclk", "dout_cam_csi1_aclk",
GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp",
GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CAM_CSI2_0_IPCLKPORT_I_ACLK, "cam_csi2_0_ipclkport_i_aclk", "dout_cam_csi2_aclk",
GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp",
GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CAM_CSI2_1_IPCLKPORT_I_ACLK, "cam_csi2_1_ipclkport_i_aclk", "dout_cam_csi2_aclk",
GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp",
GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CAM_CSI2_2_IPCLKPORT_I_ACLK, "cam_csi2_2_ipclkport_i_aclk", "dout_cam_csi2_aclk",
GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp",
GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CAM_CSI2_3_IPCLKPORT_I_ACLK, "cam_csi2_3_ipclkport_i_aclk", "dout_cam_csi2_aclk",
GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp",
GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_d",
"dout_cam_csi_busd",
GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_p",
"dout_cam_csi_busp",
GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P, 21,
CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_sysreg_cam_csi_ipclkport_pclk", "dout_cam_csi_busp",
GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(0, "cam_tbu_cam_csi_ipclkport_aclk", "dout_cam_csi_busd",
GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_cmu_info cam_csi_cmu_info __initconst = {
.pll_clks = cam_csi_pll_clks,
.nr_pll_clks = ARRAY_SIZE(cam_csi_pll_clks),
.mux_clks = cam_csi_mux_clks,
.nr_mux_clks = ARRAY_SIZE(cam_csi_mux_clks),
.div_clks = cam_csi_div_clks,
.nr_div_clks = ARRAY_SIZE(cam_csi_div_clks),
.gate_clks = cam_csi_gate_clks,
.nr_gate_clks = ARRAY_SIZE(cam_csi_gate_clks),
.nr_clk_ids = CAM_CSI_NR_CLK,
.clk_regs = cam_csi_clk_regs,
.nr_clk_regs = ARRAY_SIZE(cam_csi_clk_regs),
};
/**
* fsd_cmu_probe - Probe function for FSD platform clocks
* @pdev: Pointer to platform device
*
* Configure clock hierarchy for clock domains of FSD platform
*/
static int __init fsd_cmu_probe(struct platform_device *pdev)
{
const struct samsung_cmu_info *info;
struct device *dev = &pdev->dev;
info = of_device_get_match_data(dev);
exynos_arm64_register_cmu(dev, dev->of_node, info);
return 0;
}
/* CMUs which belong to Power Domains and need runtime PM to be implemented */
static const struct of_device_id fsd_cmu_of_match[] = {
{
.compatible = "tesla,fsd-clock-peric",
.data = &peric_cmu_info,
}, {
.compatible = "tesla,fsd-clock-fsys0",
.data = &fsys0_cmu_info,
}, {
.compatible = "tesla,fsd-clock-fsys1",
.data = &fsys1_cmu_info,
}, {
.compatible = "tesla,fsd-clock-mfc",
.data = &mfc_cmu_info,
}, {
.compatible = "tesla,fsd-clock-cam_csi",
.data = &cam_csi_cmu_info,
}, {
},
};
static struct platform_driver fsd_cmu_driver __refdata = {
.driver = {
.name = "fsd-cmu",
.of_match_table = fsd_cmu_of_match,
.suppress_bind_attrs = true,
},
.probe = fsd_cmu_probe,
};
static int __init fsd_cmu_init(void)
{
return platform_driver_register(&fsd_cmu_driver);
}
core_initcall(fsd_cmu_init);
| linux-master | drivers/clk/samsung/clk-fsd.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Author: Naveen Krishna Ch <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include "clk.h"
#include <dt-bindings/clock/exynos7-clk.h>
/* Register Offset definitions for CMU_TOPC (0x10570000) */
#define CC_PLL_LOCK 0x0000
#define BUS0_PLL_LOCK 0x0004
#define BUS1_DPLL_LOCK 0x0008
#define MFC_PLL_LOCK 0x000C
#define AUD_PLL_LOCK 0x0010
#define CC_PLL_CON0 0x0100
#define BUS0_PLL_CON0 0x0110
#define BUS1_DPLL_CON0 0x0120
#define MFC_PLL_CON0 0x0130
#define AUD_PLL_CON0 0x0140
#define MUX_SEL_TOPC0 0x0200
#define MUX_SEL_TOPC1 0x0204
#define MUX_SEL_TOPC2 0x0208
#define MUX_SEL_TOPC3 0x020C
#define DIV_TOPC0 0x0600
#define DIV_TOPC1 0x0604
#define DIV_TOPC3 0x060C
#define ENABLE_ACLK_TOPC0 0x0800
#define ENABLE_ACLK_TOPC1 0x0804
#define ENABLE_SCLK_TOPC1 0x0A04
static const struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initconst = {
FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0),
FFACTOR(0, "ffac_topc_bus0_pll_div4",
"ffac_topc_bus0_pll_div2", 1, 2, 0),
FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_topc_bus1_pll", 1, 2, 0),
FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_topc_cc_pll", 1, 2, 0),
FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_topc_mfc_pll", 1, 2, 0),
};
/* List of parent clocks for Muxes in CMU_TOPC */
PNAME(mout_topc_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" };
PNAME(mout_topc_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" };
PNAME(mout_topc_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" };
PNAME(mout_topc_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" };
PNAME(mout_topc_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" };
PNAME(mout_topc_group2) = { "mout_topc_bus0_pll_half",
"mout_topc_bus1_pll_half", "mout_topc_cc_pll_half",
"mout_topc_mfc_pll_half" };
PNAME(mout_topc_bus0_pll_half_p) = { "mout_topc_bus0_pll",
"ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"};
PNAME(mout_topc_bus1_pll_half_p) = { "mout_topc_bus1_pll",
"ffac_topc_bus1_pll_div2"};
PNAME(mout_topc_cc_pll_half_p) = { "mout_topc_cc_pll",
"ffac_topc_cc_pll_div2"};
PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll",
"ffac_topc_mfc_pll_div2"};
PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll",
"ffac_topc_bus0_pll_div2"};
static const unsigned long topc_clk_regs[] __initconst = {
CC_PLL_LOCK,
BUS0_PLL_LOCK,
BUS1_DPLL_LOCK,
MFC_PLL_LOCK,
AUD_PLL_LOCK,
CC_PLL_CON0,
BUS0_PLL_CON0,
BUS1_DPLL_CON0,
MFC_PLL_CON0,
AUD_PLL_CON0,
MUX_SEL_TOPC0,
MUX_SEL_TOPC1,
MUX_SEL_TOPC2,
MUX_SEL_TOPC3,
DIV_TOPC0,
DIV_TOPC1,
DIV_TOPC3,
};
static const struct samsung_mux_clock topc_mux_clks[] __initconst = {
MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p,
MUX_SEL_TOPC0, 0, 1),
MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p,
MUX_SEL_TOPC0, 4, 1),
MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p,
MUX_SEL_TOPC0, 8, 1),
MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p,
MUX_SEL_TOPC0, 12, 1),
MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p,
MUX_SEL_TOPC0, 16, 2),
MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p,
MUX_SEL_TOPC0, 20, 1),
MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p,
MUX_SEL_TOPC0, 24, 1),
MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p,
MUX_SEL_TOPC0, 28, 1),
MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p,
MUX_SEL_TOPC1, 0, 1),
MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p,
MUX_SEL_TOPC1, 16, 1),
MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2),
MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
};
static const struct samsung_div_clock topc_div_clks[] __initconst = {
DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
DIV_TOPC0, 4, 4),
DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532",
DIV_TOPC1, 20, 4),
DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
DIV_TOPC1, 24, 4),
DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_topc_bus0_pll_out",
DIV_TOPC3, 0, 4),
DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_topc_bus1_pll",
DIV_TOPC3, 8, 4),
DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_topc_cc_pll",
DIV_TOPC3, 12, 4),
DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_topc_mfc_pll",
DIV_TOPC3, 16, 4),
DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_topc_aud_pll",
DIV_TOPC3, 28, 4),
};
static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = {
PLL_36XX_RATE(24 * MHZ, 491519897, 20, 1, 0, 31457),
{},
};
static const struct samsung_gate_clock topc_gate_clks[] __initconst = {
GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133",
ENABLE_ACLK_TOPC0, 4, CLK_IS_CRITICAL, 0),
GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
ENABLE_ACLK_TOPC1, 20, 0, 0),
GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66",
ENABLE_ACLK_TOPC1, 24, 0, 0),
GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll",
ENABLE_SCLK_TOPC1, 20, 0, 0),
GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll",
ENABLE_SCLK_TOPC1, 17, 0, 0),
GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll",
ENABLE_SCLK_TOPC1, 16, 0, 0),
GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll",
ENABLE_SCLK_TOPC1, 13, 0, 0),
GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll",
ENABLE_SCLK_TOPC1, 12, 0, 0),
GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll",
ENABLE_SCLK_TOPC1, 5, 0, 0),
GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll",
ENABLE_SCLK_TOPC1, 4, 0, 0),
GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll",
ENABLE_SCLK_TOPC1, 1, 0, 0),
GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll",
ENABLE_SCLK_TOPC1, 0, 0, 0),
};
static const struct samsung_pll_clock topc_pll_clks[] __initconst = {
PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
BUS0_PLL_CON0, NULL),
PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
CC_PLL_CON0, NULL),
PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
BUS1_DPLL_CON0, NULL),
PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
MFC_PLL_CON0, NULL),
PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
AUD_PLL_CON0, pll1460x_24mhz_tbl),
};
static const struct samsung_cmu_info topc_cmu_info __initconst = {
.pll_clks = topc_pll_clks,
.nr_pll_clks = ARRAY_SIZE(topc_pll_clks),
.mux_clks = topc_mux_clks,
.nr_mux_clks = ARRAY_SIZE(topc_mux_clks),
.div_clks = topc_div_clks,
.nr_div_clks = ARRAY_SIZE(topc_div_clks),
.gate_clks = topc_gate_clks,
.nr_gate_clks = ARRAY_SIZE(topc_gate_clks),
.fixed_factor_clks = topc_fixed_factor_clks,
.nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks),
.nr_clk_ids = TOPC_NR_CLK,
.clk_regs = topc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(topc_clk_regs),
};
static void __init exynos7_clk_topc_init(struct device_node *np)
{
samsung_cmu_register_one(np, &topc_cmu_info);
}
CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
exynos7_clk_topc_init);
/* Register Offset definitions for CMU_TOP0 (0x105D0000) */
#define MUX_SEL_TOP00 0x0200
#define MUX_SEL_TOP01 0x0204
#define MUX_SEL_TOP03 0x020C
#define MUX_SEL_TOP0_PERIC0 0x0230
#define MUX_SEL_TOP0_PERIC1 0x0234
#define MUX_SEL_TOP0_PERIC2 0x0238
#define MUX_SEL_TOP0_PERIC3 0x023C
#define DIV_TOP03 0x060C
#define DIV_TOP0_PERIC0 0x0630
#define DIV_TOP0_PERIC1 0x0634
#define DIV_TOP0_PERIC2 0x0638
#define DIV_TOP0_PERIC3 0x063C
#define ENABLE_ACLK_TOP03 0x080C
#define ENABLE_SCLK_TOP0_PERIC0 0x0A30
#define ENABLE_SCLK_TOP0_PERIC1 0x0A34
#define ENABLE_SCLK_TOP0_PERIC2 0x0A38
#define ENABLE_SCLK_TOP0_PERIC3 0x0A3C
/* List of parent clocks for Muxes in CMU_TOP0 */
PNAME(mout_top0_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_a" };
PNAME(mout_top0_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_a" };
PNAME(mout_top0_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_a" };
PNAME(mout_top0_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_a" };
PNAME(mout_top0_aud_pll_user_p) = { "fin_pll", "sclk_aud_pll" };
PNAME(mout_top0_bus0_pll_half_p) = {"mout_top0_bus0_pll_user",
"ffac_top0_bus0_pll_div2"};
PNAME(mout_top0_bus1_pll_half_p) = {"mout_top0_bus1_pll_user",
"ffac_top0_bus1_pll_div2"};
PNAME(mout_top0_cc_pll_half_p) = {"mout_top0_cc_pll_user",
"ffac_top0_cc_pll_div2"};
PNAME(mout_top0_mfc_pll_half_p) = {"mout_top0_mfc_pll_user",
"ffac_top0_mfc_pll_div2"};
PNAME(mout_top0_group1) = {"mout_top0_bus0_pll_half",
"mout_top0_bus1_pll_half", "mout_top0_cc_pll_half",
"mout_top0_mfc_pll_half"};
PNAME(mout_top0_group3) = {"ioclk_audiocdclk0",
"ioclk_audiocdclk1", "ioclk_spdif_extclk",
"mout_top0_aud_pll_user", "mout_top0_bus0_pll_half",
"mout_top0_bus1_pll_half"};
PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll_user",
"mout_top0_bus0_pll_half", "mout_top0_bus1_pll_half"};
static const unsigned long top0_clk_regs[] __initconst = {
MUX_SEL_TOP00,
MUX_SEL_TOP01,
MUX_SEL_TOP03,
MUX_SEL_TOP0_PERIC0,
MUX_SEL_TOP0_PERIC1,
MUX_SEL_TOP0_PERIC2,
MUX_SEL_TOP0_PERIC3,
DIV_TOP03,
DIV_TOP0_PERIC0,
DIV_TOP0_PERIC1,
DIV_TOP0_PERIC2,
DIV_TOP0_PERIC3,
ENABLE_SCLK_TOP0_PERIC0,
ENABLE_SCLK_TOP0_PERIC1,
ENABLE_SCLK_TOP0_PERIC2,
ENABLE_SCLK_TOP0_PERIC3,
};
static const struct samsung_mux_clock top0_mux_clks[] __initconst = {
MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p,
MUX_SEL_TOP00, 0, 1),
MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p,
MUX_SEL_TOP00, 4, 1),
MUX(0, "mout_top0_cc_pll_user", mout_top0_cc_pll_user_p,
MUX_SEL_TOP00, 8, 1),
MUX(0, "mout_top0_bus1_pll_user", mout_top0_bus1_pll_user_p,
MUX_SEL_TOP00, 12, 1),
MUX(0, "mout_top0_bus0_pll_user", mout_top0_bus0_pll_user_p,
MUX_SEL_TOP00, 16, 1),
MUX(0, "mout_top0_mfc_pll_half", mout_top0_mfc_pll_half_p,
MUX_SEL_TOP01, 4, 1),
MUX(0, "mout_top0_cc_pll_half", mout_top0_cc_pll_half_p,
MUX_SEL_TOP01, 8, 1),
MUX(0, "mout_top0_bus1_pll_half", mout_top0_bus1_pll_half_p,
MUX_SEL_TOP01, 12, 1),
MUX(0, "mout_top0_bus0_pll_half", mout_top0_bus0_pll_half_p,
MUX_SEL_TOP01, 16, 1),
MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3),
MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2),
MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2),
MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
};
static const struct samsung_div_clock top0_div_clks[] __initconst = {
DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66",
DIV_TOP03, 12, 6),
DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
DIV_TOP03, 20, 6),
DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4),
DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12),
DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10),
DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12),
DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12),
DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12),
DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12),
DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12),
};
static const struct samsung_gate_clock top0_gate_clks[] __initconst = {
GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66",
ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0),
GATE(CLK_ACLK_PERIC1_66, "aclk_peric1_66", "dout_aclk_peric1_66",
ENABLE_ACLK_TOP03, 12, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif",
ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1",
ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1",
ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1",
ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3",
ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2",
ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0),
GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1",
ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4",
ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initconst = {
FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll_user",
1, 2, 0),
FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll_user",
1, 2, 0),
FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll_user", 1, 2, 0),
FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0),
};
static const struct samsung_cmu_info top0_cmu_info __initconst = {
.mux_clks = top0_mux_clks,
.nr_mux_clks = ARRAY_SIZE(top0_mux_clks),
.div_clks = top0_div_clks,
.nr_div_clks = ARRAY_SIZE(top0_div_clks),
.gate_clks = top0_gate_clks,
.nr_gate_clks = ARRAY_SIZE(top0_gate_clks),
.fixed_factor_clks = top0_fixed_factor_clks,
.nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks),
.nr_clk_ids = TOP0_NR_CLK,
.clk_regs = top0_clk_regs,
.nr_clk_regs = ARRAY_SIZE(top0_clk_regs),
};
static void __init exynos7_clk_top0_init(struct device_node *np)
{
samsung_cmu_register_one(np, &top0_cmu_info);
}
CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
exynos7_clk_top0_init);
/* Register Offset definitions for CMU_TOP1 (0x105E0000) */
#define MUX_SEL_TOP10 0x0200
#define MUX_SEL_TOP11 0x0204
#define MUX_SEL_TOP13 0x020C
#define MUX_SEL_TOP1_FSYS0 0x0224
#define MUX_SEL_TOP1_FSYS1 0x0228
#define MUX_SEL_TOP1_FSYS11 0x022C
#define DIV_TOP13 0x060C
#define DIV_TOP1_FSYS0 0x0624
#define DIV_TOP1_FSYS1 0x0628
#define DIV_TOP1_FSYS11 0x062C
#define ENABLE_ACLK_TOP13 0x080C
#define ENABLE_SCLK_TOP1_FSYS0 0x0A24
#define ENABLE_SCLK_TOP1_FSYS1 0x0A28
#define ENABLE_SCLK_TOP1_FSYS11 0x0A2C
/* List of parent clocks for Muxes in CMU_TOP1 */
PNAME(mout_top1_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_b" };
PNAME(mout_top1_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_b" };
PNAME(mout_top1_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_b" };
PNAME(mout_top1_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_b" };
PNAME(mout_top1_bus0_pll_half_p) = {"mout_top1_bus0_pll_user",
"ffac_top1_bus0_pll_div2"};
PNAME(mout_top1_bus1_pll_half_p) = {"mout_top1_bus1_pll_user",
"ffac_top1_bus1_pll_div2"};
PNAME(mout_top1_cc_pll_half_p) = {"mout_top1_cc_pll_user",
"ffac_top1_cc_pll_div2"};
PNAME(mout_top1_mfc_pll_half_p) = {"mout_top1_mfc_pll_user",
"ffac_top1_mfc_pll_div2"};
PNAME(mout_top1_group1) = {"mout_top1_bus0_pll_half",
"mout_top1_bus1_pll_half", "mout_top1_cc_pll_half",
"mout_top1_mfc_pll_half"};
static const unsigned long top1_clk_regs[] __initconst = {
MUX_SEL_TOP10,
MUX_SEL_TOP11,
MUX_SEL_TOP13,
MUX_SEL_TOP1_FSYS0,
MUX_SEL_TOP1_FSYS1,
MUX_SEL_TOP1_FSYS11,
DIV_TOP13,
DIV_TOP1_FSYS0,
DIV_TOP1_FSYS1,
DIV_TOP1_FSYS11,
ENABLE_ACLK_TOP13,
ENABLE_SCLK_TOP1_FSYS0,
ENABLE_SCLK_TOP1_FSYS1,
ENABLE_SCLK_TOP1_FSYS11,
};
static const struct samsung_mux_clock top1_mux_clks[] __initconst = {
MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p,
MUX_SEL_TOP10, 4, 1),
MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p,
MUX_SEL_TOP10, 8, 1),
MUX(0, "mout_top1_bus1_pll_user", mout_top1_bus1_pll_user_p,
MUX_SEL_TOP10, 12, 1),
MUX(0, "mout_top1_bus0_pll_user", mout_top1_bus0_pll_user_p,
MUX_SEL_TOP10, 16, 1),
MUX(0, "mout_top1_mfc_pll_half", mout_top1_mfc_pll_half_p,
MUX_SEL_TOP11, 4, 1),
MUX(0, "mout_top1_cc_pll_half", mout_top1_cc_pll_half_p,
MUX_SEL_TOP11, 8, 1),
MUX(0, "mout_top1_bus1_pll_half", mout_top1_bus1_pll_half_p,
MUX_SEL_TOP11, 12, 1),
MUX(0, "mout_top1_bus0_pll_half", mout_top1_bus0_pll_half_p,
MUX_SEL_TOP11, 16, 1),
MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
MUX(0, "mout_sclk_phy_fsys0_26m", mout_top1_group1,
MUX_SEL_TOP1_FSYS0, 0, 2),
MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2),
MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
MUX_SEL_TOP1_FSYS0, 28, 2),
MUX(0, "mout_sclk_phy_fsys1", mout_top1_group1,
MUX_SEL_TOP1_FSYS1, 0, 2),
MUX(0, "mout_sclk_ufsunipro20", mout_top1_group1,
MUX_SEL_TOP1_FSYS1, 16, 2),
MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2),
MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2),
MUX(0, "mout_sclk_phy_fsys1_26m", mout_top1_group1,
MUX_SEL_TOP1_FSYS11, 24, 2),
};
static const struct samsung_div_clock top1_div_clks[] __initconst = {
DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
DIV_TOP13, 24, 4),
DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
DIV_TOP13, 28, 4),
DIV(DOUT_SCLK_PHY_FSYS1, "dout_sclk_phy_fsys1",
"mout_sclk_phy_fsys1", DIV_TOP1_FSYS1, 0, 6),
DIV(DOUT_SCLK_UFSUNIPRO20, "dout_sclk_ufsunipro20",
"mout_sclk_ufsunipro20",
DIV_TOP1_FSYS1, 16, 6),
DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
DIV_TOP1_FSYS0, 16, 10),
DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
DIV_TOP1_FSYS0, 28, 4),
DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
DIV_TOP1_FSYS11, 0, 10),
DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
DIV_TOP1_FSYS11, 12, 10),
DIV(DOUT_SCLK_PHY_FSYS1_26M, "dout_sclk_phy_fsys1_26m",
"mout_sclk_phy_fsys1_26m", DIV_TOP1_FSYS11, 24, 6),
};
static const struct samsung_gate_clock top1_gate_clks[] __initconst = {
GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0),
GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
GATE(CLK_SCLK_PHY_FSYS1, "sclk_phy_fsys1", "dout_sclk_phy_fsys1",
ENABLE_SCLK_TOP1_FSYS1, 0, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UFSUNIPRO20, "sclk_ufsunipro20", "dout_sclk_ufsunipro20",
ENABLE_SCLK_TOP1_FSYS1, 16, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0),
GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200",
ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT |
CLK_IS_CRITICAL, 0),
/*
* This clock is required for the CMU_FSYS1 registers access, keep it
* enabled permanently until proper runtime PM support is added.
*/
GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200",
ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT |
CLK_IS_CRITICAL, 0),
GATE(CLK_SCLK_PHY_FSYS1_26M, "sclk_phy_fsys1_26m",
"dout_sclk_phy_fsys1_26m", ENABLE_SCLK_TOP1_FSYS11,
24, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initconst = {
FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll_user",
1, 2, 0),
FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll_user",
1, 2, 0),
FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll_user", 1, 2, 0),
FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0),
};
static const struct samsung_cmu_info top1_cmu_info __initconst = {
.mux_clks = top1_mux_clks,
.nr_mux_clks = ARRAY_SIZE(top1_mux_clks),
.div_clks = top1_div_clks,
.nr_div_clks = ARRAY_SIZE(top1_div_clks),
.gate_clks = top1_gate_clks,
.nr_gate_clks = ARRAY_SIZE(top1_gate_clks),
.fixed_factor_clks = top1_fixed_factor_clks,
.nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks),
.nr_clk_ids = TOP1_NR_CLK,
.clk_regs = top1_clk_regs,
.nr_clk_regs = ARRAY_SIZE(top1_clk_regs),
};
static void __init exynos7_clk_top1_init(struct device_node *np)
{
samsung_cmu_register_one(np, &top1_cmu_info);
}
CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
exynos7_clk_top1_init);
/* Register Offset definitions for CMU_CCORE (0x105B0000) */
#define MUX_SEL_CCORE 0x0200
#define DIV_CCORE 0x0600
#define ENABLE_ACLK_CCORE0 0x0800
#define ENABLE_ACLK_CCORE1 0x0804
#define ENABLE_PCLK_CCORE 0x0900
/*
* List of parent clocks for Muxes in CMU_CCORE
*/
PNAME(mout_aclk_ccore_133_user_p) = { "fin_pll", "aclk_ccore_133" };
static const unsigned long ccore_clk_regs[] __initconst = {
MUX_SEL_CCORE,
ENABLE_PCLK_CCORE,
};
static const struct samsung_mux_clock ccore_mux_clks[] __initconst = {
MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p,
MUX_SEL_CCORE, 1, 1),
};
static const struct samsung_gate_clock ccore_gate_clks[] __initconst = {
GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
ENABLE_PCLK_CCORE, 8, 0, 0),
};
static const struct samsung_cmu_info ccore_cmu_info __initconst = {
.mux_clks = ccore_mux_clks,
.nr_mux_clks = ARRAY_SIZE(ccore_mux_clks),
.gate_clks = ccore_gate_clks,
.nr_gate_clks = ARRAY_SIZE(ccore_gate_clks),
.nr_clk_ids = CCORE_NR_CLK,
.clk_regs = ccore_clk_regs,
.nr_clk_regs = ARRAY_SIZE(ccore_clk_regs),
};
static void __init exynos7_clk_ccore_init(struct device_node *np)
{
samsung_cmu_register_one(np, &ccore_cmu_info);
}
CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
exynos7_clk_ccore_init);
/* Register Offset definitions for CMU_PERIC0 (0x13610000) */
#define MUX_SEL_PERIC0 0x0200
#define ENABLE_PCLK_PERIC0 0x0900
#define ENABLE_SCLK_PERIC0 0x0A00
/* List of parent clocks for Muxes in CMU_PERIC0 */
PNAME(mout_aclk_peric0_66_user_p) = { "fin_pll", "aclk_peric0_66" };
PNAME(mout_sclk_uart0_user_p) = { "fin_pll", "sclk_uart0" };
static const unsigned long peric0_clk_regs[] __initconst = {
MUX_SEL_PERIC0,
ENABLE_PCLK_PERIC0,
ENABLE_SCLK_PERIC0,
};
static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p,
MUX_SEL_PERIC0, 0, 1),
MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p,
MUX_SEL_PERIC0, 16, 1),
};
static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
ENABLE_PCLK_PERIC0, 8, 0, 0),
GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
ENABLE_PCLK_PERIC0, 9, 0, 0),
GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",
ENABLE_PCLK_PERIC0, 10, 0, 0),
GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",
ENABLE_PCLK_PERIC0, 11, 0, 0),
GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",
ENABLE_PCLK_PERIC0, 12, 0, 0),
GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",
ENABLE_PCLK_PERIC0, 13, 0, 0),
GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",
ENABLE_PCLK_PERIC0, 14, 0, 0),
GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
ENABLE_PCLK_PERIC0, 16, 0, 0),
GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user",
ENABLE_PCLK_PERIC0, 20, 0, 0),
GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
ENABLE_PCLK_PERIC0, 21, 0, 0),
GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
ENABLE_SCLK_PERIC0, 16, 0, 0),
GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
};
static const struct samsung_cmu_info peric0_cmu_info __initconst = {
.mux_clks = peric0_mux_clks,
.nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
.gate_clks = peric0_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
.nr_clk_ids = PERIC0_NR_CLK,
.clk_regs = peric0_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
};
static void __init exynos7_clk_peric0_init(struct device_node *np)
{
samsung_cmu_register_one(np, &peric0_cmu_info);
}
/* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
#define MUX_SEL_PERIC10 0x0200
#define MUX_SEL_PERIC11 0x0204
#define MUX_SEL_PERIC12 0x0208
#define ENABLE_PCLK_PERIC1 0x0900
#define ENABLE_SCLK_PERIC10 0x0A00
CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0",
exynos7_clk_peric0_init);
/* List of parent clocks for Muxes in CMU_PERIC1 */
PNAME(mout_aclk_peric1_66_user_p) = { "fin_pll", "aclk_peric1_66" };
PNAME(mout_sclk_uart1_user_p) = { "fin_pll", "sclk_uart1" };
PNAME(mout_sclk_uart2_user_p) = { "fin_pll", "sclk_uart2" };
PNAME(mout_sclk_uart3_user_p) = { "fin_pll", "sclk_uart3" };
PNAME(mout_sclk_spi0_user_p) = { "fin_pll", "sclk_spi0" };
PNAME(mout_sclk_spi1_user_p) = { "fin_pll", "sclk_spi1" };
PNAME(mout_sclk_spi2_user_p) = { "fin_pll", "sclk_spi2" };
PNAME(mout_sclk_spi3_user_p) = { "fin_pll", "sclk_spi3" };
PNAME(mout_sclk_spi4_user_p) = { "fin_pll", "sclk_spi4" };
static const unsigned long peric1_clk_regs[] __initconst = {
MUX_SEL_PERIC10,
MUX_SEL_PERIC11,
MUX_SEL_PERIC12,
ENABLE_PCLK_PERIC1,
ENABLE_SCLK_PERIC10,
};
static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p,
MUX_SEL_PERIC10, 0, 1),
MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_user_p,
MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_user_p,
MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_user_p,
MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_user_p,
MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_user_p,
MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_user_p,
MUX_SEL_PERIC11, 20, 1),
MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_user_p,
MUX_SEL_PERIC11, 24, 1),
MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_user_p,
MUX_SEL_PERIC11, 28, 1),
};
static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
ENABLE_PCLK_PERIC1, 4, 0, 0),
GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
ENABLE_PCLK_PERIC1, 5, 0, 0),
GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",
ENABLE_PCLK_PERIC1, 6, 0, 0),
GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",
ENABLE_PCLK_PERIC1, 7, 0, 0),
GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",
ENABLE_PCLK_PERIC1, 8, 0, 0),
GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
ENABLE_PCLK_PERIC1, 9, 0, 0),
GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
ENABLE_PCLK_PERIC1, 10, 0, 0),
GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
ENABLE_PCLK_PERIC1, 11, 0, 0),
GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user",
ENABLE_PCLK_PERIC1, 12, 0, 0),
GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user",
ENABLE_PCLK_PERIC1, 13, 0, 0),
GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user",
ENABLE_PCLK_PERIC1, 14, 0, 0),
GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user",
ENABLE_PCLK_PERIC1, 15, 0, 0),
GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user",
ENABLE_PCLK_PERIC1, 16, 0, 0),
GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user",
ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0),
GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user",
ENABLE_PCLK_PERIC1, 18, 0, 0),
GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user",
ENABLE_PCLK_PERIC1, 19, 0, 0),
GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
ENABLE_SCLK_PERIC10, 9, 0, 0),
GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user",
ENABLE_SCLK_PERIC10, 10, 0, 0),
GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
ENABLE_SCLK_PERIC10, 11, 0, 0),
GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user",
ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0),
GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user",
ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0),
GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user",
ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0),
GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user",
ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0),
GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user",
ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0),
GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1",
ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0),
GATE(SCLK_PCM1, "sclk_pcm1_user", "sclk_pcm1",
ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0),
GATE(SCLK_SPDIF, "sclk_spdif_user", "sclk_spdif",
ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_cmu_info peric1_cmu_info __initconst = {
.mux_clks = peric1_mux_clks,
.nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
.gate_clks = peric1_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
.nr_clk_ids = PERIC1_NR_CLK,
.clk_regs = peric1_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
};
static void __init exynos7_clk_peric1_init(struct device_node *np)
{
samsung_cmu_register_one(np, &peric1_cmu_info);
}
CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
exynos7_clk_peric1_init);
/* Register Offset definitions for CMU_PERIS (0x10040000) */
#define MUX_SEL_PERIS 0x0200
#define ENABLE_PCLK_PERIS 0x0900
#define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910
#define ENABLE_SCLK_PERIS 0x0A00
#define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10
/* List of parent clocks for Muxes in CMU_PERIS */
PNAME(mout_aclk_peris_66_user_p) = { "fin_pll", "aclk_peris_66" };
static const unsigned long peris_clk_regs[] __initconst = {
MUX_SEL_PERIS,
ENABLE_PCLK_PERIS,
ENABLE_PCLK_PERIS_SECURE_CHIPID,
ENABLE_SCLK_PERIS,
ENABLE_SCLK_PERIS_SECURE_CHIPID,
};
static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
MUX(0, "mout_aclk_peris_66_user",
mout_aclk_peris_66_user_p, MUX_SEL_PERIS, 0, 1),
};
static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
ENABLE_PCLK_PERIS, 6, 0, 0),
GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
ENABLE_PCLK_PERIS, 10, 0, 0),
GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user",
ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
};
static const struct samsung_cmu_info peris_cmu_info __initconst = {
.mux_clks = peris_mux_clks,
.nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
.gate_clks = peris_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
.nr_clk_ids = PERIS_NR_CLK,
.clk_regs = peris_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
};
static void __init exynos7_clk_peris_init(struct device_node *np)
{
samsung_cmu_register_one(np, &peris_cmu_info);
}
CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
exynos7_clk_peris_init);
/* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
#define MUX_SEL_FSYS00 0x0200
#define MUX_SEL_FSYS01 0x0204
#define MUX_SEL_FSYS02 0x0208
#define ENABLE_ACLK_FSYS00 0x0800
#define ENABLE_ACLK_FSYS01 0x0804
#define ENABLE_SCLK_FSYS01 0x0A04
#define ENABLE_SCLK_FSYS02 0x0A08
#define ENABLE_SCLK_FSYS04 0x0A10
/*
* List of parent clocks for Muxes in CMU_FSYS0
*/
PNAME(mout_aclk_fsys0_200_user_p) = { "fin_pll", "aclk_fsys0_200" };
PNAME(mout_sclk_mmc2_user_p) = { "fin_pll", "sclk_mmc2" };
PNAME(mout_sclk_usbdrd300_user_p) = { "fin_pll", "sclk_usbdrd300" };
PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_user_p) = { "fin_pll",
"phyclk_usbdrd300_udrd30_phyclock" };
PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p) = { "fin_pll",
"phyclk_usbdrd300_udrd30_pipe_pclk" };
/* fixed rate clocks used in the FSYS0 block */
static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initconst = {
FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 0, 60000000),
FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 0, 125000000),
};
static const unsigned long fsys0_clk_regs[] __initconst = {
MUX_SEL_FSYS00,
MUX_SEL_FSYS01,
MUX_SEL_FSYS02,
ENABLE_ACLK_FSYS00,
ENABLE_ACLK_FSYS01,
ENABLE_SCLK_FSYS01,
ENABLE_SCLK_FSYS02,
ENABLE_SCLK_FSYS04,
};
static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p,
MUX_SEL_FSYS00, 24, 1),
MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_user_p,
MUX_SEL_FSYS01, 24, 1),
MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_user_p,
MUX_SEL_FSYS01, 28, 1),
MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p,
MUX_SEL_FSYS02, 24, 1),
MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user",
mout_phyclk_usbdrd300_udrd30_phyclk_user_p,
MUX_SEL_FSYS02, 28, 1),
};
static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user",
ENABLE_ACLK_FSYS00, 3, 0, 0),
GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user",
ENABLE_ACLK_FSYS00, 4, 0, 0),
GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",
"mout_aclk_fsys0_200_user",
ENABLE_ACLK_FSYS00, 19, 0, 0),
GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",
ENABLE_ACLK_FSYS01, 29, 0, 0),
GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
ENABLE_ACLK_FSYS01, 31, 0, 0),
GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk",
"mout_sclk_usbdrd300_user",
ENABLE_SCLK_FSYS01, 4, 0, 0),
GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll",
ENABLE_SCLK_FSYS01, 8, 0, 0),
GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER,
"phyclk_usbdrd300_udrd30_pipe_pclk_user",
"mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
ENABLE_SCLK_FSYS02, 24, 0, 0),
GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER,
"phyclk_usbdrd300_udrd30_phyclk_user",
"mout_phyclk_usbdrd300_udrd30_phyclk_user",
ENABLE_SCLK_FSYS02, 28, 0, 0),
GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy",
"fin_pll",
ENABLE_SCLK_FSYS04, 28, 0, 0),
};
static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
.fixed_clks = fixed_rate_clks_fsys0,
.nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys0),
.mux_clks = fsys0_mux_clks,
.nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
.gate_clks = fsys0_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
.nr_clk_ids = FSYS0_NR_CLK,
.clk_regs = fsys0_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
};
static void __init exynos7_clk_fsys0_init(struct device_node *np)
{
samsung_cmu_register_one(np, &fsys0_cmu_info);
}
CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
exynos7_clk_fsys0_init);
/* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
#define MUX_SEL_FSYS10 0x0200
#define MUX_SEL_FSYS11 0x0204
#define MUX_SEL_FSYS12 0x0208
#define DIV_FSYS1 0x0600
#define ENABLE_ACLK_FSYS1 0x0800
#define ENABLE_PCLK_FSYS1 0x0900
#define ENABLE_SCLK_FSYS11 0x0A04
#define ENABLE_SCLK_FSYS12 0x0A08
#define ENABLE_SCLK_FSYS13 0x0A0C
/*
* List of parent clocks for Muxes in CMU_FSYS1
*/
PNAME(mout_aclk_fsys1_200_user_p) = { "fin_pll", "aclk_fsys1_200" };
PNAME(mout_fsys1_group_p) = { "fin_pll", "fin_pll_26m",
"sclk_phy_fsys1_26m" };
PNAME(mout_sclk_mmc0_user_p) = { "fin_pll", "sclk_mmc0" };
PNAME(mout_sclk_mmc1_user_p) = { "fin_pll", "sclk_mmc1" };
PNAME(mout_sclk_ufsunipro20_user_p) = { "fin_pll", "sclk_ufsunipro20" };
PNAME(mout_phyclk_ufs20_tx0_user_p) = { "fin_pll", "phyclk_ufs20_tx0_symbol" };
PNAME(mout_phyclk_ufs20_rx0_user_p) = { "fin_pll", "phyclk_ufs20_rx0_symbol" };
PNAME(mout_phyclk_ufs20_rx1_user_p) = { "fin_pll", "phyclk_ufs20_rx1_symbol" };
/* fixed rate clocks used in the FSYS1 block */
static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initconst = {
FRATE(PHYCLK_UFS20_TX0_SYMBOL, "phyclk_ufs20_tx0_symbol", NULL,
0, 300000000),
FRATE(PHYCLK_UFS20_RX0_SYMBOL, "phyclk_ufs20_rx0_symbol", NULL,
0, 300000000),
FRATE(PHYCLK_UFS20_RX1_SYMBOL, "phyclk_ufs20_rx1_symbol", NULL,
0, 300000000),
};
static const unsigned long fsys1_clk_regs[] __initconst = {
MUX_SEL_FSYS10,
MUX_SEL_FSYS11,
MUX_SEL_FSYS12,
DIV_FSYS1,
ENABLE_ACLK_FSYS1,
ENABLE_PCLK_FSYS1,
ENABLE_SCLK_FSYS11,
ENABLE_SCLK_FSYS12,
ENABLE_SCLK_FSYS13,
};
static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
MUX(MOUT_FSYS1_PHYCLK_SEL1, "mout_fsys1_phyclk_sel1",
mout_fsys1_group_p, MUX_SEL_FSYS10, 16, 2),
MUX(0, "mout_fsys1_phyclk_sel0", mout_fsys1_group_p,
MUX_SEL_FSYS10, 20, 2),
MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_user_p,
MUX_SEL_FSYS10, 28, 1),
MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_user_p,
MUX_SEL_FSYS11, 24, 1),
MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_user_p,
MUX_SEL_FSYS11, 28, 1),
MUX(0, "mout_sclk_ufsunipro20_user", mout_sclk_ufsunipro20_user_p,
MUX_SEL_FSYS11, 20, 1),
MUX(0, "mout_phyclk_ufs20_rx1_symbol_user",
mout_phyclk_ufs20_rx1_user_p, MUX_SEL_FSYS12, 16, 1),
MUX(0, "mout_phyclk_ufs20_rx0_symbol_user",
mout_phyclk_ufs20_rx0_user_p, MUX_SEL_FSYS12, 24, 1),
MUX(0, "mout_phyclk_ufs20_tx0_symbol_user",
mout_phyclk_ufs20_tx0_user_p, MUX_SEL_FSYS12, 28, 1),
};
static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
DIV(DOUT_PCLK_FSYS1, "dout_pclk_fsys1", "mout_aclk_fsys1_200_user",
DIV_FSYS1, 0, 2),
};
static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
GATE(SCLK_UFSUNIPRO20_USER, "sclk_ufsunipro20_user",
"mout_sclk_ufsunipro20_user",
ENABLE_SCLK_FSYS11, 20, 0, 0),
GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
ENABLE_ACLK_FSYS1, 29, 0, 0),
GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
ENABLE_ACLK_FSYS1, 30, 0, 0),
GATE(ACLK_UFS20_LINK, "aclk_ufs20_link", "dout_pclk_fsys1",
ENABLE_ACLK_FSYS1, 31, 0, 0),
GATE(PCLK_GPIO_FSYS1, "pclk_gpio_fsys1", "mout_aclk_fsys1_200_user",
ENABLE_PCLK_FSYS1, 30, 0, 0),
GATE(PHYCLK_UFS20_RX1_SYMBOL_USER, "phyclk_ufs20_rx1_symbol_user",
"mout_phyclk_ufs20_rx1_symbol_user",
ENABLE_SCLK_FSYS12, 16, 0, 0),
GATE(PHYCLK_UFS20_RX0_SYMBOL_USER, "phyclk_ufs20_rx0_symbol_user",
"mout_phyclk_ufs20_rx0_symbol_user",
ENABLE_SCLK_FSYS12, 24, 0, 0),
GATE(PHYCLK_UFS20_TX0_SYMBOL_USER, "phyclk_ufs20_tx0_symbol_user",
"mout_phyclk_ufs20_tx0_symbol_user",
ENABLE_SCLK_FSYS12, 28, 0, 0),
GATE(OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY,
"oscclk_phy_clkout_embedded_combo_phy",
"fin_pll",
ENABLE_SCLK_FSYS12, 4, CLK_IGNORE_UNUSED, 0),
GATE(SCLK_COMBO_PHY_EMBEDDED_26M, "sclk_combo_phy_embedded_26m",
"mout_fsys1_phyclk_sel1",
ENABLE_SCLK_FSYS13, 24, CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
.fixed_clks = fixed_rate_clks_fsys1,
.nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys1),
.mux_clks = fsys1_mux_clks,
.nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
.div_clks = fsys1_div_clks,
.nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
.gate_clks = fsys1_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
.nr_clk_ids = FSYS1_NR_CLK,
.clk_regs = fsys1_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
};
static void __init exynos7_clk_fsys1_init(struct device_node *np)
{
samsung_cmu_register_one(np, &fsys1_cmu_info);
}
CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
exynos7_clk_fsys1_init);
#define MUX_SEL_MSCL 0x0200
#define DIV_MSCL 0x0600
#define ENABLE_ACLK_MSCL 0x0800
#define ENABLE_PCLK_MSCL 0x0900
/* List of parent clocks for Muxes in CMU_MSCL */
PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" };
static const unsigned long mscl_clk_regs[] __initconst = {
MUX_SEL_MSCL,
DIV_MSCL,
ENABLE_ACLK_MSCL,
ENABLE_PCLK_MSCL,
};
static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {
MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532",
mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1),
};
static const struct samsung_div_clock mscl_div_clks[] __initconst = {
DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532",
DIV_MSCL, 0, 3),
};
static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {
GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532",
ENABLE_ACLK_MSCL, 31, 0, 0),
GATE(ACLK_MSCL_1, "aclk_mscl_1", "usermux_aclk_mscl_532",
ENABLE_ACLK_MSCL, 30, 0, 0),
GATE(ACLK_JPEG, "aclk_jpeg", "usermux_aclk_mscl_532",
ENABLE_ACLK_MSCL, 29, 0, 0),
GATE(ACLK_G2D, "aclk_g2d", "usermux_aclk_mscl_532",
ENABLE_ACLK_MSCL, 28, 0, 0),
GATE(ACLK_LH_ASYNC_SI_MSCL_0, "aclk_lh_async_si_mscl_0",
"usermux_aclk_mscl_532",
ENABLE_ACLK_MSCL, 27, 0, 0),
GATE(ACLK_LH_ASYNC_SI_MSCL_1, "aclk_lh_async_si_mscl_1",
"usermux_aclk_mscl_532",
ENABLE_ACLK_MSCL, 26, 0, 0),
GATE(ACLK_XIU_MSCLX_0, "aclk_xiu_msclx_0", "usermux_aclk_mscl_532",
ENABLE_ACLK_MSCL, 25, 0, 0),
GATE(ACLK_XIU_MSCLX_1, "aclk_xiu_msclx_1", "usermux_aclk_mscl_532",
ENABLE_ACLK_MSCL, 24, 0, 0),
GATE(ACLK_AXI2ACEL_BRIDGE, "aclk_axi2acel_bridge",
"usermux_aclk_mscl_532",
ENABLE_ACLK_MSCL, 23, 0, 0),
GATE(ACLK_QE_MSCL_0, "aclk_qe_mscl_0", "usermux_aclk_mscl_532",
ENABLE_ACLK_MSCL, 22, 0, 0),
GATE(ACLK_QE_MSCL_1, "aclk_qe_mscl_1", "usermux_aclk_mscl_532",
ENABLE_ACLK_MSCL, 21, 0, 0),
GATE(ACLK_QE_JPEG, "aclk_qe_jpeg", "usermux_aclk_mscl_532",
ENABLE_ACLK_MSCL, 20, 0, 0),
GATE(ACLK_QE_G2D, "aclk_qe_g2d", "usermux_aclk_mscl_532",
ENABLE_ACLK_MSCL, 19, 0, 0),
GATE(ACLK_PPMU_MSCL_0, "aclk_ppmu_mscl_0", "usermux_aclk_mscl_532",
ENABLE_ACLK_MSCL, 18, 0, 0),
GATE(ACLK_PPMU_MSCL_1, "aclk_ppmu_mscl_1", "usermux_aclk_mscl_532",
ENABLE_ACLK_MSCL, 17, 0, 0),
GATE(ACLK_MSCLNP_133, "aclk_msclnp_133", "usermux_aclk_mscl_532",
ENABLE_ACLK_MSCL, 16, 0, 0),
GATE(ACLK_AHB2APB_MSCL0P, "aclk_ahb2apb_mscl0p",
"usermux_aclk_mscl_532",
ENABLE_ACLK_MSCL, 15, 0, 0),
GATE(ACLK_AHB2APB_MSCL1P, "aclk_ahb2apb_mscl1p",
"usermux_aclk_mscl_532",
ENABLE_ACLK_MSCL, 14, 0, 0),
GATE(PCLK_MSCL_0, "pclk_mscl_0", "dout_pclk_mscl",
ENABLE_PCLK_MSCL, 31, 0, 0),
GATE(PCLK_MSCL_1, "pclk_mscl_1", "dout_pclk_mscl",
ENABLE_PCLK_MSCL, 30, 0, 0),
GATE(PCLK_JPEG, "pclk_jpeg", "dout_pclk_mscl",
ENABLE_PCLK_MSCL, 29, 0, 0),
GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl",
ENABLE_PCLK_MSCL, 28, 0, 0),
GATE(PCLK_QE_MSCL_0, "pclk_qe_mscl_0", "dout_pclk_mscl",
ENABLE_PCLK_MSCL, 27, 0, 0),
GATE(PCLK_QE_MSCL_1, "pclk_qe_mscl_1", "dout_pclk_mscl",
ENABLE_PCLK_MSCL, 26, 0, 0),
GATE(PCLK_QE_JPEG, "pclk_qe_jpeg", "dout_pclk_mscl",
ENABLE_PCLK_MSCL, 25, 0, 0),
GATE(PCLK_QE_G2D, "pclk_qe_g2d", "dout_pclk_mscl",
ENABLE_PCLK_MSCL, 24, 0, 0),
GATE(PCLK_PPMU_MSCL_0, "pclk_ppmu_mscl_0", "dout_pclk_mscl",
ENABLE_PCLK_MSCL, 23, 0, 0),
GATE(PCLK_PPMU_MSCL_1, "pclk_ppmu_mscl_1", "dout_pclk_mscl",
ENABLE_PCLK_MSCL, 22, 0, 0),
GATE(PCLK_AXI2ACEL_BRIDGE, "pclk_axi2acel_bridge", "dout_pclk_mscl",
ENABLE_PCLK_MSCL, 21, 0, 0),
GATE(PCLK_PMU_MSCL, "pclk_pmu_mscl", "dout_pclk_mscl",
ENABLE_PCLK_MSCL, 20, 0, 0),
};
static const struct samsung_cmu_info mscl_cmu_info __initconst = {
.mux_clks = mscl_mux_clks,
.nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
.div_clks = mscl_div_clks,
.nr_div_clks = ARRAY_SIZE(mscl_div_clks),
.gate_clks = mscl_gate_clks,
.nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
.nr_clk_ids = MSCL_NR_CLK,
.clk_regs = mscl_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
};
static void __init exynos7_clk_mscl_init(struct device_node *np)
{
samsung_cmu_register_one(np, &mscl_cmu_info);
}
CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl",
exynos7_clk_mscl_init);
/* Register Offset definitions for CMU_AUD (0x114C0000) */
#define MUX_SEL_AUD 0x0200
#define DIV_AUD0 0x0600
#define DIV_AUD1 0x0604
#define ENABLE_ACLK_AUD 0x0800
#define ENABLE_PCLK_AUD 0x0900
#define ENABLE_SCLK_AUD 0x0A00
/*
* List of parent clocks for Muxes in CMU_AUD
*/
PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" };
PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" };
static const unsigned long aud_clk_regs[] __initconst = {
MUX_SEL_AUD,
DIV_AUD0,
DIV_AUD1,
ENABLE_ACLK_AUD,
ENABLE_PCLK_AUD,
ENABLE_SCLK_AUD,
};
static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1),
MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1),
MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1),
};
static const struct samsung_div_clock aud_div_clks[] __initconst = {
DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4),
DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4),
DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4),
DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4),
DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8),
DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4),
DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5),
DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4),
};
static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm",
ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s",
ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0),
GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0),
GATE(0, "sclk_slimbus", "dout_sclk_slimbus",
ENABLE_SCLK_AUD, 30, 0, 0),
GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0),
GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0),
GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0),
GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0),
GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0),
GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0),
GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud",
ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0),
GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud",
ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0),
GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0),
GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0),
GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud",
ENABLE_ACLK_AUD, 28, 0, 0),
GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0),
};
static const struct samsung_cmu_info aud_cmu_info __initconst = {
.mux_clks = aud_mux_clks,
.nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
.div_clks = aud_div_clks,
.nr_div_clks = ARRAY_SIZE(aud_div_clks),
.gate_clks = aud_gate_clks,
.nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
.nr_clk_ids = AUD_NR_CLK,
.clk_regs = aud_clk_regs,
.nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
};
static void __init exynos7_clk_aud_init(struct device_node *np)
{
samsung_cmu_register_one(np, &aud_cmu_info);
}
CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud",
exynos7_clk_aud_init);
| linux-master | drivers/clk/samsung/clk-exynos7.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Tarek Dakhran <[email protected]>
*
* Common Clock Framework support for Exynos5410 SoC.
*/
#include <dt-bindings/clock/exynos5410.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk.h>
#include "clk.h"
#define APLL_LOCK 0x0
#define APLL_CON0 0x100
#define CPLL_LOCK 0x10020
#define CPLL_CON0 0x10120
#define EPLL_LOCK 0x10040
#define EPLL_CON0 0x10130
#define MPLL_LOCK 0x4000
#define MPLL_CON0 0x4100
#define BPLL_LOCK 0x20010
#define BPLL_CON0 0x20110
#define KPLL_LOCK 0x28000
#define KPLL_CON0 0x28100
#define SRC_CPU 0x200
#define DIV_CPU0 0x500
#define SRC_CPERI1 0x4204
#define GATE_IP_G2D 0x8800
#define DIV_TOP0 0x10510
#define DIV_TOP1 0x10514
#define DIV_FSYS0 0x10548
#define DIV_FSYS1 0x1054c
#define DIV_FSYS2 0x10550
#define DIV_PERIC0 0x10558
#define DIV_PERIC3 0x10564
#define SRC_TOP0 0x10210
#define SRC_TOP1 0x10214
#define SRC_TOP2 0x10218
#define SRC_FSYS 0x10244
#define SRC_PERIC0 0x10250
#define SRC_MASK_FSYS 0x10340
#define SRC_MASK_PERIC0 0x10350
#define GATE_BUS_FSYS0 0x10740
#define GATE_TOP_SCLK_FSYS 0x10840
#define GATE_TOP_SCLK_PERIC 0x10850
#define GATE_IP_FSYS 0x10944
#define GATE_IP_PERIC 0x10950
#define GATE_IP_PERIS 0x10960
#define SRC_CDREX 0x20200
#define SRC_KFC 0x28200
#define DIV_KFC0 0x28500
/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR 512
/* list of PLLs */
enum exynos5410_plls {
apll, cpll, epll, mpll,
bpll, kpll,
nr_plls /* number of PLLs */
};
/* list of all parent clocks */
PNAME(apll_p) = { "fin_pll", "fout_apll", };
PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
PNAME(cpll_p) = { "fin_pll", "fout_cpll" };
PNAME(epll_p) = { "fin_pll", "fout_epll" };
PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", };
PNAME(mout_kfc_p) = { "mout_kpll", "sclk_mpll", };
PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", };
PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", };
PNAME(mpll_bpll_p) = { "sclk_mpll_muxed", "sclk_bpll_muxed", };
PNAME(sclk_mpll_bpll_p) = { "sclk_mpll_bpll", "fin_pll", };
PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none",
"none", "none", "sclk_mpll_bpll",
"none", "none", "sclk_cpll" };
static const struct samsung_mux_clock exynos5410_mux_clks[] __initconst = {
MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
MUX(0, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1),
MUX(0, "sclk_mpll_muxed", mpll_user_p, SRC_TOP2, 20, 1),
MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
MUX(0, "sclk_bpll_muxed", bpll_user_p, SRC_TOP2, 24, 1),
MUX(0, "sclk_epll", epll_p, SRC_TOP2, 12, 1),
MUX(0, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1),
MUX(0, "sclk_mpll_bpll", mpll_bpll_p, SRC_TOP1, 20, 1),
MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4),
MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4),
MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4),
MUX(0, "mout_usbd300", sclk_mpll_bpll_p, SRC_FSYS, 28, 1),
MUX(0, "mout_usbd301", sclk_mpll_bpll_p, SRC_FSYS, 29, 1),
MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4),
MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4),
MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4),
MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 12, 4),
MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 4),
MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1),
MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1),
};
static const struct samsung_div_clock exynos5410_div_clks[] __initconst = {
DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
DIV(0, "div_acp", "div_arm2", DIV_CPU0, 8, 3),
DIV(0, "div_cpud", "div_arm2", DIV_CPU0, 4, 3),
DIV(0, "div_atb", "div_arm2", DIV_CPU0, 16, 3),
DIV(0, "pclk_dbg", "div_arm2", DIV_CPU0, 20, 3),
DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
DIV(0, "div_aclk", "div_kfc", DIV_KFC0, 4, 3),
DIV(0, "div_pclk", "div_kfc", DIV_KFC0, 20, 3),
DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3),
DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 20, 4),
DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 28, 4),
DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
DIV_F(0, "div_mmc_pre0", "div_mmc0",
DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
DIV_F(0, "div_mmc_pre1", "div_mmc1",
DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
DIV_F(0, "div_mmc_pre2", "div_mmc2",
DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
DIV(0, "aclk266", "mpll_user_p", DIV_TOP0, 16, 3),
DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
};
static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = {
GATE(CLK_SSS, "sss", "aclk266", GATE_IP_G2D, 2, 0, 0),
GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
GATE(CLK_WDT, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
GATE(CLK_RTC, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
GATE(CLK_TMU, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0),
GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
GATE(CLK_PDMA1, "pdma1", "aclk200", GATE_BUS_FSYS0, 2, 0, 0),
GATE(CLK_PDMA0, "pdma0", "aclk200", GATE_BUS_FSYS0, 1, 0, 0),
GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
GATE(CLK_UART3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
GATE(CLK_I2C0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0),
GATE(CLK_I2C1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0),
GATE(CLK_I2C2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0),
GATE(CLK_I2C3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0),
GATE(CLK_USI0, "usi0", "aclk66", GATE_IP_PERIC, 10, 0, 0),
GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0),
GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0),
GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0),
GATE(CLK_TSADC, "tsadc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
};
static const struct samsung_pll_rate_table exynos5410_pll2550x_24mhz_tbl[] __initconst = {
PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
PLL_36XX_RATE(24 * MHZ, 333000000U, 111, 2, 2, 0),
PLL_36XX_RATE(24 * MHZ, 300000000U, 100, 2, 2, 0),
PLL_36XX_RATE(24 * MHZ, 266000000U, 266, 3, 3, 0),
PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
PLL_36XX_RATE(24 * MHZ, 192000000U, 192, 3, 3, 0),
PLL_36XX_RATE(24 * MHZ, 166000000U, 166, 3, 3, 0),
PLL_36XX_RATE(24 * MHZ, 133000000U, 266, 3, 4, 0),
PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
PLL_36XX_RATE(24 * MHZ, 66000000U, 176, 2, 5, 0),
};
static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
APLL_CON0, NULL),
[cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
CPLL_CON0, NULL),
[epll] = PLL(pll_2650x, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
EPLL_CON0, NULL),
[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
MPLL_CON0, NULL),
[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
BPLL_CON0, NULL),
[kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
KPLL_CON0, NULL),
};
static const struct samsung_cmu_info cmu __initconst = {
.pll_clks = exynos5410_plls,
.nr_pll_clks = ARRAY_SIZE(exynos5410_plls),
.mux_clks = exynos5410_mux_clks,
.nr_mux_clks = ARRAY_SIZE(exynos5410_mux_clks),
.div_clks = exynos5410_div_clks,
.nr_div_clks = ARRAY_SIZE(exynos5410_div_clks),
.gate_clks = exynos5410_gate_clks,
.nr_gate_clks = ARRAY_SIZE(exynos5410_gate_clks),
.nr_clk_ids = CLKS_NR,
};
/* register exynos5410 clocks */
static void __init exynos5410_clk_init(struct device_node *np)
{
struct clk *xxti = of_clk_get(np, 0);
if (!IS_ERR(xxti) && clk_get_rate(xxti) == 24 * MHZ)
exynos5410_plls[epll].rate_table = exynos5410_pll2550x_24mhz_tbl;
samsung_cmu_register_one(np, &cmu);
pr_debug("Exynos5410: clock setup completed.\n");
}
CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
| linux-master | drivers/clk/samsung/clk-exynos5410.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2021 Linaro Ltd.
* Copyright (C) 2021 Dávid Virág <[email protected]>
* Author: Sam Protsenko <[email protected]>
* Author: Dávid Virág <[email protected]>
*
* This file contains shared functions used by some arm64 Exynos SoCs,
* such as Exynos7885 or Exynos850 to register and init CMUs.
*/
#include <linux/clk.h>
#include <linux/of_address.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include "clk-exynos-arm64.h"
/* Gate register bits */
#define GATE_MANUAL BIT(20)
#define GATE_ENABLE_HWACG BIT(28)
/* Gate register offsets range */
#define GATE_OFF_START 0x2000
#define GATE_OFF_END 0x2fff
struct exynos_arm64_cmu_data {
struct samsung_clk_reg_dump *clk_save;
unsigned int nr_clk_save;
const struct samsung_clk_reg_dump *clk_suspend;
unsigned int nr_clk_suspend;
struct clk *clk;
struct clk **pclks;
int nr_pclks;
struct samsung_clk_provider *ctx;
};
/**
* exynos_arm64_init_clocks - Set clocks initial configuration
* @np: CMU device tree node with "reg" property (CMU addr)
* @reg_offs: Register offsets array for clocks to init
* @reg_offs_len: Number of register offsets in reg_offs array
*
* Set manual control mode for all gate clocks.
*/
static void __init exynos_arm64_init_clocks(struct device_node *np,
const unsigned long *reg_offs, size_t reg_offs_len)
{
void __iomem *reg_base;
size_t i;
reg_base = of_iomap(np, 0);
if (!reg_base)
panic("%s: failed to map registers\n", __func__);
for (i = 0; i < reg_offs_len; ++i) {
void __iomem *reg = reg_base + reg_offs[i];
u32 val;
/* Modify only gate clock registers */
if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)
continue;
val = readl(reg);
val |= GATE_MANUAL;
val &= ~GATE_ENABLE_HWACG;
writel(val, reg);
}
iounmap(reg_base);
}
/**
* exynos_arm64_enable_bus_clk - Enable parent clock of specified CMU
*
* @dev: Device object; may be NULL if this function is not being
* called from platform driver probe function
* @np: CMU device tree node
* @cmu: CMU data
*
* Keep CMU parent clock running (needed for CMU registers access).
*
* Return: 0 on success or a negative error code on failure.
*/
static int __init exynos_arm64_enable_bus_clk(struct device *dev,
struct device_node *np, const struct samsung_cmu_info *cmu)
{
struct clk *parent_clk;
if (!cmu->clk_name)
return 0;
if (dev) {
struct exynos_arm64_cmu_data *data;
parent_clk = clk_get(dev, cmu->clk_name);
data = dev_get_drvdata(dev);
if (data)
data->clk = parent_clk;
} else {
parent_clk = of_clk_get_by_name(np, cmu->clk_name);
}
if (IS_ERR(parent_clk))
return PTR_ERR(parent_clk);
return clk_prepare_enable(parent_clk);
}
static int __init exynos_arm64_cmu_prepare_pm(struct device *dev,
const struct samsung_cmu_info *cmu)
{
struct exynos_arm64_cmu_data *data = dev_get_drvdata(dev);
int i;
data->clk_save = samsung_clk_alloc_reg_dump(cmu->clk_regs,
cmu->nr_clk_regs);
if (!data->clk_save)
return -ENOMEM;
data->nr_clk_save = cmu->nr_clk_regs;
data->clk_suspend = cmu->suspend_regs;
data->nr_clk_suspend = cmu->nr_suspend_regs;
data->nr_pclks = of_clk_get_parent_count(dev->of_node);
if (!data->nr_pclks)
return 0;
data->pclks = devm_kcalloc(dev, sizeof(struct clk *), data->nr_pclks,
GFP_KERNEL);
if (!data->pclks) {
kfree(data->clk_save);
return -ENOMEM;
}
for (i = 0; i < data->nr_pclks; i++) {
struct clk *clk = of_clk_get(dev->of_node, i);
if (IS_ERR(clk)) {
kfree(data->clk_save);
while (--i >= 0)
clk_put(data->pclks[i]);
return PTR_ERR(clk);
}
data->pclks[i] = clk;
}
return 0;
}
/**
* exynos_arm64_register_cmu - Register specified Exynos CMU domain
* @dev: Device object; may be NULL if this function is not being
* called from platform driver probe function
* @np: CMU device tree node
* @cmu: CMU data
*
* Register specified CMU domain, which includes next steps:
*
* 1. Enable parent clock of @cmu CMU
* 2. Set initial registers configuration for @cmu CMU clocks
* 3. Register @cmu CMU clocks using Samsung clock framework API
*/
void __init exynos_arm64_register_cmu(struct device *dev,
struct device_node *np, const struct samsung_cmu_info *cmu)
{
int err;
/*
* Try to boot even if the parent clock enablement fails, as it might be
* already enabled by bootloader.
*/
err = exynos_arm64_enable_bus_clk(dev, np, cmu);
if (err)
pr_err("%s: could not enable bus clock %s; err = %d\n",
__func__, cmu->clk_name, err);
exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
samsung_cmu_register_one(np, cmu);
}
/**
* exynos_arm64_register_cmu_pm - Register Exynos CMU domain with PM support
*
* @pdev: Platform device object
* @set_manual: If true, set gate clocks to manual mode
*
* It's a version of exynos_arm64_register_cmu() with PM support. Should be
* called from probe function of platform driver.
*
* Return: 0 on success, or negative error code on error.
*/
int __init exynos_arm64_register_cmu_pm(struct platform_device *pdev,
bool set_manual)
{
const struct samsung_cmu_info *cmu;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct exynos_arm64_cmu_data *data;
void __iomem *reg_base;
int ret;
cmu = of_device_get_match_data(dev);
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
platform_set_drvdata(pdev, data);
ret = exynos_arm64_cmu_prepare_pm(dev, cmu);
if (ret)
return ret;
/*
* Try to boot even if the parent clock enablement fails, as it might be
* already enabled by bootloader.
*/
ret = exynos_arm64_enable_bus_clk(dev, NULL, cmu);
if (ret)
dev_err(dev, "%s: could not enable bus clock %s; err = %d\n",
__func__, cmu->clk_name, ret);
if (set_manual)
exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg_base))
return PTR_ERR(reg_base);
data->ctx = samsung_clk_init(dev, reg_base, cmu->nr_clk_ids);
/*
* Enable runtime PM here to allow the clock core using runtime PM
* for the registered clocks. Additionally, we increase the runtime
* PM usage count before registering the clocks, to prevent the
* clock core from runtime suspending the device.
*/
pm_runtime_get_noresume(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
samsung_cmu_register_clocks(data->ctx, cmu);
samsung_clk_of_add_provider(dev->of_node, data->ctx);
pm_runtime_put_sync(dev);
return 0;
}
int exynos_arm64_cmu_suspend(struct device *dev)
{
struct exynos_arm64_cmu_data *data = dev_get_drvdata(dev);
int i;
samsung_clk_save(data->ctx->reg_base, data->clk_save,
data->nr_clk_save);
for (i = 0; i < data->nr_pclks; i++)
clk_prepare_enable(data->pclks[i]);
/* For suspend some registers have to be set to certain values */
samsung_clk_restore(data->ctx->reg_base, data->clk_suspend,
data->nr_clk_suspend);
for (i = 0; i < data->nr_pclks; i++)
clk_disable_unprepare(data->pclks[i]);
clk_disable_unprepare(data->clk);
return 0;
}
int exynos_arm64_cmu_resume(struct device *dev)
{
struct exynos_arm64_cmu_data *data = dev_get_drvdata(dev);
int i;
clk_prepare_enable(data->clk);
for (i = 0; i < data->nr_pclks; i++)
clk_prepare_enable(data->pclks[i]);
samsung_clk_restore(data->ctx->reg_base, data->clk_save,
data->nr_clk_save);
for (i = 0; i < data->nr_pclks; i++)
clk_disable_unprepare(data->pclks[i]);
return 0;
}
| linux-master | drivers/clk/samsung/clk-exynos-arm64.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2021 Linaro Ltd.
* Author: Sam Protsenko <[email protected]>
*
* Common Clock Framework support for Exynos850 SoC.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/exynos850.h>
#include "clk.h"
#include "clk-exynos-arm64.h"
/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR_TOP (CLK_DOUT_G3D_SWITCH + 1)
#define CLKS_NR_APM (CLK_GOUT_SYSREG_APM_PCLK + 1)
#define CLKS_NR_AUD (CLK_GOUT_AUD_CMU_AUD_PCLK + 1)
#define CLKS_NR_CMGP (CLK_GOUT_SYSREG_CMGP_PCLK + 1)
#define CLKS_NR_G3D (CLK_GOUT_G3D_SYSREG_PCLK + 1)
#define CLKS_NR_HSI (CLK_GOUT_HSI_CMU_HSI_PCLK + 1)
#define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1)
#define CLKS_NR_MFCMSCL (CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1)
#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1)
#define CLKS_NR_CORE (CLK_GOUT_SYSREG_CORE_PCLK + 1)
#define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_PCLK + 1)
/* ---- CMU_TOP ------------------------------------------------------------- */
/* Register Offset definitions for CMU_TOP (0x120e0000) */
#define PLL_LOCKTIME_PLL_MMC 0x0000
#define PLL_LOCKTIME_PLL_SHARED0 0x0004
#define PLL_LOCKTIME_PLL_SHARED1 0x0008
#define PLL_CON0_PLL_MMC 0x0100
#define PLL_CON3_PLL_MMC 0x010c
#define PLL_CON0_PLL_SHARED0 0x0140
#define PLL_CON3_PLL_SHARED0 0x014c
#define PLL_CON0_PLL_SHARED1 0x0180
#define PLL_CON3_PLL_SHARED1 0x018c
#define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000
#define CLK_CON_MUX_MUX_CLKCMU_AUD 0x1004
#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
#define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
#define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020
#define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034
#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038
#define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
#define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040
#define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044
#define CLK_CON_MUX_MUX_CLKCMU_IS_BUS 0x1048
#define CLK_CON_MUX_MUX_CLKCMU_IS_GDC 0x104c
#define CLK_CON_MUX_MUX_CLKCMU_IS_ITP 0x1050
#define CLK_CON_MUX_MUX_CLKCMU_IS_VRA 0x1054
#define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG 0x1058
#define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M 0x105c
#define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC 0x1060
#define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC 0x1064
#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070
#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
#define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c
#define CLK_CON_DIV_CLKCMU_AUD 0x1810
#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820
#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
#define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
#define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c
#define CLK_CON_DIV_CLKCMU_DPU 0x1840
#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844
#define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
#define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c
#define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850
#define CLK_CON_DIV_CLKCMU_IS_BUS 0x1854
#define CLK_CON_DIV_CLKCMU_IS_GDC 0x1858
#define CLK_CON_DIV_CLKCMU_IS_ITP 0x185c
#define CLK_CON_DIV_CLKCMU_IS_VRA 0x1860
#define CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG 0x1864
#define CLK_CON_DIV_CLKCMU_MFCMSCL_M2M 0x1868
#define CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC 0x186c
#define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC 0x1870
#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c
#define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880
#define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884
#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c
#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890
#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894
#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898
#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c
#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0
#define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008
#define CLK_CON_GAT_GATE_CLKCMU_AUD 0x200c
#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
#define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
#define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028
#define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c
#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040
#define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
#define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048
#define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c
#define CLK_CON_GAT_GATE_CLKCMU_IS_BUS 0x2050
#define CLK_CON_GAT_GATE_CLKCMU_IS_GDC 0x2054
#define CLK_CON_GAT_GATE_CLKCMU_IS_ITP 0x2058
#define CLK_CON_GAT_GATE_CLKCMU_IS_VRA 0x205c
#define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG 0x2060
#define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M 0x2064
#define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC 0x2068
#define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC 0x206c
#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080
#define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084
#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
static const unsigned long top_clk_regs[] __initconst = {
PLL_LOCKTIME_PLL_MMC,
PLL_LOCKTIME_PLL_SHARED0,
PLL_LOCKTIME_PLL_SHARED1,
PLL_CON0_PLL_MMC,
PLL_CON3_PLL_MMC,
PLL_CON0_PLL_SHARED0,
PLL_CON3_PLL_SHARED0,
PLL_CON0_PLL_SHARED1,
PLL_CON3_PLL_SHARED1,
CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
CLK_CON_MUX_MUX_CLKCMU_AUD,
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
CLK_CON_MUX_MUX_CLKCMU_CORE_SSS,
CLK_CON_MUX_MUX_CLKCMU_DPU,
CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_HSI_BUS,
CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD,
CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD,
CLK_CON_MUX_MUX_CLKCMU_IS_BUS,
CLK_CON_MUX_MUX_CLKCMU_IS_GDC,
CLK_CON_MUX_MUX_CLKCMU_IS_ITP,
CLK_CON_MUX_MUX_CLKCMU_IS_VRA,
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG,
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M,
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC,
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC,
CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
CLK_CON_MUX_MUX_CLKCMU_PERI_IP,
CLK_CON_MUX_MUX_CLKCMU_PERI_UART,
CLK_CON_DIV_CLKCMU_APM_BUS,
CLK_CON_DIV_CLKCMU_AUD,
CLK_CON_DIV_CLKCMU_CORE_BUS,
CLK_CON_DIV_CLKCMU_CORE_CCI,
CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
CLK_CON_DIV_CLKCMU_CORE_SSS,
CLK_CON_DIV_CLKCMU_DPU,
CLK_CON_DIV_CLKCMU_G3D_SWITCH,
CLK_CON_DIV_CLKCMU_HSI_BUS,
CLK_CON_DIV_CLKCMU_HSI_MMC_CARD,
CLK_CON_DIV_CLKCMU_HSI_USB20DRD,
CLK_CON_DIV_CLKCMU_IS_BUS,
CLK_CON_DIV_CLKCMU_IS_GDC,
CLK_CON_DIV_CLKCMU_IS_ITP,
CLK_CON_DIV_CLKCMU_IS_VRA,
CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG,
CLK_CON_DIV_CLKCMU_MFCMSCL_M2M,
CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC,
CLK_CON_DIV_CLKCMU_MFCMSCL_MFC,
CLK_CON_DIV_CLKCMU_PERI_BUS,
CLK_CON_DIV_CLKCMU_PERI_IP,
CLK_CON_DIV_CLKCMU_PERI_UART,
CLK_CON_DIV_PLL_SHARED0_DIV2,
CLK_CON_DIV_PLL_SHARED0_DIV3,
CLK_CON_DIV_PLL_SHARED0_DIV4,
CLK_CON_DIV_PLL_SHARED1_DIV2,
CLK_CON_DIV_PLL_SHARED1_DIV3,
CLK_CON_DIV_PLL_SHARED1_DIV4,
CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
CLK_CON_GAT_GATE_CLKCMU_AUD,
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
CLK_CON_GAT_GATE_CLKCMU_CORE_SSS,
CLK_CON_GAT_GATE_CLKCMU_DPU,
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
CLK_CON_GAT_GATE_CLKCMU_HSI_BUS,
CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD,
CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD,
CLK_CON_GAT_GATE_CLKCMU_IS_BUS,
CLK_CON_GAT_GATE_CLKCMU_IS_GDC,
CLK_CON_GAT_GATE_CLKCMU_IS_ITP,
CLK_CON_GAT_GATE_CLKCMU_IS_VRA,
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG,
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M,
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC,
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC,
CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
CLK_CON_GAT_GATE_CLKCMU_PERI_IP,
CLK_CON_GAT_GATE_CLKCMU_PERI_UART,
};
/*
* Do not provide PLL tables to core PLLs, as MANUAL_PLL_CTRL bit is not set
* for those PLLs by default, so set_rate operation would fail.
*/
static const struct samsung_pll_clock top_pll_clks[] __initconst = {
/* CMU_TOP_PURECLKCOMP */
PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
NULL),
PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1,
NULL),
PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
};
/* List of parent clocks for Muxes in CMU_TOP */
PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */
PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_AUD */
PNAME(mout_aud_p) = { "fout_shared1_pll", "dout_shared0_div2",
"dout_shared1_div2", "dout_shared0_div3" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3",
"dout_shared1_div3", "dout_shared0_div4" };
PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared0_div3", "dout_shared1_div3" };
PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2",
"dout_shared1_div2", "dout_shared0_div3",
"dout_shared1_div3", "mout_mmc_pll",
"oscclk", "oscclk" };
PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3",
"dout_shared0_div4", "dout_shared1_div4" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
PNAME(mout_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared0_div3", "dout_shared1_div3" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */
PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" };
PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2",
"dout_shared1_div2", "dout_shared0_div3",
"dout_shared1_div3", "mout_mmc_pll",
"oscclk", "oscclk" };
PNAME(mout_hsi_usb20drd_p) = { "oscclk", "dout_shared0_div4",
"dout_shared1_div4", "oscclk" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_IS */
PNAME(mout_is_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared0_div3", "dout_shared1_div3" };
PNAME(mout_is_itp_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared0_div3", "dout_shared1_div3" };
PNAME(mout_is_vra_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared0_div3", "dout_shared1_div3" };
PNAME(mout_is_gdc_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared0_div3", "dout_shared1_div3" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_MFCMSCL */
PNAME(mout_mfcmscl_mfc_p) = { "dout_shared1_div2", "dout_shared0_div3",
"dout_shared1_div3", "dout_shared0_div4" };
PNAME(mout_mfcmscl_m2m_p) = { "dout_shared1_div2", "dout_shared0_div3",
"dout_shared1_div3", "dout_shared0_div4" };
PNAME(mout_mfcmscl_mcsc_p) = { "dout_shared1_div2", "dout_shared0_div3",
"dout_shared1_div3", "dout_shared0_div4" };
PNAME(mout_mfcmscl_jpeg_p) = { "dout_shared0_div3", "dout_shared1_div3",
"dout_shared0_div4", "dout_shared1_div4" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4",
"dout_shared1_div4", "oscclk" };
PNAME(mout_peri_ip_p) = { "oscclk", "dout_shared0_div4",
"dout_shared1_div4", "oscclk" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */
PNAME(mout_dpu_p) = { "dout_shared0_div3", "dout_shared1_div3",
"dout_shared0_div4", "dout_shared1_div4" };
static const struct samsung_mux_clock top_mux_clks[] __initconst = {
/* CMU_TOP_PURECLKCOMP */
MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
PLL_CON0_PLL_SHARED0, 4, 1),
MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
PLL_CON0_PLL_SHARED1, 4, 1),
MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
PLL_CON0_PLL_MMC, 4, 1),
/* APM */
MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus",
mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
/* AUD */
MUX(CLK_MOUT_AUD, "mout_aud", mout_aud_p,
CLK_CON_MUX_MUX_CLKCMU_AUD, 0, 2),
/* CORE */
MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p,
CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2),
MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p,
CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3),
MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p,
CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2),
/* DPU */
MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p,
CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2),
/* G3D */
MUX(CLK_MOUT_G3D_SWITCH, "mout_g3d_switch", mout_g3d_switch_p,
CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
/* HSI */
MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p,
CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1),
MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p,
CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3),
MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p,
CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2),
/* IS */
MUX(CLK_MOUT_IS_BUS, "mout_is_bus", mout_is_bus_p,
CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 0, 2),
MUX(CLK_MOUT_IS_ITP, "mout_is_itp", mout_is_itp_p,
CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 0, 2),
MUX(CLK_MOUT_IS_VRA, "mout_is_vra", mout_is_vra_p,
CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 0, 2),
MUX(CLK_MOUT_IS_GDC, "mout_is_gdc", mout_is_gdc_p,
CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 0, 2),
/* MFCMSCL */
MUX(CLK_MOUT_MFCMSCL_MFC, "mout_mfcmscl_mfc", mout_mfcmscl_mfc_p,
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC, 0, 2),
MUX(CLK_MOUT_MFCMSCL_M2M, "mout_mfcmscl_m2m", mout_mfcmscl_m2m_p,
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M, 0, 2),
MUX(CLK_MOUT_MFCMSCL_MCSC, "mout_mfcmscl_mcsc", mout_mfcmscl_mcsc_p,
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC, 0, 2),
MUX(CLK_MOUT_MFCMSCL_JPEG, "mout_mfcmscl_jpeg", mout_mfcmscl_jpeg_p,
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG, 0, 2),
/* PERI */
MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p,
CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2),
MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p,
CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2),
};
static const struct samsung_div_clock top_div_clks[] __initconst = {
/* CMU_TOP_PURECLKCOMP */
DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
/* APM */
DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus",
"gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
/* AUD */
DIV(CLK_DOUT_AUD, "dout_aud", "gout_aud",
CLK_CON_DIV_CLKCMU_AUD, 0, 4),
/* CORE */
DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci",
CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4),
DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd",
CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9),
DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss",
CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4),
/* DPU */
DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu",
CLK_CON_DIV_CLKCMU_DPU, 0, 4),
/* G3D */
DIV(CLK_DOUT_G3D_SWITCH, "dout_g3d_switch", "gout_g3d_switch",
CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
/* HSI */
DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus",
CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4),
DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card",
CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9),
DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd",
CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4),
/* IS */
DIV(CLK_DOUT_IS_BUS, "dout_is_bus", "gout_is_bus",
CLK_CON_DIV_CLKCMU_IS_BUS, 0, 4),
DIV(CLK_DOUT_IS_ITP, "dout_is_itp", "gout_is_itp",
CLK_CON_DIV_CLKCMU_IS_ITP, 0, 4),
DIV(CLK_DOUT_IS_VRA, "dout_is_vra", "gout_is_vra",
CLK_CON_DIV_CLKCMU_IS_VRA, 0, 4),
DIV(CLK_DOUT_IS_GDC, "dout_is_gdc", "gout_is_gdc",
CLK_CON_DIV_CLKCMU_IS_GDC, 0, 4),
/* MFCMSCL */
DIV(CLK_DOUT_MFCMSCL_MFC, "dout_mfcmscl_mfc", "gout_mfcmscl_mfc",
CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 0, 4),
DIV(CLK_DOUT_MFCMSCL_M2M, "dout_mfcmscl_m2m", "gout_mfcmscl_m2m",
CLK_CON_DIV_CLKCMU_MFCMSCL_M2M, 0, 4),
DIV(CLK_DOUT_MFCMSCL_MCSC, "dout_mfcmscl_mcsc", "gout_mfcmscl_mcsc",
CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC, 0, 4),
DIV(CLK_DOUT_MFCMSCL_JPEG, "dout_mfcmscl_jpeg", "gout_mfcmscl_jpeg",
CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG, 0, 4),
/* PERI */
DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart",
CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4),
DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip",
CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4),
};
static const struct samsung_gate_clock top_gate_clks[] __initconst = {
/* CORE */
GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus",
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci",
CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0),
GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd",
CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0),
GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss",
CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0),
/* APM */
GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus",
"mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0),
/* AUD */
GATE(CLK_GOUT_AUD, "gout_aud", "mout_aud",
CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0),
/* DPU */
GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
/* G3D */
GATE(CLK_GOUT_G3D_SWITCH, "gout_g3d_switch", "mout_g3d_switch",
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
/* HSI */
GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus",
CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0),
GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card",
CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0),
GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd",
CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0),
/* IS */
/* TODO: These clocks have to be always enabled to access CMU_IS regs */
GATE(CLK_GOUT_IS_BUS, "gout_is_bus", "mout_is_bus",
CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_IS_ITP, "gout_is_itp", "mout_is_itp",
CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_IS_VRA, "gout_is_vra", "mout_is_vra",
CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_IS_GDC, "gout_is_gdc", "mout_is_gdc",
CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 21, CLK_IS_CRITICAL, 0),
/* MFCMSCL */
/* TODO: These have to be always enabled to access CMU_MFCMSCL regs */
GATE(CLK_GOUT_MFCMSCL_MFC, "gout_mfcmscl_mfc", "mout_mfcmscl_mfc",
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_MFCMSCL_M2M, "gout_mfcmscl_m2m", "mout_mfcmscl_m2m",
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_MFCMSCL_MCSC, "gout_mfcmscl_mcsc", "mout_mfcmscl_mcsc",
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_MFCMSCL_JPEG, "gout_mfcmscl_jpeg", "mout_mfcmscl_jpeg",
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG, 21, CLK_IS_CRITICAL, 0),
/* PERI */
GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart",
CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0),
GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip",
CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0),
};
static const struct samsung_cmu_info top_cmu_info __initconst = {
.pll_clks = top_pll_clks,
.nr_pll_clks = ARRAY_SIZE(top_pll_clks),
.mux_clks = top_mux_clks,
.nr_mux_clks = ARRAY_SIZE(top_mux_clks),
.div_clks = top_div_clks,
.nr_div_clks = ARRAY_SIZE(top_div_clks),
.gate_clks = top_gate_clks,
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
.nr_clk_ids = CLKS_NR_TOP,
.clk_regs = top_clk_regs,
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
};
static void __init exynos850_cmu_top_init(struct device_node *np)
{
exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
}
/* Register CMU_TOP early, as it's a dependency for other early domains */
CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top",
exynos850_cmu_top_init);
/* ---- CMU_APM ------------------------------------------------------------- */
/* Register Offset definitions for CMU_APM (0x11800000) */
#define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0600
#define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER 0x0610
#define PLL_CON0_MUX_CLK_RCO_APM_USER 0x0620
#define PLL_CON0_MUX_DLL_USER 0x0630
#define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS 0x1000
#define CLK_CON_MUX_MUX_CLK_APM_BUS 0x1004
#define CLK_CON_MUX_MUX_CLK_APM_I3C 0x1008
#define CLK_CON_DIV_CLKCMU_CHUB_BUS 0x1800
#define CLK_CON_DIV_DIV_CLK_APM_BUS 0x1804
#define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808
#define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000
#define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014
#define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018
#define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020
#define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024
#define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028
#define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034
#define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038
#define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc
#define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0
static const unsigned long apm_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_APM_BUS_USER,
PLL_CON0_MUX_CLK_RCO_APM_I3C_USER,
PLL_CON0_MUX_CLK_RCO_APM_USER,
PLL_CON0_MUX_DLL_USER,
CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS,
CLK_CON_MUX_MUX_CLK_APM_BUS,
CLK_CON_MUX_MUX_CLK_APM_I3C,
CLK_CON_DIV_CLKCMU_CHUB_BUS,
CLK_CON_DIV_DIV_CLK_APM_BUS,
CLK_CON_DIV_DIV_CLK_APM_I3C,
CLK_CON_GAT_CLKCMU_CMGP_BUS,
CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS,
CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK,
CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK,
CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK,
CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK,
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK,
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK,
CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK,
CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK,
};
/* List of parent clocks for Muxes in CMU_APM */
PNAME(mout_apm_bus_user_p) = { "oscclk_rco_apm", "dout_clkcmu_apm_bus" };
PNAME(mout_rco_apm_i3c_user_p) = { "oscclk_rco_apm", "clk_rco_i3c_pmic" };
PNAME(mout_rco_apm_user_p) = { "oscclk_rco_apm", "clk_rco_apm__alv" };
PNAME(mout_dll_user_p) = { "oscclk_rco_apm", "clk_dll_dco" };
PNAME(mout_clkcmu_chub_bus_p) = { "mout_apm_bus_user", "mout_dll_user" };
PNAME(mout_apm_bus_p) = { "mout_rco_apm_user", "mout_apm_bus_user",
"mout_dll_user", "oscclk_rco_apm" };
PNAME(mout_apm_i3c_p) = { "dout_apm_i3c", "mout_rco_apm_i3c_user" };
static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000),
FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000),
FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000),
FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000),
};
static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
MUX(CLK_MOUT_APM_BUS_USER, "mout_apm_bus_user", mout_apm_bus_user_p,
PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1),
MUX(CLK_MOUT_RCO_APM_I3C_USER, "mout_rco_apm_i3c_user",
mout_rco_apm_i3c_user_p, PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 4, 1),
MUX(CLK_MOUT_RCO_APM_USER, "mout_rco_apm_user", mout_rco_apm_user_p,
PLL_CON0_MUX_CLK_RCO_APM_USER, 4, 1),
MUX(CLK_MOUT_DLL_USER, "mout_dll_user", mout_dll_user_p,
PLL_CON0_MUX_DLL_USER, 4, 1),
MUX(CLK_MOUT_CLKCMU_CHUB_BUS, "mout_clkcmu_chub_bus",
mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1),
MUX(CLK_MOUT_APM_BUS, "mout_apm_bus", mout_apm_bus_p,
CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2),
MUX(CLK_MOUT_APM_I3C, "mout_apm_i3c", mout_apm_i3c_p,
CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1),
};
static const struct samsung_div_clock apm_div_clks[] __initconst = {
DIV(CLK_DOUT_CLKCMU_CHUB_BUS, "dout_clkcmu_chub_bus",
"gout_clkcmu_chub_bus",
CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3),
DIV(CLK_DOUT_APM_BUS, "dout_apm_bus", "mout_apm_bus",
CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3),
DIV(CLK_DOUT_APM_I3C, "dout_apm_i3c", "mout_apm_bus",
CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3),
};
static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus",
CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0),
GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus",
"mout_clkcmu_chub_bus",
CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0),
GATE(CLK_GOUT_RTC_PCLK, "gout_rtc_pclk", "dout_apm_bus",
CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0),
GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus",
CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0),
GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus",
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0),
GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c",
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0),
GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus",
CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0),
/* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
GATE(CLK_GOUT_GPIO_ALIVE_PCLK, "gout_gpio_alive_pclk", "dout_apm_bus",
CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED,
0),
GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus",
CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus",
CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0),
};
static const struct samsung_cmu_info apm_cmu_info __initconst = {
.mux_clks = apm_mux_clks,
.nr_mux_clks = ARRAY_SIZE(apm_mux_clks),
.div_clks = apm_div_clks,
.nr_div_clks = ARRAY_SIZE(apm_div_clks),
.gate_clks = apm_gate_clks,
.nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
.fixed_clks = apm_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
.nr_clk_ids = CLKS_NR_APM,
.clk_regs = apm_clk_regs,
.nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
.clk_name = "dout_clkcmu_apm_bus",
};
/* ---- CMU_AUD ------------------------------------------------------------- */
#define PLL_LOCKTIME_PLL_AUD 0x0000
#define PLL_CON0_PLL_AUD 0x0100
#define PLL_CON3_PLL_AUD 0x010c
#define PLL_CON0_MUX_CLKCMU_AUD_CPU_USER 0x0600
#define PLL_CON0_MUX_TICK_USB_USER 0x0610
#define CLK_CON_MUX_MUX_CLK_AUD_CPU 0x1000
#define CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH 0x1004
#define CLK_CON_MUX_MUX_CLK_AUD_FM 0x1008
#define CLK_CON_MUX_MUX_CLK_AUD_UAIF0 0x100c
#define CLK_CON_MUX_MUX_CLK_AUD_UAIF1 0x1010
#define CLK_CON_MUX_MUX_CLK_AUD_UAIF2 0x1014
#define CLK_CON_MUX_MUX_CLK_AUD_UAIF3 0x1018
#define CLK_CON_MUX_MUX_CLK_AUD_UAIF4 0x101c
#define CLK_CON_MUX_MUX_CLK_AUD_UAIF5 0x1020
#define CLK_CON_MUX_MUX_CLK_AUD_UAIF6 0x1024
#define CLK_CON_DIV_DIV_CLK_AUD_MCLK 0x1800
#define CLK_CON_DIV_DIV_CLK_AUD_AUDIF 0x1804
#define CLK_CON_DIV_DIV_CLK_AUD_BUSD 0x1808
#define CLK_CON_DIV_DIV_CLK_AUD_BUSP 0x180c
#define CLK_CON_DIV_DIV_CLK_AUD_CNT 0x1810
#define CLK_CON_DIV_DIV_CLK_AUD_CPU 0x1814
#define CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK 0x1818
#define CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG 0x181c
#define CLK_CON_DIV_DIV_CLK_AUD_FM 0x1820
#define CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY 0x1824
#define CLK_CON_DIV_DIV_CLK_AUD_UAIF0 0x1828
#define CLK_CON_DIV_DIV_CLK_AUD_UAIF1 0x182c
#define CLK_CON_DIV_DIV_CLK_AUD_UAIF2 0x1830
#define CLK_CON_DIV_DIV_CLK_AUD_UAIF3 0x1834
#define CLK_CON_DIV_DIV_CLK_AUD_UAIF4 0x1838
#define CLK_CON_DIV_DIV_CLK_AUD_UAIF5 0x183c
#define CLK_CON_DIV_DIV_CLK_AUD_UAIF6 0x1840
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT 0x2000
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0 0x2004
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1 0x2008
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2 0x200c
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3 0x2010
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c
#define CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK 0x2020
#define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c
#define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050
#define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32 0x2054
#define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP 0x2058
#define CLK_CON_GAT_GOUT_AUD_CODEC_MCLK 0x206c
#define CLK_CON_GAT_GOUT_AUD_TZPC_PCLK 0x2070
#define CLK_CON_GAT_GOUT_AUD_GPIO_PCLK 0x2074
#define CLK_CON_GAT_GOUT_AUD_PPMU_ACLK 0x2088
#define CLK_CON_GAT_GOUT_AUD_PPMU_PCLK 0x208c
#define CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1 0x20b4
#define CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK 0x20b8
#define CLK_CON_GAT_GOUT_AUD_WDT_PCLK 0x20bc
static const unsigned long aud_clk_regs[] __initconst = {
PLL_LOCKTIME_PLL_AUD,
PLL_CON0_PLL_AUD,
PLL_CON3_PLL_AUD,
PLL_CON0_MUX_CLKCMU_AUD_CPU_USER,
PLL_CON0_MUX_TICK_USB_USER,
CLK_CON_MUX_MUX_CLK_AUD_CPU,
CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH,
CLK_CON_MUX_MUX_CLK_AUD_FM,
CLK_CON_MUX_MUX_CLK_AUD_UAIF0,
CLK_CON_MUX_MUX_CLK_AUD_UAIF1,
CLK_CON_MUX_MUX_CLK_AUD_UAIF2,
CLK_CON_MUX_MUX_CLK_AUD_UAIF3,
CLK_CON_MUX_MUX_CLK_AUD_UAIF4,
CLK_CON_MUX_MUX_CLK_AUD_UAIF5,
CLK_CON_MUX_MUX_CLK_AUD_UAIF6,
CLK_CON_DIV_DIV_CLK_AUD_MCLK,
CLK_CON_DIV_DIV_CLK_AUD_AUDIF,
CLK_CON_DIV_DIV_CLK_AUD_BUSD,
CLK_CON_DIV_DIV_CLK_AUD_BUSP,
CLK_CON_DIV_DIV_CLK_AUD_CNT,
CLK_CON_DIV_DIV_CLK_AUD_CPU,
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK,
CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG,
CLK_CON_DIV_DIV_CLK_AUD_FM,
CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY,
CLK_CON_DIV_DIV_CLK_AUD_UAIF0,
CLK_CON_DIV_DIV_CLK_AUD_UAIF1,
CLK_CON_DIV_DIV_CLK_AUD_UAIF2,
CLK_CON_DIV_DIV_CLK_AUD_UAIF3,
CLK_CON_DIV_DIV_CLK_AUD_UAIF4,
CLK_CON_DIV_DIV_CLK_AUD_UAIF5,
CLK_CON_DIV_DIV_CLK_AUD_UAIF6,
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT,
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0,
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1,
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2,
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3,
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4,
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5,
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6,
CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK,
CLK_CON_GAT_GOUT_AUD_ABOX_ACLK,
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY,
CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB,
CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32,
CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP,
CLK_CON_GAT_GOUT_AUD_CODEC_MCLK,
CLK_CON_GAT_GOUT_AUD_TZPC_PCLK,
CLK_CON_GAT_GOUT_AUD_GPIO_PCLK,
CLK_CON_GAT_GOUT_AUD_PPMU_ACLK,
CLK_CON_GAT_GOUT_AUD_PPMU_PCLK,
CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1,
CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK,
CLK_CON_GAT_GOUT_AUD_WDT_PCLK,
};
/* List of parent clocks for Muxes in CMU_AUD */
PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll" };
PNAME(mout_aud_cpu_user_p) = { "oscclk", "dout_aud" };
PNAME(mout_aud_cpu_p) = { "dout_aud_cpu", "mout_aud_cpu_user" };
PNAME(mout_aud_cpu_hch_p) = { "mout_aud_cpu", "oscclk" };
PNAME(mout_aud_uaif0_p) = { "dout_aud_uaif0", "ioclk_audiocdclk0" };
PNAME(mout_aud_uaif1_p) = { "dout_aud_uaif1", "ioclk_audiocdclk1" };
PNAME(mout_aud_uaif2_p) = { "dout_aud_uaif2", "ioclk_audiocdclk2" };
PNAME(mout_aud_uaif3_p) = { "dout_aud_uaif3", "ioclk_audiocdclk3" };
PNAME(mout_aud_uaif4_p) = { "dout_aud_uaif4", "ioclk_audiocdclk4" };
PNAME(mout_aud_uaif5_p) = { "dout_aud_uaif5", "ioclk_audiocdclk5" };
PNAME(mout_aud_uaif6_p) = { "dout_aud_uaif6", "ioclk_audiocdclk6" };
PNAME(mout_aud_tick_usb_user_p) = { "oscclk", "tick_usb" };
PNAME(mout_aud_fm_p) = { "oscclk", "dout_aud_fm_spdy" };
/*
* Do not provide PLL table to PLL_AUD, as MANUAL_PLL_CTRL bit is not set
* for that PLL by default, so set_rate operation would fail.
*/
static const struct samsung_pll_clock aud_pll_clks[] __initconst = {
PLL(pll_0831x, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
PLL_LOCKTIME_PLL_AUD, PLL_CON3_PLL_AUD, NULL),
};
static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
FRATE(IOCLK_AUDIOCDCLK0, "ioclk_audiocdclk0", NULL, 0, 25000000),
FRATE(IOCLK_AUDIOCDCLK1, "ioclk_audiocdclk1", NULL, 0, 25000000),
FRATE(IOCLK_AUDIOCDCLK2, "ioclk_audiocdclk2", NULL, 0, 25000000),
FRATE(IOCLK_AUDIOCDCLK3, "ioclk_audiocdclk3", NULL, 0, 25000000),
FRATE(IOCLK_AUDIOCDCLK4, "ioclk_audiocdclk4", NULL, 0, 25000000),
FRATE(IOCLK_AUDIOCDCLK5, "ioclk_audiocdclk5", NULL, 0, 25000000),
FRATE(IOCLK_AUDIOCDCLK6, "ioclk_audiocdclk6", NULL, 0, 25000000),
FRATE(TICK_USB, "tick_usb", NULL, 0, 60000000),
};
static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p,
PLL_CON0_PLL_AUD, 4, 1),
MUX(CLK_MOUT_AUD_CPU_USER, "mout_aud_cpu_user", mout_aud_cpu_user_p,
PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 4, 1),
MUX(CLK_MOUT_AUD_TICK_USB_USER, "mout_aud_tick_usb_user",
mout_aud_tick_usb_user_p,
PLL_CON0_MUX_TICK_USB_USER, 4, 1),
MUX(CLK_MOUT_AUD_CPU, "mout_aud_cpu", mout_aud_cpu_p,
CLK_CON_MUX_MUX_CLK_AUD_CPU, 0, 1),
MUX(CLK_MOUT_AUD_CPU_HCH, "mout_aud_cpu_hch", mout_aud_cpu_hch_p,
CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0, 1),
MUX(CLK_MOUT_AUD_UAIF0, "mout_aud_uaif0", mout_aud_uaif0_p,
CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0, 1),
MUX(CLK_MOUT_AUD_UAIF1, "mout_aud_uaif1", mout_aud_uaif1_p,
CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0, 1),
MUX(CLK_MOUT_AUD_UAIF2, "mout_aud_uaif2", mout_aud_uaif2_p,
CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0, 1),
MUX(CLK_MOUT_AUD_UAIF3, "mout_aud_uaif3", mout_aud_uaif3_p,
CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0, 1),
MUX(CLK_MOUT_AUD_UAIF4, "mout_aud_uaif4", mout_aud_uaif4_p,
CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 0, 1),
MUX(CLK_MOUT_AUD_UAIF5, "mout_aud_uaif5", mout_aud_uaif5_p,
CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 0, 1),
MUX(CLK_MOUT_AUD_UAIF6, "mout_aud_uaif6", mout_aud_uaif6_p,
CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 0, 1),
MUX(CLK_MOUT_AUD_FM, "mout_aud_fm", mout_aud_fm_p,
CLK_CON_MUX_MUX_CLK_AUD_FM, 0, 1),
};
static const struct samsung_div_clock aud_div_clks[] __initconst = {
DIV(CLK_DOUT_AUD_CPU, "dout_aud_cpu", "mout_aud_pll",
CLK_CON_DIV_DIV_CLK_AUD_CPU, 0, 4),
DIV(CLK_DOUT_AUD_BUSD, "dout_aud_busd", "mout_aud_pll",
CLK_CON_DIV_DIV_CLK_AUD_BUSD, 0, 4),
DIV(CLK_DOUT_AUD_BUSP, "dout_aud_busp", "mout_aud_pll",
CLK_CON_DIV_DIV_CLK_AUD_BUSP, 0, 4),
DIV(CLK_DOUT_AUD_AUDIF, "dout_aud_audif", "mout_aud_pll",
CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0, 9),
DIV(CLK_DOUT_AUD_CPU_ACLK, "dout_aud_cpu_aclk", "mout_aud_cpu_hch",
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0, 3),
DIV(CLK_DOUT_AUD_CPU_PCLKDBG, "dout_aud_cpu_pclkdbg",
"mout_aud_cpu_hch",
CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0, 3),
DIV(CLK_DOUT_AUD_MCLK, "dout_aud_mclk", "dout_aud_audif",
CLK_CON_DIV_DIV_CLK_AUD_MCLK, 0, 2),
DIV(CLK_DOUT_AUD_CNT, "dout_aud_cnt", "dout_aud_audif",
CLK_CON_DIV_DIV_CLK_AUD_CNT, 0, 10),
DIV(CLK_DOUT_AUD_UAIF0, "dout_aud_uaif0", "dout_aud_audif",
CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0, 10),
DIV(CLK_DOUT_AUD_UAIF1, "dout_aud_uaif1", "dout_aud_audif",
CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0, 10),
DIV(CLK_DOUT_AUD_UAIF2, "dout_aud_uaif2", "dout_aud_audif",
CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0, 10),
DIV(CLK_DOUT_AUD_UAIF3, "dout_aud_uaif3", "dout_aud_audif",
CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0, 10),
DIV(CLK_DOUT_AUD_UAIF4, "dout_aud_uaif4", "dout_aud_audif",
CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 0, 10),
DIV(CLK_DOUT_AUD_UAIF5, "dout_aud_uaif5", "dout_aud_audif",
CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 0, 10),
DIV(CLK_DOUT_AUD_UAIF6, "dout_aud_uaif6", "dout_aud_audif",
CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 0, 10),
DIV(CLK_DOUT_AUD_FM_SPDY, "dout_aud_fm_spdy", "mout_aud_tick_usb_user",
CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0, 1),
DIV(CLK_DOUT_AUD_FM, "dout_aud_fm", "mout_aud_fm",
CLK_CON_DIV_DIV_CLK_AUD_FM, 0, 10),
};
static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
GATE(CLK_GOUT_AUD_CMU_AUD_PCLK, "gout_aud_cmu_aud_pclk",
"dout_aud_busd",
CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch",
CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0),
GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk",
CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 21, 0, 0),
GATE(CLK_GOUT_AUD_DAP_CCLK, "gout_aud_dap_cclk", "dout_aud_cpu_pclkdbg",
CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 21, 0, 0),
/* TODO: Should be enabled in ABOX driver (or made CLK_IS_CRITICAL) */
GATE(CLK_GOUT_AUD_ABOX_ACLK, "gout_aud_abox_aclk", "dout_aud_busd",
CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_AUD_GPIO_PCLK, "gout_aud_gpio_pclk", "dout_aud_busd",
CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 21, 0, 0),
GATE(CLK_GOUT_AUD_PPMU_ACLK, "gout_aud_ppmu_aclk", "dout_aud_busd",
CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 21, 0, 0),
GATE(CLK_GOUT_AUD_PPMU_PCLK, "gout_aud_ppmu_pclk", "dout_aud_busd",
CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 21, 0, 0),
GATE(CLK_GOUT_AUD_SYSMMU_CLK, "gout_aud_sysmmu_clk", "dout_aud_busd",
CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 21, 0, 0),
GATE(CLK_GOUT_AUD_SYSREG_PCLK, "gout_aud_sysreg_pclk", "dout_aud_busd",
CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 21, 0, 0),
GATE(CLK_GOUT_AUD_WDT_PCLK, "gout_aud_wdt_pclk", "dout_aud_busd",
CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 21, 0, 0),
GATE(CLK_GOUT_AUD_TZPC_PCLK, "gout_aud_tzpc_pclk", "dout_aud_busp",
CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 21, 0, 0),
GATE(CLK_GOUT_AUD_CODEC_MCLK, "gout_aud_codec_mclk", "dout_aud_mclk",
CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 21, 0, 0),
GATE(CLK_GOUT_AUD_CNT_BCLK, "gout_aud_cnt_bclk", "dout_aud_cnt",
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 21, 0, 0),
GATE(CLK_GOUT_AUD_UAIF0_BCLK, "gout_aud_uaif0_bclk", "mout_aud_uaif0",
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 21, 0, 0),
GATE(CLK_GOUT_AUD_UAIF1_BCLK, "gout_aud_uaif1_bclk", "mout_aud_uaif1",
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 21, 0, 0),
GATE(CLK_GOUT_AUD_UAIF2_BCLK, "gout_aud_uaif2_bclk", "mout_aud_uaif2",
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 21, 0, 0),
GATE(CLK_GOUT_AUD_UAIF3_BCLK, "gout_aud_uaif3_bclk", "mout_aud_uaif3",
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 21, 0, 0),
GATE(CLK_GOUT_AUD_UAIF4_BCLK, "gout_aud_uaif4_bclk", "mout_aud_uaif4",
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 21, 0, 0),
GATE(CLK_GOUT_AUD_UAIF5_BCLK, "gout_aud_uaif5_bclk", "mout_aud_uaif5",
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 21, 0, 0),
GATE(CLK_GOUT_AUD_UAIF6_BCLK, "gout_aud_uaif6_bclk", "mout_aud_uaif6",
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 21, 0, 0),
GATE(CLK_GOUT_AUD_SPDY_BCLK, "gout_aud_spdy_bclk", "dout_aud_fm",
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 21, 0, 0),
};
static const struct samsung_cmu_info aud_cmu_info __initconst = {
.pll_clks = aud_pll_clks,
.nr_pll_clks = ARRAY_SIZE(aud_pll_clks),
.mux_clks = aud_mux_clks,
.nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
.div_clks = aud_div_clks,
.nr_div_clks = ARRAY_SIZE(aud_div_clks),
.gate_clks = aud_gate_clks,
.nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
.fixed_clks = aud_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
.nr_clk_ids = CLKS_NR_AUD,
.clk_regs = aud_clk_regs,
.nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
.clk_name = "dout_aud",
};
/* ---- CMU_CMGP ------------------------------------------------------------ */
/* Register Offset definitions for CMU_CMGP (0x11c00000) */
#define CLK_CON_MUX_CLK_CMGP_ADC 0x1000
#define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004
#define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008
#define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800
#define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804
#define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808
#define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c
#define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010
#define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018
#define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040
#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044
#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048
#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c
#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050
static const unsigned long cmgp_clk_regs[] __initconst = {
CLK_CON_MUX_CLK_CMGP_ADC,
CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0,
CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1,
CLK_CON_DIV_DIV_CLK_CMGP_ADC,
CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0,
CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1,
CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0,
CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1,
CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK,
CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK,
CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK,
CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK,
CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK,
CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK,
};
/* List of parent clocks for Muxes in CMU_CMGP */
PNAME(mout_cmgp_usi0_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
PNAME(mout_cmgp_usi1_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
PNAME(mout_cmgp_adc_p) = { "oscclk", "dout_cmgp_adc" };
static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = {
FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000),
};
static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = {
MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p,
CLK_CON_MUX_CLK_CMGP_ADC, 0, 1),
MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p,
CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1),
MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p,
CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1),
};
static const struct samsung_div_clock cmgp_div_clks[] __initconst = {
DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus",
CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4),
DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0",
CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5),
DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1",
CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5),
};
static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = {
GATE(CLK_GOUT_CMGP_ADC_S0_PCLK, "gout_adc_s0_pclk",
"gout_clkcmu_cmgp_bus",
CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0),
GATE(CLK_GOUT_CMGP_ADC_S1_PCLK, "gout_adc_s1_pclk",
"gout_clkcmu_cmgp_bus",
CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0),
/* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_gpio_cmgp_pclk",
"gout_clkcmu_cmgp_bus",
CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0",
CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0),
GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk",
"gout_clkcmu_cmgp_bus",
CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0),
GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1",
CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0),
GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk",
"gout_clkcmu_cmgp_bus",
CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0),
GATE(CLK_GOUT_SYSREG_CMGP_PCLK, "gout_sysreg_cmgp_pclk",
"gout_clkcmu_cmgp_bus",
CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0),
};
static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
.mux_clks = cmgp_mux_clks,
.nr_mux_clks = ARRAY_SIZE(cmgp_mux_clks),
.div_clks = cmgp_div_clks,
.nr_div_clks = ARRAY_SIZE(cmgp_div_clks),
.gate_clks = cmgp_gate_clks,
.nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks),
.fixed_clks = cmgp_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks),
.nr_clk_ids = CLKS_NR_CMGP,
.clk_regs = cmgp_clk_regs,
.nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs),
.clk_name = "gout_clkcmu_cmgp_bus",
};
/* ---- CMU_G3D ------------------------------------------------------------- */
/* Register Offset definitions for CMU_G3D (0x11400000) */
#define PLL_LOCKTIME_PLL_G3D 0x0000
#define PLL_CON0_PLL_G3D 0x0100
#define PLL_CON3_PLL_G3D 0x010c
#define PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER 0x0600
#define CLK_CON_MUX_MUX_CLK_G3D_BUSD 0x1000
#define CLK_CON_DIV_DIV_CLK_G3D_BUSP 0x1804
#define CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK 0x2000
#define CLK_CON_GAT_CLK_G3D_GPU_CLK 0x2004
#define CLK_CON_GAT_GOUT_G3D_TZPC_PCLK 0x200c
#define CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK 0x2010
#define CLK_CON_GAT_GOUT_G3D_BUSD_CLK 0x2024
#define CLK_CON_GAT_GOUT_G3D_BUSP_CLK 0x2028
#define CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK 0x202c
static const unsigned long g3d_clk_regs[] __initconst = {
PLL_LOCKTIME_PLL_G3D,
PLL_CON0_PLL_G3D,
PLL_CON3_PLL_G3D,
PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER,
CLK_CON_MUX_MUX_CLK_G3D_BUSD,
CLK_CON_DIV_DIV_CLK_G3D_BUSP,
CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK,
CLK_CON_GAT_CLK_G3D_GPU_CLK,
CLK_CON_GAT_GOUT_G3D_TZPC_PCLK,
CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK,
CLK_CON_GAT_GOUT_G3D_BUSD_CLK,
CLK_CON_GAT_GOUT_G3D_BUSP_CLK,
CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK,
};
/* List of parent clocks for Muxes in CMU_G3D */
PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll" };
PNAME(mout_g3d_switch_user_p) = { "oscclk", "dout_g3d_switch" };
PNAME(mout_g3d_busd_p) = { "mout_g3d_pll", "mout_g3d_switch_user" };
/*
* Do not provide PLL table to PLL_G3D, as MANUAL_PLL_CTRL bit is not set
* for that PLL by default, so set_rate operation would fail.
*/
static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
PLL(pll_0818x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL),
};
static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
PLL_CON0_PLL_G3D, 4, 1),
MUX(CLK_MOUT_G3D_SWITCH_USER, "mout_g3d_switch_user",
mout_g3d_switch_user_p,
PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 4, 1),
MUX(CLK_MOUT_G3D_BUSD, "mout_g3d_busd", mout_g3d_busd_p,
CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0, 1),
};
static const struct samsung_div_clock g3d_div_clks[] __initconst = {
DIV(CLK_DOUT_G3D_BUSP, "dout_g3d_busp", "mout_g3d_busd",
CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0, 3),
};
static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
GATE(CLK_GOUT_G3D_CMU_G3D_PCLK, "gout_g3d_cmu_g3d_pclk",
"dout_g3d_busp",
CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_G3D_GPU_CLK, "gout_g3d_gpu_clk", "mout_g3d_busd",
CLK_CON_GAT_CLK_G3D_GPU_CLK, 21, 0, 0),
GATE(CLK_GOUT_G3D_TZPC_PCLK, "gout_g3d_tzpc_pclk", "dout_g3d_busp",
CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, 21, 0, 0),
GATE(CLK_GOUT_G3D_GRAY2BIN_CLK, "gout_g3d_gray2bin_clk",
"mout_g3d_busd",
CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, 21, 0, 0),
GATE(CLK_GOUT_G3D_BUSD_CLK, "gout_g3d_busd_clk", "mout_g3d_busd",
CLK_CON_GAT_GOUT_G3D_BUSD_CLK, 21, 0, 0),
GATE(CLK_GOUT_G3D_BUSP_CLK, "gout_g3d_busp_clk", "dout_g3d_busp",
CLK_CON_GAT_GOUT_G3D_BUSP_CLK, 21, 0, 0),
GATE(CLK_GOUT_G3D_SYSREG_PCLK, "gout_g3d_sysreg_pclk", "dout_g3d_busp",
CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, 21, 0, 0),
};
static const struct samsung_cmu_info g3d_cmu_info __initconst = {
.pll_clks = g3d_pll_clks,
.nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
.mux_clks = g3d_mux_clks,
.nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
.div_clks = g3d_div_clks,
.nr_div_clks = ARRAY_SIZE(g3d_div_clks),
.gate_clks = g3d_gate_clks,
.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
.nr_clk_ids = CLKS_NR_G3D,
.clk_regs = g3d_clk_regs,
.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
.clk_name = "dout_g3d_switch",
};
/* ---- CMU_HSI ------------------------------------------------------------- */
/* Register Offset definitions for CMU_HSI (0x13400000) */
#define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600
#define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610
#define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620
#define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000
#define CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK 0x2000
#define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008
#define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c
#define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010
#define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018
#define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024
#define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028
#define CLK_CON_GAT_GOUT_HSI_PPMU_ACLK 0x202c
#define CLK_CON_GAT_GOUT_HSI_PPMU_PCLK 0x2030
#define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038
#define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c
#define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040
static const unsigned long hsi_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_HSI_BUS_USER,
PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER,
PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER,
CLK_CON_MUX_MUX_CLK_HSI_RTC,
CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK,
CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV,
CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50,
CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26,
CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK,
CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK,
CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN,
CLK_CON_GAT_GOUT_HSI_PPMU_ACLK,
CLK_CON_GAT_GOUT_HSI_PPMU_PCLK,
CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK,
CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20,
CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY,
};
/* List of parent clocks for Muxes in CMU_HSI */
PNAME(mout_hsi_bus_user_p) = { "oscclk", "dout_hsi_bus" };
PNAME(mout_hsi_mmc_card_user_p) = { "oscclk", "dout_hsi_mmc_card" };
PNAME(mout_hsi_usb20drd_user_p) = { "oscclk", "dout_hsi_usb20drd" };
PNAME(mout_hsi_rtc_p) = { "rtcclk", "oscclk" };
static const struct samsung_mux_clock hsi_mux_clks[] __initconst = {
MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p,
PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1),
MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user",
mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER,
4, 1, CLK_SET_RATE_PARENT, 0),
MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user",
mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER,
4, 1),
MUX(CLK_MOUT_HSI_RTC, "mout_hsi_rtc", mout_hsi_rtc_p,
CLK_CON_MUX_MUX_CLK_HSI_RTC, 0, 1),
};
static const struct samsung_gate_clock hsi_gate_clks[] __initconst = {
/* TODO: Should be enabled in corresponding driver */
GATE(CLK_GOUT_HSI_CMU_HSI_PCLK, "gout_hsi_cmu_hsi_pclk",
"mout_hsi_bus_user",
CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc",
CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0),
GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user",
CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0),
GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "oscclk",
CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0),
/* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
GATE(CLK_GOUT_GPIO_HSI_PCLK, "gout_gpio_hsi_pclk", "mout_hsi_bus_user",
CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user",
CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0),
GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
"mout_hsi_mmc_card_user",
CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_HSI_PPMU_ACLK, "gout_hsi_ppmu_aclk", "mout_hsi_bus_user",
CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 21, 0, 0),
GATE(CLK_GOUT_HSI_PPMU_PCLK, "gout_hsi_ppmu_pclk", "mout_hsi_bus_user",
CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 21, 0, 0),
GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk",
"mout_hsi_bus_user",
CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0),
GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user",
CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0),
GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early",
"mout_hsi_bus_user",
CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0),
};
static const struct samsung_cmu_info hsi_cmu_info __initconst = {
.mux_clks = hsi_mux_clks,
.nr_mux_clks = ARRAY_SIZE(hsi_mux_clks),
.gate_clks = hsi_gate_clks,
.nr_gate_clks = ARRAY_SIZE(hsi_gate_clks),
.nr_clk_ids = CLKS_NR_HSI,
.clk_regs = hsi_clk_regs,
.nr_clk_regs = ARRAY_SIZE(hsi_clk_regs),
.clk_name = "dout_hsi_bus",
};
/* ---- CMU_IS -------------------------------------------------------------- */
#define PLL_CON0_MUX_CLKCMU_IS_BUS_USER 0x0600
#define PLL_CON0_MUX_CLKCMU_IS_GDC_USER 0x0610
#define PLL_CON0_MUX_CLKCMU_IS_ITP_USER 0x0620
#define PLL_CON0_MUX_CLKCMU_IS_VRA_USER 0x0630
#define CLK_CON_DIV_DIV_CLK_IS_BUSP 0x1800
#define CLK_CON_GAT_CLK_IS_CMU_IS_PCLK 0x2000
#define CLK_CON_GAT_GOUT_IS_CSIS0_ACLK 0x2040
#define CLK_CON_GAT_GOUT_IS_CSIS1_ACLK 0x2044
#define CLK_CON_GAT_GOUT_IS_CSIS2_ACLK 0x2048
#define CLK_CON_GAT_GOUT_IS_TZPC_PCLK 0x204c
#define CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA 0x2050
#define CLK_CON_GAT_GOUT_IS_CLK_GDC 0x2054
#define CLK_CON_GAT_GOUT_IS_CLK_IPP 0x2058
#define CLK_CON_GAT_GOUT_IS_CLK_ITP 0x205c
#define CLK_CON_GAT_GOUT_IS_CLK_MCSC 0x2060
#define CLK_CON_GAT_GOUT_IS_CLK_VRA 0x2064
#define CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK 0x2074
#define CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK 0x2078
#define CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK 0x207c
#define CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK 0x2080
#define CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1 0x2098
#define CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1 0x209c
#define CLK_CON_GAT_GOUT_IS_SYSREG_PCLK 0x20a0
static const unsigned long is_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_IS_BUS_USER,
PLL_CON0_MUX_CLKCMU_IS_GDC_USER,
PLL_CON0_MUX_CLKCMU_IS_ITP_USER,
PLL_CON0_MUX_CLKCMU_IS_VRA_USER,
CLK_CON_DIV_DIV_CLK_IS_BUSP,
CLK_CON_GAT_CLK_IS_CMU_IS_PCLK,
CLK_CON_GAT_GOUT_IS_CSIS0_ACLK,
CLK_CON_GAT_GOUT_IS_CSIS1_ACLK,
CLK_CON_GAT_GOUT_IS_CSIS2_ACLK,
CLK_CON_GAT_GOUT_IS_TZPC_PCLK,
CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA,
CLK_CON_GAT_GOUT_IS_CLK_GDC,
CLK_CON_GAT_GOUT_IS_CLK_IPP,
CLK_CON_GAT_GOUT_IS_CLK_ITP,
CLK_CON_GAT_GOUT_IS_CLK_MCSC,
CLK_CON_GAT_GOUT_IS_CLK_VRA,
CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK,
CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK,
CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK,
CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK,
CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1,
CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1,
CLK_CON_GAT_GOUT_IS_SYSREG_PCLK,
};
/* List of parent clocks for Muxes in CMU_IS */
PNAME(mout_is_bus_user_p) = { "oscclk", "dout_is_bus" };
PNAME(mout_is_itp_user_p) = { "oscclk", "dout_is_itp" };
PNAME(mout_is_vra_user_p) = { "oscclk", "dout_is_vra" };
PNAME(mout_is_gdc_user_p) = { "oscclk", "dout_is_gdc" };
static const struct samsung_mux_clock is_mux_clks[] __initconst = {
MUX(CLK_MOUT_IS_BUS_USER, "mout_is_bus_user", mout_is_bus_user_p,
PLL_CON0_MUX_CLKCMU_IS_BUS_USER, 4, 1),
MUX(CLK_MOUT_IS_ITP_USER, "mout_is_itp_user", mout_is_itp_user_p,
PLL_CON0_MUX_CLKCMU_IS_ITP_USER, 4, 1),
MUX(CLK_MOUT_IS_VRA_USER, "mout_is_vra_user", mout_is_vra_user_p,
PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 4, 1),
MUX(CLK_MOUT_IS_GDC_USER, "mout_is_gdc_user", mout_is_gdc_user_p,
PLL_CON0_MUX_CLKCMU_IS_GDC_USER, 4, 1),
};
static const struct samsung_div_clock is_div_clks[] __initconst = {
DIV(CLK_DOUT_IS_BUSP, "dout_is_busp", "mout_is_bus_user",
CLK_CON_DIV_DIV_CLK_IS_BUSP, 0, 2),
};
static const struct samsung_gate_clock is_gate_clks[] __initconst = {
/* TODO: Should be enabled in IS driver */
GATE(CLK_GOUT_IS_CMU_IS_PCLK, "gout_is_cmu_is_pclk", "dout_is_busp",
CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_IS_CSIS0_ACLK, "gout_is_csis0_aclk", "mout_is_bus_user",
CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 21, 0, 0),
GATE(CLK_GOUT_IS_CSIS1_ACLK, "gout_is_csis1_aclk", "mout_is_bus_user",
CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 21, 0, 0),
GATE(CLK_GOUT_IS_CSIS2_ACLK, "gout_is_csis2_aclk", "mout_is_bus_user",
CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 21, 0, 0),
GATE(CLK_GOUT_IS_TZPC_PCLK, "gout_is_tzpc_pclk", "dout_is_busp",
CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 21, 0, 0),
GATE(CLK_GOUT_IS_CSIS_DMA_CLK, "gout_is_csis_dma_clk",
"mout_is_bus_user",
CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 21, 0, 0),
GATE(CLK_GOUT_IS_GDC_CLK, "gout_is_gdc_clk", "mout_is_gdc_user",
CLK_CON_GAT_GOUT_IS_CLK_GDC, 21, 0, 0),
GATE(CLK_GOUT_IS_IPP_CLK, "gout_is_ipp_clk", "mout_is_bus_user",
CLK_CON_GAT_GOUT_IS_CLK_IPP, 21, 0, 0),
GATE(CLK_GOUT_IS_ITP_CLK, "gout_is_itp_clk", "mout_is_itp_user",
CLK_CON_GAT_GOUT_IS_CLK_ITP, 21, 0, 0),
GATE(CLK_GOUT_IS_MCSC_CLK, "gout_is_mcsc_clk", "mout_is_itp_user",
CLK_CON_GAT_GOUT_IS_CLK_MCSC, 21, 0, 0),
GATE(CLK_GOUT_IS_VRA_CLK, "gout_is_vra_clk", "mout_is_vra_user",
CLK_CON_GAT_GOUT_IS_CLK_VRA, 21, 0, 0),
GATE(CLK_GOUT_IS_PPMU_IS0_ACLK, "gout_is_ppmu_is0_aclk",
"mout_is_bus_user",
CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 21, 0, 0),
GATE(CLK_GOUT_IS_PPMU_IS0_PCLK, "gout_is_ppmu_is0_pclk", "dout_is_busp",
CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 21, 0, 0),
GATE(CLK_GOUT_IS_PPMU_IS1_ACLK, "gout_is_ppmu_is1_aclk",
"mout_is_itp_user",
CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 21, 0, 0),
GATE(CLK_GOUT_IS_PPMU_IS1_PCLK, "gout_is_ppmu_is1_pclk", "dout_is_busp",
CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 21, 0, 0),
GATE(CLK_GOUT_IS_SYSMMU_IS0_CLK, "gout_is_sysmmu_is0_clk",
"mout_is_bus_user",
CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 21, 0, 0),
GATE(CLK_GOUT_IS_SYSMMU_IS1_CLK, "gout_is_sysmmu_is1_clk",
"mout_is_itp_user",
CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 21, 0, 0),
GATE(CLK_GOUT_IS_SYSREG_PCLK, "gout_is_sysreg_pclk", "dout_is_busp",
CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 21, 0, 0),
};
static const struct samsung_cmu_info is_cmu_info __initconst = {
.mux_clks = is_mux_clks,
.nr_mux_clks = ARRAY_SIZE(is_mux_clks),
.div_clks = is_div_clks,
.nr_div_clks = ARRAY_SIZE(is_div_clks),
.gate_clks = is_gate_clks,
.nr_gate_clks = ARRAY_SIZE(is_gate_clks),
.nr_clk_ids = CLKS_NR_IS,
.clk_regs = is_clk_regs,
.nr_clk_regs = ARRAY_SIZE(is_clk_regs),
.clk_name = "dout_is_bus",
};
/* ---- CMU_MFCMSCL --------------------------------------------------------- */
#define PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER 0x0600
#define PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER 0x0610
#define PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER 0x0620
#define PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER 0x0630
#define CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP 0x1800
#define CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK 0x2000
#define CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK 0x2038
#define CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK 0x203c
#define CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK 0x2048
#define CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK 0x204c
#define CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK 0x2050
#define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK 0x2054
#define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK 0x2058
#define CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1 0x2074
#define CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK 0x2078
static const unsigned long mfcmscl_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER,
PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER,
PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER,
PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER,
CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP,
CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK,
CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK,
CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK,
CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK,
CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK,
CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK,
CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK,
CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK,
CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1,
CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK,
};
/* List of parent clocks for Muxes in CMU_MFCMSCL */
PNAME(mout_mfcmscl_mfc_user_p) = { "oscclk", "dout_mfcmscl_mfc" };
PNAME(mout_mfcmscl_m2m_user_p) = { "oscclk", "dout_mfcmscl_m2m" };
PNAME(mout_mfcmscl_mcsc_user_p) = { "oscclk", "dout_mfcmscl_mcsc" };
PNAME(mout_mfcmscl_jpeg_user_p) = { "oscclk", "dout_mfcmscl_jpeg" };
static const struct samsung_mux_clock mfcmscl_mux_clks[] __initconst = {
MUX(CLK_MOUT_MFCMSCL_MFC_USER, "mout_mfcmscl_mfc_user",
mout_mfcmscl_mfc_user_p,
PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER, 4, 1),
MUX(CLK_MOUT_MFCMSCL_M2M_USER, "mout_mfcmscl_m2m_user",
mout_mfcmscl_m2m_user_p,
PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER, 4, 1),
MUX(CLK_MOUT_MFCMSCL_MCSC_USER, "mout_mfcmscl_mcsc_user",
mout_mfcmscl_mcsc_user_p,
PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER, 4, 1),
MUX(CLK_MOUT_MFCMSCL_JPEG_USER, "mout_mfcmscl_jpeg_user",
mout_mfcmscl_jpeg_user_p,
PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER, 4, 1),
};
static const struct samsung_div_clock mfcmscl_div_clks[] __initconst = {
DIV(CLK_DOUT_MFCMSCL_BUSP, "dout_mfcmscl_busp", "mout_mfcmscl_mfc_user",
CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP, 0, 3),
};
static const struct samsung_gate_clock mfcmscl_gate_clks[] __initconst = {
/* TODO: Should be enabled in MFC driver */
GATE(CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK, "gout_mfcmscl_cmu_mfcmscl_pclk",
"dout_mfcmscl_busp", CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK,
21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_MFCMSCL_TZPC_PCLK, "gout_mfcmscl_tzpc_pclk",
"dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK,
21, 0, 0),
GATE(CLK_GOUT_MFCMSCL_JPEG_ACLK, "gout_mfcmscl_jpeg_aclk",
"mout_mfcmscl_jpeg_user", CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK,
21, 0, 0),
GATE(CLK_GOUT_MFCMSCL_M2M_ACLK, "gout_mfcmscl_m2m_aclk",
"mout_mfcmscl_m2m_user", CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK,
21, 0, 0),
GATE(CLK_GOUT_MFCMSCL_MCSC_CLK, "gout_mfcmscl_mcsc_clk",
"mout_mfcmscl_mcsc_user", CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK,
21, 0, 0),
GATE(CLK_GOUT_MFCMSCL_MFC_ACLK, "gout_mfcmscl_mfc_aclk",
"mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK,
21, 0, 0),
GATE(CLK_GOUT_MFCMSCL_PPMU_ACLK, "gout_mfcmscl_ppmu_aclk",
"mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK,
21, 0, 0),
GATE(CLK_GOUT_MFCMSCL_PPMU_PCLK, "gout_mfcmscl_ppmu_pclk",
"dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK,
21, 0, 0),
GATE(CLK_GOUT_MFCMSCL_SYSMMU_CLK, "gout_mfcmscl_sysmmu_clk",
"mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1,
21, 0, 0),
GATE(CLK_GOUT_MFCMSCL_SYSREG_PCLK, "gout_mfcmscl_sysreg_pclk",
"dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK,
21, 0, 0),
};
static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = {
.mux_clks = mfcmscl_mux_clks,
.nr_mux_clks = ARRAY_SIZE(mfcmscl_mux_clks),
.div_clks = mfcmscl_div_clks,
.nr_div_clks = ARRAY_SIZE(mfcmscl_div_clks),
.gate_clks = mfcmscl_gate_clks,
.nr_gate_clks = ARRAY_SIZE(mfcmscl_gate_clks),
.nr_clk_ids = CLKS_NR_MFCMSCL,
.clk_regs = mfcmscl_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs),
.clk_name = "dout_mfcmscl_mfc",
};
/* ---- CMU_PERI ------------------------------------------------------------ */
/* Register Offset definitions for CMU_PERI (0x10030000) */
#define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600
#define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER 0x0610
#define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER 0x0620
#define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630
#define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0 0x1800
#define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1 0x1804
#define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2 0x1808
#define CLK_CON_DIV_DIV_CLK_PERI_SPI_0 0x180c
#define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c
#define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010
#define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014
#define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020
#define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024
#define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028
#define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK 0x202c
#define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x2030
#define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK 0x2034
#define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2038
#define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x203c
#define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x2040
#define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2044
#define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2048
#define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x204c
#define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x2050
#define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2054
#define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x205c
#define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2064
#define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK 0x209c
#define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x20a0
#define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20a4
#define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8
#define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac
#define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK 0x20b0
#define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK 0x20b4
static const unsigned long peri_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_PERI_BUS_USER,
PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER,
PLL_CON0_MUX_CLKCMU_PERI_SPI_USER,
PLL_CON0_MUX_CLKCMU_PERI_UART_USER,
CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0,
CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1,
CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2,
CLK_CON_DIV_DIV_CLK_PERI_SPI_0,
CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0,
CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1,
CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2,
CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK,
CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK,
CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK,
CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK,
CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK,
CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK,
CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK,
CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK,
CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK,
CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK,
CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK,
CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK,
CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK,
CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK,
CLK_CON_GAT_GOUT_PERI_MCT_PCLK,
CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK,
CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK,
CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK,
CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK,
CLK_CON_GAT_GOUT_PERI_UART_IPCLK,
CLK_CON_GAT_GOUT_PERI_UART_PCLK,
CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK,
CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK,
};
/* List of parent clocks for Muxes in CMU_PERI */
PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" };
PNAME(mout_peri_uart_user_p) = { "oscclk", "dout_peri_uart" };
PNAME(mout_peri_hsi2c_user_p) = { "oscclk", "dout_peri_ip" };
PNAME(mout_peri_spi_user_p) = { "oscclk", "dout_peri_ip" };
static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p,
PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1),
MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user",
mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1),
MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user",
mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1),
MUX(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user", mout_peri_spi_user_p,
PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1),
};
static const struct samsung_div_clock peri_div_clks[] __initconst = {
DIV(CLK_DOUT_PERI_HSI2C0, "dout_peri_hsi2c0", "gout_peri_hsi2c0",
CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 0, 5),
DIV(CLK_DOUT_PERI_HSI2C1, "dout_peri_hsi2c1", "gout_peri_hsi2c1",
CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5),
DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2",
CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5),
DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user",
CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5),
};
static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
GATE(CLK_GOUT_PERI_HSI2C0, "gout_peri_hsi2c0", "mout_peri_hsi2c_user",
CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 21, 0, 0),
GATE(CLK_GOUT_PERI_HSI2C1, "gout_peri_hsi2c1", "mout_peri_hsi2c_user",
CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 21, 0, 0),
GATE(CLK_GOUT_PERI_HSI2C2, "gout_peri_hsi2c2", "mout_peri_hsi2c_user",
CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 21, 0, 0),
GATE(CLK_GOUT_HSI2C0_IPCLK, "gout_hsi2c0_ipclk", "dout_peri_hsi2c0",
CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 21, 0, 0),
GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0),
GATE(CLK_GOUT_HSI2C1_IPCLK, "gout_hsi2c1_ipclk", "dout_peri_hsi2c1",
CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 21, 0, 0),
GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0),
GATE(CLK_GOUT_HSI2C2_IPCLK, "gout_hsi2c2_ipclk", "dout_peri_hsi2c2",
CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 21, 0, 0),
GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0),
GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0),
GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0),
GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0),
GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0),
GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0),
GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0),
GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0),
GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0),
GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk",
"mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0),
GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0",
CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, 0, 0),
GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0),
GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk",
"mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0),
GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user",
CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0),
GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0),
GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0),
GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0),
/* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk",
"mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_cmu_info peri_cmu_info __initconst = {
.mux_clks = peri_mux_clks,
.nr_mux_clks = ARRAY_SIZE(peri_mux_clks),
.div_clks = peri_div_clks,
.nr_div_clks = ARRAY_SIZE(peri_div_clks),
.gate_clks = peri_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
.nr_clk_ids = CLKS_NR_PERI,
.clk_regs = peri_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
.clk_name = "dout_peri_bus",
};
static void __init exynos850_cmu_peri_init(struct device_node *np)
{
exynos_arm64_register_cmu(NULL, np, &peri_cmu_info);
}
/* Register CMU_PERI early, as it's needed for MCT timer */
CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri",
exynos850_cmu_peri_init);
/* ---- CMU_CORE ------------------------------------------------------------ */
/* Register Offset definitions for CMU_CORE (0x12000000) */
#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600
#define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0610
#define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620
#define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER 0x0630
#define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000
#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
#define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038
#define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040
#define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044
#define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8
#define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec
#define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128
#define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c
#define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130
static const unsigned long core_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
PLL_CON0_MUX_CLKCMU_CORE_CCI_USER,
PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER,
PLL_CON0_MUX_CLKCMU_CORE_SSS_USER,
CLK_CON_MUX_MUX_CLK_CORE_GIC,
CLK_CON_DIV_DIV_CLK_CORE_BUSP,
CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK,
CLK_CON_GAT_GOUT_CORE_GIC_CLK,
CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK,
CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK,
CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK,
CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK,
CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK,
};
/* List of parent clocks for Muxes in CMU_CORE */
PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" };
PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" };
PNAME(mout_core_mmc_embd_user_p) = { "oscclk", "dout_core_mmc_embd" };
PNAME(mout_core_sss_user_p) = { "oscclk", "dout_core_sss" };
PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" };
static const struct samsung_mux_clock core_mux_clks[] __initconst = {
MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p,
PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1),
MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user",
mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER,
4, 1, CLK_SET_RATE_PARENT, 0),
MUX(CLK_MOUT_CORE_SSS_USER, "mout_core_sss_user", mout_core_sss_user_p,
PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 4, 1),
MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p,
CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1),
};
static const struct samsung_div_clock core_div_clks[] __initconst = {
DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2),
};
static const struct samsung_gate_clock core_gate_clks[] __initconst = {
/* CCI (interconnect) clock must be always running */
GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user",
CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0),
/* GIC (interrupt controller) clock must be always running */
GATE(CLK_GOUT_GIC_CLK, "gout_gic_clk", "mout_core_gic",
CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp",
CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0),
GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin",
"mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user",
CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0),
GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp",
CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0),
/* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
GATE(CLK_GOUT_GPIO_CORE_PCLK, "gout_gpio_core_pclk", "dout_core_busp",
CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_SYSREG_CORE_PCLK, "gout_sysreg_core_pclk",
"dout_core_busp",
CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0),
};
static const struct samsung_cmu_info core_cmu_info __initconst = {
.mux_clks = core_mux_clks,
.nr_mux_clks = ARRAY_SIZE(core_mux_clks),
.div_clks = core_div_clks,
.nr_div_clks = ARRAY_SIZE(core_div_clks),
.gate_clks = core_gate_clks,
.nr_gate_clks = ARRAY_SIZE(core_gate_clks),
.nr_clk_ids = CLKS_NR_CORE,
.clk_regs = core_clk_regs,
.nr_clk_regs = ARRAY_SIZE(core_clk_regs),
.clk_name = "dout_core_bus",
};
/* ---- CMU_DPU ------------------------------------------------------------- */
/* Register Offset definitions for CMU_DPU (0x13000000) */
#define PLL_CON0_MUX_CLKCMU_DPU_USER 0x0600
#define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800
#define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK 0x2004
#define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0 0x2010
#define CLK_CON_GAT_GOUT_DPU_ACLK_DMA 0x2014
#define CLK_CON_GAT_GOUT_DPU_ACLK_DPP 0x2018
#define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK 0x2028
#define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK 0x202c
#define CLK_CON_GAT_GOUT_DPU_SMMU_CLK 0x2038
#define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK 0x203c
static const unsigned long dpu_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_DPU_USER,
CLK_CON_DIV_DIV_CLK_DPU_BUSP,
CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK,
CLK_CON_GAT_GOUT_DPU_ACLK_DECON0,
CLK_CON_GAT_GOUT_DPU_ACLK_DMA,
CLK_CON_GAT_GOUT_DPU_ACLK_DPP,
CLK_CON_GAT_GOUT_DPU_PPMU_ACLK,
CLK_CON_GAT_GOUT_DPU_PPMU_PCLK,
CLK_CON_GAT_GOUT_DPU_SMMU_CLK,
CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK,
};
/* List of parent clocks for Muxes in CMU_DPU */
PNAME(mout_dpu_user_p) = { "oscclk", "dout_dpu" };
static const struct samsung_mux_clock dpu_mux_clks[] __initconst = {
MUX(CLK_MOUT_DPU_USER, "mout_dpu_user", mout_dpu_user_p,
PLL_CON0_MUX_CLKCMU_DPU_USER, 4, 1),
};
static const struct samsung_div_clock dpu_div_clks[] __initconst = {
DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_user",
CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3),
};
static const struct samsung_gate_clock dpu_gate_clks[] __initconst = {
/* TODO: Should be enabled in DSIM driver */
GATE(CLK_GOUT_DPU_CMU_DPU_PCLK, "gout_dpu_cmu_dpu_pclk",
"dout_dpu_busp",
CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_DPU_DECON0_ACLK, "gout_dpu_decon0_aclk", "mout_dpu_user",
CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0),
GATE(CLK_GOUT_DPU_DMA_ACLK, "gout_dpu_dma_aclk", "mout_dpu_user",
CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 21, 0, 0),
GATE(CLK_GOUT_DPU_DPP_ACLK, "gout_dpu_dpp_aclk", "mout_dpu_user",
CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 21, 0, 0),
GATE(CLK_GOUT_DPU_PPMU_ACLK, "gout_dpu_ppmu_aclk", "mout_dpu_user",
CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 21, 0, 0),
GATE(CLK_GOUT_DPU_PPMU_PCLK, "gout_dpu_ppmu_pclk", "dout_dpu_busp",
CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 21, 0, 0),
GATE(CLK_GOUT_DPU_SMMU_CLK, "gout_dpu_smmu_clk", "mout_dpu_user",
CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 21, 0, 0),
GATE(CLK_GOUT_DPU_SYSREG_PCLK, "gout_dpu_sysreg_pclk", "dout_dpu_busp",
CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 21, 0, 0),
};
static const struct samsung_cmu_info dpu_cmu_info __initconst = {
.mux_clks = dpu_mux_clks,
.nr_mux_clks = ARRAY_SIZE(dpu_mux_clks),
.div_clks = dpu_div_clks,
.nr_div_clks = ARRAY_SIZE(dpu_div_clks),
.gate_clks = dpu_gate_clks,
.nr_gate_clks = ARRAY_SIZE(dpu_gate_clks),
.nr_clk_ids = CLKS_NR_DPU,
.clk_regs = dpu_clk_regs,
.nr_clk_regs = ARRAY_SIZE(dpu_clk_regs),
.clk_name = "dout_dpu",
};
/* ---- platform_driver ----------------------------------------------------- */
static int __init exynos850_cmu_probe(struct platform_device *pdev)
{
const struct samsung_cmu_info *info;
struct device *dev = &pdev->dev;
info = of_device_get_match_data(dev);
exynos_arm64_register_cmu(dev, dev->of_node, info);
return 0;
}
static const struct of_device_id exynos850_cmu_of_match[] = {
{
.compatible = "samsung,exynos850-cmu-apm",
.data = &apm_cmu_info,
}, {
.compatible = "samsung,exynos850-cmu-aud",
.data = &aud_cmu_info,
}, {
.compatible = "samsung,exynos850-cmu-cmgp",
.data = &cmgp_cmu_info,
}, {
.compatible = "samsung,exynos850-cmu-g3d",
.data = &g3d_cmu_info,
}, {
.compatible = "samsung,exynos850-cmu-hsi",
.data = &hsi_cmu_info,
}, {
.compatible = "samsung,exynos850-cmu-is",
.data = &is_cmu_info,
}, {
.compatible = "samsung,exynos850-cmu-mfcmscl",
.data = &mfcmscl_cmu_info,
}, {
.compatible = "samsung,exynos850-cmu-core",
.data = &core_cmu_info,
}, {
.compatible = "samsung,exynos850-cmu-dpu",
.data = &dpu_cmu_info,
}, {
},
};
static struct platform_driver exynos850_cmu_driver __refdata = {
.driver = {
.name = "exynos850-cmu",
.of_match_table = exynos850_cmu_of_match,
.suppress_bind_attrs = true,
},
.probe = exynos850_cmu_probe,
};
static int __init exynos850_cmu_init(void)
{
return platform_driver_register(&exynos850_cmu_driver);
}
core_initcall(exynos850_cmu_init);
| linux-master | drivers/clk/samsung/clk-exynos850.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Copyright (c) 2013 Linaro Ltd.
* Author: Thomas Abraham <[email protected]>
*
* Common Clock Framework support for Exynos5250 SoC.
*/
#include <dt-bindings/clock/exynos5250.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "clk.h"
#include "clk-cpu.h"
#include "clk-exynos5-subcmu.h"
#define APLL_LOCK 0x0
#define APLL_CON0 0x100
#define SRC_CPU 0x200
#define DIV_CPU0 0x500
#define PWR_CTRL1 0x1020
#define PWR_CTRL2 0x1024
#define MPLL_LOCK 0x4000
#define MPLL_CON0 0x4100
#define SRC_CORE1 0x4204
#define GATE_IP_ACP 0x8800
#define GATE_IP_ISP0 0xc800
#define GATE_IP_ISP1 0xc804
#define CPLL_LOCK 0x10020
#define EPLL_LOCK 0x10030
#define VPLL_LOCK 0x10040
#define GPLL_LOCK 0x10050
#define CPLL_CON0 0x10120
#define EPLL_CON0 0x10130
#define VPLL_CON0 0x10140
#define GPLL_CON0 0x10150
#define SRC_TOP0 0x10210
#define SRC_TOP1 0x10214
#define SRC_TOP2 0x10218
#define SRC_TOP3 0x1021c
#define SRC_GSCL 0x10220
#define SRC_DISP1_0 0x1022c
#define SRC_MAU 0x10240
#define SRC_FSYS 0x10244
#define SRC_GEN 0x10248
#define SRC_PERIC0 0x10250
#define SRC_PERIC1 0x10254
#define SRC_MASK_GSCL 0x10320
#define SRC_MASK_DISP1_0 0x1032c
#define SRC_MASK_MAU 0x10334
#define SRC_MASK_FSYS 0x10340
#define SRC_MASK_GEN 0x10344
#define SRC_MASK_PERIC0 0x10350
#define SRC_MASK_PERIC1 0x10354
#define DIV_TOP0 0x10510
#define DIV_TOP1 0x10514
#define DIV_GSCL 0x10520
#define DIV_DISP1_0 0x1052c
#define DIV_GEN 0x1053c
#define DIV_MAU 0x10544
#define DIV_FSYS0 0x10548
#define DIV_FSYS1 0x1054c
#define DIV_FSYS2 0x10550
#define DIV_PERIC0 0x10558
#define DIV_PERIC1 0x1055c
#define DIV_PERIC2 0x10560
#define DIV_PERIC3 0x10564
#define DIV_PERIC4 0x10568
#define DIV_PERIC5 0x1056c
#define GATE_IP_GSCL 0x10920
#define GATE_IP_DISP1 0x10928
#define GATE_IP_MFC 0x1092c
#define GATE_IP_G3D 0x10930
#define GATE_IP_GEN 0x10934
#define GATE_IP_FSYS 0x10944
#define GATE_IP_PERIC 0x10950
#define GATE_IP_PERIS 0x10960
#define BPLL_LOCK 0x20010
#define BPLL_CON0 0x20110
#define SRC_CDREX 0x20200
#define PLL_DIV2_SEL 0x20a24
/*Below definitions are used for PWR_CTRL settings*/
#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
#define PWR_CTRL2_DIV2_UP_EN (1 << 25)
#define PWR_CTRL2_DIV1_UP_EN (1 << 24)
#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR (CLK_MOUT_VPLLSRC + 1)
/* list of PLLs to be registered */
enum exynos5250_plls {
apll, mpll, cpll, epll, vpll, gpll, bpll,
nr_plls /* number of PLLs */
};
static void __iomem *reg_base;
/*
* list of controller registers to be saved and restored during a
* suspend/resume cycle.
*/
static const unsigned long exynos5250_clk_regs[] __initconst = {
SRC_CPU,
DIV_CPU0,
PWR_CTRL1,
PWR_CTRL2,
SRC_CORE1,
SRC_TOP0,
SRC_TOP1,
SRC_TOP2,
SRC_TOP3,
SRC_GSCL,
SRC_DISP1_0,
SRC_MAU,
SRC_FSYS,
SRC_GEN,
SRC_PERIC0,
SRC_PERIC1,
SRC_MASK_GSCL,
SRC_MASK_DISP1_0,
SRC_MASK_MAU,
SRC_MASK_FSYS,
SRC_MASK_GEN,
SRC_MASK_PERIC0,
SRC_MASK_PERIC1,
DIV_TOP0,
DIV_TOP1,
DIV_GSCL,
DIV_DISP1_0,
DIV_GEN,
DIV_MAU,
DIV_FSYS0,
DIV_FSYS1,
DIV_FSYS2,
DIV_PERIC0,
DIV_PERIC1,
DIV_PERIC2,
DIV_PERIC3,
DIV_PERIC4,
DIV_PERIC5,
GATE_IP_GSCL,
GATE_IP_MFC,
GATE_IP_G3D,
GATE_IP_GEN,
GATE_IP_FSYS,
GATE_IP_PERIC,
GATE_IP_PERIS,
SRC_CDREX,
PLL_DIV2_SEL,
GATE_IP_DISP1,
GATE_IP_ACP,
GATE_IP_ISP0,
GATE_IP_ISP1,
};
/* list of all parent clock list */
PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", };
PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" };
PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
PNAME(mout_bpll_p) = { "fin_pll", "mout_bpll_fout" };
PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" };
PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
PNAME(mout_gpll_p) = { "fin_pll", "fout_gpll" };
PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" };
PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" };
PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" };
PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" };
PNAME(mout_aclk300_p) = { "mout_aclk300_disp1_mid",
"mout_aclk300_disp1_mid1" };
PNAME(mout_aclk400_p) = { "mout_aclk400_g3d_mid", "mout_gpll" };
PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };
PNAME(mout_aclk300_sub_p) = { "fin_pll", "div_aclk300_disp" };
PNAME(mout_aclk300_disp1_mid1_p) = { "mout_vpll", "mout_cpll" };
PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
PNAME(mout_aclk400_isp_sub_p) = { "fin_pll", "div_aclk400_isp" };
PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" };
PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" };
PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m",
"sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
"mout_mpll_user", "mout_epll", "mout_vpll",
"mout_cpll", "none", "none",
"none", "none", "none",
"none" };
PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
"sclk_uhostphy", "fin_pll",
"mout_mpll_user", "mout_epll", "mout_vpll",
"mout_cpll", "none", "none",
"none", "none", "none",
"none" };
PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
"sclk_uhostphy", "fin_pll",
"mout_mpll_user", "mout_epll", "mout_vpll",
"mout_cpll", "none", "none",
"none", "none", "none",
"none" };
PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
"sclk_uhostphy", "fin_pll",
"mout_mpll_user", "mout_epll", "mout_vpll",
"mout_cpll", "none", "none",
"none", "none", "none",
"none" };
PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
"spdif_extclk" };
/* fixed rate clocks generated outside the soc */
static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
};
/* fixed rate clocks generated inside the soc */
static const struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initconst = {
FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
FRATE(0, "sclk_hdmi27m", NULL, 0, 27000000),
FRATE(0, "sclk_dptxphy", NULL, 0, 24000000),
FRATE(0, "sclk_uhostphy", NULL, 0, 48000000),
};
static const struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initconst = {
FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
};
static const struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initconst = {
MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
};
static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {
/*
* NOTE: Following table is sorted by (clock domain, register address,
* bitfield shift) triplet in ascending order. When adding new entries,
* please make sure that the order is kept, to avoid merge conflicts
* and make further work with defined data easier.
*/
/*
* CMU_CPU
*/
MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
CLK_SET_RATE_PARENT, 0),
MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
/*
* CMU_CORE
*/
MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
/*
* CMU_TOP
*/
MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
MUX(0, "mout_aclk300_disp1_mid", mout_aclk200_p, SRC_TOP0, 14, 1),
MUX(0, "mout_aclk300", mout_aclk300_p, SRC_TOP0, 15, 1),
MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1),
MUX(0, "mout_aclk300_disp1_mid1", mout_aclk300_disp1_mid1_p, SRC_TOP1,
8, 1),
MUX(0, "mout_aclk400_isp", mout_aclk200_p, SRC_TOP1, 24, 1),
MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1),
MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1),
MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
MUX(CLK_MOUT_GPLL, "mout_gpll", mout_gpll_p, SRC_TOP2, 28, 1),
MUX(CLK_MOUT_ACLK200_DISP1_SUB, "mout_aclk200_disp1_sub",
mout_aclk200_sub_p, SRC_TOP3, 4, 1),
MUX(CLK_MOUT_ACLK300_DISP1_SUB, "mout_aclk300_disp1_sub",
mout_aclk300_sub_p, SRC_TOP3, 6, 1),
MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
MUX(0, "mout_aclk_266_isp_sub", mout_aclk266_sub_p, SRC_TOP3, 16, 1),
MUX(0, "mout_aclk_400_isp_sub", mout_aclk400_isp_sub_p,
SRC_TOP3, 20, 1),
MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1),
MUX(0, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
MUX(0, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
MUX(0, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
MUX(0, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
MUX(0, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
MUX(0, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
MUX(0, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
MUX(0, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
MUX(0, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
MUX(0, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
MUX(0, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
MUX(0, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
MUX(0, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
MUX(0, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
MUX(0, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
MUX(0, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
MUX(0, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
MUX(0, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
MUX(0, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
MUX(0, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
MUX(0, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
MUX(0, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
MUX(0, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
MUX(0, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
/*
* CMU_CDREX
*/
MUX(0, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
MUX(0, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
MUX(0, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
};
static const struct samsung_div_clock exynos5250_div_clks[] __initconst = {
/*
* NOTE: Following table is sorted by (clock domain, register address,
* bitfield shift) triplet in ascending order. When adding new entries,
* please make sure that the order is kept, to avoid merge conflicts
* and make further work with defined data easier.
*/
/*
* CMU_CPU
*/
DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
DIV(CLK_DIV_ARM2, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
/*
* CMU_TOP
*/
DIV(0, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3),
DIV(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3),
DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0,
24, 3),
DIV(0, "div_aclk300_disp", "mout_aclk300", DIV_TOP0, 28, 3),
DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1, 20, 3),
DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
DIV(0, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
DIV(0, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
DIV(0, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
DIV(0, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
DIV(0, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
DIV(0, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
DIV_F(0, "div_mipi1_pre", "div_mipi1",
DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
DIV(0, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
DIV(CLK_SCLK_PIXEL, "div_hdmi_pixel", "mout_vpll", DIV_DISP1_0, 28, 4),
DIV(0, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
DIV(0, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
DIV(CLK_DIV_PCM0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
DIV(0, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
DIV_F(0, "div_mmc_pre0", "div_mmc0",
DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
DIV_F(0, "div_mmc_pre1", "div_mmc1",
DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
DIV_F(0, "div_mmc_pre2", "div_mmc2",
DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
DIV_F(0, "div_mmc_pre3", "div_mmc3",
DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
DIV(0, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
DIV_F(0, "div_spi_pre0", "div_spi0",
DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
DIV(0, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
DIV_F(0, "div_spi_pre1", "div_spi1",
DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
DIV(0, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
DIV_F(0, "div_spi_pre2", "div_spi2",
DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
DIV(0, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
DIV(0, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
DIV(0, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
DIV(0, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
DIV(0, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
DIV(CLK_DIV_I2S1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
DIV(CLK_DIV_I2S2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
};
static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = {
/*
* NOTE: Following table is sorted by (clock domain, register address,
* bitfield shift) triplet in ascending order. When adding new entries,
* please make sure that the order is kept, to avoid merge conflicts
* and make further work with defined data easier.
*/
/*
* CMU_ACP
*/
GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0),
GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
/*
* CMU_TOP
*/
GATE(CLK_SCLK_CAM_BAYER, "sclk_cam_bayer", "div_cam_bayer",
SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0",
SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "div_gscl_wa",
SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "div_gscl_wb",
SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1",
SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi1",
SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_DP, "sclk_dp", "div_dp",
SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
SRC_MASK_DISP1_0, 20, 0, 0),
GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0",
SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3",
SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_USB3, "sclk_usb3", "div_usb3",
SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_PWM, "sclk_pwm", "div_pwm",
SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1",
SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2",
SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
SRC_MASK_PERIC1, 4, 0, 0),
GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0",
SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1",
SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2",
SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GSCL0, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 0, 0,
0),
GATE(CLK_GSCL1, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 1, 0,
0),
GATE(CLK_GSCL2, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 2, 0,
0),
GATE(CLK_GSCL3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0,
0),
GATE(CLK_CAMIF_TOP, "camif_top", "mout_aclk266_gscl_sub",
GATE_IP_GSCL, 4, 0, 0),
GATE(CLK_GSCL_WA, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
GATE(CLK_GSCL_WB, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "mout_aclk266_gscl_sub",
GATE_IP_GSCL, 7, 0, 0),
GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "mout_aclk266_gscl_sub",
GATE_IP_GSCL, 8, 0, 0),
GATE(CLK_SMMU_GSCL2, "smmu_gscl2", "mout_aclk266_gscl_sub",
GATE_IP_GSCL, 9, 0, 0),
GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub",
GATE_IP_GSCL, 10, 0, 0),
GATE(CLK_SMMU_FIMC_LITE0, "smmu_fimc_lite0", "mout_aclk266_gscl_sub",
GATE_IP_GSCL, 11, 0, 0),
GATE(CLK_SMMU_FIMC_LITE1, "smmu_fimc_lite1", "mout_aclk266_gscl_sub",
GATE_IP_GSCL, 12, 0, 0),
GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0),
GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0,
0),
GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0,
0),
GATE(CLK_G3D, "g3d", "div_aclk400_g3d", GATE_IP_G3D, 0,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0),
GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0),
GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0),
GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "div_aclk266", GATE_IP_GEN, 6, 0,
0),
GATE(CLK_SMMU_JPEG, "smmu_jpeg", "div_aclk166", GATE_IP_GEN, 7, 0, 0),
GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "div_aclk266", GATE_IP_GEN, 9, 0, 0),
GATE(CLK_PDMA0, "pdma0", "div_aclk200", GATE_IP_FSYS, 1, 0, 0),
GATE(CLK_PDMA1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0),
GATE(CLK_SATA, "sata", "div_aclk200", GATE_IP_FSYS, 6, 0, 0),
GATE(CLK_USBOTG, "usbotg", "div_aclk200", GATE_IP_FSYS, 7, 0, 0),
GATE(CLK_MIPI_HSI, "mipi_hsi", "div_aclk200", GATE_IP_FSYS, 8, 0, 0),
GATE(CLK_SDMMC0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0),
GATE(CLK_SDMMC1, "sdmmc1", "div_aclk200", GATE_IP_FSYS, 13, 0, 0),
GATE(CLK_SDMMC2, "sdmmc2", "div_aclk200", GATE_IP_FSYS, 14, 0, 0),
GATE(CLK_SDMMC3, "sdmmc3", "div_aclk200", GATE_IP_FSYS, 15, 0, 0),
GATE(CLK_SROMC, "sromc", "div_aclk200", GATE_IP_FSYS, 17, 0, 0),
GATE(CLK_USB2, "usb2", "div_aclk200", GATE_IP_FSYS, 18, 0, 0),
GATE(CLK_USB3, "usb3", "div_aclk200", GATE_IP_FSYS, 19, 0, 0),
GATE(CLK_SATA_PHYCTRL, "sata_phyctrl", "div_aclk200",
GATE_IP_FSYS, 24, 0, 0),
GATE(CLK_SATA_PHYI2C, "sata_phyi2c", "div_aclk200", GATE_IP_FSYS, 25, 0,
0),
GATE(CLK_UART0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0),
GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0),
GATE(CLK_UART2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0),
GATE(CLK_UART3, "uart3", "div_aclk66", GATE_IP_PERIC, 3, 0, 0),
GATE(CLK_UART4, "uart4", "div_aclk66", GATE_IP_PERIC, 4, 0, 0),
GATE(CLK_I2C0, "i2c0", "div_aclk66", GATE_IP_PERIC, 6, 0, 0),
GATE(CLK_I2C1, "i2c1", "div_aclk66", GATE_IP_PERIC, 7, 0, 0),
GATE(CLK_I2C2, "i2c2", "div_aclk66", GATE_IP_PERIC, 8, 0, 0),
GATE(CLK_I2C3, "i2c3", "div_aclk66", GATE_IP_PERIC, 9, 0, 0),
GATE(CLK_I2C4, "i2c4", "div_aclk66", GATE_IP_PERIC, 10, 0, 0),
GATE(CLK_I2C5, "i2c5", "div_aclk66", GATE_IP_PERIC, 11, 0, 0),
GATE(CLK_I2C6, "i2c6", "div_aclk66", GATE_IP_PERIC, 12, 0, 0),
GATE(CLK_I2C7, "i2c7", "div_aclk66", GATE_IP_PERIC, 13, 0, 0),
GATE(CLK_I2C_HDMI, "i2c_hdmi", "div_aclk66", GATE_IP_PERIC, 14, 0, 0),
GATE(CLK_ADC, "adc", "div_aclk66", GATE_IP_PERIC, 15, 0, 0),
GATE(CLK_SPI0, "spi0", "div_aclk66", GATE_IP_PERIC, 16, 0, 0),
GATE(CLK_SPI1, "spi1", "div_aclk66", GATE_IP_PERIC, 17, 0, 0),
GATE(CLK_SPI2, "spi2", "div_aclk66", GATE_IP_PERIC, 18, 0, 0),
GATE(CLK_I2S1, "i2s1", "div_aclk66", GATE_IP_PERIC, 20, 0, 0),
GATE(CLK_I2S2, "i2s2", "div_aclk66", GATE_IP_PERIC, 21, 0, 0),
GATE(CLK_PCM1, "pcm1", "div_aclk66", GATE_IP_PERIC, 22, 0, 0),
GATE(CLK_PCM2, "pcm2", "div_aclk66", GATE_IP_PERIC, 23, 0, 0),
GATE(CLK_PWM, "pwm", "div_aclk66", GATE_IP_PERIC, 24, 0, 0),
GATE(CLK_SPDIF, "spdif", "div_aclk66", GATE_IP_PERIC, 26, 0, 0),
GATE(CLK_AC97, "ac97", "div_aclk66", GATE_IP_PERIC, 27, 0, 0),
GATE(CLK_HSI2C0, "hsi2c0", "div_aclk66", GATE_IP_PERIC, 28, 0, 0),
GATE(CLK_HSI2C1, "hsi2c1", "div_aclk66", GATE_IP_PERIC, 29, 0, 0),
GATE(CLK_HSI2C2, "hsi2c2", "div_aclk66", GATE_IP_PERIC, 30, 0, 0),
GATE(CLK_HSI2C3, "hsi2c3", "div_aclk66", GATE_IP_PERIC, 31, 0, 0),
GATE(CLK_CHIPID, "chipid", "div_aclk66", GATE_IP_PERIS, 0, 0, 0),
GATE(CLK_SYSREG, "sysreg", "div_aclk66",
GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PMU, "pmu", "div_aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED,
0),
GATE(CLK_CMU_TOP, "cmu_top", "div_aclk66",
GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_CMU_CORE, "cmu_core", "div_aclk66",
GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_CMU_MEM, "cmu_mem", "div_aclk66",
GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_TZPC0, "tzpc0", "div_aclk66", GATE_IP_PERIS, 6, 0, 0),
GATE(CLK_TZPC1, "tzpc1", "div_aclk66", GATE_IP_PERIS, 7, 0, 0),
GATE(CLK_TZPC2, "tzpc2", "div_aclk66", GATE_IP_PERIS, 8, 0, 0),
GATE(CLK_TZPC3, "tzpc3", "div_aclk66", GATE_IP_PERIS, 9, 0, 0),
GATE(CLK_TZPC4, "tzpc4", "div_aclk66", GATE_IP_PERIS, 10, 0, 0),
GATE(CLK_TZPC5, "tzpc5", "div_aclk66", GATE_IP_PERIS, 11, 0, 0),
GATE(CLK_TZPC6, "tzpc6", "div_aclk66", GATE_IP_PERIS, 12, 0, 0),
GATE(CLK_TZPC7, "tzpc7", "div_aclk66", GATE_IP_PERIS, 13, 0, 0),
GATE(CLK_TZPC8, "tzpc8", "div_aclk66", GATE_IP_PERIS, 14, 0, 0),
GATE(CLK_TZPC9, "tzpc9", "div_aclk66", GATE_IP_PERIS, 15, 0, 0),
GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk66", GATE_IP_PERIS, 16, 0, 0),
GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0),
GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0),
GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
GATE(CLK_SMMU_FIMC_ISP, "smmu_fimc_isp", "mout_aclk_266_isp_sub",
GATE_IP_ISP0, 8, 0, 0),
GATE(CLK_SMMU_FIMC_DRC, "smmu_fimc_drc", "mout_aclk_266_isp_sub",
GATE_IP_ISP0, 9, 0, 0),
GATE(CLK_SMMU_FIMC_FD, "smmu_fimc_fd", "mout_aclk_266_isp_sub",
GATE_IP_ISP0, 10, 0, 0),
GATE(CLK_SMMU_FIMC_SCC, "smmu_fimc_scc", "mout_aclk_266_isp_sub",
GATE_IP_ISP0, 11, 0, 0),
GATE(CLK_SMMU_FIMC_SCP, "smmu_fimc_scp", "mout_aclk_266_isp_sub",
GATE_IP_ISP0, 12, 0, 0),
GATE(CLK_SMMU_FIMC_MCU, "smmu_fimc_mcu", "mout_aclk_400_isp_sub",
GATE_IP_ISP0, 13, 0, 0),
GATE(CLK_SMMU_FIMC_ODC, "smmu_fimc_odc", "mout_aclk_266_isp_sub",
GATE_IP_ISP1, 4, 0, 0),
GATE(CLK_SMMU_FIMC_DIS0, "smmu_fimc_dis0", "mout_aclk_266_isp_sub",
GATE_IP_ISP1, 5, 0, 0),
GATE(CLK_SMMU_FIMC_DIS1, "smmu_fimc_dis1", "mout_aclk_266_isp_sub",
GATE_IP_ISP1, 6, 0, 0),
GATE(CLK_SMMU_FIMC_3DNR, "smmu_fimc_3dnr", "mout_aclk_266_isp_sub",
GATE_IP_ISP1, 7, 0, 0),
};
static const struct samsung_gate_clock exynos5250_disp_gate_clks[] __initconst = {
GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0,
0),
GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0,
0),
GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0,
0),
GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0),
GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0,
0),
GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0,
0),
GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
GATE_IP_DISP1, 9, 0, 0),
GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",
GATE_IP_DISP1, 8, 0, 0),
};
static struct exynos5_subcmu_reg_dump exynos5250_disp_suspend_regs[] = {
{ GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */
{ SRC_TOP3, 0, BIT(4) }, /* MUX mout_aclk200_disp1_sub */
{ SRC_TOP3, 0, BIT(6) }, /* MUX mout_aclk300_disp1_sub */
};
static const struct exynos5_subcmu_info exynos5250_disp_subcmu = {
.gate_clks = exynos5250_disp_gate_clks,
.nr_gate_clks = ARRAY_SIZE(exynos5250_disp_gate_clks),
.suspend_regs = exynos5250_disp_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(exynos5250_disp_suspend_regs),
.pd_name = "DISP1",
};
static const struct exynos5_subcmu_info *exynos5250_subcmus[] = {
&exynos5250_disp_subcmu,
};
static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = {
/* sorted in descending order */
/* PLL_36XX_RATE(rate, m, p, s, k) */
PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
/* Not in UM, but need for eDP on snow */
PLL_36XX_RATE(24 * MHZ, 70500000, 94, 2, 4, 0),
{ },
};
static const struct samsung_pll_rate_table epll_24mhz_tbl[] __initconst = {
/* sorted in descending order */
/* PLL_36XX_RATE(rate, m, p, s, k) */
PLL_36XX_RATE(24 * MHZ, 192000000, 64, 2, 2, 0),
PLL_36XX_RATE(24 * MHZ, 180633605, 90, 3, 2, 20762),
PLL_36XX_RATE(24 * MHZ, 180000000, 90, 3, 2, 0),
PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923),
PLL_36XX_RATE(24 * MHZ, 67737602, 90, 2, 4, 20762),
PLL_36XX_RATE(24 * MHZ, 49152000, 98, 3, 4, 19923),
PLL_36XX_RATE(24 * MHZ, 45158401, 90, 3, 4, 20762),
PLL_36XX_RATE(24 * MHZ, 32768001, 131, 3, 5, 4719),
{ },
};
static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = {
/* sorted in descending order */
/* PLL_35XX_RATE(fin, rate, m, p, s) */
PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1),
PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1),
PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1),
PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2),
PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2),
};
static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
APLL_CON0, NULL),
[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
MPLL_CON0, NULL),
[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
BPLL_CON0, NULL),
[gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
GPLL_CON0, NULL),
[cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
CPLL_CON0, NULL),
[epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
EPLL_CON0, NULL),
[vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
VPLL_LOCK, VPLL_CON0, NULL),
};
#define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud) \
((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
((periph) << 12) | ((acp) << 8) | ((cpud) << 4)))
#define E5250_CPU_DIV1(hpm, copy) \
(((hpm) << 4) | (copy))
static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = {
{ 1700000, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
{ 1600000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
{ 1500000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
{ 1400000, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
{ 1300000, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
{ 1200000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
{ 1100000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
{ 1000000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
{ 900000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
{ 800000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
{ 700000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
{ 600000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
{ 500000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
{ 400000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
{ 300000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
{ 200000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
{ 0 },
};
static const struct samsung_cpu_clock exynos5250_cpu_clks[] __initconst = {
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL, CLK_CPU_HAS_DIV1, 0x200,
exynos5250_armclk_d),
};
static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
{ },
};
/* register exynox5250 clocks */
static void __init exynos5250_clk_init(struct device_node *np)
{
struct samsung_clk_provider *ctx;
unsigned int tmp;
struct clk_hw **hws;
if (np) {
reg_base = of_iomap(np, 0);
if (!reg_base)
panic("%s: failed to map registers\n", __func__);
} else {
panic("%s: unable to determine soc\n", __func__);
}
ctx = samsung_clk_init(NULL, reg_base, CLKS_NR);
hws = ctx->clk_data.hws;
samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
ext_clk_match);
samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks,
ARRAY_SIZE(exynos5250_pll_pmux_clks));
if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) {
exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
exynos5250_plls[apll].rate_table = apll_24mhz_tbl;
}
if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24 * MHZ)
exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
samsung_clk_register_pll(ctx, exynos5250_plls,
ARRAY_SIZE(exynos5250_plls));
samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks,
ARRAY_SIZE(exynos5250_fixed_rate_clks));
samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks,
ARRAY_SIZE(exynos5250_fixed_factor_clks));
samsung_clk_register_mux(ctx, exynos5250_mux_clks,
ARRAY_SIZE(exynos5250_mux_clks));
samsung_clk_register_div(ctx, exynos5250_div_clks,
ARRAY_SIZE(exynos5250_div_clks));
samsung_clk_register_gate(ctx, exynos5250_gate_clks,
ARRAY_SIZE(exynos5250_gate_clks));
samsung_clk_register_cpu(ctx, exynos5250_cpu_clks,
ARRAY_SIZE(exynos5250_cpu_clks));
/*
* Enable arm clock down (in idle) and set arm divider
* ratios in WFI/WFE state.
*/
tmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO |
PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
__raw_writel(tmp, reg_base + PWR_CTRL1);
/*
* Enable arm clock up (on exiting idle). Set arm divider
* ratios when not in idle along with the standby duration
* ratios.
*/
tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN |
PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL |
PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
__raw_writel(tmp, reg_base + PWR_CTRL2);
samsung_clk_sleep_init(reg_base, exynos5250_clk_regs,
ARRAY_SIZE(exynos5250_clk_regs));
exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5250_subcmus),
exynos5250_subcmus);
samsung_clk_of_add_provider(np, ctx);
pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
clk_hw_get_rate(hws[CLK_DIV_ARM2]));
}
CLK_OF_DECLARE_DRIVER(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
| linux-master | drivers/clk/samsung/clk-exynos5250.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Author: Tomasz Figa <[email protected]>
*
* Clock driver for Exynos clock output
*/
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#define EXYNOS_CLKOUT_NR_CLKS 1
#define EXYNOS_CLKOUT_PARENTS 32
#define EXYNOS_PMU_DEBUG_REG 0xa00
#define EXYNOS_CLKOUT_DISABLE_SHIFT 0
#define EXYNOS_CLKOUT_MUX_SHIFT 8
#define EXYNOS4_CLKOUT_MUX_MASK 0xf
#define EXYNOS5_CLKOUT_MUX_MASK 0x1f
struct exynos_clkout {
struct clk_gate gate;
struct clk_mux mux;
spinlock_t slock;
void __iomem *reg;
struct device_node *np;
u32 pmu_debug_save;
struct clk_hw_onecell_data data;
};
struct exynos_clkout_variant {
u32 mux_mask;
};
static const struct exynos_clkout_variant exynos_clkout_exynos4 = {
.mux_mask = EXYNOS4_CLKOUT_MUX_MASK,
};
static const struct exynos_clkout_variant exynos_clkout_exynos5 = {
.mux_mask = EXYNOS5_CLKOUT_MUX_MASK,
};
static const struct of_device_id exynos_clkout_ids[] = {
{
.compatible = "samsung,exynos3250-pmu",
.data = &exynos_clkout_exynos4,
}, {
.compatible = "samsung,exynos4210-pmu",
.data = &exynos_clkout_exynos4,
}, {
.compatible = "samsung,exynos4212-pmu",
.data = &exynos_clkout_exynos4,
}, {
.compatible = "samsung,exynos4412-pmu",
.data = &exynos_clkout_exynos4,
}, {
.compatible = "samsung,exynos5250-pmu",
.data = &exynos_clkout_exynos5,
}, {
.compatible = "samsung,exynos5410-pmu",
.data = &exynos_clkout_exynos5,
}, {
.compatible = "samsung,exynos5420-pmu",
.data = &exynos_clkout_exynos5,
}, {
.compatible = "samsung,exynos5433-pmu",
.data = &exynos_clkout_exynos5,
}, { }
};
MODULE_DEVICE_TABLE(of, exynos_clkout_ids);
/*
* Device will be instantiated as child of PMU device without its own
* device node. Therefore match compatibles against parent.
*/
static int exynos_clkout_match_parent_dev(struct device *dev, u32 *mux_mask)
{
const struct exynos_clkout_variant *variant;
const struct of_device_id *match;
if (!dev->parent) {
dev_err(dev, "not instantiated from MFD\n");
return -EINVAL;
}
match = of_match_device(exynos_clkout_ids, dev->parent);
if (!match) {
dev_err(dev, "cannot match parent device\n");
return -EINVAL;
}
variant = match->data;
*mux_mask = variant->mux_mask;
return 0;
}
static int exynos_clkout_probe(struct platform_device *pdev)
{
const char *parent_names[EXYNOS_CLKOUT_PARENTS];
struct clk *parents[EXYNOS_CLKOUT_PARENTS];
struct exynos_clkout *clkout;
int parent_count, ret, i;
u32 mux_mask;
clkout = devm_kzalloc(&pdev->dev,
struct_size(clkout, data.hws, EXYNOS_CLKOUT_NR_CLKS),
GFP_KERNEL);
if (!clkout)
return -ENOMEM;
ret = exynos_clkout_match_parent_dev(&pdev->dev, &mux_mask);
if (ret)
return ret;
clkout->np = pdev->dev.of_node;
if (!clkout->np) {
/*
* pdev->dev.parent was checked by exynos_clkout_match_parent_dev()
* so it is not NULL.
*/
clkout->np = pdev->dev.parent->of_node;
}
platform_set_drvdata(pdev, clkout);
spin_lock_init(&clkout->slock);
parent_count = 0;
for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i) {
char name[] = "clkoutXX";
snprintf(name, sizeof(name), "clkout%d", i);
parents[i] = of_clk_get_by_name(clkout->np, name);
if (IS_ERR(parents[i])) {
parent_names[i] = "none";
continue;
}
parent_names[i] = __clk_get_name(parents[i]);
parent_count = i + 1;
}
if (!parent_count)
return -EINVAL;
clkout->reg = of_iomap(clkout->np, 0);
if (!clkout->reg) {
ret = -ENODEV;
goto clks_put;
}
clkout->gate.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
clkout->gate.bit_idx = EXYNOS_CLKOUT_DISABLE_SHIFT;
clkout->gate.flags = CLK_GATE_SET_TO_DISABLE;
clkout->gate.lock = &clkout->slock;
clkout->mux.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
clkout->mux.mask = mux_mask;
clkout->mux.shift = EXYNOS_CLKOUT_MUX_SHIFT;
clkout->mux.lock = &clkout->slock;
clkout->data.hws[0] = clk_hw_register_composite(NULL, "clkout",
parent_names, parent_count, &clkout->mux.hw,
&clk_mux_ops, NULL, NULL, &clkout->gate.hw,
&clk_gate_ops, CLK_SET_RATE_PARENT
| CLK_SET_RATE_NO_REPARENT);
if (IS_ERR(clkout->data.hws[0])) {
ret = PTR_ERR(clkout->data.hws[0]);
goto err_unmap;
}
clkout->data.num = EXYNOS_CLKOUT_NR_CLKS;
ret = of_clk_add_hw_provider(clkout->np, of_clk_hw_onecell_get, &clkout->data);
if (ret)
goto err_clk_unreg;
return 0;
err_clk_unreg:
clk_hw_unregister(clkout->data.hws[0]);
err_unmap:
iounmap(clkout->reg);
clks_put:
for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i)
if (!IS_ERR(parents[i]))
clk_put(parents[i]);
dev_err(&pdev->dev, "failed to register clkout clock\n");
return ret;
}
static void exynos_clkout_remove(struct platform_device *pdev)
{
struct exynos_clkout *clkout = platform_get_drvdata(pdev);
of_clk_del_provider(clkout->np);
clk_hw_unregister(clkout->data.hws[0]);
iounmap(clkout->reg);
}
static int __maybe_unused exynos_clkout_suspend(struct device *dev)
{
struct exynos_clkout *clkout = dev_get_drvdata(dev);
clkout->pmu_debug_save = readl(clkout->reg + EXYNOS_PMU_DEBUG_REG);
return 0;
}
static int __maybe_unused exynos_clkout_resume(struct device *dev)
{
struct exynos_clkout *clkout = dev_get_drvdata(dev);
writel(clkout->pmu_debug_save, clkout->reg + EXYNOS_PMU_DEBUG_REG);
return 0;
}
static SIMPLE_DEV_PM_OPS(exynos_clkout_pm_ops, exynos_clkout_suspend,
exynos_clkout_resume);
static struct platform_driver exynos_clkout_driver = {
.driver = {
.name = "exynos-clkout",
.of_match_table = exynos_clkout_ids,
.pm = &exynos_clkout_pm_ops,
},
.probe = exynos_clkout_probe,
.remove_new = exynos_clkout_remove,
};
module_platform_driver(exynos_clkout_driver);
MODULE_AUTHOR("Krzysztof Kozlowski <[email protected]>");
MODULE_AUTHOR("Tomasz Figa <[email protected]>");
MODULE_DESCRIPTION("Samsung Exynos clock output driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/samsung/clk-exynos-clkout.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 Samsung Electronics Co., Ltd.
* Author: Marek Szyprowski <[email protected]>
*
* Common Clock Framework support for Exynos4412 ISP module.
*/
#include <dt-bindings/clock/exynos4.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include "clk.h"
/* Exynos4x12 specific registers, which belong to ISP power domain */
#define E4X12_DIV_ISP0 0x0300
#define E4X12_DIV_ISP1 0x0304
#define E4X12_GATE_ISP0 0x0800
#define E4X12_GATE_ISP1 0x0804
/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR_ISP (CLK_ISP_DIV_MCUISP1 + 1)
/*
* Support for CMU save/restore across system suspends
*/
static struct samsung_clk_reg_dump *exynos4x12_save_isp;
static const unsigned long exynos4x12_clk_isp_save[] __initconst = {
E4X12_DIV_ISP0,
E4X12_DIV_ISP1,
E4X12_GATE_ISP0,
E4X12_GATE_ISP1,
};
static struct samsung_div_clock exynos4x12_isp_div_clks[] = {
DIV(CLK_ISP_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3),
DIV(CLK_ISP_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3),
DIV(CLK_ISP_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp",
E4X12_DIV_ISP1, 4, 3),
DIV(CLK_ISP_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0",
E4X12_DIV_ISP1, 8, 3),
DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
};
static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = {
GATE(CLK_ISP_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, 0, 0),
GATE(CLK_ISP_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, 0, 0),
GATE(CLK_ISP_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, 0, 0),
GATE(CLK_ISP_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 0, 0),
GATE(CLK_ISP_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 0, 0),
GATE(CLK_ISP_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 0, 0),
GATE(CLK_ISP_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, 0, 0),
GATE(CLK_ISP_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, 0, 0),
GATE(CLK_ISP_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, 0, 0),
GATE(CLK_ISP_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, 0, 0),
GATE(CLK_ISP_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
0, 0),
GATE(CLK_ISP_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
0, 0),
GATE(CLK_ISP_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
0, 0),
GATE(CLK_ISP_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
0, 0),
GATE(CLK_ISP_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
0, 0),
GATE(CLK_ISP_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
0, 0),
GATE(CLK_ISP_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
0, 0),
GATE(CLK_ISP_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
0, 0),
GATE(CLK_ISP_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
0, 0),
GATE(CLK_ISP_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, 0, 0),
GATE(CLK_ISP_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, 0, 0),
GATE(CLK_ISP_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
0, 0),
GATE(CLK_ISP_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
0, 0),
GATE(CLK_ISP_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
0, 0),
GATE(CLK_ISP_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
0, 0),
GATE(CLK_ISP_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
0, 0),
};
static int __maybe_unused exynos4x12_isp_clk_suspend(struct device *dev)
{
struct samsung_clk_provider *ctx = dev_get_drvdata(dev);
samsung_clk_save(ctx->reg_base, exynos4x12_save_isp,
ARRAY_SIZE(exynos4x12_clk_isp_save));
return 0;
}
static int __maybe_unused exynos4x12_isp_clk_resume(struct device *dev)
{
struct samsung_clk_provider *ctx = dev_get_drvdata(dev);
samsung_clk_restore(ctx->reg_base, exynos4x12_save_isp,
ARRAY_SIZE(exynos4x12_clk_isp_save));
return 0;
}
static int __init exynos4x12_isp_clk_probe(struct platform_device *pdev)
{
struct samsung_clk_provider *ctx;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
void __iomem *reg_base;
reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg_base))
return PTR_ERR(reg_base);
exynos4x12_save_isp = samsung_clk_alloc_reg_dump(exynos4x12_clk_isp_save,
ARRAY_SIZE(exynos4x12_clk_isp_save));
if (!exynos4x12_save_isp)
return -ENOMEM;
ctx = samsung_clk_init(dev, reg_base, CLKS_NR_ISP);
platform_set_drvdata(pdev, ctx);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
samsung_clk_register_div(ctx, exynos4x12_isp_div_clks,
ARRAY_SIZE(exynos4x12_isp_div_clks));
samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks,
ARRAY_SIZE(exynos4x12_isp_gate_clks));
samsung_clk_of_add_provider(np, ctx);
pm_runtime_put(dev);
return 0;
}
static const struct of_device_id exynos4x12_isp_clk_of_match[] = {
{ .compatible = "samsung,exynos4412-isp-clock", },
{ },
};
static const struct dev_pm_ops exynos4x12_isp_pm_ops = {
SET_RUNTIME_PM_OPS(exynos4x12_isp_clk_suspend,
exynos4x12_isp_clk_resume, NULL)
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver exynos4x12_isp_clk_driver __refdata = {
.driver = {
.name = "exynos4x12-isp-clk",
.of_match_table = exynos4x12_isp_clk_of_match,
.suppress_bind_attrs = true,
.pm = &exynos4x12_isp_pm_ops,
},
.probe = exynos4x12_isp_clk_probe,
};
static int __init exynos4x12_isp_clk_init(void)
{
return platform_driver_register(&exynos4x12_isp_clk_driver);
}
core_initcall(exynos4x12_isp_clk_init);
| linux-master | drivers/clk/samsung/clk-exynos4412-isp.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Padmavathi Venna <[email protected]>
*
* Common Clock Framework support for Audio Subsystem Clock Controller.
*/
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <dt-bindings/clock/exynos-audss-clk.h>
static DEFINE_SPINLOCK(lock);
static void __iomem *reg_base;
static struct clk_hw_onecell_data *clk_data;
/*
* On Exynos5420 this will be a clock which has to be enabled before any
* access to audss registers. Typically a child of EPLL.
*
* On other platforms this will be -ENODEV.
*/
static struct clk *epll;
#define ASS_CLK_SRC 0x0
#define ASS_CLK_DIV 0x4
#define ASS_CLK_GATE 0x8
static unsigned long reg_save[][2] = {
{ ASS_CLK_SRC, 0 },
{ ASS_CLK_DIV, 0 },
{ ASS_CLK_GATE, 0 },
};
static int __maybe_unused exynos_audss_clk_suspend(struct device *dev)
{
int i;
for (i = 0; i < ARRAY_SIZE(reg_save); i++)
reg_save[i][1] = readl(reg_base + reg_save[i][0]);
return 0;
}
static int __maybe_unused exynos_audss_clk_resume(struct device *dev)
{
int i;
for (i = 0; i < ARRAY_SIZE(reg_save); i++)
writel(reg_save[i][1], reg_base + reg_save[i][0]);
return 0;
}
struct exynos_audss_clk_drvdata {
unsigned int has_adma_clk:1;
unsigned int has_mst_clk:1;
unsigned int enable_epll:1;
unsigned int num_clks;
};
static const struct exynos_audss_clk_drvdata exynos4210_drvdata = {
.num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
.enable_epll = 1,
};
static const struct exynos_audss_clk_drvdata exynos5410_drvdata = {
.num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
.has_mst_clk = 1,
};
static const struct exynos_audss_clk_drvdata exynos5420_drvdata = {
.num_clks = EXYNOS_AUDSS_MAX_CLKS,
.has_adma_clk = 1,
.enable_epll = 1,
};
static const struct of_device_id exynos_audss_clk_of_match[] = {
{
.compatible = "samsung,exynos4210-audss-clock",
.data = &exynos4210_drvdata,
}, {
.compatible = "samsung,exynos5250-audss-clock",
.data = &exynos4210_drvdata,
}, {
.compatible = "samsung,exynos5410-audss-clock",
.data = &exynos5410_drvdata,
}, {
.compatible = "samsung,exynos5420-audss-clock",
.data = &exynos5420_drvdata,
},
{ },
};
MODULE_DEVICE_TABLE(of, exynos_audss_clk_of_match);
static void exynos_audss_clk_teardown(void)
{
int i;
for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
if (!IS_ERR(clk_data->hws[i]))
clk_hw_unregister_mux(clk_data->hws[i]);
}
for (; i < EXYNOS_SRP_CLK; i++) {
if (!IS_ERR(clk_data->hws[i]))
clk_hw_unregister_divider(clk_data->hws[i]);
}
for (; i < clk_data->num; i++) {
if (!IS_ERR(clk_data->hws[i]))
clk_hw_unregister_gate(clk_data->hws[i]);
}
}
/* register exynos_audss clocks */
static int exynos_audss_clk_probe(struct platform_device *pdev)
{
const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
const char *sclk_pcm_p = "sclk_pcm0";
struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
const struct exynos_audss_clk_drvdata *variant;
struct clk_hw **clk_table;
struct device *dev = &pdev->dev;
int i, ret = 0;
variant = of_device_get_match_data(&pdev->dev);
if (!variant)
return -EINVAL;
reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg_base))
return PTR_ERR(reg_base);
epll = ERR_PTR(-ENODEV);
clk_data = devm_kzalloc(dev,
struct_size(clk_data, hws,
EXYNOS_AUDSS_MAX_CLKS),
GFP_KERNEL);
if (!clk_data)
return -ENOMEM;
clk_data->num = variant->num_clks;
clk_table = clk_data->hws;
pll_ref = devm_clk_get(dev, "pll_ref");
pll_in = devm_clk_get(dev, "pll_in");
if (!IS_ERR(pll_ref))
mout_audss_p[0] = __clk_get_name(pll_ref);
if (!IS_ERR(pll_in)) {
mout_audss_p[1] = __clk_get_name(pll_in);
if (variant->enable_epll) {
epll = pll_in;
ret = clk_prepare_enable(epll);
if (ret) {
dev_err(dev,
"failed to prepare the epll clock\n");
return ret;
}
}
}
/*
* Enable runtime PM here to allow the clock core using runtime PM
* for the registered clocks. Additionally, we increase the runtime
* PM usage count before registering the clocks, to prevent the
* clock core from runtime suspending the device.
*/
pm_runtime_get_noresume(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(dev, "mout_audss",
mout_audss_p, ARRAY_SIZE(mout_audss_p),
CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
cdclk = devm_clk_get(dev, "cdclk");
sclk_audio = devm_clk_get(dev, "sclk_audio");
if (!IS_ERR(cdclk))
mout_i2s_p[1] = __clk_get_name(cdclk);
if (!IS_ERR(sclk_audio))
mout_i2s_p[2] = __clk_get_name(sclk_audio);
clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(dev, "mout_i2s",
mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
CLK_SET_RATE_NO_REPARENT,
reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp",
"mout_audss", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev,
"dout_aud_bus", "dout_srp", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s",
"mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
&lock);
clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk",
"dout_srp", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 0, 0, &lock);
clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus",
"dout_aud_bus", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 2, 0, &lock);
clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s",
"dout_i2s", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 3, 0, &lock);
clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(dev, "pcm_bus",
"sclk_pcm", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 4, 0, &lock);
sclk_pcm_in = devm_clk_get(dev, "sclk_pcm_in");
if (!IS_ERR(sclk_pcm_in))
sclk_pcm_p = __clk_get_name(sclk_pcm_in);
clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(dev, "sclk_pcm",
sclk_pcm_p, CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 5, 0, &lock);
if (variant->has_adma_clk) {
clk_table[EXYNOS_ADMA] = clk_hw_register_gate(dev, "adma",
"dout_srp", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 9, 0, &lock);
}
for (i = 0; i < clk_data->num; i++) {
if (IS_ERR(clk_table[i])) {
dev_err(dev, "failed to register clock %d\n", i);
ret = PTR_ERR(clk_table[i]);
goto unregister;
}
}
ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
clk_data);
if (ret) {
dev_err(dev, "failed to add clock provider\n");
goto unregister;
}
pm_runtime_put_sync(dev);
return 0;
unregister:
exynos_audss_clk_teardown();
pm_runtime_put_sync(dev);
pm_runtime_disable(dev);
if (!IS_ERR(epll))
clk_disable_unprepare(epll);
return ret;
}
static void exynos_audss_clk_remove(struct platform_device *pdev)
{
of_clk_del_provider(pdev->dev.of_node);
exynos_audss_clk_teardown();
pm_runtime_disable(&pdev->dev);
if (!IS_ERR(epll))
clk_disable_unprepare(epll);
}
static const struct dev_pm_ops exynos_audss_clk_pm_ops = {
SET_RUNTIME_PM_OPS(exynos_audss_clk_suspend, exynos_audss_clk_resume,
NULL)
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver exynos_audss_clk_driver = {
.driver = {
.name = "exynos-audss-clk",
.of_match_table = exynos_audss_clk_of_match,
.pm = &exynos_audss_clk_pm_ops,
},
.probe = exynos_audss_clk_probe,
.remove_new = exynos_audss_clk_remove,
};
module_platform_driver(exynos_audss_clk_driver);
MODULE_AUTHOR("Padmavathi Venna <[email protected]>");
MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:exynos-audss-clk");
| linux-master | drivers/clk/samsung/clk-exynos-audss.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Copyright (c) 2013 Linaro Ltd.
* Author: Thomas Abraham <[email protected]>
*
* Common Clock Framework support for all Exynos4 SoCs.
*/
#include <dt-bindings/clock/exynos4.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "clk.h"
#include "clk-cpu.h"
/* Exynos4 clock controller register offsets */
#define SRC_LEFTBUS 0x4200
#define DIV_LEFTBUS 0x4500
#define GATE_IP_LEFTBUS 0x4800
#define E4X12_GATE_IP_IMAGE 0x4930
#define CLKOUT_CMU_LEFTBUS 0x4a00
#define SRC_RIGHTBUS 0x8200
#define DIV_RIGHTBUS 0x8500
#define GATE_IP_RIGHTBUS 0x8800
#define E4X12_GATE_IP_PERIR 0x8960
#define CLKOUT_CMU_RIGHTBUS 0x8a00
#define EPLL_LOCK 0xc010
#define VPLL_LOCK 0xc020
#define EPLL_CON0 0xc110
#define EPLL_CON1 0xc114
#define EPLL_CON2 0xc118
#define VPLL_CON0 0xc120
#define VPLL_CON1 0xc124
#define VPLL_CON2 0xc128
#define SRC_TOP0 0xc210
#define SRC_TOP1 0xc214
#define SRC_CAM 0xc220
#define SRC_TV 0xc224
#define SRC_MFC 0xc228
#define SRC_G3D 0xc22c
#define E4210_SRC_IMAGE 0xc230
#define SRC_LCD0 0xc234
#define E4210_SRC_LCD1 0xc238
#define E4X12_SRC_ISP 0xc238
#define SRC_MAUDIO 0xc23c
#define SRC_FSYS 0xc240
#define SRC_PERIL0 0xc250
#define SRC_PERIL1 0xc254
#define E4X12_SRC_CAM1 0xc258
#define SRC_MASK_TOP 0xc310
#define SRC_MASK_CAM 0xc320
#define SRC_MASK_TV 0xc324
#define SRC_MASK_LCD0 0xc334
#define E4210_SRC_MASK_LCD1 0xc338
#define E4X12_SRC_MASK_ISP 0xc338
#define SRC_MASK_MAUDIO 0xc33c
#define SRC_MASK_FSYS 0xc340
#define SRC_MASK_PERIL0 0xc350
#define SRC_MASK_PERIL1 0xc354
#define DIV_TOP 0xc510
#define DIV_CAM 0xc520
#define DIV_TV 0xc524
#define DIV_MFC 0xc528
#define DIV_G3D 0xc52c
#define DIV_IMAGE 0xc530
#define DIV_LCD0 0xc534
#define E4210_DIV_LCD1 0xc538
#define E4X12_DIV_ISP 0xc538
#define DIV_MAUDIO 0xc53c
#define DIV_FSYS0 0xc540
#define DIV_FSYS1 0xc544
#define DIV_FSYS2 0xc548
#define DIV_FSYS3 0xc54c
#define DIV_PERIL0 0xc550
#define DIV_PERIL1 0xc554
#define DIV_PERIL2 0xc558
#define DIV_PERIL3 0xc55c
#define DIV_PERIL4 0xc560
#define DIV_PERIL5 0xc564
#define E4X12_DIV_CAM1 0xc568
#define E4X12_GATE_BUS_FSYS1 0xc744
#define GATE_SCLK_CAM 0xc820
#define GATE_IP_CAM 0xc920
#define GATE_IP_TV 0xc924
#define GATE_IP_MFC 0xc928
#define GATE_IP_G3D 0xc92c
#define E4210_GATE_IP_IMAGE 0xc930
#define GATE_IP_LCD0 0xc934
#define E4210_GATE_IP_LCD1 0xc938
#define E4X12_GATE_IP_ISP 0xc938
#define E4X12_GATE_IP_MAUDIO 0xc93c
#define GATE_IP_FSYS 0xc940
#define GATE_IP_GPS 0xc94c
#define GATE_IP_PERIL 0xc950
#define E4210_GATE_IP_PERIR 0xc960
#define GATE_BLOCK 0xc970
#define CLKOUT_CMU_TOP 0xca00
#define E4X12_MPLL_LOCK 0x10008
#define E4X12_MPLL_CON0 0x10108
#define SRC_DMC 0x10200
#define SRC_MASK_DMC 0x10300
#define DIV_DMC0 0x10500
#define DIV_DMC1 0x10504
#define GATE_IP_DMC 0x10900
#define CLKOUT_CMU_DMC 0x10a00
#define APLL_LOCK 0x14000
#define E4210_MPLL_LOCK 0x14008
#define APLL_CON0 0x14100
#define E4210_MPLL_CON0 0x14108
#define SRC_CPU 0x14200
#define DIV_CPU0 0x14500
#define DIV_CPU1 0x14504
#define GATE_SCLK_CPU 0x14800
#define GATE_IP_CPU 0x14900
#define CLKOUT_CMU_CPU 0x14a00
#define PWR_CTRL1 0x15020
#define E4X12_PWR_CTRL2 0x15024
/* Below definitions are used for PWR_CTRL settings */
#define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
#define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
#define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
#define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
#define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
#define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR (CLK_DIV_CORE2 + 1)
/* the exynos4 soc type */
enum exynos4_soc {
EXYNOS4210,
EXYNOS4212,
EXYNOS4412,
};
/* list of PLLs to be registered */
enum exynos4_plls {
apll, mpll, epll, vpll,
nr_plls /* number of PLLs */
};
static void __iomem *reg_base;
static enum exynos4_soc exynos4_soc;
/*
* list of controller registers to be saved and restored during a
* suspend/resume cycle.
*/
static const unsigned long exynos4210_clk_save[] __initconst = {
E4210_SRC_IMAGE,
E4210_SRC_LCD1,
E4210_SRC_MASK_LCD1,
E4210_DIV_LCD1,
E4210_GATE_IP_IMAGE,
E4210_GATE_IP_LCD1,
E4210_GATE_IP_PERIR,
E4210_MPLL_CON0,
PWR_CTRL1,
};
static const unsigned long exynos4x12_clk_save[] __initconst = {
E4X12_GATE_IP_IMAGE,
E4X12_GATE_IP_PERIR,
E4X12_SRC_CAM1,
E4X12_DIV_ISP,
E4X12_DIV_CAM1,
E4X12_MPLL_CON0,
PWR_CTRL1,
E4X12_PWR_CTRL2,
};
static const unsigned long exynos4_clk_regs[] __initconst = {
EPLL_LOCK,
VPLL_LOCK,
EPLL_CON0,
EPLL_CON1,
EPLL_CON2,
VPLL_CON0,
VPLL_CON1,
VPLL_CON2,
SRC_LEFTBUS,
DIV_LEFTBUS,
GATE_IP_LEFTBUS,
SRC_RIGHTBUS,
DIV_RIGHTBUS,
GATE_IP_RIGHTBUS,
SRC_TOP0,
SRC_TOP1,
SRC_CAM,
SRC_TV,
SRC_MFC,
SRC_G3D,
SRC_LCD0,
SRC_MAUDIO,
SRC_FSYS,
SRC_PERIL0,
SRC_PERIL1,
SRC_MASK_TOP,
SRC_MASK_CAM,
SRC_MASK_TV,
SRC_MASK_LCD0,
SRC_MASK_MAUDIO,
SRC_MASK_FSYS,
SRC_MASK_PERIL0,
SRC_MASK_PERIL1,
DIV_TOP,
DIV_CAM,
DIV_TV,
DIV_MFC,
DIV_G3D,
DIV_IMAGE,
DIV_LCD0,
DIV_MAUDIO,
DIV_FSYS0,
DIV_FSYS1,
DIV_FSYS2,
DIV_FSYS3,
DIV_PERIL0,
DIV_PERIL1,
DIV_PERIL2,
DIV_PERIL3,
DIV_PERIL4,
DIV_PERIL5,
GATE_SCLK_CAM,
GATE_IP_CAM,
GATE_IP_TV,
GATE_IP_MFC,
GATE_IP_G3D,
GATE_IP_LCD0,
GATE_IP_FSYS,
GATE_IP_GPS,
GATE_IP_PERIL,
GATE_BLOCK,
SRC_MASK_DMC,
SRC_DMC,
DIV_DMC0,
DIV_DMC1,
GATE_IP_DMC,
APLL_CON0,
SRC_CPU,
DIV_CPU0,
DIV_CPU1,
GATE_SCLK_CPU,
GATE_IP_CPU,
CLKOUT_CMU_LEFTBUS,
CLKOUT_CMU_RIGHTBUS,
CLKOUT_CMU_TOP,
CLKOUT_CMU_DMC,
CLKOUT_CMU_CPU,
};
static const struct samsung_clk_reg_dump src_mask_suspend[] = {
{ .offset = VPLL_CON0, .value = 0x80600302, },
{ .offset = EPLL_CON0, .value = 0x806F0302, },
{ .offset = SRC_MASK_TOP, .value = 0x00000001, },
{ .offset = SRC_MASK_CAM, .value = 0x11111111, },
{ .offset = SRC_MASK_TV, .value = 0x00000111, },
{ .offset = SRC_MASK_LCD0, .value = 0x00001111, },
{ .offset = SRC_MASK_MAUDIO, .value = 0x00000001, },
{ .offset = SRC_MASK_FSYS, .value = 0x01011111, },
{ .offset = SRC_MASK_PERIL0, .value = 0x01111111, },
{ .offset = SRC_MASK_PERIL1, .value = 0x01110111, },
{ .offset = SRC_MASK_DMC, .value = 0x00010000, },
};
static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = {
{ .offset = E4210_SRC_MASK_LCD1, .value = 0x00001111, },
};
/* list of all parent clock list */
PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", };
PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", };
PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", };
PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", };
PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", };
PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", };
PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", };
PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
"spdif_extclk", };
PNAME(mout_onenand_p) = {"aclk133", "aclk160", };
PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", };
/* Exynos 4210-specific parent groups */
PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", };
PNAME(mout_core_p4210) = { "mout_apll", "sclk_mpll", };
PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", };
PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m",
"sclk_usbphy0", "none", "sclk_hdmiphy",
"sclk_mpll", "sclk_epll", "sclk_vpll", };
PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m",
"sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
"sclk_epll", "sclk_vpll" };
PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m",
"sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
"sclk_epll", "sclk_vpll", };
PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m",
"sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
"sclk_epll", "sclk_vpll", };
PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", };
PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", };
PNAME(mout_pwi_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
"sclk_usbphy1", "sclk_hdmiphy", "none",
"sclk_epll", "sclk_vpll" };
PNAME(clkout_left_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
"div_gdl", "div_gpl" };
PNAME(clkout_right_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
"div_gdr", "div_gpr" };
PNAME(clkout_top_p4210) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
"sclk_usbphy0", "sclk_usbphy1", "sclk_hdmiphy",
"cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
"aclk160", "aclk133", "aclk200", "aclk100",
"sclk_mfc", "sclk_g3d", "sclk_g2d",
"cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
"s_rxbyteclkhs0_4l" };
PNAME(clkout_dmc_p4210) = { "div_dmcd", "div_dmcp", "div_acp_pclk", "div_dmc",
"div_dphy", "none", "div_pwi" };
PNAME(clkout_cpu_p4210) = { "fout_apll_div_2", "none", "fout_mpll_div_2",
"none", "arm_clk_div_2", "div_corem0",
"div_corem1", "div_corem0", "div_atb",
"div_periph", "div_pclk_dbg", "div_hpm" };
/* Exynos 4x12-specific parent groups */
PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", };
PNAME(mout_gdl_p4x12) = { "mout_mpll_user_l", "sclk_apll", };
PNAME(mout_gdr_p4x12) = { "mout_mpll_user_r", "sclk_apll", };
PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", };
PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
"none", "sclk_hdmiphy", "mout_mpll_user_t",
"sclk_epll", "sclk_vpll", };
PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m",
"sclk_usbphy0", "xxti", "xusbxti",
"mout_mpll_user_t", "sclk_epll", "sclk_vpll" };
PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m",
"sclk_usbphy0", "xxti", "xusbxti",
"mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m",
"sclk_usbphy0", "xxti", "xusbxti",
"mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", };
PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
PNAME(mout_pwi_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
"none", "sclk_hdmiphy", "sclk_mpll",
"sclk_epll", "sclk_vpll" };
PNAME(clkout_left_p4x12) = { "sclk_mpll_user_l_div_2", "sclk_apll_div_2",
"div_gdl", "div_gpl" };
PNAME(clkout_right_p4x12) = { "sclk_mpll_user_r_div_2", "sclk_apll_div_2",
"div_gdr", "div_gpr" };
PNAME(clkout_top_p4x12) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
"sclk_usbphy0", "none", "sclk_hdmiphy",
"cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
"aclk160", "aclk133", "aclk200", "aclk100",
"sclk_mfc", "sclk_g3d", "aclk400_mcuisp",
"cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
"s_rxbyteclkhs0_4l", "rx_half_byte_clk_csis0",
"rx_half_byte_clk_csis1", "div_jpeg",
"sclk_pwm_isp", "sclk_spi0_isp",
"sclk_spi1_isp", "sclk_uart_isp",
"sclk_mipihsi", "sclk_hdmi", "sclk_fimd0",
"sclk_pcm0" };
PNAME(clkout_dmc_p4x12) = { "div_dmcd", "div_dmcp", "aclk_acp", "div_acp_pclk",
"div_dmc", "div_dphy", "fout_mpll_div_2",
"div_pwi", "none", "div_c2c", "div_c2c_aclk" };
PNAME(clkout_cpu_p4x12) = { "fout_apll_div_2", "none", "none", "none",
"arm_clk_div_2", "div_corem0", "div_corem1",
"div_cores", "div_atb", "div_periph",
"div_pclk_dbg", "div_hpm" };
/* fixed rate clocks generated outside the soc */
static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
FRATE(CLK_XXTI, "xxti", NULL, 0, 0),
FRATE(CLK_XUSBXTI, "xusbxti", NULL, 0, 0),
};
/* fixed rate clocks generated inside the soc */
static const struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initconst = {
FRATE(0, "sclk_hdmi24m", NULL, 0, 24000000),
FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000),
FRATE(0, "sclk_usbphy0", NULL, 0, 48000000),
};
static const struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initconst = {
FRATE(0, "sclk_usbphy1", NULL, 0, 48000000),
};
static const struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initconst = {
FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0),
FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0),
FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0),
FFACTOR(0, "arm_clk_div_2", "div_core2", 1, 2, 0),
};
static const struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initconst = {
FFACTOR(0, "sclk_mpll_div_2", "sclk_mpll", 1, 2, 0),
};
static const struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initconst = {
FFACTOR(0, "sclk_mpll_user_l_div_2", "mout_mpll_user_l", 1, 2, 0),
FFACTOR(0, "sclk_mpll_user_r_div_2", "mout_mpll_user_r", 1, 2, 0),
FFACTOR(0, "sclk_mpll_user_t_div_2", "mout_mpll_user_t", 1, 2, 0),
FFACTOR(0, "sclk_mpll_user_c_div_2", "mout_mpll_user_c", 1, 2, 0),
};
/* list of mux clocks supported in all exynos4 soc's */
static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = {
MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
MUX_F(CLK_MOUT_G3D1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
CLK_SET_RATE_PARENT, 0),
MUX_F(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
CLK_SET_RATE_PARENT, 0),
MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1),
MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
MUX(0, "mout_dmc_bus", sclk_ampll_p4210, SRC_DMC, 4, 1),
MUX(0, "mout_dphy", sclk_ampll_p4210, SRC_DMC, 8, 1),
};
/* list of mux clocks supported in exynos4210 soc */
static const struct samsung_mux_clock exynos4210_mux_early[] __initconst = {
MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
};
static const struct samsung_mux_clock exynos4210_mux_clks[] __initconst = {
MUX(0, "mout_gdl", sclk_ampll_p4210, SRC_LEFTBUS, 0, 1),
MUX(0, "mout_clkout_leftbus", clkout_left_p4210,
CLKOUT_CMU_LEFTBUS, 0, 5),
MUX(0, "mout_gdr", sclk_ampll_p4210, SRC_RIGHTBUS, 0, 1),
MUX(0, "mout_clkout_rightbus", clkout_right_p4210,
CLKOUT_CMU_RIGHTBUS, 0, 5),
MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
MUX(0, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
MUX(CLK_MOUT_MIXER, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
MUX(0, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
MUX(0, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
MUX(0, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1),
MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4),
MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4),
MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4),
MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
MUX(0, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
CLK_SET_RATE_PARENT, 0),
MUX(0, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
MUX(0, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
MUX(0, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
MUX(0, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4),
MUX(0, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4),
MUX(0, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
MUX(0, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
MUX(0, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
MUX(0, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
MUX(0, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
MUX(0, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
MUX(0, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),
MUX(0, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4),
MUX(0, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4),
MUX(0, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4),
MUX(0, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4),
MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
MUX(0, "mout_clkout_top", clkout_top_p4210, CLKOUT_CMU_TOP, 0, 5),
MUX(0, "mout_pwi", mout_pwi_p4210, SRC_DMC, 16, 4),
MUX(0, "mout_clkout_dmc", clkout_dmc_p4210, CLKOUT_CMU_DMC, 0, 5),
MUX(0, "mout_clkout_cpu", clkout_cpu_p4210, CLKOUT_CMU_CPU, 0, 5),
};
/* list of mux clocks supported in exynos4x12 soc */
static const struct samsung_mux_clock exynos4x12_mux_clks[] __initconst = {
MUX(0, "mout_mpll_user_l", mout_mpll_p, SRC_LEFTBUS, 4, 1),
MUX(0, "mout_gdl", mout_gdl_p4x12, SRC_LEFTBUS, 0, 1),
MUX(0, "mout_clkout_leftbus", clkout_left_p4x12,
CLKOUT_CMU_LEFTBUS, 0, 5),
MUX(0, "mout_mpll_user_r", mout_mpll_p, SRC_RIGHTBUS, 4, 1),
MUX(0, "mout_gdr", mout_gdr_p4x12, SRC_RIGHTBUS, 0, 1),
MUX(0, "mout_clkout_rightbus", clkout_right_p4x12,
CLKOUT_CMU_RIGHTBUS, 0, 5),
MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12,
SRC_CPU, 24, 1),
MUX(0, "mout_clkout_cpu", clkout_cpu_p4x12, CLKOUT_CMU_CPU, 0, 5),
MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12,
SRC_TOP1, 12, 1),
MUX(0, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12,
SRC_TOP1, 16, 1),
MUX(CLK_ACLK200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1),
MUX(CLK_ACLK400_MCUISP, "aclk400_mcuisp",
mout_user_aclk400_mcuisp_p4x12, SRC_TOP1, 24, 1),
MUX(0, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
MUX(0, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
MUX(0, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
MUX(0, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
MUX(0, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4),
MUX(0, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4),
MUX(0, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1),
MUX(0, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
MUX(0, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
MUX(0, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
MUX(0, "mout_hpm", mout_core_p4x12, SRC_CPU, 20, 1),
MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4),
MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4),
MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4),
MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
MUX(0, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
CLK_SET_RATE_PARENT, 0),
MUX(0, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
MUX(0, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
MUX(0, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
MUX(0, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4),
MUX(0, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4),
MUX(0, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
MUX(0, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
MUX(0, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
MUX(0, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
MUX(0, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
MUX(0, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
MUX(0, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),
MUX(0, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4),
MUX(0, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4),
MUX(0, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4),
MUX(0, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4),
MUX(0, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
MUX(0, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
MUX(0, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
MUX(0, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4),
MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
MUX(0, "mout_clkout_top", clkout_top_p4x12, CLKOUT_CMU_TOP, 0, 5),
MUX(0, "mout_c2c", sclk_ampll_p4210, SRC_DMC, 0, 1),
MUX(0, "mout_pwi", mout_pwi_p4x12, SRC_DMC, 16, 4),
MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
MUX(0, "mout_clkout_dmc", clkout_dmc_p4x12, CLKOUT_CMU_DMC, 0, 5),
};
/* list of divider clocks supported in all exynos4 soc's */
static const struct samsung_div_clock exynos4_div_clks[] __initconst = {
DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
CLKOUT_CMU_LEFTBUS, 8, 6),
DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
CLKOUT_CMU_RIGHTBUS, 8, 6),
DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
DIV(0, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
DIV(0, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
DIV(0, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
DIV(CLK_SCLK_G3D, "sclk_g3d", "mout_g3d", DIV_G3D, 0, 4),
DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
DIV(CLK_SCLK_PCM0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
DIV(CLK_SCLK_PIXEL, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
DIV(CLK_ACLK100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
DIV(CLK_ACLK160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
DIV(CLK_ACLK133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
DIV(0, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
DIV(CLK_SCLK_SLIMBUS, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
DIV(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
DIV(CLK_SCLK_PCM2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
DIV(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
DIV(CLK_SCLK_I2S2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
DIV(0, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
DIV_F(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,
CLK_SET_RATE_PARENT, 0),
DIV(0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
DIV(0, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
DIV(0, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
DIV(0, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
DIV(0, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
DIV(0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
DIV(0, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
DIV(0, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
DIV(0, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
DIV(0, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
CLK_SET_RATE_PARENT, 0),
DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
CLK_SET_RATE_PARENT, 0),
DIV_F(0, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
CLK_SET_RATE_PARENT, 0),
DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
CLK_SET_RATE_PARENT, 0),
DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
DIV(CLK_DIV_ACP, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
DIV(CLK_DIV_DMC, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
DIV(0, "div_clkout_dmc", "mout_clkout_dmc", CLKOUT_CMU_DMC, 8, 6),
};
/* list of divider clocks supported in exynos4210 soc */
static const struct samsung_div_clock exynos4210_div_clks[] __initconst = {
DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
DIV(0, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
DIV_F(0, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
CLK_SET_RATE_PARENT, 0),
};
/* list of divider clocks supported in exynos4x12 soc */
static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {
DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
DIV(0, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
DIV(0, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
DIV(CLK_DIV_ACLK200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3),
DIV(0, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3),
DIV(CLK_DIV_ACLK400_MCUISP, "div_aclk400_mcuisp", "mout_aclk400_mcuisp",
DIV_TOP, 24, 3),
DIV(0, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4),
DIV(0, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4),
DIV(0, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8),
DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
};
/* list of gate clocks supported in all exynos4 soc's */
static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = {
GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0,
0),
GATE(CLK_JPEG, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
GATE(CLK_MIE0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
GATE(CLK_DSIM0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
GATE(CLK_FIMD1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0),
GATE(CLK_MIE1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0),
GATE(CLK_DSIM1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0),
GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0,
0),
GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
GATE(CLK_G3D, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0),
GATE(CLK_PPMUG3D, "ppmug3d", "aclk200", GATE_IP_G3D, 1, 0, 0),
GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
GATE(CLK_PPMUGPS, "ppmugps", "aclk200", GATE_IP_GPS, 2, 0, 0),
GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi_pre0",
SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_VP, "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
GATE(CLK_MIXER, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
GATE(CLK_HDMI, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
GATE(CLK_PWM, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0),
GATE(CLK_SDMMC4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0),
GATE(CLK_USB_HOST, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0),
GATE(CLK_SCLK_FIMC0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_FIMC1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_FIMC2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_FIMC3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_FIMC0, "fimc0", "aclk160", GATE_IP_CAM, 0,
0, 0),
GATE(CLK_FIMC1, "fimc1", "aclk160", GATE_IP_CAM, 1,
0, 0),
GATE(CLK_FIMC2, "fimc2", "aclk160", GATE_IP_CAM, 2,
0, 0),
GATE(CLK_FIMC3, "fimc3", "aclk160", GATE_IP_CAM, 3,
0, 0),
GATE(CLK_CSIS0, "csis0", "aclk160", GATE_IP_CAM, 4,
0, 0),
GATE(CLK_CSIS1, "csis1", "aclk160", GATE_IP_CAM, 5,
0, 0),
GATE(CLK_SMMU_FIMC0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7,
0, 0),
GATE(CLK_SMMU_FIMC1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8,
0, 0),
GATE(CLK_SMMU_FIMC2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9,
0, 0),
GATE(CLK_SMMU_FIMC3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10,
0, 0),
GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11,
0, 0),
GATE(CLK_PPMUCAMIF, "ppmucamif", "aclk160", GATE_IP_CAM, 16, 0, 0),
GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4,
0, 0),
GATE(CLK_PPMUTV, "ppmutv", "aclk160", GATE_IP_TV, 5, 0, 0),
GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0),
GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1,
0, 0),
GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2,
0, 0),
GATE(CLK_PPMUMFC_L, "ppmumfc_l", "aclk100", GATE_IP_MFC, 3, 0, 0),
GATE(CLK_PPMUMFC_R, "ppmumfc_r", "aclk100", GATE_IP_MFC, 4, 0, 0),
GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0,
0, 0),
GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4,
0, 0),
GATE(CLK_PPMULCD0, "ppmulcd0", "aclk160", GATE_IP_LCD0, 5, 0, 0),
GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0,
0, 0),
GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1,
0, 0),
GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5,
0, 0),
GATE(CLK_SDMMC1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6,
0, 0),
GATE(CLK_SDMMC2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7,
0, 0),
GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8,
0, 0),
GATE(CLK_PPMUFILE, "ppmufile", "aclk133", GATE_IP_FSYS, 17, 0, 0),
GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0,
0, 0),
GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1,
0, 0),
GATE(CLK_UART2, "uart2", "aclk100", GATE_IP_PERIL, 2,
0, 0),
GATE(CLK_UART3, "uart3", "aclk100", GATE_IP_PERIL, 3,
0, 0),
GATE(CLK_UART4, "uart4", "aclk100", GATE_IP_PERIL, 4,
0, 0),
GATE(CLK_I2C0, "i2c0", "aclk100", GATE_IP_PERIL, 6,
0, 0),
GATE(CLK_I2C1, "i2c1", "aclk100", GATE_IP_PERIL, 7,
0, 0),
GATE(CLK_I2C2, "i2c2", "aclk100", GATE_IP_PERIL, 8,
0, 0),
GATE(CLK_I2C3, "i2c3", "aclk100", GATE_IP_PERIL, 9,
0, 0),
GATE(CLK_I2C4, "i2c4", "aclk100", GATE_IP_PERIL, 10,
0, 0),
GATE(CLK_I2C5, "i2c5", "aclk100", GATE_IP_PERIL, 11,
0, 0),
GATE(CLK_I2C6, "i2c6", "aclk100", GATE_IP_PERIL, 12,
0, 0),
GATE(CLK_I2C7, "i2c7", "aclk100", GATE_IP_PERIL, 13,
0, 0),
GATE(CLK_I2C_HDMI, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14,
0, 0),
GATE(CLK_SPI0, "spi0", "aclk100", GATE_IP_PERIL, 16,
0, 0),
GATE(CLK_SPI1, "spi1", "aclk100", GATE_IP_PERIL, 17,
0, 0),
GATE(CLK_SPI2, "spi2", "aclk100", GATE_IP_PERIL, 18,
0, 0),
GATE(CLK_I2S1, "i2s1", "aclk100", GATE_IP_PERIL, 20,
0, 0),
GATE(CLK_I2S2, "i2s2", "aclk100", GATE_IP_PERIL, 21,
0, 0),
GATE(CLK_PCM1, "pcm1", "aclk100", GATE_IP_PERIL, 22,
0, 0),
GATE(CLK_PCM2, "pcm2", "aclk100", GATE_IP_PERIL, 23,
0, 0),
GATE(CLK_SPDIF, "spdif", "aclk100", GATE_IP_PERIL, 26,
0, 0),
GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27,
0, 0),
GATE(CLK_SSS, "sss", "aclk133", GATE_IP_DMC, 4, 0, 0),
GATE(CLK_PPMUDMC0, "ppmudmc0", "aclk133", GATE_IP_DMC, 8, 0, 0),
GATE(CLK_PPMUDMC1, "ppmudmc1", "aclk133", GATE_IP_DMC, 9, 0, 0),
GATE(CLK_PPMUCPU, "ppmucpu", "aclk133", GATE_IP_DMC, 10, 0, 0),
GATE(CLK_PPMUACP, "ppmuacp", "aclk133", GATE_IP_DMC, 16, 0, 0),
GATE(CLK_OUT_LEFTBUS, "clkout_leftbus", "div_clkout_leftbus",
CLKOUT_CMU_LEFTBUS, 16, CLK_SET_RATE_PARENT, 0),
GATE(CLK_OUT_RIGHTBUS, "clkout_rightbus", "div_clkout_rightbus",
CLKOUT_CMU_RIGHTBUS, 16, CLK_SET_RATE_PARENT, 0),
GATE(CLK_OUT_TOP, "clkout_top", "div_clkout_top",
CLKOUT_CMU_TOP, 16, CLK_SET_RATE_PARENT, 0),
GATE(CLK_OUT_DMC, "clkout_dmc", "div_clkout_dmc",
CLKOUT_CMU_DMC, 16, CLK_SET_RATE_PARENT, 0),
GATE(CLK_OUT_CPU, "clkout_cpu", "div_clkout_cpu",
CLKOUT_CMU_CPU, 16, CLK_SET_RATE_PARENT, 0),
};
/* list of gate clocks supported in exynos4210 soc */
static const struct samsung_gate_clock exynos4210_gate_clks[] __initconst = {
GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
GATE(CLK_MDMA, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0,
0),
GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4210_GATE_IP_IMAGE, 9, 0,
0),
GATE(CLK_PPMULCD1, "ppmulcd1", "aclk160", E4210_GATE_IP_LCD1, 5, 0, 0),
GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
GATE(CLK_PCIE, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
GATE(CLK_SMMU_PCIE, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
GATE(CLK_MODEMIF, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
GATE(CLK_CHIPID, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SYSREG, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0,
0),
GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
E4210_GATE_IP_IMAGE, 4, 0, 0),
GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi_pre1",
E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MIXER, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
GATE(CLK_SCLK_DAC, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
GATE(CLK_TSADC, "tsadc", "aclk100", GATE_IP_PERIL, 15,
0, 0),
GATE(CLK_MCT, "mct", "aclk100", E4210_GATE_IP_PERIR, 13,
0, 0),
GATE(CLK_WDT, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14,
0, 0),
GATE(CLK_RTC, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15,
0, 0),
GATE(CLK_KEYIF, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16,
0, 0),
GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0,
CLK_SET_RATE_PARENT, 0),
GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0,
0),
};
/* list of gate clocks supported in exynos4x12 soc */
static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {
GATE(CLK_ASYNC_G3D, "async_g3d", "aclk200", GATE_IP_LEFTBUS, 6, 0, 0),
GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
0),
GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0,
0),
GATE(CLK_TSADC, "tsadc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, 0),
GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0,
0),
GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_mdnie0",
SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MDNIE_PWM0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0",
SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MIPIHSI, "sclk_mipihsi", "div_mipihsi",
SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
E4X12_GATE_IP_IMAGE, 4, 0, 0),
GATE(CLK_MCT, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13,
0, 0),
GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15,
0, 0),
GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0),
GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "div_pwm_isp",
E4X12_GATE_IP_ISP, 0, 0, 0),
GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "div_spi0_isp_pre",
E4X12_GATE_IP_ISP, 1, 0, 0),
GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "div_spi1_isp_pre",
E4X12_GATE_IP_ISP, 2, 0, 0),
GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "div_uart_isp",
E4X12_GATE_IP_ISP, 3, 0, 0),
GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0),
GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2,
0, 0),
GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3,
0, 0),
GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0),
GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
0),
};
/*
* The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
* resides in chipid register space, outside of the clock controller memory
* mapped space. So to determine the parent of fin_pll clock, the chipid
* controller is first remapped and the value of XOM[0] bit is read to
* determine the parent clock.
*/
static unsigned long __init exynos4_get_xom(void)
{
unsigned long xom = 0;
void __iomem *chipid_base;
struct device_node *np;
np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
if (np) {
chipid_base = of_iomap(np, 0);
if (chipid_base)
xom = readl(chipid_base + 8);
iounmap(chipid_base);
of_node_put(np);
}
return xom;
}
static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)
{
struct samsung_fixed_rate_clock fclk;
struct clk *clk;
unsigned long finpll_f = 24000000;
char *parent_name;
unsigned int xom = exynos4_get_xom();
parent_name = xom & 1 ? "xusbxti" : "xxti";
clk = clk_get(NULL, parent_name);
if (IS_ERR(clk)) {
pr_err("%s: failed to lookup parent clock %s, assuming "
"fin_pll clock frequency is 24MHz\n", __func__,
parent_name);
} else {
finpll_f = clk_get_rate(clk);
}
fclk.id = CLK_FIN_PLL;
fclk.name = "fin_pll";
fclk.parent_name = NULL;
fclk.flags = 0;
fclk.fixed_rate = finpll_f;
samsung_clk_register_fixed_rate(ctx, &fclk, 1);
}
static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
{ .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
{},
};
/* PLLs PMS values */
static const struct samsung_pll_rate_table exynos4210_apll_rates[] __initconst = {
PLL_4508_RATE(24 * MHZ, 1200000000, 150, 3, 1, 28),
PLL_4508_RATE(24 * MHZ, 1000000000, 250, 6, 1, 28),
PLL_4508_RATE(24 * MHZ, 800000000, 200, 6, 1, 28),
PLL_4508_RATE(24 * MHZ, 666857142, 389, 14, 1, 13),
PLL_4508_RATE(24 * MHZ, 600000000, 100, 4, 1, 13),
PLL_4508_RATE(24 * MHZ, 533000000, 533, 24, 1, 5),
PLL_4508_RATE(24 * MHZ, 500000000, 250, 6, 2, 28),
PLL_4508_RATE(24 * MHZ, 400000000, 200, 6, 2, 28),
PLL_4508_RATE(24 * MHZ, 200000000, 200, 6, 3, 28),
{ /* sentinel */ }
};
static const struct samsung_pll_rate_table exynos4210_epll_rates[] __initconst = {
PLL_4600_RATE(24 * MHZ, 192000000, 48, 3, 1, 0, 0),
PLL_4600_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381, 0),
PLL_4600_RATE(24 * MHZ, 180000000, 45, 3, 1, 0, 0),
PLL_4600_RATE(24 * MHZ, 73727996, 73, 3, 3, 47710, 1),
PLL_4600_RATE(24 * MHZ, 67737602, 90, 4, 3, 20762, 1),
PLL_4600_RATE(24 * MHZ, 49151992, 49, 3, 3, 9961, 0),
PLL_4600_RATE(24 * MHZ, 45158401, 45, 3, 3, 10381, 0),
{ /* sentinel */ }
};
static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst = {
PLL_4650_RATE(24 * MHZ, 360000000, 44, 3, 0, 1024, 0, 14, 0),
PLL_4650_RATE(24 * MHZ, 324000000, 53, 2, 1, 1024, 1, 1, 1),
PLL_4650_RATE(24 * MHZ, 259617187, 63, 3, 1, 1950, 0, 20, 1),
PLL_4650_RATE(24 * MHZ, 110000000, 53, 3, 2, 2048, 0, 17, 0),
PLL_4650_RATE(24 * MHZ, 55360351, 53, 3, 3, 2417, 0, 17, 0),
{ /* sentinel */ }
};
static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = {
PLL_35XX_RATE(24 * MHZ, 1704000000, 213, 3, 0),
PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1),
PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1),
PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1),
PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2),
PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2),
{ /* sentinel */ }
};
static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = {
PLL_36XX_RATE(24 * MHZ, 196608001, 197, 3, 3, -25690),
PLL_36XX_RATE(24 * MHZ, 192000000, 48, 3, 1, 0),
PLL_36XX_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381),
PLL_36XX_RATE(24 * MHZ, 180000000, 45, 3, 1, 0),
PLL_36XX_RATE(24 * MHZ, 73727996, 73, 3, 3, 47710),
PLL_36XX_RATE(24 * MHZ, 67737602, 90, 4, 3, 20762),
PLL_36XX_RATE(24 * MHZ, 49151992, 49, 3, 3, 9961),
PLL_36XX_RATE(24 * MHZ, 45158401, 45, 3, 3, 10381),
{ /* sentinel */ }
};
static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst = {
PLL_36XX_RATE(24 * MHZ, 533000000, 133, 3, 1, 16384),
PLL_36XX_RATE(24 * MHZ, 440000000, 110, 3, 1, 0),
PLL_36XX_RATE(24 * MHZ, 350000000, 175, 3, 2, 0),
PLL_36XX_RATE(24 * MHZ, 266000000, 133, 3, 2, 0),
PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3, 0),
PLL_36XX_RATE(24 * MHZ, 106031250, 53, 3, 2, 1024),
PLL_36XX_RATE(24 * MHZ, 53015625, 53, 3, 3, 1024),
{ /* sentinel */ }
};
static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
[apll] = PLL(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
APLL_LOCK, APLL_CON0, NULL),
[mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
E4210_MPLL_LOCK, E4210_MPLL_CON0, NULL),
[epll] = PLL(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
EPLL_LOCK, EPLL_CON0, NULL),
[vpll] = PLL(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
VPLL_LOCK, VPLL_CON0, NULL),
};
static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
APLL_LOCK, APLL_CON0, NULL),
[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL),
[epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
EPLL_LOCK, EPLL_CON0, NULL),
[vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
VPLL_LOCK, VPLL_CON0, NULL),
};
static void __init exynos4x12_core_down_clock(void)
{
unsigned int tmp;
/*
* Enable arm clock down (in idle) and set arm divider
* ratios in WFI/WFE state.
*/
tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
/* On Exynos4412 enable it also on core 2 and 3 */
if (num_possible_cpus() == 4)
tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE |
PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI;
writel_relaxed(tmp, reg_base + PWR_CTRL1);
/*
* Disable the clock up feature in case it was enabled by bootloader.
*/
writel_relaxed(0x0, reg_base + E4X12_PWR_CTRL2);
}
#define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0) \
(((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
((periph) << 12) | ((corem1) << 8) | ((corem0) << 4))
#define E4210_CPU_DIV1(hpm, copy) \
(((hpm) << 4) | ((copy) << 0))
static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
{ 1200000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
{ 1000000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
{ 800000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
{ 500000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
{ 400000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
{ 200000, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
{ 0 },
};
static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {
{ 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
{ 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
{ 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
{ 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
{ 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },
{ 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },
{ 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
{ 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
{ 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
{ 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
{ 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
{ 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
{ 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
{ 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },
{ 0 },
};
#define E4412_CPU_DIV1(cores, hpm, copy) \
(((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {
{ 1704000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 7), },
{ 1600000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
{ 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
{ 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), },
{ 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },
{ 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), },
{ 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), },
{ 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), },
{ 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), },
{ 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), },
{ 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), },
{ 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
{ 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
{ 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
{ 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
{ 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), },
{ 0 },
};
static const struct samsung_cpu_clock exynos4210_cpu_clks[] __initconst = {
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_SCLK_MPLL,
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4210_armclk_d),
};
static const struct samsung_cpu_clock exynos4212_cpu_clks[] __initconst = {
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4212_armclk_d),
};
static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = {
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4412_armclk_d),
};
/* register exynos4 clocks */
static void __init exynos4_clk_init(struct device_node *np,
enum exynos4_soc soc)
{
struct samsung_clk_provider *ctx;
struct clk_hw **hws;
exynos4_soc = soc;
reg_base = of_iomap(np, 0);
if (!reg_base)
panic("%s: failed to map registers\n", __func__);
ctx = samsung_clk_init(NULL, reg_base, CLKS_NR);
hws = ctx->clk_data.hws;
samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
ext_clk_match);
exynos4_clk_register_finpll(ctx);
if (exynos4_soc == EXYNOS4210) {
samsung_clk_register_mux(ctx, exynos4210_mux_early,
ARRAY_SIZE(exynos4210_mux_early));
if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) {
exynos4210_plls[apll].rate_table =
exynos4210_apll_rates;
exynos4210_plls[epll].rate_table =
exynos4210_epll_rates;
}
if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24000000)
exynos4210_plls[vpll].rate_table =
exynos4210_vpll_rates;
samsung_clk_register_pll(ctx, exynos4210_plls,
ARRAY_SIZE(exynos4210_plls));
} else {
if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) {
exynos4x12_plls[apll].rate_table =
exynos4x12_apll_rates;
exynos4x12_plls[epll].rate_table =
exynos4x12_epll_rates;
exynos4x12_plls[vpll].rate_table =
exynos4x12_vpll_rates;
}
samsung_clk_register_pll(ctx, exynos4x12_plls,
ARRAY_SIZE(exynos4x12_plls));
}
samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
ARRAY_SIZE(exynos4_fixed_rate_clks));
samsung_clk_register_mux(ctx, exynos4_mux_clks,
ARRAY_SIZE(exynos4_mux_clks));
samsung_clk_register_div(ctx, exynos4_div_clks,
ARRAY_SIZE(exynos4_div_clks));
samsung_clk_register_gate(ctx, exynos4_gate_clks,
ARRAY_SIZE(exynos4_gate_clks));
samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks,
ARRAY_SIZE(exynos4_fixed_factor_clks));
if (exynos4_soc == EXYNOS4210) {
samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
ARRAY_SIZE(exynos4210_fixed_rate_clks));
samsung_clk_register_mux(ctx, exynos4210_mux_clks,
ARRAY_SIZE(exynos4210_mux_clks));
samsung_clk_register_div(ctx, exynos4210_div_clks,
ARRAY_SIZE(exynos4210_div_clks));
samsung_clk_register_gate(ctx, exynos4210_gate_clks,
ARRAY_SIZE(exynos4210_gate_clks));
samsung_clk_register_fixed_factor(ctx,
exynos4210_fixed_factor_clks,
ARRAY_SIZE(exynos4210_fixed_factor_clks));
samsung_clk_register_cpu(ctx, exynos4210_cpu_clks,
ARRAY_SIZE(exynos4210_cpu_clks));
} else {
samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
ARRAY_SIZE(exynos4x12_mux_clks));
samsung_clk_register_div(ctx, exynos4x12_div_clks,
ARRAY_SIZE(exynos4x12_div_clks));
samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
ARRAY_SIZE(exynos4x12_gate_clks));
samsung_clk_register_fixed_factor(ctx,
exynos4x12_fixed_factor_clks,
ARRAY_SIZE(exynos4x12_fixed_factor_clks));
if (soc == EXYNOS4412)
samsung_clk_register_cpu(ctx, exynos4412_cpu_clks,
ARRAY_SIZE(exynos4412_cpu_clks));
else
samsung_clk_register_cpu(ctx, exynos4212_cpu_clks,
ARRAY_SIZE(exynos4212_cpu_clks));
}
if (soc == EXYNOS4212 || soc == EXYNOS4412)
exynos4x12_core_down_clock();
samsung_clk_extended_sleep_init(reg_base,
exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
src_mask_suspend, ARRAY_SIZE(src_mask_suspend));
if (exynos4_soc == EXYNOS4210)
samsung_clk_extended_sleep_init(reg_base,
exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save),
src_mask_suspend_e4210, ARRAY_SIZE(src_mask_suspend_e4210));
else
samsung_clk_sleep_init(reg_base, exynos4x12_clk_save,
ARRAY_SIZE(exynos4x12_clk_save));
samsung_clk_of_add_provider(np, ctx);
pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
"\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
clk_hw_get_rate(hws[CLK_SCLK_APLL]),
clk_hw_get_rate(hws[CLK_SCLK_MPLL]),
clk_hw_get_rate(hws[CLK_SCLK_EPLL]),
clk_hw_get_rate(hws[CLK_SCLK_VPLL]),
clk_hw_get_rate(hws[CLK_DIV_CORE2]));
}
static void __init exynos4210_clk_init(struct device_node *np)
{
exynos4_clk_init(np, EXYNOS4210);
}
CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init);
static void __init exynos4212_clk_init(struct device_node *np)
{
exynos4_clk_init(np, EXYNOS4212);
}
CLK_OF_DECLARE(exynos4212_clk, "samsung,exynos4212-clock", exynos4212_clk_init);
static void __init exynos4412_clk_init(struct device_node *np)
{
exynos4_clk_init(np, EXYNOS4412);
}
CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init);
| linux-master | drivers/clk/samsung/clk-exynos4.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 Tomasz Figa <[email protected]>
*
* Based on Exynos Audio Subsystem Clock Controller driver:
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Padmavathi Venna <[email protected]>
*
* Driver for Audio Subsystem Clock Controller of S5PV210-compatible SoCs.
*/
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of_address.h>
#include <linux/syscore_ops.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/s5pv210-audss.h>
static DEFINE_SPINLOCK(lock);
static void __iomem *reg_base;
static struct clk_hw_onecell_data *clk_data;
#define ASS_CLK_SRC 0x0
#define ASS_CLK_DIV 0x4
#define ASS_CLK_GATE 0x8
#ifdef CONFIG_PM_SLEEP
static unsigned long reg_save[][2] = {
{ASS_CLK_SRC, 0},
{ASS_CLK_DIV, 0},
{ASS_CLK_GATE, 0},
};
static int s5pv210_audss_clk_suspend(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(reg_save); i++)
reg_save[i][1] = readl(reg_base + reg_save[i][0]);
return 0;
}
static void s5pv210_audss_clk_resume(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(reg_save); i++)
writel(reg_save[i][1], reg_base + reg_save[i][0]);
}
static struct syscore_ops s5pv210_audss_clk_syscore_ops = {
.suspend = s5pv210_audss_clk_suspend,
.resume = s5pv210_audss_clk_resume,
};
#endif /* CONFIG_PM_SLEEP */
/* register s5pv210_audss clocks */
static int s5pv210_audss_clk_probe(struct platform_device *pdev)
{
int i, ret = 0;
const char *mout_audss_p[2];
const char *mout_i2s_p[3];
const char *hclk_p;
struct clk_hw **clk_table;
struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio;
reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg_base))
return PTR_ERR(reg_base);
clk_data = devm_kzalloc(&pdev->dev,
struct_size(clk_data, hws, AUDSS_MAX_CLKS),
GFP_KERNEL);
if (!clk_data)
return -ENOMEM;
clk_data->num = AUDSS_MAX_CLKS;
clk_table = clk_data->hws;
hclk = devm_clk_get(&pdev->dev, "hclk");
if (IS_ERR(hclk)) {
dev_err(&pdev->dev, "failed to get hclk clock\n");
return PTR_ERR(hclk);
}
pll_in = devm_clk_get(&pdev->dev, "fout_epll");
if (IS_ERR(pll_in)) {
dev_err(&pdev->dev, "failed to get fout_epll clock\n");
return PTR_ERR(pll_in);
}
sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio0");
if (IS_ERR(sclk_audio)) {
dev_err(&pdev->dev, "failed to get sclk_audio0 clock\n");
return PTR_ERR(sclk_audio);
}
/* iiscdclk0 is an optional external I2S codec clock */
cdclk = devm_clk_get(&pdev->dev, "iiscdclk0");
pll_ref = devm_clk_get(&pdev->dev, "xxti");
if (!IS_ERR(pll_ref))
mout_audss_p[0] = __clk_get_name(pll_ref);
else
mout_audss_p[0] = "xxti";
mout_audss_p[1] = __clk_get_name(pll_in);
clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss",
mout_audss_p, ARRAY_SIZE(mout_audss_p),
CLK_SET_RATE_NO_REPARENT,
reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
mout_i2s_p[0] = "mout_audss";
if (!IS_ERR(cdclk))
mout_i2s_p[1] = __clk_get_name(cdclk);
else
mout_i2s_p[1] = "iiscdclk0";
mout_i2s_p[2] = __clk_get_name(sclk_audio);
clk_table[CLK_MOUT_I2S_A] = clk_hw_register_mux(NULL, "mout_i2s_audss",
mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
CLK_SET_RATE_NO_REPARENT,
reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL,
"dout_aud_bus", "mout_audss", 0,
reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL,
"dout_i2s_audss", "mout_i2s_audss", 0,
reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss",
"dout_i2s_audss", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 6, 0, &lock);
hclk_p = __clk_get_name(hclk);
clk_table[CLK_HCLK_I2S] = clk_hw_register_gate(NULL, "hclk_i2s_audss",
hclk_p, CLK_IGNORE_UNUSED,
reg_base + ASS_CLK_GATE, 5, 0, &lock);
clk_table[CLK_HCLK_UART] = clk_hw_register_gate(NULL, "hclk_uart_audss",
hclk_p, CLK_IGNORE_UNUSED,
reg_base + ASS_CLK_GATE, 4, 0, &lock);
clk_table[CLK_HCLK_HWA] = clk_hw_register_gate(NULL, "hclk_hwa_audss",
hclk_p, CLK_IGNORE_UNUSED,
reg_base + ASS_CLK_GATE, 3, 0, &lock);
clk_table[CLK_HCLK_DMA] = clk_hw_register_gate(NULL, "hclk_dma_audss",
hclk_p, CLK_IGNORE_UNUSED,
reg_base + ASS_CLK_GATE, 2, 0, &lock);
clk_table[CLK_HCLK_BUF] = clk_hw_register_gate(NULL, "hclk_buf_audss",
hclk_p, CLK_IGNORE_UNUSED,
reg_base + ASS_CLK_GATE, 1, 0, &lock);
clk_table[CLK_HCLK_RP] = clk_hw_register_gate(NULL, "hclk_rp_audss",
hclk_p, CLK_IGNORE_UNUSED,
reg_base + ASS_CLK_GATE, 0, 0, &lock);
for (i = 0; i < clk_data->num; i++) {
if (IS_ERR(clk_table[i])) {
dev_err(&pdev->dev, "failed to register clock %d\n", i);
ret = PTR_ERR(clk_table[i]);
goto unregister;
}
}
ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
clk_data);
if (ret) {
dev_err(&pdev->dev, "failed to add clock provider\n");
goto unregister;
}
#ifdef CONFIG_PM_SLEEP
register_syscore_ops(&s5pv210_audss_clk_syscore_ops);
#endif
return 0;
unregister:
for (i = 0; i < clk_data->num; i++) {
if (!IS_ERR(clk_table[i]))
clk_hw_unregister(clk_table[i]);
}
return ret;
}
static const struct of_device_id s5pv210_audss_clk_of_match[] = {
{ .compatible = "samsung,s5pv210-audss-clock", },
{},
};
static struct platform_driver s5pv210_audss_clk_driver = {
.driver = {
.name = "s5pv210-audss-clk",
.suppress_bind_attrs = true,
.of_match_table = s5pv210_audss_clk_of_match,
},
.probe = s5pv210_audss_clk_probe,
};
static int __init s5pv210_audss_clk_init(void)
{
return platform_driver_register(&s5pv210_audss_clk_driver);
}
core_initcall(s5pv210_audss_clk_init);
| linux-master | drivers/clk/samsung/clk-s5pv210-audss.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2021 Dávid Virág <[email protected]>
* Author: Dávid Virág <[email protected]>
*
* Common Clock Framework support for Exynos7885 SoC.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/exynos7885.h>
#include "clk.h"
#include "clk-exynos-arm64.h"
/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR_TOP (CLK_GOUT_FSYS_USB30DRD + 1)
#define CLKS_NR_CORE (CLK_GOUT_TREX_P_CORE_PCLK_P_CORE + 1)
#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1)
#define CLKS_NR_FSYS (CLK_GOUT_MMC_SDIO_SDCLKIN + 1)
/* ---- CMU_TOP ------------------------------------------------------------- */
/* Register Offset definitions for CMU_TOP (0x12060000) */
#define PLL_LOCKTIME_PLL_SHARED0 0x0000
#define PLL_LOCKTIME_PLL_SHARED1 0x0004
#define PLL_CON0_PLL_SHARED0 0x0100
#define PLL_CON0_PLL_SHARED1 0x0120
#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
#define CLK_CON_MUX_MUX_CLKCMU_CORE_G3D 0x101c
#define CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS 0x1028
#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD 0x102c
#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD 0x1030
#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO 0x1034
#define CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD 0x1038
#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1058
#define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0 0x105c
#define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1 0x1060
#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART0 0x1064
#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART1 0x1068
#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART2 0x106c
#define CLK_CON_MUX_MUX_CLKCMU_PERI_USI0 0x1070
#define CLK_CON_MUX_MUX_CLKCMU_PERI_USI1 0x1074
#define CLK_CON_MUX_MUX_CLKCMU_PERI_USI2 0x1078
#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x181c
#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1820
#define CLK_CON_DIV_CLKCMU_CORE_G3D 0x1824
#define CLK_CON_DIV_CLKCMU_FSYS_BUS 0x1844
#define CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD 0x1848
#define CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD 0x184c
#define CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO 0x1850
#define CLK_CON_DIV_CLKCMU_FSYS_USB30DRD 0x1854
#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x1874
#define CLK_CON_DIV_CLKCMU_PERI_SPI0 0x1878
#define CLK_CON_DIV_CLKCMU_PERI_SPI1 0x187c
#define CLK_CON_DIV_CLKCMU_PERI_UART0 0x1880
#define CLK_CON_DIV_CLKCMU_PERI_UART1 0x1884
#define CLK_CON_DIV_CLKCMU_PERI_UART2 0x1888
#define CLK_CON_DIV_CLKCMU_PERI_USI0 0x188c
#define CLK_CON_DIV_CLKCMU_PERI_USI1 0x1890
#define CLK_CON_DIV_CLKCMU_PERI_USI2 0x1894
#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x189c
#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18a0
#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18a4
#define CLK_CON_DIV_PLL_SHARED0_DIV5 0x18a8
#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x18ac
#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x18b0
#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18b4
#define CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1 0x2004
#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
#define CLK_CON_GAT_GATE_CLKCMU_CORE_G3D 0x2024
#define CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS 0x2044
#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD 0x2048
#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD 0x204c
#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO 0x2050
#define CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD 0x2054
#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x207c
#define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0 0x2080
#define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1 0x2084
#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART0 0x2088
#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART2 0x208c
#define CLK_CON_GAT_GATE_CLKCMU_PERI_USI0 0x2090
#define CLK_CON_GAT_GATE_CLKCMU_PERI_USI1 0x2094
#define CLK_CON_GAT_GATE_CLKCMU_PERI_USI2 0x2098
static const unsigned long top_clk_regs[] __initconst = {
PLL_LOCKTIME_PLL_SHARED0,
PLL_LOCKTIME_PLL_SHARED1,
PLL_CON0_PLL_SHARED0,
PLL_CON0_PLL_SHARED1,
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
CLK_CON_MUX_MUX_CLKCMU_CORE_G3D,
CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS,
CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD,
CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD,
CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO,
CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD,
CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0,
CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1,
CLK_CON_MUX_MUX_CLKCMU_PERI_UART0,
CLK_CON_MUX_MUX_CLKCMU_PERI_UART1,
CLK_CON_MUX_MUX_CLKCMU_PERI_UART2,
CLK_CON_MUX_MUX_CLKCMU_PERI_USI0,
CLK_CON_MUX_MUX_CLKCMU_PERI_USI1,
CLK_CON_MUX_MUX_CLKCMU_PERI_USI2,
CLK_CON_DIV_CLKCMU_CORE_BUS,
CLK_CON_DIV_CLKCMU_CORE_CCI,
CLK_CON_DIV_CLKCMU_CORE_G3D,
CLK_CON_DIV_CLKCMU_FSYS_BUS,
CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD,
CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD,
CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO,
CLK_CON_DIV_CLKCMU_FSYS_USB30DRD,
CLK_CON_DIV_CLKCMU_PERI_BUS,
CLK_CON_DIV_CLKCMU_PERI_SPI0,
CLK_CON_DIV_CLKCMU_PERI_SPI1,
CLK_CON_DIV_CLKCMU_PERI_UART0,
CLK_CON_DIV_CLKCMU_PERI_UART1,
CLK_CON_DIV_CLKCMU_PERI_UART2,
CLK_CON_DIV_CLKCMU_PERI_USI0,
CLK_CON_DIV_CLKCMU_PERI_USI1,
CLK_CON_DIV_CLKCMU_PERI_USI2,
CLK_CON_DIV_PLL_SHARED0_DIV2,
CLK_CON_DIV_PLL_SHARED0_DIV3,
CLK_CON_DIV_PLL_SHARED0_DIV4,
CLK_CON_DIV_PLL_SHARED0_DIV5,
CLK_CON_DIV_PLL_SHARED1_DIV2,
CLK_CON_DIV_PLL_SHARED1_DIV3,
CLK_CON_DIV_PLL_SHARED1_DIV4,
CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1,
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
CLK_CON_GAT_GATE_CLKCMU_CORE_G3D,
CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS,
CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD,
CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD,
CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO,
CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD,
CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0,
CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1,
CLK_CON_GAT_GATE_CLKCMU_PERI_UART0,
CLK_CON_GAT_GATE_CLKCMU_PERI_UART2,
CLK_CON_GAT_GATE_CLKCMU_PERI_USI0,
CLK_CON_GAT_GATE_CLKCMU_PERI_USI1,
CLK_CON_GAT_GATE_CLKCMU_PERI_USI2,
};
static const struct samsung_pll_clock top_pll_clks[] __initconst = {
PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0,
NULL),
PLL(pll_1417x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED1, PLL_CON0_PLL_SHARED1,
NULL),
};
/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
PNAME(mout_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared0_div3", "dout_shared0_div3" };
PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared0_div3", "dout_shared0_div3" };
PNAME(mout_core_g3d_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared0_div3", "dout_shared0_div3" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
PNAME(mout_peri_spi0_p) = { "oscclk", "dout_shared0_div4" };
PNAME(mout_peri_spi1_p) = { "oscclk", "dout_shared0_div4" };
PNAME(mout_peri_uart0_p) = { "oscclk", "dout_shared0_div4" };
PNAME(mout_peri_uart1_p) = { "oscclk", "dout_shared0_div4" };
PNAME(mout_peri_uart2_p) = { "oscclk", "dout_shared0_div4" };
PNAME(mout_peri_usi0_p) = { "oscclk", "dout_shared0_div4" };
PNAME(mout_peri_usi1_p) = { "oscclk", "dout_shared0_div4" };
PNAME(mout_peri_usi2_p) = { "oscclk", "dout_shared0_div4" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_FSYS */
PNAME(mout_fsys_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" };
PNAME(mout_fsys_mmc_card_p) = { "dout_shared0_div2", "dout_shared1_div2" };
PNAME(mout_fsys_mmc_embd_p) = { "dout_shared0_div2", "dout_shared1_div2" };
PNAME(mout_fsys_mmc_sdio_p) = { "dout_shared0_div2", "dout_shared1_div2" };
PNAME(mout_fsys_usb30drd_p) = { "dout_shared0_div4", "dout_shared1_div4" };
static const struct samsung_mux_clock top_mux_clks[] __initconst = {
/* CORE */
MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p,
CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2),
MUX(CLK_MOUT_CORE_G3D, "mout_core_g3d", mout_core_g3d_p,
CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, 0, 2),
/* PERI */
MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
MUX(CLK_MOUT_PERI_SPI0, "mout_peri_spi0", mout_peri_spi0_p,
CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0, 0, 1),
MUX(CLK_MOUT_PERI_SPI1, "mout_peri_spi1", mout_peri_spi1_p,
CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1, 0, 1),
MUX(CLK_MOUT_PERI_UART0, "mout_peri_uart0", mout_peri_uart0_p,
CLK_CON_MUX_MUX_CLKCMU_PERI_UART0, 0, 1),
MUX(CLK_MOUT_PERI_UART1, "mout_peri_uart1", mout_peri_uart1_p,
CLK_CON_MUX_MUX_CLKCMU_PERI_UART1, 0, 1),
MUX(CLK_MOUT_PERI_UART2, "mout_peri_uart2", mout_peri_uart2_p,
CLK_CON_MUX_MUX_CLKCMU_PERI_UART2, 0, 1),
MUX(CLK_MOUT_PERI_USI0, "mout_peri_usi0", mout_peri_usi0_p,
CLK_CON_MUX_MUX_CLKCMU_PERI_USI0, 0, 1),
MUX(CLK_MOUT_PERI_USI1, "mout_peri_usi1", mout_peri_usi1_p,
CLK_CON_MUX_MUX_CLKCMU_PERI_USI1, 0, 1),
MUX(CLK_MOUT_PERI_USI2, "mout_peri_usi2", mout_peri_usi2_p,
CLK_CON_MUX_MUX_CLKCMU_PERI_USI2, 0, 1),
/* FSYS */
MUX(CLK_MOUT_FSYS_BUS, "mout_fsys_bus", mout_fsys_bus_p,
CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS, 0, 1),
MUX(CLK_MOUT_FSYS_MMC_CARD, "mout_fsys_mmc_card", mout_fsys_mmc_card_p,
CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD, 0, 1),
MUX(CLK_MOUT_FSYS_MMC_EMBD, "mout_fsys_mmc_embd", mout_fsys_mmc_embd_p,
CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD, 0, 1),
MUX(CLK_MOUT_FSYS_MMC_SDIO, "mout_fsys_mmc_sdio", mout_fsys_mmc_sdio_p,
CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO, 0, 1),
MUX(CLK_MOUT_FSYS_USB30DRD, "mout_fsys_usb30drd", mout_fsys_usb30drd_p,
CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD, 0, 1),
};
static const struct samsung_div_clock top_div_clks[] __initconst = {
/* TOP */
DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "fout_shared0_pll",
CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "fout_shared0_pll",
CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "fout_shared0_pll",
CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "fout_shared1_pll",
CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "fout_shared1_pll",
CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
/* CORE */
DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 3),
DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci",
CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 3),
DIV(CLK_DOUT_CORE_G3D, "dout_core_g3d", "gout_core_g3d",
CLK_CON_DIV_CLKCMU_CORE_G3D, 0, 3),
/* PERI */
DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "gout_peri_spi0",
CLK_CON_DIV_CLKCMU_PERI_SPI0, 0, 6),
DIV(CLK_DOUT_PERI_SPI1, "dout_peri_spi1", "gout_peri_spi1",
CLK_CON_DIV_CLKCMU_PERI_SPI1, 0, 6),
DIV(CLK_DOUT_PERI_UART0, "dout_peri_uart0", "gout_peri_uart0",
CLK_CON_DIV_CLKCMU_PERI_UART0, 0, 4),
DIV(CLK_DOUT_PERI_UART1, "dout_peri_uart1", "gout_peri_uart1",
CLK_CON_DIV_CLKCMU_PERI_UART1, 0, 4),
DIV(CLK_DOUT_PERI_UART2, "dout_peri_uart2", "gout_peri_uart2",
CLK_CON_DIV_CLKCMU_PERI_UART2, 0, 4),
DIV(CLK_DOUT_PERI_USI0, "dout_peri_usi0", "gout_peri_usi0",
CLK_CON_DIV_CLKCMU_PERI_USI0, 0, 4),
DIV(CLK_DOUT_PERI_USI1, "dout_peri_usi1", "gout_peri_usi1",
CLK_CON_DIV_CLKCMU_PERI_USI1, 0, 4),
DIV(CLK_DOUT_PERI_USI2, "dout_peri_usi2", "gout_peri_usi2",
CLK_CON_DIV_CLKCMU_PERI_USI2, 0, 4),
/* FSYS */
DIV(CLK_DOUT_FSYS_BUS, "dout_fsys_bus", "gout_fsys_bus",
CLK_CON_DIV_CLKCMU_FSYS_BUS, 0, 4),
DIV(CLK_DOUT_FSYS_MMC_CARD, "dout_fsys_mmc_card", "gout_fsys_mmc_card",
CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD, 0, 9),
DIV(CLK_DOUT_FSYS_MMC_EMBD, "dout_fsys_mmc_embd", "gout_fsys_mmc_embd",
CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD, 0, 9),
DIV(CLK_DOUT_FSYS_MMC_SDIO, "dout_fsys_mmc_sdio", "gout_fsys_mmc_sdio",
CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO, 0, 9),
DIV(CLK_DOUT_FSYS_USB30DRD, "dout_fsys_usb30drd", "gout_fsys_usb30drd",
CLK_CON_DIV_CLKCMU_FSYS_USB30DRD, 0, 4),
};
static const struct samsung_gate_clock top_gate_clks[] __initconst = {
/* CORE */
GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus",
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci",
CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0),
GATE(CLK_GOUT_CORE_G3D, "gout_core_g3d", "mout_core_g3d",
CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, 21, 0, 0),
/* PERI */
GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
GATE(CLK_GOUT_PERI_SPI0, "gout_peri_spi0", "mout_peri_spi0",
CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0, 21, 0, 0),
GATE(CLK_GOUT_PERI_SPI1, "gout_peri_spi1", "mout_peri_spi1",
CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1, 21, 0, 0),
GATE(CLK_GOUT_PERI_UART0, "gout_peri_uart0", "mout_peri_uart0",
CLK_CON_GAT_GATE_CLKCMU_PERI_UART0, 21, 0, 0),
GATE(CLK_GOUT_PERI_UART1, "gout_peri_uart1", "mout_peri_uart1",
CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1, 21, 0, 0),
GATE(CLK_GOUT_PERI_UART2, "gout_peri_uart2", "mout_peri_uart2",
CLK_CON_GAT_GATE_CLKCMU_PERI_UART2, 21, 0, 0),
GATE(CLK_GOUT_PERI_USI0, "gout_peri_usi0", "mout_peri_usi0",
CLK_CON_GAT_GATE_CLKCMU_PERI_USI0, 21, 0, 0),
GATE(CLK_GOUT_PERI_USI1, "gout_peri_usi1", "mout_peri_usi1",
CLK_CON_GAT_GATE_CLKCMU_PERI_USI1, 21, 0, 0),
GATE(CLK_GOUT_PERI_USI2, "gout_peri_usi2", "mout_peri_usi2",
CLK_CON_GAT_GATE_CLKCMU_PERI_USI2, 21, 0, 0),
/* FSYS */
GATE(CLK_GOUT_FSYS_BUS, "gout_fsys_bus", "mout_fsys_bus",
CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS, 21, 0, 0),
GATE(CLK_GOUT_FSYS_MMC_CARD, "gout_fsys_mmc_card", "mout_fsys_mmc_card",
CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD, 21, 0, 0),
GATE(CLK_GOUT_FSYS_MMC_EMBD, "gout_fsys_mmc_embd", "mout_fsys_mmc_embd",
CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD, 21, 0, 0),
GATE(CLK_GOUT_FSYS_MMC_SDIO, "gout_fsys_mmc_sdio", "mout_fsys_mmc_sdio",
CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO, 21, 0, 0),
GATE(CLK_GOUT_FSYS_USB30DRD, "gout_fsys_usb30drd", "mout_fsys_usb30drd",
CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD, 21, 0, 0),
};
static const struct samsung_cmu_info top_cmu_info __initconst = {
.pll_clks = top_pll_clks,
.nr_pll_clks = ARRAY_SIZE(top_pll_clks),
.mux_clks = top_mux_clks,
.nr_mux_clks = ARRAY_SIZE(top_mux_clks),
.div_clks = top_div_clks,
.nr_div_clks = ARRAY_SIZE(top_div_clks),
.gate_clks = top_gate_clks,
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
.nr_clk_ids = CLKS_NR_TOP,
.clk_regs = top_clk_regs,
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
};
static void __init exynos7885_cmu_top_init(struct device_node *np)
{
exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
}
/* Register CMU_TOP early, as it's a dependency for other early domains */
CLK_OF_DECLARE(exynos7885_cmu_top, "samsung,exynos7885-cmu-top",
exynos7885_cmu_top_init);
/* ---- CMU_PERI ------------------------------------------------------------ */
/* Register Offset definitions for CMU_PERI (0x10010000) */
#define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0100
#define PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER 0x0120
#define PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER 0x0140
#define PLL_CON0_MUX_CLKCMU_PERI_UART0_USER 0x0160
#define PLL_CON0_MUX_CLKCMU_PERI_UART1_USER 0x0180
#define PLL_CON0_MUX_CLKCMU_PERI_UART2_USER 0x01a0
#define PLL_CON0_MUX_CLKCMU_PERI_USI0_USER 0x01c0
#define PLL_CON0_MUX_CLKCMU_PERI_USI1_USER 0x01e0
#define PLL_CON0_MUX_CLKCMU_PERI_USI2_USER 0x0200
#define CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK 0x2024
#define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028
#define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x202c
#define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2030
#define CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK 0x2034
#define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x2038
#define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x203c
#define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2040
#define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2044
#define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x2048
#define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x204c
#define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2050
#define CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK 0x2054
#define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2058
#define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x205c
#define CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK 0x2060
#define CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK 0x2064
#define CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK 0x2068
#define CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK 0x206c
#define CLK_CON_GAT_GOUT_PERI_UART_0_PCLK 0x2070
#define CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK 0x2074
#define CLK_CON_GAT_GOUT_PERI_UART_1_PCLK 0x2078
#define CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK 0x207c
#define CLK_CON_GAT_GOUT_PERI_UART_2_PCLK 0x2080
#define CLK_CON_GAT_GOUT_PERI_USI0_PCLK 0x2084
#define CLK_CON_GAT_GOUT_PERI_USI0_SCLK 0x2088
#define CLK_CON_GAT_GOUT_PERI_USI1_PCLK 0x208c
#define CLK_CON_GAT_GOUT_PERI_USI1_SCLK 0x2090
#define CLK_CON_GAT_GOUT_PERI_USI2_PCLK 0x2094
#define CLK_CON_GAT_GOUT_PERI_USI2_SCLK 0x2098
#define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x20a0
#define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20b0
#define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK 0x20b4
#define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK 0x20b8
static const unsigned long peri_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_PERI_BUS_USER,
PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER,
PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER,
PLL_CON0_MUX_CLKCMU_PERI_UART0_USER,
PLL_CON0_MUX_CLKCMU_PERI_UART1_USER,
PLL_CON0_MUX_CLKCMU_PERI_UART2_USER,
PLL_CON0_MUX_CLKCMU_PERI_USI0_USER,
PLL_CON0_MUX_CLKCMU_PERI_USI1_USER,
PLL_CON0_MUX_CLKCMU_PERI_USI2_USER,
CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK,
CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK,
CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK,
CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK,
CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK,
CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK,
CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK,
CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK,
CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK,
CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK,
CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK,
CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK,
CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK,
CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK,
CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK,
CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK,
CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK,
CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK,
CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK,
CLK_CON_GAT_GOUT_PERI_UART_0_PCLK,
CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK,
CLK_CON_GAT_GOUT_PERI_UART_1_PCLK,
CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK,
CLK_CON_GAT_GOUT_PERI_UART_2_PCLK,
CLK_CON_GAT_GOUT_PERI_USI0_PCLK,
CLK_CON_GAT_GOUT_PERI_USI0_SCLK,
CLK_CON_GAT_GOUT_PERI_USI1_PCLK,
CLK_CON_GAT_GOUT_PERI_USI1_SCLK,
CLK_CON_GAT_GOUT_PERI_USI2_PCLK,
CLK_CON_GAT_GOUT_PERI_USI2_SCLK,
CLK_CON_GAT_GOUT_PERI_MCT_PCLK,
CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK,
CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK,
CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK,
};
/* List of parent clocks for Muxes in CMU_PERI */
PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" };
PNAME(mout_peri_spi0_user_p) = { "oscclk", "dout_peri_spi0" };
PNAME(mout_peri_spi1_user_p) = { "oscclk", "dout_peri_spi1" };
PNAME(mout_peri_uart0_user_p) = { "oscclk", "dout_peri_uart0" };
PNAME(mout_peri_uart1_user_p) = { "oscclk", "dout_peri_uart1" };
PNAME(mout_peri_uart2_user_p) = { "oscclk", "dout_peri_uart2" };
PNAME(mout_peri_usi0_user_p) = { "oscclk", "dout_peri_usi0" };
PNAME(mout_peri_usi1_user_p) = { "oscclk", "dout_peri_usi1" };
PNAME(mout_peri_usi2_user_p) = { "oscclk", "dout_peri_usi2" };
static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p,
PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1),
MUX(CLK_MOUT_PERI_SPI0_USER, "mout_peri_spi0_user", mout_peri_spi0_user_p,
PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER, 4, 1),
MUX(CLK_MOUT_PERI_SPI1_USER, "mout_peri_spi1_user", mout_peri_spi1_user_p,
PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER, 4, 1),
MUX(CLK_MOUT_PERI_UART0_USER, "mout_peri_uart0_user",
mout_peri_uart0_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART0_USER, 4, 1),
MUX(CLK_MOUT_PERI_UART1_USER, "mout_peri_uart1_user",
mout_peri_uart1_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART1_USER, 4, 1),
MUX(CLK_MOUT_PERI_UART2_USER, "mout_peri_uart2_user",
mout_peri_uart2_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART2_USER, 4, 1),
MUX(CLK_MOUT_PERI_USI0_USER, "mout_peri_usi0_user",
mout_peri_usi0_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI0_USER, 4, 1),
MUX(CLK_MOUT_PERI_USI1_USER, "mout_peri_usi1_user",
mout_peri_usi1_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI1_USER, 4, 1),
MUX(CLK_MOUT_PERI_USI2_USER, "mout_peri_usi2_user",
mout_peri_usi2_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI2_USER, 4, 1),
};
static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
/* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
GATE(CLK_GOUT_GPIO_TOP_PCLK, "gout_gpio_top_pclk",
"mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0),
GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0),
GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0),
GATE(CLK_GOUT_HSI2C3_PCLK, "gout_hsi2c3_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK, 21, 0, 0),
GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0),
GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0),
GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0),
GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0),
GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0),
GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0),
GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0),
GATE(CLK_GOUT_I2C7_PCLK, "gout_i2c7_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK, 21, 0, 0),
GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk",
"mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0),
GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0),
GATE(CLK_GOUT_SPI0_EXT_CLK, "gout_spi0_ipclk", "mout_peri_spi0_user",
CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK, 21, 0, 0),
GATE(CLK_GOUT_SPI1_PCLK, "gout_spi1_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK, 21, 0, 0),
GATE(CLK_GOUT_SPI1_EXT_CLK, "gout_spi1_ipclk", "mout_peri_spi1_user",
CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK, 21, 0, 0),
GATE(CLK_GOUT_UART0_EXT_UCLK, "gout_uart0_ext_uclk", "mout_peri_uart0_user",
CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK, 21, 0, 0),
GATE(CLK_GOUT_UART0_PCLK, "gout_uart0_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_UART_0_PCLK, 21, 0, 0),
GATE(CLK_GOUT_UART1_EXT_UCLK, "gout_uart1_ext_uclk", "mout_peri_uart1_user",
CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK, 21, 0, 0),
GATE(CLK_GOUT_UART1_PCLK, "gout_uart1_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_UART_1_PCLK, 21, 0, 0),
GATE(CLK_GOUT_UART2_EXT_UCLK, "gout_uart2_ext_uclk", "mout_peri_uart2_user",
CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK, 21, 0, 0),
GATE(CLK_GOUT_UART2_PCLK, "gout_uart2_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_UART_2_PCLK, 21, 0, 0),
GATE(CLK_GOUT_USI0_PCLK, "gout_usi0_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_USI0_PCLK, 21, 0, 0),
GATE(CLK_GOUT_USI0_SCLK, "gout_usi0_sclk", "mout_peri_usi0_user",
CLK_CON_GAT_GOUT_PERI_USI0_SCLK, 21, 0, 0),
GATE(CLK_GOUT_USI1_PCLK, "gout_usi1_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_USI1_PCLK, 21, 0, 0),
GATE(CLK_GOUT_USI1_SCLK, "gout_usi1_sclk", "mout_peri_usi1_user",
CLK_CON_GAT_GOUT_PERI_USI1_SCLK, 21, 0, 0),
GATE(CLK_GOUT_USI2_PCLK, "gout_usi2_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_USI2_PCLK, 21, 0, 0),
GATE(CLK_GOUT_USI2_SCLK, "gout_usi2_sclk", "mout_peri_usi2_user",
CLK_CON_GAT_GOUT_PERI_USI2_SCLK, 21, 0, 0),
GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0),
GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk",
"mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0),
GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK, 21, 0, 0),
GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK, 21, 0, 0),
};
static const struct samsung_cmu_info peri_cmu_info __initconst = {
.mux_clks = peri_mux_clks,
.nr_mux_clks = ARRAY_SIZE(peri_mux_clks),
.gate_clks = peri_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
.nr_clk_ids = CLKS_NR_PERI,
.clk_regs = peri_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
.clk_name = "dout_peri_bus",
};
static void __init exynos7885_cmu_peri_init(struct device_node *np)
{
exynos_arm64_register_cmu(NULL, np, &peri_cmu_info);
}
/* Register CMU_PERI early, as it's needed for MCT timer */
CLK_OF_DECLARE(exynos7885_cmu_peri, "samsung,exynos7885-cmu-peri",
exynos7885_cmu_peri_init);
/* ---- CMU_CORE ------------------------------------------------------------ */
/* Register Offset definitions for CMU_CORE (0x12000000) */
#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0100
#define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0120
#define PLL_CON0_MUX_CLKCMU_CORE_G3D_USER 0x0140
#define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000
#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
#define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2054
#define CLK_CON_GAT_GOUT_CORE_GIC400_CLK 0x2058
#define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK 0x215c
#define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK 0x2160
#define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK 0x2164
#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE 0x2168
#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE 0x216c
#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK 0x2170
#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE 0x2174
static const unsigned long core_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
PLL_CON0_MUX_CLKCMU_CORE_CCI_USER,
PLL_CON0_MUX_CLKCMU_CORE_G3D_USER,
CLK_CON_MUX_MUX_CLK_CORE_GIC,
CLK_CON_DIV_DIV_CLK_CORE_BUSP,
CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK,
CLK_CON_GAT_GOUT_CORE_GIC400_CLK,
CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK,
CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK,
CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK,
CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE,
CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE,
CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK,
CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE,
};
/* List of parent clocks for Muxes in CMU_CORE */
PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" };
PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" };
PNAME(mout_core_g3d_user_p) = { "oscclk", "dout_core_g3d" };
PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" };
static const struct samsung_mux_clock core_mux_clks[] __initconst = {
MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p,
PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1),
MUX(CLK_MOUT_CORE_G3D_USER, "mout_core_g3d_user", mout_core_g3d_user_p,
PLL_CON0_MUX_CLKCMU_CORE_G3D_USER, 4, 1),
MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p,
CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1),
};
static const struct samsung_div_clock core_div_clks[] __initconst = {
DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2),
};
static const struct samsung_gate_clock core_gate_clks[] __initconst = {
/* CCI (interconnect) clock must be always running */
GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user",
CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0),
/* GIC (interrupt controller) clock must be always running */
GATE(CLK_GOUT_GIC400_CLK, "gout_gic400_clk", "mout_core_gic",
CLK_CON_GAT_GOUT_CORE_GIC400_CLK, 21, CLK_IS_CRITICAL, 0),
/*
* TREX D and P Core (seems to be related to "bus traffic shaper")
* clocks must always be running
*/
GATE(CLK_GOUT_TREX_D_CORE_ACLK, "gout_trex_d_core_aclk", "mout_core_bus_user",
CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_TREX_D_CORE_GCLK, "gout_trex_d_core_gclk", "mout_core_g3d_user",
CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_TREX_D_CORE_PCLK, "gout_trex_d_core_pclk", "dout_core_busp",
CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_TREX_P_CORE_ACLK_P_CORE, "gout_trex_p_core_aclk_p_core",
"mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE, 21,
CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_TREX_P_CORE_CCLK_P_CORE, "gout_trex_p_core_cclk_p_core",
"mout_core_cci_user", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE, 21,
CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_TREX_P_CORE_PCLK, "gout_trex_p_core_pclk", "dout_core_busp",
CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_TREX_P_CORE_PCLK_P_CORE, "gout_trex_p_core_pclk_p_core",
"dout_core_busp", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE, 21,
CLK_IS_CRITICAL, 0),
};
static const struct samsung_cmu_info core_cmu_info __initconst = {
.mux_clks = core_mux_clks,
.nr_mux_clks = ARRAY_SIZE(core_mux_clks),
.div_clks = core_div_clks,
.nr_div_clks = ARRAY_SIZE(core_div_clks),
.gate_clks = core_gate_clks,
.nr_gate_clks = ARRAY_SIZE(core_gate_clks),
.nr_clk_ids = CLKS_NR_CORE,
.clk_regs = core_clk_regs,
.nr_clk_regs = ARRAY_SIZE(core_clk_regs),
.clk_name = "dout_core_bus",
};
/* ---- CMU_FSYS ------------------------------------------------------------ */
/* Register Offset definitions for CMU_FSYS (0x13400000) */
#define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER 0x0100
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER 0x0120
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER 0x0140
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER 0x0160
#define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER 0x0180
#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK 0x2030
#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN 0x2034
#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK 0x2038
#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN 0x203c
#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK 0x2040
#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN 0x2044
static const unsigned long fsys_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER,
PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER,
PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER,
PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,
PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,
CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK,
CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN,
CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK,
CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN,
CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK,
CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,
};
/* List of parent clocks for Muxes in CMU_FSYS */
PNAME(mout_fsys_bus_user_p) = { "oscclk", "dout_fsys_bus" };
PNAME(mout_fsys_mmc_card_user_p) = { "oscclk", "dout_fsys_mmc_card" };
PNAME(mout_fsys_mmc_embd_user_p) = { "oscclk", "dout_fsys_mmc_embd" };
PNAME(mout_fsys_mmc_sdio_user_p) = { "oscclk", "dout_fsys_mmc_sdio" };
PNAME(mout_fsys_usb30drd_user_p) = { "oscclk", "dout_fsys_usb30drd" };
static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
MUX(CLK_MOUT_FSYS_BUS_USER, "mout_fsys_bus_user", mout_fsys_bus_user_p,
PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER, 4, 1),
MUX_F(CLK_MOUT_FSYS_MMC_CARD_USER, "mout_fsys_mmc_card_user",
mout_fsys_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER,
4, 1, CLK_SET_RATE_PARENT, 0),
MUX_F(CLK_MOUT_FSYS_MMC_EMBD_USER, "mout_fsys_mmc_embd_user",
mout_fsys_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER,
4, 1, CLK_SET_RATE_PARENT, 0),
MUX_F(CLK_MOUT_FSYS_MMC_SDIO_USER, "mout_fsys_mmc_sdio_user",
mout_fsys_mmc_sdio_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,
4, 1, CLK_SET_RATE_PARENT, 0),
MUX_F(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user",
mout_fsys_usb30drd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,
4, 1, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_fsys_bus_user",
CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK, 21, 0, 0),
GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
"mout_fsys_mmc_card_user", CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN,
21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "mout_fsys_bus_user",
CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK, 21, 0, 0),
GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin",
"mout_fsys_mmc_embd_user", CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN,
21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_MMC_SDIO_ACLK, "gout_mmc_sdio_aclk", "mout_fsys_bus_user",
CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK, 21, 0, 0),
GATE(CLK_GOUT_MMC_SDIO_SDCLKIN, "gout_mmc_sdio_sdclkin",
"mout_fsys_mmc_sdio_user", CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,
21, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_cmu_info fsys_cmu_info __initconst = {
.mux_clks = fsys_mux_clks,
.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
.gate_clks = fsys_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
.nr_clk_ids = CLKS_NR_FSYS,
.clk_regs = fsys_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
.clk_name = "dout_fsys_bus",
};
/* ---- platform_driver ----------------------------------------------------- */
static int __init exynos7885_cmu_probe(struct platform_device *pdev)
{
const struct samsung_cmu_info *info;
struct device *dev = &pdev->dev;
info = of_device_get_match_data(dev);
exynos_arm64_register_cmu(dev, dev->of_node, info);
return 0;
}
static const struct of_device_id exynos7885_cmu_of_match[] = {
{
.compatible = "samsung,exynos7885-cmu-core",
.data = &core_cmu_info,
}, {
.compatible = "samsung,exynos7885-cmu-fsys",
.data = &fsys_cmu_info,
}, {
},
};
static struct platform_driver exynos7885_cmu_driver __refdata = {
.driver = {
.name = "exynos7885-cmu",
.of_match_table = exynos7885_cmu_of_match,
.suppress_bind_attrs = true,
},
.probe = exynos7885_cmu_probe,
};
static int __init exynos7885_cmu_init(void)
{
return platform_driver_register(&exynos7885_cmu_driver);
}
core_initcall(exynos7885_cmu_init);
| linux-master | drivers/clk/samsung/clk-exynos7885.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Copyright (c) 2013 Linaro Ltd.
*
* This file contains the utility functions to register the pll clocks.
*/
#include <linux/errno.h>
#include <linux/hrtimer.h>
#include <linux/iopoll.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/timekeeping.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include "clk.h"
#include "clk-pll.h"
#define PLL_TIMEOUT_US 20000U
#define PLL_TIMEOUT_LOOPS 1000000U
struct samsung_clk_pll {
struct clk_hw hw;
void __iomem *lock_reg;
void __iomem *con_reg;
/* PLL enable control bit offset in @con_reg register */
unsigned short enable_offs;
/* PLL lock status bit offset in @con_reg register */
unsigned short lock_offs;
enum samsung_pll_type type;
unsigned int rate_count;
const struct samsung_pll_rate_table *rate_table;
};
#define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
static const struct samsung_pll_rate_table *samsung_get_pll_settings(
struct samsung_clk_pll *pll, unsigned long rate)
{
const struct samsung_pll_rate_table *rate_table = pll->rate_table;
int i;
for (i = 0; i < pll->rate_count; i++) {
if (rate == rate_table[i].rate)
return &rate_table[i];
}
return NULL;
}
static long samsung_pll_round_rate(struct clk_hw *hw,
unsigned long drate, unsigned long *prate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
const struct samsung_pll_rate_table *rate_table = pll->rate_table;
int i;
/* Assumming rate_table is in descending order */
for (i = 0; i < pll->rate_count; i++) {
if (drate >= rate_table[i].rate)
return rate_table[i].rate;
}
/* return minimum supported value */
return rate_table[i - 1].rate;
}
static bool pll_early_timeout = true;
static int __init samsung_pll_disable_early_timeout(void)
{
pll_early_timeout = false;
return 0;
}
arch_initcall(samsung_pll_disable_early_timeout);
/* Wait until the PLL is locked */
static int samsung_pll_lock_wait(struct samsung_clk_pll *pll,
unsigned int reg_mask)
{
int i, ret;
u32 val;
/*
* This function might be called when the timekeeping API can't be used
* to detect timeouts. One situation is when the clocksource is not yet
* initialized, another when the timekeeping is suspended. udelay() also
* cannot be used when the clocksource is not running on arm64, since
* the current timer is used as cycle counter. So a simple busy loop
* is used here in that special cases. The limit of iterations has been
* derived from experimental measurements of various PLLs on multiple
* Exynos SoC variants. Single register read time was usually in range
* 0.4...1.5 us, never less than 0.4 us.
*/
if (pll_early_timeout || timekeeping_suspended) {
i = PLL_TIMEOUT_LOOPS;
while (i-- > 0) {
if (readl_relaxed(pll->con_reg) & reg_mask)
return 0;
cpu_relax();
}
ret = -ETIMEDOUT;
} else {
ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val,
val & reg_mask, 0, PLL_TIMEOUT_US);
}
if (ret < 0)
pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw));
return ret;
}
static int samsung_pll3xxx_enable(struct clk_hw *hw)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 tmp;
tmp = readl_relaxed(pll->con_reg);
tmp |= BIT(pll->enable_offs);
writel_relaxed(tmp, pll->con_reg);
return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
}
static void samsung_pll3xxx_disable(struct clk_hw *hw)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 tmp;
tmp = readl_relaxed(pll->con_reg);
tmp &= ~BIT(pll->enable_offs);
writel_relaxed(tmp, pll->con_reg);
}
/*
* PLL2126 Clock Type
*/
#define PLL2126_MDIV_MASK (0xff)
#define PLL2126_PDIV_MASK (0x3f)
#define PLL2126_SDIV_MASK (0x3)
#define PLL2126_MDIV_SHIFT (16)
#define PLL2126_PDIV_SHIFT (8)
#define PLL2126_SDIV_SHIFT (0)
static unsigned long samsung_pll2126_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 pll_con, mdiv, pdiv, sdiv;
u64 fvco = parent_rate;
pll_con = readl_relaxed(pll->con_reg);
mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK;
pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK;
sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK;
fvco *= (mdiv + 8);
do_div(fvco, (pdiv + 2) << sdiv);
return (unsigned long)fvco;
}
static const struct clk_ops samsung_pll2126_clk_ops = {
.recalc_rate = samsung_pll2126_recalc_rate,
};
/*
* PLL3000 Clock Type
*/
#define PLL3000_MDIV_MASK (0xff)
#define PLL3000_PDIV_MASK (0x3)
#define PLL3000_SDIV_MASK (0x3)
#define PLL3000_MDIV_SHIFT (16)
#define PLL3000_PDIV_SHIFT (8)
#define PLL3000_SDIV_SHIFT (0)
static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 pll_con, mdiv, pdiv, sdiv;
u64 fvco = parent_rate;
pll_con = readl_relaxed(pll->con_reg);
mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK;
pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK;
sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK;
fvco *= (2 * (mdiv + 8));
do_div(fvco, pdiv << sdiv);
return (unsigned long)fvco;
}
static const struct clk_ops samsung_pll3000_clk_ops = {
.recalc_rate = samsung_pll3000_recalc_rate,
};
/*
* PLL35xx Clock Type
*/
/* Maximum lock time can be 270 * PDIV cycles */
#define PLL35XX_LOCK_FACTOR (270)
#define PLL35XX_MDIV_MASK (0x3FF)
#define PLL35XX_PDIV_MASK (0x3F)
#define PLL35XX_SDIV_MASK (0x7)
#define PLL35XX_MDIV_SHIFT (16)
#define PLL35XX_PDIV_SHIFT (8)
#define PLL35XX_SDIV_SHIFT (0)
#define PLL35XX_LOCK_STAT_SHIFT (29)
#define PLL35XX_ENABLE_SHIFT (31)
static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 mdiv, pdiv, sdiv, pll_con;
u64 fvco = parent_rate;
pll_con = readl_relaxed(pll->con_reg);
mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
fvco *= mdiv;
do_div(fvco, (pdiv << sdiv));
return (unsigned long)fvco;
}
static inline bool samsung_pll35xx_mp_change(
const struct samsung_pll_rate_table *rate, u32 pll_con)
{
u32 old_mdiv, old_pdiv;
old_mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
old_pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv);
}
static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
unsigned long prate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
const struct samsung_pll_rate_table *rate;
u32 tmp;
/* Get required rate settings from table */
rate = samsung_get_pll_settings(pll, drate);
if (!rate) {
pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
drate, clk_hw_get_name(hw));
return -EINVAL;
}
tmp = readl_relaxed(pll->con_reg);
if (!(samsung_pll35xx_mp_change(rate, tmp))) {
/* If only s change, change just s value only*/
tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT);
tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT;
writel_relaxed(tmp, pll->con_reg);
return 0;
}
/* Set PLL lock time. */
writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
pll->lock_reg);
/* Change PLL PMS values */
tmp &= ~((PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) |
(PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT) |
(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT));
tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) |
(rate->pdiv << PLL35XX_PDIV_SHIFT) |
(rate->sdiv << PLL35XX_SDIV_SHIFT);
writel_relaxed(tmp, pll->con_reg);
/* Wait for PLL lock if the PLL is enabled */
if (tmp & BIT(pll->enable_offs))
return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
return 0;
}
static const struct clk_ops samsung_pll35xx_clk_ops = {
.recalc_rate = samsung_pll35xx_recalc_rate,
.round_rate = samsung_pll_round_rate,
.set_rate = samsung_pll35xx_set_rate,
.enable = samsung_pll3xxx_enable,
.disable = samsung_pll3xxx_disable,
};
static const struct clk_ops samsung_pll35xx_clk_min_ops = {
.recalc_rate = samsung_pll35xx_recalc_rate,
};
/*
* PLL36xx Clock Type
*/
/* Maximum lock time can be 3000 * PDIV cycles */
#define PLL36XX_LOCK_FACTOR (3000)
#define PLL36XX_KDIV_MASK (0xFFFF)
#define PLL36XX_MDIV_MASK (0x1FF)
#define PLL36XX_PDIV_MASK (0x3F)
#define PLL36XX_SDIV_MASK (0x7)
#define PLL36XX_MDIV_SHIFT (16)
#define PLL36XX_PDIV_SHIFT (8)
#define PLL36XX_SDIV_SHIFT (0)
#define PLL36XX_KDIV_SHIFT (0)
#define PLL36XX_LOCK_STAT_SHIFT (29)
#define PLL36XX_ENABLE_SHIFT (31)
static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
s16 kdiv;
u64 fvco = parent_rate;
pll_con0 = readl_relaxed(pll->con_reg);
pll_con1 = readl_relaxed(pll->con_reg + 4);
mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
kdiv = (s16)(pll_con1 & PLL36XX_KDIV_MASK);
fvco *= (mdiv << 16) + kdiv;
do_div(fvco, (pdiv << sdiv));
fvco >>= 16;
return (unsigned long)fvco;
}
static inline bool samsung_pll36xx_mpk_change(
const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1)
{
u32 old_mdiv, old_pdiv, old_kdiv;
old_mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
old_pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
old_kdiv = (pll_con1 >> PLL36XX_KDIV_SHIFT) & PLL36XX_KDIV_MASK;
return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
rate->kdiv != old_kdiv);
}
static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
unsigned long parent_rate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 pll_con0, pll_con1;
const struct samsung_pll_rate_table *rate;
rate = samsung_get_pll_settings(pll, drate);
if (!rate) {
pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
drate, clk_hw_get_name(hw));
return -EINVAL;
}
pll_con0 = readl_relaxed(pll->con_reg);
pll_con1 = readl_relaxed(pll->con_reg + 4);
if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) {
/* If only s change, change just s value only*/
pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT);
pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT);
writel_relaxed(pll_con0, pll->con_reg);
return 0;
}
/* Set PLL lock time. */
writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg);
/* Change PLL PMS values */
pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) |
(PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT) |
(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT));
pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) |
(rate->pdiv << PLL36XX_PDIV_SHIFT) |
(rate->sdiv << PLL36XX_SDIV_SHIFT);
writel_relaxed(pll_con0, pll->con_reg);
pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT);
pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT;
writel_relaxed(pll_con1, pll->con_reg + 4);
if (pll_con0 & BIT(pll->enable_offs))
return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
return 0;
}
static const struct clk_ops samsung_pll36xx_clk_ops = {
.recalc_rate = samsung_pll36xx_recalc_rate,
.set_rate = samsung_pll36xx_set_rate,
.round_rate = samsung_pll_round_rate,
.enable = samsung_pll3xxx_enable,
.disable = samsung_pll3xxx_disable,
};
static const struct clk_ops samsung_pll36xx_clk_min_ops = {
.recalc_rate = samsung_pll36xx_recalc_rate,
};
/*
* PLL0822x Clock Type
*/
/* Maximum lock time can be 150 * PDIV cycles */
#define PLL0822X_LOCK_FACTOR (150)
#define PLL0822X_MDIV_MASK (0x3FF)
#define PLL0822X_PDIV_MASK (0x3F)
#define PLL0822X_SDIV_MASK (0x7)
#define PLL0822X_MDIV_SHIFT (16)
#define PLL0822X_PDIV_SHIFT (8)
#define PLL0822X_SDIV_SHIFT (0)
#define PLL0822X_LOCK_STAT_SHIFT (29)
#define PLL0822X_ENABLE_SHIFT (31)
static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 mdiv, pdiv, sdiv, pll_con3;
u64 fvco = parent_rate;
pll_con3 = readl_relaxed(pll->con_reg);
mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK;
pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
fvco *= mdiv;
do_div(fvco, (pdiv << sdiv));
return (unsigned long)fvco;
}
static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate,
unsigned long prate)
{
const struct samsung_pll_rate_table *rate;
struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 pll_con3;
/* Get required rate settings from table */
rate = samsung_get_pll_settings(pll, drate);
if (!rate) {
pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
drate, clk_hw_get_name(hw));
return -EINVAL;
}
/* Change PLL PMS values */
pll_con3 = readl_relaxed(pll->con_reg);
pll_con3 &= ~((PLL0822X_MDIV_MASK << PLL0822X_MDIV_SHIFT) |
(PLL0822X_PDIV_MASK << PLL0822X_PDIV_SHIFT) |
(PLL0822X_SDIV_MASK << PLL0822X_SDIV_SHIFT));
pll_con3 |= (rate->mdiv << PLL0822X_MDIV_SHIFT) |
(rate->pdiv << PLL0822X_PDIV_SHIFT) |
(rate->sdiv << PLL0822X_SDIV_SHIFT);
/* Set PLL lock time */
writel_relaxed(rate->pdiv * PLL0822X_LOCK_FACTOR,
pll->lock_reg);
/* Write PMS values */
writel_relaxed(pll_con3, pll->con_reg);
/* Wait for PLL lock if the PLL is enabled */
if (pll_con3 & BIT(pll->enable_offs))
return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
return 0;
}
static const struct clk_ops samsung_pll0822x_clk_ops = {
.recalc_rate = samsung_pll0822x_recalc_rate,
.round_rate = samsung_pll_round_rate,
.set_rate = samsung_pll0822x_set_rate,
.enable = samsung_pll3xxx_enable,
.disable = samsung_pll3xxx_disable,
};
static const struct clk_ops samsung_pll0822x_clk_min_ops = {
.recalc_rate = samsung_pll0822x_recalc_rate,
};
/*
* PLL0831x Clock Type
*/
/* Maximum lock time can be 500 * PDIV cycles */
#define PLL0831X_LOCK_FACTOR (500)
#define PLL0831X_KDIV_MASK (0xFFFF)
#define PLL0831X_MDIV_MASK (0x1FF)
#define PLL0831X_PDIV_MASK (0x3F)
#define PLL0831X_SDIV_MASK (0x7)
#define PLL0831X_MDIV_SHIFT (16)
#define PLL0831X_PDIV_SHIFT (8)
#define PLL0831X_SDIV_SHIFT (0)
#define PLL0831X_KDIV_SHIFT (0)
#define PLL0831X_LOCK_STAT_SHIFT (29)
#define PLL0831X_ENABLE_SHIFT (31)
static unsigned long samsung_pll0831x_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 mdiv, pdiv, sdiv, pll_con3, pll_con5;
s16 kdiv;
u64 fvco = parent_rate;
pll_con3 = readl_relaxed(pll->con_reg);
pll_con5 = readl_relaxed(pll->con_reg + 8);
mdiv = (pll_con3 >> PLL0831X_MDIV_SHIFT) & PLL0831X_MDIV_MASK;
pdiv = (pll_con3 >> PLL0831X_PDIV_SHIFT) & PLL0831X_PDIV_MASK;
sdiv = (pll_con3 >> PLL0831X_SDIV_SHIFT) & PLL0831X_SDIV_MASK;
kdiv = (s16)((pll_con5 >> PLL0831X_KDIV_SHIFT) & PLL0831X_KDIV_MASK);
fvco *= (mdiv << 16) + kdiv;
do_div(fvco, (pdiv << sdiv));
fvco >>= 16;
return (unsigned long)fvco;
}
static int samsung_pll0831x_set_rate(struct clk_hw *hw, unsigned long drate,
unsigned long parent_rate)
{
const struct samsung_pll_rate_table *rate;
struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 pll_con3, pll_con5;
/* Get required rate settings from table */
rate = samsung_get_pll_settings(pll, drate);
if (!rate) {
pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
drate, clk_hw_get_name(hw));
return -EINVAL;
}
pll_con3 = readl_relaxed(pll->con_reg);
pll_con5 = readl_relaxed(pll->con_reg + 8);
/* Change PLL PMSK values */
pll_con3 &= ~((PLL0831X_MDIV_MASK << PLL0831X_MDIV_SHIFT) |
(PLL0831X_PDIV_MASK << PLL0831X_PDIV_SHIFT) |
(PLL0831X_SDIV_MASK << PLL0831X_SDIV_SHIFT));
pll_con3 |= (rate->mdiv << PLL0831X_MDIV_SHIFT) |
(rate->pdiv << PLL0831X_PDIV_SHIFT) |
(rate->sdiv << PLL0831X_SDIV_SHIFT);
pll_con5 &= ~(PLL0831X_KDIV_MASK << PLL0831X_KDIV_SHIFT);
/*
* kdiv is 16-bit 2's complement (s16), but stored as unsigned int.
* Cast it to u16 to avoid leading 0xffff's in case of negative value.
*/
pll_con5 |= ((u16)rate->kdiv << PLL0831X_KDIV_SHIFT);
/* Set PLL lock time */
writel_relaxed(rate->pdiv * PLL0831X_LOCK_FACTOR, pll->lock_reg);
/* Write PMSK values */
writel_relaxed(pll_con3, pll->con_reg);
writel_relaxed(pll_con5, pll->con_reg + 8);
/* Wait for PLL lock if the PLL is enabled */
if (pll_con3 & BIT(pll->enable_offs))
return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
return 0;
}
static const struct clk_ops samsung_pll0831x_clk_ops = {
.recalc_rate = samsung_pll0831x_recalc_rate,
.set_rate = samsung_pll0831x_set_rate,
.round_rate = samsung_pll_round_rate,
.enable = samsung_pll3xxx_enable,
.disable = samsung_pll3xxx_disable,
};
static const struct clk_ops samsung_pll0831x_clk_min_ops = {
.recalc_rate = samsung_pll0831x_recalc_rate,
};
/*
* PLL45xx Clock Type
*/
#define PLL4502_LOCK_FACTOR 400
#define PLL4508_LOCK_FACTOR 240
#define PLL45XX_MDIV_MASK (0x3FF)
#define PLL45XX_PDIV_MASK (0x3F)
#define PLL45XX_SDIV_MASK (0x7)
#define PLL45XX_AFC_MASK (0x1F)
#define PLL45XX_MDIV_SHIFT (16)
#define PLL45XX_PDIV_SHIFT (8)
#define PLL45XX_SDIV_SHIFT (0)
#define PLL45XX_AFC_SHIFT (0)
#define PLL45XX_ENABLE BIT(31)
#define PLL45XX_LOCKED BIT(29)
static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 mdiv, pdiv, sdiv, pll_con;
u64 fvco = parent_rate;
pll_con = readl_relaxed(pll->con_reg);
mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
if (pll->type == pll_4508)
sdiv = sdiv - 1;
fvco *= mdiv;
do_div(fvco, (pdiv << sdiv));
return (unsigned long)fvco;
}
static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1,
const struct samsung_pll_rate_table *rate)
{
u32 old_mdiv, old_pdiv, old_afc;
old_mdiv = (pll_con0 >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
old_pdiv = (pll_con0 >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
old_afc = (pll_con1 >> PLL45XX_AFC_SHIFT) & PLL45XX_AFC_MASK;
return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv
|| old_afc != rate->afc);
}
static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
unsigned long prate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
const struct samsung_pll_rate_table *rate;
u32 con0, con1;
/* Get required rate settings from table */
rate = samsung_get_pll_settings(pll, drate);
if (!rate) {
pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
drate, clk_hw_get_name(hw));
return -EINVAL;
}
con0 = readl_relaxed(pll->con_reg);
con1 = readl_relaxed(pll->con_reg + 0x4);
if (!(samsung_pll45xx_mp_change(con0, con1, rate))) {
/* If only s change, change just s value only*/
con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT);
con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT;
writel_relaxed(con0, pll->con_reg);
return 0;
}
/* Set PLL PMS values. */
con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) |
(PLL45XX_PDIV_MASK << PLL45XX_PDIV_SHIFT) |
(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT));
con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) |
(rate->pdiv << PLL45XX_PDIV_SHIFT) |
(rate->sdiv << PLL45XX_SDIV_SHIFT);
/* Set PLL AFC value. */
con1 = readl_relaxed(pll->con_reg + 0x4);
con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT);
con1 |= (rate->afc << PLL45XX_AFC_SHIFT);
/* Set PLL lock time. */
switch (pll->type) {
case pll_4502:
writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg);
break;
case pll_4508:
writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg);
break;
default:
break;
}
/* Set new configuration. */
writel_relaxed(con1, pll->con_reg + 0x4);
writel_relaxed(con0, pll->con_reg);
/* Wait for PLL lock */
return samsung_pll_lock_wait(pll, PLL45XX_LOCKED);
}
static const struct clk_ops samsung_pll45xx_clk_ops = {
.recalc_rate = samsung_pll45xx_recalc_rate,
.round_rate = samsung_pll_round_rate,
.set_rate = samsung_pll45xx_set_rate,
};
static const struct clk_ops samsung_pll45xx_clk_min_ops = {
.recalc_rate = samsung_pll45xx_recalc_rate,
};
/*
* PLL46xx Clock Type
*/
#define PLL46XX_LOCK_FACTOR 3000
#define PLL46XX_VSEL_MASK (1)
#define PLL46XX_MDIV_MASK (0x1FF)
#define PLL1460X_MDIV_MASK (0x3FF)
#define PLL46XX_PDIV_MASK (0x3F)
#define PLL46XX_SDIV_MASK (0x7)
#define PLL46XX_VSEL_SHIFT (27)
#define PLL46XX_MDIV_SHIFT (16)
#define PLL46XX_PDIV_SHIFT (8)
#define PLL46XX_SDIV_SHIFT (0)
#define PLL46XX_KDIV_MASK (0xFFFF)
#define PLL4650C_KDIV_MASK (0xFFF)
#define PLL46XX_KDIV_SHIFT (0)
#define PLL46XX_MFR_MASK (0x3F)
#define PLL46XX_MRR_MASK (0x1F)
#define PLL46XX_KDIV_SHIFT (0)
#define PLL46XX_MFR_SHIFT (16)
#define PLL46XX_MRR_SHIFT (24)
#define PLL46XX_ENABLE BIT(31)
#define PLL46XX_LOCKED BIT(29)
#define PLL46XX_VSEL BIT(27)
static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
u64 fvco = parent_rate;
pll_con0 = readl_relaxed(pll->con_reg);
pll_con1 = readl_relaxed(pll->con_reg + 4);
mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ?
PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK);
pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
pll_con1 & PLL46XX_KDIV_MASK;
shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10;
fvco *= (mdiv << shift) + kdiv;
do_div(fvco, (pdiv << sdiv));
fvco >>= shift;
return (unsigned long)fvco;
}
static bool samsung_pll46xx_mpk_change(u32 pll_con0, u32 pll_con1,
const struct samsung_pll_rate_table *rate)
{
u32 old_mdiv, old_pdiv, old_kdiv;
old_mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
old_pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
old_kdiv = (pll_con1 >> PLL46XX_KDIV_SHIFT) & PLL46XX_KDIV_MASK;
return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv
|| old_kdiv != rate->kdiv);
}
static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
unsigned long prate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
const struct samsung_pll_rate_table *rate;
u32 con0, con1, lock;
/* Get required rate settings from table */
rate = samsung_get_pll_settings(pll, drate);
if (!rate) {
pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
drate, clk_hw_get_name(hw));
return -EINVAL;
}
con0 = readl_relaxed(pll->con_reg);
con1 = readl_relaxed(pll->con_reg + 0x4);
if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) {
/* If only s change, change just s value only*/
con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT;
writel_relaxed(con0, pll->con_reg);
return 0;
}
/* Set PLL lock time. */
lock = rate->pdiv * PLL46XX_LOCK_FACTOR;
if (lock > 0xffff)
/* Maximum lock time bitfield is 16-bit. */
lock = 0xffff;
/* Set PLL PMS and VSEL values. */
if (pll->type == pll_1460x) {
con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
(PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT));
} else {
con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
(PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) |
(PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT));
con0 |= rate->vsel << PLL46XX_VSEL_SHIFT;
}
con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) |
(rate->pdiv << PLL46XX_PDIV_SHIFT) |
(rate->sdiv << PLL46XX_SDIV_SHIFT);
/* Set PLL K, MFR and MRR values. */
con1 = readl_relaxed(pll->con_reg + 0x4);
con1 &= ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) |
(PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT) |
(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT));
con1 |= (rate->kdiv << PLL46XX_KDIV_SHIFT) |
(rate->mfr << PLL46XX_MFR_SHIFT) |
(rate->mrr << PLL46XX_MRR_SHIFT);
/* Write configuration to PLL */
writel_relaxed(lock, pll->lock_reg);
writel_relaxed(con0, pll->con_reg);
writel_relaxed(con1, pll->con_reg + 0x4);
/* Wait for PLL lock */
return samsung_pll_lock_wait(pll, PLL46XX_LOCKED);
}
static const struct clk_ops samsung_pll46xx_clk_ops = {
.recalc_rate = samsung_pll46xx_recalc_rate,
.round_rate = samsung_pll_round_rate,
.set_rate = samsung_pll46xx_set_rate,
};
static const struct clk_ops samsung_pll46xx_clk_min_ops = {
.recalc_rate = samsung_pll46xx_recalc_rate,
};
/*
* PLL6552 Clock Type
*/
#define PLL6552_MDIV_MASK 0x3ff
#define PLL6552_PDIV_MASK 0x3f
#define PLL6552_SDIV_MASK 0x7
#define PLL6552_MDIV_SHIFT 16
#define PLL6552_MDIV_SHIFT_2416 14
#define PLL6552_PDIV_SHIFT 8
#define PLL6552_PDIV_SHIFT_2416 5
#define PLL6552_SDIV_SHIFT 0
static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 mdiv, pdiv, sdiv, pll_con;
u64 fvco = parent_rate;
pll_con = readl_relaxed(pll->con_reg);
if (pll->type == pll_6552_s3c2416) {
mdiv = (pll_con >> PLL6552_MDIV_SHIFT_2416) & PLL6552_MDIV_MASK;
pdiv = (pll_con >> PLL6552_PDIV_SHIFT_2416) & PLL6552_PDIV_MASK;
} else {
mdiv = (pll_con >> PLL6552_MDIV_SHIFT) & PLL6552_MDIV_MASK;
pdiv = (pll_con >> PLL6552_PDIV_SHIFT) & PLL6552_PDIV_MASK;
}
sdiv = (pll_con >> PLL6552_SDIV_SHIFT) & PLL6552_SDIV_MASK;
fvco *= mdiv;
do_div(fvco, (pdiv << sdiv));
return (unsigned long)fvco;
}
static const struct clk_ops samsung_pll6552_clk_ops = {
.recalc_rate = samsung_pll6552_recalc_rate,
};
/*
* PLL6553 Clock Type
*/
#define PLL6553_MDIV_MASK 0xff
#define PLL6553_PDIV_MASK 0x3f
#define PLL6553_SDIV_MASK 0x7
#define PLL6553_KDIV_MASK 0xffff
#define PLL6553_MDIV_SHIFT 16
#define PLL6553_PDIV_SHIFT 8
#define PLL6553_SDIV_SHIFT 0
#define PLL6553_KDIV_SHIFT 0
static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
u64 fvco = parent_rate;
pll_con0 = readl_relaxed(pll->con_reg);
pll_con1 = readl_relaxed(pll->con_reg + 0x4);
mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK;
pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK;
sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK;
kdiv = (pll_con1 >> PLL6553_KDIV_SHIFT) & PLL6553_KDIV_MASK;
fvco *= (mdiv << 16) + kdiv;
do_div(fvco, (pdiv << sdiv));
fvco >>= 16;
return (unsigned long)fvco;
}
static const struct clk_ops samsung_pll6553_clk_ops = {
.recalc_rate = samsung_pll6553_recalc_rate,
};
/*
* PLL2550x Clock Type
*/
#define PLL2550X_R_MASK (0x1)
#define PLL2550X_P_MASK (0x3F)
#define PLL2550X_M_MASK (0x3FF)
#define PLL2550X_S_MASK (0x7)
#define PLL2550X_R_SHIFT (20)
#define PLL2550X_P_SHIFT (14)
#define PLL2550X_M_SHIFT (4)
#define PLL2550X_S_SHIFT (0)
static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 r, p, m, s, pll_stat;
u64 fvco = parent_rate;
pll_stat = readl_relaxed(pll->con_reg);
r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK;
if (!r)
return 0;
p = (pll_stat >> PLL2550X_P_SHIFT) & PLL2550X_P_MASK;
m = (pll_stat >> PLL2550X_M_SHIFT) & PLL2550X_M_MASK;
s = (pll_stat >> PLL2550X_S_SHIFT) & PLL2550X_S_MASK;
fvco *= m;
do_div(fvco, (p << s));
return (unsigned long)fvco;
}
static const struct clk_ops samsung_pll2550x_clk_ops = {
.recalc_rate = samsung_pll2550x_recalc_rate,
};
/*
* PLL2550xx Clock Type
*/
/* Maximum lock time can be 270 * PDIV cycles */
#define PLL2550XX_LOCK_FACTOR 270
#define PLL2550XX_M_MASK 0x3FF
#define PLL2550XX_P_MASK 0x3F
#define PLL2550XX_S_MASK 0x7
#define PLL2550XX_LOCK_STAT_MASK 0x1
#define PLL2550XX_M_SHIFT 9
#define PLL2550XX_P_SHIFT 3
#define PLL2550XX_S_SHIFT 0
#define PLL2550XX_LOCK_STAT_SHIFT 21
static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 mdiv, pdiv, sdiv, pll_con;
u64 fvco = parent_rate;
pll_con = readl_relaxed(pll->con_reg);
mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK;
pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK;
sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK;
fvco *= mdiv;
do_div(fvco, (pdiv << sdiv));
return (unsigned long)fvco;
}
static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con)
{
u32 old_mdiv, old_pdiv;
old_mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK;
old_pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK;
return mdiv != old_mdiv || pdiv != old_pdiv;
}
static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate,
unsigned long prate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
const struct samsung_pll_rate_table *rate;
u32 tmp;
/* Get required rate settings from table */
rate = samsung_get_pll_settings(pll, drate);
if (!rate) {
pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
drate, clk_hw_get_name(hw));
return -EINVAL;
}
tmp = readl_relaxed(pll->con_reg);
if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) {
/* If only s change, change just s value only*/
tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT);
tmp |= rate->sdiv << PLL2550XX_S_SHIFT;
writel_relaxed(tmp, pll->con_reg);
return 0;
}
/* Set PLL lock time. */
writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg);
/* Change PLL PMS values */
tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) |
(PLL2550XX_P_MASK << PLL2550XX_P_SHIFT) |
(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT));
tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) |
(rate->pdiv << PLL2550XX_P_SHIFT) |
(rate->sdiv << PLL2550XX_S_SHIFT);
writel_relaxed(tmp, pll->con_reg);
/* Wait for PLL lock */
return samsung_pll_lock_wait(pll,
PLL2550XX_LOCK_STAT_MASK << PLL2550XX_LOCK_STAT_SHIFT);
}
static const struct clk_ops samsung_pll2550xx_clk_ops = {
.recalc_rate = samsung_pll2550xx_recalc_rate,
.round_rate = samsung_pll_round_rate,
.set_rate = samsung_pll2550xx_set_rate,
};
static const struct clk_ops samsung_pll2550xx_clk_min_ops = {
.recalc_rate = samsung_pll2550xx_recalc_rate,
};
/*
* PLL2650x Clock Type
*/
/* Maximum lock time can be 3000 * PDIV cycles */
#define PLL2650X_LOCK_FACTOR 3000
#define PLL2650X_M_MASK 0x1ff
#define PLL2650X_P_MASK 0x3f
#define PLL2650X_S_MASK 0x7
#define PLL2650X_K_MASK 0xffff
#define PLL2650X_LOCK_STAT_MASK 0x1
#define PLL2650X_M_SHIFT 16
#define PLL2650X_P_SHIFT 8
#define PLL2650X_S_SHIFT 0
#define PLL2650X_K_SHIFT 0
#define PLL2650X_LOCK_STAT_SHIFT 29
#define PLL2650X_PLL_ENABLE_SHIFT 31
static unsigned long samsung_pll2650x_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
u64 fout = parent_rate;
u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
s16 kdiv;
pll_con0 = readl_relaxed(pll->con_reg);
mdiv = (pll_con0 >> PLL2650X_M_SHIFT) & PLL2650X_M_MASK;
pdiv = (pll_con0 >> PLL2650X_P_SHIFT) & PLL2650X_P_MASK;
sdiv = (pll_con0 >> PLL2650X_S_SHIFT) & PLL2650X_S_MASK;
pll_con1 = readl_relaxed(pll->con_reg + 4);
kdiv = (s16)((pll_con1 >> PLL2650X_K_SHIFT) & PLL2650X_K_MASK);
fout *= (mdiv << 16) + kdiv;
do_div(fout, (pdiv << sdiv));
fout >>= 16;
return (unsigned long)fout;
}
static int samsung_pll2650x_set_rate(struct clk_hw *hw, unsigned long drate,
unsigned long prate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
const struct samsung_pll_rate_table *rate;
u32 con0, con1;
/* Get required rate settings from table */
rate = samsung_get_pll_settings(pll, drate);
if (!rate) {
pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
drate, clk_hw_get_name(hw));
return -EINVAL;
}
con0 = readl_relaxed(pll->con_reg);
con1 = readl_relaxed(pll->con_reg + 4);
/* Set PLL lock time. */
writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg);
/* Change PLL PMS values */
con0 &= ~((PLL2650X_M_MASK << PLL2650X_M_SHIFT) |
(PLL2650X_P_MASK << PLL2650X_P_SHIFT) |
(PLL2650X_S_MASK << PLL2650X_S_SHIFT));
con0 |= (rate->mdiv << PLL2650X_M_SHIFT) |
(rate->pdiv << PLL2650X_P_SHIFT) |
(rate->sdiv << PLL2650X_S_SHIFT);
con0 |= (1 << PLL2650X_PLL_ENABLE_SHIFT);
writel_relaxed(con0, pll->con_reg);
con1 &= ~(PLL2650X_K_MASK << PLL2650X_K_SHIFT);
con1 |= ((rate->kdiv & PLL2650X_K_MASK) << PLL2650X_K_SHIFT);
writel_relaxed(con1, pll->con_reg + 4);
/* Wait for PLL lock */
return samsung_pll_lock_wait(pll,
PLL2650X_LOCK_STAT_MASK << PLL2650X_LOCK_STAT_SHIFT);
}
static const struct clk_ops samsung_pll2650x_clk_ops = {
.recalc_rate = samsung_pll2650x_recalc_rate,
.round_rate = samsung_pll_round_rate,
.set_rate = samsung_pll2650x_set_rate,
};
static const struct clk_ops samsung_pll2650x_clk_min_ops = {
.recalc_rate = samsung_pll2650x_recalc_rate,
};
/*
* PLL2650XX Clock Type
*/
/* Maximum lock time can be 3000 * PDIV cycles */
#define PLL2650XX_LOCK_FACTOR 3000
#define PLL2650XX_MDIV_SHIFT 9
#define PLL2650XX_PDIV_SHIFT 3
#define PLL2650XX_SDIV_SHIFT 0
#define PLL2650XX_KDIV_SHIFT 0
#define PLL2650XX_MDIV_MASK 0x1ff
#define PLL2650XX_PDIV_MASK 0x3f
#define PLL2650XX_SDIV_MASK 0x7
#define PLL2650XX_KDIV_MASK 0xffff
#define PLL2650XX_PLL_ENABLE_SHIFT 23
#define PLL2650XX_PLL_LOCKTIME_SHIFT 21
#define PLL2650XX_PLL_FOUTMASK_SHIFT 31
static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 mdiv, pdiv, sdiv, pll_con0, pll_con2;
s16 kdiv;
u64 fvco = parent_rate;
pll_con0 = readl_relaxed(pll->con_reg);
pll_con2 = readl_relaxed(pll->con_reg + 8);
mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK;
pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK;
sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK;
kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK);
fvco *= (mdiv << 16) + kdiv;
do_div(fvco, (pdiv << sdiv));
fvco >>= 16;
return (unsigned long)fvco;
}
static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate,
unsigned long parent_rate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
u32 pll_con0, pll_con2;
const struct samsung_pll_rate_table *rate;
rate = samsung_get_pll_settings(pll, drate);
if (!rate) {
pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
drate, clk_hw_get_name(hw));
return -EINVAL;
}
pll_con0 = readl_relaxed(pll->con_reg);
pll_con2 = readl_relaxed(pll->con_reg + 8);
/* Change PLL PMS values */
pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT |
PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT |
PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT);
pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT;
pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT;
pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT;
pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT;
pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT;
pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT);
pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK)
<< PLL2650XX_KDIV_SHIFT;
/* Set PLL lock time. */
writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
writel_relaxed(pll_con0, pll->con_reg);
writel_relaxed(pll_con2, pll->con_reg + 8);
return samsung_pll_lock_wait(pll, 0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT);
}
static const struct clk_ops samsung_pll2650xx_clk_ops = {
.recalc_rate = samsung_pll2650xx_recalc_rate,
.set_rate = samsung_pll2650xx_set_rate,
.round_rate = samsung_pll_round_rate,
};
static const struct clk_ops samsung_pll2650xx_clk_min_ops = {
.recalc_rate = samsung_pll2650xx_recalc_rate,
};
static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
const struct samsung_pll_clock *pll_clk)
{
struct samsung_clk_pll *pll;
struct clk_init_data init;
int ret, len;
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
if (!pll) {
pr_err("%s: could not allocate pll clk %s\n",
__func__, pll_clk->name);
return;
}
init.name = pll_clk->name;
init.flags = pll_clk->flags;
init.parent_names = &pll_clk->parent_name;
init.num_parents = 1;
if (pll_clk->rate_table) {
/* find count of rates in rate_table */
for (len = 0; pll_clk->rate_table[len].rate != 0; )
len++;
pll->rate_count = len;
pll->rate_table = kmemdup(pll_clk->rate_table,
pll->rate_count *
sizeof(struct samsung_pll_rate_table),
GFP_KERNEL);
WARN(!pll->rate_table,
"%s: could not allocate rate table for %s\n",
__func__, pll_clk->name);
}
switch (pll_clk->type) {
case pll_2126:
init.ops = &samsung_pll2126_clk_ops;
break;
case pll_3000:
init.ops = &samsung_pll3000_clk_ops;
break;
/* clk_ops for 35xx and 2550 are similar */
case pll_35xx:
case pll_2550:
case pll_1450x:
case pll_1451x:
case pll_1452x:
case pll_142xx:
pll->enable_offs = PLL35XX_ENABLE_SHIFT;
pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT;
if (!pll->rate_table)
init.ops = &samsung_pll35xx_clk_min_ops;
else
init.ops = &samsung_pll35xx_clk_ops;
break;
case pll_1417x:
case pll_0818x:
case pll_0822x:
pll->enable_offs = PLL0822X_ENABLE_SHIFT;
pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
if (!pll->rate_table)
init.ops = &samsung_pll0822x_clk_min_ops;
else
init.ops = &samsung_pll0822x_clk_ops;
break;
case pll_4500:
init.ops = &samsung_pll45xx_clk_min_ops;
break;
case pll_4502:
case pll_4508:
if (!pll->rate_table)
init.ops = &samsung_pll45xx_clk_min_ops;
else
init.ops = &samsung_pll45xx_clk_ops;
break;
/* clk_ops for 36xx and 2650 are similar */
case pll_36xx:
case pll_2650:
pll->enable_offs = PLL36XX_ENABLE_SHIFT;
pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT;
if (!pll->rate_table)
init.ops = &samsung_pll36xx_clk_min_ops;
else
init.ops = &samsung_pll36xx_clk_ops;
break;
case pll_0831x:
pll->enable_offs = PLL0831X_ENABLE_SHIFT;
pll->lock_offs = PLL0831X_LOCK_STAT_SHIFT;
if (!pll->rate_table)
init.ops = &samsung_pll0831x_clk_min_ops;
else
init.ops = &samsung_pll0831x_clk_ops;
break;
case pll_6552:
case pll_6552_s3c2416:
init.ops = &samsung_pll6552_clk_ops;
break;
case pll_6553:
init.ops = &samsung_pll6553_clk_ops;
break;
case pll_4600:
case pll_4650:
case pll_4650c:
case pll_1460x:
if (!pll->rate_table)
init.ops = &samsung_pll46xx_clk_min_ops;
else
init.ops = &samsung_pll46xx_clk_ops;
break;
case pll_2550x:
init.ops = &samsung_pll2550x_clk_ops;
break;
case pll_2550xx:
if (!pll->rate_table)
init.ops = &samsung_pll2550xx_clk_min_ops;
else
init.ops = &samsung_pll2550xx_clk_ops;
break;
case pll_2650x:
if (!pll->rate_table)
init.ops = &samsung_pll2650x_clk_min_ops;
else
init.ops = &samsung_pll2650x_clk_ops;
break;
case pll_2650xx:
if (!pll->rate_table)
init.ops = &samsung_pll2650xx_clk_min_ops;
else
init.ops = &samsung_pll2650xx_clk_ops;
break;
default:
pr_warn("%s: Unknown pll type for pll clk %s\n",
__func__, pll_clk->name);
}
pll->hw.init = &init;
pll->type = pll_clk->type;
pll->lock_reg = ctx->reg_base + pll_clk->lock_offset;
pll->con_reg = ctx->reg_base + pll_clk->con_offset;
ret = clk_hw_register(ctx->dev, &pll->hw);
if (ret) {
pr_err("%s: failed to register pll clock %s : %d\n",
__func__, pll_clk->name, ret);
kfree(pll->rate_table);
kfree(pll);
return;
}
samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id);
}
void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
const struct samsung_pll_clock *pll_list,
unsigned int nr_pll)
{
int cnt;
for (cnt = 0; cnt < nr_pll; cnt++)
_samsung_clk_register_pll(ctx, &pll_list[cnt]);
}
| linux-master | drivers/clk/samsung/clk-pll.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
*
* Common Clock Framework support for Exynos3250 SoC.
*/
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/exynos3250.h>
#include "clk.h"
#include "clk-cpu.h"
#include "clk-pll.h"
#define SRC_LEFTBUS 0x4200
#define DIV_LEFTBUS 0x4500
#define GATE_IP_LEFTBUS 0x4800
#define SRC_RIGHTBUS 0x8200
#define DIV_RIGHTBUS 0x8500
#define GATE_IP_RIGHTBUS 0x8800
#define GATE_IP_PERIR 0x8960
#define MPLL_LOCK 0xc010
#define MPLL_CON0 0xc110
#define VPLL_LOCK 0xc020
#define VPLL_CON0 0xc120
#define UPLL_LOCK 0xc030
#define UPLL_CON0 0xc130
#define SRC_TOP0 0xc210
#define SRC_TOP1 0xc214
#define SRC_CAM 0xc220
#define SRC_MFC 0xc228
#define SRC_G3D 0xc22c
#define SRC_LCD 0xc234
#define SRC_ISP 0xc238
#define SRC_FSYS 0xc240
#define SRC_PERIL0 0xc250
#define SRC_PERIL1 0xc254
#define SRC_MASK_TOP 0xc310
#define SRC_MASK_CAM 0xc320
#define SRC_MASK_LCD 0xc334
#define SRC_MASK_ISP 0xc338
#define SRC_MASK_FSYS 0xc340
#define SRC_MASK_PERIL0 0xc350
#define SRC_MASK_PERIL1 0xc354
#define DIV_TOP 0xc510
#define DIV_CAM 0xc520
#define DIV_MFC 0xc528
#define DIV_G3D 0xc52c
#define DIV_LCD 0xc534
#define DIV_ISP 0xc538
#define DIV_FSYS0 0xc540
#define DIV_FSYS1 0xc544
#define DIV_FSYS2 0xc548
#define DIV_PERIL0 0xc550
#define DIV_PERIL1 0xc554
#define DIV_PERIL3 0xc55c
#define DIV_PERIL4 0xc560
#define DIV_PERIL5 0xc564
#define DIV_CAM1 0xc568
#define CLKDIV2_RATIO 0xc580
#define GATE_SCLK_CAM 0xc820
#define GATE_SCLK_MFC 0xc828
#define GATE_SCLK_G3D 0xc82c
#define GATE_SCLK_LCD 0xc834
#define GATE_SCLK_ISP_TOP 0xc838
#define GATE_SCLK_FSYS 0xc840
#define GATE_SCLK_PERIL 0xc850
#define GATE_IP_CAM 0xc920
#define GATE_IP_MFC 0xc928
#define GATE_IP_G3D 0xc92c
#define GATE_IP_LCD 0xc934
#define GATE_IP_ISP 0xc938
#define GATE_IP_FSYS 0xc940
#define GATE_IP_PERIL 0xc950
#define GATE_BLOCK 0xc970
#define APLL_LOCK 0x14000
#define APLL_CON0 0x14100
#define SRC_CPU 0x14200
#define DIV_CPU0 0x14500
#define DIV_CPU1 0x14504
#define PWR_CTRL1 0x15020
#define PWR_CTRL2 0x15024
/* Below definitions are used for PWR_CTRL settings */
#define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
#define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
#define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
#define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
#define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
#define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR_MAIN (CLK_SCLK_MMC2 + 1)
#define CLKS_NR_DMC (CLK_DIV_DMCD + 1)
#define CLKS_NR_ISP (CLK_SCLK_MPWM_ISP + 1)
static const unsigned long exynos3250_cmu_clk_regs[] __initconst = {
SRC_LEFTBUS,
DIV_LEFTBUS,
GATE_IP_LEFTBUS,
SRC_RIGHTBUS,
DIV_RIGHTBUS,
GATE_IP_RIGHTBUS,
GATE_IP_PERIR,
MPLL_LOCK,
MPLL_CON0,
VPLL_LOCK,
VPLL_CON0,
UPLL_LOCK,
UPLL_CON0,
SRC_TOP0,
SRC_TOP1,
SRC_CAM,
SRC_MFC,
SRC_G3D,
SRC_LCD,
SRC_ISP,
SRC_FSYS,
SRC_PERIL0,
SRC_PERIL1,
SRC_MASK_TOP,
SRC_MASK_CAM,
SRC_MASK_LCD,
SRC_MASK_ISP,
SRC_MASK_FSYS,
SRC_MASK_PERIL0,
SRC_MASK_PERIL1,
DIV_TOP,
DIV_CAM,
DIV_MFC,
DIV_G3D,
DIV_LCD,
DIV_ISP,
DIV_FSYS0,
DIV_FSYS1,
DIV_FSYS2,
DIV_PERIL0,
DIV_PERIL1,
DIV_PERIL3,
DIV_PERIL4,
DIV_PERIL5,
DIV_CAM1,
CLKDIV2_RATIO,
GATE_SCLK_CAM,
GATE_SCLK_MFC,
GATE_SCLK_G3D,
GATE_SCLK_LCD,
GATE_SCLK_ISP_TOP,
GATE_SCLK_FSYS,
GATE_SCLK_PERIL,
GATE_IP_CAM,
GATE_IP_MFC,
GATE_IP_G3D,
GATE_IP_LCD,
GATE_IP_ISP,
GATE_IP_FSYS,
GATE_IP_PERIL,
GATE_BLOCK,
APLL_LOCK,
SRC_CPU,
DIV_CPU0,
DIV_CPU1,
PWR_CTRL1,
PWR_CTRL2,
};
/* list of all parent clock list */
PNAME(mout_vpllsrc_p) = { "fin_pll", };
PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
PNAME(mout_upll_p) = { "fin_pll", "fout_upll", };
PNAME(mout_mpll_user_p) = { "fin_pll", "div_mpll_pre", };
PNAME(mout_epll_user_p) = { "fin_pll", "mout_epll", };
PNAME(mout_core_p) = { "mout_apll", "mout_mpll_user_c", };
PNAME(mout_hpm_p) = { "mout_apll", "mout_mpll_user_c", };
PNAME(mout_ebi_p) = { "div_aclk_200", "div_aclk_160", };
PNAME(mout_ebi_1_p) = { "mout_ebi", "mout_vpll", };
PNAME(mout_gdl_p) = { "mout_mpll_user_l", };
PNAME(mout_gdr_p) = { "mout_mpll_user_r", };
PNAME(mout_aclk_400_mcuisp_sub_p)
= { "fin_pll", "div_aclk_400_mcuisp", };
PNAME(mout_aclk_266_0_p) = { "div_mpll_pre", "mout_vpll", };
PNAME(mout_aclk_266_1_p) = { "mout_epll_user", };
PNAME(mout_aclk_266_p) = { "mout_aclk_266_0", "mout_aclk_266_1", };
PNAME(mout_aclk_266_sub_p) = { "fin_pll", "div_aclk_266", };
PNAME(group_div_mpll_pre_p) = { "div_mpll_pre", };
PNAME(group_epll_vpll_p) = { "mout_epll_user", "mout_vpll" };
PNAME(group_sclk_p) = { "xxti", "xusbxti",
"none", "none",
"none", "none", "div_mpll_pre",
"mout_epll_user", "mout_vpll", };
PNAME(group_sclk_audio_p) = { "audiocdclk", "none",
"none", "none",
"xxti", "xusbxti",
"div_mpll_pre", "mout_epll_user",
"mout_vpll", };
PNAME(group_sclk_cam_blk_p) = { "xxti", "xusbxti",
"none", "none", "none",
"none", "div_mpll_pre",
"mout_epll_user", "mout_vpll",
"none", "none", "none",
"div_cam_blk_320", };
PNAME(group_sclk_fimd0_p) = { "xxti", "xusbxti",
"m_bitclkhsdiv4_2l", "none",
"none", "none", "div_mpll_pre",
"mout_epll_user", "mout_vpll",
"none", "none", "none",
"div_lcd_blk_145", };
PNAME(mout_mfc_p) = { "mout_mfc_0", "mout_mfc_1" };
PNAME(mout_g3d_p) = { "mout_g3d_0", "mout_g3d_1" };
static const struct samsung_fixed_factor_clock fixed_factor_clks[] __initconst = {
FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0),
FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),
FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),
FFACTOR(0, "div_cam_blk_320", "sclk_mpll_1600", 1, 5, 0),
FFACTOR(0, "div_lcd_blk_145", "sclk_mpll_1600", 1, 11, 0),
/* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */
FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
};
static const struct samsung_mux_clock mux_clks[] __initconst = {
/*
* NOTE: Following table is sorted by register address in ascending
* order and then bitfield shift in descending order, as it is done
* in the User's Manual. When adding new entries, please make sure
* that the order is preserved, to avoid merge conflicts and make
* further work with defined data easier.
*/
/* SRC_LEFTBUS */
MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
SRC_LEFTBUS, 4, 1),
MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
/* SRC_RIGHTBUS */
MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
SRC_RIGHTBUS, 4, 1),
MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
/* SRC_TOP0 */
MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1),
MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1),
MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1),
MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1),
MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1),
MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p, SRC_TOP0, 12, 1),
MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, SRC_TOP0, 4, 1),
MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
/* SRC_TOP1 */
MUX(CLK_MOUT_UPLL, "mout_upll", mout_upll_p, SRC_TOP1, 28, 1),
MUX(CLK_MOUT_ACLK_400_MCUISP_SUB, "mout_aclk_400_mcuisp_sub", mout_aclk_400_mcuisp_sub_p,
SRC_TOP1, 24, 1),
MUX(CLK_MOUT_ACLK_266_SUB, "mout_aclk_266_sub", mout_aclk_266_sub_p, SRC_TOP1, 20, 1),
MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_TOP1, 12, 1),
MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", group_div_mpll_pre_p, SRC_TOP1, 8, 1),
MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
/* SRC_CAM */
MUX(CLK_MOUT_CAM1, "mout_cam1", group_sclk_p, SRC_CAM, 20, 4),
MUX(CLK_MOUT_CAM_BLK, "mout_cam_blk", group_sclk_cam_blk_p, SRC_CAM, 0, 4),
/* SRC_MFC */
MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_vpll_p, SRC_MFC, 4, 1),
MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_div_mpll_pre_p, SRC_MFC, 0, 1),
/* SRC_G3D */
MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_vpll_p, SRC_G3D, 4, 1),
MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_div_mpll_pre_p, SRC_G3D, 0, 1),
/* SRC_LCD */
MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_sclk_p, SRC_LCD, 12, 4),
MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
/* SRC_ISP */
MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_sclk_p, SRC_ISP, 12, 4),
MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_sclk_p, SRC_ISP, 8, 4),
MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_sclk_p, SRC_ISP, 4, 4),
/* SRC_FSYS */
MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
/* SRC_PERIL0 */
MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
/* SRC_PERIL1 */
MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
MUX(CLK_MOUT_AUDIO, "mout_audio", group_sclk_audio_p, SRC_PERIL1, 4, 4),
/* SRC_CPU */
MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
SRC_CPU, 24, 1),
MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1,
CLK_SET_RATE_PARENT, 0),
MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_div_clock div_clks[] __initconst = {
/*
* NOTE: Following table is sorted by register address in ascending
* order and then bitfield shift in descending order, as it is done
* in the User's Manual. When adding new entries, please make sure
* that the order is preserved, to avoid merge conflicts and make
* further work with defined data easier.
*/
/* DIV_LEFTBUS */
DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
/* DIV_RIGHTBUS */
DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
/* DIV_TOP */
DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2),
DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
"mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
/* DIV_CAM */
DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
DIV(CLK_DIV_CAM_BLK, "div_cam_blk", "mout_cam_blk", DIV_CAM, 0, 4),
/* DIV_MFC */
DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
/* DIV_G3D */
DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
/* DIV_LCD */
DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
CLK_SET_RATE_PARENT, 0),
DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
/* DIV_ISP */
DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 4, 4),
/* DIV_FSYS0 */
DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
CLK_SET_RATE_PARENT, 0),
DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
/* DIV_FSYS1 */
DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
CLK_SET_RATE_PARENT, 0),
DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
CLK_SET_RATE_PARENT, 0),
DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
/* DIV_FSYS2 */
DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
CLK_SET_RATE_PARENT, 0),
DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
/* DIV_PERIL0 */
DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
/* DIV_PERIL1 */
DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
CLK_SET_RATE_PARENT, 0),
DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
CLK_SET_RATE_PARENT, 0),
DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
/* DIV_PERIL4 */
DIV(CLK_DIV_PCM, "div_pcm", "div_audio", DIV_PERIL4, 20, 8),
DIV(CLK_DIV_AUDIO, "div_audio", "mout_audio", DIV_PERIL4, 16, 4),
/* DIV_PERIL5 */
DIV(CLK_DIV_I2S, "div_i2s", "div_audio", DIV_PERIL5, 8, 6),
/* DIV_CPU0 */
DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
DIV(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
DIV(CLK_DIV_COREM, "div_corem", "div_core2", DIV_CPU0, 4, 3),
DIV(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3),
/* DIV_CPU1 */
DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
};
static const struct samsung_gate_clock gate_clks[] __initconst = {
/*
* NOTE: Following table is sorted by register address in ascending
* order and then bitfield shift in descending order, as it is done
* in the User's Manual. When adding new entries, please make sure
* that the order is preserved, to avoid merge conflicts and make
* further work with defined data easier.
*/
/* GATE_IP_LEFTBUS */
GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
CLK_IGNORE_UNUSED, 0),
/* GATE_IP_RIGHTBUS */
GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0,
CLK_IGNORE_UNUSED, 0),
/* GATE_IP_PERIR */
GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
GATE_IP_PERIR, 17, 0, 0),
GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
CLK_IGNORE_UNUSED, 0),
/* GATE_SCLK_CAM */
GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_cam_blk",
GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_M2MSCALER, "sclk_m2mscaler", "div_cam_blk",
GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_GSCALER1, "sclk_gscaler1", "div_cam_blk",
GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_GSCALER0, "sclk_gscaler0", "div_cam_blk",
GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
/* GATE_SCLK_MFC */
GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
/* GATE_SCLK_G3D */
GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
/* GATE_SCLK_LCD */
GATE(CLK_SCLK_MIPIDPHY2L, "sclk_mipidphy2l", "div_mipi0",
GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
/* GATE_SCLK_ISP_TOP */
GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
GATE_SCLK_ISP_TOP, 4, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",
GATE_SCLK_ISP_TOP, 3, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp",
GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp",
GATE_SCLK_ISP_TOP, 1, CLK_SET_RATE_PARENT, 0),
/* GATE_SCLK_FSYS */
GATE(CLK_SCLK_UPLL, "sclk_upll", "mout_upll", GATE_SCLK_FSYS, 10, 0, 0),
GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
/* GATE_SCLK_PERIL */
GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s",
GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm",
GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
/* GATE_IP_CAM */
GATE(CLK_QEJPEG, "qejpeg", "div_cam_blk_320", GATE_IP_CAM, 19,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_cam_blk_320",
GATE_IP_CAM, 18, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_cam_blk_320",
GATE_IP_CAM, 17, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PPMUCAMIF, "ppmucamif", "div_cam_blk_320",
GATE_IP_CAM, 16, CLK_IGNORE_UNUSED, 0),
GATE(CLK_QEM2MSCALER, "qem2mscaler", "div_cam_blk_320",
GATE_IP_CAM, 14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_QEGSCALER1, "qegscaler1", "div_cam_blk_320",
GATE_IP_CAM, 13, CLK_IGNORE_UNUSED, 0),
GATE(CLK_QEGSCALER0, "qegscaler0", "div_cam_blk_320",
GATE_IP_CAM, 12, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SMMUJPEG, "smmujpeg", "div_cam_blk_320",
GATE_IP_CAM, 11, 0, 0),
GATE(CLK_SMMUM2M2SCALER, "smmum2m2scaler", "div_cam_blk_320",
GATE_IP_CAM, 9, 0, 0),
GATE(CLK_SMMUGSCALER1, "smmugscaler1", "div_cam_blk_320",
GATE_IP_CAM, 8, 0, 0),
GATE(CLK_SMMUGSCALER0, "smmugscaler0", "div_cam_blk_320",
GATE_IP_CAM, 7, 0, 0),
GATE(CLK_JPEG, "jpeg", "div_cam_blk_320", GATE_IP_CAM, 6, 0, 0),
GATE(CLK_M2MSCALER, "m2mscaler", "div_cam_blk_320",
GATE_IP_CAM, 2, 0, 0),
GATE(CLK_GSCALER1, "gscaler1", "div_cam_blk_320", GATE_IP_CAM, 1, 0, 0),
GATE(CLK_GSCALER0, "gscaler0", "div_cam_blk_320", GATE_IP_CAM, 0, 0, 0),
/* GATE_IP_MFC */
GATE(CLK_QEMFC, "qemfc", "div_aclk_200", GATE_IP_MFC, 5,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
/* GATE_IP_G3D */
GATE(CLK_SMMUG3D, "smmug3d", "div_aclk_200", GATE_IP_G3D, 3, 0, 0),
GATE(CLK_QEG3D, "qeg3d", "div_aclk_200", GATE_IP_G3D, 2,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
/* GATE_IP_LCD */
GATE(CLK_QE_CH1_LCD, "qe_ch1_lcd", "div_aclk_160", GATE_IP_LCD, 7,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_QE_CH0_LCD, "qe_ch0_lcd", "div_aclk_160", GATE_IP_LCD, 6,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
/* GATE_IP_ISP */
GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0),
GATE(CLK_UART_ISP_TOP, "uart_isp_top", "mout_aclk_266_sub",
GATE_IP_ISP, 3, 0, 0),
GATE(CLK_SPI1_ISP_TOP, "spi1_isp_top", "mout_aclk_266_sub",
GATE_IP_ISP, 2, 0, 0),
GATE(CLK_SPI0_ISP_TOP, "spi0_isp_top", "mout_aclk_266_sub",
GATE_IP_ISP, 1, 0, 0),
/* GATE_IP_FSYS */
GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
/* GATE_IP_PERIL */
GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
GATE(CLK_PCM, "pcm", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
GATE(CLK_I2S, "i2s", "div_aclk_100", GATE_IP_PERIL, 21, 0, 0),
GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
};
/* APLL & MPLL & BPLL & UPLL */
static const struct samsung_pll_rate_table exynos3250_pll_rates[] __initconst = {
PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 6, 1),
PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
PLL_35XX_RATE(24 * MHZ, 960000000, 320, 4, 1),
PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
PLL_35XX_RATE(24 * MHZ, 850000000, 425, 6, 1),
PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),
PLL_35XX_RATE(24 * MHZ, 600000000, 400, 4, 2),
PLL_35XX_RATE(24 * MHZ, 533000000, 533, 6, 2),
PLL_35XX_RATE(24 * MHZ, 520000000, 260, 3, 2),
PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2),
PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2),
PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
PLL_35XX_RATE(24 * MHZ, 100000000, 200, 3, 4),
{ /* sentinel */ }
};
/* EPLL */
static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst = {
PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1, 0),
PLL_36XX_RATE(24 * MHZ, 288000000, 96, 2, 2, 0),
PLL_36XX_RATE(24 * MHZ, 192000000, 128, 2, 3, 0),
PLL_36XX_RATE(24 * MHZ, 144000000, 96, 2, 3, 0),
PLL_36XX_RATE(24 * MHZ, 96000000, 128, 2, 4, 0),
PLL_36XX_RATE(24 * MHZ, 84000000, 112, 2, 4, 0),
PLL_36XX_RATE(24 * MHZ, 80000003, 106, 2, 4, 43691),
PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923),
PLL_36XX_RATE(24 * MHZ, 67737598, 270, 3, 5, 62285),
PLL_36XX_RATE(24 * MHZ, 65535999, 174, 2, 5, 49982),
PLL_36XX_RATE(24 * MHZ, 50000000, 200, 3, 5, 0),
PLL_36XX_RATE(24 * MHZ, 49152002, 131, 2, 5, 4719),
PLL_36XX_RATE(24 * MHZ, 48000000, 128, 2, 5, 0),
PLL_36XX_RATE(24 * MHZ, 45158401, 180, 3, 5, 41524),
{ /* sentinel */ }
};
/* VPLL */
static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst = {
PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1, 0),
PLL_36XX_RATE(24 * MHZ, 533000000, 266, 3, 2, 32768),
PLL_36XX_RATE(24 * MHZ, 519230987, 173, 2, 2, 5046),
PLL_36XX_RATE(24 * MHZ, 500000000, 250, 3, 2, 0),
PLL_36XX_RATE(24 * MHZ, 445500000, 148, 2, 2, 32768),
PLL_36XX_RATE(24 * MHZ, 445055007, 148, 2, 2, 23047),
PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2, 0),
PLL_36XX_RATE(24 * MHZ, 371250000, 123, 2, 2, 49152),
PLL_36XX_RATE(24 * MHZ, 370878997, 185, 3, 2, 28803),
PLL_36XX_RATE(24 * MHZ, 340000000, 170, 3, 2, 0),
PLL_36XX_RATE(24 * MHZ, 335000015, 111, 2, 2, 43691),
PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2, 0),
PLL_36XX_RATE(24 * MHZ, 330000000, 110, 2, 2, 0),
PLL_36XX_RATE(24 * MHZ, 320000015, 106, 2, 2, 43691),
PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2, 0),
PLL_36XX_RATE(24 * MHZ, 275000000, 275, 3, 3, 0),
PLL_36XX_RATE(24 * MHZ, 222750000, 148, 2, 3, 32768),
PLL_36XX_RATE(24 * MHZ, 222528007, 148, 2, 3, 23069),
PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3, 0),
PLL_36XX_RATE(24 * MHZ, 148500000, 99, 2, 3, 0),
PLL_36XX_RATE(24 * MHZ, 148352005, 98, 2, 3, 59070),
PLL_36XX_RATE(24 * MHZ, 108000000, 144, 2, 4, 0),
PLL_36XX_RATE(24 * MHZ, 74250000, 99, 2, 4, 0),
PLL_36XX_RATE(24 * MHZ, 74176002, 98, 2, 4, 59070),
PLL_36XX_RATE(24 * MHZ, 54054000, 216, 3, 5, 14156),
PLL_36XX_RATE(24 * MHZ, 54000000, 144, 2, 5, 0),
{ /* sentinel */ }
};
static const struct samsung_pll_clock exynos3250_plls[] __initconst = {
PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
APLL_LOCK, APLL_CON0, exynos3250_pll_rates),
PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
MPLL_LOCK, MPLL_CON0, exynos3250_pll_rates),
PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
VPLL_LOCK, VPLL_CON0, exynos3250_vpll_rates),
PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll",
UPLL_LOCK, UPLL_CON0, exynos3250_pll_rates),
};
#define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \
(((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
((corem) << 4))
#define E3250_CPU_DIV1(hpm, copy) \
(((hpm) << 4) | ((copy) << 0))
static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {
{ 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), },
{ 900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
{ 800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
{ 700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
{ 600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
{ 500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
{ 400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
{ 300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), },
{ 200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), },
{ 100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), },
{ 0 },
};
static const struct samsung_cpu_clock exynos3250_cpu_clks[] __initconst = {
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
CLK_CPU_HAS_DIV1, 0x14200, e3250_armclk_d),
};
static void __init exynos3_core_down_clock(void __iomem *reg_base)
{
unsigned int tmp;
/*
* Enable arm clock down (in idle) and set arm divider
* ratios in WFI/WFE state.
*/
tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
__raw_writel(tmp, reg_base + PWR_CTRL1);
/*
* Disable the clock up feature on Exynos4x12, in case it was
* enabled by bootloader.
*/
__raw_writel(0x0, reg_base + PWR_CTRL2);
}
static const struct samsung_cmu_info cmu_info __initconst = {
.pll_clks = exynos3250_plls,
.nr_pll_clks = ARRAY_SIZE(exynos3250_plls),
.mux_clks = mux_clks,
.nr_mux_clks = ARRAY_SIZE(mux_clks),
.div_clks = div_clks,
.nr_div_clks = ARRAY_SIZE(div_clks),
.gate_clks = gate_clks,
.nr_gate_clks = ARRAY_SIZE(gate_clks),
.fixed_factor_clks = fixed_factor_clks,
.nr_fixed_factor_clks = ARRAY_SIZE(fixed_factor_clks),
.cpu_clks = exynos3250_cpu_clks,
.nr_cpu_clks = ARRAY_SIZE(exynos3250_cpu_clks),
.nr_clk_ids = CLKS_NR_MAIN,
.clk_regs = exynos3250_cmu_clk_regs,
.nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs),
};
static void __init exynos3250_cmu_init(struct device_node *np)
{
struct samsung_clk_provider *ctx;
ctx = samsung_cmu_register_one(np, &cmu_info);
if (!ctx)
return;
exynos3_core_down_clock(ctx->reg_base);
}
CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
/*
* CMU DMC
*/
#define BPLL_LOCK 0x0118
#define BPLL_CON0 0x0218
#define BPLL_CON1 0x021c
#define BPLL_CON2 0x0220
#define SRC_DMC 0x0300
#define DIV_DMC1 0x0504
#define GATE_BUS_DMC0 0x0700
#define GATE_BUS_DMC1 0x0704
#define GATE_BUS_DMC2 0x0708
#define GATE_BUS_DMC3 0x070c
#define GATE_SCLK_DMC 0x0800
#define GATE_IP_DMC0 0x0900
#define GATE_IP_DMC1 0x0904
#define EPLL_LOCK 0x1110
#define EPLL_CON0 0x1114
#define EPLL_CON1 0x1118
#define EPLL_CON2 0x111c
#define SRC_EPLL 0x1120
static const unsigned long exynos3250_cmu_dmc_clk_regs[] __initconst = {
BPLL_LOCK,
BPLL_CON0,
BPLL_CON1,
BPLL_CON2,
SRC_DMC,
DIV_DMC1,
GATE_BUS_DMC0,
GATE_BUS_DMC1,
GATE_BUS_DMC2,
GATE_BUS_DMC3,
GATE_SCLK_DMC,
GATE_IP_DMC0,
GATE_IP_DMC1,
EPLL_LOCK,
EPLL_CON0,
EPLL_CON1,
EPLL_CON2,
SRC_EPLL,
};
PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", };
PNAME(mout_mpll_mif_p) = { "fin_pll", "sclk_mpll_mif", };
PNAME(mout_dphy_p) = { "mout_mpll_mif", "mout_bpll", };
static const struct samsung_mux_clock dmc_mux_clks[] __initconst = {
/*
* NOTE: Following table is sorted by register address in ascending
* order and then bitfield shift in descending order, as it is done
* in the User's Manual. When adding new entries, please make sure
* that the order is preserved, to avoid merge conflicts and make
* further work with defined data easier.
*/
/* SRC_DMC */
MUX(CLK_MOUT_MPLL_MIF, "mout_mpll_mif", mout_mpll_mif_p, SRC_DMC, 12, 1),
MUX(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1),
MUX(CLK_MOUT_DPHY, "mout_dphy", mout_dphy_p, SRC_DMC, 8, 1),
MUX(CLK_MOUT_DMC_BUS, "mout_dmc_bus", mout_dphy_p, SRC_DMC, 4, 1),
/* SRC_EPLL */
MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_EPLL, 4, 1),
};
static const struct samsung_div_clock dmc_div_clks[] __initconst = {
/*
* NOTE: Following table is sorted by register address in ascending
* order and then bitfield shift in descending order, as it is done
* in the User's Manual. When adding new entries, please make sure
* that the order is preserved, to avoid merge conflicts and make
* further work with defined data easier.
*/
/* DIV_DMC1 */
DIV(CLK_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3),
DIV(CLK_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3),
DIV(CLK_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus", DIV_DMC1, 19, 2),
DIV(CLK_DIV_DMCP, "div_dmcp", "div_dmcd", DIV_DMC1, 15, 3),
DIV(CLK_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),
};
static const struct samsung_pll_clock exynos3250_dmc_plls[] __initconst = {
PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll",
BPLL_LOCK, BPLL_CON0, exynos3250_pll_rates),
PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
EPLL_LOCK, EPLL_CON0, exynos3250_epll_rates),
};
static const struct samsung_cmu_info dmc_cmu_info __initconst = {
.pll_clks = exynos3250_dmc_plls,
.nr_pll_clks = ARRAY_SIZE(exynos3250_dmc_plls),
.mux_clks = dmc_mux_clks,
.nr_mux_clks = ARRAY_SIZE(dmc_mux_clks),
.div_clks = dmc_div_clks,
.nr_div_clks = ARRAY_SIZE(dmc_div_clks),
.nr_clk_ids = CLKS_NR_DMC,
.clk_regs = exynos3250_cmu_dmc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs),
};
static void __init exynos3250_cmu_dmc_init(struct device_node *np)
{
samsung_cmu_register_one(np, &dmc_cmu_info);
}
CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc",
exynos3250_cmu_dmc_init);
/*
* CMU ISP
*/
#define DIV_ISP0 0x300
#define DIV_ISP1 0x304
#define GATE_IP_ISP0 0x800
#define GATE_IP_ISP1 0x804
#define GATE_SCLK_ISP 0x900
static const struct samsung_div_clock isp_div_clks[] __initconst = {
/*
* NOTE: Following table is sorted by register address in ascending
* order and then bitfield shift in descending order, as it is done
* in the User's Manual. When adding new entries, please make sure
* that the order is preserved, to avoid merge conflicts and make
* further work with defined data easier.
*/
/* DIV_ISP0 */
DIV(CLK_DIV_ISP1, "div_isp1", "mout_aclk_266_sub", DIV_ISP0, 4, 3),
DIV(CLK_DIV_ISP0, "div_isp0", "mout_aclk_266_sub", DIV_ISP0, 0, 3),
/* DIV_ISP1 */
DIV(CLK_DIV_MCUISP1, "div_mcuisp1", "mout_aclk_400_mcuisp_sub",
DIV_ISP1, 8, 3),
DIV(CLK_DIV_MCUISP0, "div_mcuisp0", "mout_aclk_400_mcuisp_sub",
DIV_ISP1, 4, 3),
DIV(CLK_DIV_MPWM, "div_mpwm", "div_isp1", DIV_ISP1, 0, 3),
};
static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
/*
* NOTE: Following table is sorted by register address in ascending
* order and then bitfield shift in descending order, as it is done
* in the User's Manual. When adding new entries, please make sure
* that the order is preserved, to avoid merge conflicts and make
* further work with defined data easier.
*/
/* GATE_IP_ISP0 */
GATE(CLK_UART_ISP, "uart_isp", "uart_isp_top",
GATE_IP_ISP0, 31, CLK_IGNORE_UNUSED, 0),
GATE(CLK_WDT_ISP, "wdt_isp", "mout_aclk_266_sub",
GATE_IP_ISP0, 30, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PWM_ISP, "pwm_isp", "mout_aclk_266_sub",
GATE_IP_ISP0, 28, CLK_IGNORE_UNUSED, 0),
GATE(CLK_I2C1_ISP, "i2c1_isp", "mout_aclk_266_sub",
GATE_IP_ISP0, 26, CLK_IGNORE_UNUSED, 0),
GATE(CLK_I2C0_ISP, "i2c0_isp", "mout_aclk_266_sub",
GATE_IP_ISP0, 25, CLK_IGNORE_UNUSED, 0),
GATE(CLK_MPWM_ISP, "mpwm_isp", "mout_aclk_266_sub",
GATE_IP_ISP0, 24, CLK_IGNORE_UNUSED, 0),
GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "mout_aclk_266_sub",
GATE_IP_ISP0, 23, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PPMUISPX, "ppmuispx", "mout_aclk_266_sub",
GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PPMUISPMX, "ppmuispmx", "mout_aclk_266_sub",
GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0),
GATE(CLK_QE_LITE1, "qe_lite1", "mout_aclk_266_sub",
GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0),
GATE(CLK_QE_LITE0, "qe_lite0", "mout_aclk_266_sub",
GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0),
GATE(CLK_QE_FD, "qe_fd", "mout_aclk_266_sub",
GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0),
GATE(CLK_QE_DRC, "qe_drc", "mout_aclk_266_sub",
GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_QE_ISP, "qe_isp", "mout_aclk_266_sub",
GATE_IP_ISP0, 14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_CSIS1, "csis1", "mout_aclk_266_sub",
GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SMMU_LITE1, "smmu_lite1", "mout_aclk_266_sub",
GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SMMU_LITE0, "smmu_lite0", "mout_aclk_266_sub",
GATE_IP_ISP0, 11, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SMMU_FD, "smmu_fd", "mout_aclk_266_sub",
GATE_IP_ISP0, 10, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SMMU_DRC, "smmu_drc", "mout_aclk_266_sub",
GATE_IP_ISP0, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SMMU_ISP, "smmu_isp", "mout_aclk_266_sub",
GATE_IP_ISP0, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GICISP, "gicisp", "mout_aclk_266_sub",
GATE_IP_ISP0, 7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_CSIS0, "csis0", "mout_aclk_266_sub",
GATE_IP_ISP0, 6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_MCUISP, "mcuisp", "mout_aclk_266_sub",
GATE_IP_ISP0, 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_LITE1, "lite1", "mout_aclk_266_sub",
GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_LITE0, "lite0", "mout_aclk_266_sub",
GATE_IP_ISP0, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_FD, "fd", "mout_aclk_266_sub",
GATE_IP_ISP0, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_DRC, "drc", "mout_aclk_266_sub",
GATE_IP_ISP0, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ISP, "isp", "mout_aclk_266_sub",
GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0),
/* GATE_IP_ISP1 */
GATE(CLK_QE_ISPCX, "qe_ispcx", "uart_isp_top",
GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_QE_SCALERP, "qe_scalerp", "uart_isp_top",
GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0),
GATE(CLK_QE_SCALERC, "qe_scalerc", "uart_isp_top",
GATE_IP_ISP0, 19, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SMMU_SCALERP, "smmu_scalerp", "uart_isp_top",
GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SMMU_SCALERC, "smmu_scalerc", "uart_isp_top",
GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCALERP, "scalerp", "uart_isp_top",
GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCALERC, "scalerc", "uart_isp_top",
GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SPI1_ISP, "spi1_isp", "uart_isp_top",
GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SPI0_ISP, "spi0_isp", "uart_isp_top",
GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "uart_isp_top",
GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ASYNCAXIM, "asyncaxim", "uart_isp_top",
GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0),
/* GATE_SCLK_ISP */
GATE(CLK_SCLK_MPWM_ISP, "sclk_mpwm_isp", "div_mpwm",
GATE_SCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_cmu_info isp_cmu_info __initconst = {
.div_clks = isp_div_clks,
.nr_div_clks = ARRAY_SIZE(isp_div_clks),
.gate_clks = isp_gate_clks,
.nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
.nr_clk_ids = CLKS_NR_ISP,
};
static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
samsung_cmu_register_one(np, &isp_cmu_info);
return 0;
}
static const struct of_device_id exynos3250_cmu_isp_of_match[] __initconst = {
{ .compatible = "samsung,exynos3250-cmu-isp", },
{ /* sentinel */ }
};
static struct platform_driver exynos3250_cmu_isp_driver __initdata = {
.driver = {
.name = "exynos3250-cmu-isp",
.suppress_bind_attrs = true,
.of_match_table = exynos3250_cmu_isp_of_match,
},
};
static int __init exynos3250_cmu_platform_init(void)
{
return platform_driver_probe(&exynos3250_cmu_isp_driver,
exynos3250_cmu_isp_probe);
}
subsys_initcall(exynos3250_cmu_platform_init);
| linux-master | drivers/clk/samsung/clk-exynos3250.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Author: Chanwoo Choi <[email protected]>
*
* Common Clock Framework support for Exynos5433 SoC.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <dt-bindings/clock/exynos5433.h>
#include "clk.h"
#include "clk-cpu.h"
#include "clk-exynos-arm64.h"
#include "clk-pll.h"
/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR_TOP (CLK_SCLK_HDMI_SPDIF_DISP + 1)
#define CLKS_NR_CPIF (CLK_SCLK_UFS_MPHY + 1)
#define CLKS_NR_MIF (CLK_SCLK_BUS_PLL_ATLAS + 1)
#define CLKS_NR_PERIC (CLK_DIV_SCLK_SC_IN + 1)
#define CLKS_NR_PERIS (CLK_SCLK_OTP_CON + 1)
#define CLKS_NR_FSYS (CLK_PCIE + 1)
#define CLKS_NR_G2D (CLK_PCLK_SMMU_G2D + 1)
#define CLKS_NR_DISP (CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY + 1)
#define CLKS_NR_AUD (CLK_SCLK_AUD_I2S + 1)
#define CLKS_NR_BUSX (CLK_ACLK_BUS2RTND_400 + 1)
#define CLKS_NR_G3D (CLK_SCLK_HPM_G3D + 1)
#define CLKS_NR_GSCL (CLK_PCLK_SMMU_GSCL2 + 1)
#define CLKS_NR_APOLLO (CLK_SCLK_APOLLO + 1)
#define CLKS_NR_ATLAS (CLK_SCLK_ATLAS + 1)
#define CLKS_NR_MSCL (CLK_SCLK_JPEG + 1)
#define CLKS_NR_MFC (CLK_PCLK_SMMU_MFC_0 + 1)
#define CLKS_NR_HEVC (CLK_PCLK_SMMU_HEVC_0 + 1)
#define CLKS_NR_ISP (CLK_SCLK_PIXELASYNCM_ISPC + 1)
#define CLKS_NR_CAM0 (CLK_SCLK_PIXELASYNCS_LITE_C_INIT + 1)
#define CLKS_NR_CAM1 (CLK_SCLK_ISP_CA5 + 1)
#define CLKS_NR_IMEM (CLK_PCLK_SLIMSSS + 1)
/*
* Register offset definitions for CMU_TOP
*/
#define ISP_PLL_LOCK 0x0000
#define AUD_PLL_LOCK 0x0004
#define ISP_PLL_CON0 0x0100
#define ISP_PLL_CON1 0x0104
#define ISP_PLL_FREQ_DET 0x0108
#define AUD_PLL_CON0 0x0110
#define AUD_PLL_CON1 0x0114
#define AUD_PLL_CON2 0x0118
#define AUD_PLL_FREQ_DET 0x011c
#define MUX_SEL_TOP0 0x0200
#define MUX_SEL_TOP1 0x0204
#define MUX_SEL_TOP2 0x0208
#define MUX_SEL_TOP3 0x020c
#define MUX_SEL_TOP4 0x0210
#define MUX_SEL_TOP_MSCL 0x0220
#define MUX_SEL_TOP_CAM1 0x0224
#define MUX_SEL_TOP_DISP 0x0228
#define MUX_SEL_TOP_FSYS0 0x0230
#define MUX_SEL_TOP_FSYS1 0x0234
#define MUX_SEL_TOP_PERIC0 0x0238
#define MUX_SEL_TOP_PERIC1 0x023c
#define MUX_ENABLE_TOP0 0x0300
#define MUX_ENABLE_TOP1 0x0304
#define MUX_ENABLE_TOP2 0x0308
#define MUX_ENABLE_TOP3 0x030c
#define MUX_ENABLE_TOP4 0x0310
#define MUX_ENABLE_TOP_MSCL 0x0320
#define MUX_ENABLE_TOP_CAM1 0x0324
#define MUX_ENABLE_TOP_DISP 0x0328
#define MUX_ENABLE_TOP_FSYS0 0x0330
#define MUX_ENABLE_TOP_FSYS1 0x0334
#define MUX_ENABLE_TOP_PERIC0 0x0338
#define MUX_ENABLE_TOP_PERIC1 0x033c
#define MUX_STAT_TOP0 0x0400
#define MUX_STAT_TOP1 0x0404
#define MUX_STAT_TOP2 0x0408
#define MUX_STAT_TOP3 0x040c
#define MUX_STAT_TOP4 0x0410
#define MUX_STAT_TOP_MSCL 0x0420
#define MUX_STAT_TOP_CAM1 0x0424
#define MUX_STAT_TOP_FSYS0 0x0430
#define MUX_STAT_TOP_FSYS1 0x0434
#define MUX_STAT_TOP_PERIC0 0x0438
#define MUX_STAT_TOP_PERIC1 0x043c
#define DIV_TOP0 0x0600
#define DIV_TOP1 0x0604
#define DIV_TOP2 0x0608
#define DIV_TOP3 0x060c
#define DIV_TOP4 0x0610
#define DIV_TOP_MSCL 0x0618
#define DIV_TOP_CAM10 0x061c
#define DIV_TOP_CAM11 0x0620
#define DIV_TOP_FSYS0 0x062c
#define DIV_TOP_FSYS1 0x0630
#define DIV_TOP_FSYS2 0x0634
#define DIV_TOP_PERIC0 0x0638
#define DIV_TOP_PERIC1 0x063c
#define DIV_TOP_PERIC2 0x0640
#define DIV_TOP_PERIC3 0x0644
#define DIV_TOP_PERIC4 0x0648
#define DIV_TOP_PLL_FREQ_DET 0x064c
#define DIV_STAT_TOP0 0x0700
#define DIV_STAT_TOP1 0x0704
#define DIV_STAT_TOP2 0x0708
#define DIV_STAT_TOP3 0x070c
#define DIV_STAT_TOP4 0x0710
#define DIV_STAT_TOP_MSCL 0x0718
#define DIV_STAT_TOP_CAM10 0x071c
#define DIV_STAT_TOP_CAM11 0x0720
#define DIV_STAT_TOP_FSYS0 0x072c
#define DIV_STAT_TOP_FSYS1 0x0730
#define DIV_STAT_TOP_FSYS2 0x0734
#define DIV_STAT_TOP_PERIC0 0x0738
#define DIV_STAT_TOP_PERIC1 0x073c
#define DIV_STAT_TOP_PERIC2 0x0740
#define DIV_STAT_TOP_PERIC3 0x0744
#define DIV_STAT_TOP_PLL_FREQ_DET 0x074c
#define ENABLE_ACLK_TOP 0x0800
#define ENABLE_SCLK_TOP 0x0a00
#define ENABLE_SCLK_TOP_MSCL 0x0a04
#define ENABLE_SCLK_TOP_CAM1 0x0a08
#define ENABLE_SCLK_TOP_DISP 0x0a0c
#define ENABLE_SCLK_TOP_FSYS 0x0a10
#define ENABLE_SCLK_TOP_PERIC 0x0a14
#define ENABLE_IP_TOP 0x0b00
#define ENABLE_CMU_TOP 0x0c00
#define ENABLE_CMU_TOP_DIV_STAT 0x0c04
static const unsigned long top_clk_regs[] __initconst = {
ISP_PLL_LOCK,
AUD_PLL_LOCK,
ISP_PLL_CON0,
ISP_PLL_CON1,
ISP_PLL_FREQ_DET,
AUD_PLL_CON0,
AUD_PLL_CON1,
AUD_PLL_CON2,
AUD_PLL_FREQ_DET,
MUX_SEL_TOP0,
MUX_SEL_TOP1,
MUX_SEL_TOP2,
MUX_SEL_TOP3,
MUX_SEL_TOP4,
MUX_SEL_TOP_MSCL,
MUX_SEL_TOP_CAM1,
MUX_SEL_TOP_DISP,
MUX_SEL_TOP_FSYS0,
MUX_SEL_TOP_FSYS1,
MUX_SEL_TOP_PERIC0,
MUX_SEL_TOP_PERIC1,
MUX_ENABLE_TOP0,
MUX_ENABLE_TOP1,
MUX_ENABLE_TOP2,
MUX_ENABLE_TOP3,
MUX_ENABLE_TOP4,
MUX_ENABLE_TOP_MSCL,
MUX_ENABLE_TOP_CAM1,
MUX_ENABLE_TOP_DISP,
MUX_ENABLE_TOP_FSYS0,
MUX_ENABLE_TOP_FSYS1,
MUX_ENABLE_TOP_PERIC0,
MUX_ENABLE_TOP_PERIC1,
DIV_TOP0,
DIV_TOP1,
DIV_TOP2,
DIV_TOP3,
DIV_TOP4,
DIV_TOP_MSCL,
DIV_TOP_CAM10,
DIV_TOP_CAM11,
DIV_TOP_FSYS0,
DIV_TOP_FSYS1,
DIV_TOP_FSYS2,
DIV_TOP_PERIC0,
DIV_TOP_PERIC1,
DIV_TOP_PERIC2,
DIV_TOP_PERIC3,
DIV_TOP_PERIC4,
DIV_TOP_PLL_FREQ_DET,
ENABLE_ACLK_TOP,
ENABLE_SCLK_TOP,
ENABLE_SCLK_TOP_MSCL,
ENABLE_SCLK_TOP_CAM1,
ENABLE_SCLK_TOP_DISP,
ENABLE_SCLK_TOP_FSYS,
ENABLE_SCLK_TOP_PERIC,
ENABLE_IP_TOP,
ENABLE_CMU_TOP,
ENABLE_CMU_TOP_DIV_STAT,
};
static const struct samsung_clk_reg_dump top_suspend_regs[] = {
/* force all aclk clocks enabled */
{ ENABLE_ACLK_TOP, 0x67ecffed },
/* force all sclk_uart clocks enabled */
{ ENABLE_SCLK_TOP_PERIC, 0x38 },
/* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
{ ISP_PLL_CON0, 0x85cc0502 },
/* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
{ AUD_PLL_CON0, 0x84830202 },
};
/* list of all parent clock list */
PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", };
PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", };
PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", };
PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", };
PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", };
PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", };
PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", };
PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", };
PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",};
PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",};
PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a",
"mout_mfc_pll_user", };
PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", };
PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b",
"mout_mphy_pll_user", };
PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a",
"mout_bus_pll_user", };
PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", };
PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
"mout_mphy_pll_user", };
PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a",
"mout_mphy_pll_user", };
PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a",
"mout_mphy_pll_user", };
PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", };
PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1",
"oscclk", "ioclk_spdif_extclk", };
PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk",
"mout_aud_pll_user_t",};
PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk",
"mout_aud_pll_user_t",};
PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", };
static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
};
static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = {
/* Xi2s{0|1}CDCLK input clock for I2S/PCM */
FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000),
FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000),
/* Xi2s1SDI input clock for SPDIF */
FRATE(0, "ioclk_spdif_extclk", NULL, 0, 100000000),
/* XspiCLK[4:0] input clock for SPI */
FRATE(0, "ioclk_spi4_clk_in", NULL, 0, 50000000),
FRATE(0, "ioclk_spi3_clk_in", NULL, 0, 50000000),
FRATE(0, "ioclk_spi2_clk_in", NULL, 0, 50000000),
FRATE(0, "ioclk_spi1_clk_in", NULL, 0, 50000000),
FRATE(0, "ioclk_spi0_clk_in", NULL, 0, 50000000),
/* Xi2s1SCLK input clock for I2S1_BCLK */
FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000),
};
static const struct samsung_mux_clock top_mux_clks[] __initconst = {
/* MUX_SEL_TOP0 */
MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
4, 1),
MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
0, 1),
/* MUX_SEL_TOP1 */
MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
MUX_SEL_TOP1, 8, 1),
MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
MUX_SEL_TOP1, 4, 1),
MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
MUX_SEL_TOP1, 0, 1),
/* MUX_SEL_TOP2 */
MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
/* MUX_SEL_TOP3 */
MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
/* MUX_SEL_TOP4 */
MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
/* MUX_SEL_TOP_MSCL */
MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
MUX_SEL_TOP_MSCL, 8, 1),
MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
MUX_SEL_TOP_MSCL, 4, 1),
MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
MUX_SEL_TOP_MSCL, 0, 1),
/* MUX_SEL_TOP_CAM1 */
MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
/* MUX_SEL_TOP_FSYS0 */
MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
MUX_SEL_TOP_FSYS0, 28, 1),
MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
MUX_SEL_TOP_FSYS0, 24, 1),
MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
MUX_SEL_TOP_FSYS0, 20, 1),
MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
MUX_SEL_TOP_FSYS0, 16, 1),
MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
MUX_SEL_TOP_FSYS0, 12, 1),
MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
MUX_SEL_TOP_FSYS0, 8, 1),
MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
MUX_SEL_TOP_FSYS0, 4, 1),
MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
MUX_SEL_TOP_FSYS0, 0, 1),
/* MUX_SEL_TOP_FSYS1 */
MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
MUX_SEL_TOP_FSYS1, 12, 1),
MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
/* MUX_SEL_TOP_PERIC0 */
MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
MUX_SEL_TOP_PERIC0, 28, 1),
MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
MUX_SEL_TOP_PERIC0, 24, 1),
MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
MUX_SEL_TOP_PERIC0, 20, 1),
MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
MUX_SEL_TOP_PERIC0, 16, 1),
MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
MUX_SEL_TOP_PERIC0, 12, 1),
MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
MUX_SEL_TOP_PERIC0, 8, 1),
MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
MUX_SEL_TOP_PERIC0, 4, 1),
MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
MUX_SEL_TOP_PERIC0, 0, 1),
/* MUX_SEL_TOP_PERIC1 */
MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
MUX_SEL_TOP_PERIC1, 16, 1),
MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
MUX_SEL_TOP_PERIC1, 12, 2),
MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
MUX_SEL_TOP_PERIC1, 4, 2),
MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
MUX_SEL_TOP_PERIC1, 0, 2),
/* MUX_SEL_TOP_DISP */
MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
};
static const struct samsung_div_clock top_div_clks[] __initconst = {
/* DIV_TOP0 */
DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333",
DIV_TOP0, 28, 3),
DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user",
DIV_TOP0, 24, 3),
DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b",
DIV_TOP0, 20, 3),
DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user",
DIV_TOP0, 16, 3),
DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user",
DIV_TOP0, 12, 3),
DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll",
DIV_TOP0, 8, 3),
DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400",
"mout_aclk_isp_dis_400", DIV_TOP0, 4, 4),
DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400",
"mout_aclk_isp_400", DIV_TOP0, 0, 4),
/* DIV_TOP1 */
DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
DIV_TOP1, 28, 3),
DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
DIV_TOP1, 24, 3),
DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
DIV_TOP1, 20, 3),
DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
DIV_TOP1, 12, 3),
DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
DIV_TOP1, 8, 3),
DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
DIV_TOP1, 0, 3),
/* DIV_TOP2 */
DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b",
DIV_TOP2, 4, 3),
DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
DIV_TOP2, 0, 3),
/* DIV_TOP3 */
DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
"mout_bus_pll_user", DIV_TOP3, 24, 3),
DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
"mout_bus_pll_user", DIV_TOP3, 20, 3),
DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
"mout_bus_pll_user", DIV_TOP3, 16, 3),
DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
"div_aclk_peric_66_a", DIV_TOP3, 12, 3),
DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
"mout_bus_pll_user", DIV_TOP3, 8, 3),
DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
"div_aclk_peris_66_a", DIV_TOP3, 4, 3),
DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
"mout_bus_pll_user", DIV_TOP3, 0, 3),
/* DIV_TOP4 */
DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
DIV_TOP4, 8, 3),
DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
DIV_TOP4, 4, 3),
DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
DIV_TOP4, 0, 3),
/* DIV_TOP_MSCL */
DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c",
DIV_TOP_MSCL, 0, 4),
/* DIV_TOP_CAM10 */
DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart",
DIV_TOP_CAM10, 24, 5),
DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b",
"div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8),
DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a",
"mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4),
DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b",
"div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8),
DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a",
"mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4),
/* DIV_TOP_CAM11 */
DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b",
"div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4),
DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a",
"mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4),
DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b",
"div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4),
DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a",
"mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4),
DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b",
"div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 4, 4),
DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a",
"mout_sclk_isp_sensor0", DIV_TOP_CAM11, 0, 4),
/* DIV_TOP_FSYS0 */
DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
DIV_TOP_FSYS0, 16, 8),
DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
DIV_TOP_FSYS0, 12, 4),
DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
/* DIV_TOP_FSYS1 */
DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
DIV_TOP_FSYS1, 4, 8),
DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
DIV_TOP_FSYS1, 0, 4),
/* DIV_TOP_FSYS2 */
DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
DIV_TOP_FSYS2, 12, 3),
DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
"mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
"mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
DIV_TOP_FSYS2, 0, 4),
/* DIV_TOP_PERIC0 */
DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
DIV_TOP_PERIC0, 16, 8),
DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
DIV_TOP_PERIC0, 12, 4),
DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
DIV_TOP_PERIC0, 4, 8),
DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
DIV_TOP_PERIC0, 0, 4),
/* DIV_TOP_PERIC1 */
DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
DIV_TOP_PERIC1, 4, 8),
DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
DIV_TOP_PERIC1, 0, 4),
/* DIV_TOP_PERIC2 */
DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
DIV_TOP_PERIC2, 8, 4),
DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
DIV_TOP_PERIC2, 4, 4),
DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
DIV_TOP_PERIC2, 0, 4),
/* DIV_TOP_PERIC3 */
DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
DIV_TOP_PERIC3, 16, 6),
DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
DIV_TOP_PERIC3, 8, 8),
DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
DIV_TOP_PERIC3, 4, 4),
DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
DIV_TOP_PERIC3, 0, 4),
/* DIV_TOP_PERIC4 */
DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
DIV_TOP_PERIC4, 16, 8),
DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
DIV_TOP_PERIC4, 12, 4),
DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
DIV_TOP_PERIC4, 4, 8),
DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
DIV_TOP_PERIC4, 0, 4),
};
static const struct samsung_gate_clock top_gate_clks[] __initconst = {
/* ENABLE_ACLK_TOP */
GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0),
GATE(CLK_ACLK_IMEM_SSSX_266, "aclk_imem_sssx_266",
"div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
29, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
ENABLE_ACLK_TOP, 26,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
ENABLE_ACLK_TOP, 25,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_200",
ENABLE_ACLK_TOP, 24,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_266",
ENABLE_ACLK_TOP, 23,
CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
ENABLE_ACLK_TOP, 22,
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
ENABLE_ACLK_TOP, 21,
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
ENABLE_ACLK_TOP, 19,
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
ENABLE_ACLK_TOP, 18,
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
ENABLE_ACLK_TOP, 15,
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
ENABLE_ACLK_TOP, 14,
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333",
ENABLE_ACLK_TOP, 13,
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
ENABLE_ACLK_TOP, 12,
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
ENABLE_ACLK_TOP, 11,
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333",
ENABLE_ACLK_TOP, 10,
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
ENABLE_ACLK_TOP, 9,
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
ENABLE_ACLK_TOP, 8,
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
ENABLE_ACLK_TOP, 7,
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
ENABLE_ACLK_TOP, 6,
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
ENABLE_ACLK_TOP, 5,
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
ENABLE_ACLK_TOP, 3,
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
ENABLE_ACLK_TOP, 2,
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
ENABLE_ACLK_TOP, 0,
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
/* ENABLE_SCLK_TOP_MSCL */
GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
ENABLE_SCLK_TOP_MSCL, 0, CLK_SET_RATE_PARENT, 0),
/* ENABLE_SCLK_TOP_CAM1 */
GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk",
ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
ENABLE_SCLK_TOP_CAM1, 2, 0, 0),
GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
/* ENABLE_SCLK_TOP_DISP */
GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
"mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
CLK_IGNORE_UNUSED, 0),
/* ENABLE_SCLK_TOP_FSYS */
GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
"div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
3, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
"div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
1, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
"div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS,
0, CLK_SET_RATE_PARENT, 0),
/* ENABLE_SCLK_TOP_PERIC */
GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT |
CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT |
CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT |
CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
/* MUX_ENABLE_TOP_PERIC1 */
GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
};
/*
* ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
* & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
*/
static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = {
PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0),
PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0),
PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0),
PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6, 0),
PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4, 0),
PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6, 0),
PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6, 0),
PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5, 0),
PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6, 0),
PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6, 0),
PLL_35XX_RATE(24 * MHZ, 1500000000U, 250, 4, 0),
PLL_35XX_RATE(24 * MHZ, 1400000000U, 350, 6, 0),
PLL_35XX_RATE(24 * MHZ, 1332000000U, 222, 4, 0),
PLL_35XX_RATE(24 * MHZ, 1300000000U, 325, 6, 0),
PLL_35XX_RATE(24 * MHZ, 1200000000U, 500, 5, 1),
PLL_35XX_RATE(24 * MHZ, 1100000000U, 550, 6, 1),
PLL_35XX_RATE(24 * MHZ, 1086000000U, 362, 4, 1),
PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 6, 1),
PLL_35XX_RATE(24 * MHZ, 1000000000U, 500, 6, 1),
PLL_35XX_RATE(24 * MHZ, 933000000U, 311, 4, 1),
PLL_35XX_RATE(24 * MHZ, 921000000U, 307, 4, 1),
PLL_35XX_RATE(24 * MHZ, 900000000U, 375, 5, 1),
PLL_35XX_RATE(24 * MHZ, 825000000U, 275, 4, 1),
PLL_35XX_RATE(24 * MHZ, 800000000U, 400, 6, 1),
PLL_35XX_RATE(24 * MHZ, 733000000U, 733, 12, 1),
PLL_35XX_RATE(24 * MHZ, 700000000U, 175, 3, 1),
PLL_35XX_RATE(24 * MHZ, 666000000U, 222, 4, 1),
PLL_35XX_RATE(24 * MHZ, 633000000U, 211, 4, 1),
PLL_35XX_RATE(24 * MHZ, 600000000U, 500, 5, 2),
PLL_35XX_RATE(24 * MHZ, 552000000U, 460, 5, 2),
PLL_35XX_RATE(24 * MHZ, 550000000U, 550, 6, 2),
PLL_35XX_RATE(24 * MHZ, 543000000U, 362, 4, 2),
PLL_35XX_RATE(24 * MHZ, 533000000U, 533, 6, 2),
PLL_35XX_RATE(24 * MHZ, 500000000U, 500, 6, 2),
PLL_35XX_RATE(24 * MHZ, 444000000U, 370, 5, 2),
PLL_35XX_RATE(24 * MHZ, 420000000U, 350, 5, 2),
PLL_35XX_RATE(24 * MHZ, 400000000U, 400, 6, 2),
PLL_35XX_RATE(24 * MHZ, 350000000U, 350, 6, 2),
PLL_35XX_RATE(24 * MHZ, 333000000U, 222, 4, 2),
PLL_35XX_RATE(24 * MHZ, 300000000U, 500, 5, 3),
PLL_35XX_RATE(24 * MHZ, 278000000U, 556, 6, 3),
PLL_35XX_RATE(24 * MHZ, 266000000U, 532, 6, 3),
PLL_35XX_RATE(24 * MHZ, 250000000U, 500, 6, 3),
PLL_35XX_RATE(24 * MHZ, 200000000U, 400, 6, 3),
PLL_35XX_RATE(24 * MHZ, 166000000U, 332, 6, 3),
PLL_35XX_RATE(24 * MHZ, 160000000U, 320, 6, 3),
PLL_35XX_RATE(24 * MHZ, 133000000U, 532, 6, 4),
PLL_35XX_RATE(24 * MHZ, 100000000U, 400, 6, 4),
{ /* sentinel */ }
};
/* AUD_PLL */
static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = {
PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
PLL_36XX_RATE(24 * MHZ, 384000000U, 128, 2, 2, 0),
PLL_36XX_RATE(24 * MHZ, 368639991U, 246, 4, 2, -15729),
PLL_36XX_RATE(24 * MHZ, 361507202U, 181, 3, 2, -16148),
PLL_36XX_RATE(24 * MHZ, 338687988U, 113, 2, 2, -6816),
PLL_36XX_RATE(24 * MHZ, 294912002U, 98, 1, 3, 19923),
PLL_36XX_RATE(24 * MHZ, 288000000U, 96, 1, 3, 0),
PLL_36XX_RATE(24 * MHZ, 252000000U, 84, 1, 3, 0),
PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
{ /* sentinel */ }
};
static const struct samsung_pll_clock top_pll_clks[] __initconst = {
PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
ISP_PLL_LOCK, ISP_PLL_CON0, exynos5433_pll_rates),
PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
AUD_PLL_LOCK, AUD_PLL_CON0, exynos5433_aud_pll_rates),
};
static const struct samsung_cmu_info top_cmu_info __initconst = {
.pll_clks = top_pll_clks,
.nr_pll_clks = ARRAY_SIZE(top_pll_clks),
.mux_clks = top_mux_clks,
.nr_mux_clks = ARRAY_SIZE(top_mux_clks),
.div_clks = top_div_clks,
.nr_div_clks = ARRAY_SIZE(top_div_clks),
.gate_clks = top_gate_clks,
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
.fixed_clks = top_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(top_fixed_clks),
.fixed_factor_clks = top_fixed_factor_clks,
.nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
.nr_clk_ids = CLKS_NR_TOP,
.clk_regs = top_clk_regs,
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
.suspend_regs = top_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(top_suspend_regs),
};
static void __init exynos5433_cmu_top_init(struct device_node *np)
{
samsung_cmu_register_one(np, &top_cmu_info);
}
CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
exynos5433_cmu_top_init);
/*
* Register offset definitions for CMU_CPIF
*/
#define MPHY_PLL_LOCK 0x0000
#define MPHY_PLL_CON0 0x0100
#define MPHY_PLL_CON1 0x0104
#define MPHY_PLL_FREQ_DET 0x010c
#define MUX_SEL_CPIF0 0x0200
#define DIV_CPIF 0x0600
#define ENABLE_SCLK_CPIF 0x0a00
static const unsigned long cpif_clk_regs[] __initconst = {
MPHY_PLL_LOCK,
MPHY_PLL_CON0,
MPHY_PLL_CON1,
MPHY_PLL_FREQ_DET,
MUX_SEL_CPIF0,
DIV_CPIF,
ENABLE_SCLK_CPIF,
};
static const struct samsung_clk_reg_dump cpif_suspend_regs[] = {
/* force all sclk clocks enabled */
{ ENABLE_SCLK_CPIF, 0x3ff },
/* MPHY PLL has to be enabled for suspend: reset value + ENABLE bit */
{ MPHY_PLL_CON0, 0x81c70601 },
};
/* list of all parent clock list */
PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", };
static const struct samsung_pll_clock cpif_pll_clks[] __initconst = {
PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5433_pll_rates),
};
static const struct samsung_mux_clock cpif_mux_clks[] __initconst = {
/* MUX_SEL_CPIF0 */
MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
0, 1),
};
static const struct samsung_div_clock cpif_div_clks[] __initconst = {
/* DIV_CPIF */
DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
0, 6),
};
static const struct samsung_gate_clock cpif_gate_clks[] __initconst = {
/* ENABLE_SCLK_CPIF */
GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
ENABLE_SCLK_CPIF, 4, 0, 0),
};
static const struct samsung_cmu_info cpif_cmu_info __initconst = {
.pll_clks = cpif_pll_clks,
.nr_pll_clks = ARRAY_SIZE(cpif_pll_clks),
.mux_clks = cpif_mux_clks,
.nr_mux_clks = ARRAY_SIZE(cpif_mux_clks),
.div_clks = cpif_div_clks,
.nr_div_clks = ARRAY_SIZE(cpif_div_clks),
.gate_clks = cpif_gate_clks,
.nr_gate_clks = ARRAY_SIZE(cpif_gate_clks),
.nr_clk_ids = CLKS_NR_CPIF,
.clk_regs = cpif_clk_regs,
.nr_clk_regs = ARRAY_SIZE(cpif_clk_regs),
.suspend_regs = cpif_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(cpif_suspend_regs),
};
static void __init exynos5433_cmu_cpif_init(struct device_node *np)
{
samsung_cmu_register_one(np, &cpif_cmu_info);
}
CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
exynos5433_cmu_cpif_init);
/*
* Register offset definitions for CMU_MIF
*/
#define MEM0_PLL_LOCK 0x0000
#define MEM1_PLL_LOCK 0x0004
#define BUS_PLL_LOCK 0x0008
#define MFC_PLL_LOCK 0x000c
#define MEM0_PLL_CON0 0x0100
#define MEM0_PLL_CON1 0x0104
#define MEM0_PLL_FREQ_DET 0x010c
#define MEM1_PLL_CON0 0x0110
#define MEM1_PLL_CON1 0x0114
#define MEM1_PLL_FREQ_DET 0x011c
#define BUS_PLL_CON0 0x0120
#define BUS_PLL_CON1 0x0124
#define BUS_PLL_FREQ_DET 0x012c
#define MFC_PLL_CON0 0x0130
#define MFC_PLL_CON1 0x0134
#define MFC_PLL_FREQ_DET 0x013c
#define MUX_SEL_MIF0 0x0200
#define MUX_SEL_MIF1 0x0204
#define MUX_SEL_MIF2 0x0208
#define MUX_SEL_MIF3 0x020c
#define MUX_SEL_MIF4 0x0210
#define MUX_SEL_MIF5 0x0214
#define MUX_SEL_MIF6 0x0218
#define MUX_SEL_MIF7 0x021c
#define MUX_ENABLE_MIF0 0x0300
#define MUX_ENABLE_MIF1 0x0304
#define MUX_ENABLE_MIF2 0x0308
#define MUX_ENABLE_MIF3 0x030c
#define MUX_ENABLE_MIF4 0x0310
#define MUX_ENABLE_MIF5 0x0314
#define MUX_ENABLE_MIF6 0x0318
#define MUX_ENABLE_MIF7 0x031c
#define MUX_STAT_MIF0 0x0400
#define MUX_STAT_MIF1 0x0404
#define MUX_STAT_MIF2 0x0408
#define MUX_STAT_MIF3 0x040c
#define MUX_STAT_MIF4 0x0410
#define MUX_STAT_MIF5 0x0414
#define MUX_STAT_MIF6 0x0418
#define MUX_STAT_MIF7 0x041c
#define DIV_MIF1 0x0604
#define DIV_MIF2 0x0608
#define DIV_MIF3 0x060c
#define DIV_MIF4 0x0610
#define DIV_MIF5 0x0614
#define DIV_MIF_PLL_FREQ_DET 0x0618
#define DIV_STAT_MIF1 0x0704
#define DIV_STAT_MIF2 0x0708
#define DIV_STAT_MIF3 0x070c
#define DIV_STAT_MIF4 0x0710
#define DIV_STAT_MIF5 0x0714
#define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
#define ENABLE_ACLK_MIF0 0x0800
#define ENABLE_ACLK_MIF1 0x0804
#define ENABLE_ACLK_MIF2 0x0808
#define ENABLE_ACLK_MIF3 0x080c
#define ENABLE_PCLK_MIF 0x0900
#define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
#define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
#define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
#define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
#define ENABLE_SCLK_MIF 0x0a00
#define ENABLE_IP_MIF0 0x0b00
#define ENABLE_IP_MIF1 0x0b04
#define ENABLE_IP_MIF2 0x0b08
#define ENABLE_IP_MIF3 0x0b0c
#define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
#define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
#define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
#define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
#define CLKOUT_CMU_MIF 0x0c00
#define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
#define DREX_FREQ_CTRL0 0x1000
#define DREX_FREQ_CTRL1 0x1004
#define PAUSE 0x1008
#define DDRPHY_LOCK_CTRL 0x100c
static const unsigned long mif_clk_regs[] __initconst = {
MEM0_PLL_LOCK,
MEM1_PLL_LOCK,
BUS_PLL_LOCK,
MFC_PLL_LOCK,
MEM0_PLL_CON0,
MEM0_PLL_CON1,
MEM0_PLL_FREQ_DET,
MEM1_PLL_CON0,
MEM1_PLL_CON1,
MEM1_PLL_FREQ_DET,
BUS_PLL_CON0,
BUS_PLL_CON1,
BUS_PLL_FREQ_DET,
MFC_PLL_CON0,
MFC_PLL_CON1,
MFC_PLL_FREQ_DET,
MUX_SEL_MIF0,
MUX_SEL_MIF1,
MUX_SEL_MIF2,
MUX_SEL_MIF3,
MUX_SEL_MIF4,
MUX_SEL_MIF5,
MUX_SEL_MIF6,
MUX_SEL_MIF7,
MUX_ENABLE_MIF0,
MUX_ENABLE_MIF1,
MUX_ENABLE_MIF2,
MUX_ENABLE_MIF3,
MUX_ENABLE_MIF4,
MUX_ENABLE_MIF5,
MUX_ENABLE_MIF6,
MUX_ENABLE_MIF7,
DIV_MIF1,
DIV_MIF2,
DIV_MIF3,
DIV_MIF4,
DIV_MIF5,
DIV_MIF_PLL_FREQ_DET,
ENABLE_ACLK_MIF0,
ENABLE_ACLK_MIF1,
ENABLE_ACLK_MIF2,
ENABLE_ACLK_MIF3,
ENABLE_PCLK_MIF,
ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
ENABLE_PCLK_MIF_SECURE_RTC,
ENABLE_SCLK_MIF,
ENABLE_IP_MIF0,
ENABLE_IP_MIF1,
ENABLE_IP_MIF2,
ENABLE_IP_MIF3,
ENABLE_IP_MIF_SECURE_DREX0_TZ,
ENABLE_IP_MIF_SECURE_DREX1_TZ,
ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
ENABLE_IP_MIF_SECURE_RTC,
CLKOUT_CMU_MIF,
CLKOUT_CMU_MIF_DIV_STAT,
DREX_FREQ_CTRL0,
DREX_FREQ_CTRL1,
PAUSE,
DDRPHY_LOCK_CTRL,
};
static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5433_pll_rates),
PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5433_pll_rates),
PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
BUS_PLL_LOCK, BUS_PLL_CON0, exynos5433_pll_rates),
PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
MFC_PLL_LOCK, MFC_PLL_CON0, exynos5433_pll_rates),
};
/* list of all parent clock list */
PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", };
PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", };
PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", };
PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", };
PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", };
PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", };
PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", };
PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", };
PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", };
PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a",
"mout_bus_pll_div2", };
PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b",
"sclk_mphy_pll", };
PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a",
"mout_mfc_pll_div2", };
PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", };
PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b",
"sclk_mphy_pll", };
PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a",
"mout_mfc_pll_div2", };
PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
"sclk_mphy_pll", };
PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
"mout_mfc_pll_div2", };
PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", };
PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
"sclk_mphy_pll", };
PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
"mout_mfc_pll_div2", };
PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = {
/* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
};
static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
/* MUX_SEL_MIF0 */
MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
MUX_SEL_MIF0, 28, 1),
MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
MUX_SEL_MIF0, 24, 1),
MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
MUX_SEL_MIF0, 20, 1),
MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
MUX_SEL_MIF0, 16, 1),
MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
12, 1),
MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
8, 1),
MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
4, 1),
MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
0, 1),
/* MUX_SEL_MIF1 */
MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
MUX_SEL_MIF1, 24, 1),
MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
MUX_SEL_MIF1, 20, 1),
MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
MUX_SEL_MIF1, 16, 1),
MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p,
MUX_SEL_MIF1, 12, 1),
MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
MUX_SEL_MIF1, 8, 1),
MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p,
MUX_SEL_MIF1, 4, 1),
/* MUX_SEL_MIF2 */
MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
/* MUX_SEL_MIF3 */
MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
/* MUX_SEL_MIF4 */
MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1),
MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
/* MUX_SEL_MIF5 */
MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1),
MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
MUX_SEL_MIF5, 8, 1),
MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
MUX_SEL_MIF5, 4, 1),
MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
MUX_SEL_MIF5, 0, 1),
/* MUX_SEL_MIF6 */
MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
MUX_SEL_MIF6, 8, 1),
MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
MUX_SEL_MIF6, 4, 1),
MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p,
MUX_SEL_MIF6, 0, 1),
/* MUX_SEL_MIF7 */
MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1),
MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
MUX_SEL_MIF7, 8, 1),
MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
MUX_SEL_MIF7, 4, 1),
MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p,
MUX_SEL_MIF7, 0, 1),
};
static const struct samsung_div_clock mif_div_clks[] __initconst = {
/* DIV_MIF1 */
DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
DIV_MIF1, 16, 2),
DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
12, 2),
DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
8, 2),
DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
4, 4),
/* DIV_MIF2 */
DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
DIV_MIF2, 20, 3),
DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
DIV_MIF2, 16, 4),
DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
DIV_MIF2, 12, 4),
DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
"mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
DIV_MIF2, 4, 2),
DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
DIV_MIF2, 0, 3),
/* DIV_MIF3 */
DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
DIV_MIF3, 16, 4),
DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
DIV_MIF3, 4, 3),
DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
DIV_MIF3, 0, 3),
/* DIV_MIF4 */
DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
DIV_MIF4, 24, 4),
DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
"mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
DIV_MIF4, 16, 4),
DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
DIV_MIF4, 12, 4),
DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
"mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
"mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
"mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
/* DIV_MIF5 */
DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
0, 3),
};
static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
/* ENABLE_ACLK_MIF0 */
GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
19, CLK_IGNORE_UNUSED, 0),
GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
18, CLK_IGNORE_UNUSED, 0),
GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
17, CLK_IGNORE_UNUSED, 0),
GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
16, CLK_IGNORE_UNUSED, 0),
GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0,
15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0,
14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
/* ENABLE_ACLK_MIF1 */
GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
"div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
"div_aclk_mif_200", ENABLE_ACLK_MIF1,
27, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
"div_aclk_mif_133", ENABLE_ACLK_MIF1,
26, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
"div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
25, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
"div_aclk_drex1", ENABLE_ACLK_MIF1,
24, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
"div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
23, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
"div_aclk_drex0", ENABLE_ACLK_MIF1,
22, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
"div_aclk_mif_133", ENABLE_ACLK_MIF1,
21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
"div_aclk_drex1", ENABLE_ACLK_MIF1,
20, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
"div_aclk_mif_133", ENABLE_ACLK_MIF1,
19, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
"div_aclk_drex1", ENABLE_ACLK_MIF1,
18, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
"div_aclk_mif_133", ENABLE_ACLK_MIF1,
17, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
"div_aclk_drex1", ENABLE_ACLK_MIF1,
16, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
"div_aclk_mif_133", ENABLE_ACLK_MIF1,
15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
"div_aclk_drex0", ENABLE_ACLK_MIF1,
14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
"div_aclk_mif_133", ENABLE_ACLK_MIF1,
13, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
"div_aclk_drex0", ENABLE_ACLK_MIF1,
12, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
"div_aclk_mif_133", ENABLE_ACLK_MIF1,
11, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
"div_aclk_drex0", ENABLE_ACLK_MIF1,
10, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_ACLK_MIF2 */
GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
"div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
"div_aclk_mif_400", ENABLE_ACLK_MIF2,
5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
"div_aclk_mif_200", ENABLE_ACLK_MIF2,
3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
"div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
/* ENABLE_ACLK_MIF3 */
GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
ENABLE_ACLK_MIF3, 4,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
ENABLE_ACLK_MIF3, 1,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
ENABLE_ACLK_MIF3, 0,
CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
/* ENABLE_PCLK_MIF */
GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
"div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
ENABLE_PCLK_MIF, 19, 0, 0),
GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
ENABLE_PCLK_MIF, 18, 0, 0),
GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
"div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
"div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
"div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
"div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
"div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
"div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
ENABLE_PCLK_MIF, 11, 0, 0),
GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
ENABLE_PCLK_MIF, 7, 0, 0),
GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
ENABLE_PCLK_MIF, 5, 0, 0),
GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
ENABLE_PCLK_MIF, 2, 0, 0),
GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0,
CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0,
CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0),
/* ENABLE_PCLK_MIF_SECURE_RTC */
GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
/* ENABLE_SCLK_MIF */
GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
"div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
"div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
"div_sclk_decon_vclk", ENABLE_SCLK_MIF,
6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
"div_sclk_decon_eclk", ENABLE_SCLK_MIF,
5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
ENABLE_SCLK_MIF, 4,
CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_cmu_info mif_cmu_info __initconst = {
.pll_clks = mif_pll_clks,
.nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
.mux_clks = mif_mux_clks,
.nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
.div_clks = mif_div_clks,
.nr_div_clks = ARRAY_SIZE(mif_div_clks),
.gate_clks = mif_gate_clks,
.nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
.fixed_factor_clks = mif_fixed_factor_clks,
.nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks),
.nr_clk_ids = CLKS_NR_MIF,
.clk_regs = mif_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
};
static void __init exynos5433_cmu_mif_init(struct device_node *np)
{
samsung_cmu_register_one(np, &mif_cmu_info);
}
CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
exynos5433_cmu_mif_init);
/*
* Register offset definitions for CMU_PERIC
*/
#define DIV_PERIC 0x0600
#define DIV_STAT_PERIC 0x0700
#define ENABLE_ACLK_PERIC 0x0800
#define ENABLE_PCLK_PERIC0 0x0900
#define ENABLE_PCLK_PERIC1 0x0904
#define ENABLE_SCLK_PERIC 0x0A00
#define ENABLE_IP_PERIC0 0x0B00
#define ENABLE_IP_PERIC1 0x0B04
#define ENABLE_IP_PERIC2 0x0B08
static const unsigned long peric_clk_regs[] __initconst = {
DIV_PERIC,
ENABLE_ACLK_PERIC,
ENABLE_PCLK_PERIC0,
ENABLE_PCLK_PERIC1,
ENABLE_SCLK_PERIC,
ENABLE_IP_PERIC0,
ENABLE_IP_PERIC1,
ENABLE_IP_PERIC2,
};
static const struct samsung_clk_reg_dump peric_suspend_regs[] = {
/* pclk: sci, pmu, sysreg, gpio_{finger, ese, touch, nfc}, uart2-0 */
{ ENABLE_PCLK_PERIC0, 0xe00ff000 },
/* sclk: uart2-0 */
{ ENABLE_SCLK_PERIC, 0x7 },
};
static const struct samsung_div_clock peric_div_clks[] __initconst = {
/* DIV_PERIC */
DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
};
static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
/* ENABLE_ACLK_PERIC */
GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_PERIC0 */
GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
31, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
28, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
26, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
25, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
24, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
23, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
22, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
20, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
ENABLE_PCLK_PERIC0, 15,
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
14, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
13, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
12, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
7, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
6, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
5, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
4, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
3, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
0, CLK_SET_RATE_PARENT, 0),
/* ENABLE_PCLK_PERIC1 */
GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
9, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
8, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
/* ENABLE_SCLK_PERIC */
GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
19, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
18, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
17, 0, 0),
GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
16, 0, 0),
GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
"ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
ENABLE_SCLK_PERIC, 6,
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
5, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
4, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
3, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
ENABLE_SCLK_PERIC, 2,
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
ENABLE_SCLK_PERIC, 1,
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
ENABLE_SCLK_PERIC, 0,
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_cmu_info peric_cmu_info __initconst = {
.div_clks = peric_div_clks,
.nr_div_clks = ARRAY_SIZE(peric_div_clks),
.gate_clks = peric_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
.nr_clk_ids = CLKS_NR_PERIC,
.clk_regs = peric_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
.suspend_regs = peric_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(peric_suspend_regs),
};
static void __init exynos5433_cmu_peric_init(struct device_node *np)
{
samsung_cmu_register_one(np, &peric_cmu_info);
}
CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
exynos5433_cmu_peric_init);
/*
* Register offset definitions for CMU_PERIS
*/
#define ENABLE_ACLK_PERIS 0x0800
#define ENABLE_PCLK_PERIS 0x0900
#define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
#define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
#define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
#define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910
#define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914
#define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
#define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
#define ENABLE_SCLK_PERIS 0x0a00
#define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04
#define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08
#define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c
#define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
#define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
#define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
#define ENABLE_IP_PERIS0 0x0b00
#define ENABLE_IP_PERIS1 0x0b04
#define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08
#define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
#define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
#define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
#define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18
#define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
#define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
static const unsigned long peris_clk_regs[] __initconst = {
ENABLE_ACLK_PERIS,
ENABLE_PCLK_PERIS,
ENABLE_PCLK_PERIS_SECURE_TZPC,
ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
ENABLE_PCLK_PERIS_SECURE_TOPRTC,
ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
ENABLE_SCLK_PERIS,
ENABLE_SCLK_PERIS_SECURE_SECKEY,
ENABLE_SCLK_PERIS_SECURE_CHIPID,
ENABLE_SCLK_PERIS_SECURE_TOPRTC,
ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
ENABLE_SCLK_PERIS_SECURE_OTP_CON,
ENABLE_IP_PERIS0,
ENABLE_IP_PERIS1,
ENABLE_IP_PERIS_SECURE_TZPC,
ENABLE_IP_PERIS_SECURE_SECKEY,
ENABLE_IP_PERIS_SECURE_CHIPID,
ENABLE_IP_PERIS_SECURE_TOPRTC,
ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
ENABLE_IP_PERIS_SECURE_OTP_CON,
};
static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
/* ENABLE_ACLK_PERIS */
GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_PERIS */
GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_PERIS_SECURE_TZPC */
GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
/* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
"aclk_peris_66",
ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
/* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
"aclk_peris_66",
ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
/* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
"aclk_peris_66",
ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
/* ENABLE_SCLK_PERIS */
GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
ENABLE_SCLK_PERIS, 10, 0, 0),
GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
ENABLE_SCLK_PERIS, 4, 0, 0),
GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
ENABLE_SCLK_PERIS, 3, 0, 0),
/* ENABLE_SCLK_PERIS_SECURE_SECKEY */
GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_SCLK_PERIS_SECURE_CHIPID */
GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
/* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
/* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
/* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
};
static const struct samsung_cmu_info peris_cmu_info __initconst = {
.gate_clks = peris_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
.nr_clk_ids = CLKS_NR_PERIS,
.clk_regs = peris_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
};
static void __init exynos5433_cmu_peris_init(struct device_node *np)
{
samsung_cmu_register_one(np, &peris_cmu_info);
}
CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
exynos5433_cmu_peris_init);
/*
* Register offset definitions for CMU_FSYS
*/
#define MUX_SEL_FSYS0 0x0200
#define MUX_SEL_FSYS1 0x0204
#define MUX_SEL_FSYS2 0x0208
#define MUX_SEL_FSYS3 0x020c
#define MUX_SEL_FSYS4 0x0210
#define MUX_ENABLE_FSYS0 0x0300
#define MUX_ENABLE_FSYS1 0x0304
#define MUX_ENABLE_FSYS2 0x0308
#define MUX_ENABLE_FSYS3 0x030c
#define MUX_ENABLE_FSYS4 0x0310
#define MUX_STAT_FSYS0 0x0400
#define MUX_STAT_FSYS1 0x0404
#define MUX_STAT_FSYS2 0x0408
#define MUX_STAT_FSYS3 0x040c
#define MUX_STAT_FSYS4 0x0410
#define MUX_IGNORE_FSYS2 0x0508
#define MUX_IGNORE_FSYS3 0x050c
#define ENABLE_ACLK_FSYS0 0x0800
#define ENABLE_ACLK_FSYS1 0x0804
#define ENABLE_PCLK_FSYS 0x0900
#define ENABLE_SCLK_FSYS 0x0a00
#define ENABLE_IP_FSYS0 0x0b00
#define ENABLE_IP_FSYS1 0x0b04
/* list of all parent clock list */
PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", };
PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "aclk_fsys_200", };
PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",};
PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",};
PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", };
PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", };
PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", };
PNAME(mout_sclk_usbhost30_user_p) = { "oscclk", "sclk_usbhost30_fsys",};
PNAME(mout_sclk_usbdrd30_user_p) = { "oscclk", "sclk_usbdrd30_fsys", };
PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
= { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
= { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", };
PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
= { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", };
PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
= { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", };
PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
= { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", };
PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
= { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", };
PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
= { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", };
PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
= { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", };
PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
= { "oscclk", "phyclk_ufs_rx1_symbol_phy", };
PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
= { "oscclk", "phyclk_ufs_rx0_symbol_phy", };
PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
= { "oscclk", "phyclk_ufs_tx1_symbol_phy", };
PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
= { "oscclk", "phyclk_ufs_tx0_symbol_phy", };
PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
= { "oscclk", "phyclk_lli_mphy_to_ufs_phy", };
PNAME(mout_sclk_mphy_p)
= { "mout_sclk_ufs_mphy_user",
"mout_phyclk_lli_mphy_to_ufs_user", };
static const unsigned long fsys_clk_regs[] __initconst = {
MUX_SEL_FSYS0,
MUX_SEL_FSYS1,
MUX_SEL_FSYS2,
MUX_SEL_FSYS3,
MUX_SEL_FSYS4,
MUX_ENABLE_FSYS0,
MUX_ENABLE_FSYS1,
MUX_ENABLE_FSYS2,
MUX_ENABLE_FSYS3,
MUX_ENABLE_FSYS4,
MUX_IGNORE_FSYS2,
MUX_IGNORE_FSYS3,
ENABLE_ACLK_FSYS0,
ENABLE_ACLK_FSYS1,
ENABLE_PCLK_FSYS,
ENABLE_SCLK_FSYS,
ENABLE_IP_FSYS0,
ENABLE_IP_FSYS1,
};
static const struct samsung_clk_reg_dump fsys_suspend_regs[] = {
{ MUX_SEL_FSYS0, 0 },
{ MUX_SEL_FSYS1, 0 },
{ MUX_SEL_FSYS2, 0 },
{ MUX_SEL_FSYS3, 0 },
{ MUX_SEL_FSYS4, 0 },
};
static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = {
/* PHY clocks from USBDRD30_PHY */
FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
"phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
0, 60000000),
FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY,
"phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL,
0, 125000000),
/* PHY clocks from USBHOST30_PHY */
FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY,
"phyclk_usbhost30_uhost30_phyclock_phy", NULL,
0, 60000000),
FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY,
"phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL,
0, 125000000),
/* PHY clocks from USBHOST20_PHY */
FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY,
"phyclk_usbhost20_phy_freeclk_phy", NULL, 0, 60000000),
FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY,
"phyclk_usbhost20_phy_phyclock_phy", NULL, 0, 60000000),
FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY,
"phyclk_usbhost20_phy_clk48mohci_phy", NULL,
0, 48000000),
FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY,
"phyclk_usbhost20_phy_hsic1_phy", NULL, 0,
60000000),
/* PHY clocks from UFS_PHY */
FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy",
NULL, 0, 300000000),
FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy",
NULL, 0, 300000000),
FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy",
NULL, 0, 300000000),
FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy",
NULL, 0, 300000000),
/* PHY clocks from LLI_PHY */
FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy",
NULL, 0, 26000000),
};
static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
/* MUX_SEL_FSYS0 */
MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
/* MUX_SEL_FSYS1 */
MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
/* MUX_SEL_FSYS2 */
MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
"mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
MUX_SEL_FSYS2, 28, 1),
MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
"mout_phyclk_usbhost30_uhost30_phyclock_user",
mout_phyclk_usbhost30_uhost30_phyclock_user_p,
MUX_SEL_FSYS2, 24, 1),
MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
"mout_phyclk_usbhost20_phy_hsic1",
mout_phyclk_usbhost20_phy_hsic1_p,
MUX_SEL_FSYS2, 20, 1),
MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
"mout_phyclk_usbhost20_phy_clk48mohci_user",
mout_phyclk_usbhost20_phy_clk48mohci_user_p,
MUX_SEL_FSYS2, 16, 1),
MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
"mout_phyclk_usbhost20_phy_phyclock_user",
mout_phyclk_usbhost20_phy_phyclock_user_p,
MUX_SEL_FSYS2, 12, 1),
MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
"mout_phyclk_usbhost20_phy_freeclk_user",
mout_phyclk_usbhost20_phy_freeclk_user_p,
MUX_SEL_FSYS2, 8, 1),
MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
"mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
MUX_SEL_FSYS2, 4, 1),
MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
"mout_phyclk_usbdrd30_udrd30_phyclock_user",
mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
MUX_SEL_FSYS2, 0, 1),
/* MUX_SEL_FSYS3 */
MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
"mout_phyclk_ufs_rx1_symbol_user",
mout_phyclk_ufs_rx1_symbol_user_p,
MUX_SEL_FSYS3, 16, 1),
MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
"mout_phyclk_ufs_rx0_symbol_user",
mout_phyclk_ufs_rx0_symbol_user_p,
MUX_SEL_FSYS3, 12, 1),
MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
"mout_phyclk_ufs_tx1_symbol_user",
mout_phyclk_ufs_tx1_symbol_user_p,
MUX_SEL_FSYS3, 8, 1),
MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
"mout_phyclk_ufs_tx0_symbol_user",
mout_phyclk_ufs_tx0_symbol_user_p,
MUX_SEL_FSYS3, 4, 1),
MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
"mout_phyclk_lli_mphy_to_ufs_user",
mout_phyclk_lli_mphy_to_ufs_user_p,
MUX_SEL_FSYS3, 0, 1),
/* MUX_SEL_FSYS4 */
MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
MUX_SEL_FSYS4, 0, 1),
};
static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
/* ENABLE_ACLK_FSYS0 */
GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_ACLK_FSYS1 */
GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1",
"mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
26, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
"mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
22, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30",
"mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
13, 0, 0),
GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30",
"mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
12, 0, 0),
GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0",
"mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
11, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs",
"mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
10, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx",
"mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp",
"mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs",
"mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0",
"mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_FSYS */
GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
ENABLE_PCLK_FSYS, 5, 0, 0),
GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30",
"mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30",
"mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys",
"mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS,
0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_SCLK_FSYS */
GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user",
ENABLE_SCLK_FSYS, 21, 0, 0),
GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
"phyclk_usbhost30_uhost30_pipe_pclk",
"mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
ENABLE_SCLK_FSYS, 18, 0, 0),
GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
"phyclk_usbhost30_uhost30_phyclock",
"mout_phyclk_usbhost30_uhost30_phyclock_user",
ENABLE_SCLK_FSYS, 17, 0, 0),
GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol",
"mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS,
16, 0, 0),
GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
"mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS,
15, 0, 0),
GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol",
"mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS,
14, 0, 0),
GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
"mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS,
13, 0, 0),
GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1",
"mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS,
12, 0, 0),
GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
"phyclk_usbhost20_phy_clk48mohci",
"mout_phyclk_usbhost20_phy_clk48mohci_user",
ENABLE_SCLK_FSYS, 11, 0, 0),
GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
"phyclk_usbhost20_phy_phyclock",
"mout_phyclk_usbhost20_phy_phyclock_user",
ENABLE_SCLK_FSYS, 10, 0, 0),
GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
"phyclk_usbhost20_phy_freeclk",
"mout_phyclk_usbhost20_phy_freeclk_user",
ENABLE_SCLK_FSYS, 9, 0, 0),
GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
"phyclk_usbdrd30_udrd30_pipe_pclk",
"mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
ENABLE_SCLK_FSYS, 8, 0, 0),
GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
"phyclk_usbdrd30_udrd30_phyclock",
"mout_phyclk_usbdrd30_udrd30_phyclock_user",
ENABLE_SCLK_FSYS, 7, 0, 0),
GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy",
ENABLE_SCLK_FSYS, 6, 0, 0),
GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
ENABLE_SCLK_FSYS, 5, 0, 0),
GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user",
ENABLE_SCLK_FSYS, 1, 0, 0),
GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
ENABLE_SCLK_FSYS, 0, 0, 0),
/* ENABLE_IP_FSYS0 */
GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0),
GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
};
static const struct samsung_cmu_info fsys_cmu_info __initconst = {
.mux_clks = fsys_mux_clks,
.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
.gate_clks = fsys_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
.fixed_clks = fsys_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks),
.nr_clk_ids = CLKS_NR_FSYS,
.clk_regs = fsys_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
.suspend_regs = fsys_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(fsys_suspend_regs),
.clk_name = "aclk_fsys_200",
};
/*
* Register offset definitions for CMU_G2D
*/
#define MUX_SEL_G2D0 0x0200
#define MUX_SEL_ENABLE_G2D0 0x0300
#define MUX_SEL_STAT_G2D0 0x0400
#define DIV_G2D 0x0600
#define DIV_STAT_G2D 0x0700
#define DIV_ENABLE_ACLK_G2D 0x0800
#define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804
#define DIV_ENABLE_PCLK_G2D 0x0900
#define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904
#define DIV_ENABLE_IP_G2D0 0x0b00
#define DIV_ENABLE_IP_G2D1 0x0b04
#define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
static const unsigned long g2d_clk_regs[] __initconst = {
MUX_SEL_G2D0,
MUX_SEL_ENABLE_G2D0,
DIV_G2D,
DIV_ENABLE_ACLK_G2D,
DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
DIV_ENABLE_PCLK_G2D,
DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
DIV_ENABLE_IP_G2D0,
DIV_ENABLE_IP_G2D1,
DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
};
static const struct samsung_clk_reg_dump g2d_suspend_regs[] = {
{ MUX_SEL_G2D0, 0 },
};
/* list of all parent clock list */
PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", };
PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", };
static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {
/* MUX_SEL_G2D0 */
MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user",
mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
};
static const struct samsung_div_clock g2d_div_clks[] __initconst = {
/* DIV_G2D */
DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
DIV_G2D, 0, 2),
};
static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
/* DIV_ENABLE_ACLK_G2D */
GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
DIV_ENABLE_ACLK_G2D, 12, 0, 0),
GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
DIV_ENABLE_ACLK_G2D, 11, 0, 0),
GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
DIV_ENABLE_ACLK_G2D, 10, 0, 0),
GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
DIV_ENABLE_ACLK_G2D, 9, 0, 0),
GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
DIV_ENABLE_ACLK_G2D, 8, 0, 0),
GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx",
"mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D,
7, 0, 0),
GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d",
DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user",
DIV_ENABLE_ACLK_G2D, 1, 0, 0),
GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user",
DIV_ENABLE_ACLK_G2D, 0, 0, 0),
/* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
/* DIV_ENABLE_PCLK_G2D */
GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d",
DIV_ENABLE_PCLK_G2D, 7, 0, 0),
GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d",
DIV_ENABLE_PCLK_G2D, 6, 0, 0),
GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d",
DIV_ENABLE_PCLK_G2D, 5, 0, 0),
GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d",
DIV_ENABLE_PCLK_G2D, 4, 0, 0),
GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d",
DIV_ENABLE_PCLK_G2D, 3, 0, 0),
GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d",
DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d",
DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D,
0, 0, 0),
/* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d",
DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
};
static const struct samsung_cmu_info g2d_cmu_info __initconst = {
.mux_clks = g2d_mux_clks,
.nr_mux_clks = ARRAY_SIZE(g2d_mux_clks),
.div_clks = g2d_div_clks,
.nr_div_clks = ARRAY_SIZE(g2d_div_clks),
.gate_clks = g2d_gate_clks,
.nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
.nr_clk_ids = CLKS_NR_G2D,
.clk_regs = g2d_clk_regs,
.nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
.suspend_regs = g2d_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(g2d_suspend_regs),
.clk_name = "aclk_g2d_400",
};
/*
* Register offset definitions for CMU_DISP
*/
#define DISP_PLL_LOCK 0x0000
#define DISP_PLL_CON0 0x0100
#define DISP_PLL_CON1 0x0104
#define DISP_PLL_FREQ_DET 0x0108
#define MUX_SEL_DISP0 0x0200
#define MUX_SEL_DISP1 0x0204
#define MUX_SEL_DISP2 0x0208
#define MUX_SEL_DISP3 0x020c
#define MUX_SEL_DISP4 0x0210
#define MUX_ENABLE_DISP0 0x0300
#define MUX_ENABLE_DISP1 0x0304
#define MUX_ENABLE_DISP2 0x0308
#define MUX_ENABLE_DISP3 0x030c
#define MUX_ENABLE_DISP4 0x0310
#define MUX_STAT_DISP0 0x0400
#define MUX_STAT_DISP1 0x0404
#define MUX_STAT_DISP2 0x0408
#define MUX_STAT_DISP3 0x040c
#define MUX_STAT_DISP4 0x0410
#define MUX_IGNORE_DISP2 0x0508
#define DIV_DISP 0x0600
#define DIV_DISP_PLL_FREQ_DET 0x0604
#define DIV_STAT_DISP 0x0700
#define DIV_STAT_DISP_PLL_FREQ_DET 0x0704
#define ENABLE_ACLK_DISP0 0x0800
#define ENABLE_ACLK_DISP1 0x0804
#define ENABLE_PCLK_DISP 0x0900
#define ENABLE_SCLK_DISP 0x0a00
#define ENABLE_IP_DISP0 0x0b00
#define ENABLE_IP_DISP1 0x0b04
#define CLKOUT_CMU_DISP 0x0c00
#define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
static const unsigned long disp_clk_regs[] __initconst = {
DISP_PLL_LOCK,
DISP_PLL_CON0,
DISP_PLL_CON1,
DISP_PLL_FREQ_DET,
MUX_SEL_DISP0,
MUX_SEL_DISP1,
MUX_SEL_DISP2,
MUX_SEL_DISP3,
MUX_SEL_DISP4,
MUX_ENABLE_DISP0,
MUX_ENABLE_DISP1,
MUX_ENABLE_DISP2,
MUX_ENABLE_DISP3,
MUX_ENABLE_DISP4,
MUX_IGNORE_DISP2,
DIV_DISP,
DIV_DISP_PLL_FREQ_DET,
ENABLE_ACLK_DISP0,
ENABLE_ACLK_DISP1,
ENABLE_PCLK_DISP,
ENABLE_SCLK_DISP,
ENABLE_IP_DISP0,
ENABLE_IP_DISP1,
CLKOUT_CMU_DISP,
CLKOUT_CMU_DISP_DIV_STAT,
};
static const struct samsung_clk_reg_dump disp_suspend_regs[] = {
/* PLL has to be enabled for suspend */
{ DISP_PLL_CON0, 0x85f40502 },
/* ignore status of external PHY muxes during suspend to avoid hangs */
{ MUX_IGNORE_DISP2, 0x00111111 },
{ MUX_SEL_DISP0, 0 },
{ MUX_SEL_DISP1, 0 },
{ MUX_SEL_DISP2, 0 },
{ MUX_SEL_DISP3, 0 },
{ MUX_SEL_DISP4, 0 },
};
/* list of all parent clock list */
PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", };
PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", };
PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", };
PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", };
PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk",
"sclk_decon_tv_eclk_disp", };
PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk",
"sclk_decon_vclk_disp", };
PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk",
"sclk_decon_eclk_disp", };
PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk",
"sclk_decon_tv_vclk_disp", };
PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", };
PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk",
"phyclk_mipidphy1_bitclkdiv8_phy", };
PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk",
"phyclk_mipidphy1_rxclkesc0_phy", };
PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk",
"phyclk_mipidphy0_bitclkdiv8_phy", };
PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk",
"phyclk_mipidphy0_rxclkesc0_phy", };
PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk",
"phyclk_hdmiphy_tmds_clko_phy", };
PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk",
"phyclk_hdmiphy_pixel_clko_phy", };
PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll",
"mout_sclk_dsim0_user", };
PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll",
"mout_sclk_decon_tv_eclk_user", };
PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll",
"mout_sclk_decon_vclk_user", };
PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll",
"mout_sclk_decon_eclk_user", };
PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp",
"mout_sclk_dsim1_user", };
PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
"mout_phyclk_hdmiphy_pixel_clko_user",
"mout_sclk_decon_tv_vclk_b_disp", };
PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
"mout_sclk_decon_tv_vclk_user", };
static const struct samsung_pll_clock disp_pll_clks[] __initconst = {
PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
DISP_PLL_LOCK, DISP_PLL_CON0, exynos5433_pll_rates),
};
static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = {
/*
* sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
* The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
* and sclk_decon_{vclk|tv_vclk}.
*/
FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
1, 2, 0),
FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
1, 2, 0),
};
static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = {
/* PHY clocks from MIPI_DPHY1 */
FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
/* PHY clocks from MIPI_DPHY0 */
FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy",
NULL, 0, 188000000),
FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy",
NULL, 0, 100000000),
/* PHY clocks from HDMI_PHY */
FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
NULL, 0, 300000000),
FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy",
NULL, 0, 166000000),
};
static const struct samsung_mux_clock disp_mux_clks[] __initconst = {
/* MUX_SEL_DISP0 */
MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
0, 1),
/* MUX_SEL_DISP1 */
MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user",
mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user",
mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p,
MUX_SEL_DISP1, 20, 1),
MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user",
mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user",
mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user",
mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user",
mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
/* MUX_SEL_DISP2 */
MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
"mout_phyclk_mipidphy1_bitclkdiv8_user",
mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
20, 1),
MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
"mout_phyclk_mipidphy1_rxclkesc0_user",
mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
16, 1),
MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
"mout_phyclk_mipidphy0_bitclkdiv8_user",
mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
12, 1),
MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
"mout_phyclk_mipidphy0_rxclkesc0_user",
mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
8, 1),
MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
"mout_phyclk_hdmiphy_tmds_clko_user",
mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
4, 1),
MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
"mout_phyclk_hdmiphy_pixel_clko_user",
mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,
0, 1),
/* MUX_SEL_DISP3 */
MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p,
MUX_SEL_DISP3, 12, 1),
MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk",
mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1),
MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk",
mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1),
MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk",
mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
/* MUX_SEL_DISP4 */
MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp",
mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1),
MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp",
mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1),
MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
"mout_sclk_decon_tv_vclk_c_disp",
mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1),
MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
"mout_sclk_decon_tv_vclk_b_disp",
mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1),
MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
"mout_sclk_decon_tv_vclk_a_disp",
mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
};
static const struct samsung_div_clock disp_div_clks[] __initconst = {
/* DIV_DISP */
DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
"mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp",
"mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3),
DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
DIV_DISP, 16, 3),
DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp",
"mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3),
DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp",
"mout_sclk_decon_vclk", DIV_DISP, 8, 3),
DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp",
"mout_sclk_decon_eclk", DIV_DISP, 4, 3),
DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user",
DIV_DISP, 0, 2),
};
static const struct samsung_gate_clock disp_gate_clks[] __initconst = {
/* ENABLE_ACLK_DISP0 */
GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
ENABLE_ACLK_DISP0, 2, 0, 0),
GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user",
ENABLE_ACLK_DISP0, 0, 0, 0),
/* ENABLE_ACLK_DISP1 */
GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
ENABLE_ACLK_DISP1, 25, 0, 0),
GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
ENABLE_ACLK_DISP1, 24, 0, 0),
GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x",
"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x",
"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3",
"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2",
"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1",
"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0",
"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4",
"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3",
"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2",
"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1",
"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0",
"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p",
"div_pclk_disp", ENABLE_ACLK_DISP1,
12, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p",
"div_pclk_disp", ENABLE_ACLK_DISP1,
11, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p",
"div_pclk_disp", ENABLE_ACLK_DISP1,
10, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp",
ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
ENABLE_ACLK_DISP1, 7, 0, 0),
GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
ENABLE_ACLK_DISP1, 6, 0, 0),
GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x",
"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x",
"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp",
ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333",
"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333",
"mout_aclk_disp_333_user", ENABLE_ACLK_DISP1,
0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_DISP */
GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp",
ENABLE_PCLK_DISP, 23, 0, 0),
GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp",
ENABLE_PCLK_DISP, 22, 0, 0),
GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp",
ENABLE_PCLK_DISP, 21, 0, 0),
GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp",
ENABLE_PCLK_DISP, 20, 0, 0),
GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp",
ENABLE_PCLK_DISP, 19, 0, 0),
GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp",
ENABLE_PCLK_DISP, 18, 0, 0),
GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp",
ENABLE_PCLK_DISP, 17, 0, 0),
GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp",
ENABLE_PCLK_DISP, 16, 0, 0),
GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp",
ENABLE_PCLK_DISP, 15, 0, 0),
GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp",
ENABLE_PCLK_DISP, 14, 0, 0),
GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp",
ENABLE_PCLK_DISP, 13, 0, 0),
GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp",
ENABLE_PCLK_DISP, 12, 0, 0),
GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp",
ENABLE_PCLK_DISP, 11, 0, 0),
GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp",
ENABLE_PCLK_DISP, 10, 0, 0),
GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp",
ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp",
ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp",
ENABLE_PCLK_DISP, 7, 0, 0),
GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp",
ENABLE_PCLK_DISP, 6, 0, 0),
GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp",
ENABLE_PCLK_DISP, 5, 0, 0),
GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp",
ENABLE_PCLK_DISP, 3, 0, 0),
GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp",
ENABLE_PCLK_DISP, 2, 0, 0),
GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
ENABLE_PCLK_DISP, 1, 0, 0),
GATE(CLK_PCLK_DECON, "pclk_decon", "div_pclk_disp",
ENABLE_PCLK_DISP, 0, 0, 0),
/* ENABLE_SCLK_DISP */
GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
"mout_phyclk_mipidphy1_bitclkdiv8_user",
ENABLE_SCLK_DISP, 26, 0, 0),
GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0",
"mout_phyclk_mipidphy1_rxclkesc0_user",
ENABLE_SCLK_DISP, 25, 0, 0),
GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1",
"sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1",
"sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp",
ENABLE_SCLK_DISP, 22, 0, 0),
GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk",
"div_sclk_decon_tv_vclk_disp",
ENABLE_SCLK_DISP, 21, 0, 0),
GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8",
"mout_phyclk_mipidphy0_bitclkdiv8_user",
ENABLE_SCLK_DISP, 15, 0, 0),
GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",
"mout_phyclk_mipidphy0_rxclkesc0_user",
ENABLE_SCLK_DISP, 14, 0, 0),
GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko",
"mout_phyclk_hdmiphy_tmds_clko_user",
ENABLE_SCLK_DISP, 13, 0, 0),
GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel",
"sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies",
"sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0",
"sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0",
"sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user",
ENABLE_SCLK_DISP, 7, 0, 0),
GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
ENABLE_SCLK_DISP, 6, 0, 0),
GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp",
ENABLE_SCLK_DISP, 5, 0, 0),
GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk",
"div_sclk_decon_tv_eclk_disp",
ENABLE_SCLK_DISP, 4, 0, 0),
GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk",
"div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk",
"div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
};
static const struct samsung_cmu_info disp_cmu_info __initconst = {
.pll_clks = disp_pll_clks,
.nr_pll_clks = ARRAY_SIZE(disp_pll_clks),
.mux_clks = disp_mux_clks,
.nr_mux_clks = ARRAY_SIZE(disp_mux_clks),
.div_clks = disp_div_clks,
.nr_div_clks = ARRAY_SIZE(disp_div_clks),
.gate_clks = disp_gate_clks,
.nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
.fixed_clks = disp_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks),
.fixed_factor_clks = disp_fixed_factor_clks,
.nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks),
.nr_clk_ids = CLKS_NR_DISP,
.clk_regs = disp_clk_regs,
.nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
.suspend_regs = disp_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(disp_suspend_regs),
.clk_name = "aclk_disp_333",
};
/*
* Register offset definitions for CMU_AUD
*/
#define MUX_SEL_AUD0 0x0200
#define MUX_SEL_AUD1 0x0204
#define MUX_ENABLE_AUD0 0x0300
#define MUX_ENABLE_AUD1 0x0304
#define MUX_STAT_AUD0 0x0400
#define DIV_AUD0 0x0600
#define DIV_AUD1 0x0604
#define DIV_STAT_AUD0 0x0700
#define DIV_STAT_AUD1 0x0704
#define ENABLE_ACLK_AUD 0x0800
#define ENABLE_PCLK_AUD 0x0900
#define ENABLE_SCLK_AUD0 0x0a00
#define ENABLE_SCLK_AUD1 0x0a04
#define ENABLE_IP_AUD0 0x0b00
#define ENABLE_IP_AUD1 0x0b04
static const unsigned long aud_clk_regs[] __initconst = {
MUX_SEL_AUD0,
MUX_SEL_AUD1,
MUX_ENABLE_AUD0,
MUX_ENABLE_AUD1,
DIV_AUD0,
DIV_AUD1,
ENABLE_ACLK_AUD,
ENABLE_PCLK_AUD,
ENABLE_SCLK_AUD0,
ENABLE_SCLK_AUD1,
ENABLE_IP_AUD0,
ENABLE_IP_AUD1,
};
static const struct samsung_clk_reg_dump aud_suspend_regs[] = {
{ MUX_SEL_AUD0, 0 },
{ MUX_SEL_AUD1, 0 },
};
/* list of all parent clock list */
PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", };
PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000),
FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000),
FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000),
};
static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
/* MUX_SEL_AUD0 */
MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
/* MUX_SEL_AUD1 */
MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
MUX_SEL_AUD1, 8, 1),
MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p,
MUX_SEL_AUD1, 0, 1),
};
static const struct samsung_div_clock aud_div_clks[] __initconst = {
/* DIV_AUD0 */
DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
12, 4),
DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
8, 4),
DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
4, 4),
DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
0, 4),
/* DIV_AUD1 */
DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
"mout_aud_pll_user", DIV_AUD1, 16, 5),
DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
DIV_AUD1, 12, 4),
DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
DIV_AUD1, 4, 8),
DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s",
DIV_AUD1, 0, 4),
};
static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
/* ENABLE_ACLK_AUD */
GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
ENABLE_ACLK_AUD, 12, 0, 0),
GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
ENABLE_ACLK_AUD, 7, 0, 0),
GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
ENABLE_ACLK_AUD, 0, 4, 0),
GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
ENABLE_ACLK_AUD, 0, 3, 0),
GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
ENABLE_ACLK_AUD, 0, 2, 0),
GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
0, 1, 0),
GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD,
0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_AUD */
GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
13, 0, 0),
GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
12, 0, 0),
GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
11, 0, 0),
GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
ENABLE_PCLK_AUD, 10, 0, 0),
GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
ENABLE_PCLK_AUD, 6, 0, 0),
GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
ENABLE_PCLK_AUD, 5, 0, 0),
GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
ENABLE_PCLK_AUD, 4, 0, 0),
GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
ENABLE_PCLK_AUD, 3, 0, 0),
GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
2, 0, 0),
GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
ENABLE_PCLK_AUD, 0, 0, 0),
/* ENABLE_SCLK_AUD0 */
GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
ENABLE_SCLK_AUD0, 1, 0, 0),
GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
0, 0, 0),
/* ENABLE_SCLK_AUD1 */
GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
ENABLE_SCLK_AUD1, 6, 0, 0),
GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
ENABLE_SCLK_AUD1, 5, 0, 0),
GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
ENABLE_SCLK_AUD1, 4, 0, 0),
GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
ENABLE_SCLK_AUD1, 2, 0, 0),
GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_cmu_info aud_cmu_info __initconst = {
.mux_clks = aud_mux_clks,
.nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
.div_clks = aud_div_clks,
.nr_div_clks = ARRAY_SIZE(aud_div_clks),
.gate_clks = aud_gate_clks,
.nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
.fixed_clks = aud_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
.nr_clk_ids = CLKS_NR_AUD,
.clk_regs = aud_clk_regs,
.nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
.suspend_regs = aud_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(aud_suspend_regs),
.clk_name = "fout_aud_pll",
};
/*
* Register offset definitions for CMU_BUS{0|1|2}
*/
#define DIV_BUS 0x0600
#define DIV_STAT_BUS 0x0700
#define ENABLE_ACLK_BUS 0x0800
#define ENABLE_PCLK_BUS 0x0900
#define ENABLE_IP_BUS0 0x0b00
#define ENABLE_IP_BUS1 0x0b04
#define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */
#define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */
#define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */
/* list of all parent clock list */
PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", };
#define CMU_BUS_COMMON_CLK_REGS \
DIV_BUS, \
ENABLE_ACLK_BUS, \
ENABLE_PCLK_BUS, \
ENABLE_IP_BUS0, \
ENABLE_IP_BUS1
static const unsigned long bus01_clk_regs[] __initconst = {
CMU_BUS_COMMON_CLK_REGS,
};
static const unsigned long bus2_clk_regs[] __initconst = {
MUX_SEL_BUS2,
MUX_ENABLE_BUS2,
CMU_BUS_COMMON_CLK_REGS,
};
static const struct samsung_div_clock bus0_div_clks[] __initconst = {
/* DIV_BUS0 */
DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
DIV_BUS, 0, 3),
};
/* CMU_BUS0 clocks */
static const struct samsung_gate_clock bus0_gate_clks[] __initconst = {
/* ENABLE_ACLK_BUS0 */
GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133",
ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400",
ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_BUS0 */
GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
ENABLE_PCLK_BUS, 2, 0, 0),
GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133",
ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133",
ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
};
/* CMU_BUS1 clocks */
static const struct samsung_div_clock bus1_div_clks[] __initconst = {
/* DIV_BUS1 */
DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
DIV_BUS, 0, 3),
};
static const struct samsung_gate_clock bus1_gate_clks[] __initconst = {
/* ENABLE_ACLK_BUS1 */
GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133",
ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400",
ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_BUS1 */
GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
ENABLE_PCLK_BUS, 2, 0, 0),
GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133",
ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133",
ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
};
/* CMU_BUS2 clocks */
static const struct samsung_mux_clock bus2_mux_clks[] __initconst = {
/* MUX_SEL_BUS2 */
MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
};
static const struct samsung_div_clock bus2_div_clks[] __initconst = {
/* DIV_BUS2 */
DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
"mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
};
static const struct samsung_gate_clock bus2_gate_clks[] __initconst = {
/* ENABLE_ACLK_BUS2 */
GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133",
ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400",
"mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400",
"mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_BUS2 */
GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
ENABLE_PCLK_BUS, 2, 0, 0),
GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133",
ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133",
ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
};
#define CMU_BUS_INFO_CLKS(id) \
.div_clks = bus##id##_div_clks, \
.nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \
.gate_clks = bus##id##_gate_clks, \
.nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \
.nr_clk_ids = CLKS_NR_BUSX
static const struct samsung_cmu_info bus0_cmu_info __initconst = {
CMU_BUS_INFO_CLKS(0),
.clk_regs = bus01_clk_regs,
.nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
};
static const struct samsung_cmu_info bus1_cmu_info __initconst = {
CMU_BUS_INFO_CLKS(1),
.clk_regs = bus01_clk_regs,
.nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
};
static const struct samsung_cmu_info bus2_cmu_info __initconst = {
CMU_BUS_INFO_CLKS(2),
.mux_clks = bus2_mux_clks,
.nr_mux_clks = ARRAY_SIZE(bus2_mux_clks),
.clk_regs = bus2_clk_regs,
.nr_clk_regs = ARRAY_SIZE(bus2_clk_regs),
};
#define exynos5433_cmu_bus_init(id) \
static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\
{ \
samsung_cmu_register_one(np, &bus##id##_cmu_info); \
} \
CLK_OF_DECLARE(exynos5433_cmu_bus##id, \
"samsung,exynos5433-cmu-bus"#id, \
exynos5433_cmu_bus##id##_init)
exynos5433_cmu_bus_init(0);
exynos5433_cmu_bus_init(1);
exynos5433_cmu_bus_init(2);
/*
* Register offset definitions for CMU_G3D
*/
#define G3D_PLL_LOCK 0x0000
#define G3D_PLL_CON0 0x0100
#define G3D_PLL_CON1 0x0104
#define G3D_PLL_FREQ_DET 0x010c
#define MUX_SEL_G3D 0x0200
#define MUX_ENABLE_G3D 0x0300
#define MUX_STAT_G3D 0x0400
#define DIV_G3D 0x0600
#define DIV_G3D_PLL_FREQ_DET 0x0604
#define DIV_STAT_G3D 0x0700
#define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
#define ENABLE_ACLK_G3D 0x0800
#define ENABLE_PCLK_G3D 0x0900
#define ENABLE_SCLK_G3D 0x0a00
#define ENABLE_IP_G3D0 0x0b00
#define ENABLE_IP_G3D1 0x0b04
#define CLKOUT_CMU_G3D 0x0c00
#define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
#define CLK_STOPCTRL 0x1000
static const unsigned long g3d_clk_regs[] __initconst = {
G3D_PLL_LOCK,
G3D_PLL_CON0,
G3D_PLL_CON1,
G3D_PLL_FREQ_DET,
MUX_SEL_G3D,
MUX_ENABLE_G3D,
DIV_G3D,
DIV_G3D_PLL_FREQ_DET,
ENABLE_ACLK_G3D,
ENABLE_PCLK_G3D,
ENABLE_SCLK_G3D,
ENABLE_IP_G3D0,
ENABLE_IP_G3D1,
CLKOUT_CMU_G3D,
CLKOUT_CMU_G3D_DIV_STAT,
CLK_STOPCTRL,
};
static const struct samsung_clk_reg_dump g3d_suspend_regs[] = {
{ MUX_SEL_G3D, 0 },
};
/* list of all parent clock list */
PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", };
PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", };
static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
G3D_PLL_LOCK, G3D_PLL_CON0, exynos5433_pll_rates),
};
static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
/* MUX_SEL_G3D */
MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0),
MUX_F(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_div_clock g3d_div_clks[] __initconst = {
/* DIV_G3D */
DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
8, 2),
DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
4, 3),
DIV_F(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
0, 3, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
/* ENABLE_ACLK_G3D */
GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
ENABLE_ACLK_G3D, 7, 0, 0),
GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
ENABLE_ACLK_G3D, 6, 0, 0),
GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
/* ENABLE_PCLK_G3D */
GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
ENABLE_PCLK_G3D, 3, 0, 0),
GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
ENABLE_PCLK_G3D, 2, 0, 0),
GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_SCLK_G3D */
GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
ENABLE_SCLK_G3D, 0, 0, 0),
};
static const struct samsung_cmu_info g3d_cmu_info __initconst = {
.pll_clks = g3d_pll_clks,
.nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
.mux_clks = g3d_mux_clks,
.nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
.div_clks = g3d_div_clks,
.nr_div_clks = ARRAY_SIZE(g3d_div_clks),
.gate_clks = g3d_gate_clks,
.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
.nr_clk_ids = CLKS_NR_G3D,
.clk_regs = g3d_clk_regs,
.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
.suspend_regs = g3d_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(g3d_suspend_regs),
.clk_name = "aclk_g3d_400",
};
/*
* Register offset definitions for CMU_GSCL
*/
#define MUX_SEL_GSCL 0x0200
#define MUX_ENABLE_GSCL 0x0300
#define MUX_STAT_GSCL 0x0400
#define ENABLE_ACLK_GSCL 0x0800
#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
#define ENABLE_PCLK_GSCL 0x0900
#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
#define ENABLE_IP_GSCL0 0x0b00
#define ENABLE_IP_GSCL1 0x0b04
#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
static const unsigned long gscl_clk_regs[] __initconst = {
MUX_SEL_GSCL,
MUX_ENABLE_GSCL,
ENABLE_ACLK_GSCL,
ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
ENABLE_PCLK_GSCL,
ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
ENABLE_IP_GSCL0,
ENABLE_IP_GSCL1,
ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
};
static const struct samsung_clk_reg_dump gscl_suspend_regs[] = {
{ MUX_SEL_GSCL, 0 },
{ ENABLE_ACLK_GSCL, 0xfff },
{ ENABLE_PCLK_GSCL, 0xff },
};
/* list of all parent clock list */
PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", };
PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", };
static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {
/* MUX_SEL_GSCL */
MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
};
static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
/* ENABLE_ACLK_GSCL */
GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
ENABLE_ACLK_GSCL, 11, 0, 0),
GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
ENABLE_ACLK_GSCL, 10, 0, 0),
GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
ENABLE_ACLK_GSCL, 9, 0, 0),
GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp",
"mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL,
8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
ENABLE_ACLK_GSCL, 7, 0, 0),
GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
"mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
"mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4,
CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
ENABLE_ACLK_GSCL, 3, 0, 0),
GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
ENABLE_ACLK_GSCL, 2, 0, 0),
GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user",
ENABLE_ACLK_GSCL, 1, 0, 0),
GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user",
ENABLE_ACLK_GSCL, 0, 0, 0),
/* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
/* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
/* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
/* ENABLE_PCLK_GSCL */
GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
ENABLE_PCLK_GSCL, 7, 0, 0),
GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
ENABLE_PCLK_GSCL, 6, 0, 0),
GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
ENABLE_PCLK_GSCL, 5, 0, 0),
GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl",
"mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL,
3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user",
ENABLE_PCLK_GSCL, 2, 0, 0),
GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user",
ENABLE_PCLK_GSCL, 1, 0, 0),
GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user",
ENABLE_PCLK_GSCL, 0, 0, 0),
/* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
/* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
/* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
};
static const struct samsung_cmu_info gscl_cmu_info __initconst = {
.mux_clks = gscl_mux_clks,
.nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
.gate_clks = gscl_gate_clks,
.nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
.nr_clk_ids = CLKS_NR_GSCL,
.clk_regs = gscl_clk_regs,
.nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
.suspend_regs = gscl_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(gscl_suspend_regs),
.clk_name = "aclk_gscl_111",
};
/*
* Register offset definitions for CMU_APOLLO
*/
#define APOLLO_PLL_LOCK 0x0000
#define APOLLO_PLL_CON0 0x0100
#define APOLLO_PLL_CON1 0x0104
#define APOLLO_PLL_FREQ_DET 0x010c
#define MUX_SEL_APOLLO0 0x0200
#define MUX_SEL_APOLLO1 0x0204
#define MUX_SEL_APOLLO2 0x0208
#define MUX_ENABLE_APOLLO0 0x0300
#define MUX_ENABLE_APOLLO1 0x0304
#define MUX_ENABLE_APOLLO2 0x0308
#define MUX_STAT_APOLLO0 0x0400
#define MUX_STAT_APOLLO1 0x0404
#define MUX_STAT_APOLLO2 0x0408
#define DIV_APOLLO0 0x0600
#define DIV_APOLLO1 0x0604
#define DIV_APOLLO_PLL_FREQ_DET 0x0608
#define DIV_STAT_APOLLO0 0x0700
#define DIV_STAT_APOLLO1 0x0704
#define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708
#define ENABLE_ACLK_APOLLO 0x0800
#define ENABLE_PCLK_APOLLO 0x0900
#define ENABLE_SCLK_APOLLO 0x0a00
#define ENABLE_IP_APOLLO0 0x0b00
#define ENABLE_IP_APOLLO1 0x0b04
#define CLKOUT_CMU_APOLLO 0x0c00
#define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04
#define ARMCLK_STOPCTRL 0x1000
#define APOLLO_PWR_CTRL 0x1020
#define APOLLO_PWR_CTRL2 0x1024
#define APOLLO_INTR_SPREAD_ENABLE 0x1080
#define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084
#define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088
static const unsigned long apollo_clk_regs[] __initconst = {
APOLLO_PLL_LOCK,
APOLLO_PLL_CON0,
APOLLO_PLL_CON1,
APOLLO_PLL_FREQ_DET,
MUX_SEL_APOLLO0,
MUX_SEL_APOLLO1,
MUX_SEL_APOLLO2,
MUX_ENABLE_APOLLO0,
MUX_ENABLE_APOLLO1,
MUX_ENABLE_APOLLO2,
DIV_APOLLO0,
DIV_APOLLO1,
DIV_APOLLO_PLL_FREQ_DET,
ENABLE_ACLK_APOLLO,
ENABLE_PCLK_APOLLO,
ENABLE_SCLK_APOLLO,
ENABLE_IP_APOLLO0,
ENABLE_IP_APOLLO1,
CLKOUT_CMU_APOLLO,
CLKOUT_CMU_APOLLO_DIV_STAT,
ARMCLK_STOPCTRL,
APOLLO_PWR_CTRL,
APOLLO_PWR_CTRL2,
APOLLO_INTR_SPREAD_ENABLE,
APOLLO_INTR_SPREAD_USE_STANDBYWFI,
APOLLO_INTR_SPREAD_BLOCKING_DURATION,
};
/* list of all parent clock list */
PNAME(mout_apollo_pll_p) = { "oscclk", "fout_apollo_pll", };
PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", };
PNAME(mout_apollo_p) = { "mout_apollo_pll",
"mout_bus_pll_apollo_user", };
static const struct samsung_pll_clock apollo_pll_clks[] __initconst = {
PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5433_pll_rates),
};
static const struct samsung_mux_clock apollo_mux_clks[] __initconst = {
/* MUX_SEL_APOLLO0 */
MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT |
CLK_RECALC_NEW_RATES, 0),
/* MUX_SEL_APOLLO1 */
MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
/* MUX_SEL_APOLLO2 */
MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2,
0, 1, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_div_clock apollo_div_clks[] __initconst = {
/* DIV_APOLLO0 */
DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2",
DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE,
CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2",
DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE,
CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2",
DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE,
CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2",
DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE,
CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1",
DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo",
DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0),
/* DIV_APOLLO1 */
DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo",
DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE,
CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo",
DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
CLK_DIVIDER_READ_ONLY),
};
static const struct samsung_gate_clock apollo_gate_clks[] __initconst = {
/* ENABLE_ACLK_APOLLO */
GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
"div_atclk_apollo", ENABLE_ACLK_APOLLO,
6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys",
"div_atclk_apollo", ENABLE_ACLK_APOLLO,
5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys",
"div_atclk_apollo", ENABLE_ACLK_APOLLO,
4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys",
"div_atclk_apollo", ENABLE_ACLK_APOLLO,
3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci",
"div_aclk_apollo", ENABLE_ACLK_APOLLO,
2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop",
"div_pclk_apollo", ENABLE_ACLK_APOLLO,
1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200",
"div_pclk_apollo", ENABLE_ACLK_APOLLO,
0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_APOLLO */
GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo",
"div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO,
2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo",
ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo",
"div_pclk_apollo", ENABLE_PCLK_APOLLO,
0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_SCLK_APOLLO */
GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo",
ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
};
#define E5433_APOLLO_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
(((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
((pclk) << 12) | ((aclk) << 8))
#define E5433_APOLLO_DIV1(hpm, copy) \
(((hpm) << 4) | ((copy) << 0))
static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst = {
{ 1300000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
{ 1200000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
{ 1100000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
{ 1000000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
{ 900000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
{ 800000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
{ 700000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
{ 600000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
{ 500000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
{ 400000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
{ 0 },
};
static const struct samsung_cpu_clock apollo_cpu_clks[] __initconst = {
CPU_CLK(CLK_SCLK_APOLLO, "apolloclk", CLK_MOUT_APOLLO_PLL,
CLK_MOUT_BUS_PLL_APOLLO_USER,
CLK_CPU_HAS_E5433_REGS_LAYOUT, 0x200,
exynos5433_apolloclk_d),
};
static const struct samsung_cmu_info apollo_cmu_info __initconst = {
.pll_clks = apollo_pll_clks,
.nr_pll_clks = ARRAY_SIZE(apollo_pll_clks),
.mux_clks = apollo_mux_clks,
.nr_mux_clks = ARRAY_SIZE(apollo_mux_clks),
.div_clks = apollo_div_clks,
.nr_div_clks = ARRAY_SIZE(apollo_div_clks),
.gate_clks = apollo_gate_clks,
.nr_gate_clks = ARRAY_SIZE(apollo_gate_clks),
.cpu_clks = apollo_cpu_clks,
.nr_cpu_clks = ARRAY_SIZE(apollo_cpu_clks),
.nr_clk_ids = CLKS_NR_APOLLO,
.clk_regs = apollo_clk_regs,
.nr_clk_regs = ARRAY_SIZE(apollo_clk_regs),
};
static void __init exynos5433_cmu_apollo_init(struct device_node *np)
{
samsung_cmu_register_one(np, &apollo_cmu_info);
}
CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
exynos5433_cmu_apollo_init);
/*
* Register offset definitions for CMU_ATLAS
*/
#define ATLAS_PLL_LOCK 0x0000
#define ATLAS_PLL_CON0 0x0100
#define ATLAS_PLL_CON1 0x0104
#define ATLAS_PLL_FREQ_DET 0x010c
#define MUX_SEL_ATLAS0 0x0200
#define MUX_SEL_ATLAS1 0x0204
#define MUX_SEL_ATLAS2 0x0208
#define MUX_ENABLE_ATLAS0 0x0300
#define MUX_ENABLE_ATLAS1 0x0304
#define MUX_ENABLE_ATLAS2 0x0308
#define MUX_STAT_ATLAS0 0x0400
#define MUX_STAT_ATLAS1 0x0404
#define MUX_STAT_ATLAS2 0x0408
#define DIV_ATLAS0 0x0600
#define DIV_ATLAS1 0x0604
#define DIV_ATLAS_PLL_FREQ_DET 0x0608
#define DIV_STAT_ATLAS0 0x0700
#define DIV_STAT_ATLAS1 0x0704
#define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708
#define ENABLE_ACLK_ATLAS 0x0800
#define ENABLE_PCLK_ATLAS 0x0900
#define ENABLE_SCLK_ATLAS 0x0a00
#define ENABLE_IP_ATLAS0 0x0b00
#define ENABLE_IP_ATLAS1 0x0b04
#define CLKOUT_CMU_ATLAS 0x0c00
#define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04
#define ARMCLK_STOPCTRL 0x1000
#define ATLAS_PWR_CTRL 0x1020
#define ATLAS_PWR_CTRL2 0x1024
#define ATLAS_INTR_SPREAD_ENABLE 0x1080
#define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084
#define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088
static const unsigned long atlas_clk_regs[] __initconst = {
ATLAS_PLL_LOCK,
ATLAS_PLL_CON0,
ATLAS_PLL_CON1,
ATLAS_PLL_FREQ_DET,
MUX_SEL_ATLAS0,
MUX_SEL_ATLAS1,
MUX_SEL_ATLAS2,
MUX_ENABLE_ATLAS0,
MUX_ENABLE_ATLAS1,
MUX_ENABLE_ATLAS2,
DIV_ATLAS0,
DIV_ATLAS1,
DIV_ATLAS_PLL_FREQ_DET,
ENABLE_ACLK_ATLAS,
ENABLE_PCLK_ATLAS,
ENABLE_SCLK_ATLAS,
ENABLE_IP_ATLAS0,
ENABLE_IP_ATLAS1,
CLKOUT_CMU_ATLAS,
CLKOUT_CMU_ATLAS_DIV_STAT,
ARMCLK_STOPCTRL,
ATLAS_PWR_CTRL,
ATLAS_PWR_CTRL2,
ATLAS_INTR_SPREAD_ENABLE,
ATLAS_INTR_SPREAD_USE_STANDBYWFI,
ATLAS_INTR_SPREAD_BLOCKING_DURATION,
};
/* list of all parent clock list */
PNAME(mout_atlas_pll_p) = { "oscclk", "fout_atlas_pll", };
PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", };
PNAME(mout_atlas_p) = { "mout_atlas_pll",
"mout_bus_pll_atlas_user", };
static const struct samsung_pll_clock atlas_pll_clks[] __initconst = {
PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5433_pll_rates),
};
static const struct samsung_mux_clock atlas_mux_clks[] __initconst = {
/* MUX_SEL_ATLAS0 */
MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT |
CLK_RECALC_NEW_RATES, 0),
/* MUX_SEL_ATLAS1 */
MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
/* MUX_SEL_ATLAS2 */
MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2,
0, 1, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_div_clock atlas_div_clks[] __initconst = {
/* DIV_ATLAS0 */
DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas",
DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE,
CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2",
DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE,
CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2",
DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE,
CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2",
DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE,
CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1",
DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas",
DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0),
/* DIV_ATLAS1 */
DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas",
DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE,
CLK_DIVIDER_READ_ONLY),
DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas",
DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
CLK_DIVIDER_READ_ONLY),
};
static const struct samsung_gate_clock atlas_gate_clks[] __initconst = {
/* ENABLE_ACLK_ATLAS */
GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
"div_atclk_atlas", ENABLE_ACLK_ATLAS,
9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys",
"div_atclk_atlas", ENABLE_ACLK_ATLAS,
8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys",
"div_atclk_atlas", ENABLE_ACLK_ATLAS,
7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys",
"div_atclk_atlas", ENABLE_ACLK_ATLAS,
6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys",
"div_atclk_atlas", ENABLE_ACLK_ATLAS,
5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss",
"div_atclk_atlas", ENABLE_ACLK_ATLAS,
4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix",
"div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS,
3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci",
"div_aclk_atlas", ENABLE_ACLK_ATLAS,
2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas",
ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas",
ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_ATLAS */
GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys",
"div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys",
"div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys",
"div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas",
ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas",
ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas",
ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_SCLK_ATLAS */
GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas",
ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas",
ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas",
ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas",
ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas",
ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas",
ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas",
ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
};
#define E5433_ATLAS_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
(((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
((pclk) << 12) | ((aclk) << 8))
#define E5433_ATLAS_DIV1(hpm, copy) \
(((hpm) << 4) | ((copy) << 0))
static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = {
{ 1900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
{ 1800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
{ 1700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
{ 1600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
{ 1500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
{ 1400000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
{ 1300000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
{ 1200000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
{ 1100000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
{ 1000000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
{ 900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
{ 800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
{ 700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
{ 600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
{ 500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
{ 0 },
};
static const struct samsung_cpu_clock atlas_cpu_clks[] __initconst = {
CPU_CLK(CLK_SCLK_ATLAS, "atlasclk", CLK_MOUT_ATLAS_PLL,
CLK_MOUT_BUS_PLL_ATLAS_USER,
CLK_CPU_HAS_E5433_REGS_LAYOUT, 0x200,
exynos5433_atlasclk_d),
};
static const struct samsung_cmu_info atlas_cmu_info __initconst = {
.pll_clks = atlas_pll_clks,
.nr_pll_clks = ARRAY_SIZE(atlas_pll_clks),
.mux_clks = atlas_mux_clks,
.nr_mux_clks = ARRAY_SIZE(atlas_mux_clks),
.div_clks = atlas_div_clks,
.nr_div_clks = ARRAY_SIZE(atlas_div_clks),
.gate_clks = atlas_gate_clks,
.nr_gate_clks = ARRAY_SIZE(atlas_gate_clks),
.cpu_clks = atlas_cpu_clks,
.nr_cpu_clks = ARRAY_SIZE(atlas_cpu_clks),
.nr_clk_ids = CLKS_NR_ATLAS,
.clk_regs = atlas_clk_regs,
.nr_clk_regs = ARRAY_SIZE(atlas_clk_regs),
};
static void __init exynos5433_cmu_atlas_init(struct device_node *np)
{
samsung_cmu_register_one(np, &atlas_cmu_info);
}
CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
exynos5433_cmu_atlas_init);
/*
* Register offset definitions for CMU_MSCL
*/
#define MUX_SEL_MSCL0 0x0200
#define MUX_SEL_MSCL1 0x0204
#define MUX_ENABLE_MSCL0 0x0300
#define MUX_ENABLE_MSCL1 0x0304
#define MUX_STAT_MSCL0 0x0400
#define MUX_STAT_MSCL1 0x0404
#define DIV_MSCL 0x0600
#define DIV_STAT_MSCL 0x0700
#define ENABLE_ACLK_MSCL 0x0800
#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804
#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808
#define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c
#define ENABLE_PCLK_MSCL 0x0900
#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904
#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908
#define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c
#define ENABLE_SCLK_MSCL 0x0a00
#define ENABLE_IP_MSCL0 0x0b00
#define ENABLE_IP_MSCL1 0x0b04
#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08
#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c
#define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10
static const unsigned long mscl_clk_regs[] __initconst = {
MUX_SEL_MSCL0,
MUX_SEL_MSCL1,
MUX_ENABLE_MSCL0,
MUX_ENABLE_MSCL1,
DIV_MSCL,
ENABLE_ACLK_MSCL,
ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
ENABLE_PCLK_MSCL,
ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
ENABLE_SCLK_MSCL,
ENABLE_IP_MSCL0,
ENABLE_IP_MSCL1,
ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0,
ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1,
ENABLE_IP_MSCL_SECURE_SMMU_JPEG,
};
static const struct samsung_clk_reg_dump mscl_suspend_regs[] = {
{ MUX_SEL_MSCL0, 0 },
{ MUX_SEL_MSCL1, 0 },
};
/* list of all parent clock list */
PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", };
PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", };
PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user",
"mout_aclk_mscl_400_user", };
static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {
/* MUX_SEL_MSCL0 */
MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user",
mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
/* MUX_SEL_MSCL1 */
MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p,
MUX_SEL_MSCL1, 0, 1),
};
static const struct samsung_div_clock mscl_div_clks[] __initconst = {
/* DIV_MSCL */
DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
DIV_MSCL, 0, 3),
};
static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {
/* ENABLE_ACLK_MSCL */
GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
ENABLE_ACLK_MSCL, 9, 0, 0),
GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1",
"mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0",
"mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl",
ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user",
ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl",
ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user",
ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user",
ENABLE_ACLK_MSCL, 2, 0, 0),
GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user",
ENABLE_ACLK_MSCL, 1, 0, 0),
GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user",
ENABLE_ACLK_MSCL, 0, 0, 0),
/* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */
GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0",
"mout_aclk_mscl_400_user",
ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */
GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1",
"mout_aclk_mscl_400_user",
ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */
GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user",
ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_MSCL */
GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl",
ENABLE_PCLK_MSCL, 7, 0, 0),
GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl",
ENABLE_PCLK_MSCL, 6, 0, 0),
GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl",
ENABLE_PCLK_MSCL, 5, 0, 0),
GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl",
ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl",
ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl",
ENABLE_PCLK_MSCL, 2, 0, 0),
GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl",
ENABLE_PCLK_MSCL, 1, 0, 0),
GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl",
ENABLE_PCLK_MSCL, 0, 0, 0),
/* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */
GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl",
ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */
GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl",
ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */
GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl",
ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_SCLK_MSCL */
GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_cmu_info mscl_cmu_info __initconst = {
.mux_clks = mscl_mux_clks,
.nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
.div_clks = mscl_div_clks,
.nr_div_clks = ARRAY_SIZE(mscl_div_clks),
.gate_clks = mscl_gate_clks,
.nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
.nr_clk_ids = CLKS_NR_MSCL,
.clk_regs = mscl_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
.suspend_regs = mscl_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(mscl_suspend_regs),
.clk_name = "aclk_mscl_400",
};
/*
* Register offset definitions for CMU_MFC
*/
#define MUX_SEL_MFC 0x0200
#define MUX_ENABLE_MFC 0x0300
#define MUX_STAT_MFC 0x0400
#define DIV_MFC 0x0600
#define DIV_STAT_MFC 0x0700
#define ENABLE_ACLK_MFC 0x0800
#define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804
#define ENABLE_PCLK_MFC 0x0900
#define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904
#define ENABLE_IP_MFC0 0x0b00
#define ENABLE_IP_MFC1 0x0b04
#define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08
static const unsigned long mfc_clk_regs[] __initconst = {
MUX_SEL_MFC,
MUX_ENABLE_MFC,
DIV_MFC,
ENABLE_ACLK_MFC,
ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
ENABLE_PCLK_MFC,
ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
ENABLE_IP_MFC0,
ENABLE_IP_MFC1,
ENABLE_IP_MFC_SECURE_SMMU_MFC,
};
static const struct samsung_clk_reg_dump mfc_suspend_regs[] = {
{ MUX_SEL_MFC, 0 },
};
PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", };
static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
/* MUX_SEL_MFC */
MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
};
static const struct samsung_div_clock mfc_div_clks[] __initconst = {
/* DIV_MFC */
DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
DIV_MFC, 0, 2),
};
static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
/* ENABLE_ACLK_MFC */
GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
ENABLE_ACLK_MFC, 6, 0, 0),
GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user",
ENABLE_ACLK_MFC, 5, 0, 0),
GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc",
ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user",
ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc",
ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user",
ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user",
ENABLE_ACLK_MFC, 0, 0, 0),
/* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */
GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user",
ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user",
ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_MFC */
GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc",
ENABLE_PCLK_MFC, 4, 0, 0),
GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc",
ENABLE_PCLK_MFC, 3, 0, 0),
GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc",
ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc",
ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc",
ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */
GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc",
ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc",
ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
0, CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_cmu_info mfc_cmu_info __initconst = {
.mux_clks = mfc_mux_clks,
.nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
.div_clks = mfc_div_clks,
.nr_div_clks = ARRAY_SIZE(mfc_div_clks),
.gate_clks = mfc_gate_clks,
.nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
.nr_clk_ids = CLKS_NR_MFC,
.clk_regs = mfc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
.suspend_regs = mfc_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(mfc_suspend_regs),
.clk_name = "aclk_mfc_400",
};
/*
* Register offset definitions for CMU_HEVC
*/
#define MUX_SEL_HEVC 0x0200
#define MUX_ENABLE_HEVC 0x0300
#define MUX_STAT_HEVC 0x0400
#define DIV_HEVC 0x0600
#define DIV_STAT_HEVC 0x0700
#define ENABLE_ACLK_HEVC 0x0800
#define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804
#define ENABLE_PCLK_HEVC 0x0900
#define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904
#define ENABLE_IP_HEVC0 0x0b00
#define ENABLE_IP_HEVC1 0x0b04
#define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08
static const unsigned long hevc_clk_regs[] __initconst = {
MUX_SEL_HEVC,
MUX_ENABLE_HEVC,
DIV_HEVC,
ENABLE_ACLK_HEVC,
ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
ENABLE_PCLK_HEVC,
ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
ENABLE_IP_HEVC0,
ENABLE_IP_HEVC1,
ENABLE_IP_HEVC_SECURE_SMMU_HEVC,
};
static const struct samsung_clk_reg_dump hevc_suspend_regs[] = {
{ MUX_SEL_HEVC, 0 },
};
PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", };
static const struct samsung_mux_clock hevc_mux_clks[] __initconst = {
/* MUX_SEL_HEVC */
MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
};
static const struct samsung_div_clock hevc_div_clks[] __initconst = {
/* DIV_HEVC */
DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
DIV_HEVC, 0, 2),
};
static const struct samsung_gate_clock hevc_gate_clks[] __initconst = {
/* ENABLE_ACLK_HEVC */
GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
ENABLE_ACLK_HEVC, 6, 0, 0),
GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user",
ENABLE_ACLK_HEVC, 5, 0, 0),
GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc",
ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user",
ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc",
ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user",
ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user",
ENABLE_ACLK_HEVC, 0, 0, 0),
/* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */
GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1",
"mout_aclk_hevc_400_user",
ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0",
"mout_aclk_hevc_400_user",
ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_HEVC */
GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc",
ENABLE_PCLK_HEVC, 4, 0, 0),
GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc",
ENABLE_PCLK_HEVC, 3, 0, 0),
GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc",
ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc",
ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc",
ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */
GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc",
ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc",
ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
0, CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_cmu_info hevc_cmu_info __initconst = {
.mux_clks = hevc_mux_clks,
.nr_mux_clks = ARRAY_SIZE(hevc_mux_clks),
.div_clks = hevc_div_clks,
.nr_div_clks = ARRAY_SIZE(hevc_div_clks),
.gate_clks = hevc_gate_clks,
.nr_gate_clks = ARRAY_SIZE(hevc_gate_clks),
.nr_clk_ids = CLKS_NR_HEVC,
.clk_regs = hevc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(hevc_clk_regs),
.suspend_regs = hevc_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(hevc_suspend_regs),
.clk_name = "aclk_hevc_400",
};
/*
* Register offset definitions for CMU_ISP
*/
#define MUX_SEL_ISP 0x0200
#define MUX_ENABLE_ISP 0x0300
#define MUX_STAT_ISP 0x0400
#define DIV_ISP 0x0600
#define DIV_STAT_ISP 0x0700
#define ENABLE_ACLK_ISP0 0x0800
#define ENABLE_ACLK_ISP1 0x0804
#define ENABLE_ACLK_ISP2 0x0808
#define ENABLE_PCLK_ISP 0x0900
#define ENABLE_SCLK_ISP 0x0a00
#define ENABLE_IP_ISP0 0x0b00
#define ENABLE_IP_ISP1 0x0b04
#define ENABLE_IP_ISP2 0x0b08
#define ENABLE_IP_ISP3 0x0b0c
static const unsigned long isp_clk_regs[] __initconst = {
MUX_SEL_ISP,
MUX_ENABLE_ISP,
DIV_ISP,
ENABLE_ACLK_ISP0,
ENABLE_ACLK_ISP1,
ENABLE_ACLK_ISP2,
ENABLE_PCLK_ISP,
ENABLE_SCLK_ISP,
ENABLE_IP_ISP0,
ENABLE_IP_ISP1,
ENABLE_IP_ISP2,
ENABLE_IP_ISP3,
};
static const struct samsung_clk_reg_dump isp_suspend_regs[] = {
{ MUX_SEL_ISP, 0 },
};
PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", };
PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", };
static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
/* MUX_SEL_ISP */
MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user",
mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user",
mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
};
static const struct samsung_div_clock isp_div_clks[] __initconst = {
/* DIV_ISP */
DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis",
"mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3),
DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user",
DIV_ISP, 8, 3),
DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200",
"mout_aclk_isp_400_user", DIV_ISP, 4, 3),
DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200",
"mout_aclk_isp_400_user", DIV_ISP, 0, 3),
};
static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
/* ENABLE_ACLK_ISP0 */
GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user",
ENABLE_ACLK_ISP0, 5, 0, 0),
GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user",
ENABLE_ACLK_ISP0, 4, 0, 0),
GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user",
ENABLE_ACLK_ISP0, 3, 0, 0),
GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user",
ENABLE_ACLK_ISP0, 2, 0, 0),
GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user",
ENABLE_ACLK_ISP0, 1, 0, 0),
GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user",
ENABLE_ACLK_ISP0, 0, 0, 0),
/* ENABLE_ACLK_ISP1 */
GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp",
"mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
17, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc",
"mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
16, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc",
"mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p",
"div_pclk_isp", ENABLE_ACLK_ISP1,
14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p",
"div_pclk_isp", ENABLE_ACLK_ISP1,
13, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1",
"mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
12, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0",
"mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
11, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1",
"mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
10, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0",
"mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p",
"div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p",
"div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp",
ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp",
ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p",
"div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p",
"div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user",
ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user",
ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user",
ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
/* ENABLE_ACLK_ISP2 */
GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp",
"mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
13, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user",
ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user",
ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user",
ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc",
"mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user",
ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user",
ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp",
"mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user",
ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user",
ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user",
ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc",
"mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user",
ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user",
ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_ISP */
GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200",
ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200",
ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200",
ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200",
ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200",
ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200",
ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200",
ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp",
ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp",
ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp",
ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp",
ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp",
ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp",
ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp",
ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp",
ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp",
ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp",
ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp",
ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local",
"div_aclk_isp_c_200", ENABLE_PCLK_ISP,
7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200",
ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200",
ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis",
ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200",
ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200",
ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200",
ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200",
ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_SCLK_ISP */
GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis",
"mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis",
"mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp",
"mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd",
"mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc",
"mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc",
"mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
0, CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_cmu_info isp_cmu_info __initconst = {
.mux_clks = isp_mux_clks,
.nr_mux_clks = ARRAY_SIZE(isp_mux_clks),
.div_clks = isp_div_clks,
.nr_div_clks = ARRAY_SIZE(isp_div_clks),
.gate_clks = isp_gate_clks,
.nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
.nr_clk_ids = CLKS_NR_ISP,
.clk_regs = isp_clk_regs,
.nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
.suspend_regs = isp_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(isp_suspend_regs),
.clk_name = "aclk_isp_400",
};
/*
* Register offset definitions for CMU_CAM0
*/
#define MUX_SEL_CAM00 0x0200
#define MUX_SEL_CAM01 0x0204
#define MUX_SEL_CAM02 0x0208
#define MUX_SEL_CAM03 0x020c
#define MUX_SEL_CAM04 0x0210
#define MUX_ENABLE_CAM00 0x0300
#define MUX_ENABLE_CAM01 0x0304
#define MUX_ENABLE_CAM02 0x0308
#define MUX_ENABLE_CAM03 0x030c
#define MUX_ENABLE_CAM04 0x0310
#define MUX_STAT_CAM00 0x0400
#define MUX_STAT_CAM01 0x0404
#define MUX_STAT_CAM02 0x0408
#define MUX_STAT_CAM03 0x040c
#define MUX_STAT_CAM04 0x0410
#define MUX_IGNORE_CAM01 0x0504
#define DIV_CAM00 0x0600
#define DIV_CAM01 0x0604
#define DIV_CAM02 0x0608
#define DIV_CAM03 0x060c
#define DIV_STAT_CAM00 0x0700
#define DIV_STAT_CAM01 0x0704
#define DIV_STAT_CAM02 0x0708
#define DIV_STAT_CAM03 0x070c
#define ENABLE_ACLK_CAM00 0X0800
#define ENABLE_ACLK_CAM01 0X0804
#define ENABLE_ACLK_CAM02 0X0808
#define ENABLE_PCLK_CAM0 0X0900
#define ENABLE_SCLK_CAM0 0X0a00
#define ENABLE_IP_CAM00 0X0b00
#define ENABLE_IP_CAM01 0X0b04
#define ENABLE_IP_CAM02 0X0b08
#define ENABLE_IP_CAM03 0X0b0C
static const unsigned long cam0_clk_regs[] __initconst = {
MUX_SEL_CAM00,
MUX_SEL_CAM01,
MUX_SEL_CAM02,
MUX_SEL_CAM03,
MUX_SEL_CAM04,
MUX_ENABLE_CAM00,
MUX_ENABLE_CAM01,
MUX_ENABLE_CAM02,
MUX_ENABLE_CAM03,
MUX_ENABLE_CAM04,
MUX_IGNORE_CAM01,
DIV_CAM00,
DIV_CAM01,
DIV_CAM02,
DIV_CAM03,
ENABLE_ACLK_CAM00,
ENABLE_ACLK_CAM01,
ENABLE_ACLK_CAM02,
ENABLE_PCLK_CAM0,
ENABLE_SCLK_CAM0,
ENABLE_IP_CAM00,
ENABLE_IP_CAM01,
ENABLE_IP_CAM02,
ENABLE_IP_CAM03,
};
static const struct samsung_clk_reg_dump cam0_suspend_regs[] = {
{ MUX_SEL_CAM00, 0 },
{ MUX_SEL_CAM01, 0 },
{ MUX_SEL_CAM02, 0 },
{ MUX_SEL_CAM03, 0 },
{ MUX_SEL_CAM04, 0 },
};
PNAME(mout_aclk_cam0_333_user_p) = { "oscclk", "aclk_cam0_333", };
PNAME(mout_aclk_cam0_400_user_p) = { "oscclk", "aclk_cam0_400", };
PNAME(mout_aclk_cam0_552_user_p) = { "oscclk", "aclk_cam0_552", };
PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk",
"phyclk_rxbyteclkhs0_s4_phy", };
PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk",
"phyclk_rxbyteclkhs0_s2a_phy", };
PNAME(mout_aclk_lite_d_b_p) = { "mout_aclk_lite_d_a",
"mout_aclk_cam0_333_user", };
PNAME(mout_aclk_lite_d_a_p) = { "mout_aclk_cam0_552_user",
"mout_aclk_cam0_400_user", };
PNAME(mout_aclk_lite_b_b_p) = { "mout_aclk_lite_b_a",
"mout_aclk_cam0_333_user", };
PNAME(mout_aclk_lite_b_a_p) = { "mout_aclk_cam0_552_user",
"mout_aclk_cam0_400_user", };
PNAME(mout_aclk_lite_a_b_p) = { "mout_aclk_lite_a_a",
"mout_aclk_cam0_333_user", };
PNAME(mout_aclk_lite_a_a_p) = { "mout_aclk_cam0_552_user",
"mout_aclk_cam0_400_user", };
PNAME(mout_aclk_cam0_400_p) = { "mout_aclk_cam0_400_user",
"mout_aclk_cam0_333_user", };
PNAME(mout_aclk_csis1_b_p) = { "mout_aclk_csis1_a",
"mout_aclk_cam0_333_user" };
PNAME(mout_aclk_csis1_a_p) = { "mout_aclk_cam0_552_user",
"mout_aclk_cam0_400_user", };
PNAME(mout_aclk_csis0_b_p) = { "mout_aclk_csis0_a",
"mout_aclk_cam0_333_user", };
PNAME(mout_aclk_csis0_a_p) = { "mout_aclk_cam0_552_user",
"mout_aclk-cam0_400_user", };
PNAME(mout_aclk_3aa1_b_p) = { "mout_aclk_3aa1_a",
"mout_aclk_cam0_333_user", };
PNAME(mout_aclk_3aa1_a_p) = { "mout_aclk_cam0_552_user",
"mout_aclk_cam0_400_user", };
PNAME(mout_aclk_3aa0_b_p) = { "mout_aclk_3aa0_a",
"mout_aclk_cam0_333_user", };
PNAME(mout_aclk_3aa0_a_p) = { "mout_aclk_cam0_552_user",
"mout_aclk_cam0_400_user", };
PNAME(mout_sclk_lite_freecnt_c_p) = { "mout_sclk_lite_freecnt_b",
"div_pclk_lite_d", };
PNAME(mout_sclk_lite_freecnt_b_p) = { "mout_sclk_lite_freecnt_a",
"div_pclk_pixelasync_lite_c", };
PNAME(mout_sclk_lite_freecnt_a_p) = { "div_pclk_lite_a",
"div_pclk_lite_b", };
PNAME(mout_sclk_pixelasync_lite_c_b_p) = { "mout_sclk_pixelasync_lite_c_a",
"mout_aclk_cam0_333_user", };
PNAME(mout_sclk_pixelasync_lite_c_a_p) = { "mout_aclk_cam0_552_user",
"mout_aclk_cam0_400_user", };
PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = {
"mout_sclk_pixelasync_lite_c_init_a",
"mout_aclk_cam0_400_user", };
PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = {
"mout_aclk_cam0_552_user",
"mout_aclk_cam0_400_user", };
static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = {
FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy",
NULL, 0, 100000000),
FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy",
NULL, 0, 100000000),
};
static const struct samsung_mux_clock cam0_mux_clks[] __initconst = {
/* MUX_SEL_CAM00 */
MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user",
mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1),
MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user",
mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1),
MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user",
mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1),
/* MUX_SEL_CAM01 */
MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER,
"mout_phyclk_rxbyteclkhs0_s4_user",
mout_phyclk_rxbyteclkhs0_s4_user_p,
MUX_SEL_CAM01, 4, 1),
MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER,
"mout_phyclk_rxbyteclkhs0_s2a_user",
mout_phyclk_rxbyteclkhs0_s2a_user_p,
MUX_SEL_CAM01, 0, 1),
/* MUX_SEL_CAM02 */
MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p,
MUX_SEL_CAM02, 24, 1),
MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p,
MUX_SEL_CAM02, 20, 1),
MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p,
MUX_SEL_CAM02, 16, 1),
MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p,
MUX_SEL_CAM02, 12, 1),
MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p,
MUX_SEL_CAM02, 8, 1),
MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p,
MUX_SEL_CAM02, 4, 1),
MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p,
MUX_SEL_CAM02, 0, 1),
/* MUX_SEL_CAM03 */
MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p,
MUX_SEL_CAM03, 28, 1),
MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p,
MUX_SEL_CAM03, 24, 1),
MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p,
MUX_SEL_CAM03, 20, 1),
MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p,
MUX_SEL_CAM03, 16, 1),
MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p,
MUX_SEL_CAM03, 12, 1),
MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p,
MUX_SEL_CAM03, 8, 1),
MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p,
MUX_SEL_CAM03, 4, 1),
MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p,
MUX_SEL_CAM03, 0, 1),
/* MUX_SEL_CAM04 */
MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c",
mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1),
MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b",
mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 20, 1),
MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a",
mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 16, 1),
MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b",
mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 12, 1),
MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a",
mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 8, 1),
MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B,
"mout_sclk_pixelasync_lite_c_init_b",
mout_sclk_pixelasync_lite_c_init_b_p,
MUX_SEL_CAM04, 4, 1),
MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A,
"mout_sclk_pixelasync_lite_c_init_a",
mout_sclk_pixelasync_lite_c_init_a_p,
MUX_SEL_CAM04, 0, 1),
};
static const struct samsung_div_clock cam0_div_clks[] __initconst = {
/* DIV_CAM00 */
DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200",
DIV_CAM00, 8, 2),
DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400",
DIV_CAM00, 4, 3),
DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400",
"mout_aclk_cam0_400", DIV_CAM00, 0, 3),
/* DIV_CAM01 */
DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d",
DIV_CAM01, 20, 2),
DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b",
DIV_CAM01, 16, 3),
DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b",
DIV_CAM01, 12, 2),
DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b",
DIV_CAM01, 8, 3),
DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a",
DIV_CAM01, 4, 2),
DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b",
DIV_CAM01, 0, 3),
/* DIV_CAM02 */
DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b",
DIV_CAM02, 20, 3),
DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b",
DIV_CAM02, 16, 3),
DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1",
DIV_CAM02, 12, 2),
DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b",
DIV_CAM02, 8, 3),
DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0",
DIV_CAM02, 4, 2),
DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b",
DIV_CAM02, 0, 3),
/* DIV_CAM03 */
DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c",
"mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3),
DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c",
"div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2),
DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT,
"div_sclk_pixelasync_lite_c_init",
"mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3),
};
static const struct samsung_gate_clock cam0_gate_clks[] __initconst = {
/* ENABLE_ACLK_CAM00 */
GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00,
6, 0, 0),
GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00,
5, 0, 0),
GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00,
4, 0, 0),
GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00,
3, 0, 0),
GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d",
ENABLE_ACLK_CAM00, 2, 0, 0),
GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b",
ENABLE_ACLK_CAM00, 1, 0, 0),
GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a",
ENABLE_ACLK_CAM00, 0, 0, 0),
/* ENABLE_ACLK_CAM01 */
GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200",
ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400",
ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400",
ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400",
ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1",
ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1",
ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0",
ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0",
ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d",
"div_pclk_lite_d", ENABLE_ACLK_CAM01,
23, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d",
"div_aclk_cam0_200", ENABLE_ACLK_CAM01,
22, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b",
"div_pclk_lite_b", ENABLE_ACLK_CAM01,
21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b",
"div_aclk_cam0_200", ENABLE_ACLK_CAM01,
20, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a",
"div_pclk_lite_a", ENABLE_ACLK_CAM01,
19, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a",
"div_aclk_cam0_200", ENABLE_ACLK_CAM01,
18, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p",
"div_aclk_cam0_200", ENABLE_ACLK_CAM01,
17, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1",
"div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
16, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1",
"div_aclk_3aa1", ENABLE_ACLK_CAM01,
15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0",
"div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0",
"div_aclk_3aa0", ENABLE_ACLK_CAM01,
13, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d",
"div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
12, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d",
"div_aclk_lite_d", ENABLE_ACLK_CAM01,
11, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b",
"div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
10, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b",
"div_aclk_lite_b", ENABLE_ACLK_CAM01,
9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a",
"div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a",
"div_aclk_lite_a", ENABLE_ACLK_CAM01,
7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp",
"div_pclk_cam0_50", ENABLE_ACLK_CAM01,
6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200",
ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200",
ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200",
ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400",
ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200",
ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400",
ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_ACLK_CAM02 */
GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400",
ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400",
ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400",
ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400",
ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400",
ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400",
ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400",
ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400",
ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400",
ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400",
ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_CAM0 */
GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200",
ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200",
ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200",
ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200",
ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200",
ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50",
ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50",
ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50",
ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50",
ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50",
ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50",
ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50",
ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50",
ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d",
"div_pclk_cam0_50", ENABLE_PCLK_CAM0,
12, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b",
"div_pclk_cam0_50", ENABLE_PCLK_CAM0,
11, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a",
"div_pclk_cam0_50", ENABLE_PCLK_CAM0,
10, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50",
ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50",
ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local",
"div_aclk_cam0_200", ENABLE_PCLK_CAM0,
7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200",
ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200",
ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1",
ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0",
ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d",
ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b",
ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a",
ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_SCLK_CAM0 */
GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4",
"mout_phyclk_rxbyteclkhs0_s4_user",
ENABLE_SCLK_CAM0, 8, 0, 0),
GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a",
"mout_phyclk_rxbyteclkhs0_s2a_user",
ENABLE_SCLK_CAM0, 7, 0, 0),
GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt",
"mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0),
GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1",
"div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0),
GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0",
"div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0),
GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0",
"div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0),
GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c",
"div_sclk_pixelasync_lite_c",
ENABLE_SCLK_CAM0, 2, 0, 0),
GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init",
"div_sclk_pixelasync_lite_c_init",
ENABLE_SCLK_CAM0, 1, 0, 0),
GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init",
"div_sclk_pixelasync_lite_c",
ENABLE_SCLK_CAM0, 0, 0, 0),
};
static const struct samsung_cmu_info cam0_cmu_info __initconst = {
.mux_clks = cam0_mux_clks,
.nr_mux_clks = ARRAY_SIZE(cam0_mux_clks),
.div_clks = cam0_div_clks,
.nr_div_clks = ARRAY_SIZE(cam0_div_clks),
.gate_clks = cam0_gate_clks,
.nr_gate_clks = ARRAY_SIZE(cam0_gate_clks),
.fixed_clks = cam0_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(cam0_fixed_clks),
.nr_clk_ids = CLKS_NR_CAM0,
.clk_regs = cam0_clk_regs,
.nr_clk_regs = ARRAY_SIZE(cam0_clk_regs),
.suspend_regs = cam0_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(cam0_suspend_regs),
.clk_name = "aclk_cam0_400",
};
/*
* Register offset definitions for CMU_CAM1
*/
#define MUX_SEL_CAM10 0x0200
#define MUX_SEL_CAM11 0x0204
#define MUX_SEL_CAM12 0x0208
#define MUX_ENABLE_CAM10 0x0300
#define MUX_ENABLE_CAM11 0x0304
#define MUX_ENABLE_CAM12 0x0308
#define MUX_STAT_CAM10 0x0400
#define MUX_STAT_CAM11 0x0404
#define MUX_STAT_CAM12 0x0408
#define MUX_IGNORE_CAM11 0x0504
#define DIV_CAM10 0x0600
#define DIV_CAM11 0x0604
#define DIV_STAT_CAM10 0x0700
#define DIV_STAT_CAM11 0x0704
#define ENABLE_ACLK_CAM10 0X0800
#define ENABLE_ACLK_CAM11 0X0804
#define ENABLE_ACLK_CAM12 0X0808
#define ENABLE_PCLK_CAM1 0X0900
#define ENABLE_SCLK_CAM1 0X0a00
#define ENABLE_IP_CAM10 0X0b00
#define ENABLE_IP_CAM11 0X0b04
#define ENABLE_IP_CAM12 0X0b08
static const unsigned long cam1_clk_regs[] __initconst = {
MUX_SEL_CAM10,
MUX_SEL_CAM11,
MUX_SEL_CAM12,
MUX_ENABLE_CAM10,
MUX_ENABLE_CAM11,
MUX_ENABLE_CAM12,
MUX_IGNORE_CAM11,
DIV_CAM10,
DIV_CAM11,
ENABLE_ACLK_CAM10,
ENABLE_ACLK_CAM11,
ENABLE_ACLK_CAM12,
ENABLE_PCLK_CAM1,
ENABLE_SCLK_CAM1,
ENABLE_IP_CAM10,
ENABLE_IP_CAM11,
ENABLE_IP_CAM12,
};
static const struct samsung_clk_reg_dump cam1_suspend_regs[] = {
{ MUX_SEL_CAM10, 0 },
{ MUX_SEL_CAM11, 0 },
{ MUX_SEL_CAM12, 0 },
};
PNAME(mout_sclk_isp_uart_user_p) = { "oscclk", "sclk_isp_uart_cam1", };
PNAME(mout_sclk_isp_spi1_user_p) = { "oscclk", "sclk_isp_spi1_cam1", };
PNAME(mout_sclk_isp_spi0_user_p) = { "oscclk", "sclk_isp_spi0_cam1", };
PNAME(mout_aclk_cam1_333_user_p) = { "oscclk", "aclk_cam1_333", };
PNAME(mout_aclk_cam1_400_user_p) = { "oscclk", "aclk_cam1_400", };
PNAME(mout_aclk_cam1_552_user_p) = { "oscclk", "aclk_cam1_552", };
PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk",
"phyclk_rxbyteclkhs0_s2b_phy", };
PNAME(mout_aclk_csis2_b_p) = { "mout_aclk_csis2_a",
"mout_aclk_cam1_333_user", };
PNAME(mout_aclk_csis2_a_p) = { "mout_aclk_cam1_552_user",
"mout_aclk_cam1_400_user", };
PNAME(mout_aclk_fd_b_p) = { "mout_aclk_fd_a",
"mout_aclk_cam1_333_user", };
PNAME(mout_aclk_fd_a_p) = { "mout_aclk_cam1_552_user",
"mout_aclk_cam1_400_user", };
PNAME(mout_aclk_lite_c_b_p) = { "mout_aclk_lite_c_a",
"mout_aclk_cam1_333_user", };
PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user",
"mout_aclk_cam1_400_user", };
static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = {
FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL,
0, 100000000),
};
static const struct samsung_mux_clock cam1_mux_clks[] __initconst = {
/* MUX_SEL_CAM10 */
MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user",
mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1),
MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user",
mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1),
MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user",
mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1),
MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user",
mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1),
MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user",
mout_aclk_cam1_400_user_p, MUX_SEL_CAM10, 4, 1),
MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user",
mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1),
/* MUX_SEL_CAM11 */
MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER,
"mout_phyclk_rxbyteclkhs0_s2b_user",
mout_phyclk_rxbyteclkhs0_s2b_user_p,
MUX_SEL_CAM11, 0, 1),
/* MUX_SEL_CAM12 */
MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p,
MUX_SEL_CAM12, 20, 1),
MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p,
MUX_SEL_CAM12, 16, 1),
MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p,
MUX_SEL_CAM12, 12, 1),
MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p,
MUX_SEL_CAM12, 8, 1),
MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p,
MUX_SEL_CAM12, 4, 1),
MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p,
MUX_SEL_CAM12, 0, 1),
};
static const struct samsung_div_clock cam1_div_clks[] __initconst = {
/* DIV_CAM10 */
DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm",
"div_pclk_cam1_83", DIV_CAM10, 16, 2),
DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83",
"mout_aclk_cam1_333_user", DIV_CAM10, 12, 2),
DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166",
"mout_aclk_cam1_333_user", DIV_CAM10, 8, 2),
DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1",
"mout_aclk_cam1_552_user", DIV_CAM10, 4, 3),
DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user",
DIV_CAM10, 0, 3),
/* DIV_CAM11 */
DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b",
DIV_CAM11, 16, 3),
DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2),
DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3),
DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c",
DIV_CAM11, 4, 2),
DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b",
DIV_CAM11, 0, 3),
};
static const struct samsung_gate_clock cam1_gate_clks[] __initconst = {
/* ENABLE_ACLK_CAM10 */
GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user",
ENABLE_ACLK_CAM10, 4, 0, 0),
GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd",
ENABLE_ACLK_CAM10, 3, 0, 0),
GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c",
ENABLE_ACLK_CAM10, 1, 0, 0),
GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2",
ENABLE_ACLK_CAM10, 0, 0, 0),
/* ENABLE_ACLK_CAM11 */
GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd",
ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166",
ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c",
"div_pclk_lite_c", ENABLE_ACLK_CAM11,
27, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c",
"div_pclk_cam1_166", ENABLE_ACLK_CAM11,
26, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2",
"div_pclk_cam1_83", ENABLE_ACLK_CAM11,
25, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1",
"div_pclk_cam1_83", ENABLE_ACLK_CAM11,
24, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5",
"mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
23, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5",
"mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11,
22, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2",
"mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1",
"mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
20, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0",
"mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
19, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex",
"mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
18, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p",
"mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
17, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p",
"mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
16, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd",
"mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd",
ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c",
"mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
13, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c",
"div_aclk_lite_c", ENABLE_ACLK_CAM11,
12, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83",
ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83",
ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p",
"mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83",
ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166",
ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166",
ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user",
ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user",
ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user",
ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user",
ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user",
ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user",
ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_ACLK_CAM12 */
GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu",
"mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
10, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user",
ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c",
"mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user",
ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user",
ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user",
ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h",
"mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p",
"mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p",
"mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user",
ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c",
"mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_CAM1 */
GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166",
ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166",
ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166",
ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83",
ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83",
ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83",
ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166",
ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex",
"div_pclk_cam1_83", ENABLE_PCLK_CAM1,
20, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p",
"div_pclk_cam1_83", ENABLE_PCLK_CAM1,
19, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83",
ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c",
"div_pclk_cam1_83", ENABLE_PCLK_CAM1,
17, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83",
ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83",
ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local",
"div_pclk_cam1_166", ENABLE_PCLK_CAM1,
14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83",
ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83",
ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83",
ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83",
ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83",
ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83",
ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83",
ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83",
ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83",
ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83",
ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_mpwm", "div_pclk_cam1_83",
ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd",
ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c",
ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166",
ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_SCLK_CAM1 */
GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1,
15, 0, 0),
GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1,
14, 0, 0),
GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1,
13, 0, 0),
GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1,
12, 0, 0),
GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b",
"mout_phyclk_rxbyteclkhs0_s2b_user",
ENABLE_SCLK_CAM1, 11, 0, 0),
GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c",
ENABLE_SCLK_CAM1, 10, 0, 0),
GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd",
ENABLE_SCLK_CAM1, 9, 0, 0),
GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1",
ENABLE_SCLK_CAM1, 7, 0, 0),
GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user",
ENABLE_SCLK_CAM1, 6, 0, 0),
GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user",
ENABLE_SCLK_CAM1, 5, 0, 0),
GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user",
ENABLE_SCLK_CAM1, 4, 0, 0),
GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_mpwm", "div_sclk_isp_mpwm",
ENABLE_SCLK_CAM1, 3, 0, 0),
GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1",
ENABLE_SCLK_CAM1, 2, 0, 0),
GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1",
ENABLE_SCLK_CAM1, 1, 0, 0),
GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user",
ENABLE_SCLK_CAM1, 0, 0, 0),
};
static const struct samsung_cmu_info cam1_cmu_info __initconst = {
.mux_clks = cam1_mux_clks,
.nr_mux_clks = ARRAY_SIZE(cam1_mux_clks),
.div_clks = cam1_div_clks,
.nr_div_clks = ARRAY_SIZE(cam1_div_clks),
.gate_clks = cam1_gate_clks,
.nr_gate_clks = ARRAY_SIZE(cam1_gate_clks),
.fixed_clks = cam1_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(cam1_fixed_clks),
.nr_clk_ids = CLKS_NR_CAM1,
.clk_regs = cam1_clk_regs,
.nr_clk_regs = ARRAY_SIZE(cam1_clk_regs),
.suspend_regs = cam1_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(cam1_suspend_regs),
.clk_name = "aclk_cam1_400",
};
/*
* Register offset definitions for CMU_IMEM
*/
#define ENABLE_ACLK_IMEM_SLIMSSS 0x080c
#define ENABLE_PCLK_IMEM_SLIMSSS 0x0908
static const unsigned long imem_clk_regs[] __initconst = {
ENABLE_ACLK_IMEM_SLIMSSS,
ENABLE_PCLK_IMEM_SLIMSSS,
};
static const struct samsung_gate_clock imem_gate_clks[] __initconst = {
/* ENABLE_ACLK_IMEM_SLIMSSS */
GATE(CLK_ACLK_SLIMSSS, "aclk_slimsss", "aclk_imem_sssx_266",
ENABLE_ACLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
/* ENABLE_PCLK_IMEM_SLIMSSS */
GATE(CLK_PCLK_SLIMSSS, "pclk_slimsss", "aclk_imem_200",
ENABLE_PCLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_cmu_info imem_cmu_info __initconst = {
.gate_clks = imem_gate_clks,
.nr_gate_clks = ARRAY_SIZE(imem_gate_clks),
.nr_clk_ids = CLKS_NR_IMEM,
.clk_regs = imem_clk_regs,
.nr_clk_regs = ARRAY_SIZE(imem_clk_regs),
.clk_name = "aclk_imem_200",
};
static int __init exynos5433_cmu_probe(struct platform_device *pdev)
{
return exynos_arm64_register_cmu_pm(pdev, false);
}
static const struct of_device_id exynos5433_cmu_of_match[] = {
{
.compatible = "samsung,exynos5433-cmu-aud",
.data = &aud_cmu_info,
}, {
.compatible = "samsung,exynos5433-cmu-cam0",
.data = &cam0_cmu_info,
}, {
.compatible = "samsung,exynos5433-cmu-cam1",
.data = &cam1_cmu_info,
}, {
.compatible = "samsung,exynos5433-cmu-disp",
.data = &disp_cmu_info,
}, {
.compatible = "samsung,exynos5433-cmu-g2d",
.data = &g2d_cmu_info,
}, {
.compatible = "samsung,exynos5433-cmu-g3d",
.data = &g3d_cmu_info,
}, {
.compatible = "samsung,exynos5433-cmu-fsys",
.data = &fsys_cmu_info,
}, {
.compatible = "samsung,exynos5433-cmu-gscl",
.data = &gscl_cmu_info,
}, {
.compatible = "samsung,exynos5433-cmu-mfc",
.data = &mfc_cmu_info,
}, {
.compatible = "samsung,exynos5433-cmu-hevc",
.data = &hevc_cmu_info,
}, {
.compatible = "samsung,exynos5433-cmu-isp",
.data = &isp_cmu_info,
}, {
.compatible = "samsung,exynos5433-cmu-mscl",
.data = &mscl_cmu_info,
}, {
.compatible = "samsung,exynos5433-cmu-imem",
.data = &imem_cmu_info,
}, {
},
};
static const struct dev_pm_ops exynos5433_cmu_pm_ops = {
SET_RUNTIME_PM_OPS(exynos_arm64_cmu_suspend, exynos_arm64_cmu_resume,
NULL)
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver exynos5433_cmu_driver __refdata = {
.driver = {
.name = "exynos5433-cmu",
.of_match_table = exynos5433_cmu_of_match,
.suppress_bind_attrs = true,
.pm = &exynos5433_cmu_pm_ops,
},
.probe = exynos5433_cmu_probe,
};
static int __init exynos5433_cmu_init(void)
{
return platform_driver_register(&exynos5433_cmu_driver);
}
core_initcall(exynos5433_cmu_init);
| linux-master | drivers/clk/samsung/clk-exynos5433.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Copyright (c) 2013 Linaro Ltd.
* Author: Thomas Abraham <[email protected]>
*
* This file includes utility functions to register clocks to common
* clock framework for Samsung platforms.
*/
#include <linux/slab.h>
#include <linux/clkdev.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/syscore_ops.h>
#include "clk.h"
static LIST_HEAD(clock_reg_cache_list);
void samsung_clk_save(void __iomem *base,
struct samsung_clk_reg_dump *rd,
unsigned int num_regs)
{
for (; num_regs > 0; --num_regs, ++rd)
rd->value = readl(base + rd->offset);
}
void samsung_clk_restore(void __iomem *base,
const struct samsung_clk_reg_dump *rd,
unsigned int num_regs)
{
for (; num_regs > 0; --num_regs, ++rd)
writel(rd->value, base + rd->offset);
}
struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
const unsigned long *rdump,
unsigned long nr_rdump)
{
struct samsung_clk_reg_dump *rd;
unsigned int i;
rd = kcalloc(nr_rdump, sizeof(*rd), GFP_KERNEL);
if (!rd)
return NULL;
for (i = 0; i < nr_rdump; ++i)
rd[i].offset = rdump[i];
return rd;
}
/**
* samsung_clk_init() - Create and initialize a clock provider object
* @dev: CMU device to enable runtime PM, or NULL if RPM is not needed
* @base: Start address (mapped) of CMU registers
* @nr_clks: Total clock count to allocate in clock provider object
*
* Setup the essentials required to support clock lookup using Common Clock
* Framework.
*
* Return: Allocated and initialized clock provider object.
*/
struct samsung_clk_provider * __init samsung_clk_init(struct device *dev,
void __iomem *base, unsigned long nr_clks)
{
struct samsung_clk_provider *ctx;
int i;
ctx = kzalloc(struct_size(ctx, clk_data.hws, nr_clks), GFP_KERNEL);
if (!ctx)
panic("could not allocate clock provider context.\n");
for (i = 0; i < nr_clks; ++i)
ctx->clk_data.hws[i] = ERR_PTR(-ENOENT);
ctx->dev = dev;
ctx->reg_base = base;
ctx->clk_data.num = nr_clks;
spin_lock_init(&ctx->lock);
return ctx;
}
void __init samsung_clk_of_add_provider(struct device_node *np,
struct samsung_clk_provider *ctx)
{
if (np) {
if (of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
&ctx->clk_data))
panic("could not register clk provider\n");
}
}
/* add a clock instance to the clock lookup table used for dt based lookup */
void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
struct clk_hw *clk_hw, unsigned int id)
{
if (id)
ctx->clk_data.hws[id] = clk_hw;
}
/* register a list of aliases */
void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx,
const struct samsung_clock_alias *list,
unsigned int nr_clk)
{
struct clk_hw *clk_hw;
unsigned int idx, ret;
for (idx = 0; idx < nr_clk; idx++, list++) {
if (!list->id) {
pr_err("%s: clock id missing for index %d\n", __func__,
idx);
continue;
}
clk_hw = ctx->clk_data.hws[list->id];
if (!clk_hw) {
pr_err("%s: failed to find clock %d\n", __func__,
list->id);
continue;
}
ret = clk_hw_register_clkdev(clk_hw, list->alias,
list->dev_name);
if (ret)
pr_err("%s: failed to register lookup %s\n",
__func__, list->alias);
}
}
/* register a list of fixed clocks */
void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx,
const struct samsung_fixed_rate_clock *list,
unsigned int nr_clk)
{
struct clk_hw *clk_hw;
unsigned int idx, ret;
for (idx = 0; idx < nr_clk; idx++, list++) {
clk_hw = clk_hw_register_fixed_rate(ctx->dev, list->name,
list->parent_name, list->flags, list->fixed_rate);
if (IS_ERR(clk_hw)) {
pr_err("%s: failed to register clock %s\n", __func__,
list->name);
continue;
}
samsung_clk_add_lookup(ctx, clk_hw, list->id);
/*
* Unconditionally add a clock lookup for the fixed rate clocks.
* There are not many of these on any of Samsung platforms.
*/
ret = clk_hw_register_clkdev(clk_hw, list->name, NULL);
if (ret)
pr_err("%s: failed to register clock lookup for %s",
__func__, list->name);
}
}
/* register a list of fixed factor clocks */
void __init samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx,
const struct samsung_fixed_factor_clock *list, unsigned int nr_clk)
{
struct clk_hw *clk_hw;
unsigned int idx;
for (idx = 0; idx < nr_clk; idx++, list++) {
clk_hw = clk_hw_register_fixed_factor(ctx->dev, list->name,
list->parent_name, list->flags, list->mult, list->div);
if (IS_ERR(clk_hw)) {
pr_err("%s: failed to register clock %s\n", __func__,
list->name);
continue;
}
samsung_clk_add_lookup(ctx, clk_hw, list->id);
}
}
/* register a list of mux clocks */
void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
const struct samsung_mux_clock *list,
unsigned int nr_clk)
{
struct clk_hw *clk_hw;
unsigned int idx;
for (idx = 0; idx < nr_clk; idx++, list++) {
clk_hw = clk_hw_register_mux(ctx->dev, list->name,
list->parent_names, list->num_parents, list->flags,
ctx->reg_base + list->offset,
list->shift, list->width, list->mux_flags, &ctx->lock);
if (IS_ERR(clk_hw)) {
pr_err("%s: failed to register clock %s\n", __func__,
list->name);
continue;
}
samsung_clk_add_lookup(ctx, clk_hw, list->id);
}
}
/* register a list of div clocks */
void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
const struct samsung_div_clock *list,
unsigned int nr_clk)
{
struct clk_hw *clk_hw;
unsigned int idx;
for (idx = 0; idx < nr_clk; idx++, list++) {
if (list->table)
clk_hw = clk_hw_register_divider_table(ctx->dev,
list->name, list->parent_name, list->flags,
ctx->reg_base + list->offset,
list->shift, list->width, list->div_flags,
list->table, &ctx->lock);
else
clk_hw = clk_hw_register_divider(ctx->dev, list->name,
list->parent_name, list->flags,
ctx->reg_base + list->offset, list->shift,
list->width, list->div_flags, &ctx->lock);
if (IS_ERR(clk_hw)) {
pr_err("%s: failed to register clock %s\n", __func__,
list->name);
continue;
}
samsung_clk_add_lookup(ctx, clk_hw, list->id);
}
}
/* register a list of gate clocks */
void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
const struct samsung_gate_clock *list,
unsigned int nr_clk)
{
struct clk_hw *clk_hw;
unsigned int idx;
for (idx = 0; idx < nr_clk; idx++, list++) {
clk_hw = clk_hw_register_gate(ctx->dev, list->name, list->parent_name,
list->flags, ctx->reg_base + list->offset,
list->bit_idx, list->gate_flags, &ctx->lock);
if (IS_ERR(clk_hw)) {
pr_err("%s: failed to register clock %s\n", __func__,
list->name);
continue;
}
samsung_clk_add_lookup(ctx, clk_hw, list->id);
}
}
/*
* obtain the clock speed of all external fixed clock sources from device
* tree and register it
*/
void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
struct samsung_fixed_rate_clock *fixed_rate_clk,
unsigned int nr_fixed_rate_clk,
const struct of_device_id *clk_matches)
{
const struct of_device_id *match;
struct device_node *clk_np;
u32 freq;
for_each_matching_node_and_match(clk_np, clk_matches, &match) {
if (of_property_read_u32(clk_np, "clock-frequency", &freq))
continue;
fixed_rate_clk[(unsigned long)match->data].fixed_rate = freq;
}
samsung_clk_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk);
}
#ifdef CONFIG_PM_SLEEP
static int samsung_clk_suspend(void)
{
struct samsung_clock_reg_cache *reg_cache;
list_for_each_entry(reg_cache, &clock_reg_cache_list, node) {
samsung_clk_save(reg_cache->reg_base, reg_cache->rdump,
reg_cache->rd_num);
samsung_clk_restore(reg_cache->reg_base, reg_cache->rsuspend,
reg_cache->rsuspend_num);
}
return 0;
}
static void samsung_clk_resume(void)
{
struct samsung_clock_reg_cache *reg_cache;
list_for_each_entry(reg_cache, &clock_reg_cache_list, node)
samsung_clk_restore(reg_cache->reg_base, reg_cache->rdump,
reg_cache->rd_num);
}
static struct syscore_ops samsung_clk_syscore_ops = {
.suspend = samsung_clk_suspend,
.resume = samsung_clk_resume,
};
void samsung_clk_extended_sleep_init(void __iomem *reg_base,
const unsigned long *rdump,
unsigned long nr_rdump,
const struct samsung_clk_reg_dump *rsuspend,
unsigned long nr_rsuspend)
{
struct samsung_clock_reg_cache *reg_cache;
reg_cache = kzalloc(sizeof(struct samsung_clock_reg_cache),
GFP_KERNEL);
if (!reg_cache)
panic("could not allocate register reg_cache.\n");
reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
if (!reg_cache->rdump)
panic("could not allocate register dump storage.\n");
if (list_empty(&clock_reg_cache_list))
register_syscore_ops(&samsung_clk_syscore_ops);
reg_cache->reg_base = reg_base;
reg_cache->rd_num = nr_rdump;
reg_cache->rsuspend = rsuspend;
reg_cache->rsuspend_num = nr_rsuspend;
list_add_tail(®_cache->node, &clock_reg_cache_list);
}
#endif
/**
* samsung_cmu_register_clocks() - Register all clocks provided in CMU object
* @ctx: Clock provider object
* @cmu: CMU object with clocks to register
*/
void __init samsung_cmu_register_clocks(struct samsung_clk_provider *ctx,
const struct samsung_cmu_info *cmu)
{
if (cmu->pll_clks)
samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks);
if (cmu->mux_clks)
samsung_clk_register_mux(ctx, cmu->mux_clks, cmu->nr_mux_clks);
if (cmu->div_clks)
samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks);
if (cmu->gate_clks)
samsung_clk_register_gate(ctx, cmu->gate_clks,
cmu->nr_gate_clks);
if (cmu->fixed_clks)
samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks,
cmu->nr_fixed_clks);
if (cmu->fixed_factor_clks)
samsung_clk_register_fixed_factor(ctx, cmu->fixed_factor_clks,
cmu->nr_fixed_factor_clks);
if (cmu->cpu_clks)
samsung_clk_register_cpu(ctx, cmu->cpu_clks, cmu->nr_cpu_clks);
}
/*
* Common function which registers plls, muxes, dividers and gates
* for each CMU. It also add CMU register list to register cache.
*/
struct samsung_clk_provider * __init samsung_cmu_register_one(
struct device_node *np,
const struct samsung_cmu_info *cmu)
{
void __iomem *reg_base;
struct samsung_clk_provider *ctx;
reg_base = of_iomap(np, 0);
if (!reg_base) {
panic("%s: failed to map registers\n", __func__);
return NULL;
}
ctx = samsung_clk_init(NULL, reg_base, cmu->nr_clk_ids);
samsung_cmu_register_clocks(ctx, cmu);
if (cmu->clk_regs)
samsung_clk_extended_sleep_init(reg_base,
cmu->clk_regs, cmu->nr_clk_regs,
cmu->suspend_regs, cmu->nr_suspend_regs);
samsung_clk_of_add_provider(np, ctx);
return ctx;
}
| linux-master | drivers/clk/samsung/clk.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 Samsung Electronics Co., Ltd.
* Author: Chanho Park <[email protected]>
*
* Common Clock Framework support for ExynosAuto V9 SoC.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/samsung,exynosautov9.h>
#include "clk.h"
#include "clk-exynos-arm64.h"
/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR_TOP (GOUT_CLKCMU_PERIS_BUS + 1)
#define CLKS_NR_BUSMC (CLK_GOUT_BUSMC_SPDMA_PCLK + 1)
#define CLKS_NR_CORE (CLK_GOUT_CORE_CMU_CORE_PCLK + 1)
#define CLKS_NR_FSYS0 (CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK + 1)
#define CLKS_NR_FSYS1 (CLK_GOUT_FSYS1_USB30_1_ACLK + 1)
#define CLKS_NR_FSYS2 (CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO + 1)
#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_PCLK_11 + 1)
#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_PCLK_11 + 1)
#define CLKS_NR_PERIS (CLK_GOUT_WDT_CLUSTER1 + 1)
/* ---- CMU_TOP ------------------------------------------------------------ */
/* Register Offset definitions for CMU_TOP (0x1b240000) */
#define PLL_LOCKTIME_PLL_SHARED0 0x0000
#define PLL_LOCKTIME_PLL_SHARED1 0x0004
#define PLL_LOCKTIME_PLL_SHARED2 0x0008
#define PLL_LOCKTIME_PLL_SHARED3 0x000c
#define PLL_LOCKTIME_PLL_SHARED4 0x0010
#define PLL_CON0_PLL_SHARED0 0x0100
#define PLL_CON3_PLL_SHARED0 0x010c
#define PLL_CON0_PLL_SHARED1 0x0140
#define PLL_CON3_PLL_SHARED1 0x014c
#define PLL_CON0_PLL_SHARED2 0x0180
#define PLL_CON3_PLL_SHARED2 0x018c
#define PLL_CON0_PLL_SHARED3 0x01c0
#define PLL_CON3_PLL_SHARED3 0x01cc
#define PLL_CON0_PLL_SHARED4 0x0200
#define PLL_CON3_PLL_SHARED4 0x020c
/* MUX */
#define CLK_CON_MUX_MUX_CLKCMU_ACC_BUS 0x1000
#define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004
#define CLK_CON_MUX_MUX_CLKCMU_AUD_BUS 0x1008
#define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x100c
#define CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS 0x1010
#define CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS 0x1018
#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x101c
#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1020
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER 0x1024
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x102c
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER 0x1030
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1034
#define CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS 0x1040
#define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC 0x1044
#define CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS 0x1048
#define CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS 0x104c
#define CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS 0x1050
#define CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS 0x1054
#define CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE 0x1058
#define CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS 0x105c
#define CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD 0x1060
#define CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD 0x1064
#define CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS 0x1068
#define CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET 0x106c
#define CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD 0x1070
#define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1074
#define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1078
#define CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH 0x107c
#define CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH 0x1080
#define CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH 0x1084
#define CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS 0x108c
#define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x1090
#define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD 0x1094
#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x109c
#define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x1098
#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x109c
#define CLK_CON_MUX_MUX_CLKCMU_NPU_BUS 0x10a0
#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10a4
#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10a8
#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10ac
#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10b0
#define CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS 0x10b4
#define CLK_CON_MUX_MUX_CMU_CMUREF 0x10c0
/* DIV */
#define CLK_CON_DIV_CLKCMU_ACC_BUS 0x1800
#define CLK_CON_DIV_CLKCMU_APM_BUS 0x1804
#define CLK_CON_DIV_CLKCMU_AUD_BUS 0x1808
#define CLK_CON_DIV_CLKCMU_AUD_CPU 0x180c
#define CLK_CON_DIV_CLKCMU_BUSC_BUS 0x1810
#define CLK_CON_DIV_CLKCMU_BUSMC_BUS 0x1818
#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x181c
#define CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER 0x1820
#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1828
#define CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER 0x182c
#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x1830
#define CLK_CON_DIV_CLKCMU_DPTX_BUS 0x183c
#define CLK_CON_DIV_CLKCMU_DPTX_DPGTC 0x1840
#define CLK_CON_DIV_CLKCMU_DPUM_BUS 0x1844
#define CLK_CON_DIV_CLKCMU_DPUS0_BUS 0x1848
#define CLK_CON_DIV_CLKCMU_DPUS1_BUS 0x184c
#define CLK_CON_DIV_CLKCMU_FSYS0_BUS 0x1850
#define CLK_CON_DIV_CLKCMU_FSYS0_PCIE 0x1854
#define CLK_CON_DIV_CLKCMU_FSYS1_BUS 0x1858
#define CLK_CON_DIV_CLKCMU_FSYS1_USBDRD 0x185c
#define CLK_CON_DIV_CLKCMU_FSYS2_BUS 0x1860
#define CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET 0x1864
#define CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD 0x1868
#define CLK_CON_DIV_CLKCMU_G2D_G2D 0x186c
#define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x1870
#define CLK_CON_DIV_CLKCMU_G3D00_SWITCH 0x1874
#define CLK_CON_DIV_CLKCMU_G3D01_SWITCH 0x1878
#define CLK_CON_DIV_CLKCMU_G3D1_SWITCH 0x187c
#define CLK_CON_DIV_CLKCMU_ISPB_BUS 0x1884
#define CLK_CON_DIV_CLKCMU_MFC_MFC 0x1888
#define CLK_CON_DIV_CLKCMU_MFC_WFD 0x188c
#define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x1890
#define CLK_CON_DIV_CLKCMU_NPU_BUS 0x1894
#define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x1898
#define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x189c
#define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18a0
#define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18a4
#define CLK_CON_DIV_CLKCMU_PERIS_BUS 0x18a8
#define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18b4
#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18b8
#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18bc
#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x18c0
#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x18c4
#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18c8
#define CLK_CON_DIV_PLL_SHARED2_DIV2 0x18cc
#define CLK_CON_DIV_PLL_SHARED2_DIV3 0x18d0
#define CLK_CON_DIV_PLL_SHARED2_DIV4 0x18d4
#define CLK_CON_DIV_PLL_SHARED4_DIV2 0x18d4
#define CLK_CON_DIV_PLL_SHARED4_DIV4 0x18d8
/* GATE */
#define CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST 0x2000
#define CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST 0x2004
#define CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST 0x2008
#define CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST 0x2010
#define CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST 0x2018
#define CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST 0x2020
#define CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD 0x2024
#define CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH 0x2028
#define CLK_CON_GAT_GATE_CLKCMU_ACC_BUS 0x202c
#define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2030
#define CLK_CON_GAT_GATE_CLKCMU_AUD_BUS 0x2034
#define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU 0x2038
#define CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS 0x203c
#define CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS 0x2044
#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2048
#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x204c
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER 0x2050
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2058
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER 0x205c
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2060
#define CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS 0x206c
#define CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC 0x2070
#define CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS 0x2060
#define CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS 0x2064
#define CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS 0x207c
#define CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS 0x2080
#define CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE 0x2084
#define CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS 0x2088
#define CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD 0x208c
#define CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS 0x2090
#define CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET 0x2094
#define CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD 0x2098
#define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x209c
#define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x20a0
#define CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH 0x20a4
#define CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH 0x20a8
#define CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH 0x20ac
#define CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS 0x20b4
#define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20b8
#define CLK_CON_GAT_GATE_CLKCMU_MFC_WFD 0x20bc
#define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20c0
#define CLK_CON_GAT_GATE_CLKCMU_NPU_BUS 0x20c4
#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20c8
#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20cc
#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x20d0
#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x20d4
#define CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS 0x20d8
static const unsigned long top_clk_regs[] __initconst = {
PLL_LOCKTIME_PLL_SHARED0,
PLL_LOCKTIME_PLL_SHARED1,
PLL_LOCKTIME_PLL_SHARED2,
PLL_LOCKTIME_PLL_SHARED3,
PLL_LOCKTIME_PLL_SHARED4,
PLL_CON0_PLL_SHARED0,
PLL_CON3_PLL_SHARED0,
PLL_CON0_PLL_SHARED1,
PLL_CON3_PLL_SHARED1,
PLL_CON0_PLL_SHARED2,
PLL_CON3_PLL_SHARED2,
PLL_CON0_PLL_SHARED3,
PLL_CON3_PLL_SHARED3,
PLL_CON0_PLL_SHARED4,
PLL_CON3_PLL_SHARED4,
CLK_CON_MUX_MUX_CLKCMU_ACC_BUS,
CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
CLK_CON_MUX_MUX_CLKCMU_AUD_BUS,
CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS,
CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER,
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER,
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS,
CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC,
CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS,
CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS,
CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS,
CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS,
CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE,
CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS,
CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD,
CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD,
CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS,
CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET,
CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD,
CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS,
CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
CLK_CON_MUX_MUX_CLKCMU_MFC_WFD,
CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_NPU_BUS,
CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS,
CLK_CON_MUX_MUX_CMU_CMUREF,
CLK_CON_DIV_CLKCMU_ACC_BUS,
CLK_CON_DIV_CLKCMU_APM_BUS,
CLK_CON_DIV_CLKCMU_AUD_BUS,
CLK_CON_DIV_CLKCMU_AUD_CPU,
CLK_CON_DIV_CLKCMU_BUSC_BUS,
CLK_CON_DIV_CLKCMU_BUSMC_BUS,
CLK_CON_DIV_CLKCMU_CORE_BUS,
CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER,
CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER,
CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
CLK_CON_DIV_CLKCMU_DPTX_BUS,
CLK_CON_DIV_CLKCMU_DPTX_DPGTC,
CLK_CON_DIV_CLKCMU_DPUM_BUS,
CLK_CON_DIV_CLKCMU_DPUS0_BUS,
CLK_CON_DIV_CLKCMU_DPUS1_BUS,
CLK_CON_DIV_CLKCMU_FSYS0_BUS,
CLK_CON_DIV_CLKCMU_FSYS0_PCIE,
CLK_CON_DIV_CLKCMU_FSYS1_BUS,
CLK_CON_DIV_CLKCMU_FSYS1_USBDRD,
CLK_CON_DIV_CLKCMU_FSYS2_BUS,
CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET,
CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD,
CLK_CON_DIV_CLKCMU_G2D_G2D,
CLK_CON_DIV_CLKCMU_G2D_MSCL,
CLK_CON_DIV_CLKCMU_G3D00_SWITCH,
CLK_CON_DIV_CLKCMU_G3D01_SWITCH,
CLK_CON_DIV_CLKCMU_G3D1_SWITCH,
CLK_CON_DIV_CLKCMU_ISPB_BUS,
CLK_CON_DIV_CLKCMU_MFC_MFC,
CLK_CON_DIV_CLKCMU_MFC_WFD,
CLK_CON_DIV_CLKCMU_MIF_BUSP,
CLK_CON_DIV_CLKCMU_NPU_BUS,
CLK_CON_DIV_CLKCMU_PERIC0_BUS,
CLK_CON_DIV_CLKCMU_PERIC0_IP,
CLK_CON_DIV_CLKCMU_PERIC1_BUS,
CLK_CON_DIV_CLKCMU_PERIC1_IP,
CLK_CON_DIV_CLKCMU_PERIS_BUS,
CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,
CLK_CON_DIV_PLL_SHARED0_DIV2,
CLK_CON_DIV_PLL_SHARED0_DIV3,
CLK_CON_DIV_PLL_SHARED1_DIV2,
CLK_CON_DIV_PLL_SHARED1_DIV3,
CLK_CON_DIV_PLL_SHARED1_DIV4,
CLK_CON_DIV_PLL_SHARED2_DIV2,
CLK_CON_DIV_PLL_SHARED2_DIV3,
CLK_CON_DIV_PLL_SHARED2_DIV4,
CLK_CON_DIV_PLL_SHARED4_DIV2,
CLK_CON_DIV_PLL_SHARED4_DIV4,
CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST,
CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST,
CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST,
CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST,
CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST,
CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST,
CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD,
CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH,
CLK_CON_GAT_GATE_CLKCMU_ACC_BUS,
CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
CLK_CON_GAT_GATE_CLKCMU_AUD_BUS,
CLK_CON_GAT_GATE_CLKCMU_AUD_CPU,
CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS,
CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS,
CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER,
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER,
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS,
CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC,
CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS,
CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS,
CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS,
CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS,
CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE,
CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS,
CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD,
CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS,
CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET,
CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD,
CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH,
CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH,
CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH,
CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS,
CLK_CON_GAT_GATE_CLKCMU_MFC_MFC,
CLK_CON_GAT_GATE_CLKCMU_MFC_WFD,
CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
CLK_CON_GAT_GATE_CLKCMU_NPU_BUS,
CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
};
static const struct samsung_pll_clock top_pll_clks[] __initconst = {
/* CMU_TOP_PURECLKCOMP */
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared1_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL),
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared2_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL),
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared3_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared4_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
};
/* List of parent clocks for Muxes in CMU_TOP */
PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" };
PNAME(mout_shared4_pll_p) = { "oscclk", "fout_shared4_pll" };
PNAME(mout_clkcmu_cmu_boost_p) = { "dout_shared2_div3", "dout_shared1_div4",
"dout_shared2_div4", "dout_shared4_div4" };
PNAME(mout_clkcmu_cmu_cmuref_p) = { "oscclk", "dout_cmu_boost" };
PNAME(mout_clkcmu_acc_bus_p) = { "dout_shared1_div3", "dout_shared2_div3",
"dout_shared1_div4", "dout_shared2_div4" };
PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared2_div3", "dout_shared1_div4",
"dout_shared2_div4", "dout_shared4_div4" };
PNAME(mout_clkcmu_aud_cpu_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared2_div2", "dout_shared0_div3",
"dout_shared4_div2", "dout_shared1_div3",
"fout_shared3_pll" };
PNAME(mout_clkcmu_aud_bus_p) = { "dout_shared4_div2", "dout_shared1_div3",
"dout_shared2_div3", "dout_shared1_div4" };
PNAME(mout_clkcmu_busc_bus_p) = { "dout_shared2_div3", "dout_shared1_div4",
"dout_shared2_div4", "dout_shared4_div4" };
PNAME(mout_clkcmu_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared2_div2", "dout_shared0_div3",
"dout_shared4_div2", "dout_shared1_div3",
"dout_shared2_div3", "fout_shared3_pll" };
PNAME(mout_clkcmu_cpucl0_switch_p) = {
"dout_shared0_div2", "dout_shared1_div2",
"dout_shared2_div2", "dout_shared4_div2" };
PNAME(mout_clkcmu_cpucl0_cluster_p) = {
"fout_shared2_pll", "fout_shared4_pll",
"dout_shared0_div2", "dout_shared1_div2",
"dout_shared2_div2", "dout_shared4_div2",
"dout_shared2_div3", "fout_shared3_pll" };
PNAME(mout_clkcmu_dptx_bus_p) = { "dout_shared4_div2", "dout_shared2_div3",
"dout_shared1_div4", "dout_shared2_div4" };
PNAME(mout_clkcmu_dptx_dpgtc_p) = { "oscclk", "dout_shared2_div3",
"dout_shared2_div4", "dout_shared4_div4" };
PNAME(mout_clkcmu_dpum_bus_p) = { "dout_shared1_div3", "dout_shared2_div3",
"dout_shared1_div4", "dout_shared2_div4",
"dout_shared4_div4", "fout_shared3_pll" };
PNAME(mout_clkcmu_fsys0_bus_p) = {
"dout_shared4_div2", "dout_shared2_div3",
"dout_shared1_div4", "dout_shared2_div4" };
PNAME(mout_clkcmu_fsys0_pcie_p) = { "oscclk", "dout_shared2_div4" };
PNAME(mout_clkcmu_fsys1_bus_p) = { "dout_shared2_div3", "dout_shared1_div4",
"dout_shared2_div4", "dout_shared4_div4" };
PNAME(mout_clkcmu_fsys1_usbdrd_p) = {
"oscclk", "dout_shared2_div3",
"dout_shared2_div4", "dout_shared4_div4" };
PNAME(mout_clkcmu_fsys1_mmc_card_p) = {
"oscclk", "dout_shared2_div2",
"dout_shared4_div2", "dout_shared2_div3" };
PNAME(mout_clkcmu_fsys2_ethernet_p) = {
"oscclk", "dout_shared2_div2",
"dout_shared0_div3", "dout_shared2_div3",
"dout_shared1_div4", "fout_shared3_pll" };
PNAME(mout_clkcmu_g2d_g2d_p) = { "dout_shared2_div2", "dout_shared0_div3",
"dout_shared4_div2", "dout_shared1_div3",
"dout_shared2_div3", "dout_shared1_div4",
"dout_shared2_div4", "dout_shared4_div4" };
PNAME(mout_clkcmu_g3d0_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared2_div2", "dout_shared4_div2" };
PNAME(mout_clkcmu_g3d1_switch_p) = { "dout_shared2_div2", "dout_shared4_div2",
"dout_shared2_div3", "dout_shared1_div4" };
PNAME(mout_clkcmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
"fout_shared2_pll", "fout_shared4_pll",
"dout_shared0_div2", "dout_shared1_div2",
"dout_shared2_div2", "fout_shared3_pll" };
PNAME(mout_clkcmu_npu_bus_p) = { "dout_shared1_div2", "dout_shared2_div2",
"dout_shared0_div3", "dout_shared4_div2",
"dout_shared1_div3", "dout_shared2_div3",
"dout_shared1_div4", "fout_shared3_pll" };
PNAME(mout_clkcmu_peric0_bus_p) = { "dout_shared2_div3", "dout_shared2_div4" };
static const struct samsung_mux_clock top_mux_clks[] __initconst = {
/* CMU_TOP_PURECLKCOMP */
MUX(MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
PLL_CON0_PLL_SHARED0, 4, 1),
MUX(MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
PLL_CON0_PLL_SHARED1, 4, 1),
MUX(MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
PLL_CON0_PLL_SHARED2, 4, 1),
MUX(MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
PLL_CON0_PLL_SHARED3, 4, 1),
MUX(MOUT_SHARED4_PLL, "mout_shared4_pll", mout_shared4_pll_p,
PLL_CON0_PLL_SHARED4, 4, 1),
/* BOOST */
MUX(MOUT_CLKCMU_CMU_BOOST, "mout_clkcmu_cmu_boost",
mout_clkcmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
MUX(MOUT_CLKCMU_CMU_CMUREF, "mout_clkcmu_cmu_cmuref",
mout_clkcmu_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
/* ACC */
MUX(MOUT_CLKCMU_ACC_BUS, "mout_clkcmu_acc_bus", mout_clkcmu_acc_bus_p,
CLK_CON_MUX_MUX_CLKCMU_ACC_BUS, 0, 2),
/* APM */
MUX(MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus", mout_clkcmu_apm_bus_p,
CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 2),
/* AUD */
MUX(MOUT_CLKCMU_AUD_CPU, "mout_clkcmu_aud_cpu", mout_clkcmu_aud_cpu_p,
CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 3),
MUX(MOUT_CLKCMU_AUD_BUS, "mout_clkcmu_aud_bus", mout_clkcmu_aud_bus_p,
CLK_CON_MUX_MUX_CLKCMU_AUD_BUS, 0, 2),
/* BUSC */
MUX(MOUT_CLKCMU_BUSC_BUS, "mout_clkcmu_busc_bus",
mout_clkcmu_busc_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS, 0, 2),
/* BUSMC */
MUX(MOUT_CLKCMU_BUSMC_BUS, "mout_clkcmu_busmc_bus",
mout_clkcmu_busc_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS, 0, 2),
/* CORE */
MUX(MOUT_CLKCMU_CORE_BUS, "mout_clkcmu_core_bus",
mout_clkcmu_core_bus_p, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3),
/* CPUCL0 */
MUX(MOUT_CLKCMU_CPUCL0_SWITCH, "mout_clkcmu_cpucl0_switch",
mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
0, 2),
MUX(MOUT_CLKCMU_CPUCL0_CLUSTER, "mout_clkcmu_cpucl0_cluster",
mout_clkcmu_cpucl0_cluster_p,
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER, 0, 3),
/* CPUCL1 */
MUX(MOUT_CLKCMU_CPUCL1_SWITCH, "mout_clkcmu_cpucl1_switch",
mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
0, 2),
MUX(MOUT_CLKCMU_CPUCL1_CLUSTER, "mout_clkcmu_cpucl1_cluster",
mout_clkcmu_cpucl0_cluster_p,
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER, 0, 3),
/* DPTX */
MUX(MOUT_CLKCMU_DPTX_BUS, "mout_clkcmu_dptx_bus",
mout_clkcmu_dptx_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS, 0, 2),
MUX(MOUT_CLKCMU_DPTX_DPGTC, "mout_clkcmu_dptx_dpgtc",
mout_clkcmu_dptx_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC, 0, 2),
/* DPUM */
MUX(MOUT_CLKCMU_DPUM_BUS, "mout_clkcmu_dpum_bus",
mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS, 0, 3),
/* DPUS */
MUX(MOUT_CLKCMU_DPUS0_BUS, "mout_clkcmu_dpus0_bus",
mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS, 0, 3),
MUX(MOUT_CLKCMU_DPUS1_BUS, "mout_clkcmu_dpus1_bus",
mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS, 0, 3),
/* FSYS0 */
MUX(MOUT_CLKCMU_FSYS0_BUS, "mout_clkcmu_fsys0_bus",
mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS, 0, 2),
MUX(MOUT_CLKCMU_FSYS0_PCIE, "mout_clkcmu_fsys0_pcie",
mout_clkcmu_fsys0_pcie_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE, 0, 1),
/* FSYS1 */
MUX(MOUT_CLKCMU_FSYS1_BUS, "mout_clkcmu_fsys1_bus",
mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS, 0, 2),
MUX(MOUT_CLKCMU_FSYS1_USBDRD, "mout_clkcmu_fsys1_usbdrd",
mout_clkcmu_fsys1_usbdrd_p, CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD,
0, 2),
MUX(MOUT_CLKCMU_FSYS1_MMC_CARD, "mout_clkcmu_fsys1_mmc_card",
mout_clkcmu_fsys1_mmc_card_p,
CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD, 0, 2),
/* FSYS2 */
MUX(MOUT_CLKCMU_FSYS2_BUS, "mout_clkcmu_fsys2_bus",
mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS, 0, 2),
MUX(MOUT_CLKCMU_FSYS2_UFS_EMBD, "mout_clkcmu_fsys2_ufs_embd",
mout_clkcmu_fsys1_usbdrd_p, CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD,
0, 2),
MUX(MOUT_CLKCMU_FSYS2_ETHERNET, "mout_clkcmu_fsys2_ethernet",
mout_clkcmu_fsys2_ethernet_p,
CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET, 0, 3),
/* G2D */
MUX(MOUT_CLKCMU_G2D_G2D, "mout_clkcmu_g2d_g2d", mout_clkcmu_g2d_g2d_p,
CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3),
MUX(MOUT_CLKCMU_G2D_MSCL, "mout_clkcmu_g2d_mscl",
mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
/* G3D0 */
MUX(MOUT_CLKCMU_G3D00_SWITCH, "mout_clkcmu_g3d00_switch",
mout_clkcmu_g3d0_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH,
0, 2),
MUX(MOUT_CLKCMU_G3D01_SWITCH, "mout_clkcmu_g3d01_switch",
mout_clkcmu_g3d0_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH,
0, 2),
/* G3D1 */
MUX(MOUT_CLKCMU_G3D1_SWITCH, "mout_clkcmu_g3d1_switch",
mout_clkcmu_g3d1_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH,
0, 2),
/* ISPB */
MUX(MOUT_CLKCMU_ISPB_BUS, "mout_clkcmu_ispb_bus",
mout_clkcmu_acc_bus_p, CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS, 0, 2),
/* MFC */
MUX(MOUT_CLKCMU_MFC_MFC, "mout_clkcmu_mfc_mfc",
mout_clkcmu_g3d1_switch_p, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
MUX(MOUT_CLKCMU_MFC_WFD, "mout_clkcmu_mfc_wfd",
mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0, 2),
/* MIF */
MUX(MOUT_CLKCMU_MIF_SWITCH, "mout_clkcmu_mif_switch",
mout_clkcmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
MUX(MOUT_CLKCMU_MIF_BUSP, "mout_clkcmu_mif_busp",
mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
/* NPU */
MUX(MOUT_CLKCMU_NPU_BUS, "mout_clkcmu_npu_bus", mout_clkcmu_npu_bus_p,
CLK_CON_MUX_MUX_CLKCMU_NPU_BUS, 0, 3),
/* PERIC0 */
MUX(MOUT_CLKCMU_PERIC0_BUS, "mout_clkcmu_peric0_bus",
mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 1),
MUX(MOUT_CLKCMU_PERIC0_IP, "mout_clkcmu_peric0_ip",
mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1),
/* PERIC1 */
MUX(MOUT_CLKCMU_PERIC1_BUS, "mout_clkcmu_peric1_bus",
mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 1),
MUX(MOUT_CLKCMU_PERIC1_IP, "mout_clkcmu_peric1_ip",
mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1),
/* PERIS */
MUX(MOUT_CLKCMU_PERIS_BUS, "mout_clkcmu_peris_bus",
mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, 0, 1),
};
static const struct samsung_div_clock top_div_clks[] __initconst = {
/* CMU_TOP_PURECLKCOMP */
DIV(DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
DIV(DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
DIV(DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
DIV(DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
DIV(DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
DIV(DOUT_SHARED2_DIV3, "dout_shared2_div3", "mout_shared2_pll",
CLK_CON_DIV_PLL_SHARED2_DIV3, 0, 2),
DIV(DOUT_SHARED2_DIV2, "dout_shared2_div2", "mout_shared2_pll",
CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
DIV(DOUT_SHARED2_DIV4, "dout_shared2_div4", "dout_shared2_div2",
CLK_CON_DIV_PLL_SHARED2_DIV4, 0, 1),
DIV(DOUT_SHARED4_DIV2, "dout_shared4_div2", "mout_shared4_pll",
CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1),
DIV(DOUT_SHARED4_DIV4, "dout_shared4_div4", "dout_shared4_div2",
CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
/* BOOST */
DIV(DOUT_CLKCMU_CMU_BOOST, "dout_clkcmu_cmu_boost",
"gout_clkcmu_cmu_boost", CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
/* ACC */
DIV(DOUT_CLKCMU_ACC_BUS, "dout_clkcmu_acc_bus", "gout_clkcmu_acc_bus",
CLK_CON_DIV_CLKCMU_ACC_BUS, 0, 4),
/* APM */
DIV(DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus", "gout_clkcmu_apm_bus",
CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
/* AUD */
DIV(DOUT_CLKCMU_AUD_CPU, "dout_clkcmu_aud_cpu", "gout_clkcmu_aud_cpu",
CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
DIV(DOUT_CLKCMU_AUD_BUS, "dout_clkcmu_aud_bus", "gout_clkcmu_aud_bus",
CLK_CON_DIV_CLKCMU_AUD_BUS, 0, 4),
/* BUSC */
DIV(DOUT_CLKCMU_BUSC_BUS, "dout_clkcmu_busc_bus",
"gout_clkcmu_busc_bus", CLK_CON_DIV_CLKCMU_BUSC_BUS, 0, 4),
/* BUSMC */
DIV(DOUT_CLKCMU_BUSMC_BUS, "dout_clkcmu_busmc_bus",
"gout_clkcmu_busmc_bus", CLK_CON_DIV_CLKCMU_BUSMC_BUS, 0, 4),
/* CORE */
DIV(DOUT_CLKCMU_CORE_BUS, "dout_clkcmu_core_bus",
"gout_clkcmu_core_bus", CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
/* CPUCL0 */
DIV(DOUT_CLKCMU_CPUCL0_SWITCH, "dout_clkcmu_cpucl0_switch",
"gout_clkcmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
0, 3),
DIV(DOUT_CLKCMU_CPUCL0_CLUSTER, "dout_clkcmu_cpucl0_cluster",
"gout_clkcmu_cpucl0_cluster", CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER,
0, 3),
/* CPUCL1 */
DIV(DOUT_CLKCMU_CPUCL1_SWITCH, "dout_clkcmu_cpucl1_switch",
"gout_clkcmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
0, 3),
DIV(DOUT_CLKCMU_CPUCL1_CLUSTER, "dout_clkcmu_cpucl1_cluster",
"gout_clkcmu_cpucl1_cluster", CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER,
0, 3),
/* DPTX */
DIV(DOUT_CLKCMU_DPTX_BUS, "dout_clkcmu_dptx_bus",
"gout_clkcmu_dptx_bus", CLK_CON_DIV_CLKCMU_DPTX_BUS, 0, 4),
DIV(DOUT_CLKCMU_DPTX_DPGTC, "dout_clkcmu_dptx_dpgtc",
"gout_clkcmu_dptx_dpgtc", CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 0, 3),
/* DPUM */
DIV(DOUT_CLKCMU_DPUM_BUS, "dout_clkcmu_dpum_bus",
"gout_clkcmu_dpum_bus", CLK_CON_DIV_CLKCMU_DPUM_BUS, 0, 4),
/* DPUS */
DIV(DOUT_CLKCMU_DPUS0_BUS, "dout_clkcmu_dpus0_bus",
"gout_clkcmu_dpus0_bus", CLK_CON_DIV_CLKCMU_DPUS0_BUS, 0, 4),
DIV(DOUT_CLKCMU_DPUS1_BUS, "dout_clkcmu_dpus1_bus",
"gout_clkcmu_dpus1_bus", CLK_CON_DIV_CLKCMU_DPUS1_BUS, 0, 4),
/* FSYS0 */
DIV(DOUT_CLKCMU_FSYS0_BUS, "dout_clkcmu_fsys0_bus",
"gout_clkcmu_fsys0_bus", CLK_CON_DIV_CLKCMU_FSYS0_BUS, 0, 4),
/* FSYS1 */
DIV(DOUT_CLKCMU_FSYS1_BUS, "dout_clkcmu_fsys1_bus",
"gout_clkcmu_fsys1_bus", CLK_CON_DIV_CLKCMU_FSYS1_BUS, 0, 4),
DIV(DOUT_CLKCMU_FSYS1_USBDRD, "dout_clkcmu_fsys1_usbdrd",
"gout_clkcmu_fsys1_usbdrd", CLK_CON_DIV_CLKCMU_FSYS1_USBDRD, 0, 4),
/* FSYS2 */
DIV(DOUT_CLKCMU_FSYS2_BUS, "dout_clkcmu_fsys2_bus",
"gout_clkcmu_fsys2_bus", CLK_CON_DIV_CLKCMU_FSYS2_BUS, 0, 4),
DIV(DOUT_CLKCMU_FSYS2_UFS_EMBD, "dout_clkcmu_fsys2_ufs_embd",
"gout_clkcmu_fsys2_ufs_embd", CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD,
0, 3),
DIV(DOUT_CLKCMU_FSYS2_ETHERNET, "dout_clkcmu_fsys2_ethernet",
"gout_clkcmu_fsys2_ethernet", CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET,
0, 3),
/* G2D */
DIV(DOUT_CLKCMU_G2D_G2D, "dout_clkcmu_g2d_g2d", "gout_clkcmu_g2d_g2d",
CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
DIV(DOUT_CLKCMU_G2D_MSCL, "dout_clkcmu_g2d_mscl",
"gout_clkcmu_g2d_mscl", CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
/* G3D0 */
DIV(DOUT_CLKCMU_G3D00_SWITCH, "dout_clkcmu_g3d00_switch",
"gout_clkcmu_g3d00_switch", CLK_CON_DIV_CLKCMU_G3D00_SWITCH, 0, 3),
DIV(DOUT_CLKCMU_G3D01_SWITCH, "dout_clkcmu_g3d01_switch",
"gout_clkcmu_g3d01_switch", CLK_CON_DIV_CLKCMU_G3D01_SWITCH, 0, 3),
/* G3D1 */
DIV(DOUT_CLKCMU_G3D1_SWITCH, "dout_clkcmu_g3d1_switch",
"gout_clkcmu_g3d1_switch", CLK_CON_DIV_CLKCMU_G3D1_SWITCH, 0, 3),
/* ISPB */
DIV(DOUT_CLKCMU_ISPB_BUS, "dout_clkcmu_ispb_bus",
"gout_clkcmu_ispb_bus", CLK_CON_DIV_CLKCMU_ISPB_BUS, 0, 4),
/* MFC */
DIV(DOUT_CLKCMU_MFC_MFC, "dout_clkcmu_mfc_mfc", "gout_clkcmu_mfc_mfc",
CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
DIV(DOUT_CLKCMU_MFC_WFD, "dout_clkcmu_mfc_wfd", "gout_clkcmu_mfc_wfd",
CLK_CON_DIV_CLKCMU_MFC_WFD, 0, 4),
/* MIF */
DIV(DOUT_CLKCMU_MIF_BUSP, "dout_clkcmu_mif_busp",
"gout_clkcmu_mif_busp", CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
/* NPU */
DIV(DOUT_CLKCMU_NPU_BUS, "dout_clkcmu_npu_bus", "gout_clkcmu_npu_bus",
CLK_CON_DIV_CLKCMU_NPU_BUS, 0, 4),
/* PERIC0 */
DIV(DOUT_CLKCMU_PERIC0_BUS, "dout_clkcmu_peric0_bus",
"gout_clkcmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
DIV(DOUT_CLKCMU_PERIC0_IP, "dout_clkcmu_peric0_ip",
"gout_clkcmu_peric0_ip", CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
/* PERIC1 */
DIV(DOUT_CLKCMU_PERIC1_BUS, "dout_clkcmu_peric1_bus",
"gout_clkcmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
DIV(DOUT_CLKCMU_PERIC1_IP, "dout_clkcmu_peric1_ip",
"gout_clkcmu_peric1_ip", CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
/* PERIS */
DIV(DOUT_CLKCMU_PERIS_BUS, "dout_clkcmu_peris_bus",
"gout_clkcmu_peris_bus", CLK_CON_DIV_CLKCMU_PERIS_BUS, 0, 4),
};
static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
FFACTOR(DOUT_CLKCMU_FSYS0_PCIE, "dout_clkcmu_fsys0_pcie",
"gout_clkcmu_fsys0_pcie", 1, 4, 0),
};
static const struct samsung_gate_clock top_gate_clks[] __initconst = {
/* BOOST */
GATE(GOUT_CLKCMU_CMU_BOOST, "gout_clkcmu_cmu_boost",
"mout_clkcmu_cmu_boost", CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
21, 0, 0),
GATE(GOUT_CLKCMU_CPUCL0_BOOST, "gout_clkcmu_cpucl0_boost",
"dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST, 21, 0, 0),
GATE(GOUT_CLKCMU_CPUCL1_BOOST, "gout_clkcmu_cpucl1_boost",
"dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST, 21, 0, 0),
GATE(GOUT_CLKCMU_CORE_BOOST, "gout_clkcmu_core_boost",
"dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST, 21, 0, 0),
GATE(GOUT_CLKCMU_BUSC_BOOST, "gout_clkcmu_busc_boost",
"dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST, 21, 0, 0),
GATE(GOUT_CLKCMU_BUSMC_BOOST, "gout_clkcmu_busmc_boost",
"dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST, 21, 0, 0),
GATE(GOUT_CLKCMU_MIF_BOOST, "gout_clkcmu_mif_boost", "dout_cmu_boost",
CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST, 21, 0, 0),
/* ACC */
GATE(GOUT_CLKCMU_ACC_BUS, "gout_clkcmu_acc_bus", "mout_clkcmu_acc_bus",
CLK_CON_GAT_GATE_CLKCMU_ACC_BUS, 21, 0, 0),
/* APM */
GATE(GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus", "mout_clkcmu_apm_bus",
CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, CLK_IGNORE_UNUSED, 0),
/* AUD */
GATE(GOUT_CLKCMU_AUD_CPU, "gout_clkcmu_aud_cpu", "mout_clkcmu_aud_cpu",
CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, 21, 0, 0),
GATE(GOUT_CLKCMU_AUD_BUS, "gout_clkcmu_aud_bus", "mout_clkcmu_aud_bus",
CLK_CON_GAT_GATE_CLKCMU_AUD_BUS, 21, 0, 0),
/* BUSC */
GATE(GOUT_CLKCMU_BUSC_BUS, "gout_clkcmu_busc_bus",
"mout_clkcmu_busc_bus", CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS, 21,
CLK_IS_CRITICAL, 0),
/* BUSMC */
GATE(GOUT_CLKCMU_BUSMC_BUS, "gout_clkcmu_busmc_bus",
"mout_clkcmu_busmc_bus", CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS, 21,
CLK_IS_CRITICAL, 0),
/* CORE */
GATE(GOUT_CLKCMU_CORE_BUS, "gout_clkcmu_core_bus",
"mout_clkcmu_core_bus", CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
21, 0, 0),
/* CPUCL0 */
GATE(GOUT_CLKCMU_CPUCL0_SWITCH, "gout_clkcmu_cpucl0_switch",
"mout_clkcmu_cpucl0_switch",
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, CLK_IGNORE_UNUSED, 0),
GATE(GOUT_CLKCMU_CPUCL0_CLUSTER, "gout_clkcmu_cpucl0_cluster",
"mout_clkcmu_cpucl0_cluster",
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER, 21, CLK_IGNORE_UNUSED, 0),
/* CPUCL1 */
GATE(GOUT_CLKCMU_CPUCL1_SWITCH, "gout_clkcmu_cpucl1_switch",
"mout_clkcmu_cpucl1_switch",
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, CLK_IGNORE_UNUSED, 0),
GATE(GOUT_CLKCMU_CPUCL1_CLUSTER, "gout_clkcmu_cpucl1_cluster",
"mout_clkcmu_cpucl1_cluster",
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER, 21, CLK_IGNORE_UNUSED, 0),
/* DPTX */
GATE(GOUT_CLKCMU_DPTX_BUS, "gout_clkcmu_dptx_bus",
"mout_clkcmu_dptx_bus", CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS,
21, 0, 0),
GATE(GOUT_CLKCMU_DPTX_DPGTC, "gout_clkcmu_dptx_dpgtc",
"mout_clkcmu_dptx_dpgtc", CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC,
21, 0, 0),
/* DPUM */
GATE(GOUT_CLKCMU_DPUM_BUS, "gout_clkcmu_dpum_bus",
"mout_clkcmu_dpum_bus", CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS,
21, 0, 0),
/* DPUS */
GATE(GOUT_CLKCMU_DPUS0_BUS, "gout_clkcmu_dpus0_bus",
"mout_clkcmu_dpus0_bus", CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS,
21, 0, 0),
GATE(GOUT_CLKCMU_DPUS1_BUS, "gout_clkcmu_dpus1_bus",
"mout_clkcmu_dpus1_bus", CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS,
21, 0, 0),
/* FSYS0 */
GATE(GOUT_CLKCMU_FSYS0_BUS, "gout_clkcmu_fsys0_bus",
"mout_clkcmu_fsys0_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS,
21, 0, 0),
GATE(GOUT_CLKCMU_FSYS0_PCIE, "gout_clkcmu_fsys0_pcie",
"mout_clkcmu_fsys0_pcie", CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE,
21, 0, 0),
/* FSYS1 */
GATE(GOUT_CLKCMU_FSYS1_BUS, "gout_clkcmu_fsys1_bus",
"mout_clkcmu_fsys1_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS,
21, 0, 0),
GATE(GOUT_CLKCMU_FSYS1_USBDRD, "gout_clkcmu_fsys1_usbdrd",
"mout_clkcmu_fsys1_usbdrd", CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD,
21, 0, 0),
GATE(GOUT_CLKCMU_FSYS1_MMC_CARD, "gout_clkcmu_fsys1_mmc_card",
"mout_clkcmu_fsys1_mmc_card",
CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD, 21, 0, 0),
/* FSYS2 */
GATE(GOUT_CLKCMU_FSYS2_BUS, "gout_clkcmu_fsys2_bus",
"mout_clkcmu_fsys2_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS,
21, 0, 0),
GATE(GOUT_CLKCMU_FSYS2_UFS_EMBD, "gout_clkcmu_fsys2_ufs_embd",
"mout_clkcmu_fsys2_ufs_embd",
CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD, 21, 0, 0),
GATE(GOUT_CLKCMU_FSYS2_ETHERNET, "gout_clkcmu_fsys2_ethernet",
"mout_clkcmu_fsys2_ethernet",
CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET, 21, 0, 0),
/* G2D */
GATE(GOUT_CLKCMU_G2D_G2D, "gout_clkcmu_g2d_g2d",
"mout_clkcmu_g2d_g2d", CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
GATE(GOUT_CLKCMU_G2D_MSCL, "gout_clkcmu_g2d_mscl",
"mout_clkcmu_g2d_mscl", CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
21, 0, 0),
/* G3D0 */
GATE(GOUT_CLKCMU_G3D00_SWITCH, "gout_clkcmu_g3d00_switch",
"mout_clkcmu_g3d00_switch", CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH,
21, 0, 0),
GATE(GOUT_CLKCMU_G3D01_SWITCH, "gout_clkcmu_g3d01_switch",
"mout_clkcmu_g3d01_switch", CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH,
21, 0, 0),
/* G3D1 */
GATE(GOUT_CLKCMU_G3D1_SWITCH, "gout_clkcmu_g3d1_switch",
"mout_clkcmu_g3d1_switch", CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH,
21, 0, 0),
/* ISPB */
GATE(GOUT_CLKCMU_ISPB_BUS, "gout_clkcmu_ispb_bus",
"mout_clkcmu_ispb_bus", CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS,
21, 0, 0),
/* MFC */
GATE(GOUT_CLKCMU_MFC_MFC, "gout_clkcmu_mfc_mfc", "mout_clkcmu_mfc_mfc",
CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
GATE(GOUT_CLKCMU_MFC_WFD, "gout_clkcmu_mfc_wfd", "mout_clkcmu_mfc_wfd",
CLK_CON_GAT_GATE_CLKCMU_MFC_WFD, 21, 0, 0),
/* MIF */
GATE(GOUT_CLKCMU_MIF_SWITCH, "gout_clkcmu_mif_switch",
"mout_clkcmu_mif_switch", CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH,
21, CLK_IGNORE_UNUSED, 0),
GATE(GOUT_CLKCMU_MIF_BUSP, "gout_clkcmu_mif_busp",
"mout_clkcmu_mif_busp", CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
21, CLK_IGNORE_UNUSED, 0),
/* NPU */
GATE(GOUT_CLKCMU_NPU_BUS, "gout_clkcmu_npu_bus", "mout_clkcmu_npu_bus",
CLK_CON_GAT_GATE_CLKCMU_NPU_BUS, 21, 0, 0),
/* PERIC0 */
GATE(GOUT_CLKCMU_PERIC0_BUS, "gout_clkcmu_peric0_bus",
"mout_clkcmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
21, 0, 0),
GATE(GOUT_CLKCMU_PERIC0_IP, "gout_clkcmu_peric0_ip",
"mout_clkcmu_peric0_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
21, 0, 0),
/* PERIC1 */
GATE(GOUT_CLKCMU_PERIC1_BUS, "gout_clkcmu_peric1_bus",
"mout_clkcmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
21, 0, 0),
GATE(GOUT_CLKCMU_PERIC1_IP, "gout_clkcmu_peric1_ip",
"mout_clkcmu_peric1_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
21, 0, 0),
/* PERIS */
GATE(GOUT_CLKCMU_PERIS_BUS, "gout_clkcmu_peris_bus",
"mout_clkcmu_peris_bus", CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
21, CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_cmu_info top_cmu_info __initconst = {
.pll_clks = top_pll_clks,
.nr_pll_clks = ARRAY_SIZE(top_pll_clks),
.mux_clks = top_mux_clks,
.nr_mux_clks = ARRAY_SIZE(top_mux_clks),
.div_clks = top_div_clks,
.nr_div_clks = ARRAY_SIZE(top_div_clks),
.fixed_factor_clks = top_fixed_factor_clks,
.nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
.gate_clks = top_gate_clks,
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
.nr_clk_ids = CLKS_NR_TOP,
.clk_regs = top_clk_regs,
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
};
static void __init exynosautov9_cmu_top_init(struct device_node *np)
{
exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
}
/* Register CMU_TOP early, as it's a dependency for other early domains */
CLK_OF_DECLARE(exynosautov9_cmu_top, "samsung,exynosautov9-cmu-top",
exynosautov9_cmu_top_init);
/* ---- CMU_BUSMC ---------------------------------------------------------- */
/* Register Offset definitions for CMU_BUSMC (0x1b200000) */
#define PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER 0x0600
#define CLK_CON_DIV_DIV_CLK_BUSMC_BUSP 0x1800
#define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK 0x2078
#define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK 0x2080
static const unsigned long busmc_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER,
CLK_CON_DIV_DIV_CLK_BUSMC_BUSP,
CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK,
};
/* List of parent clocks for Muxes in CMU_BUSMC */
PNAME(mout_busmc_bus_user_p) = { "oscclk", "dout_clkcmu_busmc_bus" };
static const struct samsung_mux_clock busmc_mux_clks[] __initconst = {
MUX(CLK_MOUT_BUSMC_BUS_USER, "mout_busmc_bus_user",
mout_busmc_bus_user_p, PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER, 4, 1),
};
static const struct samsung_div_clock busmc_div_clks[] __initconst = {
DIV(CLK_DOUT_BUSMC_BUSP, "dout_busmc_busp", "mout_busmc_bus_user",
CLK_CON_DIV_DIV_CLK_BUSMC_BUSP, 0, 3),
};
static const struct samsung_gate_clock busmc_gate_clks[] __initconst = {
GATE(CLK_GOUT_BUSMC_PDMA0_PCLK, "gout_busmc_pdma0_pclk",
"dout_busmc_busp",
CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK, 21,
0, 0),
GATE(CLK_GOUT_BUSMC_SPDMA_PCLK, "gout_busmc_spdma_pclk",
"dout_busmc_busp",
CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK, 21,
0, 0),
};
static const struct samsung_cmu_info busmc_cmu_info __initconst = {
.mux_clks = busmc_mux_clks,
.nr_mux_clks = ARRAY_SIZE(busmc_mux_clks),
.div_clks = busmc_div_clks,
.nr_div_clks = ARRAY_SIZE(busmc_div_clks),
.gate_clks = busmc_gate_clks,
.nr_gate_clks = ARRAY_SIZE(busmc_gate_clks),
.nr_clk_ids = CLKS_NR_BUSMC,
.clk_regs = busmc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(busmc_clk_regs),
.clk_name = "dout_clkcmu_busmc_bus",
};
/* ---- CMU_CORE ----------------------------------------------------------- */
/* Register Offset definitions for CMU_CORE (0x1b030000) */
#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600
#define CLK_CON_MUX_MUX_CORE_CMUREF 0x1000
#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
#define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK 0x2000
#define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK 0x2004
#define CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK 0x2008
static const unsigned long core_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
CLK_CON_MUX_MUX_CORE_CMUREF,
CLK_CON_DIV_DIV_CLK_CORE_BUSP,
CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK,
CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK,
CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK,
};
/* List of parent clocks for Muxes in CMU_CORE */
PNAME(mout_core_bus_user_p) = { "oscclk", "dout_clkcmu_core_bus" };
static const struct samsung_mux_clock core_mux_clks[] __initconst = {
MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
};
static const struct samsung_div_clock core_div_clks[] __initconst = {
DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 3),
};
static const struct samsung_gate_clock core_gate_clks[] __initconst = {
GATE(CLK_GOUT_CORE_CCI_CLK, "gout_core_cci_clk", "mout_core_bus_user",
CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK, 21,
CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_CORE_CCI_PCLK, "gout_core_cci_pclk", "dout_core_busp",
CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK, 21,
CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_CORE_CMU_CORE_PCLK, "gout_core_cmu_core_pclk",
"dout_core_busp",
CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, 21,
CLK_IS_CRITICAL, 0),
};
static const struct samsung_cmu_info core_cmu_info __initconst = {
.mux_clks = core_mux_clks,
.nr_mux_clks = ARRAY_SIZE(core_mux_clks),
.div_clks = core_div_clks,
.nr_div_clks = ARRAY_SIZE(core_div_clks),
.gate_clks = core_gate_clks,
.nr_gate_clks = ARRAY_SIZE(core_gate_clks),
.nr_clk_ids = CLKS_NR_CORE,
.clk_regs = core_clk_regs,
.nr_clk_regs = ARRAY_SIZE(core_clk_regs),
.clk_name = "dout_clkcmu_core_bus",
};
/* ---- CMU_FSYS0 ---------------------------------------------------------- */
/* Register Offset definitions for CMU_FSYS2 (0x17700000) */
#define PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER 0x0600
#define PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER 0x0610
#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x2000
#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN 0x2004
#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN 0x2008
#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN 0x200c
#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN 0x2010
#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN 0x2014
#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN 0x2018
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK 0x205c
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK 0x2060
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK 0x2064
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK 0x206c
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK 0x2070
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK 0x2074
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK 0x207c
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK 0x2084
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK 0x2088
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK 0x208c
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK 0x2094
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK 0x2098
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK 0x209c
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK 0x20a4
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK 0x20ac
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK 0x20b0
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK 0x20b4
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK 0x20bc
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK 0x20c0
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK 0x20c4
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK 0x20cc
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK 0x20d4
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK 0x20d8
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK 0x20dc
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK 0x20e0
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK 0x20e4
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK 0x20e8
static const unsigned long fsys0_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER,
PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER,
CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN,
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN,
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN,
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN,
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN,
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK,
};
/* List of parent clocks for Muxes in CMU_FSYS0 */
PNAME(mout_fsys0_bus_user_p) = { "oscclk", "dout_clkcmu_fsys0_bus" };
PNAME(mout_fsys0_pcie_user_p) = { "oscclk", "dout_clkcmu_fsys0_pcie" };
static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
MUX(CLK_MOUT_FSYS0_BUS_USER, "mout_fsys0_bus_user",
mout_fsys0_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER, 4, 1),
MUX(CLK_MOUT_FSYS0_PCIE_USER, "mout_fsys0_pcie_user",
mout_fsys0_pcie_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER, 4, 1),
};
static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
GATE(CLK_GOUT_FSYS0_BUS_PCLK, "gout_fsys0_bus_pclk",
"mout_fsys0_bus_user",
CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
21, CLK_IGNORE_UNUSED, 0),
/* Gen3 2L0 */
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_REFCLK,
"gout_fsys0_pcie_gen3_2l0_x1_refclk", "mout_fsys0_pcie_user",
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_REFCLK,
"gout_fsys0_pcie_gen3_2l0_x2_refclk", "mout_fsys0_pcie_user",
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_DBI_ACLK,
"gout_fsys0_pcie_gen3_2l0_x1_dbi_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_MSTR_ACLK,
"gout_fsys0_pcie_gen3_2l0_x1_mstr_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_SLV_ACLK,
"gout_fsys0_pcie_gen3_2l0_x1_slv_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_DBI_ACLK,
"gout_fsys0_pcie_gen3_2l0_x2_dbi_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_MSTR_ACLK,
"gout_fsys0_pcie_gen3_2l0_x2_mstr_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK,
"gout_fsys0_pcie_gen3_2l0_x2_slv_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_2L0_CLK,
"gout_fsys0_pcie_gen3a_2l0_clk", "mout_fsys0_pcie_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_2L0_CLK,
"gout_fsys0_pcie_gen3b_2l0_clk", "mout_fsys0_pcie_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK,
21, 0, 0),
/* Gen3 2L1 */
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_REFCLK,
"gout_fsys0_pcie_gen3_2l1_x1_refclk", "mout_fsys0_pcie_user",
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_REFCLK,
"gout_fsys0_pcie_gen3_2l1_x2_refclk", "mout_fsys0_pcie_user",
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_DBI_ACLK,
"gout_fsys0_pcie_gen3_2l1_x1_dbi_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_MSTR_ACLK,
"gout_fsys0_pcie_gen3_2l1_x1_mstr_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK,
"gout_fsys0_pcie_gen3_2l1_x1_slv_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK,
"gout_fsys0_pcie_gen3_2l1_x2_dbi_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_MSTR_ACLK,
"gout_fsys0_pcie_gen3_2l1_x2_mstr_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK,
"gout_fsys0_pcie_gen3_2l1_x2_slv_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_2L1_CLK,
"gout_fsys0_pcie_gen3a_2l1_clk", "mout_fsys0_pcie_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_2L1_CLK,
"gout_fsys0_pcie_gen3b_2l1_clk", "mout_fsys0_pcie_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK,
21, 0, 0),
/* Gen3 4L */
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_REFCLK,
"gout_fsys0_pcie_gen3_4l_x2_refclk", "mout_fsys0_pcie_user",
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_REFCLK,
"gout_fsys0_pcie_gen3_4l_x4_refclk", "mout_fsys0_pcie_user",
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_DBI_ACLK,
"gout_fsys0_pcie_gen3_4l_x2_dbi_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_MSTR_ACLK,
"gout_fsys0_pcie_gen3_4l_x2_mstr_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK,
"gout_fsys0_pcie_gen3_4l_x2_slv_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_DBI_ACLK,
"gout_fsys0_pcie_gen3_4l_x4_dbi_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_MSTR_ACLK,
"gout_fsys0_pcie_gen3_4l_x4_mstr_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_SLV_ACLK,
"gout_fsys0_pcie_gen3_4l_x4_slv_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK,
"gout_fsys0_pcie_gen3a_4l_clk", "mout_fsys0_pcie_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK,
"gout_fsys0_pcie_gen3b_4l_clk", "mout_fsys0_pcie_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK,
21, 0, 0),
};
static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
.mux_clks = fsys0_mux_clks,
.nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
.gate_clks = fsys0_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
.nr_clk_ids = CLKS_NR_FSYS0,
.clk_regs = fsys0_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
.clk_name = "dout_clkcmu_fsys0_bus",
};
/* ---- CMU_FSYS1 ---------------------------------------------------------- */
/* Register Offset definitions for CMU_FSYS1 (0x17040000) */
#define PLL_LOCKTIME_PLL_MMC 0x0000
#define PLL_CON0_PLL_MMC 0x0100
#define PLL_CON3_PLL_MMC 0x010c
#define PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER 0x0600
#define PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER 0x0610
#define PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER 0x0620
#define CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD 0x1000
#define CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD 0x1800
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2018
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x202c
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2028
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40 0x204c
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40 0x2058
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40 0x2064
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40 0x2070
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK 0x2074
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK 0x2078
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK 0x207c
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK 0x2080
static const unsigned long fsys1_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER,
};
static const struct samsung_pll_clock fsys1_pll_clks[] __initconst = {
PLL(pll_0831x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
};
/* List of parent clocks for Muxes in CMU_FSYS1 */
PNAME(mout_fsys1_bus_user_p) = { "oscclk", "dout_clkcmu_fsys1_bus" };
PNAME(mout_fsys1_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
PNAME(mout_fsys1_mmc_card_user_p) = { "oscclk", "gout_clkcmu_fsys1_mmc_card" };
PNAME(mout_fsys1_usbdrd_user_p) = { "oscclk", "dout_clkcmu_fsys1_usbdrd" };
PNAME(mout_fsys1_mmc_card_p) = { "mout_fsys1_mmc_card_user",
"mout_fsys1_mmc_pll" };
static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
MUX(CLK_MOUT_FSYS1_BUS_USER, "mout_fsys1_bus_user",
mout_fsys1_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER, 4, 1),
MUX(CLK_MOUT_FSYS1_MMC_PLL, "mout_fsys1_mmc_pll", mout_fsys1_mmc_pll_p,
PLL_CON0_PLL_MMC, 4, 1),
MUX(CLK_MOUT_FSYS1_MMC_CARD_USER, "mout_fsys1_mmc_card_user",
mout_fsys1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER,
4, 1),
MUX(CLK_MOUT_FSYS1_USBDRD_USER, "mout_fsys1_usbdrd_user",
mout_fsys1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER,
4, 1),
MUX(CLK_MOUT_FSYS1_MMC_CARD, "mout_fsys1_mmc_card",
mout_fsys1_mmc_card_p, CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD,
0, 1),
};
static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
DIV(CLK_DOUT_FSYS1_MMC_CARD, "dout_fsys1_mmc_card",
"mout_fsys1_mmc_card",
CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD, 0, 9),
};
static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
GATE(CLK_GOUT_FSYS1_PCLK, "gout_fsys1_pclk", "mout_fsys1_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN, "gout_fsys1_mmc_card_sdclkin",
"dout_fsys1_mmc_card",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_FSYS1_MMC_CARD_ACLK, "gout_fsys1_mmc_card_aclk",
"dout_fsys1_mmc_card",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS1_USB20DRD_0_REFCLK, "gout_fsys1_usb20drd_0_refclk",
"mout_fsys1_usbdrd_user",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40,
21, 0, 0),
GATE(CLK_GOUT_FSYS1_USB20DRD_1_REFCLK, "gout_fsys1_usb20drd_1_refclk",
"mout_fsys1_usbdrd_user",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40,
21, 0, 0),
GATE(CLK_GOUT_FSYS1_USB30DRD_0_REFCLK, "gout_fsys1_usb30drd_0_refclk",
"mout_fsys1_usbdrd_user",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40,
21, 0, 0),
GATE(CLK_GOUT_FSYS1_USB30DRD_1_REFCLK, "gout_fsys1_usb30drd_1_refclk",
"mout_fsys1_usbdrd_user",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40,
21, 0, 0),
GATE(CLK_GOUT_FSYS1_USB20_0_ACLK, "gout_fsys1_usb20_0_aclk",
"mout_fsys1_usbdrd_user",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS1_USB20_1_ACLK, "gout_fsys1_usb20_1_aclk",
"mout_fsys1_usbdrd_user",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS1_USB30_0_ACLK, "gout_fsys1_usb30_0_aclk",
"mout_fsys1_usbdrd_user",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS1_USB30_1_ACLK, "gout_fsys1_usb30_1_aclk",
"mout_fsys1_usbdrd_user",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK,
21, 0, 0),
};
static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
.pll_clks = fsys1_pll_clks,
.nr_pll_clks = ARRAY_SIZE(fsys1_pll_clks),
.mux_clks = fsys1_mux_clks,
.nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
.div_clks = fsys1_div_clks,
.nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
.gate_clks = fsys1_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
.nr_clk_ids = CLKS_NR_FSYS1,
.clk_regs = fsys1_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
.clk_name = "dout_clkcmu_fsys1_bus",
};
/* ---- CMU_FSYS2 ---------------------------------------------------------- */
/* Register Offset definitions for CMU_FSYS2 (0x17c00000) */
#define PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER 0x0600
#define PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER 0x0620
#define PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER 0x0610
#define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK 0x2098
#define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO 0x209c
#define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK 0x20a4
#define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO 0x20a8
static const unsigned long fsys2_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER,
PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER,
PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER,
CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO,
CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO,
};
/* List of parent clocks for Muxes in CMU_FSYS2 */
PNAME(mout_fsys2_bus_user_p) = { "oscclk", "dout_clkcmu_fsys2_bus" };
PNAME(mout_fsys2_ufs_embd_user_p) = { "oscclk", "dout_clkcmu_fsys2_ufs_embd" };
PNAME(mout_fsys2_ethernet_user_p) = { "oscclk", "dout_clkcmu_fsys2_ethernet" };
static const struct samsung_mux_clock fsys2_mux_clks[] __initconst = {
MUX(CLK_MOUT_FSYS2_BUS_USER, "mout_fsys2_bus_user",
mout_fsys2_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER, 4, 1),
MUX(CLK_MOUT_FSYS2_UFS_EMBD_USER, "mout_fsys2_ufs_embd_user",
mout_fsys2_ufs_embd_user_p,
PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER, 4, 1),
MUX(CLK_MOUT_FSYS2_ETHERNET_USER, "mout_fsys2_ethernet_user",
mout_fsys2_ethernet_user_p,
PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER, 4, 1),
};
static const struct samsung_gate_clock fsys2_gate_clks[] __initconst = {
GATE(CLK_GOUT_FSYS2_UFS_EMBD0_ACLK, "gout_fsys2_ufs_embd0_aclk",
"mout_fsys2_ufs_embd_user",
CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK, 21,
0, 0),
GATE(CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO, "gout_fsys2_ufs_embd0_unipro",
"mout_fsys2_ufs_embd_user",
CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO,
21, 0, 0),
GATE(CLK_GOUT_FSYS2_UFS_EMBD1_ACLK, "gout_fsys2_ufs_embd1_aclk",
"mout_fsys2_ufs_embd_user",
CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK, 21,
0, 0),
GATE(CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO, "gout_fsys2_ufs_embd1_unipro",
"mout_fsys2_ufs_embd_user",
CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO,
21, 0, 0),
};
static const struct samsung_cmu_info fsys2_cmu_info __initconst = {
.mux_clks = fsys2_mux_clks,
.nr_mux_clks = ARRAY_SIZE(fsys2_mux_clks),
.gate_clks = fsys2_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys2_gate_clks),
.nr_clk_ids = CLKS_NR_FSYS2,
.clk_regs = fsys2_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys2_clk_regs),
.clk_name = "dout_clkcmu_fsys2_bus",
};
/* ---- CMU_PERIC0 --------------------------------------------------------- */
/* Register Offset definitions for CMU_PERIC0 (0x10200000) */
#define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600
#define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER 0x0610
#define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI 0x1000
#define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI 0x1004
#define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI 0x1008
#define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI 0x100c
#define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI 0x1010
#define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI 0x1014
#define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C 0x1018
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1800
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1804
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x1808
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x180c
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1810
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1814
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1818
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x2014
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2018
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x2024
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2028
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x202c
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2030
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x2034
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2038
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x203c
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2040
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x201c
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2020
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x2044
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2048
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x2058
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x205c
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2060
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2064
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x2068
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x206c
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2070
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2074
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x204c
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2050
static const unsigned long peric0_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,
PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER,
CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI,
CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI,
CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI,
CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI,
CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI,
CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI,
CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C,
CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
};
/* List of parent clocks for Muxes in CMU_PERIC0 */
PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_clkcmu_peric0_bus" };
PNAME(mout_peric0_ip_user_p) = { "oscclk", "dout_clkcmu_peric0_ip" };
PNAME(mout_peric0_usi_p) = { "oscclk", "mout_peric0_ip_user" };
static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user",
mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1),
MUX(CLK_MOUT_PERIC0_IP_USER, "mout_peric0_ip_user",
mout_peric0_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER, 4, 1),
/* USI00 ~ USI05 */
MUX(CLK_MOUT_PERIC0_USI00_USI, "mout_peric0_usi00_usi",
mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 0, 1),
MUX(CLK_MOUT_PERIC0_USI01_USI, "mout_peric0_usi01_usi",
mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 0, 1),
MUX(CLK_MOUT_PERIC0_USI02_USI, "mout_peric0_usi02_usi",
mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 0, 1),
MUX(CLK_MOUT_PERIC0_USI03_USI, "mout_peric0_usi03_usi",
mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 0, 1),
MUX(CLK_MOUT_PERIC0_USI04_USI, "mout_peric0_usi04_usi",
mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 0, 1),
MUX(CLK_MOUT_PERIC0_USI05_USI, "mout_peric0_usi05_usi",
mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 0, 1),
/* USI_I2C */
MUX(CLK_MOUT_PERIC0_USI_I2C, "mout_peric0_usi_i2c",
mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 0, 1),
};
static const struct samsung_div_clock peric0_div_clks[] __initconst = {
/* USI00 ~ USI05 */
DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi",
"mout_peric0_usi00_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
0, 4),
DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi",
"mout_peric0_usi01_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
0, 4),
DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi",
"mout_peric0_usi02_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
0, 4),
DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi",
"mout_peric0_usi03_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
0, 4),
DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi",
"mout_peric0_usi04_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
0, 4),
DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi",
"mout_peric0_usi05_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
0, 4),
/* USI_I2C */
DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c",
"mout_peric0_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4),
};
static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
/* IPCLK */
GATE(CLK_GOUT_PERIC0_IPCLK_0, "gout_peric0_ipclk_0",
"dout_peric0_usi00_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_IPCLK_1, "gout_peric0_ipclk_1",
"dout_peric0_usi_i2c",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_IPCLK_2, "gout_peric0_ipclk_2",
"dout_peric0_usi01_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_IPCLK_3, "gout_peric0_ipclk_3",
"dout_peric0_usi_i2c",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_IPCLK_4, "gout_peric0_ipclk_4",
"dout_peric0_usi02_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_IPCLK_5, "gout_peric0_ipclk_5",
"dout_peric0_usi_i2c",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_IPCLK_6, "gout_peric0_ipclk_6",
"dout_peric0_usi03_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_IPCLK_7, "gout_peric0_ipclk_7",
"dout_peric0_usi_i2c",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_IPCLK_8, "gout_peric0_ipclk_8",
"dout_peric0_usi04_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_IPCLK_9, "gout_peric0_ipclk_9",
"dout_peric0_usi_i2c",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_IPCLK_10, "gout_peric0_ipclk_10",
"dout_peric0_usi05_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_IPCLK_11, "gout_peric0_ipclk_11",
"dout_peric0_usi_i2c",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
21, 0, 0),
/* PCLK */
GATE(CLK_GOUT_PERIC0_PCLK_0, "gout_peric0_pclk_0",
"mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_PCLK_1, "gout_peric0_pclk_1",
"mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_PCLK_2, "gout_peric0_pclk_2",
"mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_PCLK_3, "gout_peric0_pclk_3",
"mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_PCLK_4, "gout_peric0_pclk_4",
"mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_PCLK_5, "gout_peric0_pclk_5",
"mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_PCLK_6, "gout_peric0_pclk_6",
"mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_PCLK_7, "gout_peric0_pclk_7",
"mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_PCLK_8, "gout_peric0_pclk_8",
"mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_PCLK_9, "gout_peric0_pclk_9",
"mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_PCLK_10, "gout_peric0_pclk_10",
"mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_PCLK_11, "gout_peric0_pclk_11",
"mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
21, 0, 0),
};
static const struct samsung_cmu_info peric0_cmu_info __initconst = {
.mux_clks = peric0_mux_clks,
.nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
.div_clks = peric0_div_clks,
.nr_div_clks = ARRAY_SIZE(peric0_div_clks),
.gate_clks = peric0_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
.nr_clk_ids = CLKS_NR_PERIC0,
.clk_regs = peric0_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
.clk_name = "dout_clkcmu_peric0_bus",
};
/* ---- CMU_PERIC1 --------------------------------------------------------- */
/* Register Offset definitions for CMU_PERIC1 (0x10800000) */
#define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600
#define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER 0x0610
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI 0x1000
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI 0x1004
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI 0x1008
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI 0x100c
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI 0x1010
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI 0x1014
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C 0x1018
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI 0x1800
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI 0x1804
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI 0x1808
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x180c
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1810
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x1814
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x1818
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0 0x2014
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0x2018
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0x2024
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0x2028
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x202c
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0x2030
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0x2034
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7 0x2038
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0x203c
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9 0x2040
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10 0x201c
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11 0x2020
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0 0x2044
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x2048
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2054
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2058
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x205c
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2060
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2064
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7 0x2068
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x206c
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9 0x2070
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10 0x204c
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11 0x2050
static const unsigned long peric1_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,
PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER,
CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI,
CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI,
CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI,
CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI,
CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI,
CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI,
CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C,
CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI,
CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI,
CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI,
CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11,
};
/* List of parent clocks for Muxes in CMU_PERIC1 */
PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_clkcmu_peric1_bus" };
PNAME(mout_peric1_ip_user_p) = { "oscclk", "dout_clkcmu_peric1_ip" };
PNAME(mout_peric1_usi_p) = { "oscclk", "mout_peric1_ip_user" };
static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user",
mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1),
MUX(CLK_MOUT_PERIC1_IP_USER, "mout_peric1_ip_user",
mout_peric1_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 4, 1),
/* USI06 ~ USI11 */
MUX(CLK_MOUT_PERIC1_USI06_USI, "mout_peric1_usi06_usi",
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI, 0, 1),
MUX(CLK_MOUT_PERIC1_USI07_USI, "mout_peric1_usi07_usi",
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI, 0, 1),
MUX(CLK_MOUT_PERIC1_USI08_USI, "mout_peric1_usi08_usi",
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI, 0, 1),
MUX(CLK_MOUT_PERIC1_USI09_USI, "mout_peric1_usi09_usi",
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1),
MUX(CLK_MOUT_PERIC1_USI10_USI, "mout_peric1_usi10_usi",
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1),
MUX(CLK_MOUT_PERIC1_USI11_USI, "mout_peric1_usi11_usi",
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1),
/* USI_I2C */
MUX(CLK_MOUT_PERIC1_USI_I2C, "mout_peric1_usi_i2c",
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1),
};
static const struct samsung_div_clock peric1_div_clks[] __initconst = {
/* USI06 ~ USI11 */
DIV(CLK_DOUT_PERIC1_USI06_USI, "dout_peric1_usi06_usi",
"mout_peric1_usi06_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI07_USI, "dout_peric1_usi07_usi",
"mout_peric1_usi07_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI08_USI, "dout_peric1_usi08_usi",
"mout_peric1_usi08_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi",
"mout_peric1_usi09_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi",
"mout_peric1_usi10_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
0, 4),
DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi",
"mout_peric1_usi11_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
0, 4),
/* USI_I2C */
DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c",
"mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4),
};
static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
/* IPCLK */
GATE(CLK_GOUT_PERIC1_IPCLK_0, "gout_peric1_ipclk_0",
"dout_peric1_usi06_usi",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_IPCLK_1, "gout_peric1_ipclk_1",
"dout_peric1_usi_i2c",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_IPCLK_2, "gout_peric1_ipclk_2",
"dout_peric1_usi07_usi",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_IPCLK_3, "gout_peric1_ipclk_3",
"dout_peric1_usi_i2c",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_IPCLK_4, "gout_peric1_ipclk_4",
"dout_peric1_usi08_usi",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_IPCLK_5, "gout_peric1_ipclk_5",
"dout_peric1_usi_i2c",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_IPCLK_6, "gout_peric1_ipclk_6",
"dout_peric1_usi09_usi",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_IPCLK_7, "gout_peric1_ipclk_7",
"dout_peric1_usi_i2c",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_IPCLK_8, "gout_peric1_ipclk_8",
"dout_peric1_usi10_usi",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_IPCLK_9, "gout_peric1_ipclk_9",
"dout_peric1_usi_i2c",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_IPCLK_10, "gout_peric1_ipclk_10",
"dout_peric1_usi11_usi",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_IPCLK_11, "gout_peric1_ipclk_11",
"dout_peric1_usi_i2c",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11,
21, 0, 0),
/* PCLK */
GATE(CLK_GOUT_PERIC1_PCLK_0, "gout_peric1_pclk_0",
"mout_peric1_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_PCLK_1, "gout_peric1_pclk_1",
"mout_peric1_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_PCLK_2, "gout_peric1_pclk_2",
"mout_peric1_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_PCLK_3, "gout_peric1_pclk_3",
"mout_peric1_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_PCLK_4, "gout_peric1_pclk_4",
"mout_peric1_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_PCLK_5, "gout_peric1_pclk_5",
"mout_peric1_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_PCLK_6, "gout_peric1_pclk_6",
"mout_peric1_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_PCLK_7, "gout_peric1_pclk_7",
"mout_peric1_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_PCLK_8, "gout_peric1_pclk_8",
"mout_peric1_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_PCLK_9, "gout_peric1_pclk_9",
"mout_peric1_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_PCLK_10, "gout_peric1_pclk_10",
"mout_peric1_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_PCLK_11, "gout_peric1_pclk_11",
"mout_peric1_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11,
21, 0, 0),
};
static const struct samsung_cmu_info peric1_cmu_info __initconst = {
.mux_clks = peric1_mux_clks,
.nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
.div_clks = peric1_div_clks,
.nr_div_clks = ARRAY_SIZE(peric1_div_clks),
.gate_clks = peric1_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
.nr_clk_ids = CLKS_NR_PERIC1,
.clk_regs = peric1_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
.clk_name = "dout_clkcmu_peric1_bus",
};
/* ---- CMU_PERIS ---------------------------------------------------------- */
/* Register Offset definitions for CMU_PERIS (0x10020000) */
#define PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER 0x0600
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK 0x2058
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x205c
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x2060
static const unsigned long peris_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER,
CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
};
/* List of parent clocks for Muxes in CMU_PERIS */
PNAME(mout_peris_bus_user_p) = { "oscclk", "dout_clkcmu_peris_bus" };
static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
MUX(CLK_MOUT_PERIS_BUS_USER, "mout_peris_bus_user",
mout_peris_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER, 4, 1),
};
static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
GATE(CLK_GOUT_SYSREG_PERIS_PCLK, "gout_sysreg_peris_pclk",
"mout_peris_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_WDT_CLUSTER0, "gout_wdt_cluster0", "mout_peris_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_WDT_CLUSTER1, "gout_wdt_cluster1", "mout_peris_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
21, 0, 0),
};
static const struct samsung_cmu_info peris_cmu_info __initconst = {
.mux_clks = peris_mux_clks,
.nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
.gate_clks = peris_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
.nr_clk_ids = CLKS_NR_PERIS,
.clk_regs = peris_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
.clk_name = "dout_clkcmu_peris_bus",
};
static int __init exynosautov9_cmu_probe(struct platform_device *pdev)
{
const struct samsung_cmu_info *info;
struct device *dev = &pdev->dev;
info = of_device_get_match_data(dev);
exynos_arm64_register_cmu(dev, dev->of_node, info);
return 0;
}
static const struct of_device_id exynosautov9_cmu_of_match[] = {
{
.compatible = "samsung,exynosautov9-cmu-busmc",
.data = &busmc_cmu_info,
}, {
.compatible = "samsung,exynosautov9-cmu-core",
.data = &core_cmu_info,
}, {
.compatible = "samsung,exynosautov9-cmu-fsys0",
.data = &fsys0_cmu_info,
}, {
.compatible = "samsung,exynosautov9-cmu-fsys1",
.data = &fsys1_cmu_info,
}, {
.compatible = "samsung,exynosautov9-cmu-fsys2",
.data = &fsys2_cmu_info,
}, {
.compatible = "samsung,exynosautov9-cmu-peric0",
.data = &peric0_cmu_info,
}, {
.compatible = "samsung,exynosautov9-cmu-peric1",
.data = &peric1_cmu_info,
}, {
.compatible = "samsung,exynosautov9-cmu-peris",
.data = &peris_cmu_info,
}, {
},
};
static struct platform_driver exynosautov9_cmu_driver __refdata = {
.driver = {
.name = "exynosautov9-cmu",
.of_match_table = exynosautov9_cmu_of_match,
.suppress_bind_attrs = true,
},
.probe = exynosautov9_cmu_probe,
};
static int __init exynosautov9_cmu_init(void)
{
return platform_driver_register(&exynosautov9_cmu_driver);
}
core_initcall(exynosautov9_cmu_init);
| linux-master | drivers/clk/samsung/clk-exynosautov9.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Author: Thomas Abraham <[email protected]>
*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* Bartlomiej Zolnierkiewicz <[email protected]>
*
* This file contains the utility function to register CPU clock for Samsung
* Exynos platforms. A CPU clock is defined as a clock supplied to a CPU or a
* group of CPUs. The CPU clock is typically derived from a hierarchy of clock
* blocks which includes mux and divider blocks. There are a number of other
* auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
* clock for CPU domain. The rates of these auxiliary clocks are related to the
* CPU clock rate and this relation is usually specified in the hardware manual
* of the SoC or supplied after the SoC characterization.
*
* The below implementation of the CPU clock allows the rate changes of the CPU
* clock and the corresponding rate changes of the auxillary clocks of the CPU
* domain. The platform clock driver provides a clock register configuration
* for each configurable rate which is then used to program the clock hardware
* registers to acheive a fast co-oridinated rate change for all the CPU domain
* clocks.
*
* On a rate change request for the CPU clock, the rate change is propagated
* upto the PLL supplying the clock to the CPU domain clock blocks. While the
* CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
* alternate clock source. If required, the alternate clock source is divided
* down in order to keep the output clock rate within the previous OPP limits.
*/
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include "clk-cpu.h"
#define E4210_SRC_CPU 0x0
#define E4210_STAT_CPU 0x200
#define E4210_DIV_CPU0 0x300
#define E4210_DIV_CPU1 0x304
#define E4210_DIV_STAT_CPU0 0x400
#define E4210_DIV_STAT_CPU1 0x404
#define E5433_MUX_SEL2 0x008
#define E5433_MUX_STAT2 0x208
#define E5433_DIV_CPU0 0x400
#define E5433_DIV_CPU1 0x404
#define E5433_DIV_STAT_CPU0 0x500
#define E5433_DIV_STAT_CPU1 0x504
#define E4210_DIV0_RATIO0_MASK 0x7
#define E4210_DIV1_HPM_MASK (0x7 << 4)
#define E4210_DIV1_COPY_MASK (0x7 << 0)
#define E4210_MUX_HPM_MASK (1 << 20)
#define E4210_DIV0_ATB_SHIFT 16
#define E4210_DIV0_ATB_MASK (DIV_MASK << E4210_DIV0_ATB_SHIFT)
#define MAX_DIV 8
#define DIV_MASK 7
#define DIV_MASK_ALL 0xffffffff
#define MUX_MASK 7
/*
* Helper function to wait until divider(s) have stabilized after the divider
* value has changed.
*/
static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask)
{
unsigned long timeout = jiffies + msecs_to_jiffies(10);
do {
if (!(readl(div_reg) & mask))
return;
} while (time_before(jiffies, timeout));
if (!(readl(div_reg) & mask))
return;
pr_err("%s: timeout in divider stablization\n", __func__);
}
/*
* Helper function to wait until mux has stabilized after the mux selection
* value was changed.
*/
static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
unsigned long mux_value)
{
unsigned long timeout = jiffies + msecs_to_jiffies(10);
do {
if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)
return;
} while (time_before(jiffies, timeout));
if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)
return;
pr_err("%s: re-parenting mux timed-out\n", __func__);
}
/* common round rate callback useable for all types of CPU clocks */
static long exynos_cpuclk_round_rate(struct clk_hw *hw,
unsigned long drate, unsigned long *prate)
{
struct clk_hw *parent = clk_hw_get_parent(hw);
*prate = clk_hw_round_rate(parent, drate);
return *prate;
}
/* common recalc rate callback useable for all types of CPU clocks */
static unsigned long exynos_cpuclk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
/*
* The CPU clock output (armclk) rate is the same as its parent
* rate. Although there exist certain dividers inside the CPU
* clock block that could be used to divide the parent clock,
* the driver does not make use of them currently, except during
* frequency transitions.
*/
return parent_rate;
}
static const struct clk_ops exynos_cpuclk_clk_ops = {
.recalc_rate = exynos_cpuclk_recalc_rate,
.round_rate = exynos_cpuclk_round_rate,
};
/*
* Helper function to set the 'safe' dividers for the CPU clock. The parameters
* div and mask contain the divider value and the register bit mask of the
* dividers to be programmed.
*/
static void exynos_set_safe_div(void __iomem *base, unsigned long div,
unsigned long mask)
{
unsigned long div0;
div0 = readl(base + E4210_DIV_CPU0);
div0 = (div0 & ~mask) | (div & mask);
writel(div0, base + E4210_DIV_CPU0);
wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, mask);
}
/* handler for pre-rate change notification from parent clock */
static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
struct exynos_cpuclk *cpuclk, void __iomem *base)
{
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
unsigned long div0, div1 = 0, mux_reg;
unsigned long flags;
/* find out the divider values to use for clock data */
while ((cfg_data->prate * 1000) != ndata->new_rate) {
if (cfg_data->prate == 0)
return -EINVAL;
cfg_data++;
}
spin_lock_irqsave(cpuclk->lock, flags);
/*
* For the selected PLL clock frequency, get the pre-defined divider
* values. If the clock for sclk_hpm is not sourced from apll, then
* the values for DIV_COPY and DIV_HPM dividers need not be set.
*/
div0 = cfg_data->div0;
if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
div1 = cfg_data->div1;
if (readl(base + E4210_SRC_CPU) & E4210_MUX_HPM_MASK)
div1 = readl(base + E4210_DIV_CPU1) &
(E4210_DIV1_HPM_MASK | E4210_DIV1_COPY_MASK);
}
/*
* If the old parent clock speed is less than the clock speed of
* the alternate parent, then it should be ensured that at no point
* the armclk speed is more than the old_prate until the dividers are
* set. Also workaround the issue of the dividers being set to lower
* values before the parent clock speed is set to new lower speed
* (this can result in too high speed of armclk output clocks).
*/
if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
WARN_ON(alt_div >= MAX_DIV);
if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
/*
* In Exynos4210, ATB clock parent is also mout_core. So
* ATB clock also needs to be mantained at safe speed.
*/
alt_div |= E4210_DIV0_ATB_MASK;
alt_div_mask |= E4210_DIV0_ATB_MASK;
}
exynos_set_safe_div(base, alt_div, alt_div_mask);
div0 |= alt_div;
}
/* select sclk_mpll as the alternate parent */
mux_reg = readl(base + E4210_SRC_CPU);
writel(mux_reg | (1 << 16), base + E4210_SRC_CPU);
wait_until_mux_stable(base + E4210_STAT_CPU, 16, 2);
/* alternate parent is active now. set the dividers */
writel(div0, base + E4210_DIV_CPU0);
wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, DIV_MASK_ALL);
if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
writel(div1, base + E4210_DIV_CPU1);
wait_until_divider_stable(base + E4210_DIV_STAT_CPU1,
DIV_MASK_ALL);
}
spin_unlock_irqrestore(cpuclk->lock, flags);
return 0;
}
/* handler for post-rate change notification from parent clock */
static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
struct exynos_cpuclk *cpuclk, void __iomem *base)
{
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
unsigned long div = 0, div_mask = DIV_MASK;
unsigned long mux_reg;
unsigned long flags;
/* find out the divider values to use for clock data */
if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
while ((cfg_data->prate * 1000) != ndata->new_rate) {
if (cfg_data->prate == 0)
return -EINVAL;
cfg_data++;
}
}
spin_lock_irqsave(cpuclk->lock, flags);
/* select mout_apll as the alternate parent */
mux_reg = readl(base + E4210_SRC_CPU);
writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU);
wait_until_mux_stable(base + E4210_STAT_CPU, 16, 1);
if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);
div_mask |= E4210_DIV0_ATB_MASK;
}
exynos_set_safe_div(base, div, div_mask);
spin_unlock_irqrestore(cpuclk->lock, flags);
return 0;
}
/*
* Helper function to set the 'safe' dividers for the CPU clock. The parameters
* div and mask contain the divider value and the register bit mask of the
* dividers to be programmed.
*/
static void exynos5433_set_safe_div(void __iomem *base, unsigned long div,
unsigned long mask)
{
unsigned long div0;
div0 = readl(base + E5433_DIV_CPU0);
div0 = (div0 & ~mask) | (div & mask);
writel(div0, base + E5433_DIV_CPU0);
wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, mask);
}
/* handler for pre-rate change notification from parent clock */
static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
struct exynos_cpuclk *cpuclk, void __iomem *base)
{
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
unsigned long div0, div1 = 0, mux_reg;
unsigned long flags;
/* find out the divider values to use for clock data */
while ((cfg_data->prate * 1000) != ndata->new_rate) {
if (cfg_data->prate == 0)
return -EINVAL;
cfg_data++;
}
spin_lock_irqsave(cpuclk->lock, flags);
/*
* For the selected PLL clock frequency, get the pre-defined divider
* values.
*/
div0 = cfg_data->div0;
div1 = cfg_data->div1;
/*
* If the old parent clock speed is less than the clock speed of
* the alternate parent, then it should be ensured that at no point
* the armclk speed is more than the old_prate until the dividers are
* set. Also workaround the issue of the dividers being set to lower
* values before the parent clock speed is set to new lower speed
* (this can result in too high speed of armclk output clocks).
*/
if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
WARN_ON(alt_div >= MAX_DIV);
exynos5433_set_safe_div(base, alt_div, alt_div_mask);
div0 |= alt_div;
}
/* select the alternate parent */
mux_reg = readl(base + E5433_MUX_SEL2);
writel(mux_reg | 1, base + E5433_MUX_SEL2);
wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 2);
/* alternate parent is active now. set the dividers */
writel(div0, base + E5433_DIV_CPU0);
wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, DIV_MASK_ALL);
writel(div1, base + E5433_DIV_CPU1);
wait_until_divider_stable(base + E5433_DIV_STAT_CPU1, DIV_MASK_ALL);
spin_unlock_irqrestore(cpuclk->lock, flags);
return 0;
}
/* handler for post-rate change notification from parent clock */
static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
struct exynos_cpuclk *cpuclk, void __iomem *base)
{
unsigned long div = 0, div_mask = DIV_MASK;
unsigned long mux_reg;
unsigned long flags;
spin_lock_irqsave(cpuclk->lock, flags);
/* select apll as the alternate parent */
mux_reg = readl(base + E5433_MUX_SEL2);
writel(mux_reg & ~1, base + E5433_MUX_SEL2);
wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 1);
exynos5433_set_safe_div(base, div, div_mask);
spin_unlock_irqrestore(cpuclk->lock, flags);
return 0;
}
/*
* This notifier function is called for the pre-rate and post-rate change
* notifications of the parent clock of cpuclk.
*/
static int exynos_cpuclk_notifier_cb(struct notifier_block *nb,
unsigned long event, void *data)
{
struct clk_notifier_data *ndata = data;
struct exynos_cpuclk *cpuclk;
void __iomem *base;
int err = 0;
cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb);
base = cpuclk->ctrl_base;
if (event == PRE_RATE_CHANGE)
err = exynos_cpuclk_pre_rate_change(ndata, cpuclk, base);
else if (event == POST_RATE_CHANGE)
err = exynos_cpuclk_post_rate_change(ndata, cpuclk, base);
return notifier_from_errno(err);
}
/*
* This notifier function is called for the pre-rate and post-rate change
* notifications of the parent clock of cpuclk.
*/
static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb,
unsigned long event, void *data)
{
struct clk_notifier_data *ndata = data;
struct exynos_cpuclk *cpuclk;
void __iomem *base;
int err = 0;
cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb);
base = cpuclk->ctrl_base;
if (event == PRE_RATE_CHANGE)
err = exynos5433_cpuclk_pre_rate_change(ndata, cpuclk, base);
else if (event == POST_RATE_CHANGE)
err = exynos5433_cpuclk_post_rate_change(ndata, cpuclk, base);
return notifier_from_errno(err);
}
/* helper function to register a CPU clock */
static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
unsigned int lookup_id, const char *name,
const struct clk_hw *parent, const struct clk_hw *alt_parent,
unsigned long offset, const struct exynos_cpuclk_cfg_data *cfg,
unsigned long num_cfgs, unsigned long flags)
{
struct exynos_cpuclk *cpuclk;
struct clk_init_data init;
const char *parent_name;
int ret = 0;
if (IS_ERR(parent) || IS_ERR(alt_parent)) {
pr_err("%s: invalid parent clock(s)\n", __func__);
return -EINVAL;
}
cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
if (!cpuclk)
return -ENOMEM;
parent_name = clk_hw_get_name(parent);
init.name = name;
init.flags = CLK_SET_RATE_PARENT;
init.parent_names = &parent_name;
init.num_parents = 1;
init.ops = &exynos_cpuclk_clk_ops;
cpuclk->alt_parent = alt_parent;
cpuclk->hw.init = &init;
cpuclk->ctrl_base = ctx->reg_base + offset;
cpuclk->lock = &ctx->lock;
cpuclk->flags = flags;
if (flags & CLK_CPU_HAS_E5433_REGS_LAYOUT)
cpuclk->clk_nb.notifier_call = exynos5433_cpuclk_notifier_cb;
else
cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
ret = clk_notifier_register(parent->clk, &cpuclk->clk_nb);
if (ret) {
pr_err("%s: failed to register clock notifier for %s\n",
__func__, name);
goto free_cpuclk;
}
cpuclk->cfg = kmemdup(cfg, sizeof(*cfg) * num_cfgs, GFP_KERNEL);
if (!cpuclk->cfg) {
ret = -ENOMEM;
goto unregister_clk_nb;
}
ret = clk_hw_register(NULL, &cpuclk->hw);
if (ret) {
pr_err("%s: could not register cpuclk %s\n", __func__, name);
goto free_cpuclk_data;
}
samsung_clk_add_lookup(ctx, &cpuclk->hw, lookup_id);
return 0;
free_cpuclk_data:
kfree(cpuclk->cfg);
unregister_clk_nb:
clk_notifier_unregister(parent->clk, &cpuclk->clk_nb);
free_cpuclk:
kfree(cpuclk);
return ret;
}
void __init samsung_clk_register_cpu(struct samsung_clk_provider *ctx,
const struct samsung_cpu_clock *list, unsigned int nr_clk)
{
unsigned int idx;
unsigned int num_cfgs;
struct clk_hw **hws = ctx->clk_data.hws;
for (idx = 0; idx < nr_clk; idx++, list++) {
/* find count of configuration rates in cfg */
for (num_cfgs = 0; list->cfg[num_cfgs].prate != 0; )
num_cfgs++;
exynos_register_cpu_clock(ctx, list->id, list->name, hws[list->parent_id],
hws[list->alt_parent_id], list->offset, list->cfg, num_cfgs,
list->flags);
}
}
| linux-master | drivers/clk/samsung/clk-cpu.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com>
*
* Common Clock Framework support for all S3C64xx SoCs.
*/
#include <linux/slab.h>
#include <linux/clk-provider.h>
#include <linux/clk/samsung.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <dt-bindings/clock/samsung,s3c64xx-clock.h>
#include "clk.h"
#include "clk-pll.h"
/* S3C64xx clock controller register offsets. */
#define APLL_LOCK 0x000
#define MPLL_LOCK 0x004
#define EPLL_LOCK 0x008
#define APLL_CON 0x00c
#define MPLL_CON 0x010
#define EPLL_CON0 0x014
#define EPLL_CON1 0x018
#define CLK_SRC 0x01c
#define CLK_DIV0 0x020
#define CLK_DIV1 0x024
#define CLK_DIV2 0x028
#define HCLK_GATE 0x030
#define PCLK_GATE 0x034
#define SCLK_GATE 0x038
#define MEM0_GATE 0x03c
#define CLK_SRC2 0x10c
#define OTHERS 0x900
/* Helper macros to define clock arrays. */
#define FIXED_RATE_CLOCKS(name) \
static struct samsung_fixed_rate_clock name[]
#define MUX_CLOCKS(name) \
static struct samsung_mux_clock name[]
#define DIV_CLOCKS(name) \
static struct samsung_div_clock name[]
#define GATE_CLOCKS(name) \
static struct samsung_gate_clock name[]
/* Helper macros for gate types present on S3C64xx. */
#define GATE_BUS(_id, cname, pname, o, b) \
GATE(_id, cname, pname, o, b, 0, 0)
#define GATE_SCLK(_id, cname, pname, o, b) \
GATE(_id, cname, pname, o, b, CLK_SET_RATE_PARENT, 0)
#define GATE_ON(_id, cname, pname, o, b) \
GATE(_id, cname, pname, o, b, CLK_IGNORE_UNUSED, 0)
static void __iomem *reg_base;
static bool is_s3c6400;
/*
* List of controller registers to be saved and restored during
* a suspend/resume cycle.
*/
static unsigned long s3c64xx_clk_regs[] __initdata = {
APLL_LOCK,
MPLL_LOCK,
EPLL_LOCK,
APLL_CON,
MPLL_CON,
EPLL_CON0,
EPLL_CON1,
CLK_SRC,
CLK_DIV0,
CLK_DIV1,
CLK_DIV2,
HCLK_GATE,
PCLK_GATE,
SCLK_GATE,
};
static unsigned long s3c6410_clk_regs[] __initdata = {
CLK_SRC2,
MEM0_GATE,
};
/* List of parent clocks common for all S3C64xx SoCs. */
PNAME(spi_mmc_p) = { "mout_epll", "dout_mpll", "fin_pll", "clk27m" };
PNAME(uart_p) = { "mout_epll", "dout_mpll" };
PNAME(audio0_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk0",
"pcmcdclk0", "none", "none", "none" };
PNAME(audio1_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk1",
"pcmcdclk0", "none", "none", "none" };
PNAME(mfc_p) = { "hclkx2", "mout_epll" };
PNAME(apll_p) = { "fin_pll", "fout_apll" };
PNAME(mpll_p) = { "fin_pll", "fout_mpll" };
PNAME(epll_p) = { "fin_pll", "fout_epll" };
PNAME(hclkx2_p) = { "mout_mpll", "mout_apll" };
/* S3C6400-specific parent clocks. */
PNAME(scaler_lcd_p6400) = { "mout_epll", "dout_mpll", "none", "none" };
PNAME(irda_p6400) = { "mout_epll", "dout_mpll", "none", "clk48m" };
PNAME(uhost_p6400) = { "clk48m", "mout_epll", "dout_mpll", "none" };
/* S3C6410-specific parent clocks. */
PNAME(clk27_p6410) = { "clk27m", "fin_pll" };
PNAME(scaler_lcd_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "none" };
PNAME(irda_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "clk48m" };
PNAME(uhost_p6410) = { "clk48m", "mout_epll", "dout_mpll", "fin_pll" };
PNAME(audio2_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk2",
"pcmcdclk1", "none", "none", "none" };
/* Fixed rate clocks generated outside the SoC. */
FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_ext_clks) __initdata = {
FRATE(0, "fin_pll", NULL, 0, 0),
FRATE(0, "xusbxti", NULL, 0, 0),
};
/* Fixed rate clocks generated inside the SoC. */
FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_clks) __initdata = {
FRATE(CLK27M, "clk27m", NULL, 0, 27000000),
FRATE(CLK48M, "clk48m", NULL, 0, 48000000),
};
/* List of clock muxes present on all S3C64xx SoCs. */
MUX_CLOCKS(s3c64xx_mux_clks) __initdata = {
MUX_F(0, "mout_syncmux", hclkx2_p, OTHERS, 6, 1, 0, CLK_MUX_READ_ONLY),
MUX(MOUT_APLL, "mout_apll", apll_p, CLK_SRC, 0, 1),
MUX(MOUT_MPLL, "mout_mpll", mpll_p, CLK_SRC, 1, 1),
MUX(MOUT_EPLL, "mout_epll", epll_p, CLK_SRC, 2, 1),
MUX(MOUT_MFC, "mout_mfc", mfc_p, CLK_SRC, 4, 1),
MUX(MOUT_AUDIO0, "mout_audio0", audio0_p, CLK_SRC, 7, 3),
MUX(MOUT_AUDIO1, "mout_audio1", audio1_p, CLK_SRC, 10, 3),
MUX(MOUT_UART, "mout_uart", uart_p, CLK_SRC, 13, 1),
MUX(MOUT_SPI0, "mout_spi0", spi_mmc_p, CLK_SRC, 14, 2),
MUX(MOUT_SPI1, "mout_spi1", spi_mmc_p, CLK_SRC, 16, 2),
MUX(MOUT_MMC0, "mout_mmc0", spi_mmc_p, CLK_SRC, 18, 2),
MUX(MOUT_MMC1, "mout_mmc1", spi_mmc_p, CLK_SRC, 20, 2),
MUX(MOUT_MMC2, "mout_mmc2", spi_mmc_p, CLK_SRC, 22, 2),
};
/* List of clock muxes present on S3C6400. */
MUX_CLOCKS(s3c6400_mux_clks) __initdata = {
MUX(MOUT_UHOST, "mout_uhost", uhost_p6400, CLK_SRC, 5, 2),
MUX(MOUT_IRDA, "mout_irda", irda_p6400, CLK_SRC, 24, 2),
MUX(MOUT_LCD, "mout_lcd", scaler_lcd_p6400, CLK_SRC, 26, 2),
MUX(MOUT_SCALER, "mout_scaler", scaler_lcd_p6400, CLK_SRC, 28, 2),
};
/* List of clock muxes present on S3C6410. */
MUX_CLOCKS(s3c6410_mux_clks) __initdata = {
MUX(MOUT_UHOST, "mout_uhost", uhost_p6410, CLK_SRC, 5, 2),
MUX(MOUT_IRDA, "mout_irda", irda_p6410, CLK_SRC, 24, 2),
MUX(MOUT_LCD, "mout_lcd", scaler_lcd_p6410, CLK_SRC, 26, 2),
MUX(MOUT_SCALER, "mout_scaler", scaler_lcd_p6410, CLK_SRC, 28, 2),
MUX(MOUT_DAC27, "mout_dac27", clk27_p6410, CLK_SRC, 30, 1),
MUX(MOUT_TV27, "mout_tv27", clk27_p6410, CLK_SRC, 31, 1),
MUX(MOUT_AUDIO2, "mout_audio2", audio2_p6410, CLK_SRC2, 0, 3),
};
/* List of clock dividers present on all S3C64xx SoCs. */
DIV_CLOCKS(s3c64xx_div_clks) __initdata = {
DIV(DOUT_MPLL, "dout_mpll", "mout_mpll", CLK_DIV0, 4, 1),
DIV(HCLKX2, "hclkx2", "mout_syncmux", CLK_DIV0, 9, 3),
DIV(HCLK, "hclk", "hclkx2", CLK_DIV0, 8, 1),
DIV(PCLK, "pclk", "hclkx2", CLK_DIV0, 12, 4),
DIV(DOUT_SECUR, "dout_secur", "hclkx2", CLK_DIV0, 18, 2),
DIV(DOUT_CAM, "dout_cam", "hclkx2", CLK_DIV0, 20, 4),
DIV(DOUT_JPEG, "dout_jpeg", "hclkx2", CLK_DIV0, 24, 4),
DIV(DOUT_MFC, "dout_mfc", "mout_mfc", CLK_DIV0, 28, 4),
DIV(DOUT_MMC0, "dout_mmc0", "mout_mmc0", CLK_DIV1, 0, 4),
DIV(DOUT_MMC1, "dout_mmc1", "mout_mmc1", CLK_DIV1, 4, 4),
DIV(DOUT_MMC2, "dout_mmc2", "mout_mmc2", CLK_DIV1, 8, 4),
DIV(DOUT_LCD, "dout_lcd", "mout_lcd", CLK_DIV1, 12, 4),
DIV(DOUT_SCALER, "dout_scaler", "mout_scaler", CLK_DIV1, 16, 4),
DIV(DOUT_UHOST, "dout_uhost", "mout_uhost", CLK_DIV1, 20, 4),
DIV(DOUT_SPI0, "dout_spi0", "mout_spi0", CLK_DIV2, 0, 4),
DIV(DOUT_SPI1, "dout_spi1", "mout_spi1", CLK_DIV2, 4, 4),
DIV(DOUT_AUDIO0, "dout_audio0", "mout_audio0", CLK_DIV2, 8, 4),
DIV(DOUT_AUDIO1, "dout_audio1", "mout_audio1", CLK_DIV2, 12, 4),
DIV(DOUT_UART, "dout_uart", "mout_uart", CLK_DIV2, 16, 4),
DIV(DOUT_IRDA, "dout_irda", "mout_irda", CLK_DIV2, 20, 4),
};
/* List of clock dividers present on S3C6400. */
DIV_CLOCKS(s3c6400_div_clks) __initdata = {
DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 3),
};
/* List of clock dividers present on S3C6410. */
DIV_CLOCKS(s3c6410_div_clks) __initdata = {
DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 4),
DIV(DOUT_FIMC, "dout_fimc", "hclk", CLK_DIV1, 24, 4),
DIV(DOUT_AUDIO2, "dout_audio2", "mout_audio2", CLK_DIV2, 24, 4),
};
/* List of clock gates present on all S3C64xx SoCs. */
GATE_CLOCKS(s3c64xx_gate_clks) __initdata = {
GATE_BUS(HCLK_UHOST, "hclk_uhost", "hclk", HCLK_GATE, 29),
GATE_BUS(HCLK_SECUR, "hclk_secur", "hclk", HCLK_GATE, 28),
GATE_BUS(HCLK_SDMA1, "hclk_sdma1", "hclk", HCLK_GATE, 27),
GATE_BUS(HCLK_SDMA0, "hclk_sdma0", "hclk", HCLK_GATE, 26),
GATE_ON(HCLK_DDR1, "hclk_ddr1", "hclk", HCLK_GATE, 24),
GATE_BUS(HCLK_USB, "hclk_usb", "hclk", HCLK_GATE, 20),
GATE_BUS(HCLK_HSMMC2, "hclk_hsmmc2", "hclk", HCLK_GATE, 19),
GATE_BUS(HCLK_HSMMC1, "hclk_hsmmc1", "hclk", HCLK_GATE, 18),
GATE_BUS(HCLK_HSMMC0, "hclk_hsmmc0", "hclk", HCLK_GATE, 17),
GATE_BUS(HCLK_MDP, "hclk_mdp", "hclk", HCLK_GATE, 16),
GATE_BUS(HCLK_DHOST, "hclk_dhost", "hclk", HCLK_GATE, 15),
GATE_BUS(HCLK_IHOST, "hclk_ihost", "hclk", HCLK_GATE, 14),
GATE_BUS(HCLK_DMA1, "hclk_dma1", "hclk", HCLK_GATE, 13),
GATE_BUS(HCLK_DMA0, "hclk_dma0", "hclk", HCLK_GATE, 12),
GATE_BUS(HCLK_JPEG, "hclk_jpeg", "hclk", HCLK_GATE, 11),
GATE_BUS(HCLK_CAMIF, "hclk_camif", "hclk", HCLK_GATE, 10),
GATE_BUS(HCLK_SCALER, "hclk_scaler", "hclk", HCLK_GATE, 9),
GATE_BUS(HCLK_2D, "hclk_2d", "hclk", HCLK_GATE, 8),
GATE_BUS(HCLK_TV, "hclk_tv", "hclk", HCLK_GATE, 7),
GATE_BUS(HCLK_POST0, "hclk_post0", "hclk", HCLK_GATE, 5),
GATE_BUS(HCLK_ROT, "hclk_rot", "hclk", HCLK_GATE, 4),
GATE_BUS(HCLK_LCD, "hclk_lcd", "hclk", HCLK_GATE, 3),
GATE_BUS(HCLK_TZIC, "hclk_tzic", "hclk", HCLK_GATE, 2),
GATE_ON(HCLK_INTC, "hclk_intc", "hclk", HCLK_GATE, 1),
GATE_ON(PCLK_SKEY, "pclk_skey", "pclk", PCLK_GATE, 24),
GATE_ON(PCLK_CHIPID, "pclk_chipid", "pclk", PCLK_GATE, 23),
GATE_BUS(PCLK_SPI1, "pclk_spi1", "pclk", PCLK_GATE, 22),
GATE_BUS(PCLK_SPI0, "pclk_spi0", "pclk", PCLK_GATE, 21),
GATE_BUS(PCLK_HSIRX, "pclk_hsirx", "pclk", PCLK_GATE, 20),
GATE_BUS(PCLK_HSITX, "pclk_hsitx", "pclk", PCLK_GATE, 19),
GATE_ON(PCLK_GPIO, "pclk_gpio", "pclk", PCLK_GATE, 18),
GATE_BUS(PCLK_IIC0, "pclk_iic0", "pclk", PCLK_GATE, 17),
GATE_BUS(PCLK_IIS1, "pclk_iis1", "pclk", PCLK_GATE, 16),
GATE_BUS(PCLK_IIS0, "pclk_iis0", "pclk", PCLK_GATE, 15),
GATE_BUS(PCLK_AC97, "pclk_ac97", "pclk", PCLK_GATE, 14),
GATE_BUS(PCLK_TZPC, "pclk_tzpc", "pclk", PCLK_GATE, 13),
GATE_BUS(PCLK_TSADC, "pclk_tsadc", "pclk", PCLK_GATE, 12),
GATE_BUS(PCLK_KEYPAD, "pclk_keypad", "pclk", PCLK_GATE, 11),
GATE_BUS(PCLK_IRDA, "pclk_irda", "pclk", PCLK_GATE, 10),
GATE_BUS(PCLK_PCM1, "pclk_pcm1", "pclk", PCLK_GATE, 9),
GATE_BUS(PCLK_PCM0, "pclk_pcm0", "pclk", PCLK_GATE, 8),
GATE_BUS(PCLK_PWM, "pclk_pwm", "pclk", PCLK_GATE, 7),
GATE_BUS(PCLK_RTC, "pclk_rtc", "pclk", PCLK_GATE, 6),
GATE_BUS(PCLK_WDT, "pclk_wdt", "pclk", PCLK_GATE, 5),
GATE_BUS(PCLK_UART3, "pclk_uart3", "pclk", PCLK_GATE, 4),
GATE_BUS(PCLK_UART2, "pclk_uart2", "pclk", PCLK_GATE, 3),
GATE_BUS(PCLK_UART1, "pclk_uart1", "pclk", PCLK_GATE, 2),
GATE_BUS(PCLK_UART0, "pclk_uart0", "pclk", PCLK_GATE, 1),
GATE_BUS(PCLK_MFC, "pclk_mfc", "pclk", PCLK_GATE, 0),
GATE_SCLK(SCLK_UHOST, "sclk_uhost", "dout_uhost", SCLK_GATE, 30),
GATE_SCLK(SCLK_MMC2_48, "sclk_mmc2_48", "clk48m", SCLK_GATE, 29),
GATE_SCLK(SCLK_MMC1_48, "sclk_mmc1_48", "clk48m", SCLK_GATE, 28),
GATE_SCLK(SCLK_MMC0_48, "sclk_mmc0_48", "clk48m", SCLK_GATE, 27),
GATE_SCLK(SCLK_MMC2, "sclk_mmc2", "dout_mmc2", SCLK_GATE, 26),
GATE_SCLK(SCLK_MMC1, "sclk_mmc1", "dout_mmc1", SCLK_GATE, 25),
GATE_SCLK(SCLK_MMC0, "sclk_mmc0", "dout_mmc0", SCLK_GATE, 24),
GATE_SCLK(SCLK_SPI1_48, "sclk_spi1_48", "clk48m", SCLK_GATE, 23),
GATE_SCLK(SCLK_SPI0_48, "sclk_spi0_48", "clk48m", SCLK_GATE, 22),
GATE_SCLK(SCLK_SPI1, "sclk_spi1", "dout_spi1", SCLK_GATE, 21),
GATE_SCLK(SCLK_SPI0, "sclk_spi0", "dout_spi0", SCLK_GATE, 20),
GATE_SCLK(SCLK_DAC27, "sclk_dac27", "mout_dac27", SCLK_GATE, 19),
GATE_SCLK(SCLK_TV27, "sclk_tv27", "mout_tv27", SCLK_GATE, 18),
GATE_SCLK(SCLK_SCALER27, "sclk_scaler27", "clk27m", SCLK_GATE, 17),
GATE_SCLK(SCLK_SCALER, "sclk_scaler", "dout_scaler", SCLK_GATE, 16),
GATE_SCLK(SCLK_LCD27, "sclk_lcd27", "clk27m", SCLK_GATE, 15),
GATE_SCLK(SCLK_LCD, "sclk_lcd", "dout_lcd", SCLK_GATE, 14),
GATE_SCLK(SCLK_POST0_27, "sclk_post0_27", "clk27m", SCLK_GATE, 12),
GATE_SCLK(SCLK_POST0, "sclk_post0", "dout_lcd", SCLK_GATE, 10),
GATE_SCLK(SCLK_AUDIO1, "sclk_audio1", "dout_audio1", SCLK_GATE, 9),
GATE_SCLK(SCLK_AUDIO0, "sclk_audio0", "dout_audio0", SCLK_GATE, 8),
GATE_SCLK(SCLK_SECUR, "sclk_secur", "dout_secur", SCLK_GATE, 7),
GATE_SCLK(SCLK_IRDA, "sclk_irda", "dout_irda", SCLK_GATE, 6),
GATE_SCLK(SCLK_UART, "sclk_uart", "dout_uart", SCLK_GATE, 5),
GATE_SCLK(SCLK_MFC, "sclk_mfc", "dout_mfc", SCLK_GATE, 3),
GATE_SCLK(SCLK_CAM, "sclk_cam", "dout_cam", SCLK_GATE, 2),
GATE_SCLK(SCLK_JPEG, "sclk_jpeg", "dout_jpeg", SCLK_GATE, 1),
};
/* List of clock gates present on S3C6400. */
GATE_CLOCKS(s3c6400_gate_clks) __initdata = {
GATE_ON(HCLK_DDR0, "hclk_ddr0", "hclk", HCLK_GATE, 23),
GATE_SCLK(SCLK_ONENAND, "sclk_onenand", "parent", SCLK_GATE, 4),
};
/* List of clock gates present on S3C6410. */
GATE_CLOCKS(s3c6410_gate_clks) __initdata = {
GATE_BUS(HCLK_3DSE, "hclk_3dse", "hclk", HCLK_GATE, 31),
GATE_ON(HCLK_IROM, "hclk_irom", "hclk", HCLK_GATE, 25),
GATE_ON(HCLK_MEM1, "hclk_mem1", "hclk", HCLK_GATE, 22),
GATE_ON(HCLK_MEM0, "hclk_mem0", "hclk", HCLK_GATE, 21),
GATE_BUS(HCLK_MFC, "hclk_mfc", "hclk", HCLK_GATE, 0),
GATE_BUS(PCLK_IIC1, "pclk_iic1", "pclk", PCLK_GATE, 27),
GATE_BUS(PCLK_IIS2, "pclk_iis2", "pclk", PCLK_GATE, 26),
GATE_SCLK(SCLK_FIMC, "sclk_fimc", "dout_fimc", SCLK_GATE, 13),
GATE_SCLK(SCLK_AUDIO2, "sclk_audio2", "dout_audio2", SCLK_GATE, 11),
GATE_BUS(MEM0_CFCON, "mem0_cfcon", "hclk_mem0", MEM0_GATE, 5),
GATE_BUS(MEM0_ONENAND1, "mem0_onenand1", "hclk_mem0", MEM0_GATE, 4),
GATE_BUS(MEM0_ONENAND0, "mem0_onenand0", "hclk_mem0", MEM0_GATE, 3),
GATE_BUS(MEM0_NFCON, "mem0_nfcon", "hclk_mem0", MEM0_GATE, 2),
GATE_ON(MEM0_SROM, "mem0_srom", "hclk_mem0", MEM0_GATE, 1),
};
/* List of PLL clocks. */
static struct samsung_pll_clock s3c64xx_pll_clks[] __initdata = {
PLL(pll_6552, FOUT_APLL, "fout_apll", "fin_pll",
APLL_LOCK, APLL_CON, NULL),
PLL(pll_6552, FOUT_MPLL, "fout_mpll", "fin_pll",
MPLL_LOCK, MPLL_CON, NULL),
PLL(pll_6553, FOUT_EPLL, "fout_epll", "fin_pll",
EPLL_LOCK, EPLL_CON0, NULL),
};
/* Aliases for common s3c64xx clocks. */
static struct samsung_clock_alias s3c64xx_clock_aliases[] = {
ALIAS(FOUT_APLL, NULL, "fout_apll"),
ALIAS(FOUT_MPLL, NULL, "fout_mpll"),
ALIAS(FOUT_EPLL, NULL, "fout_epll"),
ALIAS(MOUT_EPLL, NULL, "mout_epll"),
ALIAS(DOUT_MPLL, NULL, "dout_mpll"),
ALIAS(HCLKX2, NULL, "hclk2"),
ALIAS(HCLK, NULL, "hclk"),
ALIAS(PCLK, NULL, "pclk"),
ALIAS(PCLK, NULL, "clk_uart_baud2"),
ALIAS(ARMCLK, NULL, "armclk"),
ALIAS(HCLK_UHOST, "s3c2410-ohci", "usb-host"),
ALIAS(HCLK_USB, "s3c-hsotg", "otg"),
ALIAS(HCLK_HSMMC2, "s3c-sdhci.2", "hsmmc"),
ALIAS(HCLK_HSMMC2, "s3c-sdhci.2", "mmc_busclk.0"),
ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "hsmmc"),
ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"),
ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"),
ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"),
ALIAS(HCLK_DMA1, "dma-pl080s.1", "apb_pclk"),
ALIAS(HCLK_DMA0, "dma-pl080s.0", "apb_pclk"),
ALIAS(HCLK_CAMIF, "s3c-camif", "camif"),
ALIAS(HCLK_LCD, "s3c-fb", "lcd"),
ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi"),
ALIAS(PCLK_SPI0, "s3c6410-spi.0", "spi"),
ALIAS(PCLK_IIC0, "s3c2440-i2c.0", "i2c"),
ALIAS(PCLK_IIS1, "samsung-i2s.1", "iis"),
ALIAS(PCLK_IIS0, "samsung-i2s.0", "iis"),
ALIAS(PCLK_AC97, "samsung-ac97", "ac97"),
ALIAS(PCLK_TSADC, "s3c64xx-adc", "adc"),
ALIAS(PCLK_KEYPAD, "samsung-keypad", "keypad"),
ALIAS(PCLK_PCM1, "samsung-pcm.1", "pcm"),
ALIAS(PCLK_PCM0, "samsung-pcm.0", "pcm"),
ALIAS(PCLK_PWM, NULL, "timers"),
ALIAS(PCLK_RTC, "s3c64xx-rtc", "rtc"),
ALIAS(PCLK_WDT, NULL, "watchdog"),
ALIAS(PCLK_UART3, "s3c6400-uart.3", "uart"),
ALIAS(PCLK_UART2, "s3c6400-uart.2", "uart"),
ALIAS(PCLK_UART1, "s3c6400-uart.1", "uart"),
ALIAS(PCLK_UART0, "s3c6400-uart.0", "uart"),
ALIAS(SCLK_UHOST, "s3c2410-ohci", "usb-bus-host"),
ALIAS(SCLK_MMC2, "s3c-sdhci.2", "mmc_busclk.2"),
ALIAS(SCLK_MMC1, "s3c-sdhci.1", "mmc_busclk.2"),
ALIAS(SCLK_MMC0, "s3c-sdhci.0", "mmc_busclk.2"),
ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi_busclk0"),
ALIAS(SCLK_SPI1, "s3c6410-spi.1", "spi_busclk2"),
ALIAS(PCLK_SPI0, "s3c6410-spi.0", "spi_busclk0"),
ALIAS(SCLK_SPI0, "s3c6410-spi.0", "spi_busclk2"),
ALIAS(SCLK_AUDIO1, "samsung-pcm.1", "audio-bus"),
ALIAS(SCLK_AUDIO1, "samsung-i2s.1", "audio-bus"),
ALIAS(SCLK_AUDIO0, "samsung-pcm.0", "audio-bus"),
ALIAS(SCLK_AUDIO0, "samsung-i2s.0", "audio-bus"),
ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
ALIAS(SCLK_CAM, "s3c-camif", "camera"),
};
/* Aliases for s3c6400-specific clocks. */
static struct samsung_clock_alias s3c6400_clock_aliases[] = {
/* Nothing to place here yet. */
};
/* Aliases for s3c6410-specific clocks. */
static struct samsung_clock_alias s3c6410_clock_aliases[] = {
ALIAS(PCLK_IIC1, "s3c2440-i2c.1", "i2c"),
ALIAS(PCLK_IIS2, "samsung-i2s.2", "iis"),
ALIAS(SCLK_FIMC, "s3c-camif", "fimc"),
ALIAS(SCLK_AUDIO2, "samsung-i2s.2", "audio-bus"),
ALIAS(MEM0_SROM, NULL, "srom"),
};
static void __init s3c64xx_clk_register_fixed_ext(
struct samsung_clk_provider *ctx,
unsigned long fin_pll_f,
unsigned long xusbxti_f)
{
s3c64xx_fixed_rate_ext_clks[0].fixed_rate = fin_pll_f;
s3c64xx_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f;
samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_ext_clks,
ARRAY_SIZE(s3c64xx_fixed_rate_ext_clks));
}
/* Register s3c64xx clocks. */
void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
unsigned long xusbxti_f, bool s3c6400,
void __iomem *base)
{
struct samsung_clk_provider *ctx;
struct clk_hw **hws;
reg_base = base;
is_s3c6400 = s3c6400;
if (np) {
reg_base = of_iomap(np, 0);
if (!reg_base)
panic("%s: failed to map registers\n", __func__);
}
ctx = samsung_clk_init(NULL, reg_base, NR_CLKS);
hws = ctx->clk_data.hws;
/* Register external clocks. */
if (!np)
s3c64xx_clk_register_fixed_ext(ctx, xtal_f, xusbxti_f);
/* Register PLLs. */
samsung_clk_register_pll(ctx, s3c64xx_pll_clks,
ARRAY_SIZE(s3c64xx_pll_clks));
/* Register common internal clocks. */
samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_clks,
ARRAY_SIZE(s3c64xx_fixed_rate_clks));
samsung_clk_register_mux(ctx, s3c64xx_mux_clks,
ARRAY_SIZE(s3c64xx_mux_clks));
samsung_clk_register_div(ctx, s3c64xx_div_clks,
ARRAY_SIZE(s3c64xx_div_clks));
samsung_clk_register_gate(ctx, s3c64xx_gate_clks,
ARRAY_SIZE(s3c64xx_gate_clks));
/* Register SoC-specific clocks. */
if (is_s3c6400) {
samsung_clk_register_mux(ctx, s3c6400_mux_clks,
ARRAY_SIZE(s3c6400_mux_clks));
samsung_clk_register_div(ctx, s3c6400_div_clks,
ARRAY_SIZE(s3c6400_div_clks));
samsung_clk_register_gate(ctx, s3c6400_gate_clks,
ARRAY_SIZE(s3c6400_gate_clks));
samsung_clk_register_alias(ctx, s3c6400_clock_aliases,
ARRAY_SIZE(s3c6400_clock_aliases));
} else {
samsung_clk_register_mux(ctx, s3c6410_mux_clks,
ARRAY_SIZE(s3c6410_mux_clks));
samsung_clk_register_div(ctx, s3c6410_div_clks,
ARRAY_SIZE(s3c6410_div_clks));
samsung_clk_register_gate(ctx, s3c6410_gate_clks,
ARRAY_SIZE(s3c6410_gate_clks));
samsung_clk_register_alias(ctx, s3c6410_clock_aliases,
ARRAY_SIZE(s3c6410_clock_aliases));
}
samsung_clk_register_alias(ctx, s3c64xx_clock_aliases,
ARRAY_SIZE(s3c64xx_clock_aliases));
samsung_clk_sleep_init(reg_base, s3c64xx_clk_regs,
ARRAY_SIZE(s3c64xx_clk_regs));
if (!is_s3c6400)
samsung_clk_sleep_init(reg_base, s3c6410_clk_regs,
ARRAY_SIZE(s3c6410_clk_regs));
samsung_clk_of_add_provider(np, ctx);
pr_info("%s clocks: apll = %lu, mpll = %lu\n"
"\tepll = %lu, arm_clk = %lu\n",
is_s3c6400 ? "S3C6400" : "S3C6410",
clk_hw_get_rate(hws[MOUT_APLL]),
clk_hw_get_rate(hws[MOUT_MPLL]),
clk_hw_get_rate(hws[MOUT_EPLL]),
clk_hw_get_rate(hws[ARMCLK]));
}
static void __init s3c6400_clk_init(struct device_node *np)
{
s3c64xx_clk_init(np, 0, 0, true, NULL);
}
CLK_OF_DECLARE(s3c6400_clk, "samsung,s3c6400-clock", s3c6400_clk_init);
static void __init s3c6410_clk_init(struct device_node *np)
{
s3c64xx_clk_init(np, 0, 0, false, NULL);
}
CLK_OF_DECLARE(s3c6410_clk, "samsung,s3c6410-clock", s3c6410_clk_init);
| linux-master | drivers/clk/samsung/clk-s3c64xx.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Author: Rahul Sharma <[email protected]>
*
* Common Clock Framework support for Exynos5260 SoC.
*/
#include <linux/of.h>
#include <linux/of_address.h>
#include "clk-exynos5260.h"
#include "clk.h"
#include "clk-pll.h"
#include <dt-bindings/clock/exynos5260-clk.h>
/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR_TOP (PHYCLK_USBDRD30_UDRD30_PHYCLOCK + 1)
#define CLKS_NR_EGL (EGL_DOUT_EGL1 + 1)
#define CLKS_NR_KFC (KFC_DOUT_KFC1 + 1)
#define CLKS_NR_MIF (MIF_SCLK_LPDDR3PHY_WRAP_U0 + 1)
#define CLKS_NR_G3D (G3D_CLK_G3D + 1)
#define CLKS_NR_AUD (AUD_SCLK_I2S + 1)
#define CLKS_NR_MFC (MFC_CLK_SMMU2_MFCM0 + 1)
#define CLKS_NR_GSCL (GSCL_SCLK_CSIS0_WRAP + 1)
#define CLKS_NR_FSYS (FSYS_PHYCLK_USBHOST20 + 1)
#define CLKS_NR_PERI (PERI_SCLK_PCM1 + 1)
#define CLKS_NR_DISP (DISP_MOUT_HDMI_PHY_PIXEL_USER + 1)
#define CLKS_NR_G2D (G2D_CLK_SMMU3_G2D + 1)
#define CLKS_NR_ISP (ISP_SCLK_UART_EXT + 1)
/*
* Applicable for all 2550 Type PLLS for Exynos5260, listed below
* DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
*/
static const struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initconst = {
PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1),
PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
PLL_35XX_RATE(24 * MHZ, 733000000, 733, 12, 1),
PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),
PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
PLL_35XX_RATE(24 * MHZ, 620000000, 310, 3, 2),
PLL_35XX_RATE(24 * MHZ, 600000000, 400, 4, 2),
PLL_35XX_RATE(24 * MHZ, 543000000, 362, 4, 2),
PLL_35XX_RATE(24 * MHZ, 533000000, 533, 6, 2),
PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2),
PLL_35XX_RATE(24 * MHZ, 450000000, 300, 4, 2),
PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2),
PLL_35XX_RATE(24 * MHZ, 350000000, 175, 3, 2),
PLL_35XX_RATE(24 * MHZ, 300000000, 400, 4, 3),
PLL_35XX_RATE(24 * MHZ, 266000000, 266, 3, 3),
PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
PLL_35XX_RATE(24 * MHZ, 160000000, 160, 3, 3),
};
/*
* Applicable for 2650 Type PLL for AUD_PLL.
*/
static const struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initconst = {
PLL_36XX_RATE(24 * MHZ, 1600000000, 200, 3, 0, 0),
PLL_36XX_RATE(24 * MHZ, 1200000000, 100, 2, 0, 0),
PLL_36XX_RATE(24 * MHZ, 1000000000, 250, 3, 1, 0),
PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1, 0),
PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1, 0),
PLL_36XX_RATE(24 * MHZ, 532000000, 266, 3, 2, 0),
PLL_36XX_RATE(24 * MHZ, 480000000, 160, 2, 2, 0),
PLL_36XX_RATE(24 * MHZ, 432000000, 144, 2, 2, 0),
PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2, 0),
PLL_36XX_RATE(24 * MHZ, 394073128, 459, 7, 2, 49282),
PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2, 0),
PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2, 0),
PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
PLL_36XX_RATE(24 * MHZ, 200000000, 200, 3, 3, 0),
PLL_36XX_RATE(24 * MHZ, 166000000, 166, 3, 3, 0),
PLL_36XX_RATE(24 * MHZ, 133000000, 266, 3, 4, 0),
PLL_36XX_RATE(24 * MHZ, 100000000, 200, 3, 4, 0),
PLL_36XX_RATE(24 * MHZ, 66000000, 176, 2, 5, 0),
};
/* CMU_AUD */
static const unsigned long aud_clk_regs[] __initconst = {
MUX_SEL_AUD,
DIV_AUD0,
DIV_AUD1,
EN_ACLK_AUD,
EN_PCLK_AUD,
EN_SCLK_AUD,
EN_IP_AUD,
};
PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"};
PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user", "ioclk_i2s_cdclk"};
PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user", "ioclk_pcm_extclk"};
static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
MUX(AUD_MOUT_AUD_PLL_USER, "mout_aud_pll_user", mout_aud_pll_user_p,
MUX_SEL_AUD, 0, 1),
MUX(AUD_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p,
MUX_SEL_AUD, 4, 1),
MUX(AUD_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
MUX_SEL_AUD, 8, 1),
};
static const struct samsung_div_clock aud_div_clks[] __initconst = {
DIV(AUD_DOUT_ACLK_AUD_131, "dout_aclk_aud_131", "mout_aud_pll_user",
DIV_AUD0, 0, 4),
DIV(AUD_DOUT_SCLK_AUD_I2S, "dout_sclk_aud_i2s", "mout_sclk_aud_i2s",
DIV_AUD1, 0, 4),
DIV(AUD_DOUT_SCLK_AUD_PCM, "dout_sclk_aud_pcm", "mout_sclk_aud_pcm",
DIV_AUD1, 4, 8),
DIV(AUD_DOUT_SCLK_AUD_UART, "dout_sclk_aud_uart", "mout_aud_pll_user",
DIV_AUD1, 12, 4),
};
static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
GATE(AUD_SCLK_I2S, "sclk_aud_i2s", "dout_sclk_aud_i2s",
EN_SCLK_AUD, 0, CLK_SET_RATE_PARENT, 0),
GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm",
EN_SCLK_AUD, 1, CLK_SET_RATE_PARENT, 0),
GATE(AUD_SCLK_AUD_UART, "sclk_aud_uart", "dout_sclk_aud_uart",
EN_SCLK_AUD, 2, CLK_SET_RATE_PARENT, 0),
GATE(AUD_CLK_SRAMC, "clk_sramc", "dout_aclk_aud_131", EN_IP_AUD,
0, 0, 0),
GATE(AUD_CLK_DMAC, "clk_dmac", "dout_aclk_aud_131",
EN_IP_AUD, 1, 0, 0),
GATE(AUD_CLK_I2S, "clk_i2s", "dout_aclk_aud_131", EN_IP_AUD, 2, 0, 0),
GATE(AUD_CLK_PCM, "clk_pcm", "dout_aclk_aud_131", EN_IP_AUD, 3, 0, 0),
GATE(AUD_CLK_AUD_UART, "clk_aud_uart", "dout_aclk_aud_131",
EN_IP_AUD, 4, 0, 0),
};
static const struct samsung_cmu_info aud_cmu __initconst = {
.mux_clks = aud_mux_clks,
.nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
.div_clks = aud_div_clks,
.nr_div_clks = ARRAY_SIZE(aud_div_clks),
.gate_clks = aud_gate_clks,
.nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
.nr_clk_ids = CLKS_NR_AUD,
.clk_regs = aud_clk_regs,
.nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
};
static void __init exynos5260_clk_aud_init(struct device_node *np)
{
samsung_cmu_register_one(np, &aud_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_aud, "samsung,exynos5260-clock-aud",
exynos5260_clk_aud_init);
/* CMU_DISP */
static const unsigned long disp_clk_regs[] __initconst = {
MUX_SEL_DISP0,
MUX_SEL_DISP1,
MUX_SEL_DISP2,
MUX_SEL_DISP3,
MUX_SEL_DISP4,
DIV_DISP,
EN_ACLK_DISP,
EN_PCLK_DISP,
EN_SCLK_DISP0,
EN_SCLK_DISP1,
EN_IP_DISP,
EN_IP_DISP_BUS,
};
PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p) = {"fin_pll",
"phyclk_dptx_phy_ch3_txd_clk"};
PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p) = {"fin_pll",
"phyclk_dptx_phy_ch2_txd_clk"};
PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p) = {"fin_pll",
"phyclk_dptx_phy_ch1_txd_clk"};
PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p) = {"fin_pll",
"phyclk_dptx_phy_ch0_txd_clk"};
PNAME(mout_aclk_disp_222_user_p) = {"fin_pll", "dout_aclk_disp_222"};
PNAME(mout_sclk_disp_pixel_user_p) = {"fin_pll", "dout_sclk_disp_pixel"};
PNAME(mout_aclk_disp_333_user_p) = {"fin_pll", "dout_aclk_disp_333"};
PNAME(mout_phyclk_hdmi_phy_tmds_clko_user_p) = {"fin_pll",
"phyclk_hdmi_phy_tmds_clko"};
PNAME(mout_phyclk_hdmi_phy_ref_clko_user_p) = {"fin_pll",
"phyclk_hdmi_phy_ref_clko"};
PNAME(mout_phyclk_hdmi_phy_pixel_clko_user_p) = {"fin_pll",
"phyclk_hdmi_phy_pixel_clko"};
PNAME(mout_phyclk_hdmi_link_o_tmds_clkhi_user_p) = {"fin_pll",
"phyclk_hdmi_link_o_tmds_clkhi"};
PNAME(mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p) = {"fin_pll",
"phyclk_mipi_dphy_4l_m_txbyte_clkhs"};
PNAME(mout_phyclk_dptx_phy_o_ref_clk_24m_user_p) = {"fin_pll",
"phyclk_dptx_phy_o_ref_clk_24m"};
PNAME(mout_phyclk_dptx_phy_clk_div2_user_p) = {"fin_pll",
"phyclk_dptx_phy_clk_div2"};
PNAME(mout_sclk_hdmi_pixel_p) = {"mout_sclk_disp_pixel_user",
"mout_aclk_disp_222_user"};
PNAME(mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p) = {"fin_pll",
"phyclk_mipi_dphy_4l_m_rxclkesc0"};
PNAME(mout_sclk_hdmi_spdif_p) = {"fin_pll", "ioclk_spdif_extclk",
"dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
static const struct samsung_mux_clock disp_mux_clks[] __initconst = {
MUX(DISP_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
mout_aclk_disp_333_user_p,
MUX_SEL_DISP0, 0, 1),
MUX(DISP_MOUT_SCLK_DISP_PIXEL_USER, "mout_sclk_disp_pixel_user",
mout_sclk_disp_pixel_user_p,
MUX_SEL_DISP0, 4, 1),
MUX(DISP_MOUT_ACLK_DISP_222_USER, "mout_aclk_disp_222_user",
mout_aclk_disp_222_user_p,
MUX_SEL_DISP0, 8, 1),
MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER,
"mout_phyclk_dptx_phy_ch0_txd_clk_user",
mout_phyclk_dptx_phy_ch0_txd_clk_user_p,
MUX_SEL_DISP0, 16, 1),
MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER,
"mout_phyclk_dptx_phy_ch1_txd_clk_user",
mout_phyclk_dptx_phy_ch1_txd_clk_user_p,
MUX_SEL_DISP0, 20, 1),
MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER,
"mout_phyclk_dptx_phy_ch2_txd_clk_user",
mout_phyclk_dptx_phy_ch2_txd_clk_user_p,
MUX_SEL_DISP0, 24, 1),
MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER,
"mout_phyclk_dptx_phy_ch3_txd_clk_user",
mout_phyclk_dptx_phy_ch3_txd_clk_user_p,
MUX_SEL_DISP0, 28, 1),
MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER,
"mout_phyclk_dptx_phy_clk_div2_user",
mout_phyclk_dptx_phy_clk_div2_user_p,
MUX_SEL_DISP1, 0, 1),
MUX(DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER,
"mout_phyclk_dptx_phy_o_ref_clk_24m_user",
mout_phyclk_dptx_phy_o_ref_clk_24m_user_p,
MUX_SEL_DISP1, 4, 1),
MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS,
"mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs",
mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p,
MUX_SEL_DISP1, 8, 1),
MUX(DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER,
"mout_phyclk_hdmi_link_o_tmds_clkhi_user",
mout_phyclk_hdmi_link_o_tmds_clkhi_user_p,
MUX_SEL_DISP1, 16, 1),
MUX(DISP_MOUT_HDMI_PHY_PIXEL,
"mout_phyclk_hdmi_phy_pixel_clko_user",
mout_phyclk_hdmi_phy_pixel_clko_user_p,
MUX_SEL_DISP1, 20, 1),
MUX(DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER,
"mout_phyclk_hdmi_phy_ref_clko_user",
mout_phyclk_hdmi_phy_ref_clko_user_p,
MUX_SEL_DISP1, 24, 1),
MUX(DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER,
"mout_phyclk_hdmi_phy_tmds_clko_user",
mout_phyclk_hdmi_phy_tmds_clko_user_p,
MUX_SEL_DISP1, 28, 1),
MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER,
"mout_phyclk_mipi_dphy_4lmrxclk_esc0_user",
mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p,
MUX_SEL_DISP2, 0, 1),
MUX(DISP_MOUT_SCLK_HDMI_PIXEL, "mout_sclk_hdmi_pixel",
mout_sclk_hdmi_pixel_p,
MUX_SEL_DISP2, 4, 1),
MUX(DISP_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
mout_sclk_hdmi_spdif_p,
MUX_SEL_DISP4, 4, 2),
};
static const struct samsung_div_clock disp_div_clks[] __initconst = {
DIV(DISP_DOUT_PCLK_DISP_111, "dout_pclk_disp_111",
"mout_aclk_disp_222_user",
DIV_DISP, 8, 4),
DIV(DISP_DOUT_SCLK_FIMD1_EXTCLKPLL, "dout_sclk_fimd1_extclkpll",
"mout_sclk_disp_pixel_user",
DIV_DISP, 12, 4),
DIV(DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI,
"dout_sclk_hdmi_phy_pixel_clki",
"mout_sclk_hdmi_pixel",
DIV_DISP, 16, 4),
};
static const struct samsung_gate_clock disp_gate_clks[] __initconst = {
GATE(DISP_MOUT_HDMI_PHY_PIXEL_USER, "sclk_hdmi_link_i_pixel",
"mout_phyclk_hdmi_phy_pixel_clko_user",
EN_SCLK_DISP0, 26, CLK_SET_RATE_PARENT, 0),
GATE(DISP_SCLK_PIXEL, "sclk_hdmi_phy_pixel_clki",
"dout_sclk_hdmi_phy_pixel_clki",
EN_SCLK_DISP0, 29, CLK_SET_RATE_PARENT, 0),
GATE(DISP_CLK_DP, "clk_dptx_link", "mout_aclk_disp_222_user",
EN_IP_DISP, 4, 0, 0),
GATE(DISP_CLK_DPPHY, "clk_dptx_phy", "mout_aclk_disp_222_user",
EN_IP_DISP, 5, 0, 0),
GATE(DISP_CLK_DSIM1, "clk_dsim1", "mout_aclk_disp_222_user",
EN_IP_DISP, 6, 0, 0),
GATE(DISP_CLK_FIMD1, "clk_fimd1", "mout_aclk_disp_222_user",
EN_IP_DISP, 7, 0, 0),
GATE(DISP_CLK_HDMI, "clk_hdmi", "mout_aclk_disp_222_user",
EN_IP_DISP, 8, 0, 0),
GATE(DISP_CLK_HDMIPHY, "clk_hdmiphy", "mout_aclk_disp_222_user",
EN_IP_DISP, 9, 0, 0),
GATE(DISP_CLK_MIPIPHY, "clk_mipi_dphy", "mout_aclk_disp_222_user",
EN_IP_DISP, 10, 0, 0),
GATE(DISP_CLK_MIXER, "clk_mixer", "mout_aclk_disp_222_user",
EN_IP_DISP, 11, 0, 0),
GATE(DISP_CLK_PIXEL_DISP, "clk_pixel_disp", "mout_aclk_disp_222_user",
EN_IP_DISP, 12, CLK_IGNORE_UNUSED, 0),
GATE(DISP_CLK_PIXEL_MIXER, "clk_pixel_mixer", "mout_aclk_disp_222_user",
EN_IP_DISP, 13, CLK_IGNORE_UNUSED, 0),
GATE(DISP_CLK_SMMU_FIMD1M0, "clk_smmu3_fimd1m0",
"mout_aclk_disp_222_user",
EN_IP_DISP, 22, 0, 0),
GATE(DISP_CLK_SMMU_FIMD1M1, "clk_smmu3_fimd1m1",
"mout_aclk_disp_222_user",
EN_IP_DISP, 23, 0, 0),
GATE(DISP_CLK_SMMU_TV, "clk_smmu3_tv", "mout_aclk_disp_222_user",
EN_IP_DISP, 25, 0, 0),
};
static const struct samsung_cmu_info disp_cmu __initconst = {
.mux_clks = disp_mux_clks,
.nr_mux_clks = ARRAY_SIZE(disp_mux_clks),
.div_clks = disp_div_clks,
.nr_div_clks = ARRAY_SIZE(disp_div_clks),
.gate_clks = disp_gate_clks,
.nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
.nr_clk_ids = CLKS_NR_DISP,
.clk_regs = disp_clk_regs,
.nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
};
static void __init exynos5260_clk_disp_init(struct device_node *np)
{
samsung_cmu_register_one(np, &disp_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_disp, "samsung,exynos5260-clock-disp",
exynos5260_clk_disp_init);
/* CMU_EGL */
static const unsigned long egl_clk_regs[] __initconst = {
EGL_PLL_LOCK,
EGL_PLL_CON0,
EGL_PLL_CON1,
EGL_PLL_FREQ_DET,
MUX_SEL_EGL,
MUX_ENABLE_EGL,
DIV_EGL,
DIV_EGL_PLL_FDET,
EN_ACLK_EGL,
EN_PCLK_EGL,
EN_SCLK_EGL,
};
PNAME(mout_egl_b_p) = {"mout_egl_pll", "dout_bus_pll"};
PNAME(mout_egl_pll_p) = {"fin_pll", "fout_egl_pll"};
static const struct samsung_mux_clock egl_mux_clks[] __initconst = {
MUX(EGL_MOUT_EGL_PLL, "mout_egl_pll", mout_egl_pll_p,
MUX_SEL_EGL, 4, 1),
MUX(EGL_MOUT_EGL_B, "mout_egl_b", mout_egl_b_p, MUX_SEL_EGL, 16, 1),
};
static const struct samsung_div_clock egl_div_clks[] __initconst = {
DIV(EGL_DOUT_EGL1, "dout_egl1", "mout_egl_b", DIV_EGL, 0, 3),
DIV(EGL_DOUT_EGL2, "dout_egl2", "dout_egl1", DIV_EGL, 4, 3),
DIV(EGL_DOUT_ACLK_EGL, "dout_aclk_egl", "dout_egl2", DIV_EGL, 8, 3),
DIV(EGL_DOUT_PCLK_EGL, "dout_pclk_egl", "dout_egl_atclk",
DIV_EGL, 12, 3),
DIV(EGL_DOUT_EGL_ATCLK, "dout_egl_atclk", "dout_egl2", DIV_EGL, 16, 3),
DIV(EGL_DOUT_EGL_PCLK_DBG, "dout_egl_pclk_dbg", "dout_egl_atclk",
DIV_EGL, 20, 3),
DIV(EGL_DOUT_EGL_PLL, "dout_egl_pll", "mout_egl_b", DIV_EGL, 24, 3),
};
static const struct samsung_pll_clock egl_pll_clks[] __initconst = {
PLL(pll_2550xx, EGL_FOUT_EGL_PLL, "fout_egl_pll", "fin_pll",
EGL_PLL_LOCK, EGL_PLL_CON0,
pll2550_24mhz_tbl),
};
static const struct samsung_cmu_info egl_cmu __initconst = {
.pll_clks = egl_pll_clks,
.nr_pll_clks = ARRAY_SIZE(egl_pll_clks),
.mux_clks = egl_mux_clks,
.nr_mux_clks = ARRAY_SIZE(egl_mux_clks),
.div_clks = egl_div_clks,
.nr_div_clks = ARRAY_SIZE(egl_div_clks),
.nr_clk_ids = CLKS_NR_EGL,
.clk_regs = egl_clk_regs,
.nr_clk_regs = ARRAY_SIZE(egl_clk_regs),
};
static void __init exynos5260_clk_egl_init(struct device_node *np)
{
samsung_cmu_register_one(np, &egl_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_egl, "samsung,exynos5260-clock-egl",
exynos5260_clk_egl_init);
/* CMU_FSYS */
static const unsigned long fsys_clk_regs[] __initconst = {
MUX_SEL_FSYS0,
MUX_SEL_FSYS1,
EN_ACLK_FSYS,
EN_ACLK_FSYS_SECURE_RTIC,
EN_ACLK_FSYS_SECURE_SMMU_RTIC,
EN_SCLK_FSYS,
EN_IP_FSYS,
EN_IP_FSYS_SECURE_RTIC,
EN_IP_FSYS_SECURE_SMMU_RTIC,
};
PNAME(mout_phyclk_usbhost20_phyclk_user_p) = {"fin_pll",
"phyclk_usbhost20_phy_phyclock"};
PNAME(mout_phyclk_usbhost20_freeclk_user_p) = {"fin_pll",
"phyclk_usbhost20_phy_freeclk"};
PNAME(mout_phyclk_usbhost20_clk48mohci_user_p) = {"fin_pll",
"phyclk_usbhost20_phy_clk48mohci"};
PNAME(mout_phyclk_usbdrd30_pipe_pclk_user_p) = {"fin_pll",
"phyclk_usbdrd30_udrd30_pipe_pclk"};
PNAME(mout_phyclk_usbdrd30_phyclock_user_p) = {"fin_pll",
"phyclk_usbdrd30_udrd30_phyclock"};
static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
MUX(FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER,
"mout_phyclk_usbdrd30_phyclock_user",
mout_phyclk_usbdrd30_phyclock_user_p,
MUX_SEL_FSYS1, 0, 1),
MUX(FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER,
"mout_phyclk_usbdrd30_pipe_pclk_user",
mout_phyclk_usbdrd30_pipe_pclk_user_p,
MUX_SEL_FSYS1, 4, 1),
MUX(FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER,
"mout_phyclk_usbhost20_clk48mohci_user",
mout_phyclk_usbhost20_clk48mohci_user_p,
MUX_SEL_FSYS1, 8, 1),
MUX(FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER,
"mout_phyclk_usbhost20_freeclk_user",
mout_phyclk_usbhost20_freeclk_user_p,
MUX_SEL_FSYS1, 12, 1),
MUX(FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER,
"mout_phyclk_usbhost20_phyclk_user",
mout_phyclk_usbhost20_phyclk_user_p,
MUX_SEL_FSYS1, 16, 1),
};
static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
GATE(FSYS_PHYCLK_USBHOST20, "phyclk_usbhost20_phyclock",
"mout_phyclk_usbdrd30_phyclock_user",
EN_SCLK_FSYS, 1, 0, 0),
GATE(FSYS_PHYCLK_USBDRD30, "phyclk_usbdrd30_udrd30_phyclock_g",
"mout_phyclk_usbdrd30_phyclock_user",
EN_SCLK_FSYS, 7, 0, 0),
GATE(FSYS_CLK_MMC0, "clk_mmc0", "dout_aclk_fsys_200",
EN_IP_FSYS, 6, 0, 0),
GATE(FSYS_CLK_MMC1, "clk_mmc1", "dout_aclk_fsys_200",
EN_IP_FSYS, 7, 0, 0),
GATE(FSYS_CLK_MMC2, "clk_mmc2", "dout_aclk_fsys_200",
EN_IP_FSYS, 8, 0, 0),
GATE(FSYS_CLK_PDMA, "clk_pdma", "dout_aclk_fsys_200",
EN_IP_FSYS, 9, 0, 0),
GATE(FSYS_CLK_SROMC, "clk_sromc", "dout_aclk_fsys_200",
EN_IP_FSYS, 13, 0, 0),
GATE(FSYS_CLK_USBDRD30, "clk_usbdrd30", "dout_aclk_fsys_200",
EN_IP_FSYS, 14, 0, 0),
GATE(FSYS_CLK_USBHOST20, "clk_usbhost20", "dout_aclk_fsys_200",
EN_IP_FSYS, 15, 0, 0),
GATE(FSYS_CLK_USBLINK, "clk_usblink", "dout_aclk_fsys_200",
EN_IP_FSYS, 18, 0, 0),
GATE(FSYS_CLK_TSI, "clk_tsi", "dout_aclk_fsys_200",
EN_IP_FSYS, 20, 0, 0),
GATE(FSYS_CLK_RTIC, "clk_rtic", "dout_aclk_fsys_200",
EN_IP_FSYS_SECURE_RTIC, 11, 0, 0),
GATE(FSYS_CLK_SMMU_RTIC, "clk_smmu_rtic", "dout_aclk_fsys_200",
EN_IP_FSYS_SECURE_SMMU_RTIC, 12, 0, 0),
};
static const struct samsung_cmu_info fsys_cmu __initconst = {
.mux_clks = fsys_mux_clks,
.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
.gate_clks = fsys_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
.nr_clk_ids = CLKS_NR_FSYS,
.clk_regs = fsys_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
};
static void __init exynos5260_clk_fsys_init(struct device_node *np)
{
samsung_cmu_register_one(np, &fsys_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_fsys, "samsung,exynos5260-clock-fsys",
exynos5260_clk_fsys_init);
/* CMU_G2D */
static const unsigned long g2d_clk_regs[] __initconst = {
MUX_SEL_G2D,
MUX_STAT_G2D,
DIV_G2D,
EN_ACLK_G2D,
EN_ACLK_G2D_SECURE_SSS,
EN_ACLK_G2D_SECURE_SLIM_SSS,
EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS,
EN_ACLK_G2D_SECURE_SMMU_SSS,
EN_ACLK_G2D_SECURE_SMMU_MDMA,
EN_ACLK_G2D_SECURE_SMMU_G2D,
EN_PCLK_G2D,
EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS,
EN_PCLK_G2D_SECURE_SMMU_SSS,
EN_PCLK_G2D_SECURE_SMMU_MDMA,
EN_PCLK_G2D_SECURE_SMMU_G2D,
EN_IP_G2D,
EN_IP_G2D_SECURE_SSS,
EN_IP_G2D_SECURE_SLIM_SSS,
EN_IP_G2D_SECURE_SMMU_SLIM_SSS,
EN_IP_G2D_SECURE_SMMU_SSS,
EN_IP_G2D_SECURE_SMMU_MDMA,
EN_IP_G2D_SECURE_SMMU_G2D,
};
PNAME(mout_aclk_g2d_333_user_p) = {"fin_pll", "dout_aclk_g2d_333"};
static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {
MUX(G2D_MOUT_ACLK_G2D_333_USER, "mout_aclk_g2d_333_user",
mout_aclk_g2d_333_user_p,
MUX_SEL_G2D, 0, 1),
};
static const struct samsung_div_clock g2d_div_clks[] __initconst = {
DIV(G2D_DOUT_PCLK_G2D_83, "dout_pclk_g2d_83", "mout_aclk_g2d_333_user",
DIV_G2D, 0, 3),
};
static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
GATE(G2D_CLK_G2D, "clk_g2d", "mout_aclk_g2d_333_user",
EN_IP_G2D, 4, 0, 0),
GATE(G2D_CLK_JPEG, "clk_jpeg", "mout_aclk_g2d_333_user",
EN_IP_G2D, 5, 0, 0),
GATE(G2D_CLK_MDMA, "clk_mdma", "mout_aclk_g2d_333_user",
EN_IP_G2D, 6, 0, 0),
GATE(G2D_CLK_SMMU3_JPEG, "clk_smmu3_jpeg", "mout_aclk_g2d_333_user",
EN_IP_G2D, 16, 0, 0),
GATE(G2D_CLK_SSS, "clk_sss", "mout_aclk_g2d_333_user",
EN_IP_G2D_SECURE_SSS, 17, 0, 0),
GATE(G2D_CLK_SLIM_SSS, "clk_slim_sss", "mout_aclk_g2d_333_user",
EN_IP_G2D_SECURE_SLIM_SSS, 11, 0, 0),
GATE(G2D_CLK_SMMU_SLIM_SSS, "clk_smmu_slim_sss",
"mout_aclk_g2d_333_user",
EN_IP_G2D_SECURE_SMMU_SLIM_SSS, 13, 0, 0),
GATE(G2D_CLK_SMMU_SSS, "clk_smmu_sss", "mout_aclk_g2d_333_user",
EN_IP_G2D_SECURE_SMMU_SSS, 14, 0, 0),
GATE(G2D_CLK_SMMU_MDMA, "clk_smmu_mdma", "mout_aclk_g2d_333_user",
EN_IP_G2D_SECURE_SMMU_MDMA, 12, 0, 0),
GATE(G2D_CLK_SMMU3_G2D, "clk_smmu3_g2d", "mout_aclk_g2d_333_user",
EN_IP_G2D_SECURE_SMMU_G2D, 15, 0, 0),
};
static const struct samsung_cmu_info g2d_cmu __initconst = {
.mux_clks = g2d_mux_clks,
.nr_mux_clks = ARRAY_SIZE(g2d_mux_clks),
.div_clks = g2d_div_clks,
.nr_div_clks = ARRAY_SIZE(g2d_div_clks),
.gate_clks = g2d_gate_clks,
.nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
.nr_clk_ids = CLKS_NR_G2D,
.clk_regs = g2d_clk_regs,
.nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
};
static void __init exynos5260_clk_g2d_init(struct device_node *np)
{
samsung_cmu_register_one(np, &g2d_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_g2d, "samsung,exynos5260-clock-g2d",
exynos5260_clk_g2d_init);
/* CMU_G3D */
static const unsigned long g3d_clk_regs[] __initconst = {
G3D_PLL_LOCK,
G3D_PLL_CON0,
G3D_PLL_CON1,
G3D_PLL_FDET,
MUX_SEL_G3D,
DIV_G3D,
DIV_G3D_PLL_FDET,
EN_ACLK_G3D,
EN_PCLK_G3D,
EN_SCLK_G3D,
EN_IP_G3D,
};
PNAME(mout_g3d_pll_p) = {"fin_pll", "fout_g3d_pll"};
static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
MUX(G3D_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
MUX_SEL_G3D, 0, 1),
};
static const struct samsung_div_clock g3d_div_clks[] __initconst = {
DIV(G3D_DOUT_PCLK_G3D, "dout_pclk_g3d", "dout_aclk_g3d", DIV_G3D, 0, 3),
DIV(G3D_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_g3d_pll", DIV_G3D, 4, 3),
};
static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
GATE(G3D_CLK_G3D, "clk_g3d", "dout_aclk_g3d", EN_IP_G3D, 2, 0, 0),
GATE(G3D_CLK_G3D_HPM, "clk_g3d_hpm", "dout_aclk_g3d",
EN_IP_G3D, 3, 0, 0),
};
static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
PLL(pll_2550, G3D_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll",
G3D_PLL_LOCK, G3D_PLL_CON0,
pll2550_24mhz_tbl),
};
static const struct samsung_cmu_info g3d_cmu __initconst = {
.pll_clks = g3d_pll_clks,
.nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
.mux_clks = g3d_mux_clks,
.nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
.div_clks = g3d_div_clks,
.nr_div_clks = ARRAY_SIZE(g3d_div_clks),
.gate_clks = g3d_gate_clks,
.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
.nr_clk_ids = CLKS_NR_G3D,
.clk_regs = g3d_clk_regs,
.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
};
static void __init exynos5260_clk_g3d_init(struct device_node *np)
{
samsung_cmu_register_one(np, &g3d_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_g3d, "samsung,exynos5260-clock-g3d",
exynos5260_clk_g3d_init);
/* CMU_GSCL */
static const unsigned long gscl_clk_regs[] __initconst = {
MUX_SEL_GSCL,
DIV_GSCL,
EN_ACLK_GSCL,
EN_ACLK_GSCL_FIMC,
EN_ACLK_GSCL_SECURE_SMMU_GSCL0,
EN_ACLK_GSCL_SECURE_SMMU_GSCL1,
EN_ACLK_GSCL_SECURE_SMMU_MSCL0,
EN_ACLK_GSCL_SECURE_SMMU_MSCL1,
EN_PCLK_GSCL,
EN_PCLK_GSCL_FIMC,
EN_PCLK_GSCL_SECURE_SMMU_GSCL0,
EN_PCLK_GSCL_SECURE_SMMU_GSCL1,
EN_PCLK_GSCL_SECURE_SMMU_MSCL0,
EN_PCLK_GSCL_SECURE_SMMU_MSCL1,
EN_SCLK_GSCL,
EN_SCLK_GSCL_FIMC,
EN_IP_GSCL,
EN_IP_GSCL_FIMC,
EN_IP_GSCL_SECURE_SMMU_GSCL0,
EN_IP_GSCL_SECURE_SMMU_GSCL1,
EN_IP_GSCL_SECURE_SMMU_MSCL0,
EN_IP_GSCL_SECURE_SMMU_MSCL1,
};
PNAME(mout_aclk_gscl_333_user_p) = {"fin_pll", "dout_aclk_gscl_333"};
PNAME(mout_aclk_m2m_400_user_p) = {"fin_pll", "dout_aclk_gscl_400"};
PNAME(mout_aclk_gscl_fimc_user_p) = {"fin_pll", "dout_aclk_gscl_400"};
PNAME(mout_aclk_csis_p) = {"dout_aclk_csis_200", "mout_aclk_gscl_fimc_user"};
static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {
MUX(GSCL_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
mout_aclk_gscl_333_user_p,
MUX_SEL_GSCL, 0, 1),
MUX(GSCL_MOUT_ACLK_M2M_400_USER, "mout_aclk_m2m_400_user",
mout_aclk_m2m_400_user_p,
MUX_SEL_GSCL, 4, 1),
MUX(GSCL_MOUT_ACLK_GSCL_FIMC_USER, "mout_aclk_gscl_fimc_user",
mout_aclk_gscl_fimc_user_p,
MUX_SEL_GSCL, 8, 1),
MUX(GSCL_MOUT_ACLK_CSIS, "mout_aclk_csis", mout_aclk_csis_p,
MUX_SEL_GSCL, 24, 1),
};
static const struct samsung_div_clock gscl_div_clks[] __initconst = {
DIV(GSCL_DOUT_PCLK_M2M_100, "dout_pclk_m2m_100",
"mout_aclk_m2m_400_user",
DIV_GSCL, 0, 3),
DIV(GSCL_DOUT_ACLK_CSIS_200, "dout_aclk_csis_200",
"mout_aclk_m2m_400_user",
DIV_GSCL, 4, 3),
};
static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
GATE(GSCL_SCLK_CSIS0_WRAP, "sclk_csis0_wrap", "dout_aclk_csis_200",
EN_SCLK_GSCL_FIMC, 0, CLK_SET_RATE_PARENT, 0),
GATE(GSCL_SCLK_CSIS1_WRAP, "sclk_csis1_wrap", "dout_aclk_csis_200",
EN_SCLK_GSCL_FIMC, 1, CLK_SET_RATE_PARENT, 0),
GATE(GSCL_CLK_GSCL0, "clk_gscl0", "mout_aclk_gscl_333_user",
EN_IP_GSCL, 2, 0, 0),
GATE(GSCL_CLK_GSCL1, "clk_gscl1", "mout_aclk_gscl_333_user",
EN_IP_GSCL, 3, 0, 0),
GATE(GSCL_CLK_MSCL0, "clk_mscl0", "mout_aclk_gscl_333_user",
EN_IP_GSCL, 4, 0, 0),
GATE(GSCL_CLK_MSCL1, "clk_mscl1", "mout_aclk_gscl_333_user",
EN_IP_GSCL, 5, 0, 0),
GATE(GSCL_CLK_PIXEL_GSCL0, "clk_pixel_gscl0",
"mout_aclk_gscl_333_user",
EN_IP_GSCL, 8, 0, 0),
GATE(GSCL_CLK_PIXEL_GSCL1, "clk_pixel_gscl1",
"mout_aclk_gscl_333_user",
EN_IP_GSCL, 9, 0, 0),
GATE(GSCL_CLK_SMMU3_LITE_A, "clk_smmu3_lite_a",
"mout_aclk_gscl_fimc_user",
EN_IP_GSCL_FIMC, 5, 0, 0),
GATE(GSCL_CLK_SMMU3_LITE_B, "clk_smmu3_lite_b",
"mout_aclk_gscl_fimc_user",
EN_IP_GSCL_FIMC, 6, 0, 0),
GATE(GSCL_CLK_SMMU3_LITE_D, "clk_smmu3_lite_d",
"mout_aclk_gscl_fimc_user",
EN_IP_GSCL_FIMC, 7, 0, 0),
GATE(GSCL_CLK_CSIS0, "clk_csis0", "mout_aclk_gscl_fimc_user",
EN_IP_GSCL_FIMC, 8, 0, 0),
GATE(GSCL_CLK_CSIS1, "clk_csis1", "mout_aclk_gscl_fimc_user",
EN_IP_GSCL_FIMC, 9, 0, 0),
GATE(GSCL_CLK_FIMC_LITE_A, "clk_fimc_lite_a",
"mout_aclk_gscl_fimc_user",
EN_IP_GSCL_FIMC, 10, 0, 0),
GATE(GSCL_CLK_FIMC_LITE_B, "clk_fimc_lite_b",
"mout_aclk_gscl_fimc_user",
EN_IP_GSCL_FIMC, 11, 0, 0),
GATE(GSCL_CLK_FIMC_LITE_D, "clk_fimc_lite_d",
"mout_aclk_gscl_fimc_user",
EN_IP_GSCL_FIMC, 12, 0, 0),
GATE(GSCL_CLK_SMMU3_GSCL0, "clk_smmu3_gscl0",
"mout_aclk_gscl_333_user",
EN_IP_GSCL_SECURE_SMMU_GSCL0, 17, 0, 0),
GATE(GSCL_CLK_SMMU3_GSCL1, "clk_smmu3_gscl1", "mout_aclk_gscl_333_user",
EN_IP_GSCL_SECURE_SMMU_GSCL1, 18, 0, 0),
GATE(GSCL_CLK_SMMU3_MSCL0, "clk_smmu3_mscl0",
"mout_aclk_m2m_400_user",
EN_IP_GSCL_SECURE_SMMU_MSCL0, 19, 0, 0),
GATE(GSCL_CLK_SMMU3_MSCL1, "clk_smmu3_mscl1",
"mout_aclk_m2m_400_user",
EN_IP_GSCL_SECURE_SMMU_MSCL1, 20, 0, 0),
};
static const struct samsung_cmu_info gscl_cmu __initconst = {
.mux_clks = gscl_mux_clks,
.nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
.div_clks = gscl_div_clks,
.nr_div_clks = ARRAY_SIZE(gscl_div_clks),
.gate_clks = gscl_gate_clks,
.nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
.nr_clk_ids = CLKS_NR_GSCL,
.clk_regs = gscl_clk_regs,
.nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
};
static void __init exynos5260_clk_gscl_init(struct device_node *np)
{
samsung_cmu_register_one(np, &gscl_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_gscl, "samsung,exynos5260-clock-gscl",
exynos5260_clk_gscl_init);
/* CMU_ISP */
static const unsigned long isp_clk_regs[] __initconst = {
MUX_SEL_ISP0,
MUX_SEL_ISP1,
DIV_ISP,
EN_ACLK_ISP0,
EN_ACLK_ISP1,
EN_PCLK_ISP0,
EN_PCLK_ISP1,
EN_SCLK_ISP,
EN_IP_ISP0,
EN_IP_ISP1,
};
PNAME(mout_isp_400_user_p) = {"fin_pll", "dout_aclk_isp1_400"};
PNAME(mout_isp_266_user_p) = {"fin_pll", "dout_aclk_isp1_266"};
static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
MUX(ISP_MOUT_ISP_266_USER, "mout_isp_266_user", mout_isp_266_user_p,
MUX_SEL_ISP0, 0, 1),
MUX(ISP_MOUT_ISP_400_USER, "mout_isp_400_user", mout_isp_400_user_p,
MUX_SEL_ISP0, 4, 1),
};
static const struct samsung_div_clock isp_div_clks[] __initconst = {
DIV(ISP_DOUT_PCLK_ISP_66, "dout_pclk_isp_66", "mout_kfc",
DIV_ISP, 0, 3),
DIV(ISP_DOUT_PCLK_ISP_133, "dout_pclk_isp_133", "mout_kfc",
DIV_ISP, 4, 4),
DIV(ISP_DOUT_CA5_ATCLKIN, "dout_ca5_atclkin", "mout_kfc",
DIV_ISP, 12, 3),
DIV(ISP_DOUT_CA5_PCLKDBG, "dout_ca5_pclkdbg", "mout_kfc",
DIV_ISP, 16, 4),
DIV(ISP_DOUT_SCLK_MPWM, "dout_sclk_mpwm", "mout_kfc", DIV_ISP, 20, 2),
};
static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
GATE(ISP_CLK_GIC, "clk_isp_gic", "mout_aclk_isp1_266",
EN_IP_ISP0, 15, 0, 0),
GATE(ISP_CLK_CA5, "clk_isp_ca5", "mout_aclk_isp1_266",
EN_IP_ISP1, 1, 0, 0),
GATE(ISP_CLK_FIMC_DRC, "clk_isp_fimc_drc", "mout_aclk_isp1_266",
EN_IP_ISP1, 2, 0, 0),
GATE(ISP_CLK_FIMC_FD, "clk_isp_fimc_fd", "mout_aclk_isp1_266",
EN_IP_ISP1, 3, 0, 0),
GATE(ISP_CLK_FIMC, "clk_isp_fimc", "mout_aclk_isp1_266",
EN_IP_ISP1, 4, 0, 0),
GATE(ISP_CLK_FIMC_SCALERC, "clk_isp_fimc_scalerc",
"mout_aclk_isp1_266",
EN_IP_ISP1, 5, 0, 0),
GATE(ISP_CLK_FIMC_SCALERP, "clk_isp_fimc_scalerp",
"mout_aclk_isp1_266",
EN_IP_ISP1, 6, 0, 0),
GATE(ISP_CLK_I2C0, "clk_isp_i2c0", "mout_aclk_isp1_266",
EN_IP_ISP1, 7, 0, 0),
GATE(ISP_CLK_I2C1, "clk_isp_i2c1", "mout_aclk_isp1_266",
EN_IP_ISP1, 8, 0, 0),
GATE(ISP_CLK_MCUCTL, "clk_isp_mcuctl", "mout_aclk_isp1_266",
EN_IP_ISP1, 9, 0, 0),
GATE(ISP_CLK_MPWM, "clk_isp_mpwm", "mout_aclk_isp1_266",
EN_IP_ISP1, 10, 0, 0),
GATE(ISP_CLK_MTCADC, "clk_isp_mtcadc", "mout_aclk_isp1_266",
EN_IP_ISP1, 11, 0, 0),
GATE(ISP_CLK_PWM, "clk_isp_pwm", "mout_aclk_isp1_266",
EN_IP_ISP1, 14, 0, 0),
GATE(ISP_CLK_SMMU_DRC, "clk_smmu_drc", "mout_aclk_isp1_266",
EN_IP_ISP1, 21, 0, 0),
GATE(ISP_CLK_SMMU_FD, "clk_smmu_fd", "mout_aclk_isp1_266",
EN_IP_ISP1, 22, 0, 0),
GATE(ISP_CLK_SMMU_ISP, "clk_smmu_isp", "mout_aclk_isp1_266",
EN_IP_ISP1, 23, 0, 0),
GATE(ISP_CLK_SMMU_ISPCX, "clk_smmu_ispcx", "mout_aclk_isp1_266",
EN_IP_ISP1, 24, 0, 0),
GATE(ISP_CLK_SMMU_SCALERC, "clk_isp_smmu_scalerc",
"mout_aclk_isp1_266",
EN_IP_ISP1, 25, 0, 0),
GATE(ISP_CLK_SMMU_SCALERP, "clk_isp_smmu_scalerp",
"mout_aclk_isp1_266",
EN_IP_ISP1, 26, 0, 0),
GATE(ISP_CLK_SPI0, "clk_isp_spi0", "mout_aclk_isp1_266",
EN_IP_ISP1, 27, 0, 0),
GATE(ISP_CLK_SPI1, "clk_isp_spi1", "mout_aclk_isp1_266",
EN_IP_ISP1, 28, 0, 0),
GATE(ISP_CLK_WDT, "clk_isp_wdt", "mout_aclk_isp1_266",
EN_IP_ISP1, 31, 0, 0),
GATE(ISP_CLK_UART, "clk_isp_uart", "mout_aclk_isp1_266",
EN_IP_ISP1, 30, 0, 0),
GATE(ISP_SCLK_UART_EXT, "sclk_isp_uart_ext", "fin_pll",
EN_SCLK_ISP, 7, CLK_SET_RATE_PARENT, 0),
GATE(ISP_SCLK_SPI1_EXT, "sclk_isp_spi1_ext", "fin_pll",
EN_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
GATE(ISP_SCLK_SPI0_EXT, "sclk_isp_spi0_ext", "fin_pll",
EN_SCLK_ISP, 9, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_cmu_info isp_cmu __initconst = {
.mux_clks = isp_mux_clks,
.nr_mux_clks = ARRAY_SIZE(isp_mux_clks),
.div_clks = isp_div_clks,
.nr_div_clks = ARRAY_SIZE(isp_div_clks),
.gate_clks = isp_gate_clks,
.nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
.nr_clk_ids = CLKS_NR_ISP,
.clk_regs = isp_clk_regs,
.nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
};
static void __init exynos5260_clk_isp_init(struct device_node *np)
{
samsung_cmu_register_one(np, &isp_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_isp, "samsung,exynos5260-clock-isp",
exynos5260_clk_isp_init);
/* CMU_KFC */
static const unsigned long kfc_clk_regs[] __initconst = {
KFC_PLL_LOCK,
KFC_PLL_CON0,
KFC_PLL_CON1,
KFC_PLL_FDET,
MUX_SEL_KFC0,
MUX_SEL_KFC2,
DIV_KFC,
DIV_KFC_PLL_FDET,
EN_ACLK_KFC,
EN_PCLK_KFC,
EN_SCLK_KFC,
EN_IP_KFC,
};
PNAME(mout_kfc_pll_p) = {"fin_pll", "fout_kfc_pll"};
PNAME(mout_kfc_p) = {"mout_kfc_pll", "dout_media_pll"};
static const struct samsung_mux_clock kfc_mux_clks[] __initconst = {
MUX(KFC_MOUT_KFC_PLL, "mout_kfc_pll", mout_kfc_pll_p,
MUX_SEL_KFC0, 0, 1),
MUX(KFC_MOUT_KFC, "mout_kfc", mout_kfc_p, MUX_SEL_KFC2, 0, 1),
};
static const struct samsung_div_clock kfc_div_clks[] __initconst = {
DIV(KFC_DOUT_KFC1, "dout_kfc1", "mout_kfc", DIV_KFC, 0, 3),
DIV(KFC_DOUT_KFC2, "dout_kfc2", "dout_kfc1", DIV_KFC, 4, 3),
DIV(KFC_DOUT_KFC_ATCLK, "dout_kfc_atclk", "dout_kfc2", DIV_KFC, 8, 3),
DIV(KFC_DOUT_KFC_PCLK_DBG, "dout_kfc_pclk_dbg", "dout_kfc2",
DIV_KFC, 12, 3),
DIV(KFC_DOUT_ACLK_KFC, "dout_aclk_kfc", "dout_kfc2", DIV_KFC, 16, 3),
DIV(KFC_DOUT_PCLK_KFC, "dout_pclk_kfc", "dout_kfc2", DIV_KFC, 20, 3),
DIV(KFC_DOUT_KFC_PLL, "dout_kfc_pll", "mout_kfc", DIV_KFC, 24, 3),
};
static const struct samsung_pll_clock kfc_pll_clks[] __initconst = {
PLL(pll_2550xx, KFC_FOUT_KFC_PLL, "fout_kfc_pll", "fin_pll",
KFC_PLL_LOCK, KFC_PLL_CON0,
pll2550_24mhz_tbl),
};
static const struct samsung_cmu_info kfc_cmu __initconst = {
.pll_clks = kfc_pll_clks,
.nr_pll_clks = ARRAY_SIZE(kfc_pll_clks),
.mux_clks = kfc_mux_clks,
.nr_mux_clks = ARRAY_SIZE(kfc_mux_clks),
.div_clks = kfc_div_clks,
.nr_div_clks = ARRAY_SIZE(kfc_div_clks),
.nr_clk_ids = CLKS_NR_KFC,
.clk_regs = kfc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(kfc_clk_regs),
};
static void __init exynos5260_clk_kfc_init(struct device_node *np)
{
samsung_cmu_register_one(np, &kfc_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_kfc, "samsung,exynos5260-clock-kfc",
exynos5260_clk_kfc_init);
/* CMU_MFC */
static const unsigned long mfc_clk_regs[] __initconst = {
MUX_SEL_MFC,
DIV_MFC,
EN_ACLK_MFC,
EN_ACLK_SECURE_SMMU2_MFC,
EN_PCLK_MFC,
EN_PCLK_SECURE_SMMU2_MFC,
EN_IP_MFC,
EN_IP_MFC_SECURE_SMMU2_MFC,
};
PNAME(mout_aclk_mfc_333_user_p) = {"fin_pll", "dout_aclk_mfc_333"};
static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
MUX(MFC_MOUT_ACLK_MFC_333_USER, "mout_aclk_mfc_333_user",
mout_aclk_mfc_333_user_p,
MUX_SEL_MFC, 0, 1),
};
static const struct samsung_div_clock mfc_div_clks[] __initconst = {
DIV(MFC_DOUT_PCLK_MFC_83, "dout_pclk_mfc_83", "mout_aclk_mfc_333_user",
DIV_MFC, 0, 3),
};
static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
GATE(MFC_CLK_MFC, "clk_mfc", "mout_aclk_mfc_333_user",
EN_IP_MFC, 1, 0, 0),
GATE(MFC_CLK_SMMU2_MFCM0, "clk_smmu2_mfcm0", "mout_aclk_mfc_333_user",
EN_IP_MFC_SECURE_SMMU2_MFC, 6, 0, 0),
GATE(MFC_CLK_SMMU2_MFCM1, "clk_smmu2_mfcm1", "mout_aclk_mfc_333_user",
EN_IP_MFC_SECURE_SMMU2_MFC, 7, 0, 0),
};
static const struct samsung_cmu_info mfc_cmu __initconst = {
.mux_clks = mfc_mux_clks,
.nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
.div_clks = mfc_div_clks,
.nr_div_clks = ARRAY_SIZE(mfc_div_clks),
.gate_clks = mfc_gate_clks,
.nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
.nr_clk_ids = CLKS_NR_MFC,
.clk_regs = mfc_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
};
static void __init exynos5260_clk_mfc_init(struct device_node *np)
{
samsung_cmu_register_one(np, &mfc_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_mfc, "samsung,exynos5260-clock-mfc",
exynos5260_clk_mfc_init);
/* CMU_MIF */
static const unsigned long mif_clk_regs[] __initconst = {
MEM_PLL_LOCK,
BUS_PLL_LOCK,
MEDIA_PLL_LOCK,
MEM_PLL_CON0,
MEM_PLL_CON1,
MEM_PLL_FDET,
BUS_PLL_CON0,
BUS_PLL_CON1,
BUS_PLL_FDET,
MEDIA_PLL_CON0,
MEDIA_PLL_CON1,
MEDIA_PLL_FDET,
MUX_SEL_MIF,
DIV_MIF,
DIV_MIF_PLL_FDET,
EN_ACLK_MIF,
EN_ACLK_MIF_SECURE_DREX1_TZ,
EN_ACLK_MIF_SECURE_DREX0_TZ,
EN_ACLK_MIF_SECURE_INTMEM,
EN_PCLK_MIF,
EN_PCLK_MIF_SECURE_MONOCNT,
EN_PCLK_MIF_SECURE_RTC_APBIF,
EN_PCLK_MIF_SECURE_DREX1_TZ,
EN_PCLK_MIF_SECURE_DREX0_TZ,
EN_SCLK_MIF,
EN_IP_MIF,
EN_IP_MIF_SECURE_MONOCNT,
EN_IP_MIF_SECURE_RTC_APBIF,
EN_IP_MIF_SECURE_DREX1_TZ,
EN_IP_MIF_SECURE_DREX0_TZ,
EN_IP_MIF_SECURE_INTEMEM,
};
PNAME(mout_mem_pll_p) = {"fin_pll", "fout_mem_pll"};
PNAME(mout_bus_pll_p) = {"fin_pll", "fout_bus_pll"};
PNAME(mout_media_pll_p) = {"fin_pll", "fout_media_pll"};
PNAME(mout_mif_drex_p) = {"dout_mem_pll", "dout_bus_pll"};
PNAME(mout_mif_drex2x_p) = {"dout_mem_pll", "dout_bus_pll"};
PNAME(mout_clkm_phy_p) = {"mout_mif_drex", "dout_media_pll"};
PNAME(mout_clk2x_phy_p) = {"mout_mif_drex2x", "dout_media_pll"};
static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
MUX(MIF_MOUT_MEM_PLL, "mout_mem_pll", mout_mem_pll_p,
MUX_SEL_MIF, 0, 1),
MUX(MIF_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p,
MUX_SEL_MIF, 4, 1),
MUX(MIF_MOUT_MEDIA_PLL, "mout_media_pll", mout_media_pll_p,
MUX_SEL_MIF, 8, 1),
MUX(MIF_MOUT_MIF_DREX, "mout_mif_drex", mout_mif_drex_p,
MUX_SEL_MIF, 12, 1),
MUX(MIF_MOUT_CLKM_PHY, "mout_clkm_phy", mout_clkm_phy_p,
MUX_SEL_MIF, 16, 1),
MUX(MIF_MOUT_MIF_DREX2X, "mout_mif_drex2x", mout_mif_drex2x_p,
MUX_SEL_MIF, 20, 1),
MUX(MIF_MOUT_CLK2X_PHY, "mout_clk2x_phy", mout_clk2x_phy_p,
MUX_SEL_MIF, 24, 1),
};
static const struct samsung_div_clock mif_div_clks[] __initconst = {
DIV(MIF_DOUT_MEDIA_PLL, "dout_media_pll", "mout_media_pll",
DIV_MIF, 0, 3),
DIV(MIF_DOUT_MEM_PLL, "dout_mem_pll", "mout_mem_pll",
DIV_MIF, 4, 3),
DIV(MIF_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll",
DIV_MIF, 8, 3),
DIV(MIF_DOUT_CLKM_PHY, "dout_clkm_phy", "mout_clkm_phy",
DIV_MIF, 12, 3),
DIV(MIF_DOUT_CLK2X_PHY, "dout_clk2x_phy", "mout_clk2x_phy",
DIV_MIF, 16, 4),
DIV(MIF_DOUT_ACLK_MIF_466, "dout_aclk_mif_466", "dout_clk2x_phy",
DIV_MIF, 20, 3),
DIV(MIF_DOUT_ACLK_BUS_200, "dout_aclk_bus_200", "dout_bus_pll",
DIV_MIF, 24, 3),
DIV(MIF_DOUT_ACLK_BUS_100, "dout_aclk_bus_100", "dout_bus_pll",
DIV_MIF, 28, 4),
};
static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
GATE(MIF_CLK_LPDDR3PHY_WRAP0, "clk_lpddr3phy_wrap0", "dout_clk2x_phy",
EN_IP_MIF, 12, CLK_IGNORE_UNUSED, 0),
GATE(MIF_CLK_LPDDR3PHY_WRAP1, "clk_lpddr3phy_wrap1", "dout_clk2x_phy",
EN_IP_MIF, 13, CLK_IGNORE_UNUSED, 0),
GATE(MIF_CLK_MONOCNT, "clk_monocnt", "dout_aclk_bus_100",
EN_IP_MIF_SECURE_MONOCNT, 22,
CLK_IGNORE_UNUSED, 0),
GATE(MIF_CLK_MIF_RTC, "clk_mif_rtc", "dout_aclk_bus_100",
EN_IP_MIF_SECURE_RTC_APBIF, 23,
CLK_IGNORE_UNUSED, 0),
GATE(MIF_CLK_DREX1, "clk_drex1", "dout_aclk_mif_466",
EN_IP_MIF_SECURE_DREX1_TZ, 9,
CLK_IGNORE_UNUSED, 0),
GATE(MIF_CLK_DREX0, "clk_drex0", "dout_aclk_mif_466",
EN_IP_MIF_SECURE_DREX0_TZ, 9,
CLK_IGNORE_UNUSED, 0),
GATE(MIF_CLK_INTMEM, "clk_intmem", "dout_aclk_bus_200",
EN_IP_MIF_SECURE_INTEMEM, 11,
CLK_IGNORE_UNUSED, 0),
GATE(MIF_SCLK_LPDDR3PHY_WRAP_U0, "sclk_lpddr3phy_wrap_u0",
"dout_clkm_phy", EN_SCLK_MIF, 0,
CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
GATE(MIF_SCLK_LPDDR3PHY_WRAP_U1, "sclk_lpddr3phy_wrap_u1",
"dout_clkm_phy", EN_SCLK_MIF, 1,
CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
PLL(pll_2550xx, MIF_FOUT_MEM_PLL, "fout_mem_pll", "fin_pll",
MEM_PLL_LOCK, MEM_PLL_CON0,
pll2550_24mhz_tbl),
PLL(pll_2550xx, MIF_FOUT_BUS_PLL, "fout_bus_pll", "fin_pll",
BUS_PLL_LOCK, BUS_PLL_CON0,
pll2550_24mhz_tbl),
PLL(pll_2550xx, MIF_FOUT_MEDIA_PLL, "fout_media_pll", "fin_pll",
MEDIA_PLL_LOCK, MEDIA_PLL_CON0,
pll2550_24mhz_tbl),
};
static const struct samsung_cmu_info mif_cmu __initconst = {
.pll_clks = mif_pll_clks,
.nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
.mux_clks = mif_mux_clks,
.nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
.div_clks = mif_div_clks,
.nr_div_clks = ARRAY_SIZE(mif_div_clks),
.gate_clks = mif_gate_clks,
.nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
.nr_clk_ids = CLKS_NR_MIF,
.clk_regs = mif_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
};
static void __init exynos5260_clk_mif_init(struct device_node *np)
{
samsung_cmu_register_one(np, &mif_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_mif, "samsung,exynos5260-clock-mif",
exynos5260_clk_mif_init);
/* CMU_PERI */
static const unsigned long peri_clk_regs[] __initconst = {
MUX_SEL_PERI,
MUX_SEL_PERI1,
DIV_PERI,
EN_PCLK_PERI0,
EN_PCLK_PERI1,
EN_PCLK_PERI2,
EN_PCLK_PERI3,
EN_PCLK_PERI_SECURE_CHIPID,
EN_PCLK_PERI_SECURE_PROVKEY0,
EN_PCLK_PERI_SECURE_PROVKEY1,
EN_PCLK_PERI_SECURE_SECKEY,
EN_PCLK_PERI_SECURE_ANTIRBKCNT,
EN_PCLK_PERI_SECURE_TOP_RTC,
EN_PCLK_PERI_SECURE_TZPC,
EN_SCLK_PERI,
EN_SCLK_PERI_SECURE_TOP_RTC,
EN_IP_PERI0,
EN_IP_PERI1,
EN_IP_PERI2,
EN_IP_PERI_SECURE_CHIPID,
EN_IP_PERI_SECURE_PROVKEY0,
EN_IP_PERI_SECURE_PROVKEY1,
EN_IP_PERI_SECURE_SECKEY,
EN_IP_PERI_SECURE_ANTIRBKCNT,
EN_IP_PERI_SECURE_TOP_RTC,
EN_IP_PERI_SECURE_TZPC,
};
PNAME(mout_sclk_pcm_p) = {"ioclk_pcm_extclk", "fin_pll", "dout_aclk_peri_aud",
"phyclk_hdmi_phy_ref_cko"};
PNAME(mout_sclk_i2scod_p) = {"ioclk_i2s_cdclk", "fin_pll", "dout_aclk_peri_aud",
"phyclk_hdmi_phy_ref_cko"};
PNAME(mout_sclk_spdif_p) = {"ioclk_spdif_extclk", "fin_pll",
"dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
MUX(PERI_MOUT_SCLK_PCM, "mout_sclk_pcm", mout_sclk_pcm_p,
MUX_SEL_PERI1, 4, 2),
MUX(PERI_MOUT_SCLK_I2SCOD, "mout_sclk_i2scod", mout_sclk_i2scod_p,
MUX_SEL_PERI1, 12, 2),
MUX(PERI_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
MUX_SEL_PERI1, 20, 2),
};
static const struct samsung_div_clock peri_div_clks[] __initconst = {
DIV(PERI_DOUT_PCM, "dout_pcm", "mout_sclk_pcm", DIV_PERI, 0, 8),
DIV(PERI_DOUT_I2S, "dout_i2s", "mout_sclk_i2scod", DIV_PERI, 8, 6),
};
static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
GATE(PERI_SCLK_PCM1, "sclk_pcm1", "dout_pcm", EN_SCLK_PERI, 0,
CLK_SET_RATE_PARENT, 0),
GATE(PERI_SCLK_I2S, "sclk_i2s", "dout_i2s", EN_SCLK_PERI, 1,
CLK_SET_RATE_PARENT, 0),
GATE(PERI_SCLK_SPDIF, "sclk_spdif", "dout_sclk_peri_spi0_b",
EN_SCLK_PERI, 2, CLK_SET_RATE_PARENT, 0),
GATE(PERI_SCLK_SPI0, "sclk_spi0", "dout_sclk_peri_spi0_b",
EN_SCLK_PERI, 7, CLK_SET_RATE_PARENT, 0),
GATE(PERI_SCLK_SPI1, "sclk_spi1", "dout_sclk_peri_spi1_b",
EN_SCLK_PERI, 8, CLK_SET_RATE_PARENT, 0),
GATE(PERI_SCLK_SPI2, "sclk_spi2", "dout_sclk_peri_spi2_b",
EN_SCLK_PERI, 9, CLK_SET_RATE_PARENT, 0),
GATE(PERI_SCLK_UART0, "sclk_uart0", "dout_sclk_peri_uart0",
EN_SCLK_PERI, 10, CLK_SET_RATE_PARENT, 0),
GATE(PERI_SCLK_UART1, "sclk_uart1", "dout_sclk_peri_uart1",
EN_SCLK_PERI, 11, CLK_SET_RATE_PARENT, 0),
GATE(PERI_SCLK_UART2, "sclk_uart2", "dout_sclk_peri_uart2",
EN_SCLK_PERI, 12, CLK_SET_RATE_PARENT, 0),
GATE(PERI_CLK_ABB, "clk_abb", "dout_aclk_peri_66",
EN_IP_PERI0, 1, 0, 0),
GATE(PERI_CLK_EFUSE_WRITER, "clk_efuse_writer", "dout_aclk_peri_66",
EN_IP_PERI0, 5, 0, 0),
GATE(PERI_CLK_HDMICEC, "clk_hdmicec", "dout_aclk_peri_66",
EN_IP_PERI0, 6, 0, 0),
GATE(PERI_CLK_I2C10, "clk_i2c10", "dout_aclk_peri_66",
EN_IP_PERI0, 7, 0, 0),
GATE(PERI_CLK_I2C11, "clk_i2c11", "dout_aclk_peri_66",
EN_IP_PERI0, 8, 0, 0),
GATE(PERI_CLK_I2C8, "clk_i2c8", "dout_aclk_peri_66",
EN_IP_PERI0, 9, 0, 0),
GATE(PERI_CLK_I2C9, "clk_i2c9", "dout_aclk_peri_66",
EN_IP_PERI0, 10, 0, 0),
GATE(PERI_CLK_I2C4, "clk_i2c4", "dout_aclk_peri_66",
EN_IP_PERI0, 11, 0, 0),
GATE(PERI_CLK_I2C5, "clk_i2c5", "dout_aclk_peri_66",
EN_IP_PERI0, 12, 0, 0),
GATE(PERI_CLK_I2C6, "clk_i2c6", "dout_aclk_peri_66",
EN_IP_PERI0, 13, 0, 0),
GATE(PERI_CLK_I2C7, "clk_i2c7", "dout_aclk_peri_66",
EN_IP_PERI0, 14, 0, 0),
GATE(PERI_CLK_I2CHDMI, "clk_i2chdmi", "dout_aclk_peri_66",
EN_IP_PERI0, 15, 0, 0),
GATE(PERI_CLK_I2S, "clk_peri_i2s", "dout_aclk_peri_66",
EN_IP_PERI0, 16, 0, 0),
GATE(PERI_CLK_MCT, "clk_mct", "dout_aclk_peri_66",
EN_IP_PERI0, 17, 0, 0),
GATE(PERI_CLK_PCM, "clk_peri_pcm", "dout_aclk_peri_66",
EN_IP_PERI0, 18, 0, 0),
GATE(PERI_CLK_HSIC0, "clk_hsic0", "dout_aclk_peri_66",
EN_IP_PERI0, 20, 0, 0),
GATE(PERI_CLK_HSIC1, "clk_hsic1", "dout_aclk_peri_66",
EN_IP_PERI0, 21, 0, 0),
GATE(PERI_CLK_HSIC2, "clk_hsic2", "dout_aclk_peri_66",
EN_IP_PERI0, 22, 0, 0),
GATE(PERI_CLK_HSIC3, "clk_hsic3", "dout_aclk_peri_66",
EN_IP_PERI0, 23, 0, 0),
GATE(PERI_CLK_WDT_EGL, "clk_wdt_egl", "dout_aclk_peri_66",
EN_IP_PERI0, 24, 0, 0),
GATE(PERI_CLK_WDT_KFC, "clk_wdt_kfc", "dout_aclk_peri_66",
EN_IP_PERI0, 25, 0, 0),
GATE(PERI_CLK_UART4, "clk_uart4", "dout_aclk_peri_66",
EN_IP_PERI2, 0, 0, 0),
GATE(PERI_CLK_PWM, "clk_pwm", "dout_aclk_peri_66",
EN_IP_PERI2, 3, 0, 0),
GATE(PERI_CLK_SPDIF, "clk_spdif", "dout_aclk_peri_66",
EN_IP_PERI2, 6, 0, 0),
GATE(PERI_CLK_SPI0, "clk_spi0", "dout_aclk_peri_66",
EN_IP_PERI2, 7, 0, 0),
GATE(PERI_CLK_SPI1, "clk_spi1", "dout_aclk_peri_66",
EN_IP_PERI2, 8, 0, 0),
GATE(PERI_CLK_SPI2, "clk_spi2", "dout_aclk_peri_66",
EN_IP_PERI2, 9, 0, 0),
GATE(PERI_CLK_TMU0, "clk_tmu0", "dout_aclk_peri_66",
EN_IP_PERI2, 10, 0, 0),
GATE(PERI_CLK_TMU1, "clk_tmu1", "dout_aclk_peri_66",
EN_IP_PERI2, 11, 0, 0),
GATE(PERI_CLK_TMU2, "clk_tmu2", "dout_aclk_peri_66",
EN_IP_PERI2, 12, 0, 0),
GATE(PERI_CLK_TMU3, "clk_tmu3", "dout_aclk_peri_66",
EN_IP_PERI2, 13, 0, 0),
GATE(PERI_CLK_TMU4, "clk_tmu4", "dout_aclk_peri_66",
EN_IP_PERI2, 14, 0, 0),
GATE(PERI_CLK_ADC, "clk_adc", "dout_aclk_peri_66",
EN_IP_PERI2, 18, 0, 0),
GATE(PERI_CLK_UART0, "clk_uart0", "dout_aclk_peri_66",
EN_IP_PERI2, 19, 0, 0),
GATE(PERI_CLK_UART1, "clk_uart1", "dout_aclk_peri_66",
EN_IP_PERI2, 20, 0, 0),
GATE(PERI_CLK_UART2, "clk_uart2", "dout_aclk_peri_66",
EN_IP_PERI2, 21, 0, 0),
GATE(PERI_CLK_CHIPID, "clk_chipid", "dout_aclk_peri_66",
EN_IP_PERI_SECURE_CHIPID, 2, 0, 0),
GATE(PERI_CLK_PROVKEY0, "clk_provkey0", "dout_aclk_peri_66",
EN_IP_PERI_SECURE_PROVKEY0, 1, 0, 0),
GATE(PERI_CLK_PROVKEY1, "clk_provkey1", "dout_aclk_peri_66",
EN_IP_PERI_SECURE_PROVKEY1, 2, 0, 0),
GATE(PERI_CLK_SECKEY, "clk_seckey", "dout_aclk_peri_66",
EN_IP_PERI_SECURE_SECKEY, 5, 0, 0),
GATE(PERI_CLK_TOP_RTC, "clk_top_rtc", "dout_aclk_peri_66",
EN_IP_PERI_SECURE_TOP_RTC, 5, 0, 0),
GATE(PERI_CLK_TZPC0, "clk_tzpc0", "dout_aclk_peri_66",
EN_IP_PERI_SECURE_TZPC, 10, 0, 0),
GATE(PERI_CLK_TZPC1, "clk_tzpc1", "dout_aclk_peri_66",
EN_IP_PERI_SECURE_TZPC, 11, 0, 0),
GATE(PERI_CLK_TZPC2, "clk_tzpc2", "dout_aclk_peri_66",
EN_IP_PERI_SECURE_TZPC, 12, 0, 0),
GATE(PERI_CLK_TZPC3, "clk_tzpc3", "dout_aclk_peri_66",
EN_IP_PERI_SECURE_TZPC, 13, 0, 0),
GATE(PERI_CLK_TZPC4, "clk_tzpc4", "dout_aclk_peri_66",
EN_IP_PERI_SECURE_TZPC, 14, 0, 0),
GATE(PERI_CLK_TZPC5, "clk_tzpc5", "dout_aclk_peri_66",
EN_IP_PERI_SECURE_TZPC, 15, 0, 0),
GATE(PERI_CLK_TZPC6, "clk_tzpc6", "dout_aclk_peri_66",
EN_IP_PERI_SECURE_TZPC, 16, 0, 0),
GATE(PERI_CLK_TZPC7, "clk_tzpc7", "dout_aclk_peri_66",
EN_IP_PERI_SECURE_TZPC, 17, 0, 0),
GATE(PERI_CLK_TZPC8, "clk_tzpc8", "dout_aclk_peri_66",
EN_IP_PERI_SECURE_TZPC, 18, 0, 0),
GATE(PERI_CLK_TZPC9, "clk_tzpc9", "dout_aclk_peri_66",
EN_IP_PERI_SECURE_TZPC, 19, 0, 0),
GATE(PERI_CLK_TZPC10, "clk_tzpc10", "dout_aclk_peri_66",
EN_IP_PERI_SECURE_TZPC, 20, 0, 0),
};
static const struct samsung_cmu_info peri_cmu __initconst = {
.mux_clks = peri_mux_clks,
.nr_mux_clks = ARRAY_SIZE(peri_mux_clks),
.div_clks = peri_div_clks,
.nr_div_clks = ARRAY_SIZE(peri_div_clks),
.gate_clks = peri_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
.nr_clk_ids = CLKS_NR_PERI,
.clk_regs = peri_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
};
static void __init exynos5260_clk_peri_init(struct device_node *np)
{
samsung_cmu_register_one(np, &peri_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_peri, "samsung,exynos5260-clock-peri",
exynos5260_clk_peri_init);
/* CMU_TOP */
static const unsigned long top_clk_regs[] __initconst = {
DISP_PLL_LOCK,
AUD_PLL_LOCK,
DISP_PLL_CON0,
DISP_PLL_CON1,
DISP_PLL_FDET,
AUD_PLL_CON0,
AUD_PLL_CON1,
AUD_PLL_CON2,
AUD_PLL_FDET,
MUX_SEL_TOP_PLL0,
MUX_SEL_TOP_MFC,
MUX_SEL_TOP_G2D,
MUX_SEL_TOP_GSCL,
MUX_SEL_TOP_ISP10,
MUX_SEL_TOP_ISP11,
MUX_SEL_TOP_DISP0,
MUX_SEL_TOP_DISP1,
MUX_SEL_TOP_BUS,
MUX_SEL_TOP_PERI0,
MUX_SEL_TOP_PERI1,
MUX_SEL_TOP_FSYS,
DIV_TOP_G2D_MFC,
DIV_TOP_GSCL_ISP0,
DIV_TOP_ISP10,
DIV_TOP_ISP11,
DIV_TOP_DISP,
DIV_TOP_BUS,
DIV_TOP_PERI0,
DIV_TOP_PERI1,
DIV_TOP_PERI2,
DIV_TOP_FSYS0,
DIV_TOP_FSYS1,
DIV_TOP_HPM,
DIV_TOP_PLL_FDET,
EN_ACLK_TOP,
EN_SCLK_TOP,
EN_IP_TOP,
};
/* fixed rate clocks generated inside the soc */
static const struct samsung_fixed_rate_clock fixed_rate_clks[] __initconst = {
FRATE(PHYCLK_DPTX_PHY_CH3_TXD_CLK, "phyclk_dptx_phy_ch3_txd_clk", NULL,
0, 270000000),
FRATE(PHYCLK_DPTX_PHY_CH2_TXD_CLK, "phyclk_dptx_phy_ch2_txd_clk", NULL,
0, 270000000),
FRATE(PHYCLK_DPTX_PHY_CH1_TXD_CLK, "phyclk_dptx_phy_ch1_txd_clk", NULL,
0, 270000000),
FRATE(PHYCLK_DPTX_PHY_CH0_TXD_CLK, "phyclk_dptx_phy_ch0_txd_clk", NULL,
0, 270000000),
FRATE(phyclk_hdmi_phy_tmds_clko, "phyclk_hdmi_phy_tmds_clko", NULL,
0, 250000000),
FRATE(PHYCLK_HDMI_PHY_PIXEL_CLKO, "phyclk_hdmi_phy_pixel_clko", NULL,
0, 1660000000),
FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi",
NULL, 0, 125000000),
FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS,
"phyclk_mipi_dphy_4l_m_txbyte_clkhs" , NULL,
0, 187500000),
FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m",
NULL, 0, 24000000),
FRATE(PHYCLK_DPTX_PHY_CLK_DIV2, "phyclk_dptx_phy_clk_div2", NULL,
0, 135000000),
FRATE(PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0,
"phyclk_mipi_dphy_4l_m_rxclkesc0", NULL, 0, 20000000),
FRATE(PHYCLK_USBHOST20_PHY_PHYCLOCK, "phyclk_usbhost20_phy_phyclock",
NULL, 0, 60000000),
FRATE(PHYCLK_USBHOST20_PHY_FREECLK, "phyclk_usbhost20_phy_freeclk",
NULL, 0, 60000000),
FRATE(PHYCLK_USBHOST20_PHY_CLK48MOHCI,
"phyclk_usbhost20_phy_clk48mohci", NULL, 0, 48000000),
FRATE(PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
"phyclk_usbdrd30_udrd30_pipe_pclk", NULL, 0, 125000000),
FRATE(PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
"phyclk_usbdrd30_udrd30_phyclock", NULL, 0, 60000000),
};
PNAME(mout_memtop_pll_user_p) = {"fin_pll", "dout_mem_pll"};
PNAME(mout_bustop_pll_user_p) = {"fin_pll", "dout_bus_pll"};
PNAME(mout_mediatop_pll_user_p) = {"fin_pll", "dout_media_pll"};
PNAME(mout_audtop_pll_user_p) = {"fin_pll", "mout_aud_pll"};
PNAME(mout_aud_pll_p) = {"fin_pll", "fout_aud_pll"};
PNAME(mout_disp_pll_p) = {"fin_pll", "fout_disp_pll"};
PNAME(mout_mfc_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
PNAME(mout_aclk_mfc_333_p) = {"mout_mediatop_pll_user", "mout_mfc_bustop_333"};
PNAME(mout_g2d_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
PNAME(mout_aclk_g2d_333_p) = {"mout_mediatop_pll_user", "mout_g2d_bustop_333"};
PNAME(mout_gscl_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
PNAME(mout_aclk_gscl_333_p) = {"mout_mediatop_pll_user",
"mout_gscl_bustop_333"};
PNAME(mout_m2m_mediatop_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"};
PNAME(mout_aclk_gscl_400_p) = {"mout_bustop_pll_user",
"mout_m2m_mediatop_400"};
PNAME(mout_gscl_bustop_fimc_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
PNAME(mout_aclk_gscl_fimc_p) = {"mout_mediatop_pll_user",
"mout_gscl_bustop_fimc"};
PNAME(mout_isp1_media_266_p) = {"mout_mediatop_pll_user",
"mout_memtop_pll_user"};
PNAME(mout_aclk_isp1_266_p) = {"mout_bustop_pll_user", "mout_isp1_media_266"};
PNAME(mout_isp1_media_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"};
PNAME(mout_aclk_isp1_400_p) = {"mout_bustop_pll_user", "mout_isp1_media_400"};
PNAME(mout_sclk_isp_spi_p) = {"fin_pll", "mout_bustop_pll_user"};
PNAME(mout_sclk_isp_uart_p) = {"fin_pll", "mout_bustop_pll_user"};
PNAME(mout_sclk_isp_sensor_p) = {"fin_pll", "mout_bustop_pll_user"};
PNAME(mout_disp_disp_333_p) = {"mout_disp_pll", "mout_bustop_pll_user"};
PNAME(mout_aclk_disp_333_p) = {"mout_mediatop_pll_user", "mout_disp_disp_333"};
PNAME(mout_disp_disp_222_p) = {"mout_disp_pll", "mout_bustop_pll_user"};
PNAME(mout_aclk_disp_222_p) = {"mout_mediatop_pll_user", "mout_disp_disp_222"};
PNAME(mout_disp_media_pixel_p) = {"mout_mediatop_pll_user",
"mout_bustop_pll_user"};
PNAME(mout_sclk_disp_pixel_p) = {"mout_disp_pll", "mout_disp_media_pixel"};
PNAME(mout_bus_bustop_400_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"};
PNAME(mout_bus_bustop_100_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"};
PNAME(mout_sclk_peri_spi_clk_p) = {"fin_pll", "mout_bustop_pll_user"};
PNAME(mout_sclk_peri_uart_uclk_p) = {"fin_pll", "mout_bustop_pll_user"};
PNAME(mout_sclk_fsys_usb_p) = {"fin_pll", "mout_bustop_pll_user"};
PNAME(mout_sclk_fsys_mmc_sdclkin_a_p) = {"fin_pll", "mout_bustop_pll_user"};
PNAME(mout_sclk_fsys_mmc0_sdclkin_b_p) = {"mout_sclk_fsys_mmc0_sdclkin_a",
"mout_mediatop_pll_user"};
PNAME(mout_sclk_fsys_mmc1_sdclkin_b_p) = {"mout_sclk_fsys_mmc1_sdclkin_a",
"mout_mediatop_pll_user"};
PNAME(mout_sclk_fsys_mmc2_sdclkin_b_p) = {"mout_sclk_fsys_mmc2_sdclkin_a",
"mout_mediatop_pll_user"};
static const struct samsung_mux_clock top_mux_clks[] __initconst = {
MUX(TOP_MOUT_MEDIATOP_PLL_USER, "mout_mediatop_pll_user",
mout_mediatop_pll_user_p,
MUX_SEL_TOP_PLL0, 0, 1),
MUX(TOP_MOUT_MEMTOP_PLL_USER, "mout_memtop_pll_user",
mout_memtop_pll_user_p,
MUX_SEL_TOP_PLL0, 4, 1),
MUX(TOP_MOUT_BUSTOP_PLL_USER, "mout_bustop_pll_user",
mout_bustop_pll_user_p,
MUX_SEL_TOP_PLL0, 8, 1),
MUX(TOP_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p,
MUX_SEL_TOP_PLL0, 12, 1),
MUX(TOP_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p,
MUX_SEL_TOP_PLL0, 16, 1),
MUX(TOP_MOUT_AUDTOP_PLL_USER, "mout_audtop_pll_user",
mout_audtop_pll_user_p,
MUX_SEL_TOP_PLL0, 24, 1),
MUX(TOP_MOUT_DISP_DISP_333, "mout_disp_disp_333", mout_disp_disp_333_p,
MUX_SEL_TOP_DISP0, 0, 1),
MUX(TOP_MOUT_ACLK_DISP_333, "mout_aclk_disp_333", mout_aclk_disp_333_p,
MUX_SEL_TOP_DISP0, 8, 1),
MUX(TOP_MOUT_DISP_DISP_222, "mout_disp_disp_222", mout_disp_disp_222_p,
MUX_SEL_TOP_DISP0, 12, 1),
MUX(TOP_MOUT_ACLK_DISP_222, "mout_aclk_disp_222", mout_aclk_disp_222_p,
MUX_SEL_TOP_DISP0, 20, 1),
MUX(TOP_MOUT_FIMD1, "mout_sclk_disp_pixel", mout_sclk_disp_pixel_p,
MUX_SEL_TOP_DISP1, 0, 1),
MUX(TOP_MOUT_DISP_MEDIA_PIXEL, "mout_disp_media_pixel",
mout_disp_media_pixel_p,
MUX_SEL_TOP_DISP1, 8, 1),
MUX(TOP_MOUT_SCLK_PERI_SPI2_CLK, "mout_sclk_peri_spi2_clk",
mout_sclk_peri_spi_clk_p,
MUX_SEL_TOP_PERI1, 0, 1),
MUX(TOP_MOUT_SCLK_PERI_SPI1_CLK, "mout_sclk_peri_spi1_clk",
mout_sclk_peri_spi_clk_p,
MUX_SEL_TOP_PERI1, 4, 1),
MUX(TOP_MOUT_SCLK_PERI_SPI0_CLK, "mout_sclk_peri_spi0_clk",
mout_sclk_peri_spi_clk_p,
MUX_SEL_TOP_PERI1, 8, 1),
MUX(TOP_MOUT_SCLK_PERI_UART1_UCLK, "mout_sclk_peri_uart1_uclk",
mout_sclk_peri_uart_uclk_p,
MUX_SEL_TOP_PERI1, 12, 1),
MUX(TOP_MOUT_SCLK_PERI_UART2_UCLK, "mout_sclk_peri_uart2_uclk",
mout_sclk_peri_uart_uclk_p,
MUX_SEL_TOP_PERI1, 16, 1),
MUX(TOP_MOUT_SCLK_PERI_UART0_UCLK, "mout_sclk_peri_uart0_uclk",
mout_sclk_peri_uart_uclk_p,
MUX_SEL_TOP_PERI1, 20, 1),
MUX(TOP_MOUT_BUS1_BUSTOP_400, "mout_bus1_bustop_400",
mout_bus_bustop_400_p,
MUX_SEL_TOP_BUS, 0, 1),
MUX(TOP_MOUT_BUS1_BUSTOP_100, "mout_bus1_bustop_100",
mout_bus_bustop_100_p,
MUX_SEL_TOP_BUS, 4, 1),
MUX(TOP_MOUT_BUS2_BUSTOP_100, "mout_bus2_bustop_100",
mout_bus_bustop_100_p,
MUX_SEL_TOP_BUS, 8, 1),
MUX(TOP_MOUT_BUS2_BUSTOP_400, "mout_bus2_bustop_400",
mout_bus_bustop_400_p,
MUX_SEL_TOP_BUS, 12, 1),
MUX(TOP_MOUT_BUS3_BUSTOP_400, "mout_bus3_bustop_400",
mout_bus_bustop_400_p,
MUX_SEL_TOP_BUS, 16, 1),
MUX(TOP_MOUT_BUS3_BUSTOP_100, "mout_bus3_bustop_100",
mout_bus_bustop_100_p,
MUX_SEL_TOP_BUS, 20, 1),
MUX(TOP_MOUT_BUS4_BUSTOP_400, "mout_bus4_bustop_400",
mout_bus_bustop_400_p,
MUX_SEL_TOP_BUS, 24, 1),
MUX(TOP_MOUT_BUS4_BUSTOP_100, "mout_bus4_bustop_100",
mout_bus_bustop_100_p,
MUX_SEL_TOP_BUS, 28, 1),
MUX(TOP_MOUT_SCLK_FSYS_USB, "mout_sclk_fsys_usb",
mout_sclk_fsys_usb_p,
MUX_SEL_TOP_FSYS, 0, 1),
MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "mout_sclk_fsys_mmc2_sdclkin_a",
mout_sclk_fsys_mmc_sdclkin_a_p,
MUX_SEL_TOP_FSYS, 4, 1),
MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "mout_sclk_fsys_mmc2_sdclkin_b",
mout_sclk_fsys_mmc2_sdclkin_b_p,
MUX_SEL_TOP_FSYS, 8, 1),
MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "mout_sclk_fsys_mmc1_sdclkin_a",
mout_sclk_fsys_mmc_sdclkin_a_p,
MUX_SEL_TOP_FSYS, 12, 1),
MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "mout_sclk_fsys_mmc1_sdclkin_b",
mout_sclk_fsys_mmc1_sdclkin_b_p,
MUX_SEL_TOP_FSYS, 16, 1),
MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "mout_sclk_fsys_mmc0_sdclkin_a",
mout_sclk_fsys_mmc_sdclkin_a_p,
MUX_SEL_TOP_FSYS, 20, 1),
MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "mout_sclk_fsys_mmc0_sdclkin_b",
mout_sclk_fsys_mmc0_sdclkin_b_p,
MUX_SEL_TOP_FSYS, 24, 1),
MUX(TOP_MOUT_ISP1_MEDIA_400, "mout_isp1_media_400",
mout_isp1_media_400_p,
MUX_SEL_TOP_ISP10, 4, 1),
MUX(TOP_MOUT_ACLK_ISP1_400, "mout_aclk_isp1_400", mout_aclk_isp1_400_p,
MUX_SEL_TOP_ISP10, 8 , 1),
MUX(TOP_MOUT_ISP1_MEDIA_266, "mout_isp1_media_266",
mout_isp1_media_266_p,
MUX_SEL_TOP_ISP10, 16, 1),
MUX(TOP_MOUT_ACLK_ISP1_266, "mout_aclk_isp1_266", mout_aclk_isp1_266_p,
MUX_SEL_TOP_ISP10, 20, 1),
MUX(TOP_MOUT_SCLK_ISP1_SPI0, "mout_sclk_isp1_spi0", mout_sclk_isp_spi_p,
MUX_SEL_TOP_ISP11, 4, 1),
MUX(TOP_MOUT_SCLK_ISP1_SPI1, "mout_sclk_isp1_spi1", mout_sclk_isp_spi_p,
MUX_SEL_TOP_ISP11, 8, 1),
MUX(TOP_MOUT_SCLK_ISP1_UART, "mout_sclk_isp1_uart",
mout_sclk_isp_uart_p,
MUX_SEL_TOP_ISP11, 12, 1),
MUX(TOP_MOUT_SCLK_ISP1_SENSOR0, "mout_sclk_isp1_sensor0",
mout_sclk_isp_sensor_p,
MUX_SEL_TOP_ISP11, 16, 1),
MUX(TOP_MOUT_SCLK_ISP1_SENSOR1, "mout_sclk_isp1_sensor1",
mout_sclk_isp_sensor_p,
MUX_SEL_TOP_ISP11, 20, 1),
MUX(TOP_MOUT_SCLK_ISP1_SENSOR2, "mout_sclk_isp1_sensor2",
mout_sclk_isp_sensor_p,
MUX_SEL_TOP_ISP11, 24, 1),
MUX(TOP_MOUT_MFC_BUSTOP_333, "mout_mfc_bustop_333",
mout_mfc_bustop_333_p,
MUX_SEL_TOP_MFC, 4, 1),
MUX(TOP_MOUT_ACLK_MFC_333, "mout_aclk_mfc_333", mout_aclk_mfc_333_p,
MUX_SEL_TOP_MFC, 8, 1),
MUX(TOP_MOUT_G2D_BUSTOP_333, "mout_g2d_bustop_333",
mout_g2d_bustop_333_p,
MUX_SEL_TOP_G2D, 4, 1),
MUX(TOP_MOUT_ACLK_G2D_333, "mout_aclk_g2d_333", mout_aclk_g2d_333_p,
MUX_SEL_TOP_G2D, 8, 1),
MUX(TOP_MOUT_M2M_MEDIATOP_400, "mout_m2m_mediatop_400",
mout_m2m_mediatop_400_p,
MUX_SEL_TOP_GSCL, 0, 1),
MUX(TOP_MOUT_ACLK_GSCL_400, "mout_aclk_gscl_400",
mout_aclk_gscl_400_p,
MUX_SEL_TOP_GSCL, 4, 1),
MUX(TOP_MOUT_GSCL_BUSTOP_333, "mout_gscl_bustop_333",
mout_gscl_bustop_333_p,
MUX_SEL_TOP_GSCL, 8, 1),
MUX(TOP_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
mout_aclk_gscl_333_p,
MUX_SEL_TOP_GSCL, 12, 1),
MUX(TOP_MOUT_GSCL_BUSTOP_FIMC, "mout_gscl_bustop_fimc",
mout_gscl_bustop_fimc_p,
MUX_SEL_TOP_GSCL, 16, 1),
MUX(TOP_MOUT_ACLK_GSCL_FIMC, "mout_aclk_gscl_fimc",
mout_aclk_gscl_fimc_p,
MUX_SEL_TOP_GSCL, 20, 1),
};
static const struct samsung_div_clock top_div_clks[] __initconst = {
DIV(TOP_DOUT_ACLK_G2D_333, "dout_aclk_g2d_333", "mout_aclk_g2d_333",
DIV_TOP_G2D_MFC, 0, 3),
DIV(TOP_DOUT_ACLK_MFC_333, "dout_aclk_mfc_333", "mout_aclk_mfc_333",
DIV_TOP_G2D_MFC, 4, 3),
DIV(TOP_DOUT_ACLK_GSCL_333, "dout_aclk_gscl_333", "mout_aclk_gscl_333",
DIV_TOP_GSCL_ISP0, 0, 3),
DIV(TOP_DOUT_ACLK_GSCL_400, "dout_aclk_gscl_400", "mout_aclk_gscl_400",
DIV_TOP_GSCL_ISP0, 4, 3),
DIV(TOP_DOUT_ACLK_GSCL_FIMC, "dout_aclk_gscl_fimc",
"mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 8, 3),
DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_A, "dout_sclk_isp1_sensor0_a",
"mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 16, 4),
DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_A, "dout_sclk_isp1_sensor1_a",
"mout_aclk_gscl_400", DIV_TOP_GSCL_ISP0, 20, 4),
DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_A, "dout_sclk_isp1_sensor2_a",
"mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 24, 4),
DIV(TOP_DOUT_ACLK_ISP1_266, "dout_aclk_isp1_266", "mout_aclk_isp1_266",
DIV_TOP_ISP10, 0, 3),
DIV(TOP_DOUT_ACLK_ISP1_400, "dout_aclk_isp1_400", "mout_aclk_isp1_400",
DIV_TOP_ISP10, 4, 3),
DIV(TOP_DOUT_SCLK_ISP1_SPI0_A, "dout_sclk_isp1_spi0_a",
"mout_sclk_isp1_spi0", DIV_TOP_ISP10, 12, 4),
DIV(TOP_DOUT_SCLK_ISP1_SPI0_B, "dout_sclk_isp1_spi0_b",
"dout_sclk_isp1_spi0_a", DIV_TOP_ISP10, 16, 8),
DIV(TOP_DOUT_SCLK_ISP1_SPI1_A, "dout_sclk_isp1_spi1_a",
"mout_sclk_isp1_spi1", DIV_TOP_ISP11, 0, 4),
DIV(TOP_DOUT_SCLK_ISP1_SPI1_B, "dout_sclk_isp1_spi1_b",
"dout_sclk_isp1_spi1_a", DIV_TOP_ISP11, 4, 8),
DIV(TOP_DOUT_SCLK_ISP1_UART, "dout_sclk_isp1_uart",
"mout_sclk_isp1_uart", DIV_TOP_ISP11, 12, 4),
DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_B, "dout_sclk_isp1_sensor0_b",
"dout_sclk_isp1_sensor0_a", DIV_TOP_ISP11, 16, 4),
DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_B, "dout_sclk_isp1_sensor1_b",
"dout_sclk_isp1_sensor1_a", DIV_TOP_ISP11, 20, 4),
DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_B, "dout_sclk_isp1_sensor2_b",
"dout_sclk_isp1_sensor2_a", DIV_TOP_ISP11, 24, 4),
DIV(TOP_DOUTTOP__SCLK_HPM_TARGETCLK, "dout_sclk_hpm_targetclk",
"mout_bustop_pll_user", DIV_TOP_HPM, 0, 3),
DIV(TOP_DOUT_ACLK_DISP_333, "dout_aclk_disp_333", "mout_aclk_disp_333",
DIV_TOP_DISP, 0, 3),
DIV(TOP_DOUT_ACLK_DISP_222, "dout_aclk_disp_222", "mout_aclk_disp_222",
DIV_TOP_DISP, 4, 3),
DIV(TOP_DOUT_SCLK_DISP_PIXEL, "dout_sclk_disp_pixel",
"mout_sclk_disp_pixel", DIV_TOP_DISP, 8, 3),
DIV(TOP_DOUT_ACLK_BUS1_400, "dout_aclk_bus1_400",
"mout_bus1_bustop_400", DIV_TOP_BUS, 0, 3),
DIV(TOP_DOUT_ACLK_BUS1_100, "dout_aclk_bus1_100",
"mout_bus1_bustop_100", DIV_TOP_BUS, 4, 4),
DIV(TOP_DOUT_ACLK_BUS2_400, "dout_aclk_bus2_400",
"mout_bus2_bustop_400", DIV_TOP_BUS, 8, 3),
DIV(TOP_DOUT_ACLK_BUS2_100, "dout_aclk_bus2_100",
"mout_bus2_bustop_100", DIV_TOP_BUS, 12, 4),
DIV(TOP_DOUT_ACLK_BUS3_400, "dout_aclk_bus3_400",
"mout_bus3_bustop_400", DIV_TOP_BUS, 16, 3),
DIV(TOP_DOUT_ACLK_BUS3_100, "dout_aclk_bus3_100",
"mout_bus3_bustop_100", DIV_TOP_BUS, 20, 4),
DIV(TOP_DOUT_ACLK_BUS4_400, "dout_aclk_bus4_400",
"mout_bus4_bustop_400", DIV_TOP_BUS, 24, 3),
DIV(TOP_DOUT_ACLK_BUS4_100, "dout_aclk_bus4_100",
"mout_bus4_bustop_100", DIV_TOP_BUS, 28, 4),
DIV(TOP_DOUT_SCLK_PERI_SPI0_A, "dout_sclk_peri_spi0_a",
"mout_sclk_peri_spi0_clk", DIV_TOP_PERI0, 4, 4),
DIV(TOP_DOUT_SCLK_PERI_SPI0_B, "dout_sclk_peri_spi0_b",
"dout_sclk_peri_spi0_a", DIV_TOP_PERI0, 8, 8),
DIV(TOP_DOUT_SCLK_PERI_SPI1_A, "dout_sclk_peri_spi1_a",
"mout_sclk_peri_spi1_clk", DIV_TOP_PERI0, 16, 4),
DIV(TOP_DOUT_SCLK_PERI_SPI1_B, "dout_sclk_peri_spi1_b",
"dout_sclk_peri_spi1_a", DIV_TOP_PERI0, 20, 8),
DIV(TOP_DOUT_SCLK_PERI_SPI2_A, "dout_sclk_peri_spi2_a",
"mout_sclk_peri_spi2_clk", DIV_TOP_PERI1, 0, 4),
DIV(TOP_DOUT_SCLK_PERI_SPI2_B, "dout_sclk_peri_spi2_b",
"dout_sclk_peri_spi2_a", DIV_TOP_PERI1, 4, 8),
DIV(TOP_DOUT_SCLK_PERI_UART1, "dout_sclk_peri_uart1",
"mout_sclk_peri_uart1_uclk", DIV_TOP_PERI1, 16, 4),
DIV(TOP_DOUT_SCLK_PERI_UART2, "dout_sclk_peri_uart2",
"mout_sclk_peri_uart2_uclk", DIV_TOP_PERI1, 20, 4),
DIV(TOP_DOUT_SCLK_PERI_UART0, "dout_sclk_peri_uart0",
"mout_sclk_peri_uart0_uclk", DIV_TOP_PERI1, 24, 4),
DIV(TOP_DOUT_ACLK_PERI_66, "dout_aclk_peri_66", "mout_bustop_pll_user",
DIV_TOP_PERI2, 20, 4),
DIV(TOP_DOUT_ACLK_PERI_AUD, "dout_aclk_peri_aud",
"mout_audtop_pll_user", DIV_TOP_PERI2, 24, 3),
DIV(TOP_DOUT_ACLK_FSYS_200, "dout_aclk_fsys_200",
"mout_bustop_pll_user", DIV_TOP_FSYS0, 0, 3),
DIV(TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK,
"dout_sclk_fsys_usbdrd30_suspend_clk",
"mout_sclk_fsys_usb", DIV_TOP_FSYS0, 4, 4),
DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "dout_sclk_fsys_mmc0_sdclkin_a",
"mout_sclk_fsys_mmc0_sdclkin_b",
DIV_TOP_FSYS0, 12, 4),
DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "dout_sclk_fsys_mmc0_sdclkin_b",
"dout_sclk_fsys_mmc0_sdclkin_a",
DIV_TOP_FSYS0, 16, 8),
DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "dout_sclk_fsys_mmc1_sdclkin_a",
"mout_sclk_fsys_mmc1_sdclkin_b",
DIV_TOP_FSYS1, 0, 4),
DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "dout_sclk_fsys_mmc1_sdclkin_b",
"dout_sclk_fsys_mmc1_sdclkin_a",
DIV_TOP_FSYS1, 4, 8),
DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "dout_sclk_fsys_mmc2_sdclkin_a",
"mout_sclk_fsys_mmc2_sdclkin_b",
DIV_TOP_FSYS1, 12, 4),
DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "dout_sclk_fsys_mmc2_sdclkin_b",
"dout_sclk_fsys_mmc2_sdclkin_a",
DIV_TOP_FSYS1, 16, 8),
};
static const struct samsung_gate_clock top_gate_clks[] __initconst = {
GATE(TOP_SCLK_MMC0, "sclk_fsys_mmc0_sdclkin",
"dout_sclk_fsys_mmc0_sdclkin_b",
EN_SCLK_TOP, 7, CLK_SET_RATE_PARENT, 0),
GATE(TOP_SCLK_MMC1, "sclk_fsys_mmc1_sdclkin",
"dout_sclk_fsys_mmc1_sdclkin_b",
EN_SCLK_TOP, 8, CLK_SET_RATE_PARENT, 0),
GATE(TOP_SCLK_MMC2, "sclk_fsys_mmc2_sdclkin",
"dout_sclk_fsys_mmc2_sdclkin_b",
EN_SCLK_TOP, 9, CLK_SET_RATE_PARENT, 0),
GATE(TOP_SCLK_FIMD1, "sclk_disp_pixel", "dout_sclk_disp_pixel",
EN_ACLK_TOP, 10, CLK_IGNORE_UNUSED |
CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_pll_clock top_pll_clks[] __initconst = {
PLL(pll_2550xx, TOP_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll",
DISP_PLL_LOCK, DISP_PLL_CON0,
pll2550_24mhz_tbl),
PLL(pll_2650xx, TOP_FOUT_AUD_PLL, "fout_aud_pll", "fin_pll",
AUD_PLL_LOCK, AUD_PLL_CON0,
pll2650_24mhz_tbl),
};
static const struct samsung_cmu_info top_cmu __initconst = {
.pll_clks = top_pll_clks,
.nr_pll_clks = ARRAY_SIZE(top_pll_clks),
.mux_clks = top_mux_clks,
.nr_mux_clks = ARRAY_SIZE(top_mux_clks),
.div_clks = top_div_clks,
.nr_div_clks = ARRAY_SIZE(top_div_clks),
.gate_clks = top_gate_clks,
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
.fixed_clks = fixed_rate_clks,
.nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks),
.nr_clk_ids = CLKS_NR_TOP,
.clk_regs = top_clk_regs,
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
};
static void __init exynos5260_clk_top_init(struct device_node *np)
{
samsung_cmu_register_one(np, &top_cmu);
}
CLK_OF_DECLARE(exynos5260_clk_top, "samsung,exynos5260-clock-top",
exynos5260_clk_top_init);
| linux-master | drivers/clk/samsung/clk-exynos5260.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Authors: Thomas Abraham <[email protected]>
* Chander Kashyap <[email protected]>
*
* Common Clock Framework support for Exynos5420 SoC.
*/
#include <dt-bindings/clock/exynos5420.h>
#include <linux/slab.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk.h>
#include "clk.h"
#include "clk-cpu.h"
#include "clk-exynos5-subcmu.h"
#define APLL_LOCK 0x0
#define APLL_CON0 0x100
#define SRC_CPU 0x200
#define DIV_CPU0 0x500
#define DIV_CPU1 0x504
#define GATE_BUS_CPU 0x700
#define GATE_SCLK_CPU 0x800
#define CLKOUT_CMU_CPU 0xa00
#define SRC_MASK_CPERI 0x4300
#define GATE_IP_G2D 0x8800
#define CPLL_LOCK 0x10020
#define DPLL_LOCK 0x10030
#define EPLL_LOCK 0x10040
#define RPLL_LOCK 0x10050
#define IPLL_LOCK 0x10060
#define SPLL_LOCK 0x10070
#define VPLL_LOCK 0x10080
#define MPLL_LOCK 0x10090
#define CPLL_CON0 0x10120
#define DPLL_CON0 0x10128
#define EPLL_CON0 0x10130
#define EPLL_CON1 0x10134
#define EPLL_CON2 0x10138
#define RPLL_CON0 0x10140
#define RPLL_CON1 0x10144
#define RPLL_CON2 0x10148
#define IPLL_CON0 0x10150
#define SPLL_CON0 0x10160
#define VPLL_CON0 0x10170
#define MPLL_CON0 0x10180
#define SRC_TOP0 0x10200
#define SRC_TOP1 0x10204
#define SRC_TOP2 0x10208
#define SRC_TOP3 0x1020c
#define SRC_TOP4 0x10210
#define SRC_TOP5 0x10214
#define SRC_TOP6 0x10218
#define SRC_TOP7 0x1021c
#define SRC_TOP8 0x10220 /* 5800 specific */
#define SRC_TOP9 0x10224 /* 5800 specific */
#define SRC_DISP10 0x1022c
#define SRC_MAU 0x10240
#define SRC_FSYS 0x10244
#define SRC_PERIC0 0x10250
#define SRC_PERIC1 0x10254
#define SRC_ISP 0x10270
#define SRC_CAM 0x10274 /* 5800 specific */
#define SRC_TOP10 0x10280
#define SRC_TOP11 0x10284
#define SRC_TOP12 0x10288
#define SRC_TOP13 0x1028c /* 5800 specific */
#define SRC_MASK_TOP0 0x10300
#define SRC_MASK_TOP1 0x10304
#define SRC_MASK_TOP2 0x10308
#define SRC_MASK_TOP7 0x1031c
#define SRC_MASK_DISP10 0x1032c
#define SRC_MASK_MAU 0x10334
#define SRC_MASK_FSYS 0x10340
#define SRC_MASK_PERIC0 0x10350
#define SRC_MASK_PERIC1 0x10354
#define SRC_MASK_ISP 0x10370
#define DIV_TOP0 0x10500
#define DIV_TOP1 0x10504
#define DIV_TOP2 0x10508
#define DIV_TOP8 0x10520 /* 5800 specific */
#define DIV_TOP9 0x10524 /* 5800 specific */
#define DIV_DISP10 0x1052c
#define DIV_MAU 0x10544
#define DIV_FSYS0 0x10548
#define DIV_FSYS1 0x1054c
#define DIV_FSYS2 0x10550
#define DIV_PERIC0 0x10558
#define DIV_PERIC1 0x1055c
#define DIV_PERIC2 0x10560
#define DIV_PERIC3 0x10564
#define DIV_PERIC4 0x10568
#define DIV_CAM 0x10574 /* 5800 specific */
#define SCLK_DIV_ISP0 0x10580
#define SCLK_DIV_ISP1 0x10584
#define DIV2_RATIO0 0x10590
#define DIV4_RATIO 0x105a0
#define GATE_BUS_TOP 0x10700
#define GATE_BUS_DISP1 0x10728
#define GATE_BUS_GEN 0x1073c
#define GATE_BUS_FSYS0 0x10740
#define GATE_BUS_FSYS2 0x10748
#define GATE_BUS_PERIC 0x10750
#define GATE_BUS_PERIC1 0x10754
#define GATE_BUS_PERIS0 0x10760
#define GATE_BUS_PERIS1 0x10764
#define GATE_BUS_NOC 0x10770
#define GATE_TOP_SCLK_ISP 0x10870
#define GATE_IP_GSCL0 0x10910
#define GATE_IP_GSCL1 0x10920
#define GATE_IP_CAM 0x10924 /* 5800 specific */
#define GATE_IP_MFC 0x1092c
#define GATE_IP_DISP1 0x10928
#define GATE_IP_G3D 0x10930
#define GATE_IP_GEN 0x10934
#define GATE_IP_FSYS 0x10944
#define GATE_IP_PERIC 0x10950
#define GATE_IP_PERIS 0x10960
#define GATE_IP_MSCL 0x10970
#define GATE_TOP_SCLK_GSCL 0x10820
#define GATE_TOP_SCLK_DISP1 0x10828
#define GATE_TOP_SCLK_MAU 0x1083c
#define GATE_TOP_SCLK_FSYS 0x10840
#define GATE_TOP_SCLK_PERIC 0x10850
#define TOP_SPARE2 0x10b08
#define BPLL_LOCK 0x20010
#define BPLL_CON0 0x20110
#define SRC_CDREX 0x20200
#define DIV_CDREX0 0x20500
#define DIV_CDREX1 0x20504
#define GATE_BUS_CDREX0 0x20700
#define GATE_BUS_CDREX1 0x20704
#define KPLL_LOCK 0x28000
#define KPLL_CON0 0x28100
#define SRC_KFC 0x28200
#define DIV_KFC0 0x28500
/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR (CLK_DOUT_PCLK_DREX1 + 1)
/* Exynos5x SoC type */
enum exynos5x_soc {
EXYNOS5420,
EXYNOS5800,
};
/* list of PLLs */
enum exynos5x_plls {
apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
bpll, kpll,
nr_plls /* number of PLLs */
};
static void __iomem *reg_base;
static enum exynos5x_soc exynos5x_soc;
/*
* list of controller registers to be saved and restored during a
* suspend/resume cycle.
*/
static const unsigned long exynos5x_clk_regs[] __initconst = {
SRC_CPU,
DIV_CPU0,
DIV_CPU1,
GATE_BUS_CPU,
GATE_SCLK_CPU,
CLKOUT_CMU_CPU,
APLL_CON0,
KPLL_CON0,
CPLL_CON0,
DPLL_CON0,
EPLL_CON0,
EPLL_CON1,
EPLL_CON2,
RPLL_CON0,
RPLL_CON1,
RPLL_CON2,
IPLL_CON0,
SPLL_CON0,
VPLL_CON0,
MPLL_CON0,
SRC_TOP0,
SRC_TOP1,
SRC_TOP2,
SRC_TOP3,
SRC_TOP4,
SRC_TOP5,
SRC_TOP6,
SRC_TOP7,
SRC_DISP10,
SRC_MAU,
SRC_FSYS,
SRC_PERIC0,
SRC_PERIC1,
SRC_TOP10,
SRC_TOP11,
SRC_TOP12,
SRC_MASK_TOP2,
SRC_MASK_TOP7,
SRC_MASK_DISP10,
SRC_MASK_FSYS,
SRC_MASK_PERIC0,
SRC_MASK_PERIC1,
SRC_MASK_TOP0,
SRC_MASK_TOP1,
SRC_MASK_MAU,
SRC_MASK_ISP,
SRC_ISP,
DIV_TOP0,
DIV_TOP1,
DIV_TOP2,
DIV_DISP10,
DIV_MAU,
DIV_FSYS0,
DIV_FSYS1,
DIV_FSYS2,
DIV_PERIC0,
DIV_PERIC1,
DIV_PERIC2,
DIV_PERIC3,
DIV_PERIC4,
SCLK_DIV_ISP0,
SCLK_DIV_ISP1,
DIV2_RATIO0,
DIV4_RATIO,
GATE_BUS_DISP1,
GATE_BUS_TOP,
GATE_BUS_GEN,
GATE_BUS_FSYS0,
GATE_BUS_FSYS2,
GATE_BUS_PERIC,
GATE_BUS_PERIC1,
GATE_BUS_PERIS0,
GATE_BUS_PERIS1,
GATE_BUS_NOC,
GATE_TOP_SCLK_ISP,
GATE_IP_GSCL0,
GATE_IP_GSCL1,
GATE_IP_MFC,
GATE_IP_DISP1,
GATE_IP_G3D,
GATE_IP_GEN,
GATE_IP_FSYS,
GATE_IP_PERIC,
GATE_IP_PERIS,
GATE_IP_MSCL,
GATE_TOP_SCLK_GSCL,
GATE_TOP_SCLK_DISP1,
GATE_TOP_SCLK_MAU,
GATE_TOP_SCLK_FSYS,
GATE_TOP_SCLK_PERIC,
TOP_SPARE2,
SRC_CDREX,
DIV_CDREX0,
DIV_CDREX1,
SRC_KFC,
DIV_KFC0,
GATE_BUS_CDREX0,
GATE_BUS_CDREX1,
};
static const unsigned long exynos5800_clk_regs[] __initconst = {
SRC_TOP8,
SRC_TOP9,
SRC_CAM,
SRC_TOP1,
DIV_TOP8,
DIV_TOP9,
DIV_CAM,
GATE_IP_CAM,
};
static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
{ .offset = SRC_MASK_CPERI, .value = 0xffffffff, },
{ .offset = SRC_MASK_TOP0, .value = 0x11111111, },
{ .offset = SRC_MASK_TOP1, .value = 0x11101111, },
{ .offset = SRC_MASK_TOP2, .value = 0x11111110, },
{ .offset = SRC_MASK_TOP7, .value = 0x00111100, },
{ .offset = SRC_MASK_DISP10, .value = 0x11111110, },
{ .offset = SRC_MASK_MAU, .value = 0x10000000, },
{ .offset = SRC_MASK_FSYS, .value = 0x11111110, },
{ .offset = SRC_MASK_PERIC0, .value = 0x11111110, },
{ .offset = SRC_MASK_PERIC1, .value = 0x11111100, },
{ .offset = SRC_MASK_ISP, .value = 0x11111000, },
{ .offset = GATE_BUS_TOP, .value = 0xffffffff, },
{ .offset = GATE_BUS_DISP1, .value = 0xffffffff, },
{ .offset = GATE_IP_PERIC, .value = 0xffffffff, },
{ .offset = GATE_IP_PERIS, .value = 0xffffffff, },
};
/* list of all parent clocks */
PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
"mout_sclk_mpll", "mout_sclk_spll"};
PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"};
PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
"mout_sclk_mpll"};
PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll",
"mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll",
"mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"};
PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"};
PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"};
PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"};
PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"};
PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"};
PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"};
PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};
PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"};
PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"};
PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"};
PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"};
PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"};
PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"};
PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"};
PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0",
"mout_sclk_spll"};
PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"};
PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"};
PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"};
PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"};
PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"};
PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"};
PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"};
PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"};
PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"};
PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"};
PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"};
PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"};
PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"};
PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"};
PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"};
PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"};
PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll",
"mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
"mout_sclk_epll", "mout_sclk_rpll"};
PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll",
"mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
"mout_sclk_epll", "mout_sclk_rpll"};
PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll",
"mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
"mout_sclk_epll", "mout_sclk_rpll"};
PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1",
"dout_audio2", "spdif_extclk", "mout_sclk_ipll",
"mout_sclk_epll", "mout_sclk_rpll"};
PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
"mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
"mout_sclk_epll", "mout_sclk_rpll"};
PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll",
"mout_sclk_mpll", "mout_sclk_spll"};
PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"};
/* List of parents specific to exynos5800 */
PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" };
PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
"mout_sclk_mpll", "ff_dout_spll2" };
PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
"mout_sclk_mpll", "ff_dout_spll2",
"mout_epll2", "mout_sclk_ipll" };
PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
"mout_sclk_mpll", "ff_dout_spll2",
"mout_epll2" };
PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
"mout_sclk_mpll", "mout_sclk_spll" };
PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll",
"mout_sclk_mpll", "ff_dout_spll2" };
PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
"mout_sclk_mpll", "mout_sclk_spll",
"mout_epll2", "mout_sclk_ipll" };
PNAME(mout_mx_mspll_ccore_p) = {"sclk_bpll", "mout_sclk_dpll",
"mout_sclk_mpll", "ff_dout_spll2",
"mout_sclk_spll", "mout_sclk_epll"};
PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll",
"mout_sclk_mpll",
"ff_dout_spll2" };
PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" };
PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" };
PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" };
PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" };
PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" };
PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" };
PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" };
PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" };
PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll",
"mout_sclk_mpll", "ff_dout_spll2",
"mout_sclk_spll", "mout_sclk_epll"};
/* fixed rate clocks generated outside the soc */
static struct samsung_fixed_rate_clock
exynos5x_fixed_rate_ext_clks[] __initdata = {
FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
};
/* fixed rate clocks generated inside the soc */
static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = {
FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
FRATE(0, "sclk_pwi", NULL, 0, 24000000),
FRATE(0, "sclk_usbh20", NULL, 0, 48000000),
FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000),
FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000),
};
static const struct samsung_fixed_factor_clock
exynos5x_fixed_factor_clks[] __initconst = {
FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
};
static const struct samsung_fixed_factor_clock
exynos5800_fixed_factor_clks[] __initconst = {
FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
};
static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2),
MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2),
MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2),
MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy",
mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3),
MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3),
MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,
SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0),
MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,
SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0),
MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
SRC_TOP9, 16, 1),
MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
SRC_TOP9, 20, 1),
MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p,
SRC_TOP9, 24, 1),
MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
SRC_TOP9, 28, 1),
MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
SRC_TOP13, 20, 1),
MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p,
SRC_TOP13, 24, 1),
MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p,
SRC_TOP13, 28, 1),
MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3),
};
static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
"mout_aclk400_wcore", DIV_TOP0, 16, 3),
DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
DIV_TOP8, 16, 3),
DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
DIV_TOP8, 20, 3),
DIV(0, "dout_aclk432_cam", "mout_aclk432_cam",
DIV_TOP8, 24, 3),
DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler",
DIV_TOP8, 28, 3),
DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3),
DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6),
};
static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = {
GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
GATE_BUS_TOP, 24, CLK_IS_CRITICAL, 0),
GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0),
};
static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
TOP_SPARE2, 4, 1),
MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
MUX(0, "mout_aclk333_432_isp", mout_group4_p,
SRC_TOP1, 4, 2),
MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
mout_group5_5800_p, SRC_TOP7, 16, 2),
MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
CLK_SET_RATE_PARENT, 0),
MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
};
static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
"mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
};
static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
/* Maudio Block */
GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
SRC_TOP7, 4, 1),
MUX(CLK_MOUT_MSPLL_KFC, "mout_mspll_kfc", mout_mspll_cpu_p,
SRC_TOP7, 8, 2),
MUX(CLK_MOUT_MSPLL_CPU, "mout_mspll_cpu", mout_mspll_cpu_p,
SRC_TOP7, 12, 2),
MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
MUX_F(CLK_MOUT_KPLL, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
MUX_F(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1,
CLK_SET_RATE_PARENT, 0),
MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
SRC_TOP3, 0, 1),
MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
SRC_TOP3, 4, 1),
MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1",
mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1),
MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
SRC_TOP3, 12, 1),
MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
SRC_TOP3, 16, 1),
MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
SRC_TOP3, 20, 1),
MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
SRC_TOP3, 24, 1),
MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
SRC_TOP3, 28, 1),
MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p,
SRC_TOP4, 0, 1),
MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
SRC_TOP4, 4, 1),
MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p,
SRC_TOP4, 8, 1),
MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
SRC_TOP4, 12, 1),
MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
SRC_TOP4, 16, 1),
MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
SRC_TOP4, 28, 1),
MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1",
mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),
MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
SRC_TOP5, 4, 1),
MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
SRC_TOP5, 8, 1),
MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
SRC_TOP5, 12, 1),
MUX_F(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
SRC_TOP5, 16, 1, CLK_SET_RATE_PARENT, 0),
MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
SRC_TOP5, 20, 1),
MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl",
mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),
MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
MUX_F(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1,
CLK_SET_RATE_PARENT, 0),
MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
CLK_SET_RATE_PARENT, 0),
MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
SRC_TOP10, 0, 1),
MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
SRC_TOP10, 4, 1),
MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
SRC_TOP10, 8, 1),
MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
SRC_TOP10, 12, 1),
MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
SRC_TOP10, 16, 1),
MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
SRC_TOP10, 20, 1),
MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
SRC_TOP10, 24, 1),
MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
SRC_TOP10, 28, 1),
MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p,
SRC_TOP11, 0, 1),
MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
SRC_TOP11, 4, 1),
MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
SRC_TOP11, 12, 1),
MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
SRC_TOP11, 28, 1),
MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1",
mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1),
MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
SRC_TOP12, 8, 1),
MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
SRC_TOP12, 12, 1),
MUX_F(CLK_MOUT_SW_ACLK_G3D, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p,
SRC_TOP12, 16, 1, CLK_SET_RATE_PARENT, 0),
MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
SRC_TOP12, 20, 1),
MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl",
mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
/* DISP1 Block */
MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
/* CDREX block */
MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p,
SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0),
MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1,
CLK_SET_RATE_PARENT, 0),
/* MAU Block */
MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),
/* FSYS Block */
MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
/* PERIC Block */
MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
/* ISP Block */
MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
};
static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp",
DIV_TOP0, 0, 3),
DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl",
DIV_TOP0, 4, 3),
DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200",
DIV_TOP0, 8, 3),
DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2",
DIV_TOP0, 12, 3),
DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
DIV_TOP0, 20, 3),
DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys",
DIV_TOP0, 24, 3),
DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys",
DIV_TOP0, 28, 3),
DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl",
"mout_aclk333_432_gscl", DIV_TOP1, 0, 3),
DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp",
"mout_aclk333_432_isp", DIV_TOP1, 4, 3),
DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66",
DIV_TOP1, 8, 6),
DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0",
"mout_aclk333_432_isp0", DIV_TOP1, 16, 3),
DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266",
DIV_TOP1, 20, 3),
DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166",
DIV_TOP1, 24, 3),
DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333",
DIV_TOP1, 28, 3),
DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d",
DIV_TOP2, 8, 3),
DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d",
DIV_TOP2, 12, 3),
DIV_F(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2,
16, 3, CLK_SET_RATE_PARENT, 0),
DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg",
DIV_TOP2, 20, 3),
DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1",
"mout_aclk300_disp1", DIV_TOP2, 24, 3),
DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl",
DIV_TOP2, 28, 3),
/* DISP1 Block */
DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1",
"mout_aclk400_disp1", DIV_TOP2, 4, 3),
/* CDREX Block */
/*
* The three clocks below are controlled using the same register and
* bits. They are put into one because there is a need of
* synchronization between the BUS and DREXs (two external memory
* interfaces).
* They are put here to show this HW assumption and for clock
* information summary completeness.
*/
DIV_F(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1",
DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
DIV_F(CLK_DOUT_PCLK_DREX0, "dout_pclk_drex0", "dout_cclk_drex0",
DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
DIV_F(CLK_DOUT_PCLK_DREX1, "dout_pclk_drex1", "dout_cclk_drex0",
DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex",
DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0),
DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0",
DIV_CDREX0, 16, 3),
DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0",
DIV_CDREX0, 8, 3),
DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex",
DIV_CDREX0, 3, 5),
DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex",
DIV_CDREX1, 8, 3),
/* Audio Block */
DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
/* USB3.0 */
DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
/* MMC */
DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
/* UART and PWM */
DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
/* SPI */
DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
/* PCM */
DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
/* Audio - I2S */
DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
/* SPI Pre-Ratio */
DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
/* GSCL Block */
DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
/* PSGEN */
DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
/* ISP Block */
DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
CLK_SET_RATE_PARENT, 0),
DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
/* G2D */
GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0),
GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0),
GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
GATE_BUS_TOP, 5, CLK_IS_CRITICAL, 0),
GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0),
GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
GATE_BUS_TOP, 8, CLK_IS_CRITICAL, 0),
GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio",
GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
GATE_BUS_TOP, 13, CLK_IS_CRITICAL, 0),
GATE(0, "aclk166", "mout_user_aclk166",
GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333",
GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0),
GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
GATE_BUS_TOP, 16, CLK_IS_CRITICAL, 0),
GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0),
GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0),
GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
GATE_BUS_TOP, 28, 0, 0),
GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m",
GATE_BUS_TOP, 29, 0, 0),
GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0),
/* sclk */
GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre",
GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre",
GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre",
GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1",
GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2",
GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
/* Display */
GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
GATE_TOP_SCLK_DISP1, 9, 0, 0),
GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
/* FSYS Block */
GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
/* PERIC Block */
GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric",
GATE_IP_PERIC, 0, 0, 0),
GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric",
GATE_IP_PERIC, 1, 0, 0),
GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric",
GATE_IP_PERIC, 2, 0, 0),
GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric",
GATE_IP_PERIC, 3, 0, 0),
GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric",
GATE_IP_PERIC, 6, 0, 0),
GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric",
GATE_IP_PERIC, 7, 0, 0),
GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric",
GATE_IP_PERIC, 8, 0, 0),
GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric",
GATE_IP_PERIC, 9, 0, 0),
GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric",
GATE_IP_PERIC, 10, 0, 0),
GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric",
GATE_IP_PERIC, 11, 0, 0),
GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric",
GATE_IP_PERIC, 12, 0, 0),
GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric",
GATE_IP_PERIC, 13, 0, 0),
GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric",
GATE_IP_PERIC, 14, 0, 0),
GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric",
GATE_IP_PERIC, 15, 0, 0),
GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric",
GATE_IP_PERIC, 16, 0, 0),
GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric",
GATE_IP_PERIC, 17, 0, 0),
GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric",
GATE_IP_PERIC, 18, 0, 0),
GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric",
GATE_IP_PERIC, 20, 0, 0),
GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric",
GATE_IP_PERIC, 21, 0, 0),
GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric",
GATE_IP_PERIC, 22, 0, 0),
GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric",
GATE_IP_PERIC, 23, 0, 0),
GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric",
GATE_IP_PERIC, 24, 0, 0),
GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric",
GATE_IP_PERIC, 26, 0, 0),
GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric",
GATE_IP_PERIC, 28, 0, 0),
GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric",
GATE_IP_PERIC, 30, 0, 0),
GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric",
GATE_IP_PERIC, 31, 0, 0),
GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric",
GATE_BUS_PERIC, 22, 0, 0),
/* PERIS Block */
GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0),
GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0),
GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0),
GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0),
GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0),
GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0),
GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0),
GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0),
GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0),
GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0),
GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0),
GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0),
GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
/* GEN Block */
GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0),
GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0),
GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk",
GATE_IP_GEN, 6, 0, 0),
GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk",
GATE_IP_GEN, 9, 0, 0),
/* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */
GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk",
GATE_BUS_GEN, 28, 0, 0),
GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
/* GSCL Block */
GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl",
GATE_TOP_SCLK_GSCL, 6, 0, 0),
GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl",
GATE_TOP_SCLK_GSCL, 7, 0, 0),
GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl",
GATE_IP_GSCL0, 4, 0, 0),
GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl",
GATE_IP_GSCL0, 5, 0, 0),
GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl",
GATE_IP_GSCL0, 6, 0, 0),
GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
GATE_IP_GSCL1, 2, 0, 0),
GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333",
GATE_IP_GSCL1, 3, 0, 0),
GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
GATE_IP_GSCL1, 4, 0, 0),
GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12,
CLK_IS_CRITICAL, 0),
GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13,
CLK_IS_CRITICAL, 0),
GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3", "dout_gscl_blk_333",
GATE_IP_GSCL1, 16, 0, 0),
GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
GATE_IP_GSCL1, 17, 0, 0),
/* ISP */
GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre",
GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre",
GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp",
GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0",
GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1",
GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
/* CDREX */
GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex",
GATE_BUS_CDREX0, 0, 0, 0),
GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex",
GATE_BUS_CDREX0, 1, 0, 0),
GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy",
SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1",
GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1",
GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1",
GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1",
GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex",
GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex",
GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex",
GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex",
GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0),
};
static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = {
DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
};
static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = {
GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
GATE_IP_DISP1, 7, 0, 0),
GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk",
GATE_IP_DISP1, 8, 0, 0),
GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1",
GATE_IP_DISP1, 9, 0, 0),
};
static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = {
{ GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */
{ SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */
{ SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */
{ SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */
{ DIV2_RATIO0, 0, 0x30000 }, /* DIV dout_disp1_blk */
};
static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = {
DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
DIV2_RATIO0, 4, 2),
};
static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = {
GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300",
GATE_IP_GSCL1, 6, 0, 0),
GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300",
GATE_IP_GSCL1, 7, 0, 0),
};
static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
{ GATE_IP_GSCL0, 0x3, 0x3 }, /* GSC gates */
{ GATE_IP_GSCL1, 0xc0, 0xc0 }, /* GSC gates */
{ SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */
{ DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */
};
static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = {
GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9,
CLK_SET_RATE_PARENT, 0),
};
static struct exynos5_subcmu_reg_dump exynos5x_g3d_suspend_regs[] = {
{ GATE_IP_G3D, 0x3ff, 0x3ff }, /* G3D gates */
{ SRC_TOP5, 0, BIT(16) }, /* MUX mout_user_aclk_g3d */
};
static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = {
DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
};
static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = {
GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
};
static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = {
{ GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */
{ SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */
{ DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */
};
static const struct samsung_gate_clock exynos5x_mscl_gate_clks[] __initconst = {
/* MSCL Block */
GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
GATE_IP_MSCL, 8, 0, 0),
GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
GATE_IP_MSCL, 9, 0, 0),
GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
GATE_IP_MSCL, 10, 0, 0),
};
static const struct samsung_div_clock exynos5x_mscl_div_clks[] __initconst = {
DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
};
static struct exynos5_subcmu_reg_dump exynos5x_mscl_suspend_regs[] = {
{ GATE_IP_MSCL, 0xffffffff, 0xffffffff }, /* MSCL gates */
{ SRC_TOP3, 0, BIT(4) }, /* MUX mout_user_aclk400_mscl */
{ DIV2_RATIO0, 0, 0x30000000 }, /* DIV dout_mscl_blk */
};
static const struct samsung_gate_clock exynos5800_mau_gate_clks[] __initconst = {
GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll",
SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
};
static struct exynos5_subcmu_reg_dump exynos5800_mau_suspend_regs[] = {
{ SRC_TOP9, 0, BIT(8) }, /* MUX mout_user_mau_epll */
};
static const struct exynos5_subcmu_info exynos5x_disp_subcmu = {
.div_clks = exynos5x_disp_div_clks,
.nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks),
.gate_clks = exynos5x_disp_gate_clks,
.nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks),
.suspend_regs = exynos5x_disp_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs),
.pd_name = "DISP",
};
static const struct exynos5_subcmu_info exynos5x_gsc_subcmu = {
.div_clks = exynos5x_gsc_div_clks,
.nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks),
.gate_clks = exynos5x_gsc_gate_clks,
.nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks),
.suspend_regs = exynos5x_gsc_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs),
.pd_name = "GSC",
};
static const struct exynos5_subcmu_info exynos5x_g3d_subcmu = {
.gate_clks = exynos5x_g3d_gate_clks,
.nr_gate_clks = ARRAY_SIZE(exynos5x_g3d_gate_clks),
.suspend_regs = exynos5x_g3d_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(exynos5x_g3d_suspend_regs),
.pd_name = "G3D",
};
static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = {
.div_clks = exynos5x_mfc_div_clks,
.nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks),
.gate_clks = exynos5x_mfc_gate_clks,
.nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks),
.suspend_regs = exynos5x_mfc_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs),
.pd_name = "MFC",
};
static const struct exynos5_subcmu_info exynos5x_mscl_subcmu = {
.div_clks = exynos5x_mscl_div_clks,
.nr_div_clks = ARRAY_SIZE(exynos5x_mscl_div_clks),
.gate_clks = exynos5x_mscl_gate_clks,
.nr_gate_clks = ARRAY_SIZE(exynos5x_mscl_gate_clks),
.suspend_regs = exynos5x_mscl_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(exynos5x_mscl_suspend_regs),
.pd_name = "MSC",
};
static const struct exynos5_subcmu_info exynos5800_mau_subcmu = {
.gate_clks = exynos5800_mau_gate_clks,
.nr_gate_clks = ARRAY_SIZE(exynos5800_mau_gate_clks),
.suspend_regs = exynos5800_mau_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(exynos5800_mau_suspend_regs),
.pd_name = "MAU",
};
static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
&exynos5x_disp_subcmu,
&exynos5x_gsc_subcmu,
&exynos5x_g3d_subcmu,
&exynos5x_mfc_subcmu,
&exynos5x_mscl_subcmu,
};
static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
&exynos5x_disp_subcmu,
&exynos5x_gsc_subcmu,
&exynos5x_g3d_subcmu,
&exynos5x_mfc_subcmu,
&exynos5x_mscl_subcmu,
&exynos5800_mau_subcmu,
};
static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0),
PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1),
PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
PLL_35XX_RATE(24 * MHZ, 900000000, 150, 2, 1),
PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
PLL_35XX_RATE(24 * MHZ, 600000000, 200, 2, 2),
PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2),
PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2),
PLL_35XX_RATE(24 * MHZ, 300000000, 200, 2, 3),
PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
};
static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = {
PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1),
PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1),
PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2),
PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2),
PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3),
PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3),
PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3),
};
static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0),
PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
PLL_36XX_RATE(24 * MHZ, 361267218U, 301, 5, 2, 3671),
PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671),
PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719),
PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
PLL_36XX_RATE(24 * MHZ, 73728000U, 98, 2, 4, 19923),
PLL_36XX_RATE(24 * MHZ, 67737602U, 90, 2, 4, 20762),
PLL_36XX_RATE(24 * MHZ, 65536003U, 131, 3, 4, 4719),
PLL_36XX_RATE(24 * MHZ, 49152000U, 197, 3, 5, -25690),
PLL_36XX_RATE(24 * MHZ, 45158401U, 90, 3, 4, 20762),
PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719),
};
static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[] = {
PLL_35XX_RATE(24 * MHZ, 600000000U, 200, 2, 2),
PLL_35XX_RATE(24 * MHZ, 543000000U, 181, 2, 2),
PLL_35XX_RATE(24 * MHZ, 480000000U, 160, 2, 2),
PLL_35XX_RATE(24 * MHZ, 420000000U, 140, 2, 2),
PLL_35XX_RATE(24 * MHZ, 350000000U, 175, 3, 2),
PLL_35XX_RATE(24 * MHZ, 266000000U, 266, 3, 3),
PLL_35XX_RATE(24 * MHZ, 177000000U, 118, 2, 3),
PLL_35XX_RATE(24 * MHZ, 100000000U, 200, 3, 4),
};
static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
[apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
APLL_CON0, NULL),
[cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
CPLL_CON0, NULL),
[dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
DPLL_CON0, NULL),
[epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
EPLL_CON0, NULL),
[rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
RPLL_CON0, NULL),
[ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
IPLL_CON0, NULL),
[spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
SPLL_CON0, NULL),
[vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
VPLL_CON0, NULL),
[mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
MPLL_CON0, NULL),
[bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
BPLL_CON0, NULL),
[kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
KPLL_CON0, NULL),
};
#define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \
((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
((cpud) << 4)))
static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
{ 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
{ 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
{ 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
{ 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
{ 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
{ 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
{ 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
{ 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
{ 1000000, E5420_EGL_DIV0(3, 6, 6, 2), },
{ 900000, E5420_EGL_DIV0(3, 6, 6, 2), },
{ 800000, E5420_EGL_DIV0(3, 5, 5, 2), },
{ 700000, E5420_EGL_DIV0(3, 5, 5, 2), },
{ 600000, E5420_EGL_DIV0(3, 4, 4, 2), },
{ 500000, E5420_EGL_DIV0(3, 3, 3, 2), },
{ 400000, E5420_EGL_DIV0(3, 3, 3, 2), },
{ 300000, E5420_EGL_DIV0(3, 3, 3, 2), },
{ 200000, E5420_EGL_DIV0(3, 3, 3, 2), },
{ 0 },
};
static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
{ 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
{ 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
{ 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
{ 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
{ 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
{ 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
{ 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
{ 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
{ 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
{ 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
{ 1000000, E5420_EGL_DIV0(3, 7, 6, 2), },
{ 900000, E5420_EGL_DIV0(3, 7, 6, 2), },
{ 800000, E5420_EGL_DIV0(3, 7, 5, 2), },
{ 700000, E5420_EGL_DIV0(3, 7, 5, 2), },
{ 600000, E5420_EGL_DIV0(3, 7, 4, 2), },
{ 500000, E5420_EGL_DIV0(3, 7, 3, 2), },
{ 400000, E5420_EGL_DIV0(3, 7, 3, 2), },
{ 300000, E5420_EGL_DIV0(3, 7, 3, 2), },
{ 200000, E5420_EGL_DIV0(3, 7, 3, 2), },
{ 0 },
};
#define E5420_KFC_DIV(kpll, pclk, aclk) \
((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
{ 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
{ 1300000, E5420_KFC_DIV(3, 5, 2), },
{ 1200000, E5420_KFC_DIV(3, 5, 2), },
{ 1100000, E5420_KFC_DIV(3, 5, 2), },
{ 1000000, E5420_KFC_DIV(3, 5, 2), },
{ 900000, E5420_KFC_DIV(3, 5, 2), },
{ 800000, E5420_KFC_DIV(3, 5, 2), },
{ 700000, E5420_KFC_DIV(3, 4, 2), },
{ 600000, E5420_KFC_DIV(3, 4, 2), },
{ 500000, E5420_KFC_DIV(3, 4, 2), },
{ 400000, E5420_KFC_DIV(3, 3, 2), },
{ 300000, E5420_KFC_DIV(3, 3, 2), },
{ 200000, E5420_KFC_DIV(3, 3, 2), },
{ 0 },
};
static const struct samsung_cpu_clock exynos5420_cpu_clks[] __initconst = {
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, 0x200,
exynos5420_eglclk_d),
CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, 0x28200,
exynos5420_kfcclk_d),
};
static const struct samsung_cpu_clock exynos5800_cpu_clks[] __initconst = {
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, 0x200,
exynos5800_eglclk_d),
CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, 0x28200,
exynos5420_kfcclk_d),
};
static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
{ },
};
/* register exynos5420 clocks */
static void __init exynos5x_clk_init(struct device_node *np,
enum exynos5x_soc soc)
{
struct samsung_clk_provider *ctx;
struct clk_hw **hws;
if (np) {
reg_base = of_iomap(np, 0);
if (!reg_base)
panic("%s: failed to map registers\n", __func__);
} else {
panic("%s: unable to determine soc\n", __func__);
}
exynos5x_soc = soc;
ctx = samsung_clk_init(NULL, reg_base, CLKS_NR);
hws = ctx->clk_data.hws;
samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
ext_clk_match);
if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) {
exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl;
}
if (soc == EXYNOS5420)
exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
else
exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table;
samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls));
samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
ARRAY_SIZE(exynos5x_fixed_rate_clks));
samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks,
ARRAY_SIZE(exynos5x_fixed_factor_clks));
samsung_clk_register_mux(ctx, exynos5x_mux_clks,
ARRAY_SIZE(exynos5x_mux_clks));
samsung_clk_register_div(ctx, exynos5x_div_clks,
ARRAY_SIZE(exynos5x_div_clks));
samsung_clk_register_gate(ctx, exynos5x_gate_clks,
ARRAY_SIZE(exynos5x_gate_clks));
if (soc == EXYNOS5420) {
samsung_clk_register_mux(ctx, exynos5420_mux_clks,
ARRAY_SIZE(exynos5420_mux_clks));
samsung_clk_register_div(ctx, exynos5420_div_clks,
ARRAY_SIZE(exynos5420_div_clks));
samsung_clk_register_gate(ctx, exynos5420_gate_clks,
ARRAY_SIZE(exynos5420_gate_clks));
} else {
samsung_clk_register_fixed_factor(
ctx, exynos5800_fixed_factor_clks,
ARRAY_SIZE(exynos5800_fixed_factor_clks));
samsung_clk_register_mux(ctx, exynos5800_mux_clks,
ARRAY_SIZE(exynos5800_mux_clks));
samsung_clk_register_div(ctx, exynos5800_div_clks,
ARRAY_SIZE(exynos5800_div_clks));
samsung_clk_register_gate(ctx, exynos5800_gate_clks,
ARRAY_SIZE(exynos5800_gate_clks));
}
if (soc == EXYNOS5420) {
samsung_clk_register_cpu(ctx, exynos5420_cpu_clks,
ARRAY_SIZE(exynos5420_cpu_clks));
} else {
samsung_clk_register_cpu(ctx, exynos5800_cpu_clks,
ARRAY_SIZE(exynos5800_cpu_clks));
}
samsung_clk_extended_sleep_init(reg_base,
exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs),
exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc));
if (soc == EXYNOS5800) {
samsung_clk_sleep_init(reg_base, exynos5800_clk_regs,
ARRAY_SIZE(exynos5800_clk_regs));
exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5800_subcmus),
exynos5800_subcmus);
} else {
exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus),
exynos5x_subcmus);
}
/*
* Keep top part of G3D clock path enabled permanently to ensure
* that the internal busses get their clock regardless of the
* main G3D clock enablement status.
*/
clk_prepare_enable(hws[CLK_MOUT_SW_ACLK_G3D]->clk);
/*
* Keep top BPLL mux enabled permanently to ensure that DRAM operates
* properly.
*/
clk_prepare_enable(hws[CLK_MOUT_BPLL]->clk);
samsung_clk_of_add_provider(np, ctx);
}
static void __init exynos5420_clk_init(struct device_node *np)
{
exynos5x_clk_init(np, EXYNOS5420);
}
CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock",
exynos5420_clk_init);
static void __init exynos5800_clk_init(struct device_node *np)
{
exynos5x_clk_init(np, EXYNOS5800);
}
CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock",
exynos5800_clk_init);
| linux-master | drivers/clk/samsung/clk-exynos5420.c |
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2017 MediaTek Inc.
* Author: Kevin Chen <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt6797-clk.h>
#include "clk-mtk.h"
#include "clk-gate.h"
static const struct mtk_gate_regs img_cg_regs = {
.set_ofs = 0x0004,
.clr_ofs = 0x0008,
.sta_ofs = 0x0000,
};
#define GATE_IMG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate img_clks[] = {
GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_sel", 11),
GATE_IMG(CLK_IMG_DPE, "img_dpe", "mm_sel", 10),
GATE_IMG(CLK_IMG_DIP, "img_dip", "mm_sel", 6),
GATE_IMG(CLK_IMG_LARB6, "img_larb6", "mm_sel", 0),
};
static const struct mtk_clk_desc img_desc = {
.clks = img_clks,
.num_clks = ARRAY_SIZE(img_clks),
};
static const struct of_device_id of_match_clk_mt6797_img[] = {
{
.compatible = "mediatek,mt6797-imgsys",
.data = &img_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6797_img);
static struct platform_driver clk_mt6797_img_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt6797-img",
.of_match_table = of_match_clk_mt6797_img,
},
};
module_platform_driver(clk_mt6797_img_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6797-img.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Garmin Chang <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs vdo0_0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs vdo0_1_cg_regs = {
.set_ofs = 0x114,
.clr_ofs = 0x118,
.sta_ofs = 0x110,
};
static const struct mtk_gate_regs vdo0_2_cg_regs = {
.set_ofs = 0x124,
.clr_ofs = 0x128,
.sta_ofs = 0x120,
};
#define GATE_VDO0_0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO0_1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO0_2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags) \
GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flags)
static const struct mtk_gate vdo0_clks[] = {
/* VDO0_0 */
GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "top_vpp", 0),
GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0", "top_vpp", 2),
GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0", "top_vpp", 4),
GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0", "top_vpp", 6),
GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0", "top_vpp", 8),
GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0", "top_vpp", 10),
GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0", "top_vpp", 17),
GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0", "top_vpp", 19),
GATE_VDO0_0(CLK_VDO0_DSI0, "vdo0_dsi0", "top_vpp", 21),
GATE_VDO0_0(CLK_VDO0_DSI1, "vdo0_dsi1", "top_vpp", 22),
GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0", "top_vpp", 23),
GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0", "top_vpp", 24),
GATE_VDO0_0(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0", "top_vpp", 25),
GATE_VDO0_0(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0", "top_vpp", 26),
GATE_VDO0_0(CLK_VDO0_INLINEROT0, "vdo0_inlinerot0", "top_vpp", 27),
GATE_VDO0_0(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "top_vpp", 28),
GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0", "top_vpp", 29),
GATE_VDO0_0(CLK_VDO0_MDP_WROT0, "vdo0_mdp_wrot0", "top_vpp", 30),
GATE_VDO0_0(CLK_VDO0_DISP_RSZ0, "vdo0_disp_rsz0", "top_vpp", 31),
/* VDO0_1 */
GATE_VDO0_1(CLK_VDO0_DISP_POSTMASK0, "vdo0_disp_postmask0", "top_vpp", 0),
GATE_VDO0_1(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1", "top_vpp", 1),
GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2", "top_vpp", 5),
GATE_VDO0_1(CLK_VDO0_DL_RELAY3, "vdo0_dl_relay3", "top_vpp", 6),
GATE_VDO0_1(CLK_VDO0_DL_RELAY4, "vdo0_dl_relay4", "top_vpp", 7),
GATE_VDO0_1(CLK_VDO0_SMI_GALS, "vdo0_smi_gals", "top_vpp", 10),
GATE_VDO0_1(CLK_VDO0_SMI_COMMON, "vdo0_smi_common", "top_vpp", 11),
GATE_VDO0_1(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "top_vpp", 12),
GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu", "top_vpp", 13),
GATE_VDO0_1(CLK_VDO0_SMI_LARB, "vdo0_smi_larb", "top_vpp", 14),
GATE_VDO0_1(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "top_vpp", 15),
/* VDO0_2 */
GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "top_dsi_occ", 0),
GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "top_dsi_occ", 8),
GATE_VDO0_2_FLAGS(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf",
"top_edp", 16, CLK_SET_RATE_PARENT),
};
static const struct mtk_clk_desc vdo0_desc = {
.clks = vdo0_clks,
.num_clks = ARRAY_SIZE(vdo0_clks),
};
static const struct platform_device_id clk_mt8188_vdo0_id_table[] = {
{ .name = "clk-mt8188-vdo0", .driver_data = (kernel_ulong_t)&vdo0_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, clk_mt8188_vdo0_id_table);
static struct platform_driver clk_mt8188_vdo0_drv = {
.probe = mtk_clk_pdev_probe,
.remove_new = mtk_clk_pdev_remove,
.driver = {
.name = "clk-mt8188-vdo0",
},
.id_table = clk_mt8188_vdo0_id_table,
};
module_platform_driver(clk_mt8188_vdo0_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8188-vdo0.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 Collabora Ltd.
* Author: AngeloGioacchino Del Regno <[email protected]>
*/
#include <dt-bindings/clock/mediatek,mt6795-clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-mux.h"
/*
* For some clocks, we don't care what their actual rates are. And these
* clocks may change their rate on different products or different scenarios.
* So we model these clocks' rate as 0, to denote it's not an actual rate.
*/
#define DUMMY_RATE 0
#define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \
MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _reg, \
(_reg + 0x4), (_reg + 0x8), _shift, _width, \
_gate, 0, -1, _flags)
#define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \
TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, \
_gate, CLK_SET_RATE_PARENT | _flags)
static DEFINE_SPINLOCK(mt6795_top_clk_lock);
static const char * const aud_1_parents[] = {
"clk26m",
"apll1_ck",
"univpll2_d4",
"univpll2_d8"
};
static const char * const aud_2_parents[] = {
"clk26m",
"apll2_ck",
"univpll2_d4",
"univpll2_d8"
};
static const char * const aud_intbus_parents[] = {
"clk26m",
"syspll1_d4",
"syspll4_d2",
"univpll3_d2",
"univpll2_d8",
"dmpll_d4",
"dmpll_d8"
};
static const char * const audio_parents[] = {
"clk26m",
"syspll3_d4",
"syspll4_d4",
"syspll1_d16"
};
static const char * const axi_mfg_in_parents[] = {
"clk26m",
"axi_sel",
"dmpll_d2"
};
static const char * const axi_parents[] = {
"clk26m",
"syspll1_d2",
"syspll_d5",
"syspll1_d4",
"univpll_d5",
"univpll2_d2",
"dmpll_d2",
"dmpll_d4"
};
static const char * const camtg_parents[] = {
"clk26m",
"univpll_d26",
"univpll2_d2",
"syspll3_d2",
"syspll3_d4",
"univpll1_d4",
"dmpll_d8"
};
static const char * const cci400_parents[] = {
"clk26m",
"vencpll_ck",
"clk26m",
"clk26m",
"univpll_d2",
"syspll_d2",
"msdcpll_ck",
"dmpll_ck"
};
static const char * const ddrphycfg_parents[] = {
"clk26m",
"syspll1_d8"
};
static const char * const dpi0_parents[] = {
"clk26m",
"tvdpll_d2",
"tvdpll_d4",
"clk26m",
"clk26m",
"tvdpll_d8",
"tvdpll_d16"
};
static const char * const i2s0_m_ck_parents[] = {
"apll1_div1",
"apll2_div1"
};
static const char * const i2s1_m_ck_parents[] = {
"apll1_div2",
"apll2_div2"
};
static const char * const i2s2_m_ck_parents[] = {
"apll1_div3",
"apll2_div3"
};
static const char * const i2s3_m_ck_parents[] = {
"apll1_div4",
"apll2_div4"
};
static const char * const i2s3_b_ck_parents[] = {
"apll1_div5",
"apll2_div5"
};
static const char * const irda_parents[] = {
"clk26m",
"univpll2_d4",
"syspll2_d4",
"dmpll_d8",
};
static const char * const mem_mfg_in_parents[] = {
"clk26m",
"mmpll_ck",
"dmpll_ck"
};
static const char * const mem_parents[] = {
"clk26m",
"dmpll_ck"
};
static const char * const mfg_parents[] = {
"clk26m",
"mmpll_ck",
"dmpll_ck",
"clk26m",
"clk26m",
"clk26m",
"clk26m",
"clk26m",
"clk26m",
"syspll_d3",
"syspll1_d2",
"syspll_d5",
"univpll_d3",
"univpll1_d2",
"univpll_d5",
"univpll2_d2"
};
static const char * const mm_parents[] = {
"clk26m",
"vencpll_d2",
"syspll_d3",
"syspll1_d2",
"syspll_d5",
"syspll1_d4",
"univpll1_d2",
"univpll2_d2",
"dmpll_d2"
};
static const char * const mjc_parents[] = {
"clk26m",
"univpll_d3",
"vcodecpll_ck",
"tvdpll_445p5m",
"vencpll_d2",
"syspll_d3",
"univpll1_d2",
"syspll_d5",
"syspll1_d2",
"univpll_d5",
"univpll2_d2",
"dmpll_ck"
};
static const char * const msdc50_0_h_parents[] = {
"clk26m",
"syspll1_d2",
"syspll2_d2",
"syspll4_d2",
"univpll_d5",
"univpll1_d4"
};
static const char * const msdc50_0_parents[] = {
"clk26m",
"msdcpll_ck",
"msdcpll_d2",
"univpll1_d4",
"syspll2_d2",
"syspll_d7",
"msdcpll_d4",
"vencpll_d4",
"tvdpll_ck",
"univpll_d2",
"univpll1_d2",
"mmpll_ck"
};
static const char * const msdc30_1_parents[] = {
"clk26m",
"univpll2_d2",
"msdcpll_d4",
"univpll1_d4",
"syspll2_d2",
"syspll_d7",
"univpll_d7",
"vencpll_d4"
};
static const char * const msdc30_2_parents[] = {
"clk26m",
"univpll2_d2",
"msdcpll_d4",
"univpll1_d4",
"syspll2_d2",
"syspll_d7",
"univpll_d7",
"vencpll_d2"
};
static const char * const msdc30_3_parents[] = {
"clk26m",
"univpll2_d2",
"msdcpll_d4",
"univpll1_d4",
"syspll2_d2",
"syspll_d7",
"univpll_d7",
"vencpll_d4"
};
static const char * const pmicspi_parents[] = {
"clk26m",
"syspll1_d8",
"syspll3_d4",
"syspll1_d16",
"univpll3_d4",
"univpll_d26",
"dmpll_d8",
"dmpll_d16"
};
static const char * const pwm_parents[] = {
"clk26m",
"univpll2_d4",
"univpll3_d2",
"univpll1_d4"
};
static const char * const scam_parents[] = {
"clk26m",
"syspll3_d2",
"univpll2_d4",
"dmpll_d4"
};
static const char * const scp_parents[] = {
"clk26m",
"syspll1_d2",
"univpll_d5",
"syspll_d5",
"dmpll_d2",
"dmpll_d4"
};
static const char * const spi_parents[] = {
"clk26m",
"syspll3_d2",
"syspll1_d4",
"syspll4_d2",
"univpll3_d2",
"univpll2_d4",
"univpll1_d8"
};
static const char * const uart_parents[] = {
"clk26m",
"univpll2_d8"
};
static const char * const usb20_parents[] = {
"clk26m",
"univpll1_d8",
"univpll3_d4"
};
static const char * const usb30_parents[] = {
"clk26m",
"univpll3_d2",
"usb_syspll_125m",
"univpll2_d4"
};
static const char * const vdec_parents[] = {
"clk26m",
"vcodecpll_ck",
"tvdpll_445p5m",
"univpll_d3",
"vencpll_d2",
"syspll_d3",
"univpll1_d2",
"mmpll_d2",
"dmpll_d2",
"dmpll_d4"
};
static const char * const venc_parents[] = {
"clk26m",
"vcodecpll_ck",
"tvdpll_445p5m",
"univpll_d3",
"vencpll_d2",
"syspll_d3",
"univpll1_d2",
"univpll2_d2",
"dmpll_d2",
"dmpll_d4"
};
static const struct mtk_fixed_clk fixed_clks[] = {
FIXED_CLK(CLK_TOP_ADSYS_26M, "adsys_26m", "clk26m", 26 * MHZ),
FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", DUMMY_RATE),
FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ),
FIXED_CLK(CLK_TOP_DSI0_DIG, "dsi0_dig", "clk26m", DUMMY_RATE),
FIXED_CLK(CLK_TOP_DSI1_DIG, "dsi1_dig", "clk26m", DUMMY_RATE),
};
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_ARMCA53PLL_754M, "armca53pll_754m", "clk26m", 1, 2),
FACTOR(CLK_TOP_ARMCA53PLL_502M, "armca53pll_502m", "clk26m", 1, 3),
FACTOR_FLAGS(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7, 0),
FACTOR(CLK_TOP_TVDPLL_445P5M, "tvdpll_445p5m", "tvdpll", 1, 4),
FACTOR(CLK_TOP_TVDPLL_594M, "tvdpll_594m", "tvdpll", 1, 3),
FACTOR_FLAGS(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7, 0),
FACTOR_FLAGS(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26, 0),
FACTOR(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", "clk32k", 1, 1),
FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793),
FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1),
FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "clk26m", 1, 2),
FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "clk26m", 1, 3),
FACTOR(CLK_TOP_ARMCA53PLL_D2, "armca53pll_d2", "clk26m", 1, 1),
FACTOR(CLK_TOP_ARMCA53PLL_D3, "armca53pll_d3", "clk26m", 1, 1),
FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "clkph_mck_o", 1, 1),
FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "clkph_mck_o", 1, 2),
FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "clkph_mck_o", 1, 4),
FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "clkph_mck_o", 1, 8),
FACTOR(CLK_TOP_DMPLL_D16, "dmpll_d16", "clkph_mck_o", 1, 16),
FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 1),
FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2", 1, 2),
FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2", 1, 4),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4, 0),
FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll_594m", 1, 1),
FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2),
FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_594m", 1, 4),
FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_594m", 1, 8),
FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_594m", 1, 16),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2, 0),
FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 3),
FACTOR(CLK_TOP_VCODECPLL_370P5, "vcodecpll_370p5", "vcodecpll", 1, 4),
FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1),
FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll", 1, 2),
FACTOR(CLK_TOP_VENCPLL_D4, "vencpll_d4", "vencpll", 1, 4),
};
static const struct mtk_mux top_muxes[] = {
/* CLK_CFG_0 */
TOP_MUX_GATE_NOSR(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
0x40, 0, 3, 7, CLK_IS_CRITICAL),
TOP_MUX_GATE_NOSR(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
0x40, 8, 1, 15, CLK_IS_CRITICAL),
TOP_MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
0x40, 16, 1, 23, CLK_IS_CRITICAL),
TOP_MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x40, 24, 3, 31, 0),
/* CLK_CFG_1 */
TOP_MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x50, 0, 2, 7, 0),
TOP_MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x50, 8, 4, 15, 0),
TOP_MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x50, 16, 4, 23, 0),
TOP_MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x50, 24, 4, 31, 0),
/* CLK_CFG_2 */
TOP_MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x60, 0, 3, 7, 0),
TOP_MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x60, 8, 1, 15, 0),
TOP_MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x60, 16, 3, 23, 0),
TOP_MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x60, 24, 2, 31, 0),
/* CLK_CFG_3 */
TOP_MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x70, 0, 2, 7, 0),
TOP_MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents,
0x70, 8, 3, 15, 0),
TOP_MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 0x70, 16, 4, 23, 0),
TOP_MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 0x70, 24, 3, 31, 0),
/* CLK_CFG_4 */
TOP_MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents, 0x80, 0, 3, 7, 0),
TOP_MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, 0x80, 8, 3, 15, 0),
TOP_MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x80, 16, 2, 23, 0),
TOP_MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
0x80, 24, 3, 31, 0),
/* CLK_CFG_5 */
TOP_MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x90, 0, 3, 5, 0),
TOP_MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x90, 8, 3, 15, 0),
TOP_MUX_GATE(CLK_TOP_MJC_SEL, "mjc_sel", mjc_parents, 0x90, 24, 4, 31, 0),
/* CLK_CFG_6 */
/*
* The dpi0_sel clock should not propagate rate changes to its parent
* clock so the dpi driver can have full control over PLL and divider.
*/
TOP_MUX_GATE_NOSR(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0xa0, 0, 3, 7, 0),
TOP_MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0xa0, 8, 2, 15, 0),
TOP_MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents,
0xa0, 16, 3, 23, CLK_IS_CRITICAL),
TOP_MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0xa0, 24, 2, 31, 0),
/* CLK_CFG_7 */
TOP_MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0xb0, 0, 2, 7, 0),
TOP_MUX_GATE(CLK_TOP_MEM_MFG_IN_SEL, "mem_mfg_in_sel", mem_mfg_in_parents,
0xb0, 8, 2, 15, 0),
TOP_MUX_GATE(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents,
0xb0, 16, 2, 23, 0),
TOP_MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0xb0, 24, 2, 31, 0),
};
static struct mtk_composite top_aud_divs[] = {
MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents, 0x120, 4, 1),
MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents, 0x120, 5, 1),
MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents, 0x120, 6, 1),
MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents, 0x120, 7, 1),
MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1),
DIV_GATE(CLK_TOP_APLL1_DIV0, "apll1_div0", "aud_1_sel", 0x12c, 8, 0x120, 4, 24),
DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, 8, 0),
DIV_GATE(CLK_TOP_APLL1_DIV2, "apll1_div2", "aud_1_sel", 0x12c, 10, 0x124, 8, 8),
DIV_GATE(CLK_TOP_APLL1_DIV3, "apll1_div3", "aud_1_sel", 0x12c, 11, 0x124, 8, 16),
DIV_GATE(CLK_TOP_APLL1_DIV4, "apll1_div4", "aud_1_sel", 0x12c, 12, 0x124, 8, 24),
DIV_GATE(CLK_TOP_APLL1_DIV5, "apll1_div5", "apll1_div4", 0x12c, 13, 0x12c, 4, 0),
DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28),
DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1", "aud_2_sel", 0x12c, 17, 0x128, 8, 0),
DIV_GATE(CLK_TOP_APLL2_DIV2, "apll2_div2", "aud_2_sel", 0x12c, 18, 0x128, 8, 8),
DIV_GATE(CLK_TOP_APLL2_DIV3, "apll2_div3", "aud_2_sel", 0x12c, 19, 0x128, 8, 16),
DIV_GATE(CLK_TOP_APLL2_DIV4, "apll2_div4", "aud_2_sel", 0x12c, 20, 0x128, 8, 24),
DIV_GATE(CLK_TOP_APLL2_DIV5, "apll2_div5", "apll2_div4", 0x12c, 21, 0x12c, 4, 4),
};
static const struct mtk_clk_desc topck_desc = {
.fixed_clks = fixed_clks,
.num_fixed_clks = ARRAY_SIZE(fixed_clks),
.factor_clks = top_divs,
.num_factor_clks = ARRAY_SIZE(top_divs),
.mux_clks = top_muxes,
.num_mux_clks = ARRAY_SIZE(top_muxes),
.composite_clks = top_aud_divs,
.num_composite_clks = ARRAY_SIZE(top_aud_divs),
.clk_lock = &mt6795_top_clk_lock,
};
static const struct of_device_id of_match_clk_mt6795_topckgen[] = {
{ .compatible = "mediatek,mt6795-topckgen", .data = &topck_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_topckgen);
static struct platform_driver clk_mt6795_topckgen_drv = {
.driver = {
.name = "clk-mt6795-topckgen",
.of_match_table = of_match_clk_mt6795_topckgen,
},
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt6795_topckgen_drv);
MODULE_DESCRIPTION("MediaTek MT6795 topckgen clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6795-topckgen.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8186-clk.h>
static const struct mtk_gate_regs vdec0_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x4,
.sta_ofs = 0x0,
};
static const struct mtk_gate_regs vdec1_cg_regs = {
.set_ofs = 0x190,
.clr_ofs = 0x190,
.sta_ofs = 0x190,
};
static const struct mtk_gate_regs vdec2_cg_regs = {
.set_ofs = 0x200,
.clr_ofs = 0x204,
.sta_ofs = 0x200,
};
static const struct mtk_gate_regs vdec3_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0xc,
.sta_ofs = 0x8,
};
#define GATE_VDEC0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
#define GATE_VDEC1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
#define GATE_VDEC2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
#define GATE_VDEC3(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec3_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate vdec_clks[] = {
/* VDEC0 */
GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "top_vdec", 0),
GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "top_vdec", 4),
GATE_VDEC0(CLK_VDEC_CKEN_ENG, "vdec_cken_eng", "top_vdec", 8),
/* VDEC1 */
GATE_VDEC1(CLK_VDEC_MINI_MDP_CKEN_CFG_RG, "vdec_mini_mdp_cken_cfg_rg", "top_vdec", 0),
/* VDEC2 */
GATE_VDEC2(CLK_VDEC_LAT_CKEN, "vdec_lat_cken", "top_vdec", 0),
GATE_VDEC2(CLK_VDEC_LAT_ACTIVE, "vdec_lat_active", "top_vdec", 4),
GATE_VDEC2(CLK_VDEC_LAT_CKEN_ENG, "vdec_lat_cken_eng", "top_vdec", 8),
/* VDEC3 */
GATE_VDEC3(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "top_vdec", 0),
};
static const struct mtk_clk_desc vdec_desc = {
.clks = vdec_clks,
.num_clks = ARRAY_SIZE(vdec_clks),
};
static const struct of_device_id of_match_clk_mt8186_vdec[] = {
{
.compatible = "mediatek,mt8186-vdecsys",
.data = &vdec_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_vdec);
static struct platform_driver clk_mt8186_vdec_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8186-vdec",
.of_match_table = of_match_clk_mt8186_vdec,
},
};
module_platform_driver(clk_mt8186_vdec_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8186-vdec.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 MediaTek Inc.
* Author: Wenzhen Yu <Wenzhen [email protected]>
* Ryder Lee <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt7629-clk.h>
#define GATE_ETH(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate_regs eth_cg_regs = {
.set_ofs = 0x30,
.clr_ofs = 0x30,
.sta_ofs = 0x30,
};
static const struct mtk_gate eth_clks[] = {
GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "eth2pll", 6),
GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 16),
};
static const struct mtk_gate_regs sgmii_cg_regs = {
.set_ofs = 0xE4,
.clr_ofs = 0xE4,
.sta_ofs = 0xE4,
};
#define GATE_SGMII(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &sgmii_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate sgmii_clks[2][4] = {
{
GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en",
"ssusb_tx250m", 2),
GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en",
"ssusb_eq_rx250m", 3),
GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
"ssusb_cdr_ref", 4),
GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
"ssusb_cdr_fb", 5),
}, {
GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en1",
"ssusb_tx250m", 2),
GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en1",
"ssusb_eq_rx250m", 3),
GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref1",
"ssusb_cdr_ref", 4),
GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb1",
"ssusb_cdr_fb", 5),
}
};
static u16 rst_ofs[] = { 0x34, };
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SIMPLE,
.rst_bank_ofs = rst_ofs,
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
static int clk_mt7629_ethsys_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
mtk_clk_register_gates(&pdev->dev, node, eth_clks,
CLK_ETH_NR_CLK, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
return r;
}
static int clk_mt7629_sgmiisys_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
static int id;
int r;
clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
mtk_clk_register_gates(&pdev->dev, node, sgmii_clks[id++],
CLK_SGMII_NR_CLK, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
return r;
}
static const struct of_device_id of_match_clk_mt7629_eth[] = {
{
.compatible = "mediatek,mt7629-ethsys",
.data = clk_mt7629_ethsys_init,
}, {
.compatible = "mediatek,mt7629-sgmiisys",
.data = clk_mt7629_sgmiisys_init,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7629_eth);
static int clk_mt7629_eth_probe(struct platform_device *pdev)
{
int (*clk_init)(struct platform_device *);
int r;
clk_init = of_device_get_match_data(&pdev->dev);
if (!clk_init)
return -EINVAL;
r = clk_init(pdev);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
return r;
}
static struct platform_driver clk_mt7629_eth_drv = {
.probe = clk_mt7629_eth_probe,
.driver = {
.name = "clk-mt7629-eth",
.of_match_table = of_match_clk_mt7629_eth,
},
};
builtin_platform_driver(clk_mt7629_eth_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt7629-eth.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 Collabora Ltd.
* Author: AngeloGioacchino Del Regno <[email protected]>
*/
#include <dt-bindings/clock/mediatek,mt6795-clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#define GATE_MM0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_MM1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate_regs mm0_cg_regs = {
.set_ofs = 0x0104,
.clr_ofs = 0x0108,
.sta_ofs = 0x0100,
};
static const struct mtk_gate_regs mm1_cg_regs = {
.set_ofs = 0x0114,
.clr_ofs = 0x0118,
.sta_ofs = 0x0110,
};
static const struct mtk_gate mm_gates[] = {
/* MM0 */
GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
GATE_MM0(CLK_MM_MDP_CROP, "mm_mdp_crop", "mm_sel", 10),
GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "clk32k", 15),
GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
GATE_MM0(CLK_MM_DISP_SPLIT1, "mm_disp_split1", "mm_sel", 29),
GATE_MM0(CLK_MM_DISP_MERGE, "mm_disp_merge", "mm_sel", 30),
GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
/* MM1 */
GATE_MM1(CLK_MM_DISP_PWM0MM, "mm_disp_pwm0mm", "mm_sel", 0),
GATE_MM1(CLK_MM_DISP_PWM026M, "mm_disp_pwm026m", "pwm_sel", 1),
GATE_MM1(CLK_MM_DISP_PWM1MM, "mm_disp_pwm1mm", "mm_sel", 2),
GATE_MM1(CLK_MM_DISP_PWM126M, "mm_disp_pwm126m", "pwm_sel", 3),
GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_dig", 5),
GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_dig", 7),
GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "dpi0_sel", 8),
GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
};
static const struct mtk_clk_desc mm_desc = {
.clks = mm_gates,
.num_clks = ARRAY_SIZE(mm_gates),
};
static const struct platform_device_id clk_mt6795_mm_id_table[] = {
{ .name = "clk-mt6795-mm", .driver_data = (kernel_ulong_t)&mm_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, clk_mt6795_mm_id_table);
static struct platform_driver clk_mt6795_mm_drv = {
.driver = {
.name = "clk-mt6795-mm",
},
.id_table = clk_mt6795_mm_id_table,
.probe = mtk_clk_pdev_probe,
.remove_new = mtk_clk_pdev_remove,
};
module_platform_driver(clk_mt6795_mm_drv);
MODULE_DESCRIPTION("MediaTek MT6795 MultiMedia clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6795-mm.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt8186-clk.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs ipe_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_IPE(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate ipe_clks[] = {
GATE_IPE(CLK_IPE_LARB19, "ipe_larb19", "top_ipe", 0),
GATE_IPE(CLK_IPE_LARB20, "ipe_larb20", "top_ipe", 1),
GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "top_ipe", 2),
GATE_IPE(CLK_IPE_FD, "ipe_fd", "top_ipe", 3),
GATE_IPE(CLK_IPE_FE, "ipe_fe", "top_ipe", 4),
GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "top_ipe", 5),
GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "top_ipe", 6),
GATE_IPE(CLK_IPE_GALS_IPE, "ipe_gals_ipe", "top_img1", 8),
};
static const struct mtk_clk_desc ipe_desc = {
.clks = ipe_clks,
.num_clks = ARRAY_SIZE(ipe_clks),
};
static const struct of_device_id of_match_clk_mt8186_ipe[] = {
{
.compatible = "mediatek,mt8186-ipesys",
.data = &ipe_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_ipe);
static struct platform_driver clk_mt8186_ipe_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8186-ipe",
.of_match_table = of_match_clk_mt8186_ipe,
},
};
module_platform_driver(clk_mt8186_ipe_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8186-ipe.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8192-clk.h>
static const struct mtk_gate_regs img_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_IMG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate img_clks[] = {
GATE_IMG(CLK_IMG_LARB9, "img_larb9", "img1_sel", 0),
GATE_IMG(CLK_IMG_LARB10, "img_larb10", "img1_sel", 1),
GATE_IMG(CLK_IMG_DIP, "img_dip", "img1_sel", 2),
GATE_IMG(CLK_IMG_GALS, "img_gals", "img1_sel", 12),
};
static const struct mtk_gate img2_clks[] = {
GATE_IMG(CLK_IMG2_LARB11, "img2_larb11", "img1_sel", 0),
GATE_IMG(CLK_IMG2_LARB12, "img2_larb12", "img1_sel", 1),
GATE_IMG(CLK_IMG2_MFB, "img2_mfb", "img1_sel", 6),
GATE_IMG(CLK_IMG2_WPE, "img2_wpe", "img1_sel", 7),
GATE_IMG(CLK_IMG2_MSS, "img2_mss", "img1_sel", 8),
GATE_IMG(CLK_IMG2_GALS, "img2_gals", "img1_sel", 12),
};
static const struct mtk_clk_desc img_desc = {
.clks = img_clks,
.num_clks = ARRAY_SIZE(img_clks),
};
static const struct mtk_clk_desc img2_desc = {
.clks = img2_clks,
.num_clks = ARRAY_SIZE(img2_clks),
};
static const struct of_device_id of_match_clk_mt8192_img[] = {
{
.compatible = "mediatek,mt8192-imgsys",
.data = &img_desc,
}, {
.compatible = "mediatek,mt8192-imgsys2",
.data = &img2_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_img);
static struct platform_driver clk_mt8192_img_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8192-img",
.of_match_table = of_match_clk_mt8192_img,
},
};
module_platform_driver(clk_mt8192_img_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8192-img.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Shunli Wang <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt2701-clk.h>
static const struct mtk_gate_regs img_cg_regs = {
.set_ofs = 0x0004,
.clr_ofs = 0x0008,
.sta_ofs = 0x0000,
};
#define GATE_IMG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate img_clks[] = {
GATE_IMG(CLK_IMG_SMI_COMM, "img_smi_comm", "mm_sel", 0),
GATE_IMG(CLK_IMG_RESZ, "img_resz", "mm_sel", 1),
GATE_IMG(CLK_IMG_JPGDEC_SMI, "img_jpgdec_smi", "mm_sel", 5),
GATE_IMG(CLK_IMG_JPGDEC, "img_jpgdec", "mm_sel", 6),
GATE_IMG(CLK_IMG_VENC_LT, "img_venc_lt", "mm_sel", 8),
GATE_IMG(CLK_IMG_VENC, "img_venc", "mm_sel", 9),
};
static const struct mtk_clk_desc img_desc = {
.clks = img_clks,
.num_clks = ARRAY_SIZE(img_clks),
};
static const struct of_device_id of_match_clk_mt2701_img[] = {
{
.compatible = "mediatek,mt2701-imgsys",
.data = &img_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_img);
static struct platform_driver clk_mt2701_img_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt2701-img",
.of_match_table = of_match_clk_mt2701_img,
},
};
module_platform_driver(clk_mt2701_img_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt2701-img.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 MediaTek Inc.
* Author: Sean Wang <[email protected]>
*
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt2701-clk.h>
#define GATE_G3D(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &g3d_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate_regs g3d_cg_regs = {
.sta_ofs = 0x0,
.set_ofs = 0x4,
.clr_ofs = 0x8,
};
static const struct mtk_gate g3d_clks[] = {
GATE_DUMMY(CLK_DUMMY, "g3d_dummy"),
GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
};
static u16 rst_ofs[] = { 0xc, };
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SIMPLE,
.rst_bank_ofs = rst_ofs,
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
static const struct mtk_clk_desc g3d_desc = {
.clks = g3d_clks,
.num_clks = ARRAY_SIZE(g3d_clks),
.rst_desc = &clk_rst_desc,
};
static const struct of_device_id of_match_clk_mt2701_g3d[] = {
{ .compatible = "mediatek,mt2701-g3dsys", .data = &g3d_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_g3d);
static struct platform_driver clk_mt2701_g3d_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt2701-g3d",
.of_match_table = of_match_clk_mt2701_g3d,
},
};
module_platform_driver(clk_mt2701_g3d_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt2701-g3d.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt8186-clk.h>
#include "clk-mtk.h"
#include "clk-mux.h"
static DEFINE_SPINLOCK(mt8186_clk_lock);
static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK(CLK_TOP_ULPOSC1, "ulposc1", NULL, 250000000),
FIXED_CLK(CLK_TOP_466M_FMEM, "hd_466m_fmem_ck", NULL, 466000000),
FIXED_CLK(CLK_TOP_MPLL, "mpll", NULL, 208000000),
};
static const struct mtk_fixed_factor top_divs[] = {
FACTOR_FLAGS(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D32, "univpll_d3_d32", "univpll_d3", 1, 32, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univ2pll", 1, 13, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32, 0),
FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
FACTOR(CLK_TOP_TVDPLL_D32, "tvdpll_d32", "tvdpll", 1, 32),
FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc1", 1, 2),
FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc1", 1, 4),
FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc1", 1, 8),
FACTOR(CLK_TOP_ULPOSC1_D10, "ulposc1_d10", "ulposc1", 1, 10),
FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc1", 1, 16),
FACTOR(CLK_TOP_ULPOSC1_D32, "ulposc1_d32", "ulposc1", 1, 32),
FACTOR(CLK_TOP_ADSPPLL_D2, "adsppll_d2", "adsppll", 1, 2),
FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
FACTOR(CLK_TOP_ADSPPLL_D8, "adsppll_d8", "adsppll", 1, 8),
FACTOR(CLK_TOP_NNAPLL_D2, "nnapll_d2", "nnapll", 1, 2),
FACTOR(CLK_TOP_NNAPLL_D4, "nnapll_d4", "nnapll", 1, 4),
FACTOR(CLK_TOP_NNAPLL_D8, "nnapll_d8", "nnapll", 1, 8),
FACTOR(CLK_TOP_NNA2PLL_D2, "nna2pll_d2", "nna2pll", 1, 2),
FACTOR(CLK_TOP_NNA2PLL_D4, "nna2pll_d4", "nna2pll", 1, 4),
FACTOR(CLK_TOP_NNA2PLL_D8, "nna2pll_d8", "nna2pll", 1, 8),
FACTOR(CLK_TOP_F_BIST2FPC, "f_bist2fpc_ck", "univpll_d3_d2", 1, 1),
};
static const char * const axi_parents[] = {
"clk26m",
"mainpll_d7",
"mainpll_d2_d4",
"univpll_d7"
};
static const char * const scp_parents[] = {
"clk26m",
"mainpll_d2_d4",
"mainpll_d5",
"mainpll_d2_d2",
"mainpll_d3",
"univpll_d3"
};
static const char * const mfg_parents[] = {
"clk26m",
"mfgpll",
"mainpll_d3",
"mainpll_d5"
};
static const char * const camtg_parents[] = {
"clk26m",
"univpll_192m_d8",
"univpll_d3_d8",
"univpll_192m_d4",
"univpll_d3_d32",
"univpll_192m_d16",
"univpll_192m_d32"
};
static const char * const uart_parents[] = {
"clk26m",
"univpll_d3_d8"
};
static const char * const spi_parents[] = {
"clk26m",
"mainpll_d5_d4",
"mainpll_d3_d4",
"mainpll_d5_d2",
"mainpll_d2_d4",
"mainpll_d7",
"mainpll_d3_d2",
"mainpll_d5"
};
static const char * const msdc5hclk_parents[] = {
"clk26m",
"mainpll_d2_d2",
"mainpll_d7",
"mainpll_d3_d2"
};
static const char * const msdc50_0_parents[] = {
"clk26m",
"msdcpll",
"univpll_d3",
"msdcpll_d2",
"mainpll_d7",
"mainpll_d3_d2",
"univpll_d2_d2"
};
static const char * const msdc30_1_parents[] = {
"clk26m",
"msdcpll_d2",
"univpll_d3_d2",
"mainpll_d3_d2",
"mainpll_d7"
};
static const char * const audio_parents[] = {
"clk26m",
"mainpll_d5_d4",
"mainpll_d7_d4",
"mainpll_d2_d16"
};
static const char * const aud_intbus_parents[] = {
"clk26m",
"mainpll_d2_d4",
"mainpll_d7_d2"
};
static const char * const aud_1_parents[] = {
"clk26m",
"apll1"
};
static const char * const aud_2_parents[] = {
"clk26m",
"apll2"
};
static const char * const aud_engen1_parents[] = {
"clk26m",
"apll1_d2",
"apll1_d4",
"apll1_d8"
};
static const char * const aud_engen2_parents[] = {
"clk26m",
"apll2_d2",
"apll2_d4",
"apll2_d8"
};
static const char * const disp_pwm_parents[] = {
"clk26m",
"univpll_d5_d2",
"univpll_d3_d4",
"ulposc1_d2",
"ulposc1_d8"
};
static const char * const sspm_parents[] = {
"clk26m",
"mainpll_d2_d2",
"mainpll_d3_d2",
"mainpll_d5",
"mainpll_d3"
};
static const char * const dxcc_parents[] = {
"clk26m",
"mainpll_d2_d2",
"mainpll_d2_d4"
};
static const char * const usb_parents[] = {
"clk26m",
"univpll_d5_d4",
"univpll_d5_d2"
};
static const char * const srck_parents[] = {
"clk32k",
"clk26m",
"ulposc1_d10"
};
static const char * const spm_parents[] = {
"clk32k",
"ulposc1_d10",
"clk26m",
"mainpll_d7_d2"
};
static const char * const i2c_parents[] = {
"clk26m",
"univpll_d5_d4",
"univpll_d3_d4",
"univpll_d5_d2"
};
static const char * const pwm_parents[] = {
"clk26m",
"univpll_d3_d8",
"univpll_d3_d4",
"univpll_d2_d4"
};
static const char * const seninf_parents[] = {
"clk26m",
"univpll_d2_d4",
"univpll_d2_d2",
"univpll_d3_d2"
};
static const char * const aes_msdcfde_parents[] = {
"clk26m",
"univpll_d3",
"mainpll_d3",
"univpll_d2_d2",
"mainpll_d2_d2",
"mainpll_d2_d4"
};
static const char * const pwrap_ulposc_parents[] = {
"clk26m",
"univpll_d5_d4",
"ulposc1_d4",
"ulposc1_d8",
"ulposc1_d10",
"ulposc1_d16",
"ulposc1_d32"
};
static const char * const camtm_parents[] = {
"clk26m",
"univpll_d2_d4",
"univpll_d3_d2"
};
static const char * const venc_parents[] = {
"clk26m",
"mmpll",
"mainpll_d2_d2",
"mainpll_d2",
"univpll_d3",
"univpll_d2_d2",
"mainpll_d3",
"mmpll"
};
static const char * const isp_parents[] = {
"clk26m",
"mainpll_d2",
"mainpll_d2_d2",
"univpll_d3",
"mainpll_d3",
"mmpll",
"univpll_d5",
"univpll_d2_d2",
"mmpll_d2"
};
static const char * const dpmaif_parents[] = {
"clk26m",
"univpll_d2_d2",
"mainpll_d3",
"mainpll_d2_d2",
"univpll_d3_d2"
};
static const char * const vdec_parents[] = {
"clk26m",
"mainpll_d3",
"mainpll_d2_d2",
"univpll_d5",
"mainpll_d2",
"univpll_d3",
"univpll_d2_d2"
};
static const char * const disp_parents[] = {
"clk26m",
"univpll_d3_d2",
"mainpll_d5",
"univpll_d5",
"univpll_d2_d2",
"mainpll_d3",
"univpll_d3",
"mainpll_d2",
"mmpll"
};
static const char * const mdp_parents[] = {
"clk26m",
"mainpll_d5",
"univpll_d5",
"mainpll_d2_d2",
"univpll_d2_d2",
"mainpll_d3",
"univpll_d3",
"mainpll_d2",
"mmpll"
};
static const char * const audio_h_parents[] = {
"clk26m",
"univpll_d7",
"apll1",
"apll2"
};
static const char * const ufs_parents[] = {
"clk26m",
"mainpll_d7",
"univpll_d2_d4",
"mainpll_d2_d4"
};
static const char * const aes_fde_parents[] = {
"clk26m",
"univpll_d3",
"mainpll_d2_d2",
"univpll_d5"
};
static const char * const audiodsp_parents[] = {
"clk26m",
"ulposc1_d10",
"adsppll",
"adsppll_d2",
"adsppll_d4",
"adsppll_d8"
};
static const char * const dvfsrc_parents[] = {
"clk26m",
"ulposc1_d10",
};
static const char * const dsi_occ_parents[] = {
"clk26m",
"univpll_d3_d2",
"mpll",
"mainpll_d5"
};
static const char * const spmi_mst_parents[] = {
"clk26m",
"univpll_d5_d4",
"ulposc1_d4",
"ulposc1_d8",
"ulposc1_d10",
"ulposc1_d16",
"ulposc1_d32"
};
static const char * const spinor_parents[] = {
"clk26m",
"clk13m",
"mainpll_d7_d4",
"univpll_d3_d8",
"univpll_d5_d4",
"mainpll_d7_d2"
};
static const char * const nna_parents[] = {
"clk26m",
"univpll_d3_d8",
"mainpll_d2_d4",
"univpll_d3_d2",
"mainpll_d2_d2",
"univpll_d2_d2",
"mainpll_d3",
"univpll_d3",
"mmpll",
"mainpll_d2",
"univpll_d2",
"nnapll_d2",
"nnapll_d4",
"nnapll_d8",
"nnapll",
"nna2pll"
};
static const char * const nna2_parents[] = {
"clk26m",
"univpll_d3_d8",
"mainpll_d2_d4",
"univpll_d3_d2",
"mainpll_d2_d2",
"univpll_d2_d2",
"mainpll_d3",
"univpll_d3",
"mmpll",
"mainpll_d2",
"univpll_d2",
"nna2pll_d2",
"nna2pll_d4",
"nna2pll_d8",
"nnapll",
"nna2pll"
};
static const char * const ssusb_parents[] = {
"clk26m",
"univpll_d5_d4",
"univpll_d5_d2"
};
static const char * const wpe_parents[] = {
"clk26m",
"univpll_d3_d2",
"mainpll_d5",
"univpll_d5",
"univpll_d2_d2",
"mainpll_d3",
"univpll_d3",
"mainpll_d2",
"mmpll"
};
static const char * const dpi_parents[] = {
"clk26m",
"tvdpll",
"tvdpll_d2",
"tvdpll_d4",
"tvdpll_d8",
"tvdpll_d16",
"tvdpll_d32"
};
static const char * const u3_occ_250m_parents[] = {
"clk26m",
"univpll_d5"
};
static const char * const u3_occ_500m_parents[] = {
"clk26m",
"nna2pll_d2"
};
static const char * const adsp_bus_parents[] = {
"clk26m",
"ulposc1_d2",
"mainpll_d5",
"mainpll_d2_d2",
"mainpll_d3",
"mainpll_d2",
"univpll_d3"
};
static const char * const apll_mck_parents[] = {
"top_aud_1",
"top_aud_2"
};
static const struct mtk_mux top_mtk_muxes[] = {
/*
* CLK_CFG_0
* top_axi is bus clock, should not be closed by Linux.
* top_scp is main clock in always-on co-processor.
*/
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi", axi_parents,
0x0040, 0x0044, 0x0048, 0, 2, 7, 0x0004, 0,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp", scp_parents,
0x0040, 0x0044, 0x0048, 8, 3, 15, 0x0004, 1,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG, "top_mfg",
mfg_parents, 0x0040, 0x0044, 0x0048, 16, 2, 23, 0x0004, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
camtg_parents, 0x0040, 0x0044, 0x0048, 24, 3, 31, 0x0004, 3),
/* CLK_CFG_1 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1, "top_camtg1",
camtg_parents, 0x0050, 0x0054, 0x0058, 0, 3, 7, 0x0004, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2",
camtg_parents, 0x0050, 0x0054, 0x0058, 8, 3, 15, 0x0004, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3",
camtg_parents, 0x0050, 0x0054, 0x0058, 16, 3, 23, 0x0004, 6),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "top_camtg4",
camtg_parents, 0x0050, 0x0054, 0x0058, 24, 3, 31, 0x0004, 7),
/* CLK_CFG_2 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "top_camtg5",
camtg_parents, 0x0060, 0x0064, 0x0068, 0, 3, 7, 0x0004, 8),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG6, "top_camtg6",
camtg_parents, 0x0060, 0x0064, 0x0068, 8, 3, 15, 0x0004, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart",
uart_parents, 0x0060, 0x0064, 0x0068, 16, 1, 23, 0x0004, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
spi_parents, 0x0060, 0x0064, 0x0068, 24, 3, 31, 0x0004, 11),
/* CLK_CFG_3 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk",
msdc5hclk_parents, 0x0070, 0x0074, 0x0078, 0, 2, 7, 0x0004, 12, 0),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0",
msdc50_0_parents, 0x0070, 0x0074, 0x0078, 8, 3, 15, 0x0004, 13, 0),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "top_msdc30_1",
msdc30_1_parents, 0x0070, 0x0074, 0x0078, 16, 3, 23, 0x0004, 14, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO, "top_audio",
audio_parents, 0x0070, 0x0074, 0x0078, 24, 2, 31, 0x0004, 15),
/* CLK_CFG_4 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
aud_intbus_parents, 0x0080, 0x0084, 0x0088, 0, 2, 7, 0x0004, 16),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1, "top_aud_1",
aud_1_parents, 0x0080, 0x0084, 0x0088, 8, 1, 15, 0x0004, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2, "top_aud_2",
aud_2_parents, 0x0080, 0x0084, 0x0088, 16, 1, 23, 0x0004, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1, "top_aud_engen1",
aud_engen1_parents, 0x0080, 0x0084, 0x0088, 24, 2, 31, 0x0004, 19),
/*
* CLK_CFG_5
* top_sspm is main clock in always-on co-processor, should not be closed
* in Linux.
*/
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2, "top_aud_engen2",
aud_engen2_parents, 0x0090, 0x0094, 0x0098, 0, 2, 7, 0x0004, 20),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM, "top_disp_pwm",
disp_pwm_parents, 0x0090, 0x0094, 0x0098, 8, 3, 15, 0x0004, 21),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM, "top_sspm", sspm_parents,
0x0090, 0x0094, 0x0098, 16, 3, 23, 0x0004, 22,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "top_dxcc",
dxcc_parents, 0x0090, 0x0094, 0x0098, 24, 2, 31, 0x0004, 23),
/*
* CLK_CFG_6
* top_spm and top_srck are main clocks in always-on co-processor.
*/
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "top_usb",
usb_parents, 0x00a0, 0x00a4, 0x00a8, 0, 2, 7, 0x0004, 24),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck", srck_parents,
0x00a0, 0x00a4, 0x00a8, 8, 2, 15, 0x0004, 25,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm", spm_parents,
0x00a0, 0x00a4, 0x00a8, 16, 2, 23, 0x0004, 26,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c",
i2c_parents, 0x00a0, 0x00a4, 0x00a8, 24, 2, 31, 0x0004, 27),
/* CLK_CFG_7 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm",
pwm_parents, 0x00b0, 0x00b4, 0x00b8, 0, 2, 7, 0x0004, 28),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "top_seninf",
seninf_parents, 0x00b0, 0x00b4, 0x00b8, 8, 2, 15, 0x0004, 29),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "top_seninf1",
seninf_parents, 0x00b0, 0x00b4, 0x00b8, 16, 2, 23, 0x0004, 30),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "top_seninf2",
seninf_parents, 0x00b0, 0x00b4, 0x00b8, 24, 2, 31, 0x0008, 0),
/* CLK_CFG_8 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3, "top_seninf3",
seninf_parents, 0x00c0, 0x00c4, 0x00c8, 0, 2, 7, 0x0008, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE, "top_aes_msdcfde",
aes_msdcfde_parents, 0x00c0, 0x00c4, 0x00c8, 8, 3, 15, 0x0008, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC, "top_pwrap_ulposc",
pwrap_ulposc_parents, 0x00c0, 0x00c4, 0x00c8, 16, 3, 23, 0x0008, 3),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
camtm_parents, 0x00c0, 0x00c4, 0x00c8, 24, 2, 31, 0x0008, 4),
/* CLK_CFG_9 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "top_venc",
venc_parents, 0x00d0, 0x00d4, 0x00d8, 0, 3, 7, 0x0008, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
isp_parents, 0x00d0, 0x00d4, 0x00d8, 8, 4, 15, 0x0008, 6),
MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1, "top_img1",
isp_parents, 0x00d0, 0x00d4, 0x00d8, 16, 4, 23, 0x0008, 7),
MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
isp_parents, 0x00d0, 0x00d4, 0x00d8, 24, 4, 31, 0x0008, 8),
/* CLK_CFG_10 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF, "top_dpmaif",
dpmaif_parents, 0x00e0, 0x00e4, 0x00e8, 0, 3, 7, 0x0008, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "top_vdec",
vdec_parents, 0x00e0, 0x00e4, 0x00e8, 8, 3, 15, 0x0008, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP, "top_disp",
disp_parents, 0x00e0, 0x00e4, 0x00e8, 16, 4, 23, 0x0008, 11),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP, "top_mdp",
mdp_parents, 0x00e0, 0x00e4, 0x00e8, 24, 4, 31, 0x0008, 12),
/* CLK_CFG_11 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H, "top_audio_h",
audio_h_parents, 0x00ec, 0x00f0, 0x00f4, 0, 2, 7, 0x0008, 13),
MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS, "top_ufs",
ufs_parents, 0x00ec, 0x00f0, 0x00f4, 8, 2, 15, 0x0008, 14),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE, "top_aes_fde",
aes_fde_parents, 0x00ec, 0x00f0, 0x00f4, 16, 2, 23, 0x0008, 15),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIODSP, "top_audiodsp",
audiodsp_parents, 0x00ec, 0x00f0, 0x00f4, 24, 3, 31, 0x0008, 16),
/*
* CLK_CFG_12
* dvfsrc is for internal DVFS usage, should not be closed in Linux.
*/
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc", dvfsrc_parents,
0x0100, 0x0104, 0x0108, 0, 1, 7, 0x0008, 17,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ",
dsi_occ_parents, 0x0100, 0x0104, 0x0108, 8, 2, 15, 0x0008, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_MST, "top_spmi_mst",
spmi_mst_parents, 0x0100, 0x0104, 0x0108, 16, 3, 23, 0x0008, 19),
/* CLK_CFG_13 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor",
spinor_parents, 0x0110, 0x0114, 0x0118, 0, 3, 6, 0x0008, 20),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA, "top_nna",
nna_parents, 0x0110, 0x0114, 0x0118, 7, 4, 14, 0x0008, 21),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA1, "top_nna1",
nna_parents, 0x0110, 0x0114, 0x0118, 15, 4, 22, 0x0008, 22),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA2, "top_nna2",
nna2_parents, 0x0110, 0x0114, 0x0118, 23, 4, 30, 0x0008, 23),
/* CLK_CFG_14 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI, "top_ssusb_xhci",
ssusb_parents, 0x0120, 0x0124, 0x0128, 0, 2, 5, 0x0008, 24),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_TOP_1P, "top_ssusb_1p",
ssusb_parents, 0x0120, 0x0124, 0x0128, 6, 2, 11, 0x0008, 25),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_1P, "top_ssusb_xhci_1p",
ssusb_parents, 0x0120, 0x0124, 0x0128, 12, 2, 17, 0x0008, 26),
MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE, "top_wpe",
wpe_parents, 0x0120, 0x0124, 0x0128, 18, 4, 25, 0x0008, 27),
/* CLK_CFG_15 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",
dpi_parents, 0x0180, 0x0184, 0x0188, 0, 3, 6, 0x0008, 28),
MUX_GATE_CLR_SET_UPD(CLK_TOP_U3_OCC_250M, "top_u3_occ_250m",
u3_occ_250m_parents, 0x0180, 0x0184, 0x0188, 7, 1, 11, 0x0008, 29),
MUX_GATE_CLR_SET_UPD(CLK_TOP_U3_OCC_500M, "top_u3_occ_500m",
u3_occ_500m_parents, 0x0180, 0x0184, 0x0188, 12, 1, 16, 0x0008, 30),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_BUS, "top_adsp_bus",
adsp_bus_parents, 0x0180, 0x0184, 0x0188, 17, 3, 23, 0x0008, 31),
};
static struct mtk_composite top_muxes[] = {
/* CLK_AUDDIV_0 */
MUX(CLK_TOP_APLL_I2S0_MCK_SEL, "apll_i2s0_mck_sel", apll_mck_parents, 0x0320, 16, 1),
MUX(CLK_TOP_APLL_I2S1_MCK_SEL, "apll_i2s1_mck_sel", apll_mck_parents, 0x0320, 17, 1),
MUX(CLK_TOP_APLL_I2S2_MCK_SEL, "apll_i2s2_mck_sel", apll_mck_parents, 0x0320, 18, 1),
MUX(CLK_TOP_APLL_I2S4_MCK_SEL, "apll_i2s4_mck_sel", apll_mck_parents, 0x0320, 19, 1),
MUX(CLK_TOP_APLL_TDMOUT_MCK_SEL, "apll_tdmout_mck_sel", apll_mck_parents,
0x0320, 20, 1),
DIV_GATE(CLK_TOP_APLL12_CK_DIV0, "apll12_div0", "apll_i2s0_mck_sel",
0x0320, 0, 0x0328, 8, 0),
DIV_GATE(CLK_TOP_APLL12_CK_DIV1, "apll12_div1", "apll_i2s1_mck_sel",
0x0320, 1, 0x0328, 8, 8),
DIV_GATE(CLK_TOP_APLL12_CK_DIV2, "apll12_div2", "apll_i2s2_mck_sel",
0x0320, 2, 0x0328, 8, 16),
DIV_GATE(CLK_TOP_APLL12_CK_DIV4, "apll12_div4", "apll_i2s4_mck_sel",
0x0320, 3, 0x0328, 8, 24),
DIV_GATE(CLK_TOP_APLL12_CK_DIV_TDMOUT_M, "apll12_div_tdmout_m", "apll_tdmout_mck_sel",
0x0320, 4, 0x0334, 8, 0),
};
/* Register mux notifier for MFG mux */
static int clk_mt8186_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
{
struct mtk_mux_nb *mfg_mux_nb;
int i;
mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
if (!mfg_mux_nb)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(top_mtk_muxes); i++)
if (top_mtk_muxes[i].id == CLK_TOP_MFG)
break;
if (i == ARRAY_SIZE(top_mtk_muxes))
return -EINVAL;
mfg_mux_nb->ops = top_mtk_muxes[i].ops;
mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */
return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
}
static const struct mtk_clk_desc topck_desc = {
.fixed_clks = top_fixed_clks,
.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
.factor_clks = top_divs,
.num_factor_clks = ARRAY_SIZE(top_divs),
.mux_clks = top_mtk_muxes,
.num_mux_clks = ARRAY_SIZE(top_mtk_muxes),
.composite_clks = top_muxes,
.num_composite_clks = ARRAY_SIZE(top_muxes),
.clk_lock = &mt8186_clk_lock,
.clk_notifier_func = clk_mt8186_reg_mfg_mux_notifier,
.mfg_clk_idx = CLK_TOP_MFG,
};
static const struct of_device_id of_match_clk_mt8186_topck[] = {
{ .compatible = "mediatek,mt8186-topckgen", .data = &topck_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_topck);
static struct platform_driver clk_mt8186_topck_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8186-topck",
.of_match_table = of_match_clk_mt8186_topck,
},
};
module_platform_driver(clk_mt8186_topck_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8186-topckgen.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 Collabora Ltd.
* Author: AngeloGioacchino Del Regno <[email protected]>
*/
#include <dt-bindings/clock/mt8173-clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#include "reset.h"
#define GATE_PERI0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &peri0_cg_regs, \
_shift, &mtk_clk_gate_ops_setclr)
#define GATE_PERI1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &peri1_cg_regs, \
_shift, &mtk_clk_gate_ops_setclr)
static DEFINE_SPINLOCK(mt8173_clk_lock);
static const struct mtk_gate_regs peri0_cg_regs = {
.set_ofs = 0x0008,
.clr_ofs = 0x0010,
.sta_ofs = 0x0018,
};
static const struct mtk_gate_regs peri1_cg_regs = {
.set_ofs = 0x000c,
.clr_ofs = 0x0014,
.sta_ofs = 0x001c,
};
static const char * const uart_ck_sel_parents[] = {
"clk26m",
"uart_sel",
};
static const struct mtk_composite peri_clks[] = {
MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
};
static const struct mtk_gate peri_gates[] = {
GATE_DUMMY(CLK_DUMMY, "peri_gate_dummy"),
/* PERI0 */
GATE_PERI0(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0),
GATE_PERI0(CLK_PERI_THERM, "peri_therm", "axi_sel", 1),
GATE_PERI0(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2),
GATE_PERI0(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3),
GATE_PERI0(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4),
GATE_PERI0(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5),
GATE_PERI0(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6),
GATE_PERI0(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7),
GATE_PERI0(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8),
GATE_PERI0(CLK_PERI_PWM, "peri_pwm", "axi_sel", 9),
GATE_PERI0(CLK_PERI_USB0, "peri_usb0", "usb20_sel", 10),
GATE_PERI0(CLK_PERI_USB1, "peri_usb1", "usb20_sel", 11),
GATE_PERI0(CLK_PERI_AP_DMA, "peri_ap_dma", "axi_sel", 12),
GATE_PERI0(CLK_PERI_MSDC30_0, "peri_msdc30_0", "msdc50_0_sel", 13),
GATE_PERI0(CLK_PERI_MSDC30_1, "peri_msdc30_1", "msdc30_1_sel", 14),
GATE_PERI0(CLK_PERI_MSDC30_2, "peri_msdc30_2", "msdc30_2_sel", 15),
GATE_PERI0(CLK_PERI_MSDC30_3, "peri_msdc30_3", "msdc30_3_sel", 16),
GATE_PERI0(CLK_PERI_NLI_ARB, "peri_nli_arb", "axi_sel", 17),
GATE_PERI0(CLK_PERI_IRDA, "peri_irda", "irda_sel", 18),
GATE_PERI0(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19),
GATE_PERI0(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20),
GATE_PERI0(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21),
GATE_PERI0(CLK_PERI_UART3, "peri_uart3", "axi_sel", 22),
GATE_PERI0(CLK_PERI_I2C0, "peri_i2c0", "axi_sel", 23),
GATE_PERI0(CLK_PERI_I2C1, "peri_i2c1", "axi_sel", 24),
GATE_PERI0(CLK_PERI_I2C2, "peri_i2c2", "axi_sel", 25),
GATE_PERI0(CLK_PERI_I2C3, "peri_i2c3", "axi_sel", 26),
GATE_PERI0(CLK_PERI_I2C4, "peri_i2c4", "axi_sel", 27),
GATE_PERI0(CLK_PERI_AUXADC, "peri_auxadc", "clk26m", 28),
GATE_PERI0(CLK_PERI_SPI0, "peri_spi0", "spi_sel", 29),
GATE_PERI0(CLK_PERI_I2C5, "peri_i2c5", "axi_sel", 30),
GATE_PERI0(CLK_PERI_NFIECC, "peri_nfiecc", "axi_sel", 31),
/* PERI1 */
GATE_PERI1(CLK_PERI_SPI, "peri_spi", "spi_sel", 0),
GATE_PERI1(CLK_PERI_IRRX, "peri_irrx", "spi_sel", 1),
GATE_PERI1(CLK_PERI_I2C6, "peri_i2c6", "axi_sel", 2),
};
static u16 pericfg_rst_ofs[] = { 0x0, 0x4 };
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SIMPLE,
.rst_bank_ofs = pericfg_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
};
static const struct mtk_clk_desc peri_desc = {
.clks = peri_gates,
.num_clks = ARRAY_SIZE(peri_gates),
.composite_clks = peri_clks,
.num_composite_clks = ARRAY_SIZE(peri_clks),
.clk_lock = &mt8173_clk_lock,
.rst_desc = &clk_rst_desc,
};
static const struct of_device_id of_match_clk_mt8173_pericfg[] = {
{ .compatible = "mediatek,mt8173-pericfg", .data = &peri_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_pericfg);
static struct platform_driver clk_mt8173_pericfg_drv = {
.driver = {
.name = "clk-mt8173-pericfg",
.of_match_table = of_match_clk_mt8173_pericfg,
},
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt8173_pericfg_drv);
MODULE_DESCRIPTION("MediaTek MT8173 pericfg clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8173-pericfg.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Weiyi Lu <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt2712-clk.h>
static const struct mtk_gate_regs jpgdec_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_JPGDEC(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &jpgdec_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate jpgdec_clks[] = {
GATE_JPGDEC(CLK_JPGDEC_JPGDEC1, "jpgdec_jpgdec1", "jpgdec_sel", 0),
GATE_JPGDEC(CLK_JPGDEC_JPGDEC, "jpgdec_jpgdec", "jpgdec_sel", 4),
};
static const struct mtk_clk_desc jpgdec_desc = {
.clks = jpgdec_clks,
.num_clks = ARRAY_SIZE(jpgdec_clks),
};
static const struct of_device_id of_match_clk_mt2712_jpgdec[] = {
{
.compatible = "mediatek,mt2712-jpgdecsys",
.data = &jpgdec_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_jpgdec);
static struct platform_driver clk_mt2712_jpgdec_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt2712-jpgdec",
.of_match_table = of_match_clk_mt2712_jpgdec,
},
};
module_platform_driver(clk_mt2712_jpgdec_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt2712-jpgdec.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs scp_adsp_cg_regs = {
.set_ofs = 0x180,
.clr_ofs = 0x180,
.sta_ofs = 0x180,
};
#define GATE_SCP_ADSP(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &scp_adsp_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate scp_adsp_clks[] = {
GATE_SCP_ADSP(CLK_SCP_ADSP_AUDIODSP, "scp_adsp_audiodsp", "top_adsp", 0),
};
static const struct mtk_clk_desc scp_adsp_desc = {
.clks = scp_adsp_clks,
.num_clks = ARRAY_SIZE(scp_adsp_clks),
};
static const struct of_device_id of_match_clk_mt8195_scp_adsp[] = {
{
.compatible = "mediatek,mt8195-scp_adsp",
.data = &scp_adsp_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_scp_adsp);
static struct platform_driver clk_mt8195_scp_adsp_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8195-scp_adsp",
.of_match_table = of_match_clk_mt8195_scp_adsp,
},
};
module_platform_driver(clk_mt8195_scp_adsp_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8195-scp_adsp.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/mfd/syscon.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-mux.h"
#include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/reset/mt8192-resets.h>
static DEFINE_SPINLOCK(mt8192_clk_lock);
static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK(CLK_TOP_ULPOSC, "ulposc", NULL, 260000000),
};
static const struct mtk_fixed_factor top_divs[] = {
FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16", "mainpll_d4", 1, 16, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0),
FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2),
FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9),
FACTOR(CLK_TOP_APUPLL, "apupll_ck", "apupll", 1, 2),
FACTOR(CLK_TOP_NPUPLL, "npupll_ck", "npupll", 1, 1),
FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
FACTOR(CLK_TOP_OSC_D2, "osc_d2", "ulposc", 1, 2),
FACTOR(CLK_TOP_OSC_D4, "osc_d4", "ulposc", 1, 4),
FACTOR(CLK_TOP_OSC_D8, "osc_d8", "ulposc", 1, 8),
FACTOR(CLK_TOP_OSC_D10, "osc_d10", "ulposc", 1, 10),
FACTOR(CLK_TOP_OSC_D16, "osc_d16", "ulposc", 1, 16),
FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20),
FACTOR(CLK_TOP_CSW_F26M_D2, "csw_f26m_d2", "clk26m", 1, 2),
FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll_192m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32, 0),
};
static const char * const axi_parents[] = {
"clk26m",
"mainpll_d4_d4",
"mainpll_d7_d2",
"mainpll_d4_d2",
"mainpll_d5_d2",
"mainpll_d6_d2",
"osc_d4"
};
static const char * const spm_parents[] = {
"clk26m",
"osc_d10",
"mainpll_d7_d4",
"clk32k"
};
static const char * const scp_parents[] = {
"clk26m",
"univpll_d5",
"mainpll_d6_d2",
"mainpll_d6",
"univpll_d6",
"mainpll_d4_d2",
"mainpll_d5_d2",
"univpll_d4_d2"
};
static const char * const bus_aximem_parents[] = {
"clk26m",
"mainpll_d7_d2",
"mainpll_d4_d2",
"mainpll_d5_d2",
"mainpll_d6"
};
static const char * const disp_parents[] = {
"clk26m",
"univpll_d6_d2",
"mainpll_d5_d2",
"mmpll_d6_d2",
"univpll_d5_d2",
"univpll_d4_d2",
"mmpll_d7",
"univpll_d6",
"mainpll_d4",
"mmpll_d5_d2"
};
static const char * const mdp_parents[] = {
"clk26m",
"mainpll_d5_d2",
"mmpll_d6_d2",
"mainpll_d4_d2",
"mmpll_d4_d2",
"mainpll_d6",
"univpll_d6",
"mainpll_d4",
"tvdpll_ck",
"univpll_d4",
"mmpll_d5_d2"
};
static const char * const img_parents[] = {
"clk26m",
"univpll_d4",
"tvdpll_ck",
"mainpll_d4",
"univpll_d5",
"mmpll_d6",
"univpll_d6",
"mainpll_d6",
"mmpll_d4_d2",
"mainpll_d4_d2",
"mmpll_d6_d2",
"mmpll_d5_d2"
};
static const char * const ipe_parents[] = {
"clk26m",
"mainpll_d4",
"mmpll_d6",
"univpll_d6",
"mainpll_d6",
"univpll_d4_d2",
"mainpll_d4_d2",
"mmpll_d6_d2",
"mmpll_d5_d2"
};
static const char * const dpe_parents[] = {
"clk26m",
"mainpll_d4",
"mmpll_d6",
"univpll_d6",
"mainpll_d6",
"univpll_d4_d2",
"univpll_d5_d2",
"mmpll_d6_d2"
};
static const char * const cam_parents[] = {
"clk26m",
"mainpll_d4",
"mmpll_d6",
"univpll_d4",
"univpll_d5",
"univpll_d6",
"mmpll_d7",
"univpll_d4_d2",
"mainpll_d4_d2",
"univpll_d6_d2"
};
static const char * const ccu_parents[] = {
"clk26m",
"mainpll_d4",
"mmpll_d6",
"mainpll_d6",
"mmpll_d7",
"univpll_d4_d2",
"mmpll_d6_d2",
"mmpll_d5_d2",
"univpll_d5",
"univpll_d6_d2"
};
static const char * const dsp7_parents[] = {
"clk26m",
"mainpll_d4_d2",
"mainpll_d6",
"mmpll_d6",
"univpll_d5",
"mmpll_d5",
"univpll_d4",
"mmpll_d4"
};
static const char * const mfg_ref_parents[] = {
"clk26m",
"clk26m",
"univpll_d6",
"mainpll_d5_d2"
};
static const char * const mfg_pll_parents[] = {
"mfg_ref_sel",
"mfgpll"
};
static const char * const camtg_parents[] = {
"clk26m",
"univpll_192m_d8",
"univpll_d6_d8",
"univpll_192m_d4",
"univpll_d6_d16",
"csw_f26m_d2",
"univpll_192m_d16",
"univpll_192m_d32"
};
static const char * const uart_parents[] = {
"clk26m",
"univpll_d6_d8"
};
static const char * const spi_parents[] = {
"clk26m",
"mainpll_d5_d4",
"mainpll_d6_d4",
"msdcpll_d4"
};
static const char * const msdc50_0_h_parents[] = {
"clk26m",
"mainpll_d4_d2",
"mainpll_d6_d2"
};
static const char * const msdc50_0_parents[] = {
"clk26m",
"msdcpll_ck",
"msdcpll_d2",
"univpll_d4_d4",
"mainpll_d6_d2",
"univpll_d4_d2"
};
static const char * const msdc30_parents[] = {
"clk26m",
"univpll_d6_d2",
"mainpll_d6_d2",
"mainpll_d7_d2",
"msdcpll_d2"
};
static const char * const audio_parents[] = {
"clk26m",
"mainpll_d5_d8",
"mainpll_d7_d8",
"mainpll_d4_d16"
};
static const char * const aud_intbus_parents[] = {
"clk26m",
"mainpll_d4_d4",
"mainpll_d7_d4"
};
static const char * const pwrap_ulposc_parents[] = {
"osc_d10",
"clk26m",
"osc_d4",
"osc_d8",
"osc_d16"
};
static const char * const atb_parents[] = {
"clk26m",
"mainpll_d4_d2",
"mainpll_d5_d2"
};
static const char * const dpi_parents[] = {
"clk26m",
"tvdpll_d2",
"tvdpll_d4",
"tvdpll_d8",
"tvdpll_d16"
};
static const char * const scam_parents[] = {
"clk26m",
"mainpll_d5_d4"
};
static const char * const disp_pwm_parents[] = {
"clk26m",
"univpll_d6_d4",
"osc_d2",
"osc_d4",
"osc_d16"
};
static const char * const usb_top_parents[] = {
"clk26m",
"univpll_d5_d4",
"univpll_d6_d4",
"univpll_d5_d2"
};
static const char * const ssusb_xhci_parents[] = {
"clk26m",
"univpll_d5_d4",
"univpll_d6_d4",
"univpll_d5_d2"
};
static const char * const i2c_parents[] = {
"clk26m",
"mainpll_d4_d8",
"univpll_d5_d4"
};
static const char * const seninf_parents[] = {
"clk26m",
"univpll_d4_d4",
"univpll_d6_d2",
"univpll_d4_d2",
"univpll_d7",
"univpll_d6",
"mmpll_d6",
"univpll_d5"
};
static const char * const tl_parents[] = {
"clk26m",
"univpll_192m_d2",
"mainpll_d6_d4"
};
static const char * const dxcc_parents[] = {
"clk26m",
"mainpll_d4_d2",
"mainpll_d4_d4",
"mainpll_d4_d8"
};
static const char * const aud_engen1_parents[] = {
"clk26m",
"apll1_d2",
"apll1_d4",
"apll1_d8"
};
static const char * const aud_engen2_parents[] = {
"clk26m",
"apll2_d2",
"apll2_d4",
"apll2_d8"
};
static const char * const aes_ufsfde_parents[] = {
"clk26m",
"mainpll_d4",
"mainpll_d4_d2",
"mainpll_d6",
"mainpll_d4_d4",
"univpll_d4_d2",
"univpll_d6"
};
static const char * const ufs_parents[] = {
"clk26m",
"mainpll_d4_d4",
"mainpll_d4_d8",
"univpll_d4_d4",
"mainpll_d6_d2",
"mainpll_d5_d2",
"msdcpll_d2"
};
static const char * const aud_1_parents[] = {
"clk26m",
"apll1_ck"
};
static const char * const aud_2_parents[] = {
"clk26m",
"apll2_ck"
};
static const char * const adsp_parents[] = {
"clk26m",
"mainpll_d6",
"mainpll_d5_d2",
"univpll_d4_d4",
"univpll_d4",
"univpll_d6",
"ulposc",
"adsppll_ck"
};
static const char * const dpmaif_main_parents[] = {
"clk26m",
"univpll_d4_d4",
"mainpll_d6",
"mainpll_d4_d2",
"univpll_d4_d2"
};
static const char * const venc_parents[] = {
"clk26m",
"mmpll_d7",
"mainpll_d6",
"univpll_d4_d2",
"mainpll_d4_d2",
"univpll_d6",
"mmpll_d6",
"mainpll_d5_d2",
"mainpll_d6_d2",
"mmpll_d9",
"univpll_d4_d4",
"mainpll_d4",
"univpll_d4",
"univpll_d5",
"univpll_d5_d2",
"mainpll_d5"
};
static const char * const vdec_parents[] = {
"clk26m",
"univpll_192m_d2",
"univpll_d5_d4",
"mainpll_d5",
"mainpll_d5_d2",
"mmpll_d6_d2",
"univpll_d5_d2",
"mainpll_d4_d2",
"univpll_d4_d2",
"univpll_d7",
"mmpll_d7",
"mmpll_d6",
"univpll_d5",
"mainpll_d4",
"univpll_d4",
"univpll_d6"
};
static const char * const camtm_parents[] = {
"clk26m",
"univpll_d7",
"univpll_d6_d2",
"univpll_d4_d2"
};
static const char * const pwm_parents[] = {
"clk26m",
"univpll_d4_d8"
};
static const char * const audio_h_parents[] = {
"clk26m",
"univpll_d7",
"apll1_ck",
"apll2_ck"
};
static const char * const spmi_mst_parents[] = {
"clk26m",
"csw_f26m_d2",
"osc_d8",
"osc_d10",
"osc_d16",
"osc_d20",
"clk32k"
};
static const char * const aes_msdcfde_parents[] = {
"clk26m",
"mainpll_d4_d2",
"mainpll_d6",
"mainpll_d4_d4",
"univpll_d4_d2",
"univpll_d6"
};
static const char * const sflash_parents[] = {
"clk26m",
"mainpll_d7_d8",
"univpll_d6_d8",
"univpll_d5_d8"
};
static const char * const apll_i2s_m_parents[] = {
"aud_1_sel",
"aud_2_sel"
};
/*
* CRITICAL CLOCK:
* axi_sel is the main bus clock of whole SOC.
* spm_sel is the clock of the always-on co-processor.
* bus_aximem_sel is clock of the bus that access emi.
*/
static const struct mtk_mux top_mtk_muxes[] = {
/* CLK_CFG_0 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel",
axi_parents, 0x010, 0x014, 0x018, 0, 3, 7, 0x004, 0,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel",
spm_parents, 0x010, 0x014, 0x018, 8, 2, 15, 0x004, 1,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel",
scp_parents, 0x010, 0x014, 0x018, 16, 3, 23, 0x004, 2),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM_SEL, "bus_aximem_sel",
bus_aximem_parents, 0x010, 0x014, 0x018, 24, 3, 31, 0x004, 3,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
/* CLK_CFG_1 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_SEL, "disp_sel",
disp_parents, 0x020, 0x024, 0x028, 0, 4, 7, 0x004, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP_SEL, "mdp_sel",
mdp_parents, 0x020, 0x024, 0x028, 8, 4, 15, 0x004, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, "img1_sel",
img_parents, 0x020, 0x024, 0x028, 16, 4, 23, 0x004, 6),
MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG2_SEL, "img2_sel",
img_parents, 0x020, 0x024, 0x028, 24, 4, 31, 0x004, 7),
/* CLK_CFG_2 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, "ipe_sel",
ipe_parents, 0x030, 0x034, 0x038, 0, 4, 7, 0x004, 8),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE_SEL, "dpe_sel",
dpe_parents, 0x030, 0x034, 0x038, 8, 3, 15, 0x004, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, "cam_sel",
cam_parents, 0x030, 0x034, 0x038, 16, 4, 23, 0x004, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel",
ccu_parents, 0x030, 0x034, 0x038, 24, 4, 31, 0x004, 11),
/* CLK_CFG_4 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SEL, "dsp7_sel",
dsp7_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x004, 16),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, "mfg_ref_sel",
mfg_ref_parents, 0x050, 0x054, 0x058, 16, 2, 23, 0x004, 18),
MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel",
mfg_pll_parents, 0x050, 0x054, 0x058, 18, 1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
camtg_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x004, 19),
/* CLK_CFG_5 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel",
camtg_parents, 0x060, 0x064, 0x068, 0, 3, 7, 0x004, 20),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel",
camtg_parents, 0x060, 0x064, 0x068, 8, 3, 15, 0x004, 21),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4_SEL, "camtg4_sel",
camtg_parents, 0x060, 0x064, 0x068, 16, 3, 23, 0x004, 22),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5_SEL, "camtg5_sel",
camtg_parents, 0x060, 0x064, 0x068, 24, 3, 31, 0x004, 23),
/* CLK_CFG_6 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG6_SEL, "camtg6_sel",
camtg_parents, 0x070, 0x074, 0x078, 0, 3, 7, 0x004, 24),
MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel",
uart_parents, 0x070, 0x074, 0x078, 8, 1, 15, 0x004, 25),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel",
spi_parents, 0x070, 0x074, 0x078, 16, 2, 23, 0x004, 26),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel",
msdc50_0_h_parents, 0x070, 0x074, 0x078, 24, 2,
31, 0x004, 27, 0),
/* CLK_CFG_7 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
msdc50_0_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x004, 28, 0),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
msdc30_parents, 0x080, 0x084, 0x088, 8, 3, 15, 0x004, 29, 0),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
msdc30_parents, 0x080, 0x084, 0x088, 16, 3, 23, 0x004, 30, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel",
audio_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x008, 0),
/* CLK_CFG_8 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
aud_intbus_parents, 0x090, 0x094, 0x098, 0, 2, 7, 0x008, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC_SEL, "pwrap_ulposc_sel",
pwrap_ulposc_parents, 0x090, 0x094, 0x098, 8, 3, 15, 0x008, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel",
atb_parents, 0x090, 0x094, 0x098, 16, 2, 23, 0x008, 3),
/* CLK_CFG_9 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI_SEL, "dpi_sel",
dpi_parents, 0x0a0, 0x0a4, 0x0a8, 0, 3, 7, 0x008, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM_SEL, "scam_sel",
scam_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x008, 6),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
disp_pwm_parents, 0x0a0, 0x0a4, 0x0a8, 16, 3, 23, 0x008, 7),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL, "usb_top_sel",
usb_top_parents, 0x0a0, 0x0a4, 0x0a8, 24, 2, 31, 0x008, 8),
/* CLK_CFG_10 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel",
ssusb_xhci_parents, 0x0b0, 0x0b4, 0x0b8, 0, 2, 7, 0x008, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel",
i2c_parents, 0x0b0, 0x0b4, 0x0b8, 8, 2, 15, 0x008, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel",
seninf_parents, 0x0b0, 0x0b4, 0x0b8, 16, 3, 23, 0x008, 11),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, "seninf1_sel",
seninf_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 0x008, 12),
/* CLK_CFG_11 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2_SEL, "seninf2_sel",
seninf_parents, 0x0c0, 0x0c4, 0x0c8, 0, 3, 7, 0x008, 13),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3_SEL, "seninf3_sel",
seninf_parents, 0x0c0, 0x0c4, 0x0c8, 8, 3, 15, 0x008, 14),
MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_SEL, "tl_sel",
tl_parents, 0x0c0, 0x0c4, 0x0c8, 16, 2, 23, 0x008, 15),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel",
dxcc_parents, 0x0c0, 0x0c4, 0x0c8, 24, 2, 31, 0x008, 16),
/* CLK_CFG_12 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
aud_engen1_parents, 0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x008, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel",
aud_engen2_parents, 0x0d0, 0x0d4, 0x0d8, 8, 2, 15, 0x008, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL, "aes_ufsfde_sel",
aes_ufsfde_parents, 0x0d0, 0x0d4, 0x0d8, 16, 3, 23, 0x008, 19),
MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_SEL, "ufs_sel",
ufs_parents, 0x0d0, 0x0d4, 0x0d8, 24, 3, 31, 0x008, 20),
/* CLK_CFG_13 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel",
aud_1_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7, 0x008, 21),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel",
aud_2_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15, 0x008, 22),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_SEL, "adsp_sel",
adsp_parents, 0x0e0, 0x0e4, 0x0e8, 16, 3, 23, 0x008, 23),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN_SEL, "dpmaif_main_sel",
dpmaif_main_parents, 0x0e0, 0x0e4, 0x0e8, 24, 3, 31, 0x008, 24),
/* CLK_CFG_14 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel",
venc_parents, 0x0f0, 0x0f4, 0x0f8, 0, 4, 7, 0x008, 25),
MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel",
vdec_parents, 0x0f0, 0x0f4, 0x0f8, 8, 4, 15, 0x008, 26),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel",
camtm_parents, 0x0f0, 0x0f4, 0x0f8, 16, 2, 23, 0x008, 27),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel",
pwm_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1, 31, 0x008, 28),
/* CLK_CFG_15 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL, "audio_h_sel",
audio_h_parents, 0x100, 0x104, 0x108, 0, 2, 7, 0x008, 29),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_MST_SEL, "spmi_mst_sel",
spmi_mst_parents, 0x100, 0x104, 0x108, 8, 3, 15, 0x008, 30),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, "aes_msdcfde_sel",
aes_msdcfde_parents, 0x100, 0x104, 0x108, 24, 3, 31, 0x00c, 1),
/* CLK_CFG_16 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, "sflash_sel",
sflash_parents, 0x110, 0x114, 0x118, 8, 2, 15, 0x00c, 3),
};
static struct mtk_composite top_muxes[] = {
/* CLK_AUDDIV_0 */
MUX(CLK_TOP_APLL_I2S0_M_SEL, "apll_i2s0_m_sel", apll_i2s_m_parents, 0x320, 16, 1),
MUX(CLK_TOP_APLL_I2S1_M_SEL, "apll_i2s1_m_sel", apll_i2s_m_parents, 0x320, 17, 1),
MUX(CLK_TOP_APLL_I2S2_M_SEL, "apll_i2s2_m_sel", apll_i2s_m_parents, 0x320, 18, 1),
MUX(CLK_TOP_APLL_I2S3_M_SEL, "apll_i2s3_m_sel", apll_i2s_m_parents, 0x320, 19, 1),
MUX(CLK_TOP_APLL_I2S4_M_SEL, "apll_i2s4_m_sel", apll_i2s_m_parents, 0x320, 20, 1),
MUX(CLK_TOP_APLL_I2S5_M_SEL, "apll_i2s5_m_sel", apll_i2s_m_parents, 0x320, 21, 1),
MUX(CLK_TOP_APLL_I2S6_M_SEL, "apll_i2s6_m_sel", apll_i2s_m_parents, 0x320, 22, 1),
MUX(CLK_TOP_APLL_I2S7_M_SEL, "apll_i2s7_m_sel", apll_i2s_m_parents, 0x320, 23, 1),
MUX(CLK_TOP_APLL_I2S8_M_SEL, "apll_i2s8_m_sel", apll_i2s_m_parents, 0x320, 24, 1),
MUX(CLK_TOP_APLL_I2S9_M_SEL, "apll_i2s9_m_sel", apll_i2s_m_parents, 0x320, 25, 1),
/* APLL_DIV */
DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_m_sel", 0x320, 0, 0x328, 8, 0),
DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_m_sel", 0x320, 1, 0x328, 8, 8),
DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_m_sel", 0x320, 2, 0x328, 8, 16),
DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_m_sel", 0x320, 3, 0x328, 8, 24),
DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_m_sel", 0x320, 4, 0x334, 8, 0),
DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 0x320, 5, 0x334, 8, 8),
DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll_i2s5_m_sel", 0x320, 6, 0x334, 8, 16),
DIV_GATE(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll_i2s6_m_sel", 0x320, 7, 0x334, 8, 24),
DIV_GATE(CLK_TOP_APLL12_DIV7, "apll12_div7", "apll_i2s7_m_sel", 0x320, 8, 0x338, 8, 0),
DIV_GATE(CLK_TOP_APLL12_DIV8, "apll12_div8", "apll_i2s8_m_sel", 0x320, 9, 0x338, 8, 8),
DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "apll_i2s9_m_sel", 0x320, 10, 0x338, 8, 16),
};
static const struct mtk_gate_regs infra0_cg_regs = {
.set_ofs = 0x80,
.clr_ofs = 0x84,
.sta_ofs = 0x90,
};
static const struct mtk_gate_regs infra1_cg_regs = {
.set_ofs = 0x88,
.clr_ofs = 0x8c,
.sta_ofs = 0x94,
};
static const struct mtk_gate_regs infra2_cg_regs = {
.set_ofs = 0xa4,
.clr_ofs = 0xa8,
.sta_ofs = 0xac,
};
static const struct mtk_gate_regs infra3_cg_regs = {
.set_ofs = 0xc0,
.clr_ofs = 0xc4,
.sta_ofs = 0xc8,
};
static const struct mtk_gate_regs infra4_cg_regs = {
.set_ofs = 0xd0,
.clr_ofs = 0xd4,
.sta_ofs = 0xd8,
};
static const struct mtk_gate_regs infra5_cg_regs = {
.set_ofs = 0xe0,
.clr_ofs = 0xe4,
.sta_ofs = 0xe8,
};
#define GATE_INFRA0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flag)
#define GATE_INFRA1(_id, _name, _parent, _shift) \
GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flag)
#define GATE_INFRA3(_id, _name, _parent, _shift) \
GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA4(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra4_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra5_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flag)
#define GATE_INFRA5(_id, _name, _parent, _shift) \
GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, 0)
/*
* CRITICAL CLOCK:
* infra_133m and infra_66m are main peripheral bus clocks of SOC.
* infra_device_apc and infra_device_apc_sync are for device access permission control module.
*/
static const struct mtk_gate infra_clks[] = {
/* INFRA0 */
GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "pwrap_ulposc_sel", 0),
GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pwrap_ulposc_sel", 1),
GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pwrap_ulposc_sel", 2),
GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pwrap_ulposc_sel", 3),
GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scpsys", "scp_sel", 4),
GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5),
GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 8),
GATE_INFRA0(CLK_INFRA_GCE2, "infra_gce2", "axi_sel", 9),
GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", "i2c_sel", 11),
GATE_INFRA0(CLK_INFRA_AP_DMA_PSEUDO, "infra_ap_dma_pseudo", "axi_sel", 12),
GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", "i2c_sel", 13),
GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", "i2c_sel", 14),
GATE_INFRA0(CLK_INFRA_PWM_H, "infra_pwm_h", "axi_sel", 15),
GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", "pwm_sel", 16),
GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", "pwm_sel", 17),
GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", "pwm_sel", 18),
GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", "pwm_sel", 19),
GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21),
GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", "axi_sel", 27),
GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cq_dma_fpc", "axi_sel", 28),
GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31),
/* INFRA1 */
GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", "spi_sel", 1),
GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_h_sel", 2),
GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc50_0_h_sel", 4),
GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc50_0_h_sel", 5),
GATE_INFRA1(CLK_INFRA_MSDC0_SRC, "infra_msdc0_src", "msdc50_0_sel", 6),
GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8),
GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9),
GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10),
GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11),
GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", "axi_sel", 12),
GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", "axi_sel", 13),
GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", "clk26m", 14),
GATE_INFRA1(CLK_INFRA_PCIE_TL_26M, "infra_pcie_tl_26m", "axi_sel", 15),
GATE_INFRA1(CLK_INFRA_MSDC1_SRC, "infra_msdc1_src", "msdc30_1_sel", 16),
GATE_INFRA1(CLK_INFRA_MSDC2_SRC, "infra_msdc2_src", "msdc30_2_sel", 17),
GATE_INFRA1(CLK_INFRA_PCIE_TL_96M, "infra_pcie_tl_96m", "tl_sel", 18),
GATE_INFRA1(CLK_INFRA_PCIE_PL_P_250M, "infra_pcie_pl_p_250m", "axi_sel", 19),
GATE_INFRA1_FLAGS(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20, CLK_IS_CRITICAL),
GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", "axi_sel", 24),
GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", "dxcc_sel", 27),
GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", "dxcc_sel", 28),
GATE_INFRA1(CLK_INFRA_DBG_TRACE, "infra_dbg_trace", "axi_sel", 29),
GATE_INFRA1(CLK_INFRA_DEVMPU_B, "infra_devmpu_b", "axi_sel", 30),
GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31),
/* INFRA2 */
GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", "clk26m", 0),
GATE_INFRA2(CLK_INFRA_SSUSB, "infra_ssusb", "usb_top_sel", 1),
GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "axi_sel", 2),
GATE_INFRA2(CLK_INFRA_CLDMA_B, "infra_cldma_b", "axi_sel", 3),
GATE_INFRA2(CLK_INFRA_AUDIO_26M_B, "infra_audio_26m_b", "clk26m", 4),
GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share", "clk26m", 5),
GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 6),
GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", "i2c_sel", 7),
GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 9),
GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 10),
GATE_INFRA2(CLK_INFRA_UNIPRO_SYS, "infra_unipro_sys", "ufs_sel", 11),
GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", "clk26m", 12),
GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_B, "infra_ufs_mp_sap_b", "clk26m", 13),
GATE_INFRA2(CLK_INFRA_MD32_B, "infra_md32_b", "axi_sel", 14),
GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16),
GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", "i2c_sel", 18),
GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", "i2c_sel", 19),
GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", "i2c_sel", 20),
GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", "i2c_sel", 21),
GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", "i2c_sel", 22),
GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", "i2c_sel", 23),
GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "i2c_sel", 24),
GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 25),
GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 26),
GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cq_dma", "axi_sel", 27),
GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", "ufs_sel", 28),
GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", "aes_ufsfde_sel", 29),
GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", "ufs_sel", 30),
GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci", "ssusb_xhci_sel", 31),
/* INFRA3 */
GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", "msdc50_0_sel", 0),
GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", "msdc50_0_sel", 1),
GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", "msdc50_0_sel", 2),
GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", "axi_sel", 5),
GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", "i2c_sel", 6),
GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", "msdc50_0_sel", 7),
GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", "msdc50_0_sel", 8),
GATE_INFRA3(CLK_INFRA_CCIF5_AP, "infra_ccif5_ap", "axi_sel", 9),
GATE_INFRA3(CLK_INFRA_CCIF5_MD, "infra_ccif5_md", "axi_sel", 10),
GATE_INFRA3(CLK_INFRA_PCIE_TOP_H_133M, "infra_pcie_top_h_133m", "axi_sel", 11),
GATE_INFRA3(CLK_INFRA_FLASHIF_TOP_H_133M, "infra_flashif_top_h_133m", "axi_sel", 14),
GATE_INFRA3(CLK_INFRA_PCIE_PERI_26M, "infra_pcie_peri_26m", "axi_sel", 15),
GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", "axi_sel", 16),
GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", "axi_sel", 17),
GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", "axi_sel", 18),
GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", "axi_sel", 19),
GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", "clk26m", 20),
GATE_INFRA3(CLK_INFRA_AES, "infra_aes", "axi_sel", 21),
GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", "i2c_sel", 22),
GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", "i2c_sel", 23),
GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", "msdc50_0_sel", 24),
GATE_INFRA3_FLAGS(CLK_INFRA_DEVICE_APC_SYNC, "infra_device_apc_sync", "axi_sel", 25,
CLK_IS_CRITICAL),
GATE_INFRA3(CLK_INFRA_DPMAIF_MAIN, "infra_dpmaif_main", "dpmaif_main_sel", 26),
GATE_INFRA3(CLK_INFRA_PCIE_TL_32K, "infra_pcie_tl_32k", "axi_sel", 27),
GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap", "axi_sel", 28),
GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md", "axi_sel", 29),
GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6", "spi_sel", 30),
GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7", "spi_sel", 31),
/* INFRA4 */
GATE_INFRA4(CLK_INFRA_AP_DMA, "infra_ap_dma", "infra_ap_dma_pseudo", 31),
/* INFRA5 */
GATE_INFRA5_FLAGS(CLK_INFRA_133M, "infra_133m", "axi_sel", 0, CLK_IS_CRITICAL),
GATE_INFRA5_FLAGS(CLK_INFRA_66M, "infra_66m", "axi_sel", 1, CLK_IS_CRITICAL),
GATE_INFRA5(CLK_INFRA_66M_PERI_BUS, "infra_66m_peri_bus", "axi_sel", 2),
GATE_INFRA5(CLK_INFRA_FREE_DCM_133M, "infra_free_dcm_133m", "axi_sel", 3),
GATE_INFRA5(CLK_INFRA_FREE_DCM_66M, "infra_free_dcm_66m", "axi_sel", 4),
GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_133M, "infra_peri_bus_dcm_133m", "axi_sel", 5),
GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_66M, "infra_peri_bus_dcm_66m", "axi_sel", 6),
GATE_INFRA5(CLK_INFRA_FLASHIF_PERI_26M, "infra_flashif_peri_26m", "axi_sel", 30),
GATE_INFRA5(CLK_INFRA_FLASHIF_SFLASH, "infra_flashif_fsflash", "axi_sel", 31),
};
static const struct mtk_gate_regs peri_cg_regs = {
.set_ofs = 0x20c,
.clr_ofs = 0x20c,
.sta_ofs = 0x20c,
};
#define GATE_PERI(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate peri_clks[] = {
GATE_PERI(CLK_PERI_PERIAXI, "peri_periaxi", "axi_sel", 31),
};
static const struct mtk_gate_regs top_cg_regs = {
.set_ofs = 0x150,
.clr_ofs = 0x150,
.sta_ofs = 0x150,
};
#define GATE_TOP(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate top_clks[] = {
GATE_TOP(CLK_TOP_SSUSB_TOP_REF, "ssusb_top_ref", "clk26m", 24),
GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25),
};
static u16 infra_ao_rst_ofs[] = {
INFRA_RST0_SET_OFFSET,
INFRA_RST1_SET_OFFSET,
INFRA_RST2_SET_OFFSET,
INFRA_RST3_SET_OFFSET,
INFRA_RST4_SET_OFFSET,
};
static u16 infra_ao_idx_map[] = {
[MT8192_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
[MT8192_INFRA_RST2_PEXTP_PHY_SWRST] = 2 * RST_NR_PER_BANK + 15,
[MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
[MT8192_INFRA_RST4_PCIE_TOP_SWRST] = 4 * RST_NR_PER_BANK + 1,
[MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 12,
};
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SET_CLR,
.rst_bank_ofs = infra_ao_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
.rst_idx_map = infra_ao_idx_map,
.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
};
/* Register mux notifier for MFG mux */
static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
{
struct mtk_mux_nb *mfg_mux_nb;
int i;
mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
if (!mfg_mux_nb)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(top_mtk_muxes); i++)
if (top_mtk_muxes[i].id == CLK_TOP_MFG_PLL_SEL)
break;
if (i == ARRAY_SIZE(top_mtk_muxes))
return -EINVAL;
mfg_mux_nb->ops = top_mtk_muxes[i].ops;
mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */
return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
}
static const struct mtk_clk_desc infra_desc = {
.clks = infra_clks,
.num_clks = ARRAY_SIZE(infra_clks),
.rst_desc = &clk_rst_desc,
};
static const struct mtk_clk_desc peri_desc = {
.clks = peri_clks,
.num_clks = ARRAY_SIZE(peri_clks),
};
static const struct mtk_clk_desc topck_desc = {
.fixed_clks = top_fixed_clks,
.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
.factor_clks = top_divs,
.num_factor_clks = ARRAY_SIZE(top_divs),
.mux_clks = top_mtk_muxes,
.num_mux_clks = ARRAY_SIZE(top_mtk_muxes),
.composite_clks = top_muxes,
.num_composite_clks = ARRAY_SIZE(top_muxes),
.clks = top_clks,
.num_clks = ARRAY_SIZE(top_clks),
.clk_lock = &mt8192_clk_lock,
.clk_notifier_func = clk_mt8192_reg_mfg_mux_notifier,
.mfg_clk_idx = CLK_TOP_MFG_PLL_SEL,
};
static const struct of_device_id of_match_clk_mt8192[] = {
{ .compatible = "mediatek,mt8192-infracfg", .data = &infra_desc },
{ .compatible = "mediatek,mt8192-pericfg", .data = &peri_desc },
{ .compatible = "mediatek,mt8192-topckgen", .data = &topck_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8192);
static struct platform_driver clk_mt8192_drv = {
.driver = {
.name = "clk-mt8192",
.of_match_table = of_match_clk_mt8192,
},
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt8192_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8192.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Garmin Chang <[email protected]>
*/
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs mfgcfg_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_MFG(_id, _name, _parent, _shift) \
GATE_MTK_FLAGS(_id, _name, _parent, &mfgcfg_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT)
static const struct mtk_gate mfgcfg_clks[] = {
GATE_MFG(CLK_MFGCFG_BG3D, "mfgcfg_bg3d", "mfg_ck_fast_ref", 0),
};
static const struct mtk_clk_desc mfgcfg_desc = {
.clks = mfgcfg_clks,
.num_clks = ARRAY_SIZE(mfgcfg_clks),
};
static const struct of_device_id of_match_clk_mt8188_mfgcfg[] = {
{ .compatible = "mediatek,mt8188-mfgcfg", .data = &mfgcfg_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_mfgcfg);
static struct platform_driver clk_mt8188_mfgcfg_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8188-mfgcfg",
.of_match_table = of_match_clk_mt8188_mfgcfg,
},
};
module_platform_driver(clk_mt8188_mfgcfg_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8188-mfg.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 MediaTek Inc.
* Author: Sam Shih <[email protected]>
* Author: Wenzhen Yu <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include "clk-mux.h"
#include <dt-bindings/clock/mt7986-clk.h>
#include <linux/clk.h>
static DEFINE_SPINLOCK(mt7986_clk_lock);
static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
FIXED_CLK(CLK_TOP_JTAG, "top_jtag", "clkxtal", 50000000),
};
static const struct mtk_fixed_factor top_divs[] = {
/* XTAL */
FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
/* MPLL */
FACTOR(CLK_TOP_MPLL_D2, "top_mpll_d2", "mpll", 1, 2),
FACTOR(CLK_TOP_MPLL_D4, "top_mpll_d4", "mpll", 1, 4),
FACTOR(CLK_TOP_MPLL_D8, "top_mpll_d8", "mpll", 1, 8),
FACTOR(CLK_TOP_MPLL_D8_D2, "top_mpll_d8_d2", "mpll", 1, 16),
FACTOR(CLK_TOP_MPLL_D3_D2, "top_mpll_d3_d2", "mpll", 1, 6),
/* MMPLL */
FACTOR(CLK_TOP_MMPLL_D2, "top_mmpll_d2", "mmpll", 1, 2),
FACTOR(CLK_TOP_MMPLL_D4, "top_mmpll_d4", "mmpll", 1, 4),
FACTOR(CLK_TOP_MMPLL_D8, "top_mmpll_d8", "mmpll", 1, 8),
FACTOR(CLK_TOP_MMPLL_D8_D2, "top_mmpll_d8_d2", "mmpll", 1, 16),
FACTOR(CLK_TOP_MMPLL_D3_D8, "top_mmpll_d3_d8", "mmpll", 1, 24),
FACTOR(CLK_TOP_MMPLL_U2PHY, "top_mmpll_u2phy", "mmpll", 1, 30),
/* APLL2 */
FACTOR(CLK_TOP_APLL2_D4, "top_apll2_d4", "apll2", 1, 4),
/* NET1PLL */
FACTOR(CLK_TOP_NET1PLL_D4, "top_net1pll_d4", "net1pll", 1, 4),
FACTOR(CLK_TOP_NET1PLL_D5, "top_net1pll_d5", "net1pll", 1, 5),
FACTOR(CLK_TOP_NET1PLL_D5_D2, "top_net1pll_d5_d2", "net1pll", 1, 10),
FACTOR(CLK_TOP_NET1PLL_D5_D4, "top_net1pll_d5_d4", "net1pll", 1, 20),
FACTOR(CLK_TOP_NET1PLL_D8_D2, "top_net1pll_d8_d2", "net1pll", 1, 16),
FACTOR(CLK_TOP_NET1PLL_D8_D4, "top_net1pll_d8_d4", "net1pll", 1, 32),
/* NET2PLL */
FACTOR(CLK_TOP_NET2PLL_D4, "top_net2pll_d4", "net2pll", 1, 4),
FACTOR(CLK_TOP_NET2PLL_D4_D2, "top_net2pll_d4_d2", "net2pll", 1, 8),
FACTOR(CLK_TOP_NET2PLL_D3_D2, "top_net2pll_d3_d2", "net2pll", 1, 2),
/* WEDMCUPLL */
FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "top_wedmcupll_d5_d2", "wedmcupll", 1,
10),
};
static const char *const nfi1x_parents[] __initconst = { "top_xtal",
"top_mmpll_d8",
"top_net1pll_d8_d2",
"top_net2pll_d3_d2",
"top_mpll_d4",
"top_mmpll_d8_d2",
"top_wedmcupll_d5_d2",
"top_mpll_d8" };
static const char *const spinfi_parents[] __initconst = {
"top_xtal_d2", "top_xtal", "top_net1pll_d5_d4",
"top_mpll_d4", "top_mmpll_d8_d2", "top_wedmcupll_d5_d2",
"top_mmpll_d3_d8", "top_mpll_d8"
};
static const char *const spi_parents[] __initconst = {
"top_xtal", "top_mpll_d2", "top_mmpll_d8",
"top_net1pll_d8_d2", "top_net2pll_d3_d2", "top_net1pll_d5_d4",
"top_mpll_d4", "top_wedmcupll_d5_d2"
};
static const char *const uart_parents[] __initconst = { "top_xtal",
"top_mpll_d8",
"top_mpll_d8_d2" };
static const char *const pwm_parents[] __initconst = {
"top_xtal", "top_net1pll_d8_d2", "top_net1pll_d5_d4", "top_mpll_d4"
};
static const char *const i2c_parents[] __initconst = {
"top_xtal", "top_net1pll_d5_d4", "top_mpll_d4", "top_net1pll_d8_d4"
};
static const char *const pextp_tl_ck_parents[] __initconst = {
"top_xtal", "top_net1pll_d5_d4", "top_net2pll_d4_d2", "top_rtc_32k"
};
static const char *const emmc_250m_parents[] __initconst = {
"top_xtal", "top_net1pll_d5_d2"
};
static const char *const emmc_416m_parents[] __initconst = { "top_xtal",
"mpll" };
static const char *const f_26m_adc_parents[] __initconst = { "top_xtal",
"top_mpll_d8_d2" };
static const char *const dramc_md32_parents[] __initconst = { "top_xtal",
"top_mpll_d2" };
static const char *const sysaxi_parents[] __initconst = { "top_xtal",
"top_net1pll_d8_d2",
"top_net2pll_d4" };
static const char *const sysapb_parents[] __initconst = { "top_xtal",
"top_mpll_d3_d2",
"top_net2pll_d4_d2" };
static const char *const arm_db_main_parents[] __initconst = {
"top_xtal", "top_net2pll_d3_d2"
};
static const char *const arm_db_jtsel_parents[] __initconst = { "top_jtag",
"top_xtal" };
static const char *const netsys_parents[] __initconst = { "top_xtal",
"top_mmpll_d4" };
static const char *const netsys_500m_parents[] __initconst = {
"top_xtal", "top_net1pll_d5"
};
static const char *const netsys_mcu_parents[] __initconst = {
"top_xtal", "wedmcupll", "top_mmpll_d2", "top_net1pll_d4",
"top_net1pll_d5"
};
static const char *const netsys_2x_parents[] __initconst = {
"top_xtal", "net2pll", "wedmcupll", "top_mmpll_d2"
};
static const char *const sgm_325m_parents[] __initconst = { "top_xtal",
"sgmpll" };
static const char *const sgm_reg_parents[] __initconst = {
"top_xtal", "top_net1pll_d8_d4"
};
static const char *const a1sys_parents[] __initconst = { "top_xtal",
"top_apll2_d4" };
static const char *const conn_mcusys_parents[] __initconst = { "top_xtal",
"top_mmpll_d2" };
static const char *const eip_b_parents[] __initconst = { "top_xtal",
"net2pll" };
static const char *const aud_l_parents[] __initconst = { "top_xtal", "apll2",
"top_mpll_d8_d2" };
static const char *const a_tuner_parents[] __initconst = { "top_xtal",
"top_apll2_d4",
"top_mpll_d8_d2" };
static const char *const u2u3_sys_parents[] __initconst = {
"top_xtal", "top_net1pll_d5_d4"
};
static const char *const da_u2_refsel_parents[] __initconst = {
"top_xtal", "top_mmpll_u2phy"
};
static const struct mtk_mux top_muxes[] = {
/* CLK_CFG_0 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
0x004, 0x008, 16, 3, 23, 0x1C0, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
/* CLK_CFG_1 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
0x014, 0x018, 0, 2, 7, 0x1C0, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
0x014, 0x018, 8, 2, 15, 0x1C0, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
0x014, 0x018, 16, 2, 23, 0x1C0, 6),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2,
31, 0x1C0, 7),
/* CLK_CFG_2 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7,
0x1C0, 8, 0),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel",
emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15,
0x1C0, 9, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,
0x1C0, 10),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
f_26m_adc_parents, 0x020, 0x024, 0x028,
24, 1, 31, 0x1C0, 11,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
/* CLK_CFG_3 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
dramc_md32_parents, 0x030, 0x034, 0x038,
0, 1, 7, 0x1C0, 12,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
sysaxi_parents, 0x030, 0x034, 0x038,
8, 2, 15, 0x1C0, 13,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
sysapb_parents, 0x030, 0x034, 0x038,
16, 2, 23, 0x1C0, 14,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1,
31, 0x1C0, 15),
/* CLK_CFG_4 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel",
arm_db_jtsel_parents, 0x040, 0x044, 0x048, 0, 1, 7,
0x1C0, 16),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1,
23, 0x1C0, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
0x1C0, 19),
/* CLK_CFG_5 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
0x1C0, 20),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
0x1C0, 21),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
sgm_reg_parents, 0x050, 0x054, 0x058,
16, 1, 23, 0x1C0, 22,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23),
/* CLK_CFG_6 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel",
conn_mcusys_parents, 0x060, 0x064, 0x068, 0, 1, 7,
0x1C0, 24),
MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents,
0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel",
f_26m_adc_parents, 0x060, 0x064, 0x068, 16, 1, 23,
0x1C0, 26),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31,
0x1C0, 27),
/* CLK_CFG_7 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
f_26m_adc_parents, 0x070, 0x074, 0x078,
0, 1, 7, 0x1C0, 28,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29),
MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
a_tuner_parents, 0x070, 0x074, 0x078, 16, 2, 23,
0x1C0, 30),
MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents,
0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0),
/* CLK_CFG_8 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
u2u3_sys_parents, 0x080, 0x084, 0x088, 0, 1, 7,
0x1C4, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
u2u3_sys_parents, 0x080, 0x084, 0x088, 8, 1, 15,
0x1C4, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel",
da_u2_refsel_parents, 0x080, 0x084, 0x088, 16, 1,
23, 0x1C4, 3),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel",
da_u2_refsel_parents, 0x080, 0x084, 0x088, 24, 1,
31, 0x1C4, 4),
/* CLK_CFG_9 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
sgm_reg_parents, 0x090, 0x094, 0x098, 0, 1, 7,
0x1C4, 5),
};
static const struct mtk_clk_desc topck_desc = {
.fixed_clks = top_fixed_clks,
.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
.factor_clks = top_divs,
.num_factor_clks = ARRAY_SIZE(top_divs),
.mux_clks = top_muxes,
.num_mux_clks = ARRAY_SIZE(top_muxes),
.clk_lock = &mt7986_clk_lock,
};
static const struct of_device_id of_match_clk_mt7986_topckgen[] = {
{ .compatible = "mediatek,mt7986-topckgen", .data = &topck_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_topckgen);
static struct platform_driver clk_mt7986_topckgen_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7986-topckgen",
.of_match_table = of_match_clk_mt7986_topckgen,
},
};
module_platform_driver(clk_mt7986_topckgen_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt7986-topckgen.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Chen Zhong <[email protected]>
* Sean Wang <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt7622-clk.h>
#define GATE_AUDIO0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
#define GATE_AUDIO1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
#define GATE_AUDIO2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &audio2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
#define GATE_AUDIO3(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &audio3_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate_regs audio0_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x0,
.sta_ofs = 0x0,
};
static const struct mtk_gate_regs audio1_cg_regs = {
.set_ofs = 0x10,
.clr_ofs = 0x10,
.sta_ofs = 0x10,
};
static const struct mtk_gate_regs audio2_cg_regs = {
.set_ofs = 0x14,
.clr_ofs = 0x14,
.sta_ofs = 0x14,
};
static const struct mtk_gate_regs audio3_cg_regs = {
.set_ofs = 0x634,
.clr_ofs = 0x634,
.sta_ofs = 0x634,
};
static const struct mtk_gate audio_clks[] = {
/* AUDIO0 */
GATE_AUDIO0(CLK_AUDIO_AFE, "audio_afe", "rtc", 2),
GATE_AUDIO0(CLK_AUDIO_HDMI, "audio_hdmi", "apll1_ck_sel", 20),
GATE_AUDIO0(CLK_AUDIO_SPDF, "audio_spdf", "apll1_ck_sel", 21),
GATE_AUDIO0(CLK_AUDIO_APLL, "audio_apll", "apll1_ck_sel", 23),
/* AUDIO1 */
GATE_AUDIO1(CLK_AUDIO_I2SIN1, "audio_i2sin1", "a1sys_hp_sel", 0),
GATE_AUDIO1(CLK_AUDIO_I2SIN2, "audio_i2sin2", "a1sys_hp_sel", 1),
GATE_AUDIO1(CLK_AUDIO_I2SIN3, "audio_i2sin3", "a1sys_hp_sel", 2),
GATE_AUDIO1(CLK_AUDIO_I2SIN4, "audio_i2sin4", "a1sys_hp_sel", 3),
GATE_AUDIO1(CLK_AUDIO_I2SO1, "audio_i2so1", "a1sys_hp_sel", 6),
GATE_AUDIO1(CLK_AUDIO_I2SO2, "audio_i2so2", "a1sys_hp_sel", 7),
GATE_AUDIO1(CLK_AUDIO_I2SO3, "audio_i2so3", "a1sys_hp_sel", 8),
GATE_AUDIO1(CLK_AUDIO_I2SO4, "audio_i2so4", "a1sys_hp_sel", 9),
GATE_AUDIO1(CLK_AUDIO_ASRCI1, "audio_asrci1", "asm_h_sel", 12),
GATE_AUDIO1(CLK_AUDIO_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
GATE_AUDIO1(CLK_AUDIO_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
GATE_AUDIO1(CLK_AUDIO_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
GATE_AUDIO1(CLK_AUDIO_INTDIR, "audio_intdir", "intdir_sel", 20),
GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21),
GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22),
GATE_AUDIO1(CLK_AUDIO_AFE_CONN, "audio_afe_conn", "a1sys_hp_sel", 23),
/* AUDIO2 */
GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0),
GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1),
GATE_AUDIO2(CLK_AUDIO_UL3, "audio_ul3", "a1sys_hp_sel", 2),
GATE_AUDIO2(CLK_AUDIO_UL4, "audio_ul4", "a1sys_hp_sel", 3),
GATE_AUDIO2(CLK_AUDIO_UL5, "audio_ul5", "a1sys_hp_sel", 4),
GATE_AUDIO2(CLK_AUDIO_UL6, "audio_ul6", "a1sys_hp_sel", 5),
GATE_AUDIO2(CLK_AUDIO_DL1, "audio_dl1", "a1sys_hp_sel", 6),
GATE_AUDIO2(CLK_AUDIO_DL2, "audio_dl2", "a1sys_hp_sel", 7),
GATE_AUDIO2(CLK_AUDIO_DL3, "audio_dl3", "a1sys_hp_sel", 8),
GATE_AUDIO2(CLK_AUDIO_DL4, "audio_dl4", "a1sys_hp_sel", 9),
GATE_AUDIO2(CLK_AUDIO_DL5, "audio_dl5", "a1sys_hp_sel", 10),
GATE_AUDIO2(CLK_AUDIO_DL6, "audio_dl6", "a1sys_hp_sel", 11),
GATE_AUDIO2(CLK_AUDIO_DLMCH, "audio_dlmch", "a1sys_hp_sel", 12),
GATE_AUDIO2(CLK_AUDIO_ARB1, "audio_arb1", "a1sys_hp_sel", 13),
GATE_AUDIO2(CLK_AUDIO_AWB, "audio_awb", "a1sys_hp_sel", 14),
GATE_AUDIO2(CLK_AUDIO_AWB2, "audio_awb2", "a1sys_hp_sel", 15),
GATE_AUDIO2(CLK_AUDIO_DAI, "audio_dai", "a1sys_hp_sel", 16),
GATE_AUDIO2(CLK_AUDIO_MOD, "audio_mod", "a1sys_hp_sel", 17),
/* AUDIO3 */
GATE_AUDIO3(CLK_AUDIO_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
GATE_AUDIO3(CLK_AUDIO_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
GATE_AUDIO3(CLK_AUDIO_ASRCO3, "audio_asrco3", "asm_h_sel", 6),
GATE_AUDIO3(CLK_AUDIO_ASRCO4, "audio_asrco4", "asm_h_sel", 7),
GATE_AUDIO3(CLK_AUDIO_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10),
GATE_AUDIO3(CLK_AUDIO_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11),
GATE_AUDIO3(CLK_AUDIO_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12),
GATE_AUDIO3(CLK_AUDIO_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13),
GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
};
static const struct mtk_clk_desc audio_desc = {
.clks = audio_clks,
.num_clks = ARRAY_SIZE(audio_clks),
};
static int clk_mt7622_aud_probe(struct platform_device *pdev)
{
int r;
r = mtk_clk_simple_probe(pdev);
if (r) {
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
return r;
}
r = devm_of_platform_populate(&pdev->dev);
if (r)
goto err_plat_populate;
return 0;
err_plat_populate:
mtk_clk_simple_remove(pdev);
return r;
}
static void clk_mt7622_aud_remove(struct platform_device *pdev)
{
of_platform_depopulate(&pdev->dev);
mtk_clk_simple_remove(pdev);
}
static const struct of_device_id of_match_clk_mt7622_aud[] = {
{ .compatible = "mediatek,mt7622-audsys", .data = &audio_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_aud);
static struct platform_driver clk_mt7622_aud_drv = {
.probe = clk_mt7622_aud_probe,
.remove_new = clk_mt7622_aud_remove,
.driver = {
.name = "clk-mt7622-aud",
.of_match_table = of_match_clk_mt7622_aud,
},
};
module_platform_driver(clk_mt7622_aud_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt7622-aud.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Kevin-CW Chen <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt6797-clk.h>
static const struct mtk_gate_regs vdec0_cg_regs = {
.set_ofs = 0x0000,
.clr_ofs = 0x0004,
.sta_ofs = 0x0000,
};
static const struct mtk_gate_regs vdec1_cg_regs = {
.set_ofs = 0x0008,
.clr_ofs = 0x000c,
.sta_ofs = 0x0008,
};
#define GATE_VDEC0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
#define GATE_VDEC1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate vdec_clks[] = {
GATE_VDEC0(CLK_VDEC_CKEN_ENG, "vdec_cken_eng", "vdec_sel", 8),
GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "vdec_sel", 4),
GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "mm_sel", 0),
};
static const struct mtk_clk_desc vdec_desc = {
.clks = vdec_clks,
.num_clks = ARRAY_SIZE(vdec_clks),
};
static const struct of_device_id of_match_clk_mt6797_vdec[] = {
{
.compatible = "mediatek,mt6797-vdecsys",
.data = &vdec_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6797_vdec);
static struct platform_driver clk_mt6797_vdec_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt6797-vdec",
.of_match_table = of_match_clk_mt6797_vdec,
},
};
module_platform_driver(clk_mt6797_vdec_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6797-vdec.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Shunli Wang <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt2701-clk.h>
static const struct mtk_gate_regs eth_cg_regs = {
.sta_ofs = 0x0030,
};
#define GATE_ETH(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate eth_clks[] = {
GATE_DUMMY(CLK_DUMMY, "eth_dummy"),
GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),
GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),
GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
GATE_ETH(CLK_ETHSYS_GP1, "gp1_clk", "ethpll_500m_ck", 8),
GATE_ETH(CLK_ETHSYS_PCM, "pcm_clk", "ethif_sel", 11),
GATE_ETH(CLK_ETHSYS_GDMA, "gdma_clk", "ethif_sel", 14),
GATE_ETH(CLK_ETHSYS_I2S, "i2s_clk", "ethif_sel", 17),
GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
};
static u16 rst_ofs[] = { 0x34, };
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SIMPLE,
.rst_bank_ofs = rst_ofs,
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
static const struct mtk_clk_desc eth_desc = {
.clks = eth_clks,
.num_clks = ARRAY_SIZE(eth_clks),
.rst_desc = &clk_rst_desc,
};
static const struct of_device_id of_match_clk_mt2701_eth[] = {
{ .compatible = "mediatek,mt2701-ethsys", .data = ð_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_eth);
static struct platform_driver clk_mt2701_eth_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt2701-eth",
.of_match_table = of_match_clk_mt2701_eth,
},
};
module_platform_driver(clk_mt2701_eth_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt2701-eth.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: James Liao <[email protected]>
* Fabien Parent <[email protected]>
* Copyright (c) 2023 Collabora Ltd.
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8516-clk.h>
static const struct mtk_gate_regs aud_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x0,
.sta_ofs = 0x0,
};
#define GATE_AUD(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &aud_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate aud_clks[] = {
GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2),
GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6),
GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8),
GATE_AUD(CLK_AUD_24M, "aud_24m", "rg_aud_engen2", 9),
GATE_AUD(CLK_AUD_INTDIR, "aud_intdir", "rg_aud_spdif_in", 15),
GATE_AUD(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "rg_aud_engen2", 18),
GATE_AUD(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "rg_aud_engen1", 19),
GATE_AUD(CLK_AUD_HDMI, "aud_hdmi", "apll12_div4", 20),
GATE_AUD(CLK_AUD_SPDF, "aud_spdf", "apll12_div6", 21),
GATE_AUD(CLK_AUD_ADC, "aud_adc", "aud_afe", 24),
GATE_AUD(CLK_AUD_DAC, "aud_dac", "aud_afe", 25),
GATE_AUD(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "aud_afe", 26),
GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27),
};
static const struct mtk_clk_desc aud_desc = {
.clks = aud_clks,
.num_clks = ARRAY_SIZE(aud_clks),
};
static const struct of_device_id of_match_clk_mt8516_aud[] = {
{ .compatible = "mediatek,mt8516-audsys", .data = &aud_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8516_aud);
static struct platform_driver clk_mt8516_aud_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8516-aud",
.of_match_table = of_match_clk_mt8516_aud,
},
};
module_platform_driver(clk_mt8516_aud_drv);
MODULE_DESCRIPTION("MediaTek MT8516 audiosys clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8516-aud.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs wpe_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x0,
.sta_ofs = 0x0,
};
static const struct mtk_gate_regs wpe_vpp0_cg_regs = {
.set_ofs = 0x58,
.clr_ofs = 0x58,
.sta_ofs = 0x58,
};
static const struct mtk_gate_regs wpe_vpp1_cg_regs = {
.set_ofs = 0x5c,
.clr_ofs = 0x5c,
.sta_ofs = 0x5c,
};
#define GATE_WPE(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &wpe_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
#define GATE_WPE_VPP0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &wpe_vpp0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
#define GATE_WPE_VPP1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &wpe_vpp1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate wpe_clks[] = {
GATE_WPE(CLK_WPE_VPP0, "wpe_vpp0", "top_wpe_vpp", 16),
GATE_WPE(CLK_WPE_VPP1, "wpe_vpp1", "top_wpe_vpp", 17),
GATE_WPE(CLK_WPE_SMI_LARB7, "wpe_smi_larb7", "top_wpe_vpp", 18),
GATE_WPE(CLK_WPE_SMI_LARB8, "wpe_smi_larb8", "top_wpe_vpp", 19),
GATE_WPE(CLK_WPE_EVENT_TX, "wpe_event_tx", "top_wpe_vpp", 20),
GATE_WPE(CLK_WPE_SMI_LARB7_P, "wpe_smi_larb7_p", "top_wpe_vpp", 24),
GATE_WPE(CLK_WPE_SMI_LARB8_P, "wpe_smi_larb8_p", "top_wpe_vpp", 25),
};
static const struct mtk_gate wpe_vpp0_clks[] = {
/* WPE_VPP0 */
GATE_WPE_VPP0(CLK_WPE_VPP0_VGEN, "wpe_vpp0_vgen", "top_img", 0),
GATE_WPE_VPP0(CLK_WPE_VPP0_EXT, "wpe_vpp0_ext", "top_img", 1),
GATE_WPE_VPP0(CLK_WPE_VPP0_VFC, "wpe_vpp0_vfc", "top_img", 2),
GATE_WPE_VPP0(CLK_WPE_VPP0_CACH0_TOP, "wpe_vpp0_cach0_top", "top_img", 3),
GATE_WPE_VPP0(CLK_WPE_VPP0_CACH0_DMA, "wpe_vpp0_cach0_dma", "top_img", 4),
GATE_WPE_VPP0(CLK_WPE_VPP0_CACH1_TOP, "wpe_vpp0_cach1_top", "top_img", 5),
GATE_WPE_VPP0(CLK_WPE_VPP0_CACH1_DMA, "wpe_vpp0_cach1_dma", "top_img", 6),
GATE_WPE_VPP0(CLK_WPE_VPP0_CACH2_TOP, "wpe_vpp0_cach2_top", "top_img", 7),
GATE_WPE_VPP0(CLK_WPE_VPP0_CACH2_DMA, "wpe_vpp0_cach2_dma", "top_img", 8),
GATE_WPE_VPP0(CLK_WPE_VPP0_CACH3_TOP, "wpe_vpp0_cach3_top", "top_img", 9),
GATE_WPE_VPP0(CLK_WPE_VPP0_CACH3_DMA, "wpe_vpp0_cach3_dma", "top_img", 10),
GATE_WPE_VPP0(CLK_WPE_VPP0_PSP, "wpe_vpp0_psp", "top_img", 11),
GATE_WPE_VPP0(CLK_WPE_VPP0_PSP2, "wpe_vpp0_psp2", "top_img", 12),
GATE_WPE_VPP0(CLK_WPE_VPP0_SYNC, "wpe_vpp0_sync", "top_img", 13),
GATE_WPE_VPP0(CLK_WPE_VPP0_C24, "wpe_vpp0_c24", "top_img", 14),
GATE_WPE_VPP0(CLK_WPE_VPP0_MDP_CROP, "wpe_vpp0_mdp_crop", "top_img", 15),
GATE_WPE_VPP0(CLK_WPE_VPP0_ISP_CROP, "wpe_vpp0_isp_crop", "top_img", 16),
GATE_WPE_VPP0(CLK_WPE_VPP0_TOP, "wpe_vpp0_top", "top_img", 17),
/* WPE_VPP1 */
GATE_WPE_VPP1(CLK_WPE_VPP0_VECI, "wpe_vpp0_veci", "top_img", 0),
GATE_WPE_VPP1(CLK_WPE_VPP0_VEC2I, "wpe_vpp0_vec2i", "top_img", 1),
GATE_WPE_VPP1(CLK_WPE_VPP0_VEC3I, "wpe_vpp0_vec3i", "top_img", 2),
GATE_WPE_VPP1(CLK_WPE_VPP0_WPEO, "wpe_vpp0_wpeo", "top_img", 3),
GATE_WPE_VPP1(CLK_WPE_VPP0_MSKO, "wpe_vpp0_msko", "top_img", 4),
};
static const struct mtk_gate wpe_vpp1_clks[] = {
/* WPE_VPP0 */
GATE_WPE_VPP0(CLK_WPE_VPP1_VGEN, "wpe_vpp1_vgen", "top_img", 0),
GATE_WPE_VPP0(CLK_WPE_VPP1_EXT, "wpe_vpp1_ext", "top_img", 1),
GATE_WPE_VPP0(CLK_WPE_VPP1_VFC, "wpe_vpp1_vfc", "top_img", 2),
GATE_WPE_VPP0(CLK_WPE_VPP1_CACH0_TOP, "wpe_vpp1_cach0_top", "top_img", 3),
GATE_WPE_VPP0(CLK_WPE_VPP1_CACH0_DMA, "wpe_vpp1_cach0_dma", "top_img", 4),
GATE_WPE_VPP0(CLK_WPE_VPP1_CACH1_TOP, "wpe_vpp1_cach1_top", "top_img", 5),
GATE_WPE_VPP0(CLK_WPE_VPP1_CACH1_DMA, "wpe_vpp1_cach1_dma", "top_img", 6),
GATE_WPE_VPP0(CLK_WPE_VPP1_CACH2_TOP, "wpe_vpp1_cach2_top", "top_img", 7),
GATE_WPE_VPP0(CLK_WPE_VPP1_CACH2_DMA, "wpe_vpp1_cach2_dma", "top_img", 8),
GATE_WPE_VPP0(CLK_WPE_VPP1_CACH3_TOP, "wpe_vpp1_cach3_top", "top_img", 9),
GATE_WPE_VPP0(CLK_WPE_VPP1_CACH3_DMA, "wpe_vpp1_cach3_dma", "top_img", 10),
GATE_WPE_VPP0(CLK_WPE_VPP1_PSP, "wpe_vpp1_psp", "top_img", 11),
GATE_WPE_VPP0(CLK_WPE_VPP1_PSP2, "wpe_vpp1_psp2", "top_img", 12),
GATE_WPE_VPP0(CLK_WPE_VPP1_SYNC, "wpe_vpp1_sync", "top_img", 13),
GATE_WPE_VPP0(CLK_WPE_VPP1_C24, "wpe_vpp1_c24", "top_img", 14),
GATE_WPE_VPP0(CLK_WPE_VPP1_MDP_CROP, "wpe_vpp1_mdp_crop", "top_img", 15),
GATE_WPE_VPP0(CLK_WPE_VPP1_ISP_CROP, "wpe_vpp1_isp_crop", "top_img", 16),
GATE_WPE_VPP0(CLK_WPE_VPP1_TOP, "wpe_vpp1_top", "top_img", 17),
/* WPE_VPP1 */
GATE_WPE_VPP1(CLK_WPE_VPP1_VECI, "wpe_vpp1_veci", "top_img", 0),
GATE_WPE_VPP1(CLK_WPE_VPP1_VEC2I, "wpe_vpp1_vec2i", "top_img", 1),
GATE_WPE_VPP1(CLK_WPE_VPP1_VEC3I, "wpe_vpp1_vec3i", "top_img", 2),
GATE_WPE_VPP1(CLK_WPE_VPP1_WPEO, "wpe_vpp1_wpeo", "top_img", 3),
GATE_WPE_VPP1(CLK_WPE_VPP1_MSKO, "wpe_vpp1_msko", "top_img", 4),
};
static const struct mtk_clk_desc wpe_desc = {
.clks = wpe_clks,
.num_clks = ARRAY_SIZE(wpe_clks),
};
static const struct mtk_clk_desc wpe_vpp0_desc = {
.clks = wpe_vpp0_clks,
.num_clks = ARRAY_SIZE(wpe_vpp0_clks),
};
static const struct mtk_clk_desc wpe_vpp1_desc = {
.clks = wpe_vpp1_clks,
.num_clks = ARRAY_SIZE(wpe_vpp1_clks),
};
static const struct of_device_id of_match_clk_mt8195_wpe[] = {
{
.compatible = "mediatek,mt8195-wpesys",
.data = &wpe_desc,
}, {
.compatible = "mediatek,mt8195-wpesys_vpp0",
.data = &wpe_vpp0_desc,
}, {
.compatible = "mediatek,mt8195-wpesys_vpp1",
.data = &wpe_vpp1_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_wpe);
static struct platform_driver clk_mt8195_wpe_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8195-wpe",
.of_match_table = of_match_clk_mt8195_wpe,
},
};
module_platform_driver(clk_mt8195_wpe_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8195-wpe.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Garmin Chang <[email protected]>
*/
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs cam_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_CAM(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate cam_main_clks[] = {
GATE_CAM(CLK_CAM_MAIN_LARB13, "cam_main_larb13", "top_cam", 0),
GATE_CAM(CLK_CAM_MAIN_LARB14, "cam_main_larb14", "top_cam", 1),
GATE_CAM(CLK_CAM_MAIN_CAM, "cam_main_cam", "top_cam", 2),
GATE_CAM(CLK_CAM_MAIN_CAM_SUBA, "cam_main_cam_suba", "top_cam", 3),
GATE_CAM(CLK_CAM_MAIN_CAM_SUBB, "cam_main_cam_subb", "top_cam", 4),
GATE_CAM(CLK_CAM_MAIN_CAMTG, "cam_main_camtg", "top_cam", 7),
GATE_CAM(CLK_CAM_MAIN_SENINF, "cam_main_seninf", "top_cam", 8),
GATE_CAM(CLK_CAM_MAIN_GCAMSVA, "cam_main_gcamsva", "top_cam", 9),
GATE_CAM(CLK_CAM_MAIN_GCAMSVB, "cam_main_gcamsvb", "top_cam", 10),
GATE_CAM(CLK_CAM_MAIN_GCAMSVC, "cam_main_gcamsvc", "top_cam", 11),
GATE_CAM(CLK_CAM_MAIN_GCAMSVD, "cam_main_gcamsvd", "top_cam", 12),
GATE_CAM(CLK_CAM_MAIN_GCAMSVE, "cam_main_gcamsve", "top_cam", 13),
GATE_CAM(CLK_CAM_MAIN_GCAMSVF, "cam_main_gcamsvf", "top_cam", 14),
GATE_CAM(CLK_CAM_MAIN_GCAMSVG, "cam_main_gcamsvg", "top_cam", 15),
GATE_CAM(CLK_CAM_MAIN_GCAMSVH, "cam_main_gcamsvh", "top_cam", 16),
GATE_CAM(CLK_CAM_MAIN_GCAMSVI, "cam_main_gcamsvi", "top_cam", 17),
GATE_CAM(CLK_CAM_MAIN_GCAMSVJ, "cam_main_gcamsvj", "top_cam", 18),
GATE_CAM(CLK_CAM_MAIN_CAMSV_TOP, "cam_main_camsv", "top_cam", 19),
GATE_CAM(CLK_CAM_MAIN_CAMSV_CQ_A, "cam_main_camsv_cq_a", "top_cam", 20),
GATE_CAM(CLK_CAM_MAIN_CAMSV_CQ_B, "cam_main_camsv_cq_b", "top_cam", 21),
GATE_CAM(CLK_CAM_MAIN_CAMSV_CQ_C, "cam_main_camsv_cq_c", "top_cam", 22),
GATE_CAM(CLK_CAM_MAIN_FAKE_ENG, "cam_main_fake_eng", "top_cam", 28),
GATE_CAM(CLK_CAM_MAIN_CAM2MM0_GALS, "cam_main_cam2mm0_gals", "top_cam", 29),
GATE_CAM(CLK_CAM_MAIN_CAM2MM1_GALS, "cam_main_cam2mm1_gals", "top_cam", 30),
GATE_CAM(CLK_CAM_MAIN_CAM2SYS_GALS, "cam_main_cam2sys_gals", "top_cam", 31),
};
static const struct mtk_gate cam_rawa_clks[] = {
GATE_CAM(CLK_CAM_RAWA_LARBX, "cam_rawa_larbx", "top_cam", 0),
GATE_CAM(CLK_CAM_RAWA_CAM, "cam_rawa_cam", "top_cam", 1),
GATE_CAM(CLK_CAM_RAWA_CAMTG, "cam_rawa_camtg", "top_cam", 2),
};
static const struct mtk_gate cam_rawb_clks[] = {
GATE_CAM(CLK_CAM_RAWB_LARBX, "cam_rawb_larbx", "top_cam", 0),
GATE_CAM(CLK_CAM_RAWB_CAM, "cam_rawb_cam", "top_cam", 1),
GATE_CAM(CLK_CAM_RAWB_CAMTG, "cam_rawb_camtg", "top_cam", 2),
};
static const struct mtk_gate cam_yuva_clks[] = {
GATE_CAM(CLK_CAM_YUVA_LARBX, "cam_yuva_larbx", "top_cam", 0),
GATE_CAM(CLK_CAM_YUVA_CAM, "cam_yuva_cam", "top_cam", 1),
GATE_CAM(CLK_CAM_YUVA_CAMTG, "cam_yuva_camtg", "top_cam", 2),
};
static const struct mtk_gate cam_yuvb_clks[] = {
GATE_CAM(CLK_CAM_YUVB_LARBX, "cam_yuvb_larbx", "top_cam", 0),
GATE_CAM(CLK_CAM_YUVB_CAM, "cam_yuvb_cam", "top_cam", 1),
GATE_CAM(CLK_CAM_YUVB_CAMTG, "cam_yuvb_camtg", "top_cam", 2),
};
static const struct mtk_clk_desc cam_main_desc = {
.clks = cam_main_clks,
.num_clks = ARRAY_SIZE(cam_main_clks),
};
static const struct mtk_clk_desc cam_rawa_desc = {
.clks = cam_rawa_clks,
.num_clks = ARRAY_SIZE(cam_rawa_clks),
};
static const struct mtk_clk_desc cam_rawb_desc = {
.clks = cam_rawb_clks,
.num_clks = ARRAY_SIZE(cam_rawb_clks),
};
static const struct mtk_clk_desc cam_yuva_desc = {
.clks = cam_yuva_clks,
.num_clks = ARRAY_SIZE(cam_yuva_clks),
};
static const struct mtk_clk_desc cam_yuvb_desc = {
.clks = cam_yuvb_clks,
.num_clks = ARRAY_SIZE(cam_yuvb_clks),
};
static const struct of_device_id of_match_clk_mt8188_cam[] = {
{ .compatible = "mediatek,mt8188-camsys", .data = &cam_main_desc },
{ .compatible = "mediatek,mt8188-camsys-rawa", .data = &cam_rawa_desc },
{ .compatible = "mediatek,mt8188-camsys-rawb", .data = &cam_rawb_desc },
{ .compatible = "mediatek,mt8188-camsys-yuva", .data = &cam_yuva_desc },
{ .compatible = "mediatek,mt8188-camsys-yuvb", .data = &cam_yuvb_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_cam);
static struct platform_driver clk_mt8188_cam_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8188-cam",
.of_match_table = of_match_clk_mt8188_cam,
},
};
module_platform_driver(clk_mt8188_cam_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8188-cam.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 MediaTek Inc.
* Copyright (c) 2020 BayLibre, SAS
* Author: James Liao <[email protected]>
* Fabien Parent <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8167-clk.h>
static const struct mtk_gate_regs vdec0_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x4,
.sta_ofs = 0x0,
};
static const struct mtk_gate_regs vdec1_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0xc,
.sta_ofs = 0x8,
};
#define GATE_VDEC0_I(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
#define GATE_VDEC1_I(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate vdec_clks[] = {
/* VDEC0 */
GATE_VDEC0_I(CLK_VDEC_CKEN, "vdec_cken", "rg_vdec", 0),
/* VDEC1 */
GATE_VDEC1_I(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "smi_mm", 0),
};
static const struct mtk_clk_desc vdec_desc = {
.clks = vdec_clks,
.num_clks = ARRAY_SIZE(vdec_clks),
};
static const struct of_device_id of_match_clk_mt8167_vdec[] = {
{ .compatible = "mediatek,mt8167-vdecsys", .data = &vdec_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_vdec);
static struct platform_driver clk_mt8167_vdec_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8167-vdecsys",
.of_match_table = of_match_clk_mt8167_vdec,
},
};
module_platform_driver(clk_mt8167_vdec_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8167-vdec.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Weiyi Lu <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt2712-clk.h>
static const struct mtk_gate_regs venc_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_VENC(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate venc_clks[] = {
GATE_VENC(CLK_VENC_SMI_COMMON_CON, "venc_smi", "mm_sel", 0),
GATE_VENC(CLK_VENC_VENC, "venc_venc", "venc_sel", 4),
GATE_VENC(CLK_VENC_SMI_LARB6, "venc_smi_larb6", "jpgdec_sel", 12),
};
static const struct mtk_clk_desc venc_desc = {
.clks = venc_clks,
.num_clks = ARRAY_SIZE(venc_clks),
};
static const struct of_device_id of_match_clk_mt2712_venc[] = {
{
.compatible = "mediatek,mt2712-vencsys",
.data = &venc_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_venc);
static struct platform_driver clk_mt2712_venc_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt2712-venc",
.of_match_table = of_match_clk_mt2712_venc,
},
};
module_platform_driver(clk_mt2712_venc_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt2712-venc.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Copyright (c) 2023 Collabora Ltd.
*/
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "clk-pll.h"
#include "clk-mtk.h"
#define MT8365_PLL_FMAX (3800UL * MHZ)
#define MT8365_PLL_FMIN (1500UL * MHZ)
#define CON0_MT8365_RST_BAR BIT(23)
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
_tuner_en_bit, _pcw_reg, _pcw_shift, _div_table, \
_rst_bar_mask, _pcw_chg_reg) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = _en_mask, \
.flags = _flags, \
.rst_bar_mask = _rst_bar_mask, \
.fmax = MT8365_PLL_FMAX, \
.fmin = MT8365_PLL_FMIN, \
.pcwbits = _pcwbits, \
.pcwibits = 8, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, \
.tuner_en_reg = _tuner_en_reg, \
.tuner_en_bit = _tuner_en_bit, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
.pcw_chg_reg = _pcw_chg_reg, \
.div_table = _div_table, \
}
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, \
_tuner_en_reg, _tuner_en_bit, _pcw_reg, \
_pcw_shift, _rst_bar_mask, _pcw_chg_reg) \
PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
_pcwbits, _pd_reg, _pd_shift, \
_tuner_reg, _tuner_en_reg, _tuner_en_bit, \
_pcw_reg, _pcw_shift, NULL, _rst_bar_mask, \
_pcw_chg_reg) \
static const struct mtk_pll_div_table armpll_div_table[] = {
{ .div = 0, .freq = MT8365_PLL_FMAX },
{ .div = 1, .freq = 1500 * MHZ },
{ .div = 2, .freq = 750 * MHZ },
{ .div = 3, .freq = 375 * MHZ },
{ .div = 4, .freq = 182500000 },
{ } /* sentinel */
};
static const struct mtk_pll_div_table mfgpll_div_table[] = {
{ .div = 0, .freq = MT8365_PLL_FMAX },
{ .div = 1, .freq = 1600 * MHZ },
{ .div = 2, .freq = 800 * MHZ },
{ .div = 3, .freq = 400 * MHZ },
{ .div = 4, .freq = 200 * MHZ },
{ } /* sentinel */
};
static const struct mtk_pll_div_table dsppll_div_table[] = {
{ .div = 0, .freq = MT8365_PLL_FMAX },
{ .div = 1, .freq = 1600 * MHZ },
{ .div = 2, .freq = 600 * MHZ },
{ .div = 3, .freq = 400 * MHZ },
{ .div = 4, .freq = 200 * MHZ },
{ } /* sentinel */
};
static const struct mtk_pll_data plls[] = {
PLL_B(CLK_APMIXED_ARMPLL, "armpll", 0x030C, 0x0318, 0x00000001, PLL_AO,
22, 0x0310, 24, 0, 0, 0, 0x0310, 0, armpll_div_table, 0, 0),
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0228, 0x0234, 0xFF000001,
HAVE_RST_BAR, 22, 0x022C, 24, 0, 0, 0, 0x022C, 0, CON0_MT8365_RST_BAR, 0),
PLL(CLK_APMIXED_UNIVPLL, "univpll2", 0x0208, 0x0214, 0xFF000001,
HAVE_RST_BAR, 22, 0x020C, 24, 0, 0, 0, 0x020C, 0, CON0_MT8365_RST_BAR, 0),
PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0218, 0x0224, 0x00000001, 0, 22,
0x021C, 24, 0, 0, 0, 0x021C, 0, mfgpll_div_table, 0, 0),
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035C, 0x00000001, 0, 22,
0x0354, 24, 0, 0, 0, 0x0354, 0, 0, 0),
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0330, 0x033C, 0x00000001, 0, 22,
0x0334, 24, 0, 0, 0, 0x0334, 0, 0, 0),
PLL(CLK_APMIXED_APLL1, "apll1", 0x031C, 0x032C, 0x00000001, 0, 32,
0x0320, 24, 0x0040, 0x000C, 0, 0x0324, 0, 0, 0x0320),
PLL(CLK_APMIXED_APLL2, "apll2", 0x0360, 0x0370, 0x00000001, 0, 32,
0x0364, 24, 0x004C, 0x000C, 5, 0x0368, 0, 0, 0x0364),
PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0374, 0x0380, 0x00000001, 0, 22,
0x0378, 24, 0, 0, 0, 0x0378, 0, 0, 0),
PLL_B(CLK_APMIXED_DSPPLL, "dsppll", 0x0390, 0x039C, 0x00000001, 0, 22,
0x0394, 24, 0, 0, 0, 0x0394, 0, dsppll_div_table, 0, 0),
PLL(CLK_APMIXED_APUPLL, "apupll", 0x03A0, 0x03AC, 0x00000001, 0, 22,
0x03A4, 24, 0, 0, 0, 0x03A4, 0, 0, 0),
};
static int clk_mt8365_apmixed_probe(struct platform_device *pdev)
{
void __iomem *base;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
struct device *dev = &pdev->dev;
struct clk_hw *hw;
int ret;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK);
if (!clk_data)
return -ENOMEM;
hw = devm_clk_hw_register_gate(dev, "univ_en", "univpll2", 0,
base + 0x204, 0, 0, NULL);
if (IS_ERR(hw))
return PTR_ERR(hw);
clk_data->hws[CLK_APMIXED_UNIV_EN] = hw;
hw = devm_clk_hw_register_gate(dev, "usb20_en", "univ_en", 0,
base + 0x204, 1, 0, NULL);
if (IS_ERR(hw))
return PTR_ERR(hw);
clk_data->hws[CLK_APMIXED_USB20_EN] = hw;
ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
if (ret)
return ret;
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (ret)
goto unregister_plls;
return 0;
unregister_plls:
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
return ret;
}
static const struct of_device_id of_match_clk_mt8365_apmixed[] = {
{ .compatible = "mediatek,mt8365-apmixedsys" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_apmixed);
static struct platform_driver clk_mt8365_apmixed_drv = {
.probe = clk_mt8365_apmixed_probe,
.driver = {
.name = "clk-mt8365-apmixed",
.of_match_table = of_match_clk_mt8365_apmixed,
},
};
builtin_platform_driver(clk_mt8365_apmixed_drv)
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8365-apmixedsys.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: James Liao <[email protected]>
*/
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/mfd/syscon.h>
#include <dt-bindings/clock/mt8135-clk.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-pll.h"
static DEFINE_SPINLOCK(mt8135_clk_lock);
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_DUMMY, "top_divs_dummy", "clk_null", 1, 1),
FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1),
FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1),
FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1),
FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1),
FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_806m", "mainpll", 1, 2),
FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_537p3m", "mainpll", 1, 3),
FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_322p4m", "mainpll", 1, 5),
FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_230p3m", "mainpll", 1, 7),
FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3),
FACTOR(CLK_TOP_UNIVPLL_249P6M, "univpll_249p6m", "univpll", 1, 5),
FACTOR(CLK_TOP_UNIVPLL_178P3M, "univpll_178p3m", "univpll", 1, 7),
FACTOR(CLK_TOP_UNIVPLL_48M, "univpll_48m", "univpll", 1, 26),
FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
FACTOR(CLK_TOP_MMPLL_D3, "mmpll_d3", "mmpll", 1, 3),
FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_d2", 1, 2),
FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_d3", 1, 2),
FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll_806m", 1, 1),
FACTOR(CLK_TOP_SYSPLL_D4, "syspll_d4", "mainpll_806m", 1, 2),
FACTOR(CLK_TOP_SYSPLL_D6, "syspll_d6", "mainpll_806m", 1, 3),
FACTOR(CLK_TOP_SYSPLL_D8, "syspll_d8", "mainpll_806m", 1, 4),
FACTOR(CLK_TOP_SYSPLL_D10, "syspll_d10", "mainpll_806m", 1, 5),
FACTOR(CLK_TOP_SYSPLL_D12, "syspll_d12", "mainpll_806m", 1, 6),
FACTOR(CLK_TOP_SYSPLL_D16, "syspll_d16", "mainpll_806m", 1, 8),
FACTOR(CLK_TOP_SYSPLL_D24, "syspll_d24", "mainpll_806m", 1, 12),
FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll_537p3m", 1, 1),
FACTOR(CLK_TOP_SYSPLL_D2P5, "syspll_d2p5", "mainpll_322p4m", 2, 1),
FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_322p4m", 1, 1),
FACTOR(CLK_TOP_SYSPLL_D3P5, "syspll_d3p5", "mainpll_230p3m", 2, 1),
FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4),
FACTOR(CLK_TOP_UNIVPLL1_D6, "univpll1_d6", "univpll_624m", 1, 6),
FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8),
FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10),
FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2),
FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4),
FACTOR(CLK_TOP_UNIVPLL2_D6, "univpll2_d6", "univpll_416m", 1, 6),
FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_416m", 1, 1),
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1),
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_178p3m", 1, 1),
FACTOR(CLK_TOP_UNIVPLL_D10, "univpll_d10", "univpll_249p6m", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1),
FACTOR(CLK_TOP_APLL, "apll_ck", "audpll", 1, 1),
FACTOR(CLK_TOP_APLL_D4, "apll_d4", "audpll", 1, 4),
FACTOR(CLK_TOP_APLL_D8, "apll_d8", "audpll", 1, 8),
FACTOR(CLK_TOP_APLL_D16, "apll_d16", "audpll", 1, 16),
FACTOR(CLK_TOP_APLL_D24, "apll_d24", "audpll", 1, 24),
FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
FACTOR(CLK_TOP_LVDSTX_CLKDIG_CT, "lvdstx_clkdig_cts", "lvdspll", 1, 1),
FACTOR(CLK_TOP_VPLL_DPIX, "vpll_dpix_ck", "lvdspll", 1, 1),
FACTOR(CLK_TOP_TVHDMI_H, "tvhdmi_h_ck", "tvdpll", 1, 1),
FACTOR(CLK_TOP_HDMITX_CLKDIG_D2, "hdmitx_clkdig_d2", "hdmitx_clkdig_cts", 1, 2),
FACTOR(CLK_TOP_HDMITX_CLKDIG_D3, "hdmitx_clkdig_d3", "hdmitx_clkdig_cts", 1, 3),
FACTOR(CLK_TOP_TVHDMI_D2, "tvhdmi_d2", "tvhdmi_h_ck", 1, 2),
FACTOR(CLK_TOP_TVHDMI_D4, "tvhdmi_d4", "tvhdmi_h_ck", 1, 4),
FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4),
};
static const char * const axi_parents[] = {
"clk26m",
"syspll_d3",
"syspll_d4",
"syspll_d6",
"univpll_d5",
"univpll2_d2",
"syspll_d3p5"
};
static const char * const smi_parents[] = {
"clk26m",
"clkph_mck",
"syspll_d2p5",
"syspll_d3",
"syspll_d8",
"univpll_d5",
"univpll1_d2",
"univpll1_d6",
"mmpll_d3",
"mmpll_d4",
"mmpll_d5",
"mmpll_d6",
"mmpll_d7",
"vdecpll",
"lvdspll"
};
static const char * const mfg_parents[] = {
"clk26m",
"univpll1_d4",
"syspll_d2",
"syspll_d2p5",
"syspll_d3",
"univpll_d5",
"univpll1_d2",
"mmpll_d2",
"mmpll_d3",
"mmpll_d4",
"mmpll_d5",
"mmpll_d6",
"mmpll_d7"
};
static const char * const irda_parents[] = {
"clk26m",
"univpll2_d8",
"univpll1_d6"
};
static const char * const cam_parents[] = {
"clk26m",
"syspll_d3",
"syspll_d3p5",
"syspll_d4",
"univpll_d5",
"univpll2_d2",
"univpll_d7",
"univpll1_d4"
};
static const char * const aud_intbus_parents[] = {
"clk26m",
"syspll_d6",
"univpll_d10"
};
static const char * const jpg_parents[] = {
"clk26m",
"syspll_d5",
"syspll_d4",
"syspll_d3",
"univpll_d7",
"univpll2_d2",
"univpll_d5"
};
static const char * const disp_parents[] = {
"clk26m",
"syspll_d3p5",
"syspll_d3",
"univpll2_d2",
"univpll_d5",
"univpll1_d2",
"lvdspll",
"vdecpll"
};
static const char * const msdc30_parents[] = {
"clk26m",
"syspll_d6",
"syspll_d5",
"univpll1_d4",
"univpll2_d4",
"msdcpll"
};
static const char * const usb20_parents[] = {
"clk26m",
"univpll2_d6",
"univpll1_d10"
};
static const char * const venc_parents[] = {
"clk26m",
"syspll_d3",
"syspll_d8",
"univpll_d5",
"univpll1_d6",
"mmpll_d4",
"mmpll_d5",
"mmpll_d6"
};
static const char * const spi_parents[] = {
"clk26m",
"syspll_d6",
"syspll_d8",
"syspll_d10",
"univpll1_d6",
"univpll1_d8"
};
static const char * const uart_parents[] = {
"clk26m",
"univpll2_d8"
};
static const char * const mem_parents[] = {
"clk26m",
"clkph_mck"
};
static const char * const camtg_parents[] = {
"clk26m",
"univpll_d26",
"univpll1_d6",
"syspll_d16",
"syspll_d8"
};
static const char * const audio_parents[] = {
"clk26m",
"syspll_d24"
};
static const char * const fix_parents[] = {
"rtc32k",
"clk26m",
"univpll_d5",
"univpll_d7",
"univpll1_d2",
"univpll1_d4",
"univpll1_d6",
"univpll1_d8"
};
static const char * const vdec_parents[] = {
"clk26m",
"vdecpll",
"clkph_mck",
"syspll_d2p5",
"syspll_d3",
"syspll_d3p5",
"syspll_d4",
"syspll_d5",
"syspll_d6",
"syspll_d8",
"univpll1_d2",
"univpll2_d2",
"univpll_d7",
"univpll_d10",
"univpll2_d4",
"lvdspll"
};
static const char * const ddrphycfg_parents[] = {
"clk26m",
"axi_sel",
"syspll_d12"
};
static const char * const dpilvds_parents[] = {
"clk26m",
"lvdspll",
"lvdspll_d2",
"lvdspll_d4",
"lvdspll_d8"
};
static const char * const pmicspi_parents[] = {
"clk26m",
"univpll2_d6",
"syspll_d8",
"syspll_d10",
"univpll1_d10",
"mempll_mck_d4",
"univpll_d26",
"syspll_d24"
};
static const char * const smi_mfg_as_parents[] = {
"clk26m",
"smi_sel",
"mfg_sel",
"mem_sel"
};
static const char * const gcpu_parents[] = {
"clk26m",
"syspll_d4",
"univpll_d7",
"syspll_d5",
"syspll_d6"
};
static const char * const dpi1_parents[] = {
"clk26m",
"tvhdmi_h_ck",
"tvhdmi_d2",
"tvhdmi_d4"
};
static const char * const cci_parents[] = {
"clk26m",
"mainpll_537p3m",
"univpll_d3",
"syspll_d2p5",
"syspll_d3",
"syspll_d5"
};
static const char * const apll_parents[] = {
"clk26m",
"apll_ck",
"apll_d4",
"apll_d8",
"apll_d16",
"apll_d24"
};
static const char * const hdmipll_parents[] = {
"clk26m",
"hdmitx_clkdig_cts",
"hdmitx_clkdig_d2",
"hdmitx_clkdig_d3"
};
static const struct mtk_composite top_muxes[] = {
/* CLK_CFG_0 */
MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
0x0140, 0, 3, INVALID_MUX_GATE_BIT),
MUX_GATE(CLK_TOP_SMI_SEL, "smi_sel", smi_parents, 0x0140, 8, 4, 15),
MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23),
MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0140, 24, 2, 31),
/* CLK_CFG_1 */
MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0144, 0, 3, 7),
MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
0x0144, 8, 2, 15),
MUX_GATE(CLK_TOP_JPG_SEL, "jpg_sel", jpg_parents, 0x0144, 16, 3, 23),
MUX_GATE(CLK_TOP_DISP_SEL, "disp_sel", disp_parents, 0x0144, 24, 3, 31),
/* CLK_CFG_2 */
MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7),
MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0148, 8, 3, 15),
MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x0148, 16, 3, 23),
MUX_GATE(CLK_TOP_MSDC30_4_SEL, "msdc30_4_sel", msdc30_parents, 0x0148, 24, 3, 31),
/* CLK_CFG_3 */
MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x014c, 0, 2, 7),
/* CLK_CFG_4 */
MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15),
MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23),
MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
/* CLK_CFG_6 */
MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7),
MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0158, 8, 3, 15),
MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0158, 24, 2, 31),
/* CLK_CFG_7 */
MUX_GATE(CLK_TOP_FIX_SEL, "fix_sel", fix_parents, 0x015c, 0, 3, 7),
MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15),
MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
0x015c, 16, 2, 23),
MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x015c, 24, 3, 31),
/* CLK_CFG_8 */
MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0164, 0, 3, 7),
MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15),
MUX_GATE(CLK_TOP_SMI_MFG_AS_SEL, "smi_mfg_as_sel", smi_mfg_as_parents,
0x0164, 16, 2, 23),
MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0164, 24, 3, 31),
/* CLK_CFG_9 */
MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0168, 0, 2, 7),
MUX_GATE_FLAGS(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15, CLK_IS_CRITICAL),
MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23),
MUX_GATE(CLK_TOP_HDMIPLL_SEL, "hdmipll_sel", hdmipll_parents, 0x0168, 24, 2, 31),
};
static const struct mtk_gate_regs infra_cg_regs = {
.set_ofs = 0x0040,
.clr_ofs = 0x0044,
.sta_ofs = 0x0048,
};
#define GATE_ICG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_ICG_AO(_id, _name, _parent, _shift) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL)
static const struct mtk_gate infra_clks[] = {
GATE_DUMMY(CLK_DUMMY, "infra_dummy"),
GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23),
GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
GATE_ICG(CLK_INFRA_CCIF1_AP_CTRL, "ccif1_ap_ctrl", "axi_sel", 21),
GATE_ICG(CLK_INFRA_CCIF0_AP_CTRL, "ccif0_ap_ctrl", "axi_sel", 20),
GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15),
GATE_ICG_AO(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
GATE_ICG(CLK_INFRA_MFGAXI, "mfgaxi_ck", "axi_sel", 7),
GATE_ICG(CLK_INFRA_DEVAPC, "devapc_ck", "axi_sel", 6),
GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5),
GATE_ICG(CLK_INFRA_MFG_BUS, "mfg_bus_ck", "axi_sel", 2),
GATE_ICG(CLK_INFRA_SMI, "smi_ck", "smi_sel", 1),
GATE_ICG(CLK_INFRA_DBGCLK, "dbgclk_ck", "axi_sel", 0),
};
static const struct mtk_gate_regs peri0_cg_regs = {
.set_ofs = 0x0008,
.clr_ofs = 0x0010,
.sta_ofs = 0x0018,
};
static const struct mtk_gate_regs peri1_cg_regs = {
.set_ofs = 0x000c,
.clr_ofs = 0x0014,
.sta_ofs = 0x001c,
};
#define GATE_PERI0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_PERI1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate peri_gates[] = {
GATE_DUMMY(CLK_DUMMY, "peri_dummy"),
/* PERI0 */
GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31),
GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30),
GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 29),
GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 28),
GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 27),
GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 26),
GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 25),
GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 24),
GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23),
GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22),
GATE_PERI0(CLK_PERI_IRDA, "irda_ck", "irda_sel", 21),
GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 20),
GATE_PERI0(CLK_PERI_MD_HIF, "md_hif_ck", "axi_sel", 19),
GATE_PERI0(CLK_PERI_AP_HIF, "ap_hif_ck", "axi_sel", 18),
GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_4_sel", 17),
GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_3_sel", 16),
GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_2_sel", 15),
GATE_PERI0(CLK_PERI_MSDC20_2, "msdc20_2_ck", "msdc30_1_sel", 14),
GATE_PERI0(CLK_PERI_MSDC20_1, "msdc20_1_ck", "msdc30_0_sel", 13),
GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0),
/* PERI1 */
GATE_PERI1(CLK_PERI_USBSLV, "usbslv_ck", "axi_sel", 8),
GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 7),
GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 6),
GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "gcpu_sel", 5),
GATE_PERI1(CLK_PERI_FHCTL, "fhctl_ck", "clk26m", 4),
GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi_sel", 3),
GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 2),
GATE_PERI1(CLK_PERI_PERI_PWRAP, "peri_pwrap_ck", "axi_sel", 1),
GATE_PERI1(CLK_PERI_I2C6, "i2c6_ck", "axi_sel", 0),
};
static const char * const uart_ck_sel_parents[] = {
"clk26m",
"uart_sel",
};
static const struct mtk_composite peri_clks[] = {
MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
};
static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
/* infrasys */
{
.version = MTK_RST_SIMPLE,
.rst_bank_ofs = infrasys_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
},
/* pericfg */
{
.version = MTK_RST_SIMPLE,
.rst_bank_ofs = pericfg_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
}
};
static const struct mtk_clk_desc infra_desc = {
.clks = infra_clks,
.num_clks = ARRAY_SIZE(infra_clks),
.rst_desc = &clk_rst_desc[0],
};
static const struct mtk_clk_desc peri_desc = {
.clks = peri_gates,
.num_clks = ARRAY_SIZE(peri_gates),
.composite_clks = peri_clks,
.num_composite_clks = ARRAY_SIZE(peri_clks),
.clk_lock = &mt8135_clk_lock,
.rst_desc = &clk_rst_desc[1],
};
static const struct mtk_clk_desc topck_desc = {
.factor_clks = top_divs,
.num_factor_clks = ARRAY_SIZE(top_divs),
.composite_clks = top_muxes,
.num_composite_clks = ARRAY_SIZE(top_muxes),
.clk_lock = &mt8135_clk_lock,
};
static const struct of_device_id of_match_clk_mt8135[] = {
{ .compatible = "mediatek,mt8135-infracfg", .data = &infra_desc },
{ .compatible = "mediatek,mt8135-pericfg", .data = &peri_desc },
{ .compatible = "mediatek,mt8135-topckgen", .data = &topck_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8135);
static struct platform_driver clk_mt8135_drv = {
.driver = {
.name = "clk-mt8135",
.of_match_table = of_match_clk_mt8135,
},
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt8135_drv);
MODULE_DESCRIPTION("MediaTek MT8135 clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8135.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8192-clk.h>
static const struct mtk_gate_regs venc_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_VENC(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate venc_clks[] = {
GATE_VENC(CLK_VENC_SET0_LARB, "venc_set0_larb", "venc_sel", 0),
GATE_VENC(CLK_VENC_SET1_VENC, "venc_set1_venc", "venc_sel", 4),
GATE_VENC(CLK_VENC_SET2_JPGENC, "venc_set2_jpgenc", "venc_sel", 8),
GATE_VENC(CLK_VENC_SET5_GALS, "venc_set5_gals", "venc_sel", 28),
};
static const struct mtk_clk_desc venc_desc = {
.clks = venc_clks,
.num_clks = ARRAY_SIZE(venc_clks),
};
static const struct of_device_id of_match_clk_mt8192_venc[] = {
{
.compatible = "mediatek,mt8192-vencsys",
.data = &venc_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_venc);
static struct platform_driver clk_mt8192_venc_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8192-venc",
.of_match_table = of_match_clk_mt8192_venc,
},
};
module_platform_driver(clk_mt8192_venc_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8192-venc.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 MediaTek Inc.
* Copyright (C) 2023 Collabora Ltd.
* AngeloGioacchino Del Regno <[email protected]>
*/
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/mfd/syscon.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-mux.h"
static DEFINE_SPINLOCK(mt8365_clk_lock);
static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
FIXED_CLK(CLK_TOP_I2S0_BCK, "i2s0_bck", NULL, 26000000),
FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, "dsi0_lntc_dsick", "clk26m",
75000000),
FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", "clk26m", 75000000),
FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx_dig_cts", "clk26m",
52500000),
};
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_SYS_26M_D2, "sys_26m_d2", "clk26m", 1, 2),
FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32),
FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 6),
FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ_en", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll", 1, 96),
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", "mfgpll", 1, 1),
FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
FACTOR(CLK_TOP_LVDSPLL_D16, "lvdspll_d16", "lvdspll", 1, 16),
FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", "usb20_en", 1, 13),
FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", "usb20_192m_ck", 1, 4),
FACTOR(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", "usb20_192m_ck", 1, 8),
FACTOR(CLK_TOP_USB20_192M_D16, "usb20_192m_d16", "usb20_192m_ck",
1, 16),
FACTOR(CLK_TOP_USB20_192M_D32, "usb20_192m_d32", "usb20_192m_ck",
1, 32),
FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4),
FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8),
FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2),
FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 4),
FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1, 8),
FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
FACTOR(CLK_TOP_DSPPLL, "dsppll_ck", "dsppll", 1, 1),
FACTOR(CLK_TOP_DSPPLL_D2, "dsppll_d2", "dsppll", 1, 2),
FACTOR(CLK_TOP_DSPPLL_D4, "dsppll_d4", "dsppll", 1, 4),
FACTOR(CLK_TOP_DSPPLL_D8, "dsppll_d8", "dsppll", 1, 8),
FACTOR(CLK_TOP_APUPLL, "apupll_ck", "apupll", 1, 1),
FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", "clk26m", 1, 52),
};
static const char * const axi_parents[] = {
"clk26m",
"syspll_d7",
"syspll1_d4",
"syspll3_d2"
};
static const char * const mem_parents[] = {
"clk26m",
"mmpll_ck",
"syspll_d3",
"syspll1_d2"
};
static const char * const mm_parents[] = {
"clk26m",
"mmpll_ck",
"syspll1_d2",
"syspll_d5",
"syspll1_d4",
"univpll_d5",
"univpll1_d2",
"mmpll_d2"
};
static const char * const scp_parents[] = {
"clk26m",
"syspll4_d2",
"univpll2_d2",
"syspll1_d2",
"univpll1_d2",
"syspll_d3",
"univpll_d3"
};
static const char * const mfg_parents[] = {
"clk26m",
"mfgpll_ck",
"syspll_d3",
"univpll_d3"
};
static const char * const atb_parents[] = {
"clk26m",
"syspll1_d4",
"syspll1_d2"
};
static const char * const camtg_parents[] = {
"clk26m",
"usb20_192m_d8",
"univpll2_d8",
"usb20_192m_d4",
"univpll2_d32",
"usb20_192m_d16",
"usb20_192m_d32"
};
static const char * const uart_parents[] = {
"clk26m",
"univpll2_d8"
};
static const char * const spi_parents[] = {
"clk26m",
"univpll2_d2",
"univpll2_d4",
"univpll2_d8"
};
static const char * const msdc50_0_hc_parents[] = {
"clk26m",
"syspll1_d2",
"univpll1_d4",
"syspll2_d2"
};
static const char * const msdc50_0_parents[] = {
"clk26m",
"msdcpll_ck",
"univpll1_d2",
"syspll1_d2",
"univpll_d5",
"syspll2_d2",
"univpll1_d4",
"syspll4_d2"
};
static const char * const msdc50_2_parents[] = {
"clk26m",
"msdcpll_ck",
"univpll_d3",
"univpll1_d2",
"syspll1_d2",
"univpll2_d2",
"syspll2_d2",
"univpll1_d4"
};
static const char * const msdc30_1_parents[] = {
"clk26m",
"msdcpll_d2",
"univpll2_d2",
"syspll2_d2",
"univpll1_d4",
"syspll1_d4",
"syspll2_d4",
"univpll2_d8"
};
static const char * const audio_parents[] = {
"clk26m",
"syspll3_d4",
"syspll4_d4",
"syspll1_d16"
};
static const char * const aud_intbus_parents[] = {
"clk26m",
"syspll1_d4",
"syspll4_d2"
};
static const char * const aud_1_parents[] = {
"clk26m",
"apll1_ck"
};
static const char * const aud_2_parents[] = {
"clk26m",
"apll2_ck"
};
static const char * const aud_engen1_parents[] = {
"clk26m",
"apll1_d2",
"apll1_d4",
"apll1_d8"
};
static const char * const aud_engen2_parents[] = {
"clk26m",
"apll2_d2",
"apll2_d4",
"apll2_d8"
};
static const char * const aud_spdif_parents[] = {
"clk26m",
"univpll_d2"
};
static const char * const disp_pwm_parents[] = {
"clk26m",
"univpll2_d4"
};
static const char * const dxcc_parents[] = {
"clk26m",
"syspll1_d2",
"syspll1_d4",
"syspll1_d8"
};
static const char * const ssusb_sys_parents[] = {
"clk26m",
"univpll3_d4",
"univpll2_d4",
"univpll3_d2"
};
static const char * const spm_parents[] = {
"clk26m",
"syspll1_d8"
};
static const char * const i2c_parents[] = {
"clk26m",
"univpll3_d4",
"univpll3_d2",
"syspll1_d8",
"syspll2_d8"
};
static const char * const pwm_parents[] = {
"clk26m",
"univpll3_d4",
"syspll1_d8"
};
static const char * const senif_parents[] = {
"clk26m",
"univpll1_d4",
"univpll1_d2",
"univpll2_d2"
};
static const char * const aes_fde_parents[] = {
"clk26m",
"msdcpll_ck",
"univpll_d3",
"univpll2_d2",
"univpll1_d2",
"syspll1_d2"
};
static const char * const dpi0_parents[] = {
"clk26m",
"lvdspll_d2",
"lvdspll_d4",
"lvdspll_d8",
"lvdspll_d16"
};
static const char * const dsp_parents[] = {
"clk26m",
"sys_26m_d2",
"dsppll_ck",
"dsppll_d2",
"dsppll_d4",
"dsppll_d8"
};
static const char * const nfi2x_parents[] = {
"clk26m",
"syspll2_d2",
"syspll_d7",
"syspll_d3",
"syspll2_d4",
"msdcpll_d2",
"univpll1_d2",
"univpll_d5"
};
static const char * const nfiecc_parents[] = {
"clk26m",
"syspll4_d2",
"univpll2_d4",
"syspll_d7",
"univpll1_d2",
"syspll1_d2",
"univpll2_d2",
"syspll_d5"
};
static const char * const ecc_parents[] = {
"clk26m",
"univpll2_d2",
"univpll1_d2",
"univpll_d3",
"syspll_d2"
};
static const char * const eth_parents[] = {
"clk26m",
"univpll2_d8",
"syspll4_d4",
"syspll1_d8",
"syspll4_d2"
};
static const char * const gcpu_parents[] = {
"clk26m",
"univpll_d3",
"univpll2_d2",
"syspll_d3",
"syspll2_d2"
};
static const char * const gcpu_cpm_parents[] = {
"clk26m",
"univpll2_d2",
"syspll2_d2"
};
static const char * const apu_parents[] = {
"clk26m",
"univpll_d2",
"apupll_ck",
"mmpll_ck",
"syspll_d3",
"univpll1_d2",
"syspll1_d2",
"syspll1_d4"
};
static const char * const mbist_diag_parents[] = {
"clk26m",
"syspll4_d4",
"univpll2_d8"
};
static const char * const apll_i2s_parents[] = {
"aud_1_sel",
"aud_2_sel"
};
static struct mtk_composite top_misc_muxes[] = {
/* CLK_CFG_11 */
MUX_GATE(CLK_TOP_MBIST_DIAG_SEL, "mbist_diag_sel", mbist_diag_parents,
0x0ec, 0, 2, 7),
/* Audio MUX */
MUX(CLK_TOP_APLL_I2S0_SEL, "apll_i2s0_sel", apll_i2s_parents, 0x0320, 11, 1),
MUX(CLK_TOP_APLL_I2S1_SEL, "apll_i2s1_sel", apll_i2s_parents, 0x0320, 12, 1),
MUX(CLK_TOP_APLL_I2S2_SEL, "apll_i2s2_sel", apll_i2s_parents, 0x0320, 13, 1),
MUX(CLK_TOP_APLL_I2S3_SEL, "apll_i2s3_sel", apll_i2s_parents, 0x0320, 14, 1),
MUX(CLK_TOP_APLL_TDMOUT_SEL, "apll_tdmout_sel", apll_i2s_parents, 0x0320, 15, 1),
MUX(CLK_TOP_APLL_TDMIN_SEL, "apll_tdmin_sel", apll_i2s_parents, 0x0320, 16, 1),
MUX(CLK_TOP_APLL_SPDIF_SEL, "apll_spdif_sel", apll_i2s_parents, 0x0320, 17, 1),
};
#define CLK_CFG_UPDATE 0x004
#define CLK_CFG_UPDATE1 0x008
static const struct mtk_mux top_muxes[] = {
/* CLK_CFG_0 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
0x040, 0x044, 0x048, 0, 2, 7, CLK_CFG_UPDATE,
0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040,
0x044, 0x048, 8, 2, 15, CLK_CFG_UPDATE, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 0x044,
0x048, 16, 3, 23, CLK_CFG_UPDATE, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x040,
0x044, 0x048, 24, 3, 31, CLK_CFG_UPDATE, 3),
/* CLK_CFG_1 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x050,
0x054, 0x058, 0, 2, 7, CLK_CFG_UPDATE, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x050,
0x054, 0x058, 8, 2, 15, CLK_CFG_UPDATE, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,
0x050, 0x054, 0x058, 16, 3, 23, CLK_CFG_UPDATE, 6),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents,
0x050, 0x054, 0x058, 24, 3, 31, CLK_CFG_UPDATE, 7),
/* CLK_CFG_2 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060,
0x064, 0x068, 0, 1, 7, CLK_CFG_UPDATE, 8),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060,
0x064, 0x068, 8, 2, 15, CLK_CFG_UPDATE, 9),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HC_SEL, "msdc50_0_hc_sel",
msdc50_0_hc_parents, 0x060, 0x064, 0x068, 16, 2,
23, CLK_CFG_UPDATE, 10, 0),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC2_2_HC_SEL, "msdc2_2_hc_sel",
msdc50_0_hc_parents, 0x060, 0x064, 0x068, 24, 2,
31, CLK_CFG_UPDATE, 11, 0),
/* CLK_CFG_3 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
msdc50_0_parents, 0x070, 0x074, 0x078, 0, 3, 7,
CLK_CFG_UPDATE, 12, 0),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_2_SEL, "msdc50_2_sel",
msdc50_2_parents, 0x070, 0x074, 0x078, 8, 3, 15,
CLK_CFG_UPDATE, 13, 0),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
msdc30_1_parents, 0x070, 0x074, 0x078, 16, 3, 23,
CLK_CFG_UPDATE, 14, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
0x070, 0x074, 0x078, 24, 2, 31, CLK_CFG_UPDATE,
15),
/* CLK_CFG_4 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
aud_intbus_parents, 0x080, 0x084, 0x088, 0, 2, 7,
CLK_CFG_UPDATE, 16),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents,
0x080, 0x084, 0x088, 8, 1, 15, CLK_CFG_UPDATE, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents,
0x080, 0x084, 0x088, 16, 1, 23, CLK_CFG_UPDATE,
18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
aud_engen1_parents, 0x080, 0x084, 0x088, 24, 2, 31,
CLK_CFG_UPDATE, 19),
/* CLK_CFG_5 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel",
aud_engen2_parents, 0x090, 0x094, 0x098, 0, 2, 7,
CLK_CFG_UPDATE, 20),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SPDIF_SEL, "aud_spdif_sel",
aud_spdif_parents, 0x090, 0x094, 0x098, 8, 1, 15,
CLK_CFG_UPDATE, 21),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
disp_pwm_parents, 0x090, 0x094, 0x098, 16, 2, 23,
CLK_CFG_UPDATE, 22),
/* CLK_CFG_6 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents,
0x0a0, 0x0a4, 0x0a8, 0, 2, 7, CLK_CFG_UPDATE,
24, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_SYS_SEL, "ssusb_sys_sel",
ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 8, 2, 15,
CLK_CFG_UPDATE, 25),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel",
ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 16, 2, 23,
CLK_CFG_UPDATE, 26),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel", spm_parents,
0x0a0, 0x0a4, 0x0a8, 24, 1, 31, CLK_CFG_UPDATE,
27, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
/* CLK_CFG_7 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x0b0,
0x0b4, 0x0b8, 0, 3, 7, CLK_CFG_UPDATE, 28),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0b0,
0x0b4, 0x0b8, 8, 2, 15, CLK_CFG_UPDATE, 29),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENIF_SEL, "senif_sel", senif_parents,
0x0b0, 0x0b4, 0x0b8, 16, 2, 23, CLK_CFG_UPDATE,
30),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE_SEL, "aes_fde_sel",
aes_fde_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31,
CLK_CFG_UPDATE, 31),
/* CLK_CFG_8 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", senif_parents,
0x0c0, 0x0c4, 0x0c8, 0, 2, 7, CLK_CFG_UPDATE1, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x0c0,
0x0c4, 0x0c8, 8, 3, 15, CLK_CFG_UPDATE1, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi0_parents, 0x0c0,
0x0c4, 0x0c8, 16, 3, 23, CLK_CFG_UPDATE1, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel", dsp_parents, 0x0c0,
0x0c4, 0x0c8, 24, 3, 31, CLK_CFG_UPDATE1, 3),
/* CLK_CFG_9 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents,
0x0d0, 0x0d4, 0x0d8, 0, 3, 7, CLK_CFG_UPDATE1, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,
0x0d0, 0x0d4, 0x0d8, 8, 3, 15, CLK_CFG_UPDATE1, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, "ecc_sel", ecc_parents, 0x0d0,
0x0d4, 0x0d8, 16, 3, 23, CLK_CFG_UPDATE1, 6),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 0x0d0,
0x0d4, 0x0d8, 24, 3, 31, CLK_CFG_UPDATE1, 7),
/* CLK_CFG_10 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0e0,
0x0e4, 0x0e8, 0, 3, 7, CLK_CFG_UPDATE1, 8),
MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_CPM_SEL, "gcpu_cpm_sel",
gcpu_cpm_parents, 0x0e0, 0x0e4, 0x0e8, 8, 2, 15,
CLK_CFG_UPDATE1, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_APU_SEL, "apu_sel", apu_parents, 0x0e0,
0x0e4, 0x0e8, 16, 3, 23, CLK_CFG_UPDATE1, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_APU_IF_SEL, "apu_if_sel", apu_parents,
0x0e0, 0x0e4, 0x0e8, 24, 3, 31, CLK_CFG_UPDATE1,
11),
};
static const char * const mcu_bus_parents[] = {
"clk26m",
"armpll",
"mainpll",
"univpll_d2"
};
static struct mtk_composite mcu_muxes[] = {
/* bus_pll_divider_cfg */
MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0,
9, 2, -1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
};
#define DIV_ADJ_F(_id, _name, _parent, _reg, _shift, _width, _flags) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.div_reg = _reg, \
.div_shift = _shift, \
.div_width = _width, \
.clk_divider_flags = _flags, \
}
static const struct mtk_clk_divider top_adj_divs[] = {
DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "apll_i2s0_sel",
0x324, 0, 8, CLK_DIVIDER_ROUND_CLOSEST),
DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "apll_i2s1_sel",
0x324, 8, 8, CLK_DIVIDER_ROUND_CLOSEST),
DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "apll_i2s2_sel",
0x324, 16, 8, CLK_DIVIDER_ROUND_CLOSEST),
DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "apll_i2s3_sel",
0x324, 24, 8, CLK_DIVIDER_ROUND_CLOSEST),
DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "apll_tdmout_sel",
0x328, 0, 8, CLK_DIVIDER_ROUND_CLOSEST),
DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll_tdmout_sel",
0x328, 8, 8, CLK_DIVIDER_ROUND_CLOSEST),
DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "apll_tdmin_sel",
0x328, 16, 8, CLK_DIVIDER_ROUND_CLOSEST),
DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll_tdmin_sel",
0x328, 24, 8, CLK_DIVIDER_ROUND_CLOSEST),
DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "apll_spdif_sel",
0x32c, 0, 8, CLK_DIVIDER_ROUND_CLOSEST),
};
static const struct mtk_gate_regs top0_cg_regs = {
.set_ofs = 0,
.clr_ofs = 0,
.sta_ofs = 0,
};
static const struct mtk_gate_regs top1_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x104,
.sta_ofs = 0x104,
};
static const struct mtk_gate_regs top2_cg_regs = {
.set_ofs = 0x320,
.clr_ofs = 0x320,
.sta_ofs = 0x320,
};
#define GATE_TOP0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top0_cg_regs, \
_shift, &mtk_clk_gate_ops_no_setclr)
#define GATE_TOP1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top1_cg_regs, \
_shift, &mtk_clk_gate_ops_no_setclr_inv)
#define GATE_TOP2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top2_cg_regs, \
_shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate top_clk_gates[] = {
GATE_TOP0(CLK_TOP_CONN_32K, "conn_32k", "clk32k", 10),
GATE_TOP0(CLK_TOP_CONN_26M, "conn_26m", "clk26m", 11),
GATE_TOP0(CLK_TOP_DSP_32K, "dsp_32k", "clk32k", 16),
GATE_TOP0(CLK_TOP_DSP_26M, "dsp_26m", "clk26m", 17),
GATE_TOP1(CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_192m_d4", 8),
GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "usb20_192m_d4", 9),
GATE_TOP1(CLK_TOP_LVDSTX_CLKDIG_EN, "lvdstx_dig_en", "lvdstx_dig_cts", 20),
GATE_TOP1(CLK_TOP_VPLL_DPIX_EN, "vpll_dpix_en", "vpll_dpix", 21),
GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, "ssusb_top_ck_en", NULL, 22),
GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, "ssusb_phy_ck_en", NULL, 23),
GATE_TOP2(CLK_TOP_AUD_I2S0_M, "aud_i2s0_m_ck", "apll12_ck_div0", 0),
GATE_TOP2(CLK_TOP_AUD_I2S1_M, "aud_i2s1_m_ck", "apll12_ck_div1", 1),
GATE_TOP2(CLK_TOP_AUD_I2S2_M, "aud_i2s2_m_ck", "apll12_ck_div2", 2),
GATE_TOP2(CLK_TOP_AUD_I2S3_M, "aud_i2s3_m_ck", "apll12_ck_div3", 3),
GATE_TOP2(CLK_TOP_AUD_TDMOUT_M, "aud_tdmout_m_ck", "apll12_ck_div4", 4),
GATE_TOP2(CLK_TOP_AUD_TDMOUT_B, "aud_tdmout_b_ck", "apll12_ck_div4b", 5),
GATE_TOP2(CLK_TOP_AUD_TDMIN_M, "aud_tdmin_m_ck", "apll12_ck_div5", 6),
GATE_TOP2(CLK_TOP_AUD_TDMIN_B, "aud_tdmin_b_ck", "apll12_ck_div5b", 7),
GATE_TOP2(CLK_TOP_AUD_SPDIF_M, "aud_spdif_m_ck", "apll12_ck_div6", 8),
};
static const struct mtk_gate_regs ifr2_cg_regs = {
.set_ofs = 0x80,
.clr_ofs = 0x84,
.sta_ofs = 0x90,
};
static const struct mtk_gate_regs ifr3_cg_regs = {
.set_ofs = 0x88,
.clr_ofs = 0x8c,
.sta_ofs = 0x94,
};
static const struct mtk_gate_regs ifr4_cg_regs = {
.set_ofs = 0xa4,
.clr_ofs = 0xa8,
.sta_ofs = 0xac,
};
static const struct mtk_gate_regs ifr5_cg_regs = {
.set_ofs = 0xc0,
.clr_ofs = 0xc4,
.sta_ofs = 0xc8,
};
static const struct mtk_gate_regs ifr6_cg_regs = {
.set_ofs = 0xd0,
.clr_ofs = 0xd4,
.sta_ofs = 0xd8,
};
#define GATE_IFRX(_id, _name, _parent, _shift, _regs) \
GATE_MTK(_id, _name, _parent, _regs, _shift, \
&mtk_clk_gate_ops_setclr)
#define GATE_IFR2(_id, _name, _parent, _shift) \
GATE_IFRX(_id, _name, _parent, _shift, &ifr2_cg_regs)
#define GATE_IFR3(_id, _name, _parent, _shift) \
GATE_IFRX(_id, _name, _parent, _shift, &ifr3_cg_regs)
#define GATE_IFR4(_id, _name, _parent, _shift) \
GATE_IFRX(_id, _name, _parent, _shift, &ifr4_cg_regs)
#define GATE_IFR5(_id, _name, _parent, _shift) \
GATE_IFRX(_id, _name, _parent, _shift, &ifr5_cg_regs)
#define GATE_IFR6(_id, _name, _parent, _shift) \
GATE_IFRX(_id, _name, _parent, _shift, &ifr6_cg_regs)
static const struct mtk_gate ifr_clks[] = {
/* IFR2 */
GATE_IFR2(CLK_IFR_PMIC_TMR, "ifr_pmic_tmr", "clk26m", 0),
GATE_IFR2(CLK_IFR_PMIC_AP, "ifr_pmic_ap", "clk26m", 1),
GATE_IFR2(CLK_IFR_PMIC_MD, "ifr_pmic_md", "clk26m", 2),
GATE_IFR2(CLK_IFR_PMIC_CONN, "ifr_pmic_conn", "clk26m", 3),
GATE_IFR2(CLK_IFR_ICUSB, "ifr_icusb", "axi_sel", 8),
GATE_IFR2(CLK_IFR_GCE, "ifr_gce", "axi_sel", 9),
GATE_IFR2(CLK_IFR_THERM, "ifr_therm", "axi_sel", 10),
GATE_IFR2(CLK_IFR_PWM_HCLK, "ifr_pwm_hclk", "axi_sel", 15),
GATE_IFR2(CLK_IFR_PWM1, "ifr_pwm1", "pwm_sel", 16),
GATE_IFR2(CLK_IFR_PWM2, "ifr_pwm2", "pwm_sel", 17),
GATE_IFR2(CLK_IFR_PWM3, "ifr_pwm3", "pwm_sel", 18),
GATE_IFR2(CLK_IFR_PWM4, "ifr_pwm4", "pwm_sel", 19),
GATE_IFR2(CLK_IFR_PWM5, "ifr_pwm5", "pwm_sel", 20),
GATE_IFR2(CLK_IFR_PWM, "ifr_pwm", "pwm_sel", 21),
GATE_IFR2(CLK_IFR_UART0, "ifr_uart0", "uart_sel", 22),
GATE_IFR2(CLK_IFR_UART1, "ifr_uart1", "uart_sel", 23),
GATE_IFR2(CLK_IFR_UART2, "ifr_uart2", "uart_sel", 24),
GATE_IFR2(CLK_IFR_DSP_UART, "ifr_dsp_uart", "uart_sel", 26),
GATE_IFR2(CLK_IFR_GCE_26M, "ifr_gce_26m", "clk26m", 27),
GATE_IFR2(CLK_IFR_CQ_DMA_FPC, "ifr_cq_dma_fpc", "axi_sel", 28),
GATE_IFR2(CLK_IFR_BTIF, "ifr_btif", "axi_sel", 31),
/* IFR3 */
GATE_IFR3(CLK_IFR_SPI0, "ifr_spi0", "spi_sel", 1),
GATE_IFR3(CLK_IFR_MSDC0_HCLK, "ifr_msdc0", "msdc50_0_hc_sel", 2),
GATE_IFR3(CLK_IFR_MSDC2_HCLK, "ifr_msdc2", "msdc2_2_hc_sel", 3),
GATE_IFR3(CLK_IFR_MSDC1_HCLK, "ifr_msdc1", "axi_sel", 4),
GATE_IFR3(CLK_IFR_DVFSRC, "ifr_dvfsrc", "clk26m", 7),
GATE_IFR3(CLK_IFR_GCPU, "ifr_gcpu", "axi_sel", 8),
GATE_IFR3(CLK_IFR_TRNG, "ifr_trng", "axi_sel", 9),
GATE_IFR3(CLK_IFR_AUXADC, "ifr_auxadc", "clk26m", 10),
GATE_IFR3(CLK_IFR_CPUM, "ifr_cpum", "clk26m", 11),
GATE_IFR3(CLK_IFR_AUXADC_MD, "ifr_auxadc_md", "clk26m", 14),
GATE_IFR3(CLK_IFR_AP_DMA, "ifr_ap_dma", "axi_sel", 18),
GATE_IFR3(CLK_IFR_DEBUGSYS, "ifr_debugsys", "axi_sel", 24),
GATE_IFR3(CLK_IFR_AUDIO, "ifr_audio", "axi_sel", 25),
/* IFR4 */
GATE_IFR4(CLK_IFR_PWM_FBCLK6, "ifr_pwm_fbclk6", "pwm_sel", 0),
GATE_IFR4(CLK_IFR_DISP_PWM, "ifr_disp_pwm", "disp_pwm_sel", 2),
GATE_IFR4(CLK_IFR_AUD_26M_BK, "ifr_aud_26m_bk", "clk26m", 4),
GATE_IFR4(CLK_IFR_CQ_DMA, "ifr_cq_dma", "axi_sel", 27),
/* IFR5 */
GATE_IFR5(CLK_IFR_MSDC0_SF, "ifr_msdc0_sf", "msdc50_0_sel", 0),
GATE_IFR5(CLK_IFR_MSDC1_SF, "ifr_msdc1_sf", "msdc50_0_sel", 1),
GATE_IFR5(CLK_IFR_MSDC2_SF, "ifr_msdc2_sf", "msdc50_0_sel", 2),
GATE_IFR5(CLK_IFR_AP_MSDC0, "ifr_ap_msdc0", "msdc50_0_sel", 7),
GATE_IFR5(CLK_IFR_MD_MSDC0, "ifr_md_msdc0", "msdc50_0_sel", 8),
GATE_IFR5(CLK_IFR_MSDC0_SRC, "ifr_msdc0_src", "msdc50_0_sel", 9),
GATE_IFR5(CLK_IFR_MSDC1_SRC, "ifr_msdc1_src", "msdc30_1_sel", 10),
GATE_IFR5(CLK_IFR_MSDC2_SRC, "ifr_msdc2_src", "msdc50_2_sel", 11),
GATE_IFR5(CLK_IFR_PWRAP_TMR, "ifr_pwrap_tmr", "clk26m", 12),
GATE_IFR5(CLK_IFR_PWRAP_SPI, "ifr_pwrap_spi", "clk26m", 13),
GATE_IFR5(CLK_IFR_PWRAP_SYS, "ifr_pwrap_sys", "clk26m", 14),
GATE_MTK_FLAGS(CLK_IFR_MCU_PM_BK, "ifr_mcu_pm_bk", NULL, &ifr5_cg_regs,
17, &mtk_clk_gate_ops_setclr, CLK_IGNORE_UNUSED),
GATE_IFR5(CLK_IFR_IRRX_26M, "ifr_irrx_26m", "clk26m", 22),
GATE_IFR5(CLK_IFR_IRRX_32K, "ifr_irrx_32k", "clk32k", 23),
GATE_IFR5(CLK_IFR_I2C0_AXI, "ifr_i2c0_axi", "i2c_sel", 24),
GATE_IFR5(CLK_IFR_I2C1_AXI, "ifr_i2c1_axi", "i2c_sel", 25),
GATE_IFR5(CLK_IFR_I2C2_AXI, "ifr_i2c2_axi", "i2c_sel", 26),
GATE_IFR5(CLK_IFR_I2C3_AXI, "ifr_i2c3_axi", "i2c_sel", 27),
GATE_IFR5(CLK_IFR_NIC_AXI, "ifr_nic_axi", "axi_sel", 28),
GATE_IFR5(CLK_IFR_NIC_SLV_AXI, "ifr_nic_slv_axi", "axi_sel", 29),
GATE_IFR5(CLK_IFR_APU_AXI, "ifr_apu_axi", "axi_sel", 30),
/* IFR6 */
GATE_IFR6(CLK_IFR_NFIECC, "ifr_nfiecc", "nfiecc_sel", 0),
GATE_IFR6(CLK_IFR_NFI1X_BK, "ifr_nfi1x_bk", "nfi2x_sel", 1),
GATE_IFR6(CLK_IFR_NFIECC_BK, "ifr_nfiecc_bk", "nfi2x_sel", 2),
GATE_IFR6(CLK_IFR_NFI_BK, "ifr_nfi_bk", "axi_sel", 3),
GATE_IFR6(CLK_IFR_MSDC2_AP_BK, "ifr_msdc2_ap_bk", "axi_sel", 4),
GATE_IFR6(CLK_IFR_MSDC2_MD_BK, "ifr_msdc2_md_bk", "axi_sel", 5),
GATE_IFR6(CLK_IFR_MSDC2_BK, "ifr_msdc2_bk", "axi_sel", 6),
GATE_IFR6(CLK_IFR_SUSB_133_BK, "ifr_susb_133_bk", "axi_sel", 7),
GATE_IFR6(CLK_IFR_SUSB_66_BK, "ifr_susb_66_bk", "axi_sel", 8),
GATE_IFR6(CLK_IFR_SSUSB_SYS, "ifr_ssusb_sys", "ssusb_sys_sel", 9),
GATE_IFR6(CLK_IFR_SSUSB_REF, "ifr_ssusb_ref", "ssusb_sys_sel", 10),
GATE_IFR6(CLK_IFR_SSUSB_XHCI, "ifr_ssusb_xhci", "ssusb_xhci_sel", 11),
};
static const struct mtk_gate_regs peri_cg_regs = {
.set_ofs = 0x20c,
.clr_ofs = 0x20c,
.sta_ofs = 0x20c,
};
static const struct mtk_gate peri_clks[] = {
GATE_MTK(CLK_PERIAXI, "periaxi", "axi_sel", &peri_cg_regs, 31,
&mtk_clk_gate_ops_no_setclr),
};
static const struct mtk_clk_desc topck_desc = {
.clks = top_clk_gates,
.num_clks = ARRAY_SIZE(top_clk_gates),
.fixed_clks = top_fixed_clks,
.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
.factor_clks = top_divs,
.num_factor_clks = ARRAY_SIZE(top_divs),
.mux_clks = top_muxes,
.num_mux_clks = ARRAY_SIZE(top_muxes),
.composite_clks = top_misc_muxes,
.num_composite_clks = ARRAY_SIZE(top_misc_muxes),
.divider_clks = top_adj_divs,
.num_divider_clks = ARRAY_SIZE(top_adj_divs),
.clk_lock = &mt8365_clk_lock,
};
static const struct mtk_clk_desc infra_desc = {
.clks = ifr_clks,
.num_clks = ARRAY_SIZE(ifr_clks),
};
static const struct mtk_clk_desc peri_desc = {
.clks = peri_clks,
.num_clks = ARRAY_SIZE(peri_clks),
};
static const struct mtk_clk_desc mcu_desc = {
.composite_clks = mcu_muxes,
.num_composite_clks = ARRAY_SIZE(mcu_muxes),
.clk_lock = &mt8365_clk_lock,
};
static const struct of_device_id of_match_clk_mt8365[] = {
{ .compatible = "mediatek,mt8365-topckgen", .data = &topck_desc },
{ .compatible = "mediatek,mt8365-infracfg", .data = &infra_desc },
{ .compatible = "mediatek,mt8365-pericfg", .data = &peri_desc },
{ .compatible = "mediatek,mt8365-mcucfg", .data = &mcu_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8365);
static struct platform_driver clk_mt8365_drv = {
.driver = {
.name = "clk-mt8365",
.of_match_table = of_match_clk_mt8365,
},
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt8365_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8365.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 Collabora Ltd.
* Author: AngeloGioacchino Del Regno <[email protected]>
*/
#include <dt-bindings/clock/mediatek,mt6795-clk.h>
#include <dt-bindings/reset/mediatek,mt6795-resets.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#include "reset.h"
#define GATE_PERI(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &peri_cg_regs, \
_shift, &mtk_clk_gate_ops_setclr)
static DEFINE_SPINLOCK(mt6795_peri_clk_lock);
static const struct mtk_gate_regs peri_cg_regs = {
.set_ofs = 0x0008,
.clr_ofs = 0x0010,
.sta_ofs = 0x0018,
};
static const char * const uart_ck_sel_parents[] = {
"clk26m",
"uart_sel",
};
static const struct mtk_composite peri_clks[] = {
MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
};
static const struct mtk_gate peri_gates[] = {
GATE_PERI(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0),
GATE_PERI(CLK_PERI_THERM, "peri_therm", "axi_sel", 1),
GATE_PERI(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2),
GATE_PERI(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3),
GATE_PERI(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4),
GATE_PERI(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5),
GATE_PERI(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6),
GATE_PERI(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7),
GATE_PERI(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8),
GATE_PERI(CLK_PERI_PWM, "peri_pwm", "axi_sel", 9),
GATE_PERI(CLK_PERI_USB0, "peri_usb0", "usb30_sel", 10),
GATE_PERI(CLK_PERI_USB1, "peri_usb1", "usb20_sel", 11),
GATE_PERI(CLK_PERI_AP_DMA, "peri_ap_dma", "axi_sel", 12),
GATE_PERI(CLK_PERI_MSDC30_0, "peri_msdc30_0", "msdc50_0_sel", 13),
GATE_PERI(CLK_PERI_MSDC30_1, "peri_msdc30_1", "msdc30_1_sel", 14),
GATE_PERI(CLK_PERI_MSDC30_2, "peri_msdc30_2", "msdc30_2_sel", 15),
GATE_PERI(CLK_PERI_MSDC30_3, "peri_msdc30_3", "msdc30_3_sel", 16),
GATE_PERI(CLK_PERI_NLI_ARB, "peri_nli_arb", "axi_sel", 17),
GATE_PERI(CLK_PERI_IRDA, "peri_irda", "irda_sel", 18),
GATE_PERI(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19),
GATE_PERI(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20),
GATE_PERI(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21),
GATE_PERI(CLK_PERI_UART3, "peri_uart3", "axi_sel", 22),
GATE_PERI(CLK_PERI_I2C0, "peri_i2c0", "axi_sel", 23),
GATE_PERI(CLK_PERI_I2C1, "peri_i2c1", "axi_sel", 24),
GATE_PERI(CLK_PERI_I2C2, "peri_i2c2", "axi_sel", 25),
GATE_PERI(CLK_PERI_I2C3, "peri_i2c3", "axi_sel", 26),
GATE_PERI(CLK_PERI_I2C4, "peri_i2c4", "axi_sel", 27),
GATE_PERI(CLK_PERI_AUXADC, "peri_auxadc", "clk26m", 28),
GATE_PERI(CLK_PERI_SPI0, "peri_spi0", "spi_sel", 29),
};
static u16 peri_rst_ofs[] = { 0x0 };
static u16 peri_idx_map[] = {
[MT6795_PERI_NFI_SW_RST] = 14,
[MT6795_PERI_THERM_SW_RST] = 16,
[MT6795_PERI_MSDC1_SW_RST] = 20,
};
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SIMPLE,
.rst_bank_ofs = peri_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(peri_rst_ofs),
.rst_idx_map = peri_idx_map,
.rst_idx_map_nr = ARRAY_SIZE(peri_idx_map),
};
static const struct of_device_id of_match_clk_mt6795_pericfg[] = {
{ .compatible = "mediatek,mt6795-pericfg" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_pericfg);
static int clk_mt6795_pericfg_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
void __iomem *base;
int ret;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
if (!clk_data)
return -ENOMEM;
ret = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
if (ret)
goto free_clk_data;
ret = mtk_clk_register_gates(&pdev->dev, node, peri_gates,
ARRAY_SIZE(peri_gates), clk_data);
if (ret)
goto free_clk_data;
ret = mtk_clk_register_composites(&pdev->dev, peri_clks,
ARRAY_SIZE(peri_clks), base,
&mt6795_peri_clk_lock, clk_data);
if (ret)
goto unregister_gates;
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (ret)
goto unregister_composites;
return 0;
unregister_composites:
mtk_clk_unregister_composites(peri_clks, ARRAY_SIZE(peri_clks), clk_data);
unregister_gates:
mtk_clk_unregister_gates(peri_gates, ARRAY_SIZE(peri_gates), clk_data);
free_clk_data:
mtk_free_clk_data(clk_data);
return ret;
}
static void clk_mt6795_pericfg_remove(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
of_clk_del_provider(node);
mtk_clk_unregister_composites(peri_clks, ARRAY_SIZE(peri_clks), clk_data);
mtk_clk_unregister_gates(peri_gates, ARRAY_SIZE(peri_gates), clk_data);
mtk_free_clk_data(clk_data);
}
static struct platform_driver clk_mt6795_pericfg_drv = {
.driver = {
.name = "clk-mt6795-pericfg",
.of_match_table = of_match_clk_mt6795_pericfg,
},
.probe = clk_mt6795_pericfg_probe,
.remove_new = clk_mt6795_pericfg_remove,
};
module_platform_driver(clk_mt6795_pericfg_drv);
MODULE_DESCRIPTION("MediaTek MT6795 pericfg clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6795-pericfg.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Garmin Chang <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs wpe_top_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x0,
.sta_ofs = 0x0,
};
static const struct mtk_gate_regs wpe_vpp0_0_cg_regs = {
.set_ofs = 0x58,
.clr_ofs = 0x58,
.sta_ofs = 0x58,
};
static const struct mtk_gate_regs wpe_vpp0_1_cg_regs = {
.set_ofs = 0x5c,
.clr_ofs = 0x5c,
.sta_ofs = 0x5c,
};
#define GATE_WPE_TOP(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &wpe_top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
#define GATE_WPE_VPP0_0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &wpe_vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
#define GATE_WPE_VPP0_1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &wpe_vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate wpe_top_clks[] = {
GATE_WPE_TOP(CLK_WPE_TOP_WPE_VPP0, "wpe_wpe_vpp0", "top_wpe_vpp", 16),
GATE_WPE_TOP(CLK_WPE_TOP_SMI_LARB7, "wpe_smi_larb7", "top_wpe_vpp", 18),
GATE_WPE_TOP(CLK_WPE_TOP_WPESYS_EVENT_TX, "wpe_wpesys_event_tx", "top_wpe_vpp", 20),
GATE_WPE_TOP(CLK_WPE_TOP_SMI_LARB7_PCLK_EN, "wpe_smi_larb7_p_en", "top_wpe_vpp", 24),
};
static const struct mtk_gate wpe_vpp0_clks[] = {
/* WPE_VPP00 */
GATE_WPE_VPP0_0(CLK_WPE_VPP0_VGEN, "wpe_vpp0_vgen", "top_img", 0),
GATE_WPE_VPP0_0(CLK_WPE_VPP0_EXT, "wpe_vpp0_ext", "top_img", 1),
GATE_WPE_VPP0_0(CLK_WPE_VPP0_VFC, "wpe_vpp0_vfc", "top_img", 2),
GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH0_TOP, "wpe_vpp0_cach0_top", "top_img", 3),
GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH0_DMA, "wpe_vpp0_cach0_dma", "top_img", 4),
GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH1_TOP, "wpe_vpp0_cach1_top", "top_img", 5),
GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH1_DMA, "wpe_vpp0_cach1_dma", "top_img", 6),
GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH2_TOP, "wpe_vpp0_cach2_top", "top_img", 7),
GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH2_DMA, "wpe_vpp0_cach2_dma", "top_img", 8),
GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH3_TOP, "wpe_vpp0_cach3_top", "top_img", 9),
GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH3_DMA, "wpe_vpp0_cach3_dma", "top_img", 10),
GATE_WPE_VPP0_0(CLK_WPE_VPP0_PSP, "wpe_vpp0_psp", "top_img", 11),
GATE_WPE_VPP0_0(CLK_WPE_VPP0_PSP2, "wpe_vpp0_psp2", "top_img", 12),
GATE_WPE_VPP0_0(CLK_WPE_VPP0_SYNC, "wpe_vpp0_sync", "top_img", 13),
GATE_WPE_VPP0_0(CLK_WPE_VPP0_C24, "wpe_vpp0_c24", "top_img", 14),
GATE_WPE_VPP0_0(CLK_WPE_VPP0_MDP_CROP, "wpe_vpp0_mdp_crop", "top_img", 15),
GATE_WPE_VPP0_0(CLK_WPE_VPP0_ISP_CROP, "wpe_vpp0_isp_crop", "top_img", 16),
GATE_WPE_VPP0_0(CLK_WPE_VPP0_TOP, "wpe_vpp0_top", "top_img", 17),
/* WPE_VPP0_1 */
GATE_WPE_VPP0_1(CLK_WPE_VPP0_VECI, "wpe_vpp0_veci", "top_img", 0),
GATE_WPE_VPP0_1(CLK_WPE_VPP0_VEC2I, "wpe_vpp0_vec2i", "top_img", 1),
GATE_WPE_VPP0_1(CLK_WPE_VPP0_VEC3I, "wpe_vpp0_vec3i", "top_img", 2),
GATE_WPE_VPP0_1(CLK_WPE_VPP0_WPEO, "wpe_vpp0_wpeo", "top_img", 3),
GATE_WPE_VPP0_1(CLK_WPE_VPP0_MSKO, "wpe_vpp0_msko", "top_img", 4),
};
static const struct mtk_clk_desc wpe_top_desc = {
.clks = wpe_top_clks,
.num_clks = ARRAY_SIZE(wpe_top_clks),
};
static const struct mtk_clk_desc wpe_vpp0_desc = {
.clks = wpe_vpp0_clks,
.num_clks = ARRAY_SIZE(wpe_vpp0_clks),
};
static const struct of_device_id of_match_clk_mt8188_wpe[] = {
{ .compatible = "mediatek,mt8188-wpesys", .data = &wpe_top_desc },
{ .compatible = "mediatek,mt8188-wpesys-vpp0", .data = &wpe_vpp0_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_wpe);
static struct platform_driver clk_mt8188_wpe_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8188-wpe",
.of_match_table = of_match_clk_mt8188_wpe,
},
};
module_platform_driver(clk_mt8188_wpe_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8188-wpe.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 MediaTek Inc.
* Author: Sam Shih <[email protected]>
* Author: Wenzhen Yu <[email protected]>
* Author: Jianhui Zhao <[email protected]>
* Author: Daniel Golle <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mediatek,mt7981-clk.h>
static const struct mtk_gate_regs sgmii0_cg_regs = {
.set_ofs = 0xE4,
.clr_ofs = 0xE4,
.sta_ofs = 0xE4,
};
#define GATE_SGMII0(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &sgmii0_cg_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
}
static const struct mtk_gate sgmii0_clks[] __initconst = {
GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2),
GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3),
GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4),
GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5),
};
static const struct mtk_gate_regs sgmii1_cg_regs = {
.set_ofs = 0xE4,
.clr_ofs = 0xE4,
.sta_ofs = 0xE4,
};
#define GATE_SGMII1(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &sgmii1_cg_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
}
static const struct mtk_gate sgmii1_clks[] __initconst = {
GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2),
GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3),
GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4),
GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5),
};
static const struct mtk_gate_regs eth_cg_regs = {
.set_ofs = 0x30,
.clr_ofs = 0x30,
.sta_ofs = 0x30,
};
#define GATE_ETH(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = ð_cg_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
}
static const struct mtk_gate eth_clks[] __initconst = {
GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6),
GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7),
GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8),
GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15),
};
static const struct mtk_clk_desc eth_desc = {
.clks = eth_clks,
.num_clks = ARRAY_SIZE(eth_clks),
};
static const struct mtk_clk_desc sgmii0_desc = {
.clks = sgmii0_clks,
.num_clks = ARRAY_SIZE(sgmii0_clks),
};
static const struct mtk_clk_desc sgmii1_desc = {
.clks = sgmii1_clks,
.num_clks = ARRAY_SIZE(sgmii1_clks),
};
static const struct of_device_id of_match_clk_mt7981_eth[] = {
{ .compatible = "mediatek,mt7981-ethsys", .data = ð_desc },
{ .compatible = "mediatek,mt7981-sgmiisys_0", .data = &sgmii0_desc },
{ .compatible = "mediatek,mt7981-sgmiisys_1", .data = &sgmii1_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7981_eth);
static struct platform_driver clk_mt7981_eth_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7981-eth",
.of_match_table = of_match_clk_mt7981_eth,
},
};
module_platform_driver(clk_mt7981_eth_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt7981-eth.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs peri_ao_cg_regs = {
.set_ofs = 0x10,
.clr_ofs = 0x14,
.sta_ofs = 0x18,
};
#define GATE_PERI_AO(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &peri_ao_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate peri_ao_clks[] = {
GATE_PERI_AO(CLK_PERI_AO_ETHERNET, "peri_ao_ethernet", "top_axi", 0),
GATE_PERI_AO(CLK_PERI_AO_ETHERNET_BUS, "peri_ao_ethernet_bus", "top_axi", 1),
GATE_PERI_AO(CLK_PERI_AO_FLASHIF_BUS, "peri_ao_flashif_bus", "top_axi", 3),
GATE_PERI_AO(CLK_PERI_AO_FLASHIF_FLASH, "peri_ao_flashif_flash", "top_spinor", 5),
GATE_PERI_AO(CLK_PERI_AO_SSUSB_1P_BUS, "peri_ao_ssusb_1p_bus", "top_usb_top_1p", 7),
GATE_PERI_AO(CLK_PERI_AO_SSUSB_1P_XHCI, "peri_ao_ssusb_1p_xhci", "top_ssusb_xhci_1p", 8),
GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_BUS, "peri_ao_ssusb_2p_bus", "top_usb_top_2p", 9),
GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_XHCI, "peri_ao_ssusb_2p_xhci", "top_ssusb_xhci_2p", 10),
GATE_PERI_AO(CLK_PERI_AO_SSUSB_3P_BUS, "peri_ao_ssusb_3p_bus", "top_usb_top_3p", 11),
GATE_PERI_AO(CLK_PERI_AO_SSUSB_3P_XHCI, "peri_ao_ssusb_3p_xhci", "top_ssusb_xhci_3p", 12),
GATE_PERI_AO(CLK_PERI_AO_SPINFI, "peri_ao_spinfi", "top_spinfi_bclk", 15),
GATE_PERI_AO(CLK_PERI_AO_ETHERNET_MAC, "peri_ao_ethernet_mac", "top_snps_eth_250m", 16),
GATE_PERI_AO(CLK_PERI_AO_NFI_H, "peri_ao_nfi_h", "top_axi", 19),
GATE_PERI_AO(CLK_PERI_AO_FNFI1X, "peri_ao_fnfi1x", "top_nfi1x", 20),
GATE_PERI_AO(CLK_PERI_AO_PCIE_P0_MEM, "peri_ao_pcie_p0_mem", "mem_466m", 24),
GATE_PERI_AO(CLK_PERI_AO_PCIE_P1_MEM, "peri_ao_pcie_p1_mem", "mem_466m", 25),
};
static const struct mtk_clk_desc peri_ao_desc = {
.clks = peri_ao_clks,
.num_clks = ARRAY_SIZE(peri_ao_clks),
};
static const struct of_device_id of_match_clk_mt8195_peri_ao[] = {
{
.compatible = "mediatek,mt8195-pericfg_ao",
.data = &peri_ao_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_peri_ao);
static struct platform_driver clk_mt8195_peri_ao_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8195-peri_ao",
.of_match_table = of_match_clk_mt8195_peri_ao,
},
};
module_platform_driver(clk_mt8195_peri_ao_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8195-peri_ao.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs cam_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_CAM(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate cam_clks[] = {
GATE_CAM(CLK_CAM_LARB13, "cam_larb13", "top_cam", 0),
GATE_CAM(CLK_CAM_LARB14, "cam_larb14", "top_cam", 1),
GATE_CAM(CLK_CAM_MAIN_CAM, "cam_main_cam", "top_cam", 3),
GATE_CAM(CLK_CAM_MAIN_CAMTG, "cam_main_camtg", "top_cam", 4),
GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "top_cam", 5),
GATE_CAM(CLK_CAM_GCAMSVA, "cam_gcamsva", "top_cam", 6),
GATE_CAM(CLK_CAM_GCAMSVB, "cam_gcamsvb", "top_cam", 7),
GATE_CAM(CLK_CAM_GCAMSVC, "cam_gcamsvc", "top_cam", 8),
GATE_CAM(CLK_CAM_SCAMSA, "cam_scamsa", "top_cam", 9),
GATE_CAM(CLK_CAM_SCAMSB, "cam_scamsb", "top_cam", 10),
GATE_CAM(CLK_CAM_CAMSV_TOP, "cam_camsv_top", "top_cam", 11),
GATE_CAM(CLK_CAM_CAMSV_CQ, "cam_camsv_cq", "top_cam", 12),
GATE_CAM(CLK_CAM_ADL, "cam_adl", "top_cam", 16),
GATE_CAM(CLK_CAM_ASG, "cam_asg", "top_cam", 17),
GATE_CAM(CLK_CAM_PDA, "cam_pda", "top_cam", 18),
GATE_CAM(CLK_CAM_FAKE_ENG, "cam_fake_eng", "top_cam", 19),
GATE_CAM(CLK_CAM_MAIN_MRAW0, "cam_main_mraw0", "top_cam", 20),
GATE_CAM(CLK_CAM_MAIN_MRAW1, "cam_main_mraw1", "top_cam", 21),
GATE_CAM(CLK_CAM_MAIN_MRAW2, "cam_main_mraw2", "top_cam", 22),
GATE_CAM(CLK_CAM_MAIN_MRAW3, "cam_main_mraw3", "top_cam", 23),
GATE_CAM(CLK_CAM_CAM2MM0_GALS, "cam_cam2mm0_gals", "top_cam", 24),
GATE_CAM(CLK_CAM_CAM2MM1_GALS, "cam_cam2mm1_gals", "top_cam", 25),
GATE_CAM(CLK_CAM_CAM2SYS_GALS, "cam_cam2sys_gals", "top_cam", 26),
};
static const struct mtk_gate cam_mraw_clks[] = {
GATE_CAM(CLK_CAM_MRAW_LARBX, "cam_mraw_larbx", "top_cam", 0),
GATE_CAM(CLK_CAM_MRAW_CAMTG, "cam_mraw_camtg", "top_cam", 2),
GATE_CAM(CLK_CAM_MRAW_MRAW0, "cam_mraw_mraw0", "top_cam", 3),
GATE_CAM(CLK_CAM_MRAW_MRAW1, "cam_mraw_mraw1", "top_cam", 4),
GATE_CAM(CLK_CAM_MRAW_MRAW2, "cam_mraw_mraw2", "top_cam", 5),
GATE_CAM(CLK_CAM_MRAW_MRAW3, "cam_mraw_mraw3", "top_cam", 6),
};
static const struct mtk_gate cam_rawa_clks[] = {
GATE_CAM(CLK_CAM_RAWA_LARBX, "cam_rawa_larbx", "top_cam", 0),
GATE_CAM(CLK_CAM_RAWA_CAM, "cam_rawa_cam", "top_cam", 1),
GATE_CAM(CLK_CAM_RAWA_CAMTG, "cam_rawa_camtg", "top_cam", 2),
};
static const struct mtk_gate cam_rawb_clks[] = {
GATE_CAM(CLK_CAM_RAWB_LARBX, "cam_rawb_larbx", "top_cam", 0),
GATE_CAM(CLK_CAM_RAWB_CAM, "cam_rawb_cam", "top_cam", 1),
GATE_CAM(CLK_CAM_RAWB_CAMTG, "cam_rawb_camtg", "top_cam", 2),
};
static const struct mtk_gate cam_yuva_clks[] = {
GATE_CAM(CLK_CAM_YUVA_LARBX, "cam_yuva_larbx", "top_cam", 0),
GATE_CAM(CLK_CAM_YUVA_CAM, "cam_yuva_cam", "top_cam", 1),
GATE_CAM(CLK_CAM_YUVA_CAMTG, "cam_yuva_camtg", "top_cam", 2),
};
static const struct mtk_gate cam_yuvb_clks[] = {
GATE_CAM(CLK_CAM_YUVB_LARBX, "cam_yuvb_larbx", "top_cam", 0),
GATE_CAM(CLK_CAM_YUVB_CAM, "cam_yuvb_cam", "top_cam", 1),
GATE_CAM(CLK_CAM_YUVB_CAMTG, "cam_yuvb_camtg", "top_cam", 2),
};
static const struct mtk_clk_desc cam_desc = {
.clks = cam_clks,
.num_clks = ARRAY_SIZE(cam_clks),
};
static const struct mtk_clk_desc cam_mraw_desc = {
.clks = cam_mraw_clks,
.num_clks = ARRAY_SIZE(cam_mraw_clks),
};
static const struct mtk_clk_desc cam_rawa_desc = {
.clks = cam_rawa_clks,
.num_clks = ARRAY_SIZE(cam_rawa_clks),
};
static const struct mtk_clk_desc cam_rawb_desc = {
.clks = cam_rawb_clks,
.num_clks = ARRAY_SIZE(cam_rawb_clks),
};
static const struct mtk_clk_desc cam_yuva_desc = {
.clks = cam_yuva_clks,
.num_clks = ARRAY_SIZE(cam_yuva_clks),
};
static const struct mtk_clk_desc cam_yuvb_desc = {
.clks = cam_yuvb_clks,
.num_clks = ARRAY_SIZE(cam_yuvb_clks),
};
static const struct of_device_id of_match_clk_mt8195_cam[] = {
{
.compatible = "mediatek,mt8195-camsys",
.data = &cam_desc,
}, {
.compatible = "mediatek,mt8195-camsys_mraw",
.data = &cam_mraw_desc,
}, {
.compatible = "mediatek,mt8195-camsys_rawa",
.data = &cam_rawa_desc,
}, {
.compatible = "mediatek,mt8195-camsys_rawb",
.data = &cam_rawb_desc,
}, {
.compatible = "mediatek,mt8195-camsys_yuva",
.data = &cam_yuva_desc,
}, {
.compatible = "mediatek,mt8195-camsys_yuvb",
.data = &cam_yuvb_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_cam);
static struct platform_driver clk_mt8195_cam_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8195-cam",
.of_match_table = of_match_clk_mt8195_cam,
},
};
module_platform_driver(clk_mt8195_cam_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8195-cam.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 MediaTek Inc.
* Author: Owen Chen <[email protected]>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/compiler_types.h>
#include <linux/container_of.h>
#include <linux/err.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
#include "clk-mux.h"
struct mtk_clk_mux {
struct clk_hw hw;
struct regmap *regmap;
const struct mtk_mux *data;
spinlock_t *lock;
bool reparent;
};
static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw)
{
return container_of(hw, struct mtk_clk_mux, hw);
}
static int mtk_clk_mux_enable_setclr(struct clk_hw *hw)
{
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
unsigned long flags = 0;
if (mux->lock)
spin_lock_irqsave(mux->lock, flags);
else
__acquire(mux->lock);
regmap_write(mux->regmap, mux->data->clr_ofs,
BIT(mux->data->gate_shift));
/*
* If the parent has been changed when the clock was disabled, it will
* not be effective yet. Set the update bit to ensure the mux gets
* updated.
*/
if (mux->reparent && mux->data->upd_shift >= 0) {
regmap_write(mux->regmap, mux->data->upd_ofs,
BIT(mux->data->upd_shift));
mux->reparent = false;
}
if (mux->lock)
spin_unlock_irqrestore(mux->lock, flags);
else
__release(mux->lock);
return 0;
}
static void mtk_clk_mux_disable_setclr(struct clk_hw *hw)
{
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
regmap_write(mux->regmap, mux->data->set_ofs,
BIT(mux->data->gate_shift));
}
static int mtk_clk_mux_is_enabled(struct clk_hw *hw)
{
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
u32 val;
regmap_read(mux->regmap, mux->data->mux_ofs, &val);
return (val & BIT(mux->data->gate_shift)) == 0;
}
static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)
{
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
u32 mask = GENMASK(mux->data->mux_width - 1, 0);
u32 val;
regmap_read(mux->regmap, mux->data->mux_ofs, &val);
val = (val >> mux->data->mux_shift) & mask;
return val;
}
static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index)
{
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
u32 mask = GENMASK(mux->data->mux_width - 1, 0);
u32 val, orig;
unsigned long flags = 0;
if (mux->lock)
spin_lock_irqsave(mux->lock, flags);
else
__acquire(mux->lock);
regmap_read(mux->regmap, mux->data->mux_ofs, &orig);
val = (orig & ~(mask << mux->data->mux_shift))
| (index << mux->data->mux_shift);
if (val != orig) {
regmap_write(mux->regmap, mux->data->clr_ofs,
mask << mux->data->mux_shift);
regmap_write(mux->regmap, mux->data->set_ofs,
index << mux->data->mux_shift);
if (mux->data->upd_shift >= 0) {
regmap_write(mux->regmap, mux->data->upd_ofs,
BIT(mux->data->upd_shift));
mux->reparent = true;
}
}
if (mux->lock)
spin_unlock_irqrestore(mux->lock, flags);
else
__release(mux->lock);
return 0;
}
static int mtk_clk_mux_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
return clk_mux_determine_rate_flags(hw, req, mux->data->flags);
}
const struct clk_ops mtk_mux_clr_set_upd_ops = {
.get_parent = mtk_clk_mux_get_parent,
.set_parent = mtk_clk_mux_set_parent_setclr_lock,
.determine_rate = mtk_clk_mux_determine_rate,
};
EXPORT_SYMBOL_GPL(mtk_mux_clr_set_upd_ops);
const struct clk_ops mtk_mux_gate_clr_set_upd_ops = {
.enable = mtk_clk_mux_enable_setclr,
.disable = mtk_clk_mux_disable_setclr,
.is_enabled = mtk_clk_mux_is_enabled,
.get_parent = mtk_clk_mux_get_parent,
.set_parent = mtk_clk_mux_set_parent_setclr_lock,
.determine_rate = mtk_clk_mux_determine_rate,
};
EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops);
static struct clk_hw *mtk_clk_register_mux(struct device *dev,
const struct mtk_mux *mux,
struct regmap *regmap,
spinlock_t *lock)
{
struct mtk_clk_mux *clk_mux;
struct clk_init_data init = {};
int ret;
clk_mux = kzalloc(sizeof(*clk_mux), GFP_KERNEL);
if (!clk_mux)
return ERR_PTR(-ENOMEM);
init.name = mux->name;
init.flags = mux->flags;
init.parent_names = mux->parent_names;
init.num_parents = mux->num_parents;
init.ops = mux->ops;
clk_mux->regmap = regmap;
clk_mux->data = mux;
clk_mux->lock = lock;
clk_mux->hw.init = &init;
ret = clk_hw_register(dev, &clk_mux->hw);
if (ret) {
kfree(clk_mux);
return ERR_PTR(ret);
}
return &clk_mux->hw;
}
static void mtk_clk_unregister_mux(struct clk_hw *hw)
{
struct mtk_clk_mux *mux;
if (!hw)
return;
mux = to_mtk_clk_mux(hw);
clk_hw_unregister(hw);
kfree(mux);
}
int mtk_clk_register_muxes(struct device *dev,
const struct mtk_mux *muxes,
int num, struct device_node *node,
spinlock_t *lock,
struct clk_hw_onecell_data *clk_data)
{
struct regmap *regmap;
struct clk_hw *hw;
int i;
regmap = device_node_to_regmap(node);
if (IS_ERR(regmap)) {
pr_err("Cannot find regmap for %pOF: %pe\n", node, regmap);
return PTR_ERR(regmap);
}
for (i = 0; i < num; i++) {
const struct mtk_mux *mux = &muxes[i];
if (!IS_ERR_OR_NULL(clk_data->hws[mux->id])) {
pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",
node, mux->id);
continue;
}
hw = mtk_clk_register_mux(dev, mux, regmap, lock);
if (IS_ERR(hw)) {
pr_err("Failed to register clk %s: %pe\n", mux->name,
hw);
goto err;
}
clk_data->hws[mux->id] = hw;
}
return 0;
err:
while (--i >= 0) {
const struct mtk_mux *mux = &muxes[i];
if (IS_ERR_OR_NULL(clk_data->hws[mux->id]))
continue;
mtk_clk_unregister_mux(clk_data->hws[mux->id]);
clk_data->hws[mux->id] = ERR_PTR(-ENOENT);
}
return PTR_ERR(hw);
}
EXPORT_SYMBOL_GPL(mtk_clk_register_muxes);
void mtk_clk_unregister_muxes(const struct mtk_mux *muxes, int num,
struct clk_hw_onecell_data *clk_data)
{
int i;
if (!clk_data)
return;
for (i = num; i > 0; i--) {
const struct mtk_mux *mux = &muxes[i - 1];
if (IS_ERR_OR_NULL(clk_data->hws[mux->id]))
continue;
mtk_clk_unregister_mux(clk_data->hws[mux->id]);
clk_data->hws[mux->id] = ERR_PTR(-ENOENT);
}
}
EXPORT_SYMBOL_GPL(mtk_clk_unregister_muxes);
/*
* This clock notifier is called when the frequency of the parent
* PLL clock is to be changed. The idea is to switch the parent to a
* stable clock, such as the main oscillator, while the PLL frequency
* stabilizes.
*/
static int mtk_clk_mux_notifier_cb(struct notifier_block *nb,
unsigned long event, void *_data)
{
struct clk_notifier_data *data = _data;
struct clk_hw *hw = __clk_get_hw(data->clk);
struct mtk_mux_nb *mux_nb = to_mtk_mux_nb(nb);
int ret = 0;
switch (event) {
case PRE_RATE_CHANGE:
mux_nb->original_index = mux_nb->ops->get_parent(hw);
ret = mux_nb->ops->set_parent(hw, mux_nb->bypass_index);
break;
case POST_RATE_CHANGE:
case ABORT_RATE_CHANGE:
ret = mux_nb->ops->set_parent(hw, mux_nb->original_index);
break;
}
return notifier_from_errno(ret);
}
int devm_mtk_clk_mux_notifier_register(struct device *dev, struct clk *clk,
struct mtk_mux_nb *mux_nb)
{
mux_nb->nb.notifier_call = mtk_clk_mux_notifier_cb;
return devm_clk_notifier_register(dev, clk, &mux_nb->nb);
}
EXPORT_SYMBOL_GPL(devm_mtk_clk_mux_notifier_register);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mux.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016 MediaTek Inc.
* Author: Kevin Chen <[email protected]>
*/
#include <linux/of.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-pll.h"
#include <dt-bindings/clock/mt6797-clk.h>
/*
* For some clocks, we don't care what their actual rates are. And these
* clocks may change their rate on different products or different scenarios.
* So we model these clocks' rate as 0, to denote it's not an actual rate.
*/
static DEFINE_SPINLOCK(mt6797_clk_lock);
static const struct mtk_fixed_factor top_fixed_divs[] = {
FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1),
FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
FACTOR(CLK_TOP_SYSPLL_D3_D3, "syspll_d3_d3", "syspll_d3", 1, 3),
FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 1),
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
FACTOR(CLK_TOP_SSUSB_PHY_48M_CK, "ssusb_phy_48m_ck", "univpll", 1, 1),
FACTOR(CLK_TOP_USB_PHY48M_CK, "usb_phy48m_ck", "univpll", 1, 1),
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 2),
FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 4),
FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
FACTOR(CLK_TOP_ULPOSC_CK_ORG, "ulposc_ck_org", "ulposc", 1, 1),
FACTOR(CLK_TOP_ULPOSC_CK, "ulposc_ck", "ulposc_ck_org", 1, 3),
FACTOR(CLK_TOP_ULPOSC_D2, "ulposc_d2", "ulposc_ck", 1, 2),
FACTOR(CLK_TOP_ULPOSC_D3, "ulposc_d3", "ulposc_ck", 1, 4),
FACTOR(CLK_TOP_ULPOSC_D4, "ulposc_d4", "ulposc_ck", 1, 8),
FACTOR(CLK_TOP_ULPOSC_D8, "ulposc_d8", "ulposc_ck", 1, 10),
FACTOR(CLK_TOP_ULPOSC_D10, "ulposc_d10", "ulposc_ck_org", 1, 1),
FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
FACTOR(CLK_TOP_MFGPLL_D2, "mfgpll_d2", "mfgpll_ck", 1, 2),
FACTOR(CLK_TOP_IMGPLL_CK, "imgpll_ck", "imgpll", 1, 1),
FACTOR(CLK_TOP_IMGPLL_D2, "imgpll_d2", "imgpll_ck", 1, 2),
FACTOR(CLK_TOP_IMGPLL_D4, "imgpll_d4", "imgpll_ck", 1, 4),
FACTOR(CLK_TOP_CODECPLL_CK, "codecpll_ck", "codecpll", 1, 1),
FACTOR(CLK_TOP_CODECPLL_D2, "codecpll_d2", "codecpll_ck", 1, 2),
FACTOR(CLK_TOP_VDECPLL_CK, "vdecpll_ck", "vdecpll", 1, 1),
FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4),
FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8),
FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_ck", 1, 16),
FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, 4),
FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll_ck", 1, 8),
};
static const char * const axi_parents[] = {
"clk26m",
"syspll_d7",
"ulposc_axi_ck_mux",
};
static const char * const ulposc_axi_ck_mux_parents[] = {
"syspll1_d4",
"ulposc_axi_ck_mux_pre",
};
static const char * const ulposc_axi_ck_mux_pre_parents[] = {
"ulposc_d2",
"ulposc_d3",
};
static const char * const ddrphycfg_parents[] = {
"clk26m",
"syspll3_d2",
"syspll2_d4",
"syspll1_d8",
};
static const char * const mm_parents[] = {
"clk26m",
"imgpll_ck",
"univpll1_d2",
"syspll1_d2",
};
static const char * const pwm_parents[] = {
"clk26m",
"univpll2_d4",
"ulposc_d2",
"ulposc_d3",
"ulposc_d8",
"ulposc_d10",
"ulposc_d4",
};
static const char * const vdec_parents[] = {
"clk26m",
"vdecpll_ck",
"imgpll_ck",
"syspll_d3",
"univpll_d5",
"clk26m",
"clk26m",
};
static const char * const venc_parents[] = {
"clk26m",
"codecpll_ck",
"syspll_d3",
};
static const char * const mfg_parents[] = {
"clk26m",
"mfgpll_ck",
"syspll_d3",
"univpll_d3",
};
static const char * const camtg[] = {
"clk26m",
"univpll_d26",
"univpll2_d2",
};
static const char * const uart_parents[] = {
"clk26m",
"univpll2_d8",
};
static const char * const spi_parents[] = {
"clk26m",
"syspll3_d2",
"syspll2_d4",
"ulposc_spi_ck_mux",
};
static const char * const ulposc_spi_ck_mux_parents[] = {
"ulposc_d2",
"ulposc_d3",
};
static const char * const usb20_parents[] = {
"clk26m",
"univpll1_d8",
"syspll4_d2",
};
static const char * const msdc50_0_hclk_parents[] = {
"clk26m",
"syspll1_d2",
"syspll2_d2",
"syspll4_d2",
};
static const char * const msdc50_0_parents[] = {
"clk26m",
"msdcpll",
"syspll_d3",
"univpll1_d4",
"syspll2_d2",
"syspll_d7",
"msdcpll_d2",
"univpll1_d2",
"univpll_d3",
};
static const char * const msdc30_1_parents[] = {
"clk26m",
"univpll2_d2",
"msdcpll_d2",
"univpll1_d4",
"syspll2_d2",
"syspll_d7",
"univpll_d7",
};
static const char * const msdc30_2_parents[] = {
"clk26m",
"univpll2_d8",
"syspll2_d8",
"syspll1_d8",
"msdcpll_d8",
"syspll3_d4",
"univpll_d26",
};
static const char * const audio_parents[] = {
"clk26m",
"syspll3_d4",
"syspll4_d4",
"syspll1_d16",
};
static const char * const aud_intbus_parents[] = {
"clk26m",
"syspll1_d4",
"syspll4_d2",
};
static const char * const pmicspi_parents[] = {
"clk26m",
"univpll_d26",
"syspll3_d4",
"syspll1_d8",
"ulposc_d4",
"ulposc_d8",
"syspll2_d8",
};
static const char * const scp_parents[] = {
"clk26m",
"syspll_d3",
"ulposc_ck",
"univpll_d5",
};
static const char * const atb_parents[] = {
"clk26m",
"syspll1_d2",
"syspll_d5",
};
static const char * const mjc_parents[] = {
"clk26m",
"imgpll_ck",
"univpll_d5",
"syspll1_d2",
};
static const char * const dpi0_parents[] = {
"clk26m",
"tvdpll_d2",
"tvdpll_d4",
"tvdpll_d8",
"tvdpll_d16",
"clk26m",
"clk26m",
};
static const char * const aud_1_parents[] = {
"clk26m",
"apll1_ck",
};
static const char * const aud_2_parents[] = {
"clk26m",
"apll2_ck",
};
static const char * const ssusb_top_sys_parents[] = {
"clk26m",
"univpll3_d2",
};
static const char * const spm_parents[] = {
"clk26m",
"syspll1_d8",
};
static const char * const bsi_spi_parents[] = {
"clk26m",
"syspll_d3_d3",
"syspll1_d4",
"syspll_d7",
};
static const char * const audio_h_parents[] = {
"clk26m",
"apll2_ck",
"apll1_ck",
"univpll_d7",
};
static const char * const mfg_52m_parents[] = {
"clk26m",
"univpll2_d8",
"univpll2_d4",
"univpll2_d4",
};
static const char * const anc_md32_parents[] = {
"clk26m",
"syspll1_d2",
"univpll_d5",
};
/*
* Clock mux ddrphycfg is needed by the DRAM controller. We mark it as
* critical as otherwise the system will hang after boot.
*/
static const struct mtk_composite top_muxes[] = {
MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE, "ulposc_axi_ck_mux_pre",
ulposc_axi_ck_mux_pre_parents, 0x0040, 3, 1),
MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX, "ulposc_axi_ck_mux",
ulposc_axi_ck_mux_parents, 0x0040, 2, 1),
MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
0x0040, 0, 2),
MUX_FLAGS(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
0x0040, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX(CLK_TOP_MUX_MM, "mm_sel", mm_parents,
0x0040, 24, 2),
MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),
MUX_GATE(CLK_TOP_MUX_VDEC, "vdec_sel", vdec_parents, 0x0050, 8, 3, 15),
MUX_GATE(CLK_TOP_MUX_VENC, "venc_sel", venc_parents, 0x0050, 16, 2, 23),
MUX_GATE(CLK_TOP_MUX_MFG, "mfg_sel", mfg_parents, 0x0050, 24, 2, 31),
MUX_GATE(CLK_TOP_MUX_CAMTG, "camtg_sel", camtg, 0x0060, 0, 2, 7),
MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
MUX_GATE(CLK_TOP_MUX_SPI, "spi_sel", spi_parents, 0x0060, 16, 2, 23),
MUX(CLK_TOP_MUX_ULPOSC_SPI_CK_MUX, "ulposc_spi_ck_mux",
ulposc_spi_ck_mux_parents, 0x0060, 18, 1),
MUX_GATE(CLK_TOP_MUX_USB20, "usb20_sel", usb20_parents,
0x0060, 24, 2, 31),
MUX(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_0_hclk_sel",
msdc50_0_hclk_parents, 0x0070, 8, 2),
MUX_GATE(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", msdc50_0_parents,
0x0070, 16, 4, 23),
MUX_GATE(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", msdc30_1_parents,
0x0070, 24, 3, 31),
MUX_GATE(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", msdc30_2_parents,
0x0080, 0, 3, 7),
MUX_GATE(CLK_TOP_MUX_AUDIO, "audio_sel", audio_parents,
0x0080, 16, 2, 23),
MUX(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", aud_intbus_parents,
0x0080, 24, 2),
MUX(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", pmicspi_parents,
0x0090, 0, 3),
MUX(CLK_TOP_MUX_SCP, "scp_sel", scp_parents,
0x0090, 8, 2),
MUX(CLK_TOP_MUX_ATB, "atb_sel", atb_parents,
0x0090, 16, 2),
MUX_GATE(CLK_TOP_MUX_MJC, "mjc_sel", mjc_parents, 0x0090, 24, 2, 31),
MUX_GATE(CLK_TOP_MUX_DPI0, "dpi0_sel", dpi0_parents, 0x00A0, 0, 3, 7),
MUX_GATE(CLK_TOP_MUX_AUD_1, "aud_1_sel", aud_1_parents,
0x00A0, 16, 1, 23),
MUX_GATE(CLK_TOP_MUX_AUD_2, "aud_2_sel", aud_2_parents,
0x00A0, 24, 1, 31),
MUX(CLK_TOP_MUX_SSUSB_TOP_SYS, "ssusb_top_sys_sel",
ssusb_top_sys_parents, 0x00B0, 8, 1),
MUX(CLK_TOP_MUX_SPM, "spm_sel", spm_parents,
0x00C0, 0, 1),
MUX(CLK_TOP_MUX_BSI_SPI, "bsi_spi_sel", bsi_spi_parents,
0x00C0, 8, 2),
MUX_GATE(CLK_TOP_MUX_AUDIO_H, "audio_h_sel", audio_h_parents,
0x00C0, 16, 2, 23),
MUX_GATE(CLK_TOP_MUX_ANC_MD32, "anc_md32_sel", anc_md32_parents,
0x00C0, 24, 2, 31),
MUX(CLK_TOP_MUX_MFG_52M, "mfg_52m_sel", mfg_52m_parents,
0x0104, 1, 2),
};
static int mtk_topckgen_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
struct device_node *node = pdev->dev.of_node;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
clk_data);
mtk_clk_register_composites(&pdev->dev, top_muxes,
ARRAY_SIZE(top_muxes), base,
&mt6797_clk_lock, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct mtk_gate_regs infra0_cg_regs = {
.set_ofs = 0x0080,
.clr_ofs = 0x0084,
.sta_ofs = 0x0090,
};
static const struct mtk_gate_regs infra1_cg_regs = {
.set_ofs = 0x0088,
.clr_ofs = 0x008c,
.sta_ofs = 0x0094,
};
static const struct mtk_gate_regs infra2_cg_regs = {
.set_ofs = 0x00a8,
.clr_ofs = 0x00ac,
.sta_ofs = 0x00b0,
};
#define GATE_ICG0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_ICG1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flags)
#define GATE_ICG2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flags)
/*
* Clock gates dramc and dramc_b are needed by the DRAM controller.
* We mark them as critical as otherwise the system will hang after boot.
*/
static const struct mtk_gate infra_clks[] = {
GATE_ICG0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "ulposc", 0),
GATE_ICG0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pmicspi_sel", 1),
GATE_ICG0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pmicspi_sel", 2),
GATE_ICG0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pmicspi_sel", 3),
GATE_ICG0(CLK_INFRA_SCP, "infra_scp", "scp_sel", 4),
GATE_ICG0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5),
GATE_ICG0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
GATE_ICG0(CLK_INFRA_SEJ_13M, "infra_sej_13m", "clk26m", 7),
GATE_ICG0(CLK_INFRA_ICUSB, "infra_icusb", "usb20_sel", 8),
GATE_ICG0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 9),
GATE_ICG0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
GATE_ICG0(CLK_INFRA_I2C0, "infra_i2c0", "axi_sel", 11),
GATE_ICG0(CLK_INFRA_I2C1, "infra_i2c1", "axi_sel", 12),
GATE_ICG0(CLK_INFRA_I2C2, "infra_i2c2", "axi_sel", 13),
GATE_ICG0(CLK_INFRA_I2C3, "infra_i2c3", "axi_sel", 14),
GATE_ICG0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", "axi_sel", 15),
GATE_ICG0(CLK_INFRA_PWM1, "infra_pwm1", "axi_sel", 16),
GATE_ICG0(CLK_INFRA_PWM2, "infra_pwm2", "axi_sel", 17),
GATE_ICG0(CLK_INFRA_PWM3, "infra_pwm3", "axi_sel", 18),
GATE_ICG0(CLK_INFRA_PWM4, "infra_pwm4", "axi_sel", 19),
GATE_ICG0(CLK_INFRA_PWM, "infra_pwm", "axi_sel", 21),
GATE_ICG0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
GATE_ICG0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
GATE_ICG0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
GATE_ICG0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
GATE_ICG0(CLK_INFRA_MD2MD_CCIF_0, "infra_md2md_ccif_0", "axi_sel", 27),
GATE_ICG0(CLK_INFRA_MD2MD_CCIF_1, "infra_md2md_ccif_1", "axi_sel", 28),
GATE_ICG0(CLK_INFRA_MD2MD_CCIF_2, "infra_md2md_ccif_2", "axi_sel", 29),
GATE_ICG0(CLK_INFRA_FHCTL, "infra_fhctl", "clk26m", 30),
GATE_ICG0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31),
GATE_ICG1(CLK_INFRA_MD2MD_CCIF_3, "infra_md2md_ccif_3", "axi_sel", 0),
GATE_ICG1(CLK_INFRA_SPI, "infra_spi", "spi_sel", 1),
GATE_ICG1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_sel", 2),
GATE_ICG1(CLK_INFRA_MD2MD_CCIF_4, "infra_md2md_ccif_4", "axi_sel", 3),
GATE_ICG1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc30_1_sel", 4),
GATE_ICG1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc30_2_sel", 5),
GATE_ICG1(CLK_INFRA_MD2MD_CCIF_5, "infra_md2md_ccif_5", "axi_sel", 7),
GATE_ICG1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8),
GATE_ICG1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9),
GATE_ICG1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10),
GATE_ICG1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11),
GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_0, "infra_ap_c2k_ccif_0",
"axi_sel", 12),
GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_1, "infra_ap_c2k_ccif_1",
"axi_sel", 13),
GATE_ICG1(CLK_INFRA_CLDMA, "infra_cldma", "axi_sel", 16),
GATE_ICG1(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "pwm_sel", 17),
GATE_ICG1(CLK_INFRA_AP_DMA, "infra_ap_dma", "axi_sel", 18),
GATE_ICG1(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20),
GATE_ICG1(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "mm_sel", 22),
GATE_ICG1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
GATE_ICG1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
GATE_ICG1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
GATE_ICG1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
"clk26m", 31, CLK_IS_CRITICAL),
GATE_ICG2(CLK_INFRA_I2C4, "infra_i2c4", "axi_sel", 0),
GATE_ICG2(CLK_INFRA_I2C_APPM, "infra_i2c_appm", "axi_sel", 1),
GATE_ICG2(CLK_INFRA_I2C_GPUPM, "infra_i2c_gpupm", "axi_sel", 2),
GATE_ICG2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "axi_sel", 3),
GATE_ICG2(CLK_INFRA_I2C2_ARB, "infra_i2c2_arb", "axi_sel", 4),
GATE_ICG2(CLK_INFRA_I2C3_IMM, "infra_i2c3_imm", "axi_sel", 5),
GATE_ICG2(CLK_INFRA_I2C3_ARB, "infra_i2c3_arb", "axi_sel", 6),
GATE_ICG2(CLK_INFRA_I2C5, "infra_i2c5", "axi_sel", 7),
GATE_ICG2(CLK_INFRA_SYS_CIRQ, "infra_sys_cirq", "axi_sel", 8),
GATE_ICG2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 10),
GATE_ICG2_FLAGS(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m",
"clk26m", 11, CLK_IS_CRITICAL),
GATE_ICG2(CLK_INFRA_ANC_MD32, "infra_anc_md32", "anc_md32_sel", 12),
GATE_ICG2(CLK_INFRA_ANC_MD32_32K, "infra_anc_md32_32k", "clk26m", 13),
GATE_ICG2(CLK_INFRA_DVFS_SPM1, "infra_dvfs_spm1", "axi_sel", 15),
GATE_ICG2(CLK_INFRA_AES_TOP0, "infra_aes_top0", "axi_sel", 16),
GATE_ICG2(CLK_INFRA_AES_TOP1, "infra_aes_top1", "axi_sel", 17),
GATE_ICG2(CLK_INFRA_SSUSB_BUS, "infra_ssusb_bus", "axi_sel", 18),
GATE_ICG2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 19),
GATE_ICG2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 20),
GATE_ICG2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 21),
GATE_ICG2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 22),
GATE_ICG2(CLK_INFRA_IRTX, "infra_irtx", "spi_sel", 23),
GATE_ICG2(CLK_INFRA_SSUSB_SYS, "infra_ssusb_sys",
"ssusb_top_sys_sel", 24),
GATE_ICG2(CLK_INFRA_SSUSB_REF, "infra_ssusb_ref", "clk26m", 9),
GATE_ICG2(CLK_INFRA_AUDIO_26M, "infra_audio_26m", "clk26m", 26),
GATE_ICG2(CLK_INFRA_AUDIO_26M_PAD_TOP, "infra_audio_26m_pad_top",
"clk26m", 27),
GATE_ICG2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share",
"axi_sel", 28),
GATE_ICG2(CLK_INFRA_VAD_WRAP_SOC, "infra_vad_wrap_soc", "axi_sel", 29),
GATE_ICG2(CLK_INFRA_DRAMC_CONF, "infra_dramc_conf", "axi_sel", 30),
GATE_ICG2(CLK_INFRA_DRAMC_B_CONF, "infra_dramc_b_conf", "axi_sel", 31),
GATE_ICG1(CLK_INFRA_MFG_VCG, "infra_mfg_vcg", "mfg_52m_sel", 14),
};
static const struct mtk_fixed_factor infra_fixed_divs[] = {
FACTOR(CLK_INFRA_13M, "clk13m", "clk26m", 1, 2),
};
static struct clk_hw_onecell_data *infra_clk_data;
static void mtk_infrasys_init_early(struct device_node *node)
{
int r, i;
if (!infra_clk_data) {
infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
for (i = 0; i < CLK_INFRA_NR; i++)
infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
}
mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
infra_clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
infra_clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
}
CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt6797-infracfg",
mtk_infrasys_init_early);
static int mtk_infrasys_init(struct platform_device *pdev)
{
int i;
struct device_node *node = pdev->dev.of_node;
if (!infra_clk_data) {
infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
} else {
for (i = 0; i < CLK_INFRA_NR; i++) {
if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER))
infra_clk_data->hws[i] = ERR_PTR(-ENOENT);
}
}
mtk_clk_register_gates(&pdev->dev, node, infra_clks,
ARRAY_SIZE(infra_clks), infra_clk_data);
mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
infra_clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
infra_clk_data);
}
#define MT6797_PLL_FMAX (3000UL * MHZ)
#define CON0_MT6797_RST_BAR BIT(24)
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
_pcw_shift, _div_table) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = _en_mask, \
.flags = _flags, \
.rst_bar_mask = CON0_MT6797_RST_BAR, \
.fmax = MT6797_PLL_FMAX, \
.pcwbits = _pcwbits, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
.div_table = _div_table, \
}
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
_pcw_shift) \
PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
NULL)
static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000100, PLL_AO,
21, 0x220, 4, 0x0, 0x224, 0),
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000010, 0, 7,
0x230, 4, 0x0, 0x234, 14),
PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000100, 0, 21,
0x244, 24, 0x0, 0x244, 0),
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000120, 0, 21,
0x250, 4, 0x0, 0x254, 0),
PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000120, 0, 21,
0x260, 4, 0x0, 0x264, 0),
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000120, 0, 21,
0x270, 4, 0x0, 0x274, 0),
PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000120, 0, 21,
0x290, 4, 0x0, 0x294, 0),
PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000120, 0, 21,
0x2E4, 4, 0x0, 0x2E8, 0),
PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000130, 0, 31,
0x2A0, 4, 0x2A8, 0x2A4, 0),
PLL(CLK_APMIXED_APLL2, "apll2", 0x02B4, 0x02C4, 0x00000130, 0, 31,
0x2B4, 4, 0x2BC, 0x2B8, 0),
};
static int mtk_apmixedsys_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct of_device_id of_match_clk_mt6797[] = {
{
.compatible = "mediatek,mt6797-topckgen",
.data = mtk_topckgen_init,
}, {
.compatible = "mediatek,mt6797-infracfg",
.data = mtk_infrasys_init,
}, {
.compatible = "mediatek,mt6797-apmixedsys",
.data = mtk_apmixedsys_init,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6797);
static int clk_mt6797_probe(struct platform_device *pdev)
{
int (*clk_init)(struct platform_device *);
int r;
clk_init = of_device_get_match_data(&pdev->dev);
if (!clk_init)
return -EINVAL;
r = clk_init(pdev);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
return r;
}
static struct platform_driver clk_mt6797_drv = {
.probe = clk_mt6797_probe,
.driver = {
.name = "clk-mt6797",
.of_match_table = of_match_clk_mt6797,
},
};
static int __init clk_mt6797_init(void)
{
return platform_driver_register(&clk_mt6797_drv);
}
arch_initcall(clk_mt6797_init);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6797.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Garmin Chang <[email protected]>
*/
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs vpp1_0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs vpp1_1_cg_regs = {
.set_ofs = 0x114,
.clr_ofs = 0x118,
.sta_ofs = 0x110,
};
#define GATE_VPP1_0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vpp1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VPP1_1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vpp1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate vpp1_clks[] = {
/* VPP1_0 */
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_OVL, "vpp1_svpp1_mdp_ovl", "top_vpp", 0),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TCC, "vpp1_svpp1_mdp_tcc", "top_vpp", 1),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_WROT, "vpp1_svpp1_mdp_wrot", "top_vpp", 2),
GATE_VPP1_0(CLK_VPP1_SVPP1_VPP_PAD, "vpp1_svpp1_vpp_pad", "top_vpp", 3),
GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_WROT, "vpp1_svpp2_mdp_wrot", "top_vpp", 4),
GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_PAD, "vpp1_svpp2_vpp_pad", "top_vpp", 5),
GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_WROT, "vpp1_svpp3_mdp_wrot", "top_vpp", 6),
GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_PAD, "vpp1_svpp3_vpp_pad", "top_vpp", 7),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RDMA, "vpp1_svpp1_mdp_rdma", "top_vpp", 8),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_FG, "vpp1_svpp1_mdp_fg", "top_vpp", 9),
GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RDMA, "vpp1_svpp2_mdp_rdma", "top_vpp", 10),
GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_FG, "vpp1_svpp2_mdp_fg", "top_vpp", 11),
GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RDMA, "vpp1_svpp3_mdp_rdma", "top_vpp", 12),
GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_FG, "vpp1_svpp3_mdp_fg", "top_vpp", 13),
GATE_VPP1_0(CLK_VPP1_VPP_SPLIT, "vpp1_vpp_split", "top_vpp", 14),
GATE_VPP1_0(CLK_VPP1_SVPP2_VDO0_DL_RELAY, "vpp1_svpp2_vdo0_dl_relay", "top_vpp", 15),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RSZ, "vpp1_svpp1_mdp_rsz", "top_vpp", 16),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TDSHP, "vpp1_svpp1_mdp_tdshp", "top_vpp", 17),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_COLOR, "vpp1_svpp1_mdp_color", "top_vpp", 18),
GATE_VPP1_0(CLK_VPP1_SVPP3_VDO1_DL_RELAY, "vpp1_svpp3_vdo1_dl_relay", "top_vpp", 19),
GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RSZ, "vpp1_svpp2_mdp_rsz", "top_vpp", 20),
GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_MERGE, "vpp1_svpp2_vpp_merge", "top_vpp", 21),
GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_TDSHP, "vpp1_svpp2_mdp_tdshp", "top_vpp", 22),
GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_COLOR, "vpp1_svpp2_mdp_color", "top_vpp", 23),
GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RSZ, "vpp1_svpp3_mdp_rsz", "top_vpp", 24),
GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_MERGE, "vpp1_svpp3_vpp_merge", "top_vpp", 25),
GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_TDSHP, "vpp1_svpp3_mdp_tdshp", "top_vpp", 26),
GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_COLOR, "vpp1_svpp3_mdp_color", "top_vpp", 27),
GATE_VPP1_0(CLK_VPP1_GALS5, "vpp1_gals5", "top_vpp", 28),
GATE_VPP1_0(CLK_VPP1_GALS6, "vpp1_gals6", "top_vpp", 29),
GATE_VPP1_0(CLK_VPP1_LARB5, "vpp1_larb5", "top_vpp", 30),
GATE_VPP1_0(CLK_VPP1_LARB6, "vpp1_larb6", "top_vpp", 31),
/* VPP1_1 */
GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_HDR, "vpp1_svpp1_mdp_hdr", "top_vpp", 0),
GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_AAL, "vpp1_svpp1_mdp_aal", "top_vpp", 1),
GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_HDR, "vpp1_svpp2_mdp_hdr", "top_vpp", 2),
GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_AAL, "vpp1_svpp2_mdp_aal", "top_vpp", 3),
GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_HDR, "vpp1_svpp3_mdp_hdr", "top_vpp", 4),
GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_AAL, "vpp1_svpp3_mdp_aal", "top_vpp", 5),
GATE_VPP1_1(CLK_VPP1_DISP_MUTEX, "vpp1_disp_mutex", "top_vpp", 7),
GATE_VPP1_1(CLK_VPP1_SVPP2_VDO1_DL_RELAY, "vpp1_svpp2_vdo1_dl_relay", "top_vpp", 8),
GATE_VPP1_1(CLK_VPP1_SVPP3_VDO0_DL_RELAY, "vpp1_svpp3_vdo0_dl_relay", "top_vpp", 9),
GATE_VPP1_1(CLK_VPP1_VPP0_DL_ASYNC, "vpp1_vpp0_dl_async", "top_vpp", 10),
GATE_VPP1_1(CLK_VPP1_VPP0_DL1_RELAY, "vpp1_vpp0_dl1_relay", "top_vpp", 11),
GATE_VPP1_1(CLK_VPP1_LARB5_FAKE_ENG, "vpp1_larb5_fake_eng", "top_vpp", 12),
GATE_VPP1_1(CLK_VPP1_LARB6_FAKE_ENG, "vpp1_larb6_fake_eng", "top_vpp", 13),
GATE_VPP1_1(CLK_VPP1_HDMI_META, "vpp1_hdmi_meta", "top_vpp", 16),
GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_HDMI, "vpp1_vpp_split_hdmi", "top_vpp", 17),
GATE_VPP1_1(CLK_VPP1_DGI_IN, "vpp1_dgi_in", "top_vpp", 18),
GATE_VPP1_1(CLK_VPP1_DGI_OUT, "vpp1_dgi_out", "top_vpp", 19),
GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_DGI, "vpp1_vpp_split_dgi", "top_vpp", 20),
GATE_VPP1_1(CLK_VPP1_DL_CON_OCC, "vpp1_dl_con_occ", "top_vpp", 21),
GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m", "top_vpp", 26),
};
static const struct mtk_clk_desc vpp1_desc = {
.clks = vpp1_clks,
.num_clks = ARRAY_SIZE(vpp1_clks),
};
static const struct platform_device_id clk_mt8188_vpp1_id_table[] = {
{ .name = "clk-mt8188-vpp1", .driver_data = (kernel_ulong_t)&vpp1_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, clk_mt8188_vpp1_id_table);
static struct platform_driver clk_mt8188_vpp1_drv = {
.probe = mtk_clk_pdev_probe,
.remove_new = mtk_clk_pdev_remove,
.driver = {
.name = "clk-mt8188-vpp1",
},
.id_table = clk_mt8188_vpp1_id_table,
};
module_platform_driver(clk_mt8188_vpp1_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8188-vpp1.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/reset/mt8195-resets.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs infra_ao0_cg_regs = {
.set_ofs = 0x80,
.clr_ofs = 0x84,
.sta_ofs = 0x90,
};
static const struct mtk_gate_regs infra_ao1_cg_regs = {
.set_ofs = 0x88,
.clr_ofs = 0x8c,
.sta_ofs = 0x94,
};
static const struct mtk_gate_regs infra_ao2_cg_regs = {
.set_ofs = 0xa4,
.clr_ofs = 0xa8,
.sta_ofs = 0xac,
};
static const struct mtk_gate_regs infra_ao3_cg_regs = {
.set_ofs = 0xc0,
.clr_ofs = 0xc4,
.sta_ofs = 0xc8,
};
static const struct mtk_gate_regs infra_ao4_cg_regs = {
.set_ofs = 0xe0,
.clr_ofs = 0xe4,
.sta_ofs = 0xe8,
};
#define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flag)
#define GATE_INFRA_AO0(_id, _name, _parent, _shift) \
GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flag)
#define GATE_INFRA_AO1(_id, _name, _parent, _shift) \
GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flag)
#define GATE_INFRA_AO2(_id, _name, _parent, _shift) \
GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flag)
#define GATE_INFRA_AO3(_id, _name, _parent, _shift) \
GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao4_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flag)
#define GATE_INFRA_AO4(_id, _name, _parent, _shift) \
GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, 0)
static const struct mtk_gate infra_ao_clks[] = {
/* INFRA_AO0 */
GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_TMR, "infra_ao_pmic_tmr", "top_pwrap_ulposc", 0),
GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_AP, "infra_ao_pmic_ap", "top_pwrap_ulposc", 1),
GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_MD, "infra_ao_pmic_md", "top_pwrap_ulposc", 2),
GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_CONN, "infra_ao_pmic_conn", "top_pwrap_ulposc", 3),
/* infra_ao_sej is main clock is for secure engine with JTAG support */
GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SEJ, "infra_ao_sej", "top_axi", 5, CLK_IS_CRITICAL),
GATE_INFRA_AO0(CLK_INFRA_AO_APXGPT, "infra_ao_apxgpt", "top_axi", 6),
GATE_INFRA_AO0(CLK_INFRA_AO_GCE, "infra_ao_gce", "top_axi", 8),
GATE_INFRA_AO0(CLK_INFRA_AO_GCE2, "infra_ao_gce2", "top_axi", 9),
GATE_INFRA_AO0(CLK_INFRA_AO_THERM, "infra_ao_therm", "top_axi", 10),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM_H, "infra_ao_pwm_h", "top_axi", 15),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM1, "infra_ao_pwm1", "top_pwm", 16),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM2, "infra_ao_pwm2", "top_pwm", 17),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM3, "infra_ao_pwm3", "top_pwm", 18),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM4, "infra_ao_pwm4", "top_pwm", 19),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM, "infra_ao_pwm", "top_pwm", 21),
GATE_INFRA_AO0(CLK_INFRA_AO_UART0, "infra_ao_uart0", "top_uart", 22),
GATE_INFRA_AO0(CLK_INFRA_AO_UART1, "infra_ao_uart1", "top_uart", 23),
GATE_INFRA_AO0(CLK_INFRA_AO_UART2, "infra_ao_uart2", "top_uart", 24),
GATE_INFRA_AO0(CLK_INFRA_AO_UART3, "infra_ao_uart3", "top_uart", 25),
GATE_INFRA_AO0(CLK_INFRA_AO_UART4, "infra_ao_uart4", "top_uart", 26),
GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, "infra_ao_gce_26m", "clk26m", 27),
GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, "infra_ao_cq_dma_fpc", "fpc", 28),
GATE_INFRA_AO0(CLK_INFRA_AO_UART5, "infra_ao_uart5", "top_uart", 29),
/* INFRA_AO1 */
GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, "infra_ao_hdmi_26m", "clk26m", 0),
GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "top_spi", 1),
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, "infra_ao_msdc0", "top_msdc50_0_hclk", 2),
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, "infra_ao_msdc1", "top_axi", 4),
GATE_INFRA_AO1(CLK_INFRA_AO_CG1_MSDC2, "infra_ao_cg1_msdc2", "top_axi", 5),
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0_SRC, "infra_ao_msdc0_src", "top_msdc50_0", 6),
GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, "infra_ao_trng", "top_axi", 9),
GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, "infra_ao_auxadc", "clk26m", 10),
GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, "infra_ao_cpum", "top_axi", 11),
GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_32K, "infra_ao_hdmi_32k", "clk32k", 12),
GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_H, "infra_ao_cec_66m_h", "top_axi", 13),
GATE_INFRA_AO1(CLK_INFRA_AO_IRRX, "infra_ao_irrx", "top_axi", 14),
GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_26M, "infra_ao_pcie_tl_26m", "clk26m", 15),
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1_SRC, "infra_ao_msdc1_src", "top_msdc30_1", 16),
GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_B, "infra_ao_cec_66m_b", "top_axi", 17),
GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_96M, "infra_ao_pcie_tl_96m", "top_tl", 18),
/* infra_ao_device_apc is for device access permission control module */
GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DEVICE_APC, "infra_ao_device_apc", "top_axi", 20,
CLK_IS_CRITICAL),
GATE_INFRA_AO1(CLK_INFRA_AO_ECC_66M_H, "infra_ao_ecc_66m_h", "top_axi", 23),
GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGSYS, "infra_ao_debugsys", "top_axi", 24),
GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, "infra_ao_audio", "top_axi", 25),
GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_32K, "infra_ao_pcie_tl_32k", "clk32k", 26),
GATE_INFRA_AO1(CLK_INFRA_AO_DBG_TRACE, "infra_ao_dbg_trace", "top_axi", 29),
GATE_INFRA_AO1(CLK_INFRA_AO_DRAMC_F26M, "infra_ao_dramc_f26m", "clk26m", 31),
/* INFRA_AO2 */
GATE_INFRA_AO2(CLK_INFRA_AO_IRTX, "infra_ao_irtx", "top_axi", 0),
GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB, "infra_ao_ssusb", "top_usb_top", 1),
GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, "infra_ao_disp_pwm", "top_disp_pwm0", 2),
GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_B, "infra_ao_cldma_b", "top_axi", 3),
GATE_INFRA_AO2(CLK_INFRA_AO_AUDIO_26M_B, "infra_ao_audio_26m_b", "clk26m", 4),
GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "top_spi", 6),
GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, "infra_ao_spi2", "top_spi", 9),
GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, "infra_ao_spi3", "top_spi", 10),
GATE_INFRA_AO2(CLK_INFRA_AO_UNIPRO_SYS, "infra_ao_unipro_sys", "top_ufs", 11),
GATE_INFRA_AO2(CLK_INFRA_AO_UNIPRO_TICK, "infra_ao_unipro_tick", "top_ufs_tick1us", 12),
GATE_INFRA_AO2(CLK_INFRA_AO_UFS_MP_SAP_B, "infra_ao_ufs_mp_sap_b", "top_ufs_mp_sap_cfg", 13),
/* pwrmcu is used by ATF for platform PM: clocks must never be disabled by the kernel */
GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_PWRMCU, "infra_ao_pwrmcu", "top_pwrmcu", 15,
CLK_IS_CRITICAL),
GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_PWRMCU_BUS_H, "infra_ao_pwrmcu_bus_h", "top_axi", 17,
CLK_IS_CRITICAL),
GATE_INFRA_AO2(CLK_INFRA_AO_APDMA_B, "infra_ao_apdma_b", "top_axi", 18),
GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, "infra_ao_spi4", "top_spi", 25),
GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, "infra_ao_spi5", "top_spi", 26),
GATE_INFRA_AO2(CLK_INFRA_AO_CQ_DMA, "infra_ao_cq_dma", "top_axi", 27),
GATE_INFRA_AO2(CLK_INFRA_AO_AES_UFSFDE, "infra_ao_aes_ufsfde", "top_ufs", 28),
GATE_INFRA_AO2(CLK_INFRA_AO_AES, "infra_ao_aes", "top_aes_ufsfde", 29),
GATE_INFRA_AO2(CLK_INFRA_AO_UFS_TICK, "infra_ao_ufs_tick", "top_ufs_tick1us", 30),
GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_XHCI, "infra_ao_ssusb_xhci", "top_ssusb_xhci", 31),
/* INFRA_AO3 */
GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SELF, "infra_ao_msdc0f", "top_msdc50_0", 0),
GATE_INFRA_AO3(CLK_INFRA_AO_MSDC1_SELF, "infra_ao_msdc1f", "top_msdc50_0", 1),
GATE_INFRA_AO3(CLK_INFRA_AO_MSDC2_SELF, "infra_ao_msdc2f", "top_msdc50_0", 2),
GATE_INFRA_AO3(CLK_INFRA_AO_I2S_DMA, "infra_ao_i2s_dma", "top_axi", 5),
GATE_INFRA_AO3(CLK_INFRA_AO_AP_MSDC0, "infra_ao_ap_msdc0", "top_msdc50_0", 7),
GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, "infra_ao_md_msdc0", "top_msdc50_0", 8),
GATE_INFRA_AO3(CLK_INFRA_AO_CG3_MSDC2, "infra_ao_cg3_msdc2", "top_msdc30_2", 9),
GATE_INFRA_AO3(CLK_INFRA_AO_GCPU, "infra_ao_gcpu", "top_gcpu", 10),
GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_PERI_26M, "infra_ao_pcie_peri_26m", "clk26m", 15),
GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_66M_B, "infra_ao_gcpu_66m_b", "top_axi", 16),
GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_133M_B, "infra_ao_gcpu_133m_b", "top_axi", 17),
GATE_INFRA_AO3(CLK_INFRA_AO_DISP_PWM1, "infra_ao_disp_pwm1", "top_disp_pwm1", 20),
GATE_INFRA_AO3(CLK_INFRA_AO_FBIST2FPC, "infra_ao_fbist2fpc", "top_msdc50_0", 24),
/* infra_ao_device_apc_sync is for device access permission control module */
GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_DEVICE_APC_SYNC, "infra_ao_device_apc_sync", "top_axi", 25,
CLK_IS_CRITICAL),
GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_P1_PERI_26M, "infra_ao_pcie_p1_peri_26m", "clk26m", 26),
GATE_INFRA_AO3(CLK_INFRA_AO_SPIS0, "infra_ao_spis0", "top_spis", 28),
GATE_INFRA_AO3(CLK_INFRA_AO_SPIS1, "infra_ao_spis1", "top_spis", 29),
/* INFRA_AO4 */
/* infra_ao_133m_m_peri infra_ao_66m_m_peri are main clocks of peripheral */
GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_133M_M_PERI, "infra_ao_133m_m_peri", "top_axi", 0,
CLK_IS_CRITICAL),
GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_66M_M_PERI, "infra_ao_66m_m_peri", "top_axi", 1,
CLK_IS_CRITICAL),
GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P0, "infra_ao_pcie_pl_p_250m_p0", "pextp_pipe", 7),
GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P1, "infra_ao_pcie_pl_p_250m_p1",
"ssusb_u3phy_p1_p_p0", 8),
GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_P1_TL_96M, "infra_ao_pcie_p1_tl_96m", "top_tl_p1", 17),
GATE_INFRA_AO4(CLK_INFRA_AO_AES_MSDCFDE_0P, "infra_ao_aes_msdcfde_0p", "top_aes_msdcfde", 18),
GATE_INFRA_AO4(CLK_INFRA_AO_UFS_TX_SYMBOL, "infra_ao_ufs_tx_symbol", "ufs_tx_symbol", 22),
GATE_INFRA_AO4(CLK_INFRA_AO_UFS_RX_SYMBOL, "infra_ao_ufs_rx_symbol", "ufs_rx_symbol", 23),
GATE_INFRA_AO4(CLK_INFRA_AO_UFS_RX_SYMBOL1, "infra_ao_ufs_rx_symbol1", "ufs_rx_symbol1", 24),
GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, "infra_ao_peri_ufs_mem_sub", "mem_466m", 31),
};
static u16 infra_ao_rst_ofs[] = {
INFRA_RST0_SET_OFFSET,
INFRA_RST1_SET_OFFSET,
INFRA_RST2_SET_OFFSET,
INFRA_RST3_SET_OFFSET,
INFRA_RST4_SET_OFFSET,
};
static u16 infra_ao_idx_map[] = {
[MT8195_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
[MT8195_INFRA_RST2_USBSIF_P1_SWRST] = 2 * RST_NR_PER_BANK + 18,
[MT8195_INFRA_RST2_PCIE_P0_SWRST] = 2 * RST_NR_PER_BANK + 26,
[MT8195_INFRA_RST2_PCIE_P1_SWRST] = 2 * RST_NR_PER_BANK + 27,
[MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
[MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 10,
};
static struct mtk_clk_rst_desc infra_ao_rst_desc = {
.version = MTK_RST_SET_CLR,
.rst_bank_ofs = infra_ao_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
.rst_idx_map = infra_ao_idx_map,
.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
};
static const struct mtk_clk_desc infra_ao_desc = {
.clks = infra_ao_clks,
.num_clks = ARRAY_SIZE(infra_ao_clks),
.rst_desc = &infra_ao_rst_desc,
};
static const struct of_device_id of_match_clk_mt8195_infra_ao[] = {
{
.compatible = "mediatek,mt8195-infracfg_ao",
.data = &infra_ao_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_infra_ao);
static struct platform_driver clk_mt8195_infra_ao_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8195-infra_ao",
.of_match_table = of_match_clk_mt8195_infra_ao,
},
};
module_platform_driver(clk_mt8195_infra_ao_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8195-infra_ao.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Garmin Chang <[email protected]>
*/
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs vdec0_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x4,
.sta_ofs = 0x0,
};
static const struct mtk_gate_regs vdec1_cg_regs = {
.set_ofs = 0x200,
.clr_ofs = 0x204,
.sta_ofs = 0x200,
};
static const struct mtk_gate_regs vdec2_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0xc,
.sta_ofs = 0x8,
};
#define GATE_VDEC0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
#define GATE_VDEC1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
#define GATE_VDEC2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate vdec1_clks[] = {
/* VDEC1_0 */
GATE_VDEC0(CLK_VDEC1_SOC_VDEC, "vdec1_soc_vdec", "top_vdec", 0),
GATE_VDEC0(CLK_VDEC1_SOC_VDEC_ACTIVE, "vdec1_soc_vdec_active", "top_vdec", 4),
GATE_VDEC0(CLK_VDEC1_SOC_VDEC_ENG, "vdec1_soc_vdec_eng", "top_vdec", 8),
/* VDEC1_1 */
GATE_VDEC1(CLK_VDEC1_SOC_LAT, "vdec1_soc_lat", "top_vdec", 0),
GATE_VDEC1(CLK_VDEC1_SOC_LAT_ACTIVE, "vdec1_soc_lat_active", "top_vdec", 4),
GATE_VDEC1(CLK_VDEC1_SOC_LAT_ENG, "vdec1_soc_lat_eng", "top_vdec", 8),
/* VDEC1_2 */
GATE_VDEC2(CLK_VDEC1_SOC_LARB1, "vdec1_soc_larb1", "top_vdec", 0),
};
static const struct mtk_gate vdec2_clks[] = {
/* VDEC2_0 */
GATE_VDEC0(CLK_VDEC2_VDEC, "vdec2_vdec", "top_vdec", 0),
GATE_VDEC0(CLK_VDEC2_VDEC_ACTIVE, "vdec2_vdec_active", "top_vdec", 4),
GATE_VDEC0(CLK_VDEC2_VDEC_ENG, "vdec2_vdec_eng", "top_vdec", 8),
/* VDEC2_1 */
GATE_VDEC1(CLK_VDEC2_LAT, "vdec2_lat", "top_vdec", 0),
/* VDEC2_2 */
GATE_VDEC2(CLK_VDEC2_LARB1, "vdec2_larb1", "top_vdec", 0),
};
static const struct mtk_clk_desc vdec1_desc = {
.clks = vdec1_clks,
.num_clks = ARRAY_SIZE(vdec1_clks),
};
static const struct mtk_clk_desc vdec2_desc = {
.clks = vdec2_clks,
.num_clks = ARRAY_SIZE(vdec2_clks),
};
static const struct of_device_id of_match_clk_mt8188_vdec[] = {
{ .compatible = "mediatek,mt8188-vdecsys-soc", .data = &vdec1_desc },
{ .compatible = "mediatek,mt8188-vdecsys", .data = &vdec2_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_vdec);
static struct platform_driver clk_mt8188_vdec_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8188-vdec",
.of_match_table = of_match_clk_mt8188_vdec,
},
};
module_platform_driver(clk_mt8188_vdec_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8188-vdec.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 MediaTek Inc.
* Weiyi Lu <[email protected]>
* Copyright (c) 2023 Collabora, Ltd.
* AngeloGioacchino Del Regno <[email protected]>
*/
#include <dt-bindings/clock/mt8183-clk.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-pll.h"
static const struct mtk_gate_regs apmixed_cg_regs = {
.set_ofs = 0x20,
.clr_ofs = 0x20,
.sta_ofs = 0x20,
};
#define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \
GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \
_shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
#define GATE_APMIXED(_id, _name, _parent, _shift) \
GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
/*
* CRITICAL CLOCK:
* apmixed_appll26m is the toppest clock gate of all PLLs.
*/
static const struct mtk_gate apmixed_clks[] = {
/* AUDIO0 */
GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m", "f_f26m_ck", 4),
GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL_26M, "apmixed_appll26m",
"f_f26m_ck", 5, CLK_IS_CRITICAL),
GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", "f_f26m_ck", 6),
GATE_APMIXED(CLK_APMIXED_MDPLLGP_26M, "apmixed_mdpll26m", "f_f26m_ck", 7),
GATE_APMIXED(CLK_APMIXED_MMSYS_26M, "apmixed_mmsys26m", "f_f26m_ck", 8),
GATE_APMIXED(CLK_APMIXED_UFS_26M, "apmixed_ufs26m", "f_f26m_ck", 9),
GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", "f_f26m_ck", 11),
GATE_APMIXED(CLK_APMIXED_MEMPLL_26M, "apmixed_mempll26m", "f_f26m_ck", 13),
GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m", "f_f26m_ck", 14),
GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", "f_f26m_ck", 16),
GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m", "f_f26m_ck", 17),
};
#define MT8183_PLL_FMAX (3800UL * MHZ)
#define MT8183_PLL_FMIN (1500UL * MHZ)
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
_rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
_pd_shift, _tuner_reg, _tuner_en_reg, \
_tuner_en_bit, _pcw_reg, _pcw_shift, \
_pcw_chg_reg, _div_table) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = _en_mask, \
.flags = _flags, \
.rst_bar_mask = _rst_bar_mask, \
.fmax = MT8183_PLL_FMAX, \
.fmin = MT8183_PLL_FMIN, \
.pcwbits = _pcwbits, \
.pcwibits = _pcwibits, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, \
.tuner_en_reg = _tuner_en_reg, \
.tuner_en_bit = _tuner_en_bit, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
.pcw_chg_reg = _pcw_chg_reg, \
.div_table = _div_table, \
}
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
_rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
_pd_shift, _tuner_reg, _tuner_en_reg, \
_tuner_en_bit, _pcw_reg, _pcw_shift, \
_pcw_chg_reg) \
PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
_rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
_pd_shift, _tuner_reg, _tuner_en_reg, \
_tuner_en_bit, _pcw_reg, _pcw_shift, \
_pcw_chg_reg, NULL)
static const struct mtk_pll_div_table armpll_div_table[] = {
{ .div = 0, .freq = MT8183_PLL_FMAX },
{ .div = 1, .freq = 1500 * MHZ },
{ .div = 2, .freq = 750 * MHZ },
{ .div = 3, .freq = 375 * MHZ },
{ .div = 4, .freq = 187500000 },
{ /* sentinel */ }
};
static const struct mtk_pll_div_table mfgpll_div_table[] = {
{ .div = 0, .freq = MT8183_PLL_FMAX },
{ .div = 1, .freq = 1600 * MHZ },
{ .div = 2, .freq = 800 * MHZ },
{ .div = 3, .freq = 400 * MHZ },
{ .div = 4, .freq = 200 * MHZ },
{ /* sentinel */ }
};
static const struct mtk_pll_data plls[] = {
PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0,
HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0,
0x0204, 0, 0, armpll_div_table),
PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0,
HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0,
0x0214, 0, 0, armpll_div_table),
PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0,
HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0,
0x0294, 0, 0),
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0,
HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0,
0x0224, 0, 0),
PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0,
HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0,
0x0234, 0, 0),
PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0,
0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0,
mfgpll_div_table),
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0,
0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0),
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0,
0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0),
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0,
HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0,
0x0274, 0, 0),
PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0,
0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0),
PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0,
0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
};
static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
{
void __iomem *base;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
struct device *dev = &pdev->dev;
int ret;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK);
if (!clk_data)
return -ENOMEM;
ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
if (ret)
return ret;
ret = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
ARRAY_SIZE(apmixed_clks), clk_data);
if (ret)
goto unregister_plls;
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (ret)
goto unregister_gates;
return 0;
unregister_gates:
mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
unregister_plls:
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
return ret;
}
static const struct of_device_id of_match_clk_mt8183_apmixed[] = {
{ .compatible = "mediatek,mt8183-apmixedsys" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_apmixed);
static struct platform_driver clk_mt8183_apmixed_drv = {
.probe = clk_mt8183_apmixed_probe,
.driver = {
.name = "clk-mt8183-apmixed",
.of_match_table = of_match_clk_mt8183_apmixed,
},
};
builtin_platform_driver(clk_mt8183_apmixed_drv)
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8183-apmixedsys.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 MediaTek Inc.
* Author: Owen Chen <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt6765-clk.h>
static const struct mtk_gate_regs mipi0a_cg_regs = {
.set_ofs = 0x80,
.clr_ofs = 0x80,
.sta_ofs = 0x80,
};
#define GATE_MIPI0A(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mipi0a_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate mipi0a_clks[] = {
GATE_MIPI0A(CLK_MIPI0A_CSR_CSI_EN_0A,
"mipi0a_csr_0a", "f_fseninf_ck", 1),
};
static const struct mtk_clk_desc mipi0a_desc = {
.clks = mipi0a_clks,
.num_clks = ARRAY_SIZE(mipi0a_clks),
};
static const struct of_device_id of_match_clk_mt6765_mipi0a[] = {
{
.compatible = "mediatek,mt6765-mipi0a",
.data = &mipi0a_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_mipi0a);
static struct platform_driver clk_mt6765_mipi0a_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt6765-mipi0a",
.of_match_table = of_match_clk_mt6765_mipi0a,
},
};
module_platform_driver(clk_mt6765_mipi0a_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6765-mipi0a.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs mfg_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_MFG(_id, _name, _parent, _shift) \
GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, \
_shift, &mtk_clk_gate_ops_setclr, \
CLK_SET_RATE_PARENT)
static const struct mtk_gate mfg_clks[] = {
GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_ck_fast_ref", 0),
};
static const struct mtk_clk_desc mfg_desc = {
.clks = mfg_clks,
.num_clks = ARRAY_SIZE(mfg_clks),
};
static const struct of_device_id of_match_clk_mt8195_mfg[] = {
{
.compatible = "mediatek,mt8195-mfgcfg",
.data = &mfg_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_mfg);
static struct platform_driver clk_mt8195_mfg_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8195-mfg",
.of_match_table = of_match_clk_mt8195_mfg,
},
};
module_platform_driver(clk_mt8195_mfg_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8195-mfg.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Chen Zhong <[email protected]>
* Sean Wang <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt7622-clk.h>
#define GATE_PCIE(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &pcie_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
#define GATE_SSUSB(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ssusb_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate_regs pcie_cg_regs = {
.set_ofs = 0x30,
.clr_ofs = 0x30,
.sta_ofs = 0x30,
};
static const struct mtk_gate_regs ssusb_cg_regs = {
.set_ofs = 0x30,
.clr_ofs = 0x30,
.sta_ofs = 0x30,
};
static const struct mtk_gate ssusb_clks[] = {
GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p",
"to_u2_phy_1p", 0),
GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1),
GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5),
GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6),
GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "axi_sel", 7),
GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "hif_sel", 8),
};
static const struct mtk_gate pcie_clks[] = {
GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12),
GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13),
GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "axi_sel", 14),
GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "hif_sel", 15),
GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16),
GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17),
GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18),
GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19),
GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "axi_sel", 20),
GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "hif_sel", 21),
GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22),
GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
GATE_PCIE(CLK_SATA_AHB_EN, "sata_ahb_en", "axi_sel", 26),
GATE_PCIE(CLK_SATA_AXI_EN, "sata_axi_en", "hif_sel", 27),
GATE_PCIE(CLK_SATA_ASIC_EN, "sata_asic_en", "sata_asic", 28),
GATE_PCIE(CLK_SATA_RBC_EN, "sata_rbc_en", "sata_rbc", 29),
GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30),
};
static u16 rst_ofs[] = { 0x34, };
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SIMPLE,
.rst_bank_ofs = rst_ofs,
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
static const struct mtk_clk_desc ssusb_desc = {
.clks = ssusb_clks,
.num_clks = ARRAY_SIZE(ssusb_clks),
.rst_desc = &clk_rst_desc,
};
static const struct mtk_clk_desc pcie_desc = {
.clks = pcie_clks,
.num_clks = ARRAY_SIZE(pcie_clks),
.rst_desc = &clk_rst_desc,
};
static const struct of_device_id of_match_clk_mt7622_hif[] = {
{ .compatible = "mediatek,mt7622-pciesys", .data = &pcie_desc },
{ .compatible = "mediatek,mt7622-ssusbsys", .data = &ssusb_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_hif);
static struct platform_driver clk_mt7622_hif_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7622-hif",
.of_match_table = of_match_clk_mt7622_hif,
},
};
module_platform_driver(clk_mt7622_hif_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt7622-hif.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs vpp0_0_cg_regs = {
.set_ofs = 0x24,
.clr_ofs = 0x28,
.sta_ofs = 0x20,
};
static const struct mtk_gate_regs vpp0_1_cg_regs = {
.set_ofs = 0x30,
.clr_ofs = 0x34,
.sta_ofs = 0x2c,
};
static const struct mtk_gate_regs vpp0_2_cg_regs = {
.set_ofs = 0x3c,
.clr_ofs = 0x40,
.sta_ofs = 0x38,
};
#define GATE_VPP0_0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VPP0_1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VPP0_2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vpp0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate vpp0_clks[] = {
/* VPP0_0 */
GATE_VPP0_0(CLK_VPP0_MDP_FG, "vpp0_mdp_fg", "top_vpp", 1),
GATE_VPP0_0(CLK_VPP0_STITCH, "vpp0_stitch", "top_vpp", 2),
GATE_VPP0_0(CLK_VPP0_PADDING, "vpp0_padding", "top_vpp", 7),
GATE_VPP0_0(CLK_VPP0_MDP_TCC, "vpp0_mdp_tcc", "top_vpp", 8),
GATE_VPP0_0(CLK_VPP0_WARP0_ASYNC_TX, "vpp0_warp0_async_tx", "top_vpp", 10),
GATE_VPP0_0(CLK_VPP0_WARP1_ASYNC_TX, "vpp0_warp1_async_tx", "top_vpp", 11),
GATE_VPP0_0(CLK_VPP0_MUTEX, "vpp0_mutex", "top_vpp", 13),
GATE_VPP0_0(CLK_VPP0_VPP02VPP1_RELAY, "vpp0_vpp02vpp1_relay", "top_vpp", 14),
GATE_VPP0_0(CLK_VPP0_VPP12VPP0_ASYNC, "vpp0_vpp12vpp0_async", "top_vpp", 15),
GATE_VPP0_0(CLK_VPP0_MMSYSRAM_TOP, "vpp0_mmsysram_top", "top_vpp", 16),
GATE_VPP0_0(CLK_VPP0_MDP_AAL, "vpp0_mdp_aal", "top_vpp", 17),
GATE_VPP0_0(CLK_VPP0_MDP_RSZ, "vpp0_mdp_rsz", "top_vpp", 18),
/* VPP0_1 */
GATE_VPP0_1(CLK_VPP0_SMI_COMMON, "vpp0_smi_common", "top_vpp", 0),
GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB0, "vpp0_gals_vdo0_larb0", "top_vpp", 1),
GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB1, "vpp0_gals_vdo0_larb1", "top_vpp", 2),
GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS, "vpp0_gals_vencsys", "top_vpp", 3),
GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_CORE1, "vpp0_gals_vencsys_core1", "top_vpp", 4),
GATE_VPP0_1(CLK_VPP0_GALS_INFRA, "vpp0_gals_infra", "top_vpp", 5),
GATE_VPP0_1(CLK_VPP0_GALS_CAMSYS, "vpp0_gals_camsys", "top_vpp", 6),
GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB5, "vpp0_gals_vpp1_larb5", "top_vpp", 7),
GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB6, "vpp0_gals_vpp1_larb6", "top_vpp", 8),
GATE_VPP0_1(CLK_VPP0_SMI_REORDER, "vpp0_smi_reorder", "top_vpp", 9),
GATE_VPP0_1(CLK_VPP0_SMI_IOMMU, "vpp0_smi_iommu", "top_vpp", 10),
GATE_VPP0_1(CLK_VPP0_GALS_IMGSYS_CAMSYS, "vpp0_gals_imgsys_camsys", "top_vpp", 11),
GATE_VPP0_1(CLK_VPP0_MDP_RDMA, "vpp0_mdp_rdma", "top_vpp", 12),
GATE_VPP0_1(CLK_VPP0_MDP_WROT, "vpp0_mdp_wrot", "top_vpp", 13),
GATE_VPP0_1(CLK_VPP0_GALS_EMI0_EMI1, "vpp0_gals_emi0_emi1", "top_vpp", 16),
GATE_VPP0_1(CLK_VPP0_SMI_SUB_COMMON_REORDER, "vpp0_smi_sub_common_reorder", "top_vpp", 17),
GATE_VPP0_1(CLK_VPP0_SMI_RSI, "vpp0_smi_rsi", "top_vpp", 18),
GATE_VPP0_1(CLK_VPP0_SMI_COMMON_LARB4, "vpp0_smi_common_larb4", "top_vpp", 19),
GATE_VPP0_1(CLK_VPP0_GALS_VDEC_VDEC_CORE1, "vpp0_gals_vdec_vdec_core1", "top_vpp", 20),
GATE_VPP0_1(CLK_VPP0_GALS_VPP1_WPE, "vpp0_gals_vpp1_wpe", "top_vpp", 21),
GATE_VPP0_1(CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1, "vpp0_gals_vdo0_vdo1_vencsys_core1",
"top_vpp", 22),
GATE_VPP0_1(CLK_VPP0_FAKE_ENG, "vpp0_fake_eng", "top_vpp", 23),
GATE_VPP0_1(CLK_VPP0_MDP_HDR, "vpp0_mdp_hdr", "top_vpp", 24),
GATE_VPP0_1(CLK_VPP0_MDP_TDSHP, "vpp0_mdp_tdshp", "top_vpp", 25),
GATE_VPP0_1(CLK_VPP0_MDP_COLOR, "vpp0_mdp_color", "top_vpp", 26),
GATE_VPP0_1(CLK_VPP0_MDP_OVL, "vpp0_mdp_ovl", "top_vpp", 27),
/* VPP0_2 */
GATE_VPP0_2(CLK_VPP0_WARP0_RELAY, "vpp0_warp0_relay", "top_wpe_vpp", 0),
GATE_VPP0_2(CLK_VPP0_WARP0_MDP_DL_ASYNC, "vpp0_warp0_mdp_dl_async", "top_wpe_vpp", 1),
GATE_VPP0_2(CLK_VPP0_WARP1_RELAY, "vpp0_warp1_relay", "top_wpe_vpp", 2),
GATE_VPP0_2(CLK_VPP0_WARP1_MDP_DL_ASYNC, "vpp0_warp1_mdp_dl_async", "top_wpe_vpp", 3),
};
static const struct mtk_clk_desc vpp0_desc = {
.clks = vpp0_clks,
.num_clks = ARRAY_SIZE(vpp0_clks),
};
static const struct platform_device_id clk_mt8195_vpp0_id_table[] = {
{ .name = "clk-mt8195-vpp0", .driver_data = (kernel_ulong_t)&vpp0_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, clk_mt8195_vpp0_id_table);
static struct platform_driver clk_mt8195_vpp0_drv = {
.probe = mtk_clk_pdev_probe,
.remove_new = mtk_clk_pdev_remove,
.driver = {
.name = "clk-mt8195-vpp0",
},
.id_table = clk_mt8195_vpp0_id_table,
};
module_platform_driver(clk_mt8195_vpp0_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8195-vpp0.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2018 MediaTek Inc.
// Author: Weiyi Lu <[email protected]>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8183-clk.h>
static const struct mtk_gate_regs ipu_adl_cg_regs = {
.set_ofs = 0x204,
.clr_ofs = 0x204,
.sta_ofs = 0x204,
};
#define GATE_IPU_ADL_I(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ipu_adl_cg_regs, _shift, \
&mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate ipu_adl_clks[] = {
GATE_IPU_ADL_I(CLK_IPU_ADL_CABGEN, "ipu_adl_cabgen", "dsp_sel", 24),
};
static const struct mtk_clk_desc ipu_adl_desc = {
.clks = ipu_adl_clks,
.num_clks = ARRAY_SIZE(ipu_adl_clks),
};
static const struct of_device_id of_match_clk_mt8183_ipu_adl[] = {
{
.compatible = "mediatek,mt8183-ipu_adl",
.data = &ipu_adl_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_ipu_adl);
static struct platform_driver clk_mt8183_ipu_adl_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8183-ipu_adl",
.of_match_table = of_match_clk_mt8183_ipu_adl,
},
};
module_platform_driver(clk_mt8183_ipu_adl_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8183-ipu_adl.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Garmin Chang <[email protected]>
*/
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs imgsys_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_IMGSYS(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &imgsys_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate imgsys_main_clks[] = {
GATE_IMGSYS(CLK_IMGSYS_MAIN_LARB9, "imgsys_main_larb9", "top_img", 0),
GATE_IMGSYS(CLK_IMGSYS_MAIN_TRAW0, "imgsys_main_traw0", "top_img", 1),
GATE_IMGSYS(CLK_IMGSYS_MAIN_TRAW1, "imgsys_main_traw1", "top_img", 2),
GATE_IMGSYS(CLK_IMGSYS_MAIN_VCORE_GALS, "imgsys_main_vcore_gals", "top_img", 3),
GATE_IMGSYS(CLK_IMGSYS_MAIN_DIP0, "imgsys_main_dip0", "top_img", 8),
GATE_IMGSYS(CLK_IMGSYS_MAIN_WPE0, "imgsys_main_wpe0", "top_img", 9),
GATE_IMGSYS(CLK_IMGSYS_MAIN_IPE, "imgsys_main_ipe", "top_img", 10),
GATE_IMGSYS(CLK_IMGSYS_MAIN_WPE1, "imgsys_main_wpe1", "top_img", 12),
GATE_IMGSYS(CLK_IMGSYS_MAIN_WPE2, "imgsys_main_wpe2", "top_img", 13),
GATE_IMGSYS(CLK_IMGSYS_MAIN_GALS, "imgsys_main_gals", "top_img", 31),
};
static const struct mtk_gate imgsys_wpe1_clks[] = {
GATE_IMGSYS(CLK_IMGSYS_WPE1_LARB11, "imgsys_wpe1_larb11", "top_img", 0),
GATE_IMGSYS(CLK_IMGSYS_WPE1, "imgsys_wpe1", "top_img", 1),
};
static const struct mtk_gate imgsys_wpe2_clks[] = {
GATE_IMGSYS(CLK_IMGSYS_WPE2_LARB11, "imgsys_wpe2_larb11", "top_img", 0),
GATE_IMGSYS(CLK_IMGSYS_WPE2, "imgsys_wpe2", "top_img", 1),
};
static const struct mtk_gate imgsys_wpe3_clks[] = {
GATE_IMGSYS(CLK_IMGSYS_WPE3_LARB11, "imgsys_wpe3_larb11", "top_img", 0),
GATE_IMGSYS(CLK_IMGSYS_WPE3, "imgsys_wpe3", "top_img", 1),
};
static const struct mtk_gate imgsys1_dip_top_clks[] = {
GATE_IMGSYS(CLK_IMGSYS1_DIP_TOP_LARB10, "imgsys1_dip_larb10", "top_img", 0),
GATE_IMGSYS(CLK_IMGSYS1_DIP_TOP_DIP_TOP, "imgsys1_dip_dip_top", "top_img", 1),
};
static const struct mtk_gate imgsys1_dip_nr_clks[] = {
GATE_IMGSYS(CLK_IMGSYS1_DIP_NR_LARB15, "imgsys1_dip_nr_larb15", "top_img", 0),
GATE_IMGSYS(CLK_IMGSYS1_DIP_NR_DIP_NR, "imgsys1_dip_nr_dip_nr", "top_img", 1),
};
static const struct mtk_clk_desc imgsys_main_desc = {
.clks = imgsys_main_clks,
.num_clks = ARRAY_SIZE(imgsys_main_clks),
};
static const struct mtk_clk_desc imgsys_wpe1_desc = {
.clks = imgsys_wpe1_clks,
.num_clks = ARRAY_SIZE(imgsys_wpe1_clks),
};
static const struct mtk_clk_desc imgsys_wpe2_desc = {
.clks = imgsys_wpe2_clks,
.num_clks = ARRAY_SIZE(imgsys_wpe2_clks),
};
static const struct mtk_clk_desc imgsys_wpe3_desc = {
.clks = imgsys_wpe3_clks,
.num_clks = ARRAY_SIZE(imgsys_wpe3_clks),
};
static const struct mtk_clk_desc imgsys1_dip_top_desc = {
.clks = imgsys1_dip_top_clks,
.num_clks = ARRAY_SIZE(imgsys1_dip_top_clks),
};
static const struct mtk_clk_desc imgsys1_dip_nr_desc = {
.clks = imgsys1_dip_nr_clks,
.num_clks = ARRAY_SIZE(imgsys1_dip_nr_clks),
};
static const struct of_device_id of_match_clk_mt8188_imgsys_main[] = {
{ .compatible = "mediatek,mt8188-imgsys", .data = &imgsys_main_desc },
{ .compatible = "mediatek,mt8188-imgsys-wpe1", .data = &imgsys_wpe1_desc },
{ .compatible = "mediatek,mt8188-imgsys-wpe2", .data = &imgsys_wpe2_desc },
{ .compatible = "mediatek,mt8188-imgsys-wpe3", .data = &imgsys_wpe3_desc },
{ .compatible = "mediatek,mt8188-imgsys1-dip-top", .data = &imgsys1_dip_top_desc },
{ .compatible = "mediatek,mt8188-imgsys1-dip-nr", .data = &imgsys1_dip_nr_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_imgsys_main);
static struct platform_driver clk_mt8188_imgsys_main_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8188-imgsys_main",
.of_match_table = of_match_clk_mt8188_imgsys_main,
},
};
module_platform_driver(clk_mt8188_imgsys_main_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8188-img.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2018 MediaTek Inc.
// Author: Weiyi Lu <[email protected]>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8183-clk.h>
static const struct mtk_gate_regs ipu_core0_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_IPU_CORE0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ipu_core0_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr)
static const struct mtk_gate ipu_core0_clks[] = {
GATE_IPU_CORE0(CLK_IPU_CORE0_JTAG, "ipu_core0_jtag", "dsp_sel", 0),
GATE_IPU_CORE0(CLK_IPU_CORE0_AXI, "ipu_core0_axi", "dsp_sel", 1),
GATE_IPU_CORE0(CLK_IPU_CORE0_IPU, "ipu_core0_ipu", "dsp_sel", 2),
};
static const struct mtk_clk_desc ipu_core0_desc = {
.clks = ipu_core0_clks,
.num_clks = ARRAY_SIZE(ipu_core0_clks),
};
static const struct of_device_id of_match_clk_mt8183_ipu_core0[] = {
{
.compatible = "mediatek,mt8183-ipu_core0",
.data = &ipu_core0_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_ipu_core0);
static struct platform_driver clk_mt8183_ipu_core0_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8183-ipu_core0",
.of_match_table = of_match_clk_mt8183_ipu_core0,
},
};
module_platform_driver(clk_mt8183_ipu_core0_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8183-ipu0.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 MediaTek Inc.
* Copyright (c) 2020 BayLibre, SAS
* Author: James Liao <[email protected]>
* Fabien Parent <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8167-clk.h>
static const struct mtk_gate_regs aud_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x0,
.sta_ofs = 0x0,
};
#define GATE_AUD(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &aud_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate aud_clks[] = {
GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2),
GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6),
GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8),
GATE_AUD(CLK_AUD_24M, "aud_24m", "rg_aud_engen2", 9),
GATE_AUD(CLK_AUD_INTDIR, "aud_intdir", "rg_aud_spdif_in", 15),
GATE_AUD(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "rg_aud_engen2", 18),
GATE_AUD(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "rg_aud_engen1", 19),
GATE_AUD(CLK_AUD_HDMI, "aud_hdmi", "apll12_div4", 20),
GATE_AUD(CLK_AUD_SPDF, "aud_spdf", "apll12_div6", 21),
GATE_AUD(CLK_AUD_ADC, "aud_adc", "aud_afe", 24),
GATE_AUD(CLK_AUD_DAC, "aud_dac", "aud_afe", 25),
GATE_AUD(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "aud_afe", 26),
GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27),
};
static const struct mtk_clk_desc aud_desc = {
.clks = aud_clks,
.num_clks = ARRAY_SIZE(aud_clks),
};
static const struct of_device_id of_match_clk_mt8167_audsys[] = {
{ .compatible = "mediatek,mt8167-audsys", .data = &aud_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_audsys);
static struct platform_driver clk_mt8167_audsys_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8167-audsys",
.of_match_table = of_match_clk_mt8167_audsys,
},
};
module_platform_driver(clk_mt8167_audsys_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8167-aud.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2018 MediaTek Inc.
// Author: Weiyi Lu <[email protected]>
#include <linux/clk-provider.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8183-clk.h>
static const struct mtk_gate_regs audio0_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x0,
.sta_ofs = 0x0,
};
static const struct mtk_gate_regs audio1_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x4,
.sta_ofs = 0x4,
};
#define GATE_AUDIO0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
&mtk_clk_gate_ops_no_setclr)
#define GATE_AUDIO1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, \
&mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate audio_clks[] = {
/* AUDIO0 */
GATE_AUDIO0(CLK_AUDIO_AFE, "aud_afe", "audio_sel",
2),
GATE_AUDIO0(CLK_AUDIO_22M, "aud_22m", "aud_eng1_sel",
8),
GATE_AUDIO0(CLK_AUDIO_24M, "aud_24m", "aud_eng2_sel",
9),
GATE_AUDIO0(CLK_AUDIO_APLL2_TUNER, "aud_apll2_tuner", "aud_eng2_sel",
18),
GATE_AUDIO0(CLK_AUDIO_APLL_TUNER, "aud_apll_tuner", "aud_eng1_sel",
19),
GATE_AUDIO0(CLK_AUDIO_TDM, "aud_tdm", "apll12_divb",
20),
GATE_AUDIO0(CLK_AUDIO_ADC, "aud_adc", "audio_sel",
24),
GATE_AUDIO0(CLK_AUDIO_DAC, "aud_dac", "audio_sel",
25),
GATE_AUDIO0(CLK_AUDIO_DAC_PREDIS, "aud_dac_predis", "audio_sel",
26),
GATE_AUDIO0(CLK_AUDIO_TML, "aud_tml", "audio_sel",
27),
/* AUDIO1 */
GATE_AUDIO1(CLK_AUDIO_I2S1, "aud_i2s1", "audio_sel",
4),
GATE_AUDIO1(CLK_AUDIO_I2S2, "aud_i2s2", "audio_sel",
5),
GATE_AUDIO1(CLK_AUDIO_I2S3, "aud_i2s3", "audio_sel",
6),
GATE_AUDIO1(CLK_AUDIO_I2S4, "aud_i2s4", "audio_sel",
7),
GATE_AUDIO1(CLK_AUDIO_PDN_ADDA6_ADC, "aud_pdn_adda6_adc", "audio_sel",
20),
};
static const struct mtk_clk_desc audio_desc = {
.clks = audio_clks,
.num_clks = ARRAY_SIZE(audio_clks),
};
static int clk_mt8183_audio_probe(struct platform_device *pdev)
{
int r;
r = mtk_clk_simple_probe(pdev);
if (r)
return r;
r = devm_of_platform_populate(&pdev->dev);
if (r)
mtk_clk_simple_remove(pdev);
return r;
}
static void clk_mt8183_audio_remove(struct platform_device *pdev)
{
of_platform_depopulate(&pdev->dev);
mtk_clk_simple_remove(pdev);
}
static const struct of_device_id of_match_clk_mt8183_audio[] = {
{ .compatible = "mediatek,mt8183-audiosys", .data = &audio_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_audio);
static struct platform_driver clk_mt8183_audio_drv = {
.probe = clk_mt8183_audio_probe,
.remove_new = clk_mt8183_audio_remove,
.driver = {
.name = "clk-mt8183-audio",
.of_match_table = of_match_clk_mt8183_audio,
},
};
module_platform_driver(clk_mt8183_audio_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8183-audio.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Garmin Chang <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs venc1_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_VENC1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &venc1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate venc1_clks[] = {
GATE_VENC1(CLK_VENC1_LARB, "venc1_larb", "top_venc", 0),
GATE_VENC1(CLK_VENC1_VENC, "venc1_venc", "top_venc", 4),
GATE_VENC1(CLK_VENC1_JPGENC, "venc1_jpgenc", "top_venc", 8),
GATE_VENC1(CLK_VENC1_JPGDEC, "venc1_jpgdec", "top_venc", 12),
GATE_VENC1(CLK_VENC1_JPGDEC_C1, "venc1_jpgdec_c1", "top_venc", 16),
GATE_VENC1(CLK_VENC1_GALS, "venc1_gals", "top_venc", 28),
GATE_VENC1(CLK_VENC1_GALS_SRAM, "venc1_gals_sram", "top_venc", 31),
};
static const struct mtk_clk_desc venc1_desc = {
.clks = venc1_clks,
.num_clks = ARRAY_SIZE(venc1_clks),
};
static const struct of_device_id of_match_clk_mt8188_venc1[] = {
{ .compatible = "mediatek,mt8188-vencsys", .data = &venc1_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_venc1);
static struct platform_driver clk_mt8188_venc1_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8188-venc1",
.of_match_table = of_match_clk_mt8188_venc1,
},
};
module_platform_driver(clk_mt8188_venc1_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8188-venc.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8192-clk.h>
static const struct mtk_gate_regs mfg_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_MFG(_id, _name, _parent, _shift) \
GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, \
_shift, &mtk_clk_gate_ops_setclr, \
CLK_SET_RATE_PARENT)
static const struct mtk_gate mfg_clks[] = {
GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_pll_sel", 0),
};
static const struct mtk_clk_desc mfg_desc = {
.clks = mfg_clks,
.num_clks = ARRAY_SIZE(mfg_clks),
};
static const struct of_device_id of_match_clk_mt8192_mfg[] = {
{
.compatible = "mediatek,mt8192-mfgcfg",
.data = &mfg_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_mfg);
static struct platform_driver clk_mt8192_mfg_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8192-mfg",
.of_match_table = of_match_clk_mt8192_mfg,
},
};
module_platform_driver(clk_mt8192_mfg_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8192-mfg.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 MediaTek Inc.
* Author: Sam Shih <[email protected]>
* Author: Wenzhen Yu <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt7986-clk.h>
static const struct mtk_gate_regs sgmii0_cg_regs = {
.set_ofs = 0xe4,
.clr_ofs = 0xe4,
.sta_ofs = 0xe4,
};
#define GATE_SGMII0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &sgmii0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate sgmii0_clks[] = {
GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2),
GATE_SGMII0(CLK_SGMII0_RX250M_EN, "sgmii0_rx250m_en", "top_xtal", 3),
GATE_SGMII0(CLK_SGMII0_CDR_REF, "sgmii0_cdr_ref", "top_xtal", 4),
GATE_SGMII0(CLK_SGMII0_CDR_FB, "sgmii0_cdr_fb", "top_xtal", 5),
};
static const struct mtk_gate_regs sgmii1_cg_regs = {
.set_ofs = 0xe4,
.clr_ofs = 0xe4,
.sta_ofs = 0xe4,
};
#define GATE_SGMII1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &sgmii1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate sgmii1_clks[] = {
GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2),
GATE_SGMII1(CLK_SGMII1_RX250M_EN, "sgmii1_rx250m_en", "top_xtal", 3),
GATE_SGMII1(CLK_SGMII1_CDR_REF, "sgmii1_cdr_ref", "top_xtal", 4),
GATE_SGMII1(CLK_SGMII1_CDR_FB, "sgmii1_cdr_fb", "top_xtal", 5),
};
static const struct mtk_gate_regs eth_cg_regs = {
.set_ofs = 0x30,
.clr_ofs = 0x30,
.sta_ofs = 0x30,
};
#define GATE_ETH(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate eth_clks[] = {
GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6),
GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m_sel", 7),
GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m_sel", 8),
GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", "netsys_mcu_sel", 14),
GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_mcu_sel", 15),
};
static const struct mtk_clk_desc eth_desc = {
.clks = eth_clks,
.num_clks = ARRAY_SIZE(eth_clks),
};
static const struct mtk_clk_desc sgmii0_desc = {
.clks = sgmii0_clks,
.num_clks = ARRAY_SIZE(sgmii0_clks),
};
static const struct mtk_clk_desc sgmii1_desc = {
.clks = sgmii1_clks,
.num_clks = ARRAY_SIZE(sgmii1_clks),
};
static const struct of_device_id of_match_clk_mt7986_eth[] = {
{ .compatible = "mediatek,mt7986-ethsys", .data = ð_desc },
{ .compatible = "mediatek,mt7986-sgmiisys_0", .data = &sgmii0_desc },
{ .compatible = "mediatek,mt7986-sgmiisys_1", .data = &sgmii1_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_eth);
static struct platform_driver clk_mt7986_eth_drv = {
.driver = {
.name = "clk-mt7986-eth",
.of_match_table = of_match_clk_mt7986_eth,
},
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt7986_eth_drv);
MODULE_DESCRIPTION("MediaTek MT7986 Ethernet clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt7986-eth.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 Collabora Ltd.
* Author: AngeloGioacchino Del Regno <[email protected]>
*/
#include <dt-bindings/clock/mediatek,mt6795-clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs mfg_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_MFG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate mfg_clks[] = {
GATE_MFG(CLK_MFG_BAXI, "mfg_baxi", "axi_mfg_in_sel", 0),
GATE_MFG(CLK_MFG_BMEM, "mfg_bmem", "mem_mfg_in_sel", 1),
GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 2),
GATE_MFG(CLK_MFG_B26M, "mfg_b26m", "clk26m", 3),
};
static const struct mtk_clk_desc mfg_desc = {
.clks = mfg_clks,
.num_clks = ARRAY_SIZE(mfg_clks),
};
static const struct of_device_id of_match_clk_mt6795_mfg[] = {
{ .compatible = "mediatek,mt6795-mfgcfg", .data = &mfg_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_mfg);
static struct platform_driver clk_mt6795_mfg_drv = {
.driver = {
.name = "clk-mt6795-mfg",
.of_match_table = of_match_clk_mt6795_mfg,
},
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt6795_mfg_drv);
MODULE_DESCRIPTION("MediaTek MT6795 mfg clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6795-mfg.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8192-clk.h>
static const struct mtk_gate_regs cam_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_CAM(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate cam_clks[] = {
GATE_CAM(CLK_CAM_LARB13, "cam_larb13", "cam_sel", 0),
GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "cam_sel", 1),
GATE_CAM(CLK_CAM_LARB14, "cam_larb14", "cam_sel", 2),
GATE_CAM(CLK_CAM_CAM, "cam_cam", "cam_sel", 6),
GATE_CAM(CLK_CAM_CAMTG, "cam_camtg", "cam_sel", 7),
GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "cam_sel", 8),
GATE_CAM(CLK_CAM_CAMSV0, "cam_camsv0", "cam_sel", 9),
GATE_CAM(CLK_CAM_CAMSV1, "cam_camsv1", "cam_sel", 10),
GATE_CAM(CLK_CAM_CAMSV2, "cam_camsv2", "cam_sel", 11),
GATE_CAM(CLK_CAM_CAMSV3, "cam_camsv3", "cam_sel", 12),
GATE_CAM(CLK_CAM_CCU0, "cam_ccu0", "cam_sel", 13),
GATE_CAM(CLK_CAM_CCU1, "cam_ccu1", "cam_sel", 14),
GATE_CAM(CLK_CAM_MRAW0, "cam_mraw0", "cam_sel", 15),
GATE_CAM(CLK_CAM_FAKE_ENG, "cam_fake_eng", "cam_sel", 17),
GATE_CAM(CLK_CAM_CCU_GALS, "cam_ccu_gals", "cam_sel", 18),
GATE_CAM(CLK_CAM_CAM2MM_GALS, "cam2mm_gals", "cam_sel", 19),
};
static const struct mtk_gate cam_rawa_clks[] = {
GATE_CAM(CLK_CAM_RAWA_LARBX, "cam_rawa_larbx", "cam_sel", 0),
GATE_CAM(CLK_CAM_RAWA_CAM, "cam_rawa_cam", "cam_sel", 1),
GATE_CAM(CLK_CAM_RAWA_CAMTG, "cam_rawa_camtg", "cam_sel", 2),
};
static const struct mtk_gate cam_rawb_clks[] = {
GATE_CAM(CLK_CAM_RAWB_LARBX, "cam_rawb_larbx", "cam_sel", 0),
GATE_CAM(CLK_CAM_RAWB_CAM, "cam_rawb_cam", "cam_sel", 1),
GATE_CAM(CLK_CAM_RAWB_CAMTG, "cam_rawb_camtg", "cam_sel", 2),
};
static const struct mtk_gate cam_rawc_clks[] = {
GATE_CAM(CLK_CAM_RAWC_LARBX, "cam_rawc_larbx", "cam_sel", 0),
GATE_CAM(CLK_CAM_RAWC_CAM, "cam_rawc_cam", "cam_sel", 1),
GATE_CAM(CLK_CAM_RAWC_CAMTG, "cam_rawc_camtg", "cam_sel", 2),
};
static const struct mtk_clk_desc cam_desc = {
.clks = cam_clks,
.num_clks = ARRAY_SIZE(cam_clks),
};
static const struct mtk_clk_desc cam_rawa_desc = {
.clks = cam_rawa_clks,
.num_clks = ARRAY_SIZE(cam_rawa_clks),
};
static const struct mtk_clk_desc cam_rawb_desc = {
.clks = cam_rawb_clks,
.num_clks = ARRAY_SIZE(cam_rawb_clks),
};
static const struct mtk_clk_desc cam_rawc_desc = {
.clks = cam_rawc_clks,
.num_clks = ARRAY_SIZE(cam_rawc_clks),
};
static const struct of_device_id of_match_clk_mt8192_cam[] = {
{
.compatible = "mediatek,mt8192-camsys",
.data = &cam_desc,
}, {
.compatible = "mediatek,mt8192-camsys_rawa",
.data = &cam_rawa_desc,
}, {
.compatible = "mediatek,mt8192-camsys_rawb",
.data = &cam_rawb_desc,
}, {
.compatible = "mediatek,mt8192-camsys_rawc",
.data = &cam_rawc_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_cam);
static struct platform_driver clk_mt8192_cam_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8192-cam",
.of_match_table = of_match_clk_mt8192_cam,
},
};
module_platform_driver(clk_mt8192_cam_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8192-cam.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 MediaTek Inc.
* Copyright (c) 2022 BayLibre, SAS
*/
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs mm0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs mm1_cg_regs = {
.set_ofs = 0x114,
.clr_ofs = 0x118,
.sta_ofs = 0x110,
};
#define GATE_MM0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr)
#define GATE_MM1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr)
static const struct mtk_gate mm_clks[] = {
/* MM0 */
GATE_MM0(CLK_MM_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 0),
GATE_MM0(CLK_MM_MM_MDP_CCORR0, "mm_mdp_ccorr0", "mm_sel", 1),
GATE_MM0(CLK_MM_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 2),
GATE_MM0(CLK_MM_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 3),
GATE_MM0(CLK_MM_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 4),
GATE_MM0(CLK_MM_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 5),
GATE_MM0(CLK_MM_MM_MDP_WDMA0, "mm_mdp_wdma0", "mm_sel", 6),
GATE_MM0(CLK_MM_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 7),
GATE_MM0(CLK_MM_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 8),
GATE_MM0(CLK_MM_MM_DISP_RSZ0, "mm_disp_rsz0", "mm_sel", 9),
GATE_MM0(CLK_MM_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 10),
GATE_MM0(CLK_MM_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 11),
GATE_MM0(CLK_MM_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 12),
GATE_MM0(CLK_MM_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_sel", 13),
GATE_MM0(CLK_MM_MM_DISP_AAL0, "mm_disp_aal0", "mm_sel", 14),
GATE_MM0(CLK_MM_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_sel", 15),
GATE_MM0(CLK_MM_MM_DISP_DITHER0, "mm_disp_dither0", "mm_sel", 16),
GATE_MM0(CLK_MM_MM_DSI0, "mm_dsi0", "mm_sel", 17),
GATE_MM0(CLK_MM_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 18),
GATE_MM0(CLK_MM_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 19),
GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "vpll_dpix", 20),
GATE_MM0(CLK_MM_MM_FAKE, "mm_fake", "mm_sel", 21),
GATE_MM0(CLK_MM_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 22),
GATE_MM0(CLK_MM_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 23),
GATE_MM0(CLK_MM_MM_SMI_COMM0, "mm_smi_comm0", "mm_sel", 24),
GATE_MM0(CLK_MM_MM_SMI_COMM1, "mm_smi_comm1", "mm_sel", 25),
GATE_MM0(CLK_MM_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 26),
GATE_MM0(CLK_MM_MM_SMI_IMG, "mm_smi_img", "mm_sel", 27),
GATE_MM0(CLK_MM_MM_SMI_CAM, "mm_smi_cam", "mm_sel", 28),
GATE_MM0(CLK_MM_IMG_IMG_DL_RELAY, "mm_dl_relay", "mm_sel", 29),
GATE_MM0(CLK_MM_IMG_IMG_DL_ASYNC_TOP, "mm_dl_async_top", "mm_sel", 30),
GATE_MM0(CLK_MM_DSI0_DIG_DSI, "mm_dsi0_dig_dsi", "dsi0_lntc_dsick", 31),
/* MM1 */
GATE_MM1(CLK_MM_26M_HRTWT, "mm_f26m_hrtwt", "clk26m", 0),
GATE_MM1(CLK_MM_MM_DPI0, "mm_dpi0", "mm_sel", 1),
GATE_MM1(CLK_MM_LVDSTX_PXL, "mm_flvdstx_pxl", "vpll_dpix", 2),
GATE_MM1(CLK_MM_LVDSTX_CTS, "mm_flvdstx_cts", "lvdstx_dig_cts", 3),
};
static const struct mtk_clk_desc mm_desc = {
.clks = mm_clks,
.num_clks = ARRAY_SIZE(mm_clks),
};
static const struct platform_device_id clk_mt8365_mm_id_table[] = {
{ .name = "clk-mt8365-mm", .driver_data = (kernel_ulong_t)&mm_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, clk_mt8365_mm_id_table);
static struct platform_driver clk_mt8365_mm_drv = {
.probe = mtk_clk_pdev_probe,
.remove_new = mtk_clk_pdev_remove,
.driver = {
.name = "clk-mt8365-mm",
},
.id_table = clk_mt8365_mm_id_table,
};
module_platform_driver(clk_mt8365_mm_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8365-mm.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015 Linaro Ltd.
* Author: Pi-Cheng Chen <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/container_of.h>
#include <linux/err.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include "clk-mtk.h"
#include "clk-cpumux.h"
struct mtk_clk_cpumux {
struct clk_hw hw;
struct regmap *regmap;
u32 reg;
u32 mask;
u8 shift;
};
static inline struct mtk_clk_cpumux *to_mtk_clk_cpumux(struct clk_hw *_hw)
{
return container_of(_hw, struct mtk_clk_cpumux, hw);
}
static u8 clk_cpumux_get_parent(struct clk_hw *hw)
{
struct mtk_clk_cpumux *mux = to_mtk_clk_cpumux(hw);
unsigned int val;
regmap_read(mux->regmap, mux->reg, &val);
val >>= mux->shift;
val &= mux->mask;
return val;
}
static int clk_cpumux_set_parent(struct clk_hw *hw, u8 index)
{
struct mtk_clk_cpumux *mux = to_mtk_clk_cpumux(hw);
u32 mask, val;
val = index << mux->shift;
mask = mux->mask << mux->shift;
return regmap_update_bits(mux->regmap, mux->reg, mask, val);
}
static const struct clk_ops clk_cpumux_ops = {
.determine_rate = clk_hw_determine_rate_no_reparent,
.get_parent = clk_cpumux_get_parent,
.set_parent = clk_cpumux_set_parent,
};
static struct clk_hw *
mtk_clk_register_cpumux(struct device *dev, const struct mtk_composite *mux,
struct regmap *regmap)
{
struct mtk_clk_cpumux *cpumux;
int ret;
struct clk_init_data init;
cpumux = kzalloc(sizeof(*cpumux), GFP_KERNEL);
if (!cpumux)
return ERR_PTR(-ENOMEM);
init.name = mux->name;
init.ops = &clk_cpumux_ops;
init.parent_names = mux->parent_names;
init.num_parents = mux->num_parents;
init.flags = mux->flags;
cpumux->reg = mux->mux_reg;
cpumux->shift = mux->mux_shift;
cpumux->mask = BIT(mux->mux_width) - 1;
cpumux->regmap = regmap;
cpumux->hw.init = &init;
ret = clk_hw_register(dev, &cpumux->hw);
if (ret) {
kfree(cpumux);
return ERR_PTR(ret);
}
return &cpumux->hw;
}
static void mtk_clk_unregister_cpumux(struct clk_hw *hw)
{
struct mtk_clk_cpumux *cpumux;
if (!hw)
return;
cpumux = to_mtk_clk_cpumux(hw);
clk_hw_unregister(hw);
kfree(cpumux);
}
int mtk_clk_register_cpumuxes(struct device *dev, struct device_node *node,
const struct mtk_composite *clks, int num,
struct clk_hw_onecell_data *clk_data)
{
int i;
struct clk_hw *hw;
struct regmap *regmap;
regmap = device_node_to_regmap(node);
if (IS_ERR(regmap)) {
pr_err("Cannot find regmap for %pOF: %pe\n", node, regmap);
return PTR_ERR(regmap);
}
for (i = 0; i < num; i++) {
const struct mtk_composite *mux = &clks[i];
if (!IS_ERR_OR_NULL(clk_data->hws[mux->id])) {
pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",
node, mux->id);
continue;
}
hw = mtk_clk_register_cpumux(dev, mux, regmap);
if (IS_ERR(hw)) {
pr_err("Failed to register clk %s: %pe\n", mux->name,
hw);
goto err;
}
clk_data->hws[mux->id] = hw;
}
return 0;
err:
while (--i >= 0) {
const struct mtk_composite *mux = &clks[i];
if (IS_ERR_OR_NULL(clk_data->hws[mux->id]))
continue;
mtk_clk_unregister_cpumux(clk_data->hws[mux->id]);
clk_data->hws[mux->id] = ERR_PTR(-ENOENT);
}
return PTR_ERR(hw);
}
EXPORT_SYMBOL_GPL(mtk_clk_register_cpumuxes);
void mtk_clk_unregister_cpumuxes(const struct mtk_composite *clks, int num,
struct clk_hw_onecell_data *clk_data)
{
int i;
for (i = num; i > 0; i--) {
const struct mtk_composite *mux = &clks[i - 1];
if (IS_ERR_OR_NULL(clk_data->hws[mux->id]))
continue;
mtk_clk_unregister_cpumux(clk_data->hws[mux->id]);
clk_data->hws[mux->id] = ERR_PTR(-ENOENT);
}
}
EXPORT_SYMBOL_GPL(mtk_clk_unregister_cpumuxes);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-cpumux.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2018 MediaTek Inc.
// Author: Weiyi Lu <[email protected]>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8183-clk.h>
static const struct mtk_gate_regs ipu_conn_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
static const struct mtk_gate_regs ipu_conn_apb_cg_regs = {
.set_ofs = 0x10,
.clr_ofs = 0x10,
.sta_ofs = 0x10,
};
static const struct mtk_gate_regs ipu_conn_axi_cg_regs = {
.set_ofs = 0x18,
.clr_ofs = 0x18,
.sta_ofs = 0x18,
};
static const struct mtk_gate_regs ipu_conn_axi1_cg_regs = {
.set_ofs = 0x1c,
.clr_ofs = 0x1c,
.sta_ofs = 0x1c,
};
static const struct mtk_gate_regs ipu_conn_axi2_cg_regs = {
.set_ofs = 0x20,
.clr_ofs = 0x20,
.sta_ofs = 0x20,
};
#define GATE_IPU_CONN(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr)
#define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift, \
&mtk_clk_gate_ops_no_setclr)
#define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift, \
&mtk_clk_gate_ops_no_setclr_inv)
#define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift, \
&mtk_clk_gate_ops_no_setclr_inv)
#define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ipu_conn_axi2_cg_regs, _shift, \
&mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate ipu_conn_clks[] = {
GATE_IPU_CONN(CLK_IPU_CONN_IPU,
"ipu_conn_ipu", "dsp_sel", 0),
GATE_IPU_CONN(CLK_IPU_CONN_AHB,
"ipu_conn_ahb", "dsp_sel", 1),
GATE_IPU_CONN(CLK_IPU_CONN_AXI,
"ipu_conn_axi", "dsp_sel", 2),
GATE_IPU_CONN(CLK_IPU_CONN_ISP,
"ipu_conn_isp", "dsp_sel", 3),
GATE_IPU_CONN(CLK_IPU_CONN_CAM_ADL,
"ipu_conn_cam_adl", "dsp_sel", 4),
GATE_IPU_CONN(CLK_IPU_CONN_IMG_ADL,
"ipu_conn_img_adl", "dsp_sel", 5),
GATE_IPU_CONN_APB(CLK_IPU_CONN_DAP_RX,
"ipu_conn_dap_rx", "dsp1_sel", 0),
GATE_IPU_CONN_APB(CLK_IPU_CONN_APB2AXI,
"ipu_conn_apb2axi", "dsp1_sel", 3),
GATE_IPU_CONN_APB(CLK_IPU_CONN_APB2AHB,
"ipu_conn_apb2ahb", "dsp1_sel", 20),
GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU_CAB1TO2,
"ipu_conn_ipu_cab1to2", "dsp1_sel", 6),
GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU1_CAB1TO2,
"ipu_conn_ipu1_cab1to2", "dsp1_sel", 13),
GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU2_CAB1TO2,
"ipu_conn_ipu2_cab1to2", "dsp1_sel", 20),
GATE_IPU_CONN_AXI1_I(CLK_IPU_CONN_CAB3TO3,
"ipu_conn_cab3to3", "dsp1_sel", 0),
GATE_IPU_CONN_AXI2_I(CLK_IPU_CONN_CAB2TO1,
"ipu_conn_cab2to1", "dsp1_sel", 14),
GATE_IPU_CONN_AXI2_I(CLK_IPU_CONN_CAB3TO1_SLICE,
"ipu_conn_cab3to1_slice", "dsp1_sel", 17),
};
static const struct mtk_clk_desc ipu_conn_desc = {
.clks = ipu_conn_clks,
.num_clks = ARRAY_SIZE(ipu_conn_clks),
};
static const struct of_device_id of_match_clk_mt8183_ipu_conn[] = {
{
.compatible = "mediatek,mt8183-ipu_conn",
.data = &ipu_conn_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_ipu_conn);
static struct platform_driver clk_mt8183_ipu_conn_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8183-ipu_conn",
.of_match_table = of_match_clk_mt8183_ipu_conn,
},
};
module_platform_driver(clk_mt8183_ipu_conn_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8183-ipu_conn.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Wendell Lin <[email protected]>
*/
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt6779-clk.h>
static const struct mtk_gate_regs audio0_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x0,
.sta_ofs = 0x0,
};
static const struct mtk_gate_regs audio1_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x4,
.sta_ofs = 0x4,
};
#define GATE_AUDIO0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
&mtk_clk_gate_ops_no_setclr)
#define GATE_AUDIO1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, \
&mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate audio_clks[] = {
/* AUDIO0 */
GATE_AUDIO0(CLK_AUD_AFE, "aud_afe", "audio_sel", 2),
GATE_AUDIO0(CLK_AUD_22M, "aud_22m", "aud_eng1_sel", 8),
GATE_AUDIO0(CLK_AUD_24M, "aud_24m", "aud_eng2_sel", 9),
GATE_AUDIO0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner",
"aud_eng2_sel", 18),
GATE_AUDIO0(CLK_AUD_APLL_TUNER, "aud_apll_tuner",
"aud_eng1_sel", 19),
GATE_AUDIO0(CLK_AUD_TDM, "aud_tdm", "aud_eng1_sel", 20),
GATE_AUDIO0(CLK_AUD_ADC, "aud_adc", "audio_sel", 24),
GATE_AUDIO0(CLK_AUD_DAC, "aud_dac", "audio_sel", 25),
GATE_AUDIO0(CLK_AUD_DAC_PREDIS, "aud_dac_predis",
"audio_sel", 26),
GATE_AUDIO0(CLK_AUD_TML, "aud_tml", "audio_sel", 27),
GATE_AUDIO0(CLK_AUD_NLE, "aud_nle", "audio_sel", 28),
/* AUDIO1 */
GATE_AUDIO1(CLK_AUD_I2S1_BCLK_SW, "aud_i2s1_bclk",
"audio_sel", 4),
GATE_AUDIO1(CLK_AUD_I2S2_BCLK_SW, "aud_i2s2_bclk",
"audio_sel", 5),
GATE_AUDIO1(CLK_AUD_I2S3_BCLK_SW, "aud_i2s3_bclk",
"audio_sel", 6),
GATE_AUDIO1(CLK_AUD_I2S4_BCLK_SW, "aud_i2s4_bclk",
"audio_sel", 7),
GATE_AUDIO1(CLK_AUD_I2S5_BCLK_SW, "aud_i2s5_bclk",
"audio_sel", 8),
GATE_AUDIO1(CLK_AUD_CONN_I2S_ASRC, "aud_conn_i2s",
"audio_sel", 12),
GATE_AUDIO1(CLK_AUD_GENERAL1_ASRC, "aud_general1",
"audio_sel", 13),
GATE_AUDIO1(CLK_AUD_GENERAL2_ASRC, "aud_general2",
"audio_sel", 14),
GATE_AUDIO1(CLK_AUD_DAC_HIRES, "aud_dac_hires",
"audio_h_sel", 15),
GATE_AUDIO1(CLK_AUD_ADC_HIRES, "aud_adc_hires",
"audio_h_sel", 16),
GATE_AUDIO1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml",
"audio_h_sel", 17),
GATE_AUDIO1(CLK_AUD_PDN_ADDA6_ADC, "aud_pdn_adda6_adc",
"audio_sel", 20),
GATE_AUDIO1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires",
"audio_h_sel",
21),
GATE_AUDIO1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "audio_sel",
28),
GATE_AUDIO1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis",
"audio_sel", 29),
GATE_AUDIO1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml",
"audio_sel", 30),
GATE_AUDIO1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires",
"audio_h_sel", 31),
};
static const struct mtk_clk_desc audio_desc = {
.clks = audio_clks,
.num_clks = ARRAY_SIZE(audio_clks),
};
static const struct of_device_id of_match_clk_mt6779_aud[] = {
{
.compatible = "mediatek,mt6779-audio",
.data = &audio_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_aud);
static struct platform_driver clk_mt6779_aud_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt6779-aud",
.of_match_table = of_match_clk_mt6779_aud,
},
};
module_platform_driver(clk_mt6779_aud_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6779-aud.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8192-clk.h>
static const struct mtk_gate_regs vdec0_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x4,
.sta_ofs = 0x0,
};
static const struct mtk_gate_regs vdec1_cg_regs = {
.set_ofs = 0x200,
.clr_ofs = 0x204,
.sta_ofs = 0x200,
};
static const struct mtk_gate_regs vdec2_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0xc,
.sta_ofs = 0x8,
};
#define GATE_VDEC0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
#define GATE_VDEC1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
#define GATE_VDEC2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate vdec_clks[] = {
/* VDEC0 */
GATE_VDEC0(CLK_VDEC_VDEC, "vdec_vdec", "vdec_sel", 0),
GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "vdec_sel", 4),
/* VDEC1 */
GATE_VDEC1(CLK_VDEC_LAT, "vdec_lat", "vdec_sel", 0),
GATE_VDEC1(CLK_VDEC_LAT_ACTIVE, "vdec_lat_active", "vdec_sel", 4),
/* VDEC2 */
GATE_VDEC2(CLK_VDEC_LARB1, "vdec_larb1", "vdec_sel", 0),
};
static const struct mtk_gate vdec_soc_clks[] = {
/* VDEC_SOC0 */
GATE_VDEC0(CLK_VDEC_SOC_VDEC, "vdec_soc_vdec", "vdec_sel", 0),
GATE_VDEC0(CLK_VDEC_SOC_VDEC_ACTIVE, "vdec_soc_vdec_active", "vdec_sel", 4),
/* VDEC_SOC1 */
GATE_VDEC1(CLK_VDEC_SOC_LAT, "vdec_soc_lat", "vdec_sel", 0),
GATE_VDEC1(CLK_VDEC_SOC_LAT_ACTIVE, "vdec_soc_lat_active", "vdec_sel", 4),
/* VDEC_SOC2 */
GATE_VDEC2(CLK_VDEC_SOC_LARB1, "vdec_soc_larb1", "vdec_sel", 0),
};
static const struct mtk_clk_desc vdec_desc = {
.clks = vdec_clks,
.num_clks = ARRAY_SIZE(vdec_clks),
};
static const struct mtk_clk_desc vdec_soc_desc = {
.clks = vdec_soc_clks,
.num_clks = ARRAY_SIZE(vdec_soc_clks),
};
static const struct of_device_id of_match_clk_mt8192_vdec[] = {
{
.compatible = "mediatek,mt8192-vdecsys",
.data = &vdec_desc,
}, {
.compatible = "mediatek,mt8192-vdecsys_soc",
.data = &vdec_soc_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_vdec);
static struct platform_driver clk_mt8192_vdec_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8192-vdec",
.of_match_table = of_match_clk_mt8192_vdec,
},
};
module_platform_driver(clk_mt8192_vdec_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8192-vdec.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-mux.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
static DEFINE_SPINLOCK(mt8195_clk_lock);
static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK(CLK_TOP_IN_DGI, "in_dgi", NULL, 165000000),
FIXED_CLK(CLK_TOP_ULPOSC1, "ulposc1", NULL, 248000000),
FIXED_CLK(CLK_TOP_ULPOSC2, "ulposc2", NULL, 326000000),
FIXED_CLK(CLK_TOP_MEM_466M, "mem_466m", NULL, 533000000),
FIXED_CLK(CLK_TOP_MPHONE_SLAVE_B, "mphone_slave_b", NULL, 49152000),
FIXED_CLK(CLK_TOP_PEXTP_PIPE, "pextp_pipe", NULL, 250000000),
FIXED_CLK(CLK_TOP_UFS_RX_SYMBOL, "ufs_rx_symbol", NULL, 166000000),
FIXED_CLK(CLK_TOP_UFS_TX_SYMBOL, "ufs_tx_symbol", NULL, 166000000),
FIXED_CLK(CLK_TOP_SSUSB_U3PHY_P1_P_P0, "ssusb_u3phy_p1_p_p0", NULL, 131000000),
FIXED_CLK(CLK_TOP_UFS_RX_SYMBOL1, "ufs_rx_symbol1", NULL, 166000000),
FIXED_CLK(CLK_TOP_FPC, "fpc", NULL, 50000000),
FIXED_CLK(CLK_TOP_HDMIRX_P, "hdmirx_p", NULL, 594000000),
};
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", "clk26m", 1, 52),
FACTOR(CLK_TOP_IN_DGI_D2, "in_dgi_d2", "in_dgi", 1, 2),
FACTOR(CLK_TOP_IN_DGI_D4, "in_dgi_d4", "in_dgi", 1, 4),
FACTOR(CLK_TOP_IN_DGI_D6, "in_dgi_d6", "in_dgi", 1, 6),
FACTOR(CLK_TOP_IN_DGI_D8, "in_dgi_d8", "in_dgi", 1, 8),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll_d6", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32, 0),
FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1", 1, 3),
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2", 1, 3),
FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
FACTOR(CLK_TOP_APLL3_D4, "apll3_d4", "apll3", 1, 4),
FACTOR(CLK_TOP_APLL4_D4, "apll4_d4", "apll4", 1, 4),
FACTOR(CLK_TOP_APLL5_D4, "apll5_d4", "apll5", 1, 4),
FACTOR(CLK_TOP_HDMIRX_APLL_D3, "hdmirx_apll_d3", "hdmirx_apll", 1, 3),
FACTOR(CLK_TOP_HDMIRX_APLL_D4, "hdmirx_apll_d4", "hdmirx_apll", 1, 4),
FACTOR(CLK_TOP_HDMIRX_APLL_D6, "hdmirx_apll_d6", "hdmirx_apll", 1, 6),
FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4),
FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2),
FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9),
FACTOR(CLK_TOP_TVDPLL1_D2, "tvdpll1_d2", "tvdpll1", 1, 2),
FACTOR(CLK_TOP_TVDPLL1_D4, "tvdpll1_d4", "tvdpll1", 1, 4),
FACTOR(CLK_TOP_TVDPLL1_D8, "tvdpll1_d8", "tvdpll1", 1, 8),
FACTOR(CLK_TOP_TVDPLL1_D16, "tvdpll1_d16", "tvdpll1", 1, 16),
FACTOR(CLK_TOP_TVDPLL2_D2, "tvdpll2_d2", "tvdpll2", 1, 2),
FACTOR(CLK_TOP_TVDPLL2_D4, "tvdpll2_d4", "tvdpll2", 1, 4),
FACTOR(CLK_TOP_TVDPLL2_D8, "tvdpll2_d8", "tvdpll2", 1, 8),
FACTOR(CLK_TOP_TVDPLL2_D16, "tvdpll2_d16", "tvdpll2", 1, 16),
FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
FACTOR(CLK_TOP_ETHPLL_D2, "ethpll_d2", "ethpll", 1, 2),
FACTOR(CLK_TOP_ETHPLL_D8, "ethpll_d8", "ethpll", 1, 8),
FACTOR(CLK_TOP_ETHPLL_D10, "ethpll_d10", "ethpll", 1, 10),
FACTOR(CLK_TOP_DGIPLL_D2, "dgipll_d2", "dgipll", 1, 2),
FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc1", 1, 2),
FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc1", 1, 4),
FACTOR(CLK_TOP_ULPOSC1_D7, "ulposc1_d7", "ulposc1", 1, 7),
FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc1", 1, 8),
FACTOR(CLK_TOP_ULPOSC1_D10, "ulposc1_d10", "ulposc1", 1, 10),
FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc1", 1, 16),
FACTOR(CLK_TOP_ADSPPLL_D2, "adsppll_d2", "adsppll", 1, 2),
FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
FACTOR(CLK_TOP_ADSPPLL_D8, "adsppll_d8", "adsppll", 1, 8),
};
static const char * const axi_parents[] = {
"clk26m",
"mainpll_d4_d4",
"mainpll_d7_d2",
"mainpll_d4_d2",
"mainpll_d5_d2",
"mainpll_d6_d2",
"ulposc1_d4"
};
static const char * const spm_parents[] = {
"clk26m",
"ulposc1_d10",
"mainpll_d7_d4",
"clk32k"
};
static const char * const scp_parents[] = {
"clk26m",
"univpll_d4",
"mainpll_d6",
"univpll_d6",
"univpll_d4_d2",
"mainpll_d4_d2",
"mainpll_d4",
"mainpll_d6_d2"
};
static const char * const bus_aximem_parents[] = {
"clk26m",
"mainpll_d7_d2",
"mainpll_d4_d2",
"mainpll_d5_d2",
"mainpll_d6"
};
static const char * const vpp_parents[] = {
"clk26m",
"univpll_d6_d2",
"mainpll_d5_d2",
"mmpll_d6_d2",
"univpll_d5_d2",
"univpll_d4_d2",
"mmpll_d4_d2",
"mmpll_d7",
"univpll_d6",
"mainpll_d4",
"mmpll_d5",
"tvdpll1",
"tvdpll2",
"univpll_d4",
"mmpll_d4"
};
static const char * const ethdr_parents[] = {
"clk26m",
"univpll_d6_d2",
"mainpll_d5_d2",
"mmpll_d6_d2",
"univpll_d5_d2",
"univpll_d4_d2",
"mmpll_d4_d2",
"mmpll_d7",
"univpll_d6",
"mainpll_d4",
"mmpll_d5_d4",
"tvdpll1",
"tvdpll2",
"univpll_d4",
"mmpll_d4"
};
static const char * const ipe_parents[] = {
"clk26m",
"imgpll",
"mainpll_d4",
"mmpll_d6",
"univpll_d6",
"mainpll_d6",
"mmpll_d4_d2",
"univpll_d4_d2",
"mainpll_d4_d2",
"mmpll_d6_d2",
"univpll_d5_d2"
};
static const char * const cam_parents[] = {
"clk26m",
"mainpll_d4",
"mmpll_d4",
"univpll_d4",
"univpll_d5",
"univpll_d6",
"mmpll_d7",
"univpll_d4_d2",
"mainpll_d4_d2",
"imgpll"
};
static const char * const ccu_parents[] = {
"clk26m",
"univpll_d6",
"mainpll_d4_d2",
"mainpll_d4",
"univpll_d5",
"mainpll_d6",
"mmpll_d6",
"mmpll_d7",
"univpll_d4_d2",
"univpll_d7"
};
static const char * const img_parents[] = {
"clk26m",
"imgpll",
"univpll_d4",
"mainpll_d4",
"univpll_d5",
"mmpll_d6",
"univpll_d6",
"mainpll_d6",
"mmpll_d4_d2",
"univpll_d4_d2",
"mainpll_d4_d2",
"univpll_d5_d2"
};
static const char * const camtm_parents[] = {
"clk26m",
"univpll_d4_d4",
"univpll_d6_d2",
"univpll_d6_d4"
};
static const char * const dsp_parents[] = {
"clk26m",
"univpll_d6_d2",
"univpll_d4_d2",
"univpll_d5",
"univpll_d4",
"mmpll_d4",
"mainpll_d3",
"univpll_d3"
};
static const char * const dsp1_parents[] = {
"clk26m",
"univpll_d6_d2",
"mainpll_d4_d2",
"univpll_d5",
"mmpll_d5",
"univpll_d4",
"mainpll_d3",
"univpll_d3"
};
static const char * const dsp2_parents[] = {
"clk26m",
"univpll_d6_d2",
"univpll_d4_d2",
"mainpll_d4",
"univpll_d4",
"mmpll_d4",
"mainpll_d3",
"univpll_d3"
};
static const char * const ipu_if_parents[] = {
"clk26m",
"univpll_d6_d2",
"univpll_d5_d2",
"mainpll_d4_d2",
"mainpll_d6",
"univpll_d5",
"univpll_d4",
"mmpll_d4"
};
/*
* MFG can be also parented to "univpll_d6" and "univpll_d7":
* these have been removed from the parents list to let us
* achieve GPU DVFS without any special clock handlers.
*/
static const char * const mfg_parents[] = {
"clk26m",
"mainpll_d5_d2"
};
static const char * const camtg_parents[] = {
"clk26m",
"univpll_192m_d8",
"univpll_d6_d8",
"univpll_192m_d4",
"univpll_d6_d16",
"clk26m_d2",
"univpll_192m_d16",
"univpll_192m_d32"
};
static const char * const uart_parents[] = {
"clk26m",
"univpll_d6_d8"
};
static const char * const spi_parents[] = {
"clk26m",
"mainpll_d5_d4",
"mainpll_d6_d4",
"msdcpll_d4",
"univpll_d6_d2",
"mainpll_d6_d2",
"mainpll_d4_d4",
"univpll_d5_d4"
};
static const char * const spis_parents[] = {
"clk26m",
"univpll_d6",
"mainpll_d6",
"univpll_d4_d2",
"univpll_d6_d2",
"univpll_d4_d4",
"univpll_d6_d4",
"mainpll_d7_d4"
};
static const char * const msdc50_0_h_parents[] = {
"clk26m",
"mainpll_d4_d2",
"mainpll_d6_d2"
};
static const char * const msdc50_0_parents[] = {
"clk26m",
"msdcpll",
"msdcpll_d2",
"univpll_d4_d4",
"mainpll_d6_d2",
"univpll_d4_d2"
};
static const char * const msdc30_parents[] = {
"clk26m",
"univpll_d6_d2",
"mainpll_d6_d2",
"mainpll_d7_d2",
"msdcpll_d2"
};
static const char * const intdir_parents[] = {
"clk26m",
"univpll_d6",
"mainpll_d4",
"univpll_d4"
};
static const char * const aud_intbus_parents[] = {
"clk26m",
"mainpll_d4_d4",
"mainpll_d7_d4"
};
static const char * const audio_h_parents[] = {
"clk26m",
"univpll_d7",
"apll1",
"apll2"
};
static const char * const pwrap_ulposc_parents[] = {
"ulposc1_d10",
"clk26m",
"ulposc1_d4",
"ulposc1_d7",
"ulposc1_d8",
"ulposc1_d16",
"mainpll_d4_d8",
"univpll_d5_d8"
};
static const char * const atb_parents[] = {
"clk26m",
"mainpll_d4_d2",
"mainpll_d5_d2"
};
static const char * const pwrmcu_parents[] = {
"clk26m",
"mainpll_d7_d2",
"mainpll_d6_d2",
"mainpll_d5_d2",
"mainpll_d9",
"mainpll_d4_d2"
};
static const char * const dp_parents[] = {
"clk26m",
"tvdpll1_d2",
"tvdpll2_d2",
"tvdpll1_d4",
"tvdpll2_d4",
"tvdpll1_d8",
"tvdpll2_d8",
"tvdpll1_d16",
"tvdpll2_d16"
};
static const char * const disp_pwm_parents[] = {
"clk26m",
"univpll_d6_d4",
"ulposc1_d2",
"ulposc1_d4",
"ulposc1_d16"
};
static const char * const usb_parents[] = {
"clk26m",
"univpll_d5_d4",
"univpll_d6_d4",
"univpll_d5_d2"
};
static const char * const i2c_parents[] = {
"clk26m",
"mainpll_d4_d8",
"univpll_d5_d4"
};
static const char * const seninf_parents[] = {
"clk26m",
"univpll_d4_d4",
"univpll_d6_d2",
"univpll_d4_d2",
"univpll_d7",
"univpll_d6",
"mmpll_d6",
"univpll_d5"
};
static const char * const gcpu_parents[] = {
"clk26m",
"mainpll_d6",
"univpll_d4_d2",
"mmpll_d5_d2",
"univpll_d5_d2"
};
static const char * const dxcc_parents[] = {
"clk26m",
"mainpll_d4_d2",
"mainpll_d4_d4",
"mainpll_d4_d8"
};
static const char * const dpmaif_parents[] = {
"clk26m",
"univpll_d4_d4",
"mainpll_d6",
"mainpll_d4_d2",
"univpll_d4_d2"
};
static const char * const aes_fde_parents[] = {
"clk26m",
"mainpll_d4_d2",
"mainpll_d6",
"mainpll_d4_d4",
"univpll_d4_d2",
"univpll_d6"
};
static const char * const ufs_parents[] = {
"clk26m",
"mainpll_d4_d4",
"mainpll_d4_d8",
"univpll_d4_d4",
"mainpll_d6_d2",
"univpll_d6_d2",
"msdcpll_d2"
};
static const char * const ufs_tick1us_parents[] = {
"clk26m_d52",
"clk26m"
};
static const char * const ufs_mp_sap_parents[] = {
"clk26m",
"msdcpll_d16"
};
static const char * const venc_parents[] = {
"clk26m",
"mmpll_d4_d2",
"mainpll_d6",
"univpll_d4_d2",
"mainpll_d4_d2",
"univpll_d6",
"mmpll_d6",
"mainpll_d5_d2",
"mainpll_d6_d2",
"mmpll_d9",
"univpll_d4_d4",
"mainpll_d4",
"univpll_d4",
"univpll_d5",
"univpll_d5_d2",
"mainpll_d5"
};
static const char * const vdec_parents[] = {
"clk26m",
"mainpll_d5_d2",
"mmpll_d6_d2",
"univpll_d4_d2",
"mmpll_d4_d2",
"mainpll_d5",
"mmpll_d6",
"mmpll_d5",
"vdecpll",
"univpll_d4",
"mmpll_d4",
"univpll_d6_d2",
"mmpll_d9",
"univpll_d6",
"univpll_d5",
"mainpll_d4"
};
static const char * const pwm_parents[] = {
"clk26m",
"univpll_d4_d8"
};
static const char * const mcupm_parents[] = {
"clk26m",
"mainpll_d6_d2",
"mainpll_d7_d4",
};
static const char * const spmi_parents[] = {
"clk26m",
"clk26m_d2",
"ulposc1_d8",
"ulposc1_d10",
"ulposc1_d16",
"ulposc1_d7",
"clk32k",
"mainpll_d7_d8",
"mainpll_d6_d8",
"mainpll_d5_d8"
};
static const char * const dvfsrc_parents[] = {
"clk26m",
"ulposc1_d10",
"univpll_d6_d8",
"msdcpll_d16"
};
static const char * const tl_parents[] = {
"clk26m",
"univpll_d5_d4",
"mainpll_d4_d4"
};
static const char * const dsi_occ_parents[] = {
"clk26m",
"mainpll_d6_d2",
"univpll_d5_d2",
"univpll_d4_d2"
};
static const char * const wpe_vpp_parents[] = {
"clk26m",
"mainpll_d5_d2",
"mmpll_d6_d2",
"univpll_d5_d2",
"mainpll_d4_d2",
"univpll_d4_d2",
"mmpll_d4_d2",
"mainpll_d6",
"mmpll_d7",
"univpll_d6",
"mainpll_d5",
"univpll_d5",
"mainpll_d4",
"tvdpll1",
"univpll_d4"
};
static const char * const hdcp_parents[] = {
"clk26m",
"univpll_d4_d8",
"mainpll_d5_d8",
"univpll_d6_d4"
};
static const char * const hdcp_24m_parents[] = {
"clk26m",
"univpll_192m_d4",
"univpll_192m_d8",
"univpll_d6_d8"
};
static const char * const hd20_dacr_ref_parents[] = {
"clk26m",
"univpll_d4_d2",
"univpll_d4_d4",
"univpll_d4_d8"
};
static const char * const hd20_hdcp_c_parents[] = {
"clk26m",
"msdcpll_d4",
"univpll_d4_d8",
"univpll_d6_d8"
};
static const char * const hdmi_xtal_parents[] = {
"clk26m",
"clk26m_d2"
};
static const char * const hdmi_apb_parents[] = {
"clk26m",
"univpll_d6_d4",
"msdcpll_d2"
};
static const char * const snps_eth_250m_parents[] = {
"clk26m",
"ethpll_d2"
};
static const char * const snps_eth_62p4m_ptp_parents[] = {
"apll2_d3",
"apll1_d3",
"clk26m",
"ethpll_d8"
};
static const char * const snps_eth_50m_rmii_parents[] = {
"clk26m",
"ethpll_d10"
};
static const char * const dgi_out_parents[] = {
"clk26m",
"dgipll",
"dgipll_d2",
"in_dgi",
"in_dgi_d2",
"mmpll_d4_d4"
};
static const char * const nna_parents[] = {
"clk26m",
"nnapll",
"univpll_d4",
"mainpll_d4",
"univpll_d5",
"mmpll_d6",
"univpll_d6",
"mainpll_d6",
"mmpll_d4_d2",
"univpll_d4_d2",
"mainpll_d4_d2",
"mmpll_d6_d2"
};
static const char * const adsp_parents[] = {
"clk26m",
"clk26m_d2",
"mainpll_d6",
"mainpll_d5_d2",
"univpll_d4_d4",
"univpll_d4",
"univpll_d6",
"ulposc1",
"adsppll",
"adsppll_d2",
"adsppll_d4",
"adsppll_d8"
};
static const char * const asm_parents[] = {
"clk26m",
"univpll_d6_d4",
"univpll_d6_d2",
"mainpll_d5_d2"
};
static const char * const apll1_parents[] = {
"clk26m",
"apll1_d4"
};
static const char * const apll2_parents[] = {
"clk26m",
"apll2_d4"
};
static const char * const apll3_parents[] = {
"clk26m",
"apll3_d4"
};
static const char * const apll4_parents[] = {
"clk26m",
"apll4_d4"
};
static const char * const apll5_parents[] = {
"clk26m",
"apll5_d4"
};
static const char * const i2s_parents[] = {
"clk26m",
"apll1",
"apll2",
"apll3",
"apll4",
"apll5",
"hdmirx_apll"
};
static const char * const a1sys_hp_parents[] = {
"clk26m",
"apll1_d4"
};
static const char * const a2sys_parents[] = {
"clk26m",
"apll2_d4"
};
static const char * const a3sys_parents[] = {
"clk26m",
"apll3_d4",
"apll4_d4",
"apll5_d4",
"hdmirx_apll_d3",
"hdmirx_apll_d4",
"hdmirx_apll_d6"
};
static const char * const spinfi_b_parents[] = {
"clk26m",
"univpll_d6_d8",
"univpll_d5_d8",
"mainpll_d4_d8",
"mainpll_d7_d4",
"mainpll_d6_d4",
"univpll_d6_d4",
"univpll_d5_d4"
};
static const char * const nfi1x_parents[] = {
"clk26m",
"univpll_d5_d4",
"mainpll_d7_d4",
"mainpll_d6_d4",
"univpll_d6_d4",
"mainpll_d4_d4",
"mainpll_d7_d2",
"mainpll_d6_d2"
};
static const char * const ecc_parents[] = {
"clk26m",
"mainpll_d4_d4",
"mainpll_d5_d2",
"mainpll_d4_d2",
"mainpll_d6",
"univpll_d6"
};
static const char * const audio_local_bus_parents[] = {
"clk26m",
"clk26m_d2",
"mainpll_d4_d4",
"mainpll_d7_d2",
"mainpll_d4_d2",
"mainpll_d5_d2",
"mainpll_d6_d2",
"mainpll_d7",
"univpll_d6",
"ulposc1",
"ulposc1_d4",
"ulposc1_d2"
};
static const char * const spinor_parents[] = {
"clk26m",
"clk26m_d2",
"mainpll_d7_d8",
"univpll_d6_d8"
};
static const char * const dvio_dgi_ref_parents[] = {
"clk26m",
"in_dgi",
"in_dgi_d2",
"in_dgi_d4",
"in_dgi_d6",
"in_dgi_d8",
"mmpll_d4_d4"
};
static const char * const ulposc_parents[] = {
"ulposc1",
"ethpll_d2",
"mainpll_d4_d2",
"ethpll_d10"
};
static const char * const ulposc_core_parents[] = {
"ulposc2",
"univpll_d7",
"mainpll_d6",
"ethpll_d10"
};
static const char * const srck_parents[] = {
"ulposc1_d10",
"clk26m"
};
static const char * const mfg_fast_parents[] = {
"top_mfg_core_tmp",
"mfgpll"
};
static const struct mtk_mux top_mtk_muxes[] = {
/*
* CLK_CFG_0
* top_axi and top_bus_aximem are bus clocks, should not be closed by Linux.
* top_spm and top_scp are main clocks in always-on co-processor.
*/
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi",
axi_parents, 0x020, 0x024, 0x028, 0, 3, 7, 0x04, 0,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm",
spm_parents, 0x020, 0x024, 0x028, 8, 2, 15, 0x04, 1,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp",
scp_parents, 0x020, 0x024, 0x028, 16, 3, 23, 0x04, 2,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM, "top_bus_aximem",
bus_aximem_parents, 0x020, 0x024, 0x028, 24, 3, 31, 0x04, 3,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
/* CLK_CFG_1 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp",
vpp_parents, 0x02C, 0x030, 0x034, 0, 4, 7, 0x04, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETHDR, "top_ethdr",
ethdr_parents, 0x02C, 0x030, 0x034, 8, 4, 15, 0x04, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
ipe_parents, 0x02C, 0x030, 0x034, 16, 4, 23, 0x04, 6),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
cam_parents, 0x02C, 0x030, 0x034, 24, 4, 31, 0x04, 7),
/* CLK_CFG_2 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "top_ccu",
ccu_parents, 0x038, 0x03C, 0x040, 0, 4, 7, 0x04, 8),
MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "top_img",
img_parents, 0x038, 0x03C, 0x040, 8, 4, 15, 0x04, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
camtm_parents, 0x038, 0x03C, 0x040, 16, 2, 23, 0x04, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "top_dsp",
dsp_parents, 0x038, 0x03C, 0x040, 24, 3, 31, 0x04, 11),
/* CLK_CFG_3 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "top_dsp1",
dsp1_parents, 0x044, 0x048, 0x04C, 0, 3, 7, 0x04, 12),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "top_dsp2",
dsp1_parents, 0x044, 0x048, 0x04C, 8, 3, 15, 0x04, 13),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "top_dsp3",
dsp1_parents, 0x044, 0x048, 0x04C, 16, 3, 23, 0x04, 14),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP4, "top_dsp4",
dsp2_parents, 0x044, 0x048, 0x04C, 24, 3, 31, 0x04, 15),
/* CLK_CFG_4 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5, "top_dsp5",
dsp2_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x04, 16),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP6, "top_dsp6",
dsp2_parents, 0x050, 0x054, 0x058, 8, 3, 15, 0x04, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7, "top_dsp7",
dsp_parents, 0x050, 0x054, 0x058, 16, 3, 23, 0x04, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF, "top_ipu_if",
ipu_if_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x04, 19),
/* CLK_CFG_5 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_CORE_TMP, "top_mfg_core_tmp",
mfg_parents, 0x05C, 0x060, 0x064, 0, 2, 7, 0x04, 20),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
camtg_parents, 0x05C, 0x060, 0x064, 8, 3, 15, 0x04, 21),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2",
camtg_parents, 0x05C, 0x060, 0x064, 16, 3, 23, 0x04, 22),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3",
camtg_parents, 0x05C, 0x060, 0x064, 24, 3, 31, 0x04, 23),
/* CLK_CFG_6 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "top_camtg4",
camtg_parents, 0x068, 0x06C, 0x070, 0, 3, 7, 0x04, 24),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "top_camtg5",
camtg_parents, 0x068, 0x06C, 0x070, 8, 3, 15, 0x04, 25),
MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart",
uart_parents, 0x068, 0x06C, 0x070, 16, 1, 23, 0x04, 26),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
spi_parents, 0x068, 0x06C, 0x070, 24, 3, 31, 0x04, 27),
/* CLK_CFG_7 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIS, "top_spis",
spis_parents, 0x074, 0x078, 0x07C, 0, 3, 7, 0x04, 28),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "top_msdc50_0_hclk",
msdc50_0_h_parents, 0x074, 0x078, 0x07C, 8, 2, 15, 0x04, 29, 0),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0",
msdc50_0_parents, 0x074, 0x078, 0x07C, 16, 3, 23, 0x04, 30, 0),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "top_msdc30_1",
msdc30_parents, 0x074, 0x078, 0x07C, 24, 3, 31, 0x04, 31, 0),
/* CLK_CFG_8 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_2, "top_msdc30_2",
msdc30_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x08, 0, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir",
intdir_parents, 0x080, 0x084, 0x088, 8, 2, 15, 0x08, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
aud_intbus_parents, 0x080, 0x084, 0x088, 16, 2, 23, 0x08, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H, "top_audio_h",
audio_h_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x08, 3),
/*
* CLK_CFG_9
* top_pwrmcu is main clock in other co-processor, should not be
* handled by Linux.
*/
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC, "top_pwrap_ulposc",
pwrap_ulposc_parents, 0x08C, 0x090, 0x094, 0, 3, 7, 0x08, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "top_atb",
atb_parents, 0x08C, 0x090, 0x094, 8, 2, 15, 0x08, 5),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRMCU, "top_pwrmcu",
pwrmcu_parents, 0x08C, 0x090, 0x094, 16, 3, 23, 0x08, 6,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp",
dp_parents, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7),
/* CLK_CFG_10 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP, "top_edp",
dp_parents, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",
dp_parents, 0x098, 0x09C, 0x0A0, 8, 4, 15, 0x08, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",
disp_pwm_parents, 0x098, 0x09C, 0x0A0, 16, 3, 23, 0x08, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM1, "top_disp_pwm1",
disp_pwm_parents, 0x098, 0x09C, 0x0A0, 24, 3, 31, 0x08, 11),
/* CLK_CFG_11 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "top_usb_top",
usb_parents, 0x0A4, 0x0A8, 0x0AC, 0, 2, 7, 0x08, 12),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI, "top_ssusb_xhci",
usb_parents, 0x0A4, 0x0A8, 0x0AC, 8, 2, 15, 0x08, 13),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_1P, "top_usb_top_1p",
usb_parents, 0x0A4, 0x0A8, 0x0AC, 16, 2, 23, 0x08, 14),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_1P, "top_ssusb_xhci_1p",
usb_parents, 0x0A4, 0x0A8, 0x0AC, 24, 2, 31, 0x08, 15),
/* CLK_CFG_12 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_2P, "top_usb_top_2p",
usb_parents, 0x0B0, 0x0B4, 0x0B8, 0, 2, 7, 0x08, 16),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_2P, "top_ssusb_xhci_2p",
usb_parents, 0x0B0, 0x0B4, 0x0B8, 8, 2, 15, 0x08, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_3P, "top_usb_top_3p",
usb_parents, 0x0B0, 0x0B4, 0x0B8, 16, 2, 23, 0x08, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_3P, "top_ssusb_xhci_3p",
usb_parents, 0x0B0, 0x0B4, 0x0B8, 24, 2, 31, 0x08, 19),
/* CLK_CFG_13 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c",
i2c_parents, 0x0BC, 0x0C0, 0x0C4, 0, 2, 7, 0x08, 20),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "top_seninf",
seninf_parents, 0x0BC, 0x0C0, 0x0C4, 8, 3, 15, 0x08, 21),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "top_seninf1",
seninf_parents, 0x0BC, 0x0C0, 0x0C4, 16, 3, 23, 0x08, 22),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "top_seninf2",
seninf_parents, 0x0BC, 0x0C0, 0x0C4, 24, 3, 31, 0x08, 23),
/* CLK_CFG_14 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3, "top_seninf3",
seninf_parents, 0x0C8, 0x0CC, 0x0D0, 0, 3, 7, 0x08, 24),
MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU, "top_gcpu",
gcpu_parents, 0x0C8, 0x0CC, 0x0D0, 8, 3, 15, 0x08, 25),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "top_dxcc",
dxcc_parents, 0x0C8, 0x0CC, 0x0D0, 16, 2, 23, 0x08, 26),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN, "top_dpmaif_main",
dpmaif_parents, 0x0C8, 0x0CC, 0x0D0, 24, 3, 31, 0x08, 27),
/* CLK_CFG_15 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE, "top_aes_ufsfde",
aes_fde_parents, 0x0D4, 0x0D8, 0x0DC, 0, 3, 7, 0x08, 28),
MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS, "top_ufs",
ufs_parents, 0x0D4, 0x0D8, 0x0DC, 8, 3, 15, 0x08, 29),
MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_TICK1US, "top_ufs_tick1us",
ufs_tick1us_parents, 0x0D4, 0x0D8, 0x0DC, 16, 1, 23, 0x08, 30),
MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_MP_SAP_CFG, "top_ufs_mp_sap_cfg",
ufs_mp_sap_parents, 0x0D4, 0x0D8, 0x0DC, 24, 1, 31, 0x08, 31),
/*
* CLK_CFG_16
* top_mcupm is main clock in other co-processor, should not be
* handled by Linux.
*/
MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "top_venc",
venc_parents, 0x0E0, 0x0E4, 0x0E8, 0, 4, 7, 0x0C, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "top_vdec",
vdec_parents, 0x0E0, 0x0E4, 0x0E8, 8, 4, 15, 0x0C, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm",
pwm_parents, 0x0E0, 0x0E4, 0x0E8, 16, 1, 23, 0x0C, 2),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MCUPM, "top_mcupm",
mcupm_parents, 0x0E0, 0x0E4, 0x0E8, 24, 2, 31, 0x0C, 3,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
/*
* CLK_CFG_17
* top_dvfsrc is for internal DVFS usage, should not be handled by Linux.
*/
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_P_MST, "top_spmi_p_mst",
spmi_parents, 0x0EC, 0x0F0, 0x0F4, 0, 4, 7, 0x0C, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST, "top_spmi_m_mst",
spmi_parents, 0x0EC, 0x0F0, 0x0F4, 8, 4, 15, 0x0C, 5),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc",
dvfsrc_parents, 0x0EC, 0x0F0, 0x0F4, 16, 2, 23, 0x0C, 6,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD(CLK_TOP_TL, "top_tl",
tl_parents, 0x0EC, 0x0F0, 0x0F4, 24, 2, 31, 0x0C, 7),
/* CLK_CFG_18 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_P1, "top_tl_p1",
tl_parents, 0x0F8, 0x0FC, 0x0100, 0, 2, 7, 0x0C, 8),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE, "top_aes_msdcfde",
aes_fde_parents, 0x0F8, 0x0FC, 0x0100, 8, 3, 15, 0x0C, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ",
dsi_occ_parents, 0x0F8, 0x0FC, 0x0100, 16, 2, 23, 0x0C, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE_VPP, "top_wpe_vpp",
wpe_vpp_parents, 0x0F8, 0x0FC, 0x0100, 24, 4, 31, 0x0C, 11),
/* CLK_CFG_19 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP, "top_hdcp",
hdcp_parents, 0x0104, 0x0108, 0x010C, 0, 2, 7, 0x0C, 12),
MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP_24M, "top_hdcp_24m",
hdcp_24m_parents, 0x0104, 0x0108, 0x010C, 8, 2, 15, 0x0C, 13),
MUX_GATE_CLR_SET_UPD(CLK_TOP_HD20_DACR_REF_CLK, "top_hd20_dacr_ref_clk",
hd20_dacr_ref_parents, 0x0104, 0x0108, 0x010C, 16, 2, 23, 0x0C, 14),
MUX_GATE_CLR_SET_UPD(CLK_TOP_HD20_HDCP_CCLK, "top_hd20_hdcp_cclk",
hd20_hdcp_c_parents, 0x0104, 0x0108, 0x010C, 24, 2, 31, 0x0C, 15),
/* CLK_CFG_20 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_XTAL, "top_hdmi_xtal",
hdmi_xtal_parents, 0x0110, 0x0114, 0x0118, 0, 1, 7, 0x0C, 16),
MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_APB, "top_hdmi_apb",
hdmi_apb_parents, 0x0110, 0x0114, 0x0118, 8, 2, 15, 0x0C, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M, "top_snps_eth_250m",
snps_eth_250m_parents, 0x0110, 0x0114, 0x0118, 16, 1, 23, 0x0C, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP, "top_snps_eth_62p4m_ptp",
snps_eth_62p4m_ptp_parents, 0x0110, 0x0114, 0x0118, 24, 2, 31, 0x0C, 19),
/* CLK_CFG_21 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII, "snps_eth_50m_rmii",
snps_eth_50m_rmii_parents, 0x011C, 0x0120, 0x0124, 0, 1, 7, 0x0C, 20),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DGI_OUT, "top_dgi_out",
dgi_out_parents, 0x011C, 0x0120, 0x0124, 8, 3, 15, 0x0C, 21),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA0, "top_nna0",
nna_parents, 0x011C, 0x0120, 0x0124, 16, 4, 23, 0x0C, 22),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA1, "top_nna1",
nna_parents, 0x011C, 0x0120, 0x0124, 24, 4, 31, 0x0C, 23),
/* CLK_CFG_22 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "top_adsp",
adsp_parents, 0x0128, 0x012C, 0x0130, 0, 4, 7, 0x0C, 24),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_H, "top_asm_h",
asm_parents, 0x0128, 0x012C, 0x0130, 8, 2, 15, 0x0C, 25),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_M, "top_asm_m",
asm_parents, 0x0128, 0x012C, 0x0130, 16, 2, 23, 0x0C, 26),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_L, "top_asm_l",
asm_parents, 0x0128, 0x012C, 0x0130, 24, 2, 31, 0x0C, 27),
/* CLK_CFG_23 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL1, "top_apll1",
apll1_parents, 0x0134, 0x0138, 0x013C, 0, 1, 7, 0x0C, 28),
MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL2, "top_apll2",
apll2_parents, 0x0134, 0x0138, 0x013C, 8, 1, 15, 0x0C, 29),
MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL3, "top_apll3",
apll3_parents, 0x0134, 0x0138, 0x013C, 16, 1, 23, 0x0C, 30),
MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL4, "top_apll4",
apll4_parents, 0x0134, 0x0138, 0x013C, 24, 1, 31, 0x0C, 31),
/*
* CLK_CFG_24
* i2so4_mck is not used in MT8195.
*/
MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL5, "top_apll5",
apll5_parents, 0x0140, 0x0144, 0x0148, 0, 1, 7, 0x010, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO1_MCK, "top_i2so1_mck",
i2s_parents, 0x0140, 0x0144, 0x0148, 8, 3, 15, 0x010, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO2_MCK, "top_i2so2_mck",
i2s_parents, 0x0140, 0x0144, 0x0148, 16, 3, 23, 0x010, 2),
/*
* CLK_CFG_25
* i2so5_mck and i2si4_mck are not used in MT8195.
*/
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI1_MCK, "top_i2si1_mck",
i2s_parents, 0x014C, 0x0150, 0x0154, 8, 3, 15, 0x010, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI2_MCK, "top_i2si2_mck",
i2s_parents, 0x014C, 0x0150, 0x0154, 16, 3, 23, 0x010, 6),
/*
* CLK_CFG_26
* i2si5_mck is not used in MT8195.
*/
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPTX_MCK, "top_dptx_mck",
i2s_parents, 0x0158, 0x015C, 0x0160, 8, 3, 15, 0x010, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_IEC_CLK, "top_aud_iec_clk",
i2s_parents, 0x0158, 0x015C, 0x0160, 16, 3, 23, 0x010, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_HP, "top_a1sys_hp",
a1sys_hp_parents, 0x0158, 0x015C, 0x0160, 24, 1, 31, 0x010, 11),
/* CLK_CFG_27 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_A2SYS_HF, "top_a2sys_hf",
a2sys_parents, 0x0164, 0x0168, 0x016C, 0, 1, 7, 0x010, 12),
MUX_GATE_CLR_SET_UPD(CLK_TOP_A3SYS_HF, "top_a3sys_hf",
a3sys_parents, 0x0164, 0x0168, 0x016C, 8, 3, 15, 0x010, 13),
MUX_GATE_CLR_SET_UPD(CLK_TOP_A4SYS_HF, "top_a4sys_hf",
a3sys_parents, 0x0164, 0x0168, 0x016C, 16, 3, 23, 0x010, 14),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_BCLK, "top_spinfi_bclk",
spinfi_b_parents, 0x0164, 0x0168, 0x016C, 24, 3, 31, 0x010, 15),
/* CLK_CFG_28 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X, "top_nfi1x",
nfi1x_parents, 0x0170, 0x0174, 0x0178, 0, 3, 7, 0x010, 16),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC, "top_ecc",
ecc_parents, 0x0170, 0x0174, 0x0178, 8, 3, 15, 0x010, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_LOCAL_BUS, "top_audio_local_bus",
audio_local_bus_parents, 0x0170, 0x0174, 0x0178, 16, 4, 23, 0x010, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor",
spinor_parents, 0x0170, 0x0174, 0x0178, 24, 2, 31, 0x010, 19),
/*
* CLK_CFG_29
* top_ulposc/top_ulposc_core/top_srck are clock source of always on co-processor,
* should not be closed by Linux.
*/
MUX_GATE_CLR_SET_UPD(CLK_TOP_DVIO_DGI_REF, "top_dvio_dgi_ref",
dvio_dgi_ref_parents, 0x017C, 0x0180, 0x0184, 0, 3, 7, 0x010, 20),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC, "top_ulposc",
ulposc_parents, 0x017C, 0x0180, 0x0184, 8, 2, 15, 0x010, 21,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC_CORE, "top_ulposc_core",
ulposc_core_parents, 0x017C, 0x0180, 0x0184, 16, 2, 23, 0x010, 22,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck",
srck_parents, 0x017C, 0x0180, 0x0184, 24, 1, 31, 0x010, 23,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
/*
* the clocks in CLK_CFG_30 ~ 37 are backup clock source, no need to handled
* by Linux.
*/
};
static const struct mtk_composite top_adj_divs[] = {
DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "top_i2si1_mck", 0x0320, 0, 0x0328, 8, 0),
DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "top_i2si2_mck", 0x0320, 1, 0x0328, 8, 8),
DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "top_i2so1_mck", 0x0320, 2, 0x0328, 8, 16),
DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "top_i2so2_mck", 0x0320, 3, 0x0328, 8, 24),
DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "top_aud_iec_clk", 0x0320, 4, 0x0334, 8, 0),
/* apll12_div5 ~ 8 are not used in MT8195. */
DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "top_dptx_mck", 0x0320, 9, 0x0338, 8, 8),
};
static const struct mtk_gate_regs top0_cg_regs = {
.set_ofs = 0x238,
.clr_ofs = 0x238,
.sta_ofs = 0x238,
};
static const struct mtk_gate_regs top1_cg_regs = {
.set_ofs = 0x250,
.clr_ofs = 0x250,
.sta_ofs = 0x250,
};
#define GATE_TOP0_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &top0_cg_regs, _shift, \
&mtk_clk_gate_ops_no_setclr_inv, _flag)
#define GATE_TOP0(_id, _name, _parent, _shift) \
GATE_TOP0_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_TOP1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate top_clks[] = {
/* TOP0 */
GATE_TOP0(CLK_TOP_CFG_VPP0, "cfg_vpp0", "top_vpp", 0),
GATE_TOP0(CLK_TOP_CFG_VPP1, "cfg_vpp1", "top_vpp", 1),
GATE_TOP0(CLK_TOP_CFG_VDO0, "cfg_vdo0", "top_vpp", 2),
GATE_TOP0(CLK_TOP_CFG_VDO1, "cfg_vdo1", "top_vpp", 3),
GATE_TOP0(CLK_TOP_CFG_UNIPLL_SES, "cfg_unipll_ses", "univpll_d2", 4),
GATE_TOP0(CLK_TOP_CFG_26M_VPP0, "cfg_26m_vpp0", "clk26m", 5),
GATE_TOP0(CLK_TOP_CFG_26M_VPP1, "cfg_26m_vpp1", "clk26m", 6),
GATE_TOP0(CLK_TOP_CFG_26M_AUD, "cfg_26m_aud", "clk26m", 9),
/*
* cfg_axi_east, cfg_axi_east_north, cfg_axi_north and cfg_axi_south
* are peripheral bus clock branches.
*/
GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_EAST, "cfg_axi_east", "top_axi", 10, CLK_IS_CRITICAL),
GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_EAST_NORTH, "cfg_axi_east_north", "top_axi", 11,
CLK_IS_CRITICAL),
GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_NORTH, "cfg_axi_north", "top_axi", 12, CLK_IS_CRITICAL),
GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_SOUTH, "cfg_axi_south", "top_axi", 13, CLK_IS_CRITICAL),
GATE_TOP0(CLK_TOP_CFG_EXT_TEST, "cfg_ext_test", "msdcpll_d2", 15),
/* TOP1 */
GATE_TOP1(CLK_TOP_SSUSB_REF, "ssusb_ref", "clk26m", 0),
GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 1),
GATE_TOP1(CLK_TOP_SSUSB_P1_REF, "ssusb_p1_ref", "clk26m", 2),
GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, "ssusb_phy_p1_ref", "clk26m", 3),
GATE_TOP1(CLK_TOP_SSUSB_P2_REF, "ssusb_p2_ref", "clk26m", 4),
GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, "ssusb_phy_p2_ref", "clk26m", 5),
GATE_TOP1(CLK_TOP_SSUSB_P3_REF, "ssusb_p3_ref", "clk26m", 6),
GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, "ssusb_phy_p3_ref", "clk26m", 7),
};
static const struct of_device_id of_match_clk_mt8195_topck[] = {
{ .compatible = "mediatek,mt8195-topckgen", },
{}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_topck);
/* Register mux notifier for MFG mux */
static int clk_mt8195_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
{
struct mtk_mux_nb *mfg_mux_nb;
mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
if (!mfg_mux_nb)
return -ENOMEM;
mfg_mux_nb->ops = &clk_mux_ops;
mfg_mux_nb->bypass_index = 0; /* Bypass to TOP_MFG_CORE_TMP */
return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
}
static int clk_mt8195_topck_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *top_clk_data;
struct device_node *node = pdev->dev.of_node;
struct clk_hw *hw;
int r;
void __iomem *base;
top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
if (!top_clk_data)
return -ENOMEM;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base)) {
r = PTR_ERR(base);
goto free_top_data;
}
r = mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
top_clk_data);
if (r)
goto free_top_data;
r = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
if (r)
goto unregister_fixed_clks;
r = mtk_clk_register_muxes(&pdev->dev, top_mtk_muxes,
ARRAY_SIZE(top_mtk_muxes), node,
&mt8195_clk_lock, top_clk_data);
if (r)
goto unregister_factors;
hw = devm_clk_hw_register_mux(&pdev->dev, "mfg_ck_fast_ref", mfg_fast_parents,
ARRAY_SIZE(mfg_fast_parents), CLK_SET_RATE_PARENT,
(base + 0x250), 8, 1, 0, &mt8195_clk_lock);
if (IS_ERR(hw)) {
r = PTR_ERR(hw);
goto unregister_muxes;
}
top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF] = hw;
r = clk_mt8195_reg_mfg_mux_notifier(&pdev->dev,
top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF]->clk);
if (r)
goto unregister_muxes;
r = mtk_clk_register_composites(&pdev->dev, top_adj_divs,
ARRAY_SIZE(top_adj_divs), base,
&mt8195_clk_lock, top_clk_data);
if (r)
goto unregister_muxes;
r = mtk_clk_register_gates(&pdev->dev, node, top_clks,
ARRAY_SIZE(top_clks), top_clk_data);
if (r)
goto unregister_composite_divs;
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
if (r)
goto unregister_gates;
platform_set_drvdata(pdev, top_clk_data);
return r;
unregister_gates:
mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data);
unregister_composite_divs:
mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data);
unregister_muxes:
mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
unregister_factors:
mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
unregister_fixed_clks:
mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
free_top_data:
mtk_free_clk_data(top_clk_data);
return r;
}
static void clk_mt8195_topck_remove(struct platform_device *pdev)
{
struct clk_hw_onecell_data *top_clk_data = platform_get_drvdata(pdev);
struct device_node *node = pdev->dev.of_node;
of_clk_del_provider(node);
mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data);
mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data);
mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
mtk_free_clk_data(top_clk_data);
}
static struct platform_driver clk_mt8195_topck_drv = {
.probe = clk_mt8195_topck_probe,
.remove_new = clk_mt8195_topck_remove,
.driver = {
.name = "clk-mt8195-topck",
.of_match_table = of_match_clk_mt8195_topck,
},
};
module_platform_driver(clk_mt8195_topck_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8195-topckgen.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015 MediaTek Inc.
* Author: James Liao <[email protected]>
*/
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include "clk-mtk.h"
#define REF2USB_TX_EN BIT(0)
#define REF2USB_TX_LPF_EN BIT(1)
#define REF2USB_TX_OUT_EN BIT(2)
#define REF2USB_EN_MASK (REF2USB_TX_EN | REF2USB_TX_LPF_EN | \
REF2USB_TX_OUT_EN)
struct mtk_ref2usb_tx {
struct clk_hw hw;
void __iomem *base_addr;
};
static inline struct mtk_ref2usb_tx *to_mtk_ref2usb_tx(struct clk_hw *hw)
{
return container_of(hw, struct mtk_ref2usb_tx, hw);
}
static int mtk_ref2usb_tx_is_prepared(struct clk_hw *hw)
{
struct mtk_ref2usb_tx *tx = to_mtk_ref2usb_tx(hw);
return (readl(tx->base_addr) & REF2USB_EN_MASK) == REF2USB_EN_MASK;
}
static int mtk_ref2usb_tx_prepare(struct clk_hw *hw)
{
struct mtk_ref2usb_tx *tx = to_mtk_ref2usb_tx(hw);
u32 val;
val = readl(tx->base_addr);
val |= REF2USB_TX_EN;
writel(val, tx->base_addr);
udelay(100);
val |= REF2USB_TX_LPF_EN;
writel(val, tx->base_addr);
val |= REF2USB_TX_OUT_EN;
writel(val, tx->base_addr);
return 0;
}
static void mtk_ref2usb_tx_unprepare(struct clk_hw *hw)
{
struct mtk_ref2usb_tx *tx = to_mtk_ref2usb_tx(hw);
u32 val;
val = readl(tx->base_addr);
val &= ~REF2USB_EN_MASK;
writel(val, tx->base_addr);
}
static const struct clk_ops mtk_ref2usb_tx_ops = {
.is_prepared = mtk_ref2usb_tx_is_prepared,
.prepare = mtk_ref2usb_tx_prepare,
.unprepare = mtk_ref2usb_tx_unprepare,
};
struct clk_hw *mtk_clk_register_ref2usb_tx(const char *name,
const char *parent_name, void __iomem *reg)
{
struct mtk_ref2usb_tx *tx;
struct clk_init_data init = {};
int ret;
tx = kzalloc(sizeof(*tx), GFP_KERNEL);
if (!tx)
return ERR_PTR(-ENOMEM);
tx->base_addr = reg;
tx->hw.init = &init;
init.name = name;
init.ops = &mtk_ref2usb_tx_ops;
init.parent_names = &parent_name;
init.num_parents = 1;
ret = clk_hw_register(NULL, &tx->hw);
if (ret) {
kfree(tx);
return ERR_PTR(ret);
}
return &tx->hw;
}
EXPORT_SYMBOL_GPL(mtk_clk_register_ref2usb_tx);
void mtk_clk_unregister_ref2usb_tx(struct clk_hw *hw)
{
struct mtk_ref2usb_tx *tx = to_mtk_ref2usb_tx(hw);
clk_hw_unregister(hw);
kfree(tx);
}
EXPORT_SYMBOL_GPL(mtk_clk_unregister_ref2usb_tx);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-apmixed.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Weiyi Lu <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt2712-clk.h>
static const struct mtk_gate_regs bdp_cg_regs = {
.set_ofs = 0x100,
.clr_ofs = 0x100,
.sta_ofs = 0x100,
};
#define GATE_BDP(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &bdp_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate bdp_clks[] = {
GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0),
GATE_BDP(CLK_BDP_BRIDGE_DRAM, "bdp_bridge_d", "mm_sel", 1),
GATE_BDP(CLK_BDP_LARB_DRAM, "bdp_larb_d", "mm_sel", 2),
GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_PXL, "bdp_vdi_pxl", "tvd_sel", 3),
GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_DRAM, "bdp_vdi_d", "mm_sel", 4),
GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_B, "bdp_vdi_b", "mm_sel", 5),
GATE_BDP(CLK_BDP_MT_B, "bdp_fmt_b", "mm_sel", 9),
GATE_BDP(CLK_BDP_DISPFMT_27M, "bdp_27m", "di_sel", 10),
GATE_BDP(CLK_BDP_DISPFMT_27M_VDOUT, "bdp_27m_vdout", "di_sel", 11),
GATE_BDP(CLK_BDP_DISPFMT_27_74_74, "bdp_27_74_74", "di_sel", 12),
GATE_BDP(CLK_BDP_DISPFMT_2FS, "bdp_2fs", "di_sel", 13),
GATE_BDP(CLK_BDP_DISPFMT_2FS_2FS74_148, "bdp_2fs74_148", "di_sel", 14),
GATE_BDP(CLK_BDP_DISPFMT_B, "bdp_b", "mm_sel", 15),
GATE_BDP(CLK_BDP_VDO_DRAM, "bdp_vdo_d", "mm_sel", 16),
GATE_BDP(CLK_BDP_VDO_2FS, "bdp_vdo_2fs", "di_sel", 17),
GATE_BDP(CLK_BDP_VDO_B, "bdp_vdo_b", "mm_sel", 18),
GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19),
GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d", "mm_sel", 20),
GATE_BDP(CLK_BDP_WR_CHANNEL_DI_B, "bdp_di_b", "mm_sel", 21),
GATE_BDP(CLK_BDP_NR_AGENT, "bdp_nr_agent", "nr_sel", 22),
GATE_BDP(CLK_BDP_NR_DRAM, "bdp_nr_d", "mm_sel", 23),
GATE_BDP(CLK_BDP_NR_B, "bdp_nr_b", "mm_sel", 24),
GATE_BDP(CLK_BDP_BRIDGE_RT_B, "bdp_bridge_rt_b", "mm_sel", 25),
GATE_BDP(CLK_BDP_BRIDGE_RT_DRAM, "bdp_bridge_rt_d", "mm_sel", 26),
GATE_BDP(CLK_BDP_LARB_RT_DRAM, "bdp_larb_rt_d", "mm_sel", 27),
GATE_BDP(CLK_BDP_TVD_TDC, "bdp_tvd_tdc", "mm_sel", 28),
GATE_BDP(CLK_BDP_TVD_54, "bdp_tvd_clk_54", "tvd_sel", 29),
GATE_BDP(CLK_BDP_TVD_CBUS, "bdp_tvd_cbus", "mm_sel", 30),
};
static const struct mtk_clk_desc bdp_desc = {
.clks = bdp_clks,
.num_clks = ARRAY_SIZE(bdp_clks),
};
static const struct of_device_id of_match_clk_mt2712_bdp[] = {
{
.compatible = "mediatek,mt2712-bdpsys",
.data = &bdp_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_bdp);
static struct platform_driver clk_mt2712_bdp_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt2712-bdp",
.of_match_table = of_match_clk_mt2712_bdp,
},
};
module_platform_driver(clk_mt2712_bdp_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt2712-bdp.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* Copyright (c) 2022 Collabora Ltd.
* Author: AngeloGioacchino Del Regno <[email protected]>
*/
#include <dt-bindings/clock/mt8173-clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-mux.h"
/*
* For some clocks, we don't care what their actual rates are. And these
* clocks may change their rate on different products or different scenarios.
* So we model these clocks' rate as 0, to denote it's not an actual rate.
*/
#define DUMMY_RATE 0
#define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \
MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _reg, \
(_reg + 0x4), (_reg + 0x8), _shift, _width, \
_gate, 0, -1, _flags)
#define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \
TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, \
_gate, CLK_SET_RATE_PARENT | _flags)
static DEFINE_SPINLOCK(mt8173_top_clk_lock);
static const char * const axi_parents[] = {
"clk26m",
"syspll1_d2",
"syspll_d5",
"syspll1_d4",
"univpll_d5",
"univpll2_d2",
"dmpll_d2",
"dmpll_d4"
};
static const char * const mem_parents[] = {
"clk26m",
"dmpll_ck"
};
static const char * const ddrphycfg_parents[] = {
"clk26m",
"syspll1_d8"
};
static const char * const mm_parents[] = {
"clk26m",
"vencpll_d2",
"main_h364m",
"syspll1_d2",
"syspll_d5",
"syspll1_d4",
"univpll1_d2",
"univpll2_d2",
"dmpll_d2"
};
static const char * const pwm_parents[] = {
"clk26m",
"univpll2_d4",
"univpll3_d2",
"univpll1_d4"
};
static const char * const vdec_parents[] = {
"clk26m",
"vcodecpll_ck",
"tvdpll_445p5m",
"univpll_d3",
"vencpll_d2",
"syspll_d3",
"univpll1_d2",
"mmpll_d2",
"dmpll_d2",
"dmpll_d4"
};
static const char * const venc_parents[] = {
"clk26m",
"vcodecpll_ck",
"tvdpll_445p5m",
"univpll_d3",
"vencpll_d2",
"syspll_d3",
"univpll1_d2",
"univpll2_d2",
"dmpll_d2",
"dmpll_d4"
};
static const char * const mfg_parents[] = {
"clk26m",
"mmpll_ck",
"dmpll_ck",
"clk26m",
"clk26m",
"clk26m",
"clk26m",
"clk26m",
"clk26m",
"syspll_d3",
"syspll1_d2",
"syspll_d5",
"univpll_d3",
"univpll1_d2",
"univpll_d5",
"univpll2_d2"
};
static const char * const camtg_parents[] = {
"clk26m",
"univpll_d26",
"univpll2_d2",
"syspll3_d2",
"syspll3_d4",
"univpll1_d4"
};
static const char * const uart_parents[] = {
"clk26m",
"univpll2_d8"
};
static const char * const spi_parents[] = {
"clk26m",
"syspll3_d2",
"syspll1_d4",
"syspll4_d2",
"univpll3_d2",
"univpll2_d4",
"univpll1_d8"
};
static const char * const usb20_parents[] = {
"clk26m",
"univpll1_d8",
"univpll3_d4"
};
static const char * const usb30_parents[] = {
"clk26m",
"univpll3_d2",
"usb_syspll_125m",
"univpll2_d4"
};
static const char * const msdc50_0_h_parents[] = {
"clk26m",
"syspll1_d2",
"syspll2_d2",
"syspll4_d2",
"univpll_d5",
"univpll1_d4"
};
static const char * const msdc50_0_parents[] = {
"clk26m",
"msdcpll_ck",
"msdcpll_d2",
"univpll1_d4",
"syspll2_d2",
"syspll_d7",
"msdcpll_d4",
"vencpll_d4",
"tvdpll_ck",
"univpll_d2",
"univpll1_d2",
"mmpll_ck",
"msdcpll2_ck",
"msdcpll2_d2",
"msdcpll2_d4"
};
static const char * const msdc30_1_parents[] = {
"clk26m",
"univpll2_d2",
"msdcpll_d4",
"univpll1_d4",
"syspll2_d2",
"syspll_d7",
"univpll_d7",
"vencpll_d4"
};
static const char * const msdc30_2_parents[] = {
"clk26m",
"univpll2_d2",
"msdcpll_d4",
"univpll1_d4",
"syspll2_d2",
"syspll_d7",
"univpll_d7",
"vencpll_d2"
};
static const char * const msdc30_3_parents[] = {
"clk26m",
"msdcpll2_ck",
"msdcpll2_d2",
"univpll2_d2",
"msdcpll2_d4",
"msdcpll_d4",
"univpll1_d4",
"syspll2_d2",
"syspll_d7",
"univpll_d7",
"vencpll_d4",
"msdcpll_ck",
"msdcpll_d2",
"msdcpll_d4"
};
static const char * const audio_parents[] = {
"clk26m",
"syspll3_d4",
"syspll4_d4",
"syspll1_d16"
};
static const char * const aud_intbus_parents[] = {
"clk26m",
"syspll1_d4",
"syspll4_d2",
"univpll3_d2",
"univpll2_d8",
"dmpll_d4",
"dmpll_d8"
};
static const char * const pmicspi_parents[] = {
"clk26m",
"syspll1_d8",
"syspll3_d4",
"syspll1_d16",
"univpll3_d4",
"univpll_d26",
"dmpll_d8",
"dmpll_d16"
};
static const char * const scp_parents[] = {
"clk26m",
"syspll1_d2",
"univpll_d5",
"syspll_d5",
"dmpll_d2",
"dmpll_d4"
};
static const char * const atb_parents[] = {
"clk26m",
"syspll1_d2",
"univpll_d5",
"dmpll_d2"
};
static const char * const venc_lt_parents[] = {
"clk26m",
"univpll_d3",
"vcodecpll_ck",
"tvdpll_445p5m",
"vencpll_d2",
"syspll_d3",
"univpll1_d2",
"univpll2_d2",
"syspll1_d2",
"univpll_d5",
"vcodecpll_370p5",
"dmpll_ck"
};
static const char * const dpi0_parents[] = {
"clk26m",
"tvdpll_d2",
"tvdpll_d4",
"clk26m",
"clk26m",
"tvdpll_d8",
"tvdpll_d16"
};
static const char * const irda_parents[] = {
"clk26m",
"univpll2_d4",
"syspll2_d4"
};
static const char * const cci400_parents[] = {
"clk26m",
"vencpll_ck",
"armca7pll_754m",
"armca7pll_502m",
"univpll_d2",
"syspll_d2",
"msdcpll_ck",
"dmpll_ck"
};
static const char * const aud_1_parents[] = {
"clk26m",
"apll1_ck",
"univpll2_d4",
"univpll2_d8"
};
static const char * const aud_2_parents[] = {
"clk26m",
"apll2_ck",
"univpll2_d4",
"univpll2_d8"
};
static const char * const mem_mfg_in_parents[] = {
"clk26m",
"mmpll_ck",
"dmpll_ck",
"clk26m"
};
static const char * const axi_mfg_in_parents[] = {
"clk26m",
"axi_sel",
"dmpll_d2"
};
static const char * const scam_parents[] = {
"clk26m",
"syspll3_d2",
"univpll2_d4",
"dmpll_d4"
};
static const char * const spinfi_ifr_parents[] = {
"clk26m",
"univpll2_d8",
"univpll3_d4",
"syspll4_d2",
"univpll2_d4",
"univpll3_d2",
"syspll1_d4",
"univpll1_d4"
};
static const char * const hdmi_parents[] = {
"clk26m",
"hdmitx_dig_cts",
"hdmitxpll_d2",
"hdmitxpll_d3"
};
static const char * const dpilvds_parents[] = {
"clk26m",
"lvdspll",
"lvdspll_d2",
"lvdspll_d4",
"lvdspll_d8",
"fpc_ck"
};
static const char * const msdc50_2_h_parents[] = {
"clk26m",
"syspll1_d2",
"syspll2_d2",
"syspll4_d2",
"univpll_d5",
"univpll1_d4"
};
static const char * const hdcp_parents[] = {
"clk26m",
"syspll4_d2",
"syspll3_d4",
"univpll2_d4"
};
static const char * const hdcp_24m_parents[] = {
"clk26m",
"univpll_d26",
"univpll_d52",
"univpll2_d8"
};
static const char * const rtc_parents[] = {
"clkrtc_int",
"clkrtc_ext",
"clk26m",
"univpll3_d8"
};
static const char * const i2s0_m_ck_parents[] = {
"apll1_div1",
"apll2_div1"
};
static const char * const i2s1_m_ck_parents[] = {
"apll1_div2",
"apll2_div2"
};
static const char * const i2s2_m_ck_parents[] = {
"apll1_div3",
"apll2_div3"
};
static const char * const i2s3_m_ck_parents[] = {
"apll1_div4",
"apll2_div4"
};
static const char * const i2s3_b_ck_parents[] = {
"apll1_div5",
"apll2_div5"
};
static const struct mtk_fixed_clk fixed_clks[] = {
FIXED_CLK(CLK_DUMMY, "topck_dummy", "clk26m", DUMMY_RATE),
FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", DUMMY_RATE),
FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ),
FIXED_CLK(CLK_TOP_DSI0_DIG, "dsi0_dig", "clk26m", DUMMY_RATE),
FIXED_CLK(CLK_TOP_DSI1_DIG, "dsi1_dig", "clk26m", DUMMY_RATE),
FIXED_CLK(CLK_TOP_LVDS_PXL, "lvds_pxl", "lvdspll", DUMMY_RATE),
FIXED_CLK(CLK_TOP_LVDS_CTS, "lvds_cts", "lvdspll", DUMMY_RATE),
};
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_ARMCA7PLL_754M, "armca7pll_754m", "armca7pll", 1, 2),
FACTOR(CLK_TOP_ARMCA7PLL_502M, "armca7pll_502m", "armca7pll", 1, 3),
FACTOR_FLAGS(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7, 0),
FACTOR(CLK_TOP_TVDPLL_445P5M, "tvdpll_445p5m", "tvdpll", 1, 4),
FACTOR(CLK_TOP_TVDPLL_594M, "tvdpll_594m", "tvdpll", 1, 3),
FACTOR_FLAGS(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7, 0),
FACTOR_FLAGS(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26, 0),
FACTOR(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", "clk32k", 1, 1),
FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793),
FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1),
FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2),
FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3),
FACTOR(CLK_TOP_ARMCA7PLL_D2, "armca7pll_d2", "armca7pll_754m", 1, 1),
FACTOR(CLK_TOP_ARMCA7PLL_D3, "armca7pll_d3", "armca7pll_502m", 1, 1),
FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "clkph_mck_o", 1, 1),
FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "clkph_mck_o", 1, 2),
FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "clkph_mck_o", 1, 4),
FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "clkph_mck_o", 1, 8),
FACTOR(CLK_TOP_DMPLL_D16, "dmpll_d16", "clkph_mck_o", 1, 16),
FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 1),
FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2", 1, 2),
FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2", 1, 4),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4, 0),
FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll_594m", 1, 1),
FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2),
FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_594m", 1, 4),
FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_594m", 1, 8),
FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_594m", 1, 16),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2, 0),
FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 3),
FACTOR(CLK_TOP_VCODECPLL_370P5, "vcodecpll_370p5", "vcodecpll", 1, 4),
FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1),
FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll", 1, 2),
FACTOR(CLK_TOP_VENCPLL_D4, "vencpll_d4", "vencpll", 1, 4),
};
static const struct mtk_composite top_muxes[] = {
/* CLK_CFG_0 */
MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
MUX_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel",
ddrphycfg_parents, 0x0040, 16, 1, 23,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31),
/* CLK_CFG_1 */
MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),
MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0050, 16, 4, 23),
MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 24, 4, 31),
/* CLK_CFG_2 */
MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0060, 0, 3, 7),
MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23),
MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 24, 2, 31),
/* CLK_CFG_3 */
MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x0070, 0, 2, 7),
MUX_GATE_FLAGS(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents,
0x0070, 8, 3, 15, 0),
MUX_GATE_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents,
0x0070, 16, 4, 23, 0),
MUX_GATE_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,
0x0070, 24, 3, 31, 0),
/* CLK_CFG_4 */
MUX_GATE_FLAGS(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents,
0x0080, 0, 3, 7, 0),
MUX_GATE_FLAGS(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents,
0x0080, 8, 4, 15, 0),
MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
0x0080, 16, 2, 23),
MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
0x0080, 24, 3, 31),
/* CLK_CFG_5 */
MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
0x0090, 0, 3, 7 /* 7:5 */),
MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0090, 8, 3, 15),
MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),
MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents,
0x0090, 24, 4, 31),
/* CLK_CFG_6 */
/*
* The dpi0_sel clock should not propagate rate changes to its parent
* clock so the dpi driver can have full control over PLL and divider.
*/
MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents,
0x00a0, 0, 3, 7, 0),
MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),
MUX_GATE_FLAGS(CLK_TOP_CCI400_SEL, "cci400_sel",
cci400_parents, 0x00a0, 16, 3, 23,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31),
/* CLK_CFG_7 */
MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7),
MUX_GATE(CLK_TOP_MEM_MFG_IN_SEL, "mem_mfg_in_sel", mem_mfg_in_parents,
0x00b0, 8, 2, 15),
MUX_GATE(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents,
0x00b0, 16, 2, 23),
MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x00b0, 24, 2, 31),
/* CLK_CFG_12 */
MUX_GATE(CLK_TOP_SPINFI_IFR_SEL, "spinfi_ifr_sel", spinfi_ifr_parents,
0x00c0, 0, 3, 7),
MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15),
MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents,
0x00c0, 24, 3, 31),
/* CLK_CFG_13 */
MUX_GATE_FLAGS(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents,
0x00d0, 0, 3, 7, 0),
MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15),
MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents,
0x00d0, 16, 2, 23),
MUX_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00d0, 24, 2,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
DIV_GATE(CLK_TOP_APLL1_DIV0, "apll1_div0", "aud_1_sel", 0x12c, 8, 0x120, 4, 24),
DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, 8, 0),
DIV_GATE(CLK_TOP_APLL1_DIV2, "apll1_div2", "aud_1_sel", 0x12c, 10, 0x124, 8, 8),
DIV_GATE(CLK_TOP_APLL1_DIV3, "apll1_div3", "aud_1_sel", 0x12c, 11, 0x124, 8, 16),
DIV_GATE(CLK_TOP_APLL1_DIV4, "apll1_div4", "aud_1_sel", 0x12c, 12, 0x124, 8, 24),
DIV_GATE(CLK_TOP_APLL1_DIV5, "apll1_div5", "apll1_div4", 0x12c, 13, 0x12c, 4, 0),
DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28),
DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1", "aud_2_sel", 0x12c, 17, 0x128, 8, 0),
DIV_GATE(CLK_TOP_APLL2_DIV2, "apll2_div2", "aud_2_sel", 0x12c, 18, 0x128, 8, 8),
DIV_GATE(CLK_TOP_APLL2_DIV3, "apll2_div3", "aud_2_sel", 0x12c, 19, 0x128, 8, 16),
DIV_GATE(CLK_TOP_APLL2_DIV4, "apll2_div4", "aud_2_sel", 0x12c, 20, 0x128, 8, 24),
DIV_GATE(CLK_TOP_APLL2_DIV5, "apll2_div5", "apll2_div4", 0x12c, 21, 0x12c, 4, 4),
MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents, 0x120, 4, 1),
MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents, 0x120, 5, 1),
MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents, 0x120, 6, 1),
MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents, 0x120, 7, 1),
MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1),
};
static const struct mtk_clk_desc topck_desc = {
.fixed_clks = fixed_clks,
.num_fixed_clks = ARRAY_SIZE(fixed_clks),
.factor_clks = top_divs,
.num_factor_clks = ARRAY_SIZE(top_divs),
.composite_clks = top_muxes,
.num_composite_clks = ARRAY_SIZE(top_muxes),
.clk_lock = &mt8173_top_clk_lock,
};
static const struct of_device_id of_match_clk_mt8173_topckgen[] = {
{ .compatible = "mediatek,mt8173-topckgen", .data = &topck_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_topckgen);
static struct platform_driver clk_mt8173_topckgen_drv = {
.driver = {
.name = "clk-mt8173-topckgen",
.of_match_table = of_match_clk_mt8173_topckgen,
},
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt8173_topckgen_drv);
MODULE_DESCRIPTION("MediaTek MT8173 topckgen clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8173-topckgen.c |
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