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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Weiyi Lu <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt2712-clk.h>
static const struct mtk_gate_regs vdec0_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x4,
.sta_ofs = 0x0,
};
static const struct mtk_gate_regs vdec1_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0xc,
.sta_ofs = 0x8,
};
#define GATE_VDEC0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
#define GATE_VDEC1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate vdec_clks[] = {
/* VDEC0 */
GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
/* VDEC1 */
GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "vdec_sel", 0),
GATE_VDEC1(CLK_VDEC_IMGRZ_CKEN, "vdec_imgrz_cken", "vdec_sel", 1),
};
static const struct mtk_clk_desc vdec_desc = {
.clks = vdec_clks,
.num_clks = ARRAY_SIZE(vdec_clks),
};
static const struct of_device_id of_match_clk_mt2712_vdec[] = {
{
.compatible = "mediatek,mt2712-vdecsys",
.data = &vdec_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_vdec);
static struct platform_driver clk_mt2712_vdec_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt2712-vdec",
.of_match_table = of_match_clk_mt2712_vdec,
},
};
module_platform_driver(clk_mt2712_vdec_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt2712-vdec.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Edward-JW Yang <[email protected]>
*/
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/clkdev.h>
#include <linux/delay.h>
#include "clk-mtk.h"
#include "clk-pllfh.h"
#include "clk-fhctl.h"
static DEFINE_SPINLOCK(pllfh_lock);
inline struct mtk_fh *to_mtk_fh(struct clk_hw *hw)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
return container_of(pll, struct mtk_fh, clk_pll);
}
static int mtk_fhctl_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
struct mtk_fh *fh = to_mtk_fh(hw);
u32 pcw = 0;
u32 postdiv;
mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
return fh->ops->hopping(fh, pcw, postdiv);
}
static const struct clk_ops mtk_pllfh_ops = {
.is_prepared = mtk_pll_is_prepared,
.prepare = mtk_pll_prepare,
.unprepare = mtk_pll_unprepare,
.recalc_rate = mtk_pll_recalc_rate,
.round_rate = mtk_pll_round_rate,
.set_rate = mtk_fhctl_set_rate,
};
static struct mtk_pllfh_data *get_pllfh_by_id(struct mtk_pllfh_data *pllfhs,
int num_fhs, int pll_id)
{
int i;
for (i = 0; i < num_fhs; i++)
if (pllfhs[i].data.pll_id == pll_id)
return &pllfhs[i];
return NULL;
}
void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs,
int num_fhs)
{
void __iomem *base;
struct device_node *node;
u32 num_clocks, pll_id, ssc_rate;
int offset, i;
node = of_find_compatible_node(NULL, NULL, compatible_node);
if (!node) {
pr_err("cannot find \"%s\"\n", compatible_node);
return;
}
base = of_iomap(node, 0);
if (!base) {
pr_err("%s(): ioremap failed\n", __func__);
goto out_node_put;
}
num_clocks = of_clk_get_parent_count(node);
if (!num_clocks) {
pr_err("%s(): failed to get clocks property\n", __func__);
goto err;
}
for (i = 0; i < num_clocks; i++) {
struct mtk_pllfh_data *pllfh;
offset = i * 2;
of_property_read_u32_index(node, "clocks", offset + 1, &pll_id);
of_property_read_u32_index(node,
"mediatek,hopping-ssc-percent",
i, &ssc_rate);
pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll_id);
if (!pllfh)
continue;
pllfh->state.fh_enable = 1;
pllfh->state.ssc_rate = ssc_rate;
pllfh->state.base = base;
}
out_node_put:
of_node_put(node);
return;
err:
iounmap(base);
goto out_node_put;
}
EXPORT_SYMBOL_GPL(fhctl_parse_dt);
static int pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data)
{
struct fh_pll_regs *regs = &fh->regs;
const struct fhctl_offset *offset;
void __iomem *base = pllfh_data->state.base;
void __iomem *fhx_base = base + pllfh_data->data.fhx_offset;
offset = fhctl_get_offset_table(pllfh_data->data.fh_ver);
if (IS_ERR(offset))
return PTR_ERR(offset);
regs->reg_hp_en = base + offset->offset_hp_en;
regs->reg_clk_con = base + offset->offset_clk_con;
regs->reg_rst_con = base + offset->offset_rst_con;
regs->reg_slope0 = base + offset->offset_slope0;
regs->reg_slope1 = base + offset->offset_slope1;
regs->reg_cfg = fhx_base + offset->offset_cfg;
regs->reg_updnlmt = fhx_base + offset->offset_updnlmt;
regs->reg_dds = fhx_base + offset->offset_dds;
regs->reg_dvfs = fhx_base + offset->offset_dvfs;
regs->reg_mon = fhx_base + offset->offset_mon;
fh->pllfh_data = pllfh_data;
fh->lock = &pllfh_lock;
fh->ops = fhctl_get_ops();
return 0;
}
static bool fhctl_is_supported_and_enabled(const struct mtk_pllfh_data *pllfh)
{
return pllfh && (pllfh->state.fh_enable == 1);
}
static struct clk_hw *
mtk_clk_register_pllfh(const struct mtk_pll_data *pll_data,
struct mtk_pllfh_data *pllfh_data, void __iomem *base)
{
struct clk_hw *hw;
struct mtk_fh *fh;
int ret;
fh = kzalloc(sizeof(*fh), GFP_KERNEL);
if (!fh)
return ERR_PTR(-ENOMEM);
ret = pllfh_init(fh, pllfh_data);
if (ret) {
hw = ERR_PTR(ret);
goto out;
}
hw = mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base,
&mtk_pllfh_ops);
if (IS_ERR(hw))
goto out;
fhctl_hw_init(fh);
out:
if (IS_ERR(hw))
kfree(fh);
return hw;
}
static void mtk_clk_unregister_pllfh(struct clk_hw *hw)
{
struct mtk_fh *fh;
if (!hw)
return;
fh = to_mtk_fh(hw);
clk_hw_unregister(hw);
kfree(fh);
}
int mtk_clk_register_pllfhs(struct device_node *node,
const struct mtk_pll_data *plls, int num_plls,
struct mtk_pllfh_data *pllfhs, int num_fhs,
struct clk_hw_onecell_data *clk_data)
{
void __iomem *base;
int i;
struct clk_hw *hw;
base = of_iomap(node, 0);
if (!base) {
pr_err("%s(): ioremap failed\n", __func__);
return -EINVAL;
}
for (i = 0; i < num_plls; i++) {
const struct mtk_pll_data *pll = &plls[i];
struct mtk_pllfh_data *pllfh;
bool use_fhctl;
pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id);
use_fhctl = fhctl_is_supported_and_enabled(pllfh);
if (use_fhctl)
hw = mtk_clk_register_pllfh(pll, pllfh, base);
else
hw = mtk_clk_register_pll(pll, base);
if (IS_ERR(hw)) {
pr_err("Failed to register %s clk %s: %ld\n",
use_fhctl ? "fhpll" : "pll", pll->name,
PTR_ERR(hw));
goto err;
}
clk_data->hws[pll->id] = hw;
}
return 0;
err:
while (--i >= 0) {
const struct mtk_pll_data *pll = &plls[i];
struct mtk_pllfh_data *pllfh;
bool use_fhctl;
pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id);
use_fhctl = fhctl_is_supported_and_enabled(pllfh);
if (use_fhctl)
mtk_clk_unregister_pllfh(clk_data->hws[pll->id]);
else
mtk_clk_unregister_pll(clk_data->hws[pll->id]);
clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
}
iounmap(base);
return PTR_ERR(hw);
}
EXPORT_SYMBOL_GPL(mtk_clk_register_pllfhs);
void mtk_clk_unregister_pllfhs(const struct mtk_pll_data *plls, int num_plls,
struct mtk_pllfh_data *pllfhs, int num_fhs,
struct clk_hw_onecell_data *clk_data)
{
void __iomem *base = NULL, *fhctl_base = NULL;
int i;
if (!clk_data)
return;
for (i = num_plls; i > 0; i--) {
const struct mtk_pll_data *pll = &plls[i - 1];
struct mtk_pllfh_data *pllfh;
bool use_fhctl;
if (IS_ERR_OR_NULL(clk_data->hws[pll->id]))
continue;
pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id);
use_fhctl = fhctl_is_supported_and_enabled(pllfh);
if (use_fhctl) {
fhctl_base = pllfh->state.base;
mtk_clk_unregister_pllfh(clk_data->hws[pll->id]);
} else {
base = mtk_clk_pll_get_base(clk_data->hws[pll->id],
pll);
mtk_clk_unregister_pll(clk_data->hws[pll->id]);
}
clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
}
if (fhctl_base)
iounmap(fhctl_base);
iounmap(base);
}
EXPORT_SYMBOL_GPL(mtk_clk_unregister_pllfhs);
| linux-master | drivers/clk/mediatek/clk-pllfh.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* Copyright (c) 2022 Collabora Ltd.
* Author: AngeloGioacchino Del Regno <[email protected]>
*/
#include <dt-bindings/clock/mt8173-clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs img_cg_regs = {
.set_ofs = 0x0004,
.clr_ofs = 0x0008,
.sta_ofs = 0x0000,
};
#define GATE_IMG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate img_clks[] = {
GATE_DUMMY(CLK_DUMMY, "img_dummy"),
GATE_IMG(CLK_IMG_LARB2_SMI, "img_larb2_smi", "mm_sel", 0),
GATE_IMG(CLK_IMG_CAM_SMI, "img_cam_smi", "mm_sel", 5),
GATE_IMG(CLK_IMG_CAM_CAM, "img_cam_cam", "mm_sel", 6),
GATE_IMG(CLK_IMG_SEN_TG, "img_sen_tg", "camtg_sel", 7),
GATE_IMG(CLK_IMG_SEN_CAM, "img_sen_cam", "mm_sel", 8),
GATE_IMG(CLK_IMG_CAM_SV, "img_cam_sv", "mm_sel", 9),
GATE_IMG(CLK_IMG_FD, "img_fd", "mm_sel", 11),
};
static const struct mtk_clk_desc img_desc = {
.clks = img_clks,
.num_clks = ARRAY_SIZE(img_clks),
};
static const struct of_device_id of_match_clk_mt8173_imgsys[] = {
{ .compatible = "mediatek,mt8173-imgsys", .data = &img_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_imgsys);
static struct platform_driver clk_mt8173_vdecsys_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8173-imgsys",
.of_match_table = of_match_clk_mt8173_imgsys,
},
};
module_platform_driver(clk_mt8173_vdecsys_drv);
MODULE_DESCRIPTION("MediaTek MT8173 vdecsys clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8173-img.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Garmin Chang <[email protected]>
*/
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-pll.h"
static const struct mtk_gate_regs apmixed_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0x8,
.sta_ofs = 0x8,
};
#define GATE_APMIXED(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate apmixed_clks[] = {
GATE_APMIXED(CLK_APMIXED_PLL_SSUSB26M_EN, "pll_ssusb26m_en", "clk26m", 1),
};
#define MT8188_PLL_FMAX (3800UL * MHZ)
#define MT8188_PLL_FMIN (1500UL * MHZ)
#define MT8188_INTEGER_BITS 8
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
_rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
_tuner_reg, _tuner_en_reg, _tuner_en_bit, \
_pcw_reg, _pcw_shift, _pcw_chg_reg, \
_en_reg, _pll_en_bit) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = _en_mask, \
.flags = _flags, \
.rst_bar_mask = _rst_bar_mask, \
.fmax = MT8188_PLL_FMAX, \
.fmin = MT8188_PLL_FMIN, \
.pcwbits = _pcwbits, \
.pcwibits = MT8188_INTEGER_BITS, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, \
.tuner_en_reg = _tuner_en_reg, \
.tuner_en_bit = _tuner_en_bit, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
.pcw_chg_reg = _pcw_chg_reg, \
.en_reg = _en_reg, \
.pll_en_bit = _pll_en_bit, \
}
static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x044C, 0x0458, 0,
0, 0, 22, 0x0450, 24, 0, 0, 0, 0x0450, 0, 0, 0, 9),
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0514, 0x0520, 0,
0, 0, 22, 0x0518, 24, 0, 0, 0, 0x0518, 0, 0, 0, 9),
PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x0524, 0x0530, 0,
0, 0, 22, 0x0528, 24, 0, 0, 0, 0x0528, 0, 0, 0, 9),
PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x0534, 0x0540, 0,
0, 0, 22, 0x0538, 24, 0, 0, 0, 0x0538, 0, 0, 0, 9),
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0544, 0x0550, 0xff000000,
HAVE_RST_BAR, BIT(23), 22, 0x0548, 24, 0, 0, 0, 0x0548, 0, 0, 0, 9),
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x045C, 0x0468, 0xff000000,
HAVE_RST_BAR, BIT(23), 22, 0x0460, 24, 0, 0, 0, 0x0460, 0, 0, 0, 9),
PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0554, 0x0560, 0,
0, 0, 22, 0x0558, 24, 0, 0, 0, 0x0558, 0, 0, 0, 9),
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0504, 0x0510, 0xff000000,
HAVE_RST_BAR, BIT(23), 22, 0x0508, 24, 0, 0, 0, 0x0508, 0, 0, 0, 9),
PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x042C, 0x0438, 0,
0, 0, 22, 0x0430, 24, 0, 0, 0, 0x0430, 0, 0, 0, 9),
PLL(CLK_APMIXED_APLL1, "apll1", 0x0304, 0x0314, 0,
0, 0, 32, 0x0308, 24, 0x0034, 0x0000, 12, 0x030C, 0, 0, 0, 9),
PLL(CLK_APMIXED_APLL2, "apll2", 0x0318, 0x0328, 0,
0, 0, 32, 0x031C, 24, 0x0038, 0x0000, 13, 0x0320, 0, 0, 0, 9),
PLL(CLK_APMIXED_APLL3, "apll3", 0x032C, 0x033C, 0,
0, 0, 32, 0x0330, 24, 0x003C, 0x0000, 14, 0x0334, 0, 0, 0, 9),
PLL(CLK_APMIXED_APLL4, "apll4", 0x0404, 0x0414, 0,
0, 0, 32, 0x0408, 24, 0x0040, 0x0000, 15, 0x040C, 0, 0, 0, 9),
PLL(CLK_APMIXED_APLL5, "apll5", 0x0418, 0x0428, 0,
0, 0, 32, 0x041C, 24, 0x0044, 0x0000, 16, 0x0420, 0, 0, 0, 9),
PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x034C, 0,
0, 0, 22, 0x0344, 24, 0, 0, 0, 0x0344, 0, 0, 0, 9),
};
static const struct of_device_id of_match_clk_mt8188_apmixed[] = {
{ .compatible = "mediatek,mt8188-apmixedsys" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_apmixed);
static int clk_mt8188_apmixed_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
if (!clk_data)
return -ENOMEM;
r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
if (r)
goto free_apmixed_data;
r = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
ARRAY_SIZE(apmixed_clks), clk_data);
if (r)
goto unregister_plls;
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_gates;
platform_set_drvdata(pdev, clk_data);
return 0;
unregister_gates:
mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
unregister_plls:
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
free_apmixed_data:
mtk_free_clk_data(clk_data);
return r;
}
static void clk_mt8188_apmixed_remove(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
of_clk_del_provider(node);
mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
mtk_free_clk_data(clk_data);
}
static struct platform_driver clk_mt8188_apmixed_drv = {
.probe = clk_mt8188_apmixed_probe,
.remove_new = clk_mt8188_apmixed_remove,
.driver = {
.name = "clk-mt8188-apmixed",
.of_match_table = of_match_clk_mt8188_apmixed,
},
};
module_platform_driver(clk_mt8188_apmixed_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8188-apmixedsys.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: James Liao <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8173-clk.h>
static const struct mtk_gate_regs mm0_cg_regs = {
.set_ofs = 0x0104,
.clr_ofs = 0x0108,
.sta_ofs = 0x0100,
};
static const struct mtk_gate_regs mm1_cg_regs = {
.set_ofs = 0x0114,
.clr_ofs = 0x0118,
.sta_ofs = 0x0110,
};
#define GATE_MM0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_MM1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate mt8173_mm_clks[] = {
GATE_DUMMY(CLK_DUMMY, "mm_dummy"),
/* MM0 */
GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 15),
GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
GATE_MM0(CLK_MM_DISP_SPLIT1, "mm_disp_split1", "mm_sel", 29),
GATE_MM0(CLK_MM_DISP_MERGE, "mm_disp_merge", "mm_sel", 30),
GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
/* MM1 */
GATE_MM1(CLK_MM_DISP_PWM0MM, "mm_disp_pwm0mm", "mm_sel", 0),
GATE_MM1(CLK_MM_DISP_PWM026M, "mm_disp_pwm026m", "pwm_sel", 1),
GATE_MM1(CLK_MM_DISP_PWM1MM, "mm_disp_pwm1mm", "mm_sel", 2),
GATE_MM1(CLK_MM_DISP_PWM126M, "mm_disp_pwm126m", "pwm_sel", 3),
GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_dig", 5),
GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_dig", 7),
GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "dpi0_sel", 8),
GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "lvds_pxl", 10),
GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
GATE_MM1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi0_sel", 12),
GATE_MM1(CLK_MM_HDMI_PLLCK, "mm_hdmi_pllck", "hdmi_sel", 13),
GATE_MM1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll1", 14),
GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll2", 15),
GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "lvds_pxl", 16),
GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvds_cts", 17),
GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
GATE_MM1(CLK_MM_HDMI_HDCP, "mm_hdmi_hdcp", "hdcp_sel", 19),
GATE_MM1(CLK_MM_HDMI_HDCP24M, "mm_hdmi_hdcp24m", "hdcp_24m_sel", 20),
};
static const struct mtk_clk_desc mm_desc = {
.clks = mt8173_mm_clks,
.num_clks = ARRAY_SIZE(mt8173_mm_clks),
};
static const struct platform_device_id clk_mt8173_mm_id_table[] = {
{ .name = "clk-mt8173-mm", .driver_data = (kernel_ulong_t)&mm_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, clk_mt8173_mm_id_table);
static struct platform_driver clk_mt8173_mm_drv = {
.driver = {
.name = "clk-mt8173-mm",
},
.id_table = clk_mt8173_mm_id_table,
.probe = mtk_clk_pdev_probe,
.remove_new = mtk_clk_pdev_remove,
};
module_platform_driver(clk_mt8173_mm_drv);
MODULE_DESCRIPTION("MediaTek MT8173 MultiMedia clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8173-mm.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Wendell Lin <[email protected]>
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-mux.h"
#include "clk-pll.h"
#include <dt-bindings/clock/mt6779-clk.h>
static DEFINE_SPINLOCK(mt6779_clk_lock);
static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000),
};
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2),
FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2),
FACTOR(CLK_TOP_MAINPLL_CK, "mainpll_ck", "mainpll", 1, 1),
FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll_ck", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D2_D8, "mainpll_d2_d8", "mainpll_d2", 1, 8),
FACTOR(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16),
FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
FACTOR(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D3_D8, "mainpll_d3_d8", "mainpll_d3", 1, 8),
FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_CK, "univpll", "univ2pll", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 16),
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
FACTOR(CLK_TOP_UNIVP_192M_CK, "univpll_192m_ck", "univ2pll", 1, 13),
FACTOR(CLK_TOP_UNIVP_192M_D2, "univpll_192m_d2", "univpll_192m_ck",
1, 2),
FACTOR(CLK_TOP_UNIVP_192M_D4, "univpll_192m_d4", "univpll_192m_ck",
1, 4),
FACTOR(CLK_TOP_UNIVP_192M_D8, "univpll_192m_d8", "univpll_192m_ck",
1, 8),
FACTOR(CLK_TOP_UNIVP_192M_D16, "univpll_192m_d16", "univpll_192m_ck",
1, 16),
FACTOR(CLK_TOP_UNIVP_192M_D32, "univpll_192m_d32", "univpll_192m_ck",
1, 32),
FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 1),
FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4),
FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
FACTOR(CLK_TOP_ADSPPLL_CK, "adsppll_ck", "adsppll", 1, 1),
FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
FACTOR(CLK_TOP_ADSPPLL_D5, "adsppll_d5", "adsppll", 1, 5),
FACTOR(CLK_TOP_ADSPPLL_D6, "adsppll_d6", "adsppll", 1, 6),
FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 1),
FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 2),
FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 4),
FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 8),
FACTOR(CLK_TOP_OSC_D10, "osc_d10", "osc", 1, 10),
FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 16),
FACTOR(CLK_TOP_AD_OSC2_CK, "ad_osc2_ck", "osc2", 1, 1),
FACTOR(CLK_TOP_OSC2_D2, "osc2_d2", "osc2", 1, 2),
FACTOR(CLK_TOP_OSC2_D3, "osc2_d3", "osc2", 1, 3),
FACTOR(CLK_TOP_TVDPLL_MAINPLL_D2_CK, "tvdpll_mainpll_d2_ck",
"tvdpll", 1, 1),
FACTOR(CLK_TOP_FMEM_466M_CK, "fmem_466m_ck", "fmem", 1, 1),
};
static const char * const axi_parents[] = {
"clk26m",
"mainpll_d2_d4",
"mainpll_d7",
"osc_d4"
};
static const char * const mm_parents[] = {
"clk26m",
"tvdpll_mainpll_d2_ck",
"mmpll_d7",
"mmpll_d5_d2",
"mainpll_d2_d2",
"mainpll_d3_d2"
};
static const char * const scp_parents[] = {
"clk26m",
"univpll_d2_d8",
"mainpll_d2_d4",
"mainpll_d3",
"univpll_d3",
"ad_osc2_ck",
"osc2_d2",
"osc2_d3"
};
static const char * const img_parents[] = {
"clk26m",
"mainpll_d2",
"mainpll_d2",
"univpll_d3",
"mainpll_d3",
"mmpll_d5_d2",
"tvdpll_mainpll_d2_ck",
"mainpll_d5"
};
static const char * const ipe_parents[] = {
"clk26m",
"mainpll_d2",
"mmpll_d7",
"univpll_d3",
"mainpll_d3",
"mmpll_d5_d2",
"mainpll_d2_d2",
"mainpll_d5"
};
static const char * const dpe_parents[] = {
"clk26m",
"mainpll_d2",
"mmpll_d7",
"univpll_d3",
"mainpll_d3",
"mmpll_d5_d2",
"mainpll_d2_d2",
"mainpll_d5"
};
static const char * const cam_parents[] = {
"clk26m",
"mainpll_d2",
"mmpll_d6",
"mainpll_d3",
"mmpll_d7",
"univpll_d3",
"mmpll_d5_d2",
"adsppll_d5",
"tvdpll_mainpll_d2_ck",
"univpll_d3_d2"
};
static const char * const ccu_parents[] = {
"clk26m",
"mainpll_d2",
"mmpll_d6",
"mainpll_d3",
"mmpll_d7",
"univpll_d3",
"mmpll_d5_d2",
"mainpll_d2_d2",
"adsppll_d5",
"univpll_d3_d2"
};
static const char * const dsp_parents[] = {
"clk26m",
"univpll_d3_d8",
"univpll_d3_d4",
"mainpll_d2_d4",
"univpll_d3_d2",
"mainpll_d2_d2",
"univpll_d2_d2",
"mainpll_d3",
"univpll_d3",
"mmpll_d7",
"mmpll_d6",
"adsppll_d5",
"tvdpll_ck",
"tvdpll_mainpll_d2_ck",
"univpll_d2",
"adsppll_d4"
};
static const char * const dsp1_parents[] = {
"clk26m",
"univpll_d3_d8",
"univpll_d3_d4",
"mainpll_d2_d4",
"univpll_d3_d2",
"mainpll_d2_d2",
"univpll_d2_d2",
"mainpll_d3",
"univpll_d3",
"mmpll_d7",
"mmpll_d6",
"adsppll_d5",
"tvdpll_ck",
"tvdpll_mainpll_d2_ck",
"univpll_d2",
"adsppll_d4"
};
static const char * const dsp2_parents[] = {
"clk26m",
"univpll_d3_d8",
"univpll_d3_d4",
"mainpll_d2_d4",
"univpll_d3_d2",
"mainpll_d2_d2",
"univpll_d2_d2",
"mainpll_d3",
"univpll_d3",
"mmpll_d7",
"mmpll_d6",
"adsppll_d5",
"tvdpll_ck",
"tvdpll_mainpll_d2_ck",
"univpll_d2",
"adsppll_d4"
};
static const char * const dsp3_parents[] = {
"clk26m",
"univpll_d3_d8",
"mainpll_d2_d4",
"univpll_d3_d2",
"mainpll_d2_d2",
"univpll_d2_d2",
"mainpll_d3",
"univpll_d3",
"mmpll_d7",
"mmpll_d6",
"mainpll_d2",
"tvdpll_ck",
"tvdpll_mainpll_d2_ck",
"univpll_d2",
"adsppll_d4",
"mmpll_d4"
};
static const char * const ipu_if_parents[] = {
"clk26m",
"univpll_d3_d8",
"univpll_d3_d4",
"mainpll_d2_d4",
"univpll_d3_d2",
"mainpll_d2_d2",
"univpll_d2_d2",
"mainpll_d3",
"univpll_d3",
"mmpll_d7",
"mmpll_d6",
"adsppll_d5",
"tvdpll_ck",
"tvdpll_mainpll_d2_ck",
"univpll_d2",
"adsppll_d4"
};
static const char * const mfg_parents[] = {
"clk26m",
"mfgpll_ck",
"univpll_d3",
"mainpll_d5"
};
static const char * const f52m_mfg_parents[] = {
"clk26m",
"univpll_d3_d2",
"univpll_d3_d4",
"univpll_d3_d8"
};
static const char * const camtg_parents[] = {
"clk26m",
"univpll_192m_d8",
"univpll_d3_d8",
"univpll_192m_d4",
"univpll_d3_d16",
"csw_f26m_ck_d2",
"univpll_192m_d16",
"univpll_192m_d32"
};
static const char * const camtg2_parents[] = {
"clk26m",
"univpll_192m_d8",
"univpll_d3_d8",
"univpll_192m_d4",
"univpll_d3_d16",
"csw_f26m_ck_d2",
"univpll_192m_d16",
"univpll_192m_d32"
};
static const char * const camtg3_parents[] = {
"clk26m",
"univpll_192m_d8",
"univpll_d3_d8",
"univpll_192m_d4",
"univpll_d3_d16",
"csw_f26m_ck_d2",
"univpll_192m_d16",
"univpll_192m_d32"
};
static const char * const camtg4_parents[] = {
"clk26m",
"univpll_192m_d8",
"univpll_d3_d8",
"univpll_192m_d4",
"univpll_d3_d16",
"csw_f26m_ck_d2",
"univpll_192m_d16",
"univpll_192m_d32"
};
static const char * const uart_parents[] = {
"clk26m",
"univpll_d3_d8"
};
static const char * const spi_parents[] = {
"clk26m",
"mainpll_d5_d2",
"mainpll_d3_d4",
"msdcpll_d4"
};
static const char * const msdc50_hclk_parents[] = {
"clk26m",
"mainpll_d2_d2",
"mainpll_d3_d2"
};
static const char * const msdc50_0_parents[] = {
"clk26m",
"msdcpll_ck",
"msdcpll_d2",
"univpll_d2_d4",
"mainpll_d3_d2",
"univpll_d2_d2"
};
static const char * const msdc30_1_parents[] = {
"clk26m",
"univpll_d3_d2",
"mainpll_d3_d2",
"mainpll_d7",
"msdcpll_d2"
};
static const char * const audio_parents[] = {
"clk26m",
"mainpll_d5_d4",
"mainpll_d7_d4",
"mainpll_d2_d16"
};
static const char * const aud_intbus_parents[] = {
"clk26m",
"mainpll_d2_d4",
"mainpll_d7_d2"
};
static const char * const fpwrap_ulposc_parents[] = {
"osc_d10",
"clk26m",
"osc_d4",
"osc_d8",
"osc_d16"
};
static const char * const atb_parents[] = {
"clk26m",
"mainpll_d2_d2",
"mainpll_d5"
};
static const char * const sspm_parents[] = {
"clk26m",
"univpll_d2_d4",
"mainpll_d2_d2",
"univpll_d2_d2",
"mainpll_d3"
};
static const char * const dpi0_parents[] = {
"clk26m",
"tvdpll_d2",
"tvdpll_d4",
"tvdpll_d8",
"tvdpll_d16"
};
static const char * const scam_parents[] = {
"clk26m",
"mainpll_d5_d2"
};
static const char * const disppwm_parents[] = {
"clk26m",
"univpll_d3_d4",
"osc_d2",
"osc_d4",
"osc_d16"
};
static const char * const usb_top_parents[] = {
"clk26m",
"univpll_d5_d4",
"univpll_d3_d4",
"univpll_d5_d2"
};
static const char * const ssusb_top_xhci_parents[] = {
"clk26m",
"univpll_d5_d4",
"univpll_d3_d4",
"univpll_d5_d2"
};
static const char * const spm_parents[] = {
"clk26m",
"osc_d8",
"mainpll_d2_d8"
};
static const char * const i2c_parents[] = {
"clk26m",
"mainpll_d2_d8",
"univpll_d5_d2"
};
static const char * const seninf_parents[] = {
"clk26m",
"univpll_d7",
"univpll_d3_d2",
"univpll_d2_d2",
"mainpll_d3",
"mmpll_d4_d2",
"mmpll_d7",
"mmpll_d6"
};
static const char * const seninf1_parents[] = {
"clk26m",
"univpll_d7",
"univpll_d3_d2",
"univpll_d2_d2",
"mainpll_d3",
"mmpll_d4_d2",
"mmpll_d7",
"mmpll_d6"
};
static const char * const seninf2_parents[] = {
"clk26m",
"univpll_d7",
"univpll_d3_d2",
"univpll_d2_d2",
"mainpll_d3",
"mmpll_d4_d2",
"mmpll_d7",
"mmpll_d6"
};
static const char * const dxcc_parents[] = {
"clk26m",
"mainpll_d2_d2",
"mainpll_d2_d4",
"mainpll_d2_d8"
};
static const char * const aud_engen1_parents[] = {
"clk26m",
"apll1_d2",
"apll1_d4",
"apll1_d8"
};
static const char * const aud_engen2_parents[] = {
"clk26m",
"apll2_d2",
"apll2_d4",
"apll2_d8"
};
static const char * const faes_ufsfde_parents[] = {
"clk26m",
"mainpll_d2",
"mainpll_d2_d2",
"mainpll_d3",
"mainpll_d2_d4",
"univpll_d3"
};
static const char * const fufs_parents[] = {
"clk26m",
"mainpll_d2_d4",
"mainpll_d2_d8",
"mainpll_d2_d16"
};
static const char * const aud_1_parents[] = {
"clk26m",
"apll1_ck"
};
static const char * const aud_2_parents[] = {
"clk26m",
"apll2_ck"
};
static const char * const adsp_parents[] = {
"clk26m",
"mainpll_d3",
"univpll_d2_d4",
"univpll_d2",
"mmpll_d4",
"adsppll_d4",
"adsppll_d6"
};
static const char * const dpmaif_parents[] = {
"clk26m",
"univpll_d2_d4",
"mainpll_d3",
"mainpll_d2_d2",
"univpll_d2_d2",
"univpll_d3"
};
static const char * const venc_parents[] = {
"clk26m",
"mmpll_d7",
"mainpll_d3",
"univpll_d2_d2",
"mainpll_d2_d2",
"univpll_d3",
"mmpll_d6",
"mainpll_d5",
"mainpll_d3_d2",
"mmpll_d4_d2",
"univpll_d2_d4",
"mmpll_d5",
"univpll_192m_d2"
};
static const char * const vdec_parents[] = {
"clk26m",
"univpll_d2_d4",
"mainpll_d3",
"univpll_d2_d2",
"mainpll_d2_d2",
"univpll_d3",
"univpll_d5",
"univpll_d5_d2",
"mainpll_d2",
"univpll_d2",
"univpll_192m_d2"
};
static const char * const camtm_parents[] = {
"clk26m",
"univpll_d7",
"univpll_d3_d2",
"univpll_d2_d2"
};
static const char * const pwm_parents[] = {
"clk26m",
"univpll_d2_d8"
};
static const char * const audio_h_parents[] = {
"clk26m",
"univpll_d7",
"apll1_ck",
"apll2_ck"
};
static const char * const camtg5_parents[] = {
"clk26m",
"univpll_192m_d8",
"univpll_d3_d8",
"univpll_192m_d4",
"univpll_d3_d16",
"csw_f26m_ck_d2",
"univpll_192m_d16",
"univpll_192m_d32"
};
/*
* CRITICAL CLOCK:
* axi_sel is the main bus clock of whole SOC.
* spm_sel is the clock of the always-on co-processor.
* sspm_sel is the clock of the always-on co-processor.
*/
static const struct mtk_mux top_muxes[] = {
/* CLK_CFG_0 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "axi_sel", axi_parents,
0x20, 0x24, 0x28, 0, 2, 7,
0x004, 0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MM, "mm_sel", mm_parents,
0x20, 0x24, 0x28, 8, 3, 15, 0x004, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP, "scp_sel", scp_parents,
0x20, 0x24, 0x28, 16, 3, 23, 0x004, 2),
/* CLK_CFG_1 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "img_sel", img_parents,
0x30, 0x34, 0x38, 0, 3, 7, 0x004, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "ipe_sel", ipe_parents,
0x30, 0x34, 0x38, 8, 3, 15, 0x004, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE, "dpe_sel", dpe_parents,
0x30, 0x34, 0x38, 16, 3, 23, 0x004, 6),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "cam_sel", cam_parents,
0x30, 0x34, 0x38, 24, 4, 31, 0x004, 7),
/* CLK_CFG_2 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "ccu_sel", ccu_parents,
0x40, 0x44, 0x48, 0, 4, 7, 0x004, 8),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "dsp_sel", dsp_parents,
0x40, 0x44, 0x48, 8, 4, 15, 0x004, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "dsp1_sel", dsp1_parents,
0x40, 0x44, 0x48, 16, 4, 23, 0x004, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "dsp2_sel", dsp2_parents,
0x40, 0x44, 0x48, 24, 4, 31, 0x004, 11),
/* CLK_CFG_3 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "dsp3_sel", dsp3_parents,
0x50, 0x54, 0x58, 0, 4, 7, 0x004, 12),
MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF, "ipu_if_sel", ipu_if_parents,
0x50, 0x54, 0x58, 8, 4, 15, 0x004, 13),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG, "mfg_sel", mfg_parents,
0x50, 0x54, 0x58, 16, 2, 23, 0x004, 14),
MUX_GATE_CLR_SET_UPD(CLK_TOP_F52M_MFG, "f52m_mfg_sel",
f52m_mfg_parents, 0x50, 0x54, 0x58,
24, 2, 31, 0x004, 15),
/* CLK_CFG_4 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "camtg_sel", camtg_parents,
0x60, 0x64, 0x68, 0, 3, 7, 0x004, 16),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "camtg2_sel", camtg2_parents,
0x60, 0x64, 0x68, 8, 3, 15, 0x004, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "camtg3_sel", camtg3_parents,
0x60, 0x64, 0x68, 16, 3, 23, 0x004, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "camtg4_sel", camtg4_parents,
0x60, 0x64, 0x68, 24, 3, 31, 0x004, 19),
/* CLK_CFG_5 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "uart_sel", uart_parents,
0x70, 0x74, 0x78, 0, 1, 7, 0x004, 20),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "spi_sel", spi_parents,
0x70, 0x74, 0x78, 8, 2, 15, 0x004, 21),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel",
msdc50_hclk_parents, 0x70, 0x74, 0x78,
16, 2, 23, 0x004, 22, 0),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "msdc50_0_sel",
msdc50_0_parents, 0x70, 0x74, 0x78,
24, 3, 31, 0x004, 23, 0),
/* CLK_CFG_6 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "msdc30_1_sel",
msdc30_1_parents, 0x80, 0x84, 0x88,
0, 3, 7, 0x004, 24, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD, "audio_sel", audio_parents,
0x80, 0x84, 0x88, 8, 2, 15, 0x004, 25),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "aud_intbus_sel",
aud_intbus_parents, 0x80, 0x84, 0x88,
16, 2, 23, 0x004, 26),
MUX_GATE_CLR_SET_UPD(CLK_TOP_FPWRAP_ULPOSC, "fpwrap_ulposc_sel",
fpwrap_ulposc_parents, 0x80, 0x84, 0x88,
24, 3, 31, 0x004, 27),
/* CLK_CFG_7 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "atb_sel", atb_parents,
0x90, 0x94, 0x98, 0, 2, 7, 0x004, 28),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM, "sspm_sel", sspm_parents,
0x90, 0x94, 0x98, 8, 3, 15,
0x004, 29, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0, "dpi0_sel", dpi0_parents,
0x90, 0x94, 0x98, 16, 3, 23, 0x004, 30),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM, "scam_sel", scam_parents,
0x90, 0x94, 0x98, 24, 1, 31, 0x004, 0),
/* CLK_CFG_8 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM, "disppwm_sel",
disppwm_parents, 0xa0, 0xa4, 0xa8,
0, 3, 7, 0x008, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "usb_top_sel",
usb_top_parents, 0xa0, 0xa4, 0xa8,
8, 2, 15, 0x008, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel",
ssusb_top_xhci_parents, 0xa0, 0xa4, 0xa8,
16, 2, 23, 0x008, 3),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "spm_sel", spm_parents,
0xa0, 0xa4, 0xa8, 24, 2, 31,
0x008, 4, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
/* CLK_CFG_9 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "i2c_sel", i2c_parents,
0xb0, 0xb4, 0xb8, 0, 2, 7, 0x008, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "seninf_sel", seninf_parents,
0xb0, 0xb4, 0xb8, 8, 2, 15, 0x008, 6),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "seninf1_sel",
seninf1_parents, 0xb0, 0xb4, 0xb8,
16, 2, 23, 0x008, 7),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "seninf2_sel",
seninf2_parents, 0xb0, 0xb4, 0xb8,
24, 2, 31, 0x008, 8),
/* CLK_CFG_10 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "dxcc_sel", dxcc_parents,
0xc0, 0xc4, 0xc8, 0, 2, 7, 0x008, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG1, "aud_eng1_sel",
aud_engen1_parents, 0xc0, 0xc4, 0xc8,
8, 2, 15, 0x008, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG2, "aud_eng2_sel",
aud_engen2_parents, 0xc0, 0xc4, 0xc8,
16, 2, 23, 0x008, 11),
MUX_GATE_CLR_SET_UPD(CLK_TOP_FAES_UFSFDE, "faes_ufsfde_sel",
faes_ufsfde_parents, 0xc0, 0xc4, 0xc8,
24, 3, 31,
0x008, 12),
/* CLK_CFG_11 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_FUFS, "fufs_sel", fufs_parents,
0xd0, 0xd4, 0xd8, 0, 2, 7, 0x008, 13),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1, "aud_1_sel", aud_1_parents,
0xd0, 0xd4, 0xd8, 8, 1, 15, 0x008, 14),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2, "aud_2_sel", aud_2_parents,
0xd0, 0xd4, 0xd8, 16, 1, 23, 0x008, 15),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "adsp_sel", adsp_parents,
0xd0, 0xd4, 0xd8, 24, 3, 31, 0x008, 16),
/* CLK_CFG_12 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF, "dpmaif_sel", dpmaif_parents,
0xe0, 0xe4, 0xe8, 0, 3, 7, 0x008, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "venc_sel", venc_parents,
0xe0, 0xe4, 0xe8, 8, 4, 15, 0x008, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "vdec_sel", vdec_parents,
0xe0, 0xe4, 0xe8, 16, 4, 23, 0x008, 19),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "camtm_sel", camtm_parents,
0xe0, 0xe4, 0xe8, 24, 2, 31, 0x004, 20),
/* CLK_CFG_13 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "pwm_sel", pwm_parents,
0xf0, 0xf4, 0xf8, 0, 1, 7, 0x008, 21),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_H, "audio_h_sel",
audio_h_parents, 0xf0, 0xf4, 0xf8,
8, 2, 15, 0x008, 22),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "camtg5_sel", camtg5_parents,
0xf0, 0xf4, 0xf8, 24, 3, 31, 0x008, 24),
};
static const char * const i2s0_m_ck_parents[] = {
"aud_1_sel",
"aud_2_sel"
};
static const char * const i2s1_m_ck_parents[] = {
"aud_1_sel",
"aud_2_sel"
};
static const char * const i2s2_m_ck_parents[] = {
"aud_1_sel",
"aud_2_sel"
};
static const char * const i2s3_m_ck_parents[] = {
"aud_1_sel",
"aud_2_sel"
};
static const char * const i2s4_m_ck_parents[] = {
"aud_1_sel",
"aud_2_sel"
};
static const char * const i2s5_m_ck_parents[] = {
"aud_1_sel",
"aud_2_sel"
};
static const struct mtk_composite top_aud_muxes[] = {
MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents,
0x320, 8, 1),
MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents,
0x320, 9, 1),
MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents,
0x320, 10, 1),
MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents,
0x320, 11, 1),
MUX(CLK_TOP_I2S4_M_SEL, "i2s4_m_ck_sel", i2s4_m_ck_parents,
0x320, 12, 1),
MUX(CLK_TOP_I2S5_M_SEL, "i2s5_m_ck_sel", i2s5_m_ck_parents,
0x328, 20, 1),
};
static struct mtk_composite top_aud_divs[] = {
DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "i2s0_m_ck_sel",
0x320, 2, 0x324, 8, 0),
DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "i2s1_m_ck_sel",
0x320, 3, 0x324, 8, 8),
DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "i2s2_m_ck_sel",
0x320, 4, 0x324, 8, 16),
DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "i2s3_m_ck_sel",
0x320, 5, 0x324, 8, 24),
DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "i2s4_m_ck_sel",
0x320, 6, 0x328, 8, 0),
DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4",
0x320, 7, 0x328, 8, 8),
DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "i2s5_m_ck_sel",
0x328, 16, 0x328, 4, 28),
};
static const struct mtk_gate_regs infra0_cg_regs = {
.set_ofs = 0x80,
.clr_ofs = 0x84,
.sta_ofs = 0x90,
};
static const struct mtk_gate_regs infra1_cg_regs = {
.set_ofs = 0x88,
.clr_ofs = 0x8c,
.sta_ofs = 0x94,
};
static const struct mtk_gate_regs infra2_cg_regs = {
.set_ofs = 0xa4,
.clr_ofs = 0xa8,
.sta_ofs = 0xac,
};
static const struct mtk_gate_regs infra3_cg_regs = {
.set_ofs = 0xc0,
.clr_ofs = 0xc4,
.sta_ofs = 0xc8,
};
#define GATE_INFRA0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr)
#define GATE_INFRA1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr)
#define GATE_INFRA2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr)
#define GATE_INFRA3(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr)
static const struct mtk_gate infra_clks[] = {
GATE_DUMMY(CLK_DUMMY, "ifa_dummy"),
/* INFRA0 */
GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr",
"axi_sel", 0),
GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap",
"axi_sel", 1),
GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md",
"axi_sel", 2),
GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn",
"axi_sel", 3),
GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp",
"axi_sel", 4),
GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej",
"f_f26m_ck", 5),
GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt",
"axi_sel", 6),
GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb",
"axi_sel", 8),
GATE_INFRA0(CLK_INFRA_GCE, "infra_gce",
"axi_sel", 9),
GATE_INFRA0(CLK_INFRA_THERM, "infra_therm",
"axi_sel", 10),
GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0",
"i2c_sel", 11),
GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1",
"i2c_sel", 12),
GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2",
"i2c_sel", 13),
GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3",
"i2c_sel", 14),
GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk",
"pwm_sel", 15),
GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1",
"pwm_sel", 16),
GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2",
"pwm_sel", 17),
GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3",
"pwm_sel", 18),
GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4",
"pwm_sel", 19),
GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
"pwm_sel", 21),
GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
"uart_sel", 22),
GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
"uart_sel", 23),
GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
"uart_sel", 24),
GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3",
"uart_sel", 25),
GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m",
"axi_sel", 27),
GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc",
"axi_sel", 28),
GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif",
"axi_sel", 31),
/* INFRA1 */
GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0",
"spi_sel", 1),
GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0",
"msdc50_hclk_sel", 2),
GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1",
"axi_sel", 4),
GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2",
"axi_sel", 5),
GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck",
"msdc50_0_sel", 6),
GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc",
"f_f26m_ck", 7),
GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu",
"axi_sel", 8),
GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng",
"axi_sel", 9),
GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc",
"f_f26m_ck", 10),
GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum",
"axi_sel", 11),
GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap",
"axi_sel", 12),
GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md",
"axi_sel", 13),
GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md",
"f_f26m_ck", 14),
GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck",
"msdc30_1_sel", 16),
GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck",
"msdc30_2_sel", 17),
GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma",
"axi_sel", 18),
GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu",
"axi_sel", 19),
GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc",
"axi_sel", 20),
GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap",
"axi_sel", 23),
GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys",
"axi_sel", 24),
GATE_INFRA1(CLK_INFRA_AUD, "infra_audio",
"axi_sel", 25),
GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md",
"axi_sel", 26),
GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core",
"dxcc_sel", 27),
GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao",
"dxcc_sel", 28),
GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk",
"axi_sel", 30),
GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
"f_f26m_ck", 31),
/* INFRA2 */
GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx",
"f_f26m_ck", 0),
GATE_INFRA2(CLK_INFRA_USB, "infra_usb",
"usb_top_sel", 1),
GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm",
"axi_sel", 2),
GATE_INFRA2(CLK_INFRA_AUD_26M_BCLK,
"infracfg_ao_audio_26m_bclk", "f_f26m_ck", 4),
GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1",
"spi_sel", 6),
GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4",
"i2c_sel", 7),
GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share",
"f_f26m_ck", 8),
GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2",
"spi_sel", 9),
GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3",
"spi_sel", 10),
GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck",
"fufs_sel", 11),
GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick",
"fufs_sel", 12),
GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck",
"fufs_sel", 13),
GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk",
"axi_sel", 14),
GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist",
"axi_sel", 16),
GATE_INFRA2(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk",
"axi_sel", 17),
GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5",
"i2c_sel", 18),
GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter",
"i2c_sel", 19),
GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm",
"i2c_sel", 20),
GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter",
"i2c_sel", 21),
GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm",
"i2c_sel", 22),
GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter",
"i2c_sel", 23),
GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm",
"i2c_sel", 24),
GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4",
"spi_sel", 25),
GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5",
"spi_sel", 26),
GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma",
"axi_sel", 27),
GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs",
"fufs_sel", 28),
GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde",
"faes_ufsfde_sel", 29),
GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick",
"fufs_sel", 30),
GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci",
"ssusb_top_xhci_sel", 31),
/* INFRA3 */
GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self",
"msdc50_0_sel", 0),
GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self",
"msdc50_0_sel", 1),
GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self",
"msdc50_0_sel", 2),
GATE_INFRA3(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self",
"f_f26m_ck", 3),
GATE_INFRA3(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self",
"f_f26m_ck", 4),
GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi",
"axi_sel", 5),
GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6",
"i2c_sel", 6),
GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0",
"msdc50_hclk_sel", 7),
GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0",
"msdc50_hclk_sel", 8),
GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap",
"axi_sel", 16),
GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md",
"axi_sel", 17),
GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap",
"axi_sel", 18),
GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md",
"axi_sel", 19),
GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m",
"f_f26m_ck", 20),
GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk",
"axi_sel", 21),
GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7",
"i2c_sel", 22),
GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8",
"i2c_sel", 23),
GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc",
"msdc50_0_sel", 24),
GATE_INFRA3(CLK_INFRA_DPMAIF_CK, "infra_dpmaif",
"dpmaif_sel", 26),
GATE_INFRA3(CLK_INFRA_FADSP, "infra_fadsp",
"adsp_sel", 27),
GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap",
"axi_sel", 28),
GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md",
"axi_sel", 29),
GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6",
"spi_sel", 30),
GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7",
"spi_sel", 31),
};
static const struct mtk_gate_regs apmixed_cg_regs = {
.set_ofs = 0x20,
.clr_ofs = 0x20,
.sta_ofs = 0x20,
};
#define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \
GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \
_shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
#define GATE_APMIXED(_id, _name, _parent, _shift) \
GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
/*
* CRITICAL CLOCK:
* apmixed_appll26m is the toppest clock gate of all PLLs.
*/
static const struct mtk_gate apmixed_clks[] = {
GATE_APMIXED(CLK_APMIXED_SSUSB26M, "apmixed_ssusb26m",
"f_f26m_ck", 4),
GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL26M, "apmixed_appll26m",
"f_f26m_ck", 5, CLK_IS_CRITICAL),
GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m",
"f_f26m_ck", 6),
GATE_APMIXED(CLK_APMIXED_MDPLLGP26M, "apmixed_mdpll26m",
"f_f26m_ck", 7),
GATE_APMIXED(CLK_APMIXED_MM_F26M, "apmixed_mmsys26m",
"f_f26m_ck", 8),
GATE_APMIXED(CLK_APMIXED_UFS26M, "apmixed_ufs26m",
"f_f26m_ck", 9),
GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m",
"f_f26m_ck", 11),
GATE_APMIXED(CLK_APMIXED_MEMPLL26M, "apmixed_mempll26m",
"f_f26m_ck", 13),
GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
"f_f26m_ck", 14),
GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m",
"f_f26m_ck", 16),
GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m",
"f_f26m_ck", 17),
};
#define MT6779_PLL_FMAX (3800UL * MHZ)
#define MT6779_PLL_FMIN (1500UL * MHZ)
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
_rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
_pd_shift, _tuner_reg, _tuner_en_reg, \
_tuner_en_bit, _pcw_reg, _pcw_shift, \
_pcw_chg_reg, _div_table) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = _en_mask, \
.flags = _flags, \
.rst_bar_mask = _rst_bar_mask, \
.fmax = MT6779_PLL_FMAX, \
.fmin = MT6779_PLL_FMIN, \
.pcwbits = _pcwbits, \
.pcwibits = _pcwibits, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, \
.tuner_en_reg = _tuner_en_reg, \
.tuner_en_bit = _tuner_en_bit, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
.pcw_chg_reg = _pcw_chg_reg, \
.div_table = _div_table, \
}
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
_rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
_pd_shift, _tuner_reg, _tuner_en_reg, \
_tuner_en_bit, _pcw_reg, _pcw_shift, \
_pcw_chg_reg) \
PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
_rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
_pd_shift, _tuner_reg, _tuner_en_reg, \
_tuner_en_bit, _pcw_reg, _pcw_shift, \
_pcw_chg_reg, NULL)
static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0,
PLL_AO, 0, 22, 8, 0x0204, 24, 0, 0, 0, 0x0204, 0, 0),
PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, 0,
PLL_AO, 0, 22, 8, 0x0214, 24, 0, 0, 0, 0x0214, 0, 0),
PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, 0,
PLL_AO, 0, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0, 0),
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0,
(HAVE_RST_BAR), BIT(24), 22, 8, 0x0234, 24, 0, 0, 0,
0x0234, 0, 0),
PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, 0,
(HAVE_RST_BAR), BIT(24), 22, 8, 0x0244, 24,
0, 0, 0, 0x0244, 0, 0),
PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, 0,
0, 0, 22, 8, 0x0254, 24, 0, 0, 0, 0x0254, 0, 0),
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, 0,
0, 0, 22, 8, 0x0264, 24, 0, 0, 0, 0x0264, 0, 0),
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0,
0, 0, 22, 8, 0x0274, 24, 0, 0, 0, 0x0274, 0, 0),
PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, 0,
(HAVE_RST_BAR), BIT(23), 22, 8, 0x02b4, 24,
0, 0, 0, 0x02b4, 0, 0),
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, 0,
(HAVE_RST_BAR), BIT(23), 22, 8, 0x0284, 24,
0, 0, 0, 0x0284, 0, 0),
PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, 0,
0, 0, 32, 8, 0x02C0, 1, 0, 0x14, 0, 0x02C4, 0, 0x2C0),
PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, 0,
0, 0, 32, 8, 0x02D4, 1, 0, 0x14, 1, 0x02D8, 0, 0x02D4),
};
static int clk_mt6779_apmixed_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
ARRAY_SIZE(apmixed_clks), clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static int clk_mt6779_top_probe(struct platform_device *pdev)
{
void __iomem *base;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
clk_data);
mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
mtk_clk_register_muxes(&pdev->dev, top_muxes,
ARRAY_SIZE(top_muxes), node,
&mt6779_clk_lock, clk_data);
mtk_clk_register_composites(&pdev->dev, top_aud_muxes,
ARRAY_SIZE(top_aud_muxes), base,
&mt6779_clk_lock, clk_data);
mtk_clk_register_composites(&pdev->dev, top_aud_divs,
ARRAY_SIZE(top_aud_divs), base,
&mt6779_clk_lock, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct of_device_id of_match_clk_mt6779[] = {
{
.compatible = "mediatek,mt6779-apmixed",
.data = clk_mt6779_apmixed_probe,
}, {
.compatible = "mediatek,mt6779-topckgen",
.data = clk_mt6779_top_probe,
}, {
/* sentinel */
}
};
static int clk_mt6779_probe(struct platform_device *pdev)
{
int (*clk_probe)(struct platform_device *pdev);
int r;
clk_probe = of_device_get_match_data(&pdev->dev);
if (!clk_probe)
return -EINVAL;
r = clk_probe(pdev);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
return r;
}
static const struct mtk_clk_desc infra_desc = {
.clks = infra_clks,
.num_clks = ARRAY_SIZE(infra_clks),
};
static const struct of_device_id of_match_clk_mt6779_infra[] = {
{ .compatible = "mediatek,mt6779-infracfg_ao", .data = &infra_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6779);
static struct platform_driver clk_mt6779_infra_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt6779-infra",
.of_match_table = of_match_clk_mt6779_infra,
},
};
static struct platform_driver clk_mt6779_drv = {
.probe = clk_mt6779_probe,
.driver = {
.name = "clk-mt6779",
.of_match_table = of_match_clk_mt6779,
},
};
static int __init clk_mt6779_init(void)
{
int ret = platform_driver_register(&clk_mt6779_drv);
if (ret)
return ret;
return platform_driver_register(&clk_mt6779_infra_drv);
}
arch_initcall(clk_mt6779_init);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6779.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Weiyi Lu <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt2712-clk.h>
static const struct mtk_gate_regs mm0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs mm1_cg_regs = {
.set_ofs = 0x114,
.clr_ofs = 0x118,
.sta_ofs = 0x110,
};
static const struct mtk_gate_regs mm2_cg_regs = {
.set_ofs = 0x224,
.clr_ofs = 0x228,
.sta_ofs = 0x220,
};
#define GATE_MM0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_MM1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_MM2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate mm_clks[] = {
/* MM0 */
GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
GATE_MM0(CLK_MM_MDP_CROP, "mm_mdp_crop", "mm_sel", 10),
GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "clk32k", 15),
GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
/* MM1 */
GATE_MM1(CLK_MM_DISP_PWM0_MM, "mm_pwm0_mm", "mm_sel", 0),
GATE_MM1(CLK_MM_DISP_PWM0_26M, "mm_pwm0_26m", "pwm_sel", 1),
GATE_MM1(CLK_MM_DISP_PWM1_MM, "mm_pwm1_mm", "mm_sel", 2),
GATE_MM1(CLK_MM_DISP_PWM1_26M, "mm_pwm1_26m", "pwm_sel", 3),
GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_lntc", 5),
GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_lntc", 7),
GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "vpll_dpix", 8),
GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "vpll3_dpix", 10),
GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "vpll_dpix", 16),
GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx", 17),
GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
GATE_MM1(CLK_MM_SMI_COMMON1, "mm_smi_common1", "mm_sel", 21),
GATE_MM1(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 22),
GATE_MM1(CLK_MM_MDP_RDMA2, "mm_mdp_rdma2", "mm_sel", 23),
GATE_MM1(CLK_MM_MDP_TDSHP2, "mm_mdp_tdshp2", "mm_sel", 24),
GATE_MM1(CLK_MM_DISP_OVL2, "mm_disp_ovl2", "mm_sel", 25),
GATE_MM1(CLK_MM_DISP_WDMA2, "mm_disp_wdma2", "mm_sel", 26),
GATE_MM1(CLK_MM_DISP_COLOR2, "mm_disp_color2", "mm_sel", 27),
GATE_MM1(CLK_MM_DISP_AAL1, "mm_disp_aal1", "mm_sel", 28),
GATE_MM1(CLK_MM_DISP_OD1, "mm_disp_od1", "mm_sel", 29),
GATE_MM1(CLK_MM_LVDS1_PIXEL, "mm_lvds1_pixel", "vpll3_dpix", 30),
GATE_MM1(CLK_MM_LVDS1_CTS, "mm_lvds1_cts", "lvdstx3", 31),
/* MM2 */
GATE_MM2(CLK_MM_SMI_LARB7, "mm_smi_larb7", "mm_sel", 0),
GATE_MM2(CLK_MM_MDP_RDMA3, "mm_mdp_rdma3", "mm_sel", 1),
GATE_MM2(CLK_MM_MDP_WROT2, "mm_mdp_wrot2", "mm_sel", 2),
GATE_MM2(CLK_MM_DSI2, "mm_dsi2", "mm_sel", 3),
GATE_MM2(CLK_MM_DSI2_DIGITAL, "mm_dsi2_digital", "dsi0_lntc", 4),
GATE_MM2(CLK_MM_DSI3, "mm_dsi3", "mm_sel", 5),
GATE_MM2(CLK_MM_DSI3_DIGITAL, "mm_dsi3_digital", "dsi1_lntc", 6),
};
static const struct mtk_clk_desc mm_desc = {
.clks = mm_clks,
.num_clks = ARRAY_SIZE(mm_clks),
};
static const struct platform_device_id clk_mt2712_mm_id_table[] = {
{ .name = "clk-mt2712-mm", .driver_data = (kernel_ulong_t)&mm_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, clk_mt2712_mm_id_table);
static struct platform_driver clk_mt2712_mm_drv = {
.probe = mtk_clk_pdev_probe,
.remove_new = mtk_clk_pdev_remove,
.driver = {
.name = "clk-mt2712-mm",
},
.id_table = clk_mt2712_mm_id_table,
};
module_platform_driver(clk_mt2712_mm_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt2712-mm.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Kevin Chen <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt6797-clk.h>
static const struct mtk_gate_regs venc_cg_regs = {
.set_ofs = 0x0004,
.clr_ofs = 0x0008,
.sta_ofs = 0x0000,
};
#define GATE_VENC(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate venc_clks[] = {
GATE_VENC(CLK_VENC_0, "venc_0", "mm_sel", 0),
GATE_VENC(CLK_VENC_1, "venc_1", "venc_sel", 4),
GATE_VENC(CLK_VENC_2, "venc_2", "venc_sel", 8),
GATE_VENC(CLK_VENC_3, "venc_3", "venc_sel", 12),
};
static const struct mtk_clk_desc venc_desc = {
.clks = venc_clks,
.num_clks = ARRAY_SIZE(venc_clks),
};
static const struct of_device_id of_match_clk_mt6797_venc[] = {
{
.compatible = "mediatek,mt6797-vencsys",
.data = &venc_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6797_venc);
static struct platform_driver clk_mt6797_venc_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt6797-venc",
.of_match_table = of_match_clk_mt6797_venc,
},
};
module_platform_driver(clk_mt6797_venc_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6797-venc.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs vdo1_0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs vdo1_1_cg_regs = {
.set_ofs = 0x124,
.clr_ofs = 0x128,
.sta_ofs = 0x120,
};
static const struct mtk_gate_regs vdo1_2_cg_regs = {
.set_ofs = 0x134,
.clr_ofs = 0x138,
.sta_ofs = 0x130,
};
static const struct mtk_gate_regs vdo1_3_cg_regs = {
.set_ofs = 0x144,
.clr_ofs = 0x148,
.sta_ofs = 0x140,
};
static const struct mtk_gate_regs vdo1_4_cg_regs = {
.set_ofs = 0x400,
.clr_ofs = 0x400,
.sta_ofs = 0x400,
};
#define GATE_VDO1_0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO1_1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO1_2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO1_2_FLAGS(_id, _name, _parent, _shift, _flags) \
GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_2_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flags)
#define GATE_VDO1_3(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO1_4(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo1_4_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate vdo1_clks[] = {
/* VDO1_0 */
GATE_VDO1_0(CLK_VDO1_SMI_LARB2, "vdo1_smi_larb2", "top_vpp", 0),
GATE_VDO1_0(CLK_VDO1_SMI_LARB3, "vdo1_smi_larb3", "top_vpp", 1),
GATE_VDO1_0(CLK_VDO1_GALS, "vdo1_gals", "top_vpp", 2),
GATE_VDO1_0(CLK_VDO1_FAKE_ENG0, "vdo1_fake_eng0", "top_vpp", 3),
GATE_VDO1_0(CLK_VDO1_FAKE_ENG, "vdo1_fake_eng", "top_vpp", 4),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA0, "vdo1_mdp_rdma0", "top_vpp", 5),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA1, "vdo1_mdp_rdma1", "top_vpp", 6),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA2, "vdo1_mdp_rdma2", "top_vpp", 7),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA3, "vdo1_mdp_rdma3", "top_vpp", 8),
GATE_VDO1_0(CLK_VDO1_VPP_MERGE0, "vdo1_vpp_merge0", "top_vpp", 9),
GATE_VDO1_0(CLK_VDO1_VPP_MERGE1, "vdo1_vpp_merge1", "top_vpp", 10),
GATE_VDO1_0(CLK_VDO1_VPP_MERGE2, "vdo1_vpp_merge2", "top_vpp", 11),
GATE_VDO1_0(CLK_VDO1_VPP_MERGE3, "vdo1_vpp_merge3", "top_vpp", 12),
GATE_VDO1_0(CLK_VDO1_VPP_MERGE4, "vdo1_vpp_merge4", "top_vpp", 13),
GATE_VDO1_0(CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC, "vdo1_vpp2_to_vdo1_dl_async", "top_vpp", 14),
GATE_VDO1_0(CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC, "vdo1_vpp3_to_vdo1_dl_async", "top_vpp", 15),
GATE_VDO1_0(CLK_VDO1_DISP_MUTEX, "vdo1_disp_mutex", "top_vpp", 16),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA4, "vdo1_mdp_rdma4", "top_vpp", 17),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA5, "vdo1_mdp_rdma5", "top_vpp", 18),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA6, "vdo1_mdp_rdma6", "top_vpp", 19),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA7, "vdo1_mdp_rdma7", "top_vpp", 20),
GATE_VDO1_0(CLK_VDO1_DP_INTF0_MM, "vdo1_dp_intf0_mm", "top_vpp", 21),
GATE_VDO1_0(CLK_VDO1_DPI0_MM, "vdo1_dpi0_mm", "top_vpp", 22),
GATE_VDO1_0(CLK_VDO1_DPI1_MM, "vdo1_dpi1_mm", "top_vpp", 23),
GATE_VDO1_0(CLK_VDO1_DISP_MONITOR, "vdo1_disp_monitor", "top_vpp", 24),
GATE_VDO1_0(CLK_VDO1_MERGE0_DL_ASYNC, "vdo1_merge0_dl_async", "top_vpp", 25),
GATE_VDO1_0(CLK_VDO1_MERGE1_DL_ASYNC, "vdo1_merge1_dl_async", "top_vpp", 26),
GATE_VDO1_0(CLK_VDO1_MERGE2_DL_ASYNC, "vdo1_merge2_dl_async", "top_vpp", 27),
GATE_VDO1_0(CLK_VDO1_MERGE3_DL_ASYNC, "vdo1_merge3_dl_async", "top_vpp", 28),
GATE_VDO1_0(CLK_VDO1_MERGE4_DL_ASYNC, "vdo1_merge4_dl_async", "top_vpp", 29),
GATE_VDO1_0(CLK_VDO1_VDO0_DSC_TO_VDO1_DL_ASYNC, "vdo1_vdo0_dsc_to_vdo1_dl_async",
"top_vpp", 30),
GATE_VDO1_0(CLK_VDO1_VDO0_MERGE_TO_VDO1_DL_ASYNC, "vdo1_vdo0_merge_to_vdo1_dl_async",
"top_vpp", 31),
/* VDO1_1 */
GATE_VDO1_1(CLK_VDO1_HDR_VDO_FE0, "vdo1_hdr_vdo_fe0", "top_vpp", 0),
GATE_VDO1_1(CLK_VDO1_HDR_GFX_FE0, "vdo1_hdr_gfx_fe0", "top_vpp", 1),
GATE_VDO1_1(CLK_VDO1_HDR_VDO_BE, "vdo1_hdr_vdo_be", "top_vpp", 2),
GATE_VDO1_1(CLK_VDO1_HDR_VDO_FE1, "vdo1_hdr_vdo_fe1", "top_vpp", 16),
GATE_VDO1_1(CLK_VDO1_HDR_GFX_FE1, "vdo1_hdr_gfx_fe1", "top_vpp", 17),
GATE_VDO1_1(CLK_VDO1_DISP_MIXER, "vdo1_disp_mixer", "top_vpp", 18),
GATE_VDO1_1(CLK_VDO1_HDR_VDO_FE0_DL_ASYNC, "vdo1_hdr_vdo_fe0_dl_async", "top_vpp", 19),
GATE_VDO1_1(CLK_VDO1_HDR_VDO_FE1_DL_ASYNC, "vdo1_hdr_vdo_fe1_dl_async", "top_vpp", 20),
GATE_VDO1_1(CLK_VDO1_HDR_GFX_FE0_DL_ASYNC, "vdo1_hdr_gfx_fe0_dl_async", "top_vpp", 21),
GATE_VDO1_1(CLK_VDO1_HDR_GFX_FE1_DL_ASYNC, "vdo1_hdr_gfx_fe1_dl_async", "top_vpp", 22),
GATE_VDO1_1(CLK_VDO1_HDR_VDO_BE_DL_ASYNC, "vdo1_hdr_vdo_be_dl_async", "top_vpp", 23),
/* VDO1_2 */
GATE_VDO1_2(CLK_VDO1_DPI0, "vdo1_dpi0", "top_vpp", 0),
GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPI0, "vdo1_disp_monitor_dpi0", "top_vpp", 1),
GATE_VDO1_2(CLK_VDO1_DPI1, "vdo1_dpi1", "top_vpp", 8),
GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPI1, "vdo1_disp_monitor_dpi1", "top_vpp", 9),
GATE_VDO1_2_FLAGS(CLK_VDO1_DPINTF, "vdo1_dpintf", "top_dp", 16, CLK_SET_RATE_PARENT),
GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf", "top_vpp", 17),
/* VDO1_3 */
GATE_VDO1_3(CLK_VDO1_26M_SLOW, "vdo1_26m_slow", "clk26m", 8),
/* VDO1_4 */
GATE_VDO1_4(CLK_VDO1_DPI1_HDMI, "vdo1_dpi1_hdmi", "hdmi_txpll", 0),
};
static const struct mtk_clk_desc vdo1_desc = {
.clks = vdo1_clks,
.num_clks = ARRAY_SIZE(vdo1_clks),
};
static const struct platform_device_id clk_mt8195_vdo1_id_table[] = {
{ .name = "clk-mt8195-vdo1", .driver_data = (kernel_ulong_t)&vdo1_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, clk_mt8195_vdo1_id_table);
static struct platform_driver clk_mt8195_vdo1_drv = {
.probe = mtk_clk_pdev_probe,
.remove_new = mtk_clk_pdev_remove,
.driver = {
.name = "clk-mt8195-vdo1",
},
.id_table = clk_mt8195_vdo1_id_table,
};
module_platform_driver(clk_mt8195_vdo1_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8195-vdo1.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 MediaTek Inc.
* Copyright (c) 2023 Collabora, Ltd.
* AngeloGioacchino Del Regno <[email protected]>
*/
#include <dt-bindings/clock/mt7622-clk.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-pll.h"
#define MT7622_PLL_FMAX (2500UL * MHZ)
#define CON0_MT7622_RST_BAR BIT(27)
#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
_pcw_shift, _div_table, _parent_name) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = _en_mask, \
.flags = _flags, \
.rst_bar_mask = CON0_MT7622_RST_BAR, \
.fmax = MT7622_PLL_FMAX, \
.pcwbits = _pcwbits, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
.div_table = _div_table, \
.parent_name = _parent_name, \
}
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
_pcw_shift) \
PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
NULL, "clkxtal")
static const struct mtk_gate_regs apmixed_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0x8,
.sta_ofs = 0x8,
};
#define GATE_APMIXED_AO(_id, _name, _parent, _shift) \
GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, _shift, \
&mtk_clk_gate_ops_no_setclr_inv, CLK_IS_CRITICAL)
static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0,
PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0,
HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0,
HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0,
0, 21, 0x0300, 1, 0, 0x0304, 0),
PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0,
0, 21, 0x0314, 1, 0, 0x0318, 0),
PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0,
0, 31, 0x0324, 1, 0, 0x0328, 0),
PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0,
0, 31, 0x0334, 1, 0, 0x0338, 0),
PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0,
0, 21, 0x0344, 1, 0, 0x0348, 0),
PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0,
0, 21, 0x0358, 1, 0, 0x035C, 0),
};
static const struct mtk_gate apmixed_clks[] = {
GATE_APMIXED_AO(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
};
static int clk_mt7622_apmixed_probe(struct platform_device *pdev)
{
void __iomem *base;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
struct device *dev = &pdev->dev;
int ret;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK);
if (!clk_data)
return -ENOMEM;
ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
if (ret)
return ret;
ret = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
ARRAY_SIZE(apmixed_clks), clk_data);
if (ret)
goto unregister_plls;
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (ret)
goto unregister_gates;
return 0;
unregister_gates:
mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
unregister_plls:
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
return ret;
}
static void clk_mt7622_apmixed_remove(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
of_clk_del_provider(node);
mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
mtk_free_clk_data(clk_data);
}
static const struct of_device_id of_match_clk_mt7622_apmixed[] = {
{ .compatible = "mediatek,mt7622-apmixedsys" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_apmixed);
static struct platform_driver clk_mt7622_apmixed_drv = {
.probe = clk_mt7622_apmixed_probe,
.remove_new = clk_mt7622_apmixed_remove,
.driver = {
.name = "clk-mt7622-apmixed",
.of_match_table = of_match_clk_mt7622_apmixed,
},
};
module_platform_driver(clk_mt7622_apmixed_drv)
MODULE_DESCRIPTION("MediaTek MT7622 apmixedsys clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt7622-apmixedsys.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8192-clk.h>
static const struct mtk_gate_regs mdp0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs mdp1_cg_regs = {
.set_ofs = 0x124,
.clr_ofs = 0x128,
.sta_ofs = 0x120,
};
#define GATE_MDP0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mdp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_MDP1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mdp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate mdp_clks[] = {
/* MDP0 */
GATE_MDP0(CLK_MDP_RDMA0, "mdp_mdp_rdma0", "mdp_sel", 0),
GATE_MDP0(CLK_MDP_TDSHP0, "mdp_mdp_tdshp0", "mdp_sel", 1),
GATE_MDP0(CLK_MDP_IMG_DL_ASYNC0, "mdp_img_dl_async0", "mdp_sel", 2),
GATE_MDP0(CLK_MDP_IMG_DL_ASYNC1, "mdp_img_dl_async1", "mdp_sel", 3),
GATE_MDP0(CLK_MDP_RDMA1, "mdp_mdp_rdma1", "mdp_sel", 4),
GATE_MDP0(CLK_MDP_TDSHP1, "mdp_mdp_tdshp1", "mdp_sel", 5),
GATE_MDP0(CLK_MDP_SMI0, "mdp_smi0", "mdp_sel", 6),
GATE_MDP0(CLK_MDP_APB_BUS, "mdp_apb_bus", "mdp_sel", 7),
GATE_MDP0(CLK_MDP_WROT0, "mdp_mdp_wrot0", "mdp_sel", 8),
GATE_MDP0(CLK_MDP_RSZ0, "mdp_mdp_rsz0", "mdp_sel", 9),
GATE_MDP0(CLK_MDP_HDR0, "mdp_mdp_hdr0", "mdp_sel", 10),
GATE_MDP0(CLK_MDP_MUTEX0, "mdp_mdp_mutex0", "mdp_sel", 11),
GATE_MDP0(CLK_MDP_WROT1, "mdp_mdp_wrot1", "mdp_sel", 12),
GATE_MDP0(CLK_MDP_RSZ1, "mdp_mdp_rsz1", "mdp_sel", 13),
GATE_MDP0(CLK_MDP_HDR1, "mdp_mdp_hdr1", "mdp_sel", 14),
GATE_MDP0(CLK_MDP_FAKE_ENG0, "mdp_mdp_fake_eng0", "mdp_sel", 15),
GATE_MDP0(CLK_MDP_AAL0, "mdp_mdp_aal0", "mdp_sel", 16),
GATE_MDP0(CLK_MDP_AAL1, "mdp_mdp_aal1", "mdp_sel", 17),
GATE_MDP0(CLK_MDP_COLOR0, "mdp_mdp_color0", "mdp_sel", 18),
GATE_MDP0(CLK_MDP_COLOR1, "mdp_mdp_color1", "mdp_sel", 19),
/* MDP1 */
GATE_MDP1(CLK_MDP_IMG_DL_RELAY0_ASYNC0, "mdp_img_dl_relay0_async0", "mdp_sel", 0),
GATE_MDP1(CLK_MDP_IMG_DL_RELAY1_ASYNC1, "mdp_img_dl_relay1_async1", "mdp_sel", 8),
};
static const struct mtk_clk_desc mdp_desc = {
.clks = mdp_clks,
.num_clks = ARRAY_SIZE(mdp_clks),
};
static const struct of_device_id of_match_clk_mt8192_mdp[] = {
{
.compatible = "mediatek,mt8192-mdpsys",
.data = &mdp_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_mdp);
static struct platform_driver clk_mt8192_mdp_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8192-mdp",
.of_match_table = of_match_clk_mt8192_mdp,
},
};
module_platform_driver(clk_mt8192_mdp_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8192-mdp.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8192-clk.h>
static const struct mtk_gate_regs scp_adsp_cg_regs = {
.set_ofs = 0x180,
.clr_ofs = 0x180,
.sta_ofs = 0x180,
};
#define GATE_SCP_ADSP(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &scp_adsp_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate scp_adsp_clks[] = {
GATE_SCP_ADSP(CLK_SCP_ADSP_AUDIODSP, "scp_adsp_audiodsp", "adsp_sel", 0),
};
static const struct mtk_clk_desc scp_adsp_desc = {
.clks = scp_adsp_clks,
.num_clks = ARRAY_SIZE(scp_adsp_clks),
};
static const struct of_device_id of_match_clk_mt8192_scp_adsp[] = {
{
.compatible = "mediatek,mt8192-scp_adsp",
.data = &scp_adsp_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_scp_adsp);
static struct platform_driver clk_mt8192_scp_adsp_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8192-scp_adsp",
.of_match_table = of_match_clk_mt8192_scp_adsp,
},
};
module_platform_driver(clk_mt8192_scp_adsp_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8192-scp_adsp.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt8186-clk.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs mm0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs mm1_cg_regs = {
.set_ofs = 0x1a4,
.clr_ofs = 0x1a8,
.sta_ofs = 0x1a0,
};
#define GATE_MM0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_MM1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate mm_clks[] = {
/* MM0 */
GATE_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0", "top_disp", 0),
GATE_MM0(CLK_MM_APB_MM_BUS, "mm_apb_mm_bus", "top_disp", 1),
GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "top_disp", 2),
GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "top_disp", 3),
GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "top_disp", 4),
GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "top_disp", 5),
GATE_MM0(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "top_disp", 7),
GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "top_disp", 8),
GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "top_disp", 9),
GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "top_disp", 10),
GATE_MM0(CLK_MM_SMI_INFRA, "mm_smi_infra", "top_disp", 11),
GATE_MM0(CLK_MM_DISP_DSC_WRAP0, "mm_disp_dsc_wrap0", "top_disp", 12),
GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "top_disp", 13),
GATE_MM0(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0", "top_disp", 14),
GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "top_disp", 16),
GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "top_disp", 17),
GATE_MM0(CLK_MM_DSI0, "mm_dsi0", "top_disp", 19),
GATE_MM0(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0", "top_disp", 20),
GATE_MM0(CLK_MM_DISP_FAKE_ENG1, "mm_disp_fake_eng1", "top_disp", 21),
GATE_MM0(CLK_MM_SMI_GALS, "mm_smi_gals", "top_disp", 22),
GATE_MM0(CLK_MM_SMI_IOMMU, "mm_smi_iommu", "top_disp", 24),
GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "top_disp", 25),
GATE_MM0(CLK_MM_DISP_DPI, "mm_disp_dpi", "top_disp", 26),
/* MM1 */
GATE_MM1(CLK_MM_DSI0_DSI_CK_DOMAIN, "mm_dsi0_dsi_domain", "top_disp", 0),
GATE_MM1(CLK_MM_DISP_26M, "mm_disp_26m_ck", "top_disp", 10),
};
static const struct mtk_clk_desc mm_desc = {
.clks = mm_clks,
.num_clks = ARRAY_SIZE(mm_clks),
};
static const struct platform_device_id clk_mt8186_mm_id_table[] = {
{ .name = "clk-mt8186-mm", .driver_data = (kernel_ulong_t)&mm_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, clk_mt8186_mm_id_table);
static struct platform_driver clk_mt8186_mm_drv = {
.probe = mtk_clk_pdev_probe,
.remove_new = mtk_clk_pdev_remove,
.driver = {
.name = "clk-mt8186-mm",
},
.id_table = clk_mt8186_mm_id_table,
};
module_platform_driver(clk_mt8186_mm_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8186-mm.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: James Liao <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/container_of.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include "clk-pll.h"
#define MHZ (1000 * 1000)
#define REG_CON0 0
#define REG_CON1 4
#define CON0_BASE_EN BIT(0)
#define CON0_PWR_ON BIT(0)
#define CON0_ISO_EN BIT(1)
#define PCW_CHG_MASK BIT(31)
#define AUDPLL_TUNER_EN BIT(31)
/* default 7 bits integer, can be overridden with pcwibits. */
#define INTEGER_BITS 7
int mtk_pll_is_prepared(struct clk_hw *hw)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;
}
static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
u32 pcw, int postdiv)
{
int pcwbits = pll->data->pcwbits;
int pcwfbits = 0;
int ibits;
u64 vco;
u8 c = 0;
/* The fractional part of the PLL divider. */
ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
if (pcwbits > ibits)
pcwfbits = pcwbits - ibits;
vco = (u64)fin * pcw;
if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
c = 1;
vco >>= pcwfbits;
if (c)
vco++;
return ((unsigned long)vco + postdiv - 1) / postdiv;
}
static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)
{
u32 r;
if (pll->tuner_en_addr) {
r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
writel(r, pll->tuner_en_addr);
} else if (pll->tuner_addr) {
r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
writel(r, pll->tuner_addr);
}
}
static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
{
u32 r;
if (pll->tuner_en_addr) {
r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
writel(r, pll->tuner_en_addr);
} else if (pll->tuner_addr) {
r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
writel(r, pll->tuner_addr);
}
}
static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
int postdiv)
{
u32 chg, val;
/* disable tuner */
__mtk_pll_tuner_disable(pll);
/* set postdiv */
val = readl(pll->pd_addr);
val &= ~(POSTDIV_MASK << pll->data->pd_shift);
val |= (ffs(postdiv) - 1) << pll->data->pd_shift;
/* postdiv and pcw need to set at the same time if on same register */
if (pll->pd_addr != pll->pcw_addr) {
writel(val, pll->pd_addr);
val = readl(pll->pcw_addr);
}
/* set pcw */
val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
pll->data->pcw_shift);
val |= pcw << pll->data->pcw_shift;
writel(val, pll->pcw_addr);
chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
writel(chg, pll->pcw_chg_addr);
if (pll->tuner_addr)
writel(val + 1, pll->tuner_addr);
/* restore tuner_en */
__mtk_pll_tuner_enable(pll);
udelay(20);
}
/*
* mtk_pll_calc_values - calculate good values for a given input frequency.
* @pll: The pll
* @pcw: The pcw value (output)
* @postdiv: The post divider (output)
* @freq: The desired target frequency
* @fin: The input frequency
*
*/
void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
u32 freq, u32 fin)
{
unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);
const struct mtk_pll_div_table *div_table = pll->data->div_table;
u64 _pcw;
int ibits;
u32 val;
if (freq > pll->data->fmax)
freq = pll->data->fmax;
if (div_table) {
if (freq > div_table[0].freq)
freq = div_table[0].freq;
for (val = 0; div_table[val + 1].freq != 0; val++) {
if (freq > div_table[val + 1].freq)
break;
}
*postdiv = 1 << val;
} else {
for (val = 0; val < 5; val++) {
*postdiv = 1 << val;
if ((u64)freq * *postdiv >= fmin)
break;
}
}
/* _pcw = freq * postdiv / fin * 2^pcwfbits */
ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
_pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);
do_div(_pcw, fin);
*pcw = (u32)_pcw;
}
int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
u32 pcw = 0;
u32 postdiv;
mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
mtk_pll_set_rate_regs(pll, pcw, postdiv);
return 0;
}
unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
u32 postdiv;
u32 pcw;
postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;
postdiv = 1 << postdiv;
pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;
pcw &= GENMASK(pll->data->pcwbits - 1, 0);
return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
}
long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
u32 pcw = 0;
int postdiv;
mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);
return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
}
int mtk_pll_prepare(struct clk_hw *hw)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
u32 r;
r = readl(pll->pwr_addr) | CON0_PWR_ON;
writel(r, pll->pwr_addr);
udelay(1);
r = readl(pll->pwr_addr) & ~CON0_ISO_EN;
writel(r, pll->pwr_addr);
udelay(1);
r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);
writel(r, pll->en_addr);
if (pll->data->en_mask) {
r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
writel(r, pll->base_addr + REG_CON0);
}
__mtk_pll_tuner_enable(pll);
udelay(20);
if (pll->data->flags & HAVE_RST_BAR) {
r = readl(pll->base_addr + REG_CON0);
r |= pll->data->rst_bar_mask;
writel(r, pll->base_addr + REG_CON0);
}
return 0;
}
void mtk_pll_unprepare(struct clk_hw *hw)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
u32 r;
if (pll->data->flags & HAVE_RST_BAR) {
r = readl(pll->base_addr + REG_CON0);
r &= ~pll->data->rst_bar_mask;
writel(r, pll->base_addr + REG_CON0);
}
__mtk_pll_tuner_disable(pll);
if (pll->data->en_mask) {
r = readl(pll->base_addr + REG_CON0) & ~pll->data->en_mask;
writel(r, pll->base_addr + REG_CON0);
}
r = readl(pll->en_addr) & ~BIT(pll->data->pll_en_bit);
writel(r, pll->en_addr);
r = readl(pll->pwr_addr) | CON0_ISO_EN;
writel(r, pll->pwr_addr);
r = readl(pll->pwr_addr) & ~CON0_PWR_ON;
writel(r, pll->pwr_addr);
}
const struct clk_ops mtk_pll_ops = {
.is_prepared = mtk_pll_is_prepared,
.prepare = mtk_pll_prepare,
.unprepare = mtk_pll_unprepare,
.recalc_rate = mtk_pll_recalc_rate,
.round_rate = mtk_pll_round_rate,
.set_rate = mtk_pll_set_rate,
};
struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
const struct mtk_pll_data *data,
void __iomem *base,
const struct clk_ops *pll_ops)
{
struct clk_init_data init = {};
int ret;
const char *parent_name = "clk26m";
pll->base_addr = base + data->reg;
pll->pwr_addr = base + data->pwr_reg;
pll->pd_addr = base + data->pd_reg;
pll->pcw_addr = base + data->pcw_reg;
if (data->pcw_chg_reg)
pll->pcw_chg_addr = base + data->pcw_chg_reg;
else
pll->pcw_chg_addr = pll->base_addr + REG_CON1;
if (data->tuner_reg)
pll->tuner_addr = base + data->tuner_reg;
if (data->tuner_en_reg || data->tuner_en_bit)
pll->tuner_en_addr = base + data->tuner_en_reg;
if (data->en_reg)
pll->en_addr = base + data->en_reg;
else
pll->en_addr = pll->base_addr + REG_CON0;
pll->hw.init = &init;
pll->data = data;
init.name = data->name;
init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
init.ops = pll_ops;
if (data->parent_name)
init.parent_names = &data->parent_name;
else
init.parent_names = &parent_name;
init.num_parents = 1;
ret = clk_hw_register(NULL, &pll->hw);
if (ret) {
kfree(pll);
return ERR_PTR(ret);
}
return &pll->hw;
}
struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
void __iomem *base)
{
struct mtk_clk_pll *pll;
struct clk_hw *hw;
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
if (!pll)
return ERR_PTR(-ENOMEM);
hw = mtk_clk_register_pll_ops(pll, data, base, &mtk_pll_ops);
return hw;
}
void mtk_clk_unregister_pll(struct clk_hw *hw)
{
struct mtk_clk_pll *pll;
if (!hw)
return;
pll = to_mtk_clk_pll(hw);
clk_hw_unregister(hw);
kfree(pll);
}
int mtk_clk_register_plls(struct device_node *node,
const struct mtk_pll_data *plls, int num_plls,
struct clk_hw_onecell_data *clk_data)
{
void __iomem *base;
int i;
struct clk_hw *hw;
base = of_iomap(node, 0);
if (!base) {
pr_err("%s(): ioremap failed\n", __func__);
return -EINVAL;
}
for (i = 0; i < num_plls; i++) {
const struct mtk_pll_data *pll = &plls[i];
if (!IS_ERR_OR_NULL(clk_data->hws[pll->id])) {
pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",
node, pll->id);
continue;
}
hw = mtk_clk_register_pll(pll, base);
if (IS_ERR(hw)) {
pr_err("Failed to register clk %s: %pe\n", pll->name,
hw);
goto err;
}
clk_data->hws[pll->id] = hw;
}
return 0;
err:
while (--i >= 0) {
const struct mtk_pll_data *pll = &plls[i];
mtk_clk_unregister_pll(clk_data->hws[pll->id]);
clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
}
iounmap(base);
return PTR_ERR(hw);
}
EXPORT_SYMBOL_GPL(mtk_clk_register_plls);
__iomem void *mtk_clk_pll_get_base(struct clk_hw *hw,
const struct mtk_pll_data *data)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
return pll->base_addr - data->reg;
}
void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
struct clk_hw_onecell_data *clk_data)
{
__iomem void *base = NULL;
int i;
if (!clk_data)
return;
for (i = num_plls; i > 0; i--) {
const struct mtk_pll_data *pll = &plls[i - 1];
if (IS_ERR_OR_NULL(clk_data->hws[pll->id]))
continue;
/*
* This is quite ugly but unfortunately the clks don't have
* any device tied to them, so there's no place to store the
* pointer to the I/O region base address. We have to fetch
* it from one of the registered clks.
*/
base = mtk_clk_pll_get_base(clk_data->hws[pll->id], pll);
mtk_clk_unregister_pll(clk_data->hws[pll->id]);
clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
}
iounmap(base);
}
EXPORT_SYMBOL_GPL(mtk_clk_unregister_plls);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-pll.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Wendell Lin <[email protected]>
*/
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt6779-clk.h>
#include "clk-mtk.h"
#include "clk-gate.h"
static const struct mtk_gate_regs ipe_cg_regs = {
.set_ofs = 0x0004,
.clr_ofs = 0x0008,
.sta_ofs = 0x0000,
};
#define GATE_IPE(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr)
static const struct mtk_gate ipe_clks[] = {
GATE_IPE(CLK_IPE_LARB7, "ipe_larb7", "ipe_sel", 0),
GATE_IPE(CLK_IPE_LARB8, "ipe_larb8", "ipe_sel", 1),
GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "ipe_sel", 2),
GATE_IPE(CLK_IPE_FD, "ipe_fd", "ipe_sel", 3),
GATE_IPE(CLK_IPE_FE, "ipe_fe", "ipe_sel", 4),
GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "ipe_sel", 5),
GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "ipe_sel", 6),
};
static const struct mtk_clk_desc ipe_desc = {
.clks = ipe_clks,
.num_clks = ARRAY_SIZE(ipe_clks),
};
static const struct of_device_id of_match_clk_mt6779_ipe[] = {
{
.compatible = "mediatek,mt6779-ipesys",
.data = &ipe_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_ipe);
static struct platform_driver clk_mt6779_ipe_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt6779-ipe",
.of_match_table = of_match_clk_mt6779_ipe,
},
};
module_platform_driver(clk_mt6779_ipe_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6779-ipe.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 MediaTek Inc.
*/
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs apu_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_APU(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &apu_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr)
static const struct mtk_gate apu_clks[] = {
GATE_APU(CLK_APU_AHB, "apu_ahb", "ifr_apu_axi", 5),
GATE_APU(CLK_APU_EDMA, "apu_edma", "apu_sel", 4),
GATE_APU(CLK_APU_IF_CK, "apu_if_ck", "apu_if_sel", 3),
GATE_APU(CLK_APU_JTAG, "apu_jtag", "clk26m", 2),
GATE_APU(CLK_APU_AXI, "apu_axi", "apu_sel", 1),
GATE_APU(CLK_APU_IPU_CK, "apu_ck", "apu_sel", 0),
};
static const struct mtk_clk_desc apu_desc = {
.clks = apu_clks,
.num_clks = ARRAY_SIZE(apu_clks),
};
static const struct of_device_id of_match_clk_mt8365_apu[] = {
{
.compatible = "mediatek,mt8365-apu",
.data = &apu_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_apu);
static struct platform_driver clk_mt8365_apu_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8365-apu",
.of_match_table = of_match_clk_mt8365_apu,
},
};
module_platform_driver(clk_mt8365_apu_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8365-apu.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 MediaTek Inc.
* Author: Sam Shih <[email protected]>
* Author: Wenzhen Yu <[email protected]>
* Author: Jianhui Zhao <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include "clk-mux.h"
#include <dt-bindings/clock/mediatek,mt7981-clk.h>
#include <linux/clk.h>
static DEFINE_SPINLOCK(mt7981_clk_lock);
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1),
FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1),
FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2),
FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3),
FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2),
FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4),
FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8),
FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16),
FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1),
FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2),
FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3),
FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15),
FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4),
FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6),
FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12),
FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8),
FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1),
FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1),
FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4),
FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5),
FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10),
FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20),
FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8),
FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16),
FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32),
FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1),
FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2),
FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4),
FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8),
FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16),
FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6),
FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1),
FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1),
FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2),
FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250),
FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220),
FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1),
FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1),
FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1),
FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1),
FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1),
FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1),
FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1),
FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1),
FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1),
FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1),
FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1),
FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1),
FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1),
FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1),
FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1),
FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1),
FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1),
FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1),
FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1),
FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1),
FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1),
FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1),
FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1),
FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1),
FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1),
FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1),
FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1),
FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1),
FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1),
FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1),
FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1),
FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1),
FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1),
FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1),
FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1),
FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1),
FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1),
FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1),
};
static const char * const nfi1x_parents[] __initconst = {
"cb_cksq_40m",
"cb_mm_d4",
"net1_d8_d2",
"cb_net2_d6",
"cb_m_d4",
"cb_mm_d8",
"net1_d8_d4",
"cb_m_d8"
};
static const char * const spinfi_parents[] __initconst = {
"cksq_40m_d2",
"cb_cksq_40m",
"net1_d5_d4",
"cb_m_d4",
"cb_mm_d8",
"net1_d8_d4",
"mm_d6_d2",
"cb_m_d8"
};
static const char * const spi_parents[] __initconst = {
"cb_cksq_40m",
"cb_m_d2",
"cb_mm_d4",
"net1_d8_d2",
"cb_net2_d6",
"net1_d5_d4",
"cb_m_d4",
"net1_d8_d4"
};
static const char * const uart_parents[] __initconst = {
"cb_cksq_40m",
"cb_m_d8",
"m_d8_d2"
};
static const char * const pwm_parents[] __initconst = {
"cb_cksq_40m",
"net1_d8_d2",
"net1_d5_d4",
"cb_m_d4",
"m_d8_d2",
"cb_rtc_32k"
};
static const char * const i2c_parents[] __initconst = {
"cb_cksq_40m",
"net1_d5_d4",
"cb_m_d4",
"net1_d8_d4"
};
static const char * const pextp_tl_ck_parents[] __initconst = {
"cb_cksq_40m",
"net1_d5_d4",
"cb_m_d4",
"cb_rtc_32k"
};
static const char * const emmc_208m_parents[] __initconst = {
"cb_cksq_40m",
"cb_m_d2",
"cb_net2_d4",
"cb_apll2_196m",
"cb_mm_d4",
"net1_d8_d2",
"cb_mm_d6"
};
static const char * const emmc_400m_parents[] __initconst = {
"cb_cksq_40m",
"cb_net2_d2",
"cb_mm_d2",
"cb_net2_d2"
};
static const char * const csw_f26m_parents[] __initconst = {
"cksq_40m_d2",
"m_d8_d2"
};
static const char * const dramc_md32_parents[] __initconst = {
"cb_cksq_40m",
"cb_m_d2",
"cb_wedmcu_208m"
};
static const char * const sysaxi_parents[] __initconst = {
"cb_cksq_40m",
"net1_d8_d2"
};
static const char * const sysapb_parents[] __initconst = {
"cb_cksq_40m",
"m_d3_d2"
};
static const char * const arm_db_main_parents[] __initconst = {
"cb_cksq_40m",
"cb_net2_d6"
};
static const char * const ap2cnn_host_parents[] __initconst = {
"cb_cksq_40m",
"net1_d8_d4"
};
static const char * const netsys_parents[] __initconst = {
"cb_cksq_40m",
"cb_mm_d2"
};
static const char * const netsys_500m_parents[] __initconst = {
"cb_cksq_40m",
"cb_net1_d5"
};
static const char * const netsys_mcu_parents[] __initconst = {
"cb_cksq_40m",
"cb_mm_720m",
"cb_net1_d4",
"cb_net1_d5",
"cb_m_416m"
};
static const char * const netsys_2x_parents[] __initconst = {
"cb_cksq_40m",
"cb_net2_800m",
"cb_mm_720m"
};
static const char * const sgm_325m_parents[] __initconst = {
"cb_cksq_40m",
"cb_sgm_325m"
};
static const char * const sgm_reg_parents[] __initconst = {
"cb_cksq_40m",
"cb_net2_d4"
};
static const char * const eip97b_parents[] __initconst = {
"cb_cksq_40m",
"cb_net1_d5",
"cb_m_416m",
"cb_mm_d2",
"net1_d5_d2"
};
static const char * const aud_parents[] __initconst = {
"cb_cksq_40m",
"cb_apll2_196m"
};
static const char * const a1sys_parents[] __initconst = {
"cb_cksq_40m",
"apll2_d4"
};
static const char * const aud_l_parents[] __initconst = {
"cb_cksq_40m",
"cb_apll2_196m",
"m_d8_d2"
};
static const char * const a_tuner_parents[] __initconst = {
"cb_cksq_40m",
"apll2_d4",
"m_d8_d2"
};
static const char * const u2u3_parents[] __initconst = {
"cb_cksq_40m",
"m_d8_d2"
};
static const char * const u2u3_sys_parents[] __initconst = {
"cb_cksq_40m",
"net1_d5_d4"
};
static const char * const usb_frmcnt_parents[] __initconst = {
"cb_cksq_40m",
"cb_mm_d3_d5"
};
static const struct mtk_mux top_muxes[] = {
/* CLK_CFG_0 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
/* CLK_CFG_1 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31,
0x1C0, 7),
/* CLK_CFG_2 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel",
emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
0x1C0, 8, 0),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15,
0x1C0, 9, 0),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23,
0x1C0, 10,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1,
31, 0x1C0, 11,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
/* CLK_CFG_3 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2,
7, 0x1C0, 12,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15,
0x1C0, 13,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
sysapb_parents, 0x030, 0x034, 0x038, 16, 1,
23, 0x1C0, 14,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31,
0x1C0, 15),
/* CLK_CFG_4 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7,
0x1C0, 16),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23,
0x1C0, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
0x1C0, 19),
/* CLK_CFG_5 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
0x1C0, 20),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
0x1C0, 21),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
/* CLK_CFG_6 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1,
7, 0x1C0, 24),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060,
0x064, 0x068, 8, 1, 15, 0x1C0, 25),
MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27),
/* CLK_CFG_7 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7,
0x1C0, 28),
MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070,
0x074, 0x078, 8, 1, 15, 0x1C0, 29),
MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23,
0x1C0, 30),
MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31,
0x1C4, 0),
/* CLK_CFG_8 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7,
0x1C4, 1),
};
static struct mtk_composite top_aud_divs[] = {
DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud",
0x0420, 0, 0x0420, 8, 8),
};
static const struct mtk_clk_desc topck_desc = {
.factor_clks = top_divs,
.num_factor_clks = ARRAY_SIZE(top_divs),
.mux_clks = top_muxes,
.num_mux_clks = ARRAY_SIZE(top_muxes),
.composite_clks = top_aud_divs,
.num_composite_clks = ARRAY_SIZE(top_aud_divs),
.clk_lock = &mt7981_clk_lock,
};
static const struct of_device_id of_match_clk_mt7981_topckgen[] = {
{ .compatible = "mediatek,mt7981-topckgen", .data = &topck_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7981_topckgen);
static struct platform_driver clk_mt7981_topckgen_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7981-topckgen",
.of_match_table = of_match_clk_mt7981_topckgen,
},
};
module_platform_driver(clk_mt7981_topckgen_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt7981-topckgen.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 MediaTek Inc.
* Author: Wenzhen Yu <Wenzhen [email protected]>
* Ryder Lee <[email protected]>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "clk-cpumux.h"
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-pll.h"
#include <dt-bindings/clock/mt7629-clk.h>
#define MT7629_PLL_FMAX (2500UL * MHZ)
#define CON0_MT7629_RST_BAR BIT(24)
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
_pcw_shift, _div_table, _parent_name) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = _en_mask, \
.flags = _flags, \
.rst_bar_mask = CON0_MT7629_RST_BAR, \
.fmax = MT7629_PLL_FMAX, \
.pcwbits = _pcwbits, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
.div_table = _div_table, \
.parent_name = _parent_name, \
}
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
_pcw_shift) \
PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
NULL, "clk20m")
#define GATE_APMIXED(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
#define GATE_INFRA(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_PERI0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_PERI1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static DEFINE_SPINLOCK(mt7629_clk_lock);
static const char * const axi_parents[] = {
"clkxtal",
"syspll1_d2",
"syspll_d5",
"syspll1_d4",
"univpll_d5",
"univpll2_d2",
"univpll_d7",
"dmpll_ck"
};
static const char * const mem_parents[] = {
"clkxtal",
"dmpll_ck"
};
static const char * const ddrphycfg_parents[] = {
"clkxtal",
"syspll1_d8"
};
static const char * const eth_parents[] = {
"clkxtal",
"syspll1_d2",
"univpll1_d2",
"syspll1_d4",
"univpll_d5",
"sgmiipll_d2",
"univpll_d7",
"dmpll_ck"
};
static const char * const pwm_parents[] = {
"clkxtal",
"univpll2_d4"
};
static const char * const f10m_ref_parents[] = {
"clkxtal",
"sgmiipll_d2"
};
static const char * const nfi_infra_parents[] = {
"clkxtal",
"clkxtal",
"clkxtal",
"clkxtal",
"clkxtal",
"clkxtal",
"univpll2_d8",
"univpll3_d4",
"syspll1_d8",
"univpll1_d8",
"syspll4_d2",
"syspll2_d4",
"univpll2_d4",
"univpll3_d2",
"syspll1_d4",
"syspll_d7"
};
static const char * const flash_parents[] = {
"clkxtal",
"univpll_d80_d4",
"syspll2_d8",
"syspll3_d4",
"univpll3_d4",
"univpll1_d8",
"syspll2_d4",
"univpll2_d4"
};
static const char * const uart_parents[] = {
"clkxtal",
"univpll2_d8"
};
static const char * const spi0_parents[] = {
"clkxtal",
"syspll3_d2",
"clkxtal",
"syspll2_d4",
"syspll4_d2",
"univpll2_d4",
"univpll1_d8",
"clkxtal"
};
static const char * const spi1_parents[] = {
"clkxtal",
"syspll3_d2",
"clkxtal",
"syspll4_d4",
"syspll4_d2",
"univpll2_d4",
"univpll1_d8",
"clkxtal"
};
static const char * const msdc30_0_parents[] = {
"clkxtal",
"univpll2_d16",
"univ48m"
};
static const char * const msdc30_1_parents[] = {
"clkxtal",
"univpll2_d16",
"univ48m",
"syspll2_d4",
"univpll2_d4",
"syspll_d7",
"syspll2_d2",
"univpll2_d2"
};
static const char * const ap2wbmcu_parents[] = {
"clkxtal",
"syspll1_d2",
"univ48m",
"syspll1_d8",
"univpll2_d4",
"syspll_d7",
"syspll2_d2",
"univpll2_d2"
};
static const char * const audio_parents[] = {
"clkxtal",
"syspll3_d4",
"syspll4_d4",
"syspll1_d16"
};
static const char * const aud_intbus_parents[] = {
"clkxtal",
"syspll1_d4",
"syspll4_d2",
"dmpll_d4"
};
static const char * const pmicspi_parents[] = {
"clkxtal",
"syspll1_d8",
"syspll3_d4",
"syspll1_d16",
"univpll3_d4",
"clkxtal",
"univpll2_d4",
"dmpll_d8"
};
static const char * const scp_parents[] = {
"clkxtal",
"syspll1_d8",
"univpll2_d2",
"univpll2_d4"
};
static const char * const atb_parents[] = {
"clkxtal",
"syspll1_d2",
"syspll_d5"
};
static const char * const hif_parents[] = {
"clkxtal",
"syspll1_d2",
"univpll1_d2",
"syspll1_d4",
"univpll_d5",
"clk_null",
"univpll_d7"
};
static const char * const sata_parents[] = {
"clkxtal",
"univpll2_d4"
};
static const char * const usb20_parents[] = {
"clkxtal",
"univpll3_d4",
"syspll1_d8"
};
static const char * const aud1_parents[] = {
"clkxtal"
};
static const char * const irrx_parents[] = {
"clkxtal",
"syspll4_d16"
};
static const char * const crypto_parents[] = {
"clkxtal",
"univpll_d3",
"univpll1_d2",
"syspll1_d2",
"univpll_d5",
"syspll_d5",
"univpll2_d2",
"syspll_d2"
};
static const char * const gpt10m_parents[] = {
"clkxtal",
"clkxtal_d4"
};
static const char * const peribus_ck_parents[] = {
"syspll1_d8",
"syspll1_d4"
};
static const char * const infra_mux1_parents[] = {
"clkxtal",
"armpll",
"main_core_en",
"armpll"
};
static const struct mtk_gate_regs apmixed_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0x8,
.sta_ofs = 0x8,
};
static const struct mtk_gate_regs infra_cg_regs = {
.set_ofs = 0x40,
.clr_ofs = 0x44,
.sta_ofs = 0x48,
};
static const struct mtk_gate_regs peri0_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0x10,
.sta_ofs = 0x18,
};
static const struct mtk_gate_regs peri1_cg_regs = {
.set_ofs = 0xC,
.clr_ofs = 0x14,
.sta_ofs = 0x1C,
};
static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0,
0, 21, 0x0204, 24, 0, 0x0204, 0),
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0,
HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0,
HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0,
0, 21, 0x0300, 1, 0, 0x0304, 0),
PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0,
0, 21, 0x0314, 1, 0, 0x0318, 0),
PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0,
0, 21, 0x0358, 1, 0, 0x035C, 0),
};
static const struct mtk_gate apmixed_clks[] = {
GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
};
static const struct mtk_gate infra_clks[] = {
GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "hd_faxi", 0),
GATE_INFRA(CLK_INFRA_TRNG_PD, "infra_trng_pd", "hd_faxi", 2),
GATE_INFRA(CLK_INFRA_DEVAPC_PD, "infra_devapc_pd", "hd_faxi", 4),
GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "infrao_10m", 18),
GATE_INFRA(CLK_INFRA_SEJ_PD, "infra_sej_pd", "infrao_10m", 19),
};
static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
31250000),
FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal",
31250000),
FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal",
125000000),
FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal",
125000000),
FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal",
250000000),
FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal",
250000000),
FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal",
33333333),
FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal",
50000000),
FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal",
50000000),
FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal",
50000000),
};
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1),
FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1),
FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024),
FACTOR(CLK_TOP_PWM_QTR_26M, "pwm_qtr_26m", "clkxtal", 1, 1),
FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "cpum_tck", 1, 1),
FACTOR(CLK_TOP_TO_USB3_DA_TOP, "to_usb3_da_top", "clkxtal", 1, 1),
FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1),
FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "mempll", 1, 4),
FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "mempll", 1, 8),
FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32),
FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 6),
FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112),
FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48),
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80),
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320),
FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25),
FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2),
FACTOR(CLK_TOP_CLKXTAL_D4, "clkxtal_d4", "clkxtal", 1, 4),
FACTOR(CLK_TOP_HD_FAXI, "hd_faxi", "axi_sel", 1, 1),
FACTOR(CLK_TOP_FAXI, "faxi", "axi_sel", 1, 1),
FACTOR(CLK_TOP_F_FAUD_INTBUS, "f_faud_intbus", "aud_intbus_sel", 1, 1),
FACTOR(CLK_TOP_AP2WBHIF_HCLK, "ap2wbhif_hclk", "syspll1_d8", 1, 1),
FACTOR(CLK_TOP_10M_INFRAO, "infrao_10m", "gpt10m_sel", 1, 1),
FACTOR(CLK_TOP_MSDC30_1, "msdc30_1", "msdc30_1_sel", 1, 1),
FACTOR(CLK_TOP_SPI, "spi", "spi0_sel", 1, 1),
FACTOR(CLK_TOP_SF, "sf", "nfi_infra_sel", 1, 1),
FACTOR(CLK_TOP_FLASH, "flash", "flash_sel", 1, 1),
FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "sata_sel", 1, 4),
FACTOR(CLK_TOP_TO_USB3_MCU, "to_usb3_mcu", "axi_sel", 1, 1),
FACTOR(CLK_TOP_TO_USB3_DMA, "to_usb3_dma", "hif_sel", 1, 1),
FACTOR(CLK_TOP_FROM_TOP_AHB, "from_top_ahb", "axi_sel", 1, 1),
FACTOR(CLK_TOP_FROM_TOP_AXI, "from_top_axi", "hif_sel", 1, 1),
FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "sata_sel", 1, 1),
FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "sata_sel", 1, 1),
};
static const struct mtk_gate peri_clks[] = {
/* PERI0 */
GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "pwm_qtr_26m", 2),
GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "pwm_qtr_26m", 3),
GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "pwm_qtr_26m", 4),
GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "pwm_qtr_26m", 5),
GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "pwm_qtr_26m", 6),
GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "pwm_qtr_26m", 7),
GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "pwm_qtr_26m", 8),
GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "pwm_qtr_26m", 9),
GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "faxi", 12),
GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1", 14),
GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "faxi", 17),
GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "faxi", 18),
GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "faxi", 19),
GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "faxi", 20),
GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "faxi", 22),
GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "faxi", 23),
GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi", 28),
GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "sf", 29),
GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "faxi", 30),
GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "faxi", 31),
/* PERI1 */
GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash", 1),
};
static struct mtk_composite infra_muxes[] = {
/* INFRA_TOPCKGEN_CKMUXSEL */
MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 0x000,
2, 2),
};
static struct mtk_composite top_muxes[] = {
/* CLK_CFG_0 */
MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
0x040, 0, 3, 7),
MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
0x040, 8, 1, 15),
MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
0x040, 16, 1, 23),
MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
0x040, 24, 3, 31),
/* CLK_CFG_1 */
MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
0x050, 0, 2, 7),
MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
0x050, 8, 1, 15),
MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
0x050, 16, 4, 23),
MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
0x050, 24, 3, 31),
/* CLK_CFG_2 */
MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
0x060, 0, 1, 7),
MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
0x060, 8, 3, 15),
MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
0x060, 16, 3, 23),
MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
0x060, 24, 3, 31),
/* CLK_CFG_3 */
MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
0x070, 0, 3, 7),
MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,
0x070, 8, 3, 15),
MUX_GATE(CLK_TOP_AP2WBMCU_SEL, "ap2wbmcu_sel", ap2wbmcu_parents,
0x070, 16, 3, 23),
MUX_GATE(CLK_TOP_AP2WBHIF_SEL, "ap2wbhif_sel", ap2wbmcu_parents,
0x070, 24, 3, 31),
/* CLK_CFG_4 */
MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
0x080, 0, 2, 7),
MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
0x080, 8, 2, 15),
MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
0x080, 16, 3, 23),
MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
0x080, 24, 2, 31),
/* CLK_CFG_5 */
MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
0x090, 0, 2, 7),
MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", hif_parents,
0x090, 8, 3, 15),
MUX_GATE(CLK_TOP_SATA_SEL, "sata_sel", sata_parents,
0x090, 16, 1, 23),
MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
0x090, 24, 2, 31),
/* CLK_CFG_6 */
MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
0x0A0, 0, 1, 7),
MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud1_parents,
0x0A0, 8, 1, 15),
MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", irrx_parents,
0x0A0, 16, 1, 23),
MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", irrx_parents,
0x0A0, 24, 1, 31),
/* CLK_CFG_7 */
MUX_GATE(CLK_TOP_SATA_MCU_SEL, "sata_mcu_sel", scp_parents,
0x0B0, 0, 2, 7),
MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, "pcie0_mcu_sel", scp_parents,
0x0B0, 8, 2, 15),
MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, "pcie1_mcu_sel", scp_parents,
0x0B0, 16, 2, 23),
MUX_GATE(CLK_TOP_SSUSB_MCU_SEL, "ssusb_mcu_sel", scp_parents,
0x0B0, 24, 2, 31),
/* CLK_CFG_8 */
MUX_GATE(CLK_TOP_CRYPTO_SEL, "crypto_sel", crypto_parents,
0x0C0, 0, 3, 7),
MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, "sgmii_ref_1_sel", f10m_ref_parents,
0x0C0, 8, 1, 15),
MUX_GATE(CLK_TOP_10M_SEL, "gpt10m_sel", gpt10m_parents,
0x0C0, 16, 1, 23),
};
static struct mtk_composite peri_muxes[] = {
/* PERI_GLOBALCON_CKSEL */
MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
};
static int mtk_topckgen_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
struct device_node *node = pdev->dev.of_node;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
clk_data);
mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
clk_data);
mtk_clk_register_composites(&pdev->dev, top_muxes,
ARRAY_SIZE(top_muxes), base,
&mt7629_clk_lock, clk_data);
clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk);
clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk);
clk_prepare_enable(clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static int mtk_infrasys_init(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct clk_hw_onecell_data *clk_data;
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
mtk_clk_register_gates(&pdev->dev, node, infra_clks,
ARRAY_SIZE(infra_clks), clk_data);
mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes,
ARRAY_SIZE(infra_muxes), clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
clk_data);
}
static int mtk_pericfg_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
int r;
struct device_node *node = pdev->dev.of_node;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
mtk_clk_register_gates(&pdev->dev, node, peri_clks,
ARRAY_SIZE(peri_clks), clk_data);
mtk_clk_register_composites(&pdev->dev, peri_muxes,
ARRAY_SIZE(peri_muxes), base,
&mt7629_clk_lock, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
return r;
clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk);
return 0;
}
static int mtk_apmixedsys_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
clk_data);
mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
ARRAY_SIZE(apmixed_clks), clk_data);
clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
clk_prepare_enable(clk_data->hws[CLK_APMIXED_MAIN_CORE_EN]->clk);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct of_device_id of_match_clk_mt7629[] = {
{
.compatible = "mediatek,mt7629-apmixedsys",
.data = mtk_apmixedsys_init,
}, {
.compatible = "mediatek,mt7629-infracfg",
.data = mtk_infrasys_init,
}, {
.compatible = "mediatek,mt7629-topckgen",
.data = mtk_topckgen_init,
}, {
.compatible = "mediatek,mt7629-pericfg",
.data = mtk_pericfg_init,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7629);
static int clk_mt7629_probe(struct platform_device *pdev)
{
int (*clk_init)(struct platform_device *);
int r;
clk_init = of_device_get_match_data(&pdev->dev);
if (!clk_init)
return -EINVAL;
r = clk_init(pdev);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
return r;
}
static struct platform_driver clk_mt7629_drv = {
.probe = clk_mt7629_probe,
.driver = {
.name = "clk-mt7629",
.of_match_table = of_match_clk_mt7629,
},
};
static int clk_mt7629_init(void)
{
return platform_driver_register(&clk_mt7629_drv);
}
arch_initcall(clk_mt7629_init);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt7629.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs img_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_IMG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate img_clks[] = {
GATE_IMG(CLK_IMG_LARB9, "img_larb9", "top_img", 0),
GATE_IMG(CLK_IMG_TRAW0, "img_traw0", "top_img", 1),
GATE_IMG(CLK_IMG_TRAW1, "img_traw1", "top_img", 2),
GATE_IMG(CLK_IMG_TRAW2, "img_traw2", "top_img", 3),
GATE_IMG(CLK_IMG_TRAW3, "img_traw3", "top_img", 4),
GATE_IMG(CLK_IMG_DIP0, "img_dip0", "top_img", 8),
GATE_IMG(CLK_IMG_WPE0, "img_wpe0", "top_img", 9),
GATE_IMG(CLK_IMG_IPE, "img_ipe", "top_img", 10),
GATE_IMG(CLK_IMG_DIP1, "img_dip1", "top_img", 11),
GATE_IMG(CLK_IMG_WPE1, "img_wpe1", "top_img", 12),
GATE_IMG(CLK_IMG_GALS, "img_gals", "top_img", 31),
};
static const struct mtk_gate img1_dip_top_clks[] = {
GATE_IMG(CLK_IMG1_DIP_TOP_LARB10, "img1_dip_top_larb10", "top_img", 0),
GATE_IMG(CLK_IMG1_DIP_TOP_DIP_TOP, "img1_dip_top_dip_top", "top_img", 1),
};
static const struct mtk_gate img1_dip_nr_clks[] = {
GATE_IMG(CLK_IMG1_DIP_NR_RESERVE, "img1_dip_nr_reserve", "top_img", 0),
GATE_IMG(CLK_IMG1_DIP_NR_DIP_NR, "img1_dip_nr_dip_nr", "top_img", 1),
};
static const struct mtk_gate img1_wpe_clks[] = {
GATE_IMG(CLK_IMG1_WPE_LARB11, "img1_wpe_larb11", "top_img", 0),
GATE_IMG(CLK_IMG1_WPE_WPE, "img1_wpe_wpe", "top_img", 1),
};
static const struct mtk_clk_desc img_desc = {
.clks = img_clks,
.num_clks = ARRAY_SIZE(img_clks),
};
static const struct mtk_clk_desc img1_dip_top_desc = {
.clks = img1_dip_top_clks,
.num_clks = ARRAY_SIZE(img1_dip_top_clks),
};
static const struct mtk_clk_desc img1_dip_nr_desc = {
.clks = img1_dip_nr_clks,
.num_clks = ARRAY_SIZE(img1_dip_nr_clks),
};
static const struct mtk_clk_desc img1_wpe_desc = {
.clks = img1_wpe_clks,
.num_clks = ARRAY_SIZE(img1_wpe_clks),
};
static const struct of_device_id of_match_clk_mt8195_img[] = {
{
.compatible = "mediatek,mt8195-imgsys",
.data = &img_desc,
}, {
.compatible = "mediatek,mt8195-imgsys1_dip_top",
.data = &img1_dip_top_desc,
}, {
.compatible = "mediatek,mt8195-imgsys1_dip_nr",
.data = &img1_dip_nr_desc,
}, {
.compatible = "mediatek,mt8195-imgsys1_wpe",
.data = &img1_wpe_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_img);
static struct platform_driver clk_mt8195_img_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8195-img",
.of_match_table = of_match_clk_mt8195_img,
},
};
module_platform_driver(clk_mt8195_img_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8195-img.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt8186-clk.h>
#include <dt-bindings/reset/mt8186-resets.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs infra_ao0_cg_regs = {
.set_ofs = 0x80,
.clr_ofs = 0x84,
.sta_ofs = 0x90,
};
static const struct mtk_gate_regs infra_ao1_cg_regs = {
.set_ofs = 0x88,
.clr_ofs = 0x8c,
.sta_ofs = 0x94,
};
static const struct mtk_gate_regs infra_ao2_cg_regs = {
.set_ofs = 0xa4,
.clr_ofs = 0xa8,
.sta_ofs = 0xac,
};
static const struct mtk_gate_regs infra_ao3_cg_regs = {
.set_ofs = 0xc0,
.clr_ofs = 0xc4,
.sta_ofs = 0xc8,
};
#define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flag)
#define GATE_INFRA_AO0(_id, _name, _parent, _shift) \
GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flag)
#define GATE_INFRA_AO1(_id, _name, _parent, _shift) \
GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flag)
#define GATE_INFRA_AO2(_id, _name, _parent, _shift) \
GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flag)
#define GATE_INFRA_AO3(_id, _name, _parent, _shift) \
GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
static const struct mtk_gate infra_ao_clks[] = {
/* INFRA_AO0 */
GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_TMR, "infra_ao_pmic_tmr", "top_pwrap_ulposc", 0),
GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_AP, "infra_ao_pmic_ap", "top_pwrap_ulposc", 1),
GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_MD, "infra_ao_pmic_md", "top_pwrap_ulposc", 2),
GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_CONN, "infra_ao_pmic_conn", "top_pwrap_ulposc", 3),
/* infra_ao_scp_core are main clock in always-on co-processor. */
GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SCP_CORE,
"infra_ao_scp_core", "top_scp", 4, CLK_IS_CRITICAL),
/* infra_ao_sej is main clock for secure engine with JTAG support */
GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SEJ,
"infra_ao_sej", "top_axi", 5, CLK_IS_CRITICAL),
GATE_INFRA_AO0(CLK_INFRA_AO_APXGPT, "infra_ao_apxgpt", "top_axi", 6),
GATE_INFRA_AO0(CLK_INFRA_AO_ICUSB, "infra_ao_icusb", "top_axi", 8),
GATE_INFRA_AO0(CLK_INFRA_AO_GCE, "infra_ao_gce", "top_axi", 9),
GATE_INFRA_AO0(CLK_INFRA_AO_THERM, "infra_ao_therm", "top_axi", 10),
GATE_INFRA_AO0(CLK_INFRA_AO_I2C_AP, "infra_ao_i2c_ap", "top_i2c", 11),
GATE_INFRA_AO0(CLK_INFRA_AO_I2C_CCU, "infra_ao_i2c_ccu", "top_i2c", 12),
GATE_INFRA_AO0(CLK_INFRA_AO_I2C_SSPM, "infra_ao_i2c_sspm", "top_i2c", 13),
GATE_INFRA_AO0(CLK_INFRA_AO_I2C_RSV, "infra_ao_i2c_rsv", "top_i2c", 14),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM_HCLK, "infra_ao_pwm_hclk", "top_axi", 15),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM1, "infra_ao_pwm1", "top_pwm", 16),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM2, "infra_ao_pwm2", "top_pwm", 17),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM3, "infra_ao_pwm3", "top_pwm", 18),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM4, "infra_ao_pwm4", "top_pwm", 19),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM5, "infra_ao_pwm5", "top_pwm", 20),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM, "infra_ao_pwm", "top_pwm", 21),
GATE_INFRA_AO0(CLK_INFRA_AO_UART0, "infra_ao_uart0", "top_uart", 22),
GATE_INFRA_AO0(CLK_INFRA_AO_UART1, "infra_ao_uart1", "top_uart", 23),
GATE_INFRA_AO0(CLK_INFRA_AO_UART2, "infra_ao_uart2", "top_uart", 24),
GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, "infra_ao_gce_26m", "clk26m", 27),
GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, "infra_ao_dma", "top_axi", 28),
GATE_INFRA_AO0(CLK_INFRA_AO_BTIF, "infra_ao_btif", "top_axi", 31),
/* INFRA_AO1 */
GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "top_spi", 1),
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, "infra_ao_msdc0", "top_msdc5hclk", 2),
GATE_INFRA_AO1(CLK_INFRA_AO_MSDCFDE, "infra_ao_msdcfde", "top_aes_msdcfde", 3),
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, "infra_ao_msdc1", "top_axi", 4),
/* infra_ao_dvfsrc is for internal DVFS usage, should not be handled by Linux */
GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DVFSRC,
"infra_ao_dvfsrc", "top_dvfsrc", 7, CLK_IS_CRITICAL),
GATE_INFRA_AO1(CLK_INFRA_AO_GCPU, "infra_ao_gcpu", "top_axi", 8),
GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, "infra_ao_trng", "top_axi", 9),
GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, "infra_ao_auxadc", "clk26m", 10),
GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, "infra_ao_cpum", "top_axi", 11),
GATE_INFRA_AO1(CLK_INFRA_AO_CCIF1_AP, "infra_ao_ccif1_ap", "top_axi", 12),
GATE_INFRA_AO1(CLK_INFRA_AO_CCIF1_MD, "infra_ao_ccif1_md", "top_axi", 13),
GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC_MD, "infra_ao_auxadc_md", "clk26m", 14),
GATE_INFRA_AO1(CLK_INFRA_AO_AP_DMA, "infra_ao_ap_dma", "top_axi", 18),
GATE_INFRA_AO1(CLK_INFRA_AO_XIU, "infra_ao_xiu", "top_axi", 19),
/* infra_ao_device_apc is for device access permission control module */
GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DEVICE_APC,
"infra_ao_dapc", "top_axi", 20, CLK_IS_CRITICAL),
GATE_INFRA_AO1(CLK_INFRA_AO_CCIF_AP, "infra_ao_ccif_ap", "top_axi", 23),
GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGTOP, "infra_ao_debugtop", "top_axi", 24),
GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, "infra_ao_audio", "top_axi", 25),
GATE_INFRA_AO1(CLK_INFRA_AO_CCIF_MD, "infra_ao_ccif_md", "top_axi", 26),
GATE_INFRA_AO1(CLK_INFRA_AO_DXCC_SEC_CORE, "infra_ao_secore", "top_dxcc", 27),
GATE_INFRA_AO1(CLK_INFRA_AO_DXCC_AO, "infra_ao_dxcc_ao", "top_dxcc", 28),
GATE_INFRA_AO1(CLK_INFRA_AO_IMP_IIC, "infra_ao_imp_iic", "top_axi", 29),
GATE_INFRA_AO1(CLK_INFRA_AO_DRAMC_F26M, "infra_ao_dramc26", "clk26m", 31),
/* INFRA_AO2 */
GATE_INFRA_AO2(CLK_INFRA_AO_RG_PWM_FBCLK6, "infra_ao_pwm_fbclk6", "clk26m", 0),
GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_HCLK, "infra_ao_ssusb_hclk", "top_axi", 1),
GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, "infra_ao_disp_pwm", "top_disp_pwm", 2),
GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_BCLK, "infra_ao_cldmabclk", "top_axi", 3),
GATE_INFRA_AO2(CLK_INFRA_AO_AUDIO_26M_BCLK, "infra_ao_audio26m", "clk26m", 4),
GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_P1_HCLK, "infra_ao_ssusb_p1_hclk", "top_axi", 5),
GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "top_spi", 6),
GATE_INFRA_AO2(CLK_INFRA_AO_I2C4, "infra_ao_i2c4", "top_i2c", 7),
GATE_INFRA_AO2(CLK_INFRA_AO_MODEM_TEMP_SHARE, "infra_ao_mdtemp", "clk26m", 8),
GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, "infra_ao_spi2", "top_spi", 9),
GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, "infra_ao_spi3", "top_spi", 10),
GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_REF, "infra_ao_ssusb_ref", "clk26m", 11),
GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_XHCI, "infra_ao_ssusb_xhci", "top_ssusb_xhci", 12),
GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_P1_REF, "infra_ao_ssusb_p1_ref", "clk26m", 13),
GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_P1_XHCI,
"infra_ao_ssusb_p1_xhci", "top_ssusb_xhci_1p", 14),
/* infra_ao_sspm is main clock in co-processor, should not be closed in Linux. */
GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_SSPM, "infra_ao_sspm", "top_sspm", 15, CLK_IS_CRITICAL),
GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_P1_SYS,
"infra_ao_ssusb_p1_sys", "top_ssusb_1p", 16),
GATE_INFRA_AO2(CLK_INFRA_AO_I2C5, "infra_ao_i2c5", "top_i2c", 18),
GATE_INFRA_AO2(CLK_INFRA_AO_I2C5_ARBITER, "infra_ao_i2c5a", "top_i2c", 19),
GATE_INFRA_AO2(CLK_INFRA_AO_I2C5_IMM, "infra_ao_i2c5_imm", "top_i2c", 20),
GATE_INFRA_AO2(CLK_INFRA_AO_I2C1_ARBITER, "infra_ao_i2c1a", "top_i2c", 21),
GATE_INFRA_AO2(CLK_INFRA_AO_I2C1_IMM, "infra_ao_i2c1_imm", "top_i2c", 22),
GATE_INFRA_AO2(CLK_INFRA_AO_I2C2_ARBITER, "infra_ao_i2c2a", "top_i2c", 23),
GATE_INFRA_AO2(CLK_INFRA_AO_I2C2_IMM, "infra_ao_i2c2_imm", "top_i2c", 24),
GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, "infra_ao_spi4", "top_spi", 25),
GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, "infra_ao_spi5", "top_spi", 26),
GATE_INFRA_AO2(CLK_INFRA_AO_CQ_DMA, "infra_ao_cq_dma", "top_axi", 27),
GATE_INFRA_AO2(CLK_INFRA_AO_BIST2FPC, "infra_ao_bist2fpc", "f_bist2fpc_ck", 28),
/* INFRA_AO3 */
GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SELF, "infra_ao_msdc0sf", "top_msdc50_0", 0),
GATE_INFRA_AO3(CLK_INFRA_AO_SPINOR, "infra_ao_spinor", "top_spinor", 1),
/*
* infra_ao_sspm_26m/infra_ao_sspm_32k are main clocks in co-processor,
* should not be closed in Linux.
*/
GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_SSPM_26M_SELF, "infra_ao_sspm_26m", "clk26m", 3,
CLK_IS_CRITICAL),
GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_SSPM_32K_SELF, "infra_ao_sspm_32k", "clk32k", 4,
CLK_IS_CRITICAL),
GATE_INFRA_AO3(CLK_INFRA_AO_I2C6, "infra_ao_i2c6", "top_i2c", 6),
GATE_INFRA_AO3(CLK_INFRA_AO_AP_MSDC0, "infra_ao_ap_msdc0", "top_axi", 7),
GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, "infra_ao_md_msdc0", "top_axi", 8),
GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SRC, "infra_ao_msdc0_clk", "top_msdc50_0", 9),
GATE_INFRA_AO3(CLK_INFRA_AO_MSDC1_SRC, "infra_ao_msdc1_clk", "top_msdc30_1", 10),
/* infra_ao_sej_f13m is main clock for secure engine with JTAG support */
GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_SEJ_F13M,
"infra_ao_sej_f13m", "clk26m", 15, CLK_IS_CRITICAL),
/* infra_ao_aes_top0_bclk is for secure encryption */
GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_AES_TOP0_BCLK,
"infra_ao_aes_top0_bclk", "top_axi", 16, CLK_IS_CRITICAL),
GATE_INFRA_AO3(CLK_INFRA_AO_MCU_PM_BCLK, "infra_ao_mcu_pm_bclk", "top_axi", 17),
GATE_INFRA_AO3(CLK_INFRA_AO_CCIF2_AP, "infra_ao_ccif2_ap", "top_axi", 18),
GATE_INFRA_AO3(CLK_INFRA_AO_CCIF2_MD, "infra_ao_ccif2_md", "top_axi", 19),
GATE_INFRA_AO3(CLK_INFRA_AO_CCIF3_AP, "infra_ao_ccif3_ap", "top_axi", 20),
GATE_INFRA_AO3(CLK_INFRA_AO_CCIF3_MD, "infra_ao_ccif3_md", "top_axi", 21),
GATE_INFRA_AO3(CLK_INFRA_AO_FADSP_26M, "infra_ao_fadsp_26m", "clk26m", 22),
GATE_INFRA_AO3(CLK_INFRA_AO_FADSP_32K, "infra_ao_fadsp_32k", "clk32k", 23),
GATE_INFRA_AO3(CLK_INFRA_AO_CCIF4_AP, "infra_ao_ccif4_ap", "top_axi", 24),
GATE_INFRA_AO3(CLK_INFRA_AO_CCIF4_MD, "infra_ao_ccif4_md", "top_axi", 25),
GATE_INFRA_AO3(CLK_INFRA_AO_FADSP, "infra_ao_fadsp", "top_audiodsp", 27),
GATE_INFRA_AO3(CLK_INFRA_AO_FLASHIF_133M, "infra_ao_flashif_133m", "top_axi", 28),
GATE_INFRA_AO3(CLK_INFRA_AO_FLASHIF_66M, "infra_ao_flashif_66m", "top_axi", 29),
};
static u16 infra_ao_rst_ofs[] = {
INFRA_RST0_SET_OFFSET,
INFRA_RST1_SET_OFFSET,
INFRA_RST2_SET_OFFSET,
INFRA_RST3_SET_OFFSET,
INFRA_RST4_SET_OFFSET,
};
static u16 infra_ao_idx_map[] = {
[MT8186_INFRA_THERMAL_CTRL_RST] = 0 * RST_NR_PER_BANK + 0,
[MT8186_INFRA_PTP_CTRL_RST] = 1 * RST_NR_PER_BANK + 0,
};
static struct mtk_clk_rst_desc infra_ao_rst_desc = {
.version = MTK_RST_SET_CLR,
.rst_bank_ofs = infra_ao_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
.rst_idx_map = infra_ao_idx_map,
.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
};
static const struct mtk_clk_desc infra_ao_desc = {
.clks = infra_ao_clks,
.num_clks = ARRAY_SIZE(infra_ao_clks),
.rst_desc = &infra_ao_rst_desc,
};
static const struct of_device_id of_match_clk_mt8186_infra_ao[] = {
{
.compatible = "mediatek,mt8186-infracfg_ao",
.data = &infra_ao_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_infra_ao);
static struct platform_driver clk_mt8186_infra_ao_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8186-infra-ao",
.of_match_table = of_match_clk_mt8186_infra_ao,
},
};
module_platform_driver(clk_mt8186_infra_ao_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8186-infra_ao.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
*/
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include "reset.h"
static inline struct mtk_clk_rst_data *to_mtk_clk_rst_data(struct reset_controller_dev *rcdev)
{
return container_of(rcdev, struct mtk_clk_rst_data, rcdev);
}
static int mtk_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool deassert)
{
struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
unsigned int val = deassert ? 0 : ~0;
return regmap_update_bits(data->regmap,
data->desc->rst_bank_ofs[id / RST_NR_PER_BANK],
BIT(id % RST_NR_PER_BANK), val);
}
static int mtk_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return mtk_reset_update(rcdev, id, false);
}
static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return mtk_reset_update(rcdev, id, true);
}
static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id)
{
int ret;
ret = mtk_reset_assert(rcdev, id);
if (ret)
return ret;
return mtk_reset_deassert(rcdev, id);
}
static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev,
unsigned long id, bool deassert)
{
struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
unsigned int deassert_ofs = deassert ? 0x4 : 0;
return regmap_write(data->regmap,
data->desc->rst_bank_ofs[id / RST_NR_PER_BANK] +
deassert_ofs,
BIT(id % RST_NR_PER_BANK));
}
static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
unsigned long id)
{
return mtk_reset_update_set_clr(rcdev, id, false);
}
static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
unsigned long id)
{
return mtk_reset_update_set_clr(rcdev, id, true);
}
static int mtk_reset_set_clr(struct reset_controller_dev *rcdev,
unsigned long id)
{
int ret;
ret = mtk_reset_assert_set_clr(rcdev, id);
if (ret)
return ret;
return mtk_reset_deassert_set_clr(rcdev, id);
}
static const struct reset_control_ops mtk_reset_ops = {
.assert = mtk_reset_assert,
.deassert = mtk_reset_deassert,
.reset = mtk_reset,
};
static const struct reset_control_ops mtk_reset_ops_set_clr = {
.assert = mtk_reset_assert_set_clr,
.deassert = mtk_reset_deassert_set_clr,
.reset = mtk_reset_set_clr,
};
static int reset_xlate(struct reset_controller_dev *rcdev,
const struct of_phandle_args *reset_spec)
{
struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
if (reset_spec->args[0] >= rcdev->nr_resets ||
reset_spec->args[0] >= data->desc->rst_idx_map_nr)
return -EINVAL;
return data->desc->rst_idx_map[reset_spec->args[0]];
}
int mtk_register_reset_controller(struct device_node *np,
const struct mtk_clk_rst_desc *desc)
{
struct regmap *regmap;
const struct reset_control_ops *rcops = NULL;
struct mtk_clk_rst_data *data;
int ret;
if (!desc) {
pr_err("mtk clock reset desc is NULL\n");
return -EINVAL;
}
switch (desc->version) {
case MTK_RST_SIMPLE:
rcops = &mtk_reset_ops;
break;
case MTK_RST_SET_CLR:
rcops = &mtk_reset_ops_set_clr;
break;
default:
pr_err("Unknown reset version %d\n", desc->version);
return -EINVAL;
}
regmap = device_node_to_regmap(np);
if (IS_ERR(regmap)) {
pr_err("Cannot find regmap for %pOF: %pe\n", np, regmap);
return -EINVAL;
}
data = kzalloc(sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->desc = desc;
data->regmap = regmap;
data->rcdev.owner = THIS_MODULE;
data->rcdev.ops = rcops;
data->rcdev.of_node = np;
if (data->desc->rst_idx_map_nr > 0) {
data->rcdev.of_reset_n_cells = 1;
data->rcdev.nr_resets = desc->rst_idx_map_nr;
data->rcdev.of_xlate = reset_xlate;
} else {
data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK;
}
ret = reset_controller_register(&data->rcdev);
if (ret) {
pr_err("could not register reset controller: %d\n", ret);
kfree(data);
return ret;
}
return 0;
}
int mtk_register_reset_controller_with_dev(struct device *dev,
const struct mtk_clk_rst_desc *desc)
{
struct device_node *np = dev->of_node;
struct regmap *regmap;
const struct reset_control_ops *rcops = NULL;
struct mtk_clk_rst_data *data;
int ret;
if (!desc) {
dev_err(dev, "mtk clock reset desc is NULL\n");
return -EINVAL;
}
switch (desc->version) {
case MTK_RST_SIMPLE:
rcops = &mtk_reset_ops;
break;
case MTK_RST_SET_CLR:
rcops = &mtk_reset_ops_set_clr;
break;
default:
dev_err(dev, "Unknown reset version %d\n", desc->version);
return -EINVAL;
}
regmap = device_node_to_regmap(np);
if (IS_ERR(regmap)) {
dev_err(dev, "Cannot find regmap %pe\n", regmap);
return -EINVAL;
}
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->desc = desc;
data->regmap = regmap;
data->rcdev.owner = THIS_MODULE;
data->rcdev.ops = rcops;
data->rcdev.of_node = np;
data->rcdev.dev = dev;
if (data->desc->rst_idx_map_nr > 0) {
data->rcdev.of_reset_n_cells = 1;
data->rcdev.nr_resets = desc->rst_idx_map_nr;
data->rcdev.of_xlate = reset_xlate;
} else {
data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK;
}
ret = devm_reset_controller_register(dev, &data->rcdev);
if (ret) {
dev_err(dev, "could not register reset controller: %d\n", ret);
return ret;
}
return 0;
}
EXPORT_SYMBOL_GPL(mtk_register_reset_controller_with_dev);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/reset.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt8186-clk.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs venc_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_VENC(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate venc_clks[] = {
GATE_VENC(CLK_VENC_CKE0_LARB, "venc_cke0_larb", "top_venc", 0),
GATE_VENC(CLK_VENC_CKE1_VENC, "venc_cke1_venc", "top_venc", 4),
GATE_VENC(CLK_VENC_CKE2_JPGENC, "venc_cke2_jpgenc", "top_venc", 8),
GATE_VENC(CLK_VENC_CKE5_GALS, "venc_cke5_gals", "top_venc", 28),
};
static const struct mtk_clk_desc venc_desc = {
.clks = venc_clks,
.num_clks = ARRAY_SIZE(venc_clks),
};
static const struct of_device_id of_match_clk_mt8186_venc[] = {
{
.compatible = "mediatek,mt8186-vencsys",
.data = &venc_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_venc);
static struct platform_driver clk_mt8186_venc_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8186-venc",
.of_match_table = of_match_clk_mt8186_venc,
},
};
module_platform_driver(clk_mt8186_venc_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8186-venc.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Wendell Lin <[email protected]>
*/
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt6779-clk.h>
#include "clk-mtk.h"
#include "clk-gate.h"
static const struct mtk_gate_regs cam_cg_regs = {
.set_ofs = 0x0004,
.clr_ofs = 0x0008,
.sta_ofs = 0x0000,
};
#define GATE_CAM(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr)
static const struct mtk_gate cam_clks[] = {
GATE_CAM(CLK_CAM_LARB10, "camsys_larb10", "cam_sel", 0),
GATE_CAM(CLK_CAM_DFP_VAD, "camsys_dfp_vad", "cam_sel", 1),
GATE_CAM(CLK_CAM_LARB11, "camsys_larb11", "cam_sel", 2),
GATE_CAM(CLK_CAM_LARB9, "camsys_larb9", "cam_sel", 3),
GATE_CAM(CLK_CAM_CAM, "camsys_cam", "cam_sel", 6),
GATE_CAM(CLK_CAM_CAMTG, "camsys_camtg", "cam_sel", 7),
GATE_CAM(CLK_CAM_SENINF, "camsys_seninf", "cam_sel", 8),
GATE_CAM(CLK_CAM_CAMSV0, "camsys_camsv0", "cam_sel", 9),
GATE_CAM(CLK_CAM_CAMSV1, "camsys_camsv1", "cam_sel", 10),
GATE_CAM(CLK_CAM_CAMSV2, "camsys_camsv2", "cam_sel", 11),
GATE_CAM(CLK_CAM_CAMSV3, "camsys_camsv3", "cam_sel", 12),
GATE_CAM(CLK_CAM_CCU, "camsys_ccu", "cam_sel", 13),
GATE_CAM(CLK_CAM_FAKE_ENG, "camsys_fake_eng", "cam_sel", 14),
};
static const struct mtk_clk_desc cam_desc = {
.clks = cam_clks,
.num_clks = ARRAY_SIZE(cam_clks),
};
static const struct of_device_id of_match_clk_mt6779_cam[] = {
{
.compatible = "mediatek,mt6779-camsys",
.data = &cam_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_cam);
static struct platform_driver clk_mt6779_cam_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt6779-cam",
.of_match_table = of_match_clk_mt6779_cam,
},
};
module_platform_driver(clk_mt6779_cam_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6779-cam.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8192-clk.h>
static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {
.set_ofs = 0xe08,
.clr_ofs = 0xe04,
.sta_ofs = 0xe00,
};
#define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift) \
GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
static const struct mtk_gate imp_iic_wrap_c_clks[] = {
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_I2C10, "imp_iic_wrap_c_i2c10", "infra_i2c0", 0),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_I2C11, "imp_iic_wrap_c_i2c11", "infra_i2c0", 1),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_I2C12, "imp_iic_wrap_c_i2c12", "infra_i2c0", 2),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_I2C13, "imp_iic_wrap_c_i2c13", "infra_i2c0", 3),
};
static const struct mtk_gate imp_iic_wrap_e_clks[] = {
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_E_I2C3, "imp_iic_wrap_e_i2c3", "infra_i2c0", 0),
};
static const struct mtk_gate imp_iic_wrap_n_clks[] = {
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_N_I2C0, "imp_iic_wrap_n_i2c0", "infra_i2c0", 0),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_N_I2C6, "imp_iic_wrap_n_i2c6", "infra_i2c0", 1),
};
static const struct mtk_gate imp_iic_wrap_s_clks[] = {
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C7, "imp_iic_wrap_s_i2c7", "infra_i2c0", 0),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C8, "imp_iic_wrap_s_i2c8", "infra_i2c0", 1),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C9, "imp_iic_wrap_s_i2c9", "infra_i2c0", 2),
};
static const struct mtk_gate imp_iic_wrap_w_clks[] = {
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C5, "imp_iic_wrap_w_i2c5", "infra_i2c0", 0),
};
static const struct mtk_gate imp_iic_wrap_ws_clks[] = {
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_WS_I2C1, "imp_iic_wrap_ws_i2c1", "infra_i2c0", 0),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_WS_I2C2, "imp_iic_wrap_ws_i2c2", "infra_i2c0", 1),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_WS_I2C4, "imp_iic_wrap_ws_i2c4", "infra_i2c0", 2),
};
static const struct mtk_clk_desc imp_iic_wrap_c_desc = {
.clks = imp_iic_wrap_c_clks,
.num_clks = ARRAY_SIZE(imp_iic_wrap_c_clks),
};
static const struct mtk_clk_desc imp_iic_wrap_e_desc = {
.clks = imp_iic_wrap_e_clks,
.num_clks = ARRAY_SIZE(imp_iic_wrap_e_clks),
};
static const struct mtk_clk_desc imp_iic_wrap_n_desc = {
.clks = imp_iic_wrap_n_clks,
.num_clks = ARRAY_SIZE(imp_iic_wrap_n_clks),
};
static const struct mtk_clk_desc imp_iic_wrap_s_desc = {
.clks = imp_iic_wrap_s_clks,
.num_clks = ARRAY_SIZE(imp_iic_wrap_s_clks),
};
static const struct mtk_clk_desc imp_iic_wrap_w_desc = {
.clks = imp_iic_wrap_w_clks,
.num_clks = ARRAY_SIZE(imp_iic_wrap_w_clks),
};
static const struct mtk_clk_desc imp_iic_wrap_ws_desc = {
.clks = imp_iic_wrap_ws_clks,
.num_clks = ARRAY_SIZE(imp_iic_wrap_ws_clks),
};
static const struct of_device_id of_match_clk_mt8192_imp_iic_wrap[] = {
{
.compatible = "mediatek,mt8192-imp_iic_wrap_c",
.data = &imp_iic_wrap_c_desc,
}, {
.compatible = "mediatek,mt8192-imp_iic_wrap_e",
.data = &imp_iic_wrap_e_desc,
}, {
.compatible = "mediatek,mt8192-imp_iic_wrap_n",
.data = &imp_iic_wrap_n_desc,
}, {
.compatible = "mediatek,mt8192-imp_iic_wrap_s",
.data = &imp_iic_wrap_s_desc,
}, {
.compatible = "mediatek,mt8192-imp_iic_wrap_w",
.data = &imp_iic_wrap_w_desc,
}, {
.compatible = "mediatek,mt8192-imp_iic_wrap_ws",
.data = &imp_iic_wrap_ws_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_imp_iic_wrap);
static struct platform_driver clk_mt8192_imp_iic_wrap_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8192-imp_iic_wrap",
.of_match_table = of_match_clk_mt8192_imp_iic_wrap,
},
};
module_platform_driver(clk_mt8192_imp_iic_wrap_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Shunli Wang <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-cpumux.h"
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-pll.h"
#include <dt-bindings/clock/mt2701-clk.h>
/*
* For some clocks, we don't care what their actual rates are. And these
* clocks may change their rate on different products or different scenarios.
* So we model these clocks' rate as 0, to denote it's not an actual rate.
*/
#define DUMMY_RATE 0
static DEFINE_SPINLOCK(mt2701_clk_lock);
static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK(CLK_TOP_DPI, "dpi_ck", "clk26m",
108 * MHZ),
FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", "clk26m",
400 * MHZ),
FIXED_CLK(CLK_TOP_VENCPLL, "vencpll_ck", "clk26m",
295750000),
FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, "hdmi_0_pix340m", "clk26m",
340 * MHZ),
FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, "hdmi_0_deep340m", "clk26m",
340 * MHZ),
FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m",
340 * MHZ),
FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m",
27 * MHZ),
FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m",
416 * MHZ),
FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, "dsi0_lntc_dsi", "clk26m",
143 * MHZ),
FIXED_CLK(CLK_TOP_HDMI_SCL_RX, "hdmi_scl_rx", "clk26m",
27 * MHZ),
FIXED_CLK(CLK_TOP_AUD_EXT1, "aud_ext1", "clk26m",
DUMMY_RATE),
FIXED_CLK(CLK_TOP_AUD_EXT2, "aud_ext2", "clk26m",
DUMMY_RATE),
FIXED_CLK(CLK_TOP_NFI1X_PAD, "nfi1x_pad", "clk26m",
DUMMY_RATE),
};
static const struct mtk_fixed_factor top_fixed_divs[] = {
FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1),
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll", 1, 52),
FACTOR(CLK_TOP_UNIVPLL_D108, "univpll_d108", "univpll", 1, 108),
FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
FACTOR(CLK_TOP_8BDAC, "8bdac_ck", "univpll_d2", 1, 1),
FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2),
FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll_d3", 1, 16),
FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32),
FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "dmpll_ck", 1, 2),
FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "dmpll_ck", 1, 4),
FACTOR(CLK_TOP_DMPLL_X2, "dmpll_x2", "dmpll_ck", 1, 1),
FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
FACTOR(CLK_TOP_VDECPLL, "vdecpll_ck", "vdecpll", 1, 1),
FACTOR(CLK_TOP_TVD2PLL, "tvd2pll_ck", "tvd2pll", 1, 1),
FACTOR(CLK_TOP_TVD2PLL_D2, "tvd2pll_d2", "tvd2pll", 1, 2),
FACTOR(CLK_TOP_MIPIPLL, "mipipll", "dpi_ck", 1, 1),
FACTOR(CLK_TOP_MIPIPLL_D2, "mipipll_d2", "dpi_ck", 1, 2),
FACTOR(CLK_TOP_MIPIPLL_D4, "mipipll_d4", "dpi_ck", 1, 4),
FACTOR(CLK_TOP_HDMIPLL, "hdmipll_ck", "hdmitx_dig_cts", 1, 1),
FACTOR(CLK_TOP_HDMIPLL_D2, "hdmipll_d2", "hdmitx_dig_cts", 1, 2),
FACTOR(CLK_TOP_HDMIPLL_D3, "hdmipll_d3", "hdmitx_dig_cts", 1, 3),
FACTOR(CLK_TOP_ARMPLL_1P3G, "armpll_1p3g_ck", "armpll", 1, 1),
FACTOR(CLK_TOP_AUDPLL, "audpll", "audpll_sel", 1, 1),
FACTOR(CLK_TOP_AUDPLL_D4, "audpll_d4", "audpll_sel", 1, 4),
FACTOR(CLK_TOP_AUDPLL_D8, "audpll_d8", "audpll_sel", 1, 8),
FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll_sel", 1, 16),
FACTOR(CLK_TOP_AUDPLL_D24, "audpll_d24", "audpll_sel", 1, 24),
FACTOR(CLK_TOP_AUD1PLL_98M, "aud1pll_98m_ck", "aud1pll", 1, 3),
FACTOR(CLK_TOP_AUD2PLL_90M, "aud2pll_90m_ck", "aud2pll", 1, 3),
FACTOR(CLK_TOP_HADDS2PLL_98M, "hadds2pll_98m", "hadds2pll", 1, 3),
FACTOR(CLK_TOP_HADDS2PLL_294M, "hadds2pll_294m", "hadds2pll", 1, 1),
FACTOR(CLK_TOP_ETHPLL_500M, "ethpll_500m_ck", "ethpll", 1, 1),
FACTOR(CLK_TOP_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8),
FACTOR(CLK_TOP_32K_INTERNAL, "32k_internal", "clk26m", 1, 793),
FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1),
FACTOR(CLK_TOP_AXISEL_D4, "axisel_d4", "axi_sel", 1, 4),
};
static const char * const axi_parents[] = {
"clk26m",
"syspll1_d2",
"syspll_d5",
"syspll1_d4",
"univpll_d5",
"univpll2_d2",
"mmpll_d2",
"dmpll_d2"
};
static const char * const mem_parents[] = {
"clk26m",
"dmpll_ck"
};
static const char * const ddrphycfg_parents[] = {
"clk26m",
"syspll1_d8"
};
static const char * const mm_parents[] = {
"clk26m",
"vencpll_ck",
"syspll1_d2",
"syspll1_d4",
"univpll_d5",
"univpll1_d2",
"univpll2_d2",
"dmpll_ck"
};
static const char * const pwm_parents[] = {
"clk26m",
"univpll2_d4",
"univpll3_d2",
"univpll1_d4",
};
static const char * const vdec_parents[] = {
"clk26m",
"vdecpll_ck",
"syspll_d5",
"syspll1_d4",
"univpll_d5",
"univpll2_d2",
"vencpll_ck",
"msdcpll_d2",
"mmpll_d2"
};
static const char * const mfg_parents[] = {
"clk26m",
"mmpll_ck",
"dmpll_x2_ck",
"msdcpll_ck",
"clk26m",
"syspll_d3",
"univpll_d3",
"univpll1_d2"
};
static const char * const camtg_parents[] = {
"clk26m",
"univpll_d26",
"univpll2_d2",
"syspll3_d2",
"syspll3_d4",
"msdcpll_d2",
"mmpll_d2"
};
static const char * const uart_parents[] = {
"clk26m",
"univpll2_d8"
};
static const char * const spi_parents[] = {
"clk26m",
"syspll3_d2",
"syspll4_d2",
"univpll2_d4",
"univpll1_d8"
};
static const char * const usb20_parents[] = {
"clk26m",
"univpll1_d8",
"univpll3_d4"
};
static const char * const msdc30_parents[] = {
"clk26m",
"msdcpll_d2",
"syspll2_d2",
"syspll1_d4",
"univpll1_d4",
"univpll2_d4"
};
static const char * const aud_intbus_parents[] = {
"clk26m",
"syspll1_d4",
"syspll3_d2",
"syspll4_d2",
"univpll3_d2",
"univpll2_d4"
};
static const char * const pmicspi_parents[] = {
"clk26m",
"syspll1_d8",
"syspll2_d4",
"syspll4_d2",
"syspll3_d4",
"syspll2_d8",
"syspll1_d16",
"univpll3_d4",
"univpll_d26",
"dmpll_d2",
"dmpll_d4"
};
static const char * const scp_parents[] = {
"clk26m",
"syspll1_d8",
"dmpll_d2",
"dmpll_d4"
};
static const char * const dpi0_parents[] = {
"clk26m",
"mipipll",
"mipipll_d2",
"mipipll_d4",
"clk26m",
"tvdpll_ck",
"tvdpll_d2",
"tvdpll_d4"
};
static const char * const dpi1_parents[] = {
"clk26m",
"tvdpll_ck",
"tvdpll_d2",
"tvdpll_d4"
};
static const char * const tve_parents[] = {
"clk26m",
"mipipll",
"mipipll_d2",
"mipipll_d4",
"clk26m",
"tvdpll_ck",
"tvdpll_d2",
"tvdpll_d4"
};
static const char * const hdmi_parents[] = {
"clk26m",
"hdmipll_ck",
"hdmipll_d2",
"hdmipll_d3"
};
static const char * const apll_parents[] = {
"clk26m",
"audpll",
"audpll_d4",
"audpll_d8",
"audpll_d16",
"audpll_d24",
"clk26m",
"clk26m"
};
static const char * const rtc_parents[] = {
"32k_internal",
"32k_external",
"clk26m",
"univpll3_d8"
};
static const char * const nfi2x_parents[] = {
"clk26m",
"syspll2_d2",
"syspll_d7",
"univpll3_d2",
"syspll2_d4",
"univpll3_d4",
"syspll4_d4",
"clk26m"
};
static const char * const emmc_hclk_parents[] = {
"clk26m",
"syspll1_d2",
"syspll1_d4",
"syspll2_d2"
};
static const char * const flash_parents[] = {
"clk26m_d8",
"clk26m",
"syspll2_d8",
"syspll3_d4",
"univpll3_d4",
"syspll4_d2",
"syspll2_d4",
"univpll2_d4"
};
static const char * const di_parents[] = {
"clk26m",
"tvd2pll_ck",
"tvd2pll_d2",
"clk26m"
};
static const char * const nr_osd_parents[] = {
"clk26m",
"vencpll_ck",
"syspll1_d2",
"syspll1_d4",
"univpll_d5",
"univpll1_d2",
"univpll2_d2",
"dmpll_ck"
};
static const char * const hdmirx_bist_parents[] = {
"clk26m",
"syspll_d3",
"clk26m",
"syspll1_d16",
"syspll4_d2",
"syspll1_d4",
"vencpll_ck",
"clk26m"
};
static const char * const intdir_parents[] = {
"clk26m",
"mmpll_ck",
"syspll_d2",
"univpll_d2"
};
static const char * const asm_parents[] = {
"clk26m",
"univpll2_d4",
"univpll2_d2",
"syspll_d5"
};
static const char * const ms_card_parents[] = {
"clk26m",
"univpll3_d8",
"syspll4_d4"
};
static const char * const ethif_parents[] = {
"clk26m",
"syspll1_d2",
"syspll_d5",
"syspll1_d4",
"univpll_d5",
"univpll1_d2",
"dmpll_ck",
"dmpll_d2"
};
static const char * const hdmirx_parents[] = {
"clk26m",
"univpll_d52"
};
static const char * const cmsys_parents[] = {
"clk26m",
"syspll1_d2",
"univpll1_d2",
"univpll_d5",
"syspll_d5",
"syspll2_d2",
"syspll1_d4",
"syspll3_d2",
"syspll2_d4",
"syspll1_d8",
"clk26m",
"clk26m",
"clk26m",
"clk26m",
"clk26m"
};
static const char * const clk_8bdac_parents[] = {
"32k_internal",
"8bdac_ck",
"clk26m",
"clk26m"
};
static const char * const aud2dvd_parents[] = {
"a1sys_hp_ck",
"a2sys_hp_ck"
};
static const char * const padmclk_parents[] = {
"clk26m",
"univpll_d26",
"univpll_d52",
"univpll_d108",
"univpll2_d8",
"univpll2_d16",
"univpll2_d32"
};
static const char * const aud_mux_parents[] = {
"clk26m",
"aud1pll_98m_ck",
"aud2pll_90m_ck",
"hadds2pll_98m",
"audio_ext1_ck",
"audio_ext2_ck"
};
static const char * const aud_src_parents[] = {
"aud_mux1_sel",
"aud_mux2_sel"
};
static const char * const cpu_parents[] = {
"clk26m",
"armpll",
"mainpll",
"mmpll"
};
static const struct mtk_composite cpu_muxes[] __initconst = {
MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
};
static const struct mtk_composite top_muxes[] = {
MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
0x0040, 0, 3, 7, CLK_IS_CRITICAL),
MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
0x0040, 8, 1, 15, CLK_IS_CRITICAL),
MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel",
ddrphycfg_parents, 0x0040, 16, 1, 23, CLK_IS_CRITICAL),
MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
0x0040, 24, 3, 31),
MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
0x0050, 0, 2, 7),
MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents,
0x0050, 8, 4, 15),
MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents,
0x0050, 16, 3, 23),
MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,
0x0050, 24, 3, 31),
MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
0x0060, 0, 1, 7),
MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents,
0x0060, 8, 3, 15),
MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents,
0x0060, 16, 2, 23),
MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents,
0x0060, 24, 3, 31),
MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents,
0x0070, 0, 3, 7),
MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents,
0x0070, 8, 3, 15),
MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", msdc30_parents,
0x0070, 16, 1, 23),
MUX_GATE(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
0x0070, 24, 3, 31),
MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
0x0080, 0, 4, 7),
MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
0x0080, 8, 2, 15),
MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents,
0x0080, 16, 3, 23),
MUX_GATE_FLAGS_2(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents,
0x0080, 24, 2, 31, 0, CLK_MUX_ROUND_CLOSEST),
MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents,
0x0090, 0, 3, 7),
MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents,
0x0090, 8, 2, 15),
MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents,
0x0090, 16, 3, 23),
MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents,
0x00A0, 0, 2, 7, CLK_IS_CRITICAL),
MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents,
0x00A0, 8, 3, 15),
MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, "emmc_hclk_sel", emmc_hclk_parents,
0x00A0, 24, 2, 31),
MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
0x00B0, 0, 3, 7),
MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents,
0x00B0, 8, 2, 15),
MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_osd_parents,
0x00B0, 16, 3, 23),
MUX_GATE(CLK_TOP_OSD_SEL, "osd_sel", nr_osd_parents,
0x00B0, 24, 3, 31),
MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, "hdmirx_bist_sel",
hdmirx_bist_parents, 0x00C0, 0, 3, 7),
MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
0x00C0, 8, 2, 15),
MUX_GATE(CLK_TOP_ASM_I_SEL, "asm_i_sel", asm_parents,
0x00C0, 16, 2, 23),
MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_parents,
0x00C0, 24, 3, 31),
MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_parents,
0x00D0, 0, 2, 7),
MUX_GATE(CLK_TOP_MS_CARD_SEL, "ms_card_sel", ms_card_parents,
0x00D0, 16, 2, 23),
MUX_GATE(CLK_TOP_ETHIF_SEL, "ethif_sel", ethif_parents,
0x00D0, 24, 3, 31),
MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, "hdmirx26_24_sel", hdmirx_parents,
0x00E0, 0, 1, 7),
MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents,
0x00E0, 8, 3, 15),
MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents,
0x00E0, 16, 4, 23),
MUX_GATE(CLK_TOP_SPI1_SEL, "spi2_sel", spi_parents,
0x00E0, 24, 3, 31),
MUX_GATE(CLK_TOP_SPI2_SEL, "spi1_sel", spi_parents,
0x00F0, 0, 3, 7),
MUX_GATE(CLK_TOP_8BDAC_SEL, "8bdac_sel", clk_8bdac_parents,
0x00F0, 8, 2, 15),
MUX_GATE(CLK_TOP_AUD2DVD_SEL, "aud2dvd_sel", aud2dvd_parents,
0x00F0, 16, 1, 23),
MUX(CLK_TOP_PADMCLK_SEL, "padmclk_sel", padmclk_parents,
0x0100, 0, 3),
MUX(CLK_TOP_AUD_MUX1_SEL, "aud_mux1_sel", aud_mux_parents,
0x012c, 0, 3),
MUX(CLK_TOP_AUD_MUX2_SEL, "aud_mux2_sel", aud_mux_parents,
0x012c, 3, 3),
MUX(CLK_TOP_AUDPLL_MUX_SEL, "audpll_sel", aud_mux_parents,
0x012c, 6, 3),
MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, "aud_k1_src_sel", aud_src_parents,
0x012c, 15, 1, 23),
MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, "aud_k2_src_sel", aud_src_parents,
0x012c, 16, 1, 24),
MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, "aud_k3_src_sel", aud_src_parents,
0x012c, 17, 1, 25),
MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, "aud_k4_src_sel", aud_src_parents,
0x012c, 18, 1, 26),
MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, "aud_k5_src_sel", aud_src_parents,
0x012c, 19, 1, 27),
MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, "aud_k6_src_sel", aud_src_parents,
0x012c, 20, 1, 28),
};
static const struct mtk_clk_divider top_adj_divs[] = {
DIV_ADJ(CLK_TOP_AUD_EXTCK1_DIV, "audio_ext1_ck", "aud_ext1",
0x0120, 0, 8),
DIV_ADJ(CLK_TOP_AUD_EXTCK2_DIV, "audio_ext2_ck", "aud_ext2",
0x0120, 8, 8),
DIV_ADJ(CLK_TOP_AUD_MUX1_DIV, "aud_mux1_div", "aud_mux1_sel",
0x0120, 16, 8),
DIV_ADJ(CLK_TOP_AUD_MUX2_DIV, "aud_mux2_div", "aud_mux2_sel",
0x0120, 24, 8),
DIV_ADJ(CLK_TOP_AUD_K1_SRC_DIV, "aud_k1_src_div", "aud_k1_src_sel",
0x0124, 0, 8),
DIV_ADJ(CLK_TOP_AUD_K2_SRC_DIV, "aud_k2_src_div", "aud_k2_src_sel",
0x0124, 8, 8),
DIV_ADJ(CLK_TOP_AUD_K3_SRC_DIV, "aud_k3_src_div", "aud_k3_src_sel",
0x0124, 16, 8),
DIV_ADJ(CLK_TOP_AUD_K4_SRC_DIV, "aud_k4_src_div", "aud_k4_src_sel",
0x0124, 24, 8),
DIV_ADJ(CLK_TOP_AUD_K5_SRC_DIV, "aud_k5_src_div", "aud_k5_src_sel",
0x0128, 0, 8),
DIV_ADJ(CLK_TOP_AUD_K6_SRC_DIV, "aud_k6_src_div", "aud_k6_src_sel",
0x0128, 8, 8),
};
static const struct mtk_gate_regs top_aud_cg_regs = {
.sta_ofs = 0x012C,
};
#define GATE_TOP_AUD(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top_aud_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate top_clks[] = {
GATE_TOP_AUD(CLK_TOP_AUD_48K_TIMING, "a1sys_hp_ck", "aud_mux1_div",
21),
GATE_TOP_AUD(CLK_TOP_AUD_44K_TIMING, "a2sys_hp_ck", "aud_mux2_div",
22),
GATE_TOP_AUD(CLK_TOP_AUD_I2S1_MCLK, "aud_i2s1_mclk", "aud_k1_src_div",
23),
GATE_TOP_AUD(CLK_TOP_AUD_I2S2_MCLK, "aud_i2s2_mclk", "aud_k2_src_div",
24),
GATE_TOP_AUD(CLK_TOP_AUD_I2S3_MCLK, "aud_i2s3_mclk", "aud_k3_src_div",
25),
GATE_TOP_AUD(CLK_TOP_AUD_I2S4_MCLK, "aud_i2s4_mclk", "aud_k4_src_div",
26),
GATE_TOP_AUD(CLK_TOP_AUD_I2S5_MCLK, "aud_i2s5_mclk", "aud_k5_src_div",
27),
GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div",
28),
};
static int mtk_topckgen_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
struct device_node *node = pdev->dev.of_node;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
clk_data);
mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
clk_data);
mtk_clk_register_composites(&pdev->dev, top_muxes,
ARRAY_SIZE(top_muxes), base,
&mt2701_clk_lock, clk_data);
mtk_clk_register_dividers(&pdev->dev, top_adj_divs, ARRAY_SIZE(top_adj_divs),
base, &mt2701_clk_lock, clk_data);
mtk_clk_register_gates(&pdev->dev, node, top_clks,
ARRAY_SIZE(top_clks), clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct mtk_gate_regs infra_cg_regs = {
.set_ofs = 0x0040,
.clr_ofs = 0x0044,
.sta_ofs = 0x0048,
};
#define GATE_ICG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate infra_clks[] = {
GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0),
GATE_ICG(CLK_INFRA_SMI, "smi_ck", "mm_sel", 1),
GATE_ICG(CLK_INFRA_QAXI_CM4, "cm4_ck", "axi_sel", 2),
GATE_ICG(CLK_INFRA_AUD_SPLIN_B, "audio_splin_bck", "hadds2pll_294m", 4),
GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "clk26m", 5),
GATE_ICG(CLK_INFRA_EFUSE, "efuse_ck", "clk26m", 6),
GATE_ICG(CLK_INFRA_L2C_SRAM, "l2c_sram_ck", "mm_sel", 7),
GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
GATE_ICG(CLK_INFRA_CONNMCU, "connsys_bus", "wbg_dig_ck_416m", 12),
GATE_ICG(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 13),
GATE_ICG(CLK_INFRA_RAMBUFIF, "rambufif_ck", "mem_sel", 14),
GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "mem_sel", 15),
GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
GATE_ICG(CLK_INFRA_CEC, "cec_ck", "rtc_sel", 18),
GATE_ICG(CLK_INFRA_IRRX, "irrx_ck", "axi_sel", 19),
GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
GATE_ICG(CLK_INFRA_PMICWRAP, "pmicwrap_ck", "axi_sel", 23),
GATE_ICG(CLK_INFRA_DDCCI, "ddcci_ck", "axi_sel", 24),
};
static const struct mtk_fixed_factor infra_fixed_divs[] = {
FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
};
static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
/* infrasys */
{
.version = MTK_RST_SIMPLE,
.rst_bank_ofs = infrasys_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
},
/* pericfg */
{
.version = MTK_RST_SIMPLE,
.rst_bank_ofs = pericfg_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
},
};
static struct clk_hw_onecell_data *infra_clk_data;
static void __init mtk_infrasys_init_early(struct device_node *node)
{
int r, i;
if (!infra_clk_data) {
infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
for (i = 0; i < CLK_INFRA_NR; i++)
infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
}
mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
infra_clk_data);
mtk_clk_register_cpumuxes(NULL, node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
infra_clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
infra_clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
}
CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg",
mtk_infrasys_init_early);
static int mtk_infrasys_init(struct platform_device *pdev)
{
int r, i;
struct device_node *node = pdev->dev.of_node;
if (!infra_clk_data) {
infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
} else {
for (i = 0; i < CLK_INFRA_NR; i++) {
if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER))
infra_clk_data->hws[i] = ERR_PTR(-ENOENT);
}
}
mtk_clk_register_gates(&pdev->dev, node, infra_clks,
ARRAY_SIZE(infra_clks), infra_clk_data);
mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
infra_clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
infra_clk_data);
if (r)
return r;
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
return 0;
}
static const struct mtk_gate_regs peri0_cg_regs = {
.set_ofs = 0x0008,
.clr_ofs = 0x0010,
.sta_ofs = 0x0018,
};
static const struct mtk_gate_regs peri1_cg_regs = {
.set_ofs = 0x000c,
.clr_ofs = 0x0014,
.sta_ofs = 0x001c,
};
#define GATE_PERI0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_PERI1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate peri_clks[] = {
GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31),
GATE_PERI0(CLK_PERI_ETH, "eth_ck", "clk26m", 30),
GATE_PERI0(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29),
GATE_PERI0(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28),
GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27),
GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26),
GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25),
GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24),
GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23),
GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 22),
GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21),
GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20),
GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19),
GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 18),
GATE_PERI0(CLK_PERI_MSDC50_3, "msdc50_3_ck", "emmc_hclk_sel", 17),
GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_3_sel", 16),
GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 15),
GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 14),
GATE_PERI0(CLK_PERI_MSDC30_0, "msdc30_0_ck", "msdc30_0_sel", 13),
GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axisel_d4", 8),
GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axisel_d4", 7),
GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axisel_d4", 6),
GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axisel_d4", 5),
GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axisel_d4", 4),
GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axisel_d4", 3),
GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axisel_d4", 2),
GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0),
GATE_PERI1(CLK_PERI_FCI, "fci_ck", "ms_card_sel", 11),
GATE_PERI1(CLK_PERI_SPI2, "spi2_ck", "spi2_sel", 10),
GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi1_sel", 9),
GATE_PERI1(CLK_PERI_HOST89_DVD, "host89_dvd_ck", "aud2dvd_sel", 8),
GATE_PERI1(CLK_PERI_HOST89_SPI, "host89_spi_ck", "spi0_sel", 7),
GATE_PERI1(CLK_PERI_HOST89_INT, "host89_int_ck", "axi_sel", 6),
GATE_PERI1(CLK_PERI_FLASH, "flash_ck", "nfi2x_sel", 5),
GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "nfi1x_pad", 4),
GATE_PERI1(CLK_PERI_NFI_ECC, "nfi_ecc_ck", "nfi1x_pad", 3),
GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "axi_sel", 2),
GATE_PERI1(CLK_PERI_USB_SLV, "usbslv_ck", "axi_sel", 1),
GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 0),
};
static const char * const uart_ck_sel_parents[] = {
"clk26m",
"uart_sel",
};
static const struct mtk_composite peri_muxs[] = {
MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents,
0x40c, 0, 1),
MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents,
0x40c, 1, 1),
MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents,
0x40c, 2, 1),
MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents,
0x40c, 3, 1),
};
static int mtk_pericfg_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
int r;
struct device_node *node = pdev->dev.of_node;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_PERI_NR);
mtk_clk_register_gates(&pdev->dev, node, peri_clks,
ARRAY_SIZE(peri_clks), clk_data);
mtk_clk_register_composites(&pdev->dev, peri_muxs,
ARRAY_SIZE(peri_muxs), base,
&mt2701_clk_lock, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
return r;
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
return 0;
}
#define MT8590_PLL_FMAX (2000 * MHZ)
#define CON0_MT8590_RST_BAR BIT(27)
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
_pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = _en_mask, \
.flags = _flags, \
.rst_bar_mask = CON0_MT8590_RST_BAR, \
.fmax = MT8590_PLL_FMAX, \
.pcwbits = _pcwbits, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
}
static const struct mtk_pll_data apmixed_plls[] = {
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000000,
PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0),
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000000,
HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0),
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000000,
HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14),
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0, 0,
21, 0x230, 4, 0x0, 0x234, 0),
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
21, 0x240, 4, 0x0, 0x244, 0),
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0,
21, 0x250, 4, 0x0, 0x254, 0),
PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0,
31, 0x270, 4, 0x0, 0x274, 0),
PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0,
31, 0x280, 4, 0x0, 0x284, 0),
PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0,
31, 0x290, 4, 0x0, 0x294, 0),
PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0,
31, 0x2a0, 4, 0x0, 0x2a4, 0),
PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000001, 0,
31, 0x2b0, 4, 0x0, 0x2b4, 0),
PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000001, 0,
31, 0x2c0, 4, 0x0, 0x2c4, 0),
PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000001, 0,
21, 0x2d0, 4, 0x0, 0x2d4, 0),
};
static const struct mtk_fixed_factor apmixed_fixed_divs[] = {
FACTOR(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", 1, 1),
};
static int mtk_apmixedsys_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls),
clk_data);
mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs),
clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct of_device_id of_match_clk_mt2701[] = {
{
.compatible = "mediatek,mt2701-topckgen",
.data = mtk_topckgen_init,
}, {
.compatible = "mediatek,mt2701-infracfg",
.data = mtk_infrasys_init,
}, {
.compatible = "mediatek,mt2701-pericfg",
.data = mtk_pericfg_init,
}, {
.compatible = "mediatek,mt2701-apmixedsys",
.data = mtk_apmixedsys_init,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt2701);
static int clk_mt2701_probe(struct platform_device *pdev)
{
int (*clk_init)(struct platform_device *);
int r;
clk_init = of_device_get_match_data(&pdev->dev);
if (!clk_init)
return -EINVAL;
r = clk_init(pdev);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
return r;
}
static struct platform_driver clk_mt2701_drv = {
.probe = clk_mt2701_probe,
.driver = {
.name = "clk-mt2701",
.of_match_table = of_match_clk_mt2701,
},
};
static int __init clk_mt2701_init(void)
{
return platform_driver_register(&clk_mt2701_drv);
}
arch_initcall(clk_mt2701_init);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt2701.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 MediaTek Inc.
* Author: Sam Shih <[email protected]>
* Author: Wenzhen Yu <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include "clk-mux.h"
#include <dt-bindings/clock/mt7986-clk.h>
#include <linux/clk.h>
static DEFINE_SPINLOCK(mt7986_clk_lock);
static const struct mtk_fixed_factor infra_divs[] = {
FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", "sysaxi_sel", 1, 2),
};
static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
"uart_sel" };
static const char *const infra_spi_parents[] __initconst = { "i2c_sel",
"spi_sel" };
static const char *const infra_pwm_bsel_parents[] __initconst = {
"top_rtc_32p7k", "csw_f26m_sel", "infra_sysaxi_d2", "pwm_sel"
};
static const char *const infra_pcie_parents[] __initconst = {
"top_rtc_32p7k", "csw_f26m_sel", "top_xtal", "pextp_tl_ck_sel"
};
static const struct mtk_mux infra_muxes[] = {
/* MODULE_CLK_SEL_0 */
MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
-1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
-1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
-1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
infra_spi_parents, 0x0018, 0x0010, 0x0014, 4, 1,
-1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
infra_spi_parents, 0x0018, 0x0010, 0x0014, 5, 1,
-1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 9,
2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 11,
2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
2, -1, -1, -1),
/* MODULE_CLK_SEL_1 */
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
-1, -1, -1),
};
static const struct mtk_gate_regs infra0_cg_regs = {
.set_ofs = 0x40,
.clr_ofs = 0x44,
.sta_ofs = 0x48,
};
static const struct mtk_gate_regs infra1_cg_regs = {
.set_ofs = 0x50,
.clr_ofs = 0x54,
.sta_ofs = 0x58,
};
static const struct mtk_gate_regs infra2_cg_regs = {
.set_ofs = 0x60,
.clr_ofs = 0x64,
.sta_ofs = 0x68,
};
#define GATE_INFRA0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_INFRA1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_INFRA2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate infra_clks[] = {
/* INFRA0 */
GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_sysaxi_d2", 0),
GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_sysaxi_d2", 1),
GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi_sel", 6),
GATE_INFRA0(CLK_INFRA_EIP97_CK, "infra_eip97", "eip_b_sel", 7),
GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi_sel", 8),
GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l_sel", 10),
GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys_sel", 11),
GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner_sel", 13),
GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
14),
GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_sysaxi_d2", 15),
GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_sysaxi_d2", 16),
GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_sysaxi_d2", 24),
GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
GATE_INFRA0(CLK_INFRA_TRNG_CK, "infra_trng", "sysaxi_sel", 26),
/* INFRA1 */
GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_sel", 1),
GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x_sel", 8),
GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_sel", 9),
GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_sysaxi_d2",
10),
GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_sysaxi_d2",
13),
GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_sysaxi_d2",
14),
GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "top_rtc_32k", 15),
GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_416m_sel", 16),
GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_250m_sel",
17),
GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi_sel",
18),
GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_sysaxi_d2",
19),
GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m_sel", 21),
GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x_sel", 23),
/* INFRA2 */
GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi_sel", 0),
GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "infra_sysaxi_d2",
1),
GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys_sel", 2),
GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_sel", 3),
GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl_ck_sel", 12),
GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "top_xtal",
13),
GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m_sel", 14),
GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi_sel", 15),
};
static const struct mtk_clk_desc infra_desc = {
.clks = infra_clks,
.num_clks = ARRAY_SIZE(infra_clks),
.factor_clks = infra_divs,
.num_factor_clks = ARRAY_SIZE(infra_divs),
.mux_clks = infra_muxes,
.num_mux_clks = ARRAY_SIZE(infra_muxes),
.clk_lock = &mt7986_clk_lock,
};
static const struct of_device_id of_match_clk_mt7986_infracfg[] = {
{ .compatible = "mediatek,mt7986-infracfg", .data = &infra_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_infracfg);
static struct platform_driver clk_mt7986_infracfg_drv = {
.driver = {
.name = "clk-mt7986-infracfg",
.of_match_table = of_match_clk_mt7986_infracfg,
},
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt7986_infracfg_drv);
MODULE_DESCRIPTION("MediaTek MT7986 infracfg clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt7986-infracfg.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2018 MediaTek Inc.
// Author: Weiyi Lu <[email protected]>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8183-clk.h>
static const struct mtk_gate_regs ipu_core1_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_IPU_CORE1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ipu_core1_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr)
static const struct mtk_gate ipu_core1_clks[] = {
GATE_IPU_CORE1(CLK_IPU_CORE1_JTAG, "ipu_core1_jtag", "dsp_sel", 0),
GATE_IPU_CORE1(CLK_IPU_CORE1_AXI, "ipu_core1_axi", "dsp_sel", 1),
GATE_IPU_CORE1(CLK_IPU_CORE1_IPU, "ipu_core1_ipu", "dsp_sel", 2),
};
static const struct mtk_clk_desc ipu_core1_desc = {
.clks = ipu_core1_clks,
.num_clks = ARRAY_SIZE(ipu_core1_clks),
};
static const struct of_device_id of_match_clk_mt8183_ipu_core1[] = {
{
.compatible = "mediatek,mt8183-ipu_core1",
.data = &ipu_core1_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_ipu_core1);
static struct platform_driver clk_mt8183_ipu_core1_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8183-ipu_core1",
.of_match_table = of_match_clk_mt8183_ipu_core1,
},
};
module_platform_driver(clk_mt8183_ipu_core1_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8183-ipu1.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Garmin Chang <[email protected]>
*/
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include <dt-bindings/reset/mt8188-resets.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs infra_ao0_cg_regs = {
.set_ofs = 0x80,
.clr_ofs = 0x84,
.sta_ofs = 0x90,
};
static const struct mtk_gate_regs infra_ao1_cg_regs = {
.set_ofs = 0x88,
.clr_ofs = 0x8c,
.sta_ofs = 0x94,
};
static const struct mtk_gate_regs infra_ao2_cg_regs = {
.set_ofs = 0xa4,
.clr_ofs = 0xa8,
.sta_ofs = 0xac,
};
static const struct mtk_gate_regs infra_ao3_cg_regs = {
.set_ofs = 0xc0,
.clr_ofs = 0xc4,
.sta_ofs = 0xc8,
};
static const struct mtk_gate_regs infra_ao4_cg_regs = {
.set_ofs = 0xe0,
.clr_ofs = 0xe4,
.sta_ofs = 0xe8,
};
#define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flag)
#define GATE_INFRA_AO0(_id, _name, _parent, _shift) \
GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flag)
#define GATE_INFRA_AO1(_id, _name, _parent, _shift) \
GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA_AO2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra_ao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flag)
#define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flag)
#define GATE_INFRA_AO3(_id, _name, _parent, _shift) \
GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, _flag) \
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao4_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flag)
#define GATE_INFRA_AO4(_id, _name, _parent, _shift) \
GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, 0)
static const struct mtk_gate infra_ao_clks[] = {
/* INFRA_AO0 */
GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_TMR, "infra_ao_pmic_tmr", "top_pwrap_ulposc", 0),
GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_AP, "infra_ao_pmic_ap", "top_pwrap_ulposc", 1),
GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_MD, "infra_ao_pmic_md", "top_pwrap_ulposc", 2),
GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_CONN, "infra_ao_pmic_conn", "top_pwrap_ulposc", 3),
/* infra_ao_sej is main clock is for secure engine with JTAG support */
GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SEJ, "infra_ao_sej", "top_axi", 5, CLK_IS_CRITICAL),
GATE_INFRA_AO0(CLK_INFRA_AO_APXGPT, "infra_ao_apxgpt", "top_axi", 6),
GATE_INFRA_AO0(CLK_INFRA_AO_GCE, "infra_ao_gce", "top_axi", 8),
GATE_INFRA_AO0(CLK_INFRA_AO_GCE2, "infra_ao_gce2", "top_axi", 9),
GATE_INFRA_AO0(CLK_INFRA_AO_THERM, "infra_ao_therm", "top_axi", 10),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM_HCLK, "infra_ao_pwm_h", "top_axi", 15),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM1, "infra_ao_pwm1", "top_pwm", 16),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM2, "infra_ao_pwm2", "top_pwm", 17),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM3, "infra_ao_pwm3", "top_pwm", 18),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM4, "infra_ao_pwm4", "top_pwm", 19),
GATE_INFRA_AO0(CLK_INFRA_AO_PWM, "infra_ao_pwm", "top_pwm", 21),
GATE_INFRA_AO0(CLK_INFRA_AO_UART0, "infra_ao_uart0", "top_uart", 22),
GATE_INFRA_AO0(CLK_INFRA_AO_UART1, "infra_ao_uart1", "top_uart", 23),
GATE_INFRA_AO0(CLK_INFRA_AO_UART2, "infra_ao_uart2", "top_uart", 24),
GATE_INFRA_AO0(CLK_INFRA_AO_UART3, "infra_ao_uart3", "top_uart", 25),
GATE_INFRA_AO0(CLK_INFRA_AO_UART4, "infra_ao_uart4", "top_uart", 26),
GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, "infra_ao_gce_26m", "clk26m", 27),
GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, "infra_ao_dma", "pad_fpc_ck", 28),
GATE_INFRA_AO0(CLK_INFRA_AO_UART5, "infra_ao_uart5", "top_uart", 29),
/* INFRA_AO1 */
GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, "infra_ao_hdmi_26m", "clk26m", 0),
GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "top_spi", 1),
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, "infra_ao_msdc0", "top_msdc5hclk", 2),
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, "infra_ao_msdc1", "top_axi", 4),
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC2, "infra_ao_msdc2", "top_axi", 5),
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0_SRC, "infra_ao_msdc0_clk", "top_msdc50_0", 6),
/* infra_ao_dvfsrc is for internal DVFS usage, should not be handled by Linux. */
GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DVFSRC, "infra_ao_dvfsrc",
"clk26m", 7, CLK_IS_CRITICAL),
GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, "infra_ao_trng", "top_axi", 9),
GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, "infra_ao_auxadc", "clk26m", 10),
GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, "infra_ao_cpum", "top_axi", 11),
GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_32K, "infra_ao_hdmi_32k", "clk32k", 12),
GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_HCLK, "infra_ao_cec_66m_hclk", "top_axi", 13),
GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_26M, "infra_ao_pcie_tl_26m", "clk26m", 15),
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1_SRC, "infra_ao_msdc1_clk", "top_msdc30_1", 16),
GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_BCLK, "infra_ao_cec_66m_bclk", "top_axi", 17),
GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_96M, "infra_ao_pcie_tl_96m", "top_tl", 18),
/* infra_ao_dapc is for device access permission control module */
GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DEVICE_APC, "infra_ao_dapc",
"top_axi", 20, CLK_IS_CRITICAL),
GATE_INFRA_AO1(CLK_INFRA_AO_ECC_66M_HCLK, "infra_ao_ecc_66m_hclk", "top_axi", 23),
GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGSYS, "infra_ao_debugsys", "top_axi", 24),
GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, "infra_ao_audio", "top_axi", 25),
GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_32K, "infra_ao_pcie_tl_32k", "clk32k", 26),
GATE_INFRA_AO1(CLK_INFRA_AO_DBG_TRACE, "infra_ao_dbg_trace", "top_axi", 29),
GATE_INFRA_AO1(CLK_INFRA_AO_DRAMC_F26M, "infra_ao_dramc26", "clk26m", 31),
/* INFRA_AO2 */
GATE_INFRA_AO2(CLK_INFRA_AO_IRTX, "infra_ao_irtx", "top_axi", 0),
GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, "infra_ao_disp_pwm", "top_disp_pwm0", 2),
GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_BCLK, "infra_ao_cldmabclk", "top_axi", 3),
GATE_INFRA_AO2(CLK_INFRA_AO_AUDIO_26M_BCLK, "infra_ao_audio26m", "clk26m", 4),
GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "top_spi", 6),
GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, "infra_ao_spi2", "top_spi", 9),
GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, "infra_ao_spi3", "top_spi", 10),
GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_FSSPM, "infra_ao_fsspm",
"top_sspm", 15, CLK_IS_CRITICAL),
GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_SSPM_BUS_HCLK, "infra_ao_sspm_hclk",
"top_axi", 17, CLK_IS_CRITICAL),
GATE_INFRA_AO2(CLK_INFRA_AO_APDMA_BCLK, "infra_ao_apdma_bclk", "top_axi", 18),
GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, "infra_ao_spi4", "top_spi", 25),
GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, "infra_ao_spi5", "top_spi", 26),
GATE_INFRA_AO2(CLK_INFRA_AO_CQ_DMA, "infra_ao_cq_dma", "top_axi", 27),
/* INFRA_AO3 */
GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SELF, "infra_ao_msdc0sf", "top_msdc50_0", 0),
GATE_INFRA_AO3(CLK_INFRA_AO_MSDC1_SELF, "infra_ao_msdc1sf", "top_msdc50_0", 1),
GATE_INFRA_AO3(CLK_INFRA_AO_MSDC2_SELF, "infra_ao_msdc2sf", "top_msdc50_0", 2),
GATE_INFRA_AO3(CLK_INFRA_AO_I2S_DMA, "infra_ao_i2s_dma", "top_axi", 5),
GATE_INFRA_AO3(CLK_INFRA_AO_AP_MSDC0, "infra_ao_ap_msdc0", "top_msdc50_0", 7),
GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, "infra_ao_md_msdc0", "top_msdc50_0", 8),
GATE_INFRA_AO3(CLK_INFRA_AO_MSDC30_2, "infra_ao_msdc30_2", "top_msdc30_2", 9),
GATE_INFRA_AO3(CLK_INFRA_AO_GCPU, "infra_ao_gcpu", "top_gcpu", 10),
GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_PERI_26M, "infra_ao_pcie_peri_26m", "clk26m", 15),
GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_66M_BCLK, "infra_ao_gcpu_66m_bclk", "top_axi", 16),
GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_133M_BCLK, "infra_ao_gcpu_133m_bclk", "top_axi", 17),
GATE_INFRA_AO3(CLK_INFRA_AO_DISP_PWM1, "infra_ao_disp_pwm1", "top_disp_pwm1", 20),
GATE_INFRA_AO3(CLK_INFRA_AO_FBIST2FPC, "infra_ao_fbist2fpc", "top_msdc50_0", 24),
/* infra_ao_dapc_sync is for device access permission control module */
GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_DEVICE_APC_SYNC, "infra_ao_dapc_sync",
"top_axi", 25, CLK_IS_CRITICAL),
GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_P1_PERI_26M, "infra_ao_pcie_p1_peri_26m", "clk26m", 26),
/* INFRA_AO4 */
/* infra_ao_133m_mclk_set/infra_ao_66m_mclk_set are main clocks of peripheral */
GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_133M_MCLK_CK, "infra_ao_133m_mclk_set",
"top_axi", 0, CLK_IS_CRITICAL),
GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_66M_MCLK_CK, "infra_ao_66m_mclk_set",
"top_axi", 1, CLK_IS_CRITICAL),
GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P0, "infra_ao_pcie_pl_p_250m_p0",
"pextp_pipe", 7),
GATE_INFRA_AO4(CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P,
"infra_ao_aes_msdcfde_0p", "top_aes_msdcfde", 18),
};
static u16 infra_ao_rst_ofs[] = {
INFRA_RST0_SET_OFFSET,
INFRA_RST1_SET_OFFSET,
INFRA_RST2_SET_OFFSET,
INFRA_RST3_SET_OFFSET,
INFRA_RST4_SET_OFFSET,
};
static u16 infra_ao_idx_map[] = {
[MT8188_INFRA_RST1_THERMAL_MCU_RST] = 1 * RST_NR_PER_BANK + 2,
[MT8188_INFRA_RST1_THERMAL_CTRL_RST] = 1 * RST_NR_PER_BANK + 4,
[MT8188_INFRA_RST3_PTP_CTRL_RST] = 3 * RST_NR_PER_BANK + 5,
};
static const struct mtk_clk_rst_desc infra_ao_rst_desc = {
.version = MTK_RST_SET_CLR,
.rst_bank_ofs = infra_ao_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
.rst_idx_map = infra_ao_idx_map,
.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
};
static const struct mtk_clk_desc infra_ao_desc = {
.clks = infra_ao_clks,
.num_clks = ARRAY_SIZE(infra_ao_clks),
.rst_desc = &infra_ao_rst_desc,
};
static const struct of_device_id of_match_clk_mt8188_infra_ao[] = {
{ .compatible = "mediatek,mt8188-infracfg-ao", .data = &infra_ao_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_infra_ao);
static struct platform_driver clk_mt8188_infra_ao_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8188-infra_ao",
.of_match_table = of_match_clk_mt8188_infra_ao,
},
};
module_platform_driver(clk_mt8188_infra_ao_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8188-infra_ao.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Garmin Chang <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs adsp_audio26m_cg_regs = {
.set_ofs = 0x80,
.clr_ofs = 0x80,
.sta_ofs = 0x80,
};
#define GATE_ADSP_FLAGS(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &adsp_audio26m_cg_regs, _shift, \
&mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate adsp_audio26m_clks[] = {
GATE_ADSP_FLAGS(CLK_AUDIODSP_AUDIO26M, "audiodsp_audio26m", "clk26m", 3),
};
static const struct mtk_clk_desc adsp_audio26m_desc = {
.clks = adsp_audio26m_clks,
.num_clks = ARRAY_SIZE(adsp_audio26m_clks),
};
static const struct of_device_id of_match_clk_mt8188_adsp_audio26m[] = {
{ .compatible = "mediatek,mt8188-adsp-audio26m", .data = &adsp_audio26m_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_adsp_audio26m);
static struct platform_driver clk_mt8188_adsp_audio26m_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8188-adsp_audio26m",
.of_match_table = of_match_clk_mt8188_adsp_audio26m,
},
};
module_platform_driver(clk_mt8188_adsp_audio26m_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs vpp1_0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs vpp1_1_cg_regs = {
.set_ofs = 0x114,
.clr_ofs = 0x118,
.sta_ofs = 0x110,
};
#define GATE_VPP1_0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vpp1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VPP1_1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vpp1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate vpp1_clks[] = {
/* VPP1_0 */
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_OVL, "vpp1_svpp1_mdp_ovl", "top_vpp", 0),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TCC, "vpp1_svpp1_mdp_tcc", "top_vpp", 1),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_WROT, "vpp1_svpp1_mdp_wrot", "top_vpp", 2),
GATE_VPP1_0(CLK_VPP1_SVPP1_VPP_PAD, "vpp1_svpp1_vpp_pad", "top_vpp", 3),
GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_WROT, "vpp1_svpp2_mdp_wrot", "top_vpp", 4),
GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_PAD, "vpp1_svpp2_vpp_pad", "top_vpp", 5),
GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_WROT, "vpp1_svpp3_mdp_wrot", "top_vpp", 6),
GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_PAD, "vpp1_svpp3_vpp_pad", "top_vpp", 7),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RDMA, "vpp1_svpp1_mdp_rdma", "top_vpp", 8),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_FG, "vpp1_svpp1_mdp_fg", "top_vpp", 9),
GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RDMA, "vpp1_svpp2_mdp_rdma", "top_vpp", 10),
GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_FG, "vpp1_svpp2_mdp_fg", "top_vpp", 11),
GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RDMA, "vpp1_svpp3_mdp_rdma", "top_vpp", 12),
GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_FG, "vpp1_svpp3_mdp_fg", "top_vpp", 13),
GATE_VPP1_0(CLK_VPP1_VPP_SPLIT, "vpp1_vpp_split", "top_vpp", 14),
GATE_VPP1_0(CLK_VPP1_SVPP2_VDO0_DL_RELAY, "vpp1_svpp2_vdo0_dl_relay", "top_vpp", 15),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TDSHP, "vpp1_svpp1_mdp_tdshp", "top_vpp", 16),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_COLOR, "vpp1_svpp1_mdp_color", "top_vpp", 17),
GATE_VPP1_0(CLK_VPP1_SVPP3_VDO1_DL_RELAY, "vpp1_svpp3_vdo1_dl_relay", "top_vpp", 18),
GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_MERGE, "vpp1_svpp2_vpp_merge", "top_vpp", 19),
GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_COLOR, "vpp1_svpp2_mdp_color", "top_vpp", 20),
GATE_VPP1_0(CLK_VPP1_VPPSYS1_GALS, "vpp1_vppsys1_gals", "top_vpp", 21),
GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_MERGE, "vpp1_svpp3_vpp_merge", "top_vpp", 22),
GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_COLOR, "vpp1_svpp3_mdp_color", "top_vpp", 23),
GATE_VPP1_0(CLK_VPP1_VPPSYS1_LARB, "vpp1_vppsys1_larb", "top_vpp", 24),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RSZ, "vpp1_svpp1_mdp_rsz", "top_vpp", 25),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_HDR, "vpp1_svpp1_mdp_hdr", "top_vpp", 26),
GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_AAL, "vpp1_svpp1_mdp_aal", "top_vpp", 27),
GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_HDR, "vpp1_svpp2_mdp_hdr", "top_vpp", 28),
GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_AAL, "vpp1_svpp2_mdp_aal", "top_vpp", 29),
GATE_VPP1_0(CLK_VPP1_DL_ASYNC, "vpp1_dl_async", "top_vpp", 30),
GATE_VPP1_0(CLK_VPP1_LARB5_FAKE_ENG, "vpp1_larb5_fake_eng", "top_vpp", 31),
/* VPP1_1 */
GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_HDR, "vpp1_svpp3_mdp_hdr", "top_vpp", 0),
GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_AAL, "vpp1_svpp3_mdp_aal", "top_vpp", 1),
GATE_VPP1_1(CLK_VPP1_SVPP2_VDO1_DL_RELAY, "vpp1_svpp2_vdo1_dl_relay", "top_vpp", 2),
GATE_VPP1_1(CLK_VPP1_LARB6_FAKE_ENG, "vpp1_larb6_fake_eng", "top_vpp", 3),
GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_RSZ, "vpp1_svpp2_mdp_rsz", "top_vpp", 4),
GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_RSZ, "vpp1_svpp3_mdp_rsz", "top_vpp", 5),
GATE_VPP1_1(CLK_VPP1_SVPP3_VDO0_DL_RELAY, "vpp1_svpp3_vdo0_dl_relay", "top_vpp", 6),
GATE_VPP1_1(CLK_VPP1_DISP_MUTEX, "vpp1_disp_mutex", "top_vpp", 7),
GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_TDSHP, "vpp1_svpp2_mdp_tdshp", "top_vpp", 8),
GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_TDSHP, "vpp1_svpp3_mdp_tdshp", "top_vpp", 9),
GATE_VPP1_1(CLK_VPP1_VPP0_DL1_RELAY, "vpp1_vpp0_dl1_relay", "top_vpp", 10),
GATE_VPP1_1(CLK_VPP1_HDMI_META, "vpp1_hdmi_meta", "hdmirx_p", 11),
GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_HDMI, "vpp1_vpp_split_hdmi", "hdmirx_p", 12),
GATE_VPP1_1(CLK_VPP1_DGI_IN, "vpp1_dgi_in", "in_dgi", 13),
GATE_VPP1_1(CLK_VPP1_DGI_OUT, "vpp1_dgi_out", "top_dgi_out", 14),
GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_DGI, "vpp1_vpp_split_dgi", "top_dgi_out", 15),
GATE_VPP1_1(CLK_VPP1_VPP0_DL_ASYNC, "vpp1_vpp0_dl_async", "top_vpp", 16),
GATE_VPP1_1(CLK_VPP1_VPP0_DL_RELAY, "vpp1_vpp0_dl_relay", "top_vpp", 17),
GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m", "clk26m", 26),
};
static const struct mtk_clk_desc vpp1_desc = {
.clks = vpp1_clks,
.num_clks = ARRAY_SIZE(vpp1_clks),
};
static const struct platform_device_id clk_mt8195_vpp1_id_table[] = {
{ .name = "clk-mt8195-vpp1", .driver_data = (kernel_ulong_t)&vpp1_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, clk_mt8195_vpp1_id_table);
static struct platform_driver clk_mt8195_vpp1_drv = {
.probe = mtk_clk_pdev_probe,
.remove_new = mtk_clk_pdev_remove,
.driver = {
.name = "clk-mt8195-vpp1",
},
.id_table = clk_mt8195_vpp1_id_table,
};
module_platform_driver(clk_mt8195_vpp1_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8195-vpp1.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Chen Zhong <[email protected]>
* Sean Wang <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt7622-clk.h>
#define GATE_ETH(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate_regs eth_cg_regs = {
.set_ofs = 0x30,
.clr_ofs = 0x30,
.sta_ofs = 0x30,
};
static const struct mtk_gate eth_clks[] = {
GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5),
GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6),
GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
};
static const struct mtk_gate_regs sgmii_cg_regs = {
.set_ofs = 0xE4,
.clr_ofs = 0xE4,
.sta_ofs = 0xE4,
};
#define GATE_SGMII(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &sgmii_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate sgmii_clks[] = {
GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en",
"ssusb_tx250m", 2),
GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en",
"ssusb_eq_rx250m", 3),
GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
"ssusb_cdr_ref", 4),
GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
"ssusb_cdr_fb", 5),
};
static u16 rst_ofs[] = { 0x34, };
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SIMPLE,
.rst_bank_ofs = rst_ofs,
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
static const struct mtk_clk_desc eth_desc = {
.clks = eth_clks,
.num_clks = ARRAY_SIZE(eth_clks),
.rst_desc = &clk_rst_desc,
};
static const struct mtk_clk_desc sgmii_desc = {
.clks = sgmii_clks,
.num_clks = ARRAY_SIZE(sgmii_clks),
};
static const struct of_device_id of_match_clk_mt7622_eth[] = {
{ .compatible = "mediatek,mt7622-ethsys", .data = ð_desc },
{ .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_eth);
static struct platform_driver clk_mt7622_eth_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7622-eth",
.of_match_table = of_match_clk_mt7622_eth,
},
};
module_platform_driver(clk_mt7622_eth_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt7622-eth.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2018 MediaTek Inc.
// Author: Weiyi Lu <[email protected]>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8183-clk.h>
static const struct mtk_gate_regs venc_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_VENC_I(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate venc_clks[] = {
GATE_VENC_I(CLK_VENC_LARB, "venc_larb",
"mm_sel", 0),
GATE_VENC_I(CLK_VENC_VENC, "venc_venc",
"mm_sel", 4),
GATE_VENC_I(CLK_VENC_JPGENC, "venc_jpgenc",
"mm_sel", 8),
};
static const struct mtk_clk_desc venc_desc = {
.clks = venc_clks,
.num_clks = ARRAY_SIZE(venc_clks),
};
static const struct of_device_id of_match_clk_mt8183_venc[] = {
{
.compatible = "mediatek,mt8183-vencsys",
.data = &venc_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_venc);
static struct platform_driver clk_mt8183_venc_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8183-venc",
.of_match_table = of_match_clk_mt8183_venc,
},
};
module_platform_driver(clk_mt8183_venc_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8183-venc.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* James Liao <[email protected]>
* Copyright (c) 2023 Collabora, Ltd.
* AngeloGioacchino Del Regno <[email protected]>
*/
#include <dt-bindings/clock/mt8135-clk.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-pll.h"
#define MT8135_PLL_FMAX (2000 * MHZ)
#define CON0_MT8135_RST_BAR BIT(27)
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = _en_mask, \
.flags = _flags, \
.rst_bar_mask = CON0_MT8135_RST_BAR, \
.fmax = MT8135_PLL_FMAX, \
.pcwbits = _pcwbits, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
}
static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000000, 0, 21, 0x204, 24, 0x0, 0x204, 0),
PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000000, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0),
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000000, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x238, 9),
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, 0),
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000000, 0, 31, 0x294, 6, 0x0, 0x298, 0),
PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000000, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),
};
static int clk_mt8135_apmixed_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int ret;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
if (!clk_data)
return -ENOMEM;
ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
if (ret)
return ret;
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (ret)
goto unregister_plls;
return 0;
unregister_plls:
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
return ret;
}
static void clk_mt8135_apmixed_remove(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
of_clk_del_provider(node);
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
mtk_free_clk_data(clk_data);
}
static const struct of_device_id of_match_clk_mt8135_apmixed[] = {
{ .compatible = "mediatek,mt8135-apmixedsys" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8135_apmixed);
static struct platform_driver clk_mt8135_apmixed_drv = {
.probe = clk_mt8135_apmixed_probe,
.remove_new = clk_mt8135_apmixed_remove,
.driver = {
.name = "clk-mt8135-apmixed",
.of_match_table = of_match_clk_mt8135_apmixed,
},
};
module_platform_driver(clk_mt8135_apmixed_drv)
MODULE_DESCRIPTION("MediaTek MT8135 apmixedsys clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8135-apmixedsys.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 MediaTek Inc.
* Copyright (c) 2020 BayLibre, SAS
* Copyright (c) 2023 Collabora, Ltd.
*/
#include <dt-bindings/clock/mt8167-clk.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "clk-pll.h"
#include "clk-mtk.h"
static DEFINE_SPINLOCK(mt8167_apmixed_clk_lock);
#define MT8167_PLL_FMAX (2500UL * MHZ)
#define CON0_MT8167_RST_BAR BIT(27)
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
_pcw_shift, _div_table) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = _en_mask, \
.flags = _flags, \
.rst_bar_mask = CON0_MT8167_RST_BAR, \
.fmax = MT8167_PLL_FMAX, \
.pcwbits = _pcwbits, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
.div_table = _div_table, \
}
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
_pcw_shift) \
PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
NULL)
static const struct mtk_pll_div_table mmpll_div_table[] = {
{ .div = 0, .freq = MT8167_PLL_FMAX },
{ .div = 1, .freq = 1000000000 },
{ .div = 2, .freq = 604500000 },
{ .div = 3, .freq = 253500000 },
{ .div = 4, .freq = 126750000 },
{ /* sentinel */ }
};
static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0,
21, 0x0104, 24, 0, 0x0104, 0),
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0,
HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0),
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000,
HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0),
PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0,
21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table),
PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0,
31, 0x0180, 1, 0x0194, 0x0184, 0),
PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0,
31, 0x01A0, 1, 0x01B4, 0x01A4, 0),
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x01C0, 0x01D0, 0, 0,
21, 0x01C4, 24, 0, 0x01C4, 0),
PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x01E0, 0x01F0, 0, 0,
21, 0x01E4, 24, 0, 0x01E4, 0),
};
#define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.div_reg = _reg, \
.div_shift = _shift, \
.div_width = _width, \
.clk_divider_flags = _flag, \
}
static const struct mtk_clk_divider adj_divs[] = {
DIV_ADJ_FLAG(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll",
0x1c4, 24, 3, CLK_DIVIDER_POWER_OF_TWO),
};
static int clk_mt8167_apmixed_probe(struct platform_device *pdev)
{
void __iomem *base;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
struct device *dev = &pdev->dev;
int ret;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_devm_alloc_clk_data(dev, MT8167_CLK_APMIXED_NR_CLK);
if (!clk_data)
return -ENOMEM;
ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
if (ret)
return ret;
ret = mtk_clk_register_dividers(dev, adj_divs, ARRAY_SIZE(adj_divs), base,
&mt8167_apmixed_clk_lock, clk_data);
if (ret)
goto unregister_plls;
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (ret)
goto unregister_dividers;
return 0;
unregister_dividers:
mtk_clk_unregister_dividers(adj_divs, ARRAY_SIZE(adj_divs), clk_data);
unregister_plls:
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
return ret;
}
static const struct of_device_id of_match_clk_mt8167_apmixed[] = {
{ .compatible = "mediatek,mt8167-apmixedsys" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_apmixed);
static struct platform_driver clk_mt8167_apmixed_drv = {
.probe = clk_mt8167_apmixed_probe,
.driver = {
.name = "clk-mt8167-apmixed",
.of_match_table = of_match_clk_mt8167_apmixed,
},
};
builtin_platform_driver(clk_mt8167_apmixed_drv)
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8167-apmixedsys.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 MediaTek Inc.
* Author: Ryder Lee <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt2701-clk.h>
#define GATE_AUDIO0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
#define GATE_AUDIO1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
#define GATE_AUDIO2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &audio2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
#define GATE_AUDIO3(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &audio3_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate_regs audio0_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x0,
.sta_ofs = 0x0,
};
static const struct mtk_gate_regs audio1_cg_regs = {
.set_ofs = 0x10,
.clr_ofs = 0x10,
.sta_ofs = 0x10,
};
static const struct mtk_gate_regs audio2_cg_regs = {
.set_ofs = 0x14,
.clr_ofs = 0x14,
.sta_ofs = 0x14,
};
static const struct mtk_gate_regs audio3_cg_regs = {
.set_ofs = 0x634,
.clr_ofs = 0x634,
.sta_ofs = 0x634,
};
static const struct mtk_gate audio_clks[] = {
GATE_DUMMY(CLK_DUMMY, "aud_dummy"),
/* AUDIO0 */
GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),
GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
GATE_AUDIO0(CLK_AUD_SPDF, "audio_spdf", "audpll_sel", 21),
GATE_AUDIO0(CLK_AUD_SPDF2, "audio_spdf2", "audpll_sel", 22),
GATE_AUDIO0(CLK_AUD_APLL, "audio_apll", "audpll_sel", 23),
/* AUDIO1 */
GATE_AUDIO1(CLK_AUD_I2SIN1, "audio_i2sin1", "aud_mux1_sel", 0),
GATE_AUDIO1(CLK_AUD_I2SIN2, "audio_i2sin2", "aud_mux1_sel", 1),
GATE_AUDIO1(CLK_AUD_I2SIN3, "audio_i2sin3", "aud_mux1_sel", 2),
GATE_AUDIO1(CLK_AUD_I2SIN4, "audio_i2sin4", "aud_mux1_sel", 3),
GATE_AUDIO1(CLK_AUD_I2SIN5, "audio_i2sin5", "aud_mux1_sel", 4),
GATE_AUDIO1(CLK_AUD_I2SIN6, "audio_i2sin6", "aud_mux1_sel", 5),
GATE_AUDIO1(CLK_AUD_I2SO1, "audio_i2so1", "aud_mux1_sel", 6),
GATE_AUDIO1(CLK_AUD_I2SO2, "audio_i2so2", "aud_mux1_sel", 7),
GATE_AUDIO1(CLK_AUD_I2SO3, "audio_i2so3", "aud_mux1_sel", 8),
GATE_AUDIO1(CLK_AUD_I2SO4, "audio_i2so4", "aud_mux1_sel", 9),
GATE_AUDIO1(CLK_AUD_I2SO5, "audio_i2so5", "aud_mux1_sel", 10),
GATE_AUDIO1(CLK_AUD_I2SO6, "audio_i2so6", "aud_mux1_sel", 11),
GATE_AUDIO1(CLK_AUD_ASRCI1, "audio_asrci1", "asm_h_sel", 12),
GATE_AUDIO1(CLK_AUD_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
GATE_AUDIO1(CLK_AUD_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
GATE_AUDIO1(CLK_AUD_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
GATE_AUDIO1(CLK_AUD_INTDIR, "audio_intdir", "intdir_sel", 20),
GATE_AUDIO1(CLK_AUD_A1SYS, "audio_a1sys", "aud_mux1_sel", 21),
GATE_AUDIO1(CLK_AUD_A2SYS, "audio_a2sys", "aud_mux2_sel", 22),
GATE_AUDIO1(CLK_AUD_AFE_CONN, "audio_afe_conn", "aud_mux1_sel", 23),
GATE_AUDIO1(CLK_AUD_AFE_MRGIF, "audio_afe_mrgif", "aud_mux1_sel", 25),
/* AUDIO2 */
GATE_AUDIO2(CLK_AUD_MMIF_UL1, "audio_ul1", "aud_mux1_sel", 0),
GATE_AUDIO2(CLK_AUD_MMIF_UL2, "audio_ul2", "aud_mux1_sel", 1),
GATE_AUDIO2(CLK_AUD_MMIF_UL3, "audio_ul3", "aud_mux1_sel", 2),
GATE_AUDIO2(CLK_AUD_MMIF_UL4, "audio_ul4", "aud_mux1_sel", 3),
GATE_AUDIO2(CLK_AUD_MMIF_UL5, "audio_ul5", "aud_mux1_sel", 4),
GATE_AUDIO2(CLK_AUD_MMIF_UL6, "audio_ul6", "aud_mux1_sel", 5),
GATE_AUDIO2(CLK_AUD_MMIF_DL1, "audio_dl1", "aud_mux1_sel", 6),
GATE_AUDIO2(CLK_AUD_MMIF_DL2, "audio_dl2", "aud_mux1_sel", 7),
GATE_AUDIO2(CLK_AUD_MMIF_DL3, "audio_dl3", "aud_mux1_sel", 8),
GATE_AUDIO2(CLK_AUD_MMIF_DL4, "audio_dl4", "aud_mux1_sel", 9),
GATE_AUDIO2(CLK_AUD_MMIF_DL5, "audio_dl5", "aud_mux1_sel", 10),
GATE_AUDIO2(CLK_AUD_MMIF_DL6, "audio_dl6", "aud_mux1_sel", 11),
GATE_AUDIO2(CLK_AUD_MMIF_DLMCH, "audio_dlmch", "aud_mux1_sel", 12),
GATE_AUDIO2(CLK_AUD_MMIF_ARB1, "audio_arb1", "aud_mux1_sel", 13),
GATE_AUDIO2(CLK_AUD_MMIF_AWB1, "audio_awb", "aud_mux1_sel", 14),
GATE_AUDIO2(CLK_AUD_MMIF_AWB2, "audio_awb2", "aud_mux1_sel", 15),
GATE_AUDIO2(CLK_AUD_MMIF_DAI, "audio_dai", "aud_mux1_sel", 16),
/* AUDIO3 */
GATE_AUDIO3(CLK_AUD_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
GATE_AUDIO3(CLK_AUD_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
GATE_AUDIO3(CLK_AUD_ASRCI5, "audio_asrci5", "asm_h_sel", 4),
GATE_AUDIO3(CLK_AUD_ASRCI6, "audio_asrci6", "asm_h_sel", 5),
GATE_AUDIO3(CLK_AUD_ASRCO3, "audio_asrco3", "asm_h_sel", 6),
GATE_AUDIO3(CLK_AUD_ASRCO4, "audio_asrco4", "asm_h_sel", 7),
GATE_AUDIO3(CLK_AUD_ASRCO5, "audio_asrco5", "asm_h_sel", 8),
GATE_AUDIO3(CLK_AUD_ASRCO6, "audio_asrco6", "asm_h_sel", 9),
GATE_AUDIO3(CLK_AUD_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10),
GATE_AUDIO3(CLK_AUD_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11),
GATE_AUDIO3(CLK_AUD_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12),
GATE_AUDIO3(CLK_AUD_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13),
GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
};
static const struct mtk_clk_desc audio_desc = {
.clks = audio_clks,
.num_clks = ARRAY_SIZE(audio_clks),
};
static const struct of_device_id of_match_clk_mt2701_aud[] = {
{ .compatible = "mediatek,mt2701-audsys", .data = &audio_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_aud);
static int clk_mt2701_aud_probe(struct platform_device *pdev)
{
int r;
r = mtk_clk_simple_probe(pdev);
if (r) {
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
return r;
}
r = devm_of_platform_populate(&pdev->dev);
if (r)
goto err_plat_populate;
return 0;
err_plat_populate:
mtk_clk_simple_remove(pdev);
return r;
}
static void clk_mt2701_aud_remove(struct platform_device *pdev)
{
of_platform_depopulate(&pdev->dev);
mtk_clk_simple_remove(pdev);
}
static struct platform_driver clk_mt2701_aud_drv = {
.probe = clk_mt2701_aud_probe,
.remove_new = clk_mt2701_aud_remove,
.driver = {
.name = "clk-mt2701-aud",
.of_match_table = of_match_clk_mt2701_aud,
},
};
module_platform_driver(clk_mt2701_aud_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt2701-aud.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Shunli Wang <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt2701-clk.h>
static const struct mtk_gate_regs bdp0_cg_regs = {
.set_ofs = 0x0104,
.clr_ofs = 0x0108,
.sta_ofs = 0x0100,
};
static const struct mtk_gate_regs bdp1_cg_regs = {
.set_ofs = 0x0114,
.clr_ofs = 0x0118,
.sta_ofs = 0x0110,
};
#define GATE_BDP0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &bdp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
#define GATE_BDP1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &bdp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate bdp_clks[] = {
GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0),
GATE_BDP0(CLK_BDP_BRG_DRAM, "brg_dram", "mm_sel", 1),
GATE_BDP0(CLK_BDP_LARB_DRAM, "larb_dram", "mm_sel", 2),
GATE_BDP0(CLK_BDP_WR_VDI_PXL, "wr_vdi_pxl", "hdmi_0_deep340m", 3),
GATE_BDP0(CLK_BDP_WR_VDI_DRAM, "wr_vdi_dram", "mm_sel", 4),
GATE_BDP0(CLK_BDP_WR_B, "wr_bclk", "mm_sel", 5),
GATE_BDP0(CLK_BDP_DGI_IN, "dgi_in", "dpi1_sel", 6),
GATE_BDP0(CLK_BDP_DGI_OUT, "dgi_out", "dpi1_sel", 7),
GATE_BDP0(CLK_BDP_FMT_MAST_27, "fmt_mast_27", "dpi1_sel", 8),
GATE_BDP0(CLK_BDP_FMT_B, "fmt_bclk", "mm_sel", 9),
GATE_BDP0(CLK_BDP_OSD_B, "osd_bclk", "mm_sel", 10),
GATE_BDP0(CLK_BDP_OSD_DRAM, "osd_dram", "mm_sel", 11),
GATE_BDP0(CLK_BDP_OSD_AGENT, "osd_agent", "osd_sel", 12),
GATE_BDP0(CLK_BDP_OSD_PXL, "osd_pxl", "dpi1_sel", 13),
GATE_BDP0(CLK_BDP_RLE_B, "rle_bclk", "mm_sel", 14),
GATE_BDP0(CLK_BDP_RLE_AGENT, "rle_agent", "mm_sel", 15),
GATE_BDP0(CLK_BDP_RLE_DRAM, "rle_dram", "mm_sel", 16),
GATE_BDP0(CLK_BDP_F27M, "f27m", "di_sel", 17),
GATE_BDP0(CLK_BDP_F27M_VDOUT, "f27m_vdout", "di_sel", 18),
GATE_BDP0(CLK_BDP_F27_74_74, "f27_74_74", "di_sel", 19),
GATE_BDP0(CLK_BDP_F2FS, "f2fs", "di_sel", 20),
GATE_BDP0(CLK_BDP_F2FS74_148, "f2fs74_148", "di_sel", 21),
GATE_BDP0(CLK_BDP_FB, "fbclk", "mm_sel", 22),
GATE_BDP0(CLK_BDP_VDO_DRAM, "vdo_dram", "mm_sel", 23),
GATE_BDP0(CLK_BDP_VDO_2FS, "vdo_2fs", "di_sel", 24),
GATE_BDP0(CLK_BDP_VDO_B, "vdo_bclk", "mm_sel", 25),
GATE_BDP0(CLK_BDP_WR_DI_PXL, "wr_di_pxl", "di_sel", 26),
GATE_BDP0(CLK_BDP_WR_DI_DRAM, "wr_di_dram", "mm_sel", 27),
GATE_BDP0(CLK_BDP_WR_DI_B, "wr_di_bclk", "mm_sel", 28),
GATE_BDP0(CLK_BDP_NR_PXL, "nr_pxl", "nr_sel", 29),
GATE_BDP0(CLK_BDP_NR_DRAM, "nr_dram", "mm_sel", 30),
GATE_BDP0(CLK_BDP_NR_B, "nr_bclk", "mm_sel", 31),
GATE_BDP1(CLK_BDP_RX_F, "rx_fclk", "hadds2_fbclk", 0),
GATE_BDP1(CLK_BDP_RX_X, "rx_xclk", "clk26m", 1),
GATE_BDP1(CLK_BDP_RXPDT, "rxpdtclk", "hdmi_0_pix340m", 2),
GATE_BDP1(CLK_BDP_RX_CSCL_N, "rx_cscl_n", "clk26m", 3),
GATE_BDP1(CLK_BDP_RX_CSCL, "rx_cscl", "clk26m", 4),
GATE_BDP1(CLK_BDP_RX_DDCSCL_N, "rx_ddcscl_n", "hdmi_scl_rx", 5),
GATE_BDP1(CLK_BDP_RX_DDCSCL, "rx_ddcscl", "hdmi_scl_rx", 6),
GATE_BDP1(CLK_BDP_RX_VCO, "rx_vcoclk", "hadds2pll_294m", 7),
GATE_BDP1(CLK_BDP_RX_DP, "rx_dpclk", "hdmi_0_pll340m", 8),
GATE_BDP1(CLK_BDP_RX_P, "rx_pclk", "hdmi_0_pll340m", 9),
GATE_BDP1(CLK_BDP_RX_M, "rx_mclk", "hadds2pll_294m", 10),
GATE_BDP1(CLK_BDP_RX_PLL, "rx_pllclk", "hdmi_0_pix340m", 11),
GATE_BDP1(CLK_BDP_BRG_RT_B, "brg_rt_bclk", "mm_sel", 12),
GATE_BDP1(CLK_BDP_BRG_RT_DRAM, "brg_rt_dram", "mm_sel", 13),
GATE_BDP1(CLK_BDP_LARBRT_DRAM, "larbrt_dram", "mm_sel", 14),
GATE_BDP1(CLK_BDP_TMDS_SYN, "tmds_syn", "hdmi_0_pll340m", 15),
GATE_BDP1(CLK_BDP_HDMI_MON, "hdmi_mon", "hdmi_0_pll340m", 16),
};
static const struct mtk_clk_desc bdp_desc = {
.clks = bdp_clks,
.num_clks = ARRAY_SIZE(bdp_clks),
};
static const struct of_device_id of_match_clk_mt2701_bdp[] = {
{
.compatible = "mediatek,mt2701-bdpsys",
.data = &bdp_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_bdp);
static struct platform_driver clk_mt2701_bdp_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt2701-bdp",
.of_match_table = of_match_clk_mt2701_bdp,
},
};
module_platform_driver(clk_mt2701_bdp_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt2701-bdp.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8192-clk.h>
static const struct mtk_gate_regs aud0_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x0,
.sta_ofs = 0x0,
};
static const struct mtk_gate_regs aud1_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x4,
.sta_ofs = 0x4,
};
static const struct mtk_gate_regs aud2_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0x8,
.sta_ofs = 0x8,
};
#define GATE_AUD0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &aud0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
#define GATE_AUD1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &aud1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
#define GATE_AUD2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &aud2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate aud_clks[] = {
/* AUD0 */
GATE_AUD0(CLK_AUD_AFE, "aud_afe", "audio_sel", 2),
GATE_AUD0(CLK_AUD_22M, "aud_22m", "aud_engen1_sel", 8),
GATE_AUD0(CLK_AUD_24M, "aud_24m", "aud_engen2_sel", 9),
GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "aud_engen2_sel", 18),
GATE_AUD0(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "aud_engen1_sel", 19),
GATE_AUD0(CLK_AUD_TDM, "aud_tdm", "aud_1_sel", 20),
GATE_AUD0(CLK_AUD_ADC, "aud_adc", "audio_sel", 24),
GATE_AUD0(CLK_AUD_DAC, "aud_dac", "audio_sel", 25),
GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "audio_sel", 26),
GATE_AUD0(CLK_AUD_TML, "aud_tml", "audio_sel", 27),
GATE_AUD0(CLK_AUD_NLE, "aud_nle", "audio_sel", 28),
/* AUD1 */
GATE_AUD1(CLK_AUD_I2S1_B, "aud_i2s1_b", "audio_sel", 4),
GATE_AUD1(CLK_AUD_I2S2_B, "aud_i2s2_b", "audio_sel", 5),
GATE_AUD1(CLK_AUD_I2S3_B, "aud_i2s3_b", "audio_sel", 6),
GATE_AUD1(CLK_AUD_I2S4_B, "aud_i2s4_b", "audio_sel", 7),
GATE_AUD1(CLK_AUD_CONNSYS_I2S_ASRC, "aud_connsys_i2s_asrc", "audio_sel", 12),
GATE_AUD1(CLK_AUD_GENERAL1_ASRC, "aud_general1_asrc", "audio_sel", 13),
GATE_AUD1(CLK_AUD_GENERAL2_ASRC, "aud_general2_asrc", "audio_sel", 14),
GATE_AUD1(CLK_AUD_DAC_HIRES, "aud_dac_hires", "audio_h_sel", 15),
GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires", "audio_h_sel", 16),
GATE_AUD1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml", "audio_h_sel", 17),
GATE_AUD1(CLK_AUD_ADDA6_ADC, "aud_adda6_adc", "audio_sel", 20),
GATE_AUD1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires", "audio_h_sel", 21),
GATE_AUD1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "audio_sel", 28),
GATE_AUD1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis", "audio_sel", 29),
GATE_AUD1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml", "audio_sel", 30),
GATE_AUD1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires", "audio_h_sel", 31),
/* AUD2 */
GATE_AUD2(CLK_AUD_I2S5_B, "aud_i2s5_b", "audio_sel", 0),
GATE_AUD2(CLK_AUD_I2S6_B, "aud_i2s6_b", "audio_sel", 1),
GATE_AUD2(CLK_AUD_I2S7_B, "aud_i2s7_b", "audio_sel", 2),
GATE_AUD2(CLK_AUD_I2S8_B, "aud_i2s8_b", "audio_sel", 3),
GATE_AUD2(CLK_AUD_I2S9_B, "aud_i2s9_b", "audio_sel", 4),
};
static const struct mtk_clk_desc aud_desc = {
.clks = aud_clks,
.num_clks = ARRAY_SIZE(aud_clks),
};
static int clk_mt8192_aud_probe(struct platform_device *pdev)
{
int r;
r = mtk_clk_simple_probe(pdev);
if (r)
return r;
r = devm_of_platform_populate(&pdev->dev);
if (r)
mtk_clk_simple_remove(pdev);
return r;
}
static void clk_mt8192_aud_remove(struct platform_device *pdev)
{
of_platform_depopulate(&pdev->dev);
mtk_clk_simple_remove(pdev);
}
static const struct of_device_id of_match_clk_mt8192_aud[] = {
{ .compatible = "mediatek,mt8192-audsys", .data = &aud_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_aud);
static struct platform_driver clk_mt8192_aud_drv = {
.probe = clk_mt8192_aud_probe,
.remove_new = clk_mt8192_aud_remove,
.driver = {
.name = "clk-mt8192-aud",
.of_match_table = of_match_clk_mt8192_aud,
},
};
module_platform_driver(clk_mt8192_aud_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8192-aud.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 Collabora Ltd.
* Author: AngeloGioacchino Del Regno <[email protected]>
*/
#include <dt-bindings/clock/mediatek,mt6795-clk.h>
#include <dt-bindings/reset/mediatek,mt6795-resets.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "clk-cpumux.h"
#include "clk-gate.h"
#include "clk-mtk.h"
#include "reset.h"
#define GATE_ICG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra_cg_regs, \
_shift, &mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate_regs infra_cg_regs = {
.set_ofs = 0x0040,
.clr_ofs = 0x0044,
.sta_ofs = 0x0048,
};
static const char * const ca53_c0_parents[] = {
"clk26m",
"armca53pll",
"mainpll",
"univpll"
};
static const char * const ca53_c1_parents[] = {
"clk26m",
"armca53pll",
"mainpll",
"univpll"
};
static const struct mtk_composite cpu_muxes[] = {
MUX(CLK_INFRA_CA53_C0_SEL, "infra_ca53_c0_sel", ca53_c0_parents, 0x00, 0, 2),
MUX(CLK_INFRA_CA53_C1_SEL, "infra_ca53_c1_sel", ca53_c1_parents, 0x00, 2, 2),
};
static const struct mtk_gate infra_gates[] = {
GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1),
GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5),
GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7),
GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
GATE_ICG(CLK_INFRA_MD1MCU, "infra_md1mcu", "clk26m", 9),
GATE_ICG(CLK_INFRA_MD1BUS, "infra_md1bus", "axi_sel", 10),
GATE_ICG(CLK_INFRA_MD1DBB, "infra_dbb", "axi_sel", 11),
GATE_ICG(CLK_INFRA_DEVICE_APC, "infra_devapc", "clk26m", 12),
GATE_ICG(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 13),
GATE_ICG(CLK_INFRA_MD1LTE, "infra_md1lte", "axi_sel", 14),
GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "cpum_ck", 15),
GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
};
static u16 infra_ao_rst_ofs[] = { 0x30, 0x34 };
static u16 infra_ao_idx_map[] = {
[MT6795_INFRA_RST0_SCPSYS_RST] = 0 * RST_NR_PER_BANK + 5,
[MT6795_INFRA_RST0_PMIC_WRAP_RST] = 0 * RST_NR_PER_BANK + 7,
[MT6795_INFRA_RST1_MIPI_DSI_RST] = 1 * RST_NR_PER_BANK + 4,
[MT6795_INFRA_RST1_MIPI_CSI_RST] = 1 * RST_NR_PER_BANK + 7,
[MT6795_INFRA_RST1_MM_IOMMU_RST] = 1 * RST_NR_PER_BANK + 15,
};
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SET_CLR,
.rst_bank_ofs = infra_ao_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
.rst_idx_map = infra_ao_idx_map,
.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
};
static const struct of_device_id of_match_clk_mt6795_infracfg[] = {
{ .compatible = "mediatek,mt6795-infracfg" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_infracfg);
static int clk_mt6795_infracfg_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
void __iomem *base;
int ret;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
if (!clk_data)
return -ENOMEM;
ret = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
if (ret)
goto free_clk_data;
ret = mtk_clk_register_gates(&pdev->dev, node, infra_gates,
ARRAY_SIZE(infra_gates), clk_data);
if (ret)
goto free_clk_data;
ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes,
ARRAY_SIZE(cpu_muxes), clk_data);
if (ret)
goto unregister_gates;
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (ret)
goto unregister_cpumuxes;
return 0;
unregister_cpumuxes:
mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
unregister_gates:
mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data);
free_clk_data:
mtk_free_clk_data(clk_data);
return ret;
}
static void clk_mt6795_infracfg_remove(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
of_clk_del_provider(node);
mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data);
mtk_free_clk_data(clk_data);
}
static struct platform_driver clk_mt6795_infracfg_drv = {
.driver = {
.name = "clk-mt6795-infracfg",
.of_match_table = of_match_clk_mt6795_infracfg,
},
.probe = clk_mt6795_infracfg_probe,
.remove_new = clk_mt6795_infracfg_remove,
};
module_platform_driver(clk_mt6795_infracfg_drv);
MODULE_DESCRIPTION("MediaTek MT6795 infracfg clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6795-infracfg.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 MediaTek Inc.
*/
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs vdec0_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x4,
.sta_ofs = 0x0,
};
static const struct mtk_gate_regs vdec1_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0xc,
.sta_ofs = 0x8,
};
#define GATE_VDEC0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr_inv)
#define GATE_VDEC1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate vdec_clks[] = {
/* VDEC0 */
GATE_VDEC0(CLK_VDEC_VDEC, "vdec_fvdec_ck", "mm_sel", 0),
/* VDEC1 */
GATE_VDEC1(CLK_VDEC_LARB1, "vdec_flarb1_ck", "mm_sel", 0),
};
static const struct mtk_clk_desc vdec_desc = {
.clks = vdec_clks,
.num_clks = ARRAY_SIZE(vdec_clks),
};
static const struct of_device_id of_match_clk_mt8365_vdec[] = {
{
.compatible = "mediatek,mt8365-vdecsys",
.data = &vdec_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_vdec);
static struct platform_driver clk_mt8365_vdec_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8365-vdec",
.of_match_table = of_match_clk_mt8365_vdec,
},
};
module_platform_driver(clk_mt8365_vdec_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8365-vdec.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Garmin Chang <[email protected]>
*/
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs peri_ao_cg_regs = {
.set_ofs = 0x10,
.clr_ofs = 0x14,
.sta_ofs = 0x18,
};
#define GATE_PERI_AO(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &peri_ao_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate peri_ao_clks[] = {
GATE_PERI_AO(CLK_PERI_AO_ETHERNET, "peri_ao_ethernet", "top_axi", 0),
GATE_PERI_AO(CLK_PERI_AO_ETHERNET_BUS, "peri_ao_ethernet_bus", "top_axi", 1),
GATE_PERI_AO(CLK_PERI_AO_FLASHIF_BUS, "peri_ao_flashif_bus", "top_axi", 3),
GATE_PERI_AO(CLK_PERI_AO_FLASHIF_26M, "peri_ao_flashif_26m", "clk26m", 4),
GATE_PERI_AO(CLK_PERI_AO_FLASHIFLASHCK, "peri_ao_flashiflashck", "top_spinor", 5),
GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_BUS, "peri_ao_ssusb_2p_bus", "top_usb_top_2p", 9),
GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_XHCI, "peri_ao_ssusb_2p_xhci", "top_ssusb_xhci_2p", 10),
GATE_PERI_AO(CLK_PERI_AO_SSUSB_3P_BUS, "peri_ao_ssusb_3p_bus", "top_usb_top_3p", 11),
GATE_PERI_AO(CLK_PERI_AO_SSUSB_3P_XHCI, "peri_ao_ssusb_3p_xhci", "top_ssusb_xhci_3p", 12),
GATE_PERI_AO(CLK_PERI_AO_SSUSB_BUS, "peri_ao_ssusb_bus", "top_usb_top", 13),
GATE_PERI_AO(CLK_PERI_AO_SSUSB_XHCI, "peri_ao_ssusb_xhci", "top_ssusb_xhci", 14),
GATE_PERI_AO(CLK_PERI_AO_ETHERNET_MAC, "peri_ao_ethernet_mac_clk", "top_snps_eth_250m", 16),
GATE_PERI_AO(CLK_PERI_AO_PCIE_P0_FMEM, "peri_ao_pcie_p0_fmem", "hd_466m_fmem_ck", 24),
};
static const struct mtk_clk_desc peri_ao_desc = {
.clks = peri_ao_clks,
.num_clks = ARRAY_SIZE(peri_ao_clks),
};
static const struct of_device_id of_match_clk_mt8188_peri_ao[] = {
{ .compatible = "mediatek,mt8188-pericfg-ao", .data = &peri_ao_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_peri_ao);
static struct platform_driver clk_mt8188_peri_ao_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8188-peri_ao",
.of_match_table = of_match_clk_mt8188_peri_ao,
},
};
module_platform_driver(clk_mt8188_peri_ao_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8188-peri_ao.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 MediaTek Inc.
* Weiyi Lu <[email protected]>
* Copyright (c) 2023 Collabora Ltd.
* AngeloGioacchino Del Regno <[email protected]>
*/
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "clk-pll.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt2712-clk.h>
#define MT2712_PLL_FMAX (3000UL * MHZ)
#define CON0_MT2712_RST_BAR BIT(24)
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
_tuner_en_bit, _pcw_reg, _pcw_shift, \
_div_table) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = _en_mask, \
.flags = _flags, \
.rst_bar_mask = CON0_MT2712_RST_BAR, \
.fmax = MT2712_PLL_FMAX, \
.pcwbits = _pcwbits, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, \
.tuner_en_reg = _tuner_en_reg, \
.tuner_en_bit = _tuner_en_bit, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
.div_table = _div_table, \
}
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
_tuner_en_bit, _pcw_reg, _pcw_shift) \
PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
_pcwbits, _pd_reg, _pd_shift, _tuner_reg, \
_tuner_en_reg, _tuner_en_bit, _pcw_reg, \
_pcw_shift, NULL)
static const struct mtk_pll_div_table armca35pll_div_table[] = {
{ .div = 0, .freq = MT2712_PLL_FMAX },
{ .div = 1, .freq = 1202500000 },
{ .div = 2, .freq = 500500000 },
{ .div = 3, .freq = 315250000 },
{ .div = 4, .freq = 157625000 },
{ /* sentinel */ }
};
static const struct mtk_pll_div_table armca72pll_div_table[] = {
{ .div = 0, .freq = MT2712_PLL_FMAX },
{ .div = 1, .freq = 994500000 },
{ .div = 2, .freq = 520000000 },
{ .div = 3, .freq = 315250000 },
{ .div = 4, .freq = 157625000 },
{ /* sentinel */ }
};
static const struct mtk_pll_div_table mmpll_div_table[] = {
{ .div = 0, .freq = MT2712_PLL_FMAX },
{ .div = 1, .freq = 1001000000 },
{ .div = 2, .freq = 601250000 },
{ .div = 3, .freq = 250250000 },
{ .div = 4, .freq = 125125000 },
{ /* sentinel */ }
};
static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100,
HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100,
HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000100,
0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100,
0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100,
0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100,
0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000100,
0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000100,
0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100,
0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000100,
0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000100,
0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000100,
0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0, mmpll_div_table),
PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000100,
HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0, armca35pll_div_table),
PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000100,
0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0, armca72pll_div_table),
PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000100,
0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
};
static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
if (!clk_data)
return -ENOMEM;
r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
if (r)
goto free_clk_data;
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
dev_err(&pdev->dev, "Cannot register clock provider: %d\n", r);
goto unregister_plls;
}
return 0;
unregister_plls:
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
free_clk_data:
mtk_free_clk_data(clk_data);
return r;
}
static void clk_mt2712_apmixed_remove(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
of_clk_del_provider(node);
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
mtk_free_clk_data(clk_data);
}
static const struct of_device_id of_match_clk_mt2712_apmixed[] = {
{ .compatible = "mediatek,mt2712-apmixedsys" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_apmixed);
static struct platform_driver clk_mt2712_apmixed_drv = {
.probe = clk_mt2712_apmixed_probe,
.remove_new = clk_mt2712_apmixed_remove,
.driver = {
.name = "clk-mt2712-apmixed",
.of_match_table = of_match_clk_mt2712_apmixed,
},
};
module_platform_driver(clk_mt2712_apmixed_drv)
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt2712-apmixedsys.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {
.set_ofs = 0xe08,
.clr_ofs = 0xe04,
.sta_ofs = 0xe00,
};
#define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift) \
GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
static const struct mtk_gate imp_iic_wrap_s_clks[] = {
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C5, "imp_iic_wrap_s_i2c5", "top_i2c", 0),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C6, "imp_iic_wrap_s_i2c6", "top_i2c", 1),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C7, "imp_iic_wrap_s_i2c7", "top_i2c", 2),
};
static const struct mtk_gate imp_iic_wrap_w_clks[] = {
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C0, "imp_iic_wrap_w_i2c0", "top_i2c", 0),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C1, "imp_iic_wrap_w_i2c1", "top_i2c", 1),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C2, "imp_iic_wrap_w_i2c2", "top_i2c", 2),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C3, "imp_iic_wrap_w_i2c3", "top_i2c", 3),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C4, "imp_iic_wrap_w_i2c4", "top_i2c", 4),
};
static const struct mtk_clk_desc imp_iic_wrap_s_desc = {
.clks = imp_iic_wrap_s_clks,
.num_clks = ARRAY_SIZE(imp_iic_wrap_s_clks),
};
static const struct mtk_clk_desc imp_iic_wrap_w_desc = {
.clks = imp_iic_wrap_w_clks,
.num_clks = ARRAY_SIZE(imp_iic_wrap_w_clks),
};
static const struct of_device_id of_match_clk_mt8195_imp_iic_wrap[] = {
{
.compatible = "mediatek,mt8195-imp_iic_wrap_s",
.data = &imp_iic_wrap_s_desc,
}, {
.compatible = "mediatek,mt8195-imp_iic_wrap_w",
.data = &imp_iic_wrap_w_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_imp_iic_wrap);
static struct platform_driver clk_mt8195_imp_iic_wrap_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8195-imp_iic_wrap",
.of_match_table = of_match_clk_mt8195_imp_iic_wrap,
},
};
module_platform_driver(clk_mt8195_imp_iic_wrap_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Wendell Lin <[email protected]>
*/
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt6779-clk.h>
static const struct mtk_gate_regs mfg_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_MFG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr)
static const struct mtk_gate mfg_clks[] = {
GATE_MFG(CLK_MFGCFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
};
static const struct mtk_clk_desc mfg_desc = {
.clks = mfg_clks,
.num_clks = ARRAY_SIZE(mfg_clks),
};
static const struct of_device_id of_match_clk_mt6779_mfg[] = {
{
.compatible = "mediatek,mt6779-mfgcfg",
.data = &mfg_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_mfg);
static struct platform_driver clk_mt6779_mfg_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt6779-mfg",
.of_match_table = of_match_clk_mt6779_mfg,
},
};
module_platform_driver(clk_mt6779_mfg_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6779-mfg.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs vdec0_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x4,
.sta_ofs = 0x0,
};
static const struct mtk_gate_regs vdec1_cg_regs = {
.set_ofs = 0x200,
.clr_ofs = 0x204,
.sta_ofs = 0x200,
};
static const struct mtk_gate_regs vdec2_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0xc,
.sta_ofs = 0x8,
};
#define GATE_VDEC0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
#define GATE_VDEC1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
#define GATE_VDEC2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate vdec_clks[] = {
/* VDEC0 */
GATE_VDEC0(CLK_VDEC_VDEC, "vdec_vdec", "top_vdec", 0),
/* VDEC1 */
GATE_VDEC1(CLK_VDEC_LAT, "vdec_lat", "top_vdec", 0),
/* VDEC2 */
GATE_VDEC2(CLK_VDEC_LARB1, "vdec_larb1", "top_vdec", 0),
};
static const struct mtk_gate vdec_core1_clks[] = {
/* VDEC0 */
GATE_VDEC0(CLK_VDEC_CORE1_VDEC, "vdec_core1_vdec", "top_vdec", 0),
/* VDEC1 */
GATE_VDEC1(CLK_VDEC_CORE1_LAT, "vdec_core1_lat", "top_vdec", 0),
/* VDEC2 */
GATE_VDEC2(CLK_VDEC_CORE1_LARB1, "vdec_core1_larb1", "top_vdec", 0),
};
static const struct mtk_gate vdec_soc_clks[] = {
/* VDEC0 */
GATE_VDEC0(CLK_VDEC_SOC_VDEC, "vdec_soc_vdec", "top_vdec", 0),
/* VDEC1 */
GATE_VDEC1(CLK_VDEC_SOC_LAT, "vdec_soc_lat", "top_vdec", 0),
/* VDEC2 */
GATE_VDEC2(CLK_VDEC_SOC_LARB1, "vdec_soc_larb1", "top_vdec", 0),
};
static const struct mtk_clk_desc vdec_desc = {
.clks = vdec_clks,
.num_clks = ARRAY_SIZE(vdec_clks),
};
static const struct mtk_clk_desc vdec_core1_desc = {
.clks = vdec_core1_clks,
.num_clks = ARRAY_SIZE(vdec_core1_clks),
};
static const struct mtk_clk_desc vdec_soc_desc = {
.clks = vdec_soc_clks,
.num_clks = ARRAY_SIZE(vdec_soc_clks),
};
static const struct of_device_id of_match_clk_mt8195_vdec[] = {
{
.compatible = "mediatek,mt8195-vdecsys",
.data = &vdec_desc,
}, {
.compatible = "mediatek,mt8195-vdecsys_core1",
.data = &vdec_core1_desc,
}, {
.compatible = "mediatek,mt8195-vdecsys_soc",
.data = &vdec_soc_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_vdec);
static struct platform_driver clk_mt8195_vdec_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8195-vdec",
.of_match_table = of_match_clk_mt8195_vdec,
},
};
module_platform_driver(clk_mt8195_vdec_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8195-vdec.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2018 MediaTek Inc.
// Author: Weiyi Lu <[email protected]>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8183-clk.h>
static const struct mtk_gate_regs cam_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_CAM(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr)
static const struct mtk_gate cam_clks[] = {
GATE_CAM(CLK_CAM_LARB6, "cam_larb6", "cam_sel", 0),
GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "cam_sel", 1),
GATE_CAM(CLK_CAM_LARB3, "cam_larb3", "cam_sel", 2),
GATE_CAM(CLK_CAM_CAM, "cam_cam", "cam_sel", 6),
GATE_CAM(CLK_CAM_CAMTG, "cam_camtg", "cam_sel", 7),
GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "cam_sel", 8),
GATE_CAM(CLK_CAM_CAMSV0, "cam_camsv0", "cam_sel", 9),
GATE_CAM(CLK_CAM_CAMSV1, "cam_camsv1", "cam_sel", 10),
GATE_CAM(CLK_CAM_CAMSV2, "cam_camsv2", "cam_sel", 11),
GATE_CAM(CLK_CAM_CCU, "cam_ccu", "cam_sel", 12),
};
static const struct mtk_clk_desc cam_desc = {
.clks = cam_clks,
.num_clks = ARRAY_SIZE(cam_clks),
};
static const struct of_device_id of_match_clk_mt8183_cam[] = {
{
.compatible = "mediatek,mt8183-camsys",
.data = &cam_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_cam);
static struct platform_driver clk_mt8183_cam_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8183-cam",
.of_match_table = of_match_clk_mt8183_cam,
},
};
module_platform_driver(clk_mt8183_cam_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8183-cam.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Garmin Chang <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {
.set_ofs = 0xe08,
.clr_ofs = 0xe04,
.sta_ofs = 0xe00,
};
#define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift) \
GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
static const struct mtk_gate imp_iic_wrap_c_clks[] = {
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0,
"imp_iic_wrap_c_ap_clock_i2c0", "top_i2c", 0),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2,
"imp_iic_wrap_c_ap_clock_i2c2", "top_i2c", 1),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3,
"imp_iic_wrap_c_ap_clock_i2c3", "top_i2c", 2),
};
static const struct mtk_gate imp_iic_wrap_w_clks[] = {
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1,
"imp_iic_wrap_w_ap_clock_i2c1", "top_i2c", 0),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4,
"imp_iic_wrap_w_ap_clock_i2c4", "top_i2c", 1),
};
static const struct mtk_gate imp_iic_wrap_en_clks[] = {
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5,
"imp_iic_wrap_en_ap_clock_i2c5", "top_i2c", 0),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6,
"imp_iic_wrap_en_ap_clock_i2c6", "top_i2c", 1),
};
static const struct mtk_clk_desc imp_iic_wrap_c_desc = {
.clks = imp_iic_wrap_c_clks,
.num_clks = ARRAY_SIZE(imp_iic_wrap_c_clks),
};
static const struct mtk_clk_desc imp_iic_wrap_w_desc = {
.clks = imp_iic_wrap_w_clks,
.num_clks = ARRAY_SIZE(imp_iic_wrap_w_clks),
};
static const struct mtk_clk_desc imp_iic_wrap_en_desc = {
.clks = imp_iic_wrap_en_clks,
.num_clks = ARRAY_SIZE(imp_iic_wrap_en_clks),
};
static const struct of_device_id of_match_clk_mt8188_imp_iic_wrap[] = {
{ .compatible = "mediatek,mt8188-imp-iic-wrap-c", .data = &imp_iic_wrap_c_desc },
{ .compatible = "mediatek,mt8188-imp-iic-wrap-w", .data = &imp_iic_wrap_w_desc },
{ .compatible = "mediatek,mt8188-imp-iic-wrap-en", .data = &imp_iic_wrap_en_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_imp_iic_wrap);
static struct platform_driver clk_mt8188_imp_iic_wrap_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8188-imp_iic_wrap",
.of_match_table = of_match_clk_mt8188_imp_iic_wrap,
},
};
module_platform_driver(clk_mt8188_imp_iic_wrap_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8188-imp_iic_wrap.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Weiyi Lu <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt2712-clk.h>
static const struct mtk_gate_regs mfg_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_MFG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate mfg_clks[] = {
GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
};
static const struct mtk_clk_desc mfg_desc = {
.clks = mfg_clks,
.num_clks = ARRAY_SIZE(mfg_clks),
};
static const struct of_device_id of_match_clk_mt2712_mfg[] = {
{
.compatible = "mediatek,mt2712-mfgcfg",
.data = &mfg_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_mfg);
static struct platform_driver clk_mt2712_mfg_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt2712-mfg",
.of_match_table = of_match_clk_mt2712_mfg,
},
};
module_platform_driver(clk_mt2712_mfg_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt2712-mfg.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 Collabora Ltd.
* Author: AngeloGioacchino Del Regno <[email protected]>
*/
#include <dt-bindings/clock/mediatek,mt6795-clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "clk-fhctl.h"
#include "clk-mtk.h"
#include "clk-pll.h"
#include "clk-pllfh.h"
#define REG_REF2USB 0x8
#define REG_AP_PLL_CON7 0x1c
#define MD1_MTCMOS_OFF BIT(0)
#define MD1_MEM_OFF BIT(1)
#define MD1_CLK_OFF BIT(4)
#define MD1_ISO_OFF BIT(8)
#define MT6795_PLL_FMAX (3000UL * MHZ)
#define MT6795_CON0_EN BIT(0)
#define MT6795_CON0_RST_BAR BIT(24)
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = MT6795_CON0_EN | _en_mask, \
.flags = _flags, \
.rst_bar_mask = MT6795_CON0_RST_BAR, \
.fmax = MT6795_PLL_FMAX, \
.pcwbits = _pcwbits, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
.div_table = NULL, \
.pll_en_bit = 0, \
}
static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_ARMCA53PLL, "armca53pll", 0x200, 0x20c, 0, PLL_AO,
21, 0x204, 24, 0x0, 0x204, 0),
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR,
21, 0x220, 4, 0x0, 0x224, 0),
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000101, HAVE_RST_BAR,
7, 0x230, 4, 0x0, 0x234, 14),
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0, 0x244, 0),
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0),
PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0),
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0),
PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x284, 0),
PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0, 0, 21, 0x290, 4, 0x0, 0x294, 0),
PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a8, 0x2a4, 0),
PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2bc, 0x2b8, 0),
};
enum fh_pll_id {
FH_CA53PLL_LL,
FH_CA53PLL_BL,
FH_MAINPLL,
FH_MPLL,
FH_MSDCPLL,
FH_MMPLL,
FH_VENCPLL,
FH_TVDPLL,
FH_VCODECPLL,
FH_NR_FH,
};
#define _FH(_pllid, _fhid, _slope, _offset) { \
.data = { \
.pll_id = _pllid, \
.fh_id = _fhid, \
.fh_ver = FHCTL_PLLFH_V1, \
.fhx_offset = _offset, \
.dds_mask = GENMASK(21, 0), \
.slope0_value = _slope, \
.slope1_value = _slope, \
.sfstrx_en = BIT(2), \
.frddsx_en = BIT(1), \
.fhctlx_en = BIT(0), \
.tgl_org = BIT(31), \
.dvfs_tri = BIT(31), \
.pcwchg = BIT(31), \
.dt_val = 0x0, \
.df_val = 0x9, \
.updnlmt_shft = 16, \
.msk_frddsx_dys = GENMASK(23, 20), \
.msk_frddsx_dts = GENMASK(19, 16), \
}, \
}
#define FH(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6003c97, _offset)
#define FH_M(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6000140, _offset)
static struct mtk_pllfh_data pllfhs[] = {
FH(CLK_APMIXED_ARMCA53PLL, FH_CA53PLL_BL, 0x38),
FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x60),
FH_M(CLK_APMIXED_MPLL, FH_MPLL, 0x74),
FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x88),
FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x9c),
FH(CLK_APMIXED_VENCPLL, FH_VENCPLL, 0xb0),
FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0xc4),
FH(CLK_APMIXED_VCODECPLL, FH_VCODECPLL, 0xd8),
};
static void clk_mt6795_apmixed_setup_md1(void __iomem *base)
{
void __iomem *reg = base + REG_AP_PLL_CON7;
/* Turn on MD1 internal clock */
writel(readl(reg) & ~MD1_CLK_OFF, reg);
/* Unlock MD1's MTCMOS power path */
writel(readl(reg) & ~MD1_MTCMOS_OFF, reg);
/* Turn on ISO */
writel(readl(reg) & ~MD1_ISO_OFF, reg);
/* Turn on memory */
writel(readl(reg) & ~MD1_MEM_OFF, reg);
}
static const struct of_device_id of_match_clk_mt6795_apmixed[] = {
{ .compatible = "mediatek,mt6795-apmixedsys" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_apmixed);
static int clk_mt6795_apmixed_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
const u8 *fhctl_node = "mediatek,mt6795-fhctl";
void __iomem *base;
struct clk_hw *hw;
int ret;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
if (!clk_data)
return -ENOMEM;
fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
ret = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (ret)
goto free_clk_data;
hw = mtk_clk_register_ref2usb_tx("ref2usb_tx", "clk26m", base + REG_REF2USB);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
dev_err(dev, "Failed to register ref2usb_tx: %d\n", ret);
goto unregister_plls;
}
clk_data->hws[CLK_APMIXED_REF2USB_TX] = hw;
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (ret) {
dev_err(dev, "Cannot register clock provider: %d\n", ret);
goto unregister_ref2usb;
}
/* Setup MD1 to avoid random crashes */
dev_dbg(dev, "Performing initial setup for MD1\n");
clk_mt6795_apmixed_setup_md1(base);
return 0;
unregister_ref2usb:
mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
unregister_plls:
mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
ARRAY_SIZE(pllfhs), clk_data);
free_clk_data:
mtk_free_clk_data(clk_data);
return ret;
}
static void clk_mt6795_apmixed_remove(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
of_clk_del_provider(node);
mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
ARRAY_SIZE(pllfhs), clk_data);
mtk_free_clk_data(clk_data);
}
static struct platform_driver clk_mt6795_apmixed_drv = {
.probe = clk_mt6795_apmixed_probe,
.remove_new = clk_mt6795_apmixed_remove,
.driver = {
.name = "clk-mt6795-apmixed",
.of_match_table = of_match_clk_mt6795_apmixed,
},
};
module_platform_driver(clk_mt6795_apmixed_drv);
MODULE_DESCRIPTION("MediaTek MT6795 apmixed clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6795-apmixedsys.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt8186-clk.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs img_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_IMG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate img1_clks[] = {
GATE_IMG(CLK_IMG1_LARB9_IMG1, "img1_larb9_img1", "top_img1", 0),
GATE_IMG(CLK_IMG1_LARB10_IMG1, "img1_larb10_img1", "top_img1", 1),
GATE_IMG(CLK_IMG1_DIP, "img1_dip", "top_img1", 2),
GATE_IMG(CLK_IMG1_GALS_IMG1, "img1_gals_img1", "top_img1", 12),
};
static const struct mtk_gate img2_clks[] = {
GATE_IMG(CLK_IMG2_LARB9_IMG2, "img2_larb9_img2", "top_img1", 0),
GATE_IMG(CLK_IMG2_LARB10_IMG2, "img2_larb10_img2", "top_img1", 1),
GATE_IMG(CLK_IMG2_MFB, "img2_mfb", "top_img1", 6),
GATE_IMG(CLK_IMG2_WPE, "img2_wpe", "top_img1", 7),
GATE_IMG(CLK_IMG2_MSS, "img2_mss", "top_img1", 8),
GATE_IMG(CLK_IMG2_GALS_IMG2, "img2_gals_img2", "top_img1", 12),
};
static const struct mtk_clk_desc img1_desc = {
.clks = img1_clks,
.num_clks = ARRAY_SIZE(img1_clks),
};
static const struct mtk_clk_desc img2_desc = {
.clks = img2_clks,
.num_clks = ARRAY_SIZE(img2_clks),
};
static const struct of_device_id of_match_clk_mt8186_img[] = {
{
.compatible = "mediatek,mt8186-imgsys1",
.data = &img1_desc,
}, {
.compatible = "mediatek,mt8186-imgsys2",
.data = &img2_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_img);
static struct platform_driver clk_mt8186_img_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8186-img",
.of_match_table = of_match_clk_mt8186_img,
},
};
module_platform_driver(clk_mt8186_img_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8186-img.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8192-clk.h>
static const struct mtk_gate_regs ipe_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_IPE(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate ipe_clks[] = {
GATE_IPE(CLK_IPE_LARB19, "ipe_larb19", "ipe_sel", 0),
GATE_IPE(CLK_IPE_LARB20, "ipe_larb20", "ipe_sel", 1),
GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "ipe_sel", 2),
GATE_IPE(CLK_IPE_FD, "ipe_fd", "ipe_sel", 3),
GATE_IPE(CLK_IPE_FE, "ipe_fe", "ipe_sel", 4),
GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "ipe_sel", 5),
GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "ipe_sel", 6),
GATE_IPE(CLK_IPE_GALS, "ipe_gals", "ipe_sel", 8),
};
static const struct mtk_clk_desc ipe_desc = {
.clks = ipe_clks,
.num_clks = ARRAY_SIZE(ipe_clks),
};
static const struct of_device_id of_match_clk_mt8192_ipe[] = {
{
.compatible = "mediatek,mt8192-ipesys",
.data = &ipe_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_ipe);
static struct platform_driver clk_mt8192_ipe_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8192-ipe",
.of_match_table = of_match_clk_mt8192_ipe,
},
};
module_platform_driver(clk_mt8192_ipe_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8192-ipe.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 MediaTek Inc.
* Author: Owen Chen <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt6765-clk.h>
static const struct mtk_gate_regs venc_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_VENC(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate venc_clks[] = {
GATE_VENC(CLK_VENC_SET0_LARB, "venc_set0_larb", "mm_ck", 0),
GATE_VENC(CLK_VENC_SET1_VENC, "venc_set1_venc", "mm_ck", 4),
GATE_VENC(CLK_VENC_SET2_JPGENC, "jpgenc", "mm_ck", 8),
GATE_VENC(CLK_VENC_SET3_VDEC, "venc_set3_vdec", "mm_ck", 12),
};
static const struct mtk_clk_desc venc_desc = {
.clks = venc_clks,
.num_clks = ARRAY_SIZE(venc_clks),
};
static const struct of_device_id of_match_clk_mt6765_vcodec[] = {
{
.compatible = "mediatek,mt6765-vcodecsys",
.data = &venc_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_vcodec);
static struct platform_driver clk_mt6765_vcodec_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt6765-vcodec",
.of_match_table = of_match_clk_mt6765_vcodec,
},
};
module_platform_driver(clk_mt6765_vcodec_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6765-vcodec.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* Copyright (c) 2022 Collabora Ltd.
* Author: AngeloGioacchino Del Regno <[email protected]>
*/
#include <dt-bindings/clock/mt8173-clk.h>
#include <linux/of_address.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "clk-fhctl.h"
#include "clk-mtk.h"
#include "clk-pll.h"
#include "clk-pllfh.h"
#define REGOFF_REF2USB 0x8
#define REGOFF_HDMI_REF 0x40
#define MT8173_PLL_FMAX (3000UL * MHZ)
#define CON0_MT8173_RST_BAR BIT(24)
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
_pcw_shift, _div_table) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = _en_mask, \
.flags = _flags, \
.rst_bar_mask = CON0_MT8173_RST_BAR, \
.fmax = MT8173_PLL_FMAX, \
.pcwbits = _pcwbits, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
.div_table = _div_table, \
}
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
_pcw_shift) \
PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
NULL)
static const struct mtk_pll_div_table mmpll_div_table[] = {
{ .div = 0, .freq = MT8173_PLL_FMAX },
{ .div = 1, .freq = 1000000000 },
{ .div = 2, .freq = 702000000 },
{ .div = 3, .freq = 253500000 },
{ .div = 4, .freq = 126750000 },
{ } /* sentinel */
};
static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, PLL_AO,
21, 0x204, 24, 0x0, 0x204, 0),
PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, PLL_AO,
21, 0x214, 24, 0x0, 0x214, 0),
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BAR, 21,
0x220, 4, 0x0, 0x224, 0),
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000, HAVE_RST_BAR, 7,
0x230, 4, 0x0, 0x234, 14),
PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0,
0x244, 0, mmpll_div_table),
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0),
PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0),
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0),
PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x284, 0),
PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0, 0, 21, 0x290, 4, 0x0, 0x294, 0),
PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0),
PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0),
PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0, 0, 21, 0x2d0, 4, 0x0, 0x2d4, 0),
PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0),
};
enum fh_pll_id {
FH_ARMCA7PLL,
FH_ARMCA15PLL,
FH_MAINPLL,
FH_MPLL,
FH_MSDCPLL,
FH_MMPLL,
FH_VENCPLL,
FH_TVDPLL,
FH_VCODECPLL,
FH_LVDSPLL,
FH_MSDC2PLL,
FH_NR_FH,
};
#define FH(_pllid, _fhid, _offset) { \
.data = { \
.pll_id = _pllid, \
.fh_id = _fhid, \
.fh_ver = FHCTL_PLLFH_V1, \
.fhx_offset = _offset, \
.dds_mask = GENMASK(21, 0), \
.slope0_value = 0x6003c97, \
.slope1_value = 0x6003c97, \
.sfstrx_en = BIT(2), \
.frddsx_en = BIT(1), \
.fhctlx_en = BIT(0), \
.tgl_org = BIT(31), \
.dvfs_tri = BIT(31), \
.pcwchg = BIT(31), \
.dt_val = 0x0, \
.df_val = 0x9, \
.updnlmt_shft = 16, \
.msk_frddsx_dys = GENMASK(23, 20), \
.msk_frddsx_dts = GENMASK(19, 16), \
}, \
}
static struct mtk_pllfh_data pllfhs[] = {
FH(CLK_APMIXED_ARMCA7PLL, FH_ARMCA7PLL, 0x38),
FH(CLK_APMIXED_ARMCA15PLL, FH_ARMCA15PLL, 0x4c),
FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x60),
FH(CLK_APMIXED_MPLL, FH_MPLL, 0x74),
FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x88),
FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x9c),
FH(CLK_APMIXED_VENCPLL, FH_VENCPLL, 0xb0),
FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0xc4),
FH(CLK_APMIXED_VCODECPLL, FH_VCODECPLL, 0xd8),
FH(CLK_APMIXED_LVDSPLL, FH_LVDSPLL, 0xec),
FH(CLK_APMIXED_MSDCPLL2, FH_MSDC2PLL, 0x100),
};
static const struct of_device_id of_match_clk_mt8173_apmixed[] = {
{ .compatible = "mediatek,mt8173-apmixedsys" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_apmixed);
static int clk_mt8173_apmixed_probe(struct platform_device *pdev)
{
const u8 *fhctl_node = "mediatek,mt8173-fhctl";
struct device_node *node = pdev->dev.of_node;
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
struct clk_hw *hw;
int r;
base = of_iomap(node, 0);
if (!base)
return -ENOMEM;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
if (IS_ERR_OR_NULL(clk_data)) {
iounmap(base);
return -ENOMEM;
}
fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (r)
goto free_clk_data;
hw = mtk_clk_register_ref2usb_tx("ref2usb_tx", "clk26m", base + REGOFF_REF2USB);
if (IS_ERR(hw)) {
r = PTR_ERR(hw);
dev_err(&pdev->dev, "Failed to register ref2usb_tx: %d\n", r);
goto unregister_plls;
}
clk_data->hws[CLK_APMIXED_REF2USB_TX] = hw;
hw = devm_clk_hw_register_divider(&pdev->dev, "hdmi_ref", "tvdpll_594m", 0,
base + REGOFF_HDMI_REF, 16, 3,
CLK_DIVIDER_POWER_OF_TWO, NULL);
clk_data->hws[CLK_APMIXED_HDMI_REF] = hw;
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_ref2usb;
return 0;
unregister_ref2usb:
mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
unregister_plls:
mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
ARRAY_SIZE(pllfhs), clk_data);
free_clk_data:
mtk_free_clk_data(clk_data);
iounmap(base);
return r;
}
static void clk_mt8173_apmixed_remove(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
of_clk_del_provider(node);
mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
ARRAY_SIZE(pllfhs), clk_data);
mtk_free_clk_data(clk_data);
}
static struct platform_driver clk_mt8173_apmixed_drv = {
.probe = clk_mt8173_apmixed_probe,
.remove_new = clk_mt8173_apmixed_remove,
.driver = {
.name = "clk-mt8173-apmixed",
.of_match_table = of_match_clk_mt8173_apmixed,
},
};
module_platform_driver(clk_mt8173_apmixed_drv);
MODULE_DESCRIPTION("MediaTek MT8173 apmixed clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8173-apmixedsys.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Wendell Lin <[email protected]>
*/
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt6779-clk.h>
static const struct mtk_gate_regs vdec0_cg_regs = {
.set_ofs = 0x0000,
.clr_ofs = 0x0004,
.sta_ofs = 0x0000,
};
static const struct mtk_gate_regs vdec1_cg_regs = {
.set_ofs = 0x0008,
.clr_ofs = 0x000c,
.sta_ofs = 0x0008,
};
#define GATE_VDEC0_I(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr_inv)
#define GATE_VDEC1_I(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate vdec_clks[] = {
/* VDEC0 */
GATE_VDEC0_I(CLK_VDEC_VDEC, "vdec_cken", "vdec_sel", 0),
/* VDEC1 */
GATE_VDEC1_I(CLK_VDEC_LARB1, "vdec_larb1_cken", "vdec_sel", 0),
};
static const struct mtk_clk_desc vdec_desc = {
.clks = vdec_clks,
.num_clks = ARRAY_SIZE(vdec_clks),
};
static const struct of_device_id of_match_clk_mt6779_vdec[] = {
{
.compatible = "mediatek,mt6779-vdecsys",
.data = &vdec_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_vdec);
static struct platform_driver clk_mt6779_vdec_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt6779-vdec",
.of_match_table = of_match_clk_mt6779_vdec,
},
};
module_platform_driver(clk_mt6779_vdec_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6779-vdec.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs vdo0_0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs vdo0_1_cg_regs = {
.set_ofs = 0x114,
.clr_ofs = 0x118,
.sta_ofs = 0x110,
};
static const struct mtk_gate_regs vdo0_2_cg_regs = {
.set_ofs = 0x124,
.clr_ofs = 0x128,
.sta_ofs = 0x120,
};
#define GATE_VDO0_0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO0_1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO0_2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags) \
GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flags)
static const struct mtk_gate vdo0_clks[] = {
/* VDO0_0 */
GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "top_vpp", 0),
GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0", "top_vpp", 2),
GATE_VDO0_0(CLK_VDO0_DISP_COLOR1, "vdo0_disp_color1", "top_vpp", 3),
GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0", "top_vpp", 4),
GATE_VDO0_0(CLK_VDO0_DISP_CCORR1, "vdo0_disp_ccorr1", "top_vpp", 5),
GATE_VDO0_0(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0", "top_vpp", 6),
GATE_VDO0_0(CLK_VDO0_DISP_AAL1, "vdo0_disp_aal1", "top_vpp", 7),
GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0", "top_vpp", 8),
GATE_VDO0_0(CLK_VDO0_DISP_GAMMA1, "vdo0_disp_gamma1", "top_vpp", 9),
GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0", "top_vpp", 10),
GATE_VDO0_0(CLK_VDO0_DISP_DITHER1, "vdo0_disp_dither1", "top_vpp", 11),
GATE_VDO0_0(CLK_VDO0_DISP_OVL1, "vdo0_disp_ovl1", "top_vpp", 16),
GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0", "top_vpp", 17),
GATE_VDO0_0(CLK_VDO0_DISP_WDMA1, "vdo0_disp_wdma1", "top_vpp", 18),
GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0", "top_vpp", 19),
GATE_VDO0_0(CLK_VDO0_DISP_RDMA1, "vdo0_disp_rdma1", "top_vpp", 20),
GATE_VDO0_0(CLK_VDO0_DSI0, "vdo0_dsi0", "top_vpp", 21),
GATE_VDO0_0(CLK_VDO0_DSI1, "vdo0_dsi1", "top_vpp", 22),
GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0", "top_vpp", 23),
GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0", "top_vpp", 24),
GATE_VDO0_0(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0", "top_vpp", 25),
GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0", "top_vpp", 26),
GATE_VDO0_0(CLK_VDO0_DISP_IL_ROT0, "vdo0_disp_il_rot0", "top_vpp", 27),
GATE_VDO0_0(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "top_vpp", 28),
GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0", "top_vpp", 29),
GATE_VDO0_0(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1", "top_vpp", 30),
/* VDO0_1 */
GATE_VDO0_1(CLK_VDO0_DL_ASYNC0, "vdo0_dl_async0", "top_vpp", 0),
GATE_VDO0_1(CLK_VDO0_DL_ASYNC1, "vdo0_dl_async1", "top_vpp", 1),
GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2", "top_vpp", 2),
GATE_VDO0_1(CLK_VDO0_DL_ASYNC3, "vdo0_dl_async3", "top_vpp", 3),
GATE_VDO0_1(CLK_VDO0_DL_ASYNC4, "vdo0_dl_async4", "top_vpp", 4),
GATE_VDO0_1(CLK_VDO0_DISP_MONITOR0, "vdo0_disp_monitor0", "top_vpp", 5),
GATE_VDO0_1(CLK_VDO0_DISP_MONITOR1, "vdo0_disp_monitor1", "top_vpp", 6),
GATE_VDO0_1(CLK_VDO0_DISP_MONITOR2, "vdo0_disp_monitor2", "top_vpp", 7),
GATE_VDO0_1(CLK_VDO0_DISP_MONITOR3, "vdo0_disp_monitor3", "top_vpp", 8),
GATE_VDO0_1(CLK_VDO0_DISP_MONITOR4, "vdo0_disp_monitor4", "top_vpp", 9),
GATE_VDO0_1(CLK_VDO0_SMI_GALS, "vdo0_smi_gals", "top_vpp", 10),
GATE_VDO0_1(CLK_VDO0_SMI_COMMON, "vdo0_smi_common", "top_vpp", 11),
GATE_VDO0_1(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "top_vpp", 12),
GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu", "top_vpp", 13),
GATE_VDO0_1(CLK_VDO0_SMI_LARB, "vdo0_smi_larb", "top_vpp", 14),
GATE_VDO0_1(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "top_vpp", 15),
/* VDO0_2 */
GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "top_dsi_occ", 0),
GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "top_dsi_occ", 8),
GATE_VDO0_2_FLAGS(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf",
"top_edp", 16, CLK_SET_RATE_PARENT),
};
static const struct mtk_clk_desc vdo0_desc = {
.clks = vdo0_clks,
.num_clks = ARRAY_SIZE(vdo0_clks),
};
static const struct platform_device_id clk_mt8195_vdo0_id_table[] = {
{ .name = "clk-mt8195-vdo0", .driver_data = (kernel_ulong_t)&vdo0_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, clk_mt8195_vdo0_id_table);
static struct platform_driver clk_mt8195_vdo0_drv = {
.probe = mtk_clk_pdev_probe,
.remove_new = mtk_clk_pdev_remove,
.driver = {
.name = "clk-mt8195-vdo0",
},
.id_table = clk_mt8195_vdo0_id_table,
};
module_platform_driver(clk_mt8195_vdo0_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8195-vdo0.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 MediaTek Inc.
* Copyright (c) 2020 BayLibre, SAS
* Author: James Liao <[email protected]>
* Fabien Parent <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8167-clk.h>
static const struct mtk_gate_regs mm0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs mm1_cg_regs = {
.set_ofs = 0x114,
.clr_ofs = 0x118,
.sta_ofs = 0x110,
};
#define GATE_MM0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_MM1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate mm_clks[] = {
/* MM0 */
GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "smi_mm", 0),
GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "smi_mm", 1),
GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "smi_mm", 2),
GATE_MM0(CLK_MM_MDP_RDMA, "mm_mdp_rdma", "smi_mm", 3),
GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "smi_mm", 4),
GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "smi_mm", 5),
GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "smi_mm", 6),
GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "smi_mm", 7),
GATE_MM0(CLK_MM_MDP_WROT, "mm_mdp_wrot", "smi_mm", 8),
GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "smi_mm", 9),
GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "smi_mm", 10),
GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "smi_mm", 11),
GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "smi_mm", 12),
GATE_MM0(CLK_MM_DISP_WDMA, "mm_disp_wdma", "smi_mm", 13),
GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color", "smi_mm", 14),
GATE_MM0(CLK_MM_DISP_CCORR, "mm_disp_ccorr", "smi_mm", 15),
GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "smi_mm", 16),
GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "smi_mm", 17),
GATE_MM0(CLK_MM_DISP_DITHER, "mm_disp_dither", "smi_mm", 18),
GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "smi_mm", 19),
/* MM1 */
GATE_MM1(CLK_MM_DISP_PWM_MM, "mm_disp_pwm_mm", "smi_mm", 0),
GATE_MM1(CLK_MM_DISP_PWM_26M, "mm_disp_pwm_26m", "smi_mm", 1),
GATE_MM1(CLK_MM_DSI_ENGINE, "mm_dsi_engine", "smi_mm", 2),
GATE_MM1(CLK_MM_DSI_DIGITAL, "mm_dsi_digital", "dsi0_lntc_dsick", 3),
GATE_MM1(CLK_MM_DPI0_ENGINE, "mm_dpi0_engine", "smi_mm", 4),
GATE_MM1(CLK_MM_DPI0_PXL, "mm_dpi0_pxl", "rg_fdpi0", 5),
GATE_MM1(CLK_MM_LVDS_PXL, "mm_lvds_pxl", "vpll_dpix", 14),
GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx_dig_cts", 15),
GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "smi_mm", 16),
GATE_MM1(CLK_MM_DPI1_PXL, "mm_dpi1_pxl", "rg_fdpi1", 17),
GATE_MM1(CLK_MM_HDMI_PXL, "mm_hdmi_pxl", "rg_fdpi1", 18),
GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll12_div6", 19),
GATE_MM1(CLK_MM_HDMI_ADSP_BCK, "mm_hdmi_adsp_b", "apll12_div4b", 20),
GATE_MM1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmtx_dig_cts", 21),
};
static const struct mtk_clk_desc mm_desc = {
.clks = mm_clks,
.num_clks = ARRAY_SIZE(mm_clks),
};
static const struct platform_device_id clk_mt8167_mm_id_table[] = {
{ .name = "clk-mt8167-mm", .driver_data = (kernel_ulong_t)&mm_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, clk_mt8167_mm_id_table);
static struct platform_driver clk_mt8167_mm_drv = {
.probe = mtk_clk_pdev_probe,
.remove_new = mtk_clk_pdev_remove,
.driver = {
.name = "clk-mt8167-mm",
},
.id_table = clk_mt8167_mm_id_table,
};
module_platform_driver(clk_mt8167_mm_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8167-mm.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 MediaTek Inc.
* Copyright (c) 2020 BayLibre, SAS
* Author: James Liao <[email protected]>
* Fabien Parent <[email protected]>
*/
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/mfd/syscon.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8167-clk.h>
static DEFINE_SPINLOCK(mt8167_clk_lock);
static const struct mtk_fixed_clk fixed_clks[] = {
FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, "i2s_infra_bck", "clk_null", 26000000),
FIXED_CLK(CLK_TOP_MEMPLL, "mempll", "clk26m", 800000000),
FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, "dsi0_lntc_dsick", "clk26m", 75000000),
FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", "clk26m", 75000000),
FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx_dig_cts", "clk26m", 52500000),
};
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D8, "mainpll_d8", "mainpll", 1, 8),
FACTOR(CLK_TOP_MAINPLL_D16, "mainpll_d16", "mainpll", 1, 16),
FACTOR(CLK_TOP_MAINPLL_D11, "mainpll_d11", "mainpll", 1, 11),
FACTOR(CLK_TOP_MAINPLL_D22, "mainpll_d22", "mainpll", 1, 22),
FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
FACTOR(CLK_TOP_MAINPLL_D12, "mainpll_d12", "mainpll", 1, 12),
FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
FACTOR(CLK_TOP_MAINPLL_D10, "mainpll_d10", "mainpll", 1, 10),
FACTOR(CLK_TOP_MAINPLL_D20, "mainpll_d20", "mainpll", 1, 20),
FACTOR(CLK_TOP_MAINPLL_D40, "mainpll_d40", "mainpll", 1, 40),
FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
FACTOR(CLK_TOP_MAINPLL_D14, "mainpll_d14", "mainpll", 1, 14),
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D8, "univpll_d8", "univpll", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D16, "univpll_d16", "univpll", 1, 16),
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
FACTOR(CLK_TOP_UNIVPLL_D12, "univpll_d12", "univpll", 1, 12),
FACTOR(CLK_TOP_UNIVPLL_D24, "univpll_d24", "univpll", 1, 24),
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
FACTOR(CLK_TOP_UNIVPLL_D20, "univpll_d20", "univpll", 1, 20),
FACTOR(CLK_TOP_MMPLL380M, "mmpll380m", "mmpll", 1, 1),
FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
FACTOR(CLK_TOP_MMPLL_200M, "mmpll_200m", "mmpll", 1, 3),
FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1, 1),
FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "rg_apll1_d2_en", 1, 2),
FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "rg_apll1_d4_en", 1, 2),
FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2),
FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "rg_apll2_d2_en", 1, 2),
FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "rg_apll2_d4_en", 1, 2),
FACTOR(CLK_TOP_CLK26M, "clk26m_ck", "clk26m", 1, 1),
FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
FACTOR(CLK_TOP_MIPI_26M, "mipi_26m", "clk26m", 1, 1),
FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4),
FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8),
FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_ck", 1, 16),
FACTOR(CLK_TOP_AHB_INFRA_D2, "ahb_infra_d2", "ahb_infra_sel", 1, 2),
FACTOR(CLK_TOP_NFI1X, "nfi1x_ck", "nfi2x_pad_sel", 1, 2),
FACTOR(CLK_TOP_ETH_D2, "eth_d2_ck", "eth_sel", 1, 2),
};
static const char * const uart0_parents[] = {
"clk26m_ck",
"univpll_d24"
};
static const char * const gfmux_emi1x_parents[] = {
"clk26m_ck",
"dmpll_ck"
};
static const char * const emi_ddrphy_parents[] = {
"gfmux_emi1x_sel",
"gfmux_emi1x_sel"
};
static const char * const ahb_infra_parents[] = {
"clk_null",
"clk26m_ck",
"mainpll_d11",
"clk_null",
"mainpll_d12",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"mainpll_d10"
};
static const char * const csw_mux_mfg_parents[] = {
"clk_null",
"clk_null",
"univpll_d3",
"univpll_d2",
"clk26m_ck",
"mainpll_d4",
"univpll_d24",
"mmpll380m"
};
static const char * const msdc0_parents[] = {
"clk26m_ck",
"univpll_d6",
"mainpll_d8",
"univpll_d8",
"mainpll_d16",
"mmpll_200m",
"mainpll_d12",
"mmpll_d2"
};
static const char * const camtg_mm_parents[] = {
"clk_null",
"clk26m_ck",
"usb_phy48m_ck",
"clk_null",
"univpll_d6"
};
static const char * const pwm_mm_parents[] = {
"clk26m_ck",
"univpll_d12"
};
static const char * const uart1_parents[] = {
"clk26m_ck",
"univpll_d24"
};
static const char * const msdc1_parents[] = {
"clk26m_ck",
"univpll_d6",
"mainpll_d8",
"univpll_d8",
"mainpll_d16",
"mmpll_200m",
"mainpll_d12",
"mmpll_d2"
};
static const char * const spm_52m_parents[] = {
"clk26m_ck",
"univpll_d24"
};
static const char * const pmicspi_parents[] = {
"univpll_d20",
"usb_phy48m_ck",
"univpll_d16",
"clk26m_ck"
};
static const char * const qaxi_aud26m_parents[] = {
"clk26m_ck",
"ahb_infra_sel"
};
static const char * const aud_intbus_parents[] = {
"clk_null",
"clk26m_ck",
"mainpll_d22",
"clk_null",
"mainpll_d11"
};
static const char * const nfi2x_pad_parents[] = {
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk26m_ck",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"mainpll_d12",
"mainpll_d8",
"clk_null",
"mainpll_d6",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"mainpll_d4",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"mainpll_d10",
"mainpll_d7",
"clk_null",
"mainpll_d5"
};
static const char * const nfi1x_pad_parents[] = {
"ahb_infra_sel",
"nfi1x_ck"
};
static const char * const mfg_mm_parents[] = {
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"csw_mux_mfg_sel",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"mainpll_d3",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"mainpll_d5",
"mainpll_d7",
"clk_null",
"mainpll_d14"
};
static const char * const ddrphycfg_parents[] = {
"clk26m_ck",
"mainpll_d16"
};
static const char * const smi_mm_parents[] = {
"clk26m_ck",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"univpll_d4",
"mainpll_d7",
"clk_null",
"mainpll_d14"
};
static const char * const usb_78m_parents[] = {
"clk_null",
"clk26m_ck",
"univpll_d16",
"clk_null",
"mainpll_d20"
};
static const char * const scam_mm_parents[] = {
"clk_null",
"clk26m_ck",
"mainpll_d14",
"clk_null",
"mainpll_d12"
};
static const char * const spinor_parents[] = {
"clk26m_d2",
"clk26m_ck",
"mainpll_d40",
"univpll_d24",
"univpll_d20",
"mainpll_d20",
"mainpll_d16",
"univpll_d12"
};
static const char * const msdc2_parents[] = {
"clk26m_ck",
"univpll_d6",
"mainpll_d8",
"univpll_d8",
"mainpll_d16",
"mmpll_200m",
"mainpll_d12",
"mmpll_d2"
};
static const char * const eth_parents[] = {
"clk26m_ck",
"mainpll_d40",
"univpll_d24",
"univpll_d20",
"mainpll_d20"
};
static const char * const vdec_mm_parents[] = {
"clk26m_ck",
"univpll_d4",
"mainpll_d4",
"univpll_d5",
"univpll_d6",
"mainpll_d6"
};
static const char * const dpi0_mm_parents[] = {
"clk26m_ck",
"lvdspll_ck",
"lvdspll_d2",
"lvdspll_d4",
"lvdspll_d8"
};
static const char * const dpi1_mm_parents[] = {
"clk26m_ck",
"tvdpll_d2",
"tvdpll_d4",
"tvdpll_d8",
"tvdpll_d16"
};
static const char * const axi_mfg_in_parents[] = {
"clk26m_ck",
"mainpll_d11",
"univpll_d24",
"mmpll380m"
};
static const char * const slow_mfg_parents[] = {
"clk26m_ck",
"univpll_d12",
"univpll_d24"
};
static const char * const aud1_parents[] = {
"clk26m_ck",
"apll1_ck"
};
static const char * const aud2_parents[] = {
"clk26m_ck",
"apll2_ck"
};
static const char * const aud_engen1_parents[] = {
"clk26m_ck",
"rg_apll1_d2_en",
"rg_apll1_d4_en",
"rg_apll1_d8_en"
};
static const char * const aud_engen2_parents[] = {
"clk26m_ck",
"rg_apll2_d2_en",
"rg_apll2_d4_en",
"rg_apll2_d8_en"
};
static const char * const i2c_parents[] = {
"clk26m_ck",
"univpll_d20",
"univpll_d16",
"univpll_d12"
};
static const char * const aud_i2s0_m_parents[] = {
"rg_aud1",
"rg_aud2"
};
static const char * const pwm_parents[] = {
"clk26m_ck",
"univpll_d12"
};
static const char * const spi_parents[] = {
"clk26m_ck",
"univpll_d12",
"univpll_d8",
"univpll_d6"
};
static const char * const aud_spdifin_parents[] = {
"clk26m_ck",
"univpll_d2"
};
static const char * const uart2_parents[] = {
"clk26m_ck",
"univpll_d24"
};
static const char * const bsi_parents[] = {
"clk26m_ck",
"mainpll_d10",
"mainpll_d12",
"mainpll_d20"
};
static const char * const dbg_atclk_parents[] = {
"clk_null",
"clk26m_ck",
"mainpll_d5",
"clk_null",
"univpll_d5"
};
static const char * const csw_nfiecc_parents[] = {
"clk_null",
"mainpll_d7",
"mainpll_d6",
"clk_null",
"mainpll_d5"
};
static const char * const nfiecc_parents[] = {
"clk_null",
"nfi2x_pad_sel",
"mainpll_d4",
"clk_null",
"csw_nfiecc_sel"
};
static struct mtk_composite top_muxes[] __initdata = {
/* CLK_MUX_SEL0 */
MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
0x000, 0, 1),
MUX(CLK_TOP_GFMUX_EMI1X_SEL, "gfmux_emi1x_sel", gfmux_emi1x_parents,
0x000, 1, 1),
MUX(CLK_TOP_EMI_DDRPHY_SEL, "emi_ddrphy_sel", emi_ddrphy_parents,
0x000, 2, 1),
MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents,
0x000, 4, 4),
MUX(CLK_TOP_CSW_MUX_MFG_SEL, "csw_mux_mfg_sel", csw_mux_mfg_parents,
0x000, 8, 3),
MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents,
0x000, 11, 3),
MUX(CLK_TOP_CAMTG_MM_SEL, "camtg_mm_sel", camtg_mm_parents,
0x000, 15, 3),
MUX(CLK_TOP_PWM_MM_SEL, "pwm_mm_sel", pwm_mm_parents,
0x000, 18, 1),
MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents,
0x000, 19, 1),
MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents,
0x000, 20, 3),
MUX(CLK_TOP_SPM_52M_SEL, "spm_52m_sel", spm_52m_parents,
0x000, 23, 1),
MUX(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
0x000, 24, 2),
MUX(CLK_TOP_QAXI_AUD26M_SEL, "qaxi_aud26m_sel", qaxi_aud26m_parents,
0x000, 26, 1),
MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
0x000, 27, 3),
/* CLK_MUX_SEL1 */
MUX(CLK_TOP_NFI2X_PAD_SEL, "nfi2x_pad_sel", nfi2x_pad_parents,
0x004, 0, 7),
MUX(CLK_TOP_NFI1X_PAD_SEL, "nfi1x_pad_sel", nfi1x_pad_parents,
0x004, 7, 1),
MUX(CLK_TOP_MFG_MM_SEL, "mfg_mm_sel", mfg_mm_parents,
0x004, 8, 6),
MUX(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
0x004, 15, 1),
MUX(CLK_TOP_SMI_MM_SEL, "smi_mm_sel", smi_mm_parents,
0x004, 16, 4),
MUX(CLK_TOP_USB_78M_SEL, "usb_78m_sel", usb_78m_parents,
0x004, 20, 3),
MUX(CLK_TOP_SCAM_MM_SEL, "scam_mm_sel", scam_mm_parents,
0x004, 23, 3),
/* CLK_MUX_SEL8 */
MUX(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents,
0x040, 0, 3),
MUX(CLK_TOP_MSDC2_SEL, "msdc2_sel", msdc2_parents,
0x040, 3, 3),
MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
0x040, 6, 3),
MUX(CLK_TOP_VDEC_MM_SEL, "vdec_mm_sel", vdec_mm_parents,
0x040, 9, 3),
MUX(CLK_TOP_DPI0_MM_SEL, "dpi0_mm_sel", dpi0_mm_parents,
0x040, 12, 3),
MUX(CLK_TOP_DPI1_MM_SEL, "dpi1_mm_sel", dpi1_mm_parents,
0x040, 15, 3),
MUX(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents,
0x040, 18, 2),
MUX(CLK_TOP_SLOW_MFG_SEL, "slow_mfg_sel", slow_mfg_parents,
0x040, 20, 2),
MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
0x040, 22, 1),
MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
0x040, 23, 1),
MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
0x040, 24, 2),
MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents,
0x040, 26, 2),
MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
0x040, 28, 2),
/* CLK_SEL_9 */
MUX(CLK_TOP_AUD_I2S0_M_SEL, "aud_i2s0_m_sel", aud_i2s0_m_parents,
0x044, 12, 1),
MUX(CLK_TOP_AUD_I2S1_M_SEL, "aud_i2s1_m_sel", aud_i2s0_m_parents,
0x044, 13, 1),
MUX(CLK_TOP_AUD_I2S2_M_SEL, "aud_i2s2_m_sel", aud_i2s0_m_parents,
0x044, 14, 1),
MUX(CLK_TOP_AUD_I2S3_M_SEL, "aud_i2s3_m_sel", aud_i2s0_m_parents,
0x044, 15, 1),
MUX(CLK_TOP_AUD_I2S4_M_SEL, "aud_i2s4_m_sel", aud_i2s0_m_parents,
0x044, 16, 1),
MUX(CLK_TOP_AUD_I2S5_M_SEL, "aud_i2s5_m_sel", aud_i2s0_m_parents,
0x044, 17, 1),
MUX(CLK_TOP_AUD_SPDIF_B_SEL, "aud_spdif_b_sel", aud_i2s0_m_parents,
0x044, 18, 1),
/* CLK_MUX_SEL13 */
MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
0x07c, 0, 1),
MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
0x07c, 1, 2),
MUX(CLK_TOP_AUD_SPDIFIN_SEL, "aud_spdifin_sel", aud_spdifin_parents,
0x07c, 3, 1),
MUX(CLK_TOP_UART2_SEL, "uart2_sel", uart2_parents,
0x07c, 4, 1),
MUX(CLK_TOP_BSI_SEL, "bsi_sel", bsi_parents,
0x07c, 5, 2),
MUX(CLK_TOP_DBG_ATCLK_SEL, "dbg_atclk_sel", dbg_atclk_parents,
0x07c, 7, 3),
MUX(CLK_TOP_CSW_NFIECC_SEL, "csw_nfiecc_sel", csw_nfiecc_parents,
0x07c, 10, 3),
MUX(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,
0x07c, 13, 3),
};
static const char * const ifr_mux1_parents[] = {
"clk26m_ck",
"armpll",
"univpll",
"mainpll_d2"
};
static const char * const ifr_eth_25m_parents[] = {
"eth_d2_ck",
"rg_eth"
};
static const char * const ifr_i2c0_parents[] = {
"ahb_infra_d2",
"rg_i2c"
};
static const struct mtk_composite ifr_muxes[] = {
MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000,
2, 2),
MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080,
0, 1),
MUX(CLK_IFR_I2C0_SEL, "ifr_i2c0_sel", ifr_i2c0_parents, 0x080,
1, 1),
MUX(CLK_IFR_I2C1_SEL, "ifr_i2c1_sel", ifr_i2c0_parents, 0x080,
2, 1),
MUX(CLK_IFR_I2C2_SEL, "ifr_i2c2_sel", ifr_i2c0_parents, 0x080,
3, 1),
};
#define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.div_reg = _reg, \
.div_shift = _shift, \
.div_width = _width, \
}
static const struct mtk_clk_divider top_adj_divs[] = {
DIV_ADJ(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "aud_i2s0_m_sel",
0x0048, 0, 8),
DIV_ADJ(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "aud_i2s1_m_sel",
0x0048, 8, 8),
DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel",
0x0048, 16, 8),
DIV_ADJ(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "aud_i2s3_m_sel",
0x0048, 24, 8),
DIV_ADJ(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "aud_i2s4_m_sel",
0x004c, 0, 8),
DIV_ADJ(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll12_div4",
0x004c, 8, 8),
DIV_ADJ(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "aud_i2s5_m_sel",
0x004c, 16, 8),
DIV_ADJ(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll12_div5",
0x004c, 24, 8),
DIV_ADJ(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "aud_spdif_b_sel",
0x0078, 0, 8),
};
static const struct mtk_gate_regs top0_cg_regs = {
.set_ofs = 0x50,
.clr_ofs = 0x80,
.sta_ofs = 0x20,
};
static const struct mtk_gate_regs top1_cg_regs = {
.set_ofs = 0x54,
.clr_ofs = 0x84,
.sta_ofs = 0x24,
};
static const struct mtk_gate_regs top2_cg_regs = {
.set_ofs = 0x6c,
.clr_ofs = 0x9c,
.sta_ofs = 0x3c,
};
static const struct mtk_gate_regs top3_cg_regs = {
.set_ofs = 0xa0,
.clr_ofs = 0xb0,
.sta_ofs = 0x70,
};
static const struct mtk_gate_regs top4_cg_regs = {
.set_ofs = 0xa4,
.clr_ofs = 0xb4,
.sta_ofs = 0x74,
};
static const struct mtk_gate_regs top5_cg_regs = {
.set_ofs = 0x44,
.clr_ofs = 0x44,
.sta_ofs = 0x44,
};
#define GATE_TOP0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_TOP0_I(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
#define GATE_TOP1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_TOP2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_TOP2_I(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
#define GATE_TOP3(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_TOP4_I(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top4_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
#define GATE_TOP5(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top5_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate top_clks[] = {
/* TOP0 */
GATE_TOP0(CLK_TOP_PWM_MM, "pwm_mm", "pwm_mm_sel", 0),
GATE_TOP0(CLK_TOP_CAM_MM, "cam_mm", "camtg_mm_sel", 1),
GATE_TOP0(CLK_TOP_MFG_MM, "mfg_mm", "mfg_mm_sel", 2),
GATE_TOP0(CLK_TOP_SPM_52M, "spm_52m", "spm_52m_sel", 3),
GATE_TOP0_I(CLK_TOP_MIPI_26M_DBG, "mipi_26m_dbg", "mipi_26m", 4),
GATE_TOP0(CLK_TOP_SCAM_MM, "scam_mm", "scam_mm_sel", 5),
GATE_TOP0(CLK_TOP_SMI_MM, "smi_mm", "smi_mm_sel", 9),
/* TOP1 */
GATE_TOP1(CLK_TOP_THEM, "them", "ahb_infra_sel", 1),
GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2),
GATE_TOP1(CLK_TOP_I2C0, "i2c0", "ifr_i2c0_sel", 3),
GATE_TOP1(CLK_TOP_I2C1, "i2c1", "ifr_i2c1_sel", 4),
GATE_TOP1(CLK_TOP_AUXADC1, "auxadc1", "ahb_infra_sel", 5),
GATE_TOP1(CLK_TOP_NFI, "nfi", "nfi1x_pad_sel", 6),
GATE_TOP1(CLK_TOP_NFIECC, "nfiecc", "rg_nfiecc", 7),
GATE_TOP1(CLK_TOP_DEBUGSYS, "debugsys", "rg_dbg_atclk", 8),
GATE_TOP1(CLK_TOP_PWM, "pwm", "ahb_infra_sel", 9),
GATE_TOP1(CLK_TOP_UART0, "uart0", "uart0_sel", 10),
GATE_TOP1(CLK_TOP_UART1, "uart1", "uart1_sel", 11),
GATE_TOP1(CLK_TOP_BTIF, "btif", "ahb_infra_sel", 12),
GATE_TOP1(CLK_TOP_USB, "usb", "usb_78m", 13),
GATE_TOP1(CLK_TOP_FLASHIF_26M, "flashif_26m", "clk26m_ck", 14),
GATE_TOP1(CLK_TOP_AUXADC2, "auxadc2", "ahb_infra_sel", 15),
GATE_TOP1(CLK_TOP_I2C2, "i2c2", "ifr_i2c2_sel", 16),
GATE_TOP1(CLK_TOP_MSDC0, "msdc0", "msdc0_sel", 17),
GATE_TOP1(CLK_TOP_MSDC1, "msdc1", "msdc1_sel", 18),
GATE_TOP1(CLK_TOP_NFI2X, "nfi2x", "nfi2x_pad_sel", 19),
GATE_TOP1(CLK_TOP_PMICWRAP_AP, "pwrap_ap", "clk26m_ck", 20),
GATE_TOP1(CLK_TOP_SEJ, "sej", "ahb_infra_sel", 21),
GATE_TOP1(CLK_TOP_MEMSLP_DLYER, "memslp_dlyer", "clk26m_ck", 22),
GATE_TOP1(CLK_TOP_SPI, "spi", "spi_sel", 23),
GATE_TOP1(CLK_TOP_APXGPT, "apxgpt", "clk26m_ck", 24),
GATE_TOP1(CLK_TOP_AUDIO, "audio", "clk26m_ck", 25),
GATE_TOP1(CLK_TOP_PMICWRAP_MD, "pwrap_md", "clk26m_ck", 27),
GATE_TOP1(CLK_TOP_PMICWRAP_CONN, "pwrap_conn", "clk26m_ck", 28),
GATE_TOP1(CLK_TOP_PMICWRAP_26M, "pwrap_26m", "clk26m_ck", 29),
GATE_TOP1(CLK_TOP_AUX_ADC, "aux_adc", "clk26m_ck", 30),
GATE_TOP1(CLK_TOP_AUX_TP, "aux_tp", "clk26m_ck", 31),
/* TOP2 */
GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0),
GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1),
GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2),
GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4),
GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5),
GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6),
GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7),
GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8),
GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9),
GATE_TOP2(CLK_TOP_PWM2_FB, "pwm2_fb", "rg_pwm_infra", 10),
GATE_TOP2(CLK_TOP_PWM3_FB, "pwm3_fb", "rg_pwm_infra", 11),
GATE_TOP2(CLK_TOP_PWM4_FB, "pwm4_fb", "rg_pwm_infra", 12),
GATE_TOP2(CLK_TOP_PWM5_FB, "pwm5_fb", "rg_pwm_infra", 13),
GATE_TOP2(CLK_TOP_USB_1P, "usb_1p", "usb_78m", 14),
GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, "flashif_freerun", "ahb_infra_sel",
15),
GATE_TOP2(CLK_TOP_26M_HDMI_SIFM, "hdmi_sifm_26m", "clk26m_ck", 16),
GATE_TOP2(CLK_TOP_26M_CEC, "cec_26m", "clk26m_ck", 17),
GATE_TOP2(CLK_TOP_32K_CEC, "cec_32k", "clk32k", 18),
GATE_TOP2(CLK_TOP_66M_ETH, "eth_66m", "ahb_infra_d2", 19),
GATE_TOP2(CLK_TOP_133M_ETH, "eth_133m", "ahb_infra_sel", 20),
GATE_TOP2(CLK_TOP_FETH_25M, "feth_25m", "ifr_eth_25m_sel", 21),
GATE_TOP2(CLK_TOP_FETH_50M, "feth_50m", "rg_eth", 22),
GATE_TOP2(CLK_TOP_FLASHIF_AXI, "flashif_axi", "ahb_infra_sel", 23),
GATE_TOP2(CLK_TOP_USBIF, "usbif", "ahb_infra_sel", 24),
GATE_TOP2(CLK_TOP_UART2, "uart2", "rg_uart2", 25),
GATE_TOP2(CLK_TOP_BSI, "bsi", "ahb_infra_sel", 26),
GATE_TOP2(CLK_TOP_GCPU_B, "gcpu_b", "ahb_infra_sel", 27),
GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, "msdc0_infra", "msdc0", 28),
GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, "msdc1_infra", "msdc1", 29),
GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, "msdc2_infra", "rg_msdc2", 30),
GATE_TOP2(CLK_TOP_USB_78M, "usb_78m", "usb_78m_sel", 31),
/* TOP3 */
GATE_TOP3(CLK_TOP_RG_SPINOR, "rg_spinor", "spinor_sel", 0),
GATE_TOP3(CLK_TOP_RG_MSDC2, "rg_msdc2", "msdc2_sel", 1),
GATE_TOP3(CLK_TOP_RG_ETH, "rg_eth", "eth_sel", 2),
GATE_TOP3(CLK_TOP_RG_VDEC, "rg_vdec", "vdec_mm_sel", 3),
GATE_TOP3(CLK_TOP_RG_FDPI0, "rg_fdpi0", "dpi0_mm_sel", 4),
GATE_TOP3(CLK_TOP_RG_FDPI1, "rg_fdpi1", "dpi1_mm_sel", 5),
GATE_TOP3(CLK_TOP_RG_AXI_MFG, "rg_axi_mfg", "axi_mfg_in_sel", 6),
GATE_TOP3(CLK_TOP_RG_SLOW_MFG, "rg_slow_mfg", "slow_mfg_sel", 7),
GATE_TOP3(CLK_TOP_RG_AUD1, "rg_aud1", "aud1_sel", 8),
GATE_TOP3(CLK_TOP_RG_AUD2, "rg_aud2", "aud2_sel", 9),
GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, "rg_aud_engen1", "aud_engen1_sel", 10),
GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, "rg_aud_engen2", "aud_engen2_sel", 11),
GATE_TOP3(CLK_TOP_RG_I2C, "rg_i2c", "i2c_sel", 12),
GATE_TOP3(CLK_TOP_RG_PWM_INFRA, "rg_pwm_infra", "pwm_sel", 13),
GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, "rg_aud_spdif_in", "aud_spdifin_sel",
14),
GATE_TOP3(CLK_TOP_RG_UART2, "rg_uart2", "uart2_sel", 15),
GATE_TOP3(CLK_TOP_RG_BSI, "rg_bsi", "bsi_sel", 16),
GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, "rg_dbg_atclk", "dbg_atclk_sel", 17),
GATE_TOP3(CLK_TOP_RG_NFIECC, "rg_nfiecc", "nfiecc_sel", 18),
/* TOP4 */
GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, "rg_apll1_d2_en", "apll1_d2", 8),
GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, "rg_apll1_d4_en", "apll1_d4", 9),
GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, "rg_apll1_d8_en", "apll1_d8", 10),
GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, "rg_apll2_d2_en", "apll2_d2", 11),
GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, "rg_apll2_d4_en", "apll2_d4", 12),
GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, "rg_apll2_d8_en", "apll2_d8", 13),
/* TOP5 */
GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0),
GATE_TOP5(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll12_ck_div1", 1),
GATE_TOP5(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll12_ck_div2", 2),
GATE_TOP5(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll12_ck_div3", 3),
GATE_TOP5(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll12_ck_div4", 4),
GATE_TOP5(CLK_TOP_APLL12_DIV4B, "apll12_div4b", "apll12_ck_div4b", 5),
GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6),
GATE_TOP5(CLK_TOP_APLL12_DIV5B, "apll12_div5b", "apll12_ck_div5b", 7),
GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8),
};
static const struct mtk_clk_desc topck_desc = {
.clks = top_clks,
.num_clks = ARRAY_SIZE(top_clks),
.fixed_clks = fixed_clks,
.num_fixed_clks = ARRAY_SIZE(fixed_clks),
.factor_clks = top_divs,
.num_factor_clks = ARRAY_SIZE(top_divs),
.composite_clks = top_muxes,
.num_composite_clks = ARRAY_SIZE(top_muxes),
.divider_clks = top_adj_divs,
.num_divider_clks = ARRAY_SIZE(top_adj_divs),
.clk_lock = &mt8167_clk_lock,
};
static const struct mtk_clk_desc infra_desc = {
.composite_clks = ifr_muxes,
.num_composite_clks = ARRAY_SIZE(ifr_muxes),
.clk_lock = &mt8167_clk_lock,
};
static const struct of_device_id of_match_clk_mt8167[] = {
{ .compatible = "mediatek,mt8167-topckgen", .data = &topck_desc },
{ .compatible = "mediatek,mt8167-infracfg", .data = &infra_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8167);
static struct platform_driver clk_mt8167_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8167",
.of_match_table = of_match_clk_mt8167,
},
};
module_platform_driver(clk_mt8167_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8167.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2018 MediaTek Inc.
// Author: Weiyi Lu <[email protected]>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8183-clk.h>
static const struct mtk_gate_regs mfg_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_MFG(_id, _name, _parent, _shift) \
GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT)
static const struct mtk_gate mfg_clks[] = {
GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0)
};
static const struct mtk_clk_desc mfg_desc = {
.clks = mfg_clks,
.num_clks = ARRAY_SIZE(mfg_clks),
};
static const struct of_device_id of_match_clk_mt8183_mfg[] = {
{
.compatible = "mediatek,mt8183-mfgcfg",
.data = &mfg_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_mfg);
static struct platform_driver clk_mt8183_mfg_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8183-mfg",
.of_match_table = of_match_clk_mt8183_mfg,
},
};
module_platform_driver(clk_mt8183_mfg_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8183-mfgcfg.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 MediaTek Inc.
* Author: Owen Chen <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt6765-clk.h>
static const struct mtk_gate_regs mm_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
#define GATE_MM(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate mm_clks[] = {
/* MM */
GATE_MM(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_ck", 0),
GATE_MM(CLK_MM_MDP_CCORR0, "mm_mdp_ccorr0", "mm_ck", 1),
GATE_MM(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_ck", 2),
GATE_MM(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_ck", 3),
GATE_MM(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_ck", 4),
GATE_MM(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_ck", 5),
GATE_MM(CLK_MM_MDP_WDMA0, "mm_mdp_wdma0", "mm_ck", 6),
GATE_MM(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_ck", 7),
GATE_MM(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_ck", 8),
GATE_MM(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "mm_ck", 9),
GATE_MM(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_ck", 10),
GATE_MM(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_ck", 11),
GATE_MM(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_ck", 12),
GATE_MM(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_ck", 13),
GATE_MM(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_ck", 14),
GATE_MM(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_ck", 15),
GATE_MM(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_ck", 16),
GATE_MM(CLK_MM_DSI0, "mm_dsi0", "mm_ck", 17),
GATE_MM(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_ck", 18),
GATE_MM(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_ck", 19),
GATE_MM(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_ck", 20),
GATE_MM(CLK_MM_SMI_COMM0, "mm_smi_comm0", "mm_ck", 21),
GATE_MM(CLK_MM_SMI_COMM1, "mm_smi_comm1", "mm_ck", 22),
GATE_MM(CLK_MM_CAM_MDP, "mm_cam_mdp_ck", "mm_ck", 23),
GATE_MM(CLK_MM_SMI_IMG, "mm_smi_img_ck", "mm_ck", 24),
GATE_MM(CLK_MM_SMI_CAM, "mm_smi_cam_ck", "mm_ck", 25),
GATE_MM(CLK_MM_IMG_DL_RELAY, "mm_img_dl_relay", "mm_ck", 26),
GATE_MM(CLK_MM_IMG_DL_ASYNC_TOP, "mm_imgdl_async", "mm_ck", 27),
GATE_MM(CLK_MM_DIG_DSI, "mm_dig_dsi_ck", "mm_ck", 28),
GATE_MM(CLK_MM_F26M_HRTWT, "mm_hrtwt", "f_f26m_ck", 29),
};
static const struct mtk_clk_desc mm_desc = {
.clks = mm_clks,
.num_clks = ARRAY_SIZE(mm_clks),
};
static const struct of_device_id of_match_clk_mt6765_mm[] = {
{
.compatible = "mediatek,mt6765-mmsys",
.data = &mm_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_mm);
static struct platform_driver clk_mt6765_mm_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt6765-mm",
.of_match_table = of_match_clk_mt6765_mm,
},
};
module_platform_driver(clk_mt6765_mm_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6765-mm.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 MediaTek Inc.
* Author: Owen Chen <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt6765-clk.h>
static const struct mtk_gate_regs img_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_IMG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate img_clks[] = {
GATE_IMG(CLK_IMG_LARB2, "img_larb2", "mm_ck", 0),
GATE_IMG(CLK_IMG_DIP, "img_dip", "mm_ck", 2),
GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_ck", 3),
GATE_IMG(CLK_IMG_DPE, "img_dpe", "mm_ck", 4),
GATE_IMG(CLK_IMG_RSC, "img_rsc", "mm_ck", 5),
};
static const struct mtk_clk_desc img_desc = {
.clks = img_clks,
.num_clks = ARRAY_SIZE(img_clks),
};
static const struct of_device_id of_match_clk_mt6765_img[] = {
{
.compatible = "mediatek,mt6765-imgsys",
.data = &img_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_img);
static struct platform_driver clk_mt6765_img_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt6765-img",
.of_match_table = of_match_clk_mt6765_img,
},
};
module_platform_driver(clk_mt6765_img_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6765-img.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Chen Zhong <[email protected]>
* Sean Wang <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-cpumux.h"
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt7622-clk.h>
#include <linux/clk.h> /* for consumer */
#define GATE_TOP0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
#define GATE_TOP1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
#define GATE_PERI0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_PERI0_AO(_id, _name, _parent, _shift) \
GATE_MTK_FLAGS(_id, _name, _parent, &peri0_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL)
#define GATE_PERI1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static DEFINE_SPINLOCK(mt7622_clk_lock);
static const char * const axi_parents[] = {
"clkxtal",
"syspll1_d2",
"syspll_d5",
"syspll1_d4",
"univpll_d5",
"univpll2_d2",
"univpll_d7"
};
static const char * const mem_parents[] = {
"clkxtal",
"dmpll_ck"
};
static const char * const ddrphycfg_parents[] = {
"clkxtal",
"syspll1_d8"
};
static const char * const eth_parents[] = {
"clkxtal",
"syspll1_d2",
"univpll1_d2",
"syspll1_d4",
"univpll_d5",
"clk_null",
"univpll_d7"
};
static const char * const pwm_parents[] = {
"clkxtal",
"univpll2_d4"
};
static const char * const f10m_ref_parents[] = {
"clkxtal",
"syspll4_d16"
};
static const char * const nfi_infra_parents[] = {
"clkxtal",
"clkxtal",
"clkxtal",
"clkxtal",
"clkxtal",
"clkxtal",
"clkxtal",
"clkxtal",
"univpll2_d8",
"syspll1_d8",
"univpll1_d8",
"syspll4_d2",
"univpll2_d4",
"univpll3_d2",
"syspll1_d4"
};
static const char * const flash_parents[] = {
"clkxtal",
"univpll_d80_d4",
"syspll2_d8",
"syspll3_d4",
"univpll3_d4",
"univpll1_d8",
"syspll2_d4",
"univpll2_d4"
};
static const char * const uart_parents[] = {
"clkxtal",
"univpll2_d8"
};
static const char * const spi0_parents[] = {
"clkxtal",
"syspll3_d2",
"clkxtal",
"syspll2_d4",
"syspll4_d2",
"univpll2_d4",
"univpll1_d8",
"clkxtal"
};
static const char * const spi1_parents[] = {
"clkxtal",
"syspll3_d2",
"clkxtal",
"syspll4_d4",
"syspll4_d2",
"univpll2_d4",
"univpll1_d8",
"clkxtal"
};
static const char * const msdc30_0_parents[] = {
"clkxtal",
"univpll2_d16",
"univ48m"
};
static const char * const a1sys_hp_parents[] = {
"clkxtal",
"aud1pll_ck",
"aud2pll_ck",
"clkxtal"
};
static const char * const intdir_parents[] = {
"clkxtal",
"syspll_d2",
"univpll_d2",
"sgmiipll_ck"
};
static const char * const aud_intbus_parents[] = {
"clkxtal",
"syspll1_d4",
"syspll4_d2",
"syspll3_d2"
};
static const char * const pmicspi_parents[] = {
"clkxtal",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"univpll2_d16"
};
static const char * const atb_parents[] = {
"clkxtal",
"syspll1_d2",
"syspll_d5"
};
static const char * const audio_parents[] = {
"clkxtal",
"syspll3_d4",
"syspll4_d4",
"univpll1_d16"
};
static const char * const usb20_parents[] = {
"clkxtal",
"univpll3_d4",
"syspll1_d8",
"clkxtal"
};
static const char * const aud1_parents[] = {
"clkxtal",
"aud1pll_ck"
};
static const char * const aud2_parents[] = {
"clkxtal",
"aud2pll_ck"
};
static const char * const asm_l_parents[] = {
"clkxtal",
"syspll_d5",
"univpll2_d2",
"univpll2_d4"
};
static const char * const apll1_ck_parents[] = {
"aud1_sel",
"aud2_sel"
};
static const char * const peribus_ck_parents[] = {
"syspll1_d8",
"syspll1_d4"
};
static const struct mtk_gate_regs top0_cg_regs = {
.set_ofs = 0x120,
.clr_ofs = 0x120,
.sta_ofs = 0x120,
};
static const struct mtk_gate_regs top1_cg_regs = {
.set_ofs = 0x128,
.clr_ofs = 0x128,
.sta_ofs = 0x128,
};
static const struct mtk_gate_regs peri0_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0x10,
.sta_ofs = 0x18,
};
static const struct mtk_gate_regs peri1_cg_regs = {
.set_ofs = 0xC,
.clr_ofs = 0x14,
.sta_ofs = 0x1C,
};
static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
31250000),
FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal",
31250000),
FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal",
125000000),
FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal",
125000000),
FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal",
250000000),
FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal",
250000000),
FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal",
33333333),
FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal",
50000000),
FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal",
50000000),
FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal",
50000000),
};
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1),
FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024),
FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1),
FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112),
FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
FACTOR(CLK_TOP_UNIVPLL1_D16, "univpll1_d16", "univpll", 1, 32),
FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48),
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80),
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320),
FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25),
FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck", "sgmipll", 1, 1),
FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2),
FACTOR(CLK_TOP_AUD1PLL, "aud1pll_ck", "aud1pll", 1, 1),
FACTOR(CLK_TOP_AUD2PLL, "aud2pll_ck", "aud2pll", 1, 1),
FACTOR(CLK_TOP_AUD_I2S2_MCK, "aud_i2s2_mck", "i2s2_mck_sel", 1, 2),
FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "univpll2_d4", 1, 4),
FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1),
FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1),
FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1),
};
static const struct mtk_gate top_clks[] = {
/* TOP0 */
GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0),
GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1),
GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div",
2),
GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div",
3),
GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div",
4),
GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div",
5),
/* TOP1 */
GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0),
GATE_TOP1(CLK_TOP_A2SYS_HP_DIV_PD, "a2sys_div_pd", "a2sys_div", 16),
};
static const struct mtk_clk_divider top_adj_divs[] = {
DIV_ADJ(CLK_TOP_APLL1_DIV, "apll1_ck_div", "apll1_ck_sel",
0x120, 24, 3),
DIV_ADJ(CLK_TOP_APLL2_DIV, "apll2_ck_div", "apll2_ck_sel",
0x120, 28, 3),
DIV_ADJ(CLK_TOP_I2S0_MCK_DIV, "i2s0_mck_div", "i2s0_mck_sel",
0x124, 0, 7),
DIV_ADJ(CLK_TOP_I2S1_MCK_DIV, "i2s1_mck_div", "i2s1_mck_sel",
0x124, 8, 7),
DIV_ADJ(CLK_TOP_I2S2_MCK_DIV, "i2s2_mck_div", "aud_i2s2_mck",
0x124, 16, 7),
DIV_ADJ(CLK_TOP_I2S3_MCK_DIV, "i2s3_mck_div", "i2s3_mck_sel",
0x124, 24, 7),
DIV_ADJ(CLK_TOP_A1SYS_HP_DIV, "a1sys_div", "a1sys_hp_sel",
0x128, 8, 7),
DIV_ADJ(CLK_TOP_A2SYS_HP_DIV, "a2sys_div", "a2sys_hp_sel",
0x128, 24, 7),
};
static const struct mtk_gate peri_clks[] = {
/* PERI0 */
GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1),
GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2),
GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3),
GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4),
GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5),
GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6),
GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7),
GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8),
GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9),
GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12),
GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13),
GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14),
GATE_PERI0_AO(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17),
GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18),
GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19),
GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20),
GATE_PERI0(CLK_PERI_UART4_PD, "peri_uart4_pd", "axi_sel", 21),
GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "axi_sel", 22),
GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "axi_sel", 23),
GATE_PERI0(CLK_PERI_I2C1_PD, "peri_i2c1_pd", "axi_sel", 24),
GATE_PERI0(CLK_PERI_I2C2_PD, "peri_i2c2_pd", "axi_sel", 25),
GATE_PERI0(CLK_PERI_SPI1_PD, "peri_spi1_pd", "spi1_sel", 26),
GATE_PERI0(CLK_PERI_AUXADC_PD, "peri_auxadc_pd", "clkxtal", 27),
GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi0_sel", 28),
GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "nfi_infra_sel", 29),
GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "axi_sel", 30),
GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "axi_sel", 31),
/* PERI1 */
GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash_sel", 1),
GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2),
};
static struct mtk_composite top_muxes[] = {
/* CLK_CFG_0 */
MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
0x040, 0, 3, 7, CLK_IS_CRITICAL),
MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
0x040, 8, 1, 15, CLK_IS_CRITICAL),
MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
0x040, 16, 1, 23, CLK_IS_CRITICAL),
MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
0x040, 24, 3, 31),
/* CLK_CFG_1 */
MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
0x050, 0, 2, 7),
MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
0x050, 8, 1, 15),
MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
0x050, 16, 4, 23),
MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
0x050, 24, 3, 31),
/* CLK_CFG_2 */
MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
0x060, 0, 1, 7),
MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
0x060, 8, 3, 15),
MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
0x060, 16, 3, 23),
MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
0x060, 24, 3, 31),
/* CLK_CFG_3 */
MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
0x070, 0, 3, 7),
MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents,
0x070, 8, 3, 15),
MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents,
0x070, 16, 2, 23),
MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a1sys_hp_parents,
0x070, 24, 2, 31),
/* CLK_CFG_4 */
MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
0x080, 0, 2, 7),
MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
0x080, 8, 2, 15),
MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
0x080, 16, 3, 23),
MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents,
0x080, 24, 2, 31),
/* CLK_CFG_5 */
MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
0x090, 0, 2, 7),
MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents,
0x090, 8, 3, 15),
MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
0x090, 16, 2, 23),
MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
0x090, 24, 2, 31),
/* CLK_CFG_6 */
MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
0x0A0, 0, 1, 7),
MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
0x0A0, 8, 1, 15),
MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", f10m_ref_parents,
0x0A0, 16, 1, 23),
MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents,
0x0A0, 24, 1, 31),
/* CLK_CFG_7 */
MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents,
0x0B0, 0, 2, 7),
MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents,
0x0B0, 8, 2, 15),
MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents,
0x0B0, 16, 2, 23),
/* CLK_AUDDIV_0 */
MUX(CLK_TOP_APLL1_SEL, "apll1_ck_sel", apll1_ck_parents,
0x120, 6, 1),
MUX(CLK_TOP_APLL2_SEL, "apll2_ck_sel", apll1_ck_parents,
0x120, 7, 1),
MUX(CLK_TOP_I2S0_MCK_SEL, "i2s0_mck_sel", apll1_ck_parents,
0x120, 8, 1),
MUX(CLK_TOP_I2S1_MCK_SEL, "i2s1_mck_sel", apll1_ck_parents,
0x120, 9, 1),
MUX(CLK_TOP_I2S2_MCK_SEL, "i2s2_mck_sel", apll1_ck_parents,
0x120, 10, 1),
MUX(CLK_TOP_I2S3_MCK_SEL, "i2s3_mck_sel", apll1_ck_parents,
0x120, 11, 1),
};
static struct mtk_composite peri_muxes[] = {
/* PERI_GLOBALCON_CKSEL */
MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
};
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SIMPLE,
.rst_bank_ofs = pericfg_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
};
static const struct mtk_clk_desc topck_desc = {
.clks = top_clks,
.num_clks = ARRAY_SIZE(top_clks),
.fixed_clks = top_fixed_clks,
.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
.factor_clks = top_divs,
.num_factor_clks = ARRAY_SIZE(top_divs),
.composite_clks = top_muxes,
.num_composite_clks = ARRAY_SIZE(top_muxes),
.divider_clks = top_adj_divs,
.num_divider_clks = ARRAY_SIZE(top_adj_divs),
.clk_lock = &mt7622_clk_lock,
};
static const struct mtk_clk_desc peri_desc = {
.clks = peri_clks,
.num_clks = ARRAY_SIZE(peri_clks),
.composite_clks = peri_muxes,
.num_composite_clks = ARRAY_SIZE(peri_muxes),
.rst_desc = &clk_rst_desc,
.clk_lock = &mt7622_clk_lock,
};
static const struct of_device_id of_match_clk_mt7622[] = {
{ .compatible = "mediatek,mt7622-topckgen", .data = &topck_desc },
{ .compatible = "mediatek,mt7622-pericfg", .data = &peri_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7622);
static struct platform_driver clk_mt7622_drv = {
.driver = {
.name = "clk-mt7622",
.of_match_table = of_match_clk_mt7622,
},
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt7622_drv)
MODULE_DESCRIPTION("MediaTek MT7622 clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt7622.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8192-clk.h>
static const struct mtk_gate_regs mm0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs mm1_cg_regs = {
.set_ofs = 0x114,
.clr_ofs = 0x118,
.sta_ofs = 0x110,
};
static const struct mtk_gate_regs mm2_cg_regs = {
.set_ofs = 0x1a4,
.clr_ofs = 0x1a8,
.sta_ofs = 0x1a0,
};
#define GATE_MM0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_MM1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_MM2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate mm_clks[] = {
/* MM0 */
GATE_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0", "disp_sel", 0),
GATE_MM0(CLK_MM_DISP_CONFIG, "mm_disp_config", "disp_sel", 1),
GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "disp_sel", 2),
GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "disp_sel", 3),
GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "disp_sel", 4),
GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "disp_sel", 5),
GATE_MM0(CLK_MM_DISP_UFBC_WDMA0, "mm_disp_ufbc_wdma0", "disp_sel", 6),
GATE_MM0(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "disp_sel", 7),
GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "disp_sel", 8),
GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "disp_sel", 9),
GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "disp_sel", 10),
GATE_MM0(CLK_MM_SMI_INFRA, "mm_smi_infra", "disp_sel", 11),
GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "disp_sel", 12),
GATE_MM0(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0", "disp_sel", 13),
GATE_MM0(CLK_MM_DISP_DSC_WRAP0, "mm_disp_dsc_wrap0", "disp_sel", 14),
GATE_MM0(CLK_MM_DSI0, "mm_dsi0", "disp_sel", 15),
GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "disp_sel", 16),
GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "disp_sel", 17),
GATE_MM0(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0", "disp_sel", 18),
GATE_MM0(CLK_MM_DISP_FAKE_ENG1, "mm_disp_fake_eng1", "disp_sel", 19),
GATE_MM0(CLK_MM_MDP_TDSHP4, "mm_mdp_tdshp4", "disp_sel", 20),
GATE_MM0(CLK_MM_MDP_RSZ4, "mm_mdp_rsz4", "disp_sel", 21),
GATE_MM0(CLK_MM_MDP_AAL4, "mm_mdp_aal4", "disp_sel", 22),
GATE_MM0(CLK_MM_MDP_HDR4, "mm_mdp_hdr4", "disp_sel", 23),
GATE_MM0(CLK_MM_MDP_RDMA4, "mm_mdp_rdma4", "disp_sel", 24),
GATE_MM0(CLK_MM_MDP_COLOR4, "mm_mdp_color4", "disp_sel", 25),
GATE_MM0(CLK_MM_DISP_Y2R0, "mm_disp_y2r0", "disp_sel", 26),
GATE_MM0(CLK_MM_SMI_GALS, "mm_smi_gals", "disp_sel", 27),
GATE_MM0(CLK_MM_DISP_OVL2_2L, "mm_disp_ovl2_2l", "disp_sel", 28),
GATE_MM0(CLK_MM_DISP_RDMA4, "mm_disp_rdma4", "disp_sel", 29),
GATE_MM0(CLK_MM_DISP_DPI0, "mm_disp_dpi0", "disp_sel", 30),
/* MM1 */
GATE_MM1(CLK_MM_SMI_IOMMU, "mm_smi_iommu", "disp_sel", 0),
/* MM2 */
GATE_MM2(CLK_MM_DSI_DSI0, "mm_dsi_dsi0", "disp_sel", 0),
GATE_MM2(CLK_MM_DPI_DPI0, "mm_dpi_dpi0", "dpi_sel", 8),
GATE_MM2(CLK_MM_26MHZ, "mm_26mhz", "clk26m", 24),
GATE_MM2(CLK_MM_32KHZ, "mm_32khz", "clk32k", 25),
};
static const struct mtk_clk_desc mm_desc = {
.clks = mm_clks,
.num_clks = ARRAY_SIZE(mm_clks),
};
static const struct platform_device_id clk_mt8192_mm_id_table[] = {
{ .name = "clk-mt8192-mm", .driver_data = (kernel_ulong_t)&mm_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, clk_mt8192_mm_id_table);
static struct platform_driver clk_mt8192_mm_drv = {
.probe = mtk_clk_pdev_probe,
.remove_new = mtk_clk_pdev_remove,
.driver = {
.name = "clk-mt8192-mm",
},
.id_table = clk_mt8192_mm_id_table,
};
module_platform_driver(clk_mt8192_mm_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8192-mm.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8192-clk.h>
static const struct mtk_gate_regs msdc_top_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x0,
.sta_ofs = 0x0,
};
#define GATE_MSDC_TOP(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &msdc_top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate msdc_top_clks[] = {
GATE_MSDC_TOP(CLK_MSDC_TOP_AES_0P, "msdc_top_aes_0p", "aes_msdcfde_sel", 0),
GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_0P, "msdc_top_src_0p", "infra_msdc0_src", 1),
GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_1P, "msdc_top_src_1p", "infra_msdc1_src", 2),
GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_2P, "msdc_top_src_2p", "infra_msdc2_src", 3),
GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC0, "msdc_top_p_msdc0", "axi_sel", 4),
GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC1, "msdc_top_p_msdc1", "axi_sel", 5),
GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC2, "msdc_top_p_msdc2", "axi_sel", 6),
GATE_MSDC_TOP(CLK_MSDC_TOP_P_CFG, "msdc_top_p_cfg", "axi_sel", 7),
GATE_MSDC_TOP(CLK_MSDC_TOP_AXI, "msdc_top_axi", "axi_sel", 8),
GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_0P, "msdc_top_h_mst_0p", "infra_msdc0", 9),
GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_1P, "msdc_top_h_mst_1p", "infra_msdc1", 10),
GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_2P, "msdc_top_h_mst_2p", "infra_msdc2", 11),
GATE_MSDC_TOP(CLK_MSDC_TOP_MEM_OFF_DLY_26M, "msdc_top_mem_off_dly_26m", "clk26m", 12),
GATE_MSDC_TOP(CLK_MSDC_TOP_32K, "msdc_top_32k", "clk32k", 13),
GATE_MSDC_TOP(CLK_MSDC_TOP_AHB2AXI_BRG_AXI, "msdc_top_ahb2axi_brg_axi", "axi_sel", 14),
};
static const struct mtk_clk_desc msdc_top_desc = {
.clks = msdc_top_clks,
.num_clks = ARRAY_SIZE(msdc_top_clks),
};
static const struct of_device_id of_match_clk_mt8192_msdc[] = {
{
.compatible = "mediatek,mt8192-msdc_top",
.data = &msdc_top_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_msdc);
static struct platform_driver clk_mt8192_msdc_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8192-msdc",
.of_match_table = of_match_clk_mt8192_msdc,
},
};
module_platform_driver(clk_mt8192_msdc_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8192-msdc.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: James Liao <[email protected]>
* Fabien Parent <[email protected]>
* Copyright (c) 2023 Collabora Ltd.
*/
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/mfd/syscon.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8516-clk.h>
static DEFINE_SPINLOCK(mt8516_clk_lock);
static const struct mtk_fixed_clk fixed_clks[] __initconst = {
FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, "i2s_infra_bck", "clk_null", 26000000),
FIXED_CLK(CLK_TOP_MEMPLL, "mempll", "clk26m", 800000000),
};
static const struct mtk_fixed_factor top_divs[] __initconst = {
FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D8, "mainpll_d8", "mainpll", 1, 8),
FACTOR(CLK_TOP_MAINPLL_D16, "mainpll_d16", "mainpll", 1, 16),
FACTOR(CLK_TOP_MAINPLL_D11, "mainpll_d11", "mainpll", 1, 11),
FACTOR(CLK_TOP_MAINPLL_D22, "mainpll_d22", "mainpll", 1, 22),
FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
FACTOR(CLK_TOP_MAINPLL_D12, "mainpll_d12", "mainpll", 1, 12),
FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
FACTOR(CLK_TOP_MAINPLL_D10, "mainpll_d10", "mainpll", 1, 10),
FACTOR(CLK_TOP_MAINPLL_D20, "mainpll_d20", "mainpll", 1, 20),
FACTOR(CLK_TOP_MAINPLL_D40, "mainpll_d40", "mainpll", 1, 40),
FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
FACTOR(CLK_TOP_MAINPLL_D14, "mainpll_d14", "mainpll", 1, 14),
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D8, "univpll_d8", "univpll", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D16, "univpll_d16", "univpll", 1, 16),
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
FACTOR(CLK_TOP_UNIVPLL_D12, "univpll_d12", "univpll", 1, 12),
FACTOR(CLK_TOP_UNIVPLL_D24, "univpll_d24", "univpll", 1, 24),
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
FACTOR(CLK_TOP_UNIVPLL_D20, "univpll_d20", "univpll", 1, 20),
FACTOR(CLK_TOP_MMPLL380M, "mmpll380m", "mmpll", 1, 1),
FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
FACTOR(CLK_TOP_MMPLL_200M, "mmpll_200m", "mmpll", 1, 3),
FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "rg_apll1_d2_en", 1, 2),
FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "rg_apll1_d4_en", 1, 2),
FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2),
FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "rg_apll2_d2_en", 1, 2),
FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "rg_apll2_d4_en", 1, 2),
FACTOR(CLK_TOP_CLK26M, "clk26m_ck", "clk26m", 1, 1),
FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
FACTOR(CLK_TOP_AHB_INFRA_D2, "ahb_infra_d2", "ahb_infra_sel", 1, 2),
FACTOR(CLK_TOP_NFI1X, "nfi1x_ck", "nfi2x_pad_sel", 1, 2),
FACTOR(CLK_TOP_ETH_D2, "eth_d2_ck", "eth_sel", 1, 2),
};
static const char * const uart0_parents[] __initconst = {
"clk26m_ck",
"univpll_d24"
};
static const char * const ahb_infra_parents[] __initconst = {
"clk_null",
"clk26m_ck",
"mainpll_d11",
"clk_null",
"mainpll_d12",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"mainpll_d10"
};
static const char * const msdc0_parents[] __initconst = {
"clk26m_ck",
"univpll_d6",
"mainpll_d8",
"univpll_d8",
"mainpll_d16",
"mmpll_200m",
"mainpll_d12",
"mmpll_d2"
};
static const char * const uart1_parents[] __initconst = {
"clk26m_ck",
"univpll_d24"
};
static const char * const msdc1_parents[] __initconst = {
"clk26m_ck",
"univpll_d6",
"mainpll_d8",
"univpll_d8",
"mainpll_d16",
"mmpll_200m",
"mainpll_d12",
"mmpll_d2"
};
static const char * const pmicspi_parents[] __initconst = {
"univpll_d20",
"usb_phy48m_ck",
"univpll_d16",
"clk26m_ck"
};
static const char * const qaxi_aud26m_parents[] __initconst = {
"clk26m_ck",
"ahb_infra_sel"
};
static const char * const aud_intbus_parents[] __initconst = {
"clk_null",
"clk26m_ck",
"mainpll_d22",
"clk_null",
"mainpll_d11"
};
static const char * const nfi2x_pad_parents[] __initconst = {
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk26m_ck",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"mainpll_d12",
"mainpll_d8",
"clk_null",
"mainpll_d6",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"mainpll_d4",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"clk_null",
"mainpll_d10",
"mainpll_d7",
"clk_null",
"mainpll_d5"
};
static const char * const nfi1x_pad_parents[] __initconst = {
"ahb_infra_sel",
"nfi1x_ck"
};
static const char * const usb_78m_parents[] __initconst = {
"clk_null",
"clk26m_ck",
"univpll_d16",
"clk_null",
"mainpll_d20"
};
static const char * const spinor_parents[] __initconst = {
"clk26m_d2",
"clk26m_ck",
"mainpll_d40",
"univpll_d24",
"univpll_d20",
"mainpll_d20",
"mainpll_d16",
"univpll_d12"
};
static const char * const msdc2_parents[] __initconst = {
"clk26m_ck",
"univpll_d6",
"mainpll_d8",
"univpll_d8",
"mainpll_d16",
"mmpll_200m",
"mainpll_d12",
"mmpll_d2"
};
static const char * const eth_parents[] __initconst = {
"clk26m_ck",
"mainpll_d40",
"univpll_d24",
"univpll_d20",
"mainpll_d20"
};
static const char * const aud1_parents[] __initconst = {
"clk26m_ck",
"apll1_ck"
};
static const char * const aud2_parents[] __initconst = {
"clk26m_ck",
"apll2_ck"
};
static const char * const aud_engen1_parents[] __initconst = {
"clk26m_ck",
"rg_apll1_d2_en",
"rg_apll1_d4_en",
"rg_apll1_d8_en"
};
static const char * const aud_engen2_parents[] __initconst = {
"clk26m_ck",
"rg_apll2_d2_en",
"rg_apll2_d4_en",
"rg_apll2_d8_en"
};
static const char * const i2c_parents[] __initconst = {
"clk26m_ck",
"univpll_d20",
"univpll_d16",
"univpll_d12"
};
static const char * const aud_i2s0_m_parents[] __initconst = {
"rg_aud1",
"rg_aud2"
};
static const char * const pwm_parents[] __initconst = {
"clk26m_ck",
"univpll_d12"
};
static const char * const spi_parents[] __initconst = {
"clk26m_ck",
"univpll_d12",
"univpll_d8",
"univpll_d6"
};
static const char * const aud_spdifin_parents[] __initconst = {
"clk26m_ck",
"univpll_d2"
};
static const char * const uart2_parents[] __initconst = {
"clk26m_ck",
"univpll_d24"
};
static const char * const bsi_parents[] __initconst = {
"clk26m_ck",
"mainpll_d10",
"mainpll_d12",
"mainpll_d20"
};
static const char * const dbg_atclk_parents[] __initconst = {
"clk_null",
"clk26m_ck",
"mainpll_d5",
"clk_null",
"univpll_d5"
};
static const char * const csw_nfiecc_parents[] __initconst = {
"clk_null",
"mainpll_d7",
"mainpll_d6",
"clk_null",
"mainpll_d5"
};
static const char * const nfiecc_parents[] __initconst = {
"clk_null",
"nfi2x_pad_sel",
"mainpll_d4",
"clk_null",
"csw_nfiecc_sel"
};
static struct mtk_composite top_muxes[] __initdata = {
/* CLK_MUX_SEL0 */
MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
0x000, 0, 1),
MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents,
0x000, 4, 4),
MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents,
0x000, 11, 3),
MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents,
0x000, 19, 1),
MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents,
0x000, 20, 3),
MUX(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
0x000, 24, 2),
MUX(CLK_TOP_QAXI_AUD26M_SEL, "qaxi_aud26m_sel", qaxi_aud26m_parents,
0x000, 26, 1),
MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
0x000, 27, 3),
/* CLK_MUX_SEL1 */
MUX(CLK_TOP_NFI2X_PAD_SEL, "nfi2x_pad_sel", nfi2x_pad_parents,
0x004, 0, 7),
MUX(CLK_TOP_NFI1X_PAD_SEL, "nfi1x_pad_sel", nfi1x_pad_parents,
0x004, 7, 1),
MUX(CLK_TOP_USB_78M_SEL, "usb_78m_sel", usb_78m_parents,
0x004, 20, 3),
/* CLK_MUX_SEL8 */
MUX(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents,
0x040, 0, 3),
MUX(CLK_TOP_MSDC2_SEL, "msdc2_sel", msdc2_parents,
0x040, 3, 3),
MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
0x040, 6, 3),
MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
0x040, 22, 1),
MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
0x040, 23, 1),
MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
0x040, 24, 2),
MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents,
0x040, 26, 2),
MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
0x040, 28, 2),
/* CLK_SEL_9 */
MUX(CLK_TOP_AUD_I2S0_M_SEL, "aud_i2s0_m_sel", aud_i2s0_m_parents,
0x044, 12, 1),
MUX(CLK_TOP_AUD_I2S1_M_SEL, "aud_i2s1_m_sel", aud_i2s0_m_parents,
0x044, 13, 1),
MUX(CLK_TOP_AUD_I2S2_M_SEL, "aud_i2s2_m_sel", aud_i2s0_m_parents,
0x044, 14, 1),
MUX(CLK_TOP_AUD_I2S3_M_SEL, "aud_i2s3_m_sel", aud_i2s0_m_parents,
0x044, 15, 1),
MUX(CLK_TOP_AUD_I2S4_M_SEL, "aud_i2s4_m_sel", aud_i2s0_m_parents,
0x044, 16, 1),
MUX(CLK_TOP_AUD_I2S5_M_SEL, "aud_i2s5_m_sel", aud_i2s0_m_parents,
0x044, 17, 1),
MUX(CLK_TOP_AUD_SPDIF_B_SEL, "aud_spdif_b_sel", aud_i2s0_m_parents,
0x044, 18, 1),
/* CLK_MUX_SEL13 */
MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
0x07c, 0, 1),
MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
0x07c, 1, 2),
MUX(CLK_TOP_AUD_SPDIFIN_SEL, "aud_spdifin_sel", aud_spdifin_parents,
0x07c, 3, 1),
MUX(CLK_TOP_UART2_SEL, "uart2_sel", uart2_parents,
0x07c, 4, 1),
MUX(CLK_TOP_BSI_SEL, "bsi_sel", bsi_parents,
0x07c, 5, 2),
MUX(CLK_TOP_DBG_ATCLK_SEL, "dbg_atclk_sel", dbg_atclk_parents,
0x07c, 7, 3),
MUX(CLK_TOP_CSW_NFIECC_SEL, "csw_nfiecc_sel", csw_nfiecc_parents,
0x07c, 10, 3),
MUX(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,
0x07c, 13, 3),
};
static const char * const ifr_mux1_parents[] __initconst = {
"clk26m_ck",
"armpll",
"univpll",
"mainpll_d2"
};
static const char * const ifr_eth_25m_parents[] __initconst = {
"eth_d2_ck",
"rg_eth"
};
static const char * const ifr_i2c0_parents[] __initconst = {
"ahb_infra_d2",
"rg_i2c"
};
static const struct mtk_composite ifr_muxes[] __initconst = {
MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000,
2, 2),
MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080,
0, 1),
MUX(CLK_IFR_I2C0_SEL, "ifr_i2c0_sel", ifr_i2c0_parents, 0x080,
1, 1),
MUX(CLK_IFR_I2C1_SEL, "ifr_i2c1_sel", ifr_i2c0_parents, 0x080,
2, 1),
MUX(CLK_IFR_I2C2_SEL, "ifr_i2c2_sel", ifr_i2c0_parents, 0x080,
3, 1),
};
#define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.div_reg = _reg, \
.div_shift = _shift, \
.div_width = _width, \
}
static const struct mtk_clk_divider top_adj_divs[] = {
DIV_ADJ(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "aud_i2s0_m_sel",
0x0048, 0, 8),
DIV_ADJ(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "aud_i2s1_m_sel",
0x0048, 8, 8),
DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel",
0x0048, 16, 8),
DIV_ADJ(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "aud_i2s3_m_sel",
0x0048, 24, 8),
DIV_ADJ(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "aud_i2s4_m_sel",
0x004c, 0, 8),
DIV_ADJ(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll12_div4",
0x004c, 8, 8),
DIV_ADJ(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "aud_i2s5_m_sel",
0x004c, 16, 8),
DIV_ADJ(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll12_div5",
0x004c, 24, 8),
DIV_ADJ(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "aud_spdif_b_sel",
0x0078, 0, 8),
};
static const struct mtk_gate_regs top1_cg_regs = {
.set_ofs = 0x54,
.clr_ofs = 0x84,
.sta_ofs = 0x24,
};
static const struct mtk_gate_regs top2_cg_regs = {
.set_ofs = 0x6c,
.clr_ofs = 0x9c,
.sta_ofs = 0x3c,
};
static const struct mtk_gate_regs top3_cg_regs = {
.set_ofs = 0xa0,
.clr_ofs = 0xb0,
.sta_ofs = 0x70,
};
static const struct mtk_gate_regs top4_cg_regs = {
.set_ofs = 0xa4,
.clr_ofs = 0xb4,
.sta_ofs = 0x74,
};
static const struct mtk_gate_regs top5_cg_regs = {
.set_ofs = 0x44,
.clr_ofs = 0x44,
.sta_ofs = 0x44,
};
#define GATE_TOP1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_TOP2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_TOP2_I(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
#define GATE_TOP3(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_TOP4_I(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top4_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
#define GATE_TOP5(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top5_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate top_clks[] __initconst = {
/* TOP1 */
GATE_TOP1(CLK_TOP_THEM, "them", "ahb_infra_sel", 1),
GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2),
GATE_TOP1(CLK_TOP_I2C0, "i2c0", "ifr_i2c0_sel", 3),
GATE_TOP1(CLK_TOP_I2C1, "i2c1", "ifr_i2c1_sel", 4),
GATE_TOP1(CLK_TOP_AUXADC1, "auxadc1", "ahb_infra_sel", 5),
GATE_TOP1(CLK_TOP_NFI, "nfi", "nfi1x_pad_sel", 6),
GATE_TOP1(CLK_TOP_NFIECC, "nfiecc", "rg_nfiecc", 7),
GATE_TOP1(CLK_TOP_DEBUGSYS, "debugsys", "rg_dbg_atclk", 8),
GATE_TOP1(CLK_TOP_PWM, "pwm", "ahb_infra_sel", 9),
GATE_TOP1(CLK_TOP_UART0, "uart0", "uart0_sel", 10),
GATE_TOP1(CLK_TOP_UART1, "uart1", "uart1_sel", 11),
GATE_TOP1(CLK_TOP_BTIF, "btif", "ahb_infra_sel", 12),
GATE_TOP1(CLK_TOP_USB, "usb", "usb_78m", 13),
GATE_TOP1(CLK_TOP_FLASHIF_26M, "flashif_26m", "clk26m_ck", 14),
GATE_TOP1(CLK_TOP_AUXADC2, "auxadc2", "ahb_infra_sel", 15),
GATE_TOP1(CLK_TOP_I2C2, "i2c2", "ifr_i2c2_sel", 16),
GATE_TOP1(CLK_TOP_MSDC0, "msdc0", "msdc0_sel", 17),
GATE_TOP1(CLK_TOP_MSDC1, "msdc1", "msdc1_sel", 18),
GATE_TOP1(CLK_TOP_NFI2X, "nfi2x", "nfi2x_pad_sel", 19),
GATE_TOP1(CLK_TOP_PMICWRAP_AP, "pwrap_ap", "clk26m_ck", 20),
GATE_TOP1(CLK_TOP_SEJ, "sej", "ahb_infra_sel", 21),
GATE_TOP1(CLK_TOP_MEMSLP_DLYER, "memslp_dlyer", "clk26m_ck", 22),
GATE_TOP1(CLK_TOP_SPI, "spi", "spi_sel", 23),
GATE_TOP1(CLK_TOP_APXGPT, "apxgpt", "clk26m_ck", 24),
GATE_TOP1(CLK_TOP_AUDIO, "audio", "clk26m_ck", 25),
GATE_TOP1(CLK_TOP_PMICWRAP_MD, "pwrap_md", "clk26m_ck", 27),
GATE_TOP1(CLK_TOP_PMICWRAP_CONN, "pwrap_conn", "clk26m_ck", 28),
GATE_TOP1(CLK_TOP_PMICWRAP_26M, "pwrap_26m", "clk26m_ck", 29),
GATE_TOP1(CLK_TOP_AUX_ADC, "aux_adc", "clk26m_ck", 30),
GATE_TOP1(CLK_TOP_AUX_TP, "aux_tp", "clk26m_ck", 31),
/* TOP2 */
GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0),
GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1),
GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2),
GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4),
GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5),
GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6),
GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7),
GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8),
GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9),
GATE_TOP2(CLK_TOP_PWM2_FB, "pwm2_fb", "rg_pwm_infra", 10),
GATE_TOP2(CLK_TOP_PWM3_FB, "pwm3_fb", "rg_pwm_infra", 11),
GATE_TOP2(CLK_TOP_PWM4_FB, "pwm4_fb", "rg_pwm_infra", 12),
GATE_TOP2(CLK_TOP_PWM5_FB, "pwm5_fb", "rg_pwm_infra", 13),
GATE_TOP2(CLK_TOP_USB_1P, "usb_1p", "usb_78m", 14),
GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, "flashif_freerun", "ahb_infra_sel",
15),
GATE_TOP2(CLK_TOP_66M_ETH, "eth_66m", "ahb_infra_d2", 19),
GATE_TOP2(CLK_TOP_133M_ETH, "eth_133m", "ahb_infra_sel", 20),
GATE_TOP2(CLK_TOP_FETH_25M, "feth_25m", "ifr_eth_25m_sel", 21),
GATE_TOP2(CLK_TOP_FETH_50M, "feth_50m", "rg_eth", 22),
GATE_TOP2(CLK_TOP_FLASHIF_AXI, "flashif_axi", "ahb_infra_sel", 23),
GATE_TOP2(CLK_TOP_USBIF, "usbif", "ahb_infra_sel", 24),
GATE_TOP2(CLK_TOP_UART2, "uart2", "rg_uart2", 25),
GATE_TOP2(CLK_TOP_BSI, "bsi", "ahb_infra_sel", 26),
GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, "msdc0_infra", "msdc0", 28),
GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, "msdc1_infra", "msdc1", 29),
GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, "msdc2_infra", "rg_msdc2", 30),
GATE_TOP2(CLK_TOP_USB_78M, "usb_78m", "usb_78m_sel", 31),
/* TOP3 */
GATE_TOP3(CLK_TOP_RG_SPINOR, "rg_spinor", "spinor_sel", 0),
GATE_TOP3(CLK_TOP_RG_MSDC2, "rg_msdc2", "msdc2_sel", 1),
GATE_TOP3(CLK_TOP_RG_ETH, "rg_eth", "eth_sel", 2),
GATE_TOP3(CLK_TOP_RG_AUD1, "rg_aud1", "aud1_sel", 8),
GATE_TOP3(CLK_TOP_RG_AUD2, "rg_aud2", "aud2_sel", 9),
GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, "rg_aud_engen1", "aud_engen1_sel", 10),
GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, "rg_aud_engen2", "aud_engen2_sel", 11),
GATE_TOP3(CLK_TOP_RG_I2C, "rg_i2c", "i2c_sel", 12),
GATE_TOP3(CLK_TOP_RG_PWM_INFRA, "rg_pwm_infra", "pwm_sel", 13),
GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, "rg_aud_spdif_in", "aud_spdifin_sel",
14),
GATE_TOP3(CLK_TOP_RG_UART2, "rg_uart2", "uart2_sel", 15),
GATE_TOP3(CLK_TOP_RG_BSI, "rg_bsi", "bsi_sel", 16),
GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, "rg_dbg_atclk", "dbg_atclk_sel", 17),
GATE_TOP3(CLK_TOP_RG_NFIECC, "rg_nfiecc", "nfiecc_sel", 18),
/* TOP4 */
GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, "rg_apll1_d2_en", "apll1_d2", 8),
GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, "rg_apll1_d4_en", "apll1_d4", 9),
GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, "rg_apll1_d8_en", "apll1_d8", 10),
GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, "rg_apll2_d2_en", "apll2_d2", 11),
GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, "rg_apll2_d4_en", "apll2_d4", 12),
GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, "rg_apll2_d8_en", "apll2_d8", 13),
/* TOP5 */
GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0),
GATE_TOP5(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll12_ck_div1", 1),
GATE_TOP5(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll12_ck_div2", 2),
GATE_TOP5(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll12_ck_div3", 3),
GATE_TOP5(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll12_ck_div4", 4),
GATE_TOP5(CLK_TOP_APLL12_DIV4B, "apll12_div4b", "apll12_ck_div4b", 5),
GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6),
GATE_TOP5(CLK_TOP_APLL12_DIV5B, "apll12_div5b", "apll12_ck_div5b", 7),
GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8),
};
static const struct mtk_clk_desc topck_desc = {
.clks = top_clks,
.num_clks = ARRAY_SIZE(top_clks),
.fixed_clks = fixed_clks,
.num_fixed_clks = ARRAY_SIZE(fixed_clks),
.factor_clks = top_divs,
.num_factor_clks = ARRAY_SIZE(top_divs),
.composite_clks = top_muxes,
.num_composite_clks = ARRAY_SIZE(top_muxes),
.divider_clks = top_adj_divs,
.num_divider_clks = ARRAY_SIZE(top_adj_divs),
.clk_lock = &mt8516_clk_lock,
};
static const struct mtk_clk_desc infra_desc = {
.composite_clks = ifr_muxes,
.num_composite_clks = ARRAY_SIZE(ifr_muxes),
.clk_lock = &mt8516_clk_lock,
};
static const struct of_device_id of_match_clk_mt8516[] = {
{ .compatible = "mediatek,mt8516-topckgen", .data = &topck_desc },
{ .compatible = "mediatek,mt8516-infracfg", .data = &infra_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8516);
static struct platform_driver clk_mt8516_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8516",
.of_match_table = of_match_clk_mt8516,
},
};
module_platform_driver(clk_mt8516_drv);
MODULE_DESCRIPTION("MediaTek MT8516 clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8516.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt8186-clk.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {
.set_ofs = 0xe08,
.clr_ofs = 0xe04,
.sta_ofs = 0xe00,
};
#define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate imp_iic_wrap_clks[] = {
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0,
"imp_iic_wrap_ap_clock_i2c0", "infra_ao_i2c_ap", 0),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1,
"imp_iic_wrap_ap_clock_i2c1", "infra_ao_i2c_ap", 1),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2,
"imp_iic_wrap_ap_clock_i2c2", "infra_ao_i2c_ap", 2),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3,
"imp_iic_wrap_ap_clock_i2c3", "infra_ao_i2c_ap", 3),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4,
"imp_iic_wrap_ap_clock_i2c4", "infra_ao_i2c_ap", 4),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5,
"imp_iic_wrap_ap_clock_i2c5", "infra_ao_i2c_ap", 5),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6,
"imp_iic_wrap_ap_clock_i2c6", "infra_ao_i2c_ap", 6),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7,
"imp_iic_wrap_ap_clock_i2c7", "infra_ao_i2c_ap", 7),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8,
"imp_iic_wrap_ap_clock_i2c8", "infra_ao_i2c_ap", 8),
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9,
"imp_iic_wrap_ap_clock_i2c9", "infra_ao_i2c_ap", 9),
};
static const struct mtk_clk_desc imp_iic_wrap_desc = {
.clks = imp_iic_wrap_clks,
.num_clks = ARRAY_SIZE(imp_iic_wrap_clks),
};
static const struct of_device_id of_match_clk_mt8186_imp_iic_wrap[] = {
{
.compatible = "mediatek,mt8186-imp_iic_wrap",
.data = &imp_iic_wrap_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_imp_iic_wrap);
static struct platform_driver clk_mt8186_imp_iic_wrap_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8186-imp_iic_wrap",
.of_match_table = of_match_clk_mt8186_imp_iic_wrap,
},
};
module_platform_driver(clk_mt8186_imp_iic_wrap_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 MediaTek Inc.
* Author: Sam Shih <[email protected]>
* Author: Wenzhen Yu <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-mux.h"
#include "clk-pll.h"
#include <dt-bindings/clock/mt7986-clk.h>
#include <linux/clk.h>
#define MT7986_PLL_FMAX (2500UL * MHZ)
#define CON0_MT7986_RST_BAR BIT(27)
#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
_div_table, _parent_name) \
{ \
.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
.en_mask = _en_mask, .flags = _flags, \
.rst_bar_mask = CON0_MT7986_RST_BAR, .fmax = MT7986_PLL_FMAX, \
.pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, .div_table = _div_table, \
.parent_name = _parent_name, \
}
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
_pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \
PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \
"clkxtal")
static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32,
0x0200, 4, 0, 0x0204, 0),
PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32,
0x0210, 4, 0, 0x0214, 0),
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x0, 0, 32,
0x0220, 4, 0, 0x0224, 0),
PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x0, 0, 32,
0x0230, 4, 0, 0x0234, 0),
PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x0, 0,
32, 0x0240, 4, 0, 0x0244, 0),
PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025c, 0x0, 0, 32,
0x0250, 4, 0, 0x0254, 0),
PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x0, 0, 32, 0x0260,
4, 0, 0x0264, 0),
PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x0, 0, 32,
0x0278, 4, 0, 0x027c, 0),
};
static const struct of_device_id of_match_clk_mt7986_apmixed[] = {
{ .compatible = "mediatek,mt7986-apmixedsys", },
{ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_apmixed);
static int clk_mt7986_apmixed_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
if (!clk_data)
return -ENOMEM;
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
goto free_apmixed_data;
}
return r;
free_apmixed_data:
mtk_free_clk_data(clk_data);
return r;
}
static struct platform_driver clk_mt7986_apmixed_drv = {
.probe = clk_mt7986_apmixed_probe,
.driver = {
.name = "clk-mt7986-apmixed",
.of_match_table = of_match_clk_mt7986_apmixed,
},
};
builtin_platform_driver(clk_mt7986_apmixed_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt7986-apmixed.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 MediaTek Inc.
* Copyright (c) 2020 BayLibre, SAS
* Author: James Liao <[email protected]>
* Fabien Parent <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8167-clk.h>
static const struct mtk_gate_regs mfg_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_MFG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate mfg_clks[] = {
GATE_MFG(CLK_MFG_BAXI, "mfg_baxi", "ahb_infra_sel", 0),
GATE_MFG(CLK_MFG_BMEM, "mfg_bmem", "gfmux_emi1x_sel", 1),
GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_mm", 2),
GATE_MFG(CLK_MFG_B26M, "mfg_b26m", "clk26m_ck", 3),
};
static const struct mtk_clk_desc mfg_desc = {
.clks = mfg_clks,
.num_clks = ARRAY_SIZE(mfg_clks),
};
static const struct of_device_id of_match_clk_mt8167_mfgcfg[] = {
{ .compatible = "mediatek,mt8167-mfgcfg", .data = &mfg_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_mfgcfg);
static struct platform_driver clk_mt8167_mfgcfg_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8167-mfgcfg",
.of_match_table = of_match_clk_mt8167_mfgcfg,
},
};
module_platform_driver(clk_mt8167_mfgcfg_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8167-mfgcfg.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 MediaTek Inc.
* Author: Owen Chen <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/mfd/syscon.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-mux.h"
#include "clk-pll.h"
#include <dt-bindings/clock/mt6765-clk.h>
/*fmeter div select 4*/
#define _DIV4_ 1
static DEFINE_SPINLOCK(mt6765_clk_lock);
/* Total 12 subsys */
static void __iomem *cksys_base;
static void __iomem *apmixed_base;
/* CKSYS */
#define CLK_SCP_CFG_0 (cksys_base + 0x200)
#define CLK_SCP_CFG_1 (cksys_base + 0x204)
/* CG */
#define AP_PLL_CON3 (apmixed_base + 0x0C)
#define PLLON_CON0 (apmixed_base + 0x44)
#define PLLON_CON1 (apmixed_base + 0x48)
/* clk cfg update */
#define CLK_CFG_0 0x40
#define CLK_CFG_0_SET 0x44
#define CLK_CFG_0_CLR 0x48
#define CLK_CFG_1 0x50
#define CLK_CFG_1_SET 0x54
#define CLK_CFG_1_CLR 0x58
#define CLK_CFG_2 0x60
#define CLK_CFG_2_SET 0x64
#define CLK_CFG_2_CLR 0x68
#define CLK_CFG_3 0x70
#define CLK_CFG_3_SET 0x74
#define CLK_CFG_3_CLR 0x78
#define CLK_CFG_4 0x80
#define CLK_CFG_4_SET 0x84
#define CLK_CFG_4_CLR 0x88
#define CLK_CFG_5 0x90
#define CLK_CFG_5_SET 0x94
#define CLK_CFG_5_CLR 0x98
#define CLK_CFG_6 0xa0
#define CLK_CFG_6_SET 0xa4
#define CLK_CFG_6_CLR 0xa8
#define CLK_CFG_7 0xb0
#define CLK_CFG_7_SET 0xb4
#define CLK_CFG_7_CLR 0xb8
#define CLK_CFG_8 0xc0
#define CLK_CFG_8_SET 0xc4
#define CLK_CFG_8_CLR 0xc8
#define CLK_CFG_9 0xd0
#define CLK_CFG_9_SET 0xd4
#define CLK_CFG_9_CLR 0xd8
#define CLK_CFG_10 0xe0
#define CLK_CFG_10_SET 0xe4
#define CLK_CFG_10_CLR 0xe8
#define CLK_CFG_UPDATE 0x004
static const struct mtk_fixed_clk fixed_clks[] = {
FIXED_CLK(CLK_TOP_F_FRTC, "f_frtc_ck", "clk32k", 32768),
FIXED_CLK(CLK_TOP_CLK26M, "clk_26m_ck", "clk26m", 26000000),
FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 466000000),
};
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", "univpll", 2, 13),
FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", "usb20_192m_ck", 1, 4),
FACTOR(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", "usb20_192m_ck", 1, 8),
FACTOR(CLK_TOP_USB20_192M_D16,
"usb20_192m_d16", "usb20_192m_ck", 1, 16),
FACTOR(CLK_TOP_USB20_192M_D32,
"usb20_192m_d32", "usb20_192m_ck", 1, 32),
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2),
FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32),
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1, 2),
FACTOR(CLK_TOP_MPLL, "mpll_ck", "mpll", 1, 1),
FACTOR(CLK_TOP_DA_MPLL_104M_DIV, "mpll_104m_div", "mpll_ck", 1, 2),
FACTOR(CLK_TOP_DA_MPLL_52M_DIV, "mpll_52m_div", "mpll_ck", 1, 4),
FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", "mfgpll", 1, 1),
FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4),
FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8),
FACTOR(CLK_TOP_ULPOSC1, "ulposc1_ck", "ulposc1", 1, 1),
FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc1_ck", 1, 2),
FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc1_ck", 1, 4),
FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc1_ck", 1, 8),
FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc1_ck", 1, 16),
FACTOR(CLK_TOP_ULPOSC1_D32, "ulposc1_d32", "ulposc1_ck", 1, 32),
FACTOR(CLK_TOP_F_F26M, "f_f26m_ck", "clk_26m_ck", 1, 1),
FACTOR(CLK_TOP_AXI, "axi_ck", "axi_sel", 1, 1),
FACTOR(CLK_TOP_MM, "mm_ck", "mm_sel", 1, 1),
FACTOR(CLK_TOP_SCP, "scp_ck", "scp_sel", 1, 1),
FACTOR(CLK_TOP_MFG, "mfg_ck", "mfg_sel", 1, 1),
FACTOR(CLK_TOP_F_FUART, "f_fuart_ck", "uart_sel", 1, 1),
FACTOR(CLK_TOP_SPI, "spi_ck", "spi_sel", 1, 1),
FACTOR(CLK_TOP_MSDC50_0, "msdc50_0_ck", "msdc50_0_sel", 1, 1),
FACTOR(CLK_TOP_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 1, 1),
FACTOR(CLK_TOP_AUDIO, "audio_ck", "audio_sel", 1, 1),
FACTOR(CLK_TOP_AUD_1, "aud_1_ck", "aud_1_sel", 1, 1),
FACTOR(CLK_TOP_AUD_ENGEN1, "aud_engen1_ck", "aud_engen1_sel", 1, 1),
FACTOR(CLK_TOP_F_FDISP_PWM, "f_fdisp_pwm_ck", "disp_pwm_sel", 1, 1),
FACTOR(CLK_TOP_SSPM, "sspm_ck", "sspm_sel", 1, 1),
FACTOR(CLK_TOP_DXCC, "dxcc_ck", "dxcc_sel", 1, 1),
FACTOR(CLK_TOP_I2C, "i2c_ck", "i2c_sel", 1, 1),
FACTOR(CLK_TOP_F_FPWM, "f_fpwm_ck", "pwm_sel", 1, 1),
FACTOR(CLK_TOP_F_FSENINF, "f_fseninf_ck", "seninf_sel", 1, 1),
FACTOR(CLK_TOP_AES_FDE, "aes_fde_ck", "aes_fde_sel", 1, 1),
FACTOR(CLK_TOP_F_BIST2FPC, "f_bist2fpc_ck", "univpll2_d2", 1, 1),
FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL0, "arm_div_pll0", "syspll_d2", 1, 1),
FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL1, "arm_div_pll1", "syspll_ck", 1, 1),
FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL2, "arm_div_pll2", "univpll_d2", 1, 1),
FACTOR(CLK_TOP_DA_USB20_48M_DIV,
"usb20_48m_div", "usb20_192m_d4", 1, 1),
FACTOR(CLK_TOP_DA_UNIV_48M_DIV, "univ_48m_div", "usb20_192m_d4", 1, 1),
};
static const char * const axi_parents[] = {
"clk26m",
"syspll_d7",
"syspll1_d4",
"syspll3_d2"
};
static const char * const mem_parents[] = {
"clk26m",
"dmpll_ck",
"apll1_ck"
};
static const char * const mm_parents[] = {
"clk26m",
"mmpll_ck",
"syspll1_d2",
"syspll_d5",
"syspll1_d4",
"univpll_d5",
"univpll1_d2",
"mmpll_d2"
};
static const char * const scp_parents[] = {
"clk26m",
"syspll4_d2",
"univpll2_d2",
"syspll1_d2",
"univpll1_d2",
"syspll_d3",
"univpll_d3"
};
static const char * const mfg_parents[] = {
"clk26m",
"mfgpll_ck",
"syspll_d3",
"univpll_d3"
};
static const char * const atb_parents[] = {
"clk26m",
"syspll1_d4",
"syspll1_d2"
};
static const char * const camtg_parents[] = {
"clk26m",
"usb20_192m_d8",
"univpll2_d8",
"usb20_192m_d4",
"univpll2_d32",
"usb20_192m_d16",
"usb20_192m_d32"
};
static const char * const uart_parents[] = {
"clk26m",
"univpll2_d8"
};
static const char * const spi_parents[] = {
"clk26m",
"syspll3_d2",
"syspll4_d2",
"syspll2_d4"
};
static const char * const msdc5hclk_parents[] = {
"clk26m",
"syspll1_d2",
"univpll1_d4",
"syspll2_d2"
};
static const char * const msdc50_0_parents[] = {
"clk26m",
"msdcpll_ck",
"syspll2_d2",
"syspll4_d2",
"univpll1_d2",
"syspll1_d2",
"univpll_d5",
"univpll1_d4"
};
static const char * const msdc30_1_parents[] = {
"clk26m",
"msdcpll_d2",
"univpll2_d2",
"syspll2_d2",
"syspll1_d4",
"univpll1_d4",
"usb20_192m_d4",
"syspll2_d4"
};
static const char * const audio_parents[] = {
"clk26m",
"syspll3_d4",
"syspll4_d4",
"syspll1_d16"
};
static const char * const aud_intbus_parents[] = {
"clk26m",
"syspll1_d4",
"syspll4_d2"
};
static const char * const aud_1_parents[] = {
"clk26m",
"apll1_ck"
};
static const char * const aud_engen1_parents[] = {
"clk26m",
"apll1_d2",
"apll1_d4",
"apll1_d8"
};
static const char * const disp_pwm_parents[] = {
"clk26m",
"univpll2_d4",
"ulposc1_d2",
"ulposc1_d8"
};
static const char * const sspm_parents[] = {
"clk26m",
"syspll1_d2",
"syspll_d3"
};
static const char * const dxcc_parents[] = {
"clk26m",
"syspll1_d2",
"syspll1_d4",
"syspll1_d8"
};
static const char * const usb_top_parents[] = {
"clk26m",
"univpll3_d4"
};
static const char * const spm_parents[] = {
"clk26m",
"syspll1_d8"
};
static const char * const i2c_parents[] = {
"clk26m",
"univpll3_d4",
"univpll3_d2",
"syspll1_d8",
"syspll2_d8"
};
static const char * const pwm_parents[] = {
"clk26m",
"univpll3_d4",
"syspll1_d8"
};
static const char * const seninf_parents[] = {
"clk26m",
"univpll1_d4",
"univpll1_d2",
"univpll2_d2"
};
static const char * const aes_fde_parents[] = {
"clk26m",
"msdcpll_ck",
"univpll_d3",
"univpll2_d2",
"univpll1_d2",
"syspll1_d2"
};
static const char * const ulposc_parents[] = {
"clk26m",
"ulposc1_d4",
"ulposc1_d8",
"ulposc1_d16",
"ulposc1_d32"
};
static const char * const camtm_parents[] = {
"clk26m",
"univpll1_d4",
"univpll1_d2",
"univpll2_d2"
};
#define INVALID_UPDATE_REG 0xFFFFFFFF
#define INVALID_UPDATE_SHIFT -1
#define INVALID_MUX_GATE -1
static const struct mtk_mux top_muxes[] = {
/* CLK_CFG_0 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
0, 2, 7, CLK_CFG_UPDATE, 0,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
8, 2, 15, CLK_CFG_UPDATE, 1,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0,
CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 3, 23,
CLK_CFG_UPDATE, 2),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, CLK_CFG_0,
CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31,
CLK_CFG_UPDATE, 3),
/* CLK_CFG_1 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, CLK_CFG_1,
CLK_CFG_1_SET, CLK_CFG_1_CLR, 0, 2, 7,
CLK_CFG_UPDATE, 4),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, CLK_CFG_1,
CLK_CFG_1_SET, CLK_CFG_1_CLR, 8, 2, 15,
CLK_CFG_UPDATE, 5),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
camtg_parents, CLK_CFG_1, CLK_CFG_1_SET,
CLK_CFG_1_CLR, 16, 3, 23, CLK_CFG_UPDATE, 6),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents,
CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR,
24, 3, 31, CLK_CFG_UPDATE, 7),
/* CLK_CFG_2 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel",
camtg_parents, CLK_CFG_2, CLK_CFG_2_SET,
CLK_CFG_2_CLR, 0, 3, 7, CLK_CFG_UPDATE, 8),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel", camtg_parents,
CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR,
8, 3, 15, CLK_CFG_UPDATE, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 16, 1, 23,
CLK_CFG_UPDATE, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, CLK_CFG_2,
CLK_CFG_2_SET, CLK_CFG_2_CLR, 24, 2, 31,
CLK_CFG_UPDATE, 11),
/* CLK_CFG_3 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk",
msdc5hclk_parents, CLK_CFG_3, CLK_CFG_3_SET,
CLK_CFG_3_CLR, 0, 2, 7, CLK_CFG_UPDATE, 12, 0),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
msdc50_0_parents, CLK_CFG_3, CLK_CFG_3_SET,
CLK_CFG_3_CLR, 8, 3, 15, CLK_CFG_UPDATE, 13, 0),
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
msdc30_1_parents, CLK_CFG_3, CLK_CFG_3_SET,
CLK_CFG_3_CLR, 16, 3, 23, CLK_CFG_UPDATE, 14, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR,
24, 2, 31, CLK_CFG_UPDATE, 15),
/* CLK_CFG_4 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
aud_intbus_parents, CLK_CFG_4, CLK_CFG_4_SET,
CLK_CFG_4_CLR, 0, 2, 7, CLK_CFG_UPDATE, 16),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents,
CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR,
8, 1, 15, CLK_CFG_UPDATE, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
aud_engen1_parents, CLK_CFG_4, CLK_CFG_4_SET,
CLK_CFG_4_CLR, 16, 2, 23, CLK_CFG_UPDATE, 18),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
disp_pwm_parents, CLK_CFG_4, CLK_CFG_4_SET,
CLK_CFG_4_CLR, 24, 2, 31, CLK_CFG_UPDATE, 19),
/* CLK_CFG_5 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPM_SEL, "sspm_sel", sspm_parents,
CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 0, 2, 7,
CLK_CFG_UPDATE, 20),
MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents,
CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 8, 2, 15,
CLK_CFG_UPDATE, 21),
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL, "usb_top_sel",
usb_top_parents, CLK_CFG_5, CLK_CFG_5_SET,
CLK_CFG_5_CLR, 16, 1, 23, CLK_CFG_UPDATE, 22),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPM_SEL, "spm_sel", spm_parents, CLK_CFG_5,
CLK_CFG_5_SET, CLK_CFG_5_CLR, 24, 1, 31,
CLK_CFG_UPDATE, 23),
/* CLK_CFG_6 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, CLK_CFG_6,
CLK_CFG_6_SET, CLK_CFG_6_CLR, 0, 3, 7, CLK_CFG_UPDATE,
24),
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, CLK_CFG_6,
CLK_CFG_6_SET, CLK_CFG_6_CLR, 8, 2, 15, CLK_CFG_UPDATE,
25),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel", seninf_parents,
CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 16, 2, 23,
CLK_CFG_UPDATE, 26),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE_SEL, "aes_fde_sel",
aes_fde_parents, CLK_CFG_6, CLK_CFG_6_SET,
CLK_CFG_6_CLR, 24, 3, 31, CLK_CFG_UPDATE, 27),
/* CLK_CFG_7 */
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRAP_ULPOSC_SEL, "ulposc_sel",
ulposc_parents, CLK_CFG_7, CLK_CFG_7_SET,
CLK_CFG_7_CLR, 0, 3, 7, CLK_CFG_UPDATE, 28,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", camtm_parents,
CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 8, 2, 15,
CLK_CFG_UPDATE, 29),
};
static const struct mtk_gate_regs top0_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x0,
.sta_ofs = 0x0,
};
static const struct mtk_gate_regs top1_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x104,
.sta_ofs = 0x104,
};
static const struct mtk_gate_regs top2_cg_regs = {
.set_ofs = 0x320,
.clr_ofs = 0x320,
.sta_ofs = 0x320,
};
#define GATE_TOP0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
#define GATE_TOP1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
#define GATE_TOP2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate top_clks[] = {
/* TOP0 */
GATE_TOP0(CLK_TOP_MD_32K, "md_32k", "f_frtc_ck", 8),
GATE_TOP0(CLK_TOP_MD_26M, "md_26m", "f_f26m_ck", 9),
GATE_TOP0(CLK_TOP_MD2_32K, "md2_32k", "f_frtc_ck", 10),
GATE_TOP0(CLK_TOP_MD2_26M, "md2_26m", "f_f26m_ck", 11),
/* TOP1 */
GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL0_EN,
"arm_div_pll0_en", "arm_div_pll0", 3),
GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL1_EN,
"arm_div_pll1_en", "arm_div_pll1", 4),
GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL2_EN,
"arm_div_pll2_en", "arm_div_pll2", 5),
GATE_TOP1(CLK_TOP_FMEM_OCC_DRC_EN, "drc_en", "univpll2_d2", 6),
GATE_TOP1(CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_48m_div", 8),
GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "univ_48m_div", 9),
GATE_TOP1(CLK_TOP_F_UFS_MP_SAP_CFG_EN, "ufs_sap", "f_f26m_ck", 12),
GATE_TOP1(CLK_TOP_F_BIST2FPC_EN, "bist2fpc", "f_bist2fpc_ck", 16),
/* TOP2 */
GATE_TOP2(CLK_TOP_APLL12_DIV0, "apll12_div0", "aud_1_ck", 2),
GATE_TOP2(CLK_TOP_APLL12_DIV1, "apll12_div1", "aud_1_ck", 3),
GATE_TOP2(CLK_TOP_APLL12_DIV2, "apll12_div2", "aud_1_ck", 4),
GATE_TOP2(CLK_TOP_APLL12_DIV3, "apll12_div3", "aud_1_ck", 5),
};
static const struct mtk_gate_regs ifr2_cg_regs = {
.set_ofs = 0x80,
.clr_ofs = 0x84,
.sta_ofs = 0x90,
};
static const struct mtk_gate_regs ifr3_cg_regs = {
.set_ofs = 0x88,
.clr_ofs = 0x8c,
.sta_ofs = 0x94,
};
static const struct mtk_gate_regs ifr4_cg_regs = {
.set_ofs = 0xa4,
.clr_ofs = 0xa8,
.sta_ofs = 0xac,
};
static const struct mtk_gate_regs ifr5_cg_regs = {
.set_ofs = 0xc0,
.clr_ofs = 0xc4,
.sta_ofs = 0xc8,
};
#define GATE_IFR2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ifr2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_IFR3(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ifr3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_IFR4(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ifr4_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_IFR5(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ifr5_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate ifr_clks[] = {
/* INFRA_TOPAXI */
/* INFRA PERI */
/* INFRA mode 0 */
GATE_IFR2(CLK_IFR_ICUSB, "ifr_icusb", "axi_ck", 8),
GATE_IFR2(CLK_IFR_GCE, "ifr_gce", "axi_ck", 9),
GATE_IFR2(CLK_IFR_THERM, "ifr_therm", "axi_ck", 10),
GATE_IFR2(CLK_IFR_I2C_AP, "ifr_i2c_ap", "i2c_ck", 11),
GATE_IFR2(CLK_IFR_I2C_CCU, "ifr_i2c_ccu", "i2c_ck", 12),
GATE_IFR2(CLK_IFR_I2C_SSPM, "ifr_i2c_sspm", "i2c_ck", 13),
GATE_IFR2(CLK_IFR_I2C_RSV, "ifr_i2c_rsv", "i2c_ck", 14),
GATE_IFR2(CLK_IFR_PWM_HCLK, "ifr_pwm_hclk", "axi_ck", 15),
GATE_IFR2(CLK_IFR_PWM1, "ifr_pwm1", "f_fpwm_ck", 16),
GATE_IFR2(CLK_IFR_PWM2, "ifr_pwm2", "f_fpwm_ck", 17),
GATE_IFR2(CLK_IFR_PWM3, "ifr_pwm3", "f_fpwm_ck", 18),
GATE_IFR2(CLK_IFR_PWM4, "ifr_pwm4", "f_fpwm_ck", 19),
GATE_IFR2(CLK_IFR_PWM5, "ifr_pwm5", "f_fpwm_ck", 20),
GATE_IFR2(CLK_IFR_PWM, "ifr_pwm", "f_fpwm_ck", 21),
GATE_IFR2(CLK_IFR_UART0, "ifr_uart0", "f_fuart_ck", 22),
GATE_IFR2(CLK_IFR_UART1, "ifr_uart1", "f_fuart_ck", 23),
GATE_IFR2(CLK_IFR_GCE_26M, "ifr_gce_26m", "f_f26m_ck", 27),
GATE_IFR2(CLK_IFR_CQ_DMA_FPC, "ifr_dma", "axi_ck", 28),
GATE_IFR2(CLK_IFR_BTIF, "ifr_btif", "axi_ck", 31),
/* INFRA mode 1 */
GATE_IFR3(CLK_IFR_SPI0, "ifr_spi0", "spi_ck", 1),
GATE_IFR3(CLK_IFR_MSDC0, "ifr_msdc0", "msdc5hclk", 2),
GATE_IFR3(CLK_IFR_MSDC1, "ifr_msdc1", "axi_ck", 4),
GATE_IFR3(CLK_IFR_TRNG, "ifr_trng", "axi_ck", 9),
GATE_IFR3(CLK_IFR_AUXADC, "ifr_auxadc", "f_f26m_ck", 10),
GATE_IFR3(CLK_IFR_CCIF1_AP, "ifr_ccif1_ap", "axi_ck", 12),
GATE_IFR3(CLK_IFR_CCIF1_MD, "ifr_ccif1_md", "axi_ck", 13),
GATE_IFR3(CLK_IFR_AUXADC_MD, "ifr_auxadc_md", "f_f26m_ck", 14),
GATE_IFR3(CLK_IFR_AP_DMA, "ifr_ap_dma", "axi_ck", 18),
GATE_IFR3(CLK_IFR_DEVICE_APC, "ifr_dapc", "axi_ck", 20),
GATE_IFR3(CLK_IFR_CCIF_AP, "ifr_ccif_ap", "axi_ck", 23),
GATE_IFR3(CLK_IFR_AUDIO, "ifr_audio", "axi_ck", 25),
GATE_IFR3(CLK_IFR_CCIF_MD, "ifr_ccif_md", "axi_ck", 26),
/* INFRA mode 2 */
GATE_IFR4(CLK_IFR_RG_PWM_FBCLK6, "ifr_pwmfb", "f_f26m_ck", 0),
GATE_IFR4(CLK_IFR_DISP_PWM, "ifr_disp_pwm", "f_fdisp_pwm_ck", 2),
GATE_IFR4(CLK_IFR_CLDMA_BCLK, "ifr_cldmabclk", "axi_ck", 3),
GATE_IFR4(CLK_IFR_AUDIO_26M_BCLK, "ifr_audio26m", "f_f26m_ck", 4),
GATE_IFR4(CLK_IFR_SPI1, "ifr_spi1", "spi_ck", 6),
GATE_IFR4(CLK_IFR_I2C4, "ifr_i2c4", "i2c_ck", 7),
GATE_IFR4(CLK_IFR_SPI2, "ifr_spi2", "spi_ck", 9),
GATE_IFR4(CLK_IFR_SPI3, "ifr_spi3", "spi_ck", 10),
GATE_IFR4(CLK_IFR_I2C5, "ifr_i2c5", "i2c_ck", 18),
GATE_IFR4(CLK_IFR_I2C5_ARBITER, "ifr_i2c5a", "i2c_ck", 19),
GATE_IFR4(CLK_IFR_I2C5_IMM, "ifr_i2c5_imm", "i2c_ck", 20),
GATE_IFR4(CLK_IFR_I2C1_ARBITER, "ifr_i2c1a", "i2c_ck", 21),
GATE_IFR4(CLK_IFR_I2C1_IMM, "ifr_i2c1_imm", "i2c_ck", 22),
GATE_IFR4(CLK_IFR_I2C2_ARBITER, "ifr_i2c2a", "i2c_ck", 23),
GATE_IFR4(CLK_IFR_I2C2_IMM, "ifr_i2c2_imm", "i2c_ck", 24),
GATE_IFR4(CLK_IFR_SPI4, "ifr_spi4", "spi_ck", 25),
GATE_IFR4(CLK_IFR_SPI5, "ifr_spi5", "spi_ck", 26),
GATE_IFR4(CLK_IFR_CQ_DMA, "ifr_cq_dma", "axi_ck", 27),
GATE_IFR4(CLK_IFR_FAES_FDE, "ifr_faes_fde_ck", "aes_fde_ck", 29),
/* INFRA mode 3 */
GATE_IFR5(CLK_IFR_MSDC0_SELF, "ifr_msdc0sf", "msdc50_0_ck", 0),
GATE_IFR5(CLK_IFR_MSDC1_SELF, "ifr_msdc1sf", "msdc50_0_ck", 1),
GATE_IFR5(CLK_IFR_I2C6, "ifr_i2c6", "i2c_ck", 6),
GATE_IFR5(CLK_IFR_AP_MSDC0, "ifr_ap_msdc0", "msdc50_0_ck", 7),
GATE_IFR5(CLK_IFR_MD_MSDC0, "ifr_md_msdc0", "msdc50_0_ck", 8),
GATE_IFR5(CLK_IFR_MSDC0_SRC, "ifr_msdc0_clk", "msdc50_0_ck", 9),
GATE_IFR5(CLK_IFR_MSDC1_SRC, "ifr_msdc1_clk", "msdc30_1_ck", 10),
GATE_IFR5(CLK_IFR_MCU_PM_BCLK, "ifr_mcu_pm_bclk", "axi_ck", 17),
GATE_IFR5(CLK_IFR_CCIF2_AP, "ifr_ccif2_ap", "axi_ck", 18),
GATE_IFR5(CLK_IFR_CCIF2_MD, "ifr_ccif2_md", "axi_ck", 19),
GATE_IFR5(CLK_IFR_CCIF3_AP, "ifr_ccif3_ap", "axi_ck", 20),
GATE_IFR5(CLK_IFR_CCIF3_MD, "ifr_ccif3_md", "axi_ck", 21),
};
/* additional CCF control for mipi26M race condition(disp/camera) */
static const struct mtk_gate_regs apmixed_cg_regs = {
.set_ofs = 0x14,
.clr_ofs = 0x14,
.sta_ofs = 0x14,
};
#define GATE_APMIXED(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate apmixed_clks[] = {
/* AUDIO0 */
GATE_APMIXED(CLK_APMIXED_SSUSB26M, "apmixed_ssusb26m", "f_f26m_ck",
4),
GATE_APMIXED(CLK_APMIXED_APPLL26M, "apmixed_appll26m", "f_f26m_ck",
5),
GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", "f_f26m_ck",
6),
GATE_APMIXED(CLK_APMIXED_MDPLLGP26M, "apmixed_mdpll26m", "f_f26m_ck",
7),
GATE_APMIXED(CLK_APMIXED_MMSYS_F26M, "apmixed_mmsys26m", "f_f26m_ck",
8),
GATE_APMIXED(CLK_APMIXED_UFS26M, "apmixed_ufs26m", "f_f26m_ck",
9),
GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", "f_f26m_ck",
11),
GATE_APMIXED(CLK_APMIXED_MEMPLL26M, "apmixed_mempll26m", "f_f26m_ck",
13),
GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
"f_f26m_ck", 14),
GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", "f_f26m_ck",
16),
};
#define MT6765_PLL_FMAX (3800UL * MHZ)
#define MT6765_PLL_FMIN (1500UL * MHZ)
#define CON0_MT6765_RST_BAR BIT(23)
#define PLL_INFO_NULL (0xFF)
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pcwibits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,\
_tuner_en_bit, _pcw_reg, _pcw_shift, _div_table) {\
.id = _id, \
.name = _name, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = _en_mask, \
.flags = _flags, \
.rst_bar_mask = CON0_MT6765_RST_BAR, \
.fmax = MT6765_PLL_FMAX, \
.fmin = MT6765_PLL_FMIN, \
.pcwbits = _pcwbits, \
.pcwibits = _pcwibits, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, \
.tuner_en_reg = _tuner_en_reg, \
.tuner_en_bit = _tuner_en_bit, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
.div_table = _div_table, \
}
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pcwibits, _pd_reg, _pd_shift, _tuner_reg, \
_tuner_en_reg, _tuner_en_bit, _pcw_reg, \
_pcw_shift) \
PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
_pcwbits, _pcwibits, _pd_reg, _pd_shift, \
_tuner_reg, _tuner_en_reg, _tuner_en_bit, \
_pcw_reg, _pcw_shift, NULL) \
static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x021C, 0x0228, 0,
PLL_AO, 22, 8, 0x0220, 24, 0, 0, 0, 0x0220, 0),
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, 0,
PLL_AO, 22, 8, 0x0210, 24, 0, 0, 0, 0x0210, 0),
PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x022C, 0x0238, 0,
PLL_AO, 22, 8, 0x0230, 24, 0, 0, 0, 0x0230, 0),
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x023C, 0x0248, 0,
(HAVE_RST_BAR | PLL_AO), 22, 8, 0x0240, 24, 0, 0, 0, 0x0240,
0),
PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x024C, 0x0258, 0,
0, 22, 8, 0x0250, 24, 0, 0, 0, 0x0250, 0),
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x025C, 0x0268, 0,
0, 22, 8, 0x0260, 24, 0, 0, 0, 0x0260, 0),
PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x026C, 0x0278, 0,
HAVE_RST_BAR, 22, 8, 0x0270, 24, 0, 0, 0, 0x0270, 0),
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x027C, 0x0288, 0,
0, 22, 8, 0x0280, 24, 0, 0, 0, 0x0280, 0),
PLL(CLK_APMIXED_APLL1, "apll1", 0x028C, 0x029C, 0,
0, 32, 8, 0x0290, 24, 0x0040, 0x000C, 0, 0x0294, 0),
PLL(CLK_APMIXED_MPLL, "mpll", 0x02A0, 0x02AC, 0,
PLL_AO, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0),
};
static int clk_mt6765_apmixed_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
void __iomem *base;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
ARRAY_SIZE(apmixed_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
apmixed_base = base;
/* MPLL, CCIPLL, MAINPLL set HW mode, TDCLKSQ, CLKSQ1 */
writel(readl(AP_PLL_CON3) & 0xFFFFFFE1, AP_PLL_CON3);
writel(readl(PLLON_CON0) & 0x01041041, PLLON_CON0);
writel(readl(PLLON_CON1) & 0x01041041, PLLON_CON1);
return r;
}
static int clk_mt6765_top_probe(struct platform_device *pdev)
{
int r;
struct device_node *node = pdev->dev.of_node;
void __iomem *base;
struct clk_hw_onecell_data *clk_data;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks),
clk_data);
mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
clk_data);
mtk_clk_register_muxes(&pdev->dev, top_muxes,
ARRAY_SIZE(top_muxes), node,
&mt6765_clk_lock, clk_data);
mtk_clk_register_gates(&pdev->dev, node, top_clks,
ARRAY_SIZE(top_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
cksys_base = base;
/* [4]:no need */
writel(readl(CLK_SCP_CFG_0) | 0x3EF, CLK_SCP_CFG_0);
/*[1,2,3,8]: no need*/
writel(readl(CLK_SCP_CFG_1) | 0x1, CLK_SCP_CFG_1);
return r;
}
static int clk_mt6765_ifr_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
void __iomem *base;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
mtk_clk_register_gates(&pdev->dev, node, ifr_clks,
ARRAY_SIZE(ifr_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
return r;
}
static const struct of_device_id of_match_clk_mt6765[] = {
{
.compatible = "mediatek,mt6765-apmixedsys",
.data = clk_mt6765_apmixed_probe,
}, {
.compatible = "mediatek,mt6765-topckgen",
.data = clk_mt6765_top_probe,
}, {
.compatible = "mediatek,mt6765-infracfg",
.data = clk_mt6765_ifr_probe,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6765);
static int clk_mt6765_probe(struct platform_device *pdev)
{
int (*clk_probe)(struct platform_device *d);
int r;
clk_probe = of_device_get_match_data(&pdev->dev);
if (!clk_probe)
return -EINVAL;
r = clk_probe(pdev);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
return r;
}
static struct platform_driver clk_mt6765_drv = {
.probe = clk_mt6765_probe,
.driver = {
.name = "clk-mt6765",
.of_match_table = of_match_clk_mt6765,
},
};
static int __init clk_mt6765_init(void)
{
return platform_driver_register(&clk_mt6765_drv);
}
arch_initcall(clk_mt6765_init);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6765.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Shunli Wang <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt2701-clk.h>
static const struct mtk_gate_regs disp0_cg_regs = {
.set_ofs = 0x0104,
.clr_ofs = 0x0108,
.sta_ofs = 0x0100,
};
static const struct mtk_gate_regs disp1_cg_regs = {
.set_ofs = 0x0114,
.clr_ofs = 0x0118,
.sta_ofs = 0x0110,
};
#define GATE_DISP0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &disp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_DISP1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &disp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate mm_clks[] = {
GATE_DISP0(CLK_MM_SMI_COMMON, "mm_smi_comm", "mm_sel", 0),
GATE_DISP0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
GATE_DISP0(CLK_MM_CMDQ, "mm_cmdq", "mm_sel", 2),
GATE_DISP0(CLK_MM_MUTEX, "mm_mutex", "mm_sel", 3),
GATE_DISP0(CLK_MM_DISP_COLOR, "mm_disp_color", "mm_sel", 4),
GATE_DISP0(CLK_MM_DISP_BLS, "mm_disp_bls", "mm_sel", 5),
GATE_DISP0(CLK_MM_DISP_WDMA, "mm_disp_wdma", "mm_sel", 6),
GATE_DISP0(CLK_MM_DISP_RDMA, "mm_disp_rdma", "mm_sel", 7),
GATE_DISP0(CLK_MM_DISP_OVL, "mm_disp_ovl", "mm_sel", 8),
GATE_DISP0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 9),
GATE_DISP0(CLK_MM_MDP_WROT, "mm_mdp_wrot", "mm_sel", 10),
GATE_DISP0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
GATE_DISP0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 12),
GATE_DISP0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 13),
GATE_DISP0(CLK_MM_MDP_RDMA, "mm_mdp_rdma", "mm_sel", 14),
GATE_DISP0(CLK_MM_MDP_BLS_26M, "mm_mdp_bls_26m", "pwm_sel", 15),
GATE_DISP0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 16),
GATE_DISP0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 17),
GATE_DISP0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 18),
GATE_DISP0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
GATE_DISP0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 20),
GATE_DISP1(CLK_MM_DSI_ENGINE, "mm_dsi_eng", "mm_sel", 0),
GATE_DISP1(CLK_MM_DSI_DIG, "mm_dsi_dig", "dsi0_lntc_dsi", 1),
GATE_DISP1(CLK_MM_DPI_DIGL, "mm_dpi_digl", "dpi0_sel", 2),
GATE_DISP1(CLK_MM_DPI_ENGINE, "mm_dpi_eng", "mm_sel", 3),
GATE_DISP1(CLK_MM_DPI1_DIGL, "mm_dpi1_digl", "dpi1_sel", 4),
GATE_DISP1(CLK_MM_DPI1_ENGINE, "mm_dpi1_eng", "mm_sel", 5),
GATE_DISP1(CLK_MM_TVE_OUTPUT, "mm_tve_output", "tve_sel", 6),
GATE_DISP1(CLK_MM_TVE_INPUT, "mm_tve_input", "dpi0_sel", 7),
GATE_DISP1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi1_sel", 8),
GATE_DISP1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmi_sel", 9),
GATE_DISP1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll_sel", 10),
GATE_DISP1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll_sel", 11),
GATE_DISP1(CLK_MM_TVE_FMM, "mm_tve_fmm", "mm_sel", 14),
};
static const struct mtk_clk_desc mm_desc = {
.clks = mm_clks,
.num_clks = ARRAY_SIZE(mm_clks),
};
static const struct platform_device_id clk_mt2701_mm_id_table[] = {
{ .name = "clk-mt2701-mm", .driver_data = (kernel_ulong_t)&mm_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, clk_mt2701_mm_id_table);
static struct platform_driver clk_mt2701_mm_drv = {
.probe = mtk_clk_pdev_probe,
.remove_new = mtk_clk_pdev_remove,
.driver = {
.name = "clk-mt2701-mm",
},
.id_table = clk_mt2701_mm_id_table,
};
module_platform_driver(clk_mt2701_mm_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt2701-mm.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 MediaTek Inc.
* Copyright (c) 2020 BayLibre, SAS
* Author: James Liao <[email protected]>
* Fabien Parent <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8167-clk.h>
static const struct mtk_gate_regs img_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_IMG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate img_clks[] = {
GATE_IMG(CLK_IMG_LARB1_SMI, "img_larb1_smi", "smi_mm", 0),
GATE_IMG(CLK_IMG_CAM_SMI, "img_cam_smi", "smi_mm", 5),
GATE_IMG(CLK_IMG_CAM_CAM, "img_cam_cam", "smi_mm", 6),
GATE_IMG(CLK_IMG_SEN_TG, "img_sen_tg", "cam_mm", 7),
GATE_IMG(CLK_IMG_SEN_CAM, "img_sen_cam", "smi_mm", 8),
GATE_IMG(CLK_IMG_VENC, "img_venc", "smi_mm", 9),
};
static const struct mtk_clk_desc img_desc = {
.clks = img_clks,
.num_clks = ARRAY_SIZE(img_clks),
};
static const struct of_device_id of_match_clk_mt8167_imgsys[] = {
{ .compatible = "mediatek,mt8167-imgsys", .data = &img_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_imgsys);
static struct platform_driver clk_mt8167_imgsys_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8167-imgsys",
.of_match_table = of_match_clk_mt8167_imgsys,
},
};
module_platform_driver(clk_mt8167_imgsys_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8167-img.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 Collabora Ltd.
* Author: AngeloGioacchino Del Regno <[email protected]>
*/
#include <dt-bindings/clock/mediatek,mt6795-clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#define GATE_VDEC(_id, _name, _parent, _regs) \
GATE_MTK(_id, _name, _parent, _regs, 0, \
&mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate_regs vdec0_cg_regs = {
.set_ofs = 0x0000,
.clr_ofs = 0x0004,
.sta_ofs = 0x0000,
};
static const struct mtk_gate_regs vdec1_cg_regs = {
.set_ofs = 0x0008,
.clr_ofs = 0x000c,
.sta_ofs = 0x0008,
};
static const struct mtk_gate vdec_clks[] = {
GATE_VDEC(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", &vdec0_cg_regs),
GATE_VDEC(CLK_VDEC_LARB_CKEN, "vdec_larb_cken", "mm_sel", &vdec1_cg_regs),
};
static const struct mtk_clk_desc vdec_desc = {
.clks = vdec_clks,
.num_clks = ARRAY_SIZE(vdec_clks),
};
static const struct of_device_id of_match_clk_mt6795_vdecsys[] = {
{ .compatible = "mediatek,mt6795-vdecsys", .data = &vdec_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_vdecsys);
static struct platform_driver clk_mt6795_vdecsys_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt6795-vdecsys",
.of_match_table = of_match_clk_mt6795_vdecsys,
},
};
module_platform_driver(clk_mt6795_vdecsys_drv);
MODULE_DESCRIPTION("MediaTek MT6795 vdecsys clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6795-vdecsys.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Garmin Chang <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs vdo1_0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs vdo1_1_cg_regs = {
.set_ofs = 0x114,
.clr_ofs = 0x118,
.sta_ofs = 0x110,
};
static const struct mtk_gate_regs vdo1_2_cg_regs = {
.set_ofs = 0x124,
.clr_ofs = 0x128,
.sta_ofs = 0x120,
};
static const struct mtk_gate_regs vdo1_3_cg_regs = {
.set_ofs = 0x134,
.clr_ofs = 0x138,
.sta_ofs = 0x130,
};
static const struct mtk_gate_regs vdo1_4_cg_regs = {
.set_ofs = 0x144,
.clr_ofs = 0x148,
.sta_ofs = 0x140,
};
#define GATE_VDO1_0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO1_1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO1_2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO1_3(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_VDO1_3_FLAGS(_id, _name, _parent, _shift, _flags) \
GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_3_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, _flags)
#define GATE_VDO1_4(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &vdo1_4_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate vdo1_clks[] = {
/* VDO1_0 */
GATE_VDO1_0(CLK_VDO1_SMI_LARB2, "vdo1_smi_larb2", "top_vpp", 0),
GATE_VDO1_0(CLK_VDO1_SMI_LARB3, "vdo1_smi_larb3", "top_vpp", 1),
GATE_VDO1_0(CLK_VDO1_GALS, "vdo1_gals", "top_vpp", 2),
GATE_VDO1_0(CLK_VDO1_FAKE_ENG0, "vdo1_fake_eng0", "top_vpp", 3),
GATE_VDO1_0(CLK_VDO1_FAKE_ENG1, "vdo1_fake_eng1", "top_vpp", 4),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA0, "vdo1_mdp_rdma0", "top_vpp", 5),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA1, "vdo1_mdp_rdma1", "top_vpp", 6),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA2, "vdo1_mdp_rdma2", "top_vpp", 7),
GATE_VDO1_0(CLK_VDO1_MDP_RDMA3, "vdo1_mdp_rdma3", "top_vpp", 8),
GATE_VDO1_0(CLK_VDO1_VPP_MERGE0, "vdo1_vpp_merge0", "top_vpp", 9),
GATE_VDO1_0(CLK_VDO1_VPP_MERGE1, "vdo1_vpp_merge1", "top_vpp", 10),
GATE_VDO1_0(CLK_VDO1_VPP_MERGE2, "vdo1_vpp_merge2", "top_vpp", 11),
/* VDO1_1 */
GATE_VDO1_1(CLK_VDO1_VPP_MERGE3, "vdo1_vpp_merge3", "top_vpp", 0),
GATE_VDO1_1(CLK_VDO1_VPP_MERGE4, "vdo1_vpp_merge4", "top_vpp", 1),
GATE_VDO1_1(CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC, "vdo1_vpp2_to_vdo1_dl_async", "top_vpp", 2),
GATE_VDO1_1(CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC, "vdo1_vpp3_to_vdo1_dl_async", "top_vpp", 3),
GATE_VDO1_1(CLK_VDO1_DISP_MUTEX, "vdo1_disp_mutex", "top_vpp", 4),
GATE_VDO1_1(CLK_VDO1_MDP_RDMA4, "vdo1_mdp_rdma4", "top_vpp", 5),
GATE_VDO1_1(CLK_VDO1_MDP_RDMA5, "vdo1_mdp_rdma5", "top_vpp", 6),
GATE_VDO1_1(CLK_VDO1_MDP_RDMA6, "vdo1_mdp_rdma6", "top_vpp", 7),
GATE_VDO1_1(CLK_VDO1_MDP_RDMA7, "vdo1_mdp_rdma7", "top_vpp", 8),
GATE_VDO1_1(CLK_VDO1_DP_INTF0_MMCK, "vdo1_dp_intf0_mmck", "top_vpp", 9),
GATE_VDO1_1(CLK_VDO1_DPI0_MM, "vdo1_dpi0_mm_ck", "top_vpp", 10),
GATE_VDO1_1(CLK_VDO1_DPI1_MM, "vdo1_dpi1_mm_ck", "top_vpp", 11),
GATE_VDO1_1(CLK_VDO1_MERGE0_DL_ASYNC, "vdo1_merge0_dl_async", "top_vpp", 13),
GATE_VDO1_1(CLK_VDO1_MERGE1_DL_ASYNC, "vdo1_merge1_dl_async", "top_vpp", 14),
GATE_VDO1_1(CLK_VDO1_MERGE2_DL_ASYNC, "vdo1_merge2_dl_async", "top_vpp", 15),
GATE_VDO1_1(CLK_VDO1_MERGE3_DL_ASYNC, "vdo1_merge3_dl_async", "top_vpp", 16),
GATE_VDO1_1(CLK_VDO1_MERGE4_DL_ASYNC, "vdo1_merge4_dl_async", "top_vpp", 17),
GATE_VDO1_1(CLK_VDO1_DSC_VDO1_DL_ASYNC, "vdo1_dsc_vdo1_dl_async", "top_vpp", 18),
GATE_VDO1_1(CLK_VDO1_MERGE_VDO1_DL_ASYNC, "vdo1_merge_vdo1_dl_async", "top_vpp", 19),
GATE_VDO1_1(CLK_VDO1_PADDING0, "vdo1_padding0", "top_vpp", 20),
GATE_VDO1_1(CLK_VDO1_PADDING1, "vdo1_padding1", "top_vpp", 21),
GATE_VDO1_1(CLK_VDO1_PADDING2, "vdo1_padding2", "top_vpp", 22),
GATE_VDO1_1(CLK_VDO1_PADDING3, "vdo1_padding3", "top_vpp", 23),
GATE_VDO1_1(CLK_VDO1_PADDING4, "vdo1_padding4", "top_vpp", 24),
GATE_VDO1_1(CLK_VDO1_PADDING5, "vdo1_padding5", "top_vpp", 25),
GATE_VDO1_1(CLK_VDO1_PADDING6, "vdo1_padding6", "top_vpp", 26),
GATE_VDO1_1(CLK_VDO1_PADDING7, "vdo1_padding7", "top_vpp", 27),
GATE_VDO1_1(CLK_VDO1_DISP_RSZ0, "vdo1_disp_rsz0", "top_vpp", 28),
GATE_VDO1_1(CLK_VDO1_DISP_RSZ1, "vdo1_disp_rsz1", "top_vpp", 29),
GATE_VDO1_1(CLK_VDO1_DISP_RSZ2, "vdo1_disp_rsz2", "top_vpp", 30),
GATE_VDO1_1(CLK_VDO1_DISP_RSZ3, "vdo1_disp_rsz3", "top_vpp", 31),
/* VDO1_2 */
GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE0, "vdo1_hdr_vdo_fe0", "top_vpp", 0),
GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE0, "vdo1_hdr_gfx_fe0", "top_vpp", 1),
GATE_VDO1_2(CLK_VDO1_HDR_VDO_BE, "vdo1_hdr_vdo_be", "top_vpp", 2),
GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE1, "vdo1_hdr_vdo_fe1", "top_vpp", 16),
GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE1, "vdo1_hdr_gfx_fe1", "top_vpp", 17),
GATE_VDO1_2(CLK_VDO1_DISP_MIXER, "vdo1_disp_mixer", "top_vpp", 18),
GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE0_DL_ASYNC, "vdo1_hdr_vdo_fe0_dl_async", "top_vpp", 19),
GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE1_DL_ASYNC, "vdo1_hdr_vdo_fe1_dl_async", "top_vpp", 20),
GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE0_DL_ASYNC, "vdo1_hdr_gfx_fe0_dl_async", "top_vpp", 21),
GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE1_DL_ASYNC, "vdo1_hdr_gfx_fe1_dl_async", "top_vpp", 22),
GATE_VDO1_2(CLK_VDO1_HDR_VDO_BE_DL_ASYNC, "vdo1_hdr_vdo_be_dl_async", "top_vpp", 23),
/* VDO1_3 */
GATE_VDO1_3(CLK_VDO1_DPI0, "vdo1_dpi0_ck", "top_vpp", 0),
GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPI0, "vdo1_disp_monitor_dpi0_ck", "top_vpp", 1),
GATE_VDO1_3(CLK_VDO1_DPI1, "vdo1_dpi1_ck", "top_vpp", 8),
GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPI1, "vdo1_disp_monitor_dpi1_ck", "top_vpp", 9),
GATE_VDO1_3_FLAGS(CLK_VDO1_DPINTF, "vdo1_dpintf", "top_dp", 16, CLK_SET_RATE_PARENT),
GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf_ck", "top_vpp", 17),
/* VDO1_4 */
GATE_VDO1_4(CLK_VDO1_26M_SLOW, "vdo1_26m_slow_ck", "clk26m", 8),
};
static const struct mtk_clk_desc vdo1_desc = {
.clks = vdo1_clks,
.num_clks = ARRAY_SIZE(vdo1_clks),
};
static const struct platform_device_id clk_mt8188_vdo1_id_table[] = {
{ .name = "clk-mt8188-vdo1", .driver_data = (kernel_ulong_t)&vdo1_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, clk_mt8188_vdo1_id_table);
static struct platform_driver clk_mt8188_vdo1_drv = {
.probe = mtk_clk_pdev_probe,
.remove_new = mtk_clk_pdev_remove,
.driver = {
.name = "clk-mt8188-vdo1",
},
.id_table = clk_mt8188_vdo1_id_table,
};
module_platform_driver(clk_mt8188_vdo1_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8188-vdo1.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt8186-clk.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs wpe_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x0,
.sta_ofs = 0x0,
};
#define GATE_WPE(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &wpe_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate wpe_clks[] = {
GATE_WPE(CLK_WPE_CK_EN, "wpe", "top_wpe", 17),
GATE_WPE(CLK_WPE_SMI_LARB8_CK_EN, "wpe_smi_larb8", "top_wpe", 19),
GATE_WPE(CLK_WPE_SYS_EVENT_TX_CK_EN, "wpe_sys_event_tx", "top_wpe", 20),
GATE_WPE(CLK_WPE_SMI_LARB8_PCLK_EN, "wpe_smi_larb8_p_en", "top_wpe", 25),
};
static const struct mtk_clk_desc wpe_desc = {
.clks = wpe_clks,
.num_clks = ARRAY_SIZE(wpe_clks),
};
static const struct of_device_id of_match_clk_mt8186_wpe[] = {
{
.compatible = "mediatek,mt8186-wpesys",
.data = &wpe_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_wpe);
static struct platform_driver clk_mt8186_wpe_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8186-wpe",
.of_match_table = of_match_clk_mt8186_wpe,
},
};
module_platform_driver(clk_mt8186_wpe_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8186-wpe.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019 MediaTek Inc.
* James Liao <[email protected]>
* Fabien Parent <[email protected]>
*
* Copyright (c) 2023 Collabora, Ltd.
* AngeloGioacchino Del Regno <[email protected]>
*/
#include <dt-bindings/clock/mt8516-clk.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-pll.h"
#define MT8516_PLL_FMAX (1502UL * MHZ)
#define CON0_MT8516_RST_BAR BIT(27)
#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
_pcw_shift, _div_table) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = _en_mask, \
.flags = _flags, \
.rst_bar_mask = CON0_MT8516_RST_BAR, \
.fmax = MT8516_PLL_FMAX, \
.pcwbits = _pcwbits, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
.div_table = _div_table, \
}
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
_pcw_shift) \
PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
NULL)
static const struct mtk_pll_div_table mmpll_div_table[] = {
{ .div = 0, .freq = MT8516_PLL_FMAX },
{ .div = 1, .freq = 1000000000 },
{ .div = 2, .freq = 604500000 },
{ .div = 3, .freq = 253500000 },
{ .div = 4, .freq = 126750000 },
{ } /* sentinel */
};
static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0,
21, 0x0104, 24, 0, 0x0104, 0),
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0,
HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0),
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000,
HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0),
PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0,
21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table),
PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0,
31, 0x0180, 1, 0x0194, 0x0184, 0),
PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0,
31, 0x01A0, 1, 0x01B4, 0x01A4, 0),
};
static int clk_mt8516_apmixed_probe(struct platform_device *pdev)
{
void __iomem *base;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
struct device *dev = &pdev->dev;
int ret;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK);
if (!clk_data)
return -ENOMEM;
ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
if (ret)
return ret;
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (ret)
goto unregister_plls;
return 0;
unregister_plls:
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
return ret;
}
static const struct of_device_id of_match_clk_mt8516_apmixed[] = {
{ .compatible = "mediatek,mt8516-apmixedsys" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8516_apmixed);
static struct platform_driver clk_mt8516_apmixed_drv = {
.probe = clk_mt8516_apmixed_probe,
.driver = {
.name = "clk-mt8516-apmixed",
.of_match_table = of_match_clk_mt8516_apmixed,
},
};
builtin_platform_driver(clk_mt8516_apmixed_drv)
MODULE_DESCRIPTION("MediaTek MT8516 apmixedsys clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8516-apmixedsys.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2018 MediaTek Inc.
// Author: Weiyi Lu <[email protected]>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8183-clk.h>
static const struct mtk_gate_regs img_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_IMG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr)
static const struct mtk_gate img_clks[] = {
GATE_IMG(CLK_IMG_LARB5, "img_larb5", "img_sel", 0),
GATE_IMG(CLK_IMG_LARB2, "img_larb2", "img_sel", 1),
GATE_IMG(CLK_IMG_DIP, "img_dip", "img_sel", 2),
GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "img_sel", 3),
GATE_IMG(CLK_IMG_DPE, "img_dpe", "img_sel", 4),
GATE_IMG(CLK_IMG_RSC, "img_rsc", "img_sel", 5),
GATE_IMG(CLK_IMG_MFB, "img_mfb", "img_sel", 6),
GATE_IMG(CLK_IMG_WPE_A, "img_wpe_a", "img_sel", 7),
GATE_IMG(CLK_IMG_WPE_B, "img_wpe_b", "img_sel", 8),
GATE_IMG(CLK_IMG_OWE, "img_owe", "img_sel", 9),
};
static const struct mtk_clk_desc img_desc = {
.clks = img_clks,
.num_clks = ARRAY_SIZE(img_clks),
};
static const struct of_device_id of_match_clk_mt8183_img[] = {
{
.compatible = "mediatek,mt8183-imgsys",
.data = &img_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_img);
static struct platform_driver clk_mt8183_img_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8183-img",
.of_match_table = of_match_clk_mt8183_img,
},
};
module_platform_driver(clk_mt8183_img_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8183-img.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Kevin Chen <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt6797-clk.h>
#include "clk-mtk.h"
#include "clk-gate.h"
static const struct mtk_gate_regs mm0_cg_regs = {
.set_ofs = 0x0104,
.clr_ofs = 0x0108,
.sta_ofs = 0x0100,
};
static const struct mtk_gate_regs mm1_cg_regs = {
.set_ofs = 0x0114,
.clr_ofs = 0x0118,
.sta_ofs = 0x0110,
};
#define GATE_MM0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_MM1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate mm_clks[] = {
GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
GATE_MM0(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 2),
GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 3),
GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 4),
GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 5),
GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 6),
GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 7),
GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 8),
GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 9),
GATE_MM0(CLK_MM_MDP_COLOR, "mm_mdp_color", "mm_sel", 10),
GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 15),
GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 16),
GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 17),
GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 18),
GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 19),
GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 20),
GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color", "mm_sel", 23),
GATE_MM0(CLK_MM_DISP_CCORR, "mm_disp_ccorr", "mm_sel", 24),
GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 27),
GATE_MM0(CLK_MM_DISP_DITHER, "mm_disp_dither", "mm_sel", 28),
GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 29),
GATE_MM0(CLK_MM_DISP_DSC, "mm_disp_dsc", "mm_sel", 30),
GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),
GATE_MM1(CLK_MM_DSI0_MM_CLOCK, "mm_dsi0_mm_clock", "mm_sel", 0),
GATE_MM1(CLK_MM_DSI1_MM_CLOCK, "mm_dsi1_mm_clock", "mm_sel", 2),
GATE_MM1(CLK_MM_DPI_MM_CLOCK, "mm_dpi_mm_clock", "mm_sel", 4),
GATE_MM1(CLK_MM_DPI_INTERFACE_CLOCK, "mm_dpi_interface_clock",
"dpi0_sel", 5),
GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MM_CLOCK, "mm_larb4_axi_asif_mm_clock",
"mm_sel", 6),
GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK, "mm_larb4_axi_asif_mjc_clock",
"mjc_sel", 7),
GATE_MM1(CLK_MM_DISP_OVL0_MOUT_CLOCK, "mm_disp_ovl0_mout_clock",
"mm_sel", 8),
GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 9),
GATE_MM1(CLK_MM_DSI0_INTERFACE_CLOCK, "mm_dsi0_interface_clock",
"clk26m", 1),
GATE_MM1(CLK_MM_DSI1_INTERFACE_CLOCK, "mm_dsi1_interface_clock",
"clk26m", 3),
};
static const struct mtk_clk_desc mm_desc = {
.clks = mm_clks,
.num_clks = ARRAY_SIZE(mm_clks),
};
static const struct platform_device_id clk_mt6797_mm_id_table[] = {
{ .name = "clk-mt6797-mm", .driver_data = (kernel_ulong_t)&mm_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, clk_mt6797_mm_id_table);
static struct platform_driver clk_mt6797_mm_drv = {
.probe = mtk_clk_pdev_probe,
.remove_new = mtk_clk_pdev_remove,
.driver = {
.name = "clk-mt6797-mm",
},
.id_table = clk_mt6797_mm_id_table,
};
module_platform_driver(clk_mt6797_mm_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6797-mm.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include "clk-mtk.h"
#include "clk-pll.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#define MT8195_PLL_FMAX (3800UL * MHZ)
#define MT8195_PLL_FMIN (1500UL * MHZ)
#define MT8195_INTEGER_BITS (8)
#define MT8195_PCW_BITS (22)
#define MT8195_POSDIV_SHIFT (24)
#define MT8195_PLL_EN_BIT (0)
#define MT8195_PCW_SHIFT (0)
/*
* The "en_reg" and "pcw_chg_reg" fields are standard offset register compared
* with "reg" field, so set zero to imply it.
* No tuner control in apu pll, so set "tuner_XXX" as zero to imply it.
* No rst or post divider enable in apu pll, so set "rst_bar_mask" and "en_mask"
* as zero to imply it.
*/
#define PLL(_id, _name, _reg, _pwr_reg, _pd_reg, _pcw_reg) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = 0, \
.flags = 0, \
.rst_bar_mask = 0, \
.fmax = MT8195_PLL_FMAX, \
.fmin = MT8195_PLL_FMIN, \
.pcwbits = MT8195_PCW_BITS, \
.pcwibits = MT8195_INTEGER_BITS, \
.pd_reg = _pd_reg, \
.pd_shift = MT8195_POSDIV_SHIFT, \
.tuner_reg = 0, \
.tuner_en_reg = 0, \
.tuner_en_bit = 0, \
.pcw_reg = _pcw_reg, \
.pcw_shift = MT8195_PCW_SHIFT, \
.pcw_chg_reg = 0, \
.en_reg = 0, \
.pll_en_bit = MT8195_PLL_EN_BIT, \
}
static const struct mtk_pll_data apusys_plls[] = {
PLL(CLK_APUSYS_PLL_APUPLL, "apusys_pll_apupll", 0x008, 0x014, 0x00c, 0x00c),
PLL(CLK_APUSYS_PLL_NPUPLL, "apusys_pll_npupll", 0x018, 0x024, 0x01c, 0x01c),
PLL(CLK_APUSYS_PLL_APUPLL1, "apusys_pll_apupll1", 0x028, 0x034, 0x02c, 0x02c),
PLL(CLK_APUSYS_PLL_APUPLL2, "apusys_pll_apupll2", 0x038, 0x044, 0x03c, 0x03c),
};
static int clk_mt8195_apusys_pll_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(CLK_APUSYS_PLL_NR_CLK);
if (!clk_data)
return -ENOMEM;
r = mtk_clk_register_plls(node, apusys_plls, ARRAY_SIZE(apusys_plls), clk_data);
if (r)
goto free_apusys_pll_data;
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_plls;
platform_set_drvdata(pdev, clk_data);
return r;
unregister_plls:
mtk_clk_unregister_plls(apusys_plls, ARRAY_SIZE(apusys_plls), clk_data);
free_apusys_pll_data:
mtk_free_clk_data(clk_data);
return r;
}
static void clk_mt8195_apusys_pll_remove(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
struct device_node *node = pdev->dev.of_node;
of_clk_del_provider(node);
mtk_clk_unregister_plls(apusys_plls, ARRAY_SIZE(apusys_plls), clk_data);
mtk_free_clk_data(clk_data);
}
static const struct of_device_id of_match_clk_mt8195_apusys_pll[] = {
{ .compatible = "mediatek,mt8195-apusys_pll", },
{}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_apusys_pll);
static struct platform_driver clk_mt8195_apusys_pll_drv = {
.probe = clk_mt8195_apusys_pll_probe,
.remove_new = clk_mt8195_apusys_pll_remove,
.driver = {
.name = "clk-mt8195-apusys_pll",
.of_match_table = of_match_clk_mt8195_apusys_pll,
},
};
module_platform_driver(clk_mt8195_apusys_pll_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8195-apusys_pll.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt8186-clk.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs mdp0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs mdp2_cg_regs = {
.set_ofs = 0x124,
.clr_ofs = 0x128,
.sta_ofs = 0x120,
};
#define GATE_MDP0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mdp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_MDP2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mdp2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate mdp_clks[] = {
/* MDP0 */
GATE_MDP0(CLK_MDP_RDMA0, "mdp_rdma0", "top_mdp", 0),
GATE_MDP0(CLK_MDP_TDSHP0, "mdp_tdshp0", "top_mdp", 1),
GATE_MDP0(CLK_MDP_IMG_DL_ASYNC0, "mdp_img_dl_async0", "top_mdp", 2),
GATE_MDP0(CLK_MDP_IMG_DL_ASYNC1, "mdp_img_dl_async1", "top_mdp", 3),
GATE_MDP0(CLK_MDP_DISP_RDMA, "mdp_disp_rdma", "top_mdp", 4),
GATE_MDP0(CLK_MDP_HMS, "mdp_hms", "top_mdp", 5),
GATE_MDP0(CLK_MDP_SMI0, "mdp_smi0", "top_mdp", 6),
GATE_MDP0(CLK_MDP_APB_BUS, "mdp_apb_bus", "top_mdp", 7),
GATE_MDP0(CLK_MDP_WROT0, "mdp_wrot0", "top_mdp", 8),
GATE_MDP0(CLK_MDP_RSZ0, "mdp_rsz0", "top_mdp", 9),
GATE_MDP0(CLK_MDP_HDR0, "mdp_hdr0", "top_mdp", 10),
GATE_MDP0(CLK_MDP_MUTEX0, "mdp_mutex0", "top_mdp", 11),
GATE_MDP0(CLK_MDP_WROT1, "mdp_wrot1", "top_mdp", 12),
GATE_MDP0(CLK_MDP_RSZ1, "mdp_rsz1", "top_mdp", 13),
GATE_MDP0(CLK_MDP_FAKE_ENG0, "mdp_fake_eng0", "top_mdp", 14),
GATE_MDP0(CLK_MDP_AAL0, "mdp_aal0", "top_mdp", 15),
GATE_MDP0(CLK_MDP_DISP_WDMA, "mdp_disp_wdma", "top_mdp", 16),
GATE_MDP0(CLK_MDP_COLOR, "mdp_color", "top_mdp", 17),
GATE_MDP0(CLK_MDP_IMG_DL_ASYNC2, "mdp_img_dl_async2", "top_mdp", 18),
/* MDP2 */
GATE_MDP2(CLK_MDP_IMG_DL_RELAY0_ASYNC0, "mdp_img_dl_rel0_as0", "top_mdp", 0),
GATE_MDP2(CLK_MDP_IMG_DL_RELAY1_ASYNC1, "mdp_img_dl_rel1_as1", "top_mdp", 8),
GATE_MDP2(CLK_MDP_IMG_DL_RELAY2_ASYNC2, "mdp_img_dl_rel2_as2", "top_mdp", 24),
};
static const struct mtk_clk_desc mdp_desc = {
.clks = mdp_clks,
.num_clks = ARRAY_SIZE(mdp_clks),
};
static const struct of_device_id of_match_clk_mt8186_mdp[] = {
{
.compatible = "mediatek,mt8186-mdpsys",
.data = &mdp_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_mdp);
static struct platform_driver clk_mt8186_mdp_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8186-mdp",
.of_match_table = of_match_clk_mt8186_mdp,
},
};
module_platform_driver(clk_mt8186_mdp_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8186-mdp.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 MediaTek Inc.
* Author: Wenzhen Yu <Wenzhen [email protected]>
* Ryder Lee <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt7629-clk.h>
#define GATE_PCIE(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &pcie_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
#define GATE_SSUSB(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ssusb_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate_regs pcie_cg_regs = {
.set_ofs = 0x30,
.clr_ofs = 0x30,
.sta_ofs = 0x30,
};
static const struct mtk_gate_regs ssusb_cg_regs = {
.set_ofs = 0x30,
.clr_ofs = 0x30,
.sta_ofs = 0x30,
};
static const struct mtk_gate ssusb_clks[] = {
GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p",
"to_u2_phy_1p", 0),
GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1),
GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5),
GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6),
GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "to_usb3_mcu", 7),
GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "to_usb3_dma", 8),
};
static const struct mtk_gate pcie_clks[] = {
GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12),
GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13),
GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "from_top_ahb", 14),
GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "from_top_axi", 15),
GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16),
GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17),
GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18),
GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19),
GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "from_top_ahb", 20),
GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "from_top_axi", 21),
GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22),
GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
};
static u16 rst_ofs[] = { 0x34, };
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SIMPLE,
.rst_bank_ofs = rst_ofs,
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
static const struct mtk_clk_desc ssusb_desc = {
.clks = ssusb_clks,
.num_clks = ARRAY_SIZE(ssusb_clks),
.rst_desc = &clk_rst_desc,
};
static const struct mtk_clk_desc pcie_desc = {
.clks = pcie_clks,
.num_clks = ARRAY_SIZE(pcie_clks),
.rst_desc = &clk_rst_desc,
};
static const struct of_device_id of_match_clk_mt7629_hif[] = {
{ .compatible = "mediatek,mt7629-pciesys", .data = &pcie_desc },
{ .compatible = "mediatek,mt7629-ssusbsys", .data = &ssusb_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7629_hif);
static struct platform_driver clk_mt7629_hif_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7629-hif",
.of_match_table = of_match_clk_mt7629_hif,
},
};
module_platform_driver(clk_mt7629_hif_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt7629-hif.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt8186-clk.h>
#include "clk-fhctl.h"
#include "clk-mtk.h"
#include "clk-pll.h"
#include "clk-pllfh.h"
#define MT8186_PLL_FMAX (3800UL * MHZ)
#define MT8186_PLL_FMIN (1500UL * MHZ)
#define MT8186_INTEGER_BITS (8)
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
_rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
_tuner_reg, _tuner_en_reg, _tuner_en_bit, \
_pcw_reg) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.pwr_reg = _pwr_reg, \
.en_mask = _en_mask, \
.flags = _flags, \
.rst_bar_mask = _rst_bar_mask, \
.fmax = MT8186_PLL_FMAX, \
.fmin = MT8186_PLL_FMIN, \
.pcwbits = _pcwbits, \
.pcwibits = MT8186_INTEGER_BITS, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, \
.tuner_en_reg = _tuner_en_reg, \
.tuner_en_bit = _tuner_en_bit, \
.pcw_reg = _pcw_reg, \
.pcw_shift = 0, \
.pcw_chg_reg = 0, \
.en_reg = 0, \
.pll_en_bit = 0, \
}
static const struct mtk_pll_data plls[] = {
/*
* armpll_ll/armpll_bl/ccipll are main clock source of AP MCU,
* should not be closed in Linux world.
*/
PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0204, 0x0210, 0,
PLL_AO, 0, 22, 0x0208, 24, 0, 0, 0, 0x0208),
PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0214, 0x0220, 0,
PLL_AO, 0, 22, 0x0218, 24, 0, 0, 0, 0x0218),
PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0224, 0x0230, 0,
PLL_AO, 0, 22, 0x0228, 24, 0, 0, 0, 0x0228),
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0244, 0x0250, 0xff000000,
HAVE_RST_BAR, BIT(23), 22, 0x0248, 24, 0, 0, 0, 0x0248),
PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0324, 0x0330, 0xff000000,
HAVE_RST_BAR, BIT(23), 22, 0x0328, 24, 0, 0, 0, 0x0328),
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x038C, 0x0398, 0,
0, 0, 22, 0x0390, 24, 0, 0, 0, 0x0390),
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0254, 0x0260, 0,
0, 0, 22, 0x0258, 24, 0, 0, 0, 0x0258),
PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x035C, 0x0368, 0,
0, 0, 22, 0x0360, 24, 0, 0, 0, 0x0360),
PLL(CLK_APMIXED_NNA2PLL, "nna2pll", 0x036C, 0x0378, 0,
0, 0, 22, 0x0370, 24, 0, 0, 0, 0x0370),
PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x0304, 0x0310, 0,
0, 0, 22, 0x0308, 24, 0, 0, 0, 0x0308),
PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0314, 0x0320, 0,
0, 0, 22, 0x0318, 24, 0, 0, 0, 0x0318),
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0264, 0x0270, 0,
0, 0, 22, 0x0268, 24, 0, 0, 0, 0x0268),
PLL(CLK_APMIXED_APLL1, "apll1", 0x0334, 0x0344, 0,
0, 0, 32, 0x0338, 24, 0x0040, 0x000C, 0, 0x033C),
PLL(CLK_APMIXED_APLL2, "apll2", 0x0348, 0x0358, 0,
0, 0, 32, 0x034C, 24, 0x0044, 0x000C, 5, 0x0350),
};
enum fh_pll_id {
FH_ARMPLL_LL,
FH_ARMPLL_BL,
FH_CCIPLL,
FH_MAINPLL,
FH_MMPLL,
FH_TVDPLL,
FH_RESERVE6,
FH_ADSPPLL,
FH_MFGPLL,
FH_NNAPLL,
FH_NNA2PLL,
FH_MSDCPLL,
FH_RESERVE12,
FH_NR_FH,
};
#define FH(_pllid, _fhid, _offset) { \
.data = { \
.pll_id = _pllid, \
.fh_id = _fhid, \
.fh_ver = FHCTL_PLLFH_V2, \
.fhx_offset = _offset, \
.dds_mask = GENMASK(21, 0), \
.slope0_value = 0x6003c97, \
.slope1_value = 0x6003c97, \
.sfstrx_en = BIT(2), \
.frddsx_en = BIT(1), \
.fhctlx_en = BIT(0), \
.tgl_org = BIT(31), \
.dvfs_tri = BIT(31), \
.pcwchg = BIT(31), \
.dt_val = 0x0, \
.df_val = 0x9, \
.updnlmt_shft = 16, \
.msk_frddsx_dys = GENMASK(23, 20), \
.msk_frddsx_dts = GENMASK(19, 16), \
}, \
}
static struct mtk_pllfh_data pllfhs[] = {
FH(CLK_APMIXED_ARMPLL_LL, FH_ARMPLL_LL, 0x003C),
FH(CLK_APMIXED_ARMPLL_BL, FH_ARMPLL_BL, 0x0050),
FH(CLK_APMIXED_CCIPLL, FH_CCIPLL, 0x0064),
FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x0078),
FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x008C),
FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x00A0),
FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x00C8),
FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0x00DC),
FH(CLK_APMIXED_NNAPLL, FH_NNAPLL, 0x00F0),
FH(CLK_APMIXED_NNA2PLL, FH_NNA2PLL, 0x0104),
FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x0118),
};
static const struct of_device_id of_match_clk_mt8186_apmixed[] = {
{ .compatible = "mediatek,mt8186-apmixedsys", },
{}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_apmixed);
static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
const u8 *fhctl_node = "mediatek,mt8186-fhctl";
int r;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
if (!clk_data)
return -ENOMEM;
fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (r)
goto free_apmixed_data;
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_plls;
platform_set_drvdata(pdev, clk_data);
return r;
unregister_plls:
mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
ARRAY_SIZE(pllfhs), clk_data);
free_apmixed_data:
mtk_free_clk_data(clk_data);
return r;
}
static void clk_mt8186_apmixed_remove(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
of_clk_del_provider(node);
mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
ARRAY_SIZE(pllfhs), clk_data);
mtk_free_clk_data(clk_data);
}
static struct platform_driver clk_mt8186_apmixed_drv = {
.probe = clk_mt8186_apmixed_probe,
.remove_new = clk_mt8186_apmixed_remove,
.driver = {
.name = "clk-mt8186-apmixed",
.of_match_table = of_match_clk_mt8186_apmixed,
},
};
module_platform_driver(clk_mt8186_apmixed_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8186-apmixedsys.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Wendell Lin <[email protected]>
*/
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt6779-clk.h>
static const struct mtk_gate_regs venc_cg_regs = {
.set_ofs = 0x0004,
.clr_ofs = 0x0008,
.sta_ofs = 0x0000,
};
#define GATE_VENC_I(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate venc_clks[] = {
GATE_VENC_I(CLK_VENC_GCON_LARB, "venc_larb", "venc_sel", 0),
GATE_VENC_I(CLK_VENC_GCON_VENC, "venc_venc", "venc_sel", 4),
GATE_VENC_I(CLK_VENC_GCON_JPGENC, "venc_jpgenc", "venc_sel", 8),
GATE_VENC_I(CLK_VENC_GCON_GALS, "venc_gals", "venc_sel", 28),
};
static const struct mtk_clk_desc venc_desc = {
.clks = venc_clks,
.num_clks = ARRAY_SIZE(venc_clks),
};
static const struct of_device_id of_match_clk_mt6779_venc[] = {
{
.compatible = "mediatek,mt6779-vencsys",
.data = &venc_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_venc);
static struct platform_driver clk_mt6779_venc_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt6779-venc",
.of_match_table = of_match_clk_mt6779_venc,
},
};
module_platform_driver(clk_mt6779_venc_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6779-venc.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2018 MediaTek Inc.
// Author: Weiyi Lu <[email protected]>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8183-clk.h>
static const struct mtk_gate_regs mm0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs mm1_cg_regs = {
.set_ofs = 0x114,
.clr_ofs = 0x118,
.sta_ofs = 0x110,
};
#define GATE_MM0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr)
#define GATE_MM1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr)
static const struct mtk_gate mm_clks[] = {
/* MM0 */
GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
GATE_MM0(CLK_MM_SMI_LARB1, "mm_smi_larb1", "mm_sel", 2),
GATE_MM0(CLK_MM_GALS_COMM0, "mm_gals_comm0", "mm_sel", 3),
GATE_MM0(CLK_MM_GALS_COMM1, "mm_gals_comm1", "mm_sel", 4),
GATE_MM0(CLK_MM_GALS_CCU2MM, "mm_gals_ccu2mm", "mm_sel", 5),
GATE_MM0(CLK_MM_GALS_IPU12MM, "mm_gals_ipu12mm", "mm_sel", 6),
GATE_MM0(CLK_MM_GALS_IMG2MM, "mm_gals_img2mm", "mm_sel", 7),
GATE_MM0(CLK_MM_GALS_CAM2MM, "mm_gals_cam2mm", "mm_sel", 8),
GATE_MM0(CLK_MM_GALS_IPU2MM, "mm_gals_ipu2mm", "mm_sel", 9),
GATE_MM0(CLK_MM_MDP_DL_TXCK, "mm_mdp_dl_txck", "mm_sel", 10),
GATE_MM0(CLK_MM_IPU_DL_TXCK, "mm_ipu_dl_txck", "mm_sel", 11),
GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 12),
GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 13),
GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 14),
GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 15),
GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 16),
GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 17),
GATE_MM0(CLK_MM_MDP_WDMA0, "mm_mdp_wdma0", "mm_sel", 18),
GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 19),
GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 20),
GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 21),
GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 22),
GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 23),
GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 24),
GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 25),
GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 26),
GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_sel", 27),
GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_sel", 28),
GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_sel", 29),
GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_sel", 30),
GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),
/* MM1 */
GATE_MM1(CLK_MM_DSI0_MM, "mm_dsi0_mm", "mm_sel", 0),
GATE_MM1(CLK_MM_DSI0_IF, "mm_dsi0_if", "mm_sel", 1),
GATE_MM1(CLK_MM_DPI_MM, "mm_dpi_mm", "mm_sel", 2),
GATE_MM1(CLK_MM_DPI_IF, "mm_dpi_if", "dpi0_sel", 3),
GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 4),
GATE_MM1(CLK_MM_MDP_DL_RX, "mm_mdp_dl_rx", "mm_sel", 5),
GATE_MM1(CLK_MM_IPU_DL_RX, "mm_ipu_dl_rx", "mm_sel", 6),
GATE_MM1(CLK_MM_26M, "mm_26m", "f_f26m_ck", 7),
GATE_MM1(CLK_MM_MMSYS_R2Y, "mm_mmsys_r2y", "mm_sel", 8),
GATE_MM1(CLK_MM_DISP_RSZ, "mm_disp_rsz", "mm_sel", 9),
GATE_MM1(CLK_MM_MDP_AAL, "mm_mdp_aal", "mm_sel", 10),
GATE_MM1(CLK_MM_MDP_CCORR, "mm_mdp_ccorr", "mm_sel", 11),
GATE_MM1(CLK_MM_DBI_MM, "mm_dbi_mm", "mm_sel", 12),
GATE_MM1(CLK_MM_DBI_IF, "mm_dbi_if", "dpi0_sel", 13),
};
static const struct mtk_clk_desc mm_desc = {
.clks = mm_clks,
.num_clks = ARRAY_SIZE(mm_clks),
};
static const struct platform_device_id clk_mt8183_mm_id_table[] = {
{ .name = "clk-mt8183-mm", .driver_data = (kernel_ulong_t)&mm_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, clk_mt8183_mm_id_table);
static struct platform_driver clk_mt8183_mm_drv = {
.probe = mtk_clk_pdev_probe,
.remove_new = mtk_clk_pdev_remove,
.driver = {
.name = "clk-mt8183-mm",
},
.id_table = clk_mt8183_mm_id_table,
};
module_platform_driver(clk_mt8183_mm_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8183-mm.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 MediaTek Inc.
* Author: Sam Shih <[email protected]>
* Author: Wenzhen Yu <[email protected]>
* Author: Jianhui Zhao <[email protected]>
* Author: Daniel Golle <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#include "clk-mux.h"
#include "clk-pll.h"
#include <dt-bindings/clock/mediatek,mt7981-clk.h>
#include <linux/clk.h>
#define MT7981_PLL_FMAX (2500UL * MHZ)
#define CON0_MT7981_RST_BAR BIT(27)
#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
_div_table, _parent_name) \
{ \
.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
.en_mask = _en_mask, .flags = _flags, \
.rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX, \
.pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, .div_table = _div_table, \
.parent_name = _parent_name, \
}
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
_pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \
PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \
"clkxtal")
static const struct mtk_pll_data plls[] = {
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO,
32, 0x0200, 4, 0, 0x0204, 0),
PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
0x0210, 4, 0, 0x0214, 0),
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
0x0220, 4, 0, 0x0224, 0),
PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32,
0x0230, 4, 0, 0x0234, 0),
PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32,
0x0240, 4, 0, 0x0244, 0),
PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32,
0x0250, 4, 0, 0x0254, 0),
PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32,
0x0260, 4, 0, 0x0264, 0),
PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
0x0278, 4, 0, 0x027C, 0),
};
static const struct of_device_id of_match_clk_mt7981_apmixed[] = {
{ .compatible = "mediatek,mt7981-apmixedsys", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7981_apmixed);
static int clk_mt7981_apmixed_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
if (!clk_data)
return -ENOMEM;
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
goto free_apmixed_data;
}
return r;
free_apmixed_data:
mtk_free_clk_data(clk_data);
return r;
}
static struct platform_driver clk_mt7981_apmixed_drv = {
.probe = clk_mt7981_apmixed_probe,
.driver = {
.name = "clk-mt7981-apmixed",
.of_match_table = of_match_clk_mt7981_apmixed,
},
};
builtin_platform_driver(clk_mt7981_apmixed_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt7981-apmixed.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Wendell Lin <[email protected]>
*/
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt6779-clk.h>
#include "clk-mtk.h"
#include "clk-gate.h"
static const struct mtk_gate_regs img_cg_regs = {
.set_ofs = 0x0004,
.clr_ofs = 0x0008,
.sta_ofs = 0x0000,
};
#define GATE_IMG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr)
static const struct mtk_gate img_clks[] = {
GATE_IMG(CLK_IMG_LARB5, "imgsys_larb5", "img_sel", 0),
GATE_IMG(CLK_IMG_LARB6, "imgsys_larb6", "img_sel", 1),
GATE_IMG(CLK_IMG_DIP, "imgsys_dip", "img_sel", 2),
GATE_IMG(CLK_IMG_MFB, "imgsys_mfb", "img_sel", 6),
GATE_IMG(CLK_IMG_WPE_A, "imgsys_wpe_a", "img_sel", 7),
};
static const struct mtk_clk_desc img_desc = {
.clks = img_clks,
.num_clks = ARRAY_SIZE(img_clks),
};
static const struct of_device_id of_match_clk_mt6779_img[] = {
{
.compatible = "mediatek,mt6779-imgsys",
.data = &img_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_img);
static struct platform_driver clk_mt6779_img_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt6779-img",
.of_match_table = of_match_clk_mt6779_img,
},
};
module_platform_driver(clk_mt6779_img_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6779-img.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 Collabora Ltd.
* Author: AngeloGioacchino Del Regno <[email protected]>
*/
#include <dt-bindings/clock/mediatek,mt6795-clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs venc_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_VENC(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate venc_clks[] = {
GATE_VENC(CLK_VENC_LARB, "venc_larb", "venc_sel", 0),
GATE_VENC(CLK_VENC_VENC, "venc_venc", "venc_sel", 4),
GATE_VENC(CLK_VENC_JPGENC, "venc_jpgenc", "venc_sel", 8),
GATE_VENC(CLK_VENC_JPGDEC, "venc_jpgdec", "venc_sel", 12),
};
static const struct mtk_clk_desc venc_desc = {
.clks = venc_clks,
.num_clks = ARRAY_SIZE(venc_clks),
};
static const struct of_device_id of_match_clk_mt6795_vencsys[] = {
{ .compatible = "mediatek,mt6795-vencsys", .data = &venc_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_vencsys);
static struct platform_driver clk_mt6795_vencsys_drv = {
.driver = {
.name = "clk-mt6795-vencsys",
.of_match_table = of_match_clk_mt6795_vencsys,
},
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt6795_vencsys_drv);
MODULE_DESCRIPTION("MediaTek MT6795 vdecsys clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6795-vencsys.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs ipe_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x0,
.sta_ofs = 0x0,
};
#define GATE_IPE(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate ipe_clks[] = {
GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "top_ipe", 0),
GATE_IPE(CLK_IPE_FDVT, "ipe_fdvt", "top_ipe", 1),
GATE_IPE(CLK_IPE_ME, "ipe_me", "top_ipe", 2),
GATE_IPE(CLK_IPE_TOP, "ipe_top", "top_ipe", 3),
GATE_IPE(CLK_IPE_SMI_LARB12, "ipe_smi_larb12", "top_ipe", 4),
};
static const struct mtk_clk_desc ipe_desc = {
.clks = ipe_clks,
.num_clks = ARRAY_SIZE(ipe_clks),
};
static const struct of_device_id of_match_clk_mt8195_ipe[] = {
{
.compatible = "mediatek,mt8195-ipesys",
.data = &ipe_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_ipe);
static struct platform_driver clk_mt8195_ipe_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8195-ipe",
.of_match_table = of_match_clk_mt8195_ipe,
},
};
module_platform_driver(clk_mt8195_ipe_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8195-ipe.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Weiyi Lu <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt2712-clk.h>
static const struct mtk_gate_regs img_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x0,
.sta_ofs = 0x0,
};
#define GATE_IMG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate img_clks[] = {
GATE_IMG(CLK_IMG_SMI_LARB2, "img_smi_larb2", "mm_sel", 0),
GATE_IMG(CLK_IMG_SENINF_SCAM_EN, "img_scam_en", "csi0", 3),
GATE_IMG(CLK_IMG_SENINF_CAM_EN, "img_cam_en", "mm_sel", 8),
GATE_IMG(CLK_IMG_CAM_SV_EN, "img_cam_sv_en", "mm_sel", 9),
GATE_IMG(CLK_IMG_CAM_SV1_EN, "img_cam_sv1_en", "mm_sel", 10),
GATE_IMG(CLK_IMG_CAM_SV2_EN, "img_cam_sv2_en", "mm_sel", 11),
};
static const struct mtk_clk_desc img_desc = {
.clks = img_clks,
.num_clks = ARRAY_SIZE(img_clks),
};
static const struct of_device_id of_match_clk_mt2712_img[] = {
{
.compatible = "mediatek,mt2712-imgsys",
.data = &img_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_img);
static struct platform_driver clk_mt2712_img_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt2712-img",
.of_match_table = of_match_clk_mt2712_img,
},
};
module_platform_driver(clk_mt2712_img_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt2712-img.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs ccu_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_CCU(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ccu_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate ccu_clks[] = {
GATE_CCU(CLK_CCU_LARB18, "ccu_larb18", "top_ccu", 0),
GATE_CCU(CLK_CCU_AHB, "ccu_ahb", "top_ccu", 1),
GATE_CCU(CLK_CCU_CCU0, "ccu_ccu0", "top_ccu", 2),
GATE_CCU(CLK_CCU_CCU1, "ccu_ccu1", "top_ccu", 3),
};
static const struct mtk_clk_desc ccu_desc = {
.clks = ccu_clks,
.num_clks = ARRAY_SIZE(ccu_clks),
};
static const struct of_device_id of_match_clk_mt8195_ccu[] = {
{
.compatible = "mediatek,mt8195-ccusys",
.data = &ccu_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_ccu);
static struct platform_driver clk_mt8195_ccu_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8195-ccu",
.of_match_table = of_match_clk_mt8195_ccu,
},
};
module_platform_driver(clk_mt8195_ccu_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8195-ccu.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: James Liao <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/printk.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/types.h>
#include "clk-gate.h"
struct mtk_clk_gate {
struct clk_hw hw;
struct regmap *regmap;
int set_ofs;
int clr_ofs;
int sta_ofs;
u8 bit;
};
static inline struct mtk_clk_gate *to_mtk_clk_gate(struct clk_hw *hw)
{
return container_of(hw, struct mtk_clk_gate, hw);
}
static u32 mtk_get_clockgating(struct clk_hw *hw)
{
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
u32 val;
regmap_read(cg->regmap, cg->sta_ofs, &val);
return val & BIT(cg->bit);
}
static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
{
return mtk_get_clockgating(hw) == 0;
}
static int mtk_cg_bit_is_set(struct clk_hw *hw)
{
return mtk_get_clockgating(hw) != 0;
}
static void mtk_cg_set_bit(struct clk_hw *hw)
{
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit));
}
static void mtk_cg_clr_bit(struct clk_hw *hw)
{
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
}
static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
{
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
regmap_set_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit));
}
static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
{
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
regmap_clear_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit));
}
static int mtk_cg_enable(struct clk_hw *hw)
{
mtk_cg_clr_bit(hw);
return 0;
}
static void mtk_cg_disable(struct clk_hw *hw)
{
mtk_cg_set_bit(hw);
}
static int mtk_cg_enable_inv(struct clk_hw *hw)
{
mtk_cg_set_bit(hw);
return 0;
}
static void mtk_cg_disable_inv(struct clk_hw *hw)
{
mtk_cg_clr_bit(hw);
}
static int mtk_cg_enable_no_setclr(struct clk_hw *hw)
{
mtk_cg_clr_bit_no_setclr(hw);
return 0;
}
static void mtk_cg_disable_no_setclr(struct clk_hw *hw)
{
mtk_cg_set_bit_no_setclr(hw);
}
static int mtk_cg_enable_inv_no_setclr(struct clk_hw *hw)
{
mtk_cg_set_bit_no_setclr(hw);
return 0;
}
static void mtk_cg_disable_inv_no_setclr(struct clk_hw *hw)
{
mtk_cg_clr_bit_no_setclr(hw);
}
const struct clk_ops mtk_clk_gate_ops_setclr = {
.is_enabled = mtk_cg_bit_is_cleared,
.enable = mtk_cg_enable,
.disable = mtk_cg_disable,
};
EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr);
const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
.is_enabled = mtk_cg_bit_is_set,
.enable = mtk_cg_enable_inv,
.disable = mtk_cg_disable_inv,
};
EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr_inv);
const struct clk_ops mtk_clk_gate_ops_no_setclr = {
.is_enabled = mtk_cg_bit_is_cleared,
.enable = mtk_cg_enable_no_setclr,
.disable = mtk_cg_disable_no_setclr,
};
EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr);
const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = {
.is_enabled = mtk_cg_bit_is_set,
.enable = mtk_cg_enable_inv_no_setclr,
.disable = mtk_cg_disable_inv_no_setclr,
};
EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv);
static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name,
const char *parent_name,
struct regmap *regmap, int set_ofs,
int clr_ofs, int sta_ofs, u8 bit,
const struct clk_ops *ops,
unsigned long flags)
{
struct mtk_clk_gate *cg;
int ret;
struct clk_init_data init = {};
cg = kzalloc(sizeof(*cg), GFP_KERNEL);
if (!cg)
return ERR_PTR(-ENOMEM);
init.name = name;
init.flags = flags | CLK_SET_RATE_PARENT;
init.parent_names = parent_name ? &parent_name : NULL;
init.num_parents = parent_name ? 1 : 0;
init.ops = ops;
cg->regmap = regmap;
cg->set_ofs = set_ofs;
cg->clr_ofs = clr_ofs;
cg->sta_ofs = sta_ofs;
cg->bit = bit;
cg->hw.init = &init;
ret = clk_hw_register(dev, &cg->hw);
if (ret) {
kfree(cg);
return ERR_PTR(ret);
}
return &cg->hw;
}
static void mtk_clk_unregister_gate(struct clk_hw *hw)
{
struct mtk_clk_gate *cg;
if (!hw)
return;
cg = to_mtk_clk_gate(hw);
clk_hw_unregister(hw);
kfree(cg);
}
int mtk_clk_register_gates(struct device *dev, struct device_node *node,
const struct mtk_gate *clks, int num,
struct clk_hw_onecell_data *clk_data)
{
int i;
struct clk_hw *hw;
struct regmap *regmap;
if (!clk_data)
return -ENOMEM;
regmap = device_node_to_regmap(node);
if (IS_ERR(regmap)) {
pr_err("Cannot find regmap for %pOF: %pe\n", node, regmap);
return PTR_ERR(regmap);
}
for (i = 0; i < num; i++) {
const struct mtk_gate *gate = &clks[i];
if (!IS_ERR_OR_NULL(clk_data->hws[gate->id])) {
pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",
node, gate->id);
continue;
}
hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name,
regmap,
gate->regs->set_ofs,
gate->regs->clr_ofs,
gate->regs->sta_ofs,
gate->shift, gate->ops,
gate->flags);
if (IS_ERR(hw)) {
pr_err("Failed to register clk %s: %pe\n", gate->name,
hw);
goto err;
}
clk_data->hws[gate->id] = hw;
}
return 0;
err:
while (--i >= 0) {
const struct mtk_gate *gate = &clks[i];
if (IS_ERR_OR_NULL(clk_data->hws[gate->id]))
continue;
mtk_clk_unregister_gate(clk_data->hws[gate->id]);
clk_data->hws[gate->id] = ERR_PTR(-ENOENT);
}
return PTR_ERR(hw);
}
EXPORT_SYMBOL_GPL(mtk_clk_register_gates);
void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
struct clk_hw_onecell_data *clk_data)
{
int i;
if (!clk_data)
return;
for (i = num; i > 0; i--) {
const struct mtk_gate *gate = &clks[i - 1];
if (IS_ERR_OR_NULL(clk_data->hws[gate->id]))
continue;
mtk_clk_unregister_gate(clk_data->hws[gate->id]);
clk_data->hws[gate->id] = ERR_PTR(-ENOENT);
}
}
EXPORT_SYMBOL_GPL(mtk_clk_unregister_gates);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-gate.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Shunli Wang <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt2701-clk.h>
static const struct mtk_gate_regs hif_cg_regs = {
.sta_ofs = 0x0030,
};
#define GATE_HIF(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &hif_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
static const struct mtk_gate hif_clks[] = {
GATE_DUMMY(CLK_DUMMY, "hif_dummy"),
GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21),
GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22),
GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24),
GATE_HIF(CLK_HIFSYS_PCIE1, "pcie1_clk", "ethpll_500m_ck", 25),
GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),
};
static u16 rst_ofs[] = { 0x34, };
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SIMPLE,
.rst_bank_ofs = rst_ofs,
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
static const struct mtk_clk_desc hif_desc = {
.clks = hif_clks,
.num_clks = ARRAY_SIZE(hif_clks),
.rst_desc = &clk_rst_desc,
};
static const struct of_device_id of_match_clk_mt2701_hif[] = {
{ .compatible = "mediatek,mt2701-hifsys", .data = &hif_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_hif);
static struct platform_driver clk_mt2701_hif_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt2701-hif",
.of_match_table = of_match_clk_mt2701_hif,
},
};
module_platform_driver(clk_mt2701_hif_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt2701-hif.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Edward-JW Yang <[email protected]>
*/
#include <linux/io.h>
#include <linux/iopoll.h>
#include "clk-mtk.h"
#include "clk-pllfh.h"
#include "clk-fhctl.h"
#define PERCENT_TO_DDSLMT(dds, percent_m10) \
((((dds) * (percent_m10)) >> 5) / 100)
static const struct fhctl_offset fhctl_offset_v1 = {
.offset_hp_en = 0x0,
.offset_clk_con = 0x4,
.offset_rst_con = 0x8,
.offset_slope0 = 0xc,
.offset_slope1 = 0x10,
.offset_cfg = 0x0,
.offset_updnlmt = 0x4,
.offset_dds = 0x8,
.offset_dvfs = 0xc,
.offset_mon = 0x10,
};
static const struct fhctl_offset fhctl_offset_v2 = {
.offset_hp_en = 0x0,
.offset_clk_con = 0x8,
.offset_rst_con = 0xc,
.offset_slope0 = 0x10,
.offset_slope1 = 0x14,
.offset_cfg = 0x0,
.offset_updnlmt = 0x4,
.offset_dds = 0x8,
.offset_dvfs = 0xc,
.offset_mon = 0x10,
};
const struct fhctl_offset *fhctl_get_offset_table(enum fhctl_variant v)
{
switch (v) {
case FHCTL_PLLFH_V1:
return &fhctl_offset_v1;
case FHCTL_PLLFH_V2:
return &fhctl_offset_v2;
default:
return ERR_PTR(-EINVAL);
};
}
static void dump_hw(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,
const struct fh_pll_data *data)
{
pr_info("hp_en<%x>,clk_con<%x>,slope0<%x>,slope1<%x>\n",
readl(regs->reg_hp_en), readl(regs->reg_clk_con),
readl(regs->reg_slope0), readl(regs->reg_slope1));
pr_info("cfg<%x>,lmt<%x>,dds<%x>,dvfs<%x>,mon<%x>\n",
readl(regs->reg_cfg), readl(regs->reg_updnlmt),
readl(regs->reg_dds), readl(regs->reg_dvfs),
readl(regs->reg_mon));
pr_info("pcw<%x>\n", readl(pll->pcw_addr));
}
static int fhctl_set_ssc_regs(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,
const struct fh_pll_data *data, u32 rate)
{
u32 updnlmt_val, r;
writel((readl(regs->reg_cfg) & ~(data->frddsx_en)), regs->reg_cfg);
writel((readl(regs->reg_cfg) & ~(data->sfstrx_en)), regs->reg_cfg);
writel((readl(regs->reg_cfg) & ~(data->fhctlx_en)), regs->reg_cfg);
if (rate > 0) {
/* Set the relative parameter registers (dt/df/upbnd/downbnd) */
r = readl(regs->reg_cfg);
r &= ~(data->msk_frddsx_dys);
r |= (data->df_val << (ffs(data->msk_frddsx_dys) - 1));
writel(r, regs->reg_cfg);
r = readl(regs->reg_cfg);
r &= ~(data->msk_frddsx_dts);
r |= (data->dt_val << (ffs(data->msk_frddsx_dts) - 1));
writel(r, regs->reg_cfg);
writel((readl(pll->pcw_addr) & data->dds_mask) | data->tgl_org,
regs->reg_dds);
/* Calculate UPDNLMT */
updnlmt_val = PERCENT_TO_DDSLMT((readl(regs->reg_dds) &
data->dds_mask), rate) <<
data->updnlmt_shft;
writel(updnlmt_val, regs->reg_updnlmt);
writel(readl(regs->reg_hp_en) | BIT(data->fh_id),
regs->reg_hp_en);
/* Enable SSC */
writel(readl(regs->reg_cfg) | data->frddsx_en, regs->reg_cfg);
/* Enable Hopping control */
writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg);
} else {
/* Switch to APMIXEDSYS control */
writel(readl(regs->reg_hp_en) & ~BIT(data->fh_id),
regs->reg_hp_en);
/* Wait for DDS to be stable */
udelay(30);
}
return 0;
}
static int hopping_hw_flow(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,
const struct fh_pll_data *data,
struct fh_pll_state *state, unsigned int new_dds)
{
u32 dds_mask = data->dds_mask;
u32 mon_dds = 0;
u32 con_pcw_tmp;
int ret;
if (state->ssc_rate)
fhctl_set_ssc_regs(pll, regs, data, 0);
writel((readl(pll->pcw_addr) & dds_mask) | data->tgl_org,
regs->reg_dds);
writel(readl(regs->reg_cfg) | data->sfstrx_en, regs->reg_cfg);
writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg);
writel(data->slope0_value, regs->reg_slope0);
writel(data->slope1_value, regs->reg_slope1);
writel(readl(regs->reg_hp_en) | BIT(data->fh_id), regs->reg_hp_en);
writel((new_dds) | (data->dvfs_tri), regs->reg_dvfs);
/* Wait 1000 us until DDS stable */
ret = readl_poll_timeout_atomic(regs->reg_mon, mon_dds,
(mon_dds & dds_mask) == new_dds,
10, 1000);
if (ret) {
pr_warn("%s: FHCTL hopping timeout\n", pll->data->name);
dump_hw(pll, regs, data);
}
con_pcw_tmp = readl(pll->pcw_addr) & (~dds_mask);
con_pcw_tmp = (con_pcw_tmp | (readl(regs->reg_mon) & dds_mask) |
data->pcwchg);
writel(con_pcw_tmp, pll->pcw_addr);
writel(readl(regs->reg_hp_en) & ~BIT(data->fh_id), regs->reg_hp_en);
if (state->ssc_rate)
fhctl_set_ssc_regs(pll, regs, data, state->ssc_rate);
return ret;
}
static unsigned int __get_postdiv(struct mtk_clk_pll *pll)
{
unsigned int regval;
regval = readl(pll->pd_addr) >> pll->data->pd_shift;
regval &= POSTDIV_MASK;
return BIT(regval);
}
static void __set_postdiv(struct mtk_clk_pll *pll, unsigned int postdiv)
{
unsigned int regval;
regval = readl(pll->pd_addr);
regval &= ~(POSTDIV_MASK << pll->data->pd_shift);
regval |= (ffs(postdiv) - 1) << pll->data->pd_shift;
writel(regval, pll->pd_addr);
}
static int fhctl_hopping(struct mtk_fh *fh, unsigned int new_dds,
unsigned int postdiv)
{
const struct fh_pll_data *data = &fh->pllfh_data->data;
struct fh_pll_state *state = &fh->pllfh_data->state;
struct fh_pll_regs *regs = &fh->regs;
struct mtk_clk_pll *pll = &fh->clk_pll;
spinlock_t *lock = fh->lock;
unsigned int pll_postdiv;
unsigned long flags = 0;
int ret;
if (postdiv) {
pll_postdiv = __get_postdiv(pll);
if (postdiv > pll_postdiv)
__set_postdiv(pll, postdiv);
}
spin_lock_irqsave(lock, flags);
ret = hopping_hw_flow(pll, regs, data, state, new_dds);
spin_unlock_irqrestore(lock, flags);
if (postdiv && postdiv < pll_postdiv)
__set_postdiv(pll, postdiv);
return ret;
}
static int fhctl_ssc_enable(struct mtk_fh *fh, u32 rate)
{
const struct fh_pll_data *data = &fh->pllfh_data->data;
struct fh_pll_state *state = &fh->pllfh_data->state;
struct fh_pll_regs *regs = &fh->regs;
struct mtk_clk_pll *pll = &fh->clk_pll;
spinlock_t *lock = fh->lock;
unsigned long flags = 0;
spin_lock_irqsave(lock, flags);
fhctl_set_ssc_regs(pll, regs, data, rate);
state->ssc_rate = rate;
spin_unlock_irqrestore(lock, flags);
return 0;
}
static const struct fh_operation fhctl_ops = {
.hopping = fhctl_hopping,
.ssc_enable = fhctl_ssc_enable,
};
const struct fh_operation *fhctl_get_ops(void)
{
return &fhctl_ops;
}
void fhctl_hw_init(struct mtk_fh *fh)
{
const struct fh_pll_data data = fh->pllfh_data->data;
struct fh_pll_state state = fh->pllfh_data->state;
struct fh_pll_regs regs = fh->regs;
u32 val;
/* initial hw register */
val = readl(regs.reg_clk_con) | BIT(data.fh_id);
writel(val, regs.reg_clk_con);
val = readl(regs.reg_rst_con) & ~BIT(data.fh_id);
writel(val, regs.reg_rst_con);
val = readl(regs.reg_rst_con) | BIT(data.fh_id);
writel(val, regs.reg_rst_con);
writel(0x0, regs.reg_cfg);
writel(0x0, regs.reg_updnlmt);
writel(0x0, regs.reg_dds);
/* enable ssc if needed */
if (state.ssc_rate)
fh->ops->ssc_enable(fh, state.ssc_rate);
}
| linux-master | drivers/clk/mediatek/clk-fhctl.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include "clk-gate.h"
#include "clk-mtk.h"
#include <dt-bindings/clock/mt8195-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
static const struct mtk_gate_regs venc_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_VENC(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate venc_clks[] = {
GATE_VENC(CLK_VENC_LARB, "venc_larb", "top_venc", 0),
GATE_VENC(CLK_VENC_VENC, "venc_venc", "top_venc", 4),
GATE_VENC(CLK_VENC_JPGENC, "venc_jpgenc", "top_venc", 8),
GATE_VENC(CLK_VENC_JPGDEC, "venc_jpgdec", "top_venc", 12),
GATE_VENC(CLK_VENC_JPGDEC_C1, "venc_jpgdec_c1", "top_venc", 16),
GATE_VENC(CLK_VENC_GALS, "venc_gals", "top_venc", 28),
};
static const struct mtk_gate venc_core1_clks[] = {
GATE_VENC(CLK_VENC_CORE1_LARB, "venc_core1_larb", "top_venc", 0),
GATE_VENC(CLK_VENC_CORE1_VENC, "venc_core1_venc", "top_venc", 4),
GATE_VENC(CLK_VENC_CORE1_JPGENC, "venc_core1_jpgenc", "top_venc", 8),
GATE_VENC(CLK_VENC_CORE1_JPGDEC, "venc_core1_jpgdec", "top_venc", 12),
GATE_VENC(CLK_VENC_CORE1_JPGDEC_C1, "venc_core1_jpgdec_c1", "top_venc", 16),
GATE_VENC(CLK_VENC_CORE1_GALS, "venc_core1_gals", "top_venc", 28),
};
static const struct mtk_clk_desc venc_desc = {
.clks = venc_clks,
.num_clks = ARRAY_SIZE(venc_clks),
};
static const struct mtk_clk_desc venc_core1_desc = {
.clks = venc_core1_clks,
.num_clks = ARRAY_SIZE(venc_core1_clks),
};
static const struct of_device_id of_match_clk_mt8195_venc[] = {
{
.compatible = "mediatek,mt8195-vencsys",
.data = &venc_desc,
}, {
.compatible = "mediatek,mt8195-vencsys_core1",
.data = &venc_core1_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_venc);
static struct platform_driver clk_mt8195_venc_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8195-venc",
.of_match_table = of_match_clk_mt8195_venc,
},
};
module_platform_driver(clk_mt8195_venc_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8195-venc.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017 MediaTek Inc.
* Copyright (c) 2023 Collabora, Ltd.
* AngeloGioacchino Del Regno <[email protected]>
*/
#include <dt-bindings/clock/mt7622-clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "clk-cpumux.h"
#include "clk-gate.h"
#include "clk-mtk.h"
#include "reset.h"
#define GATE_INFRA(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate_regs infra_cg_regs = {
.set_ofs = 0x40,
.clr_ofs = 0x44,
.sta_ofs = 0x48,
};
static const char * const infra_mux1_parents[] = {
"clkxtal",
"armpll",
"main_core_en",
"armpll"
};
static const struct mtk_composite cpu_muxes[] = {
MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 0x000, 2, 2),
};
static const struct mtk_gate infra_clks[] = {
GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),
GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2),
GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5),
GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16),
GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18),
GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22),
};
static u16 infrasys_rst_ofs[] = { 0x30 };
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SIMPLE,
.rst_bank_ofs = infrasys_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
};
static const struct of_device_id of_match_clk_mt7622_infracfg[] = {
{ .compatible = "mediatek,mt7622-infracfg" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_infracfg);
static int clk_mt7622_infracfg_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
void __iomem *base;
int ret;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
if (!clk_data)
return -ENOMEM;
ret = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
if (ret)
goto free_clk_data;
ret = mtk_clk_register_gates(&pdev->dev, node, infra_clks,
ARRAY_SIZE(infra_clks), clk_data);
if (ret)
goto free_clk_data;
ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes,
ARRAY_SIZE(cpu_muxes), clk_data);
if (ret)
goto unregister_gates;
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (ret)
goto unregister_cpumuxes;
return 0;
unregister_cpumuxes:
mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
unregister_gates:
mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data);
free_clk_data:
mtk_free_clk_data(clk_data);
return ret;
}
static void clk_mt7622_infracfg_remove(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
of_clk_del_provider(node);
mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data);
mtk_free_clk_data(clk_data);
}
static struct platform_driver clk_mt7622_infracfg_drv = {
.driver = {
.name = "clk-mt7622-infracfg",
.of_match_table = of_match_clk_mt7622_infracfg,
},
.probe = clk_mt7622_infracfg_probe,
.remove_new = clk_mt7622_infracfg_remove,
};
module_platform_driver(clk_mt7622_infracfg_drv);
MODULE_DESCRIPTION("MediaTek MT7622 infracfg clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt7622-infracfg.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Chun-Jie Chen <[email protected]>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/mt8186-clk.h>
#include "clk-mtk.h"
static const char * const mcu_armpll_ll_parents[] = {
"clk26m",
"armpll_ll",
"mainpll",
"univpll_d2"
};
static const char * const mcu_armpll_bl_parents[] = {
"clk26m",
"armpll_bl",
"mainpll",
"univpll_d2"
};
static const char * const mcu_armpll_bus_parents[] = {
"clk26m",
"ccipll",
"mainpll",
"univpll_d2"
};
/*
* We only configure the CPU muxes when adjust CPU frequency in MediaTek CPUFreq Driver.
* Other fields like divider always keep the same value. (set once in bootloader)
*/
static struct mtk_composite mcu_muxes[] = {
/* CPU_PLLDIV_CFG0 */
MUX(CLK_MCU_ARMPLL_LL_SEL, "mcu_armpll_ll_sel", mcu_armpll_ll_parents, 0x2A0, 9, 2),
/* CPU_PLLDIV_CFG1 */
MUX(CLK_MCU_ARMPLL_BL_SEL, "mcu_armpll_bl_sel", mcu_armpll_bl_parents, 0x2A4, 9, 2),
/* BUS_PLLDIV_CFG */
MUX(CLK_MCU_ARMPLL_BUS_SEL, "mcu_armpll_bus_sel", mcu_armpll_bus_parents, 0x2E0, 9, 2),
};
static const struct mtk_clk_desc mcu_desc = {
.composite_clks = mcu_muxes,
.num_composite_clks = ARRAY_SIZE(mcu_muxes),
};
static const struct of_device_id of_match_clk_mt8186_mcu[] = {
{ .compatible = "mediatek,mt8186-mcusys", .data = &mcu_desc },
{ /* sentinel */}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_mcu);
static struct platform_driver clk_mt8186_mcu_drv = {
.driver = {
.name = "clk-mt8186-mcu",
.of_match_table = of_match_clk_mt8186_mcu,
},
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
};
module_platform_driver(clk_mt8186_mcu_drv);
MODULE_DESCRIPTION("MediaTek MT8186 mcusys clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8186-mcu.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Garmin Chang <[email protected]>
*/
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs ipe_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_IPE(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate ipe_clks[] = {
GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "top_ipe", 0),
GATE_IPE(CLK_IPE_FDVT, "ipe_fdvt", "top_ipe", 1),
GATE_IPE(CLK_IPE_ME, "ipe_me", "top_ipe", 2),
GATE_IPE(CLK_IPESYS_TOP, "ipesys_top", "top_ipe", 3),
GATE_IPE(CLK_IPE_SMI_LARB12, "ipe_smi_larb12", "top_ipe", 4),
};
static const struct mtk_clk_desc ipe_desc = {
.clks = ipe_clks,
.num_clks = ARRAY_SIZE(ipe_clks),
};
static const struct of_device_id of_match_clk_mt8188_ipe[] = {
{ .compatible = "mediatek,mt8188-ipesys", .data = &ipe_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_ipe);
static struct platform_driver clk_mt8188_ipe_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8188-ipe",
.of_match_table = of_match_clk_mt8188_ipe,
},
};
module_platform_driver(clk_mt8188_ipe_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8188-ipe.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 MediaTek Inc.
* Author: Owen Chen <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt6765-clk.h>
static const struct mtk_gate_regs cam_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_CAM(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate cam_clks[] = {
GATE_CAM(CLK_CAM_LARB3, "cam_larb3", "mm_ck", 0),
GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "mm_ck", 1),
GATE_CAM(CLK_CAM, "cam", "mm_ck", 6),
GATE_CAM(CLK_CAMTG, "camtg", "mm_ck", 7),
GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "mm_ck", 8),
GATE_CAM(CLK_CAMSV0, "camsv0", "mm_ck", 9),
GATE_CAM(CLK_CAMSV1, "camsv1", "mm_ck", 10),
GATE_CAM(CLK_CAMSV2, "camsv2", "mm_ck", 11),
GATE_CAM(CLK_CAM_CCU, "cam_ccu", "mm_ck", 12),
};
static const struct mtk_clk_desc cam_desc = {
.clks = cam_clks,
.num_clks = ARRAY_SIZE(cam_clks),
};
static const struct of_device_id of_match_clk_mt6765_cam[] = {
{
.compatible = "mediatek,mt6765-camsys",
.data = &cam_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_cam);
static struct platform_driver clk_mt6765_cam_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt6765-cam",
.of_match_table = of_match_clk_mt6765_cam,
},
};
module_platform_driver(clk_mt6765_cam_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt6765-cam.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 MediaTek Inc.
*/
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs cam_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_CAM(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr)
static const struct mtk_gate cam_clks[] = {
GATE_CAM(CLK_CAM_LARB2, "cam_larb2", "mm_sel", 0),
GATE_CAM(CLK_CAM, "cam", "mm_sel", 6),
GATE_CAM(CLK_CAMTG, "camtg", "mm_sel", 7),
GATE_CAM(CLK_CAM_SENIF, "cam_senif", "mm_sel", 8),
GATE_CAM(CLK_CAMSV0, "camsv0", "mm_sel", 9),
GATE_CAM(CLK_CAMSV1, "camsv1", "mm_sel", 10),
GATE_CAM(CLK_CAM_FDVT, "cam_fdvt", "mm_sel", 11),
GATE_CAM(CLK_CAM_WPE, "cam_wpe", "mm_sel", 12),
};
static const struct mtk_clk_desc cam_desc = {
.clks = cam_clks,
.num_clks = ARRAY_SIZE(cam_clks),
};
static const struct of_device_id of_match_clk_mt8365_cam[] = {
{
.compatible = "mediatek,mt8365-imgsys",
.data = &cam_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_cam);
static struct platform_driver clk_mt8365_cam_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8365-cam",
.of_match_table = of_match_clk_mt8365_cam,
},
};
module_platform_driver(clk_mt8365_cam_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8365-cam.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 MediaTek Inc.
*/
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs venc_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_VENC(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate venc_clks[] = {
/* VENC */
GATE_VENC(CLK_VENC, "venc_fvenc_ck", "mm_sel", 4),
GATE_VENC(CLK_VENC_JPGENC, "venc_jpgenc_ck", "mm_sel", 8),
};
static const struct mtk_clk_desc venc_desc = {
.clks = venc_clks,
.num_clks = ARRAY_SIZE(venc_clks),
};
static const struct of_device_id of_match_clk_mt8365_venc[] = {
{
.compatible = "mediatek,mt8365-vencsys",
.data = &venc_desc,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_venc);
static struct platform_driver clk_mt8365_venc_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8365-venc",
.of_match_table = of_match_clk_mt8365_venc,
},
};
module_platform_driver(clk_mt8365_venc_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8365-venc.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Garmin Chang <[email protected]>
*/
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs ccu_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_CCU(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &ccu_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate ccu_clks[] = {
GATE_CCU(CLK_CCU_LARB27, "ccu_larb27", "top_ccu", 0),
GATE_CCU(CLK_CCU_AHB, "ccu_ahb", "top_ccu", 1),
GATE_CCU(CLK_CCU_CCU0, "ccu_ccu0", "top_ccu", 2),
};
static const struct mtk_clk_desc ccu_desc = {
.clks = ccu_clks,
.num_clks = ARRAY_SIZE(ccu_clks),
};
static const struct of_device_id of_match_clk_mt8188_ccu[] = {
{ .compatible = "mediatek,mt8188-ccusys", .data = &ccu_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_ccu);
static struct platform_driver clk_mt8188_ccu_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8188-ccu",
.of_match_table = of_match_clk_mt8188_ccu,
},
};
module_platform_driver(clk_mt8188_ccu_drv);
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8188-ccu.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* Copyright (c) 2022 Collabora Ltd.
* Author: AngeloGioacchino Del Regno <[email protected]>
*/
#include <dt-bindings/clock/mt8173-clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#define GATE_VDEC(_id, _name, _parent, _regs) \
GATE_MTK(_id, _name, _parent, _regs, 0, \
&mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate_regs vdec0_cg_regs = {
.set_ofs = 0x0000,
.clr_ofs = 0x0004,
.sta_ofs = 0x0000,
};
static const struct mtk_gate_regs vdec1_cg_regs = {
.set_ofs = 0x0008,
.clr_ofs = 0x000c,
.sta_ofs = 0x0008,
};
static const struct mtk_gate vdec_clks[] = {
GATE_DUMMY(CLK_DUMMY, "vdec_dummy"),
GATE_VDEC(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", &vdec0_cg_regs),
GATE_VDEC(CLK_VDEC_LARB_CKEN, "vdec_larb_cken", "mm_sel", &vdec1_cg_regs),
};
static const struct mtk_clk_desc vdec_desc = {
.clks = vdec_clks,
.num_clks = ARRAY_SIZE(vdec_clks),
};
static const struct of_device_id of_match_clk_mt8173_vdecsys[] = {
{ .compatible = "mediatek,mt8173-vdecsys", .data = &vdec_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_vdecsys);
static struct platform_driver clk_mt8173_vdecsys_drv = {
.probe = mtk_clk_simple_probe,
.remove_new = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8173-vdecsys",
.of_match_table = of_match_clk_mt8173_vdecsys,
},
};
module_platform_driver(clk_mt8173_vdecsys_drv);
MODULE_DESCRIPTION("MediaTek MT8173 vdecsys clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8173-vdecsys.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* Copyright (c) 2022 Collabora Ltd.
* Author: AngeloGioacchino Del Regno <[email protected]>
*/
#include <dt-bindings/clock/mt8173-clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "clk-cpumux.h"
#include "clk-gate.h"
#include "clk-mtk.h"
#include "reset.h"
#define GATE_ICG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &infra_cg_regs, \
_shift, &mtk_clk_gate_ops_setclr)
static struct clk_hw_onecell_data *infra_clk_data;
static const struct mtk_gate_regs infra_cg_regs = {
.set_ofs = 0x0040,
.clr_ofs = 0x0044,
.sta_ofs = 0x0048,
};
static const char * const ca53_parents[] __initconst = {
"clk26m",
"armca7pll",
"mainpll",
"univpll"
};
static const char * const ca72_parents[] __initconst = {
"clk26m",
"armca15pll",
"mainpll",
"univpll"
};
static const struct mtk_composite cpu_muxes[] = {
MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2),
};
static const struct mtk_fixed_factor infra_early_divs[] = {
FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
};
static const struct mtk_gate infra_gates[] = {
GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1),
GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5),
GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7),
GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "cpum_ck", 15),
GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
GATE_ICG(CLK_INFRA_CEC, "infra_cec", "clk26m", 18),
GATE_ICG(CLK_INFRA_PMICSPI, "infra_pmicspi", "pmicspi_sel", 22),
GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23),
};
static u16 infrasys_rst_ofs[] = { 0x30, 0x34 };
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SIMPLE,
.rst_bank_ofs = infrasys_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
};
static const struct of_device_id of_match_clk_mt8173_infracfg[] = {
{ .compatible = "mediatek,mt8173-infracfg" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_infracfg);
static void clk_mt8173_infra_init_early(struct device_node *node)
{
int i;
infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
if (!infra_clk_data)
return;
for (i = 0; i < CLK_INFRA_NR_CLK; i++)
infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
mtk_clk_register_factors(infra_early_divs,
ARRAY_SIZE(infra_early_divs), infra_clk_data);
of_clk_add_hw_provider(node, of_clk_hw_onecell_get, infra_clk_data);
}
CLK_OF_DECLARE_DRIVER(mtk_infrasys, "mediatek,mt8173-infracfg",
clk_mt8173_infra_init_early);
static int clk_mt8173_infracfg_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
int r;
r = mtk_clk_register_gates(&pdev->dev, node, infra_gates,
ARRAY_SIZE(infra_gates), infra_clk_data);
if (r)
return r;
r = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes,
ARRAY_SIZE(cpu_muxes), infra_clk_data);
if (r)
goto unregister_gates;
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, infra_clk_data);
if (r)
goto unregister_cpumuxes;
r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
if (r)
goto unregister_clk_hw;
return 0;
unregister_clk_hw:
of_clk_del_provider(node);
unregister_cpumuxes:
mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), infra_clk_data);
unregister_gates:
mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), infra_clk_data);
return r;
}
static void clk_mt8173_infracfg_remove(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
of_clk_del_provider(node);
mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data);
mtk_free_clk_data(clk_data);
}
static struct platform_driver clk_mt8173_infracfg_drv = {
.driver = {
.name = "clk-mt8173-infracfg",
.of_match_table = of_match_clk_mt8173_infracfg,
},
.probe = clk_mt8173_infracfg_probe,
.remove_new = clk_mt8173_infracfg_remove,
};
module_platform_driver(clk_mt8173_infracfg_drv);
MODULE_DESCRIPTION("MediaTek MT8173 infracfg clocks driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/clk/mediatek/clk-mt8173-infracfg.c |
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