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139,052 | data/full_repos/permissive/86722304/src/alarm.v | 86,722,304 | alarm.v | v | 49 | 76 | [] | [] | [] | null | line:9: before: ";" | null | 1: b"%Error: data/full_repos/permissive/86722304/src/alarm.v:9: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'ALARM_DLY_TICKS'\n : ... In instance alarm\n parameter ALARM_DLY_TICKS;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/alarm.v:10: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'ALARM_TICKS'\n : ... In instance alarm\n parameter ALARM_TICKS;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/alarm.v:12: Expecting expression to be constant, but variable isn't const: 'ALARM_DLY_TICKS'\n : ... In instance alarm\n localparam width = $clog2(ALARM_DLY_TICKS+1);\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 304,268 | module | module alarm(
input clk_sys,
input engage,
output talarm
);
parameter ALARM_DLY_TICKS;
parameter ALARM_TICKS;
localparam width = $clog2(ALARM_DLY_TICKS+1);
localparam S_IDLE = 'd0;
localparam S_WAIT = 'd1;
localparam S_ALARM = 'd2;
reg [0:width-1] alarm_cnt;
reg [0:1] state = S_IDLE;
always @ (posedge clk_sys) begin
case (state)
S_IDLE:
if (engage) begin
alarm_cnt <= ALARM_DLY_TICKS;
state <= S_WAIT;
end
S_WAIT:
if (~engage) state <= S_IDLE;
else if (alarm_cnt == 0) begin
state <= S_ALARM;
alarm_cnt <= ALARM_TICKS;
end else alarm_cnt <= alarm_cnt - 1'b1;
S_ALARM:
if (alarm_cnt == 0) state <= S_IDLE;
else alarm_cnt <= alarm_cnt - 1'b1;
endcase
end
assign talarm = (state == S_ALARM);
endmodule | module alarm(
input clk_sys,
input engage,
output talarm
); |
parameter ALARM_DLY_TICKS;
parameter ALARM_TICKS;
localparam width = $clog2(ALARM_DLY_TICKS+1);
localparam S_IDLE = 'd0;
localparam S_WAIT = 'd1;
localparam S_ALARM = 'd2;
reg [0:width-1] alarm_cnt;
reg [0:1] state = S_IDLE;
always @ (posedge clk_sys) begin
case (state)
S_IDLE:
if (engage) begin
alarm_cnt <= ALARM_DLY_TICKS;
state <= S_WAIT;
end
S_WAIT:
if (~engage) state <= S_IDLE;
else if (alarm_cnt == 0) begin
state <= S_ALARM;
alarm_cnt <= ALARM_TICKS;
end else alarm_cnt <= alarm_cnt - 1'b1;
S_ALARM:
if (alarm_cnt == 0) state <= S_IDLE;
else alarm_cnt <= alarm_cnt - 1'b1;
endcase
end
assign talarm = (state == S_ALARM);
endmodule | 24 |
139,053 | data/full_repos/permissive/86722304/src/alu.v | 86,722,304 | alu.v | v | 122 | 54 | [] | [] | [] | null | line:43: before: ";" | null | 1: b'%Error: data/full_repos/permissive/86722304/src/alu.v:43: Unsupported: wor\n wor __NC;\n ^~~\n%Error: Exiting due to 1 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,269 | module | module alu(
input p16_,
input [0:15] a,
input [0:15] ac,
input saryt,
input sd, sb,
input scb, sab,
input sca, saa,
output [0:15] f,
output j$,
output carry,
output zsum
);
wor __NC;
wire [3:0] g, p;
wire [3:1] c_;
wire [3:0] j$1;
wire carry_;
alu181 ALU_0_3(
.a(a[0:3]),
.b(ac[0:3]),
.m(~saryt),
.c_(c_[3]),
.s({~sd, ~scb, ~sb, ~sab}),
.f(f[0:3]),
.g(g[3]),
.p(p[3]),
.co_(carry_),
.eq(j$1[3])
);
alu181 ALU_4_7(
.a(a[4:7]),
.b(ac[4:7]),
.m(~saryt),
.c_(c_[2]),
.s({~sd, ~scb, ~sb, ~sab}),
.f(f[4:7]),
.p(p[2]),
.g(g[2]),
.co_(__NC),
.eq(j$1[2])
);
alu181 ALU_8_11(
.a(a[8:11]),
.b(ac[8:11]),
.m(~saryt),
.c_(c_[1]),
.s({~sd, ~sca, ~sb, ~saa}),
.f(f[8:11]),
.p(p[1]),
.g(g[1]),
.co_(__NC),
.eq(j$1[1])
);
alu181 ALU_12_15(
.a(a[12:15]),
.b(ac[12:15]),
.m(~saryt),
.c_(p16_),
.s({~sd, ~sca, ~sb, ~saa}),
.f(f[12:15]),
.p(p[0]),
.g(g[0]),
.co_(__NC),
.eq(j$1[0])
);
carry182 CARRY(
.g(g),
.p(p),
.c_(p16_),
.c1_(c_[1]),
.c2_(c_[2]),
.c3_(c_[3]),
.op(__NC),
.og(__NC)
);
assign carry = ~carry_;
assign zsum = ~|f;
assign j$ = &j$1;
endmodule | module alu(
input p16_,
input [0:15] a,
input [0:15] ac,
input saryt,
input sd, sb,
input scb, sab,
input sca, saa,
output [0:15] f,
output j$,
output carry,
output zsum
); |
wor __NC;
wire [3:0] g, p;
wire [3:1] c_;
wire [3:0] j$1;
wire carry_;
alu181 ALU_0_3(
.a(a[0:3]),
.b(ac[0:3]),
.m(~saryt),
.c_(c_[3]),
.s({~sd, ~scb, ~sb, ~sab}),
.f(f[0:3]),
.g(g[3]),
.p(p[3]),
.co_(carry_),
.eq(j$1[3])
);
alu181 ALU_4_7(
.a(a[4:7]),
.b(ac[4:7]),
.m(~saryt),
.c_(c_[2]),
.s({~sd, ~scb, ~sb, ~sab}),
.f(f[4:7]),
.p(p[2]),
.g(g[2]),
.co_(__NC),
.eq(j$1[2])
);
alu181 ALU_8_11(
.a(a[8:11]),
.b(ac[8:11]),
.m(~saryt),
.c_(c_[1]),
.s({~sd, ~sca, ~sb, ~saa}),
.f(f[8:11]),
.p(p[1]),
.g(g[1]),
.co_(__NC),
.eq(j$1[1])
);
alu181 ALU_12_15(
.a(a[12:15]),
.b(ac[12:15]),
.m(~saryt),
.c_(p16_),
.s({~sd, ~sca, ~sb, ~saa}),
.f(f[12:15]),
.p(p[0]),
.g(g[0]),
.co_(__NC),
.eq(j$1[0])
);
carry182 CARRY(
.g(g),
.p(p),
.c_(p16_),
.c1_(c_[1]),
.c2_(c_[2]),
.c3_(c_[3]),
.op(__NC),
.og(__NC)
);
assign carry = ~carry_;
assign zsum = ~|f;
assign j$ = &j$1;
endmodule | 24 |
139,054 | data/full_repos/permissive/86722304/src/alu181.v | 86,722,304 | alu181.v | v | 41 | 100 | [] | [] | [] | [(3, 38)] | null | data/verilator_xmls/2aeb6beb-dd6e-4aac-820f-4b00f2c715ab.xml | null | 304,270 | module | module alu181(
input [3:0] a, b,
input m,
input c_,
input [3:0] s,
output [3:0] f,
output g, p,
output co_,
output eq
);
wire [3:0] s0 = {4{s[0]}};
wire [3:0] s1 = {4{s[1]}};
wire [3:0] s2 = {4{s[2]}};
wire [3:0] s3 = {4{s[3]}};
wire [3:0] u = ~((a) | (b & s0) | (~b & s1));
wire [3:0] v = ~((~b & s2 & a) | (b & s3 & a));
wire [3:0] w = u ^ v;
wire [3:0] z;
assign z[0] = ~(~m & c_);
assign z[1] = ~(~m & ((u[0]) | (v[0] & c_)));
assign z[2] = ~(~m & ((u[1]) | (u[0] & v[1]) | (v[1] & v[0] & c_)));
assign z[3] = ~(~m & ((u[2]) | (v[2] & u[1]) | (v[2] & u[0] & v[1]) | (v[2] & v[1] & v[0] & c_)));
assign g = ~((u[0] & v[1] & v[2] & v[3]) | (u[1] & v[2] & v[3]) | (u[2] & v[3]) | (u[3]));
assign p = ~(&v);
wire g2 = ~(&v & c_);
assign co_ = ~g2 | ~g;
assign f = w ^ z;
assign eq = &f;
endmodule | module alu181(
input [3:0] a, b,
input m,
input c_,
input [3:0] s,
output [3:0] f,
output g, p,
output co_,
output eq
); |
wire [3:0] s0 = {4{s[0]}};
wire [3:0] s1 = {4{s[1]}};
wire [3:0] s2 = {4{s[2]}};
wire [3:0] s3 = {4{s[3]}};
wire [3:0] u = ~((a) | (b & s0) | (~b & s1));
wire [3:0] v = ~((~b & s2 & a) | (b & s3 & a));
wire [3:0] w = u ^ v;
wire [3:0] z;
assign z[0] = ~(~m & c_);
assign z[1] = ~(~m & ((u[0]) | (v[0] & c_)));
assign z[2] = ~(~m & ((u[1]) | (u[0] & v[1]) | (v[1] & v[0] & c_)));
assign z[3] = ~(~m & ((u[2]) | (v[2] & u[1]) | (v[2] & u[0] & v[1]) | (v[2] & v[1] & v[0] & c_)));
assign g = ~((u[0] & v[1] & v[2] & v[3]) | (u[1] & v[2] & v[3]) | (u[2] & v[3]) | (u[3]));
assign p = ~(&v);
wire g2 = ~(&v & c_);
assign co_ = ~g2 | ~g;
assign f = w ^ z;
assign eq = &f;
endmodule | 24 |
139,056 | data/full_repos/permissive/86722304/src/at.v | 86,722,304 | at.v | v | 24 | 126 | [] | [] | [] | [(3, 21)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/at.v:8: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] f,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/at.v:9: Little bit endian vector: MSB < LSB of bit range: 0:15\n output reg [0:15] at\n ^\n%Error: Exiting due to 2 warning(s)\n' | 304,272 | module | module at(
input clk_sys,
input s0, s1,
input c,
input sl,
input [0:15] f,
output reg [0:15] at
);
always @ (posedge clk_sys) begin
if (c) case ({s1, s0})
2'b00 : at <= at;
2'b01 : at <= {sl, at[0:14]};
2'b10 : at <= at;
2'b11 : at <= f;
endcase
end
endmodule | module at(
input clk_sys,
input s0, s1,
input c,
input sl,
input [0:15] f,
output reg [0:15] at
); |
always @ (posedge clk_sys) begin
if (c) case ({s1, s0})
2'b00 : at <= at;
2'b01 : at <= {sl, at[0:14]};
2'b10 : at <= at;
2'b11 : at <= f;
endcase
end
endmodule | 24 |
139,057 | data/full_repos/permissive/86722304/src/awp.v | 86,722,304 | awp.v | v | 341 | 245 | [] | [] | [] | [(3, 338)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/awp.v:5: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] w,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/awp.v:9: Little bit endian vector: MSB < LSB of bit range: 7:9\n input [7:9] ir,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/awp.v:19: Little bit endian vector: MSB < LSB of bit range: 0:15\n output [0:15] zp, \n ^\n%Error: data/full_repos/permissive/86722304/src/awp.v:43: Cannot find file containing module: \'fps\'\nfps FPS(\n^~~\n ... Looked in:\n data/full_repos/permissive/86722304/src,data/full_repos/permissive/86722304/fps\n data/full_repos/permissive/86722304/src,data/full_repos/permissive/86722304/fps.v\n data/full_repos/permissive/86722304/src,data/full_repos/permissive/86722304/fps.sv\n fps\n fps.v\n fps.sv\n obj_dir/fps\n obj_dir/fps.v\n obj_dir/fps.sv\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/awp.v:150: Little bit endian vector: MSB < LSB of bit range: -2:7\nwire [-2:7] d;\n ^\n%Error: data/full_repos/permissive/86722304/src/awp.v:153: Cannot find file containing module: \'fpm\'\nfpm FPM(\n^~~\n%Error: data/full_repos/permissive/86722304/src/awp.v:268: Cannot find file containing module: \'fpa\'\nfpa FPA(\n^~~\n%Error: Exiting due to 3 error(s), 4 warning(s)\n' | 304,273 | module | module awp(
input clk_sys,
input [0:15] w,
input r02,
input r03,
input pufa,
input [7:9] ir,
input nrf,
input mode,
input step,
input efp,
input got,
input ldstate,
input ok$,
input oken,
input zw,
output [0:15] zp,
output fi0,
output fi1,
output fi2,
output fi3,
output rlp_fp,
output lpa,
output lpb,
output s_fp,
output ustr0_fp,
output f13,
output strob_fp,
output strobb_fp,
output sr_fp,
output read_fp,
output ekc_fp
);
wire strob2_fp, strob2b_fp, _0_f, _0_t, lkb, l_d, clocktc, clocktb, clockta, t_c, fcb, t_1_t_1, tab, trb, taa, cp, frb, p_16, p_32, p_40, fab, faa, fra, f5, f6, f2, f4, f10, f9, f8, f7, scc, pc8, _0_d, _0_m, mb, ma, clockm, zpa, zpb, _0_zp, lp;
fps FPS(
.clk_sys(clk_sys),
.mode(mode),
.step(step),
.strob_fp(strob_fp),
.strobb_fp(strobb_fp),
.strob2_fp(strob2_fp),
.strob2b_fp(strob2b_fp),
.oken(oken),
.zw(zw),
.di(di),
.efp(efp),
.puf(puf),
.got(got),
.ldstate(ldstate),
.sr_fp(sr_fp),
.ekc_fp(ekc_fp),
._0_f(_0_f),
.g(g),
.wdt(wdt),
.af_sf(af_sf),
.mw(mw),
._0_t(_0_t),
.lkb(lkb),
.l_d(l_d),
.clocktc(clocktc),
.clocktb(clocktb),
.clockta(clockta),
.t_c(t_c),
.fcb(fcb),
.mf(mf),
.fp16_(fp16_),
.t_1_t_1(t_1_t_1),
.tab(tab),
.trb(trb),
.taa(taa),
.cp(cp),
.sd(sd),
.ck(ck),
.sf(sf),
.p32_(p32_),
.m14(m14),
.t0_eq_c0(t0_eq_c0),
.m38(m38),
.t0_neq_c0(t0_neq_c0),
.ws(ws),
.df(df),
.af(af),
.ad(ad),
.frb(frb),
.p_16(p_16),
.p_32(p_32),
.p_40(p_40),
.fab(fab),
.faa(faa),
.fra(fra),
.fic(fic),
.ad_sd(ad_sd),
.ta(ta),
.sgn_t0_c0(sgn_t0_c0),
.opsu(opsu),
.wc(wc),
.wt(wt),
.dw(dw),
.ss(ss),
.f5(f5),
.f6(f6),
.f2(f2),
.f4(f4),
.ok$(ok$),
.ff(ff),
.read_fp(read_fp),
.sgn(sgn),
.fwz(fwz),
.nrf(nrf),
.nz(nz),
.t0_neq_t_1(t0_neq_t_1),
.ok(ok),
.f13(f13),
.f10(f10),
.f9(f9),
.f8(f8),
.f7(f7),
.dw_df(dw_df),
.mw_mf(mw_mf),
.scc(scc),
.pc8(pc8),
._0_d(_0_d),
._0_m(_0_m),
.mb(mb),
.ma(ma),
.clockm(clockm),
.rlp_fp(rlp_fp),
.lpa(lpa),
.zpa(zpa),
.zpb(zpb),
._0_zp(_0_zp),
.s_fp(s_fp),
.ustr0_fp(ustr0_fp),
.lp(lp),
.lpb(lpb)
);
wire [-2:7] d;
wire g, wdt, wt, fic, c_f, v_f, m_f, z_f, dw, ad, sd, mw, af, sf, mf, df, dw_df, mw_mf, af_sf, ad_sd, ff, ss, puf, fwz, ws, di, wc, t_1, t0_neq_t_1, ok, nz, opsu, ta, m_1, ck, m_40, m_32, sgn_t0_c0, sgn, t_1_d, m_1_d;
fpm FPM(
.t_1_d(t_1_d),
.m_1_d(m_1_d),
.clk_sys(clk_sys),
.w(w[8:15]),
.l_d(l_d),
._0_d(_0_d),
.lkb(lkb),
.d(d),
.fcb(fcb),
.scc(scc),
.pc8(pc8),
._0_f(_0_f),
.f2(f2),
.f5(f5),
.strob_fp(strob_fp),
.strobb_fp(strobb_fp),
.strob2_fp(strob2_fp),
.strob2b_fp(strob2b_fp),
.g(g),
.wdt(wdt),
.wt(wt),
.fic(fic),
.r03(r03),
.r02(r02),
.t16(t16),
.c_f(c_f),
.v_f(v_f),
.m_f(m_f),
.z_f(z_f),
.dw(dw),
.ir(ir),
.pufa(pufa),
.f9(f9),
.nrf(nrf),
.ad(ad),
.sd(sd),
.mw(mw),
.af(af),
.sf(sf),
.mf(mf),
.df(df),
.dw_df(dw_df),
.mw_mf(mw_mf),
.af_sf(af_sf),
.ad_sd(ad_sd),
.ff(ff),
.ss(ss),
.puf(puf),
.f10(f10),
.f7(f7),
.f6(f6),
.fwz(fwz),
.ws(ws),
.lp(lp),
.f8(f8),
.f13(f13),
.di(di),
.wc(wc),
.fi0(fi0),
.fi1(fi1),
.fi2(fi2),
.fi3(fi3),
.w0_(~w[0]),
.t_1_t_1(t_1_t_1),
.fp0_(fp0_),
.fab(fab),
.faa(faa),
.c0(c0),
._0_t(_0_t),
.t0_neq_t1(t0_neq_t1),
.c0_eq_c1(c0_eq_c1),
.t1(t1),
.t0(t0),
.clockta(clockta),
.t_0_1(t_0_1),
.t_2_7(t_2_7),
.t_8_15(t_8_15),
.t_16_23(t_16_23),
.t_24_31(t_24_31),
.t_32_39(t_32_39),
.t_1(t_1),
.t0_neq_t_1(t0_neq_t_1),
.ok(ok),
.nz(nz),
.opsu(opsu),
.ta(ta),
.trb(trb),
.t39(t39),
.m0(m0),
.mb(mb),
.c39(c39),
.f4(f4),
.clockm(clockm),
._0_m(_0_m),
.m39(m39),
.m15(m15),
.m38(m38),
.m14(m14),
.m_1(m_1),
.ck(ck),
.m32(m32),
.t0_neq_c0(t0_neq_c0),
.m_40(m_40),
.m_32(m_32),
.sgn_t0_c0(sgn_t0_c0),
.sgn(sgn)
);
wire t_0_1, t_2_7, c0_eq_c1, c0, t1, t0_eq_c0, t0_neq_c0, t0_neq_t1, m0, t0, fp0_, t_8_15, m14, m15, fp16_, t16, m32, m38, m39, c39, p32_, t39, t_32_39, t_16_23, t_24_31;
fpa FPA(
.clk_sys(clk_sys),
.t_1_d(t_1_d),
.m_1_d(m_1_d),
.t0_neq_t_1(t0_neq_t_1),
.strob_fp(strob_fp),
.strobb_fp(strobb_fp),
.w(w),
.taa(taa),
.t_1(t_1),
.tab(tab),
.clockta(clockta),
.clocktb(clocktb),
.clocktc(clocktc),
.t_0_1(t_0_1),
.t_2_7(t_2_7),
.t_8_15(t_8_15),
.t_32_39(t_32_39),
.t_16_23(t_16_23),
.t_24_31(t_24_31),
.m_1(m_1),
.ma(ma),
.mb(mb),
.clockm(clockm),
._0_m(_0_m),
.c0_eq_c1(c0_eq_c1),
.c0(c0),
.t1(t1),
.t0_eq_c0(t0_eq_c0),
.t0_neq_c0(t0_neq_c0),
.t0_neq_t1(t0_neq_t1),
.m0(m0),
.t0(t0),
.fab(fab),
.faa(faa),
.fp0_(fp0_),
.p_16(p_16),
.m14(m14),
.m15(m15),
.fp16_(fp16_),
.t16(t16),
.m_32(m_32),
.p_32(p_32),
.m_40(m_40),
.cp(cp),
.t_c(t_c),
.m32(m32),
.m38(m38),
.m39(m39),
.c39(c39),
.fra(fra),
.frb(frb),
.p_40(p_40),
.p32_(p32_),
.trb(trb),
._0_t(_0_t),
.t39(t39),
.f9(f9),
.lkb(lkb),
.z_f(z_f),
.m_f(m_f),
.v_f(v_f),
.c_f(c_f),
.zp(zp),
.d(d),
._0_zp(_0_zp),
.zpb(zpb),
.zpa(zpa)
);
endmodule | module awp(
input clk_sys,
input [0:15] w,
input r02,
input r03,
input pufa,
input [7:9] ir,
input nrf,
input mode,
input step,
input efp,
input got,
input ldstate,
input ok$,
input oken,
input zw,
output [0:15] zp,
output fi0,
output fi1,
output fi2,
output fi3,
output rlp_fp,
output lpa,
output lpb,
output s_fp,
output ustr0_fp,
output f13,
output strob_fp,
output strobb_fp,
output sr_fp,
output read_fp,
output ekc_fp
); |
wire strob2_fp, strob2b_fp, _0_f, _0_t, lkb, l_d, clocktc, clocktb, clockta, t_c, fcb, t_1_t_1, tab, trb, taa, cp, frb, p_16, p_32, p_40, fab, faa, fra, f5, f6, f2, f4, f10, f9, f8, f7, scc, pc8, _0_d, _0_m, mb, ma, clockm, zpa, zpb, _0_zp, lp;
fps FPS(
.clk_sys(clk_sys),
.mode(mode),
.step(step),
.strob_fp(strob_fp),
.strobb_fp(strobb_fp),
.strob2_fp(strob2_fp),
.strob2b_fp(strob2b_fp),
.oken(oken),
.zw(zw),
.di(di),
.efp(efp),
.puf(puf),
.got(got),
.ldstate(ldstate),
.sr_fp(sr_fp),
.ekc_fp(ekc_fp),
._0_f(_0_f),
.g(g),
.wdt(wdt),
.af_sf(af_sf),
.mw(mw),
._0_t(_0_t),
.lkb(lkb),
.l_d(l_d),
.clocktc(clocktc),
.clocktb(clocktb),
.clockta(clockta),
.t_c(t_c),
.fcb(fcb),
.mf(mf),
.fp16_(fp16_),
.t_1_t_1(t_1_t_1),
.tab(tab),
.trb(trb),
.taa(taa),
.cp(cp),
.sd(sd),
.ck(ck),
.sf(sf),
.p32_(p32_),
.m14(m14),
.t0_eq_c0(t0_eq_c0),
.m38(m38),
.t0_neq_c0(t0_neq_c0),
.ws(ws),
.df(df),
.af(af),
.ad(ad),
.frb(frb),
.p_16(p_16),
.p_32(p_32),
.p_40(p_40),
.fab(fab),
.faa(faa),
.fra(fra),
.fic(fic),
.ad_sd(ad_sd),
.ta(ta),
.sgn_t0_c0(sgn_t0_c0),
.opsu(opsu),
.wc(wc),
.wt(wt),
.dw(dw),
.ss(ss),
.f5(f5),
.f6(f6),
.f2(f2),
.f4(f4),
.ok$(ok$),
.ff(ff),
.read_fp(read_fp),
.sgn(sgn),
.fwz(fwz),
.nrf(nrf),
.nz(nz),
.t0_neq_t_1(t0_neq_t_1),
.ok(ok),
.f13(f13),
.f10(f10),
.f9(f9),
.f8(f8),
.f7(f7),
.dw_df(dw_df),
.mw_mf(mw_mf),
.scc(scc),
.pc8(pc8),
._0_d(_0_d),
._0_m(_0_m),
.mb(mb),
.ma(ma),
.clockm(clockm),
.rlp_fp(rlp_fp),
.lpa(lpa),
.zpa(zpa),
.zpb(zpb),
._0_zp(_0_zp),
.s_fp(s_fp),
.ustr0_fp(ustr0_fp),
.lp(lp),
.lpb(lpb)
);
wire [-2:7] d;
wire g, wdt, wt, fic, c_f, v_f, m_f, z_f, dw, ad, sd, mw, af, sf, mf, df, dw_df, mw_mf, af_sf, ad_sd, ff, ss, puf, fwz, ws, di, wc, t_1, t0_neq_t_1, ok, nz, opsu, ta, m_1, ck, m_40, m_32, sgn_t0_c0, sgn, t_1_d, m_1_d;
fpm FPM(
.t_1_d(t_1_d),
.m_1_d(m_1_d),
.clk_sys(clk_sys),
.w(w[8:15]),
.l_d(l_d),
._0_d(_0_d),
.lkb(lkb),
.d(d),
.fcb(fcb),
.scc(scc),
.pc8(pc8),
._0_f(_0_f),
.f2(f2),
.f5(f5),
.strob_fp(strob_fp),
.strobb_fp(strobb_fp),
.strob2_fp(strob2_fp),
.strob2b_fp(strob2b_fp),
.g(g),
.wdt(wdt),
.wt(wt),
.fic(fic),
.r03(r03),
.r02(r02),
.t16(t16),
.c_f(c_f),
.v_f(v_f),
.m_f(m_f),
.z_f(z_f),
.dw(dw),
.ir(ir),
.pufa(pufa),
.f9(f9),
.nrf(nrf),
.ad(ad),
.sd(sd),
.mw(mw),
.af(af),
.sf(sf),
.mf(mf),
.df(df),
.dw_df(dw_df),
.mw_mf(mw_mf),
.af_sf(af_sf),
.ad_sd(ad_sd),
.ff(ff),
.ss(ss),
.puf(puf),
.f10(f10),
.f7(f7),
.f6(f6),
.fwz(fwz),
.ws(ws),
.lp(lp),
.f8(f8),
.f13(f13),
.di(di),
.wc(wc),
.fi0(fi0),
.fi1(fi1),
.fi2(fi2),
.fi3(fi3),
.w0_(~w[0]),
.t_1_t_1(t_1_t_1),
.fp0_(fp0_),
.fab(fab),
.faa(faa),
.c0(c0),
._0_t(_0_t),
.t0_neq_t1(t0_neq_t1),
.c0_eq_c1(c0_eq_c1),
.t1(t1),
.t0(t0),
.clockta(clockta),
.t_0_1(t_0_1),
.t_2_7(t_2_7),
.t_8_15(t_8_15),
.t_16_23(t_16_23),
.t_24_31(t_24_31),
.t_32_39(t_32_39),
.t_1(t_1),
.t0_neq_t_1(t0_neq_t_1),
.ok(ok),
.nz(nz),
.opsu(opsu),
.ta(ta),
.trb(trb),
.t39(t39),
.m0(m0),
.mb(mb),
.c39(c39),
.f4(f4),
.clockm(clockm),
._0_m(_0_m),
.m39(m39),
.m15(m15),
.m38(m38),
.m14(m14),
.m_1(m_1),
.ck(ck),
.m32(m32),
.t0_neq_c0(t0_neq_c0),
.m_40(m_40),
.m_32(m_32),
.sgn_t0_c0(sgn_t0_c0),
.sgn(sgn)
);
wire t_0_1, t_2_7, c0_eq_c1, c0, t1, t0_eq_c0, t0_neq_c0, t0_neq_t1, m0, t0, fp0_, t_8_15, m14, m15, fp16_, t16, m32, m38, m39, c39, p32_, t39, t_32_39, t_16_23, t_24_31;
fpa FPA(
.clk_sys(clk_sys),
.t_1_d(t_1_d),
.m_1_d(m_1_d),
.t0_neq_t_1(t0_neq_t_1),
.strob_fp(strob_fp),
.strobb_fp(strobb_fp),
.w(w),
.taa(taa),
.t_1(t_1),
.tab(tab),
.clockta(clockta),
.clocktb(clocktb),
.clocktc(clocktc),
.t_0_1(t_0_1),
.t_2_7(t_2_7),
.t_8_15(t_8_15),
.t_32_39(t_32_39),
.t_16_23(t_16_23),
.t_24_31(t_24_31),
.m_1(m_1),
.ma(ma),
.mb(mb),
.clockm(clockm),
._0_m(_0_m),
.c0_eq_c1(c0_eq_c1),
.c0(c0),
.t1(t1),
.t0_eq_c0(t0_eq_c0),
.t0_neq_c0(t0_neq_c0),
.t0_neq_t1(t0_neq_t1),
.m0(m0),
.t0(t0),
.fab(fab),
.faa(faa),
.fp0_(fp0_),
.p_16(p_16),
.m14(m14),
.m15(m15),
.fp16_(fp16_),
.t16(t16),
.m_32(m_32),
.p_32(p_32),
.m_40(m_40),
.cp(cp),
.t_c(t_c),
.m32(m32),
.m38(m38),
.m39(m39),
.c39(c39),
.fra(fra),
.frb(frb),
.p_40(p_40),
.p32_(p32_),
.trb(trb),
._0_t(_0_t),
.t39(t39),
.f9(f9),
.lkb(lkb),
.z_f(z_f),
.m_f(m_f),
.v_f(v_f),
.c_f(c_f),
.zp(zp),
.d(d),
._0_zp(_0_zp),
.zpb(zpb),
.zpa(zpa)
);
endmodule | 24 |
139,058 | data/full_repos/permissive/86722304/src/b.v | 86,722,304 | b.v | v | 30 | 54 | [] | [] | [] | [(1, 27)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/b.v:4: Little bit endian vector: MSB < LSB of bit range: 0:7\n input [0:7] d,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/b.v:8: Little bit endian vector: MSB < LSB of bit range: 0:7\n output [0:7] b\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/b.v:11: Little bit endian vector: MSB < LSB of bit range: 0:7\n reg [0:7] b_reg;\n ^\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/b.v:20: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'b\'\n : ... In instance b\n 2\'b00: b <= ~b_reg;\n ^\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/b.v:21: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'b\'\n : ... In instance b\n 2\'b01: b <= b_reg;\n ^\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/b.v:22: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'b\'\n : ... In instance b\n 2\'b10: b <= 8\'hff;\n ^\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/b.v:23: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'b\'\n : ... In instance b\n 2\'b11: b <= 8\'h00;\n ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n' | 304,274 | module | module b(
input clk_sys,
input f2strob,
input [0:7] d,
input fcb,
input scc,
output b0,
output [0:7] b
);
reg [0:7] b_reg;
always @ (posedge clk_sys) begin
if (f2strob) b_reg <= d;
end
assign b0 = b_reg[0];
always @ (*) begin
case ({fcb, scc})
2'b00: b <= ~b_reg;
2'b01: b <= b_reg;
2'b10: b <= 8'hff;
2'b11: b <= 8'h00;
endcase
end
endmodule | module b(
input clk_sys,
input f2strob,
input [0:7] d,
input fcb,
input scc,
output b0,
output [0:7] b
); |
reg [0:7] b_reg;
always @ (posedge clk_sys) begin
if (f2strob) b_reg <= d;
end
assign b0 = b_reg[0];
always @ (*) begin
case ({fcb, scc})
2'b00: b <= ~b_reg;
2'b01: b <= b_reg;
2'b10: b <= 8'hff;
2'b11: b <= 8'h00;
endcase
end
endmodule | 24 |
139,059 | data/full_repos/permissive/86722304/src/bar.v | 86,722,304 | bar.v | v | 29 | 54 | [] | [] | [] | [(8, 26)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/bar.v:10: Little bit endian vector: MSB < LSB of bit range: 10:15\n input [10:15] w,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/bar.v:14: Little bit endian vector: MSB < LSB of bit range: 0:5\n output reg [0:5] bar\n ^\n%Error: Exiting due to 2 warning(s)\n' | 304,275 | module | module bar(
input clk_sys,
input [10:15] w,
input cnb,
input clm,
input zer_sp,
output reg [0:5] bar
);
always @ (posedge clk_sys, posedge clm) begin
if (clm) bar <= 6'd0;
else begin
if (cnb) bar[1:5] <= w[11:15];
if (zer_sp) bar[0] <= 1'b0;
else if (cnb) bar[0] <= w[10];
end
end
endmodule | module bar(
input clk_sys,
input [10:15] w,
input cnb,
input clm,
input zer_sp,
output reg [0:5] bar
); |
always @ (posedge clk_sys, posedge clm) begin
if (clm) bar <= 6'd0;
else begin
if (cnb) bar[1:5] <= w[11:15];
if (zer_sp) bar[0] <= 1'b0;
else if (cnb) bar[0] <= w[10];
end
end
endmodule | 24 |
139,062 | data/full_repos/permissive/86722304/src/cpu.v | 86,722,304 | cpu.v | v | 790 | 472 | [] | [] | [] | null | line:57: before: ";" | null | 1: b"%Error: data/full_repos/permissive/86722304/src/cpu.v:57: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'CPU_NUMBER'\n : ... In instance cpu\n parameter CPU_NUMBER;\n ^~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 304,278 | module | module cpu(
input clk_sys,
input off,
input pon,
input pout,
input clm, clo,
input [0:15] kl,
input panel_store, panel_fetch, panel_load, panel_bin,
input oprq, stop, start, work, mode, step, stop_n, cycle,
input wre, rsa, rsb, rsc,
input wic, wac, war, wir, wrs, wrz, wkb,
input zegar,
output p0,
output [0:15] w,
output hlt_n,
output p,
output run,
output _wait,
output irq,
output q,
output mc_0,
output awaria,
input rpa,
output dmcl,
output dw,
output dr,
output ds,
output df,
output din, input rin,
output dok, input rok,
input ren,
input rpe,
output dqb,
output dpn, input rpn,
output [0:3] dnb,
output [0:15] dad,
output [0:15] ddt, input [0:15] rdt,
output zg,
input zw,
output zz
);
assign zz = 1'b1;
parameter CPU_NUMBER;
parameter AWP_PRESENT = 1'b1;
parameter INOU_USER_ILLEGAL = 1'b1;
parameter STOP_ON_NOMEM = 1'b1;
parameter LOW_MEM_WRITE_DENY = 1'b0;
parameter ALARM_DLY_TICKS = 8'd250;
parameter ALARM_TICKS = 2'd3;
assign ddt = pa_ddt | px_ddt;
assign dad = pa_dad | pp_dad | px_dad;
wire k1, wp, k2, wa, wz, w$, wr, we, p1, p2, p5, p4, p3, i5, i4, i3, i2, i1, ww, wm, wx, as2, got, strob1, strob1b, strob2, strob2b, arm4, blw_pw, ekc_i, zer_sp, lipsp, pn_nb, bp_nb, bar_nb, barnb, q_nb, w_dt, dt_w, ar_ad, ic_ad, i3_ex_przer, ck_rz_w, zerrz, ok$, oken, bod, b_parz, b_p0;
wire [0:15] px_dad;
wire [0:15] px_ddt;
wire ldstate;
px #(
.AWP_PRESENT(AWP_PRESENT),
.STOP_ON_NOMEM(STOP_ON_NOMEM),
.LOW_MEM_WRITE_DENY(LOW_MEM_WRITE_DENY),
.ALARM_DLY_TICKS(ALARM_DLY_TICKS),
.ALARM_TICKS(ALARM_TICKS)
) PX(
.clk_sys(clk_sys),
.ek1(ek1),
.ewp(ewp),
.ek2(ek2),
.ewa(ewa),
.clo(clo),
.ewe(ewe),
.ewr(ewr),
.ew$(ew$),
.ewz(ewz),
.k1(k1),
.wp(wp),
.k2(k2),
.wa(wa),
.wz(wz),
.w$(w$),
.wr(wr),
.we(we),
.sp1(sp1),
.ep1(ep1),
.sp0(sp0),
.ep0(ep0),
.stp0(stp0),
.ep2(ep2),
.ep5(ep5),
.ep4(ep4),
.ep3(ep3),
.p1(p1),
.p0(p0),
.p2(p2),
.p5(p5),
.p4(p4),
.p3(p3),
.si1(si1),
.ewx(ewx),
.ewm(ewm),
.eww(eww),
.i5(i5),
.i4(i4),
.i3(i3),
.i2(i2),
.i1(i1),
.ww(ww),
.wm(wm),
.wx(wx),
.laduj(laduj),
.as2_sum_at(as2),
.strob_fp(strob_fp),
.strobb_fp(strobb_fp),
.mode(mode),
.step(step),
.got(got),
.ldstate(ldstate),
.strob1(strob1),
.strob1b(strob1b),
.strob2(strob2),
.strob2b(strob2b),
.przerw_z(przerw_z),
.przerw(przerw),
.lip(lip),
.sp(sp),
.lg_0(lg_0),
.pp(pp),
.lg_3(lg_3),
.arm4(arm4),
.blw_pw(blw_pw),
.ekc_i(ekc_i),
.zer_sp(zer_sp),
.lipsp(lipsp),
.sbar$(sbar$),
.q(q),
.in(in),
.ou(ou),
.k2fetch(k2fetch),
.read_fp(read_fp),
.pn_nb(pn_nb),
.bp_nb(bp_nb),
.bar_nb(bar_nb),
.barnb(barnb),
.q_nb(q_nb),
.df(df),
.w_dt(w_dt),
.dr(dr),
.dt_w(dt_w),
.ar_ad(ar_ad),
.ds(ds),
.mcl(mcl),
.gi(gi),
.ir6(ir[6]),
.fi(fi),
.arz(arz),
.k2_bin_store(k2_bin_store),
.lrz(lrz),
.ic_ad(ic_ad),
.dmcl(dmcl),
.ddt(px_ddt),
.din(din),
.dw(dw),
.i3_ex_przer(i3_ex_przer),
.ck_rz_w(ck_rz_w),
.zerrz(zerrz),
.sr_fp(sr_fp),
.zw(zw),
.srez$(srez$),
.wzi(wzi),
.is(is),
.ren(ren),
.rok(rok),
.efp(efp),
.exl(exl),
.zg(zg),
.ok$(ok$),
.oken(oken),
.stop_n(stop_n),
.zga(zga),
.rpe(rpe),
.stop(stop),
.ir9(ir[9]),
.pufa(pufa),
.ir7(ir[7]),
.ir8(ir[8]),
.hlt_n(hlt_n),
.bod(bod),
.b_parz(b_parz),
.b_p0(b_p0),
.awaria(awaria),
.dad(px_dad)
);
wire sp0, przerw, si1, sp1, laduj, k2_bin_store, k2fetch, w_rbc, w_rba, w_rbb, ep0, stp0, ek2, ek1, mc_3, xi$, pp, ep5, ep4, ep3, ep1, ep2, icp1, arp1, lg_3, lg_0, rc, rb, ra, lk, wls, w_r, w_ic, w_ac, w_ar, lrz, w_bar, w_rm, baa, bab, bac, aa, ab, wpb, bwb, bwa, kia, kib, w_ir, mwa, mwb, mwc;
pm PM(
.clk_sys(clk_sys),
.start(start),
.pon(pon),
.work(work),
.hlt_n(hlt_n),
.stop(stop),
.clo(clo),
.hlt(hlt),
.cycle(cycle),
.irq(irq),
._wait(_wait),
.run(run),
.ekc_1(ekc_1),
.ekc_i(ekc_i),
.ekc_2(ekc_2),
.got(got),
.ldstate(ldstate),
.ekc_fp(ekc_fp),
.clm(clm),
.strob1(strob1),
.strob1b(strob1b),
.strob2(strob2),
.strob2b(strob2b),
.sp0(sp0),
.przerw(przerw),
.si1(si1),
.sp1(sp1),
.k2(k2),
.panel_store(panel_store),
.panel_fetch(panel_fetch),
.panel_load(panel_load),
.panel_bin(panel_bin),
.rdt9(rdt[9]),
.rdt11(rdt[11]),
.k1(k1),
.laduj(laduj),
.k2_bin_store(k2_bin_store),
.k2fetch(k2fetch),
.w_rbc(w_rbc),
.w_rba(w_rba),
.w_rbb(w_rbb),
.p0(p0),
.ep0(ep0),
.stp0(stp0),
.ek2(ek2),
.ek1(ek1),
.j$(j$),
.bcoc$(bcoc$),
.zs(zs),
.p2(p2),
.ssp$(ssp$),
.sc$(sc$),
.md(md),
.xi(xi),
.p(p),
.mc_3(mc_3),
.mc_0(mc_0),
.xi$(xi$),
.p4(p4),
.b0(b0),
.na(na),
.c0(c0),
.ka2(ka2),
.ka1(ka1),
.p3(p3),
.p1(p1),
.nef(nef),
.p5(p5),
.i2(i2),
.pp(pp),
.ep5(ep5),
.ep4(ep4),
.ep3(ep3),
.ep1(ep1),
.ep2(ep2),
.icp1(icp1),
.exl(exl),
.lipsp(lipsp),
.gr(gr),
.wx(wx),
.shc(shc),
.read_fp(read_fp),
.inou(inou),
.rok(rok),
.arp1(arp1),
.lg_3(lg_3),
.lg_0(lg_0),
.rsc(rsc),
.ir6(ir[6]),
.ir7(ir[7]),
.ir8(ir[8]),
.ir9(ir[9]),
.ir10(ir[10]),
.ir11(ir[11]),
.ir12(ir[12]),
.ir13(ir[13]),
.ir14(ir[14]),
.ir15(ir[15]),
.lpb(lpb),
.rsb(rsb),
.rsa(rsa),
.lpa(lpa),
.rlp_fp(rlp_fp),
.rc(rc),
.rb(rb),
.ra(ra),
.bod(bod),
.lk(lk),
.rj(rj),
.uj(uj),
.lwlwt(lwlwt),
.sr(sr),
.lac(lac),
.lrcb(lrcb),
.rpc(rpc),
.rc$(rc$),
.ng$(ng$),
.ls(ls),
.oc(oc),
.wa(wa),
.wm(wm),
.wz(wz),
.ww(ww),
.wr(wr),
.wp(wp),
.wls(wls),
.ri(ri),
.war(war),
.wre(wre),
.i3(i3),
.s_fp(s_fp),
.sar$(sar$),
.lar$(lar$),
.in(in),
.bs(bs),
.zb$(zb$),
.w_r(w_r),
.wic(wic),
.i4(i4),
.wac(wac),
.i1(i1),
.w_ic(w_ic),
.w_ac(w_ac),
.w_ar(w_ar),
.wrz(wrz),
.wrs(wrs),
.mb(mb),
.im(im),
.lj(lj),
.lwrs(lwrs),
.jkrb(jkrb),
.lrz(lrz),
.w_bar(w_bar),
.w_rm(w_rm),
.we(we),
.ib(ib),
.cb(cb),
.i5(i5),
.rb$(rb$),
.w$(w$),
.i3_ex_przer(i3_ex_przer),
.baa(baa),
.bab(bab),
.bac(bac),
.aa(aa),
.ab(ab),
.at15(at15),
.srez$(srez$),
.rz(rz),
.wir(wir),
.blw_pw(blw_pw),
.wpb(wpb),
.bwb(bwb),
.bwa(bwa),
.kia(kia),
.kib(kib),
.w_ir(w_ir),
.ki(ki),
.dt_w(dt_w),
.f13(f13),
.wkb(wkb),
.mwa(mwa),
.mwb(mwb),
.mwc(mwc)
);
wire [0:15] ir;
wire c0, ls, rj, bs, ou, in, is, ri, pufa, rb$, cb, sc$, oc, ka2, gr, hlt, mcl, sin, gi, lip, mb, im, ki, fi, sp, rz, ib, lpc, rpc, shc, rc$, ng$, zb$, b0, _0_v, md, xi, nef, amb, apb, jkrb, lwrs, saryt, ap1, am1, bcoc$, sd, scb, sca, sb, sab, saa, lrcb, aryt, sbar$, nrf, ust_z, ust_v, ust_mc, ust_leg, eat0, sr, ust_y, ust_x, blr, ewa, ewp, uj, lwlwt, lj, ewe, ekc_1, ewz, ew$, lar$, ssp$, ka1, na, exl, p16, ewr, ewm, efp, sar$, eww, srez$, ewx, axy, inou, ekc_2, lac;
pd #(
.INOU_USER_ILLEGAL(INOU_USER_ILLEGAL)
) PD(
.clk_sys(clk_sys),
.w(w),
.strob1(strob1),
.strob1b(strob1b),
.w_ir(w_ir),
.ir(ir),
.c0(c0),
.si1(si1),
.ls(ls),
.rj(rj),
.bs(bs),
.ou(ou),
.in(in),
.is(is),
.ri(ri),
.pufa(pufa),
.rb$(rb$),
.cb(cb),
.sc$(sc$),
.oc(oc),
.ka2(ka2),
.gr(gr),
.hlt(hlt),
.mcl(mcl),
.sin(sin),
.gi(gi),
.lip(lip),
.mb(mb),
.im(im),
.ki(ki),
.fi(fi),
.sp(sp),
.rz(rz),
.ib(ib),
.lpc(lpc),
.rpc(rpc),
.shc(shc),
.rc$(rc$),
.ng$(ng$),
.zb$(zb$),
.b0(b0),
.q(q),
.mc_3(mc_3),
.r0(r0),
._0_v(_0_v),
.p(p),
.md(md),
.xi(xi),
.nef(nef),
.w$(w$),
.p4(p4),
.we(we),
.amb(amb),
.apb(apb),
.jkrb(jkrb),
.lwrs(lwrs),
.saryt(saryt),
.ap1(ap1),
.am1(am1),
.wz(wz),
.wls(wls),
.bcoc$(bcoc$),
.sd(sd),
.scb(scb),
.sca(sca),
.sb(sb),
.sab(sab),
.saa(saa),
.lrcb(lrcb),
.aryt(aryt),
.sbar$(sbar$),
.nrf(nrf),
.at15(at15),
.wx(wx),
.wa(wa),
.ust_z(ust_z),
.ust_v(ust_v),
.ust_mc(ust_mc),
.ust_leg(ust_leg),
.eat0(eat0),
.sr(sr),
.ust_y(ust_y),
.ust_x(ust_x),
.blr(blr),
.wpb(wpb),
.wr(wr),
.pp(pp),
.ww(ww),
.wzi(wzi),
.ewa(ewa),
.ewp(ewp),
.uj(uj),
.lwlwt(lwlwt),
.lj(lj),
.ewe(ewe),
.wp(wp),
.ekc_1(ekc_1),
.ewz(ewz),
.ew$(ew$),
.lar$(lar$),
.ssp$(ssp$),
.ka1(ka1),
.na(na),
.exl(exl),
.p16(p16),
.lk(lk),
.wm(wm),
.ewr(ewr),
.ewm(ewm),
.efp(efp),
.sar$(sar$),
.eww(eww),
.srez$(srez$),
.ewx(ewx),
.axy(axy),
.inou(inou),
.ekc_2(ekc_2),
.lac(lac)
);
wire [0:15] l;
wire zgpn, zer;
wire [0:8] r0;
wire [0:15] bus_ki;
pr #(
.CPU_NUMBER(CPU_NUMBER),
.AWP_PRESENT(AWP_PRESENT)
) PR(
.clk_sys(clk_sys),
.blr(blr),
.lpc(lpc),
.wa(wa),
.rpc(rpc),
.rc(rc),
.rb(rb),
.ra(ra),
.as2(as2),
.w_r(w_r),
.strob1(strob1),
.strob1b(strob1b),
.strob2(strob2),
.strob2b(strob2b),
.w(w),
.l(l),
.bar_nb(bar_nb),
.w_rbb(w_rbb),
.w_rbc(w_rbc),
.w_rba(w_rba),
.dnb(dnb),
.rpn(rpn),
.bp_nb(bp_nb),
.pn_nb(pn_nb),
.q_nb(q_nb),
.w_bar(w_bar),
.zer_sp(zer_sp),
.clm(clm),
.ustr0_fp(ustr0_fp),
.ust_leg(ust_leg),
.aryt(aryt),
.zs(zs),
.carry(carry),
.s_1(s_1),
.zgpn(zgpn),
.dpn(dpn),
.dqb(dqb),
.q(q),
.zer(zer),
.ust_z(ust_z),
.ust_mc(ust_mc),
.s0(s0),
.ust_v(ust_v),
._0_v(_0_v),
.r0(r0),
.exy(exy),
.ust_y(ust_y),
.exx(exx),
.ust_x(ust_x),
.kia(kia),
.kib(kib),
.bus_rz(bus_rz),
.zp(zp),
.rs(rs),
.bus_ki(bus_ki)
);
wire [0:9] rs;
wire [0:15] bus_rz;
wire przerw_z;
wire [0:15] pp_dad;
pp PP(
.clk_sys(clk_sys),
.w(w),
.clm(clm),
.w_rm(w_rm),
.strob1(strob1),
.strob1b(strob1b),
.i4(i4),
.rs(rs),
.pout(pout),
.zer(zer),
.b_parz(b_parz),
.ck_rz_w(ck_rz_w),
.b_p0(b_p0),
.zerrz(zerrz),
.i1(i1),
.przerw(przerw),
.bus_rz(bus_rz),
.rpa(rpa),
.zegar(zegar),
.xi(xi$),
.fi0(fi0),
.fi1(fi1),
.fi2(fi2),
.fi3(fi3),
.przerw_z(przerw_z),
.k1(k1),
.i2(i2),
.oprq(oprq),
.ir14(ir[14]),
.ir15(ir[15]),
.wx(wx),
.sin(sin),
.rin(rin),
.zw(zw),
.zgpn(zgpn),
.rdt(rdt),
.dok(dok),
.irq(irq),
.dad(pp_dad)
);
wire s0, carry, j$, exx, at15, exy, s_1, wzi, zs, arz;
wire zga;
wire [0:15] pa_ddt;
wire [0:15] pa_dad;
pa PA(
.clk_sys(clk_sys),
.ir(ir),
.bus_ki(bus_ki),
.rdt(rdt),
.w_dt(w_dt),
.mwa(mwa),
.mwb(mwb),
.mwc(mwc),
.bwa(bwa),
.bwb(bwb),
.ddt(pa_ddt),
.w(w),
.saryt(saryt),
.sab(sab),
.scb(scb),
.sb(sb),
.sd(sd),
.s0(s0),
.carry(carry),
.p16(p16),
.saa(saa),
.sca(sca),
.j$(j$),
.exx(exx),
.wx(wx),
.eat0(eat0),
.axy(axy),
.at15(at15),
.exy(exy),
.w_ac(w_ac),
.strob1(strob1),
.strob1b(strob1b),
.strob2(strob2),
.strob2b(strob2b),
.as2(as2),
.am1(am1),
.apb(apb),
.amb(amb),
.ap1(ap1),
.s_1(s_1),
.wzi(wzi),
.zs(zs),
.arm4(arm4),
.w_ar(w_ar),
.arp1(arp1),
.arz(arz),
.icp1(icp1),
.w_ic(w_ic),
.off(off),
.baa(baa),
.bab(bab),
.bac(bac),
.ab(ab),
.aa(aa),
.l(l),
.barnb(barnb),
.kl(kl),
.ic_ad(ic_ad),
.dad(pa_dad),
.ar_ad(ar_ad),
.zga(zga)
);
wire fi0, fi1, fi2, fi3;
wire read_fp, strob_fp, strobb_fp, sr_fp, ekc_fp, rlp_fp, ustr0_fp, s_fp;
wire f13, lpa, lpb;
wire [0:15] zp;
generate
if (~AWP_PRESENT) begin
assign {fi0, fi1, fi2, fi3} = 4'b0000;
assign {read_fp, strob_fp, sr_fp, ekc_fp, rlp_fp, ustr0_fp, s_fp} = 7'b0000000;
assign {f13, lpa, lpb} = 3'b000;
assign zp = 16'h0000;
end else begin
awp AWP(
.clk_sys(clk_sys),
.w(w),
.r02(r0[2]),
.r03(r0[3]),
.pufa(pufa),
.ir(ir[7:9]),
.nrf(nrf),
.mode(mode),
.step(step),
.efp(efp),
.got(got),
.ldstate(ldstate),
.ok$(ok$),
.oken(oken),
.zw(zw),
.zp(zp),
.fi0(fi0),
.fi1(fi1),
.fi2(fi2),
.fi3(fi3),
.rlp_fp(rlp_fp),
.lpa(lpa),
.lpb(lpb),
.s_fp(s_fp),
.ustr0_fp(ustr0_fp),
.f13(f13),
.strob_fp(strob_fp),
.strobb_fp(strobb_fp),
.sr_fp(sr_fp),
.read_fp(read_fp),
.ekc_fp(ekc_fp)
);
end
endgenerate
endmodule | module cpu(
input clk_sys,
input off,
input pon,
input pout,
input clm, clo,
input [0:15] kl,
input panel_store, panel_fetch, panel_load, panel_bin,
input oprq, stop, start, work, mode, step, stop_n, cycle,
input wre, rsa, rsb, rsc,
input wic, wac, war, wir, wrs, wrz, wkb,
input zegar,
output p0,
output [0:15] w,
output hlt_n,
output p,
output run,
output _wait,
output irq,
output q,
output mc_0,
output awaria,
input rpa,
output dmcl,
output dw,
output dr,
output ds,
output df,
output din, input rin,
output dok, input rok,
input ren,
input rpe,
output dqb,
output dpn, input rpn,
output [0:3] dnb,
output [0:15] dad,
output [0:15] ddt, input [0:15] rdt,
output zg,
input zw,
output zz
); |
assign zz = 1'b1;
parameter CPU_NUMBER;
parameter AWP_PRESENT = 1'b1;
parameter INOU_USER_ILLEGAL = 1'b1;
parameter STOP_ON_NOMEM = 1'b1;
parameter LOW_MEM_WRITE_DENY = 1'b0;
parameter ALARM_DLY_TICKS = 8'd250;
parameter ALARM_TICKS = 2'd3;
assign ddt = pa_ddt | px_ddt;
assign dad = pa_dad | pp_dad | px_dad;
wire k1, wp, k2, wa, wz, w$, wr, we, p1, p2, p5, p4, p3, i5, i4, i3, i2, i1, ww, wm, wx, as2, got, strob1, strob1b, strob2, strob2b, arm4, blw_pw, ekc_i, zer_sp, lipsp, pn_nb, bp_nb, bar_nb, barnb, q_nb, w_dt, dt_w, ar_ad, ic_ad, i3_ex_przer, ck_rz_w, zerrz, ok$, oken, bod, b_parz, b_p0;
wire [0:15] px_dad;
wire [0:15] px_ddt;
wire ldstate;
px #(
.AWP_PRESENT(AWP_PRESENT),
.STOP_ON_NOMEM(STOP_ON_NOMEM),
.LOW_MEM_WRITE_DENY(LOW_MEM_WRITE_DENY),
.ALARM_DLY_TICKS(ALARM_DLY_TICKS),
.ALARM_TICKS(ALARM_TICKS)
) PX(
.clk_sys(clk_sys),
.ek1(ek1),
.ewp(ewp),
.ek2(ek2),
.ewa(ewa),
.clo(clo),
.ewe(ewe),
.ewr(ewr),
.ew$(ew$),
.ewz(ewz),
.k1(k1),
.wp(wp),
.k2(k2),
.wa(wa),
.wz(wz),
.w$(w$),
.wr(wr),
.we(we),
.sp1(sp1),
.ep1(ep1),
.sp0(sp0),
.ep0(ep0),
.stp0(stp0),
.ep2(ep2),
.ep5(ep5),
.ep4(ep4),
.ep3(ep3),
.p1(p1),
.p0(p0),
.p2(p2),
.p5(p5),
.p4(p4),
.p3(p3),
.si1(si1),
.ewx(ewx),
.ewm(ewm),
.eww(eww),
.i5(i5),
.i4(i4),
.i3(i3),
.i2(i2),
.i1(i1),
.ww(ww),
.wm(wm),
.wx(wx),
.laduj(laduj),
.as2_sum_at(as2),
.strob_fp(strob_fp),
.strobb_fp(strobb_fp),
.mode(mode),
.step(step),
.got(got),
.ldstate(ldstate),
.strob1(strob1),
.strob1b(strob1b),
.strob2(strob2),
.strob2b(strob2b),
.przerw_z(przerw_z),
.przerw(przerw),
.lip(lip),
.sp(sp),
.lg_0(lg_0),
.pp(pp),
.lg_3(lg_3),
.arm4(arm4),
.blw_pw(blw_pw),
.ekc_i(ekc_i),
.zer_sp(zer_sp),
.lipsp(lipsp),
.sbar$(sbar$),
.q(q),
.in(in),
.ou(ou),
.k2fetch(k2fetch),
.read_fp(read_fp),
.pn_nb(pn_nb),
.bp_nb(bp_nb),
.bar_nb(bar_nb),
.barnb(barnb),
.q_nb(q_nb),
.df(df),
.w_dt(w_dt),
.dr(dr),
.dt_w(dt_w),
.ar_ad(ar_ad),
.ds(ds),
.mcl(mcl),
.gi(gi),
.ir6(ir[6]),
.fi(fi),
.arz(arz),
.k2_bin_store(k2_bin_store),
.lrz(lrz),
.ic_ad(ic_ad),
.dmcl(dmcl),
.ddt(px_ddt),
.din(din),
.dw(dw),
.i3_ex_przer(i3_ex_przer),
.ck_rz_w(ck_rz_w),
.zerrz(zerrz),
.sr_fp(sr_fp),
.zw(zw),
.srez$(srez$),
.wzi(wzi),
.is(is),
.ren(ren),
.rok(rok),
.efp(efp),
.exl(exl),
.zg(zg),
.ok$(ok$),
.oken(oken),
.stop_n(stop_n),
.zga(zga),
.rpe(rpe),
.stop(stop),
.ir9(ir[9]),
.pufa(pufa),
.ir7(ir[7]),
.ir8(ir[8]),
.hlt_n(hlt_n),
.bod(bod),
.b_parz(b_parz),
.b_p0(b_p0),
.awaria(awaria),
.dad(px_dad)
);
wire sp0, przerw, si1, sp1, laduj, k2_bin_store, k2fetch, w_rbc, w_rba, w_rbb, ep0, stp0, ek2, ek1, mc_3, xi$, pp, ep5, ep4, ep3, ep1, ep2, icp1, arp1, lg_3, lg_0, rc, rb, ra, lk, wls, w_r, w_ic, w_ac, w_ar, lrz, w_bar, w_rm, baa, bab, bac, aa, ab, wpb, bwb, bwa, kia, kib, w_ir, mwa, mwb, mwc;
pm PM(
.clk_sys(clk_sys),
.start(start),
.pon(pon),
.work(work),
.hlt_n(hlt_n),
.stop(stop),
.clo(clo),
.hlt(hlt),
.cycle(cycle),
.irq(irq),
._wait(_wait),
.run(run),
.ekc_1(ekc_1),
.ekc_i(ekc_i),
.ekc_2(ekc_2),
.got(got),
.ldstate(ldstate),
.ekc_fp(ekc_fp),
.clm(clm),
.strob1(strob1),
.strob1b(strob1b),
.strob2(strob2),
.strob2b(strob2b),
.sp0(sp0),
.przerw(przerw),
.si1(si1),
.sp1(sp1),
.k2(k2),
.panel_store(panel_store),
.panel_fetch(panel_fetch),
.panel_load(panel_load),
.panel_bin(panel_bin),
.rdt9(rdt[9]),
.rdt11(rdt[11]),
.k1(k1),
.laduj(laduj),
.k2_bin_store(k2_bin_store),
.k2fetch(k2fetch),
.w_rbc(w_rbc),
.w_rba(w_rba),
.w_rbb(w_rbb),
.p0(p0),
.ep0(ep0),
.stp0(stp0),
.ek2(ek2),
.ek1(ek1),
.j$(j$),
.bcoc$(bcoc$),
.zs(zs),
.p2(p2),
.ssp$(ssp$),
.sc$(sc$),
.md(md),
.xi(xi),
.p(p),
.mc_3(mc_3),
.mc_0(mc_0),
.xi$(xi$),
.p4(p4),
.b0(b0),
.na(na),
.c0(c0),
.ka2(ka2),
.ka1(ka1),
.p3(p3),
.p1(p1),
.nef(nef),
.p5(p5),
.i2(i2),
.pp(pp),
.ep5(ep5),
.ep4(ep4),
.ep3(ep3),
.ep1(ep1),
.ep2(ep2),
.icp1(icp1),
.exl(exl),
.lipsp(lipsp),
.gr(gr),
.wx(wx),
.shc(shc),
.read_fp(read_fp),
.inou(inou),
.rok(rok),
.arp1(arp1),
.lg_3(lg_3),
.lg_0(lg_0),
.rsc(rsc),
.ir6(ir[6]),
.ir7(ir[7]),
.ir8(ir[8]),
.ir9(ir[9]),
.ir10(ir[10]),
.ir11(ir[11]),
.ir12(ir[12]),
.ir13(ir[13]),
.ir14(ir[14]),
.ir15(ir[15]),
.lpb(lpb),
.rsb(rsb),
.rsa(rsa),
.lpa(lpa),
.rlp_fp(rlp_fp),
.rc(rc),
.rb(rb),
.ra(ra),
.bod(bod),
.lk(lk),
.rj(rj),
.uj(uj),
.lwlwt(lwlwt),
.sr(sr),
.lac(lac),
.lrcb(lrcb),
.rpc(rpc),
.rc$(rc$),
.ng$(ng$),
.ls(ls),
.oc(oc),
.wa(wa),
.wm(wm),
.wz(wz),
.ww(ww),
.wr(wr),
.wp(wp),
.wls(wls),
.ri(ri),
.war(war),
.wre(wre),
.i3(i3),
.s_fp(s_fp),
.sar$(sar$),
.lar$(lar$),
.in(in),
.bs(bs),
.zb$(zb$),
.w_r(w_r),
.wic(wic),
.i4(i4),
.wac(wac),
.i1(i1),
.w_ic(w_ic),
.w_ac(w_ac),
.w_ar(w_ar),
.wrz(wrz),
.wrs(wrs),
.mb(mb),
.im(im),
.lj(lj),
.lwrs(lwrs),
.jkrb(jkrb),
.lrz(lrz),
.w_bar(w_bar),
.w_rm(w_rm),
.we(we),
.ib(ib),
.cb(cb),
.i5(i5),
.rb$(rb$),
.w$(w$),
.i3_ex_przer(i3_ex_przer),
.baa(baa),
.bab(bab),
.bac(bac),
.aa(aa),
.ab(ab),
.at15(at15),
.srez$(srez$),
.rz(rz),
.wir(wir),
.blw_pw(blw_pw),
.wpb(wpb),
.bwb(bwb),
.bwa(bwa),
.kia(kia),
.kib(kib),
.w_ir(w_ir),
.ki(ki),
.dt_w(dt_w),
.f13(f13),
.wkb(wkb),
.mwa(mwa),
.mwb(mwb),
.mwc(mwc)
);
wire [0:15] ir;
wire c0, ls, rj, bs, ou, in, is, ri, pufa, rb$, cb, sc$, oc, ka2, gr, hlt, mcl, sin, gi, lip, mb, im, ki, fi, sp, rz, ib, lpc, rpc, shc, rc$, ng$, zb$, b0, _0_v, md, xi, nef, amb, apb, jkrb, lwrs, saryt, ap1, am1, bcoc$, sd, scb, sca, sb, sab, saa, lrcb, aryt, sbar$, nrf, ust_z, ust_v, ust_mc, ust_leg, eat0, sr, ust_y, ust_x, blr, ewa, ewp, uj, lwlwt, lj, ewe, ekc_1, ewz, ew$, lar$, ssp$, ka1, na, exl, p16, ewr, ewm, efp, sar$, eww, srez$, ewx, axy, inou, ekc_2, lac;
pd #(
.INOU_USER_ILLEGAL(INOU_USER_ILLEGAL)
) PD(
.clk_sys(clk_sys),
.w(w),
.strob1(strob1),
.strob1b(strob1b),
.w_ir(w_ir),
.ir(ir),
.c0(c0),
.si1(si1),
.ls(ls),
.rj(rj),
.bs(bs),
.ou(ou),
.in(in),
.is(is),
.ri(ri),
.pufa(pufa),
.rb$(rb$),
.cb(cb),
.sc$(sc$),
.oc(oc),
.ka2(ka2),
.gr(gr),
.hlt(hlt),
.mcl(mcl),
.sin(sin),
.gi(gi),
.lip(lip),
.mb(mb),
.im(im),
.ki(ki),
.fi(fi),
.sp(sp),
.rz(rz),
.ib(ib),
.lpc(lpc),
.rpc(rpc),
.shc(shc),
.rc$(rc$),
.ng$(ng$),
.zb$(zb$),
.b0(b0),
.q(q),
.mc_3(mc_3),
.r0(r0),
._0_v(_0_v),
.p(p),
.md(md),
.xi(xi),
.nef(nef),
.w$(w$),
.p4(p4),
.we(we),
.amb(amb),
.apb(apb),
.jkrb(jkrb),
.lwrs(lwrs),
.saryt(saryt),
.ap1(ap1),
.am1(am1),
.wz(wz),
.wls(wls),
.bcoc$(bcoc$),
.sd(sd),
.scb(scb),
.sca(sca),
.sb(sb),
.sab(sab),
.saa(saa),
.lrcb(lrcb),
.aryt(aryt),
.sbar$(sbar$),
.nrf(nrf),
.at15(at15),
.wx(wx),
.wa(wa),
.ust_z(ust_z),
.ust_v(ust_v),
.ust_mc(ust_mc),
.ust_leg(ust_leg),
.eat0(eat0),
.sr(sr),
.ust_y(ust_y),
.ust_x(ust_x),
.blr(blr),
.wpb(wpb),
.wr(wr),
.pp(pp),
.ww(ww),
.wzi(wzi),
.ewa(ewa),
.ewp(ewp),
.uj(uj),
.lwlwt(lwlwt),
.lj(lj),
.ewe(ewe),
.wp(wp),
.ekc_1(ekc_1),
.ewz(ewz),
.ew$(ew$),
.lar$(lar$),
.ssp$(ssp$),
.ka1(ka1),
.na(na),
.exl(exl),
.p16(p16),
.lk(lk),
.wm(wm),
.ewr(ewr),
.ewm(ewm),
.efp(efp),
.sar$(sar$),
.eww(eww),
.srez$(srez$),
.ewx(ewx),
.axy(axy),
.inou(inou),
.ekc_2(ekc_2),
.lac(lac)
);
wire [0:15] l;
wire zgpn, zer;
wire [0:8] r0;
wire [0:15] bus_ki;
pr #(
.CPU_NUMBER(CPU_NUMBER),
.AWP_PRESENT(AWP_PRESENT)
) PR(
.clk_sys(clk_sys),
.blr(blr),
.lpc(lpc),
.wa(wa),
.rpc(rpc),
.rc(rc),
.rb(rb),
.ra(ra),
.as2(as2),
.w_r(w_r),
.strob1(strob1),
.strob1b(strob1b),
.strob2(strob2),
.strob2b(strob2b),
.w(w),
.l(l),
.bar_nb(bar_nb),
.w_rbb(w_rbb),
.w_rbc(w_rbc),
.w_rba(w_rba),
.dnb(dnb),
.rpn(rpn),
.bp_nb(bp_nb),
.pn_nb(pn_nb),
.q_nb(q_nb),
.w_bar(w_bar),
.zer_sp(zer_sp),
.clm(clm),
.ustr0_fp(ustr0_fp),
.ust_leg(ust_leg),
.aryt(aryt),
.zs(zs),
.carry(carry),
.s_1(s_1),
.zgpn(zgpn),
.dpn(dpn),
.dqb(dqb),
.q(q),
.zer(zer),
.ust_z(ust_z),
.ust_mc(ust_mc),
.s0(s0),
.ust_v(ust_v),
._0_v(_0_v),
.r0(r0),
.exy(exy),
.ust_y(ust_y),
.exx(exx),
.ust_x(ust_x),
.kia(kia),
.kib(kib),
.bus_rz(bus_rz),
.zp(zp),
.rs(rs),
.bus_ki(bus_ki)
);
wire [0:9] rs;
wire [0:15] bus_rz;
wire przerw_z;
wire [0:15] pp_dad;
pp PP(
.clk_sys(clk_sys),
.w(w),
.clm(clm),
.w_rm(w_rm),
.strob1(strob1),
.strob1b(strob1b),
.i4(i4),
.rs(rs),
.pout(pout),
.zer(zer),
.b_parz(b_parz),
.ck_rz_w(ck_rz_w),
.b_p0(b_p0),
.zerrz(zerrz),
.i1(i1),
.przerw(przerw),
.bus_rz(bus_rz),
.rpa(rpa),
.zegar(zegar),
.xi(xi$),
.fi0(fi0),
.fi1(fi1),
.fi2(fi2),
.fi3(fi3),
.przerw_z(przerw_z),
.k1(k1),
.i2(i2),
.oprq(oprq),
.ir14(ir[14]),
.ir15(ir[15]),
.wx(wx),
.sin(sin),
.rin(rin),
.zw(zw),
.zgpn(zgpn),
.rdt(rdt),
.dok(dok),
.irq(irq),
.dad(pp_dad)
);
wire s0, carry, j$, exx, at15, exy, s_1, wzi, zs, arz;
wire zga;
wire [0:15] pa_ddt;
wire [0:15] pa_dad;
pa PA(
.clk_sys(clk_sys),
.ir(ir),
.bus_ki(bus_ki),
.rdt(rdt),
.w_dt(w_dt),
.mwa(mwa),
.mwb(mwb),
.mwc(mwc),
.bwa(bwa),
.bwb(bwb),
.ddt(pa_ddt),
.w(w),
.saryt(saryt),
.sab(sab),
.scb(scb),
.sb(sb),
.sd(sd),
.s0(s0),
.carry(carry),
.p16(p16),
.saa(saa),
.sca(sca),
.j$(j$),
.exx(exx),
.wx(wx),
.eat0(eat0),
.axy(axy),
.at15(at15),
.exy(exy),
.w_ac(w_ac),
.strob1(strob1),
.strob1b(strob1b),
.strob2(strob2),
.strob2b(strob2b),
.as2(as2),
.am1(am1),
.apb(apb),
.amb(amb),
.ap1(ap1),
.s_1(s_1),
.wzi(wzi),
.zs(zs),
.arm4(arm4),
.w_ar(w_ar),
.arp1(arp1),
.arz(arz),
.icp1(icp1),
.w_ic(w_ic),
.off(off),
.baa(baa),
.bab(bab),
.bac(bac),
.ab(ab),
.aa(aa),
.l(l),
.barnb(barnb),
.kl(kl),
.ic_ad(ic_ad),
.dad(pa_dad),
.ar_ad(ar_ad),
.zga(zga)
);
wire fi0, fi1, fi2, fi3;
wire read_fp, strob_fp, strobb_fp, sr_fp, ekc_fp, rlp_fp, ustr0_fp, s_fp;
wire f13, lpa, lpb;
wire [0:15] zp;
generate
if (~AWP_PRESENT) begin
assign {fi0, fi1, fi2, fi3} = 4'b0000;
assign {read_fp, strob_fp, sr_fp, ekc_fp, rlp_fp, ustr0_fp, s_fp} = 7'b0000000;
assign {f13, lpa, lpb} = 3'b000;
assign zp = 16'h0000;
end else begin
awp AWP(
.clk_sys(clk_sys),
.w(w),
.r02(r0[2]),
.r03(r0[3]),
.pufa(pufa),
.ir(ir[7:9]),
.nrf(nrf),
.mode(mode),
.step(step),
.efp(efp),
.got(got),
.ldstate(ldstate),
.ok$(ok$),
.oken(oken),
.zw(zw),
.zp(zp),
.fi0(fi0),
.fi1(fi1),
.fi2(fi2),
.fi3(fi3),
.rlp_fp(rlp_fp),
.lpa(lpa),
.lpb(lpb),
.s_fp(s_fp),
.ustr0_fp(ustr0_fp),
.f13(f13),
.strob_fp(strob_fp),
.strobb_fp(strobb_fp),
.sr_fp(sr_fp),
.read_fp(read_fp),
.ekc_fp(ekc_fp)
);
end
endgenerate
endmodule | 24 |
139,064 | data/full_repos/permissive/86722304/src/decoder8.v | 86,722,304 | decoder8.v | v | 24 | 54 | [] | [] | [] | [(1, 21)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/decoder8.v:2: Little bit endian vector: MSB < LSB of bit range: 0:2\n input [0:2] i,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/decoder8.v:4: Little bit endian vector: MSB < LSB of bit range: 0:7\n output [0:7] o\n ^\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/decoder8.v:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'o\'\n : ... In instance decoder8\n 4\'h0: o <= 8\'b10000000;\n ^\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/decoder8.v:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'o\'\n : ... In instance decoder8\n 4\'h1: o <= 8\'b01000000;\n ^\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/decoder8.v:11: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'o\'\n : ... In instance decoder8\n 4\'h2: o <= 8\'b00100000;\n ^\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/decoder8.v:12: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'o\'\n : ... In instance decoder8\n 4\'h3: o <= 8\'b00010000;\n ^\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/decoder8.v:13: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'o\'\n : ... In instance decoder8\n 4\'h4: o <= 8\'b00001000;\n ^\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/decoder8.v:14: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'o\'\n : ... In instance decoder8\n 4\'h5: o <= 8\'b00000100;\n ^\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/decoder8.v:15: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'o\'\n : ... In instance decoder8\n 4\'h6: o <= 8\'b00000010;\n ^\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/decoder8.v:16: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'o\'\n : ... In instance decoder8\n 4\'h7: o <= 8\'b00000001;\n ^\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/decoder8.v:17: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'o\'\n : ... In instance decoder8\n default: o <= 8\'b00000000;\n ^\n%Error: Exiting due to 9 error(s), 2 warning(s)\n' | 304,280 | module | module decoder8(
input [0:2] i,
input ena,
output [0:7] o
);
always @ (*) begin
case ({~ena, i})
4'h0: o <= 8'b10000000;
4'h1: o <= 8'b01000000;
4'h2: o <= 8'b00100000;
4'h3: o <= 8'b00010000;
4'h4: o <= 8'b00001000;
4'h5: o <= 8'b00000100;
4'h6: o <= 8'b00000010;
4'h7: o <= 8'b00000001;
default: o <= 8'b00000000;
endcase
end
endmodule | module decoder8(
input [0:2] i,
input ena,
output [0:7] o
); |
always @ (*) begin
case ({~ena, i})
4'h0: o <= 8'b10000000;
4'h1: o <= 8'b01000000;
4'h2: o <= 8'b00100000;
4'h3: o <= 8'b00010000;
4'h4: o <= 8'b00001000;
4'h5: o <= 8'b00000100;
4'h6: o <= 8'b00000010;
4'h7: o <= 8'b00000001;
default: o <= 8'b00000000;
endcase
end
endmodule | 24 |
139,065 | data/full_repos/permissive/86722304/src/display.v | 86,722,304 | display.v | v | 37 | 59 | [] | [] | [] | [(3, 34)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/display.v:5: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] w,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/86722304/src/display.v:14: Cannot find file containing module: \'hex2seg\'\n hex2seg d0(.hex(w[12:15]), .seg(digs[0]));\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/86722304/src,data/full_repos/permissive/86722304/hex2seg\n data/full_repos/permissive/86722304/src,data/full_repos/permissive/86722304/hex2seg.v\n data/full_repos/permissive/86722304/src,data/full_repos/permissive/86722304/hex2seg.sv\n hex2seg\n hex2seg.v\n hex2seg.sv\n obj_dir/hex2seg\n obj_dir/hex2seg.v\n obj_dir/hex2seg.sv\n%Error: data/full_repos/permissive/86722304/src/display.v:15: Cannot find file containing module: \'hex2seg\'\n hex2seg d1(.hex(w[8:11]), .seg(digs[1]));\n ^~~~~~~\n%Error: data/full_repos/permissive/86722304/src/display.v:16: Cannot find file containing module: \'hex2seg\'\n hex2seg d2(.hex(w[4:7]), .seg(digs[2]));\n ^~~~~~~\n%Error: data/full_repos/permissive/86722304/src/display.v:17: Cannot find file containing module: \'hex2seg\'\n hex2seg d3(.hex(w[0:3]), .seg(digs[3]));\n ^~~~~~~\n%Error: data/full_repos/permissive/86722304/src/display.v:18: Cannot find file containing module: \'none2seg\'\n none2seg d4(.seg(digs[4]));\n ^~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/display.v:19: Cannot find file containing module: \'rb2seg\'\n rb2seg d5(.r(rotary_bus), .seg(digs[5]));\n ^~~~~~\n%Error: data/full_repos/permissive/86722304/src/display.v:20: Cannot find file containing module: \'ra2seg\'\n ra2seg d6(.r(rotary_bus), .seg(digs[6]));\n ^~~~~~\n%Error: data/full_repos/permissive/86722304/src/display.v:26: Cannot find file containing module: \'sevenseg_drv\'\n sevenseg_drv DRV(\n ^~~~~~~~~~~~\n%Error: Exiting due to 8 error(s), 1 warning(s)\n' | 304,281 | module | module display(
input clk_sys,
input [0:15] w,
input [10:0] rotary_bus,
input [9:0] indicators,
output [7:0] seg,
output [7:0] dig
);
wire [6:0] digs [7:0];
hex2seg d0(.hex(w[12:15]), .seg(digs[0]));
hex2seg d1(.hex(w[8:11]), .seg(digs[1]));
hex2seg d2(.hex(w[4:7]), .seg(digs[2]));
hex2seg d3(.hex(w[0:3]), .seg(digs[3]));
none2seg d4(.seg(digs[4]));
rb2seg d5(.r(rotary_bus), .seg(digs[5]));
ra2seg d6(.r(rotary_bus), .seg(digs[6]));
assign digs[7][0] = indicators[5];
assign digs[7][6] = indicators[4];
assign digs[7][5:1] = 0;
sevenseg_drv DRV(
.clk(clk_sys),
.seg(seg),
.dig(dig),
.digs(digs),
.dots({indicators[2:0], indicators[3], indicators[9:6]})
);
endmodule | module display(
input clk_sys,
input [0:15] w,
input [10:0] rotary_bus,
input [9:0] indicators,
output [7:0] seg,
output [7:0] dig
); |
wire [6:0] digs [7:0];
hex2seg d0(.hex(w[12:15]), .seg(digs[0]));
hex2seg d1(.hex(w[8:11]), .seg(digs[1]));
hex2seg d2(.hex(w[4:7]), .seg(digs[2]));
hex2seg d3(.hex(w[0:3]), .seg(digs[3]));
none2seg d4(.seg(digs[4]));
rb2seg d5(.r(rotary_bus), .seg(digs[5]));
ra2seg d6(.r(rotary_bus), .seg(digs[6]));
assign digs[7][0] = indicators[5];
assign digs[7][6] = indicators[4];
assign digs[7][5:1] = 0;
sevenseg_drv DRV(
.clk(clk_sys),
.seg(seg),
.dig(dig),
.digs(digs),
.dots({indicators[2:0], indicators[3], indicators[9:6]})
);
endmodule | 24 |
139,069 | data/full_repos/permissive/86722304/src/drv_bus_resp.v | 86,722,304 | drv_bus_resp.v | v | 53 | 57 | [] | [] | [] | [(1, 50)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/drv_bus_resp.v:7: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] a3,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/drv_bus_resp.v:12: Little bit endian vector: MSB < LSB of bit range: 0:15\n output reg [0:15] ddt\n ^\n%Warning-WIDTH: data/full_repos/permissive/86722304/src/drv_bus_resp.v:20: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 4 bits.\n : ... In instance drv_bus_resp\n reg [0:0] state = IDLE;\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/86722304/src/drv_bus_resp.v:32: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'RESP\' generates 4 bits.\n : ... In instance drv_bus_resp\n state <= RESP;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/86722304/src/drv_bus_resp.v:42: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 4 bits.\n : ... In instance drv_bus_resp\n state <= IDLE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/86722304/src/drv_bus_resp.v:24: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 1 bits.\n : ... In instance drv_bus_resp\n case (state)\n ^~~~\n%Error: Exiting due to 6 warning(s)\n' | 304,285 | module | module drv_bus_resp(
input clk_sys,
input ready,
input ok,
input en,
input pe,
input [0:15] a3,
input req,
output reg dok,
output reg den,
output reg dpe,
output reg [0:15] ddt
);
wire resp = req & ready & (ok | en);
localparam IDLE = 4'd0;
localparam RESP = 4'd1;
reg [0:0] state = IDLE;
always @ (posedge clk_sys) begin
case (state)
IDLE: begin
if (resp) begin
dok <= ok;
den <= en;
dpe <= pe;
ddt <= a3;
state <= RESP;
end
end
RESP: begin
if (!req) begin
dok <= 0;
den <= 0;
dpe <= 0;
ddt <= 16'd0;
state <= IDLE;
end
end
endcase
end
endmodule | module drv_bus_resp(
input clk_sys,
input ready,
input ok,
input en,
input pe,
input [0:15] a3,
input req,
output reg dok,
output reg den,
output reg dpe,
output reg [0:15] ddt
); |
wire resp = req & ready & (ok | en);
localparam IDLE = 4'd0;
localparam RESP = 4'd1;
reg [0:0] state = IDLE;
always @ (posedge clk_sys) begin
case (state)
IDLE: begin
if (resp) begin
dok <= ok;
den <= en;
dpe <= pe;
ddt <= a3;
state <= RESP;
end
end
RESP: begin
if (!req) begin
dok <= 0;
den <= 0;
dpe <= 0;
ddt <= 16'd0;
state <= IDLE;
end
end
endcase
end
endmodule | 24 |
139,070 | data/full_repos/permissive/86722304/src/drv_cp_in.v | 86,722,304 | drv_cp_in.v | v | 29 | 54 | [] | [] | [] | [(1, 26)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/drv_cp_in.v:6: Little bit endian vector: MSB < LSB of bit range: 0:7\n input [0:7] a1,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/drv_cp_in.v:7: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] a3,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/drv_cp_in.v:8: Little bit endian vector: MSB < LSB of bit range: 0:3\n output [0:3] rotary_out,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/drv_cp_in.v:10: Little bit endian vector: MSB < LSB of bit range: 0:15\n output [0:15] keys,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/drv_cp_in.v:12: Little bit endian vector: MSB < LSB of bit range: 0:3\n output [0:3] fn,\n ^\n%Error: Exiting due to 5 warning(s)\n' | 304,286 | module | module drv_cp_in(
input ready,
input cpd,
input cpr,
input cpf,
input [0:7] a1,
input [0:15] a3,
output [0:3] rotary_out,
output rotary_trig,
output [0:15] keys,
output keys_trig,
output [0:3] fn,
output fn_v,
output fn_trig
);
assign keys = a3;
assign rotary_out = a1[4:7];
assign fn = a1[4:7];
assign fn_v = a1[3];
assign fn_trig = ready & cpf;
assign rotary_trig = ready & cpr;
assign keys_trig = ready & cpd;
endmodule | module drv_cp_in(
input ready,
input cpd,
input cpr,
input cpf,
input [0:7] a1,
input [0:15] a3,
output [0:3] rotary_out,
output rotary_trig,
output [0:15] keys,
output keys_trig,
output [0:3] fn,
output fn_v,
output fn_trig
); |
assign keys = a3;
assign rotary_out = a1[4:7];
assign fn = a1[4:7];
assign fn_v = a1[3];
assign fn_trig = ready & cpf;
assign rotary_trig = ready & cpr;
assign keys_trig = ready & cpd;
endmodule | 24 |
139,073 | data/full_repos/permissive/86722304/src/fpa.v | 86,722,304 | fpa.v | v | 230 | 75 | [] | [] | [] | [(9, 227)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/fpa.v:14: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] w,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/fpa.v:94: Little bit endian vector: MSB < LSB of bit range: 0:15\n output [0:15] zp,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/fpa.v:96: Little bit endian vector: MSB < LSB of bit range: -2:7\n input [-2:7] d,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/fpa.v:104: Little bit endian vector: MSB < LSB of bit range: 0:39\n wire [0:39] k;\n ^\n%Error: data/full_repos/permissive/86722304/src/fpa.v:106: Cannot find file containing module: \'k\'\n k K(\n ^\n ... Looked in:\n data/full_repos/permissive/86722304/src,data/full_repos/permissive/86722304/k\n data/full_repos/permissive/86722304/src,data/full_repos/permissive/86722304/k.v\n data/full_repos/permissive/86722304/src,data/full_repos/permissive/86722304/k.sv\n k\n k.v\n k.sv\n obj_dir/k\n obj_dir/k.v\n obj_dir/k.sv\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/fpa.v:117: Little bit endian vector: MSB < LSB of bit range: -1:39\n wire [-1:39] t;\n ^\n%Error: data/full_repos/permissive/86722304/src/fpa.v:119: Cannot find file containing module: \'t\'\n t T(\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/fpa.v:178: Little bit endian vector: MSB < LSB of bit range: 0:39\n wire [0:39] c;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/fpa.v:154: Little bit endian vector: MSB < LSB of bit range: -1:39\n wire [-1:39] m;\n ^\n%Error: data/full_repos/permissive/86722304/src/fpa.v:155: Cannot find file containing module: \'m\'\n m M(\n ^\n%Error: data/full_repos/permissive/86722304/src/fpa.v:180: Cannot find file containing module: \'c\'\n c C(\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/fpa.v:194: Little bit endian vector: MSB < LSB of bit range: 0:39\n wire [0:39] sum;\n ^\n%Error: data/full_repos/permissive/86722304/src/fpa.v:196: Cannot find file containing module: \'fpalu\'\n fpalu FPALU(\n ^~~~~\n%Error: data/full_repos/permissive/86722304/src/fpa.v:214: Cannot find file containing module: \'zp\'\n zp ZP(\n ^~\n%Error: Exiting due to 6 error(s), 8 warning(s)\n' | 304,289 | module | module fpa(
input clk_sys,
input strob_fp,
input strobb_fp,
input [0:15] w,
input taa,
output t_1,
input t_1_d,
input m_1_d,
input tab,
input clockta,
input clocktb,
input clocktc,
output t_0_1,
output t_2_7,
output t_8_15,
output t_16_23,
output t_24_31,
output t_32_39,
output m_1,
input ma,
input mb,
input clockm,
input _0_m,
output c0_eq_c1,
output c0,
output t1,
output t0_eq_c0,
output t0_neq_c0,
output t0_neq_t1,
output t0_neq_t_1,
output m0,
output t0,
input fab,
input faa,
output fp0_,
input p_16,
output m14,
output m15,
output fp16_,
output t16,
input m_32,
input p_32,
input m_40,
input cp,
input t_c,
output m32,
output m38,
output m39,
output c39,
input fra,
input frb,
input p_40,
output p32_,
input trb,
input _0_t,
output t39,
input f9,
input lkb,
input z_f,
input m_f,
input v_f,
input c_f,
output [0:15] zp,
input [-2:7] d,
input _0_zp,
input zpb,
input zpa
);
wire [0:39] k;
k K(
.lkb(lkb),
.f9(f9),
.sum(sum),
.m(m[0:39]),
.w(w),
.k(k)
);
wire [-1:39] t;
t T(
.clk_sys(clk_sys),
._0_t(_0_t),
.taa(taa),
.tab(tab),
.trb(trb),
.clockta(clockta),
.clocktb(clocktb),
.clocktc(clocktc),
.t_1_d(t_1_d),
.k(k),
.m_1(m[-1]),
.t(t)
);
assign t_1 = t[-1];
assign t0 = t[0];
assign t1 = t[1];
assign t16 = t[16];
assign t39 = t[39];
assign t0_eq_c0 = t[0] == c[0];
assign t0_neq_c0 = c[0] != t[0];
assign t0_neq_t1 = t[0] != t[1];
assign t0_neq_t_1 = t[0] != t[-1];
assign t_0_1 = |t[0:1];
assign t_2_7 = |t[2:7];
assign t_8_15 = |t[8:15];
assign t_16_23 = |t[16:23];
assign t_24_31 = |t[24:31];
assign t_32_39 = |t[32:39];
wire [-1:39] m;
m M(
.clk_sys(clk_sys),
._0_m(_0_m),
.clockm(clockm),
.ma(ma),
.mb(mb),
.m_32(m_32),
.m_40(m_40),
.m_1_d(m_1_d),
.t(t[0:39]),
.m(m)
);
assign m_1 = m[-1];
assign m0 = m[0];
assign m14 = m[14];
assign m15 = m[15];
assign m32 = m[32];
assign m38 = m[38];
assign m39 = m[39];
wire [0:39] c;
c C(
.clk_sys(clk_sys),
.t(t[0:39]),
.t_c(t_c),
.cp(cp),
.c(c)
);
assign c0_eq_c1 = c[0] == c[1];
assign c0 = c[0];
assign c39 = c[39];
wire [0:39] sum;
fpalu FPALU(
.t(t[0:39]),
.c(c),
.faa(faa),
.fab(fab),
.fra(fra),
.frb(frb),
.p_16(p_16),
.p_32(p_32),
.p_40(p_40),
.fp0_(fp0_),
.fp16_(fp16_),
.p32_(p32_),
.sum(sum)
);
zp ZP(
._0_zp(_0_zp),
.zpa(zpa),
.zpb(zpb),
.t(t[0:39]),
.d(d[0:7]),
.z_f(z_f),
.m_f(m_f),
.v_f(v_f),
.c_f(c_f),
.zp(zp)
);
endmodule | module fpa(
input clk_sys,
input strob_fp,
input strobb_fp,
input [0:15] w,
input taa,
output t_1,
input t_1_d,
input m_1_d,
input tab,
input clockta,
input clocktb,
input clocktc,
output t_0_1,
output t_2_7,
output t_8_15,
output t_16_23,
output t_24_31,
output t_32_39,
output m_1,
input ma,
input mb,
input clockm,
input _0_m,
output c0_eq_c1,
output c0,
output t1,
output t0_eq_c0,
output t0_neq_c0,
output t0_neq_t1,
output t0_neq_t_1,
output m0,
output t0,
input fab,
input faa,
output fp0_,
input p_16,
output m14,
output m15,
output fp16_,
output t16,
input m_32,
input p_32,
input m_40,
input cp,
input t_c,
output m32,
output m38,
output m39,
output c39,
input fra,
input frb,
input p_40,
output p32_,
input trb,
input _0_t,
output t39,
input f9,
input lkb,
input z_f,
input m_f,
input v_f,
input c_f,
output [0:15] zp,
input [-2:7] d,
input _0_zp,
input zpb,
input zpa
); |
wire [0:39] k;
k K(
.lkb(lkb),
.f9(f9),
.sum(sum),
.m(m[0:39]),
.w(w),
.k(k)
);
wire [-1:39] t;
t T(
.clk_sys(clk_sys),
._0_t(_0_t),
.taa(taa),
.tab(tab),
.trb(trb),
.clockta(clockta),
.clocktb(clocktb),
.clocktc(clocktc),
.t_1_d(t_1_d),
.k(k),
.m_1(m[-1]),
.t(t)
);
assign t_1 = t[-1];
assign t0 = t[0];
assign t1 = t[1];
assign t16 = t[16];
assign t39 = t[39];
assign t0_eq_c0 = t[0] == c[0];
assign t0_neq_c0 = c[0] != t[0];
assign t0_neq_t1 = t[0] != t[1];
assign t0_neq_t_1 = t[0] != t[-1];
assign t_0_1 = |t[0:1];
assign t_2_7 = |t[2:7];
assign t_8_15 = |t[8:15];
assign t_16_23 = |t[16:23];
assign t_24_31 = |t[24:31];
assign t_32_39 = |t[32:39];
wire [-1:39] m;
m M(
.clk_sys(clk_sys),
._0_m(_0_m),
.clockm(clockm),
.ma(ma),
.mb(mb),
.m_32(m_32),
.m_40(m_40),
.m_1_d(m_1_d),
.t(t[0:39]),
.m(m)
);
assign m_1 = m[-1];
assign m0 = m[0];
assign m14 = m[14];
assign m15 = m[15];
assign m32 = m[32];
assign m38 = m[38];
assign m39 = m[39];
wire [0:39] c;
c C(
.clk_sys(clk_sys),
.t(t[0:39]),
.t_c(t_c),
.cp(cp),
.c(c)
);
assign c0_eq_c1 = c[0] == c[1];
assign c0 = c[0];
assign c39 = c[39];
wire [0:39] sum;
fpalu FPALU(
.t(t[0:39]),
.c(c),
.faa(faa),
.fab(fab),
.fra(fra),
.frb(frb),
.p_16(p_16),
.p_32(p_32),
.p_40(p_40),
.fp0_(fp0_),
.fp16_(fp16_),
.p32_(p32_),
.sum(sum)
);
zp ZP(
._0_zp(_0_zp),
.zpa(zpa),
.zpb(zpb),
.t(t[0:39]),
.d(d[0:7]),
.z_f(z_f),
.m_f(m_f),
.v_f(v_f),
.c_f(c_f),
.zp(zp)
);
endmodule | 24 |
139,076 | data/full_repos/permissive/86722304/src/fps.v | 86,722,304 | fps.v | v | 364 | 164 | [] | [] | [] | [(9, 361)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/fps.v:134: Little bit endian vector: MSB < LSB of bit range: 0:1\n reg [0:1] start_state;\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/86722304/src/fps.v:157: Cannot find file containing module: \'fp_strobgen\'\n fp_strobgen FP_STROBGEN(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86722304/src,data/full_repos/permissive/86722304/fp_strobgen\n data/full_repos/permissive/86722304/src,data/full_repos/permissive/86722304/fp_strobgen.v\n data/full_repos/permissive/86722304/src,data/full_repos/permissive/86722304/fp_strobgen.sv\n fp_strobgen\n fp_strobgen.v\n fp_strobgen.sv\n obj_dir/fp_strobgen\n obj_dir/fp_strobgen.v\n obj_dir/fp_strobgen.sv\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/fps.v:192: Little bit endian vector: MSB < LSB of bit range: 0:1\n reg [0:1] ekc_state;\n ^\n%Error: data/full_repos/permissive/86722304/src/fps.v:342: Cannot find file containing module: \'lp\'\n lp LP(\n ^~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 304,292 | module | module fps(
input clk_sys,
input mode,
input step,
output strob_fp,
output strobb_fp,
output strob2_fp,
output strob2b_fp,
input oken,
input zw,
input di,
input efp,
input puf,
input got,
input ldstate,
output sr_fp,
output ekc_fp,
output _0_f,
input g,
input wdt,
input af_sf,
input mw,
output _0_t,
output lkb,
output l_d,
output clocktc,
output clocktb,
output clockta,
output t_c,
output fcb,
input mf,
input fp16_,
output t_1_t_1,
output tab,
output trb,
output taa,
output cp,
input sd,
input ck,
input sf,
input p32_,
input m14,
input t0_eq_c0,
input m38,
input t0_neq_c0,
input ws,
input df,
input af,
input ad,
output frb,
output p_16,
output p_32,
output p_40,
output fab,
output faa,
output fra,
input fic,
input ad_sd,
input ta,
input sgn_t0_c0,
input opsu,
input wc,
input wt,
input dw,
input ss,
output f5,
output f6,
output f2,
output f4,
input ok$,
input ff,
output read_fp,
input sgn,
input fwz,
input nrf,
input nz,
input t0_neq_t_1,
input ok,
output f13,
output f10,
output f9,
output f8,
output f7,
input dw_df,
input mw_mf,
output scc,
output pc8,
output _0_d,
output _0_m,
output mb,
output ma,
output clockm,
output rlp_fp,
output lpa,
output lpb,
output zpa,
output zpb,
output _0_zp,
output s_fp,
output ustr0_fp,
output lp
);
localparam STS_IDLE = 2'd0;
localparam STS_DLY = 2'd1;
localparam STS_START = 2'd2;
localparam STS_WAIT = 2'd3;
reg [0:1] start_state;
wire start = (start_state == STS_START);
wire pre_start = (start_state == STS_DLY);
always @ (posedge clk_sys) begin
case (start_state)
STS_IDLE: if (efp & ldstate) start_state <= STS_DLY;
STS_DLY: start_state <= STS_START;
STS_START: start_state <= STS_WAIT;
STS_WAIT: if (_0_f) start_state <= STS_IDLE;
endcase
end
wire dp8 = f4 | f8 | f3 | (ok$ & f1) | f9 | f13;
wire dp2 = f6 | f5 | f12;
wire dp6 = f2 | f10;
wire dp5 = f11 | f7;
wire strob1, strob1b;
wire strob2, strob2b;
wire ldstate_fp;
fp_strobgen FP_STROBGEN(
.clk_sys(clk_sys),
.start(start),
.di(di),
.dp8(dp8),
.dp2(dp2),
.dp6(dp6),
.dp5(dp5),
.mode(mode),
.step(step),
.oken(oken),
.f1(f1),
.zw(zw),
.ldstate(ldstate_fp),
.strob1(strob1),
.strob1b(strob1b),
.strob2(strob2),
.strob2b(strob2b),
.sr_fp(sr_fp)
);
assign strob_fp = strob1;
assign strobb_fp = strob1b;
assign strob2_fp = strob2;
assign strob2b_fp = strob2b;
wire dkc = ~df13 & f13;
wire d_ekc = dkc | di;
localparam EKCS_IDLE = 2'd0;
localparam EKCS_EKC = 2'd1;
localparam EKCS_WAIT = 2'd2;
reg [0:1] ekc_state;
assign ekc_fp = (ekc_state == EKCS_EKC);
always @ (posedge clk_sys) begin
case (ekc_state)
EKCS_IDLE: if (ldstate_fp & d_ekc) ekc_state <= EKCS_EKC;
EKCS_EKC: ekc_state <= EKCS_WAIT;
EKCS_WAIT: if (~puf) ekc_state <= EKCS_IDLE;
endcase
end
assign _0_f = ekc_fp | ~puf;
wire f1_s = pre_start & ~nrf;
wire f3_s = pre_start & nrf;
reg f1, f3, f11, f12;
always @ (posedge clk_sys, posedge _0_f) begin
if (_0_f) begin
{f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13} <= 0;
end else begin
if (ldstate_fp) {f2, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13} <= {ef2, ef4, ef5, ef6, ef7, ef8, ef9, ef10, ef11, ef12, ef13};
if (f3_s) f3 <= 1'b1;
else if (ldstate_fp) f3 <= ef3;
if (f1_s) f1 <= 1'b1;
else if (ldstate_fp) f1 <= ef1;
end
end
assign read_fp = f1;
assign rlp_fp = f13 | f3;
assign fcb = f12 | f11;
assign lkb = f3 | f1;
wire f9dw = dw & f9;
assign t_c = strob1 & f2;
assign l_d = strob1b & ((f5 & ~af_sf) | lp3lkb | ((wdt | wc) & ~ws & f7) | fcb);
wire lp3lkb = lp3 & lkb;
wire M9_3 = lp3lkb | f7_f12;
wire M19_6 = ((mw | lp1) & lkb) | (f7 & ta_alpha) | f7_f12 | f6;
wire M19_8 = f7_f12 | (sgn & f7) | (lp2 & lkb & ~mw);
assign clocktc = strob1b & M9_3;
assign clocktb = strob1b & M19_8;
assign clockta = strob1b & M19_6;
assign _0_t = start | (strob2 & ((g & wdt & f5) | (wc & f4) | (mw & f4) | (f4 & mf)));
wire M53_3 = f8 & (mw | mf | wdt);
assign taa = (dw_df & f8) | f12;
assign tab = f9dw | f11 | M53_3;
assign trb = M53_3 | f11;
wire M30_3 = ~(af_sf & ~wdt);
wire dwsgnf7 = dw & sgn & f7;
wire f7_f12 = f9 | f12 | f11 | (~dw & f7) | (M30_3 & f8);
assign t_1_t_1 = f8 | f12 | f11 | f9dw;
assign cp = strob1 & f8 & af_sf & ~wdt;
wire dw_p16 = dwsgnf7 | ~fp16_ | mw_p16;
wire M54_8 = wdt | ck;
wire M76_8 = ~ws & sf;
wire M76_3 = df & fic;
wire M76_6 = mf & ~ws;
wire M67_8 = f7 & ~sgn & dw;
wire M77_6 = (M54_8 & M76_8) | (~fic & df);
wire M65_6 = (mw & ~m14) | (dw & t0_neq_c0);
wire M78_8 = (~m38 & M76_6) | (ad) | (df & fic & t0_neq_c0) | (~ws & af);
wire M52_3 = M65_6 & f6;
wire M80_6 = ~p32_ | dwsgnf7 | sd;
wire M77_8 = (t0_eq_c0 & M76_3) | (M76_6 & m38);
wire mw_p16 = ~M65_6 & f6;
assign p_16 = dw_p16 & ~M67_8 & ~M52_3;
assign p_32 = M80_6 & ~ad;
assign p_40 = sd | ws | M77_6 | M77_8;
assign faa = M67_8 | M52_3 | fra;
assign fab = dwsgnf7 | frb;
assign fra = M52_3 | M78_8;
assign frb = mw_p16 | sd | M77_8 | M76_8;
wire df13 = (~lp3 & ss) | (ff & lp);
wire f4mwdw = f4 & dw_mw;
wire ta_alpha = ta & sgn_t0_c0;
wire f5_f8 = f5 | f8;
wire dw_mw = mw | dw;
wire f1f2_sel = (~dw & lp2) | (lp & ff);
wire ef1 = f1 & f1f2_sel;
wire ef2 = f1 & ~f1f2_sel;
wire ef3 = (f2 & ~(mw & fwz)) | (f3 & df13);
wire ef4 = f3 & (~lp | (lp3 & dw_mw));
wire ef5 = f4 & ~fwz & ~wt & ~wc & ~nrf & ff;
wire ef6 = opsu & ((dw & fic & f8) | (f8 & mw) | (f4mwdw & ~fwz));
wire ef7 = (ws & f10) | (sgn_t0_c0 & ta & f9dw) | (f4 & wc) | (f9 & sgn) | (f5_f8 & opsu & (mf | (df & fic))) | (f5_f8 & af_sf & ~fic & ~wt) | (f3 & lp3 & ad_sd);
wire M22_11 = (f5 & ff) | (f4 & dw_mw) | f8;
wire ef8 = (~opsu & ~fwz & M22_11 & fic) | (dw_mw & fic & f6) | (fic & f7);
wire ef9 = f8 & ~fic & dw_df;
wire ef10 = f11 | (f12 & ok) | (~sgn & df & f9) | (nrf & f4 & ~fwz) | (ff & f7 & ~fic) | (~fic & ~opsu & (f8 & mf));
wire ef11 = f10 & t0_neq_t_1;
wire ef12 = (f12 | f10) & nz;
wire M52_8 = f6 | (~opsu & f8);
wire M24_6 = f10 | f4 | (mw & f2);
wire ef13 = (M24_6 & fwz) | (ss & f7) | (~ws & ok & f10) | (df13 & f13) | (M52_8 & mw & ~fic) | (~sgn & f9dw & ~ta_alpha) | (wt & (f5 | f4));
assign scc = (mf & f5) | f7 | f11;
assign pc8 = (~mf & f5) | f11;
assign _0_d = strob2 & ((f5 & wdt) | (wc & f4));
assign _0_m = (strob2 & f9) | start;
assign mb = f11 | (af_sf & f8) | (mw_mf & f8);
assign ma = (dw_df & f8) | f12;
wire M27_12 = (mw_mf & f4) | fcb | f8;
assign clockm = M27_12 & strob1b;
wire M3_8 = mw & strob1b & f2;
wire lpb_s = (start & mw) | (~fwz & M3_8);
wire lpa_s = (start & ~mw) | (f2 & ~mw);
wire lpab_r = (M3_8 & fwz) | f7 | (f4 & ~dw) | (f4 & fwz);
wire lp_clk = strob1b & ((f8 & lp & dw) | f1 | f3 | f13);
wire lp1, lp2, lp3;
lp LP(
.clk_sys(clk_sys),
.lp_clk(lp_clk),
.lpb_s(lpb_s),
.lpa_s(lpa_s),
.lpab_r(lpab_r),
.out({lpb, lpa}),
.lp(lp),
.lp1(lp1),
.lp2(lp2),
.lp3(lp3)
);
assign zpa = f13 & ~lpa;
assign zpb = f13 & (~lpb ^ lpa);
assign _0_zp = f13 & fwz & lp;
assign s_fp = f13 & lp;
assign ustr0_fp = f13 & ~lp;
endmodule | module fps(
input clk_sys,
input mode,
input step,
output strob_fp,
output strobb_fp,
output strob2_fp,
output strob2b_fp,
input oken,
input zw,
input di,
input efp,
input puf,
input got,
input ldstate,
output sr_fp,
output ekc_fp,
output _0_f,
input g,
input wdt,
input af_sf,
input mw,
output _0_t,
output lkb,
output l_d,
output clocktc,
output clocktb,
output clockta,
output t_c,
output fcb,
input mf,
input fp16_,
output t_1_t_1,
output tab,
output trb,
output taa,
output cp,
input sd,
input ck,
input sf,
input p32_,
input m14,
input t0_eq_c0,
input m38,
input t0_neq_c0,
input ws,
input df,
input af,
input ad,
output frb,
output p_16,
output p_32,
output p_40,
output fab,
output faa,
output fra,
input fic,
input ad_sd,
input ta,
input sgn_t0_c0,
input opsu,
input wc,
input wt,
input dw,
input ss,
output f5,
output f6,
output f2,
output f4,
input ok$,
input ff,
output read_fp,
input sgn,
input fwz,
input nrf,
input nz,
input t0_neq_t_1,
input ok,
output f13,
output f10,
output f9,
output f8,
output f7,
input dw_df,
input mw_mf,
output scc,
output pc8,
output _0_d,
output _0_m,
output mb,
output ma,
output clockm,
output rlp_fp,
output lpa,
output lpb,
output zpa,
output zpb,
output _0_zp,
output s_fp,
output ustr0_fp,
output lp
); |
localparam STS_IDLE = 2'd0;
localparam STS_DLY = 2'd1;
localparam STS_START = 2'd2;
localparam STS_WAIT = 2'd3;
reg [0:1] start_state;
wire start = (start_state == STS_START);
wire pre_start = (start_state == STS_DLY);
always @ (posedge clk_sys) begin
case (start_state)
STS_IDLE: if (efp & ldstate) start_state <= STS_DLY;
STS_DLY: start_state <= STS_START;
STS_START: start_state <= STS_WAIT;
STS_WAIT: if (_0_f) start_state <= STS_IDLE;
endcase
end
wire dp8 = f4 | f8 | f3 | (ok$ & f1) | f9 | f13;
wire dp2 = f6 | f5 | f12;
wire dp6 = f2 | f10;
wire dp5 = f11 | f7;
wire strob1, strob1b;
wire strob2, strob2b;
wire ldstate_fp;
fp_strobgen FP_STROBGEN(
.clk_sys(clk_sys),
.start(start),
.di(di),
.dp8(dp8),
.dp2(dp2),
.dp6(dp6),
.dp5(dp5),
.mode(mode),
.step(step),
.oken(oken),
.f1(f1),
.zw(zw),
.ldstate(ldstate_fp),
.strob1(strob1),
.strob1b(strob1b),
.strob2(strob2),
.strob2b(strob2b),
.sr_fp(sr_fp)
);
assign strob_fp = strob1;
assign strobb_fp = strob1b;
assign strob2_fp = strob2;
assign strob2b_fp = strob2b;
wire dkc = ~df13 & f13;
wire d_ekc = dkc | di;
localparam EKCS_IDLE = 2'd0;
localparam EKCS_EKC = 2'd1;
localparam EKCS_WAIT = 2'd2;
reg [0:1] ekc_state;
assign ekc_fp = (ekc_state == EKCS_EKC);
always @ (posedge clk_sys) begin
case (ekc_state)
EKCS_IDLE: if (ldstate_fp & d_ekc) ekc_state <= EKCS_EKC;
EKCS_EKC: ekc_state <= EKCS_WAIT;
EKCS_WAIT: if (~puf) ekc_state <= EKCS_IDLE;
endcase
end
assign _0_f = ekc_fp | ~puf;
wire f1_s = pre_start & ~nrf;
wire f3_s = pre_start & nrf;
reg f1, f3, f11, f12;
always @ (posedge clk_sys, posedge _0_f) begin
if (_0_f) begin
{f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13} <= 0;
end else begin
if (ldstate_fp) {f2, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13} <= {ef2, ef4, ef5, ef6, ef7, ef8, ef9, ef10, ef11, ef12, ef13};
if (f3_s) f3 <= 1'b1;
else if (ldstate_fp) f3 <= ef3;
if (f1_s) f1 <= 1'b1;
else if (ldstate_fp) f1 <= ef1;
end
end
assign read_fp = f1;
assign rlp_fp = f13 | f3;
assign fcb = f12 | f11;
assign lkb = f3 | f1;
wire f9dw = dw & f9;
assign t_c = strob1 & f2;
assign l_d = strob1b & ((f5 & ~af_sf) | lp3lkb | ((wdt | wc) & ~ws & f7) | fcb);
wire lp3lkb = lp3 & lkb;
wire M9_3 = lp3lkb | f7_f12;
wire M19_6 = ((mw | lp1) & lkb) | (f7 & ta_alpha) | f7_f12 | f6;
wire M19_8 = f7_f12 | (sgn & f7) | (lp2 & lkb & ~mw);
assign clocktc = strob1b & M9_3;
assign clocktb = strob1b & M19_8;
assign clockta = strob1b & M19_6;
assign _0_t = start | (strob2 & ((g & wdt & f5) | (wc & f4) | (mw & f4) | (f4 & mf)));
wire M53_3 = f8 & (mw | mf | wdt);
assign taa = (dw_df & f8) | f12;
assign tab = f9dw | f11 | M53_3;
assign trb = M53_3 | f11;
wire M30_3 = ~(af_sf & ~wdt);
wire dwsgnf7 = dw & sgn & f7;
wire f7_f12 = f9 | f12 | f11 | (~dw & f7) | (M30_3 & f8);
assign t_1_t_1 = f8 | f12 | f11 | f9dw;
assign cp = strob1 & f8 & af_sf & ~wdt;
wire dw_p16 = dwsgnf7 | ~fp16_ | mw_p16;
wire M54_8 = wdt | ck;
wire M76_8 = ~ws & sf;
wire M76_3 = df & fic;
wire M76_6 = mf & ~ws;
wire M67_8 = f7 & ~sgn & dw;
wire M77_6 = (M54_8 & M76_8) | (~fic & df);
wire M65_6 = (mw & ~m14) | (dw & t0_neq_c0);
wire M78_8 = (~m38 & M76_6) | (ad) | (df & fic & t0_neq_c0) | (~ws & af);
wire M52_3 = M65_6 & f6;
wire M80_6 = ~p32_ | dwsgnf7 | sd;
wire M77_8 = (t0_eq_c0 & M76_3) | (M76_6 & m38);
wire mw_p16 = ~M65_6 & f6;
assign p_16 = dw_p16 & ~M67_8 & ~M52_3;
assign p_32 = M80_6 & ~ad;
assign p_40 = sd | ws | M77_6 | M77_8;
assign faa = M67_8 | M52_3 | fra;
assign fab = dwsgnf7 | frb;
assign fra = M52_3 | M78_8;
assign frb = mw_p16 | sd | M77_8 | M76_8;
wire df13 = (~lp3 & ss) | (ff & lp);
wire f4mwdw = f4 & dw_mw;
wire ta_alpha = ta & sgn_t0_c0;
wire f5_f8 = f5 | f8;
wire dw_mw = mw | dw;
wire f1f2_sel = (~dw & lp2) | (lp & ff);
wire ef1 = f1 & f1f2_sel;
wire ef2 = f1 & ~f1f2_sel;
wire ef3 = (f2 & ~(mw & fwz)) | (f3 & df13);
wire ef4 = f3 & (~lp | (lp3 & dw_mw));
wire ef5 = f4 & ~fwz & ~wt & ~wc & ~nrf & ff;
wire ef6 = opsu & ((dw & fic & f8) | (f8 & mw) | (f4mwdw & ~fwz));
wire ef7 = (ws & f10) | (sgn_t0_c0 & ta & f9dw) | (f4 & wc) | (f9 & sgn) | (f5_f8 & opsu & (mf | (df & fic))) | (f5_f8 & af_sf & ~fic & ~wt) | (f3 & lp3 & ad_sd);
wire M22_11 = (f5 & ff) | (f4 & dw_mw) | f8;
wire ef8 = (~opsu & ~fwz & M22_11 & fic) | (dw_mw & fic & f6) | (fic & f7);
wire ef9 = f8 & ~fic & dw_df;
wire ef10 = f11 | (f12 & ok) | (~sgn & df & f9) | (nrf & f4 & ~fwz) | (ff & f7 & ~fic) | (~fic & ~opsu & (f8 & mf));
wire ef11 = f10 & t0_neq_t_1;
wire ef12 = (f12 | f10) & nz;
wire M52_8 = f6 | (~opsu & f8);
wire M24_6 = f10 | f4 | (mw & f2);
wire ef13 = (M24_6 & fwz) | (ss & f7) | (~ws & ok & f10) | (df13 & f13) | (M52_8 & mw & ~fic) | (~sgn & f9dw & ~ta_alpha) | (wt & (f5 | f4));
assign scc = (mf & f5) | f7 | f11;
assign pc8 = (~mf & f5) | f11;
assign _0_d = strob2 & ((f5 & wdt) | (wc & f4));
assign _0_m = (strob2 & f9) | start;
assign mb = f11 | (af_sf & f8) | (mw_mf & f8);
assign ma = (dw_df & f8) | f12;
wire M27_12 = (mw_mf & f4) | fcb | f8;
assign clockm = M27_12 & strob1b;
wire M3_8 = mw & strob1b & f2;
wire lpb_s = (start & mw) | (~fwz & M3_8);
wire lpa_s = (start & ~mw) | (f2 & ~mw);
wire lpab_r = (M3_8 & fwz) | f7 | (f4 & ~dw) | (f4 & fwz);
wire lp_clk = strob1b & ((f8 & lp & dw) | f1 | f3 | f13);
wire lp1, lp2, lp3;
lp LP(
.clk_sys(clk_sys),
.lp_clk(lp_clk),
.lpb_s(lpb_s),
.lpa_s(lpa_s),
.lpab_r(lpab_r),
.out({lpb, lpa}),
.lp(lp),
.lp1(lp1),
.lp2(lp2),
.lp3(lp3)
);
assign zpa = f13 & ~lpa;
assign zpb = f13 & (~lpb ^ lpa);
assign _0_zp = f13 & fwz & lp;
assign s_fp = f13 & lp;
assign ustr0_fp = f13 & ~lp;
endmodule | 24 |
139,077 | data/full_repos/permissive/86722304/src/fp_strobgen.v | 86,722,304 | fp_strobgen.v | v | 122 | 104 | [] | [] | [] | [(1, 119)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/fp_strobgen.v:40: Little bit endian vector: MSB < LSB of bit range: 0:2\n reg [0:2] state;\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 304,293 | module | module fp_strobgen(
input clk_sys,
input start,
input di,
input dp8, dp2, dp6, dp5,
input mode,
input step,
input oken,
input f1,
input zw,
output ldstate,
output strob1,
output strob1b,
output strob2,
output strob2b,
output sr_fp
);
localparam S_GOT = 3'd0;
localparam S_GOTW = 3'd1;
localparam S_ST1 = 3'd2;
localparam S_ST1W = 3'd3;
localparam S_ST1B = 3'd4;
localparam S_PGOT = 3'd5;
localparam S_ST2 = 3'd6;
localparam S_ST2B = 3'd7;
wire if_busy = oken & f1 & zw;
wire es1 = dp8 | dp2 | dp6 | dp5;
wire has_strob2 = dp8 | dp2;
wire no_strob2 = dp6 | dp5;
wire __got = state == S_GOT;
assign strob1 = state == S_ST1;
assign strob1b = state == S_ST1B;
assign strob2 = state == S_ST2;
assign strob2b = state == S_ST2B;
assign ldstate = ~if_busy & ((state == S_PGOT) | ((state == S_ST1B) & no_strob2) | (state == S_ST2B));
reg [0:2] state;
always @ (posedge clk_sys) begin
case (state)
S_GOT:
if (es1) state <= S_ST1;
else state <= S_GOTW;
S_GOTW:
if (es1) state <= S_ST1;
S_ST1:
state <= S_ST1B;
S_ST1B:
if (has_strob2) state <= S_ST2;
else if (no_strob2 & !if_busy) state <= S_GOT;
else state <= S_PGOT;
S_ST2:
state <= S_ST2B;
S_ST2B:
if (!if_busy) state <= S_GOT;
else state <= S_PGOT;
S_PGOT:
if (!if_busy) state <= S_GOT;
endcase
end
wire got_fp = ~di & __got;
wire sr = start | got_fp;
assign sr_fp = sr & f1;
endmodule | module fp_strobgen(
input clk_sys,
input start,
input di,
input dp8, dp2, dp6, dp5,
input mode,
input step,
input oken,
input f1,
input zw,
output ldstate,
output strob1,
output strob1b,
output strob2,
output strob2b,
output sr_fp
); |
localparam S_GOT = 3'd0;
localparam S_GOTW = 3'd1;
localparam S_ST1 = 3'd2;
localparam S_ST1W = 3'd3;
localparam S_ST1B = 3'd4;
localparam S_PGOT = 3'd5;
localparam S_ST2 = 3'd6;
localparam S_ST2B = 3'd7;
wire if_busy = oken & f1 & zw;
wire es1 = dp8 | dp2 | dp6 | dp5;
wire has_strob2 = dp8 | dp2;
wire no_strob2 = dp6 | dp5;
wire __got = state == S_GOT;
assign strob1 = state == S_ST1;
assign strob1b = state == S_ST1B;
assign strob2 = state == S_ST2;
assign strob2b = state == S_ST2B;
assign ldstate = ~if_busy & ((state == S_PGOT) | ((state == S_ST1B) & no_strob2) | (state == S_ST2B));
reg [0:2] state;
always @ (posedge clk_sys) begin
case (state)
S_GOT:
if (es1) state <= S_ST1;
else state <= S_GOTW;
S_GOTW:
if (es1) state <= S_ST1;
S_ST1:
state <= S_ST1B;
S_ST1B:
if (has_strob2) state <= S_ST2;
else if (no_strob2 & !if_busy) state <= S_GOT;
else state <= S_PGOT;
S_ST2:
state <= S_ST2B;
S_ST2B:
if (!if_busy) state <= S_GOT;
else state <= S_PGOT;
S_PGOT:
if (!if_busy) state <= S_GOT;
endcase
end
wire got_fp = ~di & __got;
wire sr = start | got_fp;
assign sr_fp = sr & f1;
endmodule | 24 |
139,080 | data/full_repos/permissive/86722304/src/ifctl.v | 86,722,304 | ifctl.v | v | 89 | 111 | [] | [] | [] | null | line:20: before: ";" | null | 1: b"%Error: data/full_repos/permissive/86722304/src/ifctl.v:20: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'ALARM_DLY_TICKS'\n : ... In instance ifctl\n parameter ALARM_DLY_TICKS;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/ifctl.v:21: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'ALARM_TICKS'\n : ... In instance ifctl\n parameter ALARM_TICKS;\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 304,296 | module | module ifctl(
input clk_sys,
input clo,
input gotst1,
input zgi_j,
input zgi_set,
input ifhold_j,
input ifhold_reset,
input zw,
input ren,
input rok,
output reg ok$,
output zg,
output zwzg,
output talarm
);
parameter ALARM_DLY_TICKS;
parameter ALARM_TICKS;
wire oken = ren | rok;
assign zwzg = zgi & zw;
assign zg = zgi | ifhold | (zw & oken);
reg zgi;
always @ (posedge clk_sys, posedge clo) begin
if (clo) zgi <= 1'b0;
else if (zgi_set) zgi <= 1'b1;
else if (gotst1) case (zgi_j)
1'b0: zgi <= 1'b0;
1'b1: zgi <= ~zgi;
endcase
end
reg ifhold;
wire ifh_reset = ifhold_reset | clo;
always @ (posedge clk_sys, posedge ifh_reset) begin
if (ifh_reset) ifhold <= 1'b0;
else if (ok$) case ({ifhold_j, ifhold})
2'b00: ifhold <= ifhold;
2'b01: ifhold <= 1'b0;
2'b10: ifhold <= 1'b1;
2'b11: ifhold <= ~ifhold;
endcase
end
wire ok_clk = ren | talarm | rok;
always @ (posedge clk_sys, negedge zgi) begin
if (!zgi) ok$ <= 0;
else ok$ <= zwzg & ok_clk;
end
wire alarm = zwzg & ~ok$;
alarm #(
.ALARM_DLY_TICKS(ALARM_DLY_TICKS),
.ALARM_TICKS(ALARM_TICKS)
) ALARM(
.clk_sys(clk_sys),
.engage(alarm),
.talarm(talarm)
);
endmodule | module ifctl(
input clk_sys,
input clo,
input gotst1,
input zgi_j,
input zgi_set,
input ifhold_j,
input ifhold_reset,
input zw,
input ren,
input rok,
output reg ok$,
output zg,
output zwzg,
output talarm
); |
parameter ALARM_DLY_TICKS;
parameter ALARM_TICKS;
wire oken = ren | rok;
assign zwzg = zgi & zw;
assign zg = zgi | ifhold | (zw & oken);
reg zgi;
always @ (posedge clk_sys, posedge clo) begin
if (clo) zgi <= 1'b0;
else if (zgi_set) zgi <= 1'b1;
else if (gotst1) case (zgi_j)
1'b0: zgi <= 1'b0;
1'b1: zgi <= ~zgi;
endcase
end
reg ifhold;
wire ifh_reset = ifhold_reset | clo;
always @ (posedge clk_sys, posedge ifh_reset) begin
if (ifh_reset) ifhold <= 1'b0;
else if (ok$) case ({ifhold_j, ifhold})
2'b00: ifhold <= ifhold;
2'b01: ifhold <= 1'b0;
2'b10: ifhold <= 1'b1;
2'b11: ifhold <= ~ifhold;
endcase
end
wire ok_clk = ren | talarm | rok;
always @ (posedge clk_sys, negedge zgi) begin
if (!zgi) ok$ <= 0;
else ok$ <= zwzg & ok_clk;
end
wire alarm = zwzg & ~ok$;
alarm #(
.ALARM_DLY_TICKS(ALARM_DLY_TICKS),
.ALARM_TICKS(ALARM_TICKS)
) ALARM(
.clk_sys(clk_sys),
.engage(alarm),
.talarm(talarm)
);
endmodule | 24 |
139,082 | data/full_repos/permissive/86722304/src/ir.v | 86,722,304 | ir.v | v | 25 | 96 | [] | [] | [] | [(3, 22)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/ir.v:5: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] d,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/ir.v:8: Little bit endian vector: MSB < LSB of bit range: 0:15\n output reg [0:15] q\n ^\n%Error: Exiting due to 2 warning(s)\n' | 304,298 | module | module ir(
input clk_sys,
input [0:15] d,
input c,
input invalidate,
output reg [0:15] q
);
always @ (posedge clk_sys, posedge invalidate) begin
if (invalidate) q[0:1] <= 2'd0;
else if (c) q <= d;
end
endmodule | module ir(
input clk_sys,
input [0:15] d,
input c,
input invalidate,
output reg [0:15] q
); |
always @ (posedge clk_sys, posedge invalidate) begin
if (invalidate) q[0:1] <= 2'd0;
else if (c) q <= d;
end
endmodule | 24 |
139,083 | data/full_repos/permissive/86722304/src/isk.v | 86,722,304 | isk.v | v | 45 | 55 | [] | [] | [] | null | line:5: before: "]" | null | 1: b"%Error: data/full_repos/permissive/86722304/src/isk.v:5: Define or directive not defined: '`BUS_MAX'\n input [0:`BUS_MAX] cpu0d,\n ^~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/isk.v:5: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\n input [0:`BUS_MAX] cpu0d,\n ^\n%Error: data/full_repos/permissive/86722304/src/isk.v:6: Define or directive not defined: '`BUS_MAX'\n output [0:`BUS_MAX] cpu0r,\n ^~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/isk.v:7: Define or directive not defined: '`BUS_MAX'\n input [0:`BUS_MAX] cpu1d,\n ^~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/isk.v:8: Define or directive not defined: '`BUS_MAX'\n output [0:`BUS_MAX] cpu1r,\n ^~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/isk.v:9: Define or directive not defined: '`BUS_MAX'\n input [0:`BUS_MAX] iobd,\n ^~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/isk.v:10: Define or directive not defined: '`BUS_MAX'\n output [0:`BUS_MAX] iobr,\n ^~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/isk.v:11: Define or directive not defined: '`BUS_MAX'\n input [0:`BUS_MAX] memd,\n ^~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/isk.v:12: Define or directive not defined: '`BUS_MAX'\n output [0:`BUS_MAX] memr,\n ^~~~~~~~\n%Error: Exiting due to 9 error(s)\n" | 304,299 | module | module isk(
input clk_sys,
input [0:`BUS_MAX] cpu0d,
output [0:`BUS_MAX] cpu0r,
input [0:`BUS_MAX] cpu1d,
output [0:`BUS_MAX] cpu1r,
input [0:`BUS_MAX] iobd,
output [0:`BUS_MAX] iobr,
input [0:`BUS_MAX] memd,
output [0:`BUS_MAX] memr,
input [1:4] zg,
input [1:4] zz,
output [1:4] zw
);
always @ (posedge clk_sys) begin
if (zg[1] & ~zw[2] & ~zw[3] & ~zw[4]) zw[1] <= 1;
else begin
zw[1] <= 0;
if (zg[2] & ~zw[1] & ~zw[3] & ~zw[4]) zw[2] <= 1;
else begin
zw[2] <= 0;
if (zg[3] & ~zw[1] & ~zw[2] & ~zw[4]) zw[3] <= 1;
else begin
zw[3] <= 0;
if (zg[4] & ~zw[1] & ~zw[2] & ~zw[3]) zw[4] <= 1;
else begin
zw[4] <= 0;
end
end
end
end
end
assign cpu0r = 0 | cpu1d | iobd | memd;
assign cpu1r = cpu0d | 0 | iobd | memd;
assign iobr = cpu0d | cpu1d | 0 | memd;
assign memr = cpu0d | cpu1d | iobd | 0;
endmodule | module isk(
input clk_sys,
input [0:`BUS_MAX] cpu0d,
output [0:`BUS_MAX] cpu0r,
input [0:`BUS_MAX] cpu1d,
output [0:`BUS_MAX] cpu1r,
input [0:`BUS_MAX] iobd,
output [0:`BUS_MAX] iobr,
input [0:`BUS_MAX] memd,
output [0:`BUS_MAX] memr,
input [1:4] zg,
input [1:4] zz,
output [1:4] zw
); |
always @ (posedge clk_sys) begin
if (zg[1] & ~zw[2] & ~zw[3] & ~zw[4]) zw[1] <= 1;
else begin
zw[1] <= 0;
if (zg[2] & ~zw[1] & ~zw[3] & ~zw[4]) zw[2] <= 1;
else begin
zw[2] <= 0;
if (zg[3] & ~zw[1] & ~zw[2] & ~zw[4]) zw[3] <= 1;
else begin
zw[3] <= 0;
if (zg[4] & ~zw[1] & ~zw[2] & ~zw[3]) zw[4] <= 1;
else begin
zw[4] <= 0;
end
end
end
end
end
assign cpu0r = 0 | cpu1d | iobd | memd;
assign cpu1r = cpu0d | 0 | iobd | memd;
assign iobr = cpu0d | cpu1d | 0 | memd;
assign memr = cpu0d | cpu1d | iobd | 0;
endmodule | 24 |
139,085 | data/full_repos/permissive/86722304/src/kcpc.v | 86,722,304 | kcpc.v | v | 53 | 54 | [] | [] | [] | [(3, 50)] | null | null | 1: b"%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/kcpc.v:44: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'pr'\n : ... In instance kcpc\n if (rescyc) pr <= 1'b0;\n ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/kcpc.v:45: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'pr'\n : ... In instance kcpc\n else if (idle & kc_trig) pr <= dpr;\n ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/kcpc.v:46: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'przerw'\n : ... In instance kcpc\n if (clm) przerw <= 1'b0;\n ^~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/kcpc.v:47: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'przerw'\n : ... In instance kcpc\n else if (idle & kc_trig) przerw <= dprzerw;\n ^~~~~~\n%Error: Exiting due to 4 error(s)\n ... See the manual and https://verilator.org for more assistance.\n" | 304,301 | module | module kcpc(
input clk_sys,
input kc_reset,
input ekc,
input ekc_fp,
input ldstate,
input rescyc,
input dpr,
output pr,
input clm,
input dprzerw,
output przerw,
output kc,
output pc
);
localparam ST_IDLE = 2'd0;
localparam ST_KC = 2'd1;
localparam ST_PC = 2'd2;
assign kc = (state == ST_KC);
assign pc = (state == ST_PC);
wire idle = (state == ST_IDLE);
wire kc_trig = (ldstate & ekc) | ekc_fp;
reg [1:0] state = ST_IDLE;
always @ (posedge clk_sys) begin
if (kc_reset) state <= ST_IDLE;
else case (state)
ST_IDLE: if (kc_trig) state <= ST_KC;
ST_KC: state <= ST_PC;
ST_PC: state <= ST_IDLE;
endcase
end
always @ (posedge clk_sys) begin
if (rescyc) pr <= 1'b0;
else if (idle & kc_trig) pr <= dpr;
if (clm) przerw <= 1'b0;
else if (idle & kc_trig) przerw <= dprzerw;
end
endmodule | module kcpc(
input clk_sys,
input kc_reset,
input ekc,
input ekc_fp,
input ldstate,
input rescyc,
input dpr,
output pr,
input clm,
input dprzerw,
output przerw,
output kc,
output pc
); |
localparam ST_IDLE = 2'd0;
localparam ST_KC = 2'd1;
localparam ST_PC = 2'd2;
assign kc = (state == ST_KC);
assign pc = (state == ST_PC);
wire idle = (state == ST_IDLE);
wire kc_trig = (ldstate & ekc) | ekc_fp;
reg [1:0] state = ST_IDLE;
always @ (posedge clk_sys) begin
if (kc_reset) state <= ST_IDLE;
else case (state)
ST_IDLE: if (kc_trig) state <= ST_KC;
ST_KC: state <= ST_PC;
ST_PC: state <= ST_IDLE;
endcase
end
always @ (posedge clk_sys) begin
if (rescyc) pr <= 1'b0;
else if (idle & kc_trig) pr <= dpr;
if (clm) przerw <= 1'b0;
else if (idle & kc_trig) przerw <= dprzerw;
end
endmodule | 24 |
139,089 | data/full_repos/permissive/86722304/src/lg.v | 86,722,304 | lg.v | v | 39 | 70 | [] | [] | [] | [(3, 36)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/lg.v:9: Little bit endian vector: MSB < LSB of bit range: 7:9\n input [7:9] ir,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/lg.v:17: Little bit endian vector: MSB < LSB of bit range: 0:2\n reg [0:2] lg;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 304,305 | module | module lg(
input clk_sys,
input reset,
input cu,
input gr,
input slg1, slg2,
input [7:9] ir,
output lg_0, lg_1, lg_2, lg_3,
output lga, lgb, lgc
);
reg [0:2] lg;
always @ (posedge clk_sys, posedge reset) begin
if (reset) lg <= 3'd0;
else case ({slg1, slg2, cu})
3'b100: lg <= ir[7:9];
3'b010: lg <= {(ir[8] & ir[9]), 2'b01};
3'b001: lg <= {gr, 2'b11} & (lg + 1'b1);
default: lg <= lg;
endcase
end
assign lga = lg[2];
assign lgb = lg[1];
assign lgc = lg[0];
assign lg_3 = lg[1:2] == 3;
assign lg_2 = lg[1:2] == 2;
assign lg_1 = lg[1:2] == 1;
assign lg_0 = lg[1:2] == 0;
endmodule | module lg(
input clk_sys,
input reset,
input cu,
input gr,
input slg1, slg2,
input [7:9] ir,
output lg_0, lg_1, lg_2, lg_3,
output lga, lgb, lgc
); |
reg [0:2] lg;
always @ (posedge clk_sys, posedge reset) begin
if (reset) lg <= 3'd0;
else case ({slg1, slg2, cu})
3'b100: lg <= ir[7:9];
3'b010: lg <= {(ir[8] & ir[9]), 2'b01};
3'b001: lg <= {gr, 2'b11} & (lg + 1'b1);
default: lg <= lg;
endcase
end
assign lga = lg[2];
assign lgb = lg[1];
assign lgc = lg[0];
assign lg_3 = lg[1:2] == 3;
assign lg_2 = lg[1:2] == 2;
assign lg_1 = lg[1:2] == 1;
assign lg_0 = lg[1:2] == 0;
endmodule | 24 |
139,093 | data/full_repos/permissive/86722304/src/mc.v | 86,722,304 | mc.v | v | 24 | 54 | [] | [] | [] | [(3, 21)] | null | data/verilator_xmls/05a1f440-3ac7-47b7-bfd8-a89300d3816d.xml | null | 304,309 | module | module mc(
input clk_sys,
input inc,
input reset,
output mc_3,
output mc_0
);
reg [1:0] mc;
always @ (posedge clk_sys, posedge reset) begin
if (reset) mc <= 2'd0;
else if (inc) mc <= mc + 1'b1;
end
assign mc_3 = (mc == 3);
assign mc_0 = (mc == 0);
endmodule | module mc(
input clk_sys,
input inc,
input reset,
output mc_3,
output mc_0
); |
reg [1:0] mc;
always @ (posedge clk_sys, posedge reset) begin
if (reset) mc <= 2'd0;
else if (inc) mc <= mc + 1'b1;
end
assign mc_3 = (mc == 3);
assign mc_0 = (mc == 0);
endmodule | 24 |
139,094 | data/full_repos/permissive/86722304/src/memcfg.v | 86,722,304 | memcfg.v | v | 135 | 78 | [] | [] | [] | null | line:16: before: ";" | null | 1: b"%Error: data/full_repos/permissive/86722304/src/memcfg.v:16: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'MODULE_ADDR_WIDTH'\n : ... In instance memcfg\n parameter MODULE_ADDR_WIDTH;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/memcfg.v:17: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'FRAME_ADDR_WIDTH'\n : ... In instance memcfg\n parameter FRAME_ADDR_WIDTH;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/memcfg.v:65: Expecting expression to be constant, but variable isn't const: 'MODULE_ADDR_WIDTH'\n : ... In instance memcfg\n localparam mmask = 2**MODULE_ADDR_WIDTH - 1;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/memcfg.v:66: Expecting expression to be constant, but variable isn't const: 'FRAME_ADDR_WIDTH'\n : ... In instance memcfg\n localparam fmask = 2**FRAME_ADDR_WIDTH - 1;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/memcfg.v:67: Expecting expression to be constant, but variable isn't const: 'fmask'\n : ... In instance memcfg\n localparam [3:0] frame_addr_mask = fmask[3:0];\n ^~~~~\n%Error: data/full_repos/permissive/86722304/src/memcfg.v:68: Expecting expression to be constant, but variable isn't const: 'mmask'\n : ... In instance memcfg\n localparam [3:0] module_addr_mask = mmask[3:0];\n ^~~~~\n%Error: data/full_repos/permissive/86722304/src/memcfg.v:69: Expecting expression to be constant, but variable isn't const: 'module_addr_mask'\n : ... In instance memcfg\n localparam [7:0] invalidity_mask = ~{module_addr_mask, frame_addr_mask};\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/memcfg.v:69: Expecting expression to be constant, but variable isn't const: 'frame_addr_mask'\n : ... In instance memcfg\n localparam [7:0] invalidity_mask = ~{module_addr_mask, frame_addr_mask};\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n" | 304,310 | module | module memcfg(
input clk,
input reset,
output reset_hold,
input s,
input [0:7] cfg_page,
input [0:7] cfg_frame,
input [0:7] page,
output cfgok,
output [0:7] frame,
output pvalid
);
parameter MODULE_ADDR_WIDTH;
parameter FRAME_ADDR_WIDTH;
wire [0:7] addr;
always @ (*) begin
case ({reset, s})
2'b00: addr = page;
2'b01: addr = cfg_page;
2'b10: addr = clr_cnt;
2'b11: addr = clr_cnt;
endcase
end
initial begin
reg [8:0] i;
for (i=0 ; i<9'd256 ; i=i+9'd1) begin
if (i == 1) map[i] = 1;
else map[i] = 0;
end
end
reg map_wr = 0;
reg [0:7] rd_addr;
reg [0:7] map [0:255];
always @ (posedge clk) begin
if (map_wr) map[addr] <= cfg_frame & frame_clear;
rd_addr <= addr;
end
assign frame = map[rd_addr];
localparam mmask = 2**MODULE_ADDR_WIDTH - 1;
localparam fmask = 2**FRAME_ADDR_WIDTH - 1;
localparam [3:0] frame_addr_mask = fmask[3:0];
localparam [3:0] module_addr_mask = mmask[3:0];
localparam [7:0] invalidity_mask = ~{module_addr_mask, frame_addr_mask};
assign pvalid = (addr < 2) || (frame != 0);
wire frame_addr_valid = (cfg_frame & invalidity_mask) == 8'd0;
wire cfg_cmd_valid = s && (cfg_page > 1) && frame_addr_valid;
localparam CIDLE = 3'd0;
localparam CCFG = 3'd1;
localparam COK = 3'd2;
localparam RESET = 3'd3;
localparam CLEAR = 3'd4;
reg [2:0] cstate = CIDLE;
reg [7:0] clr_cnt;
reg [7:0] frame_clear;
assign reset_hold = (cstate == CLEAR) | (cstate == RESET);
always @ (posedge clk) begin
if (reset & ~reset_hold) cstate <= RESET;
else case (cstate)
CIDLE: begin
frame_clear <= 8'hff;
if (cfg_cmd_valid) begin
map_wr <= 1;
cstate <= CCFG;
end
end
CCFG: begin
map_wr <= 0;
cfgok <= 1;
cstate <= COK;
end
COK: begin
if (~s) begin
cfgok <= 0;
cstate <= CIDLE;
end
end
RESET: begin
clr_cnt <= 2;
map_wr <= 1;
frame_clear <= 8'd0;
cstate <= CLEAR;
end
CLEAR: begin
if (clr_cnt == 8'hff) begin
cstate <= CIDLE;
map_wr <= 0;
end else begin
clr_cnt <= clr_cnt + 1'b1;
end
end
endcase
end
endmodule | module memcfg(
input clk,
input reset,
output reset_hold,
input s,
input [0:7] cfg_page,
input [0:7] cfg_frame,
input [0:7] page,
output cfgok,
output [0:7] frame,
output pvalid
); |
parameter MODULE_ADDR_WIDTH;
parameter FRAME_ADDR_WIDTH;
wire [0:7] addr;
always @ (*) begin
case ({reset, s})
2'b00: addr = page;
2'b01: addr = cfg_page;
2'b10: addr = clr_cnt;
2'b11: addr = clr_cnt;
endcase
end
initial begin
reg [8:0] i;
for (i=0 ; i<9'd256 ; i=i+9'd1) begin
if (i == 1) map[i] = 1;
else map[i] = 0;
end
end
reg map_wr = 0;
reg [0:7] rd_addr;
reg [0:7] map [0:255];
always @ (posedge clk) begin
if (map_wr) map[addr] <= cfg_frame & frame_clear;
rd_addr <= addr;
end
assign frame = map[rd_addr];
localparam mmask = 2**MODULE_ADDR_WIDTH - 1;
localparam fmask = 2**FRAME_ADDR_WIDTH - 1;
localparam [3:0] frame_addr_mask = fmask[3:0];
localparam [3:0] module_addr_mask = mmask[3:0];
localparam [7:0] invalidity_mask = ~{module_addr_mask, frame_addr_mask};
assign pvalid = (addr < 2) || (frame != 0);
wire frame_addr_valid = (cfg_frame & invalidity_mask) == 8'd0;
wire cfg_cmd_valid = s && (cfg_page > 1) && frame_addr_valid;
localparam CIDLE = 3'd0;
localparam CCFG = 3'd1;
localparam COK = 3'd2;
localparam RESET = 3'd3;
localparam CLEAR = 3'd4;
reg [2:0] cstate = CIDLE;
reg [7:0] clr_cnt;
reg [7:0] frame_clear;
assign reset_hold = (cstate == CLEAR) | (cstate == RESET);
always @ (posedge clk) begin
if (reset & ~reset_hold) cstate <= RESET;
else case (cstate)
CIDLE: begin
frame_clear <= 8'hff;
if (cfg_cmd_valid) begin
map_wr <= 1;
cstate <= CCFG;
end
end
CCFG: begin
map_wr <= 0;
cfgok <= 1;
cstate <= COK;
end
COK: begin
if (~s) begin
cfgok <= 0;
cstate <= CIDLE;
end
end
RESET: begin
clr_cnt <= 2;
map_wr <= 1;
frame_clear <= 8'd0;
cstate <= CLEAR;
end
CLEAR: begin
if (clr_cnt == 8'hff) begin
cstate <= CIDLE;
map_wr <= 0;
end else begin
clr_cnt <= clr_cnt + 1'b1;
end
end
endcase
end
endmodule | 24 |
139,095 | data/full_repos/permissive/86722304/src/mem_dummy_sram.v | 86,722,304 | mem_dummy_sram.v | v | 77 | 54 | [] | [] | [] | [(3, 74)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/mem_dummy_sram.v:8: Little bit endian vector: MSB < LSB of bit range: 0:3\n input [0:3] nb_,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/mem_dummy_sram.v:9: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] ad_,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/mem_dummy_sram.v:10: Little bit endian vector: MSB < LSB of bit range: 0:15\n output [0:15] ddt_,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/mem_dummy_sram.v:11: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] rdt_,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/mem_dummy_sram.v:30: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] rd_data;\n ^\n%Error: Exiting due to 5 warning(s)\n' | 304,311 | module | module mem_dummy_sram(
input clk,
output SRAM_CE, SRAM_OE, SRAM_WE, SRAM_UB, SRAM_LB,
output [17:0] SRAM_A,
inout [15:0] SRAM_D,
input [0:3] nb_,
input [0:15] ad_,
output [0:15] ddt_,
input [0:15] rdt_,
input w_, r_, s_,
output ok_
);
assign SRAM_CE = 0;
assign SRAM_UB = 0;
assign SRAM_LB = 0;
assign SRAM_WE = ~we;
assign SRAM_OE = ~oe;
assign ok_ = ~(ok & (~r_ | ~w_));
`define IDLE 0
`define READ 1
`define WRITE 2
`define OK 3
reg [1:0] state = `IDLE;
reg we, oe, ok;
reg [0:15] rd_data;
always @ (posedge clk) begin
case (state)
`IDLE: begin
if (~r_) begin
state <= `READ;
oe <= 1;
end else if (~w_) begin
state <= `WRITE;
we <= 1;
end
end
`READ: begin
rd_data <= SRAM_D;
ok <= 1;
state <= `OK;
end
`WRITE: begin
we <= 0;
ok <= 1;
state <= `OK;
end
`OK: begin
oe <= 0;
if (r_ & w_) begin
ok <= 0;
state <= `IDLE;
end
end
endcase
end
assign SRAM_A[17:0] = {2'b00, ~ad_};
assign SRAM_D = we ? ~rdt_ : 16'hzzzz;
assign ddt_ = ~r_ ? ~rd_data : 16'hffff;
endmodule | module mem_dummy_sram(
input clk,
output SRAM_CE, SRAM_OE, SRAM_WE, SRAM_UB, SRAM_LB,
output [17:0] SRAM_A,
inout [15:0] SRAM_D,
input [0:3] nb_,
input [0:15] ad_,
output [0:15] ddt_,
input [0:15] rdt_,
input w_, r_, s_,
output ok_
); |
assign SRAM_CE = 0;
assign SRAM_UB = 0;
assign SRAM_LB = 0;
assign SRAM_WE = ~we;
assign SRAM_OE = ~oe;
assign ok_ = ~(ok & (~r_ | ~w_));
`define IDLE 0
`define READ 1
`define WRITE 2
`define OK 3
reg [1:0] state = `IDLE;
reg we, oe, ok;
reg [0:15] rd_data;
always @ (posedge clk) begin
case (state)
`IDLE: begin
if (~r_) begin
state <= `READ;
oe <= 1;
end else if (~w_) begin
state <= `WRITE;
we <= 1;
end
end
`READ: begin
rd_data <= SRAM_D;
ok <= 1;
state <= `OK;
end
`WRITE: begin
we <= 0;
ok <= 1;
state <= `OK;
end
`OK: begin
oe <= 0;
if (r_ & w_) begin
ok <= 0;
state <= `IDLE;
end
end
endcase
end
assign SRAM_A[17:0] = {2'b00, ~ad_};
assign SRAM_D = we ? ~rdt_ : 16'hzzzz;
assign ddt_ = ~r_ ? ~rd_data : 16'hffff;
endmodule | 24 |
139,096 | data/full_repos/permissive/86722304/src/mem_elwro_sram.v | 86,722,304 | mem_elwro_sram.v | v | 84 | 78 | [] | [] | [] | [(3, 81)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:10: Little bit endian vector: MSB < LSB of bit range: 0:3\n input [0:3] nb,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:11: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] ad,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:12: Little bit endian vector: MSB < LSB of bit range: 0:15\n output [0:15] ddt,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:13: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] rdt,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:20: Little bit endian vector: MSB < LSB of bit range: 0:7\n wire [0:7] cfg_page = { rdt[12:15], rdt[0:3] };\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:21: Little bit endian vector: MSB < LSB of bit range: 0:7\n wire [0:7] cfg_frame = { ad[11:14], 1\'b0, ad[8:10] };\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:22: Little bit endian vector: MSB < LSB of bit range: 0:7\n wire [0:7] page = { nb, ad[0:3] };\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:23: Little bit endian vector: MSB < LSB of bit range: 0:7\n wire [0:7] frame;\n ^\n%Error: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:27: Cannot find file containing module: \'memcfg\'\n memcfg #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/86722304/src,data/full_repos/permissive/86722304/memcfg\n data/full_repos/permissive/86722304/src,data/full_repos/permissive/86722304/memcfg.v\n data/full_repos/permissive/86722304/src,data/full_repos/permissive/86722304/memcfg.sv\n memcfg\n memcfg.v\n memcfg.sv\n obj_dir/memcfg\n obj_dir/memcfg.v\n obj_dir/memcfg.sv\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:49: Little bit endian vector: MSB < LSB of bit range: 0:2\n reg [0:2] state = IDLE;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:49: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n : ... In instance mem_elwro_sram\n reg [0:2] state = IDLE;\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:56: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'MAP\' generates 2 bits.\n : ... In instance mem_elwro_sram\n if (rw) state <= MAP;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:58: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'OK1\' generates 2 bits.\n : ... In instance mem_elwro_sram\n if (pvalid) state <= OK1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:59: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n : ... In instance mem_elwro_sram\n else state <= IDLE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:61: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'OK2\' generates 2 bits.\n : ... In instance mem_elwro_sram\n state <= OK2;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:63: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n : ... In instance mem_elwro_sram\n if (~rw) state <= IDLE;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:54: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'IDLE\' generates 2 bits.\n : ... In instance mem_elwro_sram\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:54: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'MAP\' generates 2 bits.\n : ... In instance mem_elwro_sram\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:54: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'OK1\' generates 2 bits.\n : ... In instance mem_elwro_sram\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:54: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'OK2\' generates 2 bits.\n : ... In instance mem_elwro_sram\n case (state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:67: Operator EQ expects 3 bits on the RHS, but RHS\'s VARREF \'OK1\' generates 2 bits.\n : ... In instance mem_elwro_sram\n wire we = w & (state == OK1);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:68: Operator EQ expects 3 bits on the RHS, but RHS\'s VARREF \'OK1\' generates 2 bits.\n : ... In instance mem_elwro_sram\n wire rwok = rw & ((state == OK1) || (state == OK2));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/86722304/src/mem_elwro_sram.v:68: Operator EQ expects 3 bits on the RHS, but RHS\'s VARREF \'OK2\' generates 2 bits.\n : ... In instance mem_elwro_sram\n wire rwok = rw & ((state == OK1) || (state == OK2));\n ^~\n%Error: Exiting due to 1 error(s), 22 warning(s)\n' | 304,312 | module | module mem_elwro_sram(
input clk,
input reset,
output reset_hold,
output ram_ce, ram_oe, ram_we,
output [17:0] ram_a,
inout [15:0] ram_d,
input [0:3] nb,
input [0:15] ad,
output [0:15] ddt,
input [0:15] rdt,
input w, r, s,
output ok
);
wire [0:7] cfg_page = { rdt[12:15], rdt[0:3] };
wire [0:7] cfg_frame = { ad[11:14], 1'b0, ad[8:10] };
wire [0:7] page = { nb, ad[0:3] };
wire [0:7] frame;
wire cfgok;
wire pvalid;
memcfg #(
.MODULE_ADDR_WIDTH(2),
.FRAME_ADDR_WIDTH(3)
) MEMCFG(
.clk(clk),
.reset(reset),
.reset_hold(reset_hold),
.s(s & ad[15]),
.cfg_page(cfg_page),
.cfg_frame(cfg_frame),
.page(page),
.frame(frame),
.cfgok(cfgok),
.pvalid(pvalid)
);
localparam IDLE = 2'd0;
localparam MAP = 2'd1;
localparam OK1 = 2'd2;
localparam OK2 = 2'd3;
reg [0:2] state = IDLE;
wire rw = r | w;
always @ (posedge clk) begin
case (state)
IDLE:
if (rw) state <= MAP;
MAP:
if (pvalid) state <= OK1;
else state <= IDLE;
OK1:
state <= OK2;
OK2:
if (~rw) state <= IDLE;
endcase
end
wire we = w & (state == OK1);
wire rwok = rw & ((state == OK1) || (state == OK2));
assign ok = rwok | cfgok;
assign ddt = r ? ram_d : 16'h0000;
assign ram_ce = 1;
assign ram_we = we;
assign ram_oe = 1;
assign ram_a[17:0] = { frame[2:7], ad[4:15] };
assign ram_d = we ? rdt : 16'hzzzz;
endmodule | module mem_elwro_sram(
input clk,
input reset,
output reset_hold,
output ram_ce, ram_oe, ram_we,
output [17:0] ram_a,
inout [15:0] ram_d,
input [0:3] nb,
input [0:15] ad,
output [0:15] ddt,
input [0:15] rdt,
input w, r, s,
output ok
); |
wire [0:7] cfg_page = { rdt[12:15], rdt[0:3] };
wire [0:7] cfg_frame = { ad[11:14], 1'b0, ad[8:10] };
wire [0:7] page = { nb, ad[0:3] };
wire [0:7] frame;
wire cfgok;
wire pvalid;
memcfg #(
.MODULE_ADDR_WIDTH(2),
.FRAME_ADDR_WIDTH(3)
) MEMCFG(
.clk(clk),
.reset(reset),
.reset_hold(reset_hold),
.s(s & ad[15]),
.cfg_page(cfg_page),
.cfg_frame(cfg_frame),
.page(page),
.frame(frame),
.cfgok(cfgok),
.pvalid(pvalid)
);
localparam IDLE = 2'd0;
localparam MAP = 2'd1;
localparam OK1 = 2'd2;
localparam OK2 = 2'd3;
reg [0:2] state = IDLE;
wire rw = r | w;
always @ (posedge clk) begin
case (state)
IDLE:
if (rw) state <= MAP;
MAP:
if (pvalid) state <= OK1;
else state <= IDLE;
OK1:
state <= OK2;
OK2:
if (~rw) state <= IDLE;
endcase
end
wire we = w & (state == OK1);
wire rwok = rw & ((state == OK1) || (state == OK2));
assign ok = rwok | cfgok;
assign ddt = r ? ram_d : 16'h0000;
assign ram_ce = 1;
assign ram_we = we;
assign ram_oe = 1;
assign ram_a[17:0] = { frame[2:7], ad[4:15] };
assign ram_d = we ? rdt : 16'hzzzz;
endmodule | 24 |
139,097 | data/full_repos/permissive/86722304/src/mera400f.v | 86,722,304 | mera400f.v | v | 344 | 78 | [] | [] | [] | null | line:16: before: ";" | null | 1: b"%Error: data/full_repos/permissive/86722304/src/mera400f.v:16: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'CLK_EXT_HZ'\n : ... In instance mera400f\n parameter CLK_EXT_HZ;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/mera400f.v:22: Expecting expression to be constant, but variable isn't const: 'CLK_EXT_HZ'\n : ... In instance mera400f\n localparam CLK_SYS_HZ = CLK_EXT_HZ;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/mera400f.v:23: Expecting expression to be constant, but variable isn't const: 'CLK_EXT_HZ'\n : ... In instance mera400f\n localparam CLK_UART_HZ = CLK_EXT_HZ;\n ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 304,313 | module | module mera400f(
input clk_ext,
input rxd,
output txd,
output ram_ce, ram_oe, ram_we,
output [17:0] ram_a,
inout [15:0] ram_d,
output [0:15] w,
output [10:0] rotary_bus,
output [0:9] indicators
);
parameter CLK_EXT_HZ;
localparam CLK_SYS_HZ = CLK_EXT_HZ;
localparam CLK_UART_HZ = CLK_EXT_HZ;
wire clk_sys = clk_ext;
wire clk_uart = clk_ext;
wire clk_ram = clk_ext;
`define pa 0
`define cl 1
`define w 2
`define r 3
`define s 4
`define f 5
`define in 6
`define ok 7
`define en 8
`define pe 9
`define qb 10
`define pn 11
`define nb 12:15
`define ad 16:31
`define dt 32:47
`define BUS_MAX 47
wire [0:`BUS_MAX] cpu0r;
wire [0:`BUS_MAX] cpu1r;
wire [0:`BUS_MAX] memr;
wire [0:`BUS_MAX] iobr;
wire [1:4] zg;
wire [1:4] zw;
wire [1:4] zz;
isk ISK(
.clk_sys(clk_sys),
.cpu0d(cpu0d),
.cpu0r(cpu0r),
.cpu1d(48'd0),
.cpu1r(cpu1r),
.iobd(iobd),
.iobr(iobr),
.memd(memd),
.memr(memr),
.zg(zg),
.zw(zw),
.zz(zz)
);
wire [0:`BUS_MAX] cpu0d;
wire dmcl;
assign cpu0d[`cl] = dcl | dmcl;
wire p0;
wire hlt_n, p, run, _wait, irq, q, mc_0, awaria;
cpu #(
.CPU_NUMBER(1'b0),
.AWP_PRESENT(1'b1),
.INOU_USER_ILLEGAL(1'b1),
.STOP_ON_NOMEM(1'b1),
.LOW_MEM_WRITE_DENY(1'b0),
.ALARM_DLY_TICKS(23'd5_000_000),
.ALARM_TICKS(8'd3)
) CPU0(
.clk_sys(clk_sys),
.off(off),
.pon(pon),
.pout(pout),
.clm(clm),
.clo(clo),
.kl(kl),
.panel_store(panel_store),
.panel_fetch(panel_fetch),
.panel_load(panel_load),
.panel_bin(panel_bin),
.oprq(oprq),
.stop(stop),
.start(start),
.work(work),
.mode(mode),
.step(step),
.stop_n(stop_n),
.cycle(cycle),
.wre(wre),
.rsa(rsa),
.rsb(rsb),
.rsc(rsc),
.wic(wic),
.wac(wac),
.war(war),
.wir(wir),
.wrs(wrs),
.wrz(wrz),
.wkb(wkb),
.zegar(zegar),
.p0(p0),
.w(w),
.hlt_n(hlt_n),
.p(p),
.run(run),
._wait(_wait),
.irq(irq),
.q(q),
.mc_0(mc_0),
.awaria(awaria),
.dmcl(dmcl),
.dw(cpu0d[`w]),
.dr(cpu0d[`r]),
.ds(cpu0d[`s]),
.df(cpu0d[`f]),
.din(cpu0d[`in]),
.dok(cpu0d[`ok]),
.dqb(cpu0d[`qb]),
.dpn(cpu0d[`pn]),
.dnb(cpu0d[`nb]),
.dad(cpu0d[`ad]),
.ddt(cpu0d[`dt]),
.rpa(cpu0r[`pa]),
.rin(cpu0r[`in]),
.rok(cpu0r[`ok]),
.ren(cpu0r[`en]),
.rpe(cpu0r[`pe]),
.rpn(cpu0r[`pn]),
.rdt(cpu0r[`dt]),
.zg(zg[1]),
.zw(zw[1]),
.zz(zz[1])
);
wire [0:15] kl;
wire zegar;
wire wre, rsa, rsb, rsc;
wire wic, wac, war, wir, wrs, wrz, wkb;
wire panel_store, panel_fetch, panel_load, panel_bin;
wire oprq, stop, start, work, mode, step, stop_n, cycle;
wire dcl;
wire [0:3] rotary_pos;
assign rotary_bus = {wre, rsc, rsb, rsa, wic, wac, war, wir, wrs, wrz, wkb};
pk #(
.TIMER_CYCLE_MS(8'd10),
.CLK_SYS_HZ(CLK_SYS_HZ)
) PK(
.clk_sys(clk_sys),
.hlt_n(hlt_n),
.off(off),
.work(work),
.stop(stop),
.start(start),
.mode(mode),
.stop_n(stop_n),
.p0(p0),
.kl(kl),
.dcl(dcl),
.step(step),
.fetch(panel_fetch),
.store(panel_store),
.cycle(cycle),
.load(panel_load),
.bin(panel_bin),
.oprq(oprq),
.zegar(zegar),
.p(p),
.mc_0(mc_0),
.alarm(awaria),
._wait(_wait),
.irq(irq),
.q(q),
.run(run),
.wre(wre),
.rsa(rsa),
.rsb(rsb),
.rsc(rsc),
.wic(wic),
.wac(wac),
.war(war),
.wir(wir),
.wrs(wrs),
.wrz(wrz),
.wkb(wkb),
.indicators(indicators),
.rotary_pos(rotary_pos),
.rotary_in(rotary_out),
.rotary_trig(rotary_trig),
.keys(keys),
.keys_trig(keys_trig),
.fn(fn),
.fn_v(fn_v),
.fn_trig(fn_trig)
);
wire [0:`BUS_MAX] iobd;
wire [0:3] rotary_out;
wire rotary_trig;
wire [0:15] keys;
wire keys_trig;
wire [0:3] fn;
wire fn_v;
wire fn_trig;
iobus #(
.CLK_UART_HZ(CLK_UART_HZ),
.UART_BAUD(1_000_000)
) IOBUS(
.clk_sys(clk_sys),
.clk_uart(clk_uart),
.rxd(rxd),
.txd(txd),
.zg(zg[4]),
.zw(zw[4]),
.dpa(iobd[`pa]),
.rcl(iobr[`cl]),
.dw(iobd[`w]),
.dr(iobd[`r]),
.rs(iobr[`s]),
.rf(iobr[`f]),
.din(iobd[`in]),
.rok(iobr[`ok]),
.dok(iobd[`ok]),
.den(iobd[`en]),
.dpe(iobd[`pe]),
.rpe(iobr[`pe]),
.rqb(iobr[`qb]),
.rpn(iobr[`pn]),
.dpn(iobd[`pn]),
.rnb(iobr[`nb]),
.dnb(iobd[`nb]),
.rad(iobr[`ad]),
.dad(iobd[`ad]),
.rdt(iobr[`dt]),
.ddt(iobd[`dt]),
.w(w),
.rotary_pos(rotary_pos),
.indicators(indicators),
.rotary_out(rotary_out),
.rotary_trig(rotary_trig),
.keys(keys),
.keys_trig(keys_trig),
.fn(fn),
.fn_v(fn_v),
.fn_trig(fn_trig)
);
wire [0:`BUS_MAX] memd;
mem_elwro_sram MEM(
.clk(clk_ram),
.ram_ce(ram_ce),
.ram_oe(ram_oe),
.ram_we(ram_we),
.ram_a(ram_a),
.ram_d(ram_d),
.reset(memr[`cl]),
.reset_hold(memd[`cl]),
.nb(memr[`nb]),
.ad(memr[`ad]),
.rdt(memr[`dt]),
.ddt(memd[`dt]),
.w(memr[`w]),
.r(memr[`r]),
.s(memr[`s]),
.ok(memd[`ok])
);
wire off, pout, pon, clo, clm;
puks PUKS(
.clk_sys(clk_sys),
.rcl(cpu0r[`cl]),
.dcl(dcl),
.off(off),
.pout(pout),
.pon(pon),
.clo(clo),
.clm(clm)
);
endmodule | module mera400f(
input clk_ext,
input rxd,
output txd,
output ram_ce, ram_oe, ram_we,
output [17:0] ram_a,
inout [15:0] ram_d,
output [0:15] w,
output [10:0] rotary_bus,
output [0:9] indicators
); |
parameter CLK_EXT_HZ;
localparam CLK_SYS_HZ = CLK_EXT_HZ;
localparam CLK_UART_HZ = CLK_EXT_HZ;
wire clk_sys = clk_ext;
wire clk_uart = clk_ext;
wire clk_ram = clk_ext;
`define pa 0
`define cl 1
`define w 2
`define r 3
`define s 4
`define f 5
`define in 6
`define ok 7
`define en 8
`define pe 9
`define qb 10
`define pn 11
`define nb 12:15
`define ad 16:31
`define dt 32:47
`define BUS_MAX 47
wire [0:`BUS_MAX] cpu0r;
wire [0:`BUS_MAX] cpu1r;
wire [0:`BUS_MAX] memr;
wire [0:`BUS_MAX] iobr;
wire [1:4] zg;
wire [1:4] zw;
wire [1:4] zz;
isk ISK(
.clk_sys(clk_sys),
.cpu0d(cpu0d),
.cpu0r(cpu0r),
.cpu1d(48'd0),
.cpu1r(cpu1r),
.iobd(iobd),
.iobr(iobr),
.memd(memd),
.memr(memr),
.zg(zg),
.zw(zw),
.zz(zz)
);
wire [0:`BUS_MAX] cpu0d;
wire dmcl;
assign cpu0d[`cl] = dcl | dmcl;
wire p0;
wire hlt_n, p, run, _wait, irq, q, mc_0, awaria;
cpu #(
.CPU_NUMBER(1'b0),
.AWP_PRESENT(1'b1),
.INOU_USER_ILLEGAL(1'b1),
.STOP_ON_NOMEM(1'b1),
.LOW_MEM_WRITE_DENY(1'b0),
.ALARM_DLY_TICKS(23'd5_000_000),
.ALARM_TICKS(8'd3)
) CPU0(
.clk_sys(clk_sys),
.off(off),
.pon(pon),
.pout(pout),
.clm(clm),
.clo(clo),
.kl(kl),
.panel_store(panel_store),
.panel_fetch(panel_fetch),
.panel_load(panel_load),
.panel_bin(panel_bin),
.oprq(oprq),
.stop(stop),
.start(start),
.work(work),
.mode(mode),
.step(step),
.stop_n(stop_n),
.cycle(cycle),
.wre(wre),
.rsa(rsa),
.rsb(rsb),
.rsc(rsc),
.wic(wic),
.wac(wac),
.war(war),
.wir(wir),
.wrs(wrs),
.wrz(wrz),
.wkb(wkb),
.zegar(zegar),
.p0(p0),
.w(w),
.hlt_n(hlt_n),
.p(p),
.run(run),
._wait(_wait),
.irq(irq),
.q(q),
.mc_0(mc_0),
.awaria(awaria),
.dmcl(dmcl),
.dw(cpu0d[`w]),
.dr(cpu0d[`r]),
.ds(cpu0d[`s]),
.df(cpu0d[`f]),
.din(cpu0d[`in]),
.dok(cpu0d[`ok]),
.dqb(cpu0d[`qb]),
.dpn(cpu0d[`pn]),
.dnb(cpu0d[`nb]),
.dad(cpu0d[`ad]),
.ddt(cpu0d[`dt]),
.rpa(cpu0r[`pa]),
.rin(cpu0r[`in]),
.rok(cpu0r[`ok]),
.ren(cpu0r[`en]),
.rpe(cpu0r[`pe]),
.rpn(cpu0r[`pn]),
.rdt(cpu0r[`dt]),
.zg(zg[1]),
.zw(zw[1]),
.zz(zz[1])
);
wire [0:15] kl;
wire zegar;
wire wre, rsa, rsb, rsc;
wire wic, wac, war, wir, wrs, wrz, wkb;
wire panel_store, panel_fetch, panel_load, panel_bin;
wire oprq, stop, start, work, mode, step, stop_n, cycle;
wire dcl;
wire [0:3] rotary_pos;
assign rotary_bus = {wre, rsc, rsb, rsa, wic, wac, war, wir, wrs, wrz, wkb};
pk #(
.TIMER_CYCLE_MS(8'd10),
.CLK_SYS_HZ(CLK_SYS_HZ)
) PK(
.clk_sys(clk_sys),
.hlt_n(hlt_n),
.off(off),
.work(work),
.stop(stop),
.start(start),
.mode(mode),
.stop_n(stop_n),
.p0(p0),
.kl(kl),
.dcl(dcl),
.step(step),
.fetch(panel_fetch),
.store(panel_store),
.cycle(cycle),
.load(panel_load),
.bin(panel_bin),
.oprq(oprq),
.zegar(zegar),
.p(p),
.mc_0(mc_0),
.alarm(awaria),
._wait(_wait),
.irq(irq),
.q(q),
.run(run),
.wre(wre),
.rsa(rsa),
.rsb(rsb),
.rsc(rsc),
.wic(wic),
.wac(wac),
.war(war),
.wir(wir),
.wrs(wrs),
.wrz(wrz),
.wkb(wkb),
.indicators(indicators),
.rotary_pos(rotary_pos),
.rotary_in(rotary_out),
.rotary_trig(rotary_trig),
.keys(keys),
.keys_trig(keys_trig),
.fn(fn),
.fn_v(fn_v),
.fn_trig(fn_trig)
);
wire [0:`BUS_MAX] iobd;
wire [0:3] rotary_out;
wire rotary_trig;
wire [0:15] keys;
wire keys_trig;
wire [0:3] fn;
wire fn_v;
wire fn_trig;
iobus #(
.CLK_UART_HZ(CLK_UART_HZ),
.UART_BAUD(1_000_000)
) IOBUS(
.clk_sys(clk_sys),
.clk_uart(clk_uart),
.rxd(rxd),
.txd(txd),
.zg(zg[4]),
.zw(zw[4]),
.dpa(iobd[`pa]),
.rcl(iobr[`cl]),
.dw(iobd[`w]),
.dr(iobd[`r]),
.rs(iobr[`s]),
.rf(iobr[`f]),
.din(iobd[`in]),
.rok(iobr[`ok]),
.dok(iobd[`ok]),
.den(iobd[`en]),
.dpe(iobd[`pe]),
.rpe(iobr[`pe]),
.rqb(iobr[`qb]),
.rpn(iobr[`pn]),
.dpn(iobd[`pn]),
.rnb(iobr[`nb]),
.dnb(iobd[`nb]),
.rad(iobr[`ad]),
.dad(iobd[`ad]),
.rdt(iobr[`dt]),
.ddt(iobd[`dt]),
.w(w),
.rotary_pos(rotary_pos),
.indicators(indicators),
.rotary_out(rotary_out),
.rotary_trig(rotary_trig),
.keys(keys),
.keys_trig(keys_trig),
.fn(fn),
.fn_v(fn_v),
.fn_trig(fn_trig)
);
wire [0:`BUS_MAX] memd;
mem_elwro_sram MEM(
.clk(clk_ram),
.ram_ce(ram_ce),
.ram_oe(ram_oe),
.ram_we(ram_we),
.ram_a(ram_a),
.ram_d(ram_d),
.reset(memr[`cl]),
.reset_hold(memd[`cl]),
.nb(memr[`nb]),
.ad(memr[`ad]),
.rdt(memr[`dt]),
.ddt(memd[`dt]),
.w(memr[`w]),
.r(memr[`r]),
.s(memr[`s]),
.ok(memd[`ok])
);
wire off, pout, pon, clo, clm;
puks PUKS(
.clk_sys(clk_sys),
.rcl(cpu0r[`cl]),
.dcl(dcl),
.off(off),
.pout(pout),
.pon(pon),
.clo(clo),
.clm(clm)
);
endmodule | 24 |
139,101 | data/full_repos/permissive/86722304/src/msg_tx.v | 86,722,304 | msg_tx.v | v | 120 | 76 | [] | [] | [] | [(1, 117)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/msg_tx.v:5: Little bit endian vector: MSB < LSB of bit range: 0:7\n output [0:7] uart_data,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/msg_tx.v:9: Little bit endian vector: MSB < LSB of bit range: 0:2\n input [0:2] trig,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/msg_tx.v:10: Little bit endian vector: MSB < LSB of bit range: 0:2\n output [0:2] ena,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/msg_tx.v:12: Little bit endian vector: MSB < LSB of bit range: 0:7\n input [0:7] cmd,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/msg_tx.v:13: Little bit endian vector: MSB < LSB of bit range: 0:7\n input [0:7] a1,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/msg_tx.v:14: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] a2,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/msg_tx.v:15: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] a3\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/msg_tx.v:29: Little bit endian vector: MSB < LSB of bit range: 0:2\n reg [0:2] state = IDLE;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/msg_tx.v:31: Little bit endian vector: MSB < LSB of bit range: 1:3\n reg [1:3] a;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/msg_tx.v:32: Little bit endian vector: MSB < LSB of bit range: 0:7\n reg [0:7] ia1;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/msg_tx.v:33: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] ia2;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/msg_tx.v:34: Little bit endian vector: MSB < LSB of bit range: 0:15\n reg [0:15] ia3;\n ^\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/msg_tx.v:38: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'uart_send\'\n : ... In instance msg_tx\n uart_send <= 0;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/msg_tx.v:56: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'uart_data\'\n : ... In instance msg_tx\n uart_data <= cmd;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/msg_tx.v:57: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'uart_send\'\n : ... In instance msg_tx\n uart_send <= 1;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/msg_tx.v:66: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'uart_data\'\n : ... In instance msg_tx\n uart_data <= ia1;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/msg_tx.v:67: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'uart_send\'\n : ... In instance msg_tx\n uart_send <= 1;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/msg_tx.v:76: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'uart_data\'\n : ... In instance msg_tx\n uart_data <= ia2[0:7];\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/msg_tx.v:77: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'uart_send\'\n : ... In instance msg_tx\n uart_send <= 1;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/msg_tx.v:84: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'uart_data\'\n : ... In instance msg_tx\n uart_data <= ia2[8:15];\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/msg_tx.v:85: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'uart_send\'\n : ... In instance msg_tx\n uart_send <= 1;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/msg_tx.v:93: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'uart_data\'\n : ... In instance msg_tx\n uart_data <= ia3[0:7];\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/msg_tx.v:94: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'uart_send\'\n : ... In instance msg_tx\n uart_send <= 1;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/msg_tx.v:101: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'uart_data\'\n : ... In instance msg_tx\n uart_data <= ia3[8:15];\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/msg_tx.v:102: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'uart_send\'\n : ... In instance msg_tx\n uart_send <= 1;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/msg_tx.v:109: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'ena\'\n : ... In instance msg_tx\n ena <= 3\'d0;\n ^~~\n%Error: Exiting due to 14 error(s), 12 warning(s)\n' | 304,317 | module | module msg_tx(
input clk_sys,
output [0:7] uart_data,
output uart_send,
input uart_ready,
input [0:2] trig,
output [0:2] ena,
input [0:7] cmd,
input [0:7] a1,
input [0:15] a2,
input [0:15] a3
);
localparam IDLE = 3'd0;
localparam LOAD = 3'd1;
localparam A1 = 3'd2;
localparam A2H = 3'd3;
localparam A2L = 3'd4;
localparam A3H = 3'd5;
localparam A3L = 3'd6;
localparam WAIT = 3'd7;
reg [0:2] state = IDLE;
reg [1:3] a;
reg [0:7] ia1;
reg [0:15] ia2;
reg [0:15] ia3;
always @ (posedge clk_sys) begin
uart_send <= 0;
case (state)
IDLE: begin
if (trig != 3'b0) begin
ena[0] <= trig[0];
ena[1] <= trig[1] & ~trig[0];
ena[2] <= trig[2] & ~trig[1] & ~trig[0];
state <= LOAD;
end
end
LOAD: begin
a <= cmd[5:7];
ia1 <= a1;
ia2 <= a2;
ia3 <= a3;
uart_data <= cmd;
uart_send <= 1;
if (cmd[5]) state <= A1;
else if (cmd[6]) state <= A2H;
else if (cmd[7]) state <= A3H;
else state <= WAIT;
end
A1: begin
if (uart_ready) begin
uart_data <= ia1;
uart_send <= 1;
if (a[2]) state <= A2H;
else if (a[3]) state <= A3H;
else state <= WAIT;
end
end
A2H: begin
if (uart_ready) begin
uart_data <= ia2[0:7];
uart_send <= 1;
state <= A2L;
end
end
A2L: begin
if (uart_ready) begin
uart_data <= ia2[8:15];
uart_send <= 1;
if (a[3]) state <= A3H;
else state <= WAIT;
end
end
A3H: begin
if (uart_ready) begin
uart_data <= ia3[0:7];
uart_send <= 1;
state <= A3L;
end
end
A3L: begin
if (uart_ready) begin
uart_data <= ia3[8:15];
uart_send <= 1;
state <= WAIT;
end
end
WAIT: begin
if (uart_ready) begin
ena <= 3'd0;
state <= IDLE;
end
end
endcase
end
endmodule | module msg_tx(
input clk_sys,
output [0:7] uart_data,
output uart_send,
input uart_ready,
input [0:2] trig,
output [0:2] ena,
input [0:7] cmd,
input [0:7] a1,
input [0:15] a2,
input [0:15] a3
); |
localparam IDLE = 3'd0;
localparam LOAD = 3'd1;
localparam A1 = 3'd2;
localparam A2H = 3'd3;
localparam A2L = 3'd4;
localparam A3H = 3'd5;
localparam A3L = 3'd6;
localparam WAIT = 3'd7;
reg [0:2] state = IDLE;
reg [1:3] a;
reg [0:7] ia1;
reg [0:15] ia2;
reg [0:15] ia3;
always @ (posedge clk_sys) begin
uart_send <= 0;
case (state)
IDLE: begin
if (trig != 3'b0) begin
ena[0] <= trig[0];
ena[1] <= trig[1] & ~trig[0];
ena[2] <= trig[2] & ~trig[1] & ~trig[0];
state <= LOAD;
end
end
LOAD: begin
a <= cmd[5:7];
ia1 <= a1;
ia2 <= a2;
ia3 <= a3;
uart_data <= cmd;
uart_send <= 1;
if (cmd[5]) state <= A1;
else if (cmd[6]) state <= A2H;
else if (cmd[7]) state <= A3H;
else state <= WAIT;
end
A1: begin
if (uart_ready) begin
uart_data <= ia1;
uart_send <= 1;
if (a[2]) state <= A2H;
else if (a[3]) state <= A3H;
else state <= WAIT;
end
end
A2H: begin
if (uart_ready) begin
uart_data <= ia2[0:7];
uart_send <= 1;
state <= A2L;
end
end
A2L: begin
if (uart_ready) begin
uart_data <= ia2[8:15];
uart_send <= 1;
if (a[3]) state <= A3H;
else state <= WAIT;
end
end
A3H: begin
if (uart_ready) begin
uart_data <= ia3[0:7];
uart_send <= 1;
state <= A3L;
end
end
A3L: begin
if (uart_ready) begin
uart_data <= ia3[8:15];
uart_send <= 1;
state <= WAIT;
end
end
WAIT: begin
if (uart_ready) begin
ena <= 3'd0;
state <= IDLE;
end
end
endcase
end
endmodule | 24 |
139,105 | data/full_repos/permissive/86722304/src/platform.v | 86,722,304 | platform.v | v | 73 | 75 | [] | [] | [] | null | line:46: before: "word" | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/platform.v:21: Little bit endian vector: MSB < LSB of bit range: 0:15\n wire [0:15] w;\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/platform.v:23: Little bit endian vector: MSB < LSB of bit range: 0:9\n wire [0:9] indicators;\n ^\n%Error: data/full_repos/permissive/86722304/src/platform.v:25: Cannot find file containing module: \'mera400f\'\n mera400f #(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86722304/src,data/full_repos/permissive/86722304/mera400f\n data/full_repos/permissive/86722304/src,data/full_repos/permissive/86722304/mera400f.v\n data/full_repos/permissive/86722304/src,data/full_repos/permissive/86722304/mera400f.sv\n mera400f\n mera400f.v\n mera400f.sv\n obj_dir/mera400f\n obj_dir/mera400f.v\n obj_dir/mera400f.sv\n%Error: data/full_repos/permissive/86722304/src/platform.v:61: Cannot find file containing module: \'display\'\n display DISPLAY(\n ^~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 304,321 | module | module platform(
input CLK_EXT,
output BUZZER_,
input RXD,
output TXD,
output [7:0] DIG,
output [7:0] SEG,
output SRAM_CE_, SRAM_OE_, SRAM_WE_, SRAM_UB_, SRAM_LB_,
output [17:0] SRAM_A,
inout [15:0] SRAM_D,
output F_CS_, F_OE_, F_WE_
);
localparam CLK_EXT_HZ = 50_000_000;
wire sram_ce, sram_oe, sram_we;
wire [0:15] w;
wire [10:0] rotary_bus;
wire [0:9] indicators;
mera400f #(
.CLK_EXT_HZ(CLK_EXT_HZ)
) MERA400F (
.clk_ext(CLK_EXT),
.rxd(RXD),
.txd(TXD),
.ram_ce(sram_ce),
.ram_oe(sram_oe),
.ram_we(sram_we),
.ram_a(SRAM_A),
.ram_d(SRAM_D),
.w(w),
.rotary_bus(rotary_bus),
.indicators(indicators)
);
assign BUZZER_ = 1'b1;
assign F_CS_ = 1'b1;
assign F_OE_ = 1'b1;
assign F_WE_ = 1'b1;
assign SRAM_LB_ = 1'b0;
assign SRAM_UB_ = 1'b0;
assign SRAM_CE_ = ~sram_ce;
assign SRAM_OE_ = ~sram_oe;
assign SRAM_WE_ = ~sram_we;
display DISPLAY(
.clk_sys(CLK_EXT),
.w(w),
.rotary_bus(rotary_bus),
.indicators(indicators),
.seg(SEG),
.dig(DIG)
);
endmodule | module platform(
input CLK_EXT,
output BUZZER_,
input RXD,
output TXD,
output [7:0] DIG,
output [7:0] SEG,
output SRAM_CE_, SRAM_OE_, SRAM_WE_, SRAM_UB_, SRAM_LB_,
output [17:0] SRAM_A,
inout [15:0] SRAM_D,
output F_CS_, F_OE_, F_WE_
); |
localparam CLK_EXT_HZ = 50_000_000;
wire sram_ce, sram_oe, sram_we;
wire [0:15] w;
wire [10:0] rotary_bus;
wire [0:9] indicators;
mera400f #(
.CLK_EXT_HZ(CLK_EXT_HZ)
) MERA400F (
.clk_ext(CLK_EXT),
.rxd(RXD),
.txd(TXD),
.ram_ce(sram_ce),
.ram_oe(sram_oe),
.ram_we(sram_we),
.ram_a(SRAM_A),
.ram_d(SRAM_D),
.w(w),
.rotary_bus(rotary_bus),
.indicators(indicators)
);
assign BUZZER_ = 1'b1;
assign F_CS_ = 1'b1;
assign F_OE_ = 1'b1;
assign F_WE_ = 1'b1;
assign SRAM_LB_ = 1'b0;
assign SRAM_UB_ = 1'b0;
assign SRAM_CE_ = ~sram_ce;
assign SRAM_OE_ = ~sram_oe;
assign SRAM_WE_ = ~sram_we;
display DISPLAY(
.clk_sys(CLK_EXT),
.w(w),
.rotary_bus(rotary_bus),
.indicators(indicators),
.seg(SEG),
.dig(DIG)
);
endmodule | 24 |
139,106 | data/full_repos/permissive/86722304/src/pm.v | 86,722,304 | pm.v | v | 566 | 96 | [] | [] | [] | [(3, 563)] | null | null | 1: b'%Error: data/full_repos/permissive/86722304/src/pm.v:228: Cannot find file containing module: \'kcpc\'\n kcpc KCPC(\n ^~~~\n ... Looked in:\n data/full_repos/permissive/86722304/src,data/full_repos/permissive/86722304/kcpc\n data/full_repos/permissive/86722304/src,data/full_repos/permissive/86722304/kcpc.v\n data/full_repos/permissive/86722304/src,data/full_repos/permissive/86722304/kcpc.sv\n kcpc\n kcpc.v\n kcpc.sv\n obj_dir/kcpc\n obj_dir/kcpc.v\n obj_dir/kcpc.sv\n%Error: data/full_repos/permissive/86722304/src/pm.v:323: Cannot find file containing module: \'mc\'\n mc MC(\n ^~\n%Error: data/full_repos/permissive/86722304/src/pm.v:422: Cannot find file containing module: \'lg\'\n lg LG(\n ^~\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/pm.v:450: Little bit endian vector: MSB < LSB of bit range: 0:3\n wire [0:3] lk_in;\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/86722304/src/pm.v:457: Cannot find file containing module: \'lk\'\n lk CNT_LK(\n ^~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 304,322 | module | module pm(
input clk_sys,
input start,
input pon,
input work,
input hlt_n,
input stop,
input clo,
input hlt,
input cycle,
input irq,
output _wait,
output run,
input ekc_1,
input ekc_i,
input ekc_2,
input got,
input ekc_fp,
input clm,
input strob1,
input strob1b,
input strob2,
input strob2b,
input ldstate,
output sp0,
output przerw,
output si1,
output sp1,
input k2,
input panel_store,
input panel_fetch,
input panel_load,
input panel_bin,
input rdt9,
input rdt11,
input k1,
output laduj,
output k2_bin_store,
output k2fetch,
output w_rbc,
output w_rba,
output w_rbb,
input p0,
output ep0,
output stp0,
output ek2,
output ek1,
input j$,
input bcoc$,
input zs,
input p2,
input ssp$,
input sc$,
input md,
input xi,
output p,
output mc_3,
output mc_0,
output xi$,
input p4,
input b0,
input na,
input c0,
input ka2,
input ka1,
input p3,
input p1,
input nef,
input p5,
input i2,
output pp,
output ep5,
output ep4,
output ep3,
output ep1,
output ep2,
output icp1,
input exl,
input lipsp,
input gr,
input wx,
input shc,
input read_fp,
input ir7,
input inou,
input rok,
output arp1,
output lg_3,
output lg_0,
input rsc,
input ir10,
input lpb,
input ir11,
input rsb,
input ir12,
input rsa,
input lpa,
input rlp_fp,
output rc,
output rb,
output ra,
input bod,
input ir15,
input ir14,
input ir13,
input ir9,
input ir8,
output lk,
input rj,
input uj,
input lwlwt,
input sr,
input lac,
input lrcb,
input rpc,
input rc$,
input ng$,
input ls,
input oc,
input wa,
input wm,
input wz,
input ww,
input wr,
input wp,
output wls,
input ri,
input war,
input wre,
input i3,
input s_fp,
input sar$,
input lar$,
input in,
input bs,
input zb$,
output w_r,
input wic,
input i4,
input wac,
input i1,
output w_ic,
output w_ac,
output w_ar,
input wrz,
input wrs,
input mb,
input im,
input lj,
input lwrs,
input jkrb,
output lrz,
output w_bar,
output w_rm,
input we,
input ib,
input ir6,
input cb,
input i5,
input rb$,
input w$,
input i3_ex_przer,
output baa,
output bab,
output bac,
output aa,
output ab,
input at15,
input srez$,
input rz,
input wir,
input blw_pw,
output wpb,
output bwb,
output bwa,
output kia,
output kib,
output w_ir,
input ki,
input dt_w,
input f13,
input wkb,
output mwa,
output mwb,
output mwc
);
wire start_reset = hlt_n | stop | clo;
wire start_clk = pon & work;
reg startq;
always @ (posedge clk_sys, posedge start_reset) begin
if (start_reset) startq <= 1'b0;
else if (start_clk | start) startq <= 1'b1;
end
wire wait_reset = start_reset | si1;
always @ (posedge clk_sys, posedge wait_reset) begin
if (wait_reset) _wait <= 1'b0;
else if (wx) _wait <= hlt;
end
reg __cycle_q;
always @ (posedge clk_sys, posedge cycle) begin
if (cycle) __cycle_q <= 1'b1;
else if (rescyc) __cycle_q <= 1'b0;
end
assign run = startq & ~_wait;
wire stpc = dpr | dprzerw;
wire ekc = ekc_1 | ekc_i | ekc_2 | p2 | p0stpc;
wire kc_reset = clo | pc;
wire rescyc = clm | strob2 | si1;
wire dpr = run | __cycle_q;
wire dprzerw = (__cycle_q | startq) & irq & ~p & mc_0;
wire kc, pc;
wire pr;
kcpc KCPC(
.clk_sys(clk_sys),
.kc_reset(kc_reset),
.ekc(ekc),
.ekc_fp(ekc_fp),
.ldstate(ldstate),
.rescyc(rescyc),
.dpr(dpr),
.clm(clm),
.dprzerw(dprzerw),
.przerw(przerw),
.pr(pr),
.kc(kc),
.pc(pc)
);
assign sp0 = ~pr & ~przerw & pc;
assign si1 = pc & przerw;
assign sp1 = ~przerw & pr & pc;
wire zerstan = kc | clm | p0;
wire st2k2 = strob2 & k2;
wire bin, load;
reg fetch;
wire store;
always @ (posedge clk_sys, posedge panel_store) begin
if (panel_store) store <= 1'b1;
else if (clm | st2k2) store <= 1'b0;
end
always @ (posedge clk_sys, posedge panel_fetch) begin
if (panel_fetch) fetch <= 1'b1;
else if (clm | st2k2) fetch <= 1'b0;
end
always @ (posedge clk_sys, posedge panel_load) begin
if (panel_load) load <= 1'b1;
else if (clm | st2k2) load <= 1'b0;
end
wire bin_d = ~(rdt9 & rdt11 & lg_0);
wire s1k1 = strob1 & k1;
always @ (posedge clk_sys, posedge panel_bin) begin
if (panel_bin) bin <= 1'b1;
else if (clm) bin <= 1'b0;
else if (s1k1) bin <= bin_d;
end
assign laduj = load;
wire sfl = store | fetch | load;
wire ur = k2 & (load | fetch);
wire ar_1 = k2 & ~load;
wire k2store = k2 & store;
assign k2_bin_store = k2 & (store | bin);
assign k2fetch = k2 & fetch;
wire k1s1 = k1 & strob1;
assign w_rbc = k1s1 & lg_0;
assign w_rba = k1s1 & lg_2;
assign w_rbb = k1s1 & lg_1;
wire psr = p0 | k2store;
wire p0stpc = p0 & stpc;
wire p0_k2 = p0 | k2;
assign ep0 = (k2 | k1) & ~bin;
assign stp0 = bin | stpc | sfl;
assign ek2 = (p0 & sfl) | (bin & lg_3 & k1);
assign ek1 = (p0_k2 & bin) | (k1 & bin & ~lg_3);
wire lg_plus_1 = (bin & k2) | (k1 & rdt9);
always @ (posedge clk_sys, posedge clm) begin
if (clm) p <= 1'b0;
else if (strob1) begin
if (rok & ~inou & wm) p <= 1'b1;
else if (p2) p <= 1'b0;
else if (ssp$ & w$) p <= p_d;
end
end
wire p_d = (~j$ & bcoc$) | zs;
wire p_set = (p2 & strob1) | clm;
wire setwp = strob1 & wx & md;
wire reswp = p_set | (sc$ & strob2 & p1);
wire reset_mc = reswp | (~md & p4);
mc MC(
.clk_sys(clk_sys),
.inc(setwp),
.reset(reset_mc),
.mc_3(mc_3),
.mc_0(mc_0)
);
assign xi$ = ~p & p1 & strob2 & xi;
wire wm_d = pr & ~c0 & na;
reg wm_q;
always @ (posedge clk_sys) begin
if (strob1b) begin
if (~p & p1 & xi) wm_q <= 1'b0;
else wm_q <= wm_d;
end
end
wire wb_j = pr & ~b0 & na;
wire wb_k = (p4 & ~wpp) | p2;
reg wb;
always @ (posedge clk_sys, posedge zerstan) begin
if (zerstan) wb <= 1'b0;
else if (strob1b) begin
case ({wb_j, wb_k})
2'b00: wb <= wb;
2'b01: wb <= 1'b0;
2'b10: wb <= 1'b1;
2'b11: wb <= ~wb;
endcase
end
end
reg wpp;
always @ (posedge clk_sys, posedge reswp) begin
if (reswp) wpp <= 1'b0;
else if (strob1b) begin
if (wx & md) wpp <= 1'b1;
else if (p4) wpp <= 1'b0;
end
end
wire p4wp = p4 & wpp;
wire wpbmod = wb | wpp;
wire bla = p4 & ka1ir6 & ~wpp;
wire nair6 = na & ir6;
wire ka12x = (na & c0) | ka2 | ka1;
wire ka1ir6 = ka1 & ir6;
wire p3_p4 = p3 | p4;
wire p5_p4 = p5 | p4;
wire p1ef = p1 & ~nef;
wire p3ka1ir6 = p3 & ka1ir6;
wire wm_ka12x = wm_q | ka12x;
wire nair6_wpbmod = nair6 | wpbmod;
assign pp = p5 | (p3_p4 & ~nair6_wpbmod & ~p3ka1ir6) | (p1ef & ~nair6_wpbmod & ~wm_ka12x);
assign ep1 = p1ef & wm_q;
assign ep2 = p1 & nef;
assign ep3 = p1ef & ka12x;
assign ep4 = p3ka1ir6 | (p3_p4 & wpbmod) | (~wm_ka12x & p1ef & wpbmod);
assign ep5 = (p3_p4 & nair6 & ~wpbmod) | (nair6 & ~wm_ka12x & p1ef & ~wpbmod);
wire load_ac = p5_p4 | p1 | p3 | i2;
assign icp1 = (wm_q & p2) | p1 | ic_1;
wire lolk = slg2 | (strob2 & p1 & shc) | (strob1 & wm & inou);
wire downlk = strob1 & (wrwwgr | ((shc | inou) & wx));
wire wrwwgr = gr & wrww;
assign arp1 = ar_1 | read_fp | i3 | wrwwgr;
wire lg_p1 = strob1b & (i3 | wrwwgr | lg_plus_1);
wire lg_reset = zerstan | i1;
wire slg1 = strob2 & ~gr & p1 & ~exl & ~lipsp;
wire slg2 = strob1 & gr & wx;
wire lg_2, lg_1;
wire lga, lgb, lgc;
lg LG(
.clk_sys(clk_sys),
.cu(lg_p1),
.reset(lg_reset),
.gr(gr),
.slg1(slg1),
.slg2(slg2),
.ir({ir7, ir8, ir9}),
.lg_0(lg_0),
.lg_1(lg_1),
.lg_2(lg_2),
.lg_3(lg_3),
.lga(lga),
.lgb(lgb),
.lgc(lgc)
);
wire ic_1 = wx & inou;
wire okinou = inou & rok;
assign rc = _7_rkod | (p3 & ir13) | (p4 & ir10) | (p0_k2 & rsc) | (rlp_fp & 1'b0) | (w & lgc);
assign rb = _7_rkod | (p3 & ir14) | (p4 & ir11) | (p0_k2 & rsb) | (rlp_fp & lpb) | (w & lgb);
assign ra = _7_rkod | (p3 & ir15) | (p4 & ir12) | (p0_k2 & rsa) | (rlp_fp & lpa) | (w & lga);
wire [0:3] lk_in;
assign lk_in[3] = (shc & ir15) | (gr & (ir9 | ir8)) | (inou & bod);
assign lk_in[2] = (shc & ir14) | (gr) | okinou;
assign lk_in[1] = (shc & ir13) | (gr & (~ir9 & ir8));
assign lk_in[0] = (shc & ir6);
lk CNT_LK(
.clk_sys(clk_sys),
.cd(downlk),
.i(lk_in),
.l(lolk),
.r(zerstan),
.lk(lk)
);
wire ruj = rj | uj;
wire pac = rj | uj | lwlwt;
wire lwtsr = lwlwt | sr;
wire lrcblac = lac | lrcb;
wire pat = lrcb | sr;
wire rjcpc = rj | rpc | rc$;
wire lrcbngls$ = lrcb | ng$ | ls;
wire M95_10 = ~w$ & ls;
always @ (posedge clk_sys, negedge M95_10) begin
if (~M95_10) wls <= 1'b0;
else if (wa & strob1) wls <= 1'b1;
end
wire M24_8 = ~oc & ~bs & w$;
wire M36_3 = ~ls & we;
wire w = wa | M24_8 | M36_3 | wm | wz | ww | wr | wp;
wire wrww = wr | ww;
wire warx = (p1 & ~wpp) | (~wpp & p3) | (ri & wa) | (war & ur);
wire w_r_1 = (ur & wre) | (lipsp & lg_1 & i3) | (lwtsr & wp) | (wa & rjcpc);
wire w_r_2 = (wr & sar$) | (zb$ & we) | (lar$ & w$) | (wm & in & rok);
assign w_r = w_r_1 | s_fp | w_r_2;
wire _7_rkod = (w$ & bs) | (ls & we);
wire bs_wls = bs | wls;
wire wrinou = inou & wr;
assign w_ic = (lg_0 & lipsp & i3) | (ljkrb & we) | (wp & ruj) | (ur & wic) | wrinou | i4;
assign w_ac = (bs_wls & we) | (ur & wac) | (wa & lrcbngls$) | (wr & lrcblac) | load_ac;
assign w_ar = (~wls & ls & we) | (we & lwrs) | (wp & lrcb) | warx | i1 | p5_p4;
assign lrz = ur & wrz;
wire wrsz = wrz ^ wrs;
assign w_bar = (wrs & ur) | (mb & wr) | (i3 & lipsp & lg_2);
assign w_rm = (wrs & ur) | (wr & im) | (lg_2 & lipsp & i3);
wire abx = (psr & wic) | (wa & rj) | (we & (lwrs | jkrb)) | (lj & ww);
wire ljkrb = lj | jkrb;
wire ib_ng = ib | ng$;
wire cb_oc = cb | oc;
wire M9_6 = (zb$ & ir6) ^ lj;
wire M9_3 = (zb$ & ~ir6) ^ lj;
wire M67_8 = (we & M9_6) | (w$ & ib_ng);
wire M72_8 = (ib_ng & w$) | (cb_oc & w$) | (we & M9_3) | (~na & p3);
wire M71_8 = (w$ & ls) | (psr & war);
wire M89_4 = ~wpb & rb$;
wire M71_6 = (~na & p3) | (w$ & M89_4);
wire M10_4 = ~ir6 & rc$;
wire M55_8 = (M10_4 & wa) | (lg_0 & i3_ex_przer);
assign baa = bla | M67_8;
assign bab = bla | M67_8 | (ka1 & p3);
assign bac = bla | M72_8;
assign aa = M71_6 | i5 | p4wp | M71_8;
assign ab = M71_6 | M55_8 | abx;
wire str1wx = strob1b & wx;
reg WPB;
assign wpb = WPB;
always @ (posedge clk_sys, negedge lrcb) begin
if (~lrcb) WPB <= 1'b0;
else if (str1wx) WPB <= at15;
end
assign w_ir = (wir & ur) | pr;
assign kia = f13 | (psr & wrs) | i3_ex_przer;
assign kib = f13 | bin;
wire bw = blw_pw | (ww & rz);
assign bwa = bw;
assign bwb = bw | (cb & wpb & wr);
wire wirpsr = wir & psr;
wire mwax = (i3_ex_przer & lg_3) | (wp & pac) | (ri & ww) | (wac & psr);
wire mwbx = (pat & wp) | (srez$ & ww);
wire M56_8 = (wrsz & psr) | (i3_ex_przer & lg_2) | (bin & k2) | (ww & ki);
wire M73_8 = (k2 & load) | (psr & wkb) | (ir6 & wa & rc$);
assign mwa = wirpsr | mwax | M56_8 | f13 | dt_w;
assign mwb = wirpsr | mwbx | M56_8 | f13 | we | w$ | p4 | M73_8;
assign mwc = wirpsr | dt_w | M73_8 | (wa & lrcb);
endmodule | module pm(
input clk_sys,
input start,
input pon,
input work,
input hlt_n,
input stop,
input clo,
input hlt,
input cycle,
input irq,
output _wait,
output run,
input ekc_1,
input ekc_i,
input ekc_2,
input got,
input ekc_fp,
input clm,
input strob1,
input strob1b,
input strob2,
input strob2b,
input ldstate,
output sp0,
output przerw,
output si1,
output sp1,
input k2,
input panel_store,
input panel_fetch,
input panel_load,
input panel_bin,
input rdt9,
input rdt11,
input k1,
output laduj,
output k2_bin_store,
output k2fetch,
output w_rbc,
output w_rba,
output w_rbb,
input p0,
output ep0,
output stp0,
output ek2,
output ek1,
input j$,
input bcoc$,
input zs,
input p2,
input ssp$,
input sc$,
input md,
input xi,
output p,
output mc_3,
output mc_0,
output xi$,
input p4,
input b0,
input na,
input c0,
input ka2,
input ka1,
input p3,
input p1,
input nef,
input p5,
input i2,
output pp,
output ep5,
output ep4,
output ep3,
output ep1,
output ep2,
output icp1,
input exl,
input lipsp,
input gr,
input wx,
input shc,
input read_fp,
input ir7,
input inou,
input rok,
output arp1,
output lg_3,
output lg_0,
input rsc,
input ir10,
input lpb,
input ir11,
input rsb,
input ir12,
input rsa,
input lpa,
input rlp_fp,
output rc,
output rb,
output ra,
input bod,
input ir15,
input ir14,
input ir13,
input ir9,
input ir8,
output lk,
input rj,
input uj,
input lwlwt,
input sr,
input lac,
input lrcb,
input rpc,
input rc$,
input ng$,
input ls,
input oc,
input wa,
input wm,
input wz,
input ww,
input wr,
input wp,
output wls,
input ri,
input war,
input wre,
input i3,
input s_fp,
input sar$,
input lar$,
input in,
input bs,
input zb$,
output w_r,
input wic,
input i4,
input wac,
input i1,
output w_ic,
output w_ac,
output w_ar,
input wrz,
input wrs,
input mb,
input im,
input lj,
input lwrs,
input jkrb,
output lrz,
output w_bar,
output w_rm,
input we,
input ib,
input ir6,
input cb,
input i5,
input rb$,
input w$,
input i3_ex_przer,
output baa,
output bab,
output bac,
output aa,
output ab,
input at15,
input srez$,
input rz,
input wir,
input blw_pw,
output wpb,
output bwb,
output bwa,
output kia,
output kib,
output w_ir,
input ki,
input dt_w,
input f13,
input wkb,
output mwa,
output mwb,
output mwc
); |
wire start_reset = hlt_n | stop | clo;
wire start_clk = pon & work;
reg startq;
always @ (posedge clk_sys, posedge start_reset) begin
if (start_reset) startq <= 1'b0;
else if (start_clk | start) startq <= 1'b1;
end
wire wait_reset = start_reset | si1;
always @ (posedge clk_sys, posedge wait_reset) begin
if (wait_reset) _wait <= 1'b0;
else if (wx) _wait <= hlt;
end
reg __cycle_q;
always @ (posedge clk_sys, posedge cycle) begin
if (cycle) __cycle_q <= 1'b1;
else if (rescyc) __cycle_q <= 1'b0;
end
assign run = startq & ~_wait;
wire stpc = dpr | dprzerw;
wire ekc = ekc_1 | ekc_i | ekc_2 | p2 | p0stpc;
wire kc_reset = clo | pc;
wire rescyc = clm | strob2 | si1;
wire dpr = run | __cycle_q;
wire dprzerw = (__cycle_q | startq) & irq & ~p & mc_0;
wire kc, pc;
wire pr;
kcpc KCPC(
.clk_sys(clk_sys),
.kc_reset(kc_reset),
.ekc(ekc),
.ekc_fp(ekc_fp),
.ldstate(ldstate),
.rescyc(rescyc),
.dpr(dpr),
.clm(clm),
.dprzerw(dprzerw),
.przerw(przerw),
.pr(pr),
.kc(kc),
.pc(pc)
);
assign sp0 = ~pr & ~przerw & pc;
assign si1 = pc & przerw;
assign sp1 = ~przerw & pr & pc;
wire zerstan = kc | clm | p0;
wire st2k2 = strob2 & k2;
wire bin, load;
reg fetch;
wire store;
always @ (posedge clk_sys, posedge panel_store) begin
if (panel_store) store <= 1'b1;
else if (clm | st2k2) store <= 1'b0;
end
always @ (posedge clk_sys, posedge panel_fetch) begin
if (panel_fetch) fetch <= 1'b1;
else if (clm | st2k2) fetch <= 1'b0;
end
always @ (posedge clk_sys, posedge panel_load) begin
if (panel_load) load <= 1'b1;
else if (clm | st2k2) load <= 1'b0;
end
wire bin_d = ~(rdt9 & rdt11 & lg_0);
wire s1k1 = strob1 & k1;
always @ (posedge clk_sys, posedge panel_bin) begin
if (panel_bin) bin <= 1'b1;
else if (clm) bin <= 1'b0;
else if (s1k1) bin <= bin_d;
end
assign laduj = load;
wire sfl = store | fetch | load;
wire ur = k2 & (load | fetch);
wire ar_1 = k2 & ~load;
wire k2store = k2 & store;
assign k2_bin_store = k2 & (store | bin);
assign k2fetch = k2 & fetch;
wire k1s1 = k1 & strob1;
assign w_rbc = k1s1 & lg_0;
assign w_rba = k1s1 & lg_2;
assign w_rbb = k1s1 & lg_1;
wire psr = p0 | k2store;
wire p0stpc = p0 & stpc;
wire p0_k2 = p0 | k2;
assign ep0 = (k2 | k1) & ~bin;
assign stp0 = bin | stpc | sfl;
assign ek2 = (p0 & sfl) | (bin & lg_3 & k1);
assign ek1 = (p0_k2 & bin) | (k1 & bin & ~lg_3);
wire lg_plus_1 = (bin & k2) | (k1 & rdt9);
always @ (posedge clk_sys, posedge clm) begin
if (clm) p <= 1'b0;
else if (strob1) begin
if (rok & ~inou & wm) p <= 1'b1;
else if (p2) p <= 1'b0;
else if (ssp$ & w$) p <= p_d;
end
end
wire p_d = (~j$ & bcoc$) | zs;
wire p_set = (p2 & strob1) | clm;
wire setwp = strob1 & wx & md;
wire reswp = p_set | (sc$ & strob2 & p1);
wire reset_mc = reswp | (~md & p4);
mc MC(
.clk_sys(clk_sys),
.inc(setwp),
.reset(reset_mc),
.mc_3(mc_3),
.mc_0(mc_0)
);
assign xi$ = ~p & p1 & strob2 & xi;
wire wm_d = pr & ~c0 & na;
reg wm_q;
always @ (posedge clk_sys) begin
if (strob1b) begin
if (~p & p1 & xi) wm_q <= 1'b0;
else wm_q <= wm_d;
end
end
wire wb_j = pr & ~b0 & na;
wire wb_k = (p4 & ~wpp) | p2;
reg wb;
always @ (posedge clk_sys, posedge zerstan) begin
if (zerstan) wb <= 1'b0;
else if (strob1b) begin
case ({wb_j, wb_k})
2'b00: wb <= wb;
2'b01: wb <= 1'b0;
2'b10: wb <= 1'b1;
2'b11: wb <= ~wb;
endcase
end
end
reg wpp;
always @ (posedge clk_sys, posedge reswp) begin
if (reswp) wpp <= 1'b0;
else if (strob1b) begin
if (wx & md) wpp <= 1'b1;
else if (p4) wpp <= 1'b0;
end
end
wire p4wp = p4 & wpp;
wire wpbmod = wb | wpp;
wire bla = p4 & ka1ir6 & ~wpp;
wire nair6 = na & ir6;
wire ka12x = (na & c0) | ka2 | ka1;
wire ka1ir6 = ka1 & ir6;
wire p3_p4 = p3 | p4;
wire p5_p4 = p5 | p4;
wire p1ef = p1 & ~nef;
wire p3ka1ir6 = p3 & ka1ir6;
wire wm_ka12x = wm_q | ka12x;
wire nair6_wpbmod = nair6 | wpbmod;
assign pp = p5 | (p3_p4 & ~nair6_wpbmod & ~p3ka1ir6) | (p1ef & ~nair6_wpbmod & ~wm_ka12x);
assign ep1 = p1ef & wm_q;
assign ep2 = p1 & nef;
assign ep3 = p1ef & ka12x;
assign ep4 = p3ka1ir6 | (p3_p4 & wpbmod) | (~wm_ka12x & p1ef & wpbmod);
assign ep5 = (p3_p4 & nair6 & ~wpbmod) | (nair6 & ~wm_ka12x & p1ef & ~wpbmod);
wire load_ac = p5_p4 | p1 | p3 | i2;
assign icp1 = (wm_q & p2) | p1 | ic_1;
wire lolk = slg2 | (strob2 & p1 & shc) | (strob1 & wm & inou);
wire downlk = strob1 & (wrwwgr | ((shc | inou) & wx));
wire wrwwgr = gr & wrww;
assign arp1 = ar_1 | read_fp | i3 | wrwwgr;
wire lg_p1 = strob1b & (i3 | wrwwgr | lg_plus_1);
wire lg_reset = zerstan | i1;
wire slg1 = strob2 & ~gr & p1 & ~exl & ~lipsp;
wire slg2 = strob1 & gr & wx;
wire lg_2, lg_1;
wire lga, lgb, lgc;
lg LG(
.clk_sys(clk_sys),
.cu(lg_p1),
.reset(lg_reset),
.gr(gr),
.slg1(slg1),
.slg2(slg2),
.ir({ir7, ir8, ir9}),
.lg_0(lg_0),
.lg_1(lg_1),
.lg_2(lg_2),
.lg_3(lg_3),
.lga(lga),
.lgb(lgb),
.lgc(lgc)
);
wire ic_1 = wx & inou;
wire okinou = inou & rok;
assign rc = _7_rkod | (p3 & ir13) | (p4 & ir10) | (p0_k2 & rsc) | (rlp_fp & 1'b0) | (w & lgc);
assign rb = _7_rkod | (p3 & ir14) | (p4 & ir11) | (p0_k2 & rsb) | (rlp_fp & lpb) | (w & lgb);
assign ra = _7_rkod | (p3 & ir15) | (p4 & ir12) | (p0_k2 & rsa) | (rlp_fp & lpa) | (w & lga);
wire [0:3] lk_in;
assign lk_in[3] = (shc & ir15) | (gr & (ir9 | ir8)) | (inou & bod);
assign lk_in[2] = (shc & ir14) | (gr) | okinou;
assign lk_in[1] = (shc & ir13) | (gr & (~ir9 & ir8));
assign lk_in[0] = (shc & ir6);
lk CNT_LK(
.clk_sys(clk_sys),
.cd(downlk),
.i(lk_in),
.l(lolk),
.r(zerstan),
.lk(lk)
);
wire ruj = rj | uj;
wire pac = rj | uj | lwlwt;
wire lwtsr = lwlwt | sr;
wire lrcblac = lac | lrcb;
wire pat = lrcb | sr;
wire rjcpc = rj | rpc | rc$;
wire lrcbngls$ = lrcb | ng$ | ls;
wire M95_10 = ~w$ & ls;
always @ (posedge clk_sys, negedge M95_10) begin
if (~M95_10) wls <= 1'b0;
else if (wa & strob1) wls <= 1'b1;
end
wire M24_8 = ~oc & ~bs & w$;
wire M36_3 = ~ls & we;
wire w = wa | M24_8 | M36_3 | wm | wz | ww | wr | wp;
wire wrww = wr | ww;
wire warx = (p1 & ~wpp) | (~wpp & p3) | (ri & wa) | (war & ur);
wire w_r_1 = (ur & wre) | (lipsp & lg_1 & i3) | (lwtsr & wp) | (wa & rjcpc);
wire w_r_2 = (wr & sar$) | (zb$ & we) | (lar$ & w$) | (wm & in & rok);
assign w_r = w_r_1 | s_fp | w_r_2;
wire _7_rkod = (w$ & bs) | (ls & we);
wire bs_wls = bs | wls;
wire wrinou = inou & wr;
assign w_ic = (lg_0 & lipsp & i3) | (ljkrb & we) | (wp & ruj) | (ur & wic) | wrinou | i4;
assign w_ac = (bs_wls & we) | (ur & wac) | (wa & lrcbngls$) | (wr & lrcblac) | load_ac;
assign w_ar = (~wls & ls & we) | (we & lwrs) | (wp & lrcb) | warx | i1 | p5_p4;
assign lrz = ur & wrz;
wire wrsz = wrz ^ wrs;
assign w_bar = (wrs & ur) | (mb & wr) | (i3 & lipsp & lg_2);
assign w_rm = (wrs & ur) | (wr & im) | (lg_2 & lipsp & i3);
wire abx = (psr & wic) | (wa & rj) | (we & (lwrs | jkrb)) | (lj & ww);
wire ljkrb = lj | jkrb;
wire ib_ng = ib | ng$;
wire cb_oc = cb | oc;
wire M9_6 = (zb$ & ir6) ^ lj;
wire M9_3 = (zb$ & ~ir6) ^ lj;
wire M67_8 = (we & M9_6) | (w$ & ib_ng);
wire M72_8 = (ib_ng & w$) | (cb_oc & w$) | (we & M9_3) | (~na & p3);
wire M71_8 = (w$ & ls) | (psr & war);
wire M89_4 = ~wpb & rb$;
wire M71_6 = (~na & p3) | (w$ & M89_4);
wire M10_4 = ~ir6 & rc$;
wire M55_8 = (M10_4 & wa) | (lg_0 & i3_ex_przer);
assign baa = bla | M67_8;
assign bab = bla | M67_8 | (ka1 & p3);
assign bac = bla | M72_8;
assign aa = M71_6 | i5 | p4wp | M71_8;
assign ab = M71_6 | M55_8 | abx;
wire str1wx = strob1b & wx;
reg WPB;
assign wpb = WPB;
always @ (posedge clk_sys, negedge lrcb) begin
if (~lrcb) WPB <= 1'b0;
else if (str1wx) WPB <= at15;
end
assign w_ir = (wir & ur) | pr;
assign kia = f13 | (psr & wrs) | i3_ex_przer;
assign kib = f13 | bin;
wire bw = blw_pw | (ww & rz);
assign bwa = bw;
assign bwb = bw | (cb & wpb & wr);
wire wirpsr = wir & psr;
wire mwax = (i3_ex_przer & lg_3) | (wp & pac) | (ri & ww) | (wac & psr);
wire mwbx = (pat & wp) | (srez$ & ww);
wire M56_8 = (wrsz & psr) | (i3_ex_przer & lg_2) | (bin & k2) | (ww & ki);
wire M73_8 = (k2 & load) | (psr & wkb) | (ir6 & wa & rc$);
assign mwa = wirpsr | mwax | M56_8 | f13 | dt_w;
assign mwb = wirpsr | mwbx | M56_8 | f13 | we | w$ | p4 | M73_8;
assign mwc = wirpsr | dt_w | M73_8 | (wa & lrcb);
endmodule | 24 |
139,108 | data/full_repos/permissive/86722304/src/pr.v | 86,722,304 | pr.v | v | 184 | 108 | [] | [] | [] | null | line:62: before: ";" | null | 1: b"%Error: data/full_repos/permissive/86722304/src/pr.v:62: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'CPU_NUMBER'\n : ... In instance pr\n parameter CPU_NUMBER;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/pr.v:63: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'AWP_PRESENT'\n : ... In instance pr\n parameter AWP_PRESENT;\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 304,324 | module | module pr(
input clk_sys,
input blr,
input lpc,
input wa,
input rpc,
input ra,
input rb,
input rc,
input as2,
input w_r,
input strob1,
input strob1b,
input strob2,
input strob2b,
input [0:15] w,
output [0:15] l,
input bar_nb,
input w_rbb,
input w_rbc,
input w_rba,
output [0:3] dnb,
input rpn,
input bp_nb,
input pn_nb,
input q_nb,
input w_bar,
input zer_sp,
input clm,
input ustr0_fp,
input ust_leg,
input aryt,
input zs,
input carry,
input s_1,
output zgpn,
output dpn,
output dqb,
output q,
output zer,
input ust_z,
input ust_mc,
input s0,
input ust_v,
input _0_v,
output [0:8] r0,
input exy,
input ust_y,
input exx,
input ust_x,
input kia,
input kib,
input [0:15] bus_rz,
input [0:15] zp,
input [0:9] rs,
output [0:15] bus_ki
);
parameter CPU_NUMBER;
parameter AWP_PRESENT;
wire strob_a = ~as2 & strob1;
wire strob_b = as2 & strob2;
wire sel_r1_r7 = rb | ra | rc;
wire wr0 = ~sel_r1_r7;
wire M60_6 = ~(wa & rpc);
wire [0:15] R1_7;
regs USER_REGS(
.clk_sys(clk_sys),
.w(w),
.addr({rc, rb, ra}),
.we((strob_a | strob_b) & w_r & sel_r1_r7),
.l(R1_7)
);
l BUS_L(
.r0({r0, r0low}),
.rn(R1_7),
.sel({blr, sel_r1_r7 & M60_6}),
.l(l)
);
wire [0:15] rRB;
rb REG_RB(
.clk_sys(clk_sys),
.w(w[10:15]),
.w_rba(w_rba),
.w_rbb(w_rbb),
.w_rbc(w_rbc),
.rb(rRB)
);
assign zgpn = rpn ^ ~CPU_NUMBER;
wire M35_8 = CPU_NUMBER ^ bs;
wire M23_11 = CPU_NUMBER & pn_nb;
assign dpn = (M35_8 & bp_nb) | M23_11;
assign dqb = q_nb & q;
wire cnb0_3 = w_bar & strob1b;
assign zer = zer_sp | clm;
wire [0:3] nb;
wire bs;
bar REG_BAR(
.clk_sys(clk_sys),
.w(w[10:15]),
.cnb(cnb0_3),
.clm(clm),
.zer_sp(zer_sp),
.bar({q, bs, nb})
);
assign dnb = nb & {4{bar_nb}};
wire M60_3 = strob_a & AWP_PRESENT & ustr0_fp;
wire M62_6 = strob_a & w_r & wr0 & ~q;
wire M62_8 = strob_b & w_r & wr0 & ~q;
wire M61_8 = strob_a & w_r & wr0;
wire M61_12 = strob_b & w_r & wr0;
wire lr0 = lpc & strob_a & wa;
wire w_zmvc = lr0 | M62_8 | M62_6 | M60_3;
wire w_legy = lr0 | M62_8 | M62_6;
wire lrp = lr0 | M61_8 | M61_12;
wire cleg = as2 & strob2b & ust_leg;
wire vg = (~aryt & ~(zs | ~carry)) | (~(zs | s_1) & aryt);
wire vl = (~aryt & ~carry) | (aryt & s_1);
wire [9:15] r0low;
r0 REG_R0(
.clk_sys(clk_sys),
.w(w),
.r0({r0, r0low}),
.zs(zs),
.s_1(s_1),
.s0(s0),
.carry(carry),
.vl(vl),
.vg(vg),
.exy(exy),
.exx(exx),
.strob1b(strob1b),
.ust_z(ust_z),
.ust_v(ust_v),
.ust_mc(ust_mc),
.ust_y(ust_y),
.ust_x(ust_x),
.cleg(cleg),
.w_zmvc(w_zmvc),
.w_legy(w_legy),
._0_v(_0_v),
.lrp(lrp),
.zer(zer)
);
bus_ki BUS_KI(
.kia(kia),
.kib(kib),
.rz(bus_rz),
.sr({rs[0:9], q, bs, nb[0:3]}),
.rb(rRB),
.zp(zp),
.ki(bus_ki)
);
endmodule | module pr(
input clk_sys,
input blr,
input lpc,
input wa,
input rpc,
input ra,
input rb,
input rc,
input as2,
input w_r,
input strob1,
input strob1b,
input strob2,
input strob2b,
input [0:15] w,
output [0:15] l,
input bar_nb,
input w_rbb,
input w_rbc,
input w_rba,
output [0:3] dnb,
input rpn,
input bp_nb,
input pn_nb,
input q_nb,
input w_bar,
input zer_sp,
input clm,
input ustr0_fp,
input ust_leg,
input aryt,
input zs,
input carry,
input s_1,
output zgpn,
output dpn,
output dqb,
output q,
output zer,
input ust_z,
input ust_mc,
input s0,
input ust_v,
input _0_v,
output [0:8] r0,
input exy,
input ust_y,
input exx,
input ust_x,
input kia,
input kib,
input [0:15] bus_rz,
input [0:15] zp,
input [0:9] rs,
output [0:15] bus_ki
); |
parameter CPU_NUMBER;
parameter AWP_PRESENT;
wire strob_a = ~as2 & strob1;
wire strob_b = as2 & strob2;
wire sel_r1_r7 = rb | ra | rc;
wire wr0 = ~sel_r1_r7;
wire M60_6 = ~(wa & rpc);
wire [0:15] R1_7;
regs USER_REGS(
.clk_sys(clk_sys),
.w(w),
.addr({rc, rb, ra}),
.we((strob_a | strob_b) & w_r & sel_r1_r7),
.l(R1_7)
);
l BUS_L(
.r0({r0, r0low}),
.rn(R1_7),
.sel({blr, sel_r1_r7 & M60_6}),
.l(l)
);
wire [0:15] rRB;
rb REG_RB(
.clk_sys(clk_sys),
.w(w[10:15]),
.w_rba(w_rba),
.w_rbb(w_rbb),
.w_rbc(w_rbc),
.rb(rRB)
);
assign zgpn = rpn ^ ~CPU_NUMBER;
wire M35_8 = CPU_NUMBER ^ bs;
wire M23_11 = CPU_NUMBER & pn_nb;
assign dpn = (M35_8 & bp_nb) | M23_11;
assign dqb = q_nb & q;
wire cnb0_3 = w_bar & strob1b;
assign zer = zer_sp | clm;
wire [0:3] nb;
wire bs;
bar REG_BAR(
.clk_sys(clk_sys),
.w(w[10:15]),
.cnb(cnb0_3),
.clm(clm),
.zer_sp(zer_sp),
.bar({q, bs, nb})
);
assign dnb = nb & {4{bar_nb}};
wire M60_3 = strob_a & AWP_PRESENT & ustr0_fp;
wire M62_6 = strob_a & w_r & wr0 & ~q;
wire M62_8 = strob_b & w_r & wr0 & ~q;
wire M61_8 = strob_a & w_r & wr0;
wire M61_12 = strob_b & w_r & wr0;
wire lr0 = lpc & strob_a & wa;
wire w_zmvc = lr0 | M62_8 | M62_6 | M60_3;
wire w_legy = lr0 | M62_8 | M62_6;
wire lrp = lr0 | M61_8 | M61_12;
wire cleg = as2 & strob2b & ust_leg;
wire vg = (~aryt & ~(zs | ~carry)) | (~(zs | s_1) & aryt);
wire vl = (~aryt & ~carry) | (aryt & s_1);
wire [9:15] r0low;
r0 REG_R0(
.clk_sys(clk_sys),
.w(w),
.r0({r0, r0low}),
.zs(zs),
.s_1(s_1),
.s0(s0),
.carry(carry),
.vl(vl),
.vg(vg),
.exy(exy),
.exx(exx),
.strob1b(strob1b),
.ust_z(ust_z),
.ust_v(ust_v),
.ust_mc(ust_mc),
.ust_y(ust_y),
.ust_x(ust_x),
.cleg(cleg),
.w_zmvc(w_zmvc),
.w_legy(w_legy),
._0_v(_0_v),
.lrp(lrp),
.zer(zer)
);
bus_ki BUS_KI(
.kia(kia),
.kib(kib),
.rz(bus_rz),
.sr({rs[0:9], q, bs, nb[0:3]}),
.rb(rRB),
.zp(zp),
.ki(bus_ki)
);
endmodule | 24 |
139,109 | data/full_repos/permissive/86722304/src/puks.v | 86,722,304 | puks.v | v | 37 | 106 | [] | [] | [] | [(9, 34)] | null | null | 1: b"%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/puks.v:25: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'pon'\n : ... In instance puks\n if (pwon_cnt == 4'd3) pon <= 1'b1;\n ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/puks.v:26: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'pon'\n : ... In instance puks\n else if (pwon_cnt == 4'd5) pon <= 1'b0;\n ^~~\n%Error: Exiting due to 2 error(s)\n ... See the manual and https://verilator.org for more assistance.\n" | 304,325 | module | module puks(
input clk_sys,
input rcl,
input dcl,
output off,
output pout,
output pon,
output clo,
output clm
);
reg on = 1'b0;
reg [3:0] pwon_cnt = 4'd0;
always @ (posedge clk_sys) begin
if (pwon_cnt != 4'b111) pwon_cnt <= pwon_cnt + 1'b1;
if (pwon_cnt == 4'd3) on <= 1'b1;
if (pwon_cnt == 4'd3) pon <= 1'b1;
else if (pwon_cnt == 4'd5) pon <= 1'b0;
end
assign off = ~on;
assign pout = 1'b0;
assign clm = off | dcl | rcl;
assign clo = off | dcl;
endmodule | module puks(
input clk_sys,
input rcl,
input dcl,
output off,
output pout,
output pon,
output clo,
output clm
); |
reg on = 1'b0;
reg [3:0] pwon_cnt = 4'd0;
always @ (posedge clk_sys) begin
if (pwon_cnt != 4'b111) pwon_cnt <= pwon_cnt + 1'b1;
if (pwon_cnt == 4'd3) on <= 1'b1;
if (pwon_cnt == 4'd3) pon <= 1'b1;
else if (pwon_cnt == 4'd5) pon <= 1'b0;
end
assign off = ~on;
assign pout = 1'b0;
assign clm = off | dcl | rcl;
assign clo = off | dcl;
endmodule | 24 |
139,112 | data/full_repos/permissive/86722304/src/rb.v | 86,722,304 | rb.v | v | 21 | 54 | [] | [] | [] | [(3, 18)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/rb.v:5: Little bit endian vector: MSB < LSB of bit range: 10:15\n input [10:15] w,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/rb.v:9: Little bit endian vector: MSB < LSB of bit range: 0:15\n output reg [0:15] rb\n ^\n%Error: Exiting due to 2 warning(s)\n' | 304,328 | module | module rb(
input clk_sys,
input [10:15] w,
input w_rba,
input w_rbb,
input w_rbc,
output reg [0:15] rb
);
always @ (posedge clk_sys) begin
if (w_rbc) rb[0:3] <= w[12:15];
if (w_rbb) rb[4:9] <= w[10:15];
if (w_rba) rb[10:15] <= w[10:15];
end
endmodule | module rb(
input clk_sys,
input [10:15] w,
input w_rba,
input w_rbb,
input w_rbc,
output reg [0:15] rb
); |
always @ (posedge clk_sys) begin
if (w_rbc) rb[0:3] <= w[12:15];
if (w_rbb) rb[4:9] <= w[10:15];
if (w_rba) rb[10:15] <= w[10:15];
end
endmodule | 24 |
139,114 | data/full_repos/permissive/86722304/src/recv_cl.v | 86,722,304 | recv_cl.v | v | 42 | 73 | [] | [] | [] | null | line:37: before: "," | null | 1: b"%Error: data/full_repos/permissive/86722304/src/recv_cl.v:37: Define or directive not defined: '`MSG_REQ'\n assign tx_reset_cmd = tx_ena_cl ? { `MSG_REQ, `CMD_CL, 3'b000 } : 8'd0;\n ^~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/recv_cl.v:37: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n assign tx_reset_cmd = tx_ena_cl ? { `MSG_REQ, `CMD_CL, 3'b000 } : 8'd0;\n ^\n%Error: data/full_repos/permissive/86722304/src/recv_cl.v:37: Define or directive not defined: '`CMD_CL'\n assign tx_reset_cmd = tx_ena_cl ? { `MSG_REQ, `CMD_CL, 3'b000 } : 8'd0;\n ^~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 304,330 | module | module recv_cl(
input clk_sys,
input rcl,
input tx_ena_cl,
output reg tx_trig_cl,
output [0:7] tx_reset_cmd
);
localparam IDLE = 2'd0;
localparam ACCESS = 2'd1;
localparam WAIT = 2'd2;
reg [0:1] rstate = IDLE;
always @ (posedge clk_sys) begin
case (rstate)
IDLE: begin
if (rcl) begin
tx_trig_cl <= 1;
rstate <= ACCESS;
end
end
ACCESS: begin
if (tx_ena_cl) begin
tx_trig_cl <= 0;
rstate <= WAIT;
end
end
WAIT: begin
if (!tx_ena_cl & !rcl) begin
rstate <= IDLE;
end
end
endcase
end
assign tx_reset_cmd = tx_ena_cl ? { `MSG_REQ, `CMD_CL, 3'b000 } : 8'd0;
endmodule | module recv_cl(
input clk_sys,
input rcl,
input tx_ena_cl,
output reg tx_trig_cl,
output [0:7] tx_reset_cmd
); |
localparam IDLE = 2'd0;
localparam ACCESS = 2'd1;
localparam WAIT = 2'd2;
reg [0:1] rstate = IDLE;
always @ (posedge clk_sys) begin
case (rstate)
IDLE: begin
if (rcl) begin
tx_trig_cl <= 1;
rstate <= ACCESS;
end
end
ACCESS: begin
if (tx_ena_cl) begin
tx_trig_cl <= 0;
rstate <= WAIT;
end
end
WAIT: begin
if (!tx_ena_cl & !rcl) begin
rstate <= IDLE;
end
end
endcase
end
assign tx_reset_cmd = tx_ena_cl ? { `MSG_REQ, `CMD_CL, 3'b000 } : 8'd0;
endmodule | 24 |
139,117 | data/full_repos/permissive/86722304/src/rm.v | 86,722,304 | rm.v | v | 26 | 54 | [] | [] | [] | [(3, 23)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/rm.v:7: Little bit endian vector: MSB < LSB of bit range: 0:9\n input [0:9] zi,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/rm.v:8: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] w,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/rm.v:9: Little bit endian vector: MSB < LSB of bit range: 0:9\n output reg [0:9] rs\n ^\n%Error: Exiting due to 3 warning(s)\n' | 304,333 | module | module rm(
input clk_sys,
input clm$,
input clrs,
input [0:9] zi,
input [0:15] w,
output reg [0:9] rs
);
genvar num;
generate
for (num=0 ; num<10 ; num=num+1) begin : REG_RM
wire rm_reset = zi[num] & clm$;
always @ (posedge clk_sys, posedge rm_reset) begin
if (rm_reset) rs[num] <= 1'b0;
else if (clrs) rs[num] <= w[num];
end
end
endgenerate
endmodule | module rm(
input clk_sys,
input clm$,
input clrs,
input [0:9] zi,
input [0:15] w,
output reg [0:9] rs
); |
genvar num;
generate
for (num=0 ; num<10 ; num=num+1) begin : REG_RM
wire rm_reset = zi[num] & clm$;
always @ (posedge clk_sys, posedge rm_reset) begin
if (rm_reset) rs[num] <= 1'b0;
else if (clrs) rs[num] <= w[num];
end
end
endgenerate
endmodule | 24 |
139,119 | data/full_repos/permissive/86722304/src/rzrp.v | 86,722,304 | rzrp.v | v | 42 | 99 | [] | [] | [] | [(3, 39)] | null | null | 1: b"%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/rzrp.v:21: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'rz'\n : ... In instance rzrp\n if (irq) rz <= 1'b1;\n ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/rzrp.v:22: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'rz'\n : ... In instance rzrp\n else if (rz_r) rz <= 1'b0;\n ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/rzrp.v:24: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'rz'\n : ... In instance rzrp\n 2'b00 : rz <= rz;\n ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/rzrp.v:25: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'rz'\n : ... In instance rzrp\n 2'b01 : rz <= 1'b0;\n ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/rzrp.v:26: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'rz'\n : ... In instance rzrp\n 2'b10 : rz <= 1'b1;\n ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/rzrp.v:27: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'rz'\n : ... In instance rzrp\n 2'b11 : rz <= ~rz;\n ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/rzrp.v:33: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'rp'\n : ... In instance rzrp\n if (prio_in) rp <= 1'b0;\n ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/rzrp.v:34: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'rp'\n : ... In instance rzrp\n else if (rp_c) rp <= sz;\n ^~\n%Error: Exiting due to 8 error(s)\n ... See the manual and https://verilator.org for more assistance.\n" | 304,335 | module | module rzrp(
input clk_sys,
input imask,
input irq,
input w,
input rz_c,
input rz_r,
input rp_c,
input prio_in,
output rz,
output sz,
output rp,
output prio_out
);
assign sz = rz & imask;
always @ (posedge clk_sys, posedge irq) begin
if (irq) rz <= 1'b1;
else if (rz_r) rz <= 1'b0;
else if (rz_c) case ({w, rp})
2'b00 : rz <= rz;
2'b01 : rz <= 1'b0;
2'b10 : rz <= 1'b1;
2'b11 : rz <= ~rz;
endcase
end
always @ (posedge clk_sys, posedge prio_in) begin
if (prio_in) rp <= 1'b0;
else if (rp_c) rp <= sz;
end
assign prio_out = rp | prio_in;
endmodule | module rzrp(
input clk_sys,
input imask,
input irq,
input w,
input rz_c,
input rz_r,
input rp_c,
input prio_in,
output rz,
output sz,
output rp,
output prio_out
); |
assign sz = rz & imask;
always @ (posedge clk_sys, posedge irq) begin
if (irq) rz <= 1'b1;
else if (rz_r) rz <= 1'b0;
else if (rz_c) case ({w, rp})
2'b00 : rz <= rz;
2'b01 : rz <= 1'b0;
2'b10 : rz <= 1'b1;
2'b11 : rz <= ~rz;
endcase
end
always @ (posedge clk_sys, posedge prio_in) begin
if (prio_in) rp <= 1'b0;
else if (rp_c) rp <= sz;
end
assign prio_out = rp | prio_in;
endmodule | 24 |
139,125 | data/full_repos/permissive/86722304/src/strobgen.v | 86,722,304 | strobgen.v | v | 120 | 146 | [] | [] | [] | [(3, 117)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/strobgen.v:54: Little bit endian vector: MSB < LSB of bit range: 0:2\n reg [0:2] state;\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 304,337 | module | module strobgen(
input clk_sys,
input ss11, ss12, ss13, ss14, ss15,
input ok$, zw, oken,
input mode, step,
input strob_fp,
input strobb_fp,
output ldstate,
output got,
output strob1,
output strob1b,
output strob2,
output strob2b
);
localparam S_GOT = 3'd0;
localparam S_GOTW = 3'd1;
localparam S_ST1 = 3'd2;
localparam S_ST1W = 3'd3;
localparam S_ST1B = 3'd4;
localparam S_PGOT = 3'd5;
localparam S_ST2 = 3'd6;
localparam S_ST2B = 3'd7;
wire if_busy = zw & oken;
wire es1 = ss11 | (ss12 & ok$) | (ss13 & ok$) | ss14 | ss15;
wire has_strob2 = ss11 | ss12;
wire no_strob2 = ss13 | ss14 | ss15;
assign got = state == S_GOT;
assign strob1 = (state == S_ST1) | strob_fp;
assign strob1b = (state == S_ST1B) | strobb_fp;
assign strob2 = state == S_ST2;
assign strob2b = state == S_ST2B;
assign ldstate = ~if_busy & ((state == S_PGOT) | ((state == S_ST1B) & no_strob2) | (state == S_ST2B));
reg lstep;
always @ (posedge clk_sys) begin
lstep <= step;
end
wire step_trig = ~mode | (step & ~lstep);
reg [0:2] state;
always @ (posedge clk_sys) begin
case (state)
S_GOT: begin
if (es1) begin
state <= S_ST1;
end else begin
state <= S_GOTW;
end
end
S_GOTW: begin
if (es1) begin
state <= S_ST1;
end
end
S_ST1: begin
if (step_trig) state <= S_ST1B;
else state <= S_ST1W;
end
S_ST1W: begin
if (step_trig) state <= S_ST1B;
end
S_ST1B: begin
if (has_strob2) begin
state <= S_ST2;
end else if (no_strob2 & ~if_busy) begin
state <= S_GOT;
end else begin
state <= S_PGOT;
end
end
S_ST2: begin
state <= S_ST2B;
end
S_ST2B: begin
if (~if_busy) begin
state <= S_GOT;
end else begin
state <= S_PGOT;
end
end
S_PGOT: begin
if (~if_busy) begin
state <= S_GOT;
end
end
endcase
end
endmodule | module strobgen(
input clk_sys,
input ss11, ss12, ss13, ss14, ss15,
input ok$, zw, oken,
input mode, step,
input strob_fp,
input strobb_fp,
output ldstate,
output got,
output strob1,
output strob1b,
output strob2,
output strob2b
); |
localparam S_GOT = 3'd0;
localparam S_GOTW = 3'd1;
localparam S_ST1 = 3'd2;
localparam S_ST1W = 3'd3;
localparam S_ST1B = 3'd4;
localparam S_PGOT = 3'd5;
localparam S_ST2 = 3'd6;
localparam S_ST2B = 3'd7;
wire if_busy = zw & oken;
wire es1 = ss11 | (ss12 & ok$) | (ss13 & ok$) | ss14 | ss15;
wire has_strob2 = ss11 | ss12;
wire no_strob2 = ss13 | ss14 | ss15;
assign got = state == S_GOT;
assign strob1 = (state == S_ST1) | strob_fp;
assign strob1b = (state == S_ST1B) | strobb_fp;
assign strob2 = state == S_ST2;
assign strob2b = state == S_ST2B;
assign ldstate = ~if_busy & ((state == S_PGOT) | ((state == S_ST1B) & no_strob2) | (state == S_ST2B));
reg lstep;
always @ (posedge clk_sys) begin
lstep <= step;
end
wire step_trig = ~mode | (step & ~lstep);
reg [0:2] state;
always @ (posedge clk_sys) begin
case (state)
S_GOT: begin
if (es1) begin
state <= S_ST1;
end else begin
state <= S_GOTW;
end
end
S_GOTW: begin
if (es1) begin
state <= S_ST1;
end
end
S_ST1: begin
if (step_trig) state <= S_ST1B;
else state <= S_ST1W;
end
S_ST1W: begin
if (step_trig) state <= S_ST1B;
end
S_ST1B: begin
if (has_strob2) begin
state <= S_ST2;
end else if (no_strob2 & ~if_busy) begin
state <= S_GOT;
end else begin
state <= S_PGOT;
end
end
S_ST2: begin
state <= S_ST2B;
end
S_ST2B: begin
if (~if_busy) begin
state <= S_GOT;
end else begin
state <= S_PGOT;
end
end
S_PGOT: begin
if (~if_busy) begin
state <= S_GOT;
end
end
endcase
end
endmodule | 24 |
139,126 | data/full_repos/permissive/86722304/src/t.v | 86,722,304 | t.v | v | 54 | 54 | [] | [] | [] | [(1, 51)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/t.v:11: Little bit endian vector: MSB < LSB of bit range: 0:39\n input [0:39] k,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/t.v:13: Little bit endian vector: MSB < LSB of bit range: -1:39\n output reg [-1:39] t\n ^\n%Error: Exiting due to 2 warning(s)\n' | 304,338 | module | module t(
input clk_sys,
input _0_t,
input taa,
input tab,
input trb,
input clockta,
input clocktb,
input clocktc,
input t_1_d,
input [0:39] k,
input m_1,
output reg [-1:39] t
);
always @ (posedge clk_sys, posedge _0_t) begin
if (_0_t) t[0:15] <= 0;
else if (clockta) case ({~tab, ~taa})
2'b00: t[0:15] <= t[0:15];
2'b01: t[0:15] <= t[-1:14];
2'b10: t[0:15] <= t[1:16];
2'b11: t[0:15] <= k[0:15];
endcase
end
always @ (posedge clk_sys, posedge _0_t) begin
if (_0_t) t[16:31] <= 0;
else if (clocktb) case ({~trb, ~taa})
2'b00: t[16:31] <= t[16:31];
2'b01: t[16:31] <= t[15:30];
2'b10: t[16:31] <= t[17:32];
2'b11: t[16:31] <= k[16:31];
endcase
end
always @ (posedge clk_sys, posedge _0_t) begin
if (_0_t) t[32:39] <= 0;
else if (clocktc) case ({~trb, ~taa})
2'b00: t[32:39] <= t[32:39];
2'b01: t[32:39] <= t[31:38];
2'b10: t[32:39] <= {t[33:39], m_1};
2'b11: t[32:39] <= k[32:39];
endcase
end
always @ (posedge clk_sys, posedge _0_t) begin
if (_0_t) t[-1] <= 1'b0;
else if (clockta) t[-1] <= t_1_d;
end
endmodule | module t(
input clk_sys,
input _0_t,
input taa,
input tab,
input trb,
input clockta,
input clocktb,
input clocktc,
input t_1_d,
input [0:39] k,
input m_1,
output reg [-1:39] t
); |
always @ (posedge clk_sys, posedge _0_t) begin
if (_0_t) t[0:15] <= 0;
else if (clockta) case ({~tab, ~taa})
2'b00: t[0:15] <= t[0:15];
2'b01: t[0:15] <= t[-1:14];
2'b10: t[0:15] <= t[1:16];
2'b11: t[0:15] <= k[0:15];
endcase
end
always @ (posedge clk_sys, posedge _0_t) begin
if (_0_t) t[16:31] <= 0;
else if (clocktb) case ({~trb, ~taa})
2'b00: t[16:31] <= t[16:31];
2'b01: t[16:31] <= t[15:30];
2'b10: t[16:31] <= t[17:32];
2'b11: t[16:31] <= k[16:31];
endcase
end
always @ (posedge clk_sys, posedge _0_t) begin
if (_0_t) t[32:39] <= 0;
else if (clocktc) case ({~trb, ~taa})
2'b00: t[32:39] <= t[32:39];
2'b01: t[32:39] <= t[31:38];
2'b10: t[32:39] <= {t[33:39], m_1};
2'b11: t[32:39] <= k[32:39];
endcase
end
always @ (posedge clk_sys, posedge _0_t) begin
if (_0_t) t[-1] <= 1'b0;
else if (clockta) t[-1] <= t_1_d;
end
endmodule | 24 |
139,127 | data/full_repos/permissive/86722304/src/timer.v | 86,722,304 | timer.v | v | 34 | 62 | [] | [] | [] | null | line:9: before: ";" | null | 1: b"%Error: data/full_repos/permissive/86722304/src/timer.v:9: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'TIMER_CYCLE_MS'\n : ... In instance timer\n parameter TIMER_CYCLE_MS;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/timer.v:10: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'CLK_SYS_HZ'\n : ... In instance timer\n parameter CLK_SYS_HZ;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/timer.v:18: Expecting expression to be constant, but variable isn't const: 'TIMER_CYCLE_MS'\n : ... In instance timer\n localparam prescale = TIMER_CYCLE_MS * (CLK_SYS_HZ / 1_000);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/timer.v:18: Expecting expression to be constant, but variable isn't const: 'CLK_SYS_HZ'\n : ... In instance timer\n localparam prescale = TIMER_CYCLE_MS * (CLK_SYS_HZ / 1_000);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/timer.v:19: Expecting expression to be constant, but variable isn't const: 'prescale'\n : ... In instance timer\n localparam width = $clog2(prescale+1);\n ^~~~~~~~\n%Error: data/full_repos/permissive/86722304/src/timer.v:20: Expecting expression to be constant, but variable isn't const: 'width'\n localparam [width-1:0] period = prescale[width-1:0] - 1'b1;\n ^~~~~\n%Error: data/full_repos/permissive/86722304/src/timer.v:20: MSB of bit range isn't a constant\n localparam [width-1:0] period = prescale[width-1:0] - 1'b1;\n ^\n%Error: data/full_repos/permissive/86722304/src/timer.v:20: Expecting expression to be constant, but variable isn't const: 'width'\n : ... In instance timer\n localparam [width-1:0] period = prescale[width-1:0] - 1'b1;\n ^~~~~\n%Error: data/full_repos/permissive/86722304/src/timer.v:20: Second value of [a:b] isn't a constant, maybe you want +: or -:\n : ... In instance timer\n localparam [width-1:0] period = prescale[width-1:0] - 1'b1;\n ^\n%Error: data/full_repos/permissive/86722304/src/timer.v:20: Expecting expression to be constant, but variable isn't const: 'prescale'\n : ... In instance timer\n localparam [width-1:0] period = prescale[width-1:0] - 1'b1;\n ^~~~~~~~\n%Error: Exiting due to 10 error(s)\n" | 304,339 | module | module timer(
input clk_sys,
input enable,
output zegar
);
parameter TIMER_CYCLE_MS;
parameter CLK_SYS_HZ;
localparam prescale = TIMER_CYCLE_MS * (CLK_SYS_HZ / 1_000);
localparam width = $clog2(prescale+1);
localparam [width-1:0] period = prescale[width-1:0] - 1'b1;
reg [width-1:0] timer_cnt = period;
always @ (posedge clk_sys) begin
if (timer_cnt == 0) timer_cnt <= period;
else timer_cnt <= timer_cnt - 1'b1;
end
assign zegar = enable & (timer_cnt == 0);
endmodule | module timer(
input clk_sys,
input enable,
output zegar
); |
parameter TIMER_CYCLE_MS;
parameter CLK_SYS_HZ;
localparam prescale = TIMER_CYCLE_MS * (CLK_SYS_HZ / 1_000);
localparam width = $clog2(prescale+1);
localparam [width-1:0] period = prescale[width-1:0] - 1'b1;
reg [width-1:0] timer_cnt = period;
always @ (posedge clk_sys) begin
if (timer_cnt == 0) timer_cnt <= period;
else timer_cnt <= timer_cnt - 1'b1;
end
assign zegar = enable & (timer_cnt == 0);
endmodule | 24 |
139,132 | data/full_repos/permissive/86722304/src/zp.v | 86,722,304 | zp.v | v | 27 | 54 | [] | [] | [] | [(1, 24)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/zp.v:5: Little bit endian vector: MSB < LSB of bit range: 0:39\n input [0:39] t,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/zp.v:6: Little bit endian vector: MSB < LSB of bit range: 0:7\n input [0:7] d,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/zp.v:11: Little bit endian vector: MSB < LSB of bit range: 0:15\n output [0:15] zp\n ^\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/zp.v:15: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'zp\'\n : ... In instance zp\n if (_0_zp) zp <= 16\'d0;\n ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/zp.v:17: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'zp\'\n : ... In instance zp\n 2\'b00: zp <= t[0:15];\n ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/zp.v:18: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'zp\'\n : ... In instance zp\n 2\'b01: zp <= t[16:31];\n ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/zp.v:19: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'zp\'\n : ... In instance zp\n 2\'b10: zp <= {t[32:39], d[0:7]};\n ^~\n%Error-PROCASSWIRE: data/full_repos/permissive/86722304/src/zp.v:20: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'zp\'\n : ... In instance zp\n 2\'b11: zp <= {z_f, m_f, v_f, c_f, 12\'d0};\n ^~\n%Error: Exiting due to 5 error(s), 3 warning(s)\n' | 304,342 | module | module zp(
input _0_zp,
input zpa,
input zpb,
input [0:39] t,
input [0:7] d,
input z_f,
input m_f,
input v_f,
input c_f,
output [0:15] zp
);
always @ (*) begin
if (_0_zp) zp <= 16'd0;
else case ({zpb, zpa})
2'b00: zp <= t[0:15];
2'b01: zp <= t[16:31];
2'b10: zp <= {t[32:39], d[0:7]};
2'b11: zp <= {z_f, m_f, v_f, c_f, 12'd0};
endcase
end
endmodule | module zp(
input _0_zp,
input zpa,
input zpb,
input [0:39] t,
input [0:7] d,
input z_f,
input m_f,
input v_f,
input c_f,
output [0:15] zp
); |
always @ (*) begin
if (_0_zp) zp <= 16'd0;
else case ({zpb, zpa})
2'b00: zp <= t[0:15];
2'b01: zp <= t[16:31];
2'b10: zp <= {t[32:39], d[0:7]};
2'b11: zp <= {z_f, m_f, v_f, c_f, 12'd0};
endcase
end
endmodule | 24 |
139,133 | data/full_repos/permissive/86754567/memory/async_bridge.v | 86,754,567 | async_bridge.v | v | 177 | 71 | [] | [] | [] | [(18, 68), (71, 174)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86754567/memory/async_bridge.v:102: Unsupported: Ignoring delay on this delayed statement.\n #5 clk_i <= ~clk_i;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:106: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("async_bridge.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:107: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:110: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:110: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:113: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:113: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:118: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:118: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:122: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:122: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:124: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:124: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:127: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:127: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:129: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:129: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:131: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:131: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:134: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:134: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:138: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:138: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:139: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:139: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:145: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:145: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:148: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:148: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:151: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:151: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:154: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:154: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:158: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:158: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:161: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:161: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:164: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:164: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:167: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:167: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/86754567/memory/async_bridge.v:171: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: Exiting due to 40 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,344 | module | module async_bridge(
input clk_i,
input reset_i,
input cyc_i,
input stb_i,
input we_i,
input [1:0] sel_i,
input [19:1] adr_i,
input [15:0] dat_i,
output ack_o,
output [15:0] dat_o,
output stall_o,
output _sram_ce,
output _sram_we,
output _sram_oe,
output _sram_ub,
output _sram_lb,
output [19:1] sram_a,
output [15:0] sram_d_out,
input [15:0] sram_d_in
);
reg transfer;
reg [1:0] selects;
reg write;
reg [15:0] data_in;
reg [19:1] address;
assign ack_o = transfer;
wire sram_we = transfer & write & ~clk_i;
wire sram_oe = transfer & ~write & ~clk_i;
assign _sram_ce = 0;
assign _sram_we = ~sram_we;
assign _sram_oe = ~sram_oe;
assign _sram_ub = ~selects[1];
assign _sram_lb = ~selects[0];
assign dat_o = sram_oe ? sram_d_in : 0;
assign sram_a = address;
assign sram_d_out = data_in;
assign stall_o = 0;
always @(posedge clk_i) begin
transfer <= cyc_i & stb_i;
selects <= sel_i;
write <= we_i;
address <= adr_i;
data_in <= dat_i;
end
endmodule | module async_bridge(
input clk_i,
input reset_i,
input cyc_i,
input stb_i,
input we_i,
input [1:0] sel_i,
input [19:1] adr_i,
input [15:0] dat_i,
output ack_o,
output [15:0] dat_o,
output stall_o,
output _sram_ce,
output _sram_we,
output _sram_oe,
output _sram_ub,
output _sram_lb,
output [19:1] sram_a,
output [15:0] sram_d_out,
input [15:0] sram_d_in
); |
reg transfer;
reg [1:0] selects;
reg write;
reg [15:0] data_in;
reg [19:1] address;
assign ack_o = transfer;
wire sram_we = transfer & write & ~clk_i;
wire sram_oe = transfer & ~write & ~clk_i;
assign _sram_ce = 0;
assign _sram_we = ~sram_we;
assign _sram_oe = ~sram_oe;
assign _sram_ub = ~selects[1];
assign _sram_lb = ~selects[0];
assign dat_o = sram_oe ? sram_d_in : 0;
assign sram_a = address;
assign sram_d_out = data_in;
assign stall_o = 0;
always @(posedge clk_i) begin
transfer <= cyc_i & stb_i;
selects <= sel_i;
write <= we_i;
address <= adr_i;
data_in <= dat_i;
end
endmodule | 0 |
139,134 | data/full_repos/permissive/86754567/memory/async_bridge.v | 86,754,567 | async_bridge.v | v | 177 | 71 | [] | [] | [] | [(18, 68), (71, 174)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86754567/memory/async_bridge.v:102: Unsupported: Ignoring delay on this delayed statement.\n #5 clk_i <= ~clk_i;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:106: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("async_bridge.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:107: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:110: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:110: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:113: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:113: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:118: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:118: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:122: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:122: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:124: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:124: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:127: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:127: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:129: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:129: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:131: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:131: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:134: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:134: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:138: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:138: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:139: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:139: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:145: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:145: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:148: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:148: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:151: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:151: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:154: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:154: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:158: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:158: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:161: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:161: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:164: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:164: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:167: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/memory/async_bridge.v:167: Unsupported: wait statements\n wait(~clk_i); wait(clk_i);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/86754567/memory/async_bridge.v:171: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: Exiting due to 40 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,344 | module | module async_bridge_tb();
reg clk_i, reset_i, cyc_i, stb_i, we_i;
reg [1:0] sel_i;
reg [19:1] adr_i;
reg [15:0] dat_i;
wire ack_o;
wire _sram_we, _sram_oe, _sram_ub, _sram_lb;
wire [15:0] dat_o, sram_d_out;
wire [19:1] sram_a;
async_bridge rc(
.clk_i(clk_i),
.reset_i(reset_i),
.cyc_i(cyc_i),
.stb_i(stb_i),
.we_i(we_i),
.sel_i(sel_i),
.adr_i(adr_i),
.ack_o(ack_o),
.dat_o(dat_o),
.dat_i(dat_i),
._sram_we(_sram_we),
._sram_oe(_sram_oe),
._sram_ub(_sram_ub),
._sram_lb(_sram_lb),
.sram_a(sram_a),
.sram_d_in(16'hF00D),
.sram_d_out(sram_d_out)
);
always begin
#5 clk_i <= ~clk_i;
end
initial begin
$dumpfile("async_bridge.vcd");
$dumpvars;
{clk_i, reset_i, cyc_i, stb_i, we_i, sel_i, adr_i, dat_i} = 0;
wait(~clk_i); wait(clk_i);
reset_i <= 1;
wait(~clk_i); wait(clk_i);
adr_i <= 0;
reset_i <= 0;
wait(~clk_i); wait(clk_i);
cyc_i <= 1;
stb_i <= 1;
wait(~clk_i); wait(clk_i);
stb_i <= 0;
wait(~clk_i); wait(clk_i);
stb_i <= 1;
wait(~clk_i); wait(clk_i);
sel_i <= 2'b01;
wait(~clk_i); wait(clk_i);
sel_i <= 2'b10;
wait(~clk_i); wait(clk_i);
sel_i <= 2'b11;
stb_i <= 0;
wait(~clk_i); wait(clk_i);
cyc_i <= 0;
sel_i <= 0;
wait(~clk_i); wait(clk_i);
wait(~clk_i); wait(clk_i);
cyc_i <= 1;
stb_i <= 1;
adr_i <= 20'h00000;
we_i <= 0;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00001;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00002;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00003;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00000;
we_i <= 1;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00001;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00002;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00003;
wait(~clk_i); wait(clk_i);
cyc_i <= 0;
stb_i <= 0;
#100;
$stop;
end
endmodule | module async_bridge_tb(); |
reg clk_i, reset_i, cyc_i, stb_i, we_i;
reg [1:0] sel_i;
reg [19:1] adr_i;
reg [15:0] dat_i;
wire ack_o;
wire _sram_we, _sram_oe, _sram_ub, _sram_lb;
wire [15:0] dat_o, sram_d_out;
wire [19:1] sram_a;
async_bridge rc(
.clk_i(clk_i),
.reset_i(reset_i),
.cyc_i(cyc_i),
.stb_i(stb_i),
.we_i(we_i),
.sel_i(sel_i),
.adr_i(adr_i),
.ack_o(ack_o),
.dat_o(dat_o),
.dat_i(dat_i),
._sram_we(_sram_we),
._sram_oe(_sram_oe),
._sram_ub(_sram_ub),
._sram_lb(_sram_lb),
.sram_a(sram_a),
.sram_d_in(16'hF00D),
.sram_d_out(sram_d_out)
);
always begin
#5 clk_i <= ~clk_i;
end
initial begin
$dumpfile("async_bridge.vcd");
$dumpvars;
{clk_i, reset_i, cyc_i, stb_i, we_i, sel_i, adr_i, dat_i} = 0;
wait(~clk_i); wait(clk_i);
reset_i <= 1;
wait(~clk_i); wait(clk_i);
adr_i <= 0;
reset_i <= 0;
wait(~clk_i); wait(clk_i);
cyc_i <= 1;
stb_i <= 1;
wait(~clk_i); wait(clk_i);
stb_i <= 0;
wait(~clk_i); wait(clk_i);
stb_i <= 1;
wait(~clk_i); wait(clk_i);
sel_i <= 2'b01;
wait(~clk_i); wait(clk_i);
sel_i <= 2'b10;
wait(~clk_i); wait(clk_i);
sel_i <= 2'b11;
stb_i <= 0;
wait(~clk_i); wait(clk_i);
cyc_i <= 0;
sel_i <= 0;
wait(~clk_i); wait(clk_i);
wait(~clk_i); wait(clk_i);
cyc_i <= 1;
stb_i <= 1;
adr_i <= 20'h00000;
we_i <= 0;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00001;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00002;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00003;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00000;
we_i <= 1;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00001;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00002;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00003;
wait(~clk_i); wait(clk_i);
cyc_i <= 0;
stb_i <= 0;
#100;
$stop;
end
endmodule | 0 |
139,135 | data/full_repos/permissive/86754567/muller-c-element/muller_c.v | 86,754,567 | muller_c.v | v | 11 | 53 | [] | [] | [] | [(3, 10)] | null | data/verilator_xmls/5bdf3e0e-c173-489b-b77c-ac1f7e40f457.xml | null | 304,345 | module | module muller_c(
input r,
input a,
input b,
output x
);
assign #0.1 x = ~r & ((a & b) | (a & x) | (b & x));
endmodule | module muller_c(
input r,
input a,
input b,
output x
); |
assign #0.1 x = ~r & ((a & b) | (a & x) | (b & x));
endmodule | 0 |
139,136 | data/full_repos/permissive/86754567/muller-c-element/muller_c_tb.v | 86,754,567 | muller_c_tb.v | v | 56 | 44 | [] | [] | [] | [(3, 55)] | null | null | 1: b'%Error: data/full_repos/permissive/86754567/muller-c-element/muller_c_tb.v:10: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("wtf.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86754567/muller-c-element/muller_c_tb.v:11: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/86754567/muller-c-element/muller_c_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n {a, b} = 0; #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86754567/muller-c-element/muller_c_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n {a, b} = 1; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/muller-c-element/muller_c_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n {a, b} = 2; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/muller-c-element/muller_c_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n {a, b} = 3; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/muller-c-element/muller_c_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n {a, b} = 2; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/muller-c-element/muller_c_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n {a, b} = 1; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/muller-c-element/muller_c_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n {a, b} = 0; #5;\n ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,346 | module | module muller_c_tb();
reg a, b;
wire x;
muller_c mc(.a(a), .b(b), .x(x), .r(0));
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
{a, b} = 0; #5;
if(x !== 0) begin
$display("001 X Expected 0, got %d", x);
$stop;
end
{a, b} = 1; #5;
if(x !== 0) begin
$display("002 X Expected 0, got %d", x);
$stop;
end
{a, b} = 2; #5;
if(x !== 0) begin
$display("003 X Expected 0, got %d", x);
$stop;
end
{a, b} = 3; #5;
if(x !== 1) begin
$display("004 X Expected 1, got %d", x);
$stop;
end
{a, b} = 2; #5;
if(x !== 1) begin
$display("005 X Expected 1, got %d", x);
$stop;
end
{a, b} = 1; #5;
if(x !== 1) begin
$display("006 X Expected 1, got %d", x);
$stop;
end
{a, b} = 0; #5;
if(x !== 0) begin
$display("007 X Expected 0, got %d", x);
$stop;
end
end
endmodule | module muller_c_tb(); |
reg a, b;
wire x;
muller_c mc(.a(a), .b(b), .x(x), .r(0));
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
{a, b} = 0; #5;
if(x !== 0) begin
$display("001 X Expected 0, got %d", x);
$stop;
end
{a, b} = 1; #5;
if(x !== 0) begin
$display("002 X Expected 0, got %d", x);
$stop;
end
{a, b} = 2; #5;
if(x !== 0) begin
$display("003 X Expected 0, got %d", x);
$stop;
end
{a, b} = 3; #5;
if(x !== 1) begin
$display("004 X Expected 1, got %d", x);
$stop;
end
{a, b} = 2; #5;
if(x !== 1) begin
$display("005 X Expected 1, got %d", x);
$stop;
end
{a, b} = 1; #5;
if(x !== 1) begin
$display("006 X Expected 1, got %d", x);
$stop;
end
{a, b} = 0; #5;
if(x !== 0) begin
$display("007 X Expected 0, got %d", x);
$stop;
end
end
endmodule | 0 |
139,137 | data/full_repos/permissive/86754567/muller-c-element/pipeline/pipeline_tb.v | 86,754,567 | pipeline_tb.v | v | 33 | 60 | [] | [] | [] | null | line:4: before: "," | null | 1: b'%Error: data/full_repos/permissive/86754567/muller-c-element/pipeline/pipeline_tb.v:12: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("wtf.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86754567/muller-c-element/pipeline/pipeline_tb.v:13: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/86754567/muller-c-element/pipeline/pipeline_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86754567/muller-c-element/pipeline/pipeline_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/muller-c-element/pipeline/pipeline_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/muller-c-element/pipeline/pipeline_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n req0 <= 1; #1; req0 <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/muller-c-element/pipeline/pipeline_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/muller-c-element/pipeline/pipeline_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/muller-c-element/pipeline/pipeline_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n req0 <= 1; #1; req0 <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/muller-c-element/pipeline/pipeline_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/muller-c-element/pipeline/pipeline_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n req0 <= 1; #1; req0 <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/muller-c-element/pipeline/pipeline_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/muller-c-element/pipeline/pipeline_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 2 error(s), 11 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,347 | module | module pipeline_tb();
reg req0=0, ack3=0, reset=0;
wire ack0, ack1, ack2;
muller_c stage0(.a(req0), .b(~ack1), .x(ack0), .r(reset));
muller_c stage1(.a(ack0), .b(~ack2), .x(ack1), .r(reset));
muller_c stage2(.a(ack1), .b(~ack3), .x(ack2), .r(reset));
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
#10;
reset <= 1;
#10;
reset <= 0;
#10;
req0 <= 1; #1; req0 <= 0;
#10;
ack3 <= 1;
#10;
req0 <= 1; #1; req0 <= 0;
#10;
ack3 <= 0;
req0 <= 1; #1; req0 <= 0;
#10;
ack3 <= 1;
#10;
end
endmodule | module pipeline_tb(); |
reg req0=0, ack3=0, reset=0;
wire ack0, ack1, ack2;
muller_c stage0(.a(req0), .b(~ack1), .x(ack0), .r(reset));
muller_c stage1(.a(ack0), .b(~ack2), .x(ack1), .r(reset));
muller_c stage2(.a(ack1), .b(~ack3), .x(ack2), .r(reset));
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
#10;
reset <= 1;
#10;
reset <= 0;
#10;
req0 <= 1; #1; req0 <= 0;
#10;
ack3 <= 1;
#10;
req0 <= 1; #1; req0 <= 0;
#10;
ack3 <= 0;
req0 <= 1; #1; req0 <= 0;
#10;
ack3 <= 1;
#10;
end
endmodule | 0 |
139,138 | data/full_repos/permissive/86754567/queue/queue.v | 86,754,567 | queue.v | v | 69 | 42 | [] | [] | [] | [(3, 68)] | null | data/verilator_xmls/125768d5-0373-4d0a-9b9f-c9832637da71.xml | null | 304,348 | module | module queue(
input clk_i,
input reset_i,
input [DHB:0] dat_i,
input push_i,
input pop_i,
input oe_i,
output [DHB:0] dat_o,
output full_o,
output empty_o,
output [PHB:0] rp_to,
output [PHB:0] wp_to,
output [PHB+1:0] room_to
);
parameter DEPTH_BITS = 4;
parameter DATA_BITS = 8;
parameter DHB = DATA_BITS - 1;
parameter PHB = DEPTH_BITS - 1;
parameter CAPACITY = 1 << DEPTH_BITS;
reg [PHB:0] rp, wp;
reg [PHB+1:0] room;
reg [DHB:0] storage[0:CAPACITY-1];
assign dat_o = (oe_i ? storage[rp] : 0);
assign full_o = (room == 0);
assign empty_o = (room == CAPACITY);
assign rp_to = rp;
assign wp_to = wp;
assign room_to = room;
always @(posedge clk_i) begin
rp <= rp;
wp <= wp;
room <= room;
if(reset_i) begin
rp <= 0;
wp <= 0;
room <= CAPACITY;
end
if(push_i & ~pop_i & ~full_o) begin
storage[wp] <= dat_i;
wp <= wp + 1;
room <= room - 1;
end
if(~push_i & pop_i & ~empty_o) begin
rp <= rp + 1;
room <= room + 1;
end
if(push_i & pop_i) begin
storage[wp] <= dat_i;
wp <= wp + 1;
rp <= rp + 1;
end
end
endmodule | module queue(
input clk_i,
input reset_i,
input [DHB:0] dat_i,
input push_i,
input pop_i,
input oe_i,
output [DHB:0] dat_o,
output full_o,
output empty_o,
output [PHB:0] rp_to,
output [PHB:0] wp_to,
output [PHB+1:0] room_to
); |
parameter DEPTH_BITS = 4;
parameter DATA_BITS = 8;
parameter DHB = DATA_BITS - 1;
parameter PHB = DEPTH_BITS - 1;
parameter CAPACITY = 1 << DEPTH_BITS;
reg [PHB:0] rp, wp;
reg [PHB+1:0] room;
reg [DHB:0] storage[0:CAPACITY-1];
assign dat_o = (oe_i ? storage[rp] : 0);
assign full_o = (room == 0);
assign empty_o = (room == CAPACITY);
assign rp_to = rp;
assign wp_to = wp;
assign room_to = room;
always @(posedge clk_i) begin
rp <= rp;
wp <= wp;
room <= room;
if(reset_i) begin
rp <= 0;
wp <= 0;
room <= CAPACITY;
end
if(push_i & ~pop_i & ~full_o) begin
storage[wp] <= dat_i;
wp <= wp + 1;
room <= room - 1;
end
if(~push_i & pop_i & ~empty_o) begin
rp <= rp + 1;
room <= room + 1;
end
if(push_i & pop_i) begin
storage[wp] <= dat_i;
wp <= wp + 1;
rp <= rp + 1;
end
end
endmodule | 0 |
139,139 | data/full_repos/permissive/86754567/queue/queue_tb.v | 86,754,567 | queue_tb.v | v | 309 | 64 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/86754567/queue/queue_tb.v:4: Cannot find include file: asserts.vh\n`include "asserts.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86754567/queue,data/full_repos/permissive/86754567/asserts.vh\n data/full_repos/permissive/86754567/queue,data/full_repos/permissive/86754567/asserts.vh.v\n data/full_repos/permissive/86754567/queue,data/full_repos/permissive/86754567/asserts.vh.sv\n asserts.vh\n asserts.vh.v\n asserts.vh.sv\n obj_dir/asserts.vh\n obj_dir/asserts.vh.v\n obj_dir/asserts.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/86754567/queue/queue_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #20 clk_i <= ~clk_i;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/86754567/queue/queue_tb.v:53: Define or directive not defined: \'`DEFASSERT\'\n `DEFASSERT(rp,2,to)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86754567/queue/queue_tb.v:53: syntax error, unexpected \'(\'\n `DEFASSERT(rp,2,to)\n ^~\n%Error: data/full_repos/permissive/86754567/queue/queue_tb.v:54: Define or directive not defined: \'`DEFASSERT\'\n `DEFASSERT(wp,2,to)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86754567/queue/queue_tb.v:55: Define or directive not defined: \'`DEFASSERT\'\n `DEFASSERT(room,3,to)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86754567/queue/queue_tb.v:57: Define or directive not defined: \'`DEFASSERT0\'\n `DEFASSERT0(empty,o)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86754567/queue/queue_tb.v:58: Define or directive not defined: \'`DEFASSERT0\'\n `DEFASSERT0(full,o)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86754567/queue/queue_tb.v:59: Define or directive not defined: \'`DEFASSERT\'\n `DEFASSERT(dat,7,o)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86754567/queue/queue_tb.v:68: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("wtf.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86754567/queue/queue_tb.v:69: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Cannot continue\n' | 304,349 | module | module queue_tb();
reg [11:0] story_to;
reg clk_i, reset_i;
reg [7:0] dat_i;
reg push_i, pop_i, oe_i;
wire [7:0] dat_o;
wire full_o, empty_o;
wire [2:0] rp_to;
wire [2:0] wp_to;
wire [3:0] room_to;
queue #(
.DEPTH_BITS(3),
.DATA_BITS(8)
) q (
.clk_i(clk_i),
.reset_i(reset_i),
.dat_i(dat_i),
.push_i(push_i),
.dat_o(dat_o),
.pop_i(pop_i),
.oe_i(oe_i),
.full_o(full_o),
.empty_o(empty_o),
.rp_to(rp_to),
.wp_to(wp_to),
.room_to(room_to)
);
always begin
#20 clk_i <= ~clk_i;
end
task story;
input [11:0] expected;
begin
story_to = expected;
end
endtask
`DEFASSERT(rp,2,to)
`DEFASSERT(wp,2,to)
`DEFASSERT(room,3,to)
`DEFASSERT0(empty,o)
`DEFASSERT0(full,o)
`DEFASSERT(dat,7,o)
task tick;
begin
wait(clk_i); wait(~clk_i);
end
endtask
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
{clk_i, reset_i, dat_i, push_i, pop_i, oe_i} <= 0;
story(0);
wait(~clk_i);
reset_i <= 1;
tick;
assert_rp(0);
assert_wp(0);
assert_room(8);
assert_dat(0);
assert_empty(1);
assert_full(0);
story(2);
reset_i <= 0;
push_i <= 1;
dat_i <= 8'hFF;
tick;
assert_room(7);
assert_wp(1);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(6);
assert_wp(2);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(5);
assert_wp(3);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(4);
assert_wp(4);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(3);
assert_wp(5);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(2);
assert_wp(6);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(1);
assert_wp(7);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(0);
assert_wp(0);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(1);
tick;
assert_room(0);
assert_wp(0);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(1);
story(3);
push_i <= 0;
pop_i <= 1;
oe_i <= 1;
tick;
assert_room(1);
assert_wp(0);
assert_rp(1);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(2);
assert_wp(0);
assert_rp(2);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(3);
assert_wp(0);
assert_rp(3);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(4);
assert_wp(0);
assert_rp(4);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(5);
assert_wp(0);
assert_rp(5);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(6);
assert_wp(0);
assert_rp(6);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(7);
assert_wp(0);
assert_rp(7);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(8);
assert_wp(0);
assert_rp(0);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(0);
assert_rp(0);
assert_dat(255);
assert_empty(1);
assert_full(0);
story(4);
dat_i <= 8'hAA;
push_i <= 1;
pop_i <= 1;
oe_i <= 1;
tick;
assert_room(8);
assert_wp(1);
assert_rp(1);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(2);
assert_rp(2);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(3);
assert_rp(3);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(4);
assert_rp(4);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(5);
assert_rp(5);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(6);
assert_rp(6);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(7);
assert_rp(7);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(0);
assert_rp(0);
assert_dat(8'hAA);
assert_empty(1);
assert_full(0);
$display("@I Done.");
$stop;
end
endmodule | module queue_tb(); |
reg [11:0] story_to;
reg clk_i, reset_i;
reg [7:0] dat_i;
reg push_i, pop_i, oe_i;
wire [7:0] dat_o;
wire full_o, empty_o;
wire [2:0] rp_to;
wire [2:0] wp_to;
wire [3:0] room_to;
queue #(
.DEPTH_BITS(3),
.DATA_BITS(8)
) q (
.clk_i(clk_i),
.reset_i(reset_i),
.dat_i(dat_i),
.push_i(push_i),
.dat_o(dat_o),
.pop_i(pop_i),
.oe_i(oe_i),
.full_o(full_o),
.empty_o(empty_o),
.rp_to(rp_to),
.wp_to(wp_to),
.room_to(room_to)
);
always begin
#20 clk_i <= ~clk_i;
end
task story;
input [11:0] expected;
begin
story_to = expected;
end
endtask
`DEFASSERT(rp,2,to)
`DEFASSERT(wp,2,to)
`DEFASSERT(room,3,to)
`DEFASSERT0(empty,o)
`DEFASSERT0(full,o)
`DEFASSERT(dat,7,o)
task tick;
begin
wait(clk_i); wait(~clk_i);
end
endtask
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
{clk_i, reset_i, dat_i, push_i, pop_i, oe_i} <= 0;
story(0);
wait(~clk_i);
reset_i <= 1;
tick;
assert_rp(0);
assert_wp(0);
assert_room(8);
assert_dat(0);
assert_empty(1);
assert_full(0);
story(2);
reset_i <= 0;
push_i <= 1;
dat_i <= 8'hFF;
tick;
assert_room(7);
assert_wp(1);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(6);
assert_wp(2);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(5);
assert_wp(3);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(4);
assert_wp(4);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(3);
assert_wp(5);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(2);
assert_wp(6);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(1);
assert_wp(7);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(0);
assert_wp(0);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(1);
tick;
assert_room(0);
assert_wp(0);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(1);
story(3);
push_i <= 0;
pop_i <= 1;
oe_i <= 1;
tick;
assert_room(1);
assert_wp(0);
assert_rp(1);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(2);
assert_wp(0);
assert_rp(2);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(3);
assert_wp(0);
assert_rp(3);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(4);
assert_wp(0);
assert_rp(4);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(5);
assert_wp(0);
assert_rp(5);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(6);
assert_wp(0);
assert_rp(6);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(7);
assert_wp(0);
assert_rp(7);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(8);
assert_wp(0);
assert_rp(0);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(0);
assert_rp(0);
assert_dat(255);
assert_empty(1);
assert_full(0);
story(4);
dat_i <= 8'hAA;
push_i <= 1;
pop_i <= 1;
oe_i <= 1;
tick;
assert_room(8);
assert_wp(1);
assert_rp(1);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(2);
assert_rp(2);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(3);
assert_rp(3);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(4);
assert_rp(4);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(5);
assert_rp(5);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(6);
assert_rp(6);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(7);
assert_rp(7);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(0);
assert_rp(0);
assert_dat(8'hAA);
assert_empty(1);
assert_full(0);
$display("@I Done.");
$stop;
end
endmodule | 0 |
139,140 | data/full_repos/permissive/86754567/serial/receiver.v | 86,754,567 | receiver.v | v | 115 | 73 | [] | [] | [] | [(23, 113)] | null | data/verilator_xmls/51d20966-a9e5-4123-af57-daf51c40ccc2.xml | null | 304,350 | module | module receiver(
input clk_i,
input reset_i,
input [5:0] bits_i,
input [BRW:0] baud_i,
input eedd_i,
input eedc_i,
input rxd_i,
input rxc_i,
output [SRW:0] dat_o,
output idle_o,
output sample_to
);
parameter SHIFT_REG_WIDTH = 16;
parameter BAUD_RATE_WIDTH = 32;
parameter SRW = SHIFT_REG_WIDTH - 1;
parameter BRW = BAUD_RATE_WIDTH - 1;
reg [SRW:0] shiftRegister;
reg [BRW:0] sampleCtr;
reg [5:0] bitsLeft;
reg d0, d1, c0, c1;
wire edgeDetected = (eedd_i & (d0 ^ d1)) | (eedc_i & (~c1 & c0));
wire sampleBit = ~idle_o && (sampleCtr == 0);
wire [SRW:0] shiftRegister_rev;
genvar i;
generate
for(i = 0; i <= SRW; i = i + 1) begin
assign shiftRegister_rev[i] = shiftRegister[SRW-i];
end
endgenerate
assign idle_o = (bitsLeft == 0);
assign dat_o = shiftRegister;
always @(posedge clk_i) begin
shiftRegister <= shiftRegister;
bitsLeft <= bitsLeft;
sampleCtr <= sampleCtr;
d1 <= d0;
d0 <= rxd_i;
c1 <= c0;
c0 <= rxc_i;
if(reset_i) begin
shiftRegister <= ~(0);
bitsLeft <= 0;
sampleCtr <= baud_i;
d0 <= 1;
d1 <= 1;
end
else begin
if(edgeDetected) begin
if(idle_o) begin
bitsLeft <= bits_i;
end
sampleCtr <= {1'b0, baud_i[BRW:1]};
end
else if(sampleBit) begin
sampleCtr <= baud_i;
bitsLeft <= bitsLeft - 1;
shiftRegister <= {d0, shiftRegister[SRW:1]};
end
else if(idle_o) begin
sampleCtr <= baud_i;
end
else begin
sampleCtr <= sampleCtr - 1;
end
end
end
assign sample_to = sampleBit;
endmodule | module receiver(
input clk_i,
input reset_i,
input [5:0] bits_i,
input [BRW:0] baud_i,
input eedd_i,
input eedc_i,
input rxd_i,
input rxc_i,
output [SRW:0] dat_o,
output idle_o,
output sample_to
); |
parameter SHIFT_REG_WIDTH = 16;
parameter BAUD_RATE_WIDTH = 32;
parameter SRW = SHIFT_REG_WIDTH - 1;
parameter BRW = BAUD_RATE_WIDTH - 1;
reg [SRW:0] shiftRegister;
reg [BRW:0] sampleCtr;
reg [5:0] bitsLeft;
reg d0, d1, c0, c1;
wire edgeDetected = (eedd_i & (d0 ^ d1)) | (eedc_i & (~c1 & c0));
wire sampleBit = ~idle_o && (sampleCtr == 0);
wire [SRW:0] shiftRegister_rev;
genvar i;
generate
for(i = 0; i <= SRW; i = i + 1) begin
assign shiftRegister_rev[i] = shiftRegister[SRW-i];
end
endgenerate
assign idle_o = (bitsLeft == 0);
assign dat_o = shiftRegister;
always @(posedge clk_i) begin
shiftRegister <= shiftRegister;
bitsLeft <= bitsLeft;
sampleCtr <= sampleCtr;
d1 <= d0;
d0 <= rxd_i;
c1 <= c0;
c0 <= rxc_i;
if(reset_i) begin
shiftRegister <= ~(0);
bitsLeft <= 0;
sampleCtr <= baud_i;
d0 <= 1;
d1 <= 1;
end
else begin
if(edgeDetected) begin
if(idle_o) begin
bitsLeft <= bits_i;
end
sampleCtr <= {1'b0, baud_i[BRW:1]};
end
else if(sampleBit) begin
sampleCtr <= baud_i;
bitsLeft <= bitsLeft - 1;
shiftRegister <= {d0, shiftRegister[SRW:1]};
end
else if(idle_o) begin
sampleCtr <= baud_i;
end
else begin
sampleCtr <= sampleCtr - 1;
end
end
end
assign sample_to = sampleBit;
endmodule | 0 |
139,141 | data/full_repos/permissive/86754567/serial/receiver_tb.v | 86,754,567 | receiver_tb.v | v | 126 | 88 | [] | [] | [] | null | line:6: before: "," | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #10 clk_i <= ~clk_i;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/86754567/serial/receiver_tb.v:61: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("receiver.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86754567/serial/receiver_tb.v:62: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86754567/serial/receiver_tb.v:67: Unsupported: wait statements\n wait(clk_i); wait(~clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/serial/receiver_tb.v:67: Unsupported: wait statements\n wait(clk_i); wait(~clk_i);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 0; #1000; assert_dat({1\'b0, ~(63\'h0)});\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 1; #1000; assert_dat({2\'b10, ~(62\'h0)});\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 0; #1000; assert_dat({3\'b010, ~(61\'h0)});\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 1; #1000; assert_dat({4\'b1010, ~(60\'h0)});\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 0; #1000; assert_dat({5\'b01010, ~(59\'h0)});\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 0; #1000; assert_dat({6\'b001010, ~(58\'h0)});\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 0; #1000; assert_dat({7\'b0001010, ~(57\'h0)});\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 0; #1000; assert_dat({8\'b00001010, ~(56\'h0)});\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 1; #1000; assert_dat({9\'b100001010, ~(55\'h0)});\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 0; #1000; assert_dat({10\'b0100001010, ~(54\'h0)});\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 1; #1000; assert_dat({11\'b10100001010, ~(53\'h0)});\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 0; #1000; assert_dat({12\'b010100001010, ~(52\'h0)});\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 1; #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 0; #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 1; #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 0; #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 0; #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 0; #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 0; #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 1; #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 0; #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 1; #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 1; #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 1; #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 1; #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n rxd_i <= 1; #1000;\n ^\n%Error: data/full_repos/permissive/86754567/serial/receiver_tb.v:104: Unsupported: wait statements\n wait(clk_i); wait(~clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/serial/receiver_tb.v:104: Unsupported: wait statements\n wait(clk_i); wait(~clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/serial/receiver_tb.v:105: Unsupported: wait statements\n wait(clk_i); wait(~clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/serial/receiver_tb.v:105: Unsupported: wait statements\n wait(clk_i); wait(~clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/serial/receiver_tb.v:108: Unsupported: wait statements\n wait(clk_i); wait(~clk_i);\n ^~~~\n%Error: data/full_repos/permissive/86754567/serial/receiver_tb.v:108: Unsupported: wait statements\n wait(clk_i); wait(~clk_i);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{1\'b0},{63{1\'b1}}}); assert_idle(0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{1\'b0},{63{1\'b1}}}); assert_idle(0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{2\'b0},{62{1\'b1}}}); assert_idle(0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{2\'b0},{62{1\'b1}}}); assert_idle(0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{3\'b0},{61{1\'b1}}}); assert_idle(0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{3\'b0},{61{1\'b1}}}); assert_idle(0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{4\'b0},{60{1\'b1}}}); assert_idle(0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{4\'b0},{60{1\'b1}}}); assert_idle(0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{5\'b0},{59{1\'b1}}}); assert_idle(0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{5\'b0},{59{1\'b1}}}); assert_idle(0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{6\'b0},{58{1\'b1}}}); assert_idle(0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{6\'b0},{58{1\'b1}}}); assert_idle(0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{7\'b0},{57{1\'b1}}}); assert_idle(0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{7\'b0},{57{1\'b1}}}); assert_idle(0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{8\'b0},{56{1\'b1}}}); assert_idle(0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{8\'b0},{56{1\'b1}}}); assert_idle(0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{9\'b0},{55{1\'b1}}}); assert_idle(0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{9\'b0},{55{1\'b1}}}); assert_idle(0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{10\'b0},{54{1\'b1}}}); assert_idle(0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{10\'b0},{54{1\'b1}}}); assert_idle(0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{11\'b0},{53{1\'b1}}}); assert_idle(1);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86754567/serial/receiver_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{11\'b0},{53{1\'b1}}}); assert_idle(1);\n ^\n%Error: Exiting due to 10 error(s), 49 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,351 | module | module receiver_tb();
reg [15:0] story;
reg clk_i = 0, reset_i = 0;
reg rxd_i = 1, rxc_i = 0;
reg rxreg_oe_i = 0, rxregr_oe_i = 0;
wire idle_o;
wire [63:0] dat_o;
wire sample_to;
receiver #(
.SHIFT_REG_WIDTH(64),
.BAUD_RATE_WIDTH(32)
) x(
.clk_i(clk_i),
.reset_i(reset_i),
.bits_i(6'd11),
.baud_i(32'd49),
.eedd_i(1'b1),
.eedc_i(1'b1),
.rxd_i(rxd_i),
.rxc_i(rxc_i),
.dat_o(dat_o),
.idle_o(idle_o),
.sample_to(sample_to)
);
always begin
#10 clk_i <= ~clk_i;
end
task assert_idle;
input expected;
begin
if (expected !== idle_o) begin
$display("@E %d idle_o Expected %d; got %d", story, expected, idle_o);
$stop;
end
end
endtask
task assert_dat;
input [63:0] expected;
begin
if (expected !== dat_o) begin
$display("@E %d dat_o Expected %064B; got %064B", story, expected, dat_o);
$stop;
end
end
endtask
initial begin
$dumpfile("receiver.vcd");
$dumpvars;
story <= 1;
reset_i <= 1;
wait(clk_i); wait(~clk_i);
reset_i <= 0;
assert_idle(1);
assert_dat(64'hFFFFFFFFFFFFFFFF);
rxd_i <= 0; #1000; assert_dat({1'b0, ~(63'h0)});
rxd_i <= 1; #1000; assert_dat({2'b10, ~(62'h0)});
rxd_i <= 0; #1000; assert_dat({3'b010, ~(61'h0)});
rxd_i <= 1; #1000; assert_dat({4'b1010, ~(60'h0)});
rxd_i <= 0; #1000; assert_dat({5'b01010, ~(59'h0)});
rxd_i <= 0; #1000; assert_dat({6'b001010, ~(58'h0)});
rxd_i <= 0; #1000; assert_dat({7'b0001010, ~(57'h0)});
rxd_i <= 0; #1000; assert_dat({8'b00001010, ~(56'h0)});
rxd_i <= 1; #1000; assert_dat({9'b100001010, ~(55'h0)});
rxd_i <= 0; #1000; assert_dat({10'b0100001010, ~(54'h0)});
rxd_i <= 1; #1000; assert_dat({11'b10100001010, ~(53'h0)});
rxd_i <= 0; #1000; assert_dat({12'b010100001010, ~(52'h0)});
rxd_i <= 1; #1000;
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 1; #1000;
rxd_i <= 1; #1000;
rxd_i <= 1; #1000;
rxd_i <= 1; #1000;
story <= 2;
reset_i <= 1;
wait(clk_i); wait(~clk_i);
wait(clk_i); wait(~clk_i);
reset_i <= 0;
rxd_i <= 0;
wait(clk_i); wait(~clk_i);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{1'b0},{63{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{2'b0},{62{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{3'b0},{61{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{4'b0},{60{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{5'b0},{59{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{6'b0},{58{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{7'b0},{57{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{8'b0},{56{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{9'b0},{55{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{10'b0},{54{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{11'b0},{53{1'b1}}}); assert_idle(1);
$display("@I Done.");
$stop;
end
endmodule | module receiver_tb(); |
reg [15:0] story;
reg clk_i = 0, reset_i = 0;
reg rxd_i = 1, rxc_i = 0;
reg rxreg_oe_i = 0, rxregr_oe_i = 0;
wire idle_o;
wire [63:0] dat_o;
wire sample_to;
receiver #(
.SHIFT_REG_WIDTH(64),
.BAUD_RATE_WIDTH(32)
) x(
.clk_i(clk_i),
.reset_i(reset_i),
.bits_i(6'd11),
.baud_i(32'd49),
.eedd_i(1'b1),
.eedc_i(1'b1),
.rxd_i(rxd_i),
.rxc_i(rxc_i),
.dat_o(dat_o),
.idle_o(idle_o),
.sample_to(sample_to)
);
always begin
#10 clk_i <= ~clk_i;
end
task assert_idle;
input expected;
begin
if (expected !== idle_o) begin
$display("@E %d idle_o Expected %d; got %d", story, expected, idle_o);
$stop;
end
end
endtask
task assert_dat;
input [63:0] expected;
begin
if (expected !== dat_o) begin
$display("@E %d dat_o Expected %064B; got %064B", story, expected, dat_o);
$stop;
end
end
endtask
initial begin
$dumpfile("receiver.vcd");
$dumpvars;
story <= 1;
reset_i <= 1;
wait(clk_i); wait(~clk_i);
reset_i <= 0;
assert_idle(1);
assert_dat(64'hFFFFFFFFFFFFFFFF);
rxd_i <= 0; #1000; assert_dat({1'b0, ~(63'h0)});
rxd_i <= 1; #1000; assert_dat({2'b10, ~(62'h0)});
rxd_i <= 0; #1000; assert_dat({3'b010, ~(61'h0)});
rxd_i <= 1; #1000; assert_dat({4'b1010, ~(60'h0)});
rxd_i <= 0; #1000; assert_dat({5'b01010, ~(59'h0)});
rxd_i <= 0; #1000; assert_dat({6'b001010, ~(58'h0)});
rxd_i <= 0; #1000; assert_dat({7'b0001010, ~(57'h0)});
rxd_i <= 0; #1000; assert_dat({8'b00001010, ~(56'h0)});
rxd_i <= 1; #1000; assert_dat({9'b100001010, ~(55'h0)});
rxd_i <= 0; #1000; assert_dat({10'b0100001010, ~(54'h0)});
rxd_i <= 1; #1000; assert_dat({11'b10100001010, ~(53'h0)});
rxd_i <= 0; #1000; assert_dat({12'b010100001010, ~(52'h0)});
rxd_i <= 1; #1000;
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 1; #1000;
rxd_i <= 1; #1000;
rxd_i <= 1; #1000;
rxd_i <= 1; #1000;
story <= 2;
reset_i <= 1;
wait(clk_i); wait(~clk_i);
wait(clk_i); wait(~clk_i);
reset_i <= 0;
rxd_i <= 0;
wait(clk_i); wait(~clk_i);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{1'b0},{63{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{2'b0},{62{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{3'b0},{61{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{4'b0},{60{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{5'b0},{59{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{6'b0},{58{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{7'b0},{57{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{8'b0},{56{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{9'b0},{55{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{10'b0},{54{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{11'b0},{53{1'b1}}}); assert_idle(1);
$display("@I Done.");
$stop;
end
endmodule | 0 |
139,142 | data/full_repos/permissive/86754567/wishbone/pipelined/master.v | 86,754,567 | master.v | v | 177 | 95 | [] | [] | [] | [(77, 176)] | null | null | 1: b'%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master.v:4: Cannot find include file: ipl_config.vh\n`include "ipl_config.vh" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86754567/wishbone/pipelined,data/full_repos/permissive/86754567/ipl_config.vh\n data/full_repos/permissive/86754567/wishbone/pipelined,data/full_repos/permissive/86754567/ipl_config.vh.v\n data/full_repos/permissive/86754567/wishbone/pipelined,data/full_repos/permissive/86754567/ipl_config.vh.sv\n ipl_config.vh\n ipl_config.vh.v\n ipl_config.vh.sv\n obj_dir/ipl_config.vh\n obj_dir/ipl_config.vh.v\n obj_dir/ipl_config.vh.sv\n%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master.v:90: Define or directive not defined: \'`IPL_READ_ADDR\'\n parameter IPL_READ_ADDR = `IPL_READ_ADDR;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master.v:90: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter IPL_READ_ADDR = `IPL_READ_ADDR;\n ^\n%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master.v:91: Define or directive not defined: \'`IPL_WRITE_ADDR\'\n parameter IPL_WRITE_ADDR = `IPL_WRITE_ADDR;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master.v:91: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter IPL_WRITE_ADDR = `IPL_WRITE_ADDR;\n ^\n%Error: Exiting due to 5 error(s)\n' | 304,353 | module | module master(
input clk_i,
input reset_i,
input dreq_i,
output dack_o,
output [AW:0] adr_o,
output cyc_o,
output stb_o,
output we_o,
input ack_i
);
parameter ADDR_WIDTH = 16;
parameter IPL_READ_ADDR = `IPL_READ_ADDR;
parameter IPL_WRITE_ADDR = `IPL_WRITE_ADDR;
parameter AW = ADDR_WIDTH - 1;
reg [AW:0] adr_o;
reg stb_o;
reg we_o;
reg [AW:0] rd_adr, wr_adr;
reg rd_cyc, wr_cyc;
reg dack_o;
assign cyc_o = rd_cyc | wr_cyc;
always @(posedge clk_i) begin
adr_o <= 0;
stb_o <= 0;
we_o <= 0;
rd_cyc <= rd_cyc;
wr_cyc <= wr_cyc;
dack_o <= 0;
if(reset_i) begin
rd_adr <= IPL_READ_ADDR;
wr_adr <= IPL_WRITE_ADDR;
rd_cyc <= 0;
wr_cyc <= 0;
end
else begin
if(dreq_i && ~cyc_o) begin
adr_o <= rd_adr;
stb_o <= 1;
rd_cyc <= 1;
dack_o <= 1;
end
if(rd_cyc && ack_i) begin
rd_cyc <= 0;
wr_cyc <= 1;
adr_o <= wr_adr;
stb_o <= 1;
we_o <= 1;
end
if(wr_cyc && ack_i) begin
wr_cyc <= 0;
if(dreq_i) begin
adr_o <= rd_adr;
stb_o <= 1;
rd_cyc <= 1;
dack_o <= 1;
end
end
end
end
endmodule | module master(
input clk_i,
input reset_i,
input dreq_i,
output dack_o,
output [AW:0] adr_o,
output cyc_o,
output stb_o,
output we_o,
input ack_i
); |
parameter ADDR_WIDTH = 16;
parameter IPL_READ_ADDR = `IPL_READ_ADDR;
parameter IPL_WRITE_ADDR = `IPL_WRITE_ADDR;
parameter AW = ADDR_WIDTH - 1;
reg [AW:0] adr_o;
reg stb_o;
reg we_o;
reg [AW:0] rd_adr, wr_adr;
reg rd_cyc, wr_cyc;
reg dack_o;
assign cyc_o = rd_cyc | wr_cyc;
always @(posedge clk_i) begin
adr_o <= 0;
stb_o <= 0;
we_o <= 0;
rd_cyc <= rd_cyc;
wr_cyc <= wr_cyc;
dack_o <= 0;
if(reset_i) begin
rd_adr <= IPL_READ_ADDR;
wr_adr <= IPL_WRITE_ADDR;
rd_cyc <= 0;
wr_cyc <= 0;
end
else begin
if(dreq_i && ~cyc_o) begin
adr_o <= rd_adr;
stb_o <= 1;
rd_cyc <= 1;
dack_o <= 1;
end
if(rd_cyc && ack_i) begin
rd_cyc <= 0;
wr_cyc <= 1;
adr_o <= wr_adr;
stb_o <= 1;
we_o <= 1;
end
if(wr_cyc && ack_i) begin
wr_cyc <= 0;
if(dreq_i) begin
adr_o <= rd_adr;
stb_o <= 1;
rd_cyc <= 1;
dack_o <= 1;
end
end
end
end
endmodule | 0 |
139,143 | data/full_repos/permissive/86754567/wishbone/pipelined/master_tb.v | 86,754,567 | master_tb.v | v | 198 | 89 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master_tb.v:4: Cannot find include file: ipl_config.vh\n`include "ipl_config.vh" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86754567/wishbone/pipelined,data/full_repos/permissive/86754567/ipl_config.vh\n data/full_repos/permissive/86754567/wishbone/pipelined,data/full_repos/permissive/86754567/ipl_config.vh.v\n data/full_repos/permissive/86754567/wishbone/pipelined,data/full_repos/permissive/86754567/ipl_config.vh.sv\n ipl_config.vh\n ipl_config.vh.v\n ipl_config.vh.sv\n obj_dir/ipl_config.vh\n obj_dir/ipl_config.vh.v\n obj_dir/ipl_config.vh.sv\n%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master_tb.v:24: Cannot find include file: asserts.vh\n`include "asserts.vh" \n ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/86754567/wishbone/pipelined/master_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #5 clk_i <= ~clk_i;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master_tb.v:61: Define or directive not defined: \'`STANDARD_FAULT\'\n `STANDARD_FAULT\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master_tb.v:63: Define or directive not defined: \'`DEFASSERT\'\n `DEFASSERT(adr, AW, o)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master_tb.v:63: syntax error, unexpected \'(\'\n `DEFASSERT(adr, AW, o)\n ^~~\n%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master_tb.v:64: Define or directive not defined: \'`DEFASSERT0\'\n `DEFASSERT0(cyc, o)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master_tb.v:65: Define or directive not defined: \'`DEFASSERT0\'\n `DEFASSERT0(stb, o)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master_tb.v:66: Define or directive not defined: \'`DEFASSERT0\'\n `DEFASSERT0(we, o)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master_tb.v:67: Define or directive not defined: \'`DEFASSERT0\'\n `DEFASSERT0(dack, o)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master_tb.v:70: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("master.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master_tb.v:71: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master_tb.v:99: Define or directive not defined: \'`IPL_READ_ADDR\'\n assert_adr(`IPL_READ_ADDR);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master_tb.v:124: Define or directive not defined: \'`IPL_WRITE_ADDR\'\n assert_adr(`IPL_WRITE_ADDR);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master_tb.v:165: Define or directive not defined: \'`IPL_READ_ADDR\'\n assert_adr(`IPL_READ_ADDR);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master_tb.v:172: Define or directive not defined: \'`IPL_WRITE_ADDR\'\n assert_adr(`IPL_WRITE_ADDR);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master_tb.v:179: Define or directive not defined: \'`IPL_READ_ADDR\'\n assert_adr(`IPL_READ_ADDR);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86754567/wishbone/pipelined/master_tb.v:187: Define or directive not defined: \'`IPL_WRITE_ADDR\'\n assert_adr(`IPL_WRITE_ADDR);\n ^~~~~~~~~~~~~~~\n%Error: Cannot continue\n' | 304,354 | module | module master_tb();
parameter ADDR_WIDTH = 16;
parameter AW = ADDR_WIDTH - 1;
reg [11:0] story_to;
reg clk_i, reset_i, fault_to;
wire [AW:0] adr_o;
wire cyc_o, stb_o, we_o;
reg ack_i;
reg dreq_i;
wire dack_o;
always begin
#5 clk_i <= ~clk_i;
end
master #(
.ADDR_WIDTH(ADDR_WIDTH)
) m(
.clk_i(clk_i),
.reset_i(reset_i),
.dreq_i(dreq_i),
.dack_o(dack_o),
.adr_o(adr_o),
.cyc_o(cyc_o),
.stb_o(stb_o),
.we_o(we_o),
.ack_i(ack_i)
);
`STANDARD_FAULT
`DEFASSERT(adr, AW, o)
`DEFASSERT0(cyc, o)
`DEFASSERT0(stb, o)
`DEFASSERT0(we, o)
`DEFASSERT0(dack, o)
initial begin
$dumpfile("master.vcd");
$dumpvars;
{ack_i, dreq_i, clk_i, reset_i, fault_to} <= 0;
wait(~clk_i); wait(clk_i);
reset_i <= 1;
wait(~clk_i); wait(clk_i);
reset_i <= 0;
story_to <= 12'h000;
wait(~clk_i); wait(clk_i); #1;
assert_adr(0);
assert_cyc(0);
assert_stb(0);
assert_we(0);
assert_dack(0);
dreq_i <= 1;
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(1);
assert_we(0);
assert_adr(`IPL_READ_ADDR);
assert_dack(1);
dreq_i <= 0;
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(0);
assert_we(0);
assert_adr(0);
assert_dack(0);
ack_i <= 1;
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(1);
assert_we(1);
assert_adr(`IPL_WRITE_ADDR);
assert_dack(0);
ack_i <= 0;
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(0);
assert_we(0);
assert_adr(0);
assert_dack(0);
ack_i <= 1;
wait(~clk_i); wait(clk_i); #1;
assert_cyc(0);
assert_stb(0);
assert_we(0);
assert_adr(0);
assert_dack(0);
ack_i <= 0;
wait(~clk_i); wait(clk_i);
dreq_i <= 1;
wait(~clk_i); wait(clk_i); #1;
ack_i <= 1;
assert_cyc(1);
assert_stb(1);
assert_we(0);
assert_adr(`IPL_READ_ADDR);
assert_dack(1);
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(1);
assert_we(1);
assert_adr(`IPL_WRITE_ADDR);
assert_dack(0);
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(1);
assert_we(0);
assert_adr(`IPL_READ_ADDR);
assert_dack(1);
wait(~clk_i); wait(clk_i); #1;
dreq_i <= 0;
assert_cyc(1);
assert_stb(1);
assert_we(1);
assert_adr(`IPL_WRITE_ADDR);
assert_dack(0);
wait(~clk_i); wait(clk_i);
ack_i <= 0;
$display("@I Done.");
onFault;
end
endmodule | module master_tb(); |
parameter ADDR_WIDTH = 16;
parameter AW = ADDR_WIDTH - 1;
reg [11:0] story_to;
reg clk_i, reset_i, fault_to;
wire [AW:0] adr_o;
wire cyc_o, stb_o, we_o;
reg ack_i;
reg dreq_i;
wire dack_o;
always begin
#5 clk_i <= ~clk_i;
end
master #(
.ADDR_WIDTH(ADDR_WIDTH)
) m(
.clk_i(clk_i),
.reset_i(reset_i),
.dreq_i(dreq_i),
.dack_o(dack_o),
.adr_o(adr_o),
.cyc_o(cyc_o),
.stb_o(stb_o),
.we_o(we_o),
.ack_i(ack_i)
);
`STANDARD_FAULT
`DEFASSERT(adr, AW, o)
`DEFASSERT0(cyc, o)
`DEFASSERT0(stb, o)
`DEFASSERT0(we, o)
`DEFASSERT0(dack, o)
initial begin
$dumpfile("master.vcd");
$dumpvars;
{ack_i, dreq_i, clk_i, reset_i, fault_to} <= 0;
wait(~clk_i); wait(clk_i);
reset_i <= 1;
wait(~clk_i); wait(clk_i);
reset_i <= 0;
story_to <= 12'h000;
wait(~clk_i); wait(clk_i); #1;
assert_adr(0);
assert_cyc(0);
assert_stb(0);
assert_we(0);
assert_dack(0);
dreq_i <= 1;
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(1);
assert_we(0);
assert_adr(`IPL_READ_ADDR);
assert_dack(1);
dreq_i <= 0;
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(0);
assert_we(0);
assert_adr(0);
assert_dack(0);
ack_i <= 1;
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(1);
assert_we(1);
assert_adr(`IPL_WRITE_ADDR);
assert_dack(0);
ack_i <= 0;
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(0);
assert_we(0);
assert_adr(0);
assert_dack(0);
ack_i <= 1;
wait(~clk_i); wait(clk_i); #1;
assert_cyc(0);
assert_stb(0);
assert_we(0);
assert_adr(0);
assert_dack(0);
ack_i <= 0;
wait(~clk_i); wait(clk_i);
dreq_i <= 1;
wait(~clk_i); wait(clk_i); #1;
ack_i <= 1;
assert_cyc(1);
assert_stb(1);
assert_we(0);
assert_adr(`IPL_READ_ADDR);
assert_dack(1);
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(1);
assert_we(1);
assert_adr(`IPL_WRITE_ADDR);
assert_dack(0);
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(1);
assert_we(0);
assert_adr(`IPL_READ_ADDR);
assert_dack(1);
wait(~clk_i); wait(clk_i); #1;
dreq_i <= 0;
assert_cyc(1);
assert_stb(1);
assert_we(1);
assert_adr(`IPL_WRITE_ADDR);
assert_dack(0);
wait(~clk_i); wait(clk_i);
ack_i <= 0;
$display("@I Done.");
onFault;
end
endmodule | 0 |
139,145 | data/full_repos/permissive/86852558/src/adc_standalone.v | 86,852,558 | adc_standalone.v | v | 90 | 109 | [] | [] | [] | [(58, 143)] | null | null | 1: b'%Error: data/full_repos/permissive/86852558/src/adc_standalone.v:3: Cannot find include file: mfp_adc_max10_core.vh\n`include "mfp_adc_max10_core.vh" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86852558/src,data/full_repos/permissive/86852558/mfp_adc_max10_core.vh\n data/full_repos/permissive/86852558/src,data/full_repos/permissive/86852558/mfp_adc_max10_core.vh.v\n data/full_repos/permissive/86852558/src,data/full_repos/permissive/86852558/mfp_adc_max10_core.vh.sv\n mfp_adc_max10_core.vh\n mfp_adc_max10_core.vh.v\n mfp_adc_max10_core.vh.sv\n obj_dir/mfp_adc_max10_core.vh\n obj_dir/mfp_adc_max10_core.vh.v\n obj_dir/mfp_adc_max10_core.vh.sv\n%Error: data/full_repos/permissive/86852558/src/adc_standalone.v:22: Define or directive not defined: \'`ADC_ADDR_WIDTH\'\n input [ `ADC_ADDR_WIDTH - 1 : 0 ] RADDR,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/adc_standalone.v:26: Define or directive not defined: \'`ADC_ADDR_WIDTH\'\n reg [ `ADC_ADDR_WIDTH - 1 : 0 ] write_addr;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/adc_standalone.v:49: Define or directive not defined: \'`ADC_CELL_1\'\n ( (1\'b1 << `ADC_CELL_1) | (1\'b1 << `ADC_CELL_2) \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/adc_standalone.v:49: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n ( (1\'b1 << `ADC_CELL_1) | (1\'b1 << `ADC_CELL_2) \n ^\n%Error: data/full_repos/permissive/86852558/src/adc_standalone.v:49: Define or directive not defined: \'`ADC_CELL_2\'\n ( (1\'b1 << `ADC_CELL_1) | (1\'b1 << `ADC_CELL_2) \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/adc_standalone.v:50: Define or directive not defined: \'`ADC_CELL_3\'\n | (1\'b1 << `ADC_CELL_3) | (1\'b1 << `ADC_CELL_4) \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/adc_standalone.v:50: Define or directive not defined: \'`ADC_CELL_4\'\n | (1\'b1 << `ADC_CELL_3) | (1\'b1 << `ADC_CELL_4) \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/adc_standalone.v:51: Define or directive not defined: \'`ADC_CELL_5\'\n | (1\'b1 << `ADC_CELL_5) | (1\'b1 << `ADC_CELL_6) \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/adc_standalone.v:51: Define or directive not defined: \'`ADC_CELL_6\'\n | (1\'b1 << `ADC_CELL_5) | (1\'b1 << `ADC_CELL_6) \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/adc_standalone.v:52: Define or directive not defined: \'`ADC_CELL_T\'\n | (1\'b1 << `ADC_CELL_T) );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/adc_standalone.v:55: Define or directive not defined: \'`ADC_FIELD_ADCS_EN\'\n ( (1\'b1 << `ADC_FIELD_ADCS_EN) \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/adc_standalone.v:55: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n ( (1\'b1 << `ADC_FIELD_ADCS_EN) \n ^\n%Error: data/full_repos/permissive/86852558/src/adc_standalone.v:56: Define or directive not defined: \'`ADC_FIELD_ADCS_SC\'\n | (1\'b1 << `ADC_FIELD_ADCS_SC) \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/adc_standalone.v:57: Define or directive not defined: \'`ADC_FIELD_ADCS_FR\'\n | (1\'b1 << `ADC_FIELD_ADCS_FR) ); \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/adc_standalone.v:61: Define or directive not defined: \'`ADC_REG_ADMSK\'\n S_INIT_MASK : begin write_addr = `ADC_REG_ADMSK; write_data = ADC_MASK; write_enable = 1\'b1; end\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/adc_standalone.v:61: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n S_INIT_MASK : begin write_addr = `ADC_REG_ADMSK; write_data = ADC_MASK; write_enable = 1\'b1; end\n ^\n%Error: data/full_repos/permissive/86852558/src/adc_standalone.v:62: Define or directive not defined: \'`ADC_REG_ADCS\'\n S_INIT_MODE : begin write_addr = `ADC_REG_ADCS; write_data = ADC_MODE; write_enable = 1\'b1; end\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/adc_standalone.v:62: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n S_INIT_MODE : begin write_addr = `ADC_REG_ADCS; write_data = ADC_MODE; write_enable = 1\'b1; end\n ^\n%Error: Exiting due to 19 error(s)\n' | 304,358 | module | module adc_standalone
(
input CLK,
input RESETn,
output ADC_C_Valid,
output [ 4:0 ] ADC_C_Channel,
output ADC_C_SOP,
output ADC_C_EOP,
input ADC_C_Ready,
input ADC_R_Valid,
input [ 4:0 ] ADC_R_Channel,
input [ 11:0 ] ADC_R_Data,
input ADC_R_SOP,
input ADC_R_EOP,
input [ `ADC_ADDR_WIDTH - 1 : 0 ] RADDR,
output [ 31 : 0 ] RDATA
);
reg [ `ADC_ADDR_WIDTH - 1 : 0 ] write_addr;
reg [ 31 : 0 ] write_data;
reg write_enable;
parameter S_INIT = 0,
S_INIT_MASK = 1,
S_INIT_MODE = 2,
S_IDLE = 3;
wire [ 2 : 0 ] State;
reg [ 2 : 0 ] Next;
mfp_register_r #(.WIDTH(3), .RESET(S_INIT)) r_FSM_State (CLK, RESETn, Next, 1'b1, State );
always @(*) begin
case (State)
S_INIT : Next = S_INIT_MASK;
S_INIT_MASK : Next = S_INIT_MODE;
S_INIT_MODE : Next = S_IDLE;
S_IDLE : Next = S_IDLE;
endcase
end
parameter ADC_MASK = 32'b0 |
( (1'b1 << `ADC_CELL_1) | (1'b1 << `ADC_CELL_2)
| (1'b1 << `ADC_CELL_3) | (1'b1 << `ADC_CELL_4)
| (1'b1 << `ADC_CELL_5) | (1'b1 << `ADC_CELL_6)
| (1'b1 << `ADC_CELL_T) );
parameter ADC_MODE = 32'b0 |
( (1'b1 << `ADC_FIELD_ADCS_EN)
| (1'b1 << `ADC_FIELD_ADCS_SC)
| (1'b1 << `ADC_FIELD_ADCS_FR) );
always @(*) begin
case (State)
S_INIT_MASK : begin write_addr = `ADC_REG_ADMSK; write_data = ADC_MASK; write_enable = 1'b1; end
S_INIT_MODE : begin write_addr = `ADC_REG_ADCS; write_data = ADC_MODE; write_enable = 1'b1; end
default : begin write_addr = 4'b0; write_data = 32'b0; write_enable = 1'b0; end
endcase
end
mfp_adc_max10_core adc_core
(
.CLK ( CLK ),
.RESETn ( RESETn ),
.read_addr ( RADDR ),
.read_data ( RDATA ),
.write_addr ( write_addr ),
.write_data ( write_data ),
.write_enable ( write_enable ),
.ADC_C_Valid ( ADC_C_Valid ),
.ADC_C_Channel ( ADC_C_Channel ),
.ADC_C_SOP ( ADC_C_SOP ),
.ADC_C_EOP ( ADC_C_EOP ),
.ADC_C_Ready ( ADC_C_Ready ),
.ADC_R_Valid ( ADC_R_Valid ),
.ADC_R_Channel ( ADC_R_Channel ),
.ADC_R_Data ( ADC_R_Data ),
.ADC_R_SOP ( ADC_R_SOP ),
.ADC_R_EOP ( ADC_R_EOP ),
.ADC_Trigger ( ADC_Trigger ),
.ADC_Interrupt ( ADC_Interrupt )
);
endmodule | module adc_standalone
(
input CLK,
input RESETn,
output ADC_C_Valid,
output [ 4:0 ] ADC_C_Channel,
output ADC_C_SOP,
output ADC_C_EOP,
input ADC_C_Ready,
input ADC_R_Valid,
input [ 4:0 ] ADC_R_Channel,
input [ 11:0 ] ADC_R_Data,
input ADC_R_SOP,
input ADC_R_EOP,
input [ `ADC_ADDR_WIDTH - 1 : 0 ] RADDR,
output [ 31 : 0 ] RDATA
); |
reg [ `ADC_ADDR_WIDTH - 1 : 0 ] write_addr;
reg [ 31 : 0 ] write_data;
reg write_enable;
parameter S_INIT = 0,
S_INIT_MASK = 1,
S_INIT_MODE = 2,
S_IDLE = 3;
wire [ 2 : 0 ] State;
reg [ 2 : 0 ] Next;
mfp_register_r #(.WIDTH(3), .RESET(S_INIT)) r_FSM_State (CLK, RESETn, Next, 1'b1, State );
always @(*) begin
case (State)
S_INIT : Next = S_INIT_MASK;
S_INIT_MASK : Next = S_INIT_MODE;
S_INIT_MODE : Next = S_IDLE;
S_IDLE : Next = S_IDLE;
endcase
end
parameter ADC_MASK = 32'b0 |
( (1'b1 << `ADC_CELL_1) | (1'b1 << `ADC_CELL_2)
| (1'b1 << `ADC_CELL_3) | (1'b1 << `ADC_CELL_4)
| (1'b1 << `ADC_CELL_5) | (1'b1 << `ADC_CELL_6)
| (1'b1 << `ADC_CELL_T) );
parameter ADC_MODE = 32'b0 |
( (1'b1 << `ADC_FIELD_ADCS_EN)
| (1'b1 << `ADC_FIELD_ADCS_SC)
| (1'b1 << `ADC_FIELD_ADCS_FR) );
always @(*) begin
case (State)
S_INIT_MASK : begin write_addr = `ADC_REG_ADMSK; write_data = ADC_MASK; write_enable = 1'b1; end
S_INIT_MODE : begin write_addr = `ADC_REG_ADCS; write_data = ADC_MODE; write_enable = 1'b1; end
default : begin write_addr = 4'b0; write_data = 32'b0; write_enable = 1'b0; end
endcase
end
mfp_adc_max10_core adc_core
(
.CLK ( CLK ),
.RESETn ( RESETn ),
.read_addr ( RADDR ),
.read_data ( RDATA ),
.write_addr ( write_addr ),
.write_data ( write_data ),
.write_enable ( write_enable ),
.ADC_C_Valid ( ADC_C_Valid ),
.ADC_C_Channel ( ADC_C_Channel ),
.ADC_C_SOP ( ADC_C_SOP ),
.ADC_C_EOP ( ADC_C_EOP ),
.ADC_C_Ready ( ADC_C_Ready ),
.ADC_R_Valid ( ADC_R_Valid ),
.ADC_R_Channel ( ADC_R_Channel ),
.ADC_R_Data ( ADC_R_Data ),
.ADC_R_SOP ( ADC_R_SOP ),
.ADC_R_EOP ( ADC_R_EOP ),
.ADC_Trigger ( ADC_Trigger ),
.ADC_Interrupt ( ADC_Interrupt )
);
endmodule | 2 |
139,146 | data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v | 86,852,558 | mfp_adc_max10_core.v | v | 245 | 121 | [] | [] | [] | [(61, 264), (266, 297)] | null | null | 1: b'%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:6: Cannot find include file: mfp_adc_max10_core.vh\n`include "mfp_adc_max10_core.vh" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86852558/src,data/full_repos/permissive/86852558/mfp_adc_max10_core.vh\n data/full_repos/permissive/86852558/src,data/full_repos/permissive/86852558/mfp_adc_max10_core.vh.v\n data/full_repos/permissive/86852558/src,data/full_repos/permissive/86852558/mfp_adc_max10_core.vh.sv\n mfp_adc_max10_core.vh\n mfp_adc_max10_core.vh.v\n mfp_adc_max10_core.vh.sv\n obj_dir/mfp_adc_max10_core.vh\n obj_dir/mfp_adc_max10_core.vh.v\n obj_dir/mfp_adc_max10_core.vh.sv\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:14: Define or directive not defined: \'`ADC_ADDR_WIDTH\'\n input [ `ADC_ADDR_WIDTH - 1 : 0 ] read_addr,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:16: Define or directive not defined: \'`ADC_ADDR_WIDTH\'\n input [ `ADC_ADDR_WIDTH - 1 : 0 ] write_addr,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:38: Define or directive not defined: \'`ADC_CH_COUNT\'\n wire [ `ADC_CH_COUNT - 1 : 0 ] ADC_wr;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:39: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n wire [ `ADC_DATA_WIDTH - 1 : 0 ] ADC [ `ADC_CH_COUNT - 1 : 0 ];\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:39: Define or directive not defined: \'`ADC_CH_COUNT\'\n wire [ `ADC_DATA_WIDTH - 1 : 0 ] ADC [ `ADC_CH_COUNT - 1 : 0 ];\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:41: Define or directive not defined: \'`ADC_CELL_0\'\n assign ADC_wr[`ADC_CELL_0] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_0;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:41: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ADC_wr[`ADC_CELL_0] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_0;\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:41: Define or directive not defined: \'`ADC_CH_0\'\n assign ADC_wr[`ADC_CELL_0] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_0;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:42: Define or directive not defined: \'`ADC_CELL_1\'\n assign ADC_wr[`ADC_CELL_1] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_1;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:42: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ADC_wr[`ADC_CELL_1] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_1;\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:42: Define or directive not defined: \'`ADC_CH_1\'\n assign ADC_wr[`ADC_CELL_1] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_1;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:43: Define or directive not defined: \'`ADC_CELL_2\'\n assign ADC_wr[`ADC_CELL_2] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_2;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:43: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ADC_wr[`ADC_CELL_2] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_2;\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:43: Define or directive not defined: \'`ADC_CH_2\'\n assign ADC_wr[`ADC_CELL_2] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_2;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:44: Define or directive not defined: \'`ADC_CELL_3\'\n assign ADC_wr[`ADC_CELL_3] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_3;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:44: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ADC_wr[`ADC_CELL_3] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_3;\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:44: Define or directive not defined: \'`ADC_CH_3\'\n assign ADC_wr[`ADC_CELL_3] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_3;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:45: Define or directive not defined: \'`ADC_CELL_4\'\n assign ADC_wr[`ADC_CELL_4] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_4;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:45: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ADC_wr[`ADC_CELL_4] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_4;\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:45: Define or directive not defined: \'`ADC_CH_4\'\n assign ADC_wr[`ADC_CELL_4] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_4;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:46: Define or directive not defined: \'`ADC_CELL_5\'\n assign ADC_wr[`ADC_CELL_5] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_5;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:46: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ADC_wr[`ADC_CELL_5] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_5;\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:46: Define or directive not defined: \'`ADC_CH_5\'\n assign ADC_wr[`ADC_CELL_5] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_5;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:47: Define or directive not defined: \'`ADC_CELL_6\'\n assign ADC_wr[`ADC_CELL_6] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_6;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:47: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ADC_wr[`ADC_CELL_6] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_6;\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:47: Define or directive not defined: \'`ADC_CH_6\'\n assign ADC_wr[`ADC_CELL_6] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_6;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:48: Define or directive not defined: \'`ADC_CELL_7\'\n assign ADC_wr[`ADC_CELL_7] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_7;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:48: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ADC_wr[`ADC_CELL_7] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_7;\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:48: Define or directive not defined: \'`ADC_CH_7\'\n assign ADC_wr[`ADC_CELL_7] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_7;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:49: Define or directive not defined: \'`ADC_CELL_8\'\n assign ADC_wr[`ADC_CELL_8] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_8;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:49: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ADC_wr[`ADC_CELL_8] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_8;\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:49: Define or directive not defined: \'`ADC_CH_8\'\n assign ADC_wr[`ADC_CELL_8] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_8;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:50: Define or directive not defined: \'`ADC_CELL_T\'\n assign ADC_wr[`ADC_CELL_T] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_T;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:50: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ADC_wr[`ADC_CELL_T] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_T;\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:50: Define or directive not defined: \'`ADC_CH_T\'\n assign ADC_wr[`ADC_CELL_T] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_T;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:52: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC0 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_0], ADC[`ADC_CELL_0] );\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:52: Define or directive not defined: \'`ADC_CELL_0\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC0 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_0], ADC[`ADC_CELL_0] );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:52: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC0 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_0], ADC[`ADC_CELL_0] );\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:52: Define or directive not defined: \'`ADC_CELL_0\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC0 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_0], ADC[`ADC_CELL_0] );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:53: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC1 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_1], ADC[`ADC_CELL_1] );\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:53: Define or directive not defined: \'`ADC_CELL_1\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC1 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_1], ADC[`ADC_CELL_1] );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:53: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC1 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_1], ADC[`ADC_CELL_1] );\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:53: Define or directive not defined: \'`ADC_CELL_1\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC1 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_1], ADC[`ADC_CELL_1] );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:54: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC2 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_2], ADC[`ADC_CELL_2] );\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:54: Define or directive not defined: \'`ADC_CELL_2\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC2 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_2], ADC[`ADC_CELL_2] );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:54: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC2 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_2], ADC[`ADC_CELL_2] );\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:54: Define or directive not defined: \'`ADC_CELL_2\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC2 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_2], ADC[`ADC_CELL_2] );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:55: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC3 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_3], ADC[`ADC_CELL_3] );\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:55: Define or directive not defined: \'`ADC_CELL_3\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC3 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_3], ADC[`ADC_CELL_3] );\n ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 304,359 | module | module mfp_adc_max10_core
(
input CLK,
input RESETn,
input [ `ADC_ADDR_WIDTH - 1 : 0 ] read_addr,
output reg [ 31 : 0 ] read_data,
input [ `ADC_ADDR_WIDTH - 1 : 0 ] write_addr,
input [ 31 : 0 ] write_data,
input write_enable,
output ADC_C_Valid,
output reg [ 4:0 ] ADC_C_Channel,
output ADC_C_SOP,
output ADC_C_EOP,
input ADC_C_Ready,
input ADC_R_Valid,
input [ 4:0 ] ADC_R_Channel,
input [ 11:0 ] ADC_R_Data,
input ADC_R_SOP,
input ADC_R_EOP,
input ADC_Trigger,
output ADC_Interrupt
);
wire [ `ADC_CH_COUNT - 1 : 0 ] ADC_wr;
wire [ `ADC_DATA_WIDTH - 1 : 0 ] ADC [ `ADC_CH_COUNT - 1 : 0 ];
assign ADC_wr[`ADC_CELL_0] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_0;
assign ADC_wr[`ADC_CELL_1] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_1;
assign ADC_wr[`ADC_CELL_2] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_2;
assign ADC_wr[`ADC_CELL_3] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_3;
assign ADC_wr[`ADC_CELL_4] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_4;
assign ADC_wr[`ADC_CELL_5] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_5;
assign ADC_wr[`ADC_CELL_6] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_6;
assign ADC_wr[`ADC_CELL_7] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_7;
assign ADC_wr[`ADC_CELL_8] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_8;
assign ADC_wr[`ADC_CELL_T] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_T;
mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC0 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_0], ADC[`ADC_CELL_0] );
mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC1 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_1], ADC[`ADC_CELL_1] );
mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC2 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_2], ADC[`ADC_CELL_2] );
mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC3 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_3], ADC[`ADC_CELL_3] );
mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC4 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_4], ADC[`ADC_CELL_4] );
mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC5 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_5], ADC[`ADC_CELL_5] );
mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC6 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_6], ADC[`ADC_CELL_6] );
mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC7 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_7], ADC[`ADC_CELL_7] );
mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC8 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_8], ADC[`ADC_CELL_8] );
mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADCT (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_T], ADC[`ADC_CELL_T] );
wire [`ADC_CH_COUNT - 1 : 0] ADMSK;
wire ADMSK_wr = write_enable && write_addr == `ADC_REG_ADMSK;
mfp_register_r #(.WIDTH(`ADC_CH_COUNT)) r_ADMSK (CLK, RESETn, write_data[`ADC_CH_COUNT - 1 : 0], ADMSK_wr, ADMSK );
wire ADCS_EN;
wire ADCS_TE;
wire ADCS_FR;
wire ADCS_IE;
wire ADCS_wr = write_enable && write_addr == `ADC_REG_ADCS;
mfp_register_r #(.WIDTH(1)) r_ADCS_EN (CLK, RESETn, write_data[`ADC_FIELD_ADCS_EN], ADCS_wr, ADCS_EN );
mfp_register_r #(.WIDTH(1)) r_ADCS_TE (CLK, RESETn, write_data[`ADC_FIELD_ADCS_TE], ADCS_wr, ADCS_TE );
mfp_register_r #(.WIDTH(1)) r_ADCS_FR (CLK, RESETn, write_data[`ADC_FIELD_ADCS_FR], ADCS_wr, ADCS_FR );
mfp_register_r #(.WIDTH(1)) r_ADCS_IE (CLK, RESETn, write_data[`ADC_FIELD_ADCS_IE], ADCS_wr, ADCS_IE );
wire ADCS_SC;
wire ADCS_SC_wr = ADCS_wr | (ADC_R_EOP & ~ADCS_FR);
wire ADCS_SC_new = ADCS_wr ? write_data[`ADC_FIELD_ADCS_SC] : 1'b0;
mfp_register_r #(.WIDTH(1)) r_ADCS_SC (CLK, RESETn, ADCS_SC_new, ADCS_SC_wr, ADCS_SC );
wire ADCS_IF;
wire ConversionEnd = !(ADMSK >> ADC_R_Channel + 1);
wire ADCS_IF_wr = (ConversionEnd & ADCS_IE & ADCS_EN)
| (ADCS_wr & write_data[`ADC_FIELD_ADCS_IF])
| ~ADCS_EN;
wire ADCS_IF_new = (ConversionEnd & ADCS_IE & ADCS_EN);
mfp_register_r #(.WIDTH(1)) r_ADCS_IF (CLK, RESETn, ADCS_IF_new, ADCS_IF_wr, ADCS_IF );
assign ADC_Interrupt = ADCS_IF;
wire [ 31:0 ] ADCS = 32'b0 | (ADCS_IF << `ADC_FIELD_ADCS_IF) | (ADCS_IE << `ADC_FIELD_ADCS_IE)
| (ADCS_FR << `ADC_FIELD_ADCS_FR) | (ADCS_TE << `ADC_FIELD_ADCS_TE)
| (ADCS_SC << `ADC_FIELD_ADCS_SC) | (ADCS_EN << `ADC_FIELD_ADCS_EN);
always @ (*)
case(read_addr)
default : read_data = 32'b0;
`ADC_REG_ADCS : read_data = ADCS;
`ADC_REG_ADMSK : read_data = {{ 32 - `ADC_CH_COUNT {1'b0}}, ADMSK };
`ADC_REG_ADC0 : read_data = {{ 32 - `ADC_DATA_WIDTH {1'b0}}, ADC[`ADC_CELL_0] };
`ADC_REG_ADC1 : read_data = {{ 32 - `ADC_DATA_WIDTH {1'b0}}, ADC[`ADC_CELL_1] };
`ADC_REG_ADC2 : read_data = {{ 32 - `ADC_DATA_WIDTH {1'b0}}, ADC[`ADC_CELL_2] };
`ADC_REG_ADC3 : read_data = {{ 32 - `ADC_DATA_WIDTH {1'b0}}, ADC[`ADC_CELL_3] };
`ADC_REG_ADC4 : read_data = {{ 32 - `ADC_DATA_WIDTH {1'b0}}, ADC[`ADC_CELL_4] };
`ADC_REG_ADC5 : read_data = {{ 32 - `ADC_DATA_WIDTH {1'b0}}, ADC[`ADC_CELL_5] };
`ADC_REG_ADC6 : read_data = {{ 32 - `ADC_DATA_WIDTH {1'b0}}, ADC[`ADC_CELL_6] };
`ADC_REG_ADC7 : read_data = {{ 32 - `ADC_DATA_WIDTH {1'b0}}, ADC[`ADC_CELL_7] };
`ADC_REG_ADC8 : read_data = {{ 32 - `ADC_DATA_WIDTH {1'b0}}, ADC[`ADC_CELL_8] };
`ADC_REG_ADCT : read_data = {{ 32 - `ADC_DATA_WIDTH {1'b0}}, ADC[`ADC_CELL_T] };
endcase
parameter S_IDLE = 3'b000,
S_FIRST = 3'b001,
S_NEXT = 3'b010,
S_LAST = 3'b011,
S_SINGLE = 3'b100,
S_WAIT = 3'b101;
wire [ 2 : 0 ] State;
reg [ 2 : 0 ] Next;
mfp_register_r #(.WIDTH(3), .RESET(S_IDLE)) r_FSM_State (CLK, RESETn, Next, 1'b1, State );
wire [ 3 : 0 ] ActiveCell;
wire [ 3 : 0 ] NextCell;
reg ActiveCell_wr;
mfp_register_r #(.WIDTH(4)) r_ActiveCell (CLK, RESETn, NextCell, ActiveCell_wr, ActiveCell );
always @ (*) begin
case(State)
S_IDLE : ActiveCell_wr = 1'b1;
S_FIRST,
S_NEXT : ActiveCell_wr = ADC_C_Ready;
default : ActiveCell_wr = 1'b0;
endcase
end
wire NextIsValid, NextIsFirst, NextIsLast;
wire NeedFirst = State == S_IDLE;
offset_revolver offset_revolver
(
.bitMask ( ADMSK ),
.offset ( ActiveCell ),
.needFirst ( NeedFirst ),
.nextOffset ( NextCell ),
.nextIsValid ( NextIsValid ),
.nextIsFirst ( NextIsFirst ),
.nextIsLast ( NextIsLast )
);
wire NeedStart = NextIsValid & ADCS_EN & (ADCS_SC | (ADCS_TE & ADC_Trigger));
wire FreeRun = ADCS_FR & ADCS_EN & NextIsValid;
always @ (*)
case(State)
S_IDLE : Next = ~NeedStart ? S_IDLE : (
FreeRun ? S_FIRST : (
NextIsLast ? S_SINGLE : S_FIRST ));
S_FIRST : Next = ~ADC_C_Ready ? S_FIRST : (
FreeRun ? S_NEXT : (
NextIsLast ? S_LAST : S_NEXT ));
S_NEXT : Next = ~ADC_C_Ready | FreeRun ? S_NEXT : (
NextIsLast ? S_LAST : S_NEXT );
S_LAST : Next = ~ADC_C_Ready ? S_LAST : S_WAIT;
S_SINGLE : Next = ~ADC_C_Ready ? S_SINGLE : S_WAIT;
S_WAIT : Next = ~ADC_R_EOP ? S_WAIT : S_IDLE;
endcase
reg [ 2 : 0 ] out;
assign { ADC_C_Valid, ADC_C_SOP, ADC_C_EOP } = out;
always @ (*) begin
case(State)
S_IDLE : out = 3'b000;
S_FIRST : out = 3'b110;
S_NEXT : out = 3'b100;
S_LAST : out = 3'b101;
S_SINGLE : out = 3'b111;
S_WAIT : out = 3'b000;
endcase
case(ActiveCell)
default : ADC_C_Channel = `ADC_CH_NONE;
`ADC_CELL_0 : ADC_C_Channel = `ADC_CH_0;
`ADC_CELL_1 : ADC_C_Channel = `ADC_CH_1;
`ADC_CELL_2 : ADC_C_Channel = `ADC_CH_2;
`ADC_CELL_3 : ADC_C_Channel = `ADC_CH_3;
`ADC_CELL_4 : ADC_C_Channel = `ADC_CH_4;
`ADC_CELL_5 : ADC_C_Channel = `ADC_CH_5;
`ADC_CELL_6 : ADC_C_Channel = `ADC_CH_6;
`ADC_CELL_7 : ADC_C_Channel = `ADC_CH_7;
`ADC_CELL_8 : ADC_C_Channel = `ADC_CH_8;
`ADC_CELL_T : ADC_C_Channel = `ADC_CH_T;
endcase
end
endmodule | module mfp_adc_max10_core
(
input CLK,
input RESETn,
input [ `ADC_ADDR_WIDTH - 1 : 0 ] read_addr,
output reg [ 31 : 0 ] read_data,
input [ `ADC_ADDR_WIDTH - 1 : 0 ] write_addr,
input [ 31 : 0 ] write_data,
input write_enable,
output ADC_C_Valid,
output reg [ 4:0 ] ADC_C_Channel,
output ADC_C_SOP,
output ADC_C_EOP,
input ADC_C_Ready,
input ADC_R_Valid,
input [ 4:0 ] ADC_R_Channel,
input [ 11:0 ] ADC_R_Data,
input ADC_R_SOP,
input ADC_R_EOP,
input ADC_Trigger,
output ADC_Interrupt
); |
wire [ `ADC_CH_COUNT - 1 : 0 ] ADC_wr;
wire [ `ADC_DATA_WIDTH - 1 : 0 ] ADC [ `ADC_CH_COUNT - 1 : 0 ];
assign ADC_wr[`ADC_CELL_0] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_0;
assign ADC_wr[`ADC_CELL_1] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_1;
assign ADC_wr[`ADC_CELL_2] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_2;
assign ADC_wr[`ADC_CELL_3] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_3;
assign ADC_wr[`ADC_CELL_4] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_4;
assign ADC_wr[`ADC_CELL_5] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_5;
assign ADC_wr[`ADC_CELL_6] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_6;
assign ADC_wr[`ADC_CELL_7] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_7;
assign ADC_wr[`ADC_CELL_8] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_8;
assign ADC_wr[`ADC_CELL_T] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_T;
mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC0 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_0], ADC[`ADC_CELL_0] );
mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC1 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_1], ADC[`ADC_CELL_1] );
mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC2 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_2], ADC[`ADC_CELL_2] );
mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC3 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_3], ADC[`ADC_CELL_3] );
mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC4 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_4], ADC[`ADC_CELL_4] );
mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC5 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_5], ADC[`ADC_CELL_5] );
mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC6 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_6], ADC[`ADC_CELL_6] );
mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC7 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_7], ADC[`ADC_CELL_7] );
mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC8 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_8], ADC[`ADC_CELL_8] );
mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADCT (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_T], ADC[`ADC_CELL_T] );
wire [`ADC_CH_COUNT - 1 : 0] ADMSK;
wire ADMSK_wr = write_enable && write_addr == `ADC_REG_ADMSK;
mfp_register_r #(.WIDTH(`ADC_CH_COUNT)) r_ADMSK (CLK, RESETn, write_data[`ADC_CH_COUNT - 1 : 0], ADMSK_wr, ADMSK );
wire ADCS_EN;
wire ADCS_TE;
wire ADCS_FR;
wire ADCS_IE;
wire ADCS_wr = write_enable && write_addr == `ADC_REG_ADCS;
mfp_register_r #(.WIDTH(1)) r_ADCS_EN (CLK, RESETn, write_data[`ADC_FIELD_ADCS_EN], ADCS_wr, ADCS_EN );
mfp_register_r #(.WIDTH(1)) r_ADCS_TE (CLK, RESETn, write_data[`ADC_FIELD_ADCS_TE], ADCS_wr, ADCS_TE );
mfp_register_r #(.WIDTH(1)) r_ADCS_FR (CLK, RESETn, write_data[`ADC_FIELD_ADCS_FR], ADCS_wr, ADCS_FR );
mfp_register_r #(.WIDTH(1)) r_ADCS_IE (CLK, RESETn, write_data[`ADC_FIELD_ADCS_IE], ADCS_wr, ADCS_IE );
wire ADCS_SC;
wire ADCS_SC_wr = ADCS_wr | (ADC_R_EOP & ~ADCS_FR);
wire ADCS_SC_new = ADCS_wr ? write_data[`ADC_FIELD_ADCS_SC] : 1'b0;
mfp_register_r #(.WIDTH(1)) r_ADCS_SC (CLK, RESETn, ADCS_SC_new, ADCS_SC_wr, ADCS_SC );
wire ADCS_IF;
wire ConversionEnd = !(ADMSK >> ADC_R_Channel + 1);
wire ADCS_IF_wr = (ConversionEnd & ADCS_IE & ADCS_EN)
| (ADCS_wr & write_data[`ADC_FIELD_ADCS_IF])
| ~ADCS_EN;
wire ADCS_IF_new = (ConversionEnd & ADCS_IE & ADCS_EN);
mfp_register_r #(.WIDTH(1)) r_ADCS_IF (CLK, RESETn, ADCS_IF_new, ADCS_IF_wr, ADCS_IF );
assign ADC_Interrupt = ADCS_IF;
wire [ 31:0 ] ADCS = 32'b0 | (ADCS_IF << `ADC_FIELD_ADCS_IF) | (ADCS_IE << `ADC_FIELD_ADCS_IE)
| (ADCS_FR << `ADC_FIELD_ADCS_FR) | (ADCS_TE << `ADC_FIELD_ADCS_TE)
| (ADCS_SC << `ADC_FIELD_ADCS_SC) | (ADCS_EN << `ADC_FIELD_ADCS_EN);
always @ (*)
case(read_addr)
default : read_data = 32'b0;
`ADC_REG_ADCS : read_data = ADCS;
`ADC_REG_ADMSK : read_data = {{ 32 - `ADC_CH_COUNT {1'b0}}, ADMSK };
`ADC_REG_ADC0 : read_data = {{ 32 - `ADC_DATA_WIDTH {1'b0}}, ADC[`ADC_CELL_0] };
`ADC_REG_ADC1 : read_data = {{ 32 - `ADC_DATA_WIDTH {1'b0}}, ADC[`ADC_CELL_1] };
`ADC_REG_ADC2 : read_data = {{ 32 - `ADC_DATA_WIDTH {1'b0}}, ADC[`ADC_CELL_2] };
`ADC_REG_ADC3 : read_data = {{ 32 - `ADC_DATA_WIDTH {1'b0}}, ADC[`ADC_CELL_3] };
`ADC_REG_ADC4 : read_data = {{ 32 - `ADC_DATA_WIDTH {1'b0}}, ADC[`ADC_CELL_4] };
`ADC_REG_ADC5 : read_data = {{ 32 - `ADC_DATA_WIDTH {1'b0}}, ADC[`ADC_CELL_5] };
`ADC_REG_ADC6 : read_data = {{ 32 - `ADC_DATA_WIDTH {1'b0}}, ADC[`ADC_CELL_6] };
`ADC_REG_ADC7 : read_data = {{ 32 - `ADC_DATA_WIDTH {1'b0}}, ADC[`ADC_CELL_7] };
`ADC_REG_ADC8 : read_data = {{ 32 - `ADC_DATA_WIDTH {1'b0}}, ADC[`ADC_CELL_8] };
`ADC_REG_ADCT : read_data = {{ 32 - `ADC_DATA_WIDTH {1'b0}}, ADC[`ADC_CELL_T] };
endcase
parameter S_IDLE = 3'b000,
S_FIRST = 3'b001,
S_NEXT = 3'b010,
S_LAST = 3'b011,
S_SINGLE = 3'b100,
S_WAIT = 3'b101;
wire [ 2 : 0 ] State;
reg [ 2 : 0 ] Next;
mfp_register_r #(.WIDTH(3), .RESET(S_IDLE)) r_FSM_State (CLK, RESETn, Next, 1'b1, State );
wire [ 3 : 0 ] ActiveCell;
wire [ 3 : 0 ] NextCell;
reg ActiveCell_wr;
mfp_register_r #(.WIDTH(4)) r_ActiveCell (CLK, RESETn, NextCell, ActiveCell_wr, ActiveCell );
always @ (*) begin
case(State)
S_IDLE : ActiveCell_wr = 1'b1;
S_FIRST,
S_NEXT : ActiveCell_wr = ADC_C_Ready;
default : ActiveCell_wr = 1'b0;
endcase
end
wire NextIsValid, NextIsFirst, NextIsLast;
wire NeedFirst = State == S_IDLE;
offset_revolver offset_revolver
(
.bitMask ( ADMSK ),
.offset ( ActiveCell ),
.needFirst ( NeedFirst ),
.nextOffset ( NextCell ),
.nextIsValid ( NextIsValid ),
.nextIsFirst ( NextIsFirst ),
.nextIsLast ( NextIsLast )
);
wire NeedStart = NextIsValid & ADCS_EN & (ADCS_SC | (ADCS_TE & ADC_Trigger));
wire FreeRun = ADCS_FR & ADCS_EN & NextIsValid;
always @ (*)
case(State)
S_IDLE : Next = ~NeedStart ? S_IDLE : (
FreeRun ? S_FIRST : (
NextIsLast ? S_SINGLE : S_FIRST ));
S_FIRST : Next = ~ADC_C_Ready ? S_FIRST : (
FreeRun ? S_NEXT : (
NextIsLast ? S_LAST : S_NEXT ));
S_NEXT : Next = ~ADC_C_Ready | FreeRun ? S_NEXT : (
NextIsLast ? S_LAST : S_NEXT );
S_LAST : Next = ~ADC_C_Ready ? S_LAST : S_WAIT;
S_SINGLE : Next = ~ADC_C_Ready ? S_SINGLE : S_WAIT;
S_WAIT : Next = ~ADC_R_EOP ? S_WAIT : S_IDLE;
endcase
reg [ 2 : 0 ] out;
assign { ADC_C_Valid, ADC_C_SOP, ADC_C_EOP } = out;
always @ (*) begin
case(State)
S_IDLE : out = 3'b000;
S_FIRST : out = 3'b110;
S_NEXT : out = 3'b100;
S_LAST : out = 3'b101;
S_SINGLE : out = 3'b111;
S_WAIT : out = 3'b000;
endcase
case(ActiveCell)
default : ADC_C_Channel = `ADC_CH_NONE;
`ADC_CELL_0 : ADC_C_Channel = `ADC_CH_0;
`ADC_CELL_1 : ADC_C_Channel = `ADC_CH_1;
`ADC_CELL_2 : ADC_C_Channel = `ADC_CH_2;
`ADC_CELL_3 : ADC_C_Channel = `ADC_CH_3;
`ADC_CELL_4 : ADC_C_Channel = `ADC_CH_4;
`ADC_CELL_5 : ADC_C_Channel = `ADC_CH_5;
`ADC_CELL_6 : ADC_C_Channel = `ADC_CH_6;
`ADC_CELL_7 : ADC_C_Channel = `ADC_CH_7;
`ADC_CELL_8 : ADC_C_Channel = `ADC_CH_8;
`ADC_CELL_T : ADC_C_Channel = `ADC_CH_T;
endcase
end
endmodule | 2 |
139,147 | data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v | 86,852,558 | mfp_adc_max10_core.v | v | 245 | 121 | [] | [] | [] | [(61, 264), (266, 297)] | null | null | 1: b'%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:6: Cannot find include file: mfp_adc_max10_core.vh\n`include "mfp_adc_max10_core.vh" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86852558/src,data/full_repos/permissive/86852558/mfp_adc_max10_core.vh\n data/full_repos/permissive/86852558/src,data/full_repos/permissive/86852558/mfp_adc_max10_core.vh.v\n data/full_repos/permissive/86852558/src,data/full_repos/permissive/86852558/mfp_adc_max10_core.vh.sv\n mfp_adc_max10_core.vh\n mfp_adc_max10_core.vh.v\n mfp_adc_max10_core.vh.sv\n obj_dir/mfp_adc_max10_core.vh\n obj_dir/mfp_adc_max10_core.vh.v\n obj_dir/mfp_adc_max10_core.vh.sv\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:14: Define or directive not defined: \'`ADC_ADDR_WIDTH\'\n input [ `ADC_ADDR_WIDTH - 1 : 0 ] read_addr,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:16: Define or directive not defined: \'`ADC_ADDR_WIDTH\'\n input [ `ADC_ADDR_WIDTH - 1 : 0 ] write_addr,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:38: Define or directive not defined: \'`ADC_CH_COUNT\'\n wire [ `ADC_CH_COUNT - 1 : 0 ] ADC_wr;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:39: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n wire [ `ADC_DATA_WIDTH - 1 : 0 ] ADC [ `ADC_CH_COUNT - 1 : 0 ];\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:39: Define or directive not defined: \'`ADC_CH_COUNT\'\n wire [ `ADC_DATA_WIDTH - 1 : 0 ] ADC [ `ADC_CH_COUNT - 1 : 0 ];\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:41: Define or directive not defined: \'`ADC_CELL_0\'\n assign ADC_wr[`ADC_CELL_0] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_0;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:41: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ADC_wr[`ADC_CELL_0] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_0;\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:41: Define or directive not defined: \'`ADC_CH_0\'\n assign ADC_wr[`ADC_CELL_0] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_0;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:42: Define or directive not defined: \'`ADC_CELL_1\'\n assign ADC_wr[`ADC_CELL_1] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_1;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:42: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ADC_wr[`ADC_CELL_1] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_1;\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:42: Define or directive not defined: \'`ADC_CH_1\'\n assign ADC_wr[`ADC_CELL_1] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_1;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:43: Define or directive not defined: \'`ADC_CELL_2\'\n assign ADC_wr[`ADC_CELL_2] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_2;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:43: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ADC_wr[`ADC_CELL_2] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_2;\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:43: Define or directive not defined: \'`ADC_CH_2\'\n assign ADC_wr[`ADC_CELL_2] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_2;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:44: Define or directive not defined: \'`ADC_CELL_3\'\n assign ADC_wr[`ADC_CELL_3] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_3;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:44: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ADC_wr[`ADC_CELL_3] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_3;\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:44: Define or directive not defined: \'`ADC_CH_3\'\n assign ADC_wr[`ADC_CELL_3] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_3;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:45: Define or directive not defined: \'`ADC_CELL_4\'\n assign ADC_wr[`ADC_CELL_4] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_4;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:45: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ADC_wr[`ADC_CELL_4] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_4;\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:45: Define or directive not defined: \'`ADC_CH_4\'\n assign ADC_wr[`ADC_CELL_4] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_4;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:46: Define or directive not defined: \'`ADC_CELL_5\'\n assign ADC_wr[`ADC_CELL_5] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_5;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:46: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ADC_wr[`ADC_CELL_5] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_5;\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:46: Define or directive not defined: \'`ADC_CH_5\'\n assign ADC_wr[`ADC_CELL_5] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_5;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:47: Define or directive not defined: \'`ADC_CELL_6\'\n assign ADC_wr[`ADC_CELL_6] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_6;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:47: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ADC_wr[`ADC_CELL_6] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_6;\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:47: Define or directive not defined: \'`ADC_CH_6\'\n assign ADC_wr[`ADC_CELL_6] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_6;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:48: Define or directive not defined: \'`ADC_CELL_7\'\n assign ADC_wr[`ADC_CELL_7] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_7;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:48: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ADC_wr[`ADC_CELL_7] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_7;\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:48: Define or directive not defined: \'`ADC_CH_7\'\n assign ADC_wr[`ADC_CELL_7] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_7;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:49: Define or directive not defined: \'`ADC_CELL_8\'\n assign ADC_wr[`ADC_CELL_8] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_8;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:49: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ADC_wr[`ADC_CELL_8] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_8;\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:49: Define or directive not defined: \'`ADC_CH_8\'\n assign ADC_wr[`ADC_CELL_8] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_8;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:50: Define or directive not defined: \'`ADC_CELL_T\'\n assign ADC_wr[`ADC_CELL_T] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_T;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:50: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ADC_wr[`ADC_CELL_T] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_T;\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:50: Define or directive not defined: \'`ADC_CH_T\'\n assign ADC_wr[`ADC_CELL_T] = ADC_R_Valid && ADC_R_Channel == `ADC_CH_T;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:52: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC0 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_0], ADC[`ADC_CELL_0] );\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:52: Define or directive not defined: \'`ADC_CELL_0\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC0 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_0], ADC[`ADC_CELL_0] );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:52: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC0 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_0], ADC[`ADC_CELL_0] );\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:52: Define or directive not defined: \'`ADC_CELL_0\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC0 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_0], ADC[`ADC_CELL_0] );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:53: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC1 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_1], ADC[`ADC_CELL_1] );\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:53: Define or directive not defined: \'`ADC_CELL_1\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC1 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_1], ADC[`ADC_CELL_1] );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:53: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC1 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_1], ADC[`ADC_CELL_1] );\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:53: Define or directive not defined: \'`ADC_CELL_1\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC1 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_1], ADC[`ADC_CELL_1] );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:54: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC2 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_2], ADC[`ADC_CELL_2] );\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:54: Define or directive not defined: \'`ADC_CELL_2\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC2 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_2], ADC[`ADC_CELL_2] );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:54: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC2 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_2], ADC[`ADC_CELL_2] );\n ^\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:54: Define or directive not defined: \'`ADC_CELL_2\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC2 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_2], ADC[`ADC_CELL_2] );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:55: Define or directive not defined: \'`ADC_DATA_WIDTH\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC3 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_3], ADC[`ADC_CELL_3] );\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_adc_max10_core.v:55: Define or directive not defined: \'`ADC_CELL_3\'\n mfp_register_r #(.WIDTH(`ADC_DATA_WIDTH)) r_ADC3 (CLK, RESETn, ADC_R_Data, ADC_wr[`ADC_CELL_3], ADC[`ADC_CELL_3] );\n ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 304,359 | module | module offset_revolver
(
input [`ADC_CH_COUNT - 1 : 0 ] bitMask,
input [ 3 : 0 ] offset,
input needFirst,
output [ 3 : 0 ] nextOffset,
output nextIsValid,
output nextIsFirst,
output nextIsLast
);
localparam ALL_VALUES = {`ADC_CH_COUNT {1'b1}};
assign nextIsValid = | (bitMask & (1 << nextOffset));
assign nextIsFirst = nextIsValid && !(bitMask << `ADC_CH_COUNT - nextOffset);
assign nextIsLast = nextIsValid && !(bitMask >> nextOffset + 1);
wire curIsLast = !(bitMask >> offset + 1);
wire [`ADC_CH_COUNT - 1 : 0] nextFilter = curIsLast | needFirst
? ALL_VALUES
: ALL_VALUES << offset + 1;
wire [ 15 : 0 ] filteredMask = {{ 15 - `ADC_CH_COUNT { 1'b0 }}, bitMask & nextFilter };
wire detect;
priority_encoder16_r mask_en
(
.in ( filteredMask ),
.detect ( detect ),
.out ( nextOffset )
);
endmodule | module offset_revolver
(
input [`ADC_CH_COUNT - 1 : 0 ] bitMask,
input [ 3 : 0 ] offset,
input needFirst,
output [ 3 : 0 ] nextOffset,
output nextIsValid,
output nextIsFirst,
output nextIsLast
); |
localparam ALL_VALUES = {`ADC_CH_COUNT {1'b1}};
assign nextIsValid = | (bitMask & (1 << nextOffset));
assign nextIsFirst = nextIsValid && !(bitMask << `ADC_CH_COUNT - nextOffset);
assign nextIsLast = nextIsValid && !(bitMask >> nextOffset + 1);
wire curIsLast = !(bitMask >> offset + 1);
wire [`ADC_CH_COUNT - 1 : 0] nextFilter = curIsLast | needFirst
? ALL_VALUES
: ALL_VALUES << offset + 1;
wire [ 15 : 0 ] filteredMask = {{ 15 - `ADC_CH_COUNT { 1'b0 }}, bitMask & nextFilter };
wire detect;
priority_encoder16_r mask_en
(
.in ( filteredMask ),
.detect ( detect ),
.out ( nextOffset )
);
endmodule | 2 |
139,148 | data/full_repos/permissive/86852558/src/mfp_ahb_lite_adc_max10.v | 86,852,558 | mfp_ahb_lite_adc_max10.v | v | 99 | 70 | [] | [] | [] | [(61, 150)] | null | null | 1: b'%Error: data/full_repos/permissive/86852558/src/mfp_ahb_lite_adc_max10.v:6: Cannot find include file: mfp_adc_max10_core.vh\n`include "mfp_adc_max10_core.vh" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86852558/src,data/full_repos/permissive/86852558/mfp_adc_max10_core.vh\n data/full_repos/permissive/86852558/src,data/full_repos/permissive/86852558/mfp_adc_max10_core.vh.v\n data/full_repos/permissive/86852558/src,data/full_repos/permissive/86852558/mfp_adc_max10_core.vh.sv\n mfp_adc_max10_core.vh\n mfp_adc_max10_core.vh.v\n mfp_adc_max10_core.vh.sv\n obj_dir/mfp_adc_max10_core.vh\n obj_dir/mfp_adc_max10_core.vh.v\n obj_dir/mfp_adc_max10_core.vh.sv\n%Error: data/full_repos/permissive/86852558/src/mfp_ahb_lite_adc_max10.v:44: Define or directive not defined: \'`ADC_ADDR_WIDTH\'\n wire [ `ADC_ADDR_WIDTH - 1 : 0 ] read_addr;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_ahb_lite_adc_max10.v:46: Define or directive not defined: \'`ADC_ADDR_WIDTH\'\n wire [ `ADC_ADDR_WIDTH - 1 : 0 ] write_addr;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86852558/src/mfp_ahb_lite_adc_max10.v:54: Define or directive not defined: \'`ADC_ADDR_WIDTH\'\n .ADDR_WIDTH ( `ADC_ADDR_WIDTH ),\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n' | 304,362 | module | module mfp_ahb_lite_adc_max10
(
input HCLK,
input HRESETn,
input [ 31 : 0 ] HADDR,
input [ 2 : 0 ] HBURST,
input HMASTLOCK,
input [ 3 : 0 ] HPROT,
input HSEL,
input [ 2 : 0 ] HSIZE,
input [ 1 : 0 ] HTRANS,
input [ 31 : 0 ] HWDATA,
input HWRITE,
output [ 31 : 0 ] HRDATA,
output HREADY,
output HRESP,
input SI_Endian,
output ADC_C_Valid,
output [ 4 : 0 ] ADC_C_Channel,
output ADC_C_SOP,
output ADC_C_EOP,
input ADC_C_Ready,
input ADC_R_Valid,
input [ 4 :0 ] ADC_R_Channel,
input [ 11 :0 ] ADC_R_Data,
input ADC_R_SOP,
input ADC_R_EOP,
input ADC_Trigger,
output ADC_Interrupt
);
wire [ `ADC_ADDR_WIDTH - 1 : 0 ] read_addr;
wire read_enable;
wire [ `ADC_ADDR_WIDTH - 1 : 0 ] write_addr;
wire [ 3 : 0 ] write_mask;
wire write_enable;
assign HRESP = 1'b0;
mfp_ahb_lite_slave
#(
.ADDR_WIDTH ( `ADC_ADDR_WIDTH ),
.ADDR_START ( 2 )
)
decoder
(
.HCLK ( HCLK ),
.HRESETn ( HRESETn ),
.HADDR ( HADDR ),
.HSIZE ( HSIZE ),
.HTRANS ( HTRANS ),
.HWRITE ( HWRITE ),
.HSEL ( HSEL ),
.HREADY ( HREADY ),
.read_enable ( read_enable ),
.read_addr ( read_addr ),
.write_enable ( write_enable ),
.write_addr ( write_addr ),
.write_mask ( write_mask )
);
mfp_adc_max10_core adc_core
(
.CLK ( HCLK ),
.RESETn ( HRESETn ),
.read_addr ( read_addr ),
.read_data ( HRDATA ),
.write_addr ( write_addr ),
.write_data ( HWDATA ),
.write_enable ( write_enable ),
.ADC_C_Valid ( ADC_C_Valid ),
.ADC_C_Channel ( ADC_C_Channel ),
.ADC_C_SOP ( ADC_C_SOP ),
.ADC_C_EOP ( ADC_C_EOP ),
.ADC_C_Ready ( ADC_C_Ready ),
.ADC_R_Valid ( ADC_R_Valid ),
.ADC_R_Channel ( ADC_R_Channel ),
.ADC_R_Data ( ADC_R_Data ),
.ADC_R_SOP ( ADC_R_SOP ),
.ADC_R_EOP ( ADC_R_EOP ),
.ADC_Trigger ( ADC_Trigger ),
.ADC_Interrupt ( ADC_Interrupt )
);
endmodule | module mfp_ahb_lite_adc_max10
(
input HCLK,
input HRESETn,
input [ 31 : 0 ] HADDR,
input [ 2 : 0 ] HBURST,
input HMASTLOCK,
input [ 3 : 0 ] HPROT,
input HSEL,
input [ 2 : 0 ] HSIZE,
input [ 1 : 0 ] HTRANS,
input [ 31 : 0 ] HWDATA,
input HWRITE,
output [ 31 : 0 ] HRDATA,
output HREADY,
output HRESP,
input SI_Endian,
output ADC_C_Valid,
output [ 4 : 0 ] ADC_C_Channel,
output ADC_C_SOP,
output ADC_C_EOP,
input ADC_C_Ready,
input ADC_R_Valid,
input [ 4 :0 ] ADC_R_Channel,
input [ 11 :0 ] ADC_R_Data,
input ADC_R_SOP,
input ADC_R_EOP,
input ADC_Trigger,
output ADC_Interrupt
); |
wire [ `ADC_ADDR_WIDTH - 1 : 0 ] read_addr;
wire read_enable;
wire [ `ADC_ADDR_WIDTH - 1 : 0 ] write_addr;
wire [ 3 : 0 ] write_mask;
wire write_enable;
assign HRESP = 1'b0;
mfp_ahb_lite_slave
#(
.ADDR_WIDTH ( `ADC_ADDR_WIDTH ),
.ADDR_START ( 2 )
)
decoder
(
.HCLK ( HCLK ),
.HRESETn ( HRESETn ),
.HADDR ( HADDR ),
.HSIZE ( HSIZE ),
.HTRANS ( HTRANS ),
.HWRITE ( HWRITE ),
.HSEL ( HSEL ),
.HREADY ( HREADY ),
.read_enable ( read_enable ),
.read_addr ( read_addr ),
.write_enable ( write_enable ),
.write_addr ( write_addr ),
.write_mask ( write_mask )
);
mfp_adc_max10_core adc_core
(
.CLK ( HCLK ),
.RESETn ( HRESETn ),
.read_addr ( read_addr ),
.read_data ( HRDATA ),
.write_addr ( write_addr ),
.write_data ( HWDATA ),
.write_enable ( write_enable ),
.ADC_C_Valid ( ADC_C_Valid ),
.ADC_C_Channel ( ADC_C_Channel ),
.ADC_C_SOP ( ADC_C_SOP ),
.ADC_C_EOP ( ADC_C_EOP ),
.ADC_C_Ready ( ADC_C_Ready ),
.ADC_R_Valid ( ADC_R_Valid ),
.ADC_R_Channel ( ADC_R_Channel ),
.ADC_R_Data ( ADC_R_Data ),
.ADC_R_SOP ( ADC_R_SOP ),
.ADC_R_EOP ( ADC_R_EOP ),
.ADC_Trigger ( ADC_Trigger ),
.ADC_Interrupt ( ADC_Interrupt )
);
endmodule | 2 |
139,150 | data/full_repos/permissive/86852558/src/mfp_priority_encoder.v | 86,852,558 | mfp_priority_encoder.v | v | 45 | 67 | [] | [] | [] | [(5, 23), (25, 44)] | null | data/verilator_xmls/50d071ad-ade9-45ec-ba7a-6a15c4ad9cdc.xml | null | 304,364 | module | module priority_encoder8_r
(
input [ 7 : 0 ] in,
output reg detect,
output reg [ 2 : 0 ] out
);
always @ (*)
casez(in)
default : {detect, out} = 4'b0000;
8'b???????1 : {detect, out} = 4'b1000;
8'b??????10 : {detect, out} = 4'b1001;
8'b?????100 : {detect, out} = 4'b1010;
8'b????1000 : {detect, out} = 4'b1011;
8'b???10000 : {detect, out} = 4'b1100;
8'b??100000 : {detect, out} = 4'b1101;
8'b?1000000 : {detect, out} = 4'b1110;
8'b10000000 : {detect, out} = 4'b1111;
endcase
endmodule | module priority_encoder8_r
(
input [ 7 : 0 ] in,
output reg detect,
output reg [ 2 : 0 ] out
); |
always @ (*)
casez(in)
default : {detect, out} = 4'b0000;
8'b???????1 : {detect, out} = 4'b1000;
8'b??????10 : {detect, out} = 4'b1001;
8'b?????100 : {detect, out} = 4'b1010;
8'b????1000 : {detect, out} = 4'b1011;
8'b???10000 : {detect, out} = 4'b1100;
8'b??100000 : {detect, out} = 4'b1101;
8'b?1000000 : {detect, out} = 4'b1110;
8'b10000000 : {detect, out} = 4'b1111;
endcase
endmodule | 2 |
139,151 | data/full_repos/permissive/86852558/src/mfp_priority_encoder.v | 86,852,558 | mfp_priority_encoder.v | v | 45 | 67 | [] | [] | [] | [(5, 23), (25, 44)] | null | data/verilator_xmls/50d071ad-ade9-45ec-ba7a-6a15c4ad9cdc.xml | null | 304,364 | module | module priority_encoder16_r
(
input [ 15 : 0 ] in,
output reg detect,
output reg [ 3 : 0 ] out
);
wire [1:0] detectL;
wire [2:0] preoutL [1:0];
priority_encoder8_r e10( in[ 7:0 ], detectL[0], preoutL[0] );
priority_encoder8_r e11( in[ 15:8 ], detectL[1], preoutL[1] );
always @ (*)
casez(detectL)
default : {detect, out} = 5'b0;
2'b?1 : {detect, out} = { 2'b10, preoutL[0] };
2'b10 : {detect, out} = { 2'b11, preoutL[1] };
endcase
endmodule | module priority_encoder16_r
(
input [ 15 : 0 ] in,
output reg detect,
output reg [ 3 : 0 ] out
); |
wire [1:0] detectL;
wire [2:0] preoutL [1:0];
priority_encoder8_r e10( in[ 7:0 ], detectL[0], preoutL[0] );
priority_encoder8_r e11( in[ 15:8 ], detectL[1], preoutL[1] );
always @ (*)
casez(detectL)
default : {detect, out} = 5'b0;
2'b?1 : {detect, out} = { 2'b10, preoutL[0] };
2'b10 : {detect, out} = { 2'b11, preoutL[1] };
endcase
endmodule | 2 |
139,152 | data/full_repos/permissive/86852558/src/mfp_register.v | 86,852,558 | mfp_register.v | v | 21 | 42 | [] | [] | [] | [(3, 20)] | null | data/verilator_xmls/493c2142-cfda-4e1e-b40d-277b9400f93e.xml | null | 304,365 | module | module mfp_register_r
#(
parameter WIDTH = 32,
parameter RESET = { WIDTH { 1'b0 } }
)
(
input clk,
input rst,
input [ WIDTH - 1 : 0 ] d,
input wr,
output reg [ WIDTH - 1 : 0 ] q
);
always @ (posedge clk or negedge rst)
if(~rst)
q <= RESET;
else
if(wr) q <= d;
endmodule | module mfp_register_r
#(
parameter WIDTH = 32,
parameter RESET = { WIDTH { 1'b0 } }
)
(
input clk,
input rst,
input [ WIDTH - 1 : 0 ] d,
input wr,
output reg [ WIDTH - 1 : 0 ] q
); |
always @ (posedge clk or negedge rst)
if(~rst)
q <= RESET;
else
if(wr) q <= d;
endmodule | 2 |
139,157 | data/full_repos/permissive/86862934/ip/axi_atomic_gpo/src/atomic_gpo_v1_0.v | 86,862,934 | atomic_gpo_v1_0.v | v | 305 | 84 | [] | [] | [] | null | line:86: before: "=" | null | 1: b'%Error: data/full_repos/permissive/86862934/ip/axi_atomic_gpo/src/atomic_gpo_v1_0.v:132: Cannot find file containing module: \'axi_lite_slave\'\naxi_lite_slave #(\n^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86862934/ip/axi_atomic_gpo/src,data/full_repos/permissive/86862934/axi_lite_slave\n data/full_repos/permissive/86862934/ip/axi_atomic_gpo/src,data/full_repos/permissive/86862934/axi_lite_slave.v\n data/full_repos/permissive/86862934/ip/axi_atomic_gpo/src,data/full_repos/permissive/86862934/axi_lite_slave.sv\n axi_lite_slave\n axi_lite_slave.v\n axi_lite_slave.sv\n obj_dir/axi_lite_slave\n obj_dir/axi_lite_slave.v\n obj_dir/axi_lite_slave.sv\n%Warning-WIDTH: data/full_repos/permissive/86862934/ip/axi_atomic_gpo/src/atomic_gpo_v1_0.v:268: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'o_gpo\' generates 16 bits.\n : ... In instance axi_atomic_gpio\n r_reg_out_data <= o_gpo;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 304,376 | module | module axi_atomic_gpio #(
parameter integer C_S_AXI_ADDR_WIDTH = 8,
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter STROBE_WIDTH = (C_S_AXI_DATA_WIDTH / 8)
)(
input axi_clk,
input axi_rst_n,
input i_awvalid,
input [C_S_AXI_ADDR_WIDTH - 1: 0] i_awaddr,
output o_awready,
input i_wvalid,
output o_wready,
input [C_S_AXI_DATA_WIDTH - 1: 0] i_wdata,
output o_bvalid,
input i_bready,
output [1:0] o_bresp,
input i_arvalid,
output o_arready,
input [C_S_AXI_ADDR_WIDTH - 1: 0] i_araddr,
output o_rvalid,
input i_rready,
output [1:0] o_rresp,
output [C_S_AXI_DATA_WIDTH - 1: 0] o_rdata,
output reg [15:0] o_gpo,
input [5:0] i_cam0_slave_frame_ptr,
input [5:0] i_cam1_slave_frame_ptr,
input [5:0] i_cam2_slave_frame_ptr,
output reg [5:0] o_master_frame_ptr = 1,
output reg o_interrupt
);
localparam REG_CONTROL = 0;
localparam REG_GPO_VALUE = 1;
localparam REG_GPO_ACK = 2;
localparam REG_MASTER_FRAME_PTR = 3;
localparam REG_CAM0_SLAVE_FRAME_PTR = 4;
localparam REG_CAM1_SLAVE_FRAME_PTR = 5;
localparam REG_CAM2_SLAVE_FRAME_PTR = 6;
localparam REG_VERSION = 7;
localparam CTRL_BIT_ENABLE = 0;
wire [31:0] status;
wire [C_S_AXI_ADDR_WIDTH - 1: 0] w_reg_address;
wire [((C_S_AXI_ADDR_WIDTH - 1) - 2): 0] w_reg_32bit_address;
reg r_reg_invalid_addr;
wire w_reg_in_rdy;
reg r_reg_in_ack_stb;
wire [C_S_AXI_DATA_WIDTH - 1: 0] w_reg_in_data;
wire w_reg_out_req;
reg r_reg_out_rdy_stb;
reg [C_S_AXI_DATA_WIDTH - 1: 0] r_reg_out_data;
wire w_axi_rst;
reg [15: 0] r_gpo_value;
reg r_enable;
reg r_new_value_stb;
axi_lite_slave #(
.ADDR_WIDTH (C_S_AXI_ADDR_WIDTH ),
.DATA_WIDTH (C_S_AXI_DATA_WIDTH )
) axi_lite_reg_interface (
.clk (axi_clk ),
.rst (w_axi_rst ),
.i_awvalid (i_awvalid ),
.i_awaddr (i_awaddr ),
.o_awready (o_awready ),
.i_wvalid (i_wvalid ),
.o_wready (o_wready ),
.i_wdata (i_wdata ),
.o_bvalid (o_bvalid ),
.i_bready (i_bready ),
.o_bresp (o_bresp ),
.i_arvalid (i_arvalid ),
.o_arready (o_arready ),
.i_araddr (i_araddr ),
.o_rvalid (o_rvalid ),
.i_rready (i_rready ),
.o_rresp (o_rresp ),
.o_rdata (o_rdata ),
.o_reg_address (w_reg_address ),
.i_reg_invalid_addr (r_reg_invalid_addr ),
.o_reg_in_rdy (w_reg_in_rdy ),
.i_reg_in_ack_stb (r_reg_in_ack_stb ),
.o_reg_in_data (w_reg_in_data ),
.o_reg_out_req (w_reg_out_req ),
.i_reg_out_rdy_stb (r_reg_out_rdy_stb ),
.i_reg_out_data (r_reg_out_data )
);
assign w_axi_rst = ~axi_rst_n;
assign w_reg_32bit_address = w_reg_address[(C_S_AXI_ADDR_WIDTH - 1): 2];
always @(*) begin
if (w_axi_rst) begin
r_gpo_value <= 0;
end
else begin
if (r_enable) begin
case(o_master_frame_ptr)
6'h01: begin
r_gpo_value = 16'h4 << 2;
end
6'h03: begin
r_gpo_value = 16'h1 << 2;
end
6'h02: begin
r_gpo_value = 16'h2 << 2;
end
6'h06: begin
r_gpo_value = 16'h4 << 2;
end
6'h07: begin
r_gpo_value = 16'h1 << 2;
end
6'h05: begin
r_gpo_value = 16'h2 << 2;
end
default: begin
r_gpo_value = 0;
end
endcase
end
end
end
always @ (posedge axi_clk) begin
r_reg_in_ack_stb <= 0;
r_reg_out_rdy_stb <= 0;
r_reg_invalid_addr <= 0;
r_new_value_stb <= 0;
if (w_axi_rst) begin
o_gpo <= 0;
r_reg_out_data <= 0;
r_enable <= 0;
o_master_frame_ptr <= 0;
o_interrupt <= 0;
end
else begin
if (r_new_value_stb) begin
o_gpo <= r_gpo_value;
end
if (w_reg_in_rdy && !r_reg_in_ack_stb) begin
case (w_reg_32bit_address)
REG_CONTROL: begin
r_enable <= w_reg_in_data[CTRL_BIT_ENABLE];
o_interrupt <= 0;
end
REG_GPO_ACK: begin
o_gpo <= 0;
o_interrupt <= 1;
end
REG_MASTER_FRAME_PTR: begin
o_master_frame_ptr <= w_reg_in_data[5:0];
o_interrupt <= 0;
r_new_value_stb <= 1;
end
default: begin
end
endcase
if (w_reg_32bit_address > REG_VERSION) begin
r_reg_invalid_addr <= 1;
end
r_reg_in_ack_stb <= 1;
end
else if (w_reg_out_req && !r_reg_out_rdy_stb) begin
case (w_reg_32bit_address)
REG_CONTROL: begin
r_reg_out_data[CTRL_BIT_ENABLE] <= r_enable;
end
REG_GPO_VALUE: begin
r_reg_out_data <= o_gpo;
end
REG_MASTER_FRAME_PTR: begin
r_reg_out_data <= {26'h0, o_master_frame_ptr};
end
REG_CAM0_SLAVE_FRAME_PTR: begin
r_reg_out_data <= {26'h0, i_cam0_slave_frame_ptr};
end
REG_CAM1_SLAVE_FRAME_PTR: begin
r_reg_out_data <= {26'h0, i_cam1_slave_frame_ptr};
end
REG_CAM2_SLAVE_FRAME_PTR: begin
r_reg_out_data <= {26'h0, i_cam2_slave_frame_ptr};
end
REG_VERSION: begin
r_reg_out_data <= 32'h00;
r_reg_out_data[`MAJOR_RANGE] <= `MAJOR_VERSION;
r_reg_out_data[`MINOR_RANGE] <= `MINOR_VERSION;
r_reg_out_data[`REVISION_RANGE] <= `REVISION;
end
default: begin
r_reg_out_data <= 32'h00;
end
endcase
if (w_reg_32bit_address > REG_VERSION) begin
r_reg_invalid_addr <= 1;
end
r_reg_out_rdy_stb <= 1;
end
end
end
endmodule | module axi_atomic_gpio #(
parameter integer C_S_AXI_ADDR_WIDTH = 8,
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter STROBE_WIDTH = (C_S_AXI_DATA_WIDTH / 8)
)(
input axi_clk,
input axi_rst_n,
input i_awvalid,
input [C_S_AXI_ADDR_WIDTH - 1: 0] i_awaddr,
output o_awready,
input i_wvalid,
output o_wready,
input [C_S_AXI_DATA_WIDTH - 1: 0] i_wdata,
output o_bvalid,
input i_bready,
output [1:0] o_bresp,
input i_arvalid,
output o_arready,
input [C_S_AXI_ADDR_WIDTH - 1: 0] i_araddr,
output o_rvalid,
input i_rready,
output [1:0] o_rresp,
output [C_S_AXI_DATA_WIDTH - 1: 0] o_rdata,
output reg [15:0] o_gpo,
input [5:0] i_cam0_slave_frame_ptr,
input [5:0] i_cam1_slave_frame_ptr,
input [5:0] i_cam2_slave_frame_ptr,
output reg [5:0] o_master_frame_ptr = 1,
output reg o_interrupt
); |
localparam REG_CONTROL = 0;
localparam REG_GPO_VALUE = 1;
localparam REG_GPO_ACK = 2;
localparam REG_MASTER_FRAME_PTR = 3;
localparam REG_CAM0_SLAVE_FRAME_PTR = 4;
localparam REG_CAM1_SLAVE_FRAME_PTR = 5;
localparam REG_CAM2_SLAVE_FRAME_PTR = 6;
localparam REG_VERSION = 7;
localparam CTRL_BIT_ENABLE = 0;
wire [31:0] status;
wire [C_S_AXI_ADDR_WIDTH - 1: 0] w_reg_address;
wire [((C_S_AXI_ADDR_WIDTH - 1) - 2): 0] w_reg_32bit_address;
reg r_reg_invalid_addr;
wire w_reg_in_rdy;
reg r_reg_in_ack_stb;
wire [C_S_AXI_DATA_WIDTH - 1: 0] w_reg_in_data;
wire w_reg_out_req;
reg r_reg_out_rdy_stb;
reg [C_S_AXI_DATA_WIDTH - 1: 0] r_reg_out_data;
wire w_axi_rst;
reg [15: 0] r_gpo_value;
reg r_enable;
reg r_new_value_stb;
axi_lite_slave #(
.ADDR_WIDTH (C_S_AXI_ADDR_WIDTH ),
.DATA_WIDTH (C_S_AXI_DATA_WIDTH )
) axi_lite_reg_interface (
.clk (axi_clk ),
.rst (w_axi_rst ),
.i_awvalid (i_awvalid ),
.i_awaddr (i_awaddr ),
.o_awready (o_awready ),
.i_wvalid (i_wvalid ),
.o_wready (o_wready ),
.i_wdata (i_wdata ),
.o_bvalid (o_bvalid ),
.i_bready (i_bready ),
.o_bresp (o_bresp ),
.i_arvalid (i_arvalid ),
.o_arready (o_arready ),
.i_araddr (i_araddr ),
.o_rvalid (o_rvalid ),
.i_rready (i_rready ),
.o_rresp (o_rresp ),
.o_rdata (o_rdata ),
.o_reg_address (w_reg_address ),
.i_reg_invalid_addr (r_reg_invalid_addr ),
.o_reg_in_rdy (w_reg_in_rdy ),
.i_reg_in_ack_stb (r_reg_in_ack_stb ),
.o_reg_in_data (w_reg_in_data ),
.o_reg_out_req (w_reg_out_req ),
.i_reg_out_rdy_stb (r_reg_out_rdy_stb ),
.i_reg_out_data (r_reg_out_data )
);
assign w_axi_rst = ~axi_rst_n;
assign w_reg_32bit_address = w_reg_address[(C_S_AXI_ADDR_WIDTH - 1): 2];
always @(*) begin
if (w_axi_rst) begin
r_gpo_value <= 0;
end
else begin
if (r_enable) begin
case(o_master_frame_ptr)
6'h01: begin
r_gpo_value = 16'h4 << 2;
end
6'h03: begin
r_gpo_value = 16'h1 << 2;
end
6'h02: begin
r_gpo_value = 16'h2 << 2;
end
6'h06: begin
r_gpo_value = 16'h4 << 2;
end
6'h07: begin
r_gpo_value = 16'h1 << 2;
end
6'h05: begin
r_gpo_value = 16'h2 << 2;
end
default: begin
r_gpo_value = 0;
end
endcase
end
end
end
always @ (posedge axi_clk) begin
r_reg_in_ack_stb <= 0;
r_reg_out_rdy_stb <= 0;
r_reg_invalid_addr <= 0;
r_new_value_stb <= 0;
if (w_axi_rst) begin
o_gpo <= 0;
r_reg_out_data <= 0;
r_enable <= 0;
o_master_frame_ptr <= 0;
o_interrupt <= 0;
end
else begin
if (r_new_value_stb) begin
o_gpo <= r_gpo_value;
end
if (w_reg_in_rdy && !r_reg_in_ack_stb) begin
case (w_reg_32bit_address)
REG_CONTROL: begin
r_enable <= w_reg_in_data[CTRL_BIT_ENABLE];
o_interrupt <= 0;
end
REG_GPO_ACK: begin
o_gpo <= 0;
o_interrupt <= 1;
end
REG_MASTER_FRAME_PTR: begin
o_master_frame_ptr <= w_reg_in_data[5:0];
o_interrupt <= 0;
r_new_value_stb <= 1;
end
default: begin
end
endcase
if (w_reg_32bit_address > REG_VERSION) begin
r_reg_invalid_addr <= 1;
end
r_reg_in_ack_stb <= 1;
end
else if (w_reg_out_req && !r_reg_out_rdy_stb) begin
case (w_reg_32bit_address)
REG_CONTROL: begin
r_reg_out_data[CTRL_BIT_ENABLE] <= r_enable;
end
REG_GPO_VALUE: begin
r_reg_out_data <= o_gpo;
end
REG_MASTER_FRAME_PTR: begin
r_reg_out_data <= {26'h0, o_master_frame_ptr};
end
REG_CAM0_SLAVE_FRAME_PTR: begin
r_reg_out_data <= {26'h0, i_cam0_slave_frame_ptr};
end
REG_CAM1_SLAVE_FRAME_PTR: begin
r_reg_out_data <= {26'h0, i_cam1_slave_frame_ptr};
end
REG_CAM2_SLAVE_FRAME_PTR: begin
r_reg_out_data <= {26'h0, i_cam2_slave_frame_ptr};
end
REG_VERSION: begin
r_reg_out_data <= 32'h00;
r_reg_out_data[`MAJOR_RANGE] <= `MAJOR_VERSION;
r_reg_out_data[`MINOR_RANGE] <= `MINOR_VERSION;
r_reg_out_data[`REVISION_RANGE] <= `REVISION;
end
default: begin
r_reg_out_data <= 32'h00;
end
endcase
if (w_reg_32bit_address > REG_VERSION) begin
r_reg_invalid_addr <= 1;
end
r_reg_out_rdy_stb <= 1;
end
end
end
endmodule | 20 |
139,158 | data/full_repos/permissive/86862934/ip/axi_on_screen_display/axi_on_screen_display.v | 86,862,934 | axi_on_screen_display.v | v | 517 | 90 | [] | [] | [] | [(62, 516)] | null | null | 1: b'%Error: data/full_repos/permissive/86862934/ip/axi_on_screen_display/axi_on_screen_display.v:212: Cannot find file containing module: \'axi_lite_slave\'\naxi_lite_slave #(\n^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86862934/ip/axi_on_screen_display,data/full_repos/permissive/86862934/axi_lite_slave\n data/full_repos/permissive/86862934/ip/axi_on_screen_display,data/full_repos/permissive/86862934/axi_lite_slave.v\n data/full_repos/permissive/86862934/ip/axi_on_screen_display,data/full_repos/permissive/86862934/axi_lite_slave.sv\n axi_lite_slave\n axi_lite_slave.v\n axi_lite_slave.sv\n obj_dir/axi_lite_slave\n obj_dir/axi_lite_slave.v\n obj_dir/axi_lite_slave.sv\n%Error: data/full_repos/permissive/86862934/ip/axi_on_screen_display/axi_on_screen_display.v:256: Cannot find file containing module: \'console_osd\'\nconsole_osd #(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/86862934/ip/axi_on_screen_display/axi_on_screen_display.v:308: Cannot find file containing module: \'adapter_ppfifo_2_axi_stream\'\nadapter_ppfifo_2_axi_stream #(\n^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/86862934/ip/axi_on_screen_display/axi_on_screen_display.v:475: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'r_char_data\' generates 8 bits.\n : ... In instance axi_on_screen_display\n r_reg_out_data <= r_char_data;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n' | 304,388 | module | module axi_on_screen_display #(
parameter CONSOLE_DEPTH = 12,
parameter ADDR_WIDTH = 7,
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = (DATA_WIDTH / 8),
parameter AXIS_WIDTH = 24,
parameter INVERT_AXI_RESET = 1,
parameter INVERT_AXIS_RESET = 1,
parameter IMAGE_WIDTH = 480,
parameter IMAGE_HEIGHT = 272,
parameter BUFFER_DEPTH = 9,
parameter PIXEL_WIDTH = 24,
parameter FOREGROUND_COLOR = 24'hFFFFFF,
parameter BACKGROUND_COLOR = 24'h000000,
parameter FONT_WIDTH = 5,
parameter FONT_HEIGHT = 7,
parameter DEFAULT_TAB_COUNT = 2,
parameter DEFAULT_X_START = 0,
parameter DEFAULT_X_END = IMAGE_WIDTH,
parameter DEFAULT_Y_START = 0,
parameter DEFAULT_Y_END = IMAGE_HEIGHT
)(
input clk,
input rst,
input i_awvalid,
input [ADDR_WIDTH - 1: 0] i_awaddr,
output o_awready,
input i_wvalid,
output o_wready,
input [STROBE_WIDTH - 1:0] i_wstrb,
input [DATA_WIDTH - 1: 0] i_wdata,
output o_bvalid,
input i_bready,
output [1:0] o_bresp,
input i_arvalid,
output o_arready,
input [ADDR_WIDTH - 1: 0] i_araddr,
output o_rvalid,
input i_rready,
output [1:0] o_rresp,
output [DATA_WIDTH - 1: 0] o_rdata,
input i_axis_clk,
input i_axis_rst,
output [3:0] o_axis_user,
output [AXIS_WIDTH - 1:0] o_axis_data,
input i_axis_ready,
output o_axis_last,
output o_axis_valid
);
localparam REG_CONTROL = 0;
localparam REG_STATUS = 1;
localparam REG_IMAGE_WIDTH = 2;
localparam REG_IMAGE_HEIGHT = 3;
localparam REG_IMAGE_SIZE = 4;
localparam REG_FG_COLOR = 5;
localparam REG_BG_COLOR = 6;
localparam REG_CONSOLE_CHAR = 7;
localparam REG_CONSOLE_COMMAND = 8;
localparam REG_TAB_COUNT = 9;
localparam REG_X_START = 10;
localparam REG_X_END = 11;
localparam REG_Y_START = 12;
localparam REG_Y_END = 13;
localparam REG_ADAPTER_DEBUG = 14;
localparam REG_VERSION = 15;
wire [31:0] status;
reg r_enable;
reg r_clear_screen_stb;
reg r_scroll_en;
reg r_scroll_up_stb;
reg r_scroll_down_stb;
reg [31:0] r_image_width;
reg [31:0] r_image_height;
reg [31:0] r_image_size;
reg [31:0] r_console_command;
reg [7:0] r_char_data;
(* KEEP *) wire [23:0] wfifo_size;
(* KEEP *) wire wfifo_rdy;
(* KEEP *) wire wfifo_act;
(* KEEP *) wire wfifo_stb;
(* KEEP *) wire [AXIS_WIDTH:0] wfifo_data;
wire [31:0] w_adapter_debug;
wire [ADDR_WIDTH - 1: 0] w_reg_address;
wire [((ADDR_WIDTH-1) - 2):0] w_reg_32bit_address;
reg r_reg_invalid_addr;
wire w_reg_in_rdy;
reg r_reg_in_ack_stb;
wire [DATA_WIDTH - 1: 0] w_reg_in_data;
wire w_reg_out_req;
reg r_reg_out_rdy_stb;
reg [DATA_WIDTH - 1: 0] r_reg_out_data;
wire w_axi_rst;
wire w_axis_rst;
wire [31:0] w_debug;
reg [PIXEL_WIDTH - 1: 0] r_fg_color;
reg [PIXEL_WIDTH - 1: 0] r_bg_color;
reg r_alt_char;
reg [2:0] r_tab_count;
reg r_cmd_stb;
reg r_char_stb;
wire w_wr_char_rdy;
wire [3:0] w_cosd_state;
wire [15:0] w_pcount;
reg [31:0] r_x_start;
reg [31:0] r_x_end;
reg [31:0] r_y_start;
reg [31:0] r_y_end;
axi_lite_slave #(
.ADDR_WIDTH (ADDR_WIDTH ),
.DATA_WIDTH (DATA_WIDTH )
) axi_lite_reg_interface (
.clk (clk ),
.rst (w_axi_rst ),
.i_awvalid (i_awvalid ),
.i_awaddr (i_awaddr ),
.o_awready (o_awready ),
.i_wvalid (i_wvalid ),
.o_wready (o_wready ),
.i_wstrb (i_wstrb ),
.i_wdata (i_wdata ),
.o_bvalid (o_bvalid ),
.i_bready (i_bready ),
.o_bresp (o_bresp ),
.i_arvalid (i_arvalid ),
.o_arready (o_arready ),
.i_araddr (i_araddr ),
.o_rvalid (o_rvalid ),
.i_rready (i_rready ),
.o_rresp (o_rresp ),
.o_rdata (o_rdata ),
.o_reg_address (w_reg_address ),
.i_reg_invalid_addr (r_reg_invalid_addr ),
.o_reg_in_rdy (w_reg_in_rdy ),
.i_reg_in_ack_stb (r_reg_in_ack_stb ),
.o_reg_in_data (w_reg_in_data ),
.o_reg_out_req (w_reg_out_req ),
.i_reg_out_rdy_stb (r_reg_out_rdy_stb ),
.i_reg_out_data (r_reg_out_data )
);
console_osd #(
.CONSOLE_DEPTH (CONSOLE_DEPTH ),
.IMAGE_WIDTH (IMAGE_WIDTH ),
.IMAGE_HEIGHT (IMAGE_HEIGHT ),
.BUFFER_DEPTH (BUFFER_DEPTH ),
.PIXEL_WIDTH (PIXEL_WIDTH ),
.FONT_WIDTH (FONT_WIDTH ),
.FONT_HEIGHT (FONT_HEIGHT )
)cosd(
.clk (clk ),
.rst (w_axi_rst ),
.i_enable (r_enable ),
.i_fg_color (r_fg_color ),
.i_bg_color (r_bg_color ),
.i_cmd_stb (r_cmd_stb ),
.i_cmd (r_console_command ),
.i_char_stb (r_char_stb ),
.i_char (r_char_data ),
.o_wr_char_rdy (w_wr_char_rdy ),
.i_clear_screen_stb (r_clear_screen_stb ),
.i_alt_func_en (r_alt_char ),
.i_tab_count (r_tab_count ),
.i_scroll_en (r_scroll_en ),
.i_scroll_up_stb (r_scroll_up_stb ),
.i_scroll_down_stb (r_scroll_down_stb ),
.i_x_start (r_x_start ),
.i_x_end (r_x_end ),
.i_y_start (r_y_start ),
.i_y_end (r_y_end ),
.i_ppfifo_clk (i_axis_clk ),
.i_ppfifo_rst (w_axis_rst ),
.o_ppfifo_rdy (wfifo_rdy ),
.i_ppfifo_act (wfifo_act ),
.o_ppfifo_size (wfifo_size ),
.o_ppfifo_data (wfifo_data ),
.i_ppfifo_stb (wfifo_stb ),
.o_state (w_cosd_state ),
.o_pixel_count (w_pcount )
);
adapter_ppfifo_2_axi_stream #(
.DATA_WIDTH (AXIS_WIDTH )
) as2p (
.rst (w_axis_rst ),
.i_axi_clk (i_axis_clk ),
.i_axi_ready (i_axis_ready ),
.o_axi_data (o_axis_data ),
.o_axi_last (o_axis_last ),
.o_axi_valid (o_axis_valid ),
.o_axi_user (o_axis_user ),
.i_ppfifo_rdy (wfifo_rdy ),
.o_ppfifo_act (wfifo_act ),
.i_ppfifo_size (wfifo_size ),
.o_ppfifo_stb (wfifo_stb ),
.i_ppfifo_data (wfifo_data ),
.o_debug (w_adapter_debug )
);
assign w_axi_rst = (INVERT_AXI_RESET) ? ~rst : rst;
assign w_axis_rst = (INVERT_AXIS_RESET) ? ~i_axis_rst : i_axis_rst;
assign w_reg_32bit_address = w_reg_address[(ADDR_WIDTH - 1):2];
always @ (posedge clk) begin
r_reg_in_ack_stb <= 0;
r_reg_out_rdy_stb <= 0;
r_reg_invalid_addr <= 0;
r_cmd_stb <= 0;
r_char_stb <= 0;
r_alt_char <= 0;
r_clear_screen_stb <= 0;
r_scroll_up_stb <= 0;
r_scroll_down_stb <= 0;
if (w_axi_rst) begin
r_enable <= 0;
r_scroll_en <= 0;
r_reg_out_data <= 0;
r_image_width <= IMAGE_WIDTH;
r_image_height <= IMAGE_HEIGHT;
r_image_size <= (IMAGE_WIDTH * IMAGE_HEIGHT);
r_x_start <= DEFAULT_X_START;
r_x_end <= DEFAULT_X_END;
r_y_start <= DEFAULT_Y_START;
r_y_end <= DEFAULT_Y_END;
r_fg_color <= FOREGROUND_COLOR;
r_bg_color <= BACKGROUND_COLOR;
r_tab_count <= DEFAULT_TAB_COUNT;
r_char_data <= 0;
r_console_command <= 0;
end
else begin
if (w_reg_in_rdy) begin
case (w_reg_32bit_address)
REG_CONTROL: begin
r_enable <= w_reg_in_data[`BIT_CTRL_EN];
r_clear_screen_stb <= w_reg_in_data[`BIT_CTRL_CLEAR_SCREEN_STB];
r_scroll_en <= w_reg_in_data[`BIT_CTRL_SCROLL_EN];
r_scroll_up_stb <= w_reg_in_data[`BIT_CTRL_SCROLL_UP_STB];
r_scroll_down_stb <= w_reg_in_data[`BIT_CTRL_SCROLL_DOWN_STB];
end
REG_FG_COLOR: begin
r_fg_color <= w_reg_in_data[AXIS_WIDTH - 1: 0];
end
REG_BG_COLOR: begin
r_bg_color <= w_reg_in_data[AXIS_WIDTH - 1: 0];
end
REG_CONSOLE_CHAR: begin
r_char_data <= w_reg_in_data[`CHAR_ADDR_RANGE];
r_alt_char <= w_reg_in_data[`BIT_CHAR_ALT_ENABLE];
if (w_wr_char_rdy) begin
r_char_stb <= 1;
end
end
REG_CONSOLE_COMMAND: begin
r_console_command <= w_reg_in_data;
end
REG_X_START: begin
r_x_start <= w_reg_in_data;
end
REG_X_END: begin
r_x_end <= w_reg_in_data;
end
REG_Y_START: begin
r_y_start <= w_reg_in_data;
end
REG_Y_END: begin
r_y_end <= w_reg_in_data;
end
REG_TAB_COUNT: begin
r_tab_count <= w_reg_in_data[`TAB_COUNT_RANGE];
end
default: begin
end
endcase
if (w_reg_32bit_address > REG_VERSION) begin
r_reg_invalid_addr <= 1;
end
else if (w_reg_32bit_address == REG_CONSOLE_CHAR) begin
if (w_wr_char_rdy) begin
r_reg_in_ack_stb <= 1;
end
end
else begin
r_reg_in_ack_stb <= 1;
end
end
else if (w_reg_out_req) begin
case (w_reg_32bit_address)
REG_CONTROL: begin
r_reg_out_data <= 0;
r_reg_out_data[`BIT_CTRL_EN] <= r_enable;
r_reg_out_data[`BIT_CTRL_SCROLL_EN] <= r_scroll_en;
end
REG_STATUS: begin
r_reg_out_data <= 0;
r_reg_out_data[`BIT_AXIS_RST] <= w_axis_rst;
r_reg_out_data[`BIT_RANGE_COSD_STATE]<= w_cosd_state;
r_reg_out_data[`BIT_AXIS_RDY] <= i_axis_ready;
r_reg_out_data[`BIT_AXIS_VLD] <= o_axis_valid;
r_reg_out_data[`BIT_AXIS_USR] <= o_axis_user[0];
r_reg_out_data[`BIT_AXIS_LST] <= o_axis_last;
r_reg_out_data[`BIT_RANGE_PCOUNT] <= w_pcount;
end
REG_IMAGE_WIDTH: begin
r_reg_out_data <= r_image_width;
end
REG_IMAGE_HEIGHT: begin
r_reg_out_data <= r_image_height;
end
REG_IMAGE_SIZE: begin
r_reg_out_data <= r_image_size;
end
REG_FG_COLOR: begin
r_reg_out_data <= {8'h0, r_fg_color};
end
REG_BG_COLOR: begin
r_reg_out_data <= {8'h0, r_bg_color};
end
REG_CONSOLE_CHAR: begin
r_reg_out_data <= r_char_data;
end
REG_CONSOLE_COMMAND: begin
r_reg_out_data <= r_console_command;
end
REG_X_START: begin
r_reg_out_data <= r_x_start;
end
REG_X_END: begin
r_reg_out_data <= r_x_end;
end
REG_Y_START: begin
r_reg_out_data <= r_y_start;
end
REG_Y_END: begin
r_reg_out_data <= r_y_end;
end
REG_TAB_COUNT: begin
r_reg_out_data[`TAB_COUNT_RANGE]<= r_tab_count;
end
REG_ADAPTER_DEBUG: begin
r_reg_out_data <= w_adapter_debug;
end
REG_VERSION: begin
r_reg_out_data <= 32'h00;
r_reg_out_data[`MAJOR_RANGE] <= `MAJOR_VERSION;
r_reg_out_data[`MINOR_RANGE] <= `MINOR_VERSION;
r_reg_out_data[`REVISION_RANGE] <= `REVISION;
end
default: begin
r_reg_out_data <= 32'h00;
end
endcase
if (w_reg_32bit_address > REG_VERSION) begin
r_reg_invalid_addr <= 1;
end
r_reg_out_rdy_stb <= 1;
end
end
end
endmodule | module axi_on_screen_display #(
parameter CONSOLE_DEPTH = 12,
parameter ADDR_WIDTH = 7,
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = (DATA_WIDTH / 8),
parameter AXIS_WIDTH = 24,
parameter INVERT_AXI_RESET = 1,
parameter INVERT_AXIS_RESET = 1,
parameter IMAGE_WIDTH = 480,
parameter IMAGE_HEIGHT = 272,
parameter BUFFER_DEPTH = 9,
parameter PIXEL_WIDTH = 24,
parameter FOREGROUND_COLOR = 24'hFFFFFF,
parameter BACKGROUND_COLOR = 24'h000000,
parameter FONT_WIDTH = 5,
parameter FONT_HEIGHT = 7,
parameter DEFAULT_TAB_COUNT = 2,
parameter DEFAULT_X_START = 0,
parameter DEFAULT_X_END = IMAGE_WIDTH,
parameter DEFAULT_Y_START = 0,
parameter DEFAULT_Y_END = IMAGE_HEIGHT
)(
input clk,
input rst,
input i_awvalid,
input [ADDR_WIDTH - 1: 0] i_awaddr,
output o_awready,
input i_wvalid,
output o_wready,
input [STROBE_WIDTH - 1:0] i_wstrb,
input [DATA_WIDTH - 1: 0] i_wdata,
output o_bvalid,
input i_bready,
output [1:0] o_bresp,
input i_arvalid,
output o_arready,
input [ADDR_WIDTH - 1: 0] i_araddr,
output o_rvalid,
input i_rready,
output [1:0] o_rresp,
output [DATA_WIDTH - 1: 0] o_rdata,
input i_axis_clk,
input i_axis_rst,
output [3:0] o_axis_user,
output [AXIS_WIDTH - 1:0] o_axis_data,
input i_axis_ready,
output o_axis_last,
output o_axis_valid
); |
localparam REG_CONTROL = 0;
localparam REG_STATUS = 1;
localparam REG_IMAGE_WIDTH = 2;
localparam REG_IMAGE_HEIGHT = 3;
localparam REG_IMAGE_SIZE = 4;
localparam REG_FG_COLOR = 5;
localparam REG_BG_COLOR = 6;
localparam REG_CONSOLE_CHAR = 7;
localparam REG_CONSOLE_COMMAND = 8;
localparam REG_TAB_COUNT = 9;
localparam REG_X_START = 10;
localparam REG_X_END = 11;
localparam REG_Y_START = 12;
localparam REG_Y_END = 13;
localparam REG_ADAPTER_DEBUG = 14;
localparam REG_VERSION = 15;
wire [31:0] status;
reg r_enable;
reg r_clear_screen_stb;
reg r_scroll_en;
reg r_scroll_up_stb;
reg r_scroll_down_stb;
reg [31:0] r_image_width;
reg [31:0] r_image_height;
reg [31:0] r_image_size;
reg [31:0] r_console_command;
reg [7:0] r_char_data;
(* KEEP *) wire [23:0] wfifo_size;
(* KEEP *) wire wfifo_rdy;
(* KEEP *) wire wfifo_act;
(* KEEP *) wire wfifo_stb;
(* KEEP *) wire [AXIS_WIDTH:0] wfifo_data;
wire [31:0] w_adapter_debug;
wire [ADDR_WIDTH - 1: 0] w_reg_address;
wire [((ADDR_WIDTH-1) - 2):0] w_reg_32bit_address;
reg r_reg_invalid_addr;
wire w_reg_in_rdy;
reg r_reg_in_ack_stb;
wire [DATA_WIDTH - 1: 0] w_reg_in_data;
wire w_reg_out_req;
reg r_reg_out_rdy_stb;
reg [DATA_WIDTH - 1: 0] r_reg_out_data;
wire w_axi_rst;
wire w_axis_rst;
wire [31:0] w_debug;
reg [PIXEL_WIDTH - 1: 0] r_fg_color;
reg [PIXEL_WIDTH - 1: 0] r_bg_color;
reg r_alt_char;
reg [2:0] r_tab_count;
reg r_cmd_stb;
reg r_char_stb;
wire w_wr_char_rdy;
wire [3:0] w_cosd_state;
wire [15:0] w_pcount;
reg [31:0] r_x_start;
reg [31:0] r_x_end;
reg [31:0] r_y_start;
reg [31:0] r_y_end;
axi_lite_slave #(
.ADDR_WIDTH (ADDR_WIDTH ),
.DATA_WIDTH (DATA_WIDTH )
) axi_lite_reg_interface (
.clk (clk ),
.rst (w_axi_rst ),
.i_awvalid (i_awvalid ),
.i_awaddr (i_awaddr ),
.o_awready (o_awready ),
.i_wvalid (i_wvalid ),
.o_wready (o_wready ),
.i_wstrb (i_wstrb ),
.i_wdata (i_wdata ),
.o_bvalid (o_bvalid ),
.i_bready (i_bready ),
.o_bresp (o_bresp ),
.i_arvalid (i_arvalid ),
.o_arready (o_arready ),
.i_araddr (i_araddr ),
.o_rvalid (o_rvalid ),
.i_rready (i_rready ),
.o_rresp (o_rresp ),
.o_rdata (o_rdata ),
.o_reg_address (w_reg_address ),
.i_reg_invalid_addr (r_reg_invalid_addr ),
.o_reg_in_rdy (w_reg_in_rdy ),
.i_reg_in_ack_stb (r_reg_in_ack_stb ),
.o_reg_in_data (w_reg_in_data ),
.o_reg_out_req (w_reg_out_req ),
.i_reg_out_rdy_stb (r_reg_out_rdy_stb ),
.i_reg_out_data (r_reg_out_data )
);
console_osd #(
.CONSOLE_DEPTH (CONSOLE_DEPTH ),
.IMAGE_WIDTH (IMAGE_WIDTH ),
.IMAGE_HEIGHT (IMAGE_HEIGHT ),
.BUFFER_DEPTH (BUFFER_DEPTH ),
.PIXEL_WIDTH (PIXEL_WIDTH ),
.FONT_WIDTH (FONT_WIDTH ),
.FONT_HEIGHT (FONT_HEIGHT )
)cosd(
.clk (clk ),
.rst (w_axi_rst ),
.i_enable (r_enable ),
.i_fg_color (r_fg_color ),
.i_bg_color (r_bg_color ),
.i_cmd_stb (r_cmd_stb ),
.i_cmd (r_console_command ),
.i_char_stb (r_char_stb ),
.i_char (r_char_data ),
.o_wr_char_rdy (w_wr_char_rdy ),
.i_clear_screen_stb (r_clear_screen_stb ),
.i_alt_func_en (r_alt_char ),
.i_tab_count (r_tab_count ),
.i_scroll_en (r_scroll_en ),
.i_scroll_up_stb (r_scroll_up_stb ),
.i_scroll_down_stb (r_scroll_down_stb ),
.i_x_start (r_x_start ),
.i_x_end (r_x_end ),
.i_y_start (r_y_start ),
.i_y_end (r_y_end ),
.i_ppfifo_clk (i_axis_clk ),
.i_ppfifo_rst (w_axis_rst ),
.o_ppfifo_rdy (wfifo_rdy ),
.i_ppfifo_act (wfifo_act ),
.o_ppfifo_size (wfifo_size ),
.o_ppfifo_data (wfifo_data ),
.i_ppfifo_stb (wfifo_stb ),
.o_state (w_cosd_state ),
.o_pixel_count (w_pcount )
);
adapter_ppfifo_2_axi_stream #(
.DATA_WIDTH (AXIS_WIDTH )
) as2p (
.rst (w_axis_rst ),
.i_axi_clk (i_axis_clk ),
.i_axi_ready (i_axis_ready ),
.o_axi_data (o_axis_data ),
.o_axi_last (o_axis_last ),
.o_axi_valid (o_axis_valid ),
.o_axi_user (o_axis_user ),
.i_ppfifo_rdy (wfifo_rdy ),
.o_ppfifo_act (wfifo_act ),
.i_ppfifo_size (wfifo_size ),
.o_ppfifo_stb (wfifo_stb ),
.i_ppfifo_data (wfifo_data ),
.o_debug (w_adapter_debug )
);
assign w_axi_rst = (INVERT_AXI_RESET) ? ~rst : rst;
assign w_axis_rst = (INVERT_AXIS_RESET) ? ~i_axis_rst : i_axis_rst;
assign w_reg_32bit_address = w_reg_address[(ADDR_WIDTH - 1):2];
always @ (posedge clk) begin
r_reg_in_ack_stb <= 0;
r_reg_out_rdy_stb <= 0;
r_reg_invalid_addr <= 0;
r_cmd_stb <= 0;
r_char_stb <= 0;
r_alt_char <= 0;
r_clear_screen_stb <= 0;
r_scroll_up_stb <= 0;
r_scroll_down_stb <= 0;
if (w_axi_rst) begin
r_enable <= 0;
r_scroll_en <= 0;
r_reg_out_data <= 0;
r_image_width <= IMAGE_WIDTH;
r_image_height <= IMAGE_HEIGHT;
r_image_size <= (IMAGE_WIDTH * IMAGE_HEIGHT);
r_x_start <= DEFAULT_X_START;
r_x_end <= DEFAULT_X_END;
r_y_start <= DEFAULT_Y_START;
r_y_end <= DEFAULT_Y_END;
r_fg_color <= FOREGROUND_COLOR;
r_bg_color <= BACKGROUND_COLOR;
r_tab_count <= DEFAULT_TAB_COUNT;
r_char_data <= 0;
r_console_command <= 0;
end
else begin
if (w_reg_in_rdy) begin
case (w_reg_32bit_address)
REG_CONTROL: begin
r_enable <= w_reg_in_data[`BIT_CTRL_EN];
r_clear_screen_stb <= w_reg_in_data[`BIT_CTRL_CLEAR_SCREEN_STB];
r_scroll_en <= w_reg_in_data[`BIT_CTRL_SCROLL_EN];
r_scroll_up_stb <= w_reg_in_data[`BIT_CTRL_SCROLL_UP_STB];
r_scroll_down_stb <= w_reg_in_data[`BIT_CTRL_SCROLL_DOWN_STB];
end
REG_FG_COLOR: begin
r_fg_color <= w_reg_in_data[AXIS_WIDTH - 1: 0];
end
REG_BG_COLOR: begin
r_bg_color <= w_reg_in_data[AXIS_WIDTH - 1: 0];
end
REG_CONSOLE_CHAR: begin
r_char_data <= w_reg_in_data[`CHAR_ADDR_RANGE];
r_alt_char <= w_reg_in_data[`BIT_CHAR_ALT_ENABLE];
if (w_wr_char_rdy) begin
r_char_stb <= 1;
end
end
REG_CONSOLE_COMMAND: begin
r_console_command <= w_reg_in_data;
end
REG_X_START: begin
r_x_start <= w_reg_in_data;
end
REG_X_END: begin
r_x_end <= w_reg_in_data;
end
REG_Y_START: begin
r_y_start <= w_reg_in_data;
end
REG_Y_END: begin
r_y_end <= w_reg_in_data;
end
REG_TAB_COUNT: begin
r_tab_count <= w_reg_in_data[`TAB_COUNT_RANGE];
end
default: begin
end
endcase
if (w_reg_32bit_address > REG_VERSION) begin
r_reg_invalid_addr <= 1;
end
else if (w_reg_32bit_address == REG_CONSOLE_CHAR) begin
if (w_wr_char_rdy) begin
r_reg_in_ack_stb <= 1;
end
end
else begin
r_reg_in_ack_stb <= 1;
end
end
else if (w_reg_out_req) begin
case (w_reg_32bit_address)
REG_CONTROL: begin
r_reg_out_data <= 0;
r_reg_out_data[`BIT_CTRL_EN] <= r_enable;
r_reg_out_data[`BIT_CTRL_SCROLL_EN] <= r_scroll_en;
end
REG_STATUS: begin
r_reg_out_data <= 0;
r_reg_out_data[`BIT_AXIS_RST] <= w_axis_rst;
r_reg_out_data[`BIT_RANGE_COSD_STATE]<= w_cosd_state;
r_reg_out_data[`BIT_AXIS_RDY] <= i_axis_ready;
r_reg_out_data[`BIT_AXIS_VLD] <= o_axis_valid;
r_reg_out_data[`BIT_AXIS_USR] <= o_axis_user[0];
r_reg_out_data[`BIT_AXIS_LST] <= o_axis_last;
r_reg_out_data[`BIT_RANGE_PCOUNT] <= w_pcount;
end
REG_IMAGE_WIDTH: begin
r_reg_out_data <= r_image_width;
end
REG_IMAGE_HEIGHT: begin
r_reg_out_data <= r_image_height;
end
REG_IMAGE_SIZE: begin
r_reg_out_data <= r_image_size;
end
REG_FG_COLOR: begin
r_reg_out_data <= {8'h0, r_fg_color};
end
REG_BG_COLOR: begin
r_reg_out_data <= {8'h0, r_bg_color};
end
REG_CONSOLE_CHAR: begin
r_reg_out_data <= r_char_data;
end
REG_CONSOLE_COMMAND: begin
r_reg_out_data <= r_console_command;
end
REG_X_START: begin
r_reg_out_data <= r_x_start;
end
REG_X_END: begin
r_reg_out_data <= r_x_end;
end
REG_Y_START: begin
r_reg_out_data <= r_y_start;
end
REG_Y_END: begin
r_reg_out_data <= r_y_end;
end
REG_TAB_COUNT: begin
r_reg_out_data[`TAB_COUNT_RANGE]<= r_tab_count;
end
REG_ADAPTER_DEBUG: begin
r_reg_out_data <= w_adapter_debug;
end
REG_VERSION: begin
r_reg_out_data <= 32'h00;
r_reg_out_data[`MAJOR_RANGE] <= `MAJOR_VERSION;
r_reg_out_data[`MINOR_RANGE] <= `MINOR_VERSION;
r_reg_out_data[`REVISION_RANGE] <= `REVISION;
end
default: begin
r_reg_out_data <= 32'h00;
end
endcase
if (w_reg_32bit_address > REG_VERSION) begin
r_reg_invalid_addr <= 1;
end
r_reg_out_rdy_stb <= 1;
end
end
end
endmodule | 20 |
139,159 | data/full_repos/permissive/86862934/ip/axi_pmod_tft/verilog/axi/slave/axi_pmod_tft/rtl/axi_pmod_tft.v | 86,862,934 | axi_pmod_tft.v | v | 521 | 90 | [] | [] | [] | [(89, 531)] | null | null | 1: b'%Error: data/full_repos/permissive/86862934/ip/axi_pmod_tft/verilog/axi/slave/axi_pmod_tft/rtl/axi_pmod_tft.v:33: Cannot find include file: nh_lcd_defines.v\n`include "nh_lcd_defines.v" \n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86862934/ip/axi_pmod_tft/verilog/axi/slave/axi_pmod_tft/rtl,data/full_repos/permissive/86862934/nh_lcd_defines.v\n data/full_repos/permissive/86862934/ip/axi_pmod_tft/verilog/axi/slave/axi_pmod_tft/rtl,data/full_repos/permissive/86862934/nh_lcd_defines.v.v\n data/full_repos/permissive/86862934/ip/axi_pmod_tft/verilog/axi/slave/axi_pmod_tft/rtl,data/full_repos/permissive/86862934/nh_lcd_defines.v.sv\n nh_lcd_defines.v\n nh_lcd_defines.v.v\n nh_lcd_defines.v.sv\n obj_dir/nh_lcd_defines.v\n obj_dir/nh_lcd_defines.v.v\n obj_dir/nh_lcd_defines.v.sv\n%Error: Exiting due to 1 error(s)\n' | 304,395 | module | module axi_pmod_tft #(
parameter ADDR_WIDTH = 7,
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = (DATA_WIDTH / 8),
parameter AXIS_WIDTH = 24,
parameter INVERT_AXI_RESET = 1,
parameter INVERT_AXIS_RESET = 1,
parameter IMAGE_WIDTH = 480,
parameter IMAGE_HEIGHT = 272,
parameter BUFFER_SIZE = 10
)(
input clk,
input rst,
output o_fsync,
output o_register_data_sel,
output o_write_n,
output o_read_n,
output o_cs_n,
output o_reset_n,
input i_tearing_effect,
output o_pmod_out_tft_data1,
output o_pmod_out_tft_data2,
output o_pmod_out_tft_data3,
output o_pmod_out_tft_data4,
output o_pmod_out_tft_data7,
output o_pmod_out_tft_data8,
output o_pmod_out_tft_data9,
output o_pmod_out_tft_data10,
output o_pmod_tri_tft_data1,
output o_pmod_tri_tft_data2,
output o_pmod_tri_tft_data3,
output o_pmod_tri_tft_data4,
output o_pmod_tri_tft_data7,
output o_pmod_tri_tft_data8,
output o_pmod_tri_tft_data9,
output o_pmod_tri_tft_data10,
input i_pmod_in_tft_data1,
input i_pmod_in_tft_data2,
input i_pmod_in_tft_data3,
input i_pmod_in_tft_data4,
input i_pmod_in_tft_data7,
input i_pmod_in_tft_data8,
input i_pmod_in_tft_data9,
input i_pmod_in_tft_data10,
input i_awvalid,
input [ADDR_WIDTH - 1: 0] i_awaddr,
output o_awready,
input i_wvalid,
output o_wready,
input [STROBE_WIDTH - 1:0] i_wstrb,
input [DATA_WIDTH - 1: 0] i_wdata,
output o_bvalid,
input i_bready,
output [1:0] o_bresp,
input i_arvalid,
output o_arready,
input [ADDR_WIDTH - 1: 0] i_araddr,
output o_rvalid,
input i_rready,
output [1:0] o_rresp,
output [DATA_WIDTH - 1: 0] o_rdata,
input i_axis_clk,
input [3:0] i_axis_user,
input i_axis_rst,
input [AXIS_WIDTH - 1:0] i_axis_data,
output o_axis_ready,
input i_axis_last,
input i_axis_valid
);
localparam REG_CONTROL = 0;
localparam REG_STATUS = 1;
localparam REG_COMMAND_DATA = 2;
localparam REG_IMAGE_WIDTH = 3;
localparam REG_IMAGE_HEIGHT = 4;
localparam REG_IMAGE_SIZE = 5;
localparam REG_VERSION = 6;
reg [31:0] control;
wire [31:0] status;
wire w_enable;
wire w_enable_interrupt;
wire w_reset_display;
wire w_cmd_mode;
wire w_cmd_write_stb;
wire w_cmd_read_stb;
wire w_cmd_parameter;
wire w_write_override;
wire w_chip_select;
wire w_enable_tearing;
wire w_cmd_finished;
reg [7:0] r_cmd_data_out;
wire [7:0] w_cmd_data_in;
reg [31:0] r_image_width;
reg [31:0] r_image_height;
reg [31:0] r_image_size;
wire wfifo_clk;
wire [23:0] wfifo_size;
wire [1:0] wfifo_ready;
wire [1:0] wfifo_activate;
wire wfifo_strobe;
wire [AXIS_WIDTH:0] wfifo_data;
wire [ADDR_WIDTH - 1: 0] w_reg_address;
wire [((ADDR_WIDTH-1) - 2):0] w_reg_32bit_address;
reg r_reg_invalid_addr;
wire w_reg_in_rdy;
reg r_reg_in_ack_stb;
wire [DATA_WIDTH - 1: 0] w_reg_in_data;
wire w_reg_out_req;
reg r_reg_out_rdy_stb;
reg [DATA_WIDTH - 1: 0] r_reg_out_data;
wire w_axi_rst;
wire w_axis_rst;
wire [31:0] w_debug;
wire [7:0] w_tft_data_out;
wire [7:0] w_tft_data_in;
wire w_read_en;
wire w_tp_red;
wire w_tp_blue;
wire w_tp_green;
axi_lite_slave #(
.ADDR_WIDTH (ADDR_WIDTH ),
.DATA_WIDTH (DATA_WIDTH )
) axi_lite_reg_interface (
.clk (clk ),
.rst (w_axi_rst ),
.i_awvalid (i_awvalid ),
.i_awaddr (i_awaddr ),
.o_awready (o_awready ),
.i_wvalid (i_wvalid ),
.o_wready (o_wready ),
.i_wstrb (i_wstrb ),
.i_wdata (i_wdata ),
.o_bvalid (o_bvalid ),
.i_bready (i_bready ),
.o_bresp (o_bresp ),
.i_arvalid (i_arvalid ),
.o_arready (o_arready ),
.i_araddr (i_araddr ),
.o_rvalid (o_rvalid ),
.i_rready (i_rready ),
.o_rresp (o_rresp ),
.o_rdata (o_rdata ),
.o_reg_address (w_reg_address ),
.i_reg_invalid_addr (r_reg_invalid_addr ),
.o_reg_in_rdy (w_reg_in_rdy ),
.i_reg_in_ack_stb (r_reg_in_ack_stb ),
.o_reg_in_data (w_reg_in_data ),
.o_reg_out_req (w_reg_out_req ),
.i_reg_out_rdy_stb (r_reg_out_rdy_stb ),
.i_reg_out_data (r_reg_out_data )
);
adapter_axi_stream_2_ppfifo_wl #(
.DATA_WIDTH (AXIS_WIDTH )
) as2p (
.rst (w_axis_rst || ~w_enable ),
.i_tear_effect (i_tearing_effect ),
.i_fsync (i_axis_user[0] ),
.i_pixel_count (r_image_size ),
.i_axi_clk (i_axis_clk ),
.o_axi_ready (o_axis_ready ),
.i_axi_data (i_axis_data ),
.i_axi_last (i_axis_last ),
.i_axi_valid (i_axis_valid ),
.o_ppfifo_clk (wfifo_clk ),
.i_ppfifo_rdy (wfifo_ready ),
.o_ppfifo_act (wfifo_activate ),
.i_ppfifo_size (wfifo_size ),
.o_ppfifo_stb (wfifo_strobe ),
.o_ppfifo_data (wfifo_data )
);
nh_lcd #(
.BUFFER_SIZE (BUFFER_SIZE ),
.DATAS_WIDTH (AXIS_WIDTH )
) lcd (
.rst (w_axi_rst || ~w_enable ),
.clk (clk ),
.debug (w_debug ),
.i_enable (w_enable ),
.i_enable_tearing (w_enable_tearing ),
.i_reset_display (w_reset_display ),
.i_cmd_mode (w_cmd_mode ),
.i_cmd_parameter (w_cmd_parameter ),
.i_cmd_write_stb (w_cmd_write_stb ),
.i_cmd_read_stb (w_cmd_read_stb ),
.i_cmd_data (r_cmd_data_out ),
.o_cmd_data (w_cmd_data_in ),
.o_cmd_finished (w_cmd_finished ),
.i_write_override (w_write_override ),
.i_chip_select (w_chip_select ),
.i_image_width (r_image_width ),
.i_image_height (r_image_height ),
.i_fifo_clk (wfifo_clk ),
.i_fifo_rst (w_axis_rst ),
.o_fifo_rdy (wfifo_ready ),
.i_fifo_act (wfifo_activate ),
.i_fifo_stb (wfifo_strobe ),
.o_fifo_size (wfifo_size ),
.i_fifo_data (wfifo_data ),
.o_register_data_sel (o_register_data_sel ),
.o_write_n (o_write_n ),
.o_read_n (o_read_n ),
.o_read_en (w_read_en ),
.o_data (w_tft_data_out ),
.i_data (w_tft_data_in ),
.o_cs_n (o_cs_n ),
.o_reset_n (o_reset_n ),
.i_tearing_effect (i_tearing_effect ),
.i_tp_red (w_tp_red ),
.i_tp_blue (w_tp_blue ),
.i_tp_green (w_tp_green )
);
assign w_enable = control[`CONTROL_ENABLE];
assign w_enable_interrupt = control[`CONTROL_ENABLE_INTERRUPT];
assign w_cmd_mode = control[`CONTROL_COMMAND_MODE];
assign w_reset_display = control[`CONTROL_RESET_DISPLAY];
assign w_cmd_write_stb = control[`CONTROL_COMMAND_WRITE];
assign w_cmd_read_stb = control[`CONTROL_COMMAND_READ];
assign w_cmd_parameter = control[`CONTROL_COMMAND_PARAMETER];
assign w_write_override = control[`CONTROL_WRITE_OVERRIDE];
assign w_chip_select = control[`CONTROL_CHIP_SELECT];
assign w_enable_tearing = control[`CONTROL_ENABLE_TEARING];
assign w_tp_red = control[`CONTROL_TP_RED];
assign w_tp_green = control[`CONTROL_TP_GREEN];
assign w_tp_blue = control[`CONTROL_TP_BLUE];
assign status[31:0] = 0;
assign w_axi_rst = (INVERT_AXI_RESET) ? ~rst : rst;
assign w_axis_rst = (INVERT_AXIS_RESET) ? ~i_axis_rst : i_axis_rst;
assign o_pmod_out_tft_data3 = w_tft_data_out[0];
assign o_pmod_out_tft_data8 = w_tft_data_out[1];
assign o_pmod_out_tft_data2 = w_tft_data_out[2];
assign o_pmod_out_tft_data1 = w_tft_data_out[3];
assign o_pmod_out_tft_data7 = w_tft_data_out[4];
assign o_pmod_out_tft_data9 = w_tft_data_out[5];
assign o_pmod_out_tft_data4 = w_tft_data_out[6];
assign o_pmod_out_tft_data10 = w_tft_data_out[7];
assign o_pmod_tri_tft_data1 = !w_read_en;
assign o_pmod_tri_tft_data2 = !w_read_en;
assign o_pmod_tri_tft_data3 = !w_read_en;
assign o_pmod_tri_tft_data4 = !w_read_en;
assign o_pmod_tri_tft_data7 = !w_read_en;
assign o_pmod_tri_tft_data8 = !w_read_en;
assign o_pmod_tri_tft_data9 = !w_read_en;
assign o_pmod_tri_tft_data10 = !w_read_en;
assign w_tft_data_in[0] = i_pmod_in_tft_data3;
assign w_tft_data_in[1] = i_pmod_in_tft_data8;
assign w_tft_data_in[2] = i_pmod_in_tft_data2;
assign w_tft_data_in[3] = i_pmod_in_tft_data1;
assign w_tft_data_in[4] = i_pmod_in_tft_data7;
assign w_tft_data_in[5] = i_pmod_in_tft_data9;
assign w_tft_data_in[6] = i_pmod_in_tft_data4;
assign w_tft_data_in[7] = i_pmod_in_tft_data10;
assign o_fsync = ~i_tearing_effect;
assign w_reg_32bit_address = w_reg_address[(ADDR_WIDTH - 1):2];
always @ (posedge clk) begin
r_reg_in_ack_stb <= 0;
r_reg_out_rdy_stb <= 0;
r_reg_invalid_addr <= 0;
if (w_axi_rst) begin
control <= 0;
r_reg_out_data <= 0;
r_cmd_data_out <= 0;
r_image_width <= IMAGE_WIDTH;
r_image_height <= IMAGE_HEIGHT;
r_image_size <= (IMAGE_WIDTH * IMAGE_HEIGHT);
end
else begin
if (w_cmd_write_stb) begin
control[`CONTROL_COMMAND_WRITE] <= 0;
end
if (w_cmd_read_stb) begin
control[`CONTROL_COMMAND_READ] <= 0;
end
if (w_tp_red) begin
control[`CONTROL_TP_RED] <= 0;
end
if (w_tp_green) begin
control[`CONTROL_TP_GREEN] <= 0;
end
if (w_tp_blue) begin
control[`CONTROL_TP_BLUE] <= 0;
end
if (w_reg_in_rdy) begin
case (w_reg_32bit_address)
REG_CONTROL: begin
control <= w_reg_in_data;
end
REG_COMMAND_DATA: begin
r_cmd_data_out <= w_reg_in_data[7:0];
end
REG_IMAGE_WIDTH: begin
r_image_width <= w_reg_in_data;
end
REG_IMAGE_HEIGHT: begin
r_image_height <= w_reg_in_data;
end
REG_IMAGE_SIZE: begin
r_image_size <= w_reg_in_data;
end
default: begin
end
endcase
if (w_reg_32bit_address > REG_VERSION) begin
r_reg_invalid_addr <= 1;
end
r_reg_in_ack_stb <= 1;
end
else if (w_reg_out_req) begin
case (w_reg_32bit_address)
REG_CONTROL: begin
r_reg_out_data <= control;
end
REG_STATUS: begin
r_reg_out_data <= status;
end
REG_COMMAND_DATA: begin
r_reg_out_data <= w_cmd_data_in;
end
REG_IMAGE_WIDTH: begin
r_reg_out_data <= r_image_width;
end
REG_IMAGE_HEIGHT: begin
r_reg_out_data <= r_image_height;
end
REG_IMAGE_SIZE: begin
r_reg_out_data <= r_image_size;
end
REG_VERSION: begin
r_reg_out_data <= 32'h00;
r_reg_out_data[`MAJOR_RANGE] <= `MAJOR_VERSION;
r_reg_out_data[`MINOR_RANGE] <= `MINOR_VERSION;
r_reg_out_data[`REVISION_RANGE] <= `REVISION;
end
default: begin
r_reg_out_data <= 32'h00;
end
endcase
if (w_reg_32bit_address > REG_VERSION) begin
r_reg_invalid_addr <= 1;
end
r_reg_out_rdy_stb <= 1;
end
end
end
endmodule | module axi_pmod_tft #(
parameter ADDR_WIDTH = 7,
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = (DATA_WIDTH / 8),
parameter AXIS_WIDTH = 24,
parameter INVERT_AXI_RESET = 1,
parameter INVERT_AXIS_RESET = 1,
parameter IMAGE_WIDTH = 480,
parameter IMAGE_HEIGHT = 272,
parameter BUFFER_SIZE = 10
)(
input clk,
input rst,
output o_fsync,
output o_register_data_sel,
output o_write_n,
output o_read_n,
output o_cs_n,
output o_reset_n,
input i_tearing_effect,
output o_pmod_out_tft_data1,
output o_pmod_out_tft_data2,
output o_pmod_out_tft_data3,
output o_pmod_out_tft_data4,
output o_pmod_out_tft_data7,
output o_pmod_out_tft_data8,
output o_pmod_out_tft_data9,
output o_pmod_out_tft_data10,
output o_pmod_tri_tft_data1,
output o_pmod_tri_tft_data2,
output o_pmod_tri_tft_data3,
output o_pmod_tri_tft_data4,
output o_pmod_tri_tft_data7,
output o_pmod_tri_tft_data8,
output o_pmod_tri_tft_data9,
output o_pmod_tri_tft_data10,
input i_pmod_in_tft_data1,
input i_pmod_in_tft_data2,
input i_pmod_in_tft_data3,
input i_pmod_in_tft_data4,
input i_pmod_in_tft_data7,
input i_pmod_in_tft_data8,
input i_pmod_in_tft_data9,
input i_pmod_in_tft_data10,
input i_awvalid,
input [ADDR_WIDTH - 1: 0] i_awaddr,
output o_awready,
input i_wvalid,
output o_wready,
input [STROBE_WIDTH - 1:0] i_wstrb,
input [DATA_WIDTH - 1: 0] i_wdata,
output o_bvalid,
input i_bready,
output [1:0] o_bresp,
input i_arvalid,
output o_arready,
input [ADDR_WIDTH - 1: 0] i_araddr,
output o_rvalid,
input i_rready,
output [1:0] o_rresp,
output [DATA_WIDTH - 1: 0] o_rdata,
input i_axis_clk,
input [3:0] i_axis_user,
input i_axis_rst,
input [AXIS_WIDTH - 1:0] i_axis_data,
output o_axis_ready,
input i_axis_last,
input i_axis_valid
); |
localparam REG_CONTROL = 0;
localparam REG_STATUS = 1;
localparam REG_COMMAND_DATA = 2;
localparam REG_IMAGE_WIDTH = 3;
localparam REG_IMAGE_HEIGHT = 4;
localparam REG_IMAGE_SIZE = 5;
localparam REG_VERSION = 6;
reg [31:0] control;
wire [31:0] status;
wire w_enable;
wire w_enable_interrupt;
wire w_reset_display;
wire w_cmd_mode;
wire w_cmd_write_stb;
wire w_cmd_read_stb;
wire w_cmd_parameter;
wire w_write_override;
wire w_chip_select;
wire w_enable_tearing;
wire w_cmd_finished;
reg [7:0] r_cmd_data_out;
wire [7:0] w_cmd_data_in;
reg [31:0] r_image_width;
reg [31:0] r_image_height;
reg [31:0] r_image_size;
wire wfifo_clk;
wire [23:0] wfifo_size;
wire [1:0] wfifo_ready;
wire [1:0] wfifo_activate;
wire wfifo_strobe;
wire [AXIS_WIDTH:0] wfifo_data;
wire [ADDR_WIDTH - 1: 0] w_reg_address;
wire [((ADDR_WIDTH-1) - 2):0] w_reg_32bit_address;
reg r_reg_invalid_addr;
wire w_reg_in_rdy;
reg r_reg_in_ack_stb;
wire [DATA_WIDTH - 1: 0] w_reg_in_data;
wire w_reg_out_req;
reg r_reg_out_rdy_stb;
reg [DATA_WIDTH - 1: 0] r_reg_out_data;
wire w_axi_rst;
wire w_axis_rst;
wire [31:0] w_debug;
wire [7:0] w_tft_data_out;
wire [7:0] w_tft_data_in;
wire w_read_en;
wire w_tp_red;
wire w_tp_blue;
wire w_tp_green;
axi_lite_slave #(
.ADDR_WIDTH (ADDR_WIDTH ),
.DATA_WIDTH (DATA_WIDTH )
) axi_lite_reg_interface (
.clk (clk ),
.rst (w_axi_rst ),
.i_awvalid (i_awvalid ),
.i_awaddr (i_awaddr ),
.o_awready (o_awready ),
.i_wvalid (i_wvalid ),
.o_wready (o_wready ),
.i_wstrb (i_wstrb ),
.i_wdata (i_wdata ),
.o_bvalid (o_bvalid ),
.i_bready (i_bready ),
.o_bresp (o_bresp ),
.i_arvalid (i_arvalid ),
.o_arready (o_arready ),
.i_araddr (i_araddr ),
.o_rvalid (o_rvalid ),
.i_rready (i_rready ),
.o_rresp (o_rresp ),
.o_rdata (o_rdata ),
.o_reg_address (w_reg_address ),
.i_reg_invalid_addr (r_reg_invalid_addr ),
.o_reg_in_rdy (w_reg_in_rdy ),
.i_reg_in_ack_stb (r_reg_in_ack_stb ),
.o_reg_in_data (w_reg_in_data ),
.o_reg_out_req (w_reg_out_req ),
.i_reg_out_rdy_stb (r_reg_out_rdy_stb ),
.i_reg_out_data (r_reg_out_data )
);
adapter_axi_stream_2_ppfifo_wl #(
.DATA_WIDTH (AXIS_WIDTH )
) as2p (
.rst (w_axis_rst || ~w_enable ),
.i_tear_effect (i_tearing_effect ),
.i_fsync (i_axis_user[0] ),
.i_pixel_count (r_image_size ),
.i_axi_clk (i_axis_clk ),
.o_axi_ready (o_axis_ready ),
.i_axi_data (i_axis_data ),
.i_axi_last (i_axis_last ),
.i_axi_valid (i_axis_valid ),
.o_ppfifo_clk (wfifo_clk ),
.i_ppfifo_rdy (wfifo_ready ),
.o_ppfifo_act (wfifo_activate ),
.i_ppfifo_size (wfifo_size ),
.o_ppfifo_stb (wfifo_strobe ),
.o_ppfifo_data (wfifo_data )
);
nh_lcd #(
.BUFFER_SIZE (BUFFER_SIZE ),
.DATAS_WIDTH (AXIS_WIDTH )
) lcd (
.rst (w_axi_rst || ~w_enable ),
.clk (clk ),
.debug (w_debug ),
.i_enable (w_enable ),
.i_enable_tearing (w_enable_tearing ),
.i_reset_display (w_reset_display ),
.i_cmd_mode (w_cmd_mode ),
.i_cmd_parameter (w_cmd_parameter ),
.i_cmd_write_stb (w_cmd_write_stb ),
.i_cmd_read_stb (w_cmd_read_stb ),
.i_cmd_data (r_cmd_data_out ),
.o_cmd_data (w_cmd_data_in ),
.o_cmd_finished (w_cmd_finished ),
.i_write_override (w_write_override ),
.i_chip_select (w_chip_select ),
.i_image_width (r_image_width ),
.i_image_height (r_image_height ),
.i_fifo_clk (wfifo_clk ),
.i_fifo_rst (w_axis_rst ),
.o_fifo_rdy (wfifo_ready ),
.i_fifo_act (wfifo_activate ),
.i_fifo_stb (wfifo_strobe ),
.o_fifo_size (wfifo_size ),
.i_fifo_data (wfifo_data ),
.o_register_data_sel (o_register_data_sel ),
.o_write_n (o_write_n ),
.o_read_n (o_read_n ),
.o_read_en (w_read_en ),
.o_data (w_tft_data_out ),
.i_data (w_tft_data_in ),
.o_cs_n (o_cs_n ),
.o_reset_n (o_reset_n ),
.i_tearing_effect (i_tearing_effect ),
.i_tp_red (w_tp_red ),
.i_tp_blue (w_tp_blue ),
.i_tp_green (w_tp_green )
);
assign w_enable = control[`CONTROL_ENABLE];
assign w_enable_interrupt = control[`CONTROL_ENABLE_INTERRUPT];
assign w_cmd_mode = control[`CONTROL_COMMAND_MODE];
assign w_reset_display = control[`CONTROL_RESET_DISPLAY];
assign w_cmd_write_stb = control[`CONTROL_COMMAND_WRITE];
assign w_cmd_read_stb = control[`CONTROL_COMMAND_READ];
assign w_cmd_parameter = control[`CONTROL_COMMAND_PARAMETER];
assign w_write_override = control[`CONTROL_WRITE_OVERRIDE];
assign w_chip_select = control[`CONTROL_CHIP_SELECT];
assign w_enable_tearing = control[`CONTROL_ENABLE_TEARING];
assign w_tp_red = control[`CONTROL_TP_RED];
assign w_tp_green = control[`CONTROL_TP_GREEN];
assign w_tp_blue = control[`CONTROL_TP_BLUE];
assign status[31:0] = 0;
assign w_axi_rst = (INVERT_AXI_RESET) ? ~rst : rst;
assign w_axis_rst = (INVERT_AXIS_RESET) ? ~i_axis_rst : i_axis_rst;
assign o_pmod_out_tft_data3 = w_tft_data_out[0];
assign o_pmod_out_tft_data8 = w_tft_data_out[1];
assign o_pmod_out_tft_data2 = w_tft_data_out[2];
assign o_pmod_out_tft_data1 = w_tft_data_out[3];
assign o_pmod_out_tft_data7 = w_tft_data_out[4];
assign o_pmod_out_tft_data9 = w_tft_data_out[5];
assign o_pmod_out_tft_data4 = w_tft_data_out[6];
assign o_pmod_out_tft_data10 = w_tft_data_out[7];
assign o_pmod_tri_tft_data1 = !w_read_en;
assign o_pmod_tri_tft_data2 = !w_read_en;
assign o_pmod_tri_tft_data3 = !w_read_en;
assign o_pmod_tri_tft_data4 = !w_read_en;
assign o_pmod_tri_tft_data7 = !w_read_en;
assign o_pmod_tri_tft_data8 = !w_read_en;
assign o_pmod_tri_tft_data9 = !w_read_en;
assign o_pmod_tri_tft_data10 = !w_read_en;
assign w_tft_data_in[0] = i_pmod_in_tft_data3;
assign w_tft_data_in[1] = i_pmod_in_tft_data8;
assign w_tft_data_in[2] = i_pmod_in_tft_data2;
assign w_tft_data_in[3] = i_pmod_in_tft_data1;
assign w_tft_data_in[4] = i_pmod_in_tft_data7;
assign w_tft_data_in[5] = i_pmod_in_tft_data9;
assign w_tft_data_in[6] = i_pmod_in_tft_data4;
assign w_tft_data_in[7] = i_pmod_in_tft_data10;
assign o_fsync = ~i_tearing_effect;
assign w_reg_32bit_address = w_reg_address[(ADDR_WIDTH - 1):2];
always @ (posedge clk) begin
r_reg_in_ack_stb <= 0;
r_reg_out_rdy_stb <= 0;
r_reg_invalid_addr <= 0;
if (w_axi_rst) begin
control <= 0;
r_reg_out_data <= 0;
r_cmd_data_out <= 0;
r_image_width <= IMAGE_WIDTH;
r_image_height <= IMAGE_HEIGHT;
r_image_size <= (IMAGE_WIDTH * IMAGE_HEIGHT);
end
else begin
if (w_cmd_write_stb) begin
control[`CONTROL_COMMAND_WRITE] <= 0;
end
if (w_cmd_read_stb) begin
control[`CONTROL_COMMAND_READ] <= 0;
end
if (w_tp_red) begin
control[`CONTROL_TP_RED] <= 0;
end
if (w_tp_green) begin
control[`CONTROL_TP_GREEN] <= 0;
end
if (w_tp_blue) begin
control[`CONTROL_TP_BLUE] <= 0;
end
if (w_reg_in_rdy) begin
case (w_reg_32bit_address)
REG_CONTROL: begin
control <= w_reg_in_data;
end
REG_COMMAND_DATA: begin
r_cmd_data_out <= w_reg_in_data[7:0];
end
REG_IMAGE_WIDTH: begin
r_image_width <= w_reg_in_data;
end
REG_IMAGE_HEIGHT: begin
r_image_height <= w_reg_in_data;
end
REG_IMAGE_SIZE: begin
r_image_size <= w_reg_in_data;
end
default: begin
end
endcase
if (w_reg_32bit_address > REG_VERSION) begin
r_reg_invalid_addr <= 1;
end
r_reg_in_ack_stb <= 1;
end
else if (w_reg_out_req) begin
case (w_reg_32bit_address)
REG_CONTROL: begin
r_reg_out_data <= control;
end
REG_STATUS: begin
r_reg_out_data <= status;
end
REG_COMMAND_DATA: begin
r_reg_out_data <= w_cmd_data_in;
end
REG_IMAGE_WIDTH: begin
r_reg_out_data <= r_image_width;
end
REG_IMAGE_HEIGHT: begin
r_reg_out_data <= r_image_height;
end
REG_IMAGE_SIZE: begin
r_reg_out_data <= r_image_size;
end
REG_VERSION: begin
r_reg_out_data <= 32'h00;
r_reg_out_data[`MAJOR_RANGE] <= `MAJOR_VERSION;
r_reg_out_data[`MINOR_RANGE] <= `MINOR_VERSION;
r_reg_out_data[`REVISION_RANGE] <= `REVISION;
end
default: begin
r_reg_out_data <= 32'h00;
end
endcase
if (w_reg_32bit_address > REG_VERSION) begin
r_reg_invalid_addr <= 1;
end
r_reg_out_rdy_stb <= 1;
end
end
end
endmodule | 20 |
139,160 | data/full_repos/permissive/86873408/final.v | 86,873,408 | final.v | v | 681 | 166 | [] | [] | [] | null | line:92: before: "." | null | 1: b'%Error: data/full_repos/permissive/86873408/final.v:6: syntax error, unexpected final, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule final\n ^~~~~\n%Error: data/full_repos/permissive/86873408/final.v:64: syntax error, unexpected assign\n assign colour_in = 3\'b111; \n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:70: syntax error, unexpected assign\n assign leftIn = ~KEY[3];\n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:488: syntax error, unexpected \'(\', expecting IDENTIFIER\n hex_decoder(score [3:0], HEXOutOnes);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/86873408/final.v:511: Value too large for 2 bit number: 4\n S_PLOT = 2\'d4;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 304,403 | module | module final
(
CLOCK_50,
KEY,
SW,
LEDR,
LEDG,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B
);
input CLOCK_50;
input [17:0] SW;
input [3:0] KEY;
output [17:0] LEDR;
output [8:0] LEDG;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
wire resetn, go, doneDrop, ld_val, startDrop, Ychange, draw, drawing, writeOK, write;
wire [7:0] coin_x;
wire [7:0] user_x;
wire [6:0] outY;
wire [7:0] outX;
wire [2:0] colour;
wire [7:0] x;
wire [6:0] y;
wire writeEn = write && startDrop;
wire ld_x;
wire colour_in;
assign colour_in = 3'b111;
wire [7:0] xCoorOut;
wire out_clk;
wire leftIn, rightIn;
assign leftIn = ~KEY[3];
assign rightIn = ~KEY[2];
vga_adapter VGA(
.resetn(1'b1),
.clock(clk),
.colour(colour),
.x(x),
.y(y),
.plot(writeEn),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK));
defparam VGA.RESOLUTION = "160x120";
defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
defparam VGA.BACKGROUND_IMAGE = "black.mif";
assign resetn = 1'b1;
assign clk = CLOCK_50;
assign LEDR[16] = startDrop;
assign LEDR[14] = doneDrop;
assign LEDR[13] = draw;
assign LEDR[12] = ld_x;
hex_decoder({1'b0, outY[6:4]}, HEX3);
hex_decoder(outY[3:0], HEX2);
hex_decoder(xCoorOut[7:4], HEX5);
hex_decoder(xCoorOut[3:0], HEX4);
iterateY c3(clk, startDrop, outY, Ychange, doneDrop);
fsmi c1(clk, resetn, go, doneDrop, ld_val, startDrop, LEDG[1:0]);
fsmii c2(clk, resetn, Ychange, startDrop, draw, drawing, LEDR[4:0]);
randomizer r1(clk, xCoorOut, go, outX);
scoreKeeper out0(resetn, Ychange, xCoorOut, coin_x, y, HEX0, HEX1);
control c0(clk, resetn, leftIn, rightIn, drawing, ld_x, writeOK, LEDR[7:5]);
RateDivider divide_rate(.clk(CLOCK_50), .switch(2'b01), .out(out_clk));
player player0(leftIn, rightIn, xCoorOut, out_clk);
datapath d0(clk, resetn, draw, drawing, ld_val, outX, outY, xCoorOut, ld_x, leftIn, rightIn, writeOK, colour, x, y, write, coin_x);
assign LEDG[7] = ~KEY[3];
assign LEDG[6] = ~KEY[2];
endmodule | module final
(
CLOCK_50,
KEY,
SW,
LEDR,
LEDG,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B
); |
input CLOCK_50;
input [17:0] SW;
input [3:0] KEY;
output [17:0] LEDR;
output [8:0] LEDG;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
wire resetn, go, doneDrop, ld_val, startDrop, Ychange, draw, drawing, writeOK, write;
wire [7:0] coin_x;
wire [7:0] user_x;
wire [6:0] outY;
wire [7:0] outX;
wire [2:0] colour;
wire [7:0] x;
wire [6:0] y;
wire writeEn = write && startDrop;
wire ld_x;
wire colour_in;
assign colour_in = 3'b111;
wire [7:0] xCoorOut;
wire out_clk;
wire leftIn, rightIn;
assign leftIn = ~KEY[3];
assign rightIn = ~KEY[2];
vga_adapter VGA(
.resetn(1'b1),
.clock(clk),
.colour(colour),
.x(x),
.y(y),
.plot(writeEn),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK));
defparam VGA.RESOLUTION = "160x120";
defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
defparam VGA.BACKGROUND_IMAGE = "black.mif";
assign resetn = 1'b1;
assign clk = CLOCK_50;
assign LEDR[16] = startDrop;
assign LEDR[14] = doneDrop;
assign LEDR[13] = draw;
assign LEDR[12] = ld_x;
hex_decoder({1'b0, outY[6:4]}, HEX3);
hex_decoder(outY[3:0], HEX2);
hex_decoder(xCoorOut[7:4], HEX5);
hex_decoder(xCoorOut[3:0], HEX4);
iterateY c3(clk, startDrop, outY, Ychange, doneDrop);
fsmi c1(clk, resetn, go, doneDrop, ld_val, startDrop, LEDG[1:0]);
fsmii c2(clk, resetn, Ychange, startDrop, draw, drawing, LEDR[4:0]);
randomizer r1(clk, xCoorOut, go, outX);
scoreKeeper out0(resetn, Ychange, xCoorOut, coin_x, y, HEX0, HEX1);
control c0(clk, resetn, leftIn, rightIn, drawing, ld_x, writeOK, LEDR[7:5]);
RateDivider divide_rate(.clk(CLOCK_50), .switch(2'b01), .out(out_clk));
player player0(leftIn, rightIn, xCoorOut, out_clk);
datapath d0(clk, resetn, draw, drawing, ld_val, outX, outY, xCoorOut, ld_x, leftIn, rightIn, writeOK, colour, x, y, write, coin_x);
assign LEDG[7] = ~KEY[3];
assign LEDG[6] = ~KEY[2];
endmodule | 0 |
139,161 | data/full_repos/permissive/86873408/final.v | 86,873,408 | final.v | v | 681 | 166 | [] | [] | [] | null | line:92: before: "." | null | 1: b'%Error: data/full_repos/permissive/86873408/final.v:6: syntax error, unexpected final, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule final\n ^~~~~\n%Error: data/full_repos/permissive/86873408/final.v:64: syntax error, unexpected assign\n assign colour_in = 3\'b111; \n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:70: syntax error, unexpected assign\n assign leftIn = ~KEY[3];\n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:488: syntax error, unexpected \'(\', expecting IDENTIFIER\n hex_decoder(score [3:0], HEXOutOnes);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/86873408/final.v:511: Value too large for 2 bit number: 4\n S_PLOT = 2\'d4;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 304,403 | module | module fsmi(clk, resetn, go, doneDrop, ld_val, startDrop, LEDG);
input clk;
input resetn;
input go;
input doneDrop;
output reg ld_val, startDrop;
output [1:0] LEDG;
reg [5:0] current_state, next_state;
localparam S_LOAD_Val = 2'b01,
S_PLOT = 2'b10;
always@(*)
begin: state_table
case (current_state)
S_LOAD_Val: next_state = go ? S_PLOT : S_LOAD_Val;
S_PLOT: next_state = doneDrop ? S_LOAD_Val : S_PLOT;
default: next_state = S_LOAD_Val;
endcase
end
always@(*)
begin: enable_signals
ld_val = 1'b0;
startDrop = 1'b0;
case (current_state)
S_LOAD_Val: begin
ld_val = 1'b1;
end
S_PLOT: begin
startDrop = 1'b1;
end
endcase
end
always@(posedge clk)
begin: state_FFs
if(!resetn)
current_state <= S_LOAD_Val;
else
current_state <= next_state;
end
assign LEDG = current_state;
endmodule | module fsmi(clk, resetn, go, doneDrop, ld_val, startDrop, LEDG); |
input clk;
input resetn;
input go;
input doneDrop;
output reg ld_val, startDrop;
output [1:0] LEDG;
reg [5:0] current_state, next_state;
localparam S_LOAD_Val = 2'b01,
S_PLOT = 2'b10;
always@(*)
begin: state_table
case (current_state)
S_LOAD_Val: next_state = go ? S_PLOT : S_LOAD_Val;
S_PLOT: next_state = doneDrop ? S_LOAD_Val : S_PLOT;
default: next_state = S_LOAD_Val;
endcase
end
always@(*)
begin: enable_signals
ld_val = 1'b0;
startDrop = 1'b0;
case (current_state)
S_LOAD_Val: begin
ld_val = 1'b1;
end
S_PLOT: begin
startDrop = 1'b1;
end
endcase
end
always@(posedge clk)
begin: state_FFs
if(!resetn)
current_state <= S_LOAD_Val;
else
current_state <= next_state;
end
assign LEDG = current_state;
endmodule | 0 |
139,162 | data/full_repos/permissive/86873408/final.v | 86,873,408 | final.v | v | 681 | 166 | [] | [] | [] | null | line:92: before: "." | null | 1: b'%Error: data/full_repos/permissive/86873408/final.v:6: syntax error, unexpected final, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule final\n ^~~~~\n%Error: data/full_repos/permissive/86873408/final.v:64: syntax error, unexpected assign\n assign colour_in = 3\'b111; \n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:70: syntax error, unexpected assign\n assign leftIn = ~KEY[3];\n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:488: syntax error, unexpected \'(\', expecting IDENTIFIER\n hex_decoder(score [3:0], HEXOutOnes);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/86873408/final.v:511: Value too large for 2 bit number: 4\n S_PLOT = 2\'d4;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 304,403 | module | module fsmii(clk, resetn, drawNext, drop, draw, drawing, LEDR);
input clk;
input drawNext;
input resetn;
input drop;
output reg draw, drawing;
output [4:0] LEDR;
reg [5:0] current_state, next_state;
localparam S_PLOT = 5'b00001,
S_PLOT_WAIT = 5'b00010,
S_UNPLOT = 5'b00100,
S_UNPLOT_WAIT = 5'b01000,
S_STANDBY = 5'b10000;
always@(*)
begin: state_table
if (drop) begin
case (current_state)
S_STANDBY: next_state = S_UNPLOT;
S_UNPLOT: next_state = S_PLOT;
S_PLOT: next_state = drawNext ? S_PLOT_WAIT : S_PLOT;
S_PLOT_WAIT: next_state = drawNext ? S_PLOT_WAIT : S_UNPLOT;
default: next_state = S_STANDBY;
endcase
end
else begin
case (current_state)
S_STANDBY: next_state = S_STANDBY;
S_PLOT: next_state = drawNext ? S_PLOT_WAIT : S_PLOT;
S_PLOT_WAIT: next_state = drawNext ? S_PLOT_WAIT : S_UNPLOT;
S_UNPLOT: next_state = S_STANDBY;
default: next_state = S_STANDBY;
endcase
end
end
always@(*)
begin: enable_signals
draw = 1'b0;
drawing = 1'b0;
case (current_state)
S_PLOT_WAIT: begin
draw = 1'b1;
drawing = 1'b1;
end
S_UNPLOT: begin
draw = 1'b0;
drawing = 1'b1;
end
endcase
end
always@(posedge clk)
begin: state_FFs
if(!resetn)
current_state <= S_STANDBY;
else
current_state <= next_state;
end
assign LEDR = current_state;
endmodule | module fsmii(clk, resetn, drawNext, drop, draw, drawing, LEDR); |
input clk;
input drawNext;
input resetn;
input drop;
output reg draw, drawing;
output [4:0] LEDR;
reg [5:0] current_state, next_state;
localparam S_PLOT = 5'b00001,
S_PLOT_WAIT = 5'b00010,
S_UNPLOT = 5'b00100,
S_UNPLOT_WAIT = 5'b01000,
S_STANDBY = 5'b10000;
always@(*)
begin: state_table
if (drop) begin
case (current_state)
S_STANDBY: next_state = S_UNPLOT;
S_UNPLOT: next_state = S_PLOT;
S_PLOT: next_state = drawNext ? S_PLOT_WAIT : S_PLOT;
S_PLOT_WAIT: next_state = drawNext ? S_PLOT_WAIT : S_UNPLOT;
default: next_state = S_STANDBY;
endcase
end
else begin
case (current_state)
S_STANDBY: next_state = S_STANDBY;
S_PLOT: next_state = drawNext ? S_PLOT_WAIT : S_PLOT;
S_PLOT_WAIT: next_state = drawNext ? S_PLOT_WAIT : S_UNPLOT;
S_UNPLOT: next_state = S_STANDBY;
default: next_state = S_STANDBY;
endcase
end
end
always@(*)
begin: enable_signals
draw = 1'b0;
drawing = 1'b0;
case (current_state)
S_PLOT_WAIT: begin
draw = 1'b1;
drawing = 1'b1;
end
S_UNPLOT: begin
draw = 1'b0;
drawing = 1'b1;
end
endcase
end
always@(posedge clk)
begin: state_FFs
if(!resetn)
current_state <= S_STANDBY;
else
current_state <= next_state;
end
assign LEDR = current_state;
endmodule | 0 |
139,163 | data/full_repos/permissive/86873408/final.v | 86,873,408 | final.v | v | 681 | 166 | [] | [] | [] | null | line:92: before: "." | null | 1: b'%Error: data/full_repos/permissive/86873408/final.v:6: syntax error, unexpected final, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule final\n ^~~~~\n%Error: data/full_repos/permissive/86873408/final.v:64: syntax error, unexpected assign\n assign colour_in = 3\'b111; \n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:70: syntax error, unexpected assign\n assign leftIn = ~KEY[3];\n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:488: syntax error, unexpected \'(\', expecting IDENTIFIER\n hex_decoder(score [3:0], HEXOutOnes);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/86873408/final.v:511: Value too large for 2 bit number: 4\n S_PLOT = 2\'d4;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 304,403 | module | module datapath(clk, reset, drawCoin, drawing, ld_val, X, Y, value_in, draw, LInput, RInput, plot, colour, x_out, y_out, write, coinX);
input clk;
input reset;
input drawCoin;
input drawing;
input ld_val;
input plot;
input [6:0] Y;
input [7:0] X;
input [7:0] value_in;
input draw;
input LInput, RInput;
reg [7:0] x;
wire [3:0] counter_wire;
output reg [2:0] colour;
output reg [6:0] y_out;
output reg [7:0] x_out;
output reg write;
output reg [7:0] coinX;
reg [7:0] userX;
reg counter = 2'b00;
initial begin
coinX = 8'd27;
colour <= 3'b111;
x_out = 8'd80;
repeat(4) begin
x_out = value_in + counter;
counter = counter + 1;
end
end
always@(posedge clk)
begin
write = 1'b0;
colour = 3'b000;
if (drawing) begin
if (!reset) begin
y_out = Y - 1;
colour = 3'b000;
end
else if (drawCoin)
begin
y_out = Y;
colour = 3'b111;
end
else
begin
if ((Y == 8'd120) && ((value_in == coinX) || (value_in + 1 == coinX) || (value_in + 2 == coinX) || (value_in + 3 == coinX))) begin
y_out = 9'd200;
end
else
y_out = Y - 1;
colour = 3'b000;
end
if (ld_val) begin
coinX = X;
end
x_out <= coinX;
write = 1'b1;
end
else begin
y_out = 8'd119;
if (!draw)
begin
if (RInput && LInput)
userX = 8'd255;
else if (RInput)
userX = value_in - 3'd1;
else if (LInput)
userX = value_in + 3'd4;
colour <= 3'b000;
end
else if (draw)
begin
if (RInput && LInput)
userX = 8'd255;
else if (RInput)
userX = value_in + 3'd3;
else if (LInput)
userX = value_in;
colour <= 3'b111;
end
x_out <= userX;
write = 1'b1;
end
end
endmodule | module datapath(clk, reset, drawCoin, drawing, ld_val, X, Y, value_in, draw, LInput, RInput, plot, colour, x_out, y_out, write, coinX); |
input clk;
input reset;
input drawCoin;
input drawing;
input ld_val;
input plot;
input [6:0] Y;
input [7:0] X;
input [7:0] value_in;
input draw;
input LInput, RInput;
reg [7:0] x;
wire [3:0] counter_wire;
output reg [2:0] colour;
output reg [6:0] y_out;
output reg [7:0] x_out;
output reg write;
output reg [7:0] coinX;
reg [7:0] userX;
reg counter = 2'b00;
initial begin
coinX = 8'd27;
colour <= 3'b111;
x_out = 8'd80;
repeat(4) begin
x_out = value_in + counter;
counter = counter + 1;
end
end
always@(posedge clk)
begin
write = 1'b0;
colour = 3'b000;
if (drawing) begin
if (!reset) begin
y_out = Y - 1;
colour = 3'b000;
end
else if (drawCoin)
begin
y_out = Y;
colour = 3'b111;
end
else
begin
if ((Y == 8'd120) && ((value_in == coinX) || (value_in + 1 == coinX) || (value_in + 2 == coinX) || (value_in + 3 == coinX))) begin
y_out = 9'd200;
end
else
y_out = Y - 1;
colour = 3'b000;
end
if (ld_val) begin
coinX = X;
end
x_out <= coinX;
write = 1'b1;
end
else begin
y_out = 8'd119;
if (!draw)
begin
if (RInput && LInput)
userX = 8'd255;
else if (RInput)
userX = value_in - 3'd1;
else if (LInput)
userX = value_in + 3'd4;
colour <= 3'b000;
end
else if (draw)
begin
if (RInput && LInput)
userX = 8'd255;
else if (RInput)
userX = value_in + 3'd3;
else if (LInput)
userX = value_in;
colour <= 3'b111;
end
x_out <= userX;
write = 1'b1;
end
end
endmodule | 0 |
139,164 | data/full_repos/permissive/86873408/final.v | 86,873,408 | final.v | v | 681 | 166 | [] | [] | [] | null | line:92: before: "." | null | 1: b'%Error: data/full_repos/permissive/86873408/final.v:6: syntax error, unexpected final, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule final\n ^~~~~\n%Error: data/full_repos/permissive/86873408/final.v:64: syntax error, unexpected assign\n assign colour_in = 3\'b111; \n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:70: syntax error, unexpected assign\n assign leftIn = ~KEY[3];\n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:488: syntax error, unexpected \'(\', expecting IDENTIFIER\n hex_decoder(score [3:0], HEXOutOnes);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/86873408/final.v:511: Value too large for 2 bit number: 4\n S_PLOT = 2\'d4;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 304,403 | module | module iterateY(clk, startDrop, outY, change, done);
input clk;
input startDrop;
output reg [6:0] outY;
output change;
output reg done;
wire [6:0] counterY;
always@(*)
begin
if (outY >= 8'd121 | startDrop == 1'b0) begin
outY <= 0;
done <= 1'b1;
end
else begin
outY <= counterY;
done <= 1'b0;
end
end
dropCounter Dcounter(clk, startDrop, counterY, change);
endmodule | module iterateY(clk, startDrop, outY, change, done); |
input clk;
input startDrop;
output reg [6:0] outY;
output change;
output reg done;
wire [6:0] counterY;
always@(*)
begin
if (outY >= 8'd121 | startDrop == 1'b0) begin
outY <= 0;
done <= 1'b1;
end
else begin
outY <= counterY;
done <= 1'b0;
end
end
dropCounter Dcounter(clk, startDrop, counterY, change);
endmodule | 0 |
139,165 | data/full_repos/permissive/86873408/final.v | 86,873,408 | final.v | v | 681 | 166 | [] | [] | [] | null | line:92: before: "." | null | 1: b'%Error: data/full_repos/permissive/86873408/final.v:6: syntax error, unexpected final, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule final\n ^~~~~\n%Error: data/full_repos/permissive/86873408/final.v:64: syntax error, unexpected assign\n assign colour_in = 3\'b111; \n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:70: syntax error, unexpected assign\n assign leftIn = ~KEY[3];\n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:488: syntax error, unexpected \'(\', expecting IDENTIFIER\n hex_decoder(score [3:0], HEXOutOnes);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/86873408/final.v:511: Value too large for 2 bit number: 4\n S_PLOT = 2\'d4;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 304,403 | module | module dropCounter(clk, resetn, out, change);
input clk;
input resetn;
output reg [6:0]out;
output reg change;
reg [28:0]count;
wire [28:0] interval;
reg enable;
assign interval = 27'd4500000 - 1'd1;
always@(posedge clk)
begin
if (!resetn) begin
enable = 1'b0;
count <= interval;
change <= 1'b0;
out <= 0;
end
else if (enable == 1'b1) begin
enable = 1'b0;
count <= interval;
out <= out + 1;
end
else if (count == 1'b0) begin
enable = 1'b1;
change <= 1'b1;
end
else begin
count <= count - 1'b1;
change <= 1'b0;
end
end
endmodule | module dropCounter(clk, resetn, out, change); |
input clk;
input resetn;
output reg [6:0]out;
output reg change;
reg [28:0]count;
wire [28:0] interval;
reg enable;
assign interval = 27'd4500000 - 1'd1;
always@(posedge clk)
begin
if (!resetn) begin
enable = 1'b0;
count <= interval;
change <= 1'b0;
out <= 0;
end
else if (enable == 1'b1) begin
enable = 1'b0;
count <= interval;
out <= out + 1;
end
else if (count == 1'b0) begin
enable = 1'b1;
change <= 1'b1;
end
else begin
count <= count - 1'b1;
change <= 1'b0;
end
end
endmodule | 0 |
139,166 | data/full_repos/permissive/86873408/final.v | 86,873,408 | final.v | v | 681 | 166 | [] | [] | [] | null | line:92: before: "." | null | 1: b'%Error: data/full_repos/permissive/86873408/final.v:6: syntax error, unexpected final, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule final\n ^~~~~\n%Error: data/full_repos/permissive/86873408/final.v:64: syntax error, unexpected assign\n assign colour_in = 3\'b111; \n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:70: syntax error, unexpected assign\n assign leftIn = ~KEY[3];\n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:488: syntax error, unexpected \'(\', expecting IDENTIFIER\n hex_decoder(score [3:0], HEXOutOnes);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/86873408/final.v:511: Value too large for 2 bit number: 4\n S_PLOT = 2\'d4;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 304,403 | module | module randomizer(clk, user_x, signal, out);
input clk;
input [7:0] user_x;
output reg signal;
output reg [7:0] out;
wire [8:0] count;
reg [8:0] out9;
wire [8:0] revCount = {count[0], count[1], count[2], count[3], count[4], count[5], count[6], count[7], count[8]};
wire [7:0] revUser = {user_x[0], user_x[1], user_x[2], user_x[3], user_x[4], user_x[5], user_x[6], user_x[7]};
always@(posedge clk)
begin
out9 <= revUser^revCount;
if (out9 < 8'd160) begin
signal = 1'b1;
out <= out9 [7:0];
end
else
signal = 1'b0;
end
rawCounter Rcounter(clk, count);
endmodule | module randomizer(clk, user_x, signal, out); |
input clk;
input [7:0] user_x;
output reg signal;
output reg [7:0] out;
wire [8:0] count;
reg [8:0] out9;
wire [8:0] revCount = {count[0], count[1], count[2], count[3], count[4], count[5], count[6], count[7], count[8]};
wire [7:0] revUser = {user_x[0], user_x[1], user_x[2], user_x[3], user_x[4], user_x[5], user_x[6], user_x[7]};
always@(posedge clk)
begin
out9 <= revUser^revCount;
if (out9 < 8'd160) begin
signal = 1'b1;
out <= out9 [7:0];
end
else
signal = 1'b0;
end
rawCounter Rcounter(clk, count);
endmodule | 0 |
139,167 | data/full_repos/permissive/86873408/final.v | 86,873,408 | final.v | v | 681 | 166 | [] | [] | [] | null | line:92: before: "." | null | 1: b'%Error: data/full_repos/permissive/86873408/final.v:6: syntax error, unexpected final, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule final\n ^~~~~\n%Error: data/full_repos/permissive/86873408/final.v:64: syntax error, unexpected assign\n assign colour_in = 3\'b111; \n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:70: syntax error, unexpected assign\n assign leftIn = ~KEY[3];\n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:488: syntax error, unexpected \'(\', expecting IDENTIFIER\n hex_decoder(score [3:0], HEXOutOnes);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/86873408/final.v:511: Value too large for 2 bit number: 4\n S_PLOT = 2\'d4;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 304,403 | module | module rawCounter(
input clk,
output reg [8:0] out
);
initial
out <= 9'd27;
always@(posedge clk)
out <= out + 1'b1;
endmodule | module rawCounter(
input clk,
output reg [8:0] out
); |
initial
out <= 9'd27;
always@(posedge clk)
out <= out + 1'b1;
endmodule | 0 |
139,168 | data/full_repos/permissive/86873408/final.v | 86,873,408 | final.v | v | 681 | 166 | [] | [] | [] | null | line:92: before: "." | null | 1: b'%Error: data/full_repos/permissive/86873408/final.v:6: syntax error, unexpected final, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule final\n ^~~~~\n%Error: data/full_repos/permissive/86873408/final.v:64: syntax error, unexpected assign\n assign colour_in = 3\'b111; \n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:70: syntax error, unexpected assign\n assign leftIn = ~KEY[3];\n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:488: syntax error, unexpected \'(\', expecting IDENTIFIER\n hex_decoder(score [3:0], HEXOutOnes);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/86873408/final.v:511: Value too large for 2 bit number: 4\n S_PLOT = 2\'d4;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 304,403 | module | module scoreKeeper(reset, check, userX, X, Y, HEXOutOnes, HEXOutTens);
input check;
input reset;
input [7:0] userX;
input [7:0] X;
input [6:0] Y;
output [6:0] HEXOutOnes, HEXOutTens;
reg [7:0] count_score;
reg [7:0] score;
always@(negedge check) begin
if (Y == 8'd119)
if ((userX == X) || (userX + 1 == X) || (userX + 2 == X) || (userX + 3 == X))
score = score + 1;
end
hex_decoder(score [3:0], HEXOutOnes);
hex_decoder(score [7:4], HEXOutTens);
endmodule | module scoreKeeper(reset, check, userX, X, Y, HEXOutOnes, HEXOutTens); |
input check;
input reset;
input [7:0] userX;
input [7:0] X;
input [6:0] Y;
output [6:0] HEXOutOnes, HEXOutTens;
reg [7:0] count_score;
reg [7:0] score;
always@(negedge check) begin
if (Y == 8'd119)
if ((userX == X) || (userX + 1 == X) || (userX + 2 == X) || (userX + 3 == X))
score = score + 1;
end
hex_decoder(score [3:0], HEXOutOnes);
hex_decoder(score [7:4], HEXOutTens);
endmodule | 0 |
139,169 | data/full_repos/permissive/86873408/final.v | 86,873,408 | final.v | v | 681 | 166 | [] | [] | [] | null | line:92: before: "." | null | 1: b'%Error: data/full_repos/permissive/86873408/final.v:6: syntax error, unexpected final, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule final\n ^~~~~\n%Error: data/full_repos/permissive/86873408/final.v:64: syntax error, unexpected assign\n assign colour_in = 3\'b111; \n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:70: syntax error, unexpected assign\n assign leftIn = ~KEY[3];\n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:488: syntax error, unexpected \'(\', expecting IDENTIFIER\n hex_decoder(score [3:0], HEXOutOnes);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/86873408/final.v:511: Value too large for 2 bit number: 4\n S_PLOT = 2\'d4;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 304,403 | module | module control(clk, resetn, L, R, drawing, ld_x, writeEn, LEDR);
input clk;
input resetn;
input L;
input R;
input drawing;
output LEDR;
assign LEDR = current_state;
output reg ld_x, writeEn;
reg [1:0] current_state, next_state;
localparam S_HOLD = 2'd1,
S_UNPLOT = 2'd2,
S_PLOT = 2'd4;
always@(*)
begin: state_table
case (current_state)
S_HOLD: begin
if ((L == 1'b1 || R == 1'b1))
next_state <= S_UNPLOT;
else
next_state <= S_HOLD;
end
S_UNPLOT: next_state <= S_PLOT;
S_PLOT: next_state <= S_HOLD;
default: next_state = S_HOLD;
endcase
end
always@(*)
begin: enable_signals
ld_x = 1'b0;
writeEn = 1'b0;
case (current_state)
S_UNPLOT: begin
writeEn = 1'b1;
end
S_PLOT: begin
ld_x = 1'b1;
writeEn = 1'b1;
end
S_HOLD: begin
end
endcase
end
always@(posedge clk)
begin: state_FFs
if(!drawing)
current_state <= next_state;
end
endmodule | module control(clk, resetn, L, R, drawing, ld_x, writeEn, LEDR); |
input clk;
input resetn;
input L;
input R;
input drawing;
output LEDR;
assign LEDR = current_state;
output reg ld_x, writeEn;
reg [1:0] current_state, next_state;
localparam S_HOLD = 2'd1,
S_UNPLOT = 2'd2,
S_PLOT = 2'd4;
always@(*)
begin: state_table
case (current_state)
S_HOLD: begin
if ((L == 1'b1 || R == 1'b1))
next_state <= S_UNPLOT;
else
next_state <= S_HOLD;
end
S_UNPLOT: next_state <= S_PLOT;
S_PLOT: next_state <= S_HOLD;
default: next_state = S_HOLD;
endcase
end
always@(*)
begin: enable_signals
ld_x = 1'b0;
writeEn = 1'b0;
case (current_state)
S_UNPLOT: begin
writeEn = 1'b1;
end
S_PLOT: begin
ld_x = 1'b1;
writeEn = 1'b1;
end
S_HOLD: begin
end
endcase
end
always@(posedge clk)
begin: state_FFs
if(!drawing)
current_state <= next_state;
end
endmodule | 0 |
139,170 | data/full_repos/permissive/86873408/final.v | 86,873,408 | final.v | v | 681 | 166 | [] | [] | [] | null | line:92: before: "." | null | 1: b'%Error: data/full_repos/permissive/86873408/final.v:6: syntax error, unexpected final, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule final\n ^~~~~\n%Error: data/full_repos/permissive/86873408/final.v:64: syntax error, unexpected assign\n assign colour_in = 3\'b111; \n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:70: syntax error, unexpected assign\n assign leftIn = ~KEY[3];\n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:488: syntax error, unexpected \'(\', expecting IDENTIFIER\n hex_decoder(score [3:0], HEXOutOnes);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/86873408/final.v:511: Value too large for 2 bit number: 4\n S_PLOT = 2\'d4;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 304,403 | module | module counter(
input enable,
input clk,
input resetn,
output reg [3:0] out,
input init
);
always@(posedge clk)
begin
if(resetn == 1'b0)
out <= 0;
else if (enable == 1'b1 || init == 1'b1)
out <= out + 1'b1;
end
endmodule | module counter(
input enable,
input clk,
input resetn,
output reg [3:0] out,
input init
); |
always@(posedge clk)
begin
if(resetn == 1'b0)
out <= 0;
else if (enable == 1'b1 || init == 1'b1)
out <= out + 1'b1;
end
endmodule | 0 |
139,171 | data/full_repos/permissive/86873408/final.v | 86,873,408 | final.v | v | 681 | 166 | [] | [] | [] | null | line:92: before: "." | null | 1: b'%Error: data/full_repos/permissive/86873408/final.v:6: syntax error, unexpected final, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule final\n ^~~~~\n%Error: data/full_repos/permissive/86873408/final.v:64: syntax error, unexpected assign\n assign colour_in = 3\'b111; \n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:70: syntax error, unexpected assign\n assign leftIn = ~KEY[3];\n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:488: syntax error, unexpected \'(\', expecting IDENTIFIER\n hex_decoder(score [3:0], HEXOutOnes);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/86873408/final.v:511: Value too large for 2 bit number: 4\n S_PLOT = 2\'d4;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 304,403 | module | module RateDivider(clk, switch, out);
input clk;
input [1:0] switch;
output reg out;
reg [27:0] counter0;
reg [27:0] counter50mil;
reg [27:0] counter100mil;
reg [27:0] counter200mil;
wire hertzalot, hertz1, hertz05, hertz025;
assign hertzalot = (counter0 == 28'h0000000) ? 1 : 0;
assign hertz1 = (counter50mil == 28'h0000000) ? 1 : 0;
assign hertz05 = (counter100mil == 28'h0000000) ? 1 : 0;
assign hertz025 = (counter200mil == 28'h0000000) ? 1 : 0;
always @(posedge clk)
begin
if(counter0 == 28'h0000001)
begin
counter0 <= 0;
end
else
begin
counter0 <= counter0 + 1'b1;
end
if(counter50mil == 28'h4C4B40)
begin
counter50mil <= 0;
end
else
begin
counter50mil <= counter50mil + 1'b1;
end
if(counter100mil == 28'h5F5E100)
begin
counter100mil <= 0;
end
else
begin
counter100mil <= counter100mil + 1'b1;
end
if(counter200mil == 28'hBEBC200)
begin
counter200mil <= 0;
end
else
begin
counter200mil <= counter200mil + 1'b1;
end
case(switch)
2'b00: out <= hertzalot;
2'b01: out <= hertz1;
2'b10: out <= hertz05;
2'b11: out <= hertz025;
default: out <= clk;
endcase
end
endmodule | module RateDivider(clk, switch, out); |
input clk;
input [1:0] switch;
output reg out;
reg [27:0] counter0;
reg [27:0] counter50mil;
reg [27:0] counter100mil;
reg [27:0] counter200mil;
wire hertzalot, hertz1, hertz05, hertz025;
assign hertzalot = (counter0 == 28'h0000000) ? 1 : 0;
assign hertz1 = (counter50mil == 28'h0000000) ? 1 : 0;
assign hertz05 = (counter100mil == 28'h0000000) ? 1 : 0;
assign hertz025 = (counter200mil == 28'h0000000) ? 1 : 0;
always @(posedge clk)
begin
if(counter0 == 28'h0000001)
begin
counter0 <= 0;
end
else
begin
counter0 <= counter0 + 1'b1;
end
if(counter50mil == 28'h4C4B40)
begin
counter50mil <= 0;
end
else
begin
counter50mil <= counter50mil + 1'b1;
end
if(counter100mil == 28'h5F5E100)
begin
counter100mil <= 0;
end
else
begin
counter100mil <= counter100mil + 1'b1;
end
if(counter200mil == 28'hBEBC200)
begin
counter200mil <= 0;
end
else
begin
counter200mil <= counter200mil + 1'b1;
end
case(switch)
2'b00: out <= hertzalot;
2'b01: out <= hertz1;
2'b10: out <= hertz05;
2'b11: out <= hertz025;
default: out <= clk;
endcase
end
endmodule | 0 |
139,172 | data/full_repos/permissive/86873408/final.v | 86,873,408 | final.v | v | 681 | 166 | [] | [] | [] | null | line:92: before: "." | null | 1: b'%Error: data/full_repos/permissive/86873408/final.v:6: syntax error, unexpected final, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule final\n ^~~~~\n%Error: data/full_repos/permissive/86873408/final.v:64: syntax error, unexpected assign\n assign colour_in = 3\'b111; \n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:70: syntax error, unexpected assign\n assign leftIn = ~KEY[3];\n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:488: syntax error, unexpected \'(\', expecting IDENTIFIER\n hex_decoder(score [3:0], HEXOutOnes);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/86873408/final.v:511: Value too large for 2 bit number: 4\n S_PLOT = 2\'d4;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 304,403 | module | module player(left, right, playerX, clock);
input left, right, clock;
output reg [7:0] playerX;
initial
playerX <= 8'd80;
always @(posedge clock)
begin
if (left == 1'b1 && playerX > 8'd0)
playerX = playerX - 1;
if (right == 1'b1 && playerX < 8'd156)
playerX = playerX + 1;
end
endmodule | module player(left, right, playerX, clock); |
input left, right, clock;
output reg [7:0] playerX;
initial
playerX <= 8'd80;
always @(posedge clock)
begin
if (left == 1'b1 && playerX > 8'd0)
playerX = playerX - 1;
if (right == 1'b1 && playerX < 8'd156)
playerX = playerX + 1;
end
endmodule | 0 |
139,173 | data/full_repos/permissive/86873408/final.v | 86,873,408 | final.v | v | 681 | 166 | [] | [] | [] | null | line:92: before: "." | null | 1: b'%Error: data/full_repos/permissive/86873408/final.v:6: syntax error, unexpected final, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule final\n ^~~~~\n%Error: data/full_repos/permissive/86873408/final.v:64: syntax error, unexpected assign\n assign colour_in = 3\'b111; \n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:70: syntax error, unexpected assign\n assign leftIn = ~KEY[3];\n ^~~~~~\n%Error: data/full_repos/permissive/86873408/final.v:488: syntax error, unexpected \'(\', expecting IDENTIFIER\n hex_decoder(score [3:0], HEXOutOnes);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/86873408/final.v:511: Value too large for 2 bit number: 4\n S_PLOT = 2\'d4;\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n' | 304,403 | module | module hex_decoder(hex_digit, segments);
input [3:0] hex_digit;
output reg [6:0] segments;
always @(*)
case (hex_digit)
4'h0: segments = 7'b100_0000;
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b011_0000;
4'h4: segments = 7'b001_1001;
4'h5: segments = 7'b001_0010;
4'h6: segments = 7'b000_0010;
4'h7: segments = 7'b111_1000;
4'h8: segments = 7'b000_0000;
4'h9: segments = 7'b001_0000;
4'hA: segments = 7'b000_1000;
4'hB: segments = 7'b000_0011;
4'hC: segments = 7'b100_0110;
4'hD: segments = 7'b010_0001;
4'hE: segments = 7'b000_0110;
4'hF: segments = 7'b000_1110;
default: segments = 7'h7f;
endcase
endmodule | module hex_decoder(hex_digit, segments); |
input [3:0] hex_digit;
output reg [6:0] segments;
always @(*)
case (hex_digit)
4'h0: segments = 7'b100_0000;
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b011_0000;
4'h4: segments = 7'b001_1001;
4'h5: segments = 7'b001_0010;
4'h6: segments = 7'b000_0010;
4'h7: segments = 7'b111_1000;
4'h8: segments = 7'b000_0000;
4'h9: segments = 7'b001_0000;
4'hA: segments = 7'b000_1000;
4'hB: segments = 7'b000_0011;
4'hC: segments = 7'b100_0110;
4'hD: segments = 7'b010_0001;
4'hE: segments = 7'b000_0110;
4'hF: segments = 7'b000_1110;
default: segments = 7'h7f;
endcase
endmodule | 0 |
139,180 | data/full_repos/permissive/86894739/hw2/SRC/Mux4to1_18bit.v | 86,894,739 | Mux4to1_18bit.v | v | 34 | 29 | [] | [] | [] | [(3, 33)] | null | data/verilator_xmls/5809188a-4fee-450f-b2e4-fdb52397d78f.xml | null | 304,412 | module | module Mux4to1_18bit ( I0,
I1,
I2,
I3,
S,
out);
parameter bit_size = 18;
input [bit_size-1:0] I0;
input [bit_size-1:0] I1;
input [bit_size-1:0] I2;
input [bit_size-1:0] I3;
input [1:0]S;
output [bit_size-1:0] out;
reg [bit_size-1:0] out;
always@(*)
begin
out = 0;
case(S)
0: out = I0;
1: out = I1;
2: out = I2;
3: out = I3;
endcase
end
endmodule | module Mux4to1_18bit ( I0,
I1,
I2,
I3,
S,
out); |
parameter bit_size = 18;
input [bit_size-1:0] I0;
input [bit_size-1:0] I1;
input [bit_size-1:0] I2;
input [bit_size-1:0] I3;
input [1:0]S;
output [bit_size-1:0] out;
reg [bit_size-1:0] out;
always@(*)
begin
out = 0;
case(S)
0: out = I0;
1: out = I1;
2: out = I2;
3: out = I3;
endcase
end
endmodule | 2 |
139,181 | data/full_repos/permissive/86894739/hw2/SRC/Regfile.v | 86,894,739 | Regfile.v | v | 58 | 77 | [] | [] | [] | null | None: at end of input | data/verilator_xmls/c48a3485-a6b3-45be-b04b-e43ebb58080b.xml | null | 304,414 | module | module Regfile ( clk,
rst,
Read_addr_1,
Read_addr_2,
Read_data_1,
Read_data_2,
RegWrite,
Write_addr,
Write_data);
parameter bit_size = 32;
input clk, rst;
input [4:0] Read_addr_1;
input [4:0] Read_addr_2;
output [bit_size-1:0] Read_data_1;
output [bit_size-1:0] Read_data_2;
input RegWrite;
input [4:0] Write_addr;
input [bit_size-1:0] Write_data;
reg [bit_size-1:0] register [0:31];
assign Read_data_1 = register[Read_addr_1];
assign Read_data_2 = register[Read_addr_2];
integer i;
always@(posedge clk, posedge rst)
begin
if(rst)
begin
for(i = 0; i < 32; i = i + 1)
begin
register[i] <= 32'b0;
end
end
else
begin
if(RegWrite == 1 && Write_addr != 0)
begin
register[Write_addr] <= Write_data;
end
end
end
endmodule | module Regfile ( clk,
rst,
Read_addr_1,
Read_addr_2,
Read_data_1,
Read_data_2,
RegWrite,
Write_addr,
Write_data); |
parameter bit_size = 32;
input clk, rst;
input [4:0] Read_addr_1;
input [4:0] Read_addr_2;
output [bit_size-1:0] Read_data_1;
output [bit_size-1:0] Read_data_2;
input RegWrite;
input [4:0] Write_addr;
input [bit_size-1:0] Write_data;
reg [bit_size-1:0] register [0:31];
assign Read_data_1 = register[Read_addr_1];
assign Read_data_2 = register[Read_addr_2];
integer i;
always@(posedge clk, posedge rst)
begin
if(rst)
begin
for(i = 0; i < 32; i = i + 1)
begin
register[i] <= 32'b0;
end
end
else
begin
if(RegWrite == 1 && Write_addr != 0)
begin
register[Write_addr] <= Write_data;
end
end
end
endmodule | 2 |
139,183 | data/full_repos/permissive/86894739/hw2/SRC/testfixture1.v | 86,894,739 | testfixture1.v | v | 173 | 128 | [] | [] | [] | null | line:65: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86894739/hw2/SRC/testfixture1.v:58: Unsupported: Ignoring delay on this delayed statement.\nalways #(10/2) clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86894739/hw2/SRC/testfixture1.v:64: Unsupported: Ignoring delay on this delayed statement.\n #(10 * 1000)\n ^\n%Error: data/full_repos/permissive/86894739/hw2/SRC/testfixture1.v:77: Unsupported: wait statements\n wait(IM_Address==31);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/86894739/hw2/SRC/testfixture1.v:78: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Error: data/full_repos/permissive/86894739/hw2/SRC/testfixture1.v:99: Unsupported: wait statements\n wait(IM_Address==42);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/86894739/hw2/SRC/testfixture1.v:100: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Error: data/full_repos/permissive/86894739/hw2/SRC/testfixture1.v:121: Unsupported: wait statements\n wait(IM_Address==44);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/86894739/hw2/SRC/testfixture1.v:122: Unsupported: Ignoring delay on this delayed statement.\n #(10 * 2) if(IM_Address < 51) begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86894739/hw2/SRC/testfixture1.v:125: Unsupported: Ignoring delay on this delayed statement.\n #(10 * 4) if(IM_Address > 54) begin\n ^\n%Error: data/full_repos/permissive/86894739/hw2/SRC/testfixture1.v:134: Unsupported: wait statements\n wait(IM_Address==60);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/86894739/hw2/SRC/testfixture1.v:161: Unsupported: Ignoring delay on this delayed statement.\n #6 rst = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86894739/hw2/SRC/testfixture1.v:162: Unsupported: Ignoring delay on this delayed statement.\n #(10 ) rst = 0;\n ^\n%Error: Exiting due to 4 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,416 | module | module testfixture1;
parameter bit_size = 32;
parameter mem_size = 16;
reg clk, rst;
reg [31:0] golden_DM [0:99];
reg err_R, err_I, err_J;
wire [mem_size-1:0] IM_Address;
wire [bit_size-1:0] Instruction;
wire [mem_size-1:0] DM_Address;
wire DM_enable;
wire [bit_size-1:0] DM_Write_Data;
wire [bit_size-1:0] DM_Read_Data;
IM IM1 (
.clk(clk),
.rst(rst),
.IM_Address(IM_Address),
.Instruction(Instruction)
);
DM DM1 (
.clk(clk),
.rst(rst),
.DM_Address(DM_Address),
.DM_enable(DM_enable),
.DM_Write_Data(DM_Write_Data),
.DM_Read_Data(DM_Read_Data)
);
top top1 (
.clk(clk),
.rst(rst),
.IM_Address(IM_Address),
.Instruction(Instruction),
.DM_Address(DM_Address),
.DM_enable(DM_enable),
.DM_Write_Data(DM_Write_Data),
.DM_Read_Data(DM_Read_Data)
);
always #(`PERIOD/2) clk = ~clk;
integer i;
initial begin
#(`PERIOD * `NUM_CLK)
$display("================================================================================================================");
$display("--------------------------- (/`n`)/ ~# There was something wrong with your code !! ---------------------------");
$display("------------------ The simulation can't finished!!, Please check Branch, Jtype or jr is work or not !!! -------");
$display("================================================================================================================");
$finish;
end
initial begin
$display("[ testfuxture1.v ] Rtype test START !!");
wait(IM_Address==31);
#1
for (i=0;i<10;i=i+1) begin
if(golden_DM[i] != DM1.DM_data[i]) begin
$display("DM_data[%d] = %h ERROR, EXPECT DM_data[%d]= %h ", i, DM1.DM_data[i], i, golden_DM[i]);
err_R = 1;
end
end
if (err_R) begin
$display("============================================================================================");
$display("\n (T_T) The Rtype result of DM_data is FAIL(include addi)!!! there have some errors in all.\n");
$display("============================================================================================");
$finish;
end
else begin
$display("============================================================================");
$display("\n \\(^o^)/ The Rtype result of DM_data is PASS!!!\n");
$display("============================================================================");
end
$display("[ testfuxture1.v ] Itype test START !!");
wait(IM_Address==42);
#1
for (i=10;i<15;i=i+1) begin
if(golden_DM[i] != DM1.DM_data[i]) begin
$display("DM_data[%d] = %h ERROR, EXPECT DM_data[%d]= %h ", i, DM1.DM_data[i], i, golden_DM[i]);
err_I = 1;
end
end
if (err_I) begin
$display("============================================================================================");
$display("\n (T_T) The Itype result of DM_data is FAIL!!! there have some errors in all.\n");
$display("============================================================================================");
$finish;
end
else begin
$display("============================================================================");
$display("\n \\(^o^)/ The Itype result of DM_data is PASS!!!\n");
$display("============================================================================");
end
$display("[ testfuxture1.v ] Jtype test START !!");
wait(IM_Address==44);
#(`PERIOD * 2) if(IM_Address < 51) begin
err_J = 1;
end
#(`PERIOD * 4) if(IM_Address > 54) begin
err_J = 1;
end
if (err_J) begin
$display("============================================================================================");
$display("\n (T_T) The Jtype or Jr result of DM_data is FAIL!!! there have some errors in all.\n");
$display("============================================================================================");
$finish;
end
wait(IM_Address==60);
$display("============================================================================");
$display("\n \\(^o^)/ The Jtype result of DM_data is PASS!!!\n");
$display("============================================================================");
$display("\n");
$display(" Single Cycle CPU ");
$display(" **************************** ");
$display(" ** ** /|__/|");
$display(" ** Congratulations !! ** / O,O |");
$display(" ** ** /_____ |");
$display(" ** Simulation PASS!! ** /^ ^ ^ \\ |");
$display(" ** ** |^ ^ ^ ^ |w|");
$display(" *************** ************ \\m___m__|_|");
$display(" student ID : F74046284 ");
$display("\n");
$finish;
end
initial begin
clk = 0;
rst = 0;
err_R = 0;
err_I = 0;
err_J = 0;
$readmemh(`TEST_DATA, IM1.IM_data);
$readmemh(`golden_DM_DATA, golden_DM);
#6 rst = 1;
#(`PERIOD ) rst = 0;
end
`ifdef VCD
initial begin
$dumpfile("top.vcd");
$dumpvars;
end
`endif
endmodule | module testfixture1; |
parameter bit_size = 32;
parameter mem_size = 16;
reg clk, rst;
reg [31:0] golden_DM [0:99];
reg err_R, err_I, err_J;
wire [mem_size-1:0] IM_Address;
wire [bit_size-1:0] Instruction;
wire [mem_size-1:0] DM_Address;
wire DM_enable;
wire [bit_size-1:0] DM_Write_Data;
wire [bit_size-1:0] DM_Read_Data;
IM IM1 (
.clk(clk),
.rst(rst),
.IM_Address(IM_Address),
.Instruction(Instruction)
);
DM DM1 (
.clk(clk),
.rst(rst),
.DM_Address(DM_Address),
.DM_enable(DM_enable),
.DM_Write_Data(DM_Write_Data),
.DM_Read_Data(DM_Read_Data)
);
top top1 (
.clk(clk),
.rst(rst),
.IM_Address(IM_Address),
.Instruction(Instruction),
.DM_Address(DM_Address),
.DM_enable(DM_enable),
.DM_Write_Data(DM_Write_Data),
.DM_Read_Data(DM_Read_Data)
);
always #(`PERIOD/2) clk = ~clk;
integer i;
initial begin
#(`PERIOD * `NUM_CLK)
$display("================================================================================================================");
$display("--------------------------- (/`n`)/ ~# There was something wrong with your code !! ---------------------------");
$display("------------------ The simulation can't finished!!, Please check Branch, Jtype or jr is work or not !!! -------");
$display("================================================================================================================");
$finish;
end
initial begin
$display("[ testfuxture1.v ] Rtype test START !!");
wait(IM_Address==31);
#1
for (i=0;i<10;i=i+1) begin
if(golden_DM[i] != DM1.DM_data[i]) begin
$display("DM_data[%d] = %h ERROR, EXPECT DM_data[%d]= %h ", i, DM1.DM_data[i], i, golden_DM[i]);
err_R = 1;
end
end
if (err_R) begin
$display("============================================================================================");
$display("\n (T_T) The Rtype result of DM_data is FAIL(include addi)!!! there have some errors in all.\n");
$display("============================================================================================");
$finish;
end
else begin
$display("============================================================================");
$display("\n \\(^o^)/ The Rtype result of DM_data is PASS!!!\n");
$display("============================================================================");
end
$display("[ testfuxture1.v ] Itype test START !!");
wait(IM_Address==42);
#1
for (i=10;i<15;i=i+1) begin
if(golden_DM[i] != DM1.DM_data[i]) begin
$display("DM_data[%d] = %h ERROR, EXPECT DM_data[%d]= %h ", i, DM1.DM_data[i], i, golden_DM[i]);
err_I = 1;
end
end
if (err_I) begin
$display("============================================================================================");
$display("\n (T_T) The Itype result of DM_data is FAIL!!! there have some errors in all.\n");
$display("============================================================================================");
$finish;
end
else begin
$display("============================================================================");
$display("\n \\(^o^)/ The Itype result of DM_data is PASS!!!\n");
$display("============================================================================");
end
$display("[ testfuxture1.v ] Jtype test START !!");
wait(IM_Address==44);
#(`PERIOD * 2) if(IM_Address < 51) begin
err_J = 1;
end
#(`PERIOD * 4) if(IM_Address > 54) begin
err_J = 1;
end
if (err_J) begin
$display("============================================================================================");
$display("\n (T_T) The Jtype or Jr result of DM_data is FAIL!!! there have some errors in all.\n");
$display("============================================================================================");
$finish;
end
wait(IM_Address==60);
$display("============================================================================");
$display("\n \\(^o^)/ The Jtype result of DM_data is PASS!!!\n");
$display("============================================================================");
$display("\n");
$display(" Single Cycle CPU ");
$display(" **************************** ");
$display(" ** ** /|__/|");
$display(" ** Congratulations !! ** / O,O |");
$display(" ** ** /_____ |");
$display(" ** Simulation PASS!! ** /^ ^ ^ \\ |");
$display(" ** ** |^ ^ ^ ^ |w|");
$display(" *************** ************ \\m___m__|_|");
$display(" student ID : F74046284 ");
$display("\n");
$finish;
end
initial begin
clk = 0;
rst = 0;
err_R = 0;
err_I = 0;
err_J = 0;
$readmemh(`TEST_DATA, IM1.IM_data);
$readmemh(`golden_DM_DATA, golden_DM);
#6 rst = 1;
#(`PERIOD ) rst = 0;
end
`ifdef VCD
initial begin
$dumpfile("top.vcd");
$dumpvars;
end
`endif
endmodule | 2 |
139,184 | data/full_repos/permissive/86894739/hw2/SRC/top.v | 86,894,739 | top.v | v | 275 | 114 | [] | [] | [] | [(3, 274)] | null | null | 1: b"%Error: data/full_repos/permissive/86894739/hw2/SRC/top.v:132: Cannot find file containing module: 'PC'\n PC PC1(\n ^~\n ... Looked in:\n data/full_repos/permissive/86894739/hw2/SRC,data/full_repos/permissive/86894739/PC\n data/full_repos/permissive/86894739/hw2/SRC,data/full_repos/permissive/86894739/PC.v\n data/full_repos/permissive/86894739/hw2/SRC,data/full_repos/permissive/86894739/PC.sv\n PC\n PC.v\n PC.sv\n obj_dir/PC\n obj_dir/PC.v\n obj_dir/PC.sv\n%Error: data/full_repos/permissive/86894739/hw2/SRC/top.v:139: Cannot find file containing module: 'ADD'\n ADD PC_ADD4(\n ^~~\n%Error: data/full_repos/permissive/86894739/hw2/SRC/top.v:145: Cannot find file containing module: 'Controller'\n Controller Controller1(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86894739/hw2/SRC/top.v:161: Cannot find file containing module: 'Mux2to1_5bit'\n Mux2to1_5bit Mux_RegDst(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/86894739/hw2/SRC/top.v:168: Cannot find file containing module: 'Mux2to1_5bit'\n Mux2to1_5bit Mux_Jal1( \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/86894739/hw2/SRC/top.v:175: Cannot find file containing module: 'Regfile'\n Regfile Regfile1(\n ^~~~~~~\n%Error: data/full_repos/permissive/86894739/hw2/SRC/top.v:187: Cannot find file containing module: 'Sign_Extend'\n Sign_Extend Sign_Extend_Imm( \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86894739/hw2/SRC/top.v:192: Cannot find file containing module: 'Mux2to1_32bit'\n Mux2to1_32bit Mux_ALUSrc(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86894739/hw2/SRC/top.v:199: Cannot find file containing module: 'ALU'\n ALU ALU1(\n ^~~\n%Error: data/full_repos/permissive/86894739/hw2/SRC/top.v:208: Cannot find file containing module: 'Sign_Extend'\n Sign_Extend Sign_Extend_sh( \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86894739/hw2/SRC/top.v:213: Cannot find file containing module: 'Mux2to1_32bit'\n Mux2to1_32bit Mux_sh(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86894739/hw2/SRC/top.v:220: Cannot find file containing module: 'Sign_Extend'\n Sign_Extend Sign_Extend_lh( \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86894739/hw2/SRC/top.v:225: Cannot find file containing module: 'Mux2to1_32bit'\n Mux2to1_32bit Mux_lh(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86894739/hw2/SRC/top.v:232: Cannot find file containing module: 'Mux2to1_32bit'\n Mux2to1_32bit Mux_MemToReg(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86894739/hw2/SRC/top.v:239: Cannot find file containing module: 'ADD'\n ADD PC_ADD8(\n ^~~\n%Error: data/full_repos/permissive/86894739/hw2/SRC/top.v:245: Cannot find file containing module: 'Mux2to1_32bit'\n Mux2to1_32bit Mux_Jal2( \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86894739/hw2/SRC/top.v:252: Cannot find file containing module: 'ADD'\n ADD ADD_Branch( \n ^~~\n%Error: data/full_repos/permissive/86894739/hw2/SRC/top.v:258: Cannot find file containing module: 'Jump_Ctrl'\n Jump_Ctrl Jump_Ctrl1(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86894739/hw2/SRC/top.v:266: Cannot find file containing module: 'Mux4to1_18bit'\n Mux4to1_18bit Mux_PC(\n ^~~~~~~~~~~~~\n%Error: Exiting due to 19 error(s)\n" | 304,417 | module | module top ( clk,
rst,
IM_Address,
Instruction,
DM_Address,
DM_enable,
DM_Write_Data,
DM_Read_Data);
parameter data_size = 32;
parameter mem_size = 16;
input clk, rst;
output [mem_size-1:0] IM_Address;
input [data_size-1:0] Instruction;
output [mem_size-1:0] DM_Address;
output DM_enable;
output [data_size-1:0] DM_Write_Data;
input [data_size-1:0] DM_Read_Data;
parameter bit_size = 18;
wire [bit_size-1:0] PCin;
wire [bit_size-1:0] PCout;
wire [5:0] opcode;
wire [5:0] funct;
wire RegDst, ALUSrc, MemWrite, MemRead, MemToReg, Half, Branch, Jump, Jal, Jr;
wire [3:0] ALUOp;
wire [data_size-1:0]Read_data_1;
wire [data_size-1:0]Read_data_2;
wire RegWrite;
wire [4:0] Write_addr;
wire [data_size-1:0] Write_data;
wire [mem_size-1:0] Immediate;
wire [4:0] Rs_Addr;
wire [4:0] Rt_Addr;
wire [4:0] Rd_Addr;
wire [data_size-1:0] src1;
wire [data_size-1:0] src2;
wire [4:0] shamt;
wire [data_size-1:0] ALU_result;
wire Zero;
wire [bit_size-1:0] PCout_Plus4;
wire [bit_size-1:0] PCout_Plus8;
wire [4:0] Mux_RegDst_out;
wire [data_size-1:0] Mux_MemToReg_out;
wire [data_size-1:0] Mux_lh_out;
wire [data_size-1:0] Immediate_After_Sign_Extend;
wire [data_size-1:0] Read_data_2_half_After_Sign_Extend;
wire [data_size-1:0] DM_Read_Data_half_After_Sign_Extend;
wire [1:0] JumpOP;
wire [bit_size-1:0] Jump_Addr;
wire [bit_size-1:0] Branch_Addr;
assign IM_Address = PCout [bit_size-1:2];
assign opcode = Instruction [31:26];
assign funct = Instruction [5:0];
assign DM_enable = MemWrite;
assign Immediate = Instruction[15:0];
assign Rs_Addr = Instruction[25:21];
assign Rt_Addr = Instruction[20:16];
assign Rd_Addr = Instruction[15:11];
assign shamt = Instruction[10:6];
assign src1 = Read_data_1;
assign DM_Address = ALU_result[17:2];
assign Jump_Addr = ({Immediate, 2'b0});
PC PC1(
.clk(clk),
.rst(rst),
.PCin(PCin),
.PCout(PCout)
);
ADD PC_ADD4(
.src1(PCout),
.src2(18'd4),
.out(PCout_Plus4)
);
Controller Controller1(
.opcode(opcode),
.funct(funct),
.RegDst(RegDst),
.RegWrite(RegWrite),
.ALUSrc(ALUSrc),
.ALUOp(ALUOp),
.MemWrite(MemWrite),
.MemToReg(MemToReg),
.Half(Half),
.Branch(Branch),
.Jump(Jump),
.Jal(Jal),
.Jr(Jr)
);
Mux2to1_5bit Mux_RegDst(
.I0(Rt_Addr),
.I1(Rd_Addr),
.S(RegDst),
.out(Mux_RegDst_out)
);
Mux2to1_5bit Mux_Jal1(
.I0(Mux_RegDst_out),
.I1(5'd31),
.S(Jal),
.out(Write_addr)
);
Regfile Regfile1(
.clk(clk),
.rst(rst),
.Read_addr_1(Rs_Addr),
.Read_addr_2(Rt_Addr),
.Read_data_1(Read_data_1),
.Read_data_2(Read_data_2),
.RegWrite(RegWrite),
.Write_addr(Write_addr),
.Write_data(Write_data)
);
Sign_Extend Sign_Extend_Imm(
.sign_in(Immediate),
.sign_out(Immediate_After_Sign_Extend)
);
Mux2to1_32bit Mux_ALUSrc(
.I0(Immediate_After_Sign_Extend),
.I1(Read_data_2),
.S(ALUSrc),
.out(src2)
);
ALU ALU1(
.ALUOp(ALUOp),
.src1(src1),
.src2(src2),
.shamt(shamt),
.ALU_result(ALU_result),
.Zero(Zero)
);
Sign_Extend Sign_Extend_sh(
.sign_in(Read_data_2[15:0]),
.sign_out(Read_data_2_half_After_Sign_Extend)
);
Mux2to1_32bit Mux_sh(
.I0(Read_data_2),
.I1(Read_data_2_half_After_Sign_Extend),
.S(Half),
.out(DM_Write_Data)
);
Sign_Extend Sign_Extend_lh(
.sign_in(DM_Read_Data[15:0]),
.sign_out(DM_Read_Data_half_After_Sign_Extend)
);
Mux2to1_32bit Mux_lh(
.I0(DM_Read_Data),
.I1(DM_Read_Data_half_After_Sign_Extend),
.S(Half),
.out(Mux_lh_out)
);
Mux2to1_32bit Mux_MemToReg(
.I0(ALU_result),
.I1(Mux_lh_out),
.S(MemToReg),
.out(Mux_MemToReg_out)
);
ADD PC_ADD8(
.src1(PCout),
.src2(18'd8),
.out(PCout_Plus8)
);
Mux2to1_32bit Mux_Jal2(
.I0(Mux_MemToReg_out),
.I1({14'b0, PCout_Plus8}),
.S(Jal),
.out(Write_data)
);
ADD ADD_Branch(
.src1(Jump_Addr),
.src2(PCout_Plus4),
.out(Branch_Addr)
);
Jump_Ctrl Jump_Ctrl1(
.Zero(Zero),
.JumpOP(JumpOP),
.Branch(Branch),
.Jr(Jr),
.Jump(Jump)
);
Mux4to1_18bit Mux_PC(
.I0(PCout_Plus4),
.I1(Branch_Addr),
.I2(Read_data_1[17:0]),
.I3(Jump_Addr),
.S(JumpOP),
.out(PCin)
);
endmodule | module top ( clk,
rst,
IM_Address,
Instruction,
DM_Address,
DM_enable,
DM_Write_Data,
DM_Read_Data); |
parameter data_size = 32;
parameter mem_size = 16;
input clk, rst;
output [mem_size-1:0] IM_Address;
input [data_size-1:0] Instruction;
output [mem_size-1:0] DM_Address;
output DM_enable;
output [data_size-1:0] DM_Write_Data;
input [data_size-1:0] DM_Read_Data;
parameter bit_size = 18;
wire [bit_size-1:0] PCin;
wire [bit_size-1:0] PCout;
wire [5:0] opcode;
wire [5:0] funct;
wire RegDst, ALUSrc, MemWrite, MemRead, MemToReg, Half, Branch, Jump, Jal, Jr;
wire [3:0] ALUOp;
wire [data_size-1:0]Read_data_1;
wire [data_size-1:0]Read_data_2;
wire RegWrite;
wire [4:0] Write_addr;
wire [data_size-1:0] Write_data;
wire [mem_size-1:0] Immediate;
wire [4:0] Rs_Addr;
wire [4:0] Rt_Addr;
wire [4:0] Rd_Addr;
wire [data_size-1:0] src1;
wire [data_size-1:0] src2;
wire [4:0] shamt;
wire [data_size-1:0] ALU_result;
wire Zero;
wire [bit_size-1:0] PCout_Plus4;
wire [bit_size-1:0] PCout_Plus8;
wire [4:0] Mux_RegDst_out;
wire [data_size-1:0] Mux_MemToReg_out;
wire [data_size-1:0] Mux_lh_out;
wire [data_size-1:0] Immediate_After_Sign_Extend;
wire [data_size-1:0] Read_data_2_half_After_Sign_Extend;
wire [data_size-1:0] DM_Read_Data_half_After_Sign_Extend;
wire [1:0] JumpOP;
wire [bit_size-1:0] Jump_Addr;
wire [bit_size-1:0] Branch_Addr;
assign IM_Address = PCout [bit_size-1:2];
assign opcode = Instruction [31:26];
assign funct = Instruction [5:0];
assign DM_enable = MemWrite;
assign Immediate = Instruction[15:0];
assign Rs_Addr = Instruction[25:21];
assign Rt_Addr = Instruction[20:16];
assign Rd_Addr = Instruction[15:11];
assign shamt = Instruction[10:6];
assign src1 = Read_data_1;
assign DM_Address = ALU_result[17:2];
assign Jump_Addr = ({Immediate, 2'b0});
PC PC1(
.clk(clk),
.rst(rst),
.PCin(PCin),
.PCout(PCout)
);
ADD PC_ADD4(
.src1(PCout),
.src2(18'd4),
.out(PCout_Plus4)
);
Controller Controller1(
.opcode(opcode),
.funct(funct),
.RegDst(RegDst),
.RegWrite(RegWrite),
.ALUSrc(ALUSrc),
.ALUOp(ALUOp),
.MemWrite(MemWrite),
.MemToReg(MemToReg),
.Half(Half),
.Branch(Branch),
.Jump(Jump),
.Jal(Jal),
.Jr(Jr)
);
Mux2to1_5bit Mux_RegDst(
.I0(Rt_Addr),
.I1(Rd_Addr),
.S(RegDst),
.out(Mux_RegDst_out)
);
Mux2to1_5bit Mux_Jal1(
.I0(Mux_RegDst_out),
.I1(5'd31),
.S(Jal),
.out(Write_addr)
);
Regfile Regfile1(
.clk(clk),
.rst(rst),
.Read_addr_1(Rs_Addr),
.Read_addr_2(Rt_Addr),
.Read_data_1(Read_data_1),
.Read_data_2(Read_data_2),
.RegWrite(RegWrite),
.Write_addr(Write_addr),
.Write_data(Write_data)
);
Sign_Extend Sign_Extend_Imm(
.sign_in(Immediate),
.sign_out(Immediate_After_Sign_Extend)
);
Mux2to1_32bit Mux_ALUSrc(
.I0(Immediate_After_Sign_Extend),
.I1(Read_data_2),
.S(ALUSrc),
.out(src2)
);
ALU ALU1(
.ALUOp(ALUOp),
.src1(src1),
.src2(src2),
.shamt(shamt),
.ALU_result(ALU_result),
.Zero(Zero)
);
Sign_Extend Sign_Extend_sh(
.sign_in(Read_data_2[15:0]),
.sign_out(Read_data_2_half_After_Sign_Extend)
);
Mux2to1_32bit Mux_sh(
.I0(Read_data_2),
.I1(Read_data_2_half_After_Sign_Extend),
.S(Half),
.out(DM_Write_Data)
);
Sign_Extend Sign_Extend_lh(
.sign_in(DM_Read_Data[15:0]),
.sign_out(DM_Read_Data_half_After_Sign_Extend)
);
Mux2to1_32bit Mux_lh(
.I0(DM_Read_Data),
.I1(DM_Read_Data_half_After_Sign_Extend),
.S(Half),
.out(Mux_lh_out)
);
Mux2to1_32bit Mux_MemToReg(
.I0(ALU_result),
.I1(Mux_lh_out),
.S(MemToReg),
.out(Mux_MemToReg_out)
);
ADD PC_ADD8(
.src1(PCout),
.src2(18'd8),
.out(PCout_Plus8)
);
Mux2to1_32bit Mux_Jal2(
.I0(Mux_MemToReg_out),
.I1({14'b0, PCout_Plus8}),
.S(Jal),
.out(Write_data)
);
ADD ADD_Branch(
.src1(Jump_Addr),
.src2(PCout_Plus4),
.out(Branch_Addr)
);
Jump_Ctrl Jump_Ctrl1(
.Zero(Zero),
.JumpOP(JumpOP),
.Branch(Branch),
.Jr(Jr),
.Jump(Jump)
);
Mux4to1_18bit Mux_PC(
.I0(PCout_Plus4),
.I1(Branch_Addr),
.I2(Read_data_1[17:0]),
.I3(Jump_Addr),
.S(JumpOP),
.out(PCin)
);
endmodule | 2 |
139,186 | data/full_repos/permissive/86894739/hw3/SRC/HDU.v | 86,894,739 | HDU.v | v | 55 | 104 | [] | [] | [] | [(3, 54)] | null | data/verilator_xmls/ceccde7b-9a35-4ec0-b90d-866c00fa0d42.xml | null | 304,424 | module | module HDU (
ID_Rs,
ID_Rt,
EX_WR_out,
EX_MemtoReg,
EX_JumpOP,
PCWrite,
IF_IDWrite,
IF_Flush,
ID_Flush
);
parameter bit_size = 32;
input [4:0] ID_Rs;
input [4:0] ID_Rt;
input [4:0] EX_WR_out;
input EX_MemtoReg;
input [1:0] EX_JumpOP;
output PCWrite;
output IF_IDWrite;
output IF_Flush;
output ID_Flush;
reg PCWrite;
reg IF_IDWrite;
reg IF_Flush;
reg ID_Flush;
always @(*)
begin
PCWrite = 1;
IF_IDWrite = 1;
IF_Flush = 0;
ID_Flush = 0;
if(EX_JumpOP != 0)
begin
IF_Flush = 1;
ID_Flush = 1;
end
if((EX_MemtoReg == 1) && ((EX_WR_out == ID_Rs) || (EX_WR_out == ID_Rt)))
begin
PCWrite = 0;
IF_IDWrite = 0;
end
end
endmodule | module HDU (
ID_Rs,
ID_Rt,
EX_WR_out,
EX_MemtoReg,
EX_JumpOP,
PCWrite,
IF_IDWrite,
IF_Flush,
ID_Flush
); |
parameter bit_size = 32;
input [4:0] ID_Rs;
input [4:0] ID_Rt;
input [4:0] EX_WR_out;
input EX_MemtoReg;
input [1:0] EX_JumpOP;
output PCWrite;
output IF_IDWrite;
output IF_Flush;
output ID_Flush;
reg PCWrite;
reg IF_IDWrite;
reg IF_Flush;
reg ID_Flush;
always @(*)
begin
PCWrite = 1;
IF_IDWrite = 1;
IF_Flush = 0;
ID_Flush = 0;
if(EX_JumpOP != 0)
begin
IF_Flush = 1;
ID_Flush = 1;
end
if((EX_MemtoReg == 1) && ((EX_WR_out == ID_Rs) || (EX_WR_out == ID_Rt)))
begin
PCWrite = 0;
IF_IDWrite = 0;
end
end
endmodule | 2 |
139,187 | data/full_repos/permissive/86894739/hw3/SRC/IF_ID.v | 86,894,739 | IF_ID.v | v | 51 | 35 | [] | [] | [] | [(3, 50)] | null | data/verilator_xmls/df4b72b8-a531-41f6-97b7-74333a109b6f.xml | null | 304,426 | module | module IF_ID ( clk,
rst,
IF_IDWrite,
IF_Flush,
IF_PC,
IF_ir,
ID_PC,
ID_ir);
parameter pc_size = 18;
parameter data_size = 32;
input clk, rst;
input IF_IDWrite, IF_Flush;
input [pc_size-1:0] IF_PC;
input [data_size-1:0] IF_ir;
output [pc_size-1:0] ID_PC;
output [data_size-1:0] ID_ir;
reg [pc_size-1:0] ID_PC;
reg [data_size-1:0] ID_ir;
always@(negedge clk, posedge rst)
begin
if(rst || IF_Flush)
begin
ID_PC <= 18'b0;
ID_ir <= 32'b0;
end
else
begin
if(IF_IDWrite)
begin
ID_PC <= IF_PC;
ID_ir <= IF_ir;
end
else
begin
ID_PC <= ID_PC;
ID_ir <= ID_ir;
end
end
end
endmodule | module IF_ID ( clk,
rst,
IF_IDWrite,
IF_Flush,
IF_PC,
IF_ir,
ID_PC,
ID_ir); |
parameter pc_size = 18;
parameter data_size = 32;
input clk, rst;
input IF_IDWrite, IF_Flush;
input [pc_size-1:0] IF_PC;
input [data_size-1:0] IF_ir;
output [pc_size-1:0] ID_PC;
output [data_size-1:0] ID_ir;
reg [pc_size-1:0] ID_PC;
reg [data_size-1:0] ID_ir;
always@(negedge clk, posedge rst)
begin
if(rst || IF_Flush)
begin
ID_PC <= 18'b0;
ID_ir <= 32'b0;
end
else
begin
if(IF_IDWrite)
begin
ID_PC <= IF_PC;
ID_ir <= IF_ir;
end
else
begin
ID_PC <= ID_PC;
ID_ir <= ID_ir;
end
end
end
endmodule | 2 |
139,189 | data/full_repos/permissive/86894739/hw3/SRC/PC.v | 86,894,739 | PC.v | v | 40 | 38 | [] | [] | [] | [(3, 39)] | null | data/verilator_xmls/11e2ec95-3ba7-467c-84fb-dfc294048ef2.xml | null | 304,433 | module | module PC ( clk,
rst,
PCWrite,
PCin,
PCout);
parameter pc_size = 18;
input clk, rst;
input PCWrite;
input [pc_size-1:0] PCin;
output [pc_size-1:0] PCout;
reg [pc_size-1:0] PCout;
always@(negedge clk, posedge rst)
begin
if(rst)
begin
PCout <= 18'b0;
end
else
begin
if(PCWrite)
begin
PCout <= PCin;
end
else
begin
PCout <= PCout;
end
end
end
endmodule | module PC ( clk,
rst,
PCWrite,
PCin,
PCout); |
parameter pc_size = 18;
input clk, rst;
input PCWrite;
input [pc_size-1:0] PCin;
output [pc_size-1:0] PCout;
reg [pc_size-1:0] PCout;
always@(negedge clk, posedge rst)
begin
if(rst)
begin
PCout <= 18'b0;
end
else
begin
if(PCWrite)
begin
PCout <= PCin;
end
else
begin
PCout <= PCout;
end
end
end
endmodule | 2 |
139,190 | data/full_repos/permissive/86894739/hw4/SRC/Cache.v | 86,894,739 | Cache.v | v | 130 | 67 | [] | [] | [] | [(3, 129)] | null | null | 1: b"%Error: data/full_repos/permissive/86894739/hw4/SRC/Cache.v:75: Cannot find file containing module: 'Cache_Control'\n Cache_Control Cache_Control1 (\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86894739/hw4/SRC,data/full_repos/permissive/86894739/Cache_Control\n data/full_repos/permissive/86894739/hw4/SRC,data/full_repos/permissive/86894739/Cache_Control.v\n data/full_repos/permissive/86894739/hw4/SRC,data/full_repos/permissive/86894739/Cache_Control.sv\n Cache_Control\n Cache_Control.v\n Cache_Control.sv\n obj_dir/Cache_Control\n obj_dir/Cache_Control.v\n obj_dir/Cache_Control.sv\n%Error: data/full_repos/permissive/86894739/hw4/SRC/Cache.v:97: Cannot find file containing module: 'Cache_valid'\n Cache_valid Cache_valid1 (\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86894739/hw4/SRC/Cache.v:107: Cannot find file containing module: 'Cache_tag'\n Cache_tag Cache_tag1 (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86894739/hw4/SRC/Cache.v:120: Cannot find file containing module: 'Cache_data'\n Cache_data Cache_data1 (\n ^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 304,440 | module | module Cache (
clk,
rst,
stall,
cache_addr,
en_R,
en_W,
cache_in,
cache_out,
mem_addr,
mem_en_R,
mem_en_W,
mem_out,
mem_in
);
parameter addr_size = 16;
parameter tag_size = 11;
parameter index_size = 5;
parameter data_size = 32;
input clk, rst;
output stall;
input [addr_size-1:0] cache_addr;
input en_R;
input en_W;
input [data_size-1:0] cache_in;
output [data_size-1:0] cache_out;
output [addr_size-1:0] mem_addr;
output mem_en_R;
output mem_en_W;
output [data_size-1:0] mem_in;
input [data_size-1:0] mem_out;
wire [tag_size-1:0] tag_addr;
wire [index_size-1:0] index_addr;
wire Valid_enable;
wire Tag_enable;
wire Data_enable;
wire sel_mem_core;
wire equal;
wire hit;
wire Valid_out;
wire [tag_size-1:0] Tag_out;
wire [data_size-1:0] Data_in;
assign mem_addr = cache_addr;
assign tag_addr = cache_addr[addr_size-1:index_size];
assign index_addr = cache_addr[index_size-1:0];
assign mem_in = cache_in;
Cache_Control Cache_Control1 (
.clk(clk),
.rst(rst),
.en_R(en_R),
.en_W(en_W),
.hit(hit),
.Read_mem(mem_en_R),
.Write_mem(mem_en_W),
.Valid_enable(Valid_enable),
.Tag_enable(Tag_enable),
.Data_enable(Data_enable),
.sel_mem_core(sel_mem_core),
.stall(stall)
);
assign equal = (tag_addr==Tag_out);
assign hit = (Valid_out&&equal);
Cache_valid Cache_valid1 (
.clk(clk),
.rst(rst),
.Valid_Address(index_addr),
.Valid_enable(Valid_enable),
.Valid_in(1'b1),
.Valid_out(Valid_out)
);
Cache_tag Cache_tag1 (
.clk(clk),
.rst(rst),
.Tag_Address(index_addr),
.Tag_enable(Tag_enable),
.Tag_in(tag_addr),
.Tag_out(Tag_out)
);
assign Data_in = sel_mem_core ?
cache_in : mem_out;
Cache_data Cache_data1 (
.clk(clk),
.rst(rst),
.Data_Address(index_addr),
.Data_enable(Data_enable),
.Data_in(Data_in),
.Data_out(cache_out)
);
endmodule | module Cache (
clk,
rst,
stall,
cache_addr,
en_R,
en_W,
cache_in,
cache_out,
mem_addr,
mem_en_R,
mem_en_W,
mem_out,
mem_in
); |
parameter addr_size = 16;
parameter tag_size = 11;
parameter index_size = 5;
parameter data_size = 32;
input clk, rst;
output stall;
input [addr_size-1:0] cache_addr;
input en_R;
input en_W;
input [data_size-1:0] cache_in;
output [data_size-1:0] cache_out;
output [addr_size-1:0] mem_addr;
output mem_en_R;
output mem_en_W;
output [data_size-1:0] mem_in;
input [data_size-1:0] mem_out;
wire [tag_size-1:0] tag_addr;
wire [index_size-1:0] index_addr;
wire Valid_enable;
wire Tag_enable;
wire Data_enable;
wire sel_mem_core;
wire equal;
wire hit;
wire Valid_out;
wire [tag_size-1:0] Tag_out;
wire [data_size-1:0] Data_in;
assign mem_addr = cache_addr;
assign tag_addr = cache_addr[addr_size-1:index_size];
assign index_addr = cache_addr[index_size-1:0];
assign mem_in = cache_in;
Cache_Control Cache_Control1 (
.clk(clk),
.rst(rst),
.en_R(en_R),
.en_W(en_W),
.hit(hit),
.Read_mem(mem_en_R),
.Write_mem(mem_en_W),
.Valid_enable(Valid_enable),
.Tag_enable(Tag_enable),
.Data_enable(Data_enable),
.sel_mem_core(sel_mem_core),
.stall(stall)
);
assign equal = (tag_addr==Tag_out);
assign hit = (Valid_out&&equal);
Cache_valid Cache_valid1 (
.clk(clk),
.rst(rst),
.Valid_Address(index_addr),
.Valid_enable(Valid_enable),
.Valid_in(1'b1),
.Valid_out(Valid_out)
);
Cache_tag Cache_tag1 (
.clk(clk),
.rst(rst),
.Tag_Address(index_addr),
.Tag_enable(Tag_enable),
.Tag_in(tag_addr),
.Tag_out(Tag_out)
);
assign Data_in = sel_mem_core ?
cache_in : mem_out;
Cache_data Cache_data1 (
.clk(clk),
.rst(rst),
.Data_Address(index_addr),
.Data_enable(Data_enable),
.Data_in(Data_in),
.Data_out(cache_out)
);
endmodule | 2 |
139,191 | data/full_repos/permissive/86894739/hw4/SRC/Cache_Control.v | 86,894,739 | Cache_Control.v | v | 122 | 63 | [] | [] | [] | [(3, 121)] | null | data/verilator_xmls/02c72d9e-3039-45e1-b18d-e6aae0317914.xml | null | 304,441 | module | module Cache_Control (
clk,
rst,
en_R,
en_W,
hit,
Read_mem,
Write_mem,
Valid_enable,
Tag_enable,
Data_enable,
sel_mem_core,
stall
);
input clk, rst;
input en_R;
input en_W;
input hit;
output Read_mem;
output Write_mem;
output Valid_enable;
output Tag_enable;
output Data_enable;
output sel_mem_core;
output stall;
reg Read_mem;
reg Write_mem;
reg Valid_enable;
reg Tag_enable;
reg Data_enable;
reg sel_mem_core;
reg stall;
reg [1:0] curr_R_state;
reg [1:0] next_R_state;
parameter R_Idle = 0,
R_wait = 1,
R_Read_Memory = 2;
wire Read_Miss;
assign Read_Miss = (hit == 0 && en_R == 1)? 1: 0;
always @(*)
begin
case (curr_R_state)
R_Idle :next_R_state = (Read_Miss == 1)? R_wait: R_Idle;
R_wait :next_R_state = R_Read_Memory;
R_Read_Memory :next_R_state = R_Idle;
endcase
end
always @(*)
begin
Read_mem = 0;
Write_mem = 0;
Valid_enable = 0;
Tag_enable = 0;
Data_enable = 0;
sel_mem_core = 1;
stall = Read_Miss;
if(en_R == 1 && en_W == 0)
begin
case (curr_R_state)
R_Idle:
begin
Read_mem = (Read_Miss == 1)? 1: 0;
end
R_wait:
begin
end
R_Read_Memory:
begin
Data_enable = 1;
Tag_enable = 1;
Valid_enable = 1;
sel_mem_core = 0;
end
endcase
end
else if(en_R == 0 && en_W == 1)
begin
Write_mem = 1;
if(hit == 0)
begin
end
else
begin
Data_enable = 1;
sel_mem_core = 1;
end
end
end
always @(posedge clk or posedge rst)
begin
if(rst)
begin
curr_R_state <= R_Idle;
end
else
begin
curr_R_state <= next_R_state;
end
end
endmodule | module Cache_Control (
clk,
rst,
en_R,
en_W,
hit,
Read_mem,
Write_mem,
Valid_enable,
Tag_enable,
Data_enable,
sel_mem_core,
stall
); |
input clk, rst;
input en_R;
input en_W;
input hit;
output Read_mem;
output Write_mem;
output Valid_enable;
output Tag_enable;
output Data_enable;
output sel_mem_core;
output stall;
reg Read_mem;
reg Write_mem;
reg Valid_enable;
reg Tag_enable;
reg Data_enable;
reg sel_mem_core;
reg stall;
reg [1:0] curr_R_state;
reg [1:0] next_R_state;
parameter R_Idle = 0,
R_wait = 1,
R_Read_Memory = 2;
wire Read_Miss;
assign Read_Miss = (hit == 0 && en_R == 1)? 1: 0;
always @(*)
begin
case (curr_R_state)
R_Idle :next_R_state = (Read_Miss == 1)? R_wait: R_Idle;
R_wait :next_R_state = R_Read_Memory;
R_Read_Memory :next_R_state = R_Idle;
endcase
end
always @(*)
begin
Read_mem = 0;
Write_mem = 0;
Valid_enable = 0;
Tag_enable = 0;
Data_enable = 0;
sel_mem_core = 1;
stall = Read_Miss;
if(en_R == 1 && en_W == 0)
begin
case (curr_R_state)
R_Idle:
begin
Read_mem = (Read_Miss == 1)? 1: 0;
end
R_wait:
begin
end
R_Read_Memory:
begin
Data_enable = 1;
Tag_enable = 1;
Valid_enable = 1;
sel_mem_core = 0;
end
endcase
end
else if(en_R == 0 && en_W == 1)
begin
Write_mem = 1;
if(hit == 0)
begin
end
else
begin
Data_enable = 1;
sel_mem_core = 1;
end
end
end
always @(posedge clk or posedge rst)
begin
if(rst)
begin
curr_R_state <= R_Idle;
end
else
begin
curr_R_state <= next_R_state;
end
end
endmodule | 2 |
139,192 | data/full_repos/permissive/86894739/hw4/SRC/Cache_data.v | 86,894,739 | Cache_data.v | v | 37 | 48 | [] | [] | [] | [(3, 36)] | null | data/verilator_xmls/ff6e45ab-2b1a-4972-b139-189f8451901b.xml | null | 304,442 | module | module Cache_data (
clk,
rst,
Data_Address,
Data_enable,
Data_in,
Data_out
);
parameter bit_size = 32;
parameter mem_size = 5;
input clk, rst;
input [mem_size-1:0] Data_Address;
input Data_enable;
input [bit_size-1:0] Data_in;
output [bit_size-1:0] Data_out;
reg [bit_size-1:0] Data [0:( 2**mem_size-1 )];
assign Data_out = Data[Data_Address];
integer i;
always @ (posedge clk or posedge rst) begin
if (rst)
for (i=0;i<2**mem_size;i=i+1)
Data[i] <= 0;
else if (Data_enable)
Data[Data_Address] <= Data_in;
end
endmodule | module Cache_data (
clk,
rst,
Data_Address,
Data_enable,
Data_in,
Data_out
); |
parameter bit_size = 32;
parameter mem_size = 5;
input clk, rst;
input [mem_size-1:0] Data_Address;
input Data_enable;
input [bit_size-1:0] Data_in;
output [bit_size-1:0] Data_out;
reg [bit_size-1:0] Data [0:( 2**mem_size-1 )];
assign Data_out = Data[Data_Address];
integer i;
always @ (posedge clk or posedge rst) begin
if (rst)
for (i=0;i<2**mem_size;i=i+1)
Data[i] <= 0;
else if (Data_enable)
Data[Data_Address] <= Data_in;
end
endmodule | 2 |
139,193 | data/full_repos/permissive/86894739/hw4/SRC/Cache_tag.v | 86,894,739 | Cache_tag.v | v | 37 | 47 | [] | [] | [] | [(3, 36)] | null | data/verilator_xmls/c4108a8b-d985-4720-a389-8963769af76f.xml | null | 304,443 | module | module Cache_tag (
clk,
rst,
Tag_Address,
Tag_enable,
Tag_in,
Tag_out
);
parameter bit_size = 11;
parameter mem_size = 5;
input clk, rst;
input [mem_size-1:0] Tag_Address;
input Tag_enable;
input [bit_size-1:0] Tag_in;
output [bit_size-1:0] Tag_out;
reg [bit_size-1:0] Tag [0:( 2**mem_size-1 )];
assign Tag_out = Tag[Tag_Address];
integer i;
always @ (posedge clk or posedge rst) begin
if (rst)
for (i=0;i<2**mem_size;i=i+1)
Tag[i] <= 0;
else if (Tag_enable)
Tag[Tag_Address] <= Tag_in;
end
endmodule | module Cache_tag (
clk,
rst,
Tag_Address,
Tag_enable,
Tag_in,
Tag_out
); |
parameter bit_size = 11;
parameter mem_size = 5;
input clk, rst;
input [mem_size-1:0] Tag_Address;
input Tag_enable;
input [bit_size-1:0] Tag_in;
output [bit_size-1:0] Tag_out;
reg [bit_size-1:0] Tag [0:( 2**mem_size-1 )];
assign Tag_out = Tag[Tag_Address];
integer i;
always @ (posedge clk or posedge rst) begin
if (rst)
for (i=0;i<2**mem_size;i=i+1)
Tag[i] <= 0;
else if (Tag_enable)
Tag[Tag_Address] <= Tag_in;
end
endmodule | 2 |
139,194 | data/full_repos/permissive/86894739/hw4/SRC/Cache_valid.v | 86,894,739 | Cache_valid.v | v | 35 | 45 | [] | [] | [] | [(3, 35)] | null | data/verilator_xmls/47541844-a4dc-4a40-9797-e0da51890c4d.xml | null | 304,444 | module | module Cache_valid (
clk,
rst,
Valid_Address,
Valid_enable,
Valid_in,
Valid_out
);
parameter mem_size = 5;
input clk, rst;
input [mem_size-1:0] Valid_Address;
input Valid_enable;
input Valid_in;
output Valid_out;
reg Valid [0:( 2**mem_size-1 )];
assign Valid_out = Valid[Valid_Address];
integer i;
always @ (posedge clk or posedge rst) begin
if (rst)
for (i=0;i<2**mem_size;i=i+1)
Valid[i] <= 0;
else if (Valid_enable)
Valid[Valid_Address] <= Valid_in;
end
endmodule | module Cache_valid (
clk,
rst,
Valid_Address,
Valid_enable,
Valid_in,
Valid_out
); |
parameter mem_size = 5;
input clk, rst;
input [mem_size-1:0] Valid_Address;
input Valid_enable;
input Valid_in;
output Valid_out;
reg Valid [0:( 2**mem_size-1 )];
assign Valid_out = Valid[Valid_Address];
integer i;
always @ (posedge clk or posedge rst) begin
if (rst)
for (i=0;i<2**mem_size;i=i+1)
Valid[i] <= 0;
else if (Valid_enable)
Valid[Valid_Address] <= Valid_in;
end
endmodule | 2 |
139,196 | data/full_repos/permissive/86894739/hw4/SRC/DM.v | 86,894,739 | DM.v | v | 72 | 52 | [] | [] | [] | [(3, 64)] | null | data/verilator_xmls/36f9c4c0-cf55-4295-8dc3-feeaf9966e9d.xml | null | 304,447 | module | module DM ( clk,
rst,
DM_Address,
DM_en_Read,
DM_en_Write,
DM_Write_Data,
DM_Read_Data);
parameter bit_size = 32;
parameter mem_size = 16;
input clk, rst;
input [mem_size-1:0] DM_Address;
input DM_en_Read;
input DM_en_Write;
input [bit_size-1:0] DM_Write_Data;
output [bit_size-1:0] DM_Read_Data;
reg [bit_size-1:0] DM_data [0:( 2**mem_size-1 )];
parameter Idle = 0,
Read_data = 1;
reg nxt_state;
reg cur_state;
reg [mem_size-1:0] r_DM_Addr;
assign DM_Read_Data = DM_data[r_DM_Addr];
always @ (*) begin
case (cur_state)
Idle : nxt_state = DM_en_Read ?
Read_data : Idle;
Read_data : nxt_state = Idle;
endcase
end
integer i;
always @ (posedge clk or posedge rst) begin
if (rst) begin
for (i=0;i<2**mem_size;i=i+1)
DM_data[i] <= 0;
r_DM_Addr <= 0;
cur_state <= Idle;
end
else begin
if (cur_state==Read_data)
r_DM_Addr <= DM_Address;
cur_state <= nxt_state;
if (DM_en_Write)
DM_data[DM_Address] <= DM_Write_Data;
end
end
endmodule | module DM ( clk,
rst,
DM_Address,
DM_en_Read,
DM_en_Write,
DM_Write_Data,
DM_Read_Data); |
parameter bit_size = 32;
parameter mem_size = 16;
input clk, rst;
input [mem_size-1:0] DM_Address;
input DM_en_Read;
input DM_en_Write;
input [bit_size-1:0] DM_Write_Data;
output [bit_size-1:0] DM_Read_Data;
reg [bit_size-1:0] DM_data [0:( 2**mem_size-1 )];
parameter Idle = 0,
Read_data = 1;
reg nxt_state;
reg cur_state;
reg [mem_size-1:0] r_DM_Addr;
assign DM_Read_Data = DM_data[r_DM_Addr];
always @ (*) begin
case (cur_state)
Idle : nxt_state = DM_en_Read ?
Read_data : Idle;
Read_data : nxt_state = Idle;
endcase
end
integer i;
always @ (posedge clk or posedge rst) begin
if (rst) begin
for (i=0;i<2**mem_size;i=i+1)
DM_data[i] <= 0;
r_DM_Addr <= 0;
cur_state <= Idle;
end
else begin
if (cur_state==Read_data)
r_DM_Addr <= DM_Address;
cur_state <= nxt_state;
if (DM_en_Write)
DM_data[DM_Address] <= DM_Write_Data;
end
end
endmodule | 2 |
139,198 | data/full_repos/permissive/86894739/hw4/SRC/HDU.v | 86,894,739 | HDU.v | v | 90 | 104 | [] | [] | [] | [(3, 89)] | null | data/verilator_xmls/ec248af3-61d6-4d8a-b736-3a17d5dd1ff5.xml | null | 304,450 | module | module HDU (
ID_Rs,
ID_Rt,
EX_WR_out,
EX_MemtoReg,
EX_JumpOP,
IC_stall,
DC_stall,
PCWrite,
IF_IDWrite,
ID_EXWrite,
EX_MWrite,
M_WBWrite,
IF_Flush,
ID_Flush
);
parameter bit_size = 32;
input [4:0] ID_Rs;
input [4:0] ID_Rt;
input [4:0] EX_WR_out;
input EX_MemtoReg;
input [1:0] EX_JumpOP;
input IC_stall;
input DC_stall;
output PCWrite;
output IF_IDWrite;
output ID_EXWrite;
output EX_MWrite;
output M_WBWrite;
output IF_Flush;
output ID_Flush;
reg PCWrite;
reg IF_IDWrite;
reg ID_EXWrite;
reg EX_MWrite;
reg M_WBWrite;
reg IF_Flush;
reg ID_Flush;
always @(*)
begin
PCWrite = 1;
IF_IDWrite = 1;
ID_EXWrite = 1;
EX_MWrite = 1;
M_WBWrite = 1;
IF_Flush = 0;
ID_Flush = 0;
if(EX_JumpOP != 0)
begin
IF_Flush = 1;
ID_Flush = 1;
end
if((EX_MemtoReg == 1) && ((EX_WR_out == ID_Rs) || (EX_WR_out == ID_Rt)))
begin
PCWrite = 0;
IF_IDWrite = 0;
IF_Flush = 0;
ID_Flush = 1;
end
if (IC_stall == 1 || DC_stall == 1)
begin
PCWrite = 0;
IF_IDWrite = 0;
ID_EXWrite = 0;
EX_MWrite = 0;
M_WBWrite = 0;
IF_Flush = 0;
ID_Flush = 0;
end
end
endmodule | module HDU (
ID_Rs,
ID_Rt,
EX_WR_out,
EX_MemtoReg,
EX_JumpOP,
IC_stall,
DC_stall,
PCWrite,
IF_IDWrite,
ID_EXWrite,
EX_MWrite,
M_WBWrite,
IF_Flush,
ID_Flush
); |
parameter bit_size = 32;
input [4:0] ID_Rs;
input [4:0] ID_Rt;
input [4:0] EX_WR_out;
input EX_MemtoReg;
input [1:0] EX_JumpOP;
input IC_stall;
input DC_stall;
output PCWrite;
output IF_IDWrite;
output ID_EXWrite;
output EX_MWrite;
output M_WBWrite;
output IF_Flush;
output ID_Flush;
reg PCWrite;
reg IF_IDWrite;
reg ID_EXWrite;
reg EX_MWrite;
reg M_WBWrite;
reg IF_Flush;
reg ID_Flush;
always @(*)
begin
PCWrite = 1;
IF_IDWrite = 1;
ID_EXWrite = 1;
EX_MWrite = 1;
M_WBWrite = 1;
IF_Flush = 0;
ID_Flush = 0;
if(EX_JumpOP != 0)
begin
IF_Flush = 1;
ID_Flush = 1;
end
if((EX_MemtoReg == 1) && ((EX_WR_out == ID_Rs) || (EX_WR_out == ID_Rt)))
begin
PCWrite = 0;
IF_IDWrite = 0;
IF_Flush = 0;
ID_Flush = 1;
end
if (IC_stall == 1 || DC_stall == 1)
begin
PCWrite = 0;
IF_IDWrite = 0;
ID_EXWrite = 0;
EX_MWrite = 0;
M_WBWrite = 0;
IF_Flush = 0;
ID_Flush = 0;
end
end
endmodule | 2 |
139,204 | data/full_repos/permissive/86897159/CLZ.v | 86,897,159 | CLZ.v | v | 143 | 56 | [] | [] | [] | null | line:35: before: "end" | null | 1: b"%Error: data/full_repos/permissive/86897159/CLZ.v:35: syntax error, unexpected end, expecting endcase\n end\n ^~~\n%Error: data/full_repos/permissive/86897159/CLZ.v:41: syntax error, unexpected wire\nwire [7:0] result_stage2;\n^~~~\n%Error: data/full_repos/permissive/86897159/CLZ.v:52: syntax error, unexpected INTEGER NUMBER\n 2'b11,2'b10:\n ^~~~~\n%Error: data/full_repos/permissive/86897159/CLZ.v:90: syntax error, unexpected end, expecting endcase\n end\n ^~~\n%Error: data/full_repos/permissive/86897159/CLZ.v:97: syntax error, unexpected wire\nwire [3:0] result_stage4;\n^~~~\n%Error: data/full_repos/permissive/86897159/CLZ.v:108: syntax error, unexpected INTEGER NUMBER\n 2'b11,2'b10:\n ^~~~~\n%Error: data/full_repos/permissive/86897159/CLZ.v:141: syntax error, unexpected end, expecting endcase\n end\n ^~~\n%Error: Cannot continue\n" | 304,464 | module | module CLZ(
input [31:0] rs1,
output [31:0] rd
);
assign rd[31:5]=27'd0;
wire or_upper_16,or_down_16;
assign or_upper_16=|rs1[31:16];
assign or_down_16=|rs1[15:0];
assign condition_1={or_upper_16,or_down_16};
wire [15:0] result_stage1;
always@(*)
begin
case(condition_1)
2'b00:
begin
rd[4]=1'b0;
result_stage1=rs1[15:0];
end
2'b11,2'b10:
begin
rd[4]=1'b0;
result_stage1=rs1[31:16];
end
2'b01:
begin
rd[4]=1'b1;
result_stage1=rs1[15:0];
end
end
wire or_upper_8,or_down_8;
assign or_upper_8=|result_stage1[16:8];
assign or_down_8=|rs1[7:0];
assign condition_2={or_upper_8,or_down_8};
wire [7:0] result_stage2;
always@(*)
begin
case(condition_2)
2'b00:
begin
rd[3]=1'b0;
result_stage2=result_stage[7:0];
end
2'b11,2'b10:
begin
rd[3]=1'b0;
result_stage2=result_stage1[15:8];
end
2'b01:
begin
rd[3]=1'b1;
result_stage2=result_stage1[7:0];
end
end
wire or_upper_4,or_down_4;
assign or_upper_4=|result_stage2[7:4];
assign or_down_4=|result_stage2[3:0];
assign condition_3={or_upper_4,or_down_4};
wire [3:0] result_stage3;
always@(*)
begin
case(condition_3)
2'b00:
begin
rd[2]=1'b0;
result_stage3=result_stage2[3:0];
end
2'b11,2'b10:
begin
rd[2]=1'b0;
result_stage3=result_stage2[7:4];
end
2'b01:
begin
rd[2]=1'b1;
result_stage3=result_stage2[3:0];
end
end
wire or_upper_2,or_down_2;
assign or_upper_2=|result_stage3[3:2];
assign or_down_2=|result_stage3[1:0];
assign condition_2={or_upper_2,or_down_2};
wire [3:0] result_stage4;
always@(*)
begin
case(condition_4)
2'b00:
begin
rd[1]=1'b0;
result_stage4=result_stage3[1:0];
end
2'b11,2'b10:
begin
rd[1]=1'b0;
result_stage4=result_stage3[3:2];
end
2'b01:
begin
rd[1]=1'b0;
result_stage4=result_stage3[1:0];
end
end
assign condition_1=result_stage4;
always@(*)
begin
case(condition_1)
2'b00:
begin
rd[0]=1'b0;
end
2'b11,2'b10:
begin
rd[0]=1'b0;
end
2'b01:
begin
rd[0]=1'b1;
end
end
endmodule | module CLZ(
input [31:0] rs1,
output [31:0] rd
); |
assign rd[31:5]=27'd0;
wire or_upper_16,or_down_16;
assign or_upper_16=|rs1[31:16];
assign or_down_16=|rs1[15:0];
assign condition_1={or_upper_16,or_down_16};
wire [15:0] result_stage1;
always@(*)
begin
case(condition_1)
2'b00:
begin
rd[4]=1'b0;
result_stage1=rs1[15:0];
end
2'b11,2'b10:
begin
rd[4]=1'b0;
result_stage1=rs1[31:16];
end
2'b01:
begin
rd[4]=1'b1;
result_stage1=rs1[15:0];
end
end
wire or_upper_8,or_down_8;
assign or_upper_8=|result_stage1[16:8];
assign or_down_8=|rs1[7:0];
assign condition_2={or_upper_8,or_down_8};
wire [7:0] result_stage2;
always@(*)
begin
case(condition_2)
2'b00:
begin
rd[3]=1'b0;
result_stage2=result_stage[7:0];
end
2'b11,2'b10:
begin
rd[3]=1'b0;
result_stage2=result_stage1[15:8];
end
2'b01:
begin
rd[3]=1'b1;
result_stage2=result_stage1[7:0];
end
end
wire or_upper_4,or_down_4;
assign or_upper_4=|result_stage2[7:4];
assign or_down_4=|result_stage2[3:0];
assign condition_3={or_upper_4,or_down_4};
wire [3:0] result_stage3;
always@(*)
begin
case(condition_3)
2'b00:
begin
rd[2]=1'b0;
result_stage3=result_stage2[3:0];
end
2'b11,2'b10:
begin
rd[2]=1'b0;
result_stage3=result_stage2[7:4];
end
2'b01:
begin
rd[2]=1'b1;
result_stage3=result_stage2[3:0];
end
end
wire or_upper_2,or_down_2;
assign or_upper_2=|result_stage3[3:2];
assign or_down_2=|result_stage3[1:0];
assign condition_2={or_upper_2,or_down_2};
wire [3:0] result_stage4;
always@(*)
begin
case(condition_4)
2'b00:
begin
rd[1]=1'b0;
result_stage4=result_stage3[1:0];
end
2'b11,2'b10:
begin
rd[1]=1'b0;
result_stage4=result_stage3[3:2];
end
2'b01:
begin
rd[1]=1'b0;
result_stage4=result_stage3[1:0];
end
end
assign condition_1=result_stage4;
always@(*)
begin
case(condition_1)
2'b00:
begin
rd[0]=1'b0;
end
2'b11,2'b10:
begin
rd[0]=1'b0;
end
2'b01:
begin
rd[0]=1'b1;
end
end
endmodule | 1 |
139,205 | data/full_repos/permissive/86997165/icestorm/blink.v | 86,997,165 | blink.v | v | 275 | 121 | [] | [] | [] | [(21, 274)] | null | null | 1: b"%Error: data/full_repos/permissive/86997165/icestorm/blink.v:76: Cannot find file containing module: 'GP_SYSRESET'\n GP_SYSRESET #(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86997165/icestorm,data/full_repos/permissive/86997165/GP_SYSRESET\n data/full_repos/permissive/86997165/icestorm,data/full_repos/permissive/86997165/GP_SYSRESET.v\n data/full_repos/permissive/86997165/icestorm,data/full_repos/permissive/86997165/GP_SYSRESET.sv\n GP_SYSRESET\n GP_SYSRESET.v\n GP_SYSRESET.sv\n obj_dir/GP_SYSRESET\n obj_dir/GP_SYSRESET.v\n obj_dir/GP_SYSRESET.sv\n%Error: data/full_repos/permissive/86997165/icestorm/blink.v:84: Cannot find file containing module: 'GP_POR'\n GP_POR #(\n ^~~~~~\n%Error: data/full_repos/permissive/86997165/icestorm/blink.v:95: Cannot find file containing module: 'GP_LFOSC'\n GP_LFOSC #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/86997165/icestorm/blink.v:107: Cannot find file containing module: 'GP_RINGOSC'\n GP_RINGOSC #(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86997165/icestorm/blink.v:121: Cannot find file containing module: 'GP_RCOSC'\n GP_RCOSC #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/86997165/icestorm/blink.v:168: Cannot find file containing module: 'GP_COUNT8'\n GP_COUNT8 #(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/86997165/icestorm/blink.v:183: Cannot find file containing module: 'GP_COUNT14'\n GP_COUNT14 #(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86997165/icestorm/blink.v:198: Cannot find file containing module: 'GP_COUNT14'\n GP_COUNT14 #(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86997165/icestorm/blink.v:251: Cannot find file containing module: 'GP_SHREG'\n GP_SHREG #(\n ^~~~~~~~\n%Error: Exiting due to 9 error(s)\n" | 304,465 | module | module main(
led_lfosc_ff, led_lfosc_count, led_lfosc_shreg1, led_lfosc_shreg1a, led_lfosc_shreg2, led_lfosc_shreg2a,
led_rosc_ff, led_rcosc_ff,
sys_rst, count_rst, osc_pwrdn);
(* LOC = "P20" *)
output reg led_lfosc_ff = 0;
(* LOC = "P19" *)
output reg led_lfosc_count = 0;
(* LOC = "P18" *)
output wire led_lfosc_shreg1;
(* LOC = "P17" *)
output wire led_lfosc_shreg1a;
(* LOC = "P16" *)
output wire led_lfosc_shreg2;
(* LOC = "P15" *)
output wire led_lfosc_shreg2a;
(* LOC = "P14" *)
output reg led_rosc_ff = 0;
(* LOC = "P13" *)
output reg led_rcosc_ff = 0;
(* LOC = "P2" *)
(* PULLDOWN = "10k" *)
(* SCHMITT_TRIGGER *)
input wire sys_rst;
(* LOC = "P3" *)
(* PULLDOWN = "10k" *)
(* SCHMITT_TRIGGER *)
input wire count_rst;
(* LOC = "P4" *)
(* PULLDOWN = "10k" *)
(* SCHMITT_TRIGGER *)
input wire osc_pwrdn;
GP_SYSRESET #(
.RESET_MODE("LEVEL")
) reset_ctrl (
.RST(sys_rst)
);
wire por_done;
GP_POR #(
.POR_TIME(500)
) por (
.RST_DONE(por_done)
);
wire clk_108hz;
GP_LFOSC #(
.PWRDN_EN(1),
.AUTO_PWRDN(0),
.OUT_DIV(16)
) lfosc (
.PWRDN(osc_pwrdn),
.CLKOUT(clk_108hz)
);
wire clk_1687khz_cnt;
wire clk_1687khz;
GP_RINGOSC #(
.PWRDN_EN(1),
.AUTO_PWRDN(0),
.HARDIP_DIV(16),
.FABRIC_DIV(1)
) ringosc (
.PWRDN(osc_pwrdn),
.CLKOUT_HARDIP(clk_1687khz_cnt),
.CLKOUT_FABRIC(clk_1687khz)
);
wire clk_6khz_cnt;
wire clk_6khz;
GP_RCOSC #(
.PWRDN_EN(1),
.AUTO_PWRDN(0),
.OSC_FREQ("25k"),
.HARDIP_DIV(4),
.FABRIC_DIV(1)
) rcosc (
.PWRDN(osc_pwrdn),
.CLKOUT_HARDIP(clk_6khz_cnt),
.CLKOUT_FABRIC(clk_6khz)
);
localparam COUNT_MAX = 31;
reg[7:0] count = COUNT_MAX;
always @(posedge clk_108hz, posedge count_rst) begin
if(count_rst)
count <= 0;
else begin
if(count == 0)
count <= COUNT_MAX;
else
count <= count - 1'd1;
end
end
wire led_fabric_raw = (count == 0);
wire led_lfosc_raw;
(* LOC = "COUNT8_7" *)
GP_COUNT8 #(
.RESET_MODE("LEVEL"),
.COUNT_TO(COUNT_MAX),
.CLKIN_DIVIDE(1)
) lfosc_cnt (
.CLK(clk_108hz),
.RST(count_rst),
.OUT(led_lfosc_raw)
);
wire led_rosc_raw;
GP_COUNT14 #(
.RESET_MODE("LEVEL"),
.COUNT_TO(16383),
.CLKIN_DIVIDE(1)
) ringosc_cnt (
.CLK(clk_1687khz_cnt),
.RST(count_rst),
.OUT(led_rosc_raw)
);
wire led_rcosc_raw;
GP_COUNT14 #(
.RESET_MODE("LEVEL"),
.COUNT_TO(1023),
.CLKIN_DIVIDE(1)
) rcosc_cnt (
.CLK(clk_6khz_cnt),
.RST(count_rst),
.OUT(led_rcosc_raw)
);
always @(posedge clk_108hz) begin
if(por_done) begin
if(led_fabric_raw)
led_lfosc_ff <= ~led_lfosc_ff;
if(led_lfosc_raw)
led_lfosc_count <= ~led_lfosc_count;
end
end
reg[3:0] pdiv = 0;
always @(posedge clk_1687khz) begin
if(led_rosc_raw) begin
pdiv <= pdiv + 1'd1;
if(pdiv == 0)
led_rosc_ff <= ~led_rosc_ff;
end
end
always @(posedge clk_6khz) begin
if(led_rcosc_raw)
led_rcosc_ff <= ~led_rcosc_ff;
end
GP_SHREG #(
.OUTA_TAP(8),
.OUTA_INVERT(0),
.OUTB_TAP(16)
) shreg (
.nRST(1'b1),
.CLK(clk_108hz),
.IN(led_lfosc_ff),
.OUTA(led_lfosc_shreg1),
.OUTB(led_lfosc_shreg2)
);
reg[15:0] led_lfosc_infreg = 0;
assign led_lfosc_shreg1a = led_lfosc_infreg[7];
assign led_lfosc_shreg2a = led_lfosc_infreg[15];
always @(posedge clk_108hz) begin
led_lfosc_infreg <= {led_lfosc_infreg[14:0], led_lfosc_ff};
end
endmodule | module main(
led_lfosc_ff, led_lfosc_count, led_lfosc_shreg1, led_lfosc_shreg1a, led_lfosc_shreg2, led_lfosc_shreg2a,
led_rosc_ff, led_rcosc_ff,
sys_rst, count_rst, osc_pwrdn); |
(* LOC = "P20" *)
output reg led_lfosc_ff = 0;
(* LOC = "P19" *)
output reg led_lfosc_count = 0;
(* LOC = "P18" *)
output wire led_lfosc_shreg1;
(* LOC = "P17" *)
output wire led_lfosc_shreg1a;
(* LOC = "P16" *)
output wire led_lfosc_shreg2;
(* LOC = "P15" *)
output wire led_lfosc_shreg2a;
(* LOC = "P14" *)
output reg led_rosc_ff = 0;
(* LOC = "P13" *)
output reg led_rcosc_ff = 0;
(* LOC = "P2" *)
(* PULLDOWN = "10k" *)
(* SCHMITT_TRIGGER *)
input wire sys_rst;
(* LOC = "P3" *)
(* PULLDOWN = "10k" *)
(* SCHMITT_TRIGGER *)
input wire count_rst;
(* LOC = "P4" *)
(* PULLDOWN = "10k" *)
(* SCHMITT_TRIGGER *)
input wire osc_pwrdn;
GP_SYSRESET #(
.RESET_MODE("LEVEL")
) reset_ctrl (
.RST(sys_rst)
);
wire por_done;
GP_POR #(
.POR_TIME(500)
) por (
.RST_DONE(por_done)
);
wire clk_108hz;
GP_LFOSC #(
.PWRDN_EN(1),
.AUTO_PWRDN(0),
.OUT_DIV(16)
) lfosc (
.PWRDN(osc_pwrdn),
.CLKOUT(clk_108hz)
);
wire clk_1687khz_cnt;
wire clk_1687khz;
GP_RINGOSC #(
.PWRDN_EN(1),
.AUTO_PWRDN(0),
.HARDIP_DIV(16),
.FABRIC_DIV(1)
) ringosc (
.PWRDN(osc_pwrdn),
.CLKOUT_HARDIP(clk_1687khz_cnt),
.CLKOUT_FABRIC(clk_1687khz)
);
wire clk_6khz_cnt;
wire clk_6khz;
GP_RCOSC #(
.PWRDN_EN(1),
.AUTO_PWRDN(0),
.OSC_FREQ("25k"),
.HARDIP_DIV(4),
.FABRIC_DIV(1)
) rcosc (
.PWRDN(osc_pwrdn),
.CLKOUT_HARDIP(clk_6khz_cnt),
.CLKOUT_FABRIC(clk_6khz)
);
localparam COUNT_MAX = 31;
reg[7:0] count = COUNT_MAX;
always @(posedge clk_108hz, posedge count_rst) begin
if(count_rst)
count <= 0;
else begin
if(count == 0)
count <= COUNT_MAX;
else
count <= count - 1'd1;
end
end
wire led_fabric_raw = (count == 0);
wire led_lfosc_raw;
(* LOC = "COUNT8_7" *)
GP_COUNT8 #(
.RESET_MODE("LEVEL"),
.COUNT_TO(COUNT_MAX),
.CLKIN_DIVIDE(1)
) lfosc_cnt (
.CLK(clk_108hz),
.RST(count_rst),
.OUT(led_lfosc_raw)
);
wire led_rosc_raw;
GP_COUNT14 #(
.RESET_MODE("LEVEL"),
.COUNT_TO(16383),
.CLKIN_DIVIDE(1)
) ringosc_cnt (
.CLK(clk_1687khz_cnt),
.RST(count_rst),
.OUT(led_rosc_raw)
);
wire led_rcosc_raw;
GP_COUNT14 #(
.RESET_MODE("LEVEL"),
.COUNT_TO(1023),
.CLKIN_DIVIDE(1)
) rcosc_cnt (
.CLK(clk_6khz_cnt),
.RST(count_rst),
.OUT(led_rcosc_raw)
);
always @(posedge clk_108hz) begin
if(por_done) begin
if(led_fabric_raw)
led_lfosc_ff <= ~led_lfosc_ff;
if(led_lfosc_raw)
led_lfosc_count <= ~led_lfosc_count;
end
end
reg[3:0] pdiv = 0;
always @(posedge clk_1687khz) begin
if(led_rosc_raw) begin
pdiv <= pdiv + 1'd1;
if(pdiv == 0)
led_rosc_ff <= ~led_rosc_ff;
end
end
always @(posedge clk_6khz) begin
if(led_rcosc_raw)
led_rcosc_ff <= ~led_rcosc_ff;
end
GP_SHREG #(
.OUTA_TAP(8),
.OUTA_INVERT(0),
.OUTB_TAP(16)
) shreg (
.nRST(1'b1),
.CLK(clk_108hz),
.IN(led_lfosc_ff),
.OUTA(led_lfosc_shreg1),
.OUTB(led_lfosc_shreg2)
);
reg[15:0] led_lfosc_infreg = 0;
assign led_lfosc_shreg1a = led_lfosc_infreg[7];
assign led_lfosc_shreg2a = led_lfosc_infreg[15];
always @(posedge clk_108hz) begin
led_lfosc_infreg <= {led_lfosc_infreg[14:0], led_lfosc_ff};
end
endmodule | 0 |
139,206 | data/full_repos/permissive/86997165/icestorm/LFOsc.v | 86,997,165 | LFOsc.v | v | 48 | 121 | [] | [] | [] | [(27, 47)] | null | null | 1: b"%Error: data/full_repos/permissive/86997165/icestorm/LFOsc.v:38: Cannot find file containing module: 'GP_LFOSC'\n GP_LFOSC #(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86997165/icestorm,data/full_repos/permissive/86997165/GP_LFOSC\n data/full_repos/permissive/86997165/icestorm,data/full_repos/permissive/86997165/GP_LFOSC.v\n data/full_repos/permissive/86997165/icestorm,data/full_repos/permissive/86997165/GP_LFOSC.sv\n GP_LFOSC\n GP_LFOSC.v\n GP_LFOSC.sv\n obj_dir/GP_LFOSC\n obj_dir/GP_LFOSC.v\n obj_dir/GP_LFOSC.sv\n%Error: Exiting due to 1 error(s)\n" | 304,466 | module | module main(clkout);
(* LOC = "P13" *)
output wire clkout;
GP_LFOSC #(
.PWRDN_EN(0),
.AUTO_PWRDN(0),
.OUT_DIV(2)
) lfosc (
.PWRDN(1'b0),
.CLKOUT(clkout)
);
endmodule | module main(clkout); |
(* LOC = "P13" *)
output wire clkout;
GP_LFOSC #(
.PWRDN_EN(0),
.AUTO_PWRDN(0),
.OUT_DIV(2)
) lfosc (
.PWRDN(1'b0),
.CLKOUT(clkout)
);
endmodule | 0 |
139,207 | data/full_repos/permissive/86997165/icestorm/Luts.v | 86,997,165 | Luts.v | v | 62 | 121 | [] | [] | [] | [(27, 61)] | null | null | 1: b"%Error: data/full_repos/permissive/86997165/icestorm/Luts.v:44: Cannot find file containing module: 'GP_INV'\n GP_INV inv_inst (\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/86997165/icestorm,data/full_repos/permissive/86997165/GP_INV\n data/full_repos/permissive/86997165/icestorm,data/full_repos/permissive/86997165/GP_INV.v\n data/full_repos/permissive/86997165/icestorm,data/full_repos/permissive/86997165/GP_INV.sv\n GP_INV\n GP_INV.v\n GP_INV.sv\n obj_dir/GP_INV\n obj_dir/GP_INV.v\n obj_dir/GP_INV.sv\n%Error: data/full_repos/permissive/86997165/icestorm/Luts.v:46: Cannot find file containing module: 'GP_2LUT'\n GP_2LUT #(.INIT(4'h7)) lut2_inst (\n ^~~~~~~\n%Error: data/full_repos/permissive/86997165/icestorm/Luts.v:48: Cannot find file containing module: 'GP_3LUT'\n GP_3LUT #(.INIT(8'h7F)) lut3_inst (\n ^~~~~~~\n%Error: data/full_repos/permissive/86997165/icestorm/Luts.v:50: Cannot find file containing module: 'GP_4LUT'\n GP_4LUT #(.INIT(16'h7FFF)) lut4_inst (\n ^~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 304,467 | module | module main(din, dout_instantiated, dout_inferred);
(* LOC = "P5 P4 P3 P2" *)
input wire[3:0] din;
(* LOC = "P9 P8 P7 P6" *)
output wire[3:0] dout_instantiated;
(* LOC = "P15 P14 P13 P12" *)
output wire[3:0] dout_inferred;
GP_INV inv_inst (
.IN(din[0]), .OUT(dout_instantiated[0]));
GP_2LUT #(.INIT(4'h7)) lut2_inst (
.IN0(din[0]), .IN1(din[1]), .OUT(dout_instantiated[1]));
GP_3LUT #(.INIT(8'h7F)) lut3_inst (
.IN0(din[0]), .IN1(din[1]), .IN2(din[2]), .OUT(dout_instantiated[2]));
GP_4LUT #(.INIT(16'h7FFF)) lut4_inst (
.IN0(din[0]), .IN1(din[1]), .IN2(din[2]), .IN3(din[3]), .OUT(dout_instantiated[3]));
assign dout_inferred[0] = ~din[0];
assign dout_inferred[1] = ~(din[0] & din[1]);
assign dout_inferred[2] = ~(din[0] & din[1] & din[2]);
assign dout_inferred[3] = ~(din[0] & din[1] & din[2] & din[3]);
endmodule | module main(din, dout_instantiated, dout_inferred); |
(* LOC = "P5 P4 P3 P2" *)
input wire[3:0] din;
(* LOC = "P9 P8 P7 P6" *)
output wire[3:0] dout_instantiated;
(* LOC = "P15 P14 P13 P12" *)
output wire[3:0] dout_inferred;
GP_INV inv_inst (
.IN(din[0]), .OUT(dout_instantiated[0]));
GP_2LUT #(.INIT(4'h7)) lut2_inst (
.IN0(din[0]), .IN1(din[1]), .OUT(dout_instantiated[1]));
GP_3LUT #(.INIT(8'h7F)) lut3_inst (
.IN0(din[0]), .IN1(din[1]), .IN2(din[2]), .OUT(dout_instantiated[2]));
GP_4LUT #(.INIT(16'h7FFF)) lut4_inst (
.IN0(din[0]), .IN1(din[1]), .IN2(din[2]), .IN3(din[3]), .OUT(dout_instantiated[3]));
assign dout_inferred[0] = ~din[0];
assign dout_inferred[1] = ~(din[0] & din[1]);
assign dout_inferred[2] = ~(din[0] & din[1] & din[2]);
assign dout_inferred[3] = ~(din[0] & din[1] & din[2] & din[3]);
endmodule | 0 |
139,215 | data/full_repos/permissive/87016519/fifo1.v | 87,016,519 | fifo1.v | v | 73 | 122 | [] | [] | [] | null | line:1 column:1: Illegal character '\x00' | null | 1: b'%Error: data/full_repos/permissive/87016519/fifo1.v:15: Cannot find include file: utils.v\n`include "utils.v" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87016519,data/full_repos/permissive/87016519/utils.v\n data/full_repos/permissive/87016519,data/full_repos/permissive/87016519/utils.v.v\n data/full_repos/permissive/87016519,data/full_repos/permissive/87016519/utils.v.sv\n utils.v\n utils.v.v\n utils.v.sv\n obj_dir/utils.v\n obj_dir/utils.v.v\n obj_dir/utils.v.sv\n%Error: Exiting due to 1 error(s)\n' | 304,479 | module | module fifo1(
input clk_i,
input rst_i,
input [g_width-1:0] data_i,
input push_i,
input pull_i,
output [g_width-1:0] data_o,
output full_o,
output empty_o
);
parameter g_width = 32;
reg [g_width-1:0] mem;
reg full;
reg empty;
initial mem = 0;
always @(posedge clk_i, negedge rst_i)
if(!rst_i)
begin
empty <= 1;
full <= 0;
end
else
begin
if(push_i & !full)
begin
empty <= 0;
mem <= data_i;
full <= 1;
end
else if (pull_i & !empty)
begin
empty <= 1;
full <= 0;
end
end
assign data_o = mem;
assign empty_o = empty;
assign full_o = full;
endmodule | module fifo1(
input clk_i,
input rst_i,
input [g_width-1:0] data_i,
input push_i,
input pull_i,
output [g_width-1:0] data_o,
output full_o,
output empty_o
); |
parameter g_width = 32;
reg [g_width-1:0] mem;
reg full;
reg empty;
initial mem = 0;
always @(posedge clk_i, negedge rst_i)
if(!rst_i)
begin
empty <= 1;
full <= 0;
end
else
begin
if(push_i & !full)
begin
empty <= 0;
mem <= data_i;
full <= 1;
end
else if (pull_i & !empty)
begin
empty <= 1;
full <= 0;
end
end
assign data_o = mem;
assign empty_o = empty;
assign full_o = full;
endmodule | 3 |
139,217 | data/full_repos/permissive/87016519/fifo_test.v | 87,016,519 | fifo_test.v | v | 43 | 81 | [] | [] | [] | [(25, 41)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/87016519/fifo_test.v:35: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/87016519/fifo_test.v:28: Cannot find file containing module: \'axi_spi_test\'\n axi_spi_test uut (\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87016519,data/full_repos/permissive/87016519/axi_spi_test\n data/full_repos/permissive/87016519,data/full_repos/permissive/87016519/axi_spi_test.v\n data/full_repos/permissive/87016519,data/full_repos/permissive/87016519/axi_spi_test.sv\n axi_spi_test\n axi_spi_test.v\n axi_spi_test.sv\n obj_dir/axi_spi_test\n obj_dir/axi_spi_test.v\n obj_dir/axi_spi_test.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,481 | module | module fifo_test;
axi_spi_test uut (
);
initial begin
#100;
end
endmodule | module fifo_test; |
axi_spi_test uut (
);
initial begin
#100;
end
endmodule | 3 |
139,220 | data/full_repos/permissive/87016519/spi_master.v | 87,016,519 | spi_master.v | v | 400 | 121 | [] | [] | [] | null | line:259: before: ";" | null | 1: b'%Error: data/full_repos/permissive/87016519/spi_master.v:94: Cannot find file containing module: \'CLK_gen\'\n CLK_gen sclk_gen(clk_i, clock_en_y, reset_n_i, clk_div_y, sclk_y);\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/87016519,data/full_repos/permissive/87016519/CLK_gen\n data/full_repos/permissive/87016519,data/full_repos/permissive/87016519/CLK_gen.v\n data/full_repos/permissive/87016519,data/full_repos/permissive/87016519/CLK_gen.sv\n CLK_gen\n CLK_gen.v\n CLK_gen.sv\n obj_dir/CLK_gen\n obj_dir/CLK_gen.v\n obj_dir/CLK_gen.sv\n%Warning-WIDTH: data/full_repos/permissive/87016519/spi_master.v:395: Operator NOT expects 4 bits on the LHS, but LHS\'s VARREF \'ss_y\' generates 1 bits.\n : ... In instance spi_master\n assign spi_ssel_o = (ss_y) ? ~(ss_y) : 4\'hF; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 304,484 | module | module spi_master (
input clk_i,
input reset_n_i,
input [31:0] reg_control_i,
input [31:0] reg_trans_ctrl_i,
output trans_done_o,
input trans_start_i,
input tx_empty_i,
input [31:0] tx_data_i,
output tx_pull_o,
input rx_full_i,
output [31:0] rx_data_o,
output rx_push_o,
output [3:0] spi_ssel_o,
output spi_sck_o,
output spi_mosi_o,
input spi_miso_i
);
wire [3:0] clk_div_y;
wire cpol_y,cpha_y;
wire sclk_y;
assign clk_div_y = reg_control_i[3:0];
assign cpol_y = reg_control_i[9];
assign cpha_y = reg_control_i[10];
reg clock_en_y;
wire msb_first;
assign msb_first = reg_control_i[8];
CLK_gen sclk_gen(clk_i, clock_en_y, reset_n_i, clk_div_y, sclk_y);
reg prev_sclk_y;
always @ (posedge clk_i)
prev_sclk_y <= sclk_y;
reg sclk_rise_y;
always @(posedge clk_i)
begin
if (!prev_sclk_y & sclk_y)
sclk_rise_y <= 1;
else
sclk_rise_y <= 0;
end
reg sclk_fall_y;
always @(posedge clk_i)
begin
if (prev_sclk_y & !sclk_y)
sclk_fall_y <= 1;
else
sclk_fall_y <= 0;
end
wire samp_ce_y;
wire shift_ce_y;
assign samp_ce_y = (!cpha_y) ? sclk_rise_y : sclk_fall_y;
assign shift_ce_y = (!cpha_y) ? sclk_fall_y : sclk_rise_y;
reg sclk_delay_y;
reg slave_select_en_delay_y;
always @ (posedge clk_i,negedge reset_n_i)
begin
if(!reset_n_i)
begin
sclk_delay_y <= 0;
slave_select_en_delay_y <= 0;
end
else
begin
sclk_delay_y <= sclk_y;
slave_select_en_delay_y <= slave_select_en_y;
end
end
reg spi_sclk_y;
reg ss_y;
always @ (posedge clk_i,negedge reset_n_i)
begin
if(!reset_n_i)
begin
spi_sclk_y <= 0;
ss_y = 0;
end
else
begin
spi_sclk_y <= sclk_delay_y;
ss_y = slave_select_en_delay_y;
end
end
localparam [1:0]
IDLE = 2'b00,
LOAD = 2'b01,
TRANSFER = 2'b10,
TRANSFER_DONE = 2'b11;
reg [5:0] bits;
always@(*)
begin
case(reg_trans_ctrl_i[6:5])
2'b00 : bits <= 8;
2'b01 : bits <= 16;
2'b10 : bits <= 32;
default : bits <= 8;
endcase
end
reg [1:0] state;
reg tx_pull_y,rx_push_y;
reg transfer_en_y;
reg trans_done_y;
reg [5:0] bit_counter_y;
reg [5:0] num_of_transferred_bits_y;
reg slave_select_en_y;
always @(posedge clk_i,negedge reset_n_i)
begin
if (!reset_n_i)
begin
state <= IDLE;
tx_pull_y <= 0;
trans_done_y <= 0;
transfer_en_y <= 0;
rx_push_y <= 0;
clock_en_y <= 0;
slave_select_en_y <= 0;
num_of_transferred_bits_y <= 0;
end
else
case(state)
IDLE :
begin
tx_pull_y <= 0;
trans_done_y <= 0;
transfer_en_y <= 0;
rx_push_y <= 0;
clock_en_y <= 0;
slave_select_en_y <= 0;
if(trans_start_i)
begin
state <= LOAD;
end
end
LOAD :
begin
tx_pull_y <= 1;
rx_push_y <= 0;
trans_done_y <= 0;
transfer_en_y <= 1;
clock_en_y <= 1;
slave_select_en_y <= 1;
num_of_transferred_bits_y <= bits;
state <= TRANSFER;
end
TRANSFER :
begin
transfer_en_y <= 0;
tx_pull_y <= 0;
if(bit_counter_y == num_of_transferred_bits_y)
state <= TRANSFER_DONE;
end
TRANSFER_DONE :
begin
clock_en_y <= 0;
rx_push_y <= 1;
if(!tx_empty_i)
begin
state <= LOAD;
end
else
begin
trans_done_y <= 1;
state <= IDLE;
end
end
endcase
end
always @(posedge clk_i,negedge reset_n_i)
begin
if (!reset_n_i)
bit_counter_y <= 0;
else if(transfer_en_y || rx_push_y )
bit_counter_y <= 0;
else if(state == TRANSFER && !cpha_y && shift_ce_y)
bit_counter_y <= bit_counter_y+1 ;
else if(state == TRANSFER && cpha_y && samp_ce_y)
bit_counter_y <= bit_counter_y+1;
else
bit_counter_y <= bit_counter_y;
end;
reg [7:0] fifo0,fifo1,fifo2,fifo3;
always@(posedge clk_i,negedge reset_n_i)
begin
if(!reset_n_i)
begin
fifo0 <= 0;
fifo1 <= 0;
fifo2 <= 0;
fifo3 <= 0;
end
else if(tx_pull_y)
begin
fifo0 <= tx_data_i[7:0];
fifo1 <= tx_data_i[15:8];
fifo2 <= tx_data_i[23:16];
fifo3 <= tx_data_i[31:24];
end
else if(ss_y)
begin
if(samp_ce_y)
begin
if(!msb_first)
begin
fifo0 <= {fifo1[0],fifo0[7:1]};
fifo1 <= {fifo2[0],fifo1[7:1]};
fifo2 <= {fifo3[0],fifo2[7:1]};
fifo3 <= {spi_miso_i,fifo3[7:1]};
end
else
begin
fifo0 <= {fifo0[6:0],spi_miso_i};
fifo1 <= {fifo1[6:0],fifo0[7]};
fifo2 <= {fifo2[6:0],fifo1[7]};
fifo3 <= {fifo3[6:0],fifo2[7]};
end
end
end
end
reg data_valid_y;
always@(posedge clk_i,negedge reset_n_i)
begin
if(!reset_n_i)
data_valid_y<=0;
else
data_valid_y<= tx_pull_y;
end
wire en;
assign en = (data_valid_y && !cpha_y) ? 1'b1 : 1'b0;
reg mosi_y;
reg [31:0] rx_data_y;
always@(posedge clk_i,negedge reset_n_i)
begin
if(!reset_n_i || !ss_y)
mosi_y <= 1'b0;
else if(shift_ce_y || (en))
begin
if(!msb_first)
mosi_y <= fifo0[0];
else
begin
case(num_of_transferred_bits_y)
6'd8 : mosi_y <= fifo0[7];
6'd16 : mosi_y <= fifo1[7];
6'd32 : mosi_y <= fifo3[7];
endcase
end
end
end
initial rx_data_y = 0;
always@(*)
begin
if(!msb_first)
begin
case(num_of_transferred_bits_y)
6'd8 : rx_data_y <= {24'd0,fifo3};
6'd16 : rx_data_y <= {16'd0,fifo3,fifo2};
6'd32 : rx_data_y <= {fifo3,fifo2,fifo1,fifo0};
endcase
end
else
begin
case(num_of_transferred_bits_y)
6'd8 : rx_data_y <= {24'd0,fifo0};
6'd16 : rx_data_y <= {16'd0,fifo1,fifo0};
6'd32 : rx_data_y <= {fifo3,fifo2,fifo1,fifo0};
endcase
end
end
reg [31:0] rx_data;
always@(posedge clk_i,negedge reset_n_i)
begin
if(!reset_n_i)
rx_data <= 0;
else
rx_data <= rx_data_y;
end
wire [3:0] ss_n = reg_trans_ctrl_i[3:0];
assign tx_pull_o = tx_pull_y;
assign trans_done_o = trans_done_y;
assign rx_data_o = rx_data;
assign rx_push_o = rx_push_y;
assign spi_ssel_o = (ss_y) ? ~(ss_y) : 4'hF;
assign spi_sck_o = (cpol_y) ? ~spi_sclk_y : spi_sclk_y;
assign spi_mosi_o = (ss_y) ? mosi_y : 1'bz;
endmodule | module spi_master (
input clk_i,
input reset_n_i,
input [31:0] reg_control_i,
input [31:0] reg_trans_ctrl_i,
output trans_done_o,
input trans_start_i,
input tx_empty_i,
input [31:0] tx_data_i,
output tx_pull_o,
input rx_full_i,
output [31:0] rx_data_o,
output rx_push_o,
output [3:0] spi_ssel_o,
output spi_sck_o,
output spi_mosi_o,
input spi_miso_i
); |
wire [3:0] clk_div_y;
wire cpol_y,cpha_y;
wire sclk_y;
assign clk_div_y = reg_control_i[3:0];
assign cpol_y = reg_control_i[9];
assign cpha_y = reg_control_i[10];
reg clock_en_y;
wire msb_first;
assign msb_first = reg_control_i[8];
CLK_gen sclk_gen(clk_i, clock_en_y, reset_n_i, clk_div_y, sclk_y);
reg prev_sclk_y;
always @ (posedge clk_i)
prev_sclk_y <= sclk_y;
reg sclk_rise_y;
always @(posedge clk_i)
begin
if (!prev_sclk_y & sclk_y)
sclk_rise_y <= 1;
else
sclk_rise_y <= 0;
end
reg sclk_fall_y;
always @(posedge clk_i)
begin
if (prev_sclk_y & !sclk_y)
sclk_fall_y <= 1;
else
sclk_fall_y <= 0;
end
wire samp_ce_y;
wire shift_ce_y;
assign samp_ce_y = (!cpha_y) ? sclk_rise_y : sclk_fall_y;
assign shift_ce_y = (!cpha_y) ? sclk_fall_y : sclk_rise_y;
reg sclk_delay_y;
reg slave_select_en_delay_y;
always @ (posedge clk_i,negedge reset_n_i)
begin
if(!reset_n_i)
begin
sclk_delay_y <= 0;
slave_select_en_delay_y <= 0;
end
else
begin
sclk_delay_y <= sclk_y;
slave_select_en_delay_y <= slave_select_en_y;
end
end
reg spi_sclk_y;
reg ss_y;
always @ (posedge clk_i,negedge reset_n_i)
begin
if(!reset_n_i)
begin
spi_sclk_y <= 0;
ss_y = 0;
end
else
begin
spi_sclk_y <= sclk_delay_y;
ss_y = slave_select_en_delay_y;
end
end
localparam [1:0]
IDLE = 2'b00,
LOAD = 2'b01,
TRANSFER = 2'b10,
TRANSFER_DONE = 2'b11;
reg [5:0] bits;
always@(*)
begin
case(reg_trans_ctrl_i[6:5])
2'b00 : bits <= 8;
2'b01 : bits <= 16;
2'b10 : bits <= 32;
default : bits <= 8;
endcase
end
reg [1:0] state;
reg tx_pull_y,rx_push_y;
reg transfer_en_y;
reg trans_done_y;
reg [5:0] bit_counter_y;
reg [5:0] num_of_transferred_bits_y;
reg slave_select_en_y;
always @(posedge clk_i,negedge reset_n_i)
begin
if (!reset_n_i)
begin
state <= IDLE;
tx_pull_y <= 0;
trans_done_y <= 0;
transfer_en_y <= 0;
rx_push_y <= 0;
clock_en_y <= 0;
slave_select_en_y <= 0;
num_of_transferred_bits_y <= 0;
end
else
case(state)
IDLE :
begin
tx_pull_y <= 0;
trans_done_y <= 0;
transfer_en_y <= 0;
rx_push_y <= 0;
clock_en_y <= 0;
slave_select_en_y <= 0;
if(trans_start_i)
begin
state <= LOAD;
end
end
LOAD :
begin
tx_pull_y <= 1;
rx_push_y <= 0;
trans_done_y <= 0;
transfer_en_y <= 1;
clock_en_y <= 1;
slave_select_en_y <= 1;
num_of_transferred_bits_y <= bits;
state <= TRANSFER;
end
TRANSFER :
begin
transfer_en_y <= 0;
tx_pull_y <= 0;
if(bit_counter_y == num_of_transferred_bits_y)
state <= TRANSFER_DONE;
end
TRANSFER_DONE :
begin
clock_en_y <= 0;
rx_push_y <= 1;
if(!tx_empty_i)
begin
state <= LOAD;
end
else
begin
trans_done_y <= 1;
state <= IDLE;
end
end
endcase
end
always @(posedge clk_i,negedge reset_n_i)
begin
if (!reset_n_i)
bit_counter_y <= 0;
else if(transfer_en_y || rx_push_y )
bit_counter_y <= 0;
else if(state == TRANSFER && !cpha_y && shift_ce_y)
bit_counter_y <= bit_counter_y+1 ;
else if(state == TRANSFER && cpha_y && samp_ce_y)
bit_counter_y <= bit_counter_y+1;
else
bit_counter_y <= bit_counter_y;
end;
reg [7:0] fifo0,fifo1,fifo2,fifo3;
always@(posedge clk_i,negedge reset_n_i)
begin
if(!reset_n_i)
begin
fifo0 <= 0;
fifo1 <= 0;
fifo2 <= 0;
fifo3 <= 0;
end
else if(tx_pull_y)
begin
fifo0 <= tx_data_i[7:0];
fifo1 <= tx_data_i[15:8];
fifo2 <= tx_data_i[23:16];
fifo3 <= tx_data_i[31:24];
end
else if(ss_y)
begin
if(samp_ce_y)
begin
if(!msb_first)
begin
fifo0 <= {fifo1[0],fifo0[7:1]};
fifo1 <= {fifo2[0],fifo1[7:1]};
fifo2 <= {fifo3[0],fifo2[7:1]};
fifo3 <= {spi_miso_i,fifo3[7:1]};
end
else
begin
fifo0 <= {fifo0[6:0],spi_miso_i};
fifo1 <= {fifo1[6:0],fifo0[7]};
fifo2 <= {fifo2[6:0],fifo1[7]};
fifo3 <= {fifo3[6:0],fifo2[7]};
end
end
end
end
reg data_valid_y;
always@(posedge clk_i,negedge reset_n_i)
begin
if(!reset_n_i)
data_valid_y<=0;
else
data_valid_y<= tx_pull_y;
end
wire en;
assign en = (data_valid_y && !cpha_y) ? 1'b1 : 1'b0;
reg mosi_y;
reg [31:0] rx_data_y;
always@(posedge clk_i,negedge reset_n_i)
begin
if(!reset_n_i || !ss_y)
mosi_y <= 1'b0;
else if(shift_ce_y || (en))
begin
if(!msb_first)
mosi_y <= fifo0[0];
else
begin
case(num_of_transferred_bits_y)
6'd8 : mosi_y <= fifo0[7];
6'd16 : mosi_y <= fifo1[7];
6'd32 : mosi_y <= fifo3[7];
endcase
end
end
end
initial rx_data_y = 0;
always@(*)
begin
if(!msb_first)
begin
case(num_of_transferred_bits_y)
6'd8 : rx_data_y <= {24'd0,fifo3};
6'd16 : rx_data_y <= {16'd0,fifo3,fifo2};
6'd32 : rx_data_y <= {fifo3,fifo2,fifo1,fifo0};
endcase
end
else
begin
case(num_of_transferred_bits_y)
6'd8 : rx_data_y <= {24'd0,fifo0};
6'd16 : rx_data_y <= {16'd0,fifo1,fifo0};
6'd32 : rx_data_y <= {fifo3,fifo2,fifo1,fifo0};
endcase
end
end
reg [31:0] rx_data;
always@(posedge clk_i,negedge reset_n_i)
begin
if(!reset_n_i)
rx_data <= 0;
else
rx_data <= rx_data_y;
end
wire [3:0] ss_n = reg_trans_ctrl_i[3:0];
assign tx_pull_o = tx_pull_y;
assign trans_done_o = trans_done_y;
assign rx_data_o = rx_data;
assign rx_push_o = rx_push_y;
assign spi_ssel_o = (ss_y) ? ~(ss_y) : 4'hF;
assign spi_sck_o = (cpol_y) ? ~spi_sclk_y : spi_sclk_y;
assign spi_mosi_o = (ss_y) ? mosi_y : 1'bz;
endmodule | 3 |
139,223 | data/full_repos/permissive/870676/rtl/ver1/rtl/BIOSROM.v | 870,676 | BIOSROM.v | v | 37 | 77 | [] | [] | [] | [(9, 34)] | null | data/verilator_xmls/06b782f4-f06a-484e-8b2e-cb40a96706f7.xml | null | 304,486 | module | module BIOSROM(
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [19:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input wb_stb_i,
input wb_cyc_i,
input [ 1:0] wb_sel_i,
output reg wb_ack_o
);
wire ack_o = wb_stb_i & wb_cyc_i;
always @(posedge wb_clk_i) wb_ack_o <= ack_o;
reg [15:0] rom[0:127];
initial $readmemh("biosrom.hex", rom);
wire [ 6:0] rom_addr = wb_adr_i[7:1];
wire [15:0] rom_dat = rom[rom_addr];
assign wb_dat_o = rom_dat;
endmodule | module BIOSROM(
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [19:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input wb_stb_i,
input wb_cyc_i,
input [ 1:0] wb_sel_i,
output reg wb_ack_o
); |
wire ack_o = wb_stb_i & wb_cyc_i;
always @(posedge wb_clk_i) wb_ack_o <= ack_o;
reg [15:0] rom[0:127];
initial $readmemh("biosrom.hex", rom);
wire [ 6:0] rom_addr = wb_adr_i[7:1];
wire [15:0] rom_dat = rom[rom_addr];
assign wb_dat_o = rom_dat;
endmodule | 15 |
139,226 | data/full_repos/permissive/870676/rtl/ver1/rtl/gpio.v | 870,676 | gpio.v | v | 35 | 84 | [] | [] | [] | [(7, 33)] | null | data/verilator_xmls/1aa8bc5a-4988-44bf-a8d2-22b7274f09ac.xml | null | 304,490 | module | module gpio (
input wb_clk_i,
input wb_rst_i,
input wb_adr_i,
output [15:0] wb_dat_o,
input [15:0] wb_dat_i,
input [ 1:0] wb_sel_i,
input wb_we_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
output reg [7:0] leds_,
input [7:0] sw_
);
wire op;
assign op = wb_cyc_i & wb_stb_i;
assign wb_ack_o = op;
assign wb_dat_o = wb_adr_i ? { 8'h00, leds_ } : { 8'h00, sw_ };
always @(posedge wb_clk_i)
leds_ <= wb_rst_i ? 8'h0 : ((op & wb_we_i & wb_adr_i) ? wb_dat_i[7:0] : leds_);
endmodule | module gpio (
input wb_clk_i,
input wb_rst_i,
input wb_adr_i,
output [15:0] wb_dat_o,
input [15:0] wb_dat_i,
input [ 1:0] wb_sel_i,
input wb_we_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
output reg [7:0] leds_,
input [7:0] sw_
); |
wire op;
assign op = wb_cyc_i & wb_stb_i;
assign wb_ack_o = op;
assign wb_dat_o = wb_adr_i ? { 8'h00, leds_ } : { 8'h00, sw_ };
always @(posedge wb_clk_i)
leds_ <= wb_rst_i ? 8'h0 : ((op & wb_we_i & wb_adr_i) ? wb_dat_i[7:0] : leds_);
endmodule | 15 |
139,247 | data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v | 870,676 | zbc.v | v | 874 | 119 | [] | [] | [] | [(7, 872)] | null | null | 1: b"%Error: data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v:83: Cannot find file containing module: 'pll'\n pll pll1(\n ^~~\n ... Looked in:\n data/full_repos/permissive/870676/rtl/ver1/rtl,data/full_repos/permissive/870676/pll\n data/full_repos/permissive/870676/rtl/ver1/rtl,data/full_repos/permissive/870676/pll.v\n data/full_repos/permissive/870676/rtl/ver1/rtl,data/full_repos/permissive/870676/pll.sv\n pll\n pll.v\n pll.sv\n obj_dir/pll\n obj_dir/pll.v\n obj_dir/pll.sv\n%Error: data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v:129: Cannot find file containing module: 'BIOSROM'\n BIOSROM bios( \n ^~~~~~~\n%Error: data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v:155: Cannot find file containing module: 'wb_abrgr'\n wb_abrgr wb_fmlbrg ( \n ^~~~~~~~\n%Error: data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v:191: Cannot find file containing module: 'fmlbrg'\n fmlbrg #(.fml_depth(23), .cache_depth (10)) \n ^~~~~~\n%Error: data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v:225: Cannot find file containing module: 'wb_abrgr'\n wb_abrgr wb_csrbrg ( \n ^~~~~~~~\n%Error: data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v:259: Cannot find file containing module: 'csrbrg'\n csrbrg csrbrg ( \n ^~~~~~\n%Error: data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v:287: Cannot find file containing module: 'hpdmc'\n hpdmc #(.csr_addr(1'b0),.sdram_depth(23),.sdram_columndepth(8)) hpdmc (\n ^~~~~\n%Error: data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v:324: Cannot find file containing module: 'wb_abrg'\n wb_abrg vga_brg ( \n ^~~~~~~\n%Error: data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v:363: Cannot find file containing module: 'vdu'\n vdu vga ( \n ^~~\n%Error: data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v:394: Cannot find file containing module: 'WB_Ethernet'\n WB_Ethernet Ethernet( \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v:425: Cannot find file containing module: 'sound'\n sound snd1( \n ^~~~~\n%Error: data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v:454: Cannot find file containing module: 'WB_Serial'\n WB_Serial uart1( \n ^~~~~~~~~\n%Error: data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v:483: Cannot find file containing module: 'WB_SPI_Flash'\n WB_SPI_Flash SPI_Flash( \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v:513: Cannot find file containing module: 'WB_PS2'\n WB_PS2 PS2( \n ^~~~~~\n%Error: data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v:534: Cannot find file containing module: 'timer'\n timer #(.res(33), .phase (12507)) timer0 (\n ^~~~~\n%Error: data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v:558: Cannot find file containing module: 'simple_pic'\n simple_pic pic0 ( \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v:577: Cannot find file containing module: 'wb_abrgr'\n wb_abrgr sd_brg ( \n ^~~~~~~~\n%Error: data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v:609: Cannot find file containing module: 'sdspi'\n sdspi sdspi ( \n ^~~~~\n%Error: data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v:639: Cannot find file containing module: 'gpio'\n gpio gpio1 (\n ^~~~\n%Error: data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v:661: Cannot find file containing module: 'cpu'\n cpu proc (\n ^~~\n%Error: data/full_repos/permissive/870676/rtl/ver1/rtl/zbc.v:712: Cannot find file containing module: 'wb_switch'\n wb_switch #(\n ^~~~~~~~~\n%Error: Exiting due to 21 error(s)\n" | 304,506 | module | module zbc (
input clk_50_,
input reset_,
output [1:0] GPIO_Out_,
input [1:0] GPIO_In_,
input [3:0] GamePort_In_,
input [1:0] MCU_In_,
output speaker_L,
output speaker_R,
output [11:0] sdram_addr_,
inout [15:0] sdram_data_,
output [ 1:0] sdram_ba_,
output sdram_ras_n_,
output sdram_cas_n_,
output sdram_ce_,
output sdram_clk_,
output sdram_we_n_,
output sdram_cs_n_,
output [ 3:0] vga_lcd_r_,
output [ 3:0] vga_lcd_g_,
output [ 3:0] vga_lcd_b_,
output vga_lcd_hsync_,
output vga_lcd_vsync_,
input uart_rxd_,
output uart_txd_,
input Ethernet_rx_,
output Ethernet_tx_,
inout ps2_kclk_,
inout ps2_kdat_,
inout ps2_mclk_,
inout ps2_mdat_,
output sd_sclk_,
input sd_miso_,
output sd_mosi_,
output sd_ss_,
output spi_sclk_,
input spi_miso_,
output spi_mosi_,
output spi_sels_,
output spi_mcus_
);
wire [15:0] sw_dat_o;
wire [15:0] dat_o;
wire [15:0] dat_i;
wire [19:1] adr;
wire [ 1:0] sel;
wire we;
wire tga;
wire stb;
wire cyc;
wire ack;
wire def_cyc_i;
wire def_stb_i;
wire clk12;
wire clk20;
wire clk25;
wire clk40;
wire clk100;
wire lock;
pll pll1(
.inclk0 ( clk_50_ ),
.c0 ( clk100 ),
.c1 ( clk25 ),
.c2 ( clk12 ),
.c3 ( clk40 ),
.c4 ( clk20 ),
.locked ( lock )
);
wire clk = clk12;
wire vga_clk = clk25;
wire sdram_clk = clk100;
wire rst_lck;
assign rst_lck = reset_ & lock;
reg [16:0] rst_debounce;
`ifndef SIMULATION
initial rst_debounce <= 17'h1FFFF;
reg rst;
initial rst <= 1'b1;
always @(posedge clk) begin
if(~rst_lck) rst_debounce <= 17'h1FFFF;
else if(rst_debounce != 17'd0) rst_debounce <= rst_debounce - 17'd1;
rst <= rst_debounce != 17'd0;
end
`else
wire rst;
assign rst = !rst_lck;
`endif
wire [15:0] rom_dat_o;
wire [15:0] rom_dat_i;
wire rom_tga_i;
wire [19:1] rom_adr_i;
wire [ 1:0] rom_sel_i;
wire rom_we_i;
wire rom_cyc_i;
wire rom_stb_i;
wire rom_ack_o;
BIOSROM bios(
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (rom_dat_i),
.wb_dat_o (rom_dat_o),
.wb_adr_i (rom_adr_i),
.wb_we_i (rom_we_i),
.wb_tga_i (rom_tga_i),
.wb_stb_i (rom_stb_i),
.wb_cyc_i (rom_cyc_i),
.wb_sel_i (rom_sel_i),
.wb_ack_o (rom_ack_o)
);
wire [19:1] fmlbrg_adr_s;
wire [15:0] fmlbrg_dat_w_s;
wire [15:0] fmlbrg_dat_r_s;
wire [ 1:0] fmlbrg_sel_s;
wire fmlbrg_cyc_s;
wire fmlbrg_stb_s;
wire fmlbrg_tga_s;
wire fmlbrg_we_s;
wire fmlbrg_ack_s;
wb_abrgr wb_fmlbrg (
.sys_rst (rst),
.wbs_clk_i (clk),
.wbs_adr_i (fmlbrg_adr_s),
.wbs_dat_i (fmlbrg_dat_w_s),
.wbs_dat_o (fmlbrg_dat_r_s),
.wbs_sel_i (fmlbrg_sel_s),
.wbs_tga_i (fmlbrg_tga_s),
.wbs_stb_i (fmlbrg_stb_s),
.wbs_cyc_i (fmlbrg_cyc_s),
.wbs_we_i (fmlbrg_we_s),
.wbs_ack_o (fmlbrg_ack_s),
.wbm_clk_i (sdram_clk),
.wbm_adr_o (fmlbrg_adr),
.wbm_dat_o (fmlbrg_dat_w),
.wbm_dat_i (fmlbrg_dat_r),
.wbm_sel_o (fmlbrg_sel),
.wbm_tga_o (fmlbrg_tga),
.wbm_stb_o (fmlbrg_stb),
.wbm_cyc_o (fmlbrg_cyc),
.wbm_we_o (fmlbrg_we),
.wbm_ack_i (fmlbrg_ack)
);
wire [19:1] fmlbrg_adr;
wire [15:0] fmlbrg_dat_w;
wire [15:0] fmlbrg_dat_r;
wire [ 1:0] fmlbrg_sel;
wire fmlbrg_cyc;
wire fmlbrg_stb;
wire fmlbrg_tga;
wire fmlbrg_we;
wire fmlbrg_ack;
fmlbrg #(.fml_depth(23), .cache_depth (10))
fmlbrg (
.sys_clk (sdram_clk),
.sys_rst (rst),
.wb_adr_i ({3'b000,fmlbrg_adr}),
.wb_dat_i (fmlbrg_dat_w),
.wb_dat_o (fmlbrg_dat_r),
.wb_sel_i (fmlbrg_sel),
.wb_cyc_i (fmlbrg_cyc),
.wb_stb_i (fmlbrg_stb),
.wb_tga_i (fmlbrg_tga),
.wb_we_i (fmlbrg_we),
.wb_ack_o (fmlbrg_ack),
.fml_adr (fml_adr),
.fml_stb (fml_stb),
.fml_we (fml_we),
.fml_ack (fml_ack),
.fml_sel (fml_sel),
.fml_do (fml_do),
.fml_di (fml_di)
);
wire [19:1] csrbrg_adr_s;
wire [15:0] csrbrg_dat_w_s;
wire [15:0] csrbrg_dat_r_s;
wire [ 1:0] csrbrg_sel_s;
wire csrbrg_cyc_s;
wire csrbrg_stb_s;
wire csrbrg_tga_s;
wire csrbrg_we_s;
wire csrbrg_ack_s;
wb_abrgr wb_csrbrg (
.sys_rst (rst),
.wbs_clk_i (clk),
.wbs_adr_i (csrbrg_adr_s),
.wbs_dat_i (csrbrg_dat_w_s),
.wbs_dat_o (csrbrg_dat_r_s),
.wbs_stb_i (csrbrg_stb_s),
.wbs_cyc_i (csrbrg_cyc_s),
.wbs_we_i (csrbrg_we_s),
.wbs_ack_o (csrbrg_ack_s),
.wbm_clk_i (sdram_clk),
.wbm_adr_o (csrbrg_adr),
.wbm_dat_o (csrbrg_dat_w),
.wbm_dat_i (csrbrg_dat_r),
.wbm_stb_o (csrbrg_stb),
.wbm_cyc_o (csrbrg_cyc),
.wbm_we_o (csrbrg_we),
.wbm_ack_i (csrbrg_ack)
);
wire [19:1] csrbrg_adr;
wire [15:0] csrbrg_dat_w;
wire [15:0] csrbrg_dat_r;
wire csrbrg_cyc;
wire csrbrg_stb;
wire csrbrg_we;
wire csrbrg_ack;
wire [ 2:0] csr_a;
wire csr_we;
wire [15:0] csr_dw;
wire [15:0] csr_dr_hpdmc;
csrbrg csrbrg (
.sys_clk (sdram_clk),
.sys_rst (rst),
.wb_adr_i (csrbrg_adr[3:1]),
.wb_dat_i (csrbrg_dat_w),
.wb_dat_o (csrbrg_dat_r),
.wb_cyc_i (csrbrg_cyc),
.wb_stb_i (csrbrg_stb),
.wb_we_i (csrbrg_we),
.wb_ack_o (csrbrg_ack),
.csr_a (csr_a),
.csr_we (csr_we),
.csr_do (csr_dw),
.csr_di (csr_dr_hpdmc)
);
assign sdram_clk_ = sdram_clk;
wire [ 1:0] sdram_dqm_;
wire [22:0] fml_adr;
wire fml_stb;
wire fml_we;
wire fml_ack;
wire [ 1:0] fml_sel;
wire [15:0] fml_di;
wire [15:0] fml_do;
hpdmc #(.csr_addr(1'b0),.sdram_depth(23),.sdram_columndepth(8)) hpdmc (
.sys_clk (sdram_clk),
.sys_rst (rst),
.csr_a (csr_a),
.csr_we (csr_we),
.csr_di (csr_dw),
.csr_do (csr_dr_hpdmc),
.fml_adr (fml_adr),
.fml_stb (fml_stb),
.fml_we (fml_we),
.fml_ack (fml_ack),
.fml_sel (fml_sel),
.fml_di (fml_do),
.fml_do (fml_di),
.sdram_cke (sdram_ce_),
.sdram_cs_n (sdram_cs_n_),
.sdram_we_n (sdram_we_n_),
.sdram_cas_n (sdram_cas_n_),
.sdram_ras_n (sdram_ras_n_),
.sdram_dqm (sdram_dqm_),
.sdram_adr (sdram_addr_),
.sdram_ba (sdram_ba_),
.sdram_dq (sdram_data_)
);
wire [15:0] vga_dat_o_s;
wire [15:0] vga_dat_i_s;
wire vga_tga_i_s;
wire [19:1] vga_adr_i_s;
wire [ 1:0] vga_sel_i_s;
wire vga_we_i_s;
wire vga_cyc_i_s;
wire vga_stb_i_s;
wire vga_ack_o_s;
wb_abrg vga_brg (
.sys_rst (rst),
.wbs_clk_i (clk),
.wbs_adr_i (vga_adr_i_s),
.wbs_dat_i (vga_dat_i_s),
.wbs_dat_o (vga_dat_o_s),
.wbs_sel_i (vga_sel_i_s),
.wbs_tga_i (vga_tga_i_s),
.wbs_stb_i (vga_stb_i_s),
.wbs_cyc_i (vga_cyc_i_s),
.wbs_we_i (vga_we_i_s),
.wbs_ack_o (vga_ack_o_s),
.wbm_clk_i (vga_clk),
.wbm_adr_o (vga_adr_i),
.wbm_dat_o (vga_dat_i),
.wbm_dat_i (vga_dat_o),
.wbm_sel_o (vga_sel_i),
.wbm_tga_o (vga_tga_i),
.wbm_stb_o (vga_stb_i),
.wbm_cyc_o (vga_cyc_i),
.wbm_we_o (vga_we_i),
.wbm_ack_i (vga_ack_o)
);
wire [15:0] vga_dat_o;
wire [15:0] vga_dat_i;
wire vga_tga_i;
wire [19:1] vga_adr_i;
wire [ 1:0] vga_sel_i;
wire vga_we_i;
wire vga_cyc_i;
wire vga_stb_i;
wire vga_ack_o;
assign vga_lcd_r_[1:0] = vga_lcd_r_[3:2];
assign vga_lcd_g_[1:0] = vga_lcd_g_[3:2];
assign vga_lcd_b_[1:0] = vga_lcd_b_[3:2];
vdu vga (
.wb_rst_i (rst),
.wb_clk_i (vga_clk),
.wb_dat_i (vga_dat_i),
.wb_dat_o (vga_dat_o),
.wb_adr_i (vga_adr_i),
.wb_we_i (vga_we_i),
.wb_tga_i (vga_tga_i),
.wb_sel_i (vga_sel_i),
.wb_stb_i (vga_stb_i),
.wb_cyc_i (vga_cyc_i),
.wb_ack_o (vga_ack_o),
.vga_red_o (vga_lcd_r_[3:2]),
.vga_green_o (vga_lcd_g_[3:2]),
.vga_blue_o (vga_lcd_b_[3:2]),
.horiz_sync (vga_lcd_hsync_),
.vert_sync (vga_lcd_vsync_)
);
wire [15:0] wb_net_dat_o;
wire [15:0] wb_net_dat_i;
wire wb_net_tga_i;
wire [ 2:1] wb_net_adr_i;
wire [ 1:0] wb_net_sel_i;
wire wb_net_we_i;
wire wb_net_cyc_i;
wire wb_net_stb_i;
wire wb_net_ack_o;
WB_Ethernet Ethernet(
.wb_clk_i(clk),
.wb_rst_i(rst),
.wb_dat_i(wb_net_dat_i),
.wb_dat_o(wb_net_dat_o),
.wb_cyc_i(wb_net_cyc_i),
.wb_stb_i(wb_net_stb_i),
.wb_adr_i(wb_net_adr_i),
.wb_sel_i(wb_net_sel_i),
.wb_we_i(wb_net_we_i),
.wb_ack_o(wb_net_ack_o),
.wb_tgc_o(intv[7]),
.clk20(clk20),
.clk40(clk40),
.Ethernet_Rx(Ethernet_rx_),
.Ethernet_Tx(Ethernet_tx_)
);
wire [19:1] wb_sb_adr_i;
wire [15:0] wb_sb_dat_i;
wire [15:0] wb_sb_dat_o;
wire [ 1:0] wb_sb_sel_i;
wire wb_sb_cyc_i;
wire wb_sb_stb_i;
wire wb_sb_we_i;
wire wb_sb_ack_o;
wire wb_sb_tga_i;
sound snd1(
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (wb_sb_dat_i),
.wb_dat_o (wb_sb_dat_o),
.wb_cyc_i (wb_sb_cyc_i),
.wb_stb_i (wb_sb_stb_i),
.wb_adr_i (wb_sb_adr_i[3:1]),
.wb_sel_i (wb_sb_sel_i),
.wb_we_i (wb_sb_we_i),
.wb_ack_o (wb_sb_ack_o),
.dac_clk(clk_50_),
.audio_L(speaker_L),
.audio_R(speaker_R)
);
wire [15:0] uart_dat_o;
wire [15:0] uart_dat_i;
wire uart_tga_i;
wire [19:1] uart_adr_i;
wire [ 1:0] uart_sel_i;
wire uart_we_i;
wire uart_cyc_i;
wire uart_stb_i;
wire uart_ack_o;
WB_Serial uart1(
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_adr_i (uart_adr_i[2:1]),
.wb_sel_i (uart_sel_i),
.wb_dat_i (uart_dat_i),
.wb_dat_o (uart_dat_o),
.wb_we_i (uart_we_i),
.wb_stb_i (uart_stb_i),
.wb_cyc_i (uart_cyc_i),
.wb_ack_o (uart_ack_o),
.wb_tgc_o (intv[4]),
.rs232_tx (uart_txd_),
.rs232_rx (uart_rxd_)
);
wire [15:0] wb_spi_dat_o;
wire [15:0] wb_spi_dat_i;
wire [ 1:0] wb_spi_sel_i;
wire [19:1] wb_spi_adr_i;
wire wb_spi_tga_i;
wire wb_spi_we_i;
wire wb_spi_cyc_i;
wire wb_spi_stb_i;
wire wb_spi_ack_o;
WB_SPI_Flash SPI_Flash(
.wb_clk_i(clk),
.wb_rst_i(rst),
.wb_dat_i(wb_spi_dat_i),
.wb_dat_o(wb_spi_dat_o[7:0]),
.wb_cyc_i(wb_spi_cyc_i),
.wb_stb_i(wb_spi_stb_i),
.wb_sel_i(wb_spi_sel_i),
.wb_we_i(wb_spi_we_i),
.wb_ack_o(wb_spi_ack_o),
.sclk(spi_sclk_),
.miso(spi_miso_),
.mosi(spi_mosi_),
.sels(spi_sels_),
.mcus(spi_mcus_)
);
wire [15:0] keyb_dat_o;
wire [15:0] keyb_dat_i;
wire keyb_tga_i;
wire [19:1] keyb_adr_i;
wire [ 1:0] keyb_sel_i;
wire keyb_we_i;
wire keyb_cyc_i;
wire keyb_stb_i;
wire keyb_ack_o;
WB_PS2 PS2(
.wb_clk_i(clk),
.wb_rst_i(rst),
.wb_adr_i(keyb_adr_i[2:1]),
.wb_sel_i(keyb_sel_i),
.wb_dat_i(keyb_dat_i),
.wb_dat_o(keyb_dat_o),
.wb_we_i(keyb_we_i),
.wb_stb_i(keyb_stb_i),
.wb_cyc_i(keyb_cyc_i),
.wb_ack_o(keyb_ack_o),
.wb_tgk_o(intv[1]),
.wb_tgm_o(intv[3]),
.PS2_KBD_CLK(ps2_kclk_),.PS2_KBD_DAT(ps2_kdat_),
.PS2_MSE_CLK(ps2_mclk_),.PS2_MSE_DAT(ps2_mdat_)
);
timer #(.res(33), .phase (12507)) timer0 (
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_tgc_o (intv[0])
);
wire [ 7:0] intv;
wire [ 2:0] iid;
wire intr;
wire inta;
simple_pic pic0 (
.clk (clk),
.rst (rst),
.intv (intv),
.inta (inta),
.intr (intr),
.iid (iid)
);
wire [15:0] sd_dat_o;
wire [15:0] sd_dat_i;
wire [ 1:0] sd_sel_i;
wire sd_we_i;
wire sd_cyc_i;
wire sd_stb_i;
wire sd_ack_o;
wb_abrgr sd_brg (
.sys_rst (rst),
.wbs_clk_i (clk),
.wbs_dat_i (sd_dat_i_s),
.wbs_dat_o (sd_dat_o_s),
.wbs_sel_i (sd_sel_i_s),
.wbs_stb_i (sd_stb_i_s),
.wbs_cyc_i (sd_cyc_i_s),
.wbs_we_i (sd_we_i_s),
.wbs_ack_o (sd_ack_o_s),
.wbm_clk_i (sdram_clk),
.wbm_dat_o (sd_dat_i),
.wbm_dat_i (sd_dat_o),
.wbm_sel_o (sd_sel_i),
.wbm_stb_o (sd_stb_i),
.wbm_cyc_o (sd_cyc_i),
.wbm_we_o (sd_we_i),
.wbm_ack_i (sd_ack_o)
);
wire [19:1] sd_adr_i_s;
wire [15:0] sd_dat_o_s;
wire [15:0] sd_dat_i_s;
wire sd_tga_i_s;
wire [ 1:0] sd_sel_i_s;
wire sd_we_i_s;
wire sd_cyc_i_s;
wire sd_stb_i_s;
wire sd_ack_o_s;
sdspi sdspi (
.sclk (sd_sclk_),
.miso (sd_miso_),
.mosi (sd_mosi_),
.ss (sd_ss_),
.wb_clk_i (sdram_clk),
.wb_rst_i (rst),
.wb_dat_i (sd_dat_i),
.wb_dat_o (sd_dat_o),
.wb_we_i (sd_we_i),
.wb_sel_i (sd_sel_i),
.wb_stb_i (sd_stb_i),
.wb_cyc_i (sd_cyc_i),
.wb_ack_o (sd_ack_o)
);
wire [15:0] gpio_dat_o;
wire [15:0] gpio_dat_i;
wire gpio_tga_i;
wire [19:1] gpio_adr_i;
wire [ 1:0] gpio_sel_i;
wire gpio_we_i;
wire gpio_cyc_i;
wire gpio_stb_i;
wire gpio_ack_o;
wire [7:0] GPIO_Output;
assign GPIO_Out_ = GPIO_Output[1:0];
gpio gpio1 (
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_adr_i (gpio_adr_i),
.wb_dat_o (gpio_dat_o),
.wb_dat_i (gpio_dat_i),
.wb_sel_i (gpio_sel_i),
.wb_we_i (gpio_we_i),
.wb_stb_i (gpio_stb_i),
.wb_cyc_i (gpio_cyc_i),
.wb_ack_o (gpio_ack_o),
.leds_ (GPIO_Output),
.sw_ ({GamePort_In_,GPIO_In_,MCU_In_})
);
wire [15:0] ip;
wire [15:0] cs;
wire [ 2:0] state;
cpu proc (
.ip (ip),
.cs (cs),
.state (state),
.dbg_block (1'b0),
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_i),
.wb_dat_o (dat_o),
.wb_adr_o (adr),
.wb_we_o (we),
.wb_tga_o (tga),
.wb_sel_o (sel),
.wb_stb_o (stb),
.wb_cyc_o (cyc),
.wb_ack_i (ack),
.wb_tgc_i (intr),
.wb_tgc_o (inta)
);
assign dat_i = inta ? { 13'b0000_0000_0000_1, iid } : sw_dat_o;
wb_switch #(
.s0_addr_1 (20'b0_1111_1111_1111_0000_000),
.s0_mask_1 (20'b1_1111_1111_1111_0000_000),
.s1_addr_1 (20'b0_1011_1000_0000_0000_000),
.s1_mask_1 (20'b1_1111_1000_0000_0000_000),
.s1_addr_2 (20'b1_0000_0000_0011_1100_000),
.s1_mask_2 (20'b1_0000_1111_1111_1110_000),
.s2_addr_1 (20'b1_0000_0000_0011_1111_100),
.s2_mask_1 (20'b1_0000_1111_1111_1111_100),
.s3_addr_1 (20'b1_0000_0000_0000_0110_000),
.s3_mask_1 (20'b1_0000_1111_1111_1111_101),
.s4_addr_1 (20'b1_0000_0000_0001_0000_000),
.s4_mask_1 (20'b1_0000_1111_1111_1111_111),
.s5_addr_1 (20'b1_0000_1111_0001_0000_000),
.s5_mask_1 (20'b1_0000_1111_1111_1111_110),
.s6_addr_1 (20'b1_0000_1111_0010_0000_000),
.s6_mask_1 (20'b1_0000_1111_1111_1111_000),
.s7_addr_1 (20'b1_0000_0000_0010_0011_100),
.s7_mask_1 (20'b1_0000_1111_1111_1111_100),
.s8_addr_1 (20'b1_0000_0000_0011_0110_000),
.s8_mask_1 (20'b1_0000_1111_1111_1111_100),
.s9_addr_1 (20'b1_0000_0000_0010_0001_000),
.s9_mask_1 (20'b1_0000_1111_1111_1111_000),
.sA_addr_1 (20'b1_0000_1111_0011_0000_000),
.sA_mask_1 (20'b1_0000_1111_1111_0000_000),
.sA_addr_2 (20'b0_0000_0000_0000_0000_000),
.sA_mask_2 (20'b1_0000_0000_0000_0000_000)
)
wbs (
.m_dat_i (dat_o),
.m_dat_o (sw_dat_o),
.m_adr_i ({tga,adr}),
.m_sel_i (sel),
.m_we_i (we),
.m_cyc_i (cyc),
.m_stb_i (stb),
.m_ack_o (ack),
.s0_dat_i (rom_dat_o),
.s0_dat_o (rom_dat_i),
.s0_adr_o ({rom_tga_i,rom_adr_i}),
.s0_sel_o (rom_sel_i),
.s0_we_o (rom_we_i),
.s0_cyc_o (rom_cyc_i),
.s0_stb_o (rom_stb_i),
.s0_ack_i (rom_ack_o),
.s1_dat_i (vga_dat_o_s),
.s1_dat_o (vga_dat_i_s),
.s1_adr_o ({vga_tga_i_s,vga_adr_i_s}),
.s1_sel_o (vga_sel_i_s),
.s1_we_o (vga_we_i_s),
.s1_cyc_o (vga_cyc_i_s),
.s1_stb_o (vga_stb_i_s),
.s1_ack_i (vga_ack_o_s),
.s2_dat_i (uart_dat_o),
.s2_dat_o (uart_dat_i),
.s2_adr_o ({uart_tga_i,uart_adr_i}),
.s2_sel_o (uart_sel_i),
.s2_we_o (uart_we_i),
.s2_cyc_o (uart_cyc_i),
.s2_stb_o (uart_stb_i),
.s2_ack_i (uart_ack_o),
.s3_dat_i (keyb_dat_o),
.s3_dat_o (keyb_dat_i),
.s3_adr_o ({keyb_tga_i,keyb_adr_i}),
.s3_sel_o (keyb_sel_i),
.s3_we_o (keyb_we_i),
.s3_cyc_o (keyb_cyc_i),
.s3_stb_o (keyb_stb_i),
.s3_ack_i (keyb_ack_o),
.s4_dat_i (sd_dat_o_s),
.s4_dat_o (sd_dat_i_s),
.s4_adr_o ({sd_tga_i_s,sd_adr_i_s}),
.s4_sel_o (sd_sel_i_s),
.s4_we_o (sd_we_i_s),
.s4_cyc_o (sd_cyc_i_s),
.s4_stb_o (sd_stb_i_s),
.s4_ack_i (sd_ack_o_s),
.s5_dat_i (gpio_dat_o),
.s5_dat_o (gpio_dat_i),
.s5_adr_o ({gpio_tga_i,gpio_adr_i}),
.s5_sel_o (gpio_sel_i),
.s5_we_o (gpio_we_i),
.s5_cyc_o (gpio_cyc_i),
.s5_stb_o (gpio_stb_i),
.s5_ack_i (gpio_ack_o),
.s6_dat_i (csrbrg_dat_r_s),
.s6_dat_o (csrbrg_dat_w_s),
.s6_adr_o ({csrbrg_tga_s,csrbrg_adr_s}),
.s6_sel_o (csrbrg_sel_s),
.s6_we_o (csrbrg_we_s),
.s6_cyc_o (csrbrg_cyc_s),
.s6_stb_o (csrbrg_stb_s),
.s6_ack_i (csrbrg_ack_s),
.s7_dat_i (wb_spi_dat_o),
.s7_dat_o (wb_spi_dat_i),
.s7_adr_o ({wb_spi_tga_i,wb_spi_adr_i}),
.s7_sel_o (wb_spi_sel_i),
.s7_we_o (wb_spi_we_i),
.s7_cyc_o (wb_spi_cyc_i),
.s7_stb_o (wb_spi_stb_i),
.s7_ack_i (wb_spi_ack_o),
.s8_dat_i (wb_net_dat_o),
.s8_dat_o (wb_net_dat_i),
.s8_adr_o ({wb_net_tga_i,wb_net_adr_i}),
.s8_sel_o (wb_net_sel_i),
.s8_we_o (wb_net_we_i),
.s8_cyc_o (wb_net_cyc_i),
.s8_stb_o (wb_net_stb_i),
.s8_ack_i (wb_net_ack_o),
.s9_dat_i (wb_sb_dat_o),
.s9_dat_o (wb_sb_dat_i),
.s9_adr_o ({wb_sb_tga_i,wb_sb_adr_i}),
.s9_sel_o (wb_sb_sel_i),
.s9_we_o (wb_sb_we_i),
.s9_cyc_o (wb_sb_cyc_i),
.s9_stb_o (wb_sb_stb_i),
.s9_ack_i (wb_sb_ack_o),
.sA_dat_i (fmlbrg_dat_r_s),
.sA_dat_o (fmlbrg_dat_w_s),
.sA_adr_o ({fmlbrg_tga_s,fmlbrg_adr_s}),
.sA_sel_o (fmlbrg_sel_s),
.sA_we_o (fmlbrg_we_s),
.sA_cyc_o (fmlbrg_cyc_s),
.sA_stb_o (fmlbrg_stb_s),
.sA_ack_i (fmlbrg_ack_s),
.sB_dat_i (16'hffff),
.sB_dat_o (),
.sB_adr_o (),
.sB_sel_o (),
.sB_we_o (),
.sB_cyc_o (def_cyc_i),
.sB_stb_o (def_stb_i),
.sB_ack_i (def_cyc_i & def_stb_i)
);
endmodule | module zbc (
input clk_50_,
input reset_,
output [1:0] GPIO_Out_,
input [1:0] GPIO_In_,
input [3:0] GamePort_In_,
input [1:0] MCU_In_,
output speaker_L,
output speaker_R,
output [11:0] sdram_addr_,
inout [15:0] sdram_data_,
output [ 1:0] sdram_ba_,
output sdram_ras_n_,
output sdram_cas_n_,
output sdram_ce_,
output sdram_clk_,
output sdram_we_n_,
output sdram_cs_n_,
output [ 3:0] vga_lcd_r_,
output [ 3:0] vga_lcd_g_,
output [ 3:0] vga_lcd_b_,
output vga_lcd_hsync_,
output vga_lcd_vsync_,
input uart_rxd_,
output uart_txd_,
input Ethernet_rx_,
output Ethernet_tx_,
inout ps2_kclk_,
inout ps2_kdat_,
inout ps2_mclk_,
inout ps2_mdat_,
output sd_sclk_,
input sd_miso_,
output sd_mosi_,
output sd_ss_,
output spi_sclk_,
input spi_miso_,
output spi_mosi_,
output spi_sels_,
output spi_mcus_
); |
wire [15:0] sw_dat_o;
wire [15:0] dat_o;
wire [15:0] dat_i;
wire [19:1] adr;
wire [ 1:0] sel;
wire we;
wire tga;
wire stb;
wire cyc;
wire ack;
wire def_cyc_i;
wire def_stb_i;
wire clk12;
wire clk20;
wire clk25;
wire clk40;
wire clk100;
wire lock;
pll pll1(
.inclk0 ( clk_50_ ),
.c0 ( clk100 ),
.c1 ( clk25 ),
.c2 ( clk12 ),
.c3 ( clk40 ),
.c4 ( clk20 ),
.locked ( lock )
);
wire clk = clk12;
wire vga_clk = clk25;
wire sdram_clk = clk100;
wire rst_lck;
assign rst_lck = reset_ & lock;
reg [16:0] rst_debounce;
`ifndef SIMULATION
initial rst_debounce <= 17'h1FFFF;
reg rst;
initial rst <= 1'b1;
always @(posedge clk) begin
if(~rst_lck) rst_debounce <= 17'h1FFFF;
else if(rst_debounce != 17'd0) rst_debounce <= rst_debounce - 17'd1;
rst <= rst_debounce != 17'd0;
end
`else
wire rst;
assign rst = !rst_lck;
`endif
wire [15:0] rom_dat_o;
wire [15:0] rom_dat_i;
wire rom_tga_i;
wire [19:1] rom_adr_i;
wire [ 1:0] rom_sel_i;
wire rom_we_i;
wire rom_cyc_i;
wire rom_stb_i;
wire rom_ack_o;
BIOSROM bios(
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (rom_dat_i),
.wb_dat_o (rom_dat_o),
.wb_adr_i (rom_adr_i),
.wb_we_i (rom_we_i),
.wb_tga_i (rom_tga_i),
.wb_stb_i (rom_stb_i),
.wb_cyc_i (rom_cyc_i),
.wb_sel_i (rom_sel_i),
.wb_ack_o (rom_ack_o)
);
wire [19:1] fmlbrg_adr_s;
wire [15:0] fmlbrg_dat_w_s;
wire [15:0] fmlbrg_dat_r_s;
wire [ 1:0] fmlbrg_sel_s;
wire fmlbrg_cyc_s;
wire fmlbrg_stb_s;
wire fmlbrg_tga_s;
wire fmlbrg_we_s;
wire fmlbrg_ack_s;
wb_abrgr wb_fmlbrg (
.sys_rst (rst),
.wbs_clk_i (clk),
.wbs_adr_i (fmlbrg_adr_s),
.wbs_dat_i (fmlbrg_dat_w_s),
.wbs_dat_o (fmlbrg_dat_r_s),
.wbs_sel_i (fmlbrg_sel_s),
.wbs_tga_i (fmlbrg_tga_s),
.wbs_stb_i (fmlbrg_stb_s),
.wbs_cyc_i (fmlbrg_cyc_s),
.wbs_we_i (fmlbrg_we_s),
.wbs_ack_o (fmlbrg_ack_s),
.wbm_clk_i (sdram_clk),
.wbm_adr_o (fmlbrg_adr),
.wbm_dat_o (fmlbrg_dat_w),
.wbm_dat_i (fmlbrg_dat_r),
.wbm_sel_o (fmlbrg_sel),
.wbm_tga_o (fmlbrg_tga),
.wbm_stb_o (fmlbrg_stb),
.wbm_cyc_o (fmlbrg_cyc),
.wbm_we_o (fmlbrg_we),
.wbm_ack_i (fmlbrg_ack)
);
wire [19:1] fmlbrg_adr;
wire [15:0] fmlbrg_dat_w;
wire [15:0] fmlbrg_dat_r;
wire [ 1:0] fmlbrg_sel;
wire fmlbrg_cyc;
wire fmlbrg_stb;
wire fmlbrg_tga;
wire fmlbrg_we;
wire fmlbrg_ack;
fmlbrg #(.fml_depth(23), .cache_depth (10))
fmlbrg (
.sys_clk (sdram_clk),
.sys_rst (rst),
.wb_adr_i ({3'b000,fmlbrg_adr}),
.wb_dat_i (fmlbrg_dat_w),
.wb_dat_o (fmlbrg_dat_r),
.wb_sel_i (fmlbrg_sel),
.wb_cyc_i (fmlbrg_cyc),
.wb_stb_i (fmlbrg_stb),
.wb_tga_i (fmlbrg_tga),
.wb_we_i (fmlbrg_we),
.wb_ack_o (fmlbrg_ack),
.fml_adr (fml_adr),
.fml_stb (fml_stb),
.fml_we (fml_we),
.fml_ack (fml_ack),
.fml_sel (fml_sel),
.fml_do (fml_do),
.fml_di (fml_di)
);
wire [19:1] csrbrg_adr_s;
wire [15:0] csrbrg_dat_w_s;
wire [15:0] csrbrg_dat_r_s;
wire [ 1:0] csrbrg_sel_s;
wire csrbrg_cyc_s;
wire csrbrg_stb_s;
wire csrbrg_tga_s;
wire csrbrg_we_s;
wire csrbrg_ack_s;
wb_abrgr wb_csrbrg (
.sys_rst (rst),
.wbs_clk_i (clk),
.wbs_adr_i (csrbrg_adr_s),
.wbs_dat_i (csrbrg_dat_w_s),
.wbs_dat_o (csrbrg_dat_r_s),
.wbs_stb_i (csrbrg_stb_s),
.wbs_cyc_i (csrbrg_cyc_s),
.wbs_we_i (csrbrg_we_s),
.wbs_ack_o (csrbrg_ack_s),
.wbm_clk_i (sdram_clk),
.wbm_adr_o (csrbrg_adr),
.wbm_dat_o (csrbrg_dat_w),
.wbm_dat_i (csrbrg_dat_r),
.wbm_stb_o (csrbrg_stb),
.wbm_cyc_o (csrbrg_cyc),
.wbm_we_o (csrbrg_we),
.wbm_ack_i (csrbrg_ack)
);
wire [19:1] csrbrg_adr;
wire [15:0] csrbrg_dat_w;
wire [15:0] csrbrg_dat_r;
wire csrbrg_cyc;
wire csrbrg_stb;
wire csrbrg_we;
wire csrbrg_ack;
wire [ 2:0] csr_a;
wire csr_we;
wire [15:0] csr_dw;
wire [15:0] csr_dr_hpdmc;
csrbrg csrbrg (
.sys_clk (sdram_clk),
.sys_rst (rst),
.wb_adr_i (csrbrg_adr[3:1]),
.wb_dat_i (csrbrg_dat_w),
.wb_dat_o (csrbrg_dat_r),
.wb_cyc_i (csrbrg_cyc),
.wb_stb_i (csrbrg_stb),
.wb_we_i (csrbrg_we),
.wb_ack_o (csrbrg_ack),
.csr_a (csr_a),
.csr_we (csr_we),
.csr_do (csr_dw),
.csr_di (csr_dr_hpdmc)
);
assign sdram_clk_ = sdram_clk;
wire [ 1:0] sdram_dqm_;
wire [22:0] fml_adr;
wire fml_stb;
wire fml_we;
wire fml_ack;
wire [ 1:0] fml_sel;
wire [15:0] fml_di;
wire [15:0] fml_do;
hpdmc #(.csr_addr(1'b0),.sdram_depth(23),.sdram_columndepth(8)) hpdmc (
.sys_clk (sdram_clk),
.sys_rst (rst),
.csr_a (csr_a),
.csr_we (csr_we),
.csr_di (csr_dw),
.csr_do (csr_dr_hpdmc),
.fml_adr (fml_adr),
.fml_stb (fml_stb),
.fml_we (fml_we),
.fml_ack (fml_ack),
.fml_sel (fml_sel),
.fml_di (fml_do),
.fml_do (fml_di),
.sdram_cke (sdram_ce_),
.sdram_cs_n (sdram_cs_n_),
.sdram_we_n (sdram_we_n_),
.sdram_cas_n (sdram_cas_n_),
.sdram_ras_n (sdram_ras_n_),
.sdram_dqm (sdram_dqm_),
.sdram_adr (sdram_addr_),
.sdram_ba (sdram_ba_),
.sdram_dq (sdram_data_)
);
wire [15:0] vga_dat_o_s;
wire [15:0] vga_dat_i_s;
wire vga_tga_i_s;
wire [19:1] vga_adr_i_s;
wire [ 1:0] vga_sel_i_s;
wire vga_we_i_s;
wire vga_cyc_i_s;
wire vga_stb_i_s;
wire vga_ack_o_s;
wb_abrg vga_brg (
.sys_rst (rst),
.wbs_clk_i (clk),
.wbs_adr_i (vga_adr_i_s),
.wbs_dat_i (vga_dat_i_s),
.wbs_dat_o (vga_dat_o_s),
.wbs_sel_i (vga_sel_i_s),
.wbs_tga_i (vga_tga_i_s),
.wbs_stb_i (vga_stb_i_s),
.wbs_cyc_i (vga_cyc_i_s),
.wbs_we_i (vga_we_i_s),
.wbs_ack_o (vga_ack_o_s),
.wbm_clk_i (vga_clk),
.wbm_adr_o (vga_adr_i),
.wbm_dat_o (vga_dat_i),
.wbm_dat_i (vga_dat_o),
.wbm_sel_o (vga_sel_i),
.wbm_tga_o (vga_tga_i),
.wbm_stb_o (vga_stb_i),
.wbm_cyc_o (vga_cyc_i),
.wbm_we_o (vga_we_i),
.wbm_ack_i (vga_ack_o)
);
wire [15:0] vga_dat_o;
wire [15:0] vga_dat_i;
wire vga_tga_i;
wire [19:1] vga_adr_i;
wire [ 1:0] vga_sel_i;
wire vga_we_i;
wire vga_cyc_i;
wire vga_stb_i;
wire vga_ack_o;
assign vga_lcd_r_[1:0] = vga_lcd_r_[3:2];
assign vga_lcd_g_[1:0] = vga_lcd_g_[3:2];
assign vga_lcd_b_[1:0] = vga_lcd_b_[3:2];
vdu vga (
.wb_rst_i (rst),
.wb_clk_i (vga_clk),
.wb_dat_i (vga_dat_i),
.wb_dat_o (vga_dat_o),
.wb_adr_i (vga_adr_i),
.wb_we_i (vga_we_i),
.wb_tga_i (vga_tga_i),
.wb_sel_i (vga_sel_i),
.wb_stb_i (vga_stb_i),
.wb_cyc_i (vga_cyc_i),
.wb_ack_o (vga_ack_o),
.vga_red_o (vga_lcd_r_[3:2]),
.vga_green_o (vga_lcd_g_[3:2]),
.vga_blue_o (vga_lcd_b_[3:2]),
.horiz_sync (vga_lcd_hsync_),
.vert_sync (vga_lcd_vsync_)
);
wire [15:0] wb_net_dat_o;
wire [15:0] wb_net_dat_i;
wire wb_net_tga_i;
wire [ 2:1] wb_net_adr_i;
wire [ 1:0] wb_net_sel_i;
wire wb_net_we_i;
wire wb_net_cyc_i;
wire wb_net_stb_i;
wire wb_net_ack_o;
WB_Ethernet Ethernet(
.wb_clk_i(clk),
.wb_rst_i(rst),
.wb_dat_i(wb_net_dat_i),
.wb_dat_o(wb_net_dat_o),
.wb_cyc_i(wb_net_cyc_i),
.wb_stb_i(wb_net_stb_i),
.wb_adr_i(wb_net_adr_i),
.wb_sel_i(wb_net_sel_i),
.wb_we_i(wb_net_we_i),
.wb_ack_o(wb_net_ack_o),
.wb_tgc_o(intv[7]),
.clk20(clk20),
.clk40(clk40),
.Ethernet_Rx(Ethernet_rx_),
.Ethernet_Tx(Ethernet_tx_)
);
wire [19:1] wb_sb_adr_i;
wire [15:0] wb_sb_dat_i;
wire [15:0] wb_sb_dat_o;
wire [ 1:0] wb_sb_sel_i;
wire wb_sb_cyc_i;
wire wb_sb_stb_i;
wire wb_sb_we_i;
wire wb_sb_ack_o;
wire wb_sb_tga_i;
sound snd1(
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (wb_sb_dat_i),
.wb_dat_o (wb_sb_dat_o),
.wb_cyc_i (wb_sb_cyc_i),
.wb_stb_i (wb_sb_stb_i),
.wb_adr_i (wb_sb_adr_i[3:1]),
.wb_sel_i (wb_sb_sel_i),
.wb_we_i (wb_sb_we_i),
.wb_ack_o (wb_sb_ack_o),
.dac_clk(clk_50_),
.audio_L(speaker_L),
.audio_R(speaker_R)
);
wire [15:0] uart_dat_o;
wire [15:0] uart_dat_i;
wire uart_tga_i;
wire [19:1] uart_adr_i;
wire [ 1:0] uart_sel_i;
wire uart_we_i;
wire uart_cyc_i;
wire uart_stb_i;
wire uart_ack_o;
WB_Serial uart1(
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_adr_i (uart_adr_i[2:1]),
.wb_sel_i (uart_sel_i),
.wb_dat_i (uart_dat_i),
.wb_dat_o (uart_dat_o),
.wb_we_i (uart_we_i),
.wb_stb_i (uart_stb_i),
.wb_cyc_i (uart_cyc_i),
.wb_ack_o (uart_ack_o),
.wb_tgc_o (intv[4]),
.rs232_tx (uart_txd_),
.rs232_rx (uart_rxd_)
);
wire [15:0] wb_spi_dat_o;
wire [15:0] wb_spi_dat_i;
wire [ 1:0] wb_spi_sel_i;
wire [19:1] wb_spi_adr_i;
wire wb_spi_tga_i;
wire wb_spi_we_i;
wire wb_spi_cyc_i;
wire wb_spi_stb_i;
wire wb_spi_ack_o;
WB_SPI_Flash SPI_Flash(
.wb_clk_i(clk),
.wb_rst_i(rst),
.wb_dat_i(wb_spi_dat_i),
.wb_dat_o(wb_spi_dat_o[7:0]),
.wb_cyc_i(wb_spi_cyc_i),
.wb_stb_i(wb_spi_stb_i),
.wb_sel_i(wb_spi_sel_i),
.wb_we_i(wb_spi_we_i),
.wb_ack_o(wb_spi_ack_o),
.sclk(spi_sclk_),
.miso(spi_miso_),
.mosi(spi_mosi_),
.sels(spi_sels_),
.mcus(spi_mcus_)
);
wire [15:0] keyb_dat_o;
wire [15:0] keyb_dat_i;
wire keyb_tga_i;
wire [19:1] keyb_adr_i;
wire [ 1:0] keyb_sel_i;
wire keyb_we_i;
wire keyb_cyc_i;
wire keyb_stb_i;
wire keyb_ack_o;
WB_PS2 PS2(
.wb_clk_i(clk),
.wb_rst_i(rst),
.wb_adr_i(keyb_adr_i[2:1]),
.wb_sel_i(keyb_sel_i),
.wb_dat_i(keyb_dat_i),
.wb_dat_o(keyb_dat_o),
.wb_we_i(keyb_we_i),
.wb_stb_i(keyb_stb_i),
.wb_cyc_i(keyb_cyc_i),
.wb_ack_o(keyb_ack_o),
.wb_tgk_o(intv[1]),
.wb_tgm_o(intv[3]),
.PS2_KBD_CLK(ps2_kclk_),.PS2_KBD_DAT(ps2_kdat_),
.PS2_MSE_CLK(ps2_mclk_),.PS2_MSE_DAT(ps2_mdat_)
);
timer #(.res(33), .phase (12507)) timer0 (
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_tgc_o (intv[0])
);
wire [ 7:0] intv;
wire [ 2:0] iid;
wire intr;
wire inta;
simple_pic pic0 (
.clk (clk),
.rst (rst),
.intv (intv),
.inta (inta),
.intr (intr),
.iid (iid)
);
wire [15:0] sd_dat_o;
wire [15:0] sd_dat_i;
wire [ 1:0] sd_sel_i;
wire sd_we_i;
wire sd_cyc_i;
wire sd_stb_i;
wire sd_ack_o;
wb_abrgr sd_brg (
.sys_rst (rst),
.wbs_clk_i (clk),
.wbs_dat_i (sd_dat_i_s),
.wbs_dat_o (sd_dat_o_s),
.wbs_sel_i (sd_sel_i_s),
.wbs_stb_i (sd_stb_i_s),
.wbs_cyc_i (sd_cyc_i_s),
.wbs_we_i (sd_we_i_s),
.wbs_ack_o (sd_ack_o_s),
.wbm_clk_i (sdram_clk),
.wbm_dat_o (sd_dat_i),
.wbm_dat_i (sd_dat_o),
.wbm_sel_o (sd_sel_i),
.wbm_stb_o (sd_stb_i),
.wbm_cyc_o (sd_cyc_i),
.wbm_we_o (sd_we_i),
.wbm_ack_i (sd_ack_o)
);
wire [19:1] sd_adr_i_s;
wire [15:0] sd_dat_o_s;
wire [15:0] sd_dat_i_s;
wire sd_tga_i_s;
wire [ 1:0] sd_sel_i_s;
wire sd_we_i_s;
wire sd_cyc_i_s;
wire sd_stb_i_s;
wire sd_ack_o_s;
sdspi sdspi (
.sclk (sd_sclk_),
.miso (sd_miso_),
.mosi (sd_mosi_),
.ss (sd_ss_),
.wb_clk_i (sdram_clk),
.wb_rst_i (rst),
.wb_dat_i (sd_dat_i),
.wb_dat_o (sd_dat_o),
.wb_we_i (sd_we_i),
.wb_sel_i (sd_sel_i),
.wb_stb_i (sd_stb_i),
.wb_cyc_i (sd_cyc_i),
.wb_ack_o (sd_ack_o)
);
wire [15:0] gpio_dat_o;
wire [15:0] gpio_dat_i;
wire gpio_tga_i;
wire [19:1] gpio_adr_i;
wire [ 1:0] gpio_sel_i;
wire gpio_we_i;
wire gpio_cyc_i;
wire gpio_stb_i;
wire gpio_ack_o;
wire [7:0] GPIO_Output;
assign GPIO_Out_ = GPIO_Output[1:0];
gpio gpio1 (
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_adr_i (gpio_adr_i),
.wb_dat_o (gpio_dat_o),
.wb_dat_i (gpio_dat_i),
.wb_sel_i (gpio_sel_i),
.wb_we_i (gpio_we_i),
.wb_stb_i (gpio_stb_i),
.wb_cyc_i (gpio_cyc_i),
.wb_ack_o (gpio_ack_o),
.leds_ (GPIO_Output),
.sw_ ({GamePort_In_,GPIO_In_,MCU_In_})
);
wire [15:0] ip;
wire [15:0] cs;
wire [ 2:0] state;
cpu proc (
.ip (ip),
.cs (cs),
.state (state),
.dbg_block (1'b0),
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_i),
.wb_dat_o (dat_o),
.wb_adr_o (adr),
.wb_we_o (we),
.wb_tga_o (tga),
.wb_sel_o (sel),
.wb_stb_o (stb),
.wb_cyc_o (cyc),
.wb_ack_i (ack),
.wb_tgc_i (intr),
.wb_tgc_o (inta)
);
assign dat_i = inta ? { 13'b0000_0000_0000_1, iid } : sw_dat_o;
wb_switch #(
.s0_addr_1 (20'b0_1111_1111_1111_0000_000),
.s0_mask_1 (20'b1_1111_1111_1111_0000_000),
.s1_addr_1 (20'b0_1011_1000_0000_0000_000),
.s1_mask_1 (20'b1_1111_1000_0000_0000_000),
.s1_addr_2 (20'b1_0000_0000_0011_1100_000),
.s1_mask_2 (20'b1_0000_1111_1111_1110_000),
.s2_addr_1 (20'b1_0000_0000_0011_1111_100),
.s2_mask_1 (20'b1_0000_1111_1111_1111_100),
.s3_addr_1 (20'b1_0000_0000_0000_0110_000),
.s3_mask_1 (20'b1_0000_1111_1111_1111_101),
.s4_addr_1 (20'b1_0000_0000_0001_0000_000),
.s4_mask_1 (20'b1_0000_1111_1111_1111_111),
.s5_addr_1 (20'b1_0000_1111_0001_0000_000),
.s5_mask_1 (20'b1_0000_1111_1111_1111_110),
.s6_addr_1 (20'b1_0000_1111_0010_0000_000),
.s6_mask_1 (20'b1_0000_1111_1111_1111_000),
.s7_addr_1 (20'b1_0000_0000_0010_0011_100),
.s7_mask_1 (20'b1_0000_1111_1111_1111_100),
.s8_addr_1 (20'b1_0000_0000_0011_0110_000),
.s8_mask_1 (20'b1_0000_1111_1111_1111_100),
.s9_addr_1 (20'b1_0000_0000_0010_0001_000),
.s9_mask_1 (20'b1_0000_1111_1111_1111_000),
.sA_addr_1 (20'b1_0000_1111_0011_0000_000),
.sA_mask_1 (20'b1_0000_1111_1111_0000_000),
.sA_addr_2 (20'b0_0000_0000_0000_0000_000),
.sA_mask_2 (20'b1_0000_0000_0000_0000_000)
)
wbs (
.m_dat_i (dat_o),
.m_dat_o (sw_dat_o),
.m_adr_i ({tga,adr}),
.m_sel_i (sel),
.m_we_i (we),
.m_cyc_i (cyc),
.m_stb_i (stb),
.m_ack_o (ack),
.s0_dat_i (rom_dat_o),
.s0_dat_o (rom_dat_i),
.s0_adr_o ({rom_tga_i,rom_adr_i}),
.s0_sel_o (rom_sel_i),
.s0_we_o (rom_we_i),
.s0_cyc_o (rom_cyc_i),
.s0_stb_o (rom_stb_i),
.s0_ack_i (rom_ack_o),
.s1_dat_i (vga_dat_o_s),
.s1_dat_o (vga_dat_i_s),
.s1_adr_o ({vga_tga_i_s,vga_adr_i_s}),
.s1_sel_o (vga_sel_i_s),
.s1_we_o (vga_we_i_s),
.s1_cyc_o (vga_cyc_i_s),
.s1_stb_o (vga_stb_i_s),
.s1_ack_i (vga_ack_o_s),
.s2_dat_i (uart_dat_o),
.s2_dat_o (uart_dat_i),
.s2_adr_o ({uart_tga_i,uart_adr_i}),
.s2_sel_o (uart_sel_i),
.s2_we_o (uart_we_i),
.s2_cyc_o (uart_cyc_i),
.s2_stb_o (uart_stb_i),
.s2_ack_i (uart_ack_o),
.s3_dat_i (keyb_dat_o),
.s3_dat_o (keyb_dat_i),
.s3_adr_o ({keyb_tga_i,keyb_adr_i}),
.s3_sel_o (keyb_sel_i),
.s3_we_o (keyb_we_i),
.s3_cyc_o (keyb_cyc_i),
.s3_stb_o (keyb_stb_i),
.s3_ack_i (keyb_ack_o),
.s4_dat_i (sd_dat_o_s),
.s4_dat_o (sd_dat_i_s),
.s4_adr_o ({sd_tga_i_s,sd_adr_i_s}),
.s4_sel_o (sd_sel_i_s),
.s4_we_o (sd_we_i_s),
.s4_cyc_o (sd_cyc_i_s),
.s4_stb_o (sd_stb_i_s),
.s4_ack_i (sd_ack_o_s),
.s5_dat_i (gpio_dat_o),
.s5_dat_o (gpio_dat_i),
.s5_adr_o ({gpio_tga_i,gpio_adr_i}),
.s5_sel_o (gpio_sel_i),
.s5_we_o (gpio_we_i),
.s5_cyc_o (gpio_cyc_i),
.s5_stb_o (gpio_stb_i),
.s5_ack_i (gpio_ack_o),
.s6_dat_i (csrbrg_dat_r_s),
.s6_dat_o (csrbrg_dat_w_s),
.s6_adr_o ({csrbrg_tga_s,csrbrg_adr_s}),
.s6_sel_o (csrbrg_sel_s),
.s6_we_o (csrbrg_we_s),
.s6_cyc_o (csrbrg_cyc_s),
.s6_stb_o (csrbrg_stb_s),
.s6_ack_i (csrbrg_ack_s),
.s7_dat_i (wb_spi_dat_o),
.s7_dat_o (wb_spi_dat_i),
.s7_adr_o ({wb_spi_tga_i,wb_spi_adr_i}),
.s7_sel_o (wb_spi_sel_i),
.s7_we_o (wb_spi_we_i),
.s7_cyc_o (wb_spi_cyc_i),
.s7_stb_o (wb_spi_stb_i),
.s7_ack_i (wb_spi_ack_o),
.s8_dat_i (wb_net_dat_o),
.s8_dat_o (wb_net_dat_i),
.s8_adr_o ({wb_net_tga_i,wb_net_adr_i}),
.s8_sel_o (wb_net_sel_i),
.s8_we_o (wb_net_we_i),
.s8_cyc_o (wb_net_cyc_i),
.s8_stb_o (wb_net_stb_i),
.s8_ack_i (wb_net_ack_o),
.s9_dat_i (wb_sb_dat_o),
.s9_dat_o (wb_sb_dat_i),
.s9_adr_o ({wb_sb_tga_i,wb_sb_adr_i}),
.s9_sel_o (wb_sb_sel_i),
.s9_we_o (wb_sb_we_i),
.s9_cyc_o (wb_sb_cyc_i),
.s9_stb_o (wb_sb_stb_i),
.s9_ack_i (wb_sb_ack_o),
.sA_dat_i (fmlbrg_dat_r_s),
.sA_dat_o (fmlbrg_dat_w_s),
.sA_adr_o ({fmlbrg_tga_s,fmlbrg_adr_s}),
.sA_sel_o (fmlbrg_sel_s),
.sA_we_o (fmlbrg_we_s),
.sA_cyc_o (fmlbrg_cyc_s),
.sA_stb_o (fmlbrg_stb_s),
.sA_ack_i (fmlbrg_ack_s),
.sB_dat_i (16'hffff),
.sB_dat_o (),
.sB_adr_o (),
.sB_sel_o (),
.sB_we_o (),
.sB_cyc_o (def_cyc_i),
.sB_stb_o (def_stb_i),
.sB_ack_i (def_cyc_i & def_stb_i)
);
endmodule | 15 |
139,248 | data/full_repos/permissive/87104101/components/abs_tb.v | 87,104,101 | abs_tb.v | v | 36 | 57 | [] | [] | [] | null | line:19: before: "$" | null | 1: b'%Error: data/full_repos/permissive/87104101/components/abs_tb.v:13: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n abs_z_file = $fopen("stim/abs_z");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/abs_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #50010 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/abs_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/abs_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #0 abs_a_count = $fscanf(abs_a_file, "%d\\n", abs_a);\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,508 | module | module abs_tb;
reg clk;
reg [31:0] abs_a;
wire [31:0] abs_z;
integer abs_a_file;
integer abs_z_file;
integer abs_a_count;
integer abs_z_count;
abs abs1 (clk, abs_a, abs_z);
initial
begin
abs_z_file = $fopen("stim/abs_z");
abs_a_file = $fopen("stim/abs_a", "r");
end
initial
begin
#50010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(abs_z_file, "%d", abs_z);
#0 abs_a_count = $fscanf(abs_a_file, "%d\n", abs_a);
end
endmodule | module abs_tb; |
reg clk;
reg [31:0] abs_a;
wire [31:0] abs_z;
integer abs_a_file;
integer abs_z_file;
integer abs_a_count;
integer abs_z_count;
abs abs1 (clk, abs_a, abs_z);
initial
begin
abs_z_file = $fopen("stim/abs_z");
abs_a_file = $fopen("stim/abs_a", "r");
end
initial
begin
#50010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(abs_z_file, "%d", abs_z);
#0 abs_a_count = $fscanf(abs_a_file, "%d\n", abs_a);
end
endmodule | 56 |
139,249 | data/full_repos/permissive/87104101/components/add_tb.v | 87,104,101 | add_tb.v | v | 41 | 57 | [] | [] | [] | null | line:272: before: ";" | null | 1: b'%Error: data/full_repos/permissive/87104101/components/add_tb.v:16: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n add_z_file = $fopen("stim/add_z");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/add_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #50080 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/add_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/add_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #0 add_a_count = $fscanf(add_a_file, "%d\\n", add_a);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/add_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #0 add_b_count = $fscanf(add_b_file, "%d\\n", add_b);\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,510 | module | module add_tb;
reg clk;
reg [31:0] add_a;
reg [31:0] add_b;
wire [31:0] add_z;
integer add_a_file;
integer add_b_file;
integer add_z_file;
integer add_a_count;
integer add_b_count;
integer add_z_count;
add add1 (clk, add_a, add_b, add_z);
initial
begin
add_z_file = $fopen("stim/add_z");
add_a_file = $fopen("stim/add_a", "r");
add_b_file = $fopen("stim/add_b", "r");
end
initial
begin
#50080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(add_z_file, "%d", add_z);
#0 add_a_count = $fscanf(add_a_file, "%d\n", add_a);
#0 add_b_count = $fscanf(add_b_file, "%d\n", add_b);
end
endmodule | module add_tb; |
reg clk;
reg [31:0] add_a;
reg [31:0] add_b;
wire [31:0] add_z;
integer add_a_file;
integer add_b_file;
integer add_z_file;
integer add_a_count;
integer add_b_count;
integer add_z_count;
add add1 (clk, add_a, add_b, add_z);
initial
begin
add_z_file = $fopen("stim/add_z");
add_a_file = $fopen("stim/add_a", "r");
add_b_file = $fopen("stim/add_b", "r");
end
initial
begin
#50080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(add_z_file, "%d", add_z);
#0 add_a_count = $fscanf(add_a_file, "%d\n", add_a);
#0 add_b_count = $fscanf(add_b_file, "%d\n", add_b);
end
endmodule | 56 |
139,251 | data/full_repos/permissive/87104101/components/div_tb.v | 87,104,101 | div_tb.v | v | 41 | 57 | [] | [] | [] | null | line:23: before: "$" | null | 1: b'%Error: data/full_repos/permissive/87104101/components/div_tb.v:16: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n div_z_file = $fopen("stim/div_z");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/div_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #50370 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/div_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/div_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #0 div_a_count = $fscanf(div_a_file, "%d\\n", div_a);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/div_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #0 div_b_count = $fscanf(div_b_file, "%d\\n", div_b);\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,514 | module | module div_tb;
reg clk;
reg [31:0] div_a;
reg [31:0] div_b;
wire [31:0] div_z;
integer div_a_file;
integer div_b_file;
integer div_z_file;
integer div_a_count;
integer div_b_count;
integer div_z_count;
div div1 (clk, div_a, div_b, div_z);
initial
begin
div_z_file = $fopen("stim/div_z");
div_a_file = $fopen("stim/div_a", "r");
div_b_file = $fopen("stim/div_b", "r");
end
initial
begin
#50370 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(div_z_file, "%d", div_z);
#0 div_a_count = $fscanf(div_a_file, "%d\n", div_a);
#0 div_b_count = $fscanf(div_b_file, "%d\n", div_b);
end
endmodule | module div_tb; |
reg clk;
reg [31:0] div_a;
reg [31:0] div_b;
wire [31:0] div_z;
integer div_a_file;
integer div_b_file;
integer div_z_file;
integer div_a_count;
integer div_b_count;
integer div_z_count;
div div1 (clk, div_a, div_b, div_z);
initial
begin
div_z_file = $fopen("stim/div_z");
div_a_file = $fopen("stim/div_a", "r");
div_b_file = $fopen("stim/div_b", "r");
end
initial
begin
#50370 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(div_z_file, "%d", div_z);
#0 div_a_count = $fscanf(div_a_file, "%d\n", div_a);
#0 div_b_count = $fscanf(div_b_file, "%d\n", div_b);
end
endmodule | 56 |
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