Unnamed: 0
int64 1
143k
| directory
stringlengths 39
203
| repo_id
float64 143k
552M
| file_name
stringlengths 3
107
| extension
stringclasses 6
values | no_lines
int64 5
304k
| max_line_len
int64 15
21.6k
| generation_keywords
stringclasses 3
values | license_whitelist_keywords
stringclasses 16
values | license_blacklist_keywords
stringclasses 4
values | icarus_module_spans
stringlengths 8
6.16k
⌀ | icarus_exception
stringlengths 12
124
⌀ | verilator_xml_output_path
stringlengths 60
60
⌀ | verilator_exception
stringlengths 33
1.53M
⌀ | file_index
int64 0
315k
| snippet_type
stringclasses 2
values | snippet
stringlengths 21
9.27M
| snippet_def
stringlengths 9
30.3k
| snippet_body
stringlengths 10
9.27M
| gh_stars
int64 0
1.61k
|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
139,252 | data/full_repos/permissive/87104101/components/double_abs_tb.v | 87,104,101 | double_abs_tb.v | v | 36 | 78 | [] | [] | [] | null | line:19: before: "$" | null | 1: b'%Error: data/full_repos/permissive/87104101/components/double_abs_tb.v:13: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n double_abs_z_file = $fopen("stim/double_abs_z");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_abs_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #10010 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_abs_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_abs_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #0 double_abs_a_count = $fscanf(double_abs_a_file, "%d\\n", double_abs_a);\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,516 | module | module double_abs_tb;
reg clk;
reg [63:0] double_abs_a;
wire [63:0] double_abs_z;
integer double_abs_a_file;
integer double_abs_z_file;
integer double_abs_a_count;
integer double_abs_z_count;
double_abs double_abs1 (clk, double_abs_a, double_abs_z);
initial
begin
double_abs_z_file = $fopen("stim/double_abs_z");
double_abs_a_file = $fopen("stim/double_abs_a", "r");
end
initial
begin
#10010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_abs_z_file, "%d", double_abs_z);
#0 double_abs_a_count = $fscanf(double_abs_a_file, "%d\n", double_abs_a);
end
endmodule | module double_abs_tb; |
reg clk;
reg [63:0] double_abs_a;
wire [63:0] double_abs_z;
integer double_abs_a_file;
integer double_abs_z_file;
integer double_abs_a_count;
integer double_abs_z_count;
double_abs double_abs1 (clk, double_abs_a, double_abs_z);
initial
begin
double_abs_z_file = $fopen("stim/double_abs_z");
double_abs_a_file = $fopen("stim/double_abs_a", "r");
end
initial
begin
#10010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_abs_z_file, "%d", double_abs_z);
#0 double_abs_a_count = $fscanf(double_abs_a_file, "%d\n", double_abs_a);
end
endmodule | 56 |
139,253 | data/full_repos/permissive/87104101/components/double_add_tb.v | 87,104,101 | double_add_tb.v | v | 41 | 78 | [] | [] | [] | null | line:23: before: "$" | null | 1: b'%Error: data/full_repos/permissive/87104101/components/double_add_tb.v:16: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n double_add_z_file = $fopen("stim/double_add_z");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_add_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #10080 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_add_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_add_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #0 double_add_a_count = $fscanf(double_add_a_file, "%d\\n", double_add_a);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_add_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #0 double_add_b_count = $fscanf(double_add_b_file, "%d\\n", double_add_b);\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,518 | module | module double_add_tb;
reg clk;
reg [63:0] double_add_a;
reg [63:0] double_add_b;
wire [63:0] double_add_z;
integer double_add_a_file;
integer double_add_b_file;
integer double_add_z_file;
integer double_add_a_count;
integer double_add_b_count;
integer double_add_z_count;
double_add double_add1 (clk, double_add_a, double_add_b, double_add_z);
initial
begin
double_add_z_file = $fopen("stim/double_add_z");
double_add_a_file = $fopen("stim/double_add_a", "r");
double_add_b_file = $fopen("stim/double_add_b", "r");
end
initial
begin
#10080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_add_z_file, "%d", double_add_z);
#0 double_add_a_count = $fscanf(double_add_a_file, "%d\n", double_add_a);
#0 double_add_b_count = $fscanf(double_add_b_file, "%d\n", double_add_b);
end
endmodule | module double_add_tb; |
reg clk;
reg [63:0] double_add_a;
reg [63:0] double_add_b;
wire [63:0] double_add_z;
integer double_add_a_file;
integer double_add_b_file;
integer double_add_z_file;
integer double_add_a_count;
integer double_add_b_count;
integer double_add_z_count;
double_add double_add1 (clk, double_add_a, double_add_b, double_add_z);
initial
begin
double_add_z_file = $fopen("stim/double_add_z");
double_add_a_file = $fopen("stim/double_add_a", "r");
double_add_b_file = $fopen("stim/double_add_b", "r");
end
initial
begin
#10080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_add_z_file, "%d", double_add_z);
#0 double_add_a_count = $fscanf(double_add_a_file, "%d\n", double_add_a);
#0 double_add_b_count = $fscanf(double_add_b_file, "%d\n", double_add_b);
end
endmodule | 56 |
139,254 | data/full_repos/permissive/87104101/components/double_ceil_tb.v | 87,104,101 | double_ceil_tb.v | v | 36 | 81 | [] | [] | [] | null | line:19: before: "$" | null | 1: b'%Error: data/full_repos/permissive/87104101/components/double_ceil_tb.v:13: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n double_ceil_z_file = $fopen("stim/double_ceil_z");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_ceil_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #10080 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_ceil_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_ceil_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #0 double_ceil_a_count = $fscanf(double_ceil_a_file, "%d\\n", double_ceil_a);\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,520 | module | module double_ceil_tb;
reg clk;
reg [63:0] double_ceil_a;
wire [63:0] double_ceil_z;
integer double_ceil_a_file;
integer double_ceil_z_file;
integer double_ceil_a_count;
integer double_ceil_z_count;
double_ceil double_ceil1 (clk, double_ceil_a, double_ceil_z);
initial
begin
double_ceil_z_file = $fopen("stim/double_ceil_z");
double_ceil_a_file = $fopen("stim/double_ceil_a", "r");
end
initial
begin
#10080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_ceil_z_file, "%d", double_ceil_z);
#0 double_ceil_a_count = $fscanf(double_ceil_a_file, "%d\n", double_ceil_a);
end
endmodule | module double_ceil_tb; |
reg clk;
reg [63:0] double_ceil_a;
wire [63:0] double_ceil_z;
integer double_ceil_a_file;
integer double_ceil_z_file;
integer double_ceil_a_count;
integer double_ceil_z_count;
double_ceil double_ceil1 (clk, double_ceil_a, double_ceil_z);
initial
begin
double_ceil_z_file = $fopen("stim/double_ceil_z");
double_ceil_a_file = $fopen("stim/double_ceil_a", "r");
end
initial
begin
#10080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_ceil_z_file, "%d", double_ceil_z);
#0 double_ceil_a_count = $fscanf(double_ceil_a_file, "%d\n", double_ceil_a);
end
endmodule | 56 |
139,258 | data/full_repos/permissive/87104101/components/double_ge_tb.v | 87,104,101 | double_ge_tb.v | v | 41 | 75 | [] | [] | [] | null | line:23: before: "$" | null | 1: b'%Error: data/full_repos/permissive/87104101/components/double_ge_tb.v:16: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n double_ge_z_file = $fopen("stim/double_ge_z");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_ge_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #10080 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_ge_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_ge_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #0 double_ge_a_count = $fscanf(double_ge_a_file, "%d\\n", double_ge_a);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_ge_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #0 double_ge_b_count = $fscanf(double_ge_b_file, "%d\\n", double_ge_b);\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,528 | module | module double_ge_tb;
reg clk;
reg [63:0] double_ge_a;
reg [63:0] double_ge_b;
wire [0:0] double_ge_z;
integer double_ge_a_file;
integer double_ge_b_file;
integer double_ge_z_file;
integer double_ge_a_count;
integer double_ge_b_count;
integer double_ge_z_count;
double_ge double_ge1 (clk, double_ge_a, double_ge_b, double_ge_z);
initial
begin
double_ge_z_file = $fopen("stim/double_ge_z");
double_ge_a_file = $fopen("stim/double_ge_a", "r");
double_ge_b_file = $fopen("stim/double_ge_b", "r");
end
initial
begin
#10080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_ge_z_file, "%d", double_ge_z);
#0 double_ge_a_count = $fscanf(double_ge_a_file, "%d\n", double_ge_a);
#0 double_ge_b_count = $fscanf(double_ge_b_file, "%d\n", double_ge_b);
end
endmodule | module double_ge_tb; |
reg clk;
reg [63:0] double_ge_a;
reg [63:0] double_ge_b;
wire [0:0] double_ge_z;
integer double_ge_a_file;
integer double_ge_b_file;
integer double_ge_z_file;
integer double_ge_a_count;
integer double_ge_b_count;
integer double_ge_z_count;
double_ge double_ge1 (clk, double_ge_a, double_ge_b, double_ge_z);
initial
begin
double_ge_z_file = $fopen("stim/double_ge_z");
double_ge_a_file = $fopen("stim/double_ge_a", "r");
double_ge_b_file = $fopen("stim/double_ge_b", "r");
end
initial
begin
#10080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_ge_z_file, "%d", double_ge_z);
#0 double_ge_a_count = $fscanf(double_ge_a_file, "%d\n", double_ge_a);
#0 double_ge_b_count = $fscanf(double_ge_b_file, "%d\n", double_ge_b);
end
endmodule | 56 |
139,260 | data/full_repos/permissive/87104101/components/double_le_tb.v | 87,104,101 | double_le_tb.v | v | 41 | 75 | [] | [] | [] | null | line:23: before: "$" | null | 1: b'%Error: data/full_repos/permissive/87104101/components/double_le_tb.v:16: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n double_le_z_file = $fopen("stim/double_le_z");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_le_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #10080 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_le_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_le_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #0 double_le_a_count = $fscanf(double_le_a_file, "%d\\n", double_le_a);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_le_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #0 double_le_b_count = $fscanf(double_le_b_file, "%d\\n", double_le_b);\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,532 | module | module double_le_tb;
reg clk;
reg [63:0] double_le_a;
reg [63:0] double_le_b;
wire [0:0] double_le_z;
integer double_le_a_file;
integer double_le_b_file;
integer double_le_z_file;
integer double_le_a_count;
integer double_le_b_count;
integer double_le_z_count;
double_le double_le1 (clk, double_le_a, double_le_b, double_le_z);
initial
begin
double_le_z_file = $fopen("stim/double_le_z");
double_le_a_file = $fopen("stim/double_le_a", "r");
double_le_b_file = $fopen("stim/double_le_b", "r");
end
initial
begin
#10080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_le_z_file, "%d", double_le_z);
#0 double_le_a_count = $fscanf(double_le_a_file, "%d\n", double_le_a);
#0 double_le_b_count = $fscanf(double_le_b_file, "%d\n", double_le_b);
end
endmodule | module double_le_tb; |
reg clk;
reg [63:0] double_le_a;
reg [63:0] double_le_b;
wire [0:0] double_le_z;
integer double_le_a_file;
integer double_le_b_file;
integer double_le_z_file;
integer double_le_a_count;
integer double_le_b_count;
integer double_le_z_count;
double_le double_le1 (clk, double_le_a, double_le_b, double_le_z);
initial
begin
double_le_z_file = $fopen("stim/double_le_z");
double_le_a_file = $fopen("stim/double_le_a", "r");
double_le_b_file = $fopen("stim/double_le_b", "r");
end
initial
begin
#10080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_le_z_file, "%d", double_le_z);
#0 double_le_a_count = $fscanf(double_le_a_file, "%d\n", double_le_a);
#0 double_le_b_count = $fscanf(double_le_b_file, "%d\n", double_le_b);
end
endmodule | 56 |
139,261 | data/full_repos/permissive/87104101/components/double_lt_tb.v | 87,104,101 | double_lt_tb.v | v | 41 | 75 | [] | [] | [] | null | line:23: before: "$" | null | 1: b'%Error: data/full_repos/permissive/87104101/components/double_lt_tb.v:16: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n double_lt_z_file = $fopen("stim/double_lt_z");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_lt_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #10080 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_lt_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_lt_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #0 double_lt_a_count = $fscanf(double_lt_a_file, "%d\\n", double_lt_a);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_lt_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #0 double_lt_b_count = $fscanf(double_lt_b_file, "%d\\n", double_lt_b);\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,534 | module | module double_lt_tb;
reg clk;
reg [63:0] double_lt_a;
reg [63:0] double_lt_b;
wire [0:0] double_lt_z;
integer double_lt_a_file;
integer double_lt_b_file;
integer double_lt_z_file;
integer double_lt_a_count;
integer double_lt_b_count;
integer double_lt_z_count;
double_lt double_lt1 (clk, double_lt_a, double_lt_b, double_lt_z);
initial
begin
double_lt_z_file = $fopen("stim/double_lt_z");
double_lt_a_file = $fopen("stim/double_lt_a", "r");
double_lt_b_file = $fopen("stim/double_lt_b", "r");
end
initial
begin
#10080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_lt_z_file, "%d", double_lt_z);
#0 double_lt_a_count = $fscanf(double_lt_a_file, "%d\n", double_lt_a);
#0 double_lt_b_count = $fscanf(double_lt_b_file, "%d\n", double_lt_b);
end
endmodule | module double_lt_tb; |
reg clk;
reg [63:0] double_lt_a;
reg [63:0] double_lt_b;
wire [0:0] double_lt_z;
integer double_lt_a_file;
integer double_lt_b_file;
integer double_lt_z_file;
integer double_lt_a_count;
integer double_lt_b_count;
integer double_lt_z_count;
double_lt double_lt1 (clk, double_lt_a, double_lt_b, double_lt_z);
initial
begin
double_lt_z_file = $fopen("stim/double_lt_z");
double_lt_a_file = $fopen("stim/double_lt_a", "r");
double_lt_b_file = $fopen("stim/double_lt_b", "r");
end
initial
begin
#10080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_lt_z_file, "%d", double_lt_z);
#0 double_lt_a_count = $fscanf(double_lt_a_file, "%d\n", double_lt_a);
#0 double_lt_b_count = $fscanf(double_lt_b_file, "%d\n", double_lt_b);
end
endmodule | 56 |
139,262 | data/full_repos/permissive/87104101/components/double_max_tb.v | 87,104,101 | double_max_tb.v | v | 41 | 78 | [] | [] | [] | null | line:23: before: "$" | null | 1: b'%Error: data/full_repos/permissive/87104101/components/double_max_tb.v:16: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n double_max_z_file = $fopen("stim/double_max_z");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_max_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #10080 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_max_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_max_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #0 double_max_a_count = $fscanf(double_max_a_file, "%d\\n", double_max_a);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_max_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #0 double_max_b_count = $fscanf(double_max_b_file, "%d\\n", double_max_b);\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,536 | module | module double_max_tb;
reg clk;
reg [63:0] double_max_a;
reg [63:0] double_max_b;
wire [63:0] double_max_z;
integer double_max_a_file;
integer double_max_b_file;
integer double_max_z_file;
integer double_max_a_count;
integer double_max_b_count;
integer double_max_z_count;
double_max double_max1 (clk, double_max_a, double_max_b, double_max_z);
initial
begin
double_max_z_file = $fopen("stim/double_max_z");
double_max_a_file = $fopen("stim/double_max_a", "r");
double_max_b_file = $fopen("stim/double_max_b", "r");
end
initial
begin
#10080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_max_z_file, "%d", double_max_z);
#0 double_max_a_count = $fscanf(double_max_a_file, "%d\n", double_max_a);
#0 double_max_b_count = $fscanf(double_max_b_file, "%d\n", double_max_b);
end
endmodule | module double_max_tb; |
reg clk;
reg [63:0] double_max_a;
reg [63:0] double_max_b;
wire [63:0] double_max_z;
integer double_max_a_file;
integer double_max_b_file;
integer double_max_z_file;
integer double_max_a_count;
integer double_max_b_count;
integer double_max_z_count;
double_max double_max1 (clk, double_max_a, double_max_b, double_max_z);
initial
begin
double_max_z_file = $fopen("stim/double_max_z");
double_max_a_file = $fopen("stim/double_max_a", "r");
double_max_b_file = $fopen("stim/double_max_b", "r");
end
initial
begin
#10080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_max_z_file, "%d", double_max_z);
#0 double_max_a_count = $fscanf(double_max_a_file, "%d\n", double_max_a);
#0 double_max_b_count = $fscanf(double_max_b_file, "%d\n", double_max_b);
end
endmodule | 56 |
139,265 | data/full_repos/permissive/87104101/components/double_neg_tb.v | 87,104,101 | double_neg_tb.v | v | 36 | 78 | [] | [] | [] | null | line:19: before: "$" | null | 1: b'%Error: data/full_repos/permissive/87104101/components/double_neg_tb.v:13: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n double_neg_z_file = $fopen("stim/double_neg_z");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_neg_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #10010 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_neg_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_neg_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #0 double_neg_a_count = $fscanf(double_neg_a_file, "%d\\n", double_neg_a);\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,543 | module | module double_neg_tb;
reg clk;
reg [63:0] double_neg_a;
wire [63:0] double_neg_z;
integer double_neg_a_file;
integer double_neg_z_file;
integer double_neg_a_count;
integer double_neg_z_count;
double_neg double_neg1 (clk, double_neg_a, double_neg_z);
initial
begin
double_neg_z_file = $fopen("stim/double_neg_z");
double_neg_a_file = $fopen("stim/double_neg_a", "r");
end
initial
begin
#10010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_neg_z_file, "%d", double_neg_z);
#0 double_neg_a_count = $fscanf(double_neg_a_file, "%d\n", double_neg_a);
end
endmodule | module double_neg_tb; |
reg clk;
reg [63:0] double_neg_a;
wire [63:0] double_neg_z;
integer double_neg_a_file;
integer double_neg_z_file;
integer double_neg_a_count;
integer double_neg_z_count;
double_neg double_neg1 (clk, double_neg_a, double_neg_z);
initial
begin
double_neg_z_file = $fopen("stim/double_neg_z");
double_neg_a_file = $fopen("stim/double_neg_a", "r");
end
initial
begin
#10010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_neg_z_file, "%d", double_neg_z);
#0 double_neg_a_count = $fscanf(double_neg_a_file, "%d\n", double_neg_a);
end
endmodule | 56 |
139,266 | data/full_repos/permissive/87104101/components/double_ne_tb.v | 87,104,101 | double_ne_tb.v | v | 41 | 75 | [] | [] | [] | null | line:23: before: "$" | null | 1: b'%Error: data/full_repos/permissive/87104101/components/double_ne_tb.v:16: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n double_ne_z_file = $fopen("stim/double_ne_z");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_ne_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #10010 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_ne_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_ne_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #0 double_ne_a_count = $fscanf(double_ne_a_file, "%d\\n", double_ne_a);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_ne_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #0 double_ne_b_count = $fscanf(double_ne_b_file, "%d\\n", double_ne_b);\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,544 | module | module double_ne_tb;
reg clk;
reg [63:0] double_ne_a;
reg [63:0] double_ne_b;
wire [0:0] double_ne_z;
integer double_ne_a_file;
integer double_ne_b_file;
integer double_ne_z_file;
integer double_ne_a_count;
integer double_ne_b_count;
integer double_ne_z_count;
double_ne double_ne1 (clk, double_ne_a, double_ne_b, double_ne_z);
initial
begin
double_ne_z_file = $fopen("stim/double_ne_z");
double_ne_a_file = $fopen("stim/double_ne_a", "r");
double_ne_b_file = $fopen("stim/double_ne_b", "r");
end
initial
begin
#10010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_ne_z_file, "%d", double_ne_z);
#0 double_ne_a_count = $fscanf(double_ne_a_file, "%d\n", double_ne_a);
#0 double_ne_b_count = $fscanf(double_ne_b_file, "%d\n", double_ne_b);
end
endmodule | module double_ne_tb; |
reg clk;
reg [63:0] double_ne_a;
reg [63:0] double_ne_b;
wire [0:0] double_ne_z;
integer double_ne_a_file;
integer double_ne_b_file;
integer double_ne_z_file;
integer double_ne_a_count;
integer double_ne_b_count;
integer double_ne_z_count;
double_ne double_ne1 (clk, double_ne_a, double_ne_b, double_ne_z);
initial
begin
double_ne_z_file = $fopen("stim/double_ne_z");
double_ne_a_file = $fopen("stim/double_ne_a", "r");
double_ne_b_file = $fopen("stim/double_ne_b", "r");
end
initial
begin
#10010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_ne_z_file, "%d", double_ne_z);
#0 double_ne_a_count = $fscanf(double_ne_a_file, "%d\n", double_ne_a);
#0 double_ne_b_count = $fscanf(double_ne_b_file, "%d\n", double_ne_b);
end
endmodule | 56 |
139,268 | data/full_repos/permissive/87104101/components/double_to_int_tb.v | 87,104,101 | double_to_int_tb.v | v | 36 | 87 | [] | [] | [] | null | line:19: before: "$" | null | 1: b'%Error: data/full_repos/permissive/87104101/components/double_to_int_tb.v:13: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n double_to_int_z_file = $fopen("stim/double_to_int_z");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_to_int_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #10030 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_to_int_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/double_to_int_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #0 double_to_int_a_count = $fscanf(double_to_int_a_file, "%d\\n", double_to_int_a);\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,548 | module | module double_to_int_tb;
reg clk;
reg [63:0] double_to_int_a;
wire [63:0] double_to_int_z;
integer double_to_int_a_file;
integer double_to_int_z_file;
integer double_to_int_a_count;
integer double_to_int_z_count;
double_to_int double_to_int1 (clk, double_to_int_a, double_to_int_z);
initial
begin
double_to_int_z_file = $fopen("stim/double_to_int_z");
double_to_int_a_file = $fopen("stim/double_to_int_a", "r");
end
initial
begin
#10030 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_to_int_z_file, "%d", double_to_int_z);
#0 double_to_int_a_count = $fscanf(double_to_int_a_file, "%d\n", double_to_int_a);
end
endmodule | module double_to_int_tb; |
reg clk;
reg [63:0] double_to_int_a;
wire [63:0] double_to_int_z;
integer double_to_int_a_file;
integer double_to_int_z_file;
integer double_to_int_a_count;
integer double_to_int_z_count;
double_to_int double_to_int1 (clk, double_to_int_a, double_to_int_z);
initial
begin
double_to_int_z_file = $fopen("stim/double_to_int_z");
double_to_int_a_file = $fopen("stim/double_to_int_a", "r");
end
initial
begin
#10030 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_to_int_z_file, "%d", double_to_int_z);
#0 double_to_int_a_count = $fscanf(double_to_int_a_file, "%d\n", double_to_int_a);
end
endmodule | 56 |
139,271 | data/full_repos/permissive/87104101/components/eq_tb.v | 87,104,101 | eq_tb.v | v | 41 | 54 | [] | [] | [] | null | line:23: before: "$" | null | 1: b'%Error: data/full_repos/permissive/87104101/components/eq_tb.v:16: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n eq_z_file = $fopen("stim/eq_z");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/eq_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #50010 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/eq_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/eq_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #0 eq_a_count = $fscanf(eq_a_file, "%d\\n", eq_a);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/eq_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #0 eq_b_count = $fscanf(eq_b_file, "%d\\n", eq_b);\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,554 | module | module eq_tb;
reg clk;
reg [31:0] eq_a;
reg [31:0] eq_b;
wire [0:0] eq_z;
integer eq_a_file;
integer eq_b_file;
integer eq_z_file;
integer eq_a_count;
integer eq_b_count;
integer eq_z_count;
eq eq1 (clk, eq_a, eq_b, eq_z);
initial
begin
eq_z_file = $fopen("stim/eq_z");
eq_a_file = $fopen("stim/eq_a", "r");
eq_b_file = $fopen("stim/eq_b", "r");
end
initial
begin
#50010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(eq_z_file, "%d", eq_z);
#0 eq_a_count = $fscanf(eq_a_file, "%d\n", eq_a);
#0 eq_b_count = $fscanf(eq_b_file, "%d\n", eq_b);
end
endmodule | module eq_tb; |
reg clk;
reg [31:0] eq_a;
reg [31:0] eq_b;
wire [0:0] eq_z;
integer eq_a_file;
integer eq_b_file;
integer eq_z_file;
integer eq_a_count;
integer eq_b_count;
integer eq_z_count;
eq eq1 (clk, eq_a, eq_b, eq_z);
initial
begin
eq_z_file = $fopen("stim/eq_z");
eq_a_file = $fopen("stim/eq_a", "r");
eq_b_file = $fopen("stim/eq_b", "r");
end
initial
begin
#50010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(eq_z_file, "%d", eq_z);
#0 eq_a_count = $fscanf(eq_a_file, "%d\n", eq_a);
#0 eq_b_count = $fscanf(eq_b_file, "%d\n", eq_b);
end
endmodule | 56 |
139,274 | data/full_repos/permissive/87104101/components/gt_tb.v | 87,104,101 | gt_tb.v | v | 41 | 54 | [] | [] | [] | null | line:23: before: "$" | null | 1: b'%Error: data/full_repos/permissive/87104101/components/gt_tb.v:16: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n gt_z_file = $fopen("stim/gt_z");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/gt_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #50080 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/gt_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/gt_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #0 gt_a_count = $fscanf(gt_a_file, "%d\\n", gt_a);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/gt_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #0 gt_b_count = $fscanf(gt_b_file, "%d\\n", gt_b);\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,560 | module | module gt_tb;
reg clk;
reg [31:0] gt_a;
reg [31:0] gt_b;
wire [0:0] gt_z;
integer gt_a_file;
integer gt_b_file;
integer gt_z_file;
integer gt_a_count;
integer gt_b_count;
integer gt_z_count;
gt gt1 (clk, gt_a, gt_b, gt_z);
initial
begin
gt_z_file = $fopen("stim/gt_z");
gt_a_file = $fopen("stim/gt_a", "r");
gt_b_file = $fopen("stim/gt_b", "r");
end
initial
begin
#50080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(gt_z_file, "%d", gt_z);
#0 gt_a_count = $fscanf(gt_a_file, "%d\n", gt_a);
#0 gt_b_count = $fscanf(gt_b_file, "%d\n", gt_b);
end
endmodule | module gt_tb; |
reg clk;
reg [31:0] gt_a;
reg [31:0] gt_b;
wire [0:0] gt_z;
integer gt_a_file;
integer gt_b_file;
integer gt_z_file;
integer gt_a_count;
integer gt_b_count;
integer gt_z_count;
gt gt1 (clk, gt_a, gt_b, gt_z);
initial
begin
gt_z_file = $fopen("stim/gt_z");
gt_a_file = $fopen("stim/gt_a", "r");
gt_b_file = $fopen("stim/gt_b", "r");
end
initial
begin
#50080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(gt_z_file, "%d", gt_z);
#0 gt_a_count = $fscanf(gt_a_file, "%d\n", gt_a);
#0 gt_b_count = $fscanf(gt_b_file, "%d\n", gt_b);
end
endmodule | 56 |
139,276 | data/full_repos/permissive/87104101/components/int_to_single_tb.v | 87,104,101 | int_to_single_tb.v | v | 36 | 87 | [] | [] | [] | null | line:19: before: "$" | null | 1: b'%Error: data/full_repos/permissive/87104101/components/int_to_single_tb.v:13: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n int_to_single_z_file = $fopen("stim/int_to_single_z");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/int_to_single_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #50060 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/int_to_single_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/int_to_single_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #0 int_to_single_a_count = $fscanf(int_to_single_a_file, "%d\\n", int_to_single_a);\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,564 | module | module int_to_single_tb;
reg clk;
reg [31:0] int_to_single_a;
wire [31:0] int_to_single_z;
integer int_to_single_a_file;
integer int_to_single_z_file;
integer int_to_single_a_count;
integer int_to_single_z_count;
int_to_single int_to_single1 (clk, int_to_single_a, int_to_single_z);
initial
begin
int_to_single_z_file = $fopen("stim/int_to_single_z");
int_to_single_a_file = $fopen("stim/int_to_single_a", "r");
end
initial
begin
#50060 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(int_to_single_z_file, "%d", int_to_single_z);
#0 int_to_single_a_count = $fscanf(int_to_single_a_file, "%d\n", int_to_single_a);
end
endmodule | module int_to_single_tb; |
reg clk;
reg [31:0] int_to_single_a;
wire [31:0] int_to_single_z;
integer int_to_single_a_file;
integer int_to_single_z_file;
integer int_to_single_a_count;
integer int_to_single_z_count;
int_to_single int_to_single1 (clk, int_to_single_a, int_to_single_z);
initial
begin
int_to_single_z_file = $fopen("stim/int_to_single_z");
int_to_single_a_file = $fopen("stim/int_to_single_a", "r");
end
initial
begin
#50060 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(int_to_single_z_file, "%d", int_to_single_z);
#0 int_to_single_a_count = $fscanf(int_to_single_a_file, "%d\n", int_to_single_a);
end
endmodule | 56 |
139,282 | data/full_repos/permissive/87104101/components/ne_tb.v | 87,104,101 | ne_tb.v | v | 41 | 54 | [] | [] | [] | null | line:23: before: "$" | null | 1: b'%Error: data/full_repos/permissive/87104101/components/ne_tb.v:16: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n ne_z_file = $fopen("stim/ne_z");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/ne_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #50010 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/ne_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/ne_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #0 ne_a_count = $fscanf(ne_a_file, "%d\\n", ne_a);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/ne_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #0 ne_b_count = $fscanf(ne_b_file, "%d\\n", ne_b);\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,575 | module | module ne_tb;
reg clk;
reg [31:0] ne_a;
reg [31:0] ne_b;
wire [0:0] ne_z;
integer ne_a_file;
integer ne_b_file;
integer ne_z_file;
integer ne_a_count;
integer ne_b_count;
integer ne_z_count;
ne ne1 (clk, ne_a, ne_b, ne_z);
initial
begin
ne_z_file = $fopen("stim/ne_z");
ne_a_file = $fopen("stim/ne_a", "r");
ne_b_file = $fopen("stim/ne_b", "r");
end
initial
begin
#50010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(ne_z_file, "%d", ne_z);
#0 ne_a_count = $fscanf(ne_a_file, "%d\n", ne_a);
#0 ne_b_count = $fscanf(ne_b_file, "%d\n", ne_b);
end
endmodule | module ne_tb; |
reg clk;
reg [31:0] ne_a;
reg [31:0] ne_b;
wire [0:0] ne_z;
integer ne_a_file;
integer ne_b_file;
integer ne_z_file;
integer ne_a_count;
integer ne_b_count;
integer ne_z_count;
ne ne1 (clk, ne_a, ne_b, ne_z);
initial
begin
ne_z_file = $fopen("stim/ne_z");
ne_a_file = $fopen("stim/ne_a", "r");
ne_b_file = $fopen("stim/ne_b", "r");
end
initial
begin
#50010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(ne_z_file, "%d", ne_z);
#0 ne_a_count = $fscanf(ne_a_file, "%d\n", ne_a);
#0 ne_b_count = $fscanf(ne_b_file, "%d\n", ne_b);
end
endmodule | 56 |
139,283 | data/full_repos/permissive/87104101/components/single_max_tb.v | 87,104,101 | single_max_tb.v | v | 41 | 78 | [] | [] | [] | null | line:23: before: "$" | null | 1: b'%Error: data/full_repos/permissive/87104101/components/single_max_tb.v:16: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n single_max_z_file = $fopen("stim/single_max_z");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/single_max_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #50080 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/single_max_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/single_max_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #0 single_max_a_count = $fscanf(single_max_a_file, "%d\\n", single_max_a);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/single_max_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #0 single_max_b_count = $fscanf(single_max_b_file, "%d\\n", single_max_b);\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,577 | module | module single_max_tb;
reg clk;
reg [31:0] single_max_a;
reg [31:0] single_max_b;
wire [31:0] single_max_z;
integer single_max_a_file;
integer single_max_b_file;
integer single_max_z_file;
integer single_max_a_count;
integer single_max_b_count;
integer single_max_z_count;
single_max single_max1 (clk, single_max_a, single_max_b, single_max_z);
initial
begin
single_max_z_file = $fopen("stim/single_max_z");
single_max_a_file = $fopen("stim/single_max_a", "r");
single_max_b_file = $fopen("stim/single_max_b", "r");
end
initial
begin
#50080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(single_max_z_file, "%d", single_max_z);
#0 single_max_a_count = $fscanf(single_max_a_file, "%d\n", single_max_a);
#0 single_max_b_count = $fscanf(single_max_b_file, "%d\n", single_max_b);
end
endmodule | module single_max_tb; |
reg clk;
reg [31:0] single_max_a;
reg [31:0] single_max_b;
wire [31:0] single_max_z;
integer single_max_a_file;
integer single_max_b_file;
integer single_max_z_file;
integer single_max_a_count;
integer single_max_b_count;
integer single_max_z_count;
single_max single_max1 (clk, single_max_a, single_max_b, single_max_z);
initial
begin
single_max_z_file = $fopen("stim/single_max_z");
single_max_a_file = $fopen("stim/single_max_a", "r");
single_max_b_file = $fopen("stim/single_max_b", "r");
end
initial
begin
#50080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(single_max_z_file, "%d", single_max_z);
#0 single_max_a_count = $fscanf(single_max_a_file, "%d\n", single_max_a);
#0 single_max_b_count = $fscanf(single_max_b_file, "%d\n", single_max_b);
end
endmodule | 56 |
139,284 | data/full_repos/permissive/87104101/components/single_min_tb.v | 87,104,101 | single_min_tb.v | v | 41 | 78 | [] | [] | [] | null | line:23: before: "$" | null | 1: b'%Error: data/full_repos/permissive/87104101/components/single_min_tb.v:16: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n single_min_z_file = $fopen("stim/single_min_z");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/single_min_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #50080 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/single_min_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/single_min_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #0 single_min_a_count = $fscanf(single_min_a_file, "%d\\n", single_min_a);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/single_min_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #0 single_min_b_count = $fscanf(single_min_b_file, "%d\\n", single_min_b);\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,579 | module | module single_min_tb;
reg clk;
reg [31:0] single_min_a;
reg [31:0] single_min_b;
wire [31:0] single_min_z;
integer single_min_a_file;
integer single_min_b_file;
integer single_min_z_file;
integer single_min_a_count;
integer single_min_b_count;
integer single_min_z_count;
single_min single_min1 (clk, single_min_a, single_min_b, single_min_z);
initial
begin
single_min_z_file = $fopen("stim/single_min_z");
single_min_a_file = $fopen("stim/single_min_a", "r");
single_min_b_file = $fopen("stim/single_min_b", "r");
end
initial
begin
#50080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(single_min_z_file, "%d", single_min_z);
#0 single_min_a_count = $fscanf(single_min_a_file, "%d\n", single_min_a);
#0 single_min_b_count = $fscanf(single_min_b_file, "%d\n", single_min_b);
end
endmodule | module single_min_tb; |
reg clk;
reg [31:0] single_min_a;
reg [31:0] single_min_b;
wire [31:0] single_min_z;
integer single_min_a_file;
integer single_min_b_file;
integer single_min_z_file;
integer single_min_a_count;
integer single_min_b_count;
integer single_min_z_count;
single_min single_min1 (clk, single_min_a, single_min_b, single_min_z);
initial
begin
single_min_z_file = $fopen("stim/single_min_z");
single_min_a_file = $fopen("stim/single_min_a", "r");
single_min_b_file = $fopen("stim/single_min_b", "r");
end
initial
begin
#50080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(single_min_z_file, "%d", single_min_z);
#0 single_min_a_count = $fscanf(single_min_a_file, "%d\n", single_min_a);
#0 single_min_b_count = $fscanf(single_min_b_file, "%d\n", single_min_b);
end
endmodule | 56 |
139,286 | data/full_repos/permissive/87104101/components/single_to_unsigned_int_tb.v | 87,104,101 | single_to_unsigned_int_tb.v | v | 36 | 114 | [] | [] | [] | null | line:19: before: "$" | null | 1: b'%Error: data/full_repos/permissive/87104101/components/single_to_unsigned_int_tb.v:13: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n single_to_unsigned_int_z_file = $fopen("stim/single_to_unsigned_int_z");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/single_to_unsigned_int_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #50020 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/single_to_unsigned_int_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/single_to_unsigned_int_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #0 single_to_unsigned_int_a_count = $fscanf(single_to_unsigned_int_a_file, "%d\\n", single_to_unsigned_int_a);\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,583 | module | module single_to_unsigned_int_tb;
reg clk;
reg [31:0] single_to_unsigned_int_a;
wire [31:0] single_to_unsigned_int_z;
integer single_to_unsigned_int_a_file;
integer single_to_unsigned_int_z_file;
integer single_to_unsigned_int_a_count;
integer single_to_unsigned_int_z_count;
single_to_unsigned_int single_to_unsigned_int1 (clk, single_to_unsigned_int_a, single_to_unsigned_int_z);
initial
begin
single_to_unsigned_int_z_file = $fopen("stim/single_to_unsigned_int_z");
single_to_unsigned_int_a_file = $fopen("stim/single_to_unsigned_int_a", "r");
end
initial
begin
#50020 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(single_to_unsigned_int_z_file, "%d", single_to_unsigned_int_z);
#0 single_to_unsigned_int_a_count = $fscanf(single_to_unsigned_int_a_file, "%d\n", single_to_unsigned_int_a);
end
endmodule | module single_to_unsigned_int_tb; |
reg clk;
reg [31:0] single_to_unsigned_int_a;
wire [31:0] single_to_unsigned_int_z;
integer single_to_unsigned_int_a_file;
integer single_to_unsigned_int_z_file;
integer single_to_unsigned_int_a_count;
integer single_to_unsigned_int_z_count;
single_to_unsigned_int single_to_unsigned_int1 (clk, single_to_unsigned_int_a, single_to_unsigned_int_z);
initial
begin
single_to_unsigned_int_z_file = $fopen("stim/single_to_unsigned_int_z");
single_to_unsigned_int_a_file = $fopen("stim/single_to_unsigned_int_a", "r");
end
initial
begin
#50020 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(single_to_unsigned_int_z_file, "%d", single_to_unsigned_int_z);
#0 single_to_unsigned_int_a_count = $fscanf(single_to_unsigned_int_a_file, "%d\n", single_to_unsigned_int_a);
end
endmodule | 56 |
139,288 | data/full_repos/permissive/87104101/components/to_float.v | 87,104,101 | to_float.v | v | 849 | 46 | [] | [] | [] | [(1, 16), (18, 848)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/87104101/components/to_float.v:458: Operator COND expects 25 bits on the Conditional False, but Conditional False\'s VARREF \'s_376\' generates 24 bits.\n : ... In instance to_float\n assign s_23 = s_377?s_24:s_376;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/87104101/components/to_float.v:460: Operator ADD expects 25 bits on the RHS, but RHS\'s VARREF \'s_375\' generates 1 bits.\n : ... In instance to_float\n assign s_25 = s_26 + s_375;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87104101/components/to_float.v:461: Operator ASSIGNW expects 25 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_27\' generates 24 bits.\n : ... In instance to_float\n assign s_26 = s_27;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87104101/components/to_float.v:820: Operator NEQ expects 6 bits on the RHS, but RHS\'s VARREF \'s_387\' generates 1 bits.\n : ... In instance to_float\n assign s_385 = s_386 != s_387;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87104101/components/to_float.v:832: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'s_391\' generates 1 bits.\n : ... In instance to_float\n assign s_397 = s_398 + s_391;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87104101/components/to_float.v:834: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'s_34\' generates 6 bits.\n : ... In instance to_float\n assign s_399 = s_400 - s_34;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 304,586 | module | module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line[i] <= delay_line[i-1];
end
end
assign q = delay_line[depth-1];
endmodule | module dq (clk, q, d); |
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line[i] <= delay_line[i-1];
end
end
assign q = delay_line[depth-1];
endmodule | 56 |
139,289 | data/full_repos/permissive/87104101/components/to_float.v | 87,104,101 | to_float.v | v | 849 | 46 | [] | [] | [] | [(1, 16), (18, 848)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/87104101/components/to_float.v:458: Operator COND expects 25 bits on the Conditional False, but Conditional False\'s VARREF \'s_376\' generates 24 bits.\n : ... In instance to_float\n assign s_23 = s_377?s_24:s_376;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/87104101/components/to_float.v:460: Operator ADD expects 25 bits on the RHS, but RHS\'s VARREF \'s_375\' generates 1 bits.\n : ... In instance to_float\n assign s_25 = s_26 + s_375;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87104101/components/to_float.v:461: Operator ASSIGNW expects 25 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_27\' generates 24 bits.\n : ... In instance to_float\n assign s_26 = s_27;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87104101/components/to_float.v:820: Operator NEQ expects 6 bits on the RHS, but RHS\'s VARREF \'s_387\' generates 1 bits.\n : ... In instance to_float\n assign s_385 = s_386 != s_387;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87104101/components/to_float.v:832: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'s_391\' generates 1 bits.\n : ... In instance to_float\n assign s_397 = s_398 + s_391;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87104101/components/to_float.v:834: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'s_34\' generates 6 bits.\n : ... In instance to_float\n assign s_399 = s_400 - s_34;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 304,586 | module | module to_float(clk, to_float_a, to_float_z);
input clk;
input [31:0] to_float_a;
output [31:0] to_float_z;
wire [31:0] s_0;
wire [31:0] s_1;
wire [31:0] s_2;
wire [0:0] s_3;
wire [31:0] s_4;
wire [30:0] s_5;
wire [31:0] s_6;
wire [31:0] s_7;
wire [31:0] s_8;
wire [30:0] s_9;
wire [31:0] s_10;
wire [31:0] s_11;
wire [31:0] s_12;
wire [30:0] s_13;
wire [31:0] s_14;
wire [31:0] s_15;
wire [8:0] s_16;
wire [8:0] s_17;
wire [7:0] s_18;
wire [22:0] s_19;
wire [23:0] s_20;
wire [23:0] s_21;
wire [23:0] s_22;
wire [24:0] s_23;
wire [24:0] s_24;
wire [24:0] s_25;
wire [24:0] s_26;
wire [23:0] s_27;
wire [31:0] s_28;
wire [31:0] s_29;
wire [31:0] s_30;
wire [31:0] s_31;
wire [31:0] s_32;
wire [31:0] s_33;
wire [5:0] s_34;
wire [5:0] s_35;
wire [0:0] s_36;
wire [0:0] s_37;
wire [4:0] s_38;
wire [0:0] s_39;
wire [0:0] s_40;
wire [3:0] s_41;
wire [0:0] s_42;
wire [0:0] s_43;
wire [2:0] s_44;
wire [0:0] s_45;
wire [0:0] s_46;
wire [1:0] s_47;
wire [0:0] s_48;
wire [0:0] s_49;
wire [0:0] s_50;
wire [1:0] s_51;
wire [3:0] s_52;
wire [7:0] s_53;
wire [15:0] s_54;
wire [0:0] s_55;
wire [0:0] s_56;
wire [0:0] s_57;
wire [0:0] s_58;
wire [0:0] s_59;
wire [0:0] s_60;
wire [0:0] s_61;
wire [1:0] s_62;
wire [0:0] s_63;
wire [0:0] s_64;
wire [0:0] s_65;
wire [1:0] s_66;
wire [0:0] s_67;
wire [0:0] s_68;
wire [0:0] s_69;
wire [0:0] s_70;
wire [0:0] s_71;
wire [0:0] s_72;
wire [1:0] s_73;
wire [0:0] s_74;
wire [0:0] s_75;
wire [0:0] s_76;
wire [0:0] s_77;
wire [0:0] s_78;
wire [0:0] s_79;
wire [2:0] s_80;
wire [0:0] s_81;
wire [0:0] s_82;
wire [1:0] s_83;
wire [0:0] s_84;
wire [0:0] s_85;
wire [0:0] s_86;
wire [1:0] s_87;
wire [3:0] s_88;
wire [0:0] s_89;
wire [0:0] s_90;
wire [0:0] s_91;
wire [0:0] s_92;
wire [0:0] s_93;
wire [0:0] s_94;
wire [0:0] s_95;
wire [1:0] s_96;
wire [0:0] s_97;
wire [0:0] s_98;
wire [0:0] s_99;
wire [1:0] s_100;
wire [0:0] s_101;
wire [0:0] s_102;
wire [0:0] s_103;
wire [0:0] s_104;
wire [0:0] s_105;
wire [0:0] s_106;
wire [1:0] s_107;
wire [0:0] s_108;
wire [0:0] s_109;
wire [0:0] s_110;
wire [0:0] s_111;
wire [0:0] s_112;
wire [2:0] s_113;
wire [0:0] s_114;
wire [0:0] s_115;
wire [1:0] s_116;
wire [1:0] s_117;
wire [1:0] s_118;
wire [0:0] s_119;
wire [3:0] s_120;
wire [0:0] s_121;
wire [0:0] s_122;
wire [2:0] s_123;
wire [0:0] s_124;
wire [0:0] s_125;
wire [1:0] s_126;
wire [0:0] s_127;
wire [0:0] s_128;
wire [0:0] s_129;
wire [1:0] s_130;
wire [3:0] s_131;
wire [7:0] s_132;
wire [0:0] s_133;
wire [0:0] s_134;
wire [0:0] s_135;
wire [0:0] s_136;
wire [0:0] s_137;
wire [0:0] s_138;
wire [0:0] s_139;
wire [1:0] s_140;
wire [0:0] s_141;
wire [0:0] s_142;
wire [0:0] s_143;
wire [1:0] s_144;
wire [0:0] s_145;
wire [0:0] s_146;
wire [0:0] s_147;
wire [0:0] s_148;
wire [0:0] s_149;
wire [0:0] s_150;
wire [1:0] s_151;
wire [0:0] s_152;
wire [0:0] s_153;
wire [0:0] s_154;
wire [0:0] s_155;
wire [0:0] s_156;
wire [0:0] s_157;
wire [2:0] s_158;
wire [0:0] s_159;
wire [0:0] s_160;
wire [1:0] s_161;
wire [0:0] s_162;
wire [0:0] s_163;
wire [0:0] s_164;
wire [1:0] s_165;
wire [3:0] s_166;
wire [0:0] s_167;
wire [0:0] s_168;
wire [0:0] s_169;
wire [0:0] s_170;
wire [0:0] s_171;
wire [0:0] s_172;
wire [0:0] s_173;
wire [1:0] s_174;
wire [0:0] s_175;
wire [0:0] s_176;
wire [0:0] s_177;
wire [1:0] s_178;
wire [0:0] s_179;
wire [0:0] s_180;
wire [0:0] s_181;
wire [0:0] s_182;
wire [0:0] s_183;
wire [0:0] s_184;
wire [1:0] s_185;
wire [0:0] s_186;
wire [0:0] s_187;
wire [0:0] s_188;
wire [0:0] s_189;
wire [0:0] s_190;
wire [2:0] s_191;
wire [0:0] s_192;
wire [0:0] s_193;
wire [1:0] s_194;
wire [1:0] s_195;
wire [1:0] s_196;
wire [3:0] s_197;
wire [0:0] s_198;
wire [0:0] s_199;
wire [2:0] s_200;
wire [2:0] s_201;
wire [2:0] s_202;
wire [0:0] s_203;
wire [4:0] s_204;
wire [0:0] s_205;
wire [0:0] s_206;
wire [3:0] s_207;
wire [0:0] s_208;
wire [0:0] s_209;
wire [2:0] s_210;
wire [0:0] s_211;
wire [0:0] s_212;
wire [1:0] s_213;
wire [0:0] s_214;
wire [0:0] s_215;
wire [0:0] s_216;
wire [1:0] s_217;
wire [3:0] s_218;
wire [7:0] s_219;
wire [15:0] s_220;
wire [0:0] s_221;
wire [0:0] s_222;
wire [0:0] s_223;
wire [0:0] s_224;
wire [0:0] s_225;
wire [0:0] s_226;
wire [0:0] s_227;
wire [1:0] s_228;
wire [0:0] s_229;
wire [0:0] s_230;
wire [0:0] s_231;
wire [1:0] s_232;
wire [0:0] s_233;
wire [0:0] s_234;
wire [0:0] s_235;
wire [0:0] s_236;
wire [0:0] s_237;
wire [0:0] s_238;
wire [1:0] s_239;
wire [0:0] s_240;
wire [0:0] s_241;
wire [0:0] s_242;
wire [0:0] s_243;
wire [0:0] s_244;
wire [0:0] s_245;
wire [2:0] s_246;
wire [0:0] s_247;
wire [0:0] s_248;
wire [1:0] s_249;
wire [0:0] s_250;
wire [0:0] s_251;
wire [0:0] s_252;
wire [1:0] s_253;
wire [3:0] s_254;
wire [0:0] s_255;
wire [0:0] s_256;
wire [0:0] s_257;
wire [0:0] s_258;
wire [0:0] s_259;
wire [0:0] s_260;
wire [0:0] s_261;
wire [1:0] s_262;
wire [0:0] s_263;
wire [0:0] s_264;
wire [0:0] s_265;
wire [1:0] s_266;
wire [0:0] s_267;
wire [0:0] s_268;
wire [0:0] s_269;
wire [0:0] s_270;
wire [0:0] s_271;
wire [0:0] s_272;
wire [1:0] s_273;
wire [0:0] s_274;
wire [0:0] s_275;
wire [0:0] s_276;
wire [0:0] s_277;
wire [0:0] s_278;
wire [2:0] s_279;
wire [0:0] s_280;
wire [0:0] s_281;
wire [1:0] s_282;
wire [1:0] s_283;
wire [1:0] s_284;
wire [0:0] s_285;
wire [3:0] s_286;
wire [0:0] s_287;
wire [0:0] s_288;
wire [2:0] s_289;
wire [0:0] s_290;
wire [0:0] s_291;
wire [1:0] s_292;
wire [0:0] s_293;
wire [0:0] s_294;
wire [0:0] s_295;
wire [1:0] s_296;
wire [3:0] s_297;
wire [7:0] s_298;
wire [0:0] s_299;
wire [0:0] s_300;
wire [0:0] s_301;
wire [0:0] s_302;
wire [0:0] s_303;
wire [0:0] s_304;
wire [0:0] s_305;
wire [1:0] s_306;
wire [0:0] s_307;
wire [0:0] s_308;
wire [0:0] s_309;
wire [1:0] s_310;
wire [0:0] s_311;
wire [0:0] s_312;
wire [0:0] s_313;
wire [0:0] s_314;
wire [0:0] s_315;
wire [0:0] s_316;
wire [1:0] s_317;
wire [0:0] s_318;
wire [0:0] s_319;
wire [0:0] s_320;
wire [0:0] s_321;
wire [0:0] s_322;
wire [0:0] s_323;
wire [2:0] s_324;
wire [0:0] s_325;
wire [0:0] s_326;
wire [1:0] s_327;
wire [0:0] s_328;
wire [0:0] s_329;
wire [0:0] s_330;
wire [1:0] s_331;
wire [3:0] s_332;
wire [0:0] s_333;
wire [0:0] s_334;
wire [0:0] s_335;
wire [0:0] s_336;
wire [0:0] s_337;
wire [0:0] s_338;
wire [0:0] s_339;
wire [1:0] s_340;
wire [0:0] s_341;
wire [0:0] s_342;
wire [0:0] s_343;
wire [1:0] s_344;
wire [0:0] s_345;
wire [0:0] s_346;
wire [0:0] s_347;
wire [0:0] s_348;
wire [0:0] s_349;
wire [0:0] s_350;
wire [1:0] s_351;
wire [0:0] s_352;
wire [0:0] s_353;
wire [0:0] s_354;
wire [0:0] s_355;
wire [0:0] s_356;
wire [2:0] s_357;
wire [0:0] s_358;
wire [0:0] s_359;
wire [1:0] s_360;
wire [1:0] s_361;
wire [1:0] s_362;
wire [3:0] s_363;
wire [0:0] s_364;
wire [0:0] s_365;
wire [2:0] s_366;
wire [2:0] s_367;
wire [2:0] s_368;
wire [4:0] s_369;
wire [0:0] s_370;
wire [0:0] s_371;
wire [3:0] s_372;
wire [3:0] s_373;
wire [3:0] s_374;
wire [0:0] s_375;
wire [23:0] s_376;
wire [0:0] s_377;
wire [0:0] s_378;
wire [0:0] s_379;
wire [0:0] s_380;
wire [0:0] s_381;
wire [0:0] s_382;
wire [0:0] s_383;
wire [0:0] s_384;
wire [0:0] s_385;
wire [5:0] s_386;
wire [0:0] s_387;
wire [0:0] s_388;
wire [0:0] s_389;
wire [23:0] s_390;
wire [0:0] s_391;
wire [31:0] s_392;
wire [8:0] s_393;
wire [0:0] s_394;
wire [7:0] s_395;
wire [7:0] s_396;
wire [7:0] s_397;
wire [7:0] s_398;
wire [7:0] s_399;
wire [7:0] s_400;
wire [6:0] s_401;
wire [22:0] s_402;
wire [0:0] s_403;
wire [0:0] s_404;
wire [7:0] s_405;
wire [0:0] s_406;
wire [0:0] s_407;
wire [0:0] s_408;
wire [23:0] s_409;
wire [0:0] s_410;
wire [0:0] s_411;
assign s_0 = s_411?s_1:s_6;
dq #(32, 5) dq_s_1 (clk, s_1, s_2);
assign s_2 = {s_3,s_5};
assign s_3 = s_4[31];
assign s_4 = to_float_a;
assign s_5 = 31'd2143289344;
assign s_6 = s_410?s_7:s_10;
dq #(32, 5) dq_s_7 (clk, s_7, s_8);
assign s_8 = {s_3,s_9};
assign s_9 = 31'd2139095040;
assign s_10 = s_408?s_11:s_14;
dq #(32, 5) dq_s_11 (clk, s_11, s_12);
assign s_12 = {s_3,s_13};
assign s_13 = 31'd0;
assign s_14 = s_403?s_15:s_392;
assign s_15 = {s_16,s_19};
dq #(9, 5) dq_s_16 (clk, s_16, s_17);
assign s_17 = {s_3,s_18};
assign s_18 = 8'd0;
assign s_19 = s_20[22:0];
dq #(24, 1) dq_s_20 (clk, s_20, s_21);
assign s_21 = s_391?s_22:s_390;
assign s_22 = s_23[24:1];
assign s_23 = s_377?s_24:s_376;
dq #(25, 1) dq_s_24 (clk, s_24, s_25);
assign s_25 = s_26 + s_375;
assign s_26 = s_27;
assign s_27 = s_28[31:8];
dq #(32, 1) dq_s_28 (clk, s_28, s_29);
assign s_29 = s_30 << s_34;
dq #(32, 1) dq_s_30 (clk, s_30, s_31);
dq #(32, 1) dq_s_31 (clk, s_31, s_32);
assign s_32 = s_3?s_33:s_4;
assign s_33 = -s_4;
dq #(6, 1) dq_s_34 (clk, s_34, s_35);
assign s_35 = {s_36,s_369};
assign s_36 = s_37 & s_203;
assign s_37 = s_38[4];
assign s_38 = {s_39,s_197};
assign s_39 = s_40 & s_119;
assign s_40 = s_41[3];
assign s_41 = {s_42,s_113};
assign s_42 = s_43 & s_79;
assign s_43 = s_44[2];
assign s_44 = {s_45,s_73};
assign s_45 = s_46 & s_61;
assign s_46 = s_47[1];
assign s_47 = {s_48,s_57};
assign s_48 = s_49 & s_55;
assign s_49 = ~s_50;
assign s_50 = s_51[1];
assign s_51 = s_52[3:2];
assign s_52 = s_53[7:4];
assign s_53 = s_54[15:8];
assign s_54 = s_31[31:16];
assign s_55 = ~s_56;
assign s_56 = s_51[0];
assign s_57 = s_58 & s_60;
assign s_58 = ~s_59;
assign s_59 = s_51[1];
assign s_60 = s_51[0];
assign s_61 = s_62[1];
assign s_62 = {s_63,s_69};
assign s_63 = s_64 & s_67;
assign s_64 = ~s_65;
assign s_65 = s_66[1];
assign s_66 = s_52[1:0];
assign s_67 = ~s_68;
assign s_68 = s_66[0];
assign s_69 = s_70 & s_72;
assign s_70 = ~s_71;
assign s_71 = s_66[1];
assign s_72 = s_66[0];
assign s_73 = {s_74,s_76};
assign s_74 = s_46 & s_75;
assign s_75 = ~s_61;
assign s_76 = s_46?s_77:s_78;
assign s_77 = s_62[0:0];
assign s_78 = s_47[0:0];
assign s_79 = s_80[2];
assign s_80 = {s_81,s_107};
assign s_81 = s_82 & s_95;
assign s_82 = s_83[1];
assign s_83 = {s_84,s_91};
assign s_84 = s_85 & s_89;
assign s_85 = ~s_86;
assign s_86 = s_87[1];
assign s_87 = s_88[3:2];
assign s_88 = s_53[3:0];
assign s_89 = ~s_90;
assign s_90 = s_87[0];
assign s_91 = s_92 & s_94;
assign s_92 = ~s_93;
assign s_93 = s_87[1];
assign s_94 = s_87[0];
assign s_95 = s_96[1];
assign s_96 = {s_97,s_103};
assign s_97 = s_98 & s_101;
assign s_98 = ~s_99;
assign s_99 = s_100[1];
assign s_100 = s_88[1:0];
assign s_101 = ~s_102;
assign s_102 = s_100[0];
assign s_103 = s_104 & s_106;
assign s_104 = ~s_105;
assign s_105 = s_100[1];
assign s_106 = s_100[0];
assign s_107 = {s_108,s_110};
assign s_108 = s_82 & s_109;
assign s_109 = ~s_95;
assign s_110 = s_82?s_111:s_112;
assign s_111 = s_96[0:0];
assign s_112 = s_83[0:0];
assign s_113 = {s_114,s_116};
assign s_114 = s_43 & s_115;
assign s_115 = ~s_79;
assign s_116 = s_43?s_117:s_118;
assign s_117 = s_80[1:0];
assign s_118 = s_44[1:0];
assign s_119 = s_120[3];
assign s_120 = {s_121,s_191};
assign s_121 = s_122 & s_157;
assign s_122 = s_123[2];
assign s_123 = {s_124,s_151};
assign s_124 = s_125 & s_139;
assign s_125 = s_126[1];
assign s_126 = {s_127,s_135};
assign s_127 = s_128 & s_133;
assign s_128 = ~s_129;
assign s_129 = s_130[1];
assign s_130 = s_131[3:2];
assign s_131 = s_132[7:4];
assign s_132 = s_54[7:0];
assign s_133 = ~s_134;
assign s_134 = s_130[0];
assign s_135 = s_136 & s_138;
assign s_136 = ~s_137;
assign s_137 = s_130[1];
assign s_138 = s_130[0];
assign s_139 = s_140[1];
assign s_140 = {s_141,s_147};
assign s_141 = s_142 & s_145;
assign s_142 = ~s_143;
assign s_143 = s_144[1];
assign s_144 = s_131[1:0];
assign s_145 = ~s_146;
assign s_146 = s_144[0];
assign s_147 = s_148 & s_150;
assign s_148 = ~s_149;
assign s_149 = s_144[1];
assign s_150 = s_144[0];
assign s_151 = {s_152,s_154};
assign s_152 = s_125 & s_153;
assign s_153 = ~s_139;
assign s_154 = s_125?s_155:s_156;
assign s_155 = s_140[0:0];
assign s_156 = s_126[0:0];
assign s_157 = s_158[2];
assign s_158 = {s_159,s_185};
assign s_159 = s_160 & s_173;
assign s_160 = s_161[1];
assign s_161 = {s_162,s_169};
assign s_162 = s_163 & s_167;
assign s_163 = ~s_164;
assign s_164 = s_165[1];
assign s_165 = s_166[3:2];
assign s_166 = s_132[3:0];
assign s_167 = ~s_168;
assign s_168 = s_165[0];
assign s_169 = s_170 & s_172;
assign s_170 = ~s_171;
assign s_171 = s_165[1];
assign s_172 = s_165[0];
assign s_173 = s_174[1];
assign s_174 = {s_175,s_181};
assign s_175 = s_176 & s_179;
assign s_176 = ~s_177;
assign s_177 = s_178[1];
assign s_178 = s_166[1:0];
assign s_179 = ~s_180;
assign s_180 = s_178[0];
assign s_181 = s_182 & s_184;
assign s_182 = ~s_183;
assign s_183 = s_178[1];
assign s_184 = s_178[0];
assign s_185 = {s_186,s_188};
assign s_186 = s_160 & s_187;
assign s_187 = ~s_173;
assign s_188 = s_160?s_189:s_190;
assign s_189 = s_174[0:0];
assign s_190 = s_161[0:0];
assign s_191 = {s_192,s_194};
assign s_192 = s_122 & s_193;
assign s_193 = ~s_157;
assign s_194 = s_122?s_195:s_196;
assign s_195 = s_158[1:0];
assign s_196 = s_123[1:0];
assign s_197 = {s_198,s_200};
assign s_198 = s_40 & s_199;
assign s_199 = ~s_119;
assign s_200 = s_40?s_201:s_202;
assign s_201 = s_120[2:0];
assign s_202 = s_41[2:0];
assign s_203 = s_204[4];
assign s_204 = {s_205,s_363};
assign s_205 = s_206 & s_285;
assign s_206 = s_207[3];
assign s_207 = {s_208,s_279};
assign s_208 = s_209 & s_245;
assign s_209 = s_210[2];
assign s_210 = {s_211,s_239};
assign s_211 = s_212 & s_227;
assign s_212 = s_213[1];
assign s_213 = {s_214,s_223};
assign s_214 = s_215 & s_221;
assign s_215 = ~s_216;
assign s_216 = s_217[1];
assign s_217 = s_218[3:2];
assign s_218 = s_219[7:4];
assign s_219 = s_220[15:8];
assign s_220 = s_31[15:0];
assign s_221 = ~s_222;
assign s_222 = s_217[0];
assign s_223 = s_224 & s_226;
assign s_224 = ~s_225;
assign s_225 = s_217[1];
assign s_226 = s_217[0];
assign s_227 = s_228[1];
assign s_228 = {s_229,s_235};
assign s_229 = s_230 & s_233;
assign s_230 = ~s_231;
assign s_231 = s_232[1];
assign s_232 = s_218[1:0];
assign s_233 = ~s_234;
assign s_234 = s_232[0];
assign s_235 = s_236 & s_238;
assign s_236 = ~s_237;
assign s_237 = s_232[1];
assign s_238 = s_232[0];
assign s_239 = {s_240,s_242};
assign s_240 = s_212 & s_241;
assign s_241 = ~s_227;
assign s_242 = s_212?s_243:s_244;
assign s_243 = s_228[0:0];
assign s_244 = s_213[0:0];
assign s_245 = s_246[2];
assign s_246 = {s_247,s_273};
assign s_247 = s_248 & s_261;
assign s_248 = s_249[1];
assign s_249 = {s_250,s_257};
assign s_250 = s_251 & s_255;
assign s_251 = ~s_252;
assign s_252 = s_253[1];
assign s_253 = s_254[3:2];
assign s_254 = s_219[3:0];
assign s_255 = ~s_256;
assign s_256 = s_253[0];
assign s_257 = s_258 & s_260;
assign s_258 = ~s_259;
assign s_259 = s_253[1];
assign s_260 = s_253[0];
assign s_261 = s_262[1];
assign s_262 = {s_263,s_269};
assign s_263 = s_264 & s_267;
assign s_264 = ~s_265;
assign s_265 = s_266[1];
assign s_266 = s_254[1:0];
assign s_267 = ~s_268;
assign s_268 = s_266[0];
assign s_269 = s_270 & s_272;
assign s_270 = ~s_271;
assign s_271 = s_266[1];
assign s_272 = s_266[0];
assign s_273 = {s_274,s_276};
assign s_274 = s_248 & s_275;
assign s_275 = ~s_261;
assign s_276 = s_248?s_277:s_278;
assign s_277 = s_262[0:0];
assign s_278 = s_249[0:0];
assign s_279 = {s_280,s_282};
assign s_280 = s_209 & s_281;
assign s_281 = ~s_245;
assign s_282 = s_209?s_283:s_284;
assign s_283 = s_246[1:0];
assign s_284 = s_210[1:0];
assign s_285 = s_286[3];
assign s_286 = {s_287,s_357};
assign s_287 = s_288 & s_323;
assign s_288 = s_289[2];
assign s_289 = {s_290,s_317};
assign s_290 = s_291 & s_305;
assign s_291 = s_292[1];
assign s_292 = {s_293,s_301};
assign s_293 = s_294 & s_299;
assign s_294 = ~s_295;
assign s_295 = s_296[1];
assign s_296 = s_297[3:2];
assign s_297 = s_298[7:4];
assign s_298 = s_220[7:0];
assign s_299 = ~s_300;
assign s_300 = s_296[0];
assign s_301 = s_302 & s_304;
assign s_302 = ~s_303;
assign s_303 = s_296[1];
assign s_304 = s_296[0];
assign s_305 = s_306[1];
assign s_306 = {s_307,s_313};
assign s_307 = s_308 & s_311;
assign s_308 = ~s_309;
assign s_309 = s_310[1];
assign s_310 = s_297[1:0];
assign s_311 = ~s_312;
assign s_312 = s_310[0];
assign s_313 = s_314 & s_316;
assign s_314 = ~s_315;
assign s_315 = s_310[1];
assign s_316 = s_310[0];
assign s_317 = {s_318,s_320};
assign s_318 = s_291 & s_319;
assign s_319 = ~s_305;
assign s_320 = s_291?s_321:s_322;
assign s_321 = s_306[0:0];
assign s_322 = s_292[0:0];
assign s_323 = s_324[2];
assign s_324 = {s_325,s_351};
assign s_325 = s_326 & s_339;
assign s_326 = s_327[1];
assign s_327 = {s_328,s_335};
assign s_328 = s_329 & s_333;
assign s_329 = ~s_330;
assign s_330 = s_331[1];
assign s_331 = s_332[3:2];
assign s_332 = s_298[3:0];
assign s_333 = ~s_334;
assign s_334 = s_331[0];
assign s_335 = s_336 & s_338;
assign s_336 = ~s_337;
assign s_337 = s_331[1];
assign s_338 = s_331[0];
assign s_339 = s_340[1];
assign s_340 = {s_341,s_347};
assign s_341 = s_342 & s_345;
assign s_342 = ~s_343;
assign s_343 = s_344[1];
assign s_344 = s_332[1:0];
assign s_345 = ~s_346;
assign s_346 = s_344[0];
assign s_347 = s_348 & s_350;
assign s_348 = ~s_349;
assign s_349 = s_344[1];
assign s_350 = s_344[0];
assign s_351 = {s_352,s_354};
assign s_352 = s_326 & s_353;
assign s_353 = ~s_339;
assign s_354 = s_326?s_355:s_356;
assign s_355 = s_340[0:0];
assign s_356 = s_327[0:0];
assign s_357 = {s_358,s_360};
assign s_358 = s_288 & s_359;
assign s_359 = ~s_323;
assign s_360 = s_288?s_361:s_362;
assign s_361 = s_324[1:0];
assign s_362 = s_289[1:0];
assign s_363 = {s_364,s_366};
assign s_364 = s_206 & s_365;
assign s_365 = ~s_285;
assign s_366 = s_206?s_367:s_368;
assign s_367 = s_286[2:0];
assign s_368 = s_207[2:0];
assign s_369 = {s_370,s_372};
assign s_370 = s_37 & s_371;
assign s_371 = ~s_203;
assign s_372 = s_37?s_373:s_374;
assign s_373 = s_204[3:0];
assign s_374 = s_38[3:0];
assign s_375 = 1'd1;
dq #(24, 1) dq_s_376 (clk, s_376, s_27);
assign s_377 = s_378 & s_380;
dq #(1, 1) dq_s_378 (clk, s_378, s_379);
assign s_379 = s_28[7];
assign s_380 = s_381 | s_388;
assign s_381 = s_382 | s_384;
dq #(1, 1) dq_s_382 (clk, s_382, s_383);
assign s_383 = s_28[6];
dq #(1, 1) dq_s_384 (clk, s_384, s_385);
assign s_385 = s_386 != s_387;
assign s_386 = s_28[5:0];
assign s_387 = 1'd0;
dq #(1, 1) dq_s_388 (clk, s_388, s_389);
assign s_389 = s_27[0];
assign s_390 = s_23[23:0];
assign s_391 = s_23[24];
assign s_392 = {s_393,s_402};
assign s_393 = {s_394,s_395};
dq #(1, 5) dq_s_394 (clk, s_394, s_3);
assign s_395 = s_396 + s_401;
dq #(8, 1) dq_s_396 (clk, s_396, s_397);
assign s_397 = s_398 + s_391;
dq #(8, 2) dq_s_398 (clk, s_398, s_399);
assign s_399 = s_400 - s_34;
assign s_400 = 8'd31;
assign s_401 = 7'd127;
assign s_402 = s_20[22:0];
assign s_403 = s_404 & s_406;
assign s_404 = s_396 == s_405;
assign s_405 = -8'd126;
assign s_406 = ~s_407;
assign s_407 = s_20[23];
assign s_408 = s_20 == s_409;
assign s_409 = 24'd0;
assign s_410 = 1'd0;
assign s_411 = 1'd0;
assign to_float_z = s_0;
endmodule | module to_float(clk, to_float_a, to_float_z); |
input clk;
input [31:0] to_float_a;
output [31:0] to_float_z;
wire [31:0] s_0;
wire [31:0] s_1;
wire [31:0] s_2;
wire [0:0] s_3;
wire [31:0] s_4;
wire [30:0] s_5;
wire [31:0] s_6;
wire [31:0] s_7;
wire [31:0] s_8;
wire [30:0] s_9;
wire [31:0] s_10;
wire [31:0] s_11;
wire [31:0] s_12;
wire [30:0] s_13;
wire [31:0] s_14;
wire [31:0] s_15;
wire [8:0] s_16;
wire [8:0] s_17;
wire [7:0] s_18;
wire [22:0] s_19;
wire [23:0] s_20;
wire [23:0] s_21;
wire [23:0] s_22;
wire [24:0] s_23;
wire [24:0] s_24;
wire [24:0] s_25;
wire [24:0] s_26;
wire [23:0] s_27;
wire [31:0] s_28;
wire [31:0] s_29;
wire [31:0] s_30;
wire [31:0] s_31;
wire [31:0] s_32;
wire [31:0] s_33;
wire [5:0] s_34;
wire [5:0] s_35;
wire [0:0] s_36;
wire [0:0] s_37;
wire [4:0] s_38;
wire [0:0] s_39;
wire [0:0] s_40;
wire [3:0] s_41;
wire [0:0] s_42;
wire [0:0] s_43;
wire [2:0] s_44;
wire [0:0] s_45;
wire [0:0] s_46;
wire [1:0] s_47;
wire [0:0] s_48;
wire [0:0] s_49;
wire [0:0] s_50;
wire [1:0] s_51;
wire [3:0] s_52;
wire [7:0] s_53;
wire [15:0] s_54;
wire [0:0] s_55;
wire [0:0] s_56;
wire [0:0] s_57;
wire [0:0] s_58;
wire [0:0] s_59;
wire [0:0] s_60;
wire [0:0] s_61;
wire [1:0] s_62;
wire [0:0] s_63;
wire [0:0] s_64;
wire [0:0] s_65;
wire [1:0] s_66;
wire [0:0] s_67;
wire [0:0] s_68;
wire [0:0] s_69;
wire [0:0] s_70;
wire [0:0] s_71;
wire [0:0] s_72;
wire [1:0] s_73;
wire [0:0] s_74;
wire [0:0] s_75;
wire [0:0] s_76;
wire [0:0] s_77;
wire [0:0] s_78;
wire [0:0] s_79;
wire [2:0] s_80;
wire [0:0] s_81;
wire [0:0] s_82;
wire [1:0] s_83;
wire [0:0] s_84;
wire [0:0] s_85;
wire [0:0] s_86;
wire [1:0] s_87;
wire [3:0] s_88;
wire [0:0] s_89;
wire [0:0] s_90;
wire [0:0] s_91;
wire [0:0] s_92;
wire [0:0] s_93;
wire [0:0] s_94;
wire [0:0] s_95;
wire [1:0] s_96;
wire [0:0] s_97;
wire [0:0] s_98;
wire [0:0] s_99;
wire [1:0] s_100;
wire [0:0] s_101;
wire [0:0] s_102;
wire [0:0] s_103;
wire [0:0] s_104;
wire [0:0] s_105;
wire [0:0] s_106;
wire [1:0] s_107;
wire [0:0] s_108;
wire [0:0] s_109;
wire [0:0] s_110;
wire [0:0] s_111;
wire [0:0] s_112;
wire [2:0] s_113;
wire [0:0] s_114;
wire [0:0] s_115;
wire [1:0] s_116;
wire [1:0] s_117;
wire [1:0] s_118;
wire [0:0] s_119;
wire [3:0] s_120;
wire [0:0] s_121;
wire [0:0] s_122;
wire [2:0] s_123;
wire [0:0] s_124;
wire [0:0] s_125;
wire [1:0] s_126;
wire [0:0] s_127;
wire [0:0] s_128;
wire [0:0] s_129;
wire [1:0] s_130;
wire [3:0] s_131;
wire [7:0] s_132;
wire [0:0] s_133;
wire [0:0] s_134;
wire [0:0] s_135;
wire [0:0] s_136;
wire [0:0] s_137;
wire [0:0] s_138;
wire [0:0] s_139;
wire [1:0] s_140;
wire [0:0] s_141;
wire [0:0] s_142;
wire [0:0] s_143;
wire [1:0] s_144;
wire [0:0] s_145;
wire [0:0] s_146;
wire [0:0] s_147;
wire [0:0] s_148;
wire [0:0] s_149;
wire [0:0] s_150;
wire [1:0] s_151;
wire [0:0] s_152;
wire [0:0] s_153;
wire [0:0] s_154;
wire [0:0] s_155;
wire [0:0] s_156;
wire [0:0] s_157;
wire [2:0] s_158;
wire [0:0] s_159;
wire [0:0] s_160;
wire [1:0] s_161;
wire [0:0] s_162;
wire [0:0] s_163;
wire [0:0] s_164;
wire [1:0] s_165;
wire [3:0] s_166;
wire [0:0] s_167;
wire [0:0] s_168;
wire [0:0] s_169;
wire [0:0] s_170;
wire [0:0] s_171;
wire [0:0] s_172;
wire [0:0] s_173;
wire [1:0] s_174;
wire [0:0] s_175;
wire [0:0] s_176;
wire [0:0] s_177;
wire [1:0] s_178;
wire [0:0] s_179;
wire [0:0] s_180;
wire [0:0] s_181;
wire [0:0] s_182;
wire [0:0] s_183;
wire [0:0] s_184;
wire [1:0] s_185;
wire [0:0] s_186;
wire [0:0] s_187;
wire [0:0] s_188;
wire [0:0] s_189;
wire [0:0] s_190;
wire [2:0] s_191;
wire [0:0] s_192;
wire [0:0] s_193;
wire [1:0] s_194;
wire [1:0] s_195;
wire [1:0] s_196;
wire [3:0] s_197;
wire [0:0] s_198;
wire [0:0] s_199;
wire [2:0] s_200;
wire [2:0] s_201;
wire [2:0] s_202;
wire [0:0] s_203;
wire [4:0] s_204;
wire [0:0] s_205;
wire [0:0] s_206;
wire [3:0] s_207;
wire [0:0] s_208;
wire [0:0] s_209;
wire [2:0] s_210;
wire [0:0] s_211;
wire [0:0] s_212;
wire [1:0] s_213;
wire [0:0] s_214;
wire [0:0] s_215;
wire [0:0] s_216;
wire [1:0] s_217;
wire [3:0] s_218;
wire [7:0] s_219;
wire [15:0] s_220;
wire [0:0] s_221;
wire [0:0] s_222;
wire [0:0] s_223;
wire [0:0] s_224;
wire [0:0] s_225;
wire [0:0] s_226;
wire [0:0] s_227;
wire [1:0] s_228;
wire [0:0] s_229;
wire [0:0] s_230;
wire [0:0] s_231;
wire [1:0] s_232;
wire [0:0] s_233;
wire [0:0] s_234;
wire [0:0] s_235;
wire [0:0] s_236;
wire [0:0] s_237;
wire [0:0] s_238;
wire [1:0] s_239;
wire [0:0] s_240;
wire [0:0] s_241;
wire [0:0] s_242;
wire [0:0] s_243;
wire [0:0] s_244;
wire [0:0] s_245;
wire [2:0] s_246;
wire [0:0] s_247;
wire [0:0] s_248;
wire [1:0] s_249;
wire [0:0] s_250;
wire [0:0] s_251;
wire [0:0] s_252;
wire [1:0] s_253;
wire [3:0] s_254;
wire [0:0] s_255;
wire [0:0] s_256;
wire [0:0] s_257;
wire [0:0] s_258;
wire [0:0] s_259;
wire [0:0] s_260;
wire [0:0] s_261;
wire [1:0] s_262;
wire [0:0] s_263;
wire [0:0] s_264;
wire [0:0] s_265;
wire [1:0] s_266;
wire [0:0] s_267;
wire [0:0] s_268;
wire [0:0] s_269;
wire [0:0] s_270;
wire [0:0] s_271;
wire [0:0] s_272;
wire [1:0] s_273;
wire [0:0] s_274;
wire [0:0] s_275;
wire [0:0] s_276;
wire [0:0] s_277;
wire [0:0] s_278;
wire [2:0] s_279;
wire [0:0] s_280;
wire [0:0] s_281;
wire [1:0] s_282;
wire [1:0] s_283;
wire [1:0] s_284;
wire [0:0] s_285;
wire [3:0] s_286;
wire [0:0] s_287;
wire [0:0] s_288;
wire [2:0] s_289;
wire [0:0] s_290;
wire [0:0] s_291;
wire [1:0] s_292;
wire [0:0] s_293;
wire [0:0] s_294;
wire [0:0] s_295;
wire [1:0] s_296;
wire [3:0] s_297;
wire [7:0] s_298;
wire [0:0] s_299;
wire [0:0] s_300;
wire [0:0] s_301;
wire [0:0] s_302;
wire [0:0] s_303;
wire [0:0] s_304;
wire [0:0] s_305;
wire [1:0] s_306;
wire [0:0] s_307;
wire [0:0] s_308;
wire [0:0] s_309;
wire [1:0] s_310;
wire [0:0] s_311;
wire [0:0] s_312;
wire [0:0] s_313;
wire [0:0] s_314;
wire [0:0] s_315;
wire [0:0] s_316;
wire [1:0] s_317;
wire [0:0] s_318;
wire [0:0] s_319;
wire [0:0] s_320;
wire [0:0] s_321;
wire [0:0] s_322;
wire [0:0] s_323;
wire [2:0] s_324;
wire [0:0] s_325;
wire [0:0] s_326;
wire [1:0] s_327;
wire [0:0] s_328;
wire [0:0] s_329;
wire [0:0] s_330;
wire [1:0] s_331;
wire [3:0] s_332;
wire [0:0] s_333;
wire [0:0] s_334;
wire [0:0] s_335;
wire [0:0] s_336;
wire [0:0] s_337;
wire [0:0] s_338;
wire [0:0] s_339;
wire [1:0] s_340;
wire [0:0] s_341;
wire [0:0] s_342;
wire [0:0] s_343;
wire [1:0] s_344;
wire [0:0] s_345;
wire [0:0] s_346;
wire [0:0] s_347;
wire [0:0] s_348;
wire [0:0] s_349;
wire [0:0] s_350;
wire [1:0] s_351;
wire [0:0] s_352;
wire [0:0] s_353;
wire [0:0] s_354;
wire [0:0] s_355;
wire [0:0] s_356;
wire [2:0] s_357;
wire [0:0] s_358;
wire [0:0] s_359;
wire [1:0] s_360;
wire [1:0] s_361;
wire [1:0] s_362;
wire [3:0] s_363;
wire [0:0] s_364;
wire [0:0] s_365;
wire [2:0] s_366;
wire [2:0] s_367;
wire [2:0] s_368;
wire [4:0] s_369;
wire [0:0] s_370;
wire [0:0] s_371;
wire [3:0] s_372;
wire [3:0] s_373;
wire [3:0] s_374;
wire [0:0] s_375;
wire [23:0] s_376;
wire [0:0] s_377;
wire [0:0] s_378;
wire [0:0] s_379;
wire [0:0] s_380;
wire [0:0] s_381;
wire [0:0] s_382;
wire [0:0] s_383;
wire [0:0] s_384;
wire [0:0] s_385;
wire [5:0] s_386;
wire [0:0] s_387;
wire [0:0] s_388;
wire [0:0] s_389;
wire [23:0] s_390;
wire [0:0] s_391;
wire [31:0] s_392;
wire [8:0] s_393;
wire [0:0] s_394;
wire [7:0] s_395;
wire [7:0] s_396;
wire [7:0] s_397;
wire [7:0] s_398;
wire [7:0] s_399;
wire [7:0] s_400;
wire [6:0] s_401;
wire [22:0] s_402;
wire [0:0] s_403;
wire [0:0] s_404;
wire [7:0] s_405;
wire [0:0] s_406;
wire [0:0] s_407;
wire [0:0] s_408;
wire [23:0] s_409;
wire [0:0] s_410;
wire [0:0] s_411;
assign s_0 = s_411?s_1:s_6;
dq #(32, 5) dq_s_1 (clk, s_1, s_2);
assign s_2 = {s_3,s_5};
assign s_3 = s_4[31];
assign s_4 = to_float_a;
assign s_5 = 31'd2143289344;
assign s_6 = s_410?s_7:s_10;
dq #(32, 5) dq_s_7 (clk, s_7, s_8);
assign s_8 = {s_3,s_9};
assign s_9 = 31'd2139095040;
assign s_10 = s_408?s_11:s_14;
dq #(32, 5) dq_s_11 (clk, s_11, s_12);
assign s_12 = {s_3,s_13};
assign s_13 = 31'd0;
assign s_14 = s_403?s_15:s_392;
assign s_15 = {s_16,s_19};
dq #(9, 5) dq_s_16 (clk, s_16, s_17);
assign s_17 = {s_3,s_18};
assign s_18 = 8'd0;
assign s_19 = s_20[22:0];
dq #(24, 1) dq_s_20 (clk, s_20, s_21);
assign s_21 = s_391?s_22:s_390;
assign s_22 = s_23[24:1];
assign s_23 = s_377?s_24:s_376;
dq #(25, 1) dq_s_24 (clk, s_24, s_25);
assign s_25 = s_26 + s_375;
assign s_26 = s_27;
assign s_27 = s_28[31:8];
dq #(32, 1) dq_s_28 (clk, s_28, s_29);
assign s_29 = s_30 << s_34;
dq #(32, 1) dq_s_30 (clk, s_30, s_31);
dq #(32, 1) dq_s_31 (clk, s_31, s_32);
assign s_32 = s_3?s_33:s_4;
assign s_33 = -s_4;
dq #(6, 1) dq_s_34 (clk, s_34, s_35);
assign s_35 = {s_36,s_369};
assign s_36 = s_37 & s_203;
assign s_37 = s_38[4];
assign s_38 = {s_39,s_197};
assign s_39 = s_40 & s_119;
assign s_40 = s_41[3];
assign s_41 = {s_42,s_113};
assign s_42 = s_43 & s_79;
assign s_43 = s_44[2];
assign s_44 = {s_45,s_73};
assign s_45 = s_46 & s_61;
assign s_46 = s_47[1];
assign s_47 = {s_48,s_57};
assign s_48 = s_49 & s_55;
assign s_49 = ~s_50;
assign s_50 = s_51[1];
assign s_51 = s_52[3:2];
assign s_52 = s_53[7:4];
assign s_53 = s_54[15:8];
assign s_54 = s_31[31:16];
assign s_55 = ~s_56;
assign s_56 = s_51[0];
assign s_57 = s_58 & s_60;
assign s_58 = ~s_59;
assign s_59 = s_51[1];
assign s_60 = s_51[0];
assign s_61 = s_62[1];
assign s_62 = {s_63,s_69};
assign s_63 = s_64 & s_67;
assign s_64 = ~s_65;
assign s_65 = s_66[1];
assign s_66 = s_52[1:0];
assign s_67 = ~s_68;
assign s_68 = s_66[0];
assign s_69 = s_70 & s_72;
assign s_70 = ~s_71;
assign s_71 = s_66[1];
assign s_72 = s_66[0];
assign s_73 = {s_74,s_76};
assign s_74 = s_46 & s_75;
assign s_75 = ~s_61;
assign s_76 = s_46?s_77:s_78;
assign s_77 = s_62[0:0];
assign s_78 = s_47[0:0];
assign s_79 = s_80[2];
assign s_80 = {s_81,s_107};
assign s_81 = s_82 & s_95;
assign s_82 = s_83[1];
assign s_83 = {s_84,s_91};
assign s_84 = s_85 & s_89;
assign s_85 = ~s_86;
assign s_86 = s_87[1];
assign s_87 = s_88[3:2];
assign s_88 = s_53[3:0];
assign s_89 = ~s_90;
assign s_90 = s_87[0];
assign s_91 = s_92 & s_94;
assign s_92 = ~s_93;
assign s_93 = s_87[1];
assign s_94 = s_87[0];
assign s_95 = s_96[1];
assign s_96 = {s_97,s_103};
assign s_97 = s_98 & s_101;
assign s_98 = ~s_99;
assign s_99 = s_100[1];
assign s_100 = s_88[1:0];
assign s_101 = ~s_102;
assign s_102 = s_100[0];
assign s_103 = s_104 & s_106;
assign s_104 = ~s_105;
assign s_105 = s_100[1];
assign s_106 = s_100[0];
assign s_107 = {s_108,s_110};
assign s_108 = s_82 & s_109;
assign s_109 = ~s_95;
assign s_110 = s_82?s_111:s_112;
assign s_111 = s_96[0:0];
assign s_112 = s_83[0:0];
assign s_113 = {s_114,s_116};
assign s_114 = s_43 & s_115;
assign s_115 = ~s_79;
assign s_116 = s_43?s_117:s_118;
assign s_117 = s_80[1:0];
assign s_118 = s_44[1:0];
assign s_119 = s_120[3];
assign s_120 = {s_121,s_191};
assign s_121 = s_122 & s_157;
assign s_122 = s_123[2];
assign s_123 = {s_124,s_151};
assign s_124 = s_125 & s_139;
assign s_125 = s_126[1];
assign s_126 = {s_127,s_135};
assign s_127 = s_128 & s_133;
assign s_128 = ~s_129;
assign s_129 = s_130[1];
assign s_130 = s_131[3:2];
assign s_131 = s_132[7:4];
assign s_132 = s_54[7:0];
assign s_133 = ~s_134;
assign s_134 = s_130[0];
assign s_135 = s_136 & s_138;
assign s_136 = ~s_137;
assign s_137 = s_130[1];
assign s_138 = s_130[0];
assign s_139 = s_140[1];
assign s_140 = {s_141,s_147};
assign s_141 = s_142 & s_145;
assign s_142 = ~s_143;
assign s_143 = s_144[1];
assign s_144 = s_131[1:0];
assign s_145 = ~s_146;
assign s_146 = s_144[0];
assign s_147 = s_148 & s_150;
assign s_148 = ~s_149;
assign s_149 = s_144[1];
assign s_150 = s_144[0];
assign s_151 = {s_152,s_154};
assign s_152 = s_125 & s_153;
assign s_153 = ~s_139;
assign s_154 = s_125?s_155:s_156;
assign s_155 = s_140[0:0];
assign s_156 = s_126[0:0];
assign s_157 = s_158[2];
assign s_158 = {s_159,s_185};
assign s_159 = s_160 & s_173;
assign s_160 = s_161[1];
assign s_161 = {s_162,s_169};
assign s_162 = s_163 & s_167;
assign s_163 = ~s_164;
assign s_164 = s_165[1];
assign s_165 = s_166[3:2];
assign s_166 = s_132[3:0];
assign s_167 = ~s_168;
assign s_168 = s_165[0];
assign s_169 = s_170 & s_172;
assign s_170 = ~s_171;
assign s_171 = s_165[1];
assign s_172 = s_165[0];
assign s_173 = s_174[1];
assign s_174 = {s_175,s_181};
assign s_175 = s_176 & s_179;
assign s_176 = ~s_177;
assign s_177 = s_178[1];
assign s_178 = s_166[1:0];
assign s_179 = ~s_180;
assign s_180 = s_178[0];
assign s_181 = s_182 & s_184;
assign s_182 = ~s_183;
assign s_183 = s_178[1];
assign s_184 = s_178[0];
assign s_185 = {s_186,s_188};
assign s_186 = s_160 & s_187;
assign s_187 = ~s_173;
assign s_188 = s_160?s_189:s_190;
assign s_189 = s_174[0:0];
assign s_190 = s_161[0:0];
assign s_191 = {s_192,s_194};
assign s_192 = s_122 & s_193;
assign s_193 = ~s_157;
assign s_194 = s_122?s_195:s_196;
assign s_195 = s_158[1:0];
assign s_196 = s_123[1:0];
assign s_197 = {s_198,s_200};
assign s_198 = s_40 & s_199;
assign s_199 = ~s_119;
assign s_200 = s_40?s_201:s_202;
assign s_201 = s_120[2:0];
assign s_202 = s_41[2:0];
assign s_203 = s_204[4];
assign s_204 = {s_205,s_363};
assign s_205 = s_206 & s_285;
assign s_206 = s_207[3];
assign s_207 = {s_208,s_279};
assign s_208 = s_209 & s_245;
assign s_209 = s_210[2];
assign s_210 = {s_211,s_239};
assign s_211 = s_212 & s_227;
assign s_212 = s_213[1];
assign s_213 = {s_214,s_223};
assign s_214 = s_215 & s_221;
assign s_215 = ~s_216;
assign s_216 = s_217[1];
assign s_217 = s_218[3:2];
assign s_218 = s_219[7:4];
assign s_219 = s_220[15:8];
assign s_220 = s_31[15:0];
assign s_221 = ~s_222;
assign s_222 = s_217[0];
assign s_223 = s_224 & s_226;
assign s_224 = ~s_225;
assign s_225 = s_217[1];
assign s_226 = s_217[0];
assign s_227 = s_228[1];
assign s_228 = {s_229,s_235};
assign s_229 = s_230 & s_233;
assign s_230 = ~s_231;
assign s_231 = s_232[1];
assign s_232 = s_218[1:0];
assign s_233 = ~s_234;
assign s_234 = s_232[0];
assign s_235 = s_236 & s_238;
assign s_236 = ~s_237;
assign s_237 = s_232[1];
assign s_238 = s_232[0];
assign s_239 = {s_240,s_242};
assign s_240 = s_212 & s_241;
assign s_241 = ~s_227;
assign s_242 = s_212?s_243:s_244;
assign s_243 = s_228[0:0];
assign s_244 = s_213[0:0];
assign s_245 = s_246[2];
assign s_246 = {s_247,s_273};
assign s_247 = s_248 & s_261;
assign s_248 = s_249[1];
assign s_249 = {s_250,s_257};
assign s_250 = s_251 & s_255;
assign s_251 = ~s_252;
assign s_252 = s_253[1];
assign s_253 = s_254[3:2];
assign s_254 = s_219[3:0];
assign s_255 = ~s_256;
assign s_256 = s_253[0];
assign s_257 = s_258 & s_260;
assign s_258 = ~s_259;
assign s_259 = s_253[1];
assign s_260 = s_253[0];
assign s_261 = s_262[1];
assign s_262 = {s_263,s_269};
assign s_263 = s_264 & s_267;
assign s_264 = ~s_265;
assign s_265 = s_266[1];
assign s_266 = s_254[1:0];
assign s_267 = ~s_268;
assign s_268 = s_266[0];
assign s_269 = s_270 & s_272;
assign s_270 = ~s_271;
assign s_271 = s_266[1];
assign s_272 = s_266[0];
assign s_273 = {s_274,s_276};
assign s_274 = s_248 & s_275;
assign s_275 = ~s_261;
assign s_276 = s_248?s_277:s_278;
assign s_277 = s_262[0:0];
assign s_278 = s_249[0:0];
assign s_279 = {s_280,s_282};
assign s_280 = s_209 & s_281;
assign s_281 = ~s_245;
assign s_282 = s_209?s_283:s_284;
assign s_283 = s_246[1:0];
assign s_284 = s_210[1:0];
assign s_285 = s_286[3];
assign s_286 = {s_287,s_357};
assign s_287 = s_288 & s_323;
assign s_288 = s_289[2];
assign s_289 = {s_290,s_317};
assign s_290 = s_291 & s_305;
assign s_291 = s_292[1];
assign s_292 = {s_293,s_301};
assign s_293 = s_294 & s_299;
assign s_294 = ~s_295;
assign s_295 = s_296[1];
assign s_296 = s_297[3:2];
assign s_297 = s_298[7:4];
assign s_298 = s_220[7:0];
assign s_299 = ~s_300;
assign s_300 = s_296[0];
assign s_301 = s_302 & s_304;
assign s_302 = ~s_303;
assign s_303 = s_296[1];
assign s_304 = s_296[0];
assign s_305 = s_306[1];
assign s_306 = {s_307,s_313};
assign s_307 = s_308 & s_311;
assign s_308 = ~s_309;
assign s_309 = s_310[1];
assign s_310 = s_297[1:0];
assign s_311 = ~s_312;
assign s_312 = s_310[0];
assign s_313 = s_314 & s_316;
assign s_314 = ~s_315;
assign s_315 = s_310[1];
assign s_316 = s_310[0];
assign s_317 = {s_318,s_320};
assign s_318 = s_291 & s_319;
assign s_319 = ~s_305;
assign s_320 = s_291?s_321:s_322;
assign s_321 = s_306[0:0];
assign s_322 = s_292[0:0];
assign s_323 = s_324[2];
assign s_324 = {s_325,s_351};
assign s_325 = s_326 & s_339;
assign s_326 = s_327[1];
assign s_327 = {s_328,s_335};
assign s_328 = s_329 & s_333;
assign s_329 = ~s_330;
assign s_330 = s_331[1];
assign s_331 = s_332[3:2];
assign s_332 = s_298[3:0];
assign s_333 = ~s_334;
assign s_334 = s_331[0];
assign s_335 = s_336 & s_338;
assign s_336 = ~s_337;
assign s_337 = s_331[1];
assign s_338 = s_331[0];
assign s_339 = s_340[1];
assign s_340 = {s_341,s_347};
assign s_341 = s_342 & s_345;
assign s_342 = ~s_343;
assign s_343 = s_344[1];
assign s_344 = s_332[1:0];
assign s_345 = ~s_346;
assign s_346 = s_344[0];
assign s_347 = s_348 & s_350;
assign s_348 = ~s_349;
assign s_349 = s_344[1];
assign s_350 = s_344[0];
assign s_351 = {s_352,s_354};
assign s_352 = s_326 & s_353;
assign s_353 = ~s_339;
assign s_354 = s_326?s_355:s_356;
assign s_355 = s_340[0:0];
assign s_356 = s_327[0:0];
assign s_357 = {s_358,s_360};
assign s_358 = s_288 & s_359;
assign s_359 = ~s_323;
assign s_360 = s_288?s_361:s_362;
assign s_361 = s_324[1:0];
assign s_362 = s_289[1:0];
assign s_363 = {s_364,s_366};
assign s_364 = s_206 & s_365;
assign s_365 = ~s_285;
assign s_366 = s_206?s_367:s_368;
assign s_367 = s_286[2:0];
assign s_368 = s_207[2:0];
assign s_369 = {s_370,s_372};
assign s_370 = s_37 & s_371;
assign s_371 = ~s_203;
assign s_372 = s_37?s_373:s_374;
assign s_373 = s_204[3:0];
assign s_374 = s_38[3:0];
assign s_375 = 1'd1;
dq #(24, 1) dq_s_376 (clk, s_376, s_27);
assign s_377 = s_378 & s_380;
dq #(1, 1) dq_s_378 (clk, s_378, s_379);
assign s_379 = s_28[7];
assign s_380 = s_381 | s_388;
assign s_381 = s_382 | s_384;
dq #(1, 1) dq_s_382 (clk, s_382, s_383);
assign s_383 = s_28[6];
dq #(1, 1) dq_s_384 (clk, s_384, s_385);
assign s_385 = s_386 != s_387;
assign s_386 = s_28[5:0];
assign s_387 = 1'd0;
dq #(1, 1) dq_s_388 (clk, s_388, s_389);
assign s_389 = s_27[0];
assign s_390 = s_23[23:0];
assign s_391 = s_23[24];
assign s_392 = {s_393,s_402};
assign s_393 = {s_394,s_395};
dq #(1, 5) dq_s_394 (clk, s_394, s_3);
assign s_395 = s_396 + s_401;
dq #(8, 1) dq_s_396 (clk, s_396, s_397);
assign s_397 = s_398 + s_391;
dq #(8, 2) dq_s_398 (clk, s_398, s_399);
assign s_399 = s_400 - s_34;
assign s_400 = 8'd31;
assign s_401 = 7'd127;
assign s_402 = s_20[22:0];
assign s_403 = s_404 & s_406;
assign s_404 = s_396 == s_405;
assign s_405 = -8'd126;
assign s_406 = ~s_407;
assign s_407 = s_20[23];
assign s_408 = s_20 == s_409;
assign s_409 = 24'd0;
assign s_410 = 1'd0;
assign s_411 = 1'd0;
assign to_float_z = s_0;
endmodule | 56 |
139,290 | data/full_repos/permissive/87104101/components/to_int.v | 87,104,101 | to_int.v | v | 129 | 48 | [] | [] | [] | [(1, 16), (18, 128)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/87104101/components/to_int.v:97: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'s_27\' generates 1 bits.\n : ... In instance to_int\n assign s_22 = s_23 - s_27;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/87104101/components/to_int.v:108: Operator LTS expects 8 bits on the RHS, but RHS\'s SIGNED generates 1 bits.\n : ... In instance to_int\n assign s_33 = $signed(s_25) < $signed(s_34);\n ^\n%Warning-WIDTH: data/full_repos/permissive/87104101/components/to_int.v:110: Operator EQ expects 24 bits on the RHS, but RHS\'s VARREF \'s_36\' generates 1 bits.\n : ... In instance to_int\n assign s_35 = s_10 == s_36;\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 304,587 | module | module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line[i] <= delay_line[i-1];
end
end
assign q = delay_line[depth-1];
endmodule | module dq (clk, q, d); |
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line[i] <= delay_line[i-1];
end
end
assign q = delay_line[depth-1];
endmodule | 56 |
139,291 | data/full_repos/permissive/87104101/components/to_int.v | 87,104,101 | to_int.v | v | 129 | 48 | [] | [] | [] | [(1, 16), (18, 128)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/87104101/components/to_int.v:97: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'s_27\' generates 1 bits.\n : ... In instance to_int\n assign s_22 = s_23 - s_27;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/87104101/components/to_int.v:108: Operator LTS expects 8 bits on the RHS, but RHS\'s SIGNED generates 1 bits.\n : ... In instance to_int\n assign s_33 = $signed(s_25) < $signed(s_34);\n ^\n%Warning-WIDTH: data/full_repos/permissive/87104101/components/to_int.v:110: Operator EQ expects 24 bits on the RHS, but RHS\'s VARREF \'s_36\' generates 1 bits.\n : ... In instance to_int\n assign s_35 = s_10 == s_36;\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 304,587 | module | module to_int(clk, to_int_a, to_int_z);
input clk;
input [31:0] to_int_a;
output [31:0] to_int_z;
wire [31:0] s_0;
wire [31:0] s_1;
wire [31:0] s_2;
wire [31:0] s_3;
wire [31:0] s_4;
wire [31:0] s_5;
wire [31:0] s_6;
wire [31:0] s_7;
wire [31:0] s_8;
wire [31:0] s_9;
wire [23:0] s_10;
wire [0:0] s_11;
wire [0:0] s_12;
wire [0:0] s_13;
wire [0:0] s_14;
wire [7:0] s_15;
wire [7:0] s_16;
wire [31:0] s_17;
wire [6:0] s_18;
wire [7:0] s_19;
wire [22:0] s_20;
wire [7:0] s_21;
wire [7:0] s_22;
wire [7:0] s_23;
wire [7:0] s_24;
wire [7:0] s_25;
wire [7:0] s_26;
wire [0:0] s_27;
wire [31:0] s_28;
wire [0:0] s_29;
wire [0:0] s_30;
wire [0:0] s_31;
wire [0:0] s_32;
wire [0:0] s_33;
wire [0:0] s_34;
wire [0:0] s_35;
wire [0:0] s_36;
wire [0:0] s_37;
wire [0:0] s_38;
wire [0:0] s_39;
wire [0:0] s_40;
wire [7:0] s_41;
wire [0:0] s_42;
wire [0:0] s_43;
wire [7:0] s_44;
wire [0:0] s_45;
wire [22:0] s_46;
wire [0:0] s_47;
wire [0:0] s_48;
wire [7:0] s_49;
wire [0:0] s_50;
wire [22:0] s_51;
assign s_0 = s_37?s_1:s_2;
assign s_1 = 32'd2147483648;
assign s_2 = s_31?s_3:s_4;
assign s_3 = 32'd0;
assign s_4 = s_29?s_5:s_28;
dq #(32, 1) dq_s_5 (clk, s_5, s_6);
assign s_6 = -s_7;
dq #(32, 1) dq_s_7 (clk, s_7, s_8);
assign s_8 = s_9 >> s_22;
assign s_9 = {s_10,s_21};
assign s_10 = {s_11,s_20};
assign s_11 = s_14?s_12:s_13;
assign s_12 = 1'd0;
assign s_13 = 1'd1;
assign s_14 = s_15 == s_19;
assign s_15 = s_16 - s_18;
assign s_16 = s_17[30:23];
assign s_17 = to_int_a;
assign s_18 = 7'd127;
assign s_19 = -8'd127;
assign s_20 = s_17[22:0];
assign s_21 = 8'd0;
assign s_22 = s_23 - s_27;
assign s_23 = s_24 - s_25;
assign s_24 = 8'd32;
assign s_25 = s_14?s_26:s_15;
assign s_26 = -8'd126;
assign s_27 = 1'd1;
dq #(32, 1) dq_s_28 (clk, s_28, s_7);
dq #(1, 2) dq_s_29 (clk, s_29, s_30);
assign s_30 = s_17[31];
dq #(1, 2) dq_s_31 (clk, s_31, s_32);
assign s_32 = s_33 | s_35;
assign s_33 = $signed(s_25) < $signed(s_34);
assign s_34 = 1'd0;
assign s_35 = s_10 == s_36;
assign s_36 = 1'd0;
dq #(1, 2) dq_s_37 (clk, s_37, s_38);
assign s_38 = s_39 | s_47;
assign s_39 = s_40 | s_42;
assign s_40 = $signed(s_25) >= $signed(s_41);
assign s_41 = 8'd31;
assign s_42 = s_43 & s_45;
assign s_43 = s_15 == s_44;
assign s_44 = 8'd128;
assign s_45 = s_20 == s_46;
assign s_46 = 23'd0;
assign s_47 = s_48 & s_50;
assign s_48 = s_15 == s_49;
assign s_49 = 8'd128;
assign s_50 = s_20 != s_51;
assign s_51 = 23'd0;
assign to_int_z = s_0;
endmodule | module to_int(clk, to_int_a, to_int_z); |
input clk;
input [31:0] to_int_a;
output [31:0] to_int_z;
wire [31:0] s_0;
wire [31:0] s_1;
wire [31:0] s_2;
wire [31:0] s_3;
wire [31:0] s_4;
wire [31:0] s_5;
wire [31:0] s_6;
wire [31:0] s_7;
wire [31:0] s_8;
wire [31:0] s_9;
wire [23:0] s_10;
wire [0:0] s_11;
wire [0:0] s_12;
wire [0:0] s_13;
wire [0:0] s_14;
wire [7:0] s_15;
wire [7:0] s_16;
wire [31:0] s_17;
wire [6:0] s_18;
wire [7:0] s_19;
wire [22:0] s_20;
wire [7:0] s_21;
wire [7:0] s_22;
wire [7:0] s_23;
wire [7:0] s_24;
wire [7:0] s_25;
wire [7:0] s_26;
wire [0:0] s_27;
wire [31:0] s_28;
wire [0:0] s_29;
wire [0:0] s_30;
wire [0:0] s_31;
wire [0:0] s_32;
wire [0:0] s_33;
wire [0:0] s_34;
wire [0:0] s_35;
wire [0:0] s_36;
wire [0:0] s_37;
wire [0:0] s_38;
wire [0:0] s_39;
wire [0:0] s_40;
wire [7:0] s_41;
wire [0:0] s_42;
wire [0:0] s_43;
wire [7:0] s_44;
wire [0:0] s_45;
wire [22:0] s_46;
wire [0:0] s_47;
wire [0:0] s_48;
wire [7:0] s_49;
wire [0:0] s_50;
wire [22:0] s_51;
assign s_0 = s_37?s_1:s_2;
assign s_1 = 32'd2147483648;
assign s_2 = s_31?s_3:s_4;
assign s_3 = 32'd0;
assign s_4 = s_29?s_5:s_28;
dq #(32, 1) dq_s_5 (clk, s_5, s_6);
assign s_6 = -s_7;
dq #(32, 1) dq_s_7 (clk, s_7, s_8);
assign s_8 = s_9 >> s_22;
assign s_9 = {s_10,s_21};
assign s_10 = {s_11,s_20};
assign s_11 = s_14?s_12:s_13;
assign s_12 = 1'd0;
assign s_13 = 1'd1;
assign s_14 = s_15 == s_19;
assign s_15 = s_16 - s_18;
assign s_16 = s_17[30:23];
assign s_17 = to_int_a;
assign s_18 = 7'd127;
assign s_19 = -8'd127;
assign s_20 = s_17[22:0];
assign s_21 = 8'd0;
assign s_22 = s_23 - s_27;
assign s_23 = s_24 - s_25;
assign s_24 = 8'd32;
assign s_25 = s_14?s_26:s_15;
assign s_26 = -8'd126;
assign s_27 = 1'd1;
dq #(32, 1) dq_s_28 (clk, s_28, s_7);
dq #(1, 2) dq_s_29 (clk, s_29, s_30);
assign s_30 = s_17[31];
dq #(1, 2) dq_s_31 (clk, s_31, s_32);
assign s_32 = s_33 | s_35;
assign s_33 = $signed(s_25) < $signed(s_34);
assign s_34 = 1'd0;
assign s_35 = s_10 == s_36;
assign s_36 = 1'd0;
dq #(1, 2) dq_s_37 (clk, s_37, s_38);
assign s_38 = s_39 | s_47;
assign s_39 = s_40 | s_42;
assign s_40 = $signed(s_25) >= $signed(s_41);
assign s_41 = 8'd31;
assign s_42 = s_43 & s_45;
assign s_43 = s_15 == s_44;
assign s_44 = 8'd128;
assign s_45 = s_20 == s_46;
assign s_46 = 23'd0;
assign s_47 = s_48 & s_50;
assign s_48 = s_15 == s_49;
assign s_49 = 8'd128;
assign s_50 = s_20 != s_51;
assign s_51 = 23'd0;
assign to_int_z = s_0;
endmodule | 56 |
139,292 | data/full_repos/permissive/87104101/components/trunc_tb.v | 87,104,101 | trunc_tb.v | v | 36 | 63 | [] | [] | [] | null | line:19: before: "$" | null | 1: b'%Error: data/full_repos/permissive/87104101/components/trunc_tb.v:13: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n trunc_z_file = $fopen("stim/trunc_z");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/trunc_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #50010 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/trunc_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #5 clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87104101/components/trunc_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #0 trunc_a_count = $fscanf(trunc_a_file, "%d\\n", trunc_a);\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,589 | module | module trunc_tb;
reg clk;
reg [31:0] trunc_a;
wire [31:0] trunc_z;
integer trunc_a_file;
integer trunc_z_file;
integer trunc_a_count;
integer trunc_z_count;
trunc trunc1 (clk, trunc_a, trunc_z);
initial
begin
trunc_z_file = $fopen("stim/trunc_z");
trunc_a_file = $fopen("stim/trunc_a", "r");
end
initial
begin
#50010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(trunc_z_file, "%d", trunc_z);
#0 trunc_a_count = $fscanf(trunc_a_file, "%d\n", trunc_a);
end
endmodule | module trunc_tb; |
reg clk;
reg [31:0] trunc_a;
wire [31:0] trunc_z;
integer trunc_a_file;
integer trunc_z_file;
integer trunc_a_count;
integer trunc_z_count;
trunc trunc1 (clk, trunc_a, trunc_z);
initial
begin
trunc_z_file = $fopen("stim/trunc_z");
trunc_a_file = $fopen("stim/trunc_a", "r");
end
initial
begin
#50010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(trunc_z_file, "%d", trunc_z);
#0 trunc_a_count = $fscanf(trunc_a_file, "%d\n", trunc_a);
end
endmodule | 56 |
139,295 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/03. add/add.v | 87,159,735 | add.v | v | 6 | 27 | [] | [] | [] | [(1, 6)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/03.\n%Error: Cannot find file containing module: add,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: add/add.v\n%Error: Exiting due to 6 error(s)\n' | 304,599 | module | module add(a,b,ci,co,s);
input a,b,ci;
output s,co;
assign s=a^b^ci;
assign co=a&b|a&ci|b&ci;
endmodule | module add(a,b,ci,co,s); |
input a,b,ci;
output s,co;
assign s=a^b^ci;
assign co=a&b|a&ci|b&ci;
endmodule | 0 |
139,296 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/03. add/add_32.v | 87,159,735 | add_32.v | v | 39 | 38 | [] | [] | [] | [(1, 39)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/03.\n%Error: Cannot find file containing module: add,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: add/add_32.v\n%Error: Exiting due to 6 error(s)\n' | 304,600 | module | module add_32(a,b,p);
input [0:31] a,b;
output [0:32] p;
wire [0:31] s,c;
assign p[0:31]=s[0:31];
assign p[32]=c[31];
add(a[0],b[0],0,c[0],s[0]);
add(a[1],b[1],c[0],c[1],s[1]);
add(a[2],b[2],c[1],c[2],s[2]);
add(a[3],b[3],c[2],c[3],s[3]);
add(a[4],b[4],c[3],c[4],s[4]);
add(a[5],b[5],c[4],c[5],s[5]);
add(a[6],b[6],c[5],c[6],s[6]);
add(a[7],b[7],c[6],c[7],s[7]);
add(a[8],b[8],c[7],c[8],s[8]);
add(a[9],b[9],c[8],c[9],s[9]);
add(a[10],b[10],c[9],c[10],s[10]);
add(a[11],b[11],c[10],c[11],s[11]);
add(a[12],b[12],c[11],c[12],s[12]);
add(a[13],b[13],c[12],c[13],s[13]);
add(a[14],b[14],c[13],c[14],s[14]);
add(a[15],b[15],c[14],c[15],s[15]);
add(a[16],b[16],c[15],c[16],s[16]);
add(a[17],b[17],c[16],c[17],s[17]);
add(a[18],b[18],c[17],c[18],s[18]);
add(a[19],b[19],c[18],c[19],s[19]);
add(a[20],b[20],c[19],c[20],s[20]);
add(a[21],b[21],c[20],c[21],s[21]);
add(a[22],b[22],c[21],c[22],s[22]);
add(a[23],b[23],c[22],c[23],s[23]);
add(a[24],b[24],c[23],c[24],s[24]);
add(a[25],b[25],c[24],c[25],s[25]);
add(a[26],b[26],c[25],c[26],s[26]);
add(a[27],b[27],c[26],c[27],s[27]);
add(a[28],b[28],c[27],c[28],s[28]);
add(a[29],b[29],c[28],c[29],s[29]);
add(a[30],b[30],c[29],c[30],s[30]);
add(a[31],b[31],c[30],c[31],s[31]);
endmodule | module add_32(a,b,p); |
input [0:31] a,b;
output [0:32] p;
wire [0:31] s,c;
assign p[0:31]=s[0:31];
assign p[32]=c[31];
add(a[0],b[0],0,c[0],s[0]);
add(a[1],b[1],c[0],c[1],s[1]);
add(a[2],b[2],c[1],c[2],s[2]);
add(a[3],b[3],c[2],c[3],s[3]);
add(a[4],b[4],c[3],c[4],s[4]);
add(a[5],b[5],c[4],c[5],s[5]);
add(a[6],b[6],c[5],c[6],s[6]);
add(a[7],b[7],c[6],c[7],s[7]);
add(a[8],b[8],c[7],c[8],s[8]);
add(a[9],b[9],c[8],c[9],s[9]);
add(a[10],b[10],c[9],c[10],s[10]);
add(a[11],b[11],c[10],c[11],s[11]);
add(a[12],b[12],c[11],c[12],s[12]);
add(a[13],b[13],c[12],c[13],s[13]);
add(a[14],b[14],c[13],c[14],s[14]);
add(a[15],b[15],c[14],c[15],s[15]);
add(a[16],b[16],c[15],c[16],s[16]);
add(a[17],b[17],c[16],c[17],s[17]);
add(a[18],b[18],c[17],c[18],s[18]);
add(a[19],b[19],c[18],c[19],s[19]);
add(a[20],b[20],c[19],c[20],s[20]);
add(a[21],b[21],c[20],c[21],s[21]);
add(a[22],b[22],c[21],c[22],s[22]);
add(a[23],b[23],c[22],c[23],s[23]);
add(a[24],b[24],c[23],c[24],s[24]);
add(a[25],b[25],c[24],c[25],s[25]);
add(a[26],b[26],c[25],c[26],s[26]);
add(a[27],b[27],c[26],c[27],s[27]);
add(a[28],b[28],c[27],c[28],s[28]);
add(a[29],b[29],c[28],c[29],s[29]);
add(a[30],b[30],c[29],c[30],s[30]);
add(a[31],b[31],c[30],c[31],s[31]);
endmodule | 0 |
139,297 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/04. ver/count.v | 87,159,735 | count.v | v | 17 | 40 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xac in position 158: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/04.\n%Error: Cannot find file containing module: ver,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: ver/count.v\n%Error: Exiting due to 6 error(s)\n' | 304,601 | module | module count (clk,du,cout);
input clk,du;
output [3:0] cout;
reg [3:0] cout;
always @( posedge clk) begin
if(~du) begin
cout=cout+1;
if(cout==10)
cout=0;
end
else begin
cout=cout-1;
if(cout==15)
cout=9;
end
end
endmodule | module count (clk,du,cout); |
input clk,du;
output [3:0] cout;
reg [3:0] cout;
always @( posedge clk) begin
if(~du) begin
cout=cout+1;
if(cout==10)
cout=0;
end
else begin
cout=cout-1;
if(cout==15)
cout=9;
end
end
endmodule | 0 |
139,298 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/05. count9999/count9999.v | 87,159,735 | count9999.v | v | 30 | 47 | [] | [] | [] | [(1, 30)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/05.\n%Error: Cannot find file containing module: count9999,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: count9999/count9999.v\n%Error: Exiting due to 6 error(s)\n' | 304,602 | module | module count9999(clk,s0,s1,s2,s3,z0,z1,z2,z3);
input clk;
output [3:0] s0,s1,s2,s3;
output [6:0] z0,z1,z2,z3;
reg [3:0] s0,s1,s2,s3;
print_7(s0,z0);
print_7(s1,z1);
print_7(s2,z2);
print_7(s3,z3);
always @ (negedge clk) begin
if (s0>=9) begin
s0=0;
s1=s1+1;
end
else begin
s0=s0+1;
end
if (s1>=10) begin
s1=0;
s2=s2+1;
end
if (s2>=10) begin
s2=0;
s3=s3+1;
end
if (s3>=10) begin
s3=0;
end
end
endmodule | module count9999(clk,s0,s1,s2,s3,z0,z1,z2,z3); |
input clk;
output [3:0] s0,s1,s2,s3;
output [6:0] z0,z1,z2,z3;
reg [3:0] s0,s1,s2,s3;
print_7(s0,z0);
print_7(s1,z1);
print_7(s2,z2);
print_7(s3,z3);
always @ (negedge clk) begin
if (s0>=9) begin
s0=0;
s1=s1+1;
end
else begin
s0=s0+1;
end
if (s1>=10) begin
s1=0;
s2=s2+1;
end
if (s2>=10) begin
s2=0;
s3=s3+1;
end
if (s3>=10) begin
s3=0;
end
end
endmodule | 0 |
139,299 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/05. count9999/print_7.v | 87,159,735 | print_7.v | v | 11 | 302 | [] | [] | [] | [(1, 11)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/05.\n%Error: Cannot find file containing module: count9999,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: count9999/print_7.v\n%Error: Exiting due to 6 error(s)\n' | 304,603 | module | module print_7(z,p);
input [3:0] z;
output [6:0] p;
assign p[0]=~z[3]&~z[2]&~z[1]&~z[0] | ~z[3]&~z[2]&z[1]&~z[0] | ~z[3]&~z[2]&z[1]&z[0] | ~z[3]&z[2]&~z[1]&z[0] | ~z[3]&z[2]&z[1]&~z[0] | ~z[3]&z[2]&z[1]&z[0] | z[3]&~z[2]&~z[1]&~z[0] | z[3]&~z[2]&~z[1]&z[0] | z[3]&~z[2]&z[1]&~z[0] | z[3]&z[2]&~z[1]&~z[0] | z[3]&z[2]&z[1]&~z[0] | z[3]&z[2]&z[1]&z[0];
assign p[1]=~z[3]&~z[2]&~z[1]&~z[0] | ~z[3]&~z[2]&~z[1]&z[0] | ~z[3]&~z[2]&z[1]&~z[0] | ~z[3]&~z[2]&z[1]&z[0] | ~z[3]&z[2]&~z[1]&~z[0] | ~z[3]&z[2]&z[1]&z[0] | z[3]&~z[2]&~z[1]&~z[0] | z[3]&~z[2]&~z[1]&z[0] | z[3]&~z[2]&z[1]&~z[0] | z[3]&z[2]&~z[1]&z[0];
assign p[2]=~z[3]&~z[2]&~z[1]&~z[0] | ~z[3]&~z[2]&~z[1]&z[0] | ~z[3]&~z[2]&z[1]&z[0] | ~z[3]&z[2]&~z[1]&~z[0] | ~z[3]&z[2]&~z[1]&z[0] | ~z[3]&z[2]&z[1]&~z[0] | ~z[3]&z[2]&z[1]&z[0] | z[3]&~z[2]&~z[1]&~z[0] | z[3]&~z[2]&~z[1]&z[0] | z[3]&~z[2]&z[1]&z[0] | z[3]&z[2]&~z[1]&z[0];
assign p[3]=~z[3]&~z[2]&~z[1]&~z[0] | ~z[3]&~z[2]&z[1]&~z[0] | ~z[3]&~z[2]&z[1]&z[0] | ~z[3]&z[2]&~z[1]&z[0] | ~z[3]&z[2]&z[1]&~z[0] | z[3]&~z[2]&~z[1]&~z[0] | z[3]&~z[2]&~z[1]&z[0] | z[3]&~z[2]&z[1]&~z[0] | z[3]&~z[2]&z[1]&z[0] | z[3]&z[2]&~z[1]&~z[0] | z[3]&z[2]&~z[1]&z[0] | z[3]&z[2]&z[1]&~z[0];
assign p[4]=~z[3]&~z[2]&~z[1]&~z[0] | ~z[3]&~z[2]&z[1]&~z[0] | ~z[3]&z[2]&z[1]&~z[0] | z[3]&~z[2]&~z[1]&~z[0] | z[3]&~z[2]&z[1]&~z[0] | z[3]&~z[2]&z[1]&z[0] | z[3]&z[2]&~z[1]&~z[0] | z[3]&z[2]&~z[1]&z[0] | z[3]&z[2]&z[1]&~z[0] | z[3]&z[2]&z[1]&z[0];
assign p[5]=~z[3]&~z[2]&~z[1]&~z[0] | ~z[3]&z[2]&~z[1]&~z[0] | ~z[3]&z[2]&~z[1]&z[0] | ~z[3]&z[2]&z[1]&~z[0] | z[3]&~z[2]&~z[1]&~z[0] | z[3]&~z[2]&~z[1]&z[0] | z[3]&~z[2]&z[1]&~z[0] | z[3]&~z[2]&z[1]&z[0] | z[3]&z[2]&~z[1]&~z[0] | z[3]&z[2]&z[1]&~z[0] | z[3]&z[2]&z[1]&z[0];
assign p[6]=~z[3]&~z[2]&z[1]&~z[0] | ~z[3]&~z[2]&z[1]&z[0] | ~z[3]&z[2]&~z[1]&~z[0] | ~z[3]&z[2]&~z[1]&z[0] | ~z[3]&z[2]&z[1]&~z[0] | z[3]&~z[2]&~z[1]&~z[0] | z[3]&~z[2]&~z[1]&z[0] | z[3]&~z[2]&z[1]&~z[0] | z[3]&~z[2]&z[1]&z[0] | z[3]&z[2]&~z[1]&z[0] | z[3]&z[2]&z[1]&~z[0] | z[3]&z[2]&z[1]&z[0];
endmodule | module print_7(z,p); |
input [3:0] z;
output [6:0] p;
assign p[0]=~z[3]&~z[2]&~z[1]&~z[0] | ~z[3]&~z[2]&z[1]&~z[0] | ~z[3]&~z[2]&z[1]&z[0] | ~z[3]&z[2]&~z[1]&z[0] | ~z[3]&z[2]&z[1]&~z[0] | ~z[3]&z[2]&z[1]&z[0] | z[3]&~z[2]&~z[1]&~z[0] | z[3]&~z[2]&~z[1]&z[0] | z[3]&~z[2]&z[1]&~z[0] | z[3]&z[2]&~z[1]&~z[0] | z[3]&z[2]&z[1]&~z[0] | z[3]&z[2]&z[1]&z[0];
assign p[1]=~z[3]&~z[2]&~z[1]&~z[0] | ~z[3]&~z[2]&~z[1]&z[0] | ~z[3]&~z[2]&z[1]&~z[0] | ~z[3]&~z[2]&z[1]&z[0] | ~z[3]&z[2]&~z[1]&~z[0] | ~z[3]&z[2]&z[1]&z[0] | z[3]&~z[2]&~z[1]&~z[0] | z[3]&~z[2]&~z[1]&z[0] | z[3]&~z[2]&z[1]&~z[0] | z[3]&z[2]&~z[1]&z[0];
assign p[2]=~z[3]&~z[2]&~z[1]&~z[0] | ~z[3]&~z[2]&~z[1]&z[0] | ~z[3]&~z[2]&z[1]&z[0] | ~z[3]&z[2]&~z[1]&~z[0] | ~z[3]&z[2]&~z[1]&z[0] | ~z[3]&z[2]&z[1]&~z[0] | ~z[3]&z[2]&z[1]&z[0] | z[3]&~z[2]&~z[1]&~z[0] | z[3]&~z[2]&~z[1]&z[0] | z[3]&~z[2]&z[1]&z[0] | z[3]&z[2]&~z[1]&z[0];
assign p[3]=~z[3]&~z[2]&~z[1]&~z[0] | ~z[3]&~z[2]&z[1]&~z[0] | ~z[3]&~z[2]&z[1]&z[0] | ~z[3]&z[2]&~z[1]&z[0] | ~z[3]&z[2]&z[1]&~z[0] | z[3]&~z[2]&~z[1]&~z[0] | z[3]&~z[2]&~z[1]&z[0] | z[3]&~z[2]&z[1]&~z[0] | z[3]&~z[2]&z[1]&z[0] | z[3]&z[2]&~z[1]&~z[0] | z[3]&z[2]&~z[1]&z[0] | z[3]&z[2]&z[1]&~z[0];
assign p[4]=~z[3]&~z[2]&~z[1]&~z[0] | ~z[3]&~z[2]&z[1]&~z[0] | ~z[3]&z[2]&z[1]&~z[0] | z[3]&~z[2]&~z[1]&~z[0] | z[3]&~z[2]&z[1]&~z[0] | z[3]&~z[2]&z[1]&z[0] | z[3]&z[2]&~z[1]&~z[0] | z[3]&z[2]&~z[1]&z[0] | z[3]&z[2]&z[1]&~z[0] | z[3]&z[2]&z[1]&z[0];
assign p[5]=~z[3]&~z[2]&~z[1]&~z[0] | ~z[3]&z[2]&~z[1]&~z[0] | ~z[3]&z[2]&~z[1]&z[0] | ~z[3]&z[2]&z[1]&~z[0] | z[3]&~z[2]&~z[1]&~z[0] | z[3]&~z[2]&~z[1]&z[0] | z[3]&~z[2]&z[1]&~z[0] | z[3]&~z[2]&z[1]&z[0] | z[3]&z[2]&~z[1]&~z[0] | z[3]&z[2]&z[1]&~z[0] | z[3]&z[2]&z[1]&z[0];
assign p[6]=~z[3]&~z[2]&z[1]&~z[0] | ~z[3]&~z[2]&z[1]&z[0] | ~z[3]&z[2]&~z[1]&~z[0] | ~z[3]&z[2]&~z[1]&z[0] | ~z[3]&z[2]&z[1]&~z[0] | z[3]&~z[2]&~z[1]&~z[0] | z[3]&~z[2]&~z[1]&z[0] | z[3]&~z[2]&z[1]&~z[0] | z[3]&~z[2]&z[1]&z[0] | z[3]&z[2]&~z[1]&z[0] | z[3]&z[2]&z[1]&~z[0] | z[3]&z[2]&z[1]&z[0];
endmodule | 0 |
139,300 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/06. comparator/comparator.v | 87,159,735 | comparator.v | v | 46 | 66 | [] | [] | [] | [(7, 11)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/06.\n%Error: Cannot find file containing module: comparator,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: comparator/comparator.v\n%Error: Exiting due to 6 error(s)\n' | 304,604 | module | module comparator(a,b,out);
input [3:0] a,b;
output out;
assign out=((a^b)==0)?1:0;
endmodule | module comparator(a,b,out); |
input [3:0] a,b;
output out;
assign out=((a^b)==0)?1:0;
endmodule | 0 |
139,301 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/07. print_7/print_7.v | 87,159,735 | print_7.v | v | 22 | 299 | [] | [] | [] | [(12, 22)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/07.\n%Error: Cannot find file containing module: print_7,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: print_7/print_7.v\n%Error: Exiting due to 6 error(s)\n' | 304,606 | module | module print_7(z,a,b,c,d,e,f,g);
input [3:0] z;
output a,b,c,d,e,f,g;
assign a=(z==0)|(z==2)|(z==3)|(z==5)|(z==6)|(z==7)|(z==8)|(z==9)|(z==10)|(z==12)|(z==14)|(z==15);
assign b=(z==0)|(z==1)|(z==2)|(z==3)|(z==4)|(z==7)|(z==8)|(z==9)|(z==10)|(z==13);
assign c=(z==0)|(z==1)|(z==3)|(z==4)|(z==5)|(z==6)|(z==7)|(z==8)|(z==9)|(z==11)|(z==13);
assign d=(z==0)|(z==2)|(z==3)|(z==5)|(z==6)|(z==8)|(z==9)|(z==10)|(z==11)|(z==12)|(z==13)|(z==14);
assign e=(z==0)|(z==2)|(z==6)|(z==8)|(z==10)|(z==11)|(z==12)|(z==13)|(z==14)|(z==15);
assign f=(z==0)|(z==4)|(z==5)|(z==6)|(z==8)|(z==9)|(z==10)|(z==11)|(z==12)|(z==14)|(z==15);
assign g=(z==2)|(z==3)|(z==4)|(z==5)|(z==6)|(z==8)|(z==9)|(z==10)|(z==11)|(z==13)|(z==14)|(z==15);
endmodule | module print_7(z,a,b,c,d,e,f,g); |
input [3:0] z;
output a,b,c,d,e,f,g;
assign a=(z==0)|(z==2)|(z==3)|(z==5)|(z==6)|(z==7)|(z==8)|(z==9)|(z==10)|(z==12)|(z==14)|(z==15);
assign b=(z==0)|(z==1)|(z==2)|(z==3)|(z==4)|(z==7)|(z==8)|(z==9)|(z==10)|(z==13);
assign c=(z==0)|(z==1)|(z==3)|(z==4)|(z==5)|(z==6)|(z==7)|(z==8)|(z==9)|(z==11)|(z==13);
assign d=(z==0)|(z==2)|(z==3)|(z==5)|(z==6)|(z==8)|(z==9)|(z==10)|(z==11)|(z==12)|(z==13)|(z==14);
assign e=(z==0)|(z==2)|(z==6)|(z==8)|(z==10)|(z==11)|(z==12)|(z==13)|(z==14)|(z==15);
assign f=(z==0)|(z==4)|(z==5)|(z==6)|(z==8)|(z==9)|(z==10)|(z==11)|(z==12)|(z==14)|(z==15);
assign g=(z==2)|(z==3)|(z==4)|(z==5)|(z==6)|(z==8)|(z==9)|(z==10)|(z==11)|(z==13)|(z==14)|(z==15);
endmodule | 0 |
139,302 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/08. mod6counter/mod6counter.v | 87,159,735 | mod6counter.v | v | 81 | 137 | [] | [] | [] | [(51, 80)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/08.\n%Error: Cannot find file containing module: mod6counter,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: mod6counter/mod6counter.v\n%Error: Exiting due to 6 error(s)\n' | 304,607 | module | module mod6counter(en,clk,reset,even,q);
input clk,en,reset;
output even;
output [2:0]q;
reg [2:0]q;
assign even=(q==0)|(q==2)|(q==4);
always@(negedge clk or posedge reset)
begin
if(reset==1)
begin
q<=0;
end
else if(en==0)
begin
q<=q;
end
else
begin
case(q)
0: q<=1;
1: q<=2;
2: q<=3;
3: q<=4;
4: q<=5;
5: q<=0;
default: q<=0;
endcase
end
end
endmodule | module mod6counter(en,clk,reset,even,q); |
input clk,en,reset;
output even;
output [2:0]q;
reg [2:0]q;
assign even=(q==0)|(q==2)|(q==4);
always@(negedge clk or posedge reset)
begin
if(reset==1)
begin
q<=0;
end
else if(en==0)
begin
q<=q;
end
else
begin
case(q)
0: q<=1;
1: q<=2;
2: q<=3;
3: q<=4;
4: q<=5;
5: q<=0;
default: q<=0;
endcase
end
end
endmodule | 0 |
139,303 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/09. in10to7seg/in10to7seg.v | 87,159,735 | in10to7seg.v | v | 51 | 104 | [] | [] | [] | [(1, 40), (41, 51)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/09.\n%Error: Cannot find file containing module: in10to7seg,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: in10to7seg/in10to7seg.v\n%Error: Exiting due to 6 error(s)\n' | 304,608 | module | module in10to7seg(in14,in_scan,seg,seg_scan);
input [13:0]in14;
input [1:0]in_scan;
output [3:0]seg_scan;
output [6:0]seg;
wire [15:0]single_bit;
wire [27:0]sin_bit_tran;
reg [6:0]seg;
reg [3:0]seg_scan;
assign single_bit[3:0]=(in14%10);
assign single_bit[7:4]=(in14/10)%100;
assign single_bit[11:8]=(in14/100)%1000;
assign single_bit[15:12]=(in14/1000);
print_7 s0(single_bit[3:0],sin_bit_tran[6:0]);
print_7 s1(single_bit[7:4],sin_bit_tran[13:7]);
print_7 s2(single_bit[11:8],sin_bit_tran[20:14]);
print_7 s3(single_bit[15:12],sin_bit_tran[27:21]);
always@(in_scan or in14)
begin
case(in_scan)
0: begin
seg=sin_bit_tran[6:0];
seg_scan=4'b1110;
end
1: begin
seg=sin_bit_tran[13:7];
seg_scan=4'b1101;
end
2: begin
seg=sin_bit_tran[20:14];
seg_scan=4'b1011;
end
3: begin
seg=sin_bit_tran[27:21];
seg_scan=4'b0111;
end
default: seg=0;
endcase
end
endmodule | module in10to7seg(in14,in_scan,seg,seg_scan); |
input [13:0]in14;
input [1:0]in_scan;
output [3:0]seg_scan;
output [6:0]seg;
wire [15:0]single_bit;
wire [27:0]sin_bit_tran;
reg [6:0]seg;
reg [3:0]seg_scan;
assign single_bit[3:0]=(in14%10);
assign single_bit[7:4]=(in14/10)%100;
assign single_bit[11:8]=(in14/100)%1000;
assign single_bit[15:12]=(in14/1000);
print_7 s0(single_bit[3:0],sin_bit_tran[6:0]);
print_7 s1(single_bit[7:4],sin_bit_tran[13:7]);
print_7 s2(single_bit[11:8],sin_bit_tran[20:14]);
print_7 s3(single_bit[15:12],sin_bit_tran[27:21]);
always@(in_scan or in14)
begin
case(in_scan)
0: begin
seg=sin_bit_tran[6:0];
seg_scan=4'b1110;
end
1: begin
seg=sin_bit_tran[13:7];
seg_scan=4'b1101;
end
2: begin
seg=sin_bit_tran[20:14];
seg_scan=4'b1011;
end
3: begin
seg=sin_bit_tran[27:21];
seg_scan=4'b0111;
end
default: seg=0;
endcase
end
endmodule | 0 |
139,304 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/09. in10to7seg/in10to7seg.v | 87,159,735 | in10to7seg.v | v | 51 | 104 | [] | [] | [] | [(1, 40), (41, 51)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/09.\n%Error: Cannot find file containing module: in10to7seg,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: in10to7seg/in10to7seg.v\n%Error: Exiting due to 6 error(s)\n' | 304,608 | module | module print_7(z,a);
input [3:0]z;
output [6:0]a;
assign a[0]=(z==0)|(z==2)|(z==3)|(z==5)|(z==6)|(z==7)|(z==8)|(z==9)|(z==10)|(z==12)|(z==14)|(z==15);
assign a[1]=(z==0)|(z==1)|(z==2)|(z==3)|(z==4)|(z==7)|(z==8)|(z==9)|(z==10)|(z==13);
assign a[2]=(z==0)|(z==1)|(z==3)|(z==4)|(z==5)|(z==6)|(z==7)|(z==8)|(z==9)|(z==11)|(z==13);
assign a[3]=(z==0)|(z==2)|(z==3)|(z==5)|(z==6)|(z==8)|(z==9)|(z==10)|(z==11)|(z==12)|(z==13)|(z==14);
assign a[4]=(z==0)|(z==2)|(z==6)|(z==8)|(z==10)|(z==11)|(z==12)|(z==13)|(z==14)|(z==15);
assign a[5]=(z==0)|(z==4)|(z==5)|(z==6)|(z==8)|(z==9)|(z==10)|(z==11)|(z==12)|(z==14)|(z==15);
assign a[6]=(z==2)|(z==3)|(z==4)|(z==5)|(z==6)|(z==8)|(z==9)|(z==10)|(z==11)|(z==13)|(z==14)|(z==15);
endmodule | module print_7(z,a); |
input [3:0]z;
output [6:0]a;
assign a[0]=(z==0)|(z==2)|(z==3)|(z==5)|(z==6)|(z==7)|(z==8)|(z==9)|(z==10)|(z==12)|(z==14)|(z==15);
assign a[1]=(z==0)|(z==1)|(z==2)|(z==3)|(z==4)|(z==7)|(z==8)|(z==9)|(z==10)|(z==13);
assign a[2]=(z==0)|(z==1)|(z==3)|(z==4)|(z==5)|(z==6)|(z==7)|(z==8)|(z==9)|(z==11)|(z==13);
assign a[3]=(z==0)|(z==2)|(z==3)|(z==5)|(z==6)|(z==8)|(z==9)|(z==10)|(z==11)|(z==12)|(z==13)|(z==14);
assign a[4]=(z==0)|(z==2)|(z==6)|(z==8)|(z==10)|(z==11)|(z==12)|(z==13)|(z==14)|(z==15);
assign a[5]=(z==0)|(z==4)|(z==5)|(z==6)|(z==8)|(z==9)|(z==10)|(z==11)|(z==12)|(z==14)|(z==15);
assign a[6]=(z==2)|(z==3)|(z==4)|(z==5)|(z==6)|(z==8)|(z==9)|(z==10)|(z==11)|(z==13)|(z==14)|(z==15);
endmodule | 0 |
139,305 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/10. div/div.v | 87,159,735 | div.v | v | 30 | 81 | [] | [] | [] | [(1, 8), (9, 29)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/10.\n%Error: Cannot find file containing module: div,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: div/div.v\n%Error: Exiting due to 6 error(s)\n' | 304,609 | module | module div_1(add_bit,d_dend,d_sor,quo,rem);
input d_dend;
input [3:0]d_sor,add_bit;
output quo;
output [3:0]rem;
assign quo=({add_bit,d_dend}<d_sor)?0:1;
assign rem=({add_bit,d_dend}<d_sor)?{add_bit,d_dend}:({add_bit,d_dend}-d_sor);
endmodule | module div_1(add_bit,d_dend,d_sor,quo,rem); |
input d_dend;
input [3:0]d_sor,add_bit;
output quo;
output [3:0]rem;
assign quo=({add_bit,d_dend}<d_sor)?0:1;
assign rem=({add_bit,d_dend}<d_sor)?{add_bit,d_dend}:({add_bit,d_dend}-d_sor);
endmodule | 0 |
139,306 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/10. div/div.v | 87,159,735 | div.v | v | 30 | 81 | [] | [] | [] | [(1, 8), (9, 29)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/10.\n%Error: Cannot find file containing module: div,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: div/div.v\n%Error: Exiting due to 6 error(s)\n' | 304,609 | module | module div(dend,sor,quo,rem);
input [13:0]dend;
input [3:0]sor;
output [13:0]quo;
output [3:0]rem;
wire [51:0]rem_reg;
div_1(0,dend[13],sor,quo[13],rem_reg[51:48]);
div_1(rem_reg[51:48],dend[12],sor,quo[12],rem_reg[47:44]);
div_1(rem_reg[47:44],dend[11],sor,quo[11],rem_reg[43:40]);
div_1(rem_reg[43:40],dend[10],sor,quo[10],rem_reg[39:36]);
div_1(rem_reg[39:36],dend[9],sor,quo[9],rem_reg[35:32]);
div_1(rem_reg[35:32],dend[8],sor,quo[8],rem_reg[31:28]);
div_1(rem_reg[31:28],dend[7],sor,quo[7],rem_reg[27:24]);
div_1(rem_reg[27:24],dend[6],sor,quo[6],rem_reg[23:20]);
div_1(rem_reg[23:20],dend[5],sor,quo[5],rem_reg[19:16]);
div_1(rem_reg[19:16],dend[4],sor,quo[4],rem_reg[15:12]);
div_1(rem_reg[15:12],dend[3],sor,quo[3],rem_reg[11:8]);
div_1(rem_reg[11:8],dend[2],sor,quo[2],rem_reg[7:4]);
div_1(rem_reg[7:4],dend[1],sor,quo[1],rem_reg[3:0]);
div_1(rem_reg[3:0],dend[0],sor,quo[0],rem);
endmodule | module div(dend,sor,quo,rem); |
input [13:0]dend;
input [3:0]sor;
output [13:0]quo;
output [3:0]rem;
wire [51:0]rem_reg;
div_1(0,dend[13],sor,quo[13],rem_reg[51:48]);
div_1(rem_reg[51:48],dend[12],sor,quo[12],rem_reg[47:44]);
div_1(rem_reg[47:44],dend[11],sor,quo[11],rem_reg[43:40]);
div_1(rem_reg[43:40],dend[10],sor,quo[10],rem_reg[39:36]);
div_1(rem_reg[39:36],dend[9],sor,quo[9],rem_reg[35:32]);
div_1(rem_reg[35:32],dend[8],sor,quo[8],rem_reg[31:28]);
div_1(rem_reg[31:28],dend[7],sor,quo[7],rem_reg[27:24]);
div_1(rem_reg[27:24],dend[6],sor,quo[6],rem_reg[23:20]);
div_1(rem_reg[23:20],dend[5],sor,quo[5],rem_reg[19:16]);
div_1(rem_reg[19:16],dend[4],sor,quo[4],rem_reg[15:12]);
div_1(rem_reg[15:12],dend[3],sor,quo[3],rem_reg[11:8]);
div_1(rem_reg[11:8],dend[2],sor,quo[2],rem_reg[7:4]);
div_1(rem_reg[7:4],dend[1],sor,quo[1],rem_reg[3:0]);
div_1(rem_reg[3:0],dend[0],sor,quo[0],rem);
endmodule | 0 |
139,307 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/11. in16tofpga/in16tofpga.v | 87,159,735 | in16tofpga.v | v | 90 | 262 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa1 in position 51: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/11.\n%Error: Cannot find file containing module: in16tofpga,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: in16tofpga/in16tofpga.v\n%Error: Exiting due to 6 error(s)\n' | 304,610 | module | module div_1(add_bit,d_dend,d_sor,quo,rem);
input d_dend;
input [3:0]d_sor,add_bit;
output quo;
output [3:0]rem;
assign quo=({add_bit,d_dend}<d_sor)?0:1;
assign rem=({add_bit,d_dend}<d_sor)?{add_bit,d_dend}:({add_bit,d_dend}-d_sor);
endmodule | module div_1(add_bit,d_dend,d_sor,quo,rem); |
input d_dend;
input [3:0]d_sor,add_bit;
output quo;
output [3:0]rem;
assign quo=({add_bit,d_dend}<d_sor)?0:1;
assign rem=({add_bit,d_dend}<d_sor)?{add_bit,d_dend}:({add_bit,d_dend}-d_sor);
endmodule | 0 |
139,308 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/11. in16tofpga/in16tofpga.v | 87,159,735 | in16tofpga.v | v | 90 | 262 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa1 in position 51: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/11.\n%Error: Cannot find file containing module: in16tofpga,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: in16tofpga/in16tofpga.v\n%Error: Exiting due to 6 error(s)\n' | 304,610 | module | module div(dend,sor,quo,rem);
input [13:0]dend;
input [3:0]sor;
output [13:0]quo;
output [3:0]rem;
wire [51:0]rem_reg;
div_1(0,dend[13],sor,quo[13],rem_reg[51:48]);
div_1(rem_reg[51:48],dend[12],sor,quo[12],rem_reg[47:44]);
div_1(rem_reg[47:44],dend[11],sor,quo[11],rem_reg[43:40]);
div_1(rem_reg[43:40],dend[10],sor,quo[10],rem_reg[39:36]);
div_1(rem_reg[39:36],dend[9],sor,quo[9],rem_reg[35:32]);
div_1(rem_reg[35:32],dend[8],sor,quo[8],rem_reg[31:28]);
div_1(rem_reg[31:28],dend[7],sor,quo[7],rem_reg[27:24]);
div_1(rem_reg[27:24],dend[6],sor,quo[6],rem_reg[23:20]);
div_1(rem_reg[23:20],dend[5],sor,quo[5],rem_reg[19:16]);
div_1(rem_reg[19:16],dend[4],sor,quo[4],rem_reg[15:12]);
div_1(rem_reg[15:12],dend[3],sor,quo[3],rem_reg[11:8]);
div_1(rem_reg[11:8],dend[2],sor,quo[2],rem_reg[7:4]);
div_1(rem_reg[7:4],dend[1],sor,quo[1],rem_reg[3:0]);
div_1(rem_reg[3:0],dend[0],sor,quo[0],rem);
endmodule | module div(dend,sor,quo,rem); |
input [13:0]dend;
input [3:0]sor;
output [13:0]quo;
output [3:0]rem;
wire [51:0]rem_reg;
div_1(0,dend[13],sor,quo[13],rem_reg[51:48]);
div_1(rem_reg[51:48],dend[12],sor,quo[12],rem_reg[47:44]);
div_1(rem_reg[47:44],dend[11],sor,quo[11],rem_reg[43:40]);
div_1(rem_reg[43:40],dend[10],sor,quo[10],rem_reg[39:36]);
div_1(rem_reg[39:36],dend[9],sor,quo[9],rem_reg[35:32]);
div_1(rem_reg[35:32],dend[8],sor,quo[8],rem_reg[31:28]);
div_1(rem_reg[31:28],dend[7],sor,quo[7],rem_reg[27:24]);
div_1(rem_reg[27:24],dend[6],sor,quo[6],rem_reg[23:20]);
div_1(rem_reg[23:20],dend[5],sor,quo[5],rem_reg[19:16]);
div_1(rem_reg[19:16],dend[4],sor,quo[4],rem_reg[15:12]);
div_1(rem_reg[15:12],dend[3],sor,quo[3],rem_reg[11:8]);
div_1(rem_reg[11:8],dend[2],sor,quo[2],rem_reg[7:4]);
div_1(rem_reg[7:4],dend[1],sor,quo[1],rem_reg[3:0]);
div_1(rem_reg[3:0],dend[0],sor,quo[0],rem);
endmodule | 0 |
139,309 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/11. in16tofpga/in16tofpga.v | 87,159,735 | in16tofpga.v | v | 90 | 262 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa1 in position 51: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/11.\n%Error: Cannot find file containing module: in16tofpga,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: in16tofpga/in16tofpga.v\n%Error: Exiting due to 6 error(s)\n' | 304,610 | module | module sing_bit(in14,out16_4);
input [13:0]in14;
output [15:0]out16_4;
wire [55:0]reg_out16_4;
div(in14,10,reg_out16_4[55:42],out16_4[3:0]);
div(reg_out16_4[55:42],10,reg_out16_4[41:28],out16_4[7:4]);
div(reg_out16_4[41:28],10,reg_out16_4[27:14],out16_4[11:8]);
div(reg_out16_4[27:14],10,reg_out16_4[13:0],out16_4[15:12]);
endmodule | module sing_bit(in14,out16_4); |
input [13:0]in14;
output [15:0]out16_4;
wire [55:0]reg_out16_4;
div(in14,10,reg_out16_4[55:42],out16_4[3:0]);
div(reg_out16_4[55:42],10,reg_out16_4[41:28],out16_4[7:4]);
div(reg_out16_4[41:28],10,reg_out16_4[27:14],out16_4[11:8]);
div(reg_out16_4[27:14],10,reg_out16_4[13:0],out16_4[15:12]);
endmodule | 0 |
139,310 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/11. in16tofpga/in16tofpga.v | 87,159,735 | in16tofpga.v | v | 90 | 262 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa1 in position 51: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/11.\n%Error: Cannot find file containing module: in16tofpga,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: in16tofpga/in16tofpga.v\n%Error: Exiting due to 6 error(s)\n' | 304,610 | module | module scan_com(in14,in2_scan,out2_sel,out4_scan);
input [13:0]in14;
input [1:0]in2_scan;
output [1:0]out2_sel;
output [3:0]out4_scan;
assign out2_sel[1]=(((in14>=100)&(in14<1000)&(in2_scan==2'b10))|((in14>=1000)&(in2_scan==2'b10))|((in14>=1000)&(in2_scan==2'b11)));
assign out2_sel[0]=(((in14>=10)&(in14<100)&(in2_scan==2'b01))|((in14>=10)&(in14<100)&(in2_scan==2'b11))|((in14>=100)&(in14<1000)&(in2_scan==2'b01))|((in14>=100)&(in14<1000)&(in2_scan==2'b11))|((in14>=1000)&(in2_scan==2'b01))|((in14>=1000)&(in2_scan==2'b11)));
assign out4_scan[3]=((out2_sel==2'b00)|(out2_sel==2'b01)|(out2_sel==2'b10));
assign out4_scan[2]=((out2_sel==2'b00)|(out2_sel==2'b01)|(out2_sel==2'b11));
assign out4_scan[1]=((out2_sel==2'b00)|(out2_sel==2'b10)|(out2_sel==2'b11));
assign out4_scan[0]=((out2_sel==2'b01)|(out2_sel==2'b10)|(out2_sel==2'b11));
endmodule | module scan_com(in14,in2_scan,out2_sel,out4_scan); |
input [13:0]in14;
input [1:0]in2_scan;
output [1:0]out2_sel;
output [3:0]out4_scan;
assign out2_sel[1]=(((in14>=100)&(in14<1000)&(in2_scan==2'b10))|((in14>=1000)&(in2_scan==2'b10))|((in14>=1000)&(in2_scan==2'b11)));
assign out2_sel[0]=(((in14>=10)&(in14<100)&(in2_scan==2'b01))|((in14>=10)&(in14<100)&(in2_scan==2'b11))|((in14>=100)&(in14<1000)&(in2_scan==2'b01))|((in14>=100)&(in14<1000)&(in2_scan==2'b11))|((in14>=1000)&(in2_scan==2'b01))|((in14>=1000)&(in2_scan==2'b11)));
assign out4_scan[3]=((out2_sel==2'b00)|(out2_sel==2'b01)|(out2_sel==2'b10));
assign out4_scan[2]=((out2_sel==2'b00)|(out2_sel==2'b01)|(out2_sel==2'b11));
assign out4_scan[1]=((out2_sel==2'b00)|(out2_sel==2'b10)|(out2_sel==2'b11));
assign out4_scan[0]=((out2_sel==2'b01)|(out2_sel==2'b10)|(out2_sel==2'b11));
endmodule | 0 |
139,311 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/11. in16tofpga/in16tofpga.v | 87,159,735 | in16tofpga.v | v | 90 | 262 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa1 in position 51: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/11.\n%Error: Cannot find file containing module: in16tofpga,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: in16tofpga/in16tofpga.v\n%Error: Exiting due to 6 error(s)\n' | 304,610 | module | module mul_16to4(in16_sing_bit,in2_sel,out4_sing_bit);
input [15:0]in16_sing_bit;
input [1:0]in2_sel;
output [3:0]out4_sing_bit;
assign out4_sing_bit=(in2_sel==0)?in16_sing_bit[3:0]:(in2_sel==1)?in16_sing_bit[7:4]:(in2_sel==2)?in16_sing_bit[11:8]:in16_sing_bit[15:12];
endmodule | module mul_16to4(in16_sing_bit,in2_sel,out4_sing_bit); |
input [15:0]in16_sing_bit;
input [1:0]in2_sel;
output [3:0]out4_sing_bit;
assign out4_sing_bit=(in2_sel==0)?in16_sing_bit[3:0]:(in2_sel==1)?in16_sing_bit[7:4]:(in2_sel==2)?in16_sing_bit[11:8]:in16_sing_bit[15:12];
endmodule | 0 |
139,312 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/11. in16tofpga/in16tofpga.v | 87,159,735 | in16tofpga.v | v | 90 | 262 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa1 in position 51: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/11.\n%Error: Cannot find file containing module: in16tofpga,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: in16tofpga/in16tofpga.v\n%Error: Exiting due to 6 error(s)\n' | 304,610 | module | module print_7(in4_sing_bit,out7_seg);
input [3:0] in4_sing_bit;
output [6:0]out7_seg;
assign out7_seg[0]=~((in4_sing_bit==0)|(in4_sing_bit==2)|(in4_sing_bit==3)|(in4_sing_bit==5)|(in4_sing_bit==6)|(in4_sing_bit==7)|(in4_sing_bit==8)|(in4_sing_bit==9)|(in4_sing_bit==10)|(in4_sing_bit==12)|(in4_sing_bit==14)|(in4_sing_bit==15));
assign out7_seg[1]=~((in4_sing_bit==0)|(in4_sing_bit==1)|(in4_sing_bit==2)|(in4_sing_bit==3)|(in4_sing_bit==4)|(in4_sing_bit==7)|(in4_sing_bit==8)|(in4_sing_bit==9)|(in4_sing_bit==10)|(in4_sing_bit==13));
assign out7_seg[2]=~((in4_sing_bit==0)|(in4_sing_bit==1)|(in4_sing_bit==3)|(in4_sing_bit==4)|(in4_sing_bit==5)|(in4_sing_bit==6)|(in4_sing_bit==7)|(in4_sing_bit==8)|(in4_sing_bit==9)|(in4_sing_bit==11)|(in4_sing_bit==13));
assign out7_seg[3]=~((in4_sing_bit==0)|(in4_sing_bit==2)|(in4_sing_bit==3)|(in4_sing_bit==5)|(in4_sing_bit==6)|(in4_sing_bit==8)|(in4_sing_bit==9)|(in4_sing_bit==10)|(in4_sing_bit==11)|(in4_sing_bit==12)|(in4_sing_bit==13)|(in4_sing_bit==14));
assign out7_seg[4]=~((in4_sing_bit==0)|(in4_sing_bit==2)|(in4_sing_bit==6)|(in4_sing_bit==8)|(in4_sing_bit==10)|(in4_sing_bit==11)|(in4_sing_bit==12)|(in4_sing_bit==13)|(in4_sing_bit==14)|(in4_sing_bit==15));
assign out7_seg[5]=~((in4_sing_bit==0)|(in4_sing_bit==4)|(in4_sing_bit==5)|(in4_sing_bit==6)|(in4_sing_bit==8)|(in4_sing_bit==9)|(in4_sing_bit==10)|(in4_sing_bit==11)|(in4_sing_bit==12)|(in4_sing_bit==14)|(in4_sing_bit==15));
assign out7_seg[6]=~((in4_sing_bit==2)|(in4_sing_bit==3)|(in4_sing_bit==4)|(in4_sing_bit==5)|(in4_sing_bit==6)|(in4_sing_bit==8)|(in4_sing_bit==9)|(in4_sing_bit==10)|(in4_sing_bit==11)|(in4_sing_bit==13)|(in4_sing_bit==14)|(in4_sing_bit==15));
endmodule | module print_7(in4_sing_bit,out7_seg); |
input [3:0] in4_sing_bit;
output [6:0]out7_seg;
assign out7_seg[0]=~((in4_sing_bit==0)|(in4_sing_bit==2)|(in4_sing_bit==3)|(in4_sing_bit==5)|(in4_sing_bit==6)|(in4_sing_bit==7)|(in4_sing_bit==8)|(in4_sing_bit==9)|(in4_sing_bit==10)|(in4_sing_bit==12)|(in4_sing_bit==14)|(in4_sing_bit==15));
assign out7_seg[1]=~((in4_sing_bit==0)|(in4_sing_bit==1)|(in4_sing_bit==2)|(in4_sing_bit==3)|(in4_sing_bit==4)|(in4_sing_bit==7)|(in4_sing_bit==8)|(in4_sing_bit==9)|(in4_sing_bit==10)|(in4_sing_bit==13));
assign out7_seg[2]=~((in4_sing_bit==0)|(in4_sing_bit==1)|(in4_sing_bit==3)|(in4_sing_bit==4)|(in4_sing_bit==5)|(in4_sing_bit==6)|(in4_sing_bit==7)|(in4_sing_bit==8)|(in4_sing_bit==9)|(in4_sing_bit==11)|(in4_sing_bit==13));
assign out7_seg[3]=~((in4_sing_bit==0)|(in4_sing_bit==2)|(in4_sing_bit==3)|(in4_sing_bit==5)|(in4_sing_bit==6)|(in4_sing_bit==8)|(in4_sing_bit==9)|(in4_sing_bit==10)|(in4_sing_bit==11)|(in4_sing_bit==12)|(in4_sing_bit==13)|(in4_sing_bit==14));
assign out7_seg[4]=~((in4_sing_bit==0)|(in4_sing_bit==2)|(in4_sing_bit==6)|(in4_sing_bit==8)|(in4_sing_bit==10)|(in4_sing_bit==11)|(in4_sing_bit==12)|(in4_sing_bit==13)|(in4_sing_bit==14)|(in4_sing_bit==15));
assign out7_seg[5]=~((in4_sing_bit==0)|(in4_sing_bit==4)|(in4_sing_bit==5)|(in4_sing_bit==6)|(in4_sing_bit==8)|(in4_sing_bit==9)|(in4_sing_bit==10)|(in4_sing_bit==11)|(in4_sing_bit==12)|(in4_sing_bit==14)|(in4_sing_bit==15));
assign out7_seg[6]=~((in4_sing_bit==2)|(in4_sing_bit==3)|(in4_sing_bit==4)|(in4_sing_bit==5)|(in4_sing_bit==6)|(in4_sing_bit==8)|(in4_sing_bit==9)|(in4_sing_bit==10)|(in4_sing_bit==11)|(in4_sing_bit==13)|(in4_sing_bit==14)|(in4_sing_bit==15));
endmodule | 0 |
139,313 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/11. in16tofpga/in16tofpga.v | 87,159,735 | in16tofpga.v | v | 90 | 262 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa1 in position 51: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/11.\n%Error: Cannot find file containing module: in16tofpga,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: in16tofpga/in16tofpga.v\n%Error: Exiting due to 6 error(s)\n' | 304,610 | module | module in16tofpga(in14,in2_scan,out4_scan,out7_seg);
input [13:0]in14;
input [1:0]in2_scan;
output [3:0]out4_scan;
output [6:0]out7_seg;
wire [15:0]io16_4;
wire [3:0]io4_sing_bit;
wire [1:0]io2_sel;
sing_bit(in14,io16_4);
mul_16to4(io16_4,io2_sel,io4_sing_bit);
print_7(io4_sing_bit,out7_seg);
scan_com(in14,in2_scan,io2_sel,out4_scan);
endmodule | module in16tofpga(in14,in2_scan,out4_scan,out7_seg); |
input [13:0]in14;
input [1:0]in2_scan;
output [3:0]out4_scan;
output [6:0]out7_seg;
wire [15:0]io16_4;
wire [3:0]io4_sing_bit;
wire [1:0]io2_sel;
sing_bit(in14,io16_4);
mul_16to4(io16_4,io2_sel,io4_sing_bit);
print_7(io4_sing_bit,out7_seg);
scan_com(in14,in2_scan,io2_sel,out4_scan);
endmodule | 0 |
139,314 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/12. prime/prime.v | 87,159,735 | prime.v | v | 81 | 179 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb9 in position 1450: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/12.\n%Error: Cannot find file containing module: prime,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: prime/prime.v\n%Error: Exiting due to 6 error(s)\n' | 304,611 | module | module prime(v,w,x,y,z,f);
input v,w,x,y,z;
output f;
reg f;
always@(v or w or x or y or z)
begin
case({v,w,x,y,z})
0,1,2,3,4,5,10,11,14,20,21,24,25,26,27,28,29,30:
f=1;
default:
f=0;
endcase
end
endmodule | module prime(v,w,x,y,z,f); |
input v,w,x,y,z;
output f;
reg f;
always@(v or w or x or y or z)
begin
case({v,w,x,y,z})
0,1,2,3,4,5,10,11,14,20,21,24,25,26,27,28,29,30:
f=1;
default:
f=0;
endcase
end
endmodule | 0 |
139,315 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/13. LAB7/count9999.v | 87,159,735 | count9999.v | v | 89 | 265 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa5 in position 33: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/13.\n%Error: Cannot find file containing module: LAB7,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: LAB7/count9999.v\n%Error: Exiting due to 6 error(s)\n' | 304,612 | module | module count9999(clk,scan,seg);
input clk;
output [3:0]scan;
output [6:0]seg;
wire div_1b;
wire [1:0]div_2b;
wire [15:0]num;
wire [1:0]sel;
wire [3:0]out_num;
div_fre(clk,div_1b,div_2b);
count(div_1b,num);
scan_com(num,div_2b,sel,scan);
mul_16to4(num,sel,out_num);
print_7(out_num,seg);
endmodule | module count9999(clk,scan,seg); |
input clk;
output [3:0]scan;
output [6:0]seg;
wire div_1b;
wire [1:0]div_2b;
wire [15:0]num;
wire [1:0]sel;
wire [3:0]out_num;
div_fre(clk,div_1b,div_2b);
count(div_1b,num);
scan_com(num,div_2b,sel,scan);
mul_16to4(num,sel,out_num);
print_7(out_num,seg);
endmodule | 0 |
139,316 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/13. LAB7/count9999.v | 87,159,735 | count9999.v | v | 89 | 265 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa5 in position 33: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/13.\n%Error: Cannot find file containing module: LAB7,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: LAB7/count9999.v\n%Error: Exiting due to 6 error(s)\n' | 304,612 | module | module scan_com(num,scan,sel,seg_scan);
input [15:0]num;
input [1:0]scan;
output [1:0]sel;
output [3:0]seg_scan;
assign sel[1]=((num[15:12]==0)&(num[11:8]!=0)&(scan==2'b10))|((num[15:12]!=0)&(scan==2'b10))|((num[15:12]!=0)&(scan==2'b11));
assign sel[0]=((num[15:8]==0)&(num[7:4]!=0)&(scan==2'b01))|((num[15:8]==0)&(num[7:4]!=0)&(scan==2'b11))|((num[15:12]==0)&(num[11:8]!=0)&(scan==2'b01))|((num[15:12]==0)&(num[11:8]!=0)&(scan==2'b11))|((num[15:12]!=0)&(scan==2'b01))|((num[15:12]!=0)&(scan==2'b11));
assign seg_scan[3]=((sel==2'b00)|(sel==2'b01)|(sel==2'b10));
assign seg_scan[2]=((sel==2'b00)|(sel==2'b01)|(sel==2'b11));
assign seg_scan[1]=((sel==2'b00)|(sel==2'b10)|(sel==2'b11));
assign seg_scan[0]=((sel==2'b01)|(sel==2'b10)|(sel==2'b11));
endmodule | module scan_com(num,scan,sel,seg_scan); |
input [15:0]num;
input [1:0]scan;
output [1:0]sel;
output [3:0]seg_scan;
assign sel[1]=((num[15:12]==0)&(num[11:8]!=0)&(scan==2'b10))|((num[15:12]!=0)&(scan==2'b10))|((num[15:12]!=0)&(scan==2'b11));
assign sel[0]=((num[15:8]==0)&(num[7:4]!=0)&(scan==2'b01))|((num[15:8]==0)&(num[7:4]!=0)&(scan==2'b11))|((num[15:12]==0)&(num[11:8]!=0)&(scan==2'b01))|((num[15:12]==0)&(num[11:8]!=0)&(scan==2'b11))|((num[15:12]!=0)&(scan==2'b01))|((num[15:12]!=0)&(scan==2'b11));
assign seg_scan[3]=((sel==2'b00)|(sel==2'b01)|(sel==2'b10));
assign seg_scan[2]=((sel==2'b00)|(sel==2'b01)|(sel==2'b11));
assign seg_scan[1]=((sel==2'b00)|(sel==2'b10)|(sel==2'b11));
assign seg_scan[0]=((sel==2'b01)|(sel==2'b10)|(sel==2'b11));
endmodule | 0 |
139,317 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/13. LAB7/count9999.v | 87,159,735 | count9999.v | v | 89 | 265 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa5 in position 33: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/13.\n%Error: Cannot find file containing module: LAB7,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: LAB7/count9999.v\n%Error: Exiting due to 6 error(s)\n' | 304,612 | module | module mul_16to4(num,sel,out_num);
input [15:0]num;
input [1:0]sel;
output [3:0]out_num;
assign out_num=(sel==0)?num[3:0]:(sel==1)?num[7:4]:(sel==2)?num[11:8]:num[15:12];
endmodule | module mul_16to4(num,sel,out_num); |
input [15:0]num;
input [1:0]sel;
output [3:0]out_num;
assign out_num=(sel==0)?num[3:0]:(sel==1)?num[7:4]:(sel==2)?num[11:8]:num[15:12];
endmodule | 0 |
139,318 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/13. LAB7/count9999.v | 87,159,735 | count9999.v | v | 89 | 265 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa5 in position 33: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/13.\n%Error: Cannot find file containing module: LAB7,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: LAB7/count9999.v\n%Error: Exiting due to 6 error(s)\n' | 304,612 | module | module div_fre(clk,div_1b,div_2b);
input clk;
output div_1b;
output [1:0]div_2b;
reg [15:0]div_reg;
assign div_1b=div_reg[15];
assign div_2b=div_reg[2:1];
always@(negedge clk)
begin
div_reg<=div_reg+1;
end
endmodule | module div_fre(clk,div_1b,div_2b); |
input clk;
output div_1b;
output [1:0]div_2b;
reg [15:0]div_reg;
assign div_1b=div_reg[15];
assign div_2b=div_reg[2:1];
always@(negedge clk)
begin
div_reg<=div_reg+1;
end
endmodule | 0 |
139,319 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/13. LAB7/count9999.v | 87,159,735 | count9999.v | v | 89 | 265 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa5 in position 33: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/13.\n%Error: Cannot find file containing module: LAB7,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: LAB7/count9999.v\n%Error: Exiting due to 6 error(s)\n' | 304,612 | module | module count(clk,con_num);
input clk;
output [15:0]con_num;
reg [15:0]con_num;
always@(negedge clk)
begin
con_num[3:0]<=con_num[3:0]+1;
if(con_num[3:0]>=9)
begin
con_num[3:0]<=0;
con_num[7:4]<=con_num[7:4]+1;
if(con_num[7:4]>=9)
begin
con_num[7:4]<=0;
con_num[11:8]<=con_num[11:8]+1;
if(con_num[11:8]>=9)
begin
con_num[11:8]<=0;
con_num[15:12]<=con_num[15:12]+1;
if(con_num[15:12]>=9)
begin
con_num[15:12]<=0;
end
end
end
end
end
endmodule | module count(clk,con_num); |
input clk;
output [15:0]con_num;
reg [15:0]con_num;
always@(negedge clk)
begin
con_num[3:0]<=con_num[3:0]+1;
if(con_num[3:0]>=9)
begin
con_num[3:0]<=0;
con_num[7:4]<=con_num[7:4]+1;
if(con_num[7:4]>=9)
begin
con_num[7:4]<=0;
con_num[11:8]<=con_num[11:8]+1;
if(con_num[11:8]>=9)
begin
con_num[11:8]<=0;
con_num[15:12]<=con_num[15:12]+1;
if(con_num[15:12]>=9)
begin
con_num[15:12]<=0;
end
end
end
end
end
endmodule | 0 |
139,320 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/13. LAB7/count9999.v | 87,159,735 | count9999.v | v | 89 | 265 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa5 in position 33: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/13.\n%Error: Cannot find file containing module: LAB7,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: LAB7/count9999.v\n%Error: Exiting due to 6 error(s)\n' | 304,612 | module | module print_7(bcd,seg);
input [3:0]bcd;
output [6:0]seg;
assign seg[0]=~((bcd==0)|(bcd==2)|(bcd==3)|(bcd==5)|(bcd==6)|(bcd==7)|(bcd==8)|(bcd==9)|(bcd==10)|(bcd==12)|(bcd==14)|(bcd==15));
assign seg[1]=~((bcd==0)|(bcd==1)|(bcd==2)|(bcd==3)|(bcd==4)|(bcd==7)|(bcd==8)|(bcd==9)|(bcd==10)|(bcd==13));
assign seg[2]=~((bcd==0)|(bcd==1)|(bcd==3)|(bcd==4)|(bcd==5)|(bcd==6)|(bcd==7)|(bcd==8)|(bcd==9)|(bcd==11)|(bcd==13));
assign seg[3]=~((bcd==0)|(bcd==2)|(bcd==3)|(bcd==5)|(bcd==6)|(bcd==8)|(bcd==9)|(bcd==10)|(bcd==11)|(bcd==12)|(bcd==13)|(bcd==14));
assign seg[4]=~((bcd==0)|(bcd==2)|(bcd==6)|(bcd==8)|(bcd==10)|(bcd==11)|(bcd==12)|(bcd==13)|(bcd==14)|(bcd==15));
assign seg[5]=~((bcd==0)|(bcd==4)|(bcd==5)|(bcd==6)|(bcd==8)|(bcd==9)|(bcd==10)|(bcd==11)|(bcd==12)|(bcd==14)|(bcd==15));
assign seg[6]=~((bcd==2)|(bcd==3)|(bcd==4)|(bcd==5)|(bcd==6)|(bcd==8)|(bcd==9)|(bcd==10)|(bcd==11)|(bcd==13)|(bcd==14)|(bcd==15));
endmodule | module print_7(bcd,seg); |
input [3:0]bcd;
output [6:0]seg;
assign seg[0]=~((bcd==0)|(bcd==2)|(bcd==3)|(bcd==5)|(bcd==6)|(bcd==7)|(bcd==8)|(bcd==9)|(bcd==10)|(bcd==12)|(bcd==14)|(bcd==15));
assign seg[1]=~((bcd==0)|(bcd==1)|(bcd==2)|(bcd==3)|(bcd==4)|(bcd==7)|(bcd==8)|(bcd==9)|(bcd==10)|(bcd==13));
assign seg[2]=~((bcd==0)|(bcd==1)|(bcd==3)|(bcd==4)|(bcd==5)|(bcd==6)|(bcd==7)|(bcd==8)|(bcd==9)|(bcd==11)|(bcd==13));
assign seg[3]=~((bcd==0)|(bcd==2)|(bcd==3)|(bcd==5)|(bcd==6)|(bcd==8)|(bcd==9)|(bcd==10)|(bcd==11)|(bcd==12)|(bcd==13)|(bcd==14));
assign seg[4]=~((bcd==0)|(bcd==2)|(bcd==6)|(bcd==8)|(bcd==10)|(bcd==11)|(bcd==12)|(bcd==13)|(bcd==14)|(bcd==15));
assign seg[5]=~((bcd==0)|(bcd==4)|(bcd==5)|(bcd==6)|(bcd==8)|(bcd==9)|(bcd==10)|(bcd==11)|(bcd==12)|(bcd==14)|(bcd==15));
assign seg[6]=~((bcd==2)|(bcd==3)|(bcd==4)|(bcd==5)|(bcd==6)|(bcd==8)|(bcd==9)|(bcd==10)|(bcd==11)|(bcd==13)|(bcd==14)|(bcd==15));
endmodule | 0 |
139,321 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/14. 74X138/ic74x138.v | 87,159,735 | ic74x138.v | v | 12 | 59 | [] | [] | [] | [(1, 12)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/14.\n%Error: Cannot find file containing module: 74X138,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: 74X138/ic74x138.v\n%Error: Exiting due to 6 error(s)\n' | 304,613 | module | module ic74x138(G1,G2A,G2B,C,B,A,Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0);
input G1,G2A,G2B,C,B,A;
output Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0;
assign Y7=~(G1&~G2A&~G2B&C&B&A);
assign Y6=~(G1&~G2A&~G2B&C&B&~A);
assign Y5=~(G1&~G2A&~G2B&C&~B&A);
assign Y4=~(G1&~G2A&~G2B&C&~B&~A);
assign Y3=~(G1&~G2A&~G2B&~C&B&A);
assign Y2=~(G1&~G2A&~G2B&~C&B&~A);
assign Y1=~(G1&~G2A&~G2B&~C&~B&A);
assign Y0=~(G1&~G2A&~G2B&~C&~B&~A);
endmodule | module ic74x138(G1,G2A,G2B,C,B,A,Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0); |
input G1,G2A,G2B,C,B,A;
output Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0;
assign Y7=~(G1&~G2A&~G2B&C&B&A);
assign Y6=~(G1&~G2A&~G2B&C&B&~A);
assign Y5=~(G1&~G2A&~G2B&C&~B&A);
assign Y4=~(G1&~G2A&~G2B&C&~B&~A);
assign Y3=~(G1&~G2A&~G2B&~C&B&A);
assign Y2=~(G1&~G2A&~G2B&~C&B&~A);
assign Y1=~(G1&~G2A&~G2B&~C&~B&A);
assign Y0=~(G1&~G2A&~G2B&~C&~B&~A);
endmodule | 0 |
139,322 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/15. FPS51/FPS51.v | 87,159,735 | FPS51.v | v | 155 | 82 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xad in position 80: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/15.\n%Error: Cannot find file containing module: FPS51,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: FPS51/FPS51.v\n%Error: Exiting due to 6 error(s)\n' | 304,614 | module | module FPS51(Enable_7Seg, display_7Seg,scan_clk);
output [3:0] Enable_7Seg;
output [7:0] display_7Seg;
input scan_clk;
wire [3:0] much_plus_sel;
reg [3:0] buffer;
reg [15:0] number;
reg [1:0] how_much;
reg [1:0] scan_signal;
reg [3:0] Enable_7Seg;
reg [7:0] display_7Seg;
reg [1:0] P3_Sel;
wire show_clk;
reg [13:0] P0P2_HL14;
Freq_Div(.clkout(show_clk), .clkin(scan_clk));
always @ (negedge show_clk)
begin
number[3:0] <= number[3:0] + 4'b0001 ;
if(number[3:0] >= 4'b1001)
begin
number[3:0] <= 4'b0000;
number[7:4] <= number[7:4] + 4'b0001;
if(number[7:4] >= 4'b1001)
begin
number[7:4] <= 4'b0000;
number[11:8] <= number[11:8] + 4'b0001;
if(number[11:8] >= 4'b1001)
begin
number[11:8] <= 4'b0000;
number[15:12] <= number[15:12] + 4'b0001;
if(number[15:12] >= 4'b1001)
number[15:12] <= 4'b0000;
end
end
end
end
always @ (scan_clk)
begin
P3_Sel = P3_Sel + 1; if(P3_Sel > 3 ) P3_Sel = 0;
end
always @ (number)
begin
P0P2_HL14 = number[15:12] + number[11:8] * 100 + number[7:4] * 10 + number[3:0];
end
assign much_plus_sel[3] = P3_Sel[1];
assign much_plus_sel[2] = P3_Sel[0];
assign much_plus_sel[1] = how_much[1];
assign much_plus_sel[0] = how_much[0];
always @ ( P0P2_HL14 )
begin
if(P0P2_HL14<10) how_much = 2'b00;
if((P0P2_HL14>=10) && (P0P2_HL14<100)) how_much = 2'b01;
if((P0P2_HL14>=100) && (P0P2_HL14<1000)) how_much = 2'b10;
if(P0P2_HL14>=1000) how_much = 2'b11;
end
always @ (P3_Sel or P0P2_HL14)
begin
case(much_plus_sel)
5 : scan_signal<=2'b01;
6 : scan_signal<=2'b01;
7 : scan_signal<=2'b01;
4'hA : scan_signal<=2'b10;
4'hB : scan_signal<=2'b10;
4'hD : scan_signal<=2'b01;
4'hF : scan_signal<=2'b11;
default:scan_signal=2'b00;
endcase
end
always @ (P3_Sel)
begin
case(scan_signal)
0 : Enable_7Seg <= 4'b1110;
1 : Enable_7Seg <= 4'b1101;
2 : Enable_7Seg <= 4'b1011;
3 : Enable_7Seg <= 4'b0111;
default: Enable_7Seg <= Enable_7Seg;
endcase
end
always @ (scan_signal)
begin
case(scan_signal)
0 : buffer = number[3:0];
1 : buffer = number[7:4];
2 : buffer = number[11:8];
3 : buffer = number[15:12];
endcase
end
always @ (buffer)
begin
case(buffer)
0 : display_7Seg=8'hc0;
1 : display_7Seg=8'hf9;
2 : display_7Seg=8'ha4;
3 : display_7Seg=8'hb0;
4 : display_7Seg=8'h99;
5 : display_7Seg=8'h92;
6 : display_7Seg=8'h82;
7 : display_7Seg=8'hf8;
8 : display_7Seg=8'h80;
9 : display_7Seg=8'h90;
default : display_7Seg=8'hfd;
endcase
end
endmodule | module FPS51(Enable_7Seg, display_7Seg,scan_clk); |
output [3:0] Enable_7Seg;
output [7:0] display_7Seg;
input scan_clk;
wire [3:0] much_plus_sel;
reg [3:0] buffer;
reg [15:0] number;
reg [1:0] how_much;
reg [1:0] scan_signal;
reg [3:0] Enable_7Seg;
reg [7:0] display_7Seg;
reg [1:0] P3_Sel;
wire show_clk;
reg [13:0] P0P2_HL14;
Freq_Div(.clkout(show_clk), .clkin(scan_clk));
always @ (negedge show_clk)
begin
number[3:0] <= number[3:0] + 4'b0001 ;
if(number[3:0] >= 4'b1001)
begin
number[3:0] <= 4'b0000;
number[7:4] <= number[7:4] + 4'b0001;
if(number[7:4] >= 4'b1001)
begin
number[7:4] <= 4'b0000;
number[11:8] <= number[11:8] + 4'b0001;
if(number[11:8] >= 4'b1001)
begin
number[11:8] <= 4'b0000;
number[15:12] <= number[15:12] + 4'b0001;
if(number[15:12] >= 4'b1001)
number[15:12] <= 4'b0000;
end
end
end
end
always @ (scan_clk)
begin
P3_Sel = P3_Sel + 1; if(P3_Sel > 3 ) P3_Sel = 0;
end
always @ (number)
begin
P0P2_HL14 = number[15:12] + number[11:8] * 100 + number[7:4] * 10 + number[3:0];
end
assign much_plus_sel[3] = P3_Sel[1];
assign much_plus_sel[2] = P3_Sel[0];
assign much_plus_sel[1] = how_much[1];
assign much_plus_sel[0] = how_much[0];
always @ ( P0P2_HL14 )
begin
if(P0P2_HL14<10) how_much = 2'b00;
if((P0P2_HL14>=10) && (P0P2_HL14<100)) how_much = 2'b01;
if((P0P2_HL14>=100) && (P0P2_HL14<1000)) how_much = 2'b10;
if(P0P2_HL14>=1000) how_much = 2'b11;
end
always @ (P3_Sel or P0P2_HL14)
begin
case(much_plus_sel)
5 : scan_signal<=2'b01;
6 : scan_signal<=2'b01;
7 : scan_signal<=2'b01;
4'hA : scan_signal<=2'b10;
4'hB : scan_signal<=2'b10;
4'hD : scan_signal<=2'b01;
4'hF : scan_signal<=2'b11;
default:scan_signal=2'b00;
endcase
end
always @ (P3_Sel)
begin
case(scan_signal)
0 : Enable_7Seg <= 4'b1110;
1 : Enable_7Seg <= 4'b1101;
2 : Enable_7Seg <= 4'b1011;
3 : Enable_7Seg <= 4'b0111;
default: Enable_7Seg <= Enable_7Seg;
endcase
end
always @ (scan_signal)
begin
case(scan_signal)
0 : buffer = number[3:0];
1 : buffer = number[7:4];
2 : buffer = number[11:8];
3 : buffer = number[15:12];
endcase
end
always @ (buffer)
begin
case(buffer)
0 : display_7Seg=8'hc0;
1 : display_7Seg=8'hf9;
2 : display_7Seg=8'ha4;
3 : display_7Seg=8'hb0;
4 : display_7Seg=8'h99;
5 : display_7Seg=8'h92;
6 : display_7Seg=8'h82;
7 : display_7Seg=8'hf8;
8 : display_7Seg=8'h80;
9 : display_7Seg=8'h90;
default : display_7Seg=8'hfd;
endcase
end
endmodule | 0 |
139,323 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/15. FPS51/FPS51.v | 87,159,735 | FPS51.v | v | 155 | 82 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xad in position 80: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/15.\n%Error: Cannot find file containing module: FPS51,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: FPS51/FPS51.v\n%Error: Exiting due to 6 error(s)\n' | 304,614 | module | module Freq_Div(clkout, clkin);
input clkin;
output clkout;
wire [8:0] tmp;
T_FF U6 (.Q(tmp[0]), .T(0), .clk(clkin));
T_FF U7 (.Q(tmp[1]), .T(0), .clk(tmp[0]));
T_FF U8 (.Q(tmp[2]), .T(0), .clk(tmp[1]));
T_FF U9 (.Q(tmp[3]), .T(0), .clk(tmp[2]));
T_FF U10(.Q(tmp[4]), .T(0), .clk(tmp[3]));
T_FF U11(.Q(tmp[5]), .T(0), .clk(tmp[4]));
T_FF U12(.Q(tmp[6]), .T(0), .clk(tmp[5]));
T_FF U13(.Q(tmp[7]), .T(0), .clk(tmp[6]));
T_FF U14(.Q(tmp[8]), .T(0), .clk(tmp[7]));
T_FF U15(.Q(clkout) , .T(0), .clk(tmp[8]));
endmodule | module Freq_Div(clkout, clkin); |
input clkin;
output clkout;
wire [8:0] tmp;
T_FF U6 (.Q(tmp[0]), .T(0), .clk(clkin));
T_FF U7 (.Q(tmp[1]), .T(0), .clk(tmp[0]));
T_FF U8 (.Q(tmp[2]), .T(0), .clk(tmp[1]));
T_FF U9 (.Q(tmp[3]), .T(0), .clk(tmp[2]));
T_FF U10(.Q(tmp[4]), .T(0), .clk(tmp[3]));
T_FF U11(.Q(tmp[5]), .T(0), .clk(tmp[4]));
T_FF U12(.Q(tmp[6]), .T(0), .clk(tmp[5]));
T_FF U13(.Q(tmp[7]), .T(0), .clk(tmp[6]));
T_FF U14(.Q(tmp[8]), .T(0), .clk(tmp[7]));
T_FF U15(.Q(clkout) , .T(0), .clk(tmp[8]));
endmodule | 0 |
139,324 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/15. FPS51/FPS51.v | 87,159,735 | FPS51.v | v | 155 | 82 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xad in position 80: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/15.\n%Error: Cannot find file containing module: FPS51,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: FPS51/FPS51.v\n%Error: Exiting due to 6 error(s)\n' | 304,614 | module | module T_FF(Q, T, clk);
input T, clk;
output Q;
reg Q;
always @ (negedge clk)
begin
if( T == 0 ) Q <= ~Q;
if( T == 1 ) Q <= Q;
end
endmodule | module T_FF(Q, T, clk); |
input T, clk;
output Q;
reg Q;
always @ (negedge clk)
begin
if( T == 0 ) Q <= ~Q;
if( T == 1 ) Q <= Q;
end
endmodule | 0 |
139,325 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/16. xor_4bit/xor_4bit.v | 87,159,735 | xor_4bit.v | v | 14 | 29 | [] | [] | [] | [(1, 5), (7, 14)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/16.\n%Error: Cannot find file containing module: xor_4bit,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: xor_4bit/xor_4bit.v\n%Error: Exiting due to 6 error(s)\n' | 304,615 | module | module xor_1bit(a,b,f);
input a,b;
output f;
assign f=(~a&b)|(a&~b);
endmodule | module xor_1bit(a,b,f); |
input a,b;
output f;
assign f=(~a&b)|(a&~b);
endmodule | 0 |
139,326 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/16. xor_4bit/xor_4bit.v | 87,159,735 | xor_4bit.v | v | 14 | 29 | [] | [] | [] | [(1, 5), (7, 14)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/16.\n%Error: Cannot find file containing module: xor_4bit,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: xor_4bit/xor_4bit.v\n%Error: Exiting due to 6 error(s)\n' | 304,615 | module | module xor_4bit(i,f);
input [3:0]i;
output f;
wire [1:0]re;
xor_1bit(i[3],i[2],re[1]);
xor_1bit(i[1],i[0],re[0]);
xor_1bit(re[1],re[0],f);
endmodule | module xor_4bit(i,f); |
input [3:0]i;
output f;
wire [1:0]re;
xor_1bit(i[3],i[2],re[1]);
xor_1bit(i[1],i[0],re[0]);
xor_1bit(re[1],re[0],f);
endmodule | 0 |
139,327 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/17. demul/demul.v | 87,159,735 | demul.v | v | 13 | 24 | [] | [] | [] | [(1, 13)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/17.\n%Error: Cannot find file containing module: demul,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: demul/demul.v\n%Error: Exiting due to 6 error(s)\n' | 304,616 | module | module demul(s,i,f);
input [2:0]s;
input i;
output [7:0]f;
assign f[0]=(s==0)&i;
assign f[1]=(s==1)&i;
assign f[2]=(s==2)&i;
assign f[3]=(s==3)&i;
assign f[4]=(s==4)&i;
assign f[5]=(s==5)&i;
assign f[6]=(s==6)&i;
assign f[7]=(s==7)&i;
endmodule | module demul(s,i,f); |
input [2:0]s;
input i;
output [7:0]f;
assign f[0]=(s==0)&i;
assign f[1]=(s==1)&i;
assign f[2]=(s==2)&i;
assign f[3]=(s==3)&i;
assign f[4]=(s==4)&i;
assign f[5]=(s==5)&i;
assign f[6]=(s==6)&i;
assign f[7]=(s==7)&i;
endmodule | 0 |
139,328 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/18. 74X85/ic74X85.v | 87,159,735 | ic74X85.v | v | 8 | 66 | [] | [] | [] | [(1, 8)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/18.\n%Error: Cannot find file containing module: 74X85,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: 74X85/ic74X85.v\n%Error: Exiting due to 6 error(s)\n' | 304,617 | module | module ic74X85(a,b,altbin,aeqbin,agtbin,altbout,aeqbout,agtbout);
input [3:0]a,b;
input altbin,aeqbin,agtbin;
output altbout,aeqbout,agtbout;
assign altbout=(a>b)|((a==b)&agtbin);
assign aeqbout=(a==b)&aeqbin;
assign agtbout=(a<b)|((a==b)&altbin);
endmodule | module ic74X85(a,b,altbin,aeqbin,agtbin,altbout,aeqbout,agtbout); |
input [3:0]a,b;
input altbin,aeqbin,agtbin;
output altbout,aeqbout,agtbout;
assign altbout=(a>b)|((a==b)&agtbin);
assign aeqbout=(a==b)&aeqbin;
assign agtbout=(a<b)|((a==b)&altbin);
endmodule | 0 |
139,329 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/19. mul/mul.v | 87,159,735 | mul.v | v | 13 | 33 | [] | [] | [] | [(1, 13)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/19.\n%Error: Cannot find file containing module: mul,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: mul/mul.v\n%Error: Exiting due to 6 error(s)\n' | 304,618 | module | module mul(a,b,c,d,e,f,g,h,s,y);
input [7:0]a,b,c,d,e,f,g,h;
input [2:0]s;
output[7:0]y;
assign y= (s==0)? a:
(s==1)? b:
(s==2)? c:
(s==3)? d:
(s==4)? e:
(s==5)? f:
(s==6)? g:
(s==7)? h:0;
endmodule | module mul(a,b,c,d,e,f,g,h,s,y); |
input [7:0]a,b,c,d,e,f,g,h;
input [2:0]s;
output[7:0]y;
assign y= (s==0)? a:
(s==1)? b:
(s==2)? c:
(s==3)? d:
(s==4)? e:
(s==5)? f:
(s==6)? g:
(s==7)? h:0;
endmodule | 0 |
139,330 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/20. ic74x85_32bits/ic74x85_32bits.v | 87,159,735 | ic74x85_32bits.v | v | 22 | 72 | [] | [] | [] | [(1, 8), (10, 22)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/20.\n%Error: Cannot find file containing module: ic74x85_32bits,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: ic74x85_32bits/ic74x85_32bits.v\n%Error: Exiting due to 6 error(s)\n' | 304,619 | module | module ic74x85(a,b,altbin,aeqbin,agtbin,altbout,aeqbout,agtbout);
input [3:0]a,b;
input altbin,aeqbin,agtbin;
output altbout,aeqbout,agtbout;
assign altbout=(a<b)|((a==b)&altbin);
assign aeqbout=(a==b)&aeqbin;
assign agtbout=(a>b)|((a==b)&agtbin);
endmodule | module ic74x85(a,b,altbin,aeqbin,agtbin,altbout,aeqbout,agtbout); |
input [3:0]a,b;
input altbin,aeqbin,agtbin;
output altbout,aeqbout,agtbout;
assign altbout=(a<b)|((a==b)&altbin);
assign aeqbout=(a==b)&aeqbin;
assign agtbout=(a>b)|((a==b)&agtbin);
endmodule | 0 |
139,331 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/20. ic74x85_32bits/ic74x85_32bits.v | 87,159,735 | ic74x85_32bits.v | v | 22 | 72 | [] | [] | [] | [(1, 8), (10, 22)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/20.\n%Error: Cannot find file containing module: ic74x85_32bits,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: ic74x85_32bits/ic74x85_32bits.v\n%Error: Exiting due to 6 error(s)\n' | 304,619 | module | module ic74x85_32bits(a,b,altbout,aeqbout,agtbout);
input [31:0]a,b;
output altbout,aeqbout,agtbout;
wire [6:0]alt,aeq,agt;
ic74x85(a[31:28],b[31:28],0,1,0,alt[6],aeq[6],agt[6]);
ic74x85(a[27:24],b[27:24],alt[6],aeq[6],agt[6],alt[5],aeq[5],agt[5]);
ic74x85(a[23:20],b[23:20],alt[5],aeq[5],agt[5],alt[4],aeq[4],agt[4]);
ic74x85(a[19:16],b[19:16],alt[4],aeq[4],agt[4],alt[3],aeq[3],agt[3]);
ic74x85(a[15:12],b[15:12],alt[3],aeq[3],agt[3],alt[2],aeq[2],agt[2]);
ic74x85(a[11:8],b[11:8],alt[2],aeq[2],agt[2],alt[1],aeq[1],agt[1]);
ic74x85(a[7:4],b[7:4],alt[1],aeq[1],agt[1],alt[0],aeq[0],agt[0]);
ic74x85(a[3:0],b[3:0],alt[0],aeq[0],agt[0],altbout,aeqbout,agtbout);
endmodule | module ic74x85_32bits(a,b,altbout,aeqbout,agtbout); |
input [31:0]a,b;
output altbout,aeqbout,agtbout;
wire [6:0]alt,aeq,agt;
ic74x85(a[31:28],b[31:28],0,1,0,alt[6],aeq[6],agt[6]);
ic74x85(a[27:24],b[27:24],alt[6],aeq[6],agt[6],alt[5],aeq[5],agt[5]);
ic74x85(a[23:20],b[23:20],alt[5],aeq[5],agt[5],alt[4],aeq[4],agt[4]);
ic74x85(a[19:16],b[19:16],alt[4],aeq[4],agt[4],alt[3],aeq[3],agt[3]);
ic74x85(a[15:12],b[15:12],alt[3],aeq[3],agt[3],alt[2],aeq[2],agt[2]);
ic74x85(a[11:8],b[11:8],alt[2],aeq[2],agt[2],alt[1],aeq[1],agt[1]);
ic74x85(a[7:4],b[7:4],alt[1],aeq[1],agt[1],alt[0],aeq[0],agt[0]);
ic74x85(a[3:0],b[3:0],alt[0],aeq[0],agt[0],altbout,aeqbout,agtbout);
endmodule | 0 |
139,332 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/21. adder_timing/adder.v | 87,159,735 | adder.v | v | 71 | 94 | [] | [] | [] | [(42, 60), (62, 71)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/21.\n%Error: Cannot find file containing module: adder_timing,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: adder_timing/adder.v\n%Error: Exiting due to 6 error(s)\n' | 304,620 | module | module cla_4bits(a,b,ci,co,s);
input [3:0]a,b;
input ci;
output [3:0]s;
output co;
wire [3:0]g,p,hs;
wire [2:0]c;
assign g=a&b;
assign p=a|b;
assign hs=((~a)&b)|(a&(~b));
assign c[0]=g[0]|(p[0]&ci);
assign c[1]=g[1]|(p[1]&g[0])|(p[1]&p[0]&ci);
assign c[2]=g[2]|(p[2]&g[1])|(p[2]&p[1]&g[0])|(p[2]&p[1]&p[0]&ci);
assign co=g[3]|(p[3]&g[2])|(p[3]&p[2]&g[1])|(p[3]&p[2]&p[1]&g[0])|(p[3]&p[2]&p[1]&p[0]&ci);
assign s[0]=((~hs[0])&ci)|(hs[0]&(~ci));
assign s[1]=((~hs[1])&c[0])|(hs[1]&(~c[0]));
assign s[2]=((~hs[2])&c[1])|(hs[2]&(~c[1]));
assign s[3]=((~hs[3])&c[2])|(hs[3]&(~c[2]));
endmodule | module cla_4bits(a,b,ci,co,s); |
input [3:0]a,b;
input ci;
output [3:0]s;
output co;
wire [3:0]g,p,hs;
wire [2:0]c;
assign g=a&b;
assign p=a|b;
assign hs=((~a)&b)|(a&(~b));
assign c[0]=g[0]|(p[0]&ci);
assign c[1]=g[1]|(p[1]&g[0])|(p[1]&p[0]&ci);
assign c[2]=g[2]|(p[2]&g[1])|(p[2]&p[1]&g[0])|(p[2]&p[1]&p[0]&ci);
assign co=g[3]|(p[3]&g[2])|(p[3]&p[2]&g[1])|(p[3]&p[2]&p[1]&g[0])|(p[3]&p[2]&p[1]&p[0]&ci);
assign s[0]=((~hs[0])&ci)|(hs[0]&(~ci));
assign s[1]=((~hs[1])&c[0])|(hs[1]&(~c[0]));
assign s[2]=((~hs[2])&c[1])|(hs[2]&(~c[1]));
assign s[3]=((~hs[3])&c[2])|(hs[3]&(~c[2]));
endmodule | 0 |
139,333 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/21. adder_timing/adder.v | 87,159,735 | adder.v | v | 71 | 94 | [] | [] | [] | [(42, 60), (62, 71)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/21.\n%Error: Cannot find file containing module: adder_timing,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: adder_timing/adder.v\n%Error: Exiting due to 6 error(s)\n' | 304,620 | module | module adder(x,y,co,s);
input [15:0]x,y;
output [15:0]s;
output co;
wire [2:0]c;
cla_4bits(x[3:0],y[3:0],0,c[0],s[3:0]);
cla_4bits(x[7:4],y[7:4],c[0],c[1],s[7:4]);
cla_4bits(x[11:8],y[11:8],c[1],c[2],s[11:8]);
cla_4bits(x[15:12],y[15:12],c[2],co,s[15:12]);
endmodule | module adder(x,y,co,s); |
input [15:0]x,y;
output [15:0]s;
output co;
wire [2:0]c;
cla_4bits(x[3:0],y[3:0],0,c[0],s[3:0]);
cla_4bits(x[7:4],y[7:4],c[0],c[1],s[7:4]);
cla_4bits(x[11:8],y[11:8],c[1],c[2],s[11:8]);
cla_4bits(x[15:12],y[15:12],c[2],co,s[15:12]);
endmodule | 0 |
139,334 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/22. mod5onehot/mod5onehot.v | 87,159,735 | mod5onehot.v | v | 40 | 42 | [] | [] | [] | [(1, 40)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/22.\n%Error: Cannot find file containing module: mod5onehot,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: mod5onehot/mod5onehot.v\n%Error: Exiting due to 6 error(s)\n' | 304,621 | module | module mod5onehot(clk,en,up,reset,max,q);
input clk,en,up,reset;
output max;
output [4:0]q;
reg [4:0]q;
assign max=(q[4]==1);
always@(negedge clk)
begin
if(reset==1)
begin
q<=5'b00001;
end
else
begin
if(en==0)
begin
q<=q;
end
else
begin
if(up==0)
begin
q[0]<=q[1];
q[1]<=q[2];
q[2]<=q[3];
q[3]<=q[4];
q[4]<=q[0];
end
else
begin
q[0]<=q[4];
q[1]<=q[0];
q[2]<=q[1];
q[3]<=q[2];
q[4]<=q[3];
end
end
end
end
endmodule | module mod5onehot(clk,en,up,reset,max,q); |
input clk,en,up,reset;
output max;
output [4:0]q;
reg [4:0]q;
assign max=(q[4]==1);
always@(negedge clk)
begin
if(reset==1)
begin
q<=5'b00001;
end
else
begin
if(en==0)
begin
q<=q;
end
else
begin
if(up==0)
begin
q[0]<=q[1];
q[1]<=q[2];
q[2]<=q[3];
q[3]<=q[4];
q[4]<=q[0];
end
else
begin
q[0]<=q[4];
q[1]<=q[0];
q[2]<=q[1];
q[3]<=q[2];
q[4]<=q[3];
end
end
end
end
endmodule | 0 |
139,335 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/23. LAB8/car.v | 87,159,735 | car.v | v | 57 | 78 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa5 in position 35: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/23.\n%Error: Cannot find file containing module: LAB8,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: LAB8/car.v\n%Error: Exiting due to 6 error(s)\n' | 304,622 | module | module car(clk,rst,r,l,halt,led);
input clk,rst,r,l,halt;
output [5:0]led;
wire div_clk;
reg [5:0]led;
div_fre div_one(.clk(clk),.div(div_clk));
always@(negedge clk)
begin
if(rst==0)
begin
led<=6'b111111;
end
else
begin
if(halt==1)
begin
led<=6'b000000;
end
else
begin
if((l==0)&&(r==1))
begin
led[5:3]<=3'b111;
led[0]<=(led[2:0]==3'b111)||(led[2:0]==3'b011)||(led[2:0]==3'b000);
led[1]<=(led[2:0]==3'b111)||(led[2:0]==3'b000);
led[2]<=(led[2:0]==3'b000);
end
else if((l==1)&&(r==0))
begin
led[2:0]<=3'b111;
led[3]<=(led[5:3]==3'b000);
led[4]<=(led[5:3]==3'b111)||(led[5:3]==3'b000);
led[5]<=(led[5:3]==3'b111)||(led[5:3]==3'b110)||(led[5:3]==3'b000);
end
else if((r==1)&&(l==1))
begin
led<=6'b000000;
end
else
begin
led<=6'b111111;
end
end
end
end
endmodule | module car(clk,rst,r,l,halt,led); |
input clk,rst,r,l,halt;
output [5:0]led;
wire div_clk;
reg [5:0]led;
div_fre div_one(.clk(clk),.div(div_clk));
always@(negedge clk)
begin
if(rst==0)
begin
led<=6'b111111;
end
else
begin
if(halt==1)
begin
led<=6'b000000;
end
else
begin
if((l==0)&&(r==1))
begin
led[5:3]<=3'b111;
led[0]<=(led[2:0]==3'b111)||(led[2:0]==3'b011)||(led[2:0]==3'b000);
led[1]<=(led[2:0]==3'b111)||(led[2:0]==3'b000);
led[2]<=(led[2:0]==3'b000);
end
else if((l==1)&&(r==0))
begin
led[2:0]<=3'b111;
led[3]<=(led[5:3]==3'b000);
led[4]<=(led[5:3]==3'b111)||(led[5:3]==3'b000);
led[5]<=(led[5:3]==3'b111)||(led[5:3]==3'b110)||(led[5:3]==3'b000);
end
else if((r==1)&&(l==1))
begin
led<=6'b000000;
end
else
begin
led<=6'b111111;
end
end
end
end
endmodule | 0 |
139,336 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/23. LAB8/car.v | 87,159,735 | car.v | v | 57 | 78 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa5 in position 35: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/23.\n%Error: Cannot find file containing module: LAB8,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: LAB8/car.v\n%Error: Exiting due to 6 error(s)\n' | 304,622 | module | module div_fre(clk,div);
input clk;
output div;
reg [23:0]div_reg;
assign div=div_reg[23];
always@(negedge clk)
begin
div_reg<=div_reg+1;
end
endmodule | module div_fre(clk,div); |
input clk;
output div;
reg [23:0]div_reg;
assign div=div_reg[23];
always@(negedge clk)
begin
div_reg<=div_reg+1;
end
endmodule | 0 |
139,337 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/24. mod5/mod5.v | 87,159,735 | mod5.v | v | 218 | 78 | [] | [] | [] | [(136, 218)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/24.\n%Error: Cannot find file containing module: mod5,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: mod5/mod5.v\n%Error: Exiting due to 6 error(s)\n' | 304,623 | module | module mod5(clk,en,up,q);
input clk,en,up;
output [2:0]q;
parameter s0=0,s1=1,s2=2,s3=3,s4=4;
reg [2:0]q,state;
always@(negedge clk)
begin
if(en==0)
begin
q<=q;
end
else
begin
case(state)
s0:
begin
q<=s0;
if(up==0)
begin
state<=s4;
end
else
begin
state<=s1;
end
end
s1:
begin
q<=s1;
if(up==0)
begin
state<=s0;
end
else
begin
state<=s2;
end
end
s2:
begin
q<=s2;
if(up==0)
begin
state<=s1;
end
else
begin
state<=s3;
end
end
s3:
begin
q<=s3;
if(up==0)
begin
state<=s2;
end
else
begin
state<=s4;
end
end
s4:
begin
q<=s4;
if(up==0)
begin
state<=s3;
end
else
begin
state<=s0;
end
end
default:
begin
state<=s0;
q<=s0;
end
endcase
end
end
endmodule | module mod5(clk,en,up,q); |
input clk,en,up;
output [2:0]q;
parameter s0=0,s1=1,s2=2,s3=3,s4=4;
reg [2:0]q,state;
always@(negedge clk)
begin
if(en==0)
begin
q<=q;
end
else
begin
case(state)
s0:
begin
q<=s0;
if(up==0)
begin
state<=s4;
end
else
begin
state<=s1;
end
end
s1:
begin
q<=s1;
if(up==0)
begin
state<=s0;
end
else
begin
state<=s2;
end
end
s2:
begin
q<=s2;
if(up==0)
begin
state<=s1;
end
else
begin
state<=s3;
end
end
s3:
begin
q<=s3;
if(up==0)
begin
state<=s2;
end
else
begin
state<=s4;
end
end
s4:
begin
q<=s4;
if(up==0)
begin
state<=s3;
end
else
begin
state<=s0;
end
end
default:
begin
state<=s0;
q<=s0;
end
endcase
end
end
endmodule | 0 |
139,338 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/26. c459/c459.v | 87,159,735 | c459.v | v | 22 | 30 | [] | [] | [] | [(1, 22)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/26.\n%Error: Cannot find file containing module: c459,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: c459/c459.v\n%Error: Exiting due to 6 error(s)\n' | 304,625 | module | module c459(v,w,x,y,z,f);
input v,w,x,y,z;
output f;
assign f= ({v,w,x,y,z}==0)|
({v,w,x,y,z}==1)|
({v,w,x,y,z}==2)|
({v,w,x,y,z}==3)|
({v,w,x,y,z}==4)|
({v,w,x,y,z}==5)|
({v,w,x,y,z}==10)|
({v,w,x,y,z}==11)|
({v,w,x,y,z}==14)|
({v,w,x,y,z}==20)|
({v,w,x,y,z}==21)|
({v,w,x,y,z}==24)|
({v,w,x,y,z}==25)|
({v,w,x,y,z}==26)|
({v,w,x,y,z}==27)|
({v,w,x,y,z}==28)|
({v,w,x,y,z}==29)|
({v,w,x,y,z}==30);
endmodule | module c459(v,w,x,y,z,f); |
input v,w,x,y,z;
output f;
assign f= ({v,w,x,y,z}==0)|
({v,w,x,y,z}==1)|
({v,w,x,y,z}==2)|
({v,w,x,y,z}==3)|
({v,w,x,y,z}==4)|
({v,w,x,y,z}==5)|
({v,w,x,y,z}==10)|
({v,w,x,y,z}==11)|
({v,w,x,y,z}==14)|
({v,w,x,y,z}==20)|
({v,w,x,y,z}==21)|
({v,w,x,y,z}==24)|
({v,w,x,y,z}==25)|
({v,w,x,y,z}==26)|
({v,w,x,y,z}==27)|
({v,w,x,y,z}==28)|
({v,w,x,y,z}==29)|
({v,w,x,y,z}==30);
endmodule | 0 |
139,339 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/27. stupid_car/stupid_car.v | 87,159,735 | stupid_car.v | v | 83 | 94 | [] | [] | [] | [(1, 83)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/27.\n%Error: Cannot find file containing module: stupid_car,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: stupid_car/stupid_car.v\n%Error: Exiting due to 6 error(s)\n' | 304,626 | module | module stupid_car(clk,rst,stupid_in,r,l,halt,led);
input clk,rst,stupid_in,r,l,halt;
output [5:0]led;
parameter l3=6'b111_000,l2=6'b011_000,l1=6'b001_000,
r1=6'b000_100,r2=6'b000_110,r3=6'b000_111,
idle=6'b000_000,haz=6'b111_1111;
reg [5:0]state,stupid_count;
assign led=~state;
always@(negedge div_clk)
case(state)
idle:
if(rst==0)
state<=idle;
else if((stupid_in==1)||((stupid_count>=1)&&(stupid_count<=20)&&(stupid_count%2==0)))
begin
state<=idle;
stupid_count<=stupid_count+1;
end
else if((stupid_in==1)||((stupid_count>=1)&&(stupid_count<=20)&&(stupid_count%2==1)))
begin
state<=haz;
stupid_count<=stupid_count+1;
end
else
begin
stupid_count<=0;
if(halt==1||((l==1)&&(r==1)))
state<=haz;
else
if((l==0)&&(r==0))
state<=idle;
else if((l==0)&&(r==1))
state<=r1;
else if((l==1)&&(r==0))
state<=l1;
end
haz:
if((stupid_in==1)||((stupid_count>=1)&&(stupid_count<=20)&&(stupid_count%2==0)))
begin
state<=idle;
stupid_count<=stupid_count+1;
end
else if((stupid_in==1)||((stupid_count>=1)&&(stupid_count<=20)&&(stupid_count%2==1)))
begin
state<=haz;
stupid_count<=stupid_count+1;
end
else if(((l==1)&&(r==1))||(halt==1))
begin
stupid_count<=0;
state<=haz;
end
else
begin
stupid_count<=0;
state<=idle;
end
l3:
state<=idle;
l2:
if(rst==0)
state<=idle;
else
state<=l3;
l1:
if(rst==0)
state<=idle;
else
state<=l2;
r1:
if(rst==0)
state<=idle;
else
state<=r2;
r2:
if(rst==0)
state<=idle;
else
state<=r3;
r3:
state<=idle;
endcase
endmodule | module stupid_car(clk,rst,stupid_in,r,l,halt,led); |
input clk,rst,stupid_in,r,l,halt;
output [5:0]led;
parameter l3=6'b111_000,l2=6'b011_000,l1=6'b001_000,
r1=6'b000_100,r2=6'b000_110,r3=6'b000_111,
idle=6'b000_000,haz=6'b111_1111;
reg [5:0]state,stupid_count;
assign led=~state;
always@(negedge div_clk)
case(state)
idle:
if(rst==0)
state<=idle;
else if((stupid_in==1)||((stupid_count>=1)&&(stupid_count<=20)&&(stupid_count%2==0)))
begin
state<=idle;
stupid_count<=stupid_count+1;
end
else if((stupid_in==1)||((stupid_count>=1)&&(stupid_count<=20)&&(stupid_count%2==1)))
begin
state<=haz;
stupid_count<=stupid_count+1;
end
else
begin
stupid_count<=0;
if(halt==1||((l==1)&&(r==1)))
state<=haz;
else
if((l==0)&&(r==0))
state<=idle;
else if((l==0)&&(r==1))
state<=r1;
else if((l==1)&&(r==0))
state<=l1;
end
haz:
if((stupid_in==1)||((stupid_count>=1)&&(stupid_count<=20)&&(stupid_count%2==0)))
begin
state<=idle;
stupid_count<=stupid_count+1;
end
else if((stupid_in==1)||((stupid_count>=1)&&(stupid_count<=20)&&(stupid_count%2==1)))
begin
state<=haz;
stupid_count<=stupid_count+1;
end
else if(((l==1)&&(r==1))||(halt==1))
begin
stupid_count<=0;
state<=haz;
end
else
begin
stupid_count<=0;
state<=idle;
end
l3:
state<=idle;
l2:
if(rst==0)
state<=idle;
else
state<=l3;
l1:
if(rst==0)
state<=idle;
else
state<=l2;
r1:
if(rst==0)
state<=idle;
else
state<=r2;
r2:
if(rst==0)
state<=idle;
else
state<=r3;
r3:
state<=idle;
endcase
endmodule | 0 |
139,340 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/28. lab8_new2/car.v | 87,159,735 | car.v | v | 78 | 55 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb0 in position 26: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/28.\n%Error: Cannot find file containing module: lab8_new2,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: lab8_new2/car.v\n%Error: Exiting due to 6 error(s)\n' | 304,627 | module | module div_fre(clk,div);
input clk;
output div;
reg [23:0]div_reg;
assign div=div_reg[23];
always@(negedge clk)
begin
div_reg<=div_reg+1;
end
endmodule | module div_fre(clk,div); |
input clk;
output div;
reg [23:0]div_reg;
assign div=div_reg[23];
always@(negedge clk)
begin
div_reg<=div_reg+1;
end
endmodule | 0 |
139,341 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/28. lab8_new2/car.v | 87,159,735 | car.v | v | 78 | 55 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb0 in position 26: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/28.\n%Error: Cannot find file containing module: lab8_new2,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: lab8_new2/car.v\n%Error: Exiting due to 6 error(s)\n' | 304,627 | module | module car(clk,rst,r,l,halt,led);
input clk,rst,r,l,halt;
output [5:0]led;
parameter l3=6'b111_000,l2=6'b011_000,l1=6'b001_000,
r1=6'b000_100,r2=6'b000_110,r3=6'b000_111,
idle=6'b000_000,haz=6'b111_1111;
reg [5:0]state;
assign led=~state;
div_fre div_one(.clk(clk),.div(div_clk));
always@(negedge clk)
case(state)
idle:
if(rst==0)
state<=idle;
else
if(halt==1||((l==1)&&(r==1)))
state<=haz;
else
if((l==0)&&(r==0))
state<=idle;
else if((l==0)&&(r==1))
state<=r1;
else if((l==1)&&(r==0))
state<=l1;
haz:
if(((l==1)&&(r==1))||(halt==1))
state<=haz;
else
state<=idle;
l3:
state<=idle;
l2:
if(rst==0)
state<=idle;
else
if(~(halt==0)||~(l==1)||~(r==0))
state<=idle;
else
state<=l3;
l1:
if(rst==0)
state<=idle;
else
if(~(halt==0)||~(l==1)||~(r==0))
state<=idle;
else
state<=l2;
r1:
if(rst==0)
state<=idle;
else
if(~(halt==0)||~(l==0)||~(r==1))
state<=idle;
else
state<=r2;
r2:
if(rst==0)
state<=idle;
else
if(~(halt==0)||~(l==0)||~(r==1))
state<=idle;
else
state<=r3;
r3:
state<=idle;
endcase
endmodule | module car(clk,rst,r,l,halt,led); |
input clk,rst,r,l,halt;
output [5:0]led;
parameter l3=6'b111_000,l2=6'b011_000,l1=6'b001_000,
r1=6'b000_100,r2=6'b000_110,r3=6'b000_111,
idle=6'b000_000,haz=6'b111_1111;
reg [5:0]state;
assign led=~state;
div_fre div_one(.clk(clk),.div(div_clk));
always@(negedge clk)
case(state)
idle:
if(rst==0)
state<=idle;
else
if(halt==1||((l==1)&&(r==1)))
state<=haz;
else
if((l==0)&&(r==0))
state<=idle;
else if((l==0)&&(r==1))
state<=r1;
else if((l==1)&&(r==0))
state<=l1;
haz:
if(((l==1)&&(r==1))||(halt==1))
state<=haz;
else
state<=idle;
l3:
state<=idle;
l2:
if(rst==0)
state<=idle;
else
if(~(halt==0)||~(l==1)||~(r==0))
state<=idle;
else
state<=l3;
l1:
if(rst==0)
state<=idle;
else
if(~(halt==0)||~(l==1)||~(r==0))
state<=idle;
else
state<=l2;
r1:
if(rst==0)
state<=idle;
else
if(~(halt==0)||~(l==0)||~(r==1))
state<=idle;
else
state<=r2;
r2:
if(rst==0)
state<=idle;
else
if(~(halt==0)||~(l==0)||~(r==1))
state<=idle;
else
state<=r3;
r3:
state<=idle;
endcase
endmodule | 0 |
139,342 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/29. 0528_combinational_multiplier/mul8x8.v | 87,159,735 | mul8x8.v | v | 87 | 54 | [] | [] | [] | [(1, 86)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/29.\n%Error: Cannot find file containing module: 0528_combinational_multiplier,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: 0528_combinational_multiplier/mul8x8.v\n%Error: Exiting due to 6 error(s)\n' | 304,628 | module | module mul8x8(x,y,p);
input [7:0]x,y;
output [15:0]p;
wire [55:0]s,c;
assign {c[0],s[0]}=(y[0]&x[1])+(y[1]&x[0]);
assign {c[1],s[1]}=(y[0]&x[2])+(y[1]&x[1]);
assign {c[2],s[2]}=(y[0]&x[3])+(y[1]&x[2]);
assign {c[3],s[3]}=(y[0]&x[4])+(y[1]&x[3]);
assign {c[4],s[4]}=(y[0]&x[5])+(y[1]&x[4]);
assign {c[5],s[5]}=(y[0]&x[6])+(y[1]&x[5]);
assign {c[6],s[6]}=(y[0]&x[7])+(y[1]&x[6]);
assign {c[7],s[7]}=c[0]+s[1]+(y[2]&x[0]);
assign {c[8],s[8]}=c[1]+s[2]+(y[2]&x[1]);
assign {c[9],s[9]}=c[2]+s[3]+(y[2]&x[2]);
assign {c[10],s[10]}=c[3]+s[4]+(y[2]&x[3]);
assign {c[11],s[11]}=c[4]+s[5]+(y[2]&x[4]);
assign {c[12],s[12]}=c[5]+s[6]+(y[2]&x[5]);
assign {c[13],s[13]}=c[6]+(y[1]&x[7])+(y[2]&x[6]);
assign {c[14],s[14]}=c[7]+s[8]+(y[3]&x[0]);
assign {c[15],s[15]}=c[8]+s[9]+(y[3]&x[1]);
assign {c[16],s[16]}=c[9]+s[10]+(y[3]&x[2]);
assign {c[17],s[17]}=c[10]+s[11]+(y[3]&x[3]);
assign {c[18],s[18]}=c[11]+s[12]+(y[3]&x[4]);
assign {c[19],s[19]}=c[12]+s[13]+(y[3]&x[5]);
assign {c[20],s[20]}=c[13]+(y[2]&x[7])+(y[3]&x[6]);
assign {c[21],s[21]}=c[14]+s[15]+(y[4]&x[0]);
assign {c[22],s[22]}=c[15]+s[16]+(y[4]&x[1]);
assign {c[23],s[23]}=c[16]+s[17]+(y[4]&x[2]);
assign {c[24],s[24]}=c[17]+s[18]+(y[4]&x[3]);
assign {c[25],s[25]}=c[18]+s[19]+(y[4]&x[4]);
assign {c[26],s[26]}=c[19]+s[20]+(y[4]&x[5]);
assign {c[27],s[27]}=c[20]+(y[3]&x[7])+(y[4]&x[6]);
assign {c[28],s[28]}=c[21]+s[22]+(y[5]&x[0]);
assign {c[29],s[29]}=c[22]+s[23]+(y[5]&x[1]);
assign {c[30],s[30]}=c[23]+s[24]+(y[5]&x[2]);
assign {c[31],s[31]}=c[24]+s[25]+(y[5]&x[3]);
assign {c[32],s[32]}=c[25]+s[26]+(y[5]&x[4]);
assign {c[33],s[33]}=c[26]+s[27]+(y[5]&x[5]);
assign {c[34],s[34]}=c[27]+(y[4]&x[7])+(y[5]&x[6]);
assign {c[35],s[35]}=c[28]+s[29]+(y[6]&x[0]);
assign {c[36],s[36]}=c[29]+s[30]+(y[6]&x[1]);
assign {c[37],s[37]}=c[30]+s[31]+(y[6]&x[2]);
assign {c[38],s[38]}=c[31]+s[32]+(y[6]&x[3]);
assign {c[39],s[39]}=c[32]+s[33]+(y[6]&x[4]);
assign {c[40],s[40]}=c[33]+s[34]+(y[6]&x[5]);
assign {c[41],s[41]}=c[34]+(y[5]&x[7])+(y[6]&x[6]);
assign {c[42],s[42]}=c[35]+s[36]+(y[7]&x[0]);
assign {c[43],s[43]}=c[36]+s[37]+(y[7]&x[1]);
assign {c[44],s[44]}=c[37]+s[38]+(y[7]&x[2]);
assign {c[45],s[45]}=c[38]+s[39]+(y[7]&x[3]);
assign {c[46],s[46]}=c[39]+s[40]+(y[7]&x[4]);
assign {c[47],s[47]}=c[40]+s[41]+(y[7]&x[5]);
assign {c[48],s[48]}=c[41]+(y[6]&x[7])+(y[7]&x[6]);
assign {c[49],s[49]}=c[42]+s[43];
assign {c[50],s[50]}=c[49]+c[43]+s[44];
assign {c[51],s[51]}=c[50]+c[44]+s[45];
assign {c[52],s[52]}=c[51]+c[45]+s[46];
assign {c[53],s[53]}=c[52]+c[46]+s[47];
assign {c[54],s[54]}=c[53]+c[47]+s[48];
assign {c[55],s[55]}=c[54]+c[48]+(y[7]&x[7]);
assign p[0]=(y[0]&x[0]);
assign p[1]=s[0];
assign p[2]=s[7];
assign p[3]=s[14];
assign p[4]=s[21];
assign p[5]=s[28];
assign p[6]=s[35];
assign p[7]=s[42];
assign p[8]=s[49];
assign p[9]=s[50];
assign p[10]=s[51];
assign p[11]=s[52];
assign p[12]=s[53];
assign p[13]=s[54];
assign p[14]=s[55];
assign p[15]=c[55];
endmodule | module mul8x8(x,y,p); |
input [7:0]x,y;
output [15:0]p;
wire [55:0]s,c;
assign {c[0],s[0]}=(y[0]&x[1])+(y[1]&x[0]);
assign {c[1],s[1]}=(y[0]&x[2])+(y[1]&x[1]);
assign {c[2],s[2]}=(y[0]&x[3])+(y[1]&x[2]);
assign {c[3],s[3]}=(y[0]&x[4])+(y[1]&x[3]);
assign {c[4],s[4]}=(y[0]&x[5])+(y[1]&x[4]);
assign {c[5],s[5]}=(y[0]&x[6])+(y[1]&x[5]);
assign {c[6],s[6]}=(y[0]&x[7])+(y[1]&x[6]);
assign {c[7],s[7]}=c[0]+s[1]+(y[2]&x[0]);
assign {c[8],s[8]}=c[1]+s[2]+(y[2]&x[1]);
assign {c[9],s[9]}=c[2]+s[3]+(y[2]&x[2]);
assign {c[10],s[10]}=c[3]+s[4]+(y[2]&x[3]);
assign {c[11],s[11]}=c[4]+s[5]+(y[2]&x[4]);
assign {c[12],s[12]}=c[5]+s[6]+(y[2]&x[5]);
assign {c[13],s[13]}=c[6]+(y[1]&x[7])+(y[2]&x[6]);
assign {c[14],s[14]}=c[7]+s[8]+(y[3]&x[0]);
assign {c[15],s[15]}=c[8]+s[9]+(y[3]&x[1]);
assign {c[16],s[16]}=c[9]+s[10]+(y[3]&x[2]);
assign {c[17],s[17]}=c[10]+s[11]+(y[3]&x[3]);
assign {c[18],s[18]}=c[11]+s[12]+(y[3]&x[4]);
assign {c[19],s[19]}=c[12]+s[13]+(y[3]&x[5]);
assign {c[20],s[20]}=c[13]+(y[2]&x[7])+(y[3]&x[6]);
assign {c[21],s[21]}=c[14]+s[15]+(y[4]&x[0]);
assign {c[22],s[22]}=c[15]+s[16]+(y[4]&x[1]);
assign {c[23],s[23]}=c[16]+s[17]+(y[4]&x[2]);
assign {c[24],s[24]}=c[17]+s[18]+(y[4]&x[3]);
assign {c[25],s[25]}=c[18]+s[19]+(y[4]&x[4]);
assign {c[26],s[26]}=c[19]+s[20]+(y[4]&x[5]);
assign {c[27],s[27]}=c[20]+(y[3]&x[7])+(y[4]&x[6]);
assign {c[28],s[28]}=c[21]+s[22]+(y[5]&x[0]);
assign {c[29],s[29]}=c[22]+s[23]+(y[5]&x[1]);
assign {c[30],s[30]}=c[23]+s[24]+(y[5]&x[2]);
assign {c[31],s[31]}=c[24]+s[25]+(y[5]&x[3]);
assign {c[32],s[32]}=c[25]+s[26]+(y[5]&x[4]);
assign {c[33],s[33]}=c[26]+s[27]+(y[5]&x[5]);
assign {c[34],s[34]}=c[27]+(y[4]&x[7])+(y[5]&x[6]);
assign {c[35],s[35]}=c[28]+s[29]+(y[6]&x[0]);
assign {c[36],s[36]}=c[29]+s[30]+(y[6]&x[1]);
assign {c[37],s[37]}=c[30]+s[31]+(y[6]&x[2]);
assign {c[38],s[38]}=c[31]+s[32]+(y[6]&x[3]);
assign {c[39],s[39]}=c[32]+s[33]+(y[6]&x[4]);
assign {c[40],s[40]}=c[33]+s[34]+(y[6]&x[5]);
assign {c[41],s[41]}=c[34]+(y[5]&x[7])+(y[6]&x[6]);
assign {c[42],s[42]}=c[35]+s[36]+(y[7]&x[0]);
assign {c[43],s[43]}=c[36]+s[37]+(y[7]&x[1]);
assign {c[44],s[44]}=c[37]+s[38]+(y[7]&x[2]);
assign {c[45],s[45]}=c[38]+s[39]+(y[7]&x[3]);
assign {c[46],s[46]}=c[39]+s[40]+(y[7]&x[4]);
assign {c[47],s[47]}=c[40]+s[41]+(y[7]&x[5]);
assign {c[48],s[48]}=c[41]+(y[6]&x[7])+(y[7]&x[6]);
assign {c[49],s[49]}=c[42]+s[43];
assign {c[50],s[50]}=c[49]+c[43]+s[44];
assign {c[51],s[51]}=c[50]+c[44]+s[45];
assign {c[52],s[52]}=c[51]+c[45]+s[46];
assign {c[53],s[53]}=c[52]+c[46]+s[47];
assign {c[54],s[54]}=c[53]+c[47]+s[48];
assign {c[55],s[55]}=c[54]+c[48]+(y[7]&x[7]);
assign p[0]=(y[0]&x[0]);
assign p[1]=s[0];
assign p[2]=s[7];
assign p[3]=s[14];
assign p[4]=s[21];
assign p[5]=s[28];
assign p[6]=s[35];
assign p[7]=s[42];
assign p[8]=s[49];
assign p[9]=s[50];
assign p[10]=s[51];
assign p[11]=s[52];
assign p[12]=s[53];
assign p[13]=s[54];
assign p[14]=s[55];
assign p[15]=c[55];
endmodule | 0 |
139,343 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/30. ch7_43/ch7_43.v | 87,159,735 | ch7_43.v | v | 86 | 50 | [] | [] | [] | [(1, 86)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/30.\n%Error: Cannot find file containing module: ch7_43,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: ch7_43/ch7_43.v\n%Error: Exiting due to 6 error(s)\n' | 304,629 | module | module ch7_43(clk,init,x,z);
parameter idle=0,l1=1,l2=2,l3=3,r1=4,r2=5,r3=6;
input init,x,clk;
output z;
reg z;
reg [2:0]state;
always@(posedge clk)
begin
case(state)
idle:
if(init==1)
z<=0;
else
if(x==0)
state<=l1;
else
state<=r1;
l1:
if(init==1)
begin
z<=0;
state<=idle;
end
else
if(x==0)
state<=l2;
else
state<=r1;
l2:
if(init==1)
begin
z<=0;
state<=idle;
end
else
if(x==0)
state<=l2;
else
state<=l3;
l3:
if(init==1)
begin
z<=0;
state<=idle;
end
else
if(x==0)
state<=l1;
else
z<=1;
r1:
if(init==1)
begin
z<=0;
state<=idle;
end
else
if(x==0)
state<=l1;
else
state<=r2;
r2:
if(init==1)
begin
z<=0;
state<=idle;
end
else
if(x==0)
state<=r3;
else
state<=r2;
r3:
if(init==1)
begin
z<=0;
state<=idle;
end
else
if(x==0)
z<=1;
else
state<=r1;
endcase
end
endmodule | module ch7_43(clk,init,x,z); |
parameter idle=0,l1=1,l2=2,l3=3,r1=4,r2=5,r3=6;
input init,x,clk;
output z;
reg z;
reg [2:0]state;
always@(posedge clk)
begin
case(state)
idle:
if(init==1)
z<=0;
else
if(x==0)
state<=l1;
else
state<=r1;
l1:
if(init==1)
begin
z<=0;
state<=idle;
end
else
if(x==0)
state<=l2;
else
state<=r1;
l2:
if(init==1)
begin
z<=0;
state<=idle;
end
else
if(x==0)
state<=l2;
else
state<=l3;
l3:
if(init==1)
begin
z<=0;
state<=idle;
end
else
if(x==0)
state<=l1;
else
z<=1;
r1:
if(init==1)
begin
z<=0;
state<=idle;
end
else
if(x==0)
state<=l1;
else
state<=r2;
r2:
if(init==1)
begin
z<=0;
state<=idle;
end
else
if(x==0)
state<=r3;
else
state<=r2;
r3:
if(init==1)
begin
z<=0;
state<=idle;
end
else
if(x==0)
z<=1;
else
state<=r1;
endcase
end
endmodule | 0 |
139,344 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/32. johnson_counters/johnson_counters.v | 87,159,735 | johnson_counters.v | v | 39 | 130 | [] | [] | [] | [(1, 12), (14, 30), (32, 38)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/32.\n%Error: Cannot find file containing module: johnson_counters,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: johnson_counters/johnson_counters.v\n%Error: Exiting due to 6 error(s)\n' | 304,631 | module | module d_ff(clk,clr,d,q);
input clk,clr,d;
output q;
reg q;
always@(negedge clk)
begin
if(clr==0)
q<=0;
else
q<=d;
end
endmodule | module d_ff(clk,clr,d,q); |
input clk,clr,d;
output q;
reg q;
always@(negedge clk)
begin
if(clr==0)
q<=0;
else
q<=d;
end
endmodule | 0 |
139,345 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/32. johnson_counters/johnson_counters.v | 87,159,735 | johnson_counters.v | v | 39 | 130 | [] | [] | [] | [(1, 12), (14, 30), (32, 38)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/32.\n%Error: Cannot find file containing module: johnson_counters,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: johnson_counters/johnson_counters.v\n%Error: Exiting due to 6 error(s)\n' | 304,631 | module | module ic74x194(clk,clr,s1,s0,lin,d,c,b,a,rin,qd,qc,qb,qa);
input clk,clr,s1,s0,lin,d,c,b,a,rin;
output qd,qc,qb,qa;
wire [3:0]d_wire,q_wire;
d_ff(.clk(~clk),.clr(clr),.d(d_wire[3]),.q(q_wire[3]));
d_ff(.clk(~clk),.clr(clr),.d(d_wire[2]),.q(q_wire[2]));
d_ff(.clk(~clk),.clr(clr),.d(d_wire[1]),.q(q_wire[1]));
d_ff(.clk(~clk),.clr(clr),.d(d_wire[0]),.q(q_wire[0]));
assign d_wire[3]=(lin&s1&~s0)|(q_wire[3]&~s1&~s0)|(d&s1&s0)|(q_wire[2]&~s1&s0);
assign d_wire[2]=(q_wire[3]&s1&~s0)|(q_wire[2]&~s1&~s0)|(c&s1&s0)|(q_wire[1]&~s1&s0);
assign d_wire[1]=(q_wire[2]&s1&~s0)|(q_wire[1]&~s1&~s0)|(b&s1&s0)|(q_wire[0]&~s1&s0);
assign d_wire[0]=(q_wire[1]&s1&~s0)|(q_wire[0]&~s1&~s0)|(a&s1&s0)|(rin&~s1&s0);
assign qd=q_wire[3];
assign qc=q_wire[2];
assign qb=q_wire[1];
assign qa=q_wire[0];
endmodule | module ic74x194(clk,clr,s1,s0,lin,d,c,b,a,rin,qd,qc,qb,qa); |
input clk,clr,s1,s0,lin,d,c,b,a,rin;
output qd,qc,qb,qa;
wire [3:0]d_wire,q_wire;
d_ff(.clk(~clk),.clr(clr),.d(d_wire[3]),.q(q_wire[3]));
d_ff(.clk(~clk),.clr(clr),.d(d_wire[2]),.q(q_wire[2]));
d_ff(.clk(~clk),.clr(clr),.d(d_wire[1]),.q(q_wire[1]));
d_ff(.clk(~clk),.clr(clr),.d(d_wire[0]),.q(q_wire[0]));
assign d_wire[3]=(lin&s1&~s0)|(q_wire[3]&~s1&~s0)|(d&s1&s0)|(q_wire[2]&~s1&s0);
assign d_wire[2]=(q_wire[3]&s1&~s0)|(q_wire[2]&~s1&~s0)|(c&s1&s0)|(q_wire[1]&~s1&s0);
assign d_wire[1]=(q_wire[2]&s1&~s0)|(q_wire[1]&~s1&~s0)|(b&s1&s0)|(q_wire[0]&~s1&s0);
assign d_wire[0]=(q_wire[1]&s1&~s0)|(q_wire[0]&~s1&~s0)|(a&s1&s0)|(rin&~s1&s0);
assign qd=q_wire[3];
assign qc=q_wire[2];
assign qb=q_wire[1];
assign qa=q_wire[0];
endmodule | 0 |
139,346 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/32. johnson_counters/johnson_counters.v | 87,159,735 | johnson_counters.v | v | 39 | 130 | [] | [] | [] | [(1, 12), (14, 30), (32, 38)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/32.\n%Error: Cannot find file containing module: johnson_counters,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: johnson_counters/johnson_counters.v\n%Error: Exiting due to 6 error(s)\n' | 304,631 | module | module johnson_counters(clock,reset,q0,q1,q2,q3);
input clock,reset;
output q0,q1,q2,q3;
wire q3_wire;
ic74x194(.clk(clock),.clr(reset),.s1(1),.s0(0),.lin(~q3_wire),.d(),.c(),.b(),.a(),.rin(),.qd(q0),.qc(q1),.qb(q2),.qa(q3_wire));
assign q3=q3_wire;
endmodule | module johnson_counters(clock,reset,q0,q1,q2,q3); |
input clock,reset;
output q0,q1,q2,q3;
wire q3_wire;
ic74x194(.clk(clock),.clr(reset),.s1(1),.s0(0),.lin(~q3_wire),.d(),.c(),.b(),.a(),.rin(),.qd(q0),.qc(q1),.qb(q2),.qa(q3_wire));
assign q3=q3_wire;
endmodule | 0 |
139,347 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/33. lab9/lab9.v | 87,159,735 | lab9.v | v | 43 | 61 | [] | [] | [] | [(1, 43)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/33.\n%Error: Cannot find file containing module: lab9,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: lab9/lab9.v\n%Error: Exiting due to 6 error(s)\n' | 304,632 | module | module lab9(clk,in,detect_mealy,detect_moore);
input clk,in;
output detect_mealy,detect_moore;
parameter a=0,b=1,c=2,d=3,e=4;
reg detect_moore;
reg [2:0]state;
assign detect_mealy=detect_moore∈
always@(posedge clk)
begin
if(detect_moore==1)
detect_moore<=0;
case(state)
a:
if(in==0)
state<=a;
else
state<=b;
b:
if(in==0)
state<=c;
else
state<=b;
c:
if(in==0)
state<=a;
else
state<=d;
d:
if(in==0)
state<=e;
else
state<=b;
e:
if(in==0)
state<=a;
else
begin
state<=d;
detect_moore<=1;
end
endcase
end
endmodule | module lab9(clk,in,detect_mealy,detect_moore); |
input clk,in;
output detect_mealy,detect_moore;
parameter a=0,b=1,c=2,d=3,e=4;
reg detect_moore;
reg [2:0]state;
assign detect_mealy=detect_moore∈
always@(posedge clk)
begin
if(detect_moore==1)
detect_moore<=0;
case(state)
a:
if(in==0)
state<=a;
else
state<=b;
b:
if(in==0)
state<=c;
else
state<=b;
c:
if(in==0)
state<=a;
else
state<=d;
d:
if(in==0)
state<=e;
else
state<=b;
e:
if(in==0)
state<=a;
else
begin
state<=d;
detect_moore<=1;
end
endcase
end
endmodule | 0 |
139,348 | data/full_repos/permissive/87159735/Lab.of Digital Logic Design/verilog/34. lab10/lab10.v | 87,159,735 | lab10.v | v | 16 | 26 | [] | [] | [] | [(1, 16)] | null | null | 1: b'%Error: Cannot find file containing module: Digital\n ... Looked in:\n data/full_repos/permissive/87159735/Lab.of/Digital\n data/full_repos/permissive/87159735/Lab.of/Digital.v\n data/full_repos/permissive/87159735/Lab.of/Digital.sv\n Digital\n Digital.v\n Digital.sv\n obj_dir/Digital\n obj_dir/Digital.v\n obj_dir/Digital.sv\n%Error: Cannot find file containing module: Logic\n%Error: Cannot find file containing module: Design/verilog/34.\n%Error: Cannot find file containing module: lab10,data/full_repos/permissive/87159735\n%Error: Cannot find file containing module: data/full_repos/permissive/87159735/Lab.of\n%Error: Cannot find file containing module: lab10/lab10.v\n%Error: Exiting due to 6 error(s)\n' | 304,633 | module | module lab10(clk,rst,x);
input clk,rst;
output [7:0]x;
wire serin;
reg [7:0]x;
assign serin=x[3]^x[0];
always@(posedge clk)
begin
if(x==0)
x[1]=1;
if(rst==0)
x=0;
else
x={serin,x[7:1]};
end
endmodule | module lab10(clk,rst,x); |
input clk,rst;
output [7:0]x;
wire serin;
reg [7:0]x;
assign serin=x[3]^x[0];
always@(posedge clk)
begin
if(x==0)
x[1]=1;
if(rst==0)
x=0;
else
x={serin,x[7:1]};
end
endmodule | 0 |
139,349 | data/full_repos/permissive/87161578/exp1counter/src/adder_async.v | 87,161,578 | adder_async.v | v | 38 | 67 | [] | [] | [] | [(1, 38)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/87161578/exp1counter/src/adder_async.v:2: Little bit endian vector: MSB < LSB of bit range: 0:6\noutput [0:6] leds;\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/87161578/exp1counter/src/adder_async.v:35: Cannot find file containing module: \'BCD7\'\nBCD7 bcd27seg (s,leds);\n^~~~\n ... Looked in:\n data/full_repos/permissive/87161578/exp1counter/src,data/full_repos/permissive/87161578/BCD7\n data/full_repos/permissive/87161578/exp1counter/src,data/full_repos/permissive/87161578/BCD7.v\n data/full_repos/permissive/87161578/exp1counter/src,data/full_repos/permissive/87161578/BCD7.sv\n BCD7\n BCD7.v\n BCD7.sv\n obj_dir/BCD7\n obj_dir/BCD7.v\n obj_dir/BCD7.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 304,634 | module | module top_adder_async (leds,but_input,clk,reset);
output [0:6] leds;
input but_input,clk,reset;
reg [3:0] s;
wire [0:6] leds;
initial begin
s<=4'b0000;
end
always @(posedge but_input or posedge reset)
if(reset)
s[0]<=0;
else
s[0]<=~s[0];
always @(negedge s[0] or posedge reset)
if(reset)
s[1]<=0;
else
s[1]<=~s[1];
always @(negedge s[1] or posedge reset)
if(reset)
s[2]<=0;
else
s[2]<=~s[2];
always @(negedge s[2] or posedge reset)
if(reset)
s[3]<=0;
else
s[3]<=~s[3];
BCD7 bcd27seg (s,leds);
endmodule | module top_adder_async (leds,but_input,clk,reset); |
output [0:6] leds;
input but_input,clk,reset;
reg [3:0] s;
wire [0:6] leds;
initial begin
s<=4'b0000;
end
always @(posedge but_input or posedge reset)
if(reset)
s[0]<=0;
else
s[0]<=~s[0];
always @(negedge s[0] or posedge reset)
if(reset)
s[1]<=0;
else
s[1]<=~s[1];
always @(negedge s[1] or posedge reset)
if(reset)
s[2]<=0;
else
s[2]<=~s[2];
always @(negedge s[2] or posedge reset)
if(reset)
s[3]<=0;
else
s[3]<=~s[3];
BCD7 bcd27seg (s,leds);
endmodule | 0 |
139,350 | data/full_repos/permissive/87161578/exp1counter/src/adder_async_tb.v | 87,161,578 | adder_async_tb.v | v | 20 | 47 | [] | [] | [] | [(3, 20)] | null | null | 1: b'%Error: data/full_repos/permissive/87161578/exp1counter/src/adder_async_tb.v:13: Unsupported: fork statements\ninitial fork\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp1counter/src/adder_async_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\nforever #50 but_input<=~but_input;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp1counter/src/adder_async_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\nforever #5 clk<=~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp1counter/src/adder_async_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n#910 reset<=~reset; #920 reset<=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp1counter/src/adder_async_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n#910 reset<=~reset; #920 reset<=0;\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,635 | module | module adder_async_tb;
reg clk,reset,but_input;
wire [6:0] leds;
top_adder_async tas(leds,but_input,clk,reset);
initial begin
clk<=0;
reset<=0;
but_input<=1;
end
initial fork
forever #50 but_input<=~but_input;
forever #5 clk<=~clk;
#910 reset<=~reset; #920 reset<=0;
join
endmodule | module adder_async_tb; |
reg clk,reset,but_input;
wire [6:0] leds;
top_adder_async tas(leds,but_input,clk,reset);
initial begin
clk<=0;
reset<=0;
but_input<=1;
end
initial fork
forever #50 but_input<=~but_input;
forever #5 clk<=~clk;
#910 reset<=~reset; #920 reset<=0;
join
endmodule | 0 |
139,351 | data/full_repos/permissive/87161578/exp1counter/src/adder_sync_tb.v | 87,161,578 | adder_sync_tb.v | v | 19 | 46 | [] | [] | [] | [(2, 19)] | null | null | 1: b'%Error: data/full_repos/permissive/87161578/exp1counter/src/adder_sync_tb.v:11: Unsupported: fork statements\ninitial fork\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp1counter/src/adder_sync_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\nforever #50clk_input<=~clk_input;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp1counter/src/adder_sync_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\nforever #5 clk<=~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp1counter/src/adder_sync_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n#910 reset<=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp1counter/src/adder_sync_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n#930 reset<=0;\n^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,637 | module | module adder_sync_tb;
reg clk,reset,clk_input;
top_adder_sync tas(leds,clk_input,clk,reset);
initial begin
clk<=0;
reset<=0;
clk_input<=1;
end
initial fork
forever #50clk_input<=~clk_input;
forever #5 clk<=~clk;
#910 reset<=1;
#930 reset<=0;
join
endmodule | module adder_sync_tb; |
reg clk,reset,clk_input;
top_adder_sync tas(leds,clk_input,clk,reset);
initial begin
clk<=0;
reset<=0;
clk_input<=1;
end
initial fork
forever #50clk_input<=~clk_input;
forever #5 clk<=~clk;
#910 reset<=1;
#930 reset<=0;
join
endmodule | 0 |
139,352 | data/full_repos/permissive/87161578/exp1counter/src/bcd7.v | 87,161,578 | bcd7.v | v | 23 | 41 | [] | [] | [] | [(2, 23)] | null | data/verilator_xmls/bd701575-6177-4593-af9f-c2e63f464ee1.xml | null | 304,638 | module | module BCD7(din,dout);
input [3:0] din;
output [6:0] dout;
assign dout=(din==0)?~7'b111_1110:
(din==1)?~7'b011_0000:
(din==2)?~7'b110_1101:
(din==3)?~7'b111_1001:
(din==4)?~7'b011_0011:
(din==5)?~7'b101_1011:
(din==6)?~7'b101_1111:
(din==7)?~7'b111_0000:
(din==8)?~7'b111_1111:
(din==9)?~7'b111_1011:
(din==10)?~7'b111_0111:
(din==11)?~7'b001_1111:
(din==12)?~7'b100_1110:
(din==13)?~7'b011_1101:
(din==14)?~7'b100_1111:
(din==15)?~7'b100_0111:7'b0;
endmodule | module BCD7(din,dout); |
input [3:0] din;
output [6:0] dout;
assign dout=(din==0)?~7'b111_1110:
(din==1)?~7'b011_0000:
(din==2)?~7'b110_1101:
(din==3)?~7'b111_1001:
(din==4)?~7'b011_0011:
(din==5)?~7'b101_1011:
(din==6)?~7'b101_1111:
(din==7)?~7'b111_0000:
(din==8)?~7'b111_1111:
(din==9)?~7'b111_1011:
(din==10)?~7'b111_0111:
(din==11)?~7'b001_1111:
(din==12)?~7'b100_1110:
(din==13)?~7'b011_1101:
(din==14)?~7'b100_1111:
(din==15)?~7'b100_0111:7'b0;
endmodule | 0 |
139,353 | data/full_repos/permissive/87161578/exp1counter/src/minus_sync.v | 87,161,578 | minus_sync.v | v | 27 | 66 | [] | [] | [] | [(1, 27)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/87161578/exp1counter/src/minus_sync.v:12: Signal definition not found, creating implicitly: \'but_input_dbs\'\n : ... Suggested alternative: \'but_input\'\nalways @(posedge but_input_dbs or posedge reset)\n ^~~~~~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/87161578/exp1counter/src/minus_sync.v:2: Little bit endian vector: MSB < LSB of bit range: 0:6\noutput [0:6] leds;\n ^\n%Error: data/full_repos/permissive/87161578/exp1counter/src/minus_sync.v:11: Cannot find file containing module: \'debounce\'\ndebounce xdbs(.clk(clk),.key_i(but_input),.key_o(but_input_dbs));\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87161578/exp1counter/src,data/full_repos/permissive/87161578/debounce\n data/full_repos/permissive/87161578/exp1counter/src,data/full_repos/permissive/87161578/debounce.v\n data/full_repos/permissive/87161578/exp1counter/src,data/full_repos/permissive/87161578/debounce.sv\n debounce\n debounce.v\n debounce.sv\n obj_dir/debounce\n obj_dir/debounce.v\n obj_dir/debounce.sv\n%Error: data/full_repos/permissive/87161578/exp1counter/src/minus_sync.v:24: Cannot find file containing module: \'BCD7\'\nBCD7 bcd27seg (.din(s),.dout(leds));\n^~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 304,640 | module | module top_minus_sync (leds,but_input,clk,reset);
output [0:6] leds;
input but_input,clk,reset;
reg [3:0] s;
wire [0:6] leds;
initial begin
s<=4'b0000;
end
debounce xdbs(.clk(clk),.key_i(but_input),.key_o(but_input_dbs));
always @(posedge but_input_dbs or posedge reset)
begin
if (reset)
s<=4'b0000;
else
s[3:0]<=s[3:0]-1;
end
BCD7 bcd27seg (.din(s),.dout(leds));
endmodule | module top_minus_sync (leds,but_input,clk,reset); |
output [0:6] leds;
input but_input,clk,reset;
reg [3:0] s;
wire [0:6] leds;
initial begin
s<=4'b0000;
end
debounce xdbs(.clk(clk),.key_i(but_input),.key_o(but_input_dbs));
always @(posedge but_input_dbs or posedge reset)
begin
if (reset)
s<=4'b0000;
else
s[3:0]<=s[3:0]-1;
end
BCD7 bcd27seg (.din(s),.dout(leds));
endmodule | 0 |
139,354 | data/full_repos/permissive/87161578/exp2fsm/fsm/fsm.v | 87,161,578 | fsm.v | v | 45 | 62 | [] | [] | [] | [(1, 45)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/87161578/exp2fsm/fsm/fsm.v:10: Signal definition not found, creating implicitly: \'clk\'\n : ... Suggested alternative: \'clk_i\'\nalways @(posedge clk or posedge reset)\n ^~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/87161578/exp2fsm/fsm/fsm.v:10: Signal definition not found, creating implicitly: \'reset\'\n : ... Suggested alternative: \'reset_i\'\nalways @(posedge clk or posedge reset)\n ^~~~~\n%Error: data/full_repos/permissive/87161578/exp2fsm/fsm/fsm.v:5: Cannot find file containing module: \'debounce\'\ndebounce xdb(.clk(system_clk),.key_i(reset_i),.key_o(reset));\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87161578/exp2fsm/fsm,data/full_repos/permissive/87161578/debounce\n data/full_repos/permissive/87161578/exp2fsm/fsm,data/full_repos/permissive/87161578/debounce.v\n data/full_repos/permissive/87161578/exp2fsm/fsm,data/full_repos/permissive/87161578/debounce.sv\n debounce\n debounce.v\n debounce.sv\n obj_dir/debounce\n obj_dir/debounce.v\n obj_dir/debounce.sv\n%Error: data/full_repos/permissive/87161578/exp2fsm/fsm/fsm.v:6: Cannot find file containing module: \'debounce\'\ndebounce xdb2(.clk(system_clk),.key_i(clk_i),.key_o(clk));\n^~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 304,642 | module | module fsm(found,s,clk_i,din,reset_i,system_clk);
input din,clk_i,reset_i,system_clk;
output reg [2:0] s;
output found;
debounce xdb(.clk(system_clk),.key_i(reset_i),.key_o(reset));
debounce xdb2(.clk(system_clk),.key_i(clk_i),.key_o(clk));
initial begin
s<=3'b000;
end
always @(posedge clk or posedge reset)
begin
if (reset)
begin
s<=3'b000;
end
else if(din)
begin
case(s)
3'b000:s<=3'b001;
3'b001:s<=3'b001;
3'b010:s<=3'b011;
3'b011:s<=3'b001;
3'b100:s<=3'b101;
3'b101:s<=3'b110;
3'b110:s<=3'b001;
3'b111:s<=3'b000;
endcase
end
else
begin
case(s)
3'b000:s<=3'b000;
3'b001:s<=3'b010;
3'b010:s<=3'b000;
3'b011:s<=3'b100;
3'b100:s<=3'b000;
3'b101:s<=3'b100;
3'b110:s<=3'b010;
3'b111:s<=3'b000;
endcase
end
end
assign found=(s==3'b110)?1:0;
endmodule | module fsm(found,s,clk_i,din,reset_i,system_clk); |
input din,clk_i,reset_i,system_clk;
output reg [2:0] s;
output found;
debounce xdb(.clk(system_clk),.key_i(reset_i),.key_o(reset));
debounce xdb2(.clk(system_clk),.key_i(clk_i),.key_o(clk));
initial begin
s<=3'b000;
end
always @(posedge clk or posedge reset)
begin
if (reset)
begin
s<=3'b000;
end
else if(din)
begin
case(s)
3'b000:s<=3'b001;
3'b001:s<=3'b001;
3'b010:s<=3'b011;
3'b011:s<=3'b001;
3'b100:s<=3'b101;
3'b101:s<=3'b110;
3'b110:s<=3'b001;
3'b111:s<=3'b000;
endcase
end
else
begin
case(s)
3'b000:s<=3'b000;
3'b001:s<=3'b010;
3'b010:s<=3'b000;
3'b011:s<=3'b100;
3'b100:s<=3'b000;
3'b101:s<=3'b100;
3'b110:s<=3'b010;
3'b111:s<=3'b000;
endcase
end
end
assign found=(s==3'b110)?1:0;
endmodule | 0 |
139,355 | data/full_repos/permissive/87161578/exp2fsm/shift/top_shift.v | 87,161,578 | top_shift.v | v | 27 | 63 | [] | [] | [] | [(1, 26)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/87161578/exp2fsm/shift/top_shift.v:10: Signal definition not found, creating implicitly: \'clk\'\n : ... Suggested alternative: \'clk_i\'\nalways @(posedge clk or posedge reset)\n ^~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/87161578/exp2fsm/shift/top_shift.v:10: Signal definition not found, creating implicitly: \'reset\'\n : ... Suggested alternative: \'reset_i\'\nalways @(posedge clk or posedge reset)\n ^~~~~\n%Error: data/full_repos/permissive/87161578/exp2fsm/shift/top_shift.v:5: Cannot find file containing module: \'debounce\'\ndebounce xdb(.clk(system_clk),.key_i(clk_i),.key_o(clk));\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87161578/exp2fsm/shift,data/full_repos/permissive/87161578/debounce\n data/full_repos/permissive/87161578/exp2fsm/shift,data/full_repos/permissive/87161578/debounce.v\n data/full_repos/permissive/87161578/exp2fsm/shift,data/full_repos/permissive/87161578/debounce.sv\n debounce\n debounce.v\n debounce.sv\n obj_dir/debounce\n obj_dir/debounce.v\n obj_dir/debounce.sv\n%Error: data/full_repos/permissive/87161578/exp2fsm/shift/top_shift.v:6: Cannot find file containing module: \'debounce\'\ndebounce xdb2(.clk(system_clk),.key_i(reset_i),.key_o(reset));\n^~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n' | 304,643 | module | module top_shift(found,s,clk_i,reset_i,din,system_clk);
output found;
output reg [5:0] s;
input clk_i,reset_i,din,system_clk;
debounce xdb(.clk(system_clk),.key_i(clk_i),.key_o(clk));
debounce xdb2(.clk(system_clk),.key_i(reset_i),.key_o(reset));
initial begin
s<=6'b000000;
end
always @(posedge clk or posedge reset)
begin
if (reset)
s<=6'b000000;
else
begin
s[5]<=s[4];
s[4]<=s[3];
s[3]<=s[2];
s[2]<=s[1];
s[1]<=s[0];
s[0]<=din;
end
end
assign found=(s==6'b101011)?1:0;
endmodule | module top_shift(found,s,clk_i,reset_i,din,system_clk); |
output found;
output reg [5:0] s;
input clk_i,reset_i,din,system_clk;
debounce xdb(.clk(system_clk),.key_i(clk_i),.key_o(clk));
debounce xdb2(.clk(system_clk),.key_i(reset_i),.key_o(reset));
initial begin
s<=6'b000000;
end
always @(posedge clk or posedge reset)
begin
if (reset)
s<=6'b000000;
else
begin
s[5]<=s[4];
s[4]<=s[3];
s[3]<=s[2];
s[2]<=s[1];
s[1]<=s[0];
s[0]<=din;
end
end
assign found=(s==6'b101011)?1:0;
endmodule | 0 |
139,356 | data/full_repos/permissive/87161578/exp3freq/src/control_signal.v | 87,161,578 | control_signal.v | v | 201 | 68 | [] | [] | [] | null | line:7: before: "=" | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:21: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hertz_clk_generation\'\nmodule hertz_clk_generation(hz_clk,system_clk);\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'thousand_hertz_clk_generation\'\nmodule thousand_hertz_clk_generation(hz_clk,system_clk);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'range_switch\'\nmodule range_switch(otput,iput,modecontrol);\n ^~~~~~~~~~~~\n : ... Top module \'control_signal\'\nmodule control_signal(save,enable,reset,hz_clk);\n ^~~~~~~~~~~~~~\n : ... Top module \'decimal_counter\'\nmodule decimal_counter(s3,s2,s1,s0,iput,enable,reset);\n ^~~~~~~~~~~~~~~\n : ... Top module \'saver\'\nmodule saver(saved_s3,saved_s2,saved_s1,saved_s0,save,s3,s2,s1,s0);\n ^~~~~\n : ... Top module \'show\'\nmodule show(dout,an3,an2,an1,an0,th_hz_clk,s3,s2,s1,s0);\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:62: Signal definition not found, creating implicitly: \'ten_otput\'\nten_frequency_divider tn_freq_div(.otput(ten_otput),.iput(iput));\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\ns<=4\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:54: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\ns<=4\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:52: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h4\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\nif (s==4\'d4)\n ^~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:155: Cannot find file containing module: \'BCD7\'\nBCD7 bcd1(.din(s0),.dout(d0));\n^~~~\n ... Looked in:\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7.v\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7.sv\n BCD7\n BCD7.v\n BCD7.sv\n obj_dir/BCD7\n obj_dir/BCD7.v\n obj_dir/BCD7.sv\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:156: Cannot find file containing module: \'BCD7\'\nBCD7 bcd2(.din(s1),.dout(d1));\n^~~~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:157: Cannot find file containing module: \'BCD7\'\nBCD7 bcd3(.din(s2),.dout(d2));\n^~~~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:158: Cannot find file containing module: \'BCD7\'\nBCD7 bcd4(.din(s3),.dout(d3));\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:105: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns3[3:0]<=(s/1000)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:106: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns2[3:0]<=(s/100)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:107: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns1[3:0]<=(s/10)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:108: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns0[3:0]<=s%10;\n ^~\n%Error: Exiting due to 4 error(s), 9 warning(s)\n' | 304,645 | module | module hertz_clk_generation(hz_clk,system_clk);
input system_clk;
output reg hz_clk;
reg [25:0] s;
initial begin
s<=1;
hz_clk<=0;
end
always @(posedge system_clk)
begin
s<=s+1;
if(s==26'd50000000)
begin
hz_clk<=~hz_clk;
s<=1;
end
end
endmodule | module hertz_clk_generation(hz_clk,system_clk); |
input system_clk;
output reg hz_clk;
reg [25:0] s;
initial begin
s<=1;
hz_clk<=0;
end
always @(posedge system_clk)
begin
s<=s+1;
if(s==26'd50000000)
begin
hz_clk<=~hz_clk;
s<=1;
end
end
endmodule | 0 |
139,357 | data/full_repos/permissive/87161578/exp3freq/src/control_signal.v | 87,161,578 | control_signal.v | v | 201 | 68 | [] | [] | [] | null | line:7: before: "=" | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:21: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hertz_clk_generation\'\nmodule hertz_clk_generation(hz_clk,system_clk);\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'thousand_hertz_clk_generation\'\nmodule thousand_hertz_clk_generation(hz_clk,system_clk);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'range_switch\'\nmodule range_switch(otput,iput,modecontrol);\n ^~~~~~~~~~~~\n : ... Top module \'control_signal\'\nmodule control_signal(save,enable,reset,hz_clk);\n ^~~~~~~~~~~~~~\n : ... Top module \'decimal_counter\'\nmodule decimal_counter(s3,s2,s1,s0,iput,enable,reset);\n ^~~~~~~~~~~~~~~\n : ... Top module \'saver\'\nmodule saver(saved_s3,saved_s2,saved_s1,saved_s0,save,s3,s2,s1,s0);\n ^~~~~\n : ... Top module \'show\'\nmodule show(dout,an3,an2,an1,an0,th_hz_clk,s3,s2,s1,s0);\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:62: Signal definition not found, creating implicitly: \'ten_otput\'\nten_frequency_divider tn_freq_div(.otput(ten_otput),.iput(iput));\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\ns<=4\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:54: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\ns<=4\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:52: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h4\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\nif (s==4\'d4)\n ^~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:155: Cannot find file containing module: \'BCD7\'\nBCD7 bcd1(.din(s0),.dout(d0));\n^~~~\n ... Looked in:\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7.v\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7.sv\n BCD7\n BCD7.v\n BCD7.sv\n obj_dir/BCD7\n obj_dir/BCD7.v\n obj_dir/BCD7.sv\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:156: Cannot find file containing module: \'BCD7\'\nBCD7 bcd2(.din(s1),.dout(d1));\n^~~~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:157: Cannot find file containing module: \'BCD7\'\nBCD7 bcd3(.din(s2),.dout(d2));\n^~~~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:158: Cannot find file containing module: \'BCD7\'\nBCD7 bcd4(.din(s3),.dout(d3));\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:105: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns3[3:0]<=(s/1000)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:106: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns2[3:0]<=(s/100)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:107: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns1[3:0]<=(s/10)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:108: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns0[3:0]<=s%10;\n ^~\n%Error: Exiting due to 4 error(s), 9 warning(s)\n' | 304,645 | module | module thousand_hertz_clk_generation(hz_clk,system_clk);
input system_clk;
output reg hz_clk;
reg [15:0] s;
initial begin
s<=1;
hz_clk<=0;
end
always @(posedge system_clk)
begin
s<=s+1;
if(s==16'd50000)
begin
hz_clk<=~hz_clk;
s<=1;
end
end
endmodule | module thousand_hertz_clk_generation(hz_clk,system_clk); |
input system_clk;
output reg hz_clk;
reg [15:0] s;
initial begin
s<=1;
hz_clk<=0;
end
always @(posedge system_clk)
begin
s<=s+1;
if(s==16'd50000)
begin
hz_clk<=~hz_clk;
s<=1;
end
end
endmodule | 0 |
139,358 | data/full_repos/permissive/87161578/exp3freq/src/control_signal.v | 87,161,578 | control_signal.v | v | 201 | 68 | [] | [] | [] | null | line:7: before: "=" | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:21: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hertz_clk_generation\'\nmodule hertz_clk_generation(hz_clk,system_clk);\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'thousand_hertz_clk_generation\'\nmodule thousand_hertz_clk_generation(hz_clk,system_clk);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'range_switch\'\nmodule range_switch(otput,iput,modecontrol);\n ^~~~~~~~~~~~\n : ... Top module \'control_signal\'\nmodule control_signal(save,enable,reset,hz_clk);\n ^~~~~~~~~~~~~~\n : ... Top module \'decimal_counter\'\nmodule decimal_counter(s3,s2,s1,s0,iput,enable,reset);\n ^~~~~~~~~~~~~~~\n : ... Top module \'saver\'\nmodule saver(saved_s3,saved_s2,saved_s1,saved_s0,save,s3,s2,s1,s0);\n ^~~~~\n : ... Top module \'show\'\nmodule show(dout,an3,an2,an1,an0,th_hz_clk,s3,s2,s1,s0);\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:62: Signal definition not found, creating implicitly: \'ten_otput\'\nten_frequency_divider tn_freq_div(.otput(ten_otput),.iput(iput));\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\ns<=4\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:54: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\ns<=4\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:52: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h4\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\nif (s==4\'d4)\n ^~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:155: Cannot find file containing module: \'BCD7\'\nBCD7 bcd1(.din(s0),.dout(d0));\n^~~~\n ... Looked in:\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7.v\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7.sv\n BCD7\n BCD7.v\n BCD7.sv\n obj_dir/BCD7\n obj_dir/BCD7.v\n obj_dir/BCD7.sv\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:156: Cannot find file containing module: \'BCD7\'\nBCD7 bcd2(.din(s1),.dout(d1));\n^~~~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:157: Cannot find file containing module: \'BCD7\'\nBCD7 bcd3(.din(s2),.dout(d2));\n^~~~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:158: Cannot find file containing module: \'BCD7\'\nBCD7 bcd4(.din(s3),.dout(d3));\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:105: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns3[3:0]<=(s/1000)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:106: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns2[3:0]<=(s/100)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:107: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns1[3:0]<=(s/10)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:108: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns0[3:0]<=s%10;\n ^~\n%Error: Exiting due to 4 error(s), 9 warning(s)\n' | 304,645 | module | module ten_frequency_divider(otput,iput);
output reg otput;
input iput;
reg [4:0] s;
initial begin
s<=4'd0;
otput<=0;
end
always @(posedge iput)
begin
s<=s+1;
if (s==4'd4)
begin
s<=4'd0;
otput<=~otput;
end
end
endmodule | module ten_frequency_divider(otput,iput); |
output reg otput;
input iput;
reg [4:0] s;
initial begin
s<=4'd0;
otput<=0;
end
always @(posedge iput)
begin
s<=s+1;
if (s==4'd4)
begin
s<=4'd0;
otput<=~otput;
end
end
endmodule | 0 |
139,359 | data/full_repos/permissive/87161578/exp3freq/src/control_signal.v | 87,161,578 | control_signal.v | v | 201 | 68 | [] | [] | [] | null | line:7: before: "=" | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:21: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hertz_clk_generation\'\nmodule hertz_clk_generation(hz_clk,system_clk);\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'thousand_hertz_clk_generation\'\nmodule thousand_hertz_clk_generation(hz_clk,system_clk);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'range_switch\'\nmodule range_switch(otput,iput,modecontrol);\n ^~~~~~~~~~~~\n : ... Top module \'control_signal\'\nmodule control_signal(save,enable,reset,hz_clk);\n ^~~~~~~~~~~~~~\n : ... Top module \'decimal_counter\'\nmodule decimal_counter(s3,s2,s1,s0,iput,enable,reset);\n ^~~~~~~~~~~~~~~\n : ... Top module \'saver\'\nmodule saver(saved_s3,saved_s2,saved_s1,saved_s0,save,s3,s2,s1,s0);\n ^~~~~\n : ... Top module \'show\'\nmodule show(dout,an3,an2,an1,an0,th_hz_clk,s3,s2,s1,s0);\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:62: Signal definition not found, creating implicitly: \'ten_otput\'\nten_frequency_divider tn_freq_div(.otput(ten_otput),.iput(iput));\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\ns<=4\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:54: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\ns<=4\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:52: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h4\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\nif (s==4\'d4)\n ^~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:155: Cannot find file containing module: \'BCD7\'\nBCD7 bcd1(.din(s0),.dout(d0));\n^~~~\n ... Looked in:\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7.v\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7.sv\n BCD7\n BCD7.v\n BCD7.sv\n obj_dir/BCD7\n obj_dir/BCD7.v\n obj_dir/BCD7.sv\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:156: Cannot find file containing module: \'BCD7\'\nBCD7 bcd2(.din(s1),.dout(d1));\n^~~~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:157: Cannot find file containing module: \'BCD7\'\nBCD7 bcd3(.din(s2),.dout(d2));\n^~~~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:158: Cannot find file containing module: \'BCD7\'\nBCD7 bcd4(.din(s3),.dout(d3));\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:105: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns3[3:0]<=(s/1000)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:106: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns2[3:0]<=(s/100)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:107: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns1[3:0]<=(s/10)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:108: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns0[3:0]<=s%10;\n ^~\n%Error: Exiting due to 4 error(s), 9 warning(s)\n' | 304,645 | module | module range_switch(otput,iput,modecontrol);
ten_frequency_divider tn_freq_div(.otput(ten_otput),.iput(iput));
output reg otput;
input iput,modecontrol;
always @*
begin
if (modecontrol)
otput<=ten_otput;
else
otput<=iput;
end
endmodule | module range_switch(otput,iput,modecontrol); |
ten_frequency_divider tn_freq_div(.otput(ten_otput),.iput(iput));
output reg otput;
input iput,modecontrol;
always @*
begin
if (modecontrol)
otput<=ten_otput;
else
otput<=iput;
end
endmodule | 0 |
139,360 | data/full_repos/permissive/87161578/exp3freq/src/control_signal.v | 87,161,578 | control_signal.v | v | 201 | 68 | [] | [] | [] | null | line:7: before: "=" | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:21: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hertz_clk_generation\'\nmodule hertz_clk_generation(hz_clk,system_clk);\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'thousand_hertz_clk_generation\'\nmodule thousand_hertz_clk_generation(hz_clk,system_clk);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'range_switch\'\nmodule range_switch(otput,iput,modecontrol);\n ^~~~~~~~~~~~\n : ... Top module \'control_signal\'\nmodule control_signal(save,enable,reset,hz_clk);\n ^~~~~~~~~~~~~~\n : ... Top module \'decimal_counter\'\nmodule decimal_counter(s3,s2,s1,s0,iput,enable,reset);\n ^~~~~~~~~~~~~~~\n : ... Top module \'saver\'\nmodule saver(saved_s3,saved_s2,saved_s1,saved_s0,save,s3,s2,s1,s0);\n ^~~~~\n : ... Top module \'show\'\nmodule show(dout,an3,an2,an1,an0,th_hz_clk,s3,s2,s1,s0);\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:62: Signal definition not found, creating implicitly: \'ten_otput\'\nten_frequency_divider tn_freq_div(.otput(ten_otput),.iput(iput));\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\ns<=4\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:54: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\ns<=4\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:52: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h4\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\nif (s==4\'d4)\n ^~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:155: Cannot find file containing module: \'BCD7\'\nBCD7 bcd1(.din(s0),.dout(d0));\n^~~~\n ... Looked in:\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7.v\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7.sv\n BCD7\n BCD7.v\n BCD7.sv\n obj_dir/BCD7\n obj_dir/BCD7.v\n obj_dir/BCD7.sv\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:156: Cannot find file containing module: \'BCD7\'\nBCD7 bcd2(.din(s1),.dout(d1));\n^~~~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:157: Cannot find file containing module: \'BCD7\'\nBCD7 bcd3(.din(s2),.dout(d2));\n^~~~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:158: Cannot find file containing module: \'BCD7\'\nBCD7 bcd4(.din(s3),.dout(d3));\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:105: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns3[3:0]<=(s/1000)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:106: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns2[3:0]<=(s/100)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:107: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns1[3:0]<=(s/10)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:108: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns0[3:0]<=s%10;\n ^~\n%Error: Exiting due to 4 error(s), 9 warning(s)\n' | 304,645 | module | module control_signal(save,enable,reset,hz_clk);
input hz_clk;
output reg save,enable,reset;
initial begin
save<=0;
enable<=1;
reset<=0;
end
always @(posedge hz_clk)
begin
save<=~save;
enable<=~enable;
reset<=~reset;
end
endmodule | module control_signal(save,enable,reset,hz_clk); |
input hz_clk;
output reg save,enable,reset;
initial begin
save<=0;
enable<=1;
reset<=0;
end
always @(posedge hz_clk)
begin
save<=~save;
enable<=~enable;
reset<=~reset;
end
endmodule | 0 |
139,361 | data/full_repos/permissive/87161578/exp3freq/src/control_signal.v | 87,161,578 | control_signal.v | v | 201 | 68 | [] | [] | [] | null | line:7: before: "=" | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:21: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hertz_clk_generation\'\nmodule hertz_clk_generation(hz_clk,system_clk);\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'thousand_hertz_clk_generation\'\nmodule thousand_hertz_clk_generation(hz_clk,system_clk);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'range_switch\'\nmodule range_switch(otput,iput,modecontrol);\n ^~~~~~~~~~~~\n : ... Top module \'control_signal\'\nmodule control_signal(save,enable,reset,hz_clk);\n ^~~~~~~~~~~~~~\n : ... Top module \'decimal_counter\'\nmodule decimal_counter(s3,s2,s1,s0,iput,enable,reset);\n ^~~~~~~~~~~~~~~\n : ... Top module \'saver\'\nmodule saver(saved_s3,saved_s2,saved_s1,saved_s0,save,s3,s2,s1,s0);\n ^~~~~\n : ... Top module \'show\'\nmodule show(dout,an3,an2,an1,an0,th_hz_clk,s3,s2,s1,s0);\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:62: Signal definition not found, creating implicitly: \'ten_otput\'\nten_frequency_divider tn_freq_div(.otput(ten_otput),.iput(iput));\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\ns<=4\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:54: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\ns<=4\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:52: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h4\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\nif (s==4\'d4)\n ^~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:155: Cannot find file containing module: \'BCD7\'\nBCD7 bcd1(.din(s0),.dout(d0));\n^~~~\n ... Looked in:\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7.v\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7.sv\n BCD7\n BCD7.v\n BCD7.sv\n obj_dir/BCD7\n obj_dir/BCD7.v\n obj_dir/BCD7.sv\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:156: Cannot find file containing module: \'BCD7\'\nBCD7 bcd2(.din(s1),.dout(d1));\n^~~~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:157: Cannot find file containing module: \'BCD7\'\nBCD7 bcd3(.din(s2),.dout(d2));\n^~~~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:158: Cannot find file containing module: \'BCD7\'\nBCD7 bcd4(.din(s3),.dout(d3));\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:105: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns3[3:0]<=(s/1000)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:106: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns2[3:0]<=(s/100)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:107: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns1[3:0]<=(s/10)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:108: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns0[3:0]<=s%10;\n ^~\n%Error: Exiting due to 4 error(s), 9 warning(s)\n' | 304,645 | module | module decimal_counter(s3,s2,s1,s0,iput,enable,reset);
output reg [3:0] s3;
output reg [3:0] s2;
output reg [3:0] s1;
output reg [3:0] s0;
reg [15:0] s;
input iput,enable,reset;
initial begin
s<=0;
end
always @*
begin
s3[3:0]<=(s/1000)%10;
s2[3:0]<=(s/100)%10;
s1[3:0]<=(s/10)%10;
s0[3:0]<=s%10;
end
always @(posedge iput or posedge reset)
begin
if (reset)
s<=0;
else if(enable)
s<=s+1;
end
endmodule | module decimal_counter(s3,s2,s1,s0,iput,enable,reset); |
output reg [3:0] s3;
output reg [3:0] s2;
output reg [3:0] s1;
output reg [3:0] s0;
reg [15:0] s;
input iput,enable,reset;
initial begin
s<=0;
end
always @*
begin
s3[3:0]<=(s/1000)%10;
s2[3:0]<=(s/100)%10;
s1[3:0]<=(s/10)%10;
s0[3:0]<=s%10;
end
always @(posedge iput or posedge reset)
begin
if (reset)
s<=0;
else if(enable)
s<=s+1;
end
endmodule | 0 |
139,362 | data/full_repos/permissive/87161578/exp3freq/src/control_signal.v | 87,161,578 | control_signal.v | v | 201 | 68 | [] | [] | [] | null | line:7: before: "=" | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:21: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hertz_clk_generation\'\nmodule hertz_clk_generation(hz_clk,system_clk);\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'thousand_hertz_clk_generation\'\nmodule thousand_hertz_clk_generation(hz_clk,system_clk);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'range_switch\'\nmodule range_switch(otput,iput,modecontrol);\n ^~~~~~~~~~~~\n : ... Top module \'control_signal\'\nmodule control_signal(save,enable,reset,hz_clk);\n ^~~~~~~~~~~~~~\n : ... Top module \'decimal_counter\'\nmodule decimal_counter(s3,s2,s1,s0,iput,enable,reset);\n ^~~~~~~~~~~~~~~\n : ... Top module \'saver\'\nmodule saver(saved_s3,saved_s2,saved_s1,saved_s0,save,s3,s2,s1,s0);\n ^~~~~\n : ... Top module \'show\'\nmodule show(dout,an3,an2,an1,an0,th_hz_clk,s3,s2,s1,s0);\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:62: Signal definition not found, creating implicitly: \'ten_otput\'\nten_frequency_divider tn_freq_div(.otput(ten_otput),.iput(iput));\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\ns<=4\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:54: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\ns<=4\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:52: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h4\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\nif (s==4\'d4)\n ^~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:155: Cannot find file containing module: \'BCD7\'\nBCD7 bcd1(.din(s0),.dout(d0));\n^~~~\n ... Looked in:\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7.v\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7.sv\n BCD7\n BCD7.v\n BCD7.sv\n obj_dir/BCD7\n obj_dir/BCD7.v\n obj_dir/BCD7.sv\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:156: Cannot find file containing module: \'BCD7\'\nBCD7 bcd2(.din(s1),.dout(d1));\n^~~~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:157: Cannot find file containing module: \'BCD7\'\nBCD7 bcd3(.din(s2),.dout(d2));\n^~~~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:158: Cannot find file containing module: \'BCD7\'\nBCD7 bcd4(.din(s3),.dout(d3));\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:105: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns3[3:0]<=(s/1000)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:106: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns2[3:0]<=(s/100)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:107: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns1[3:0]<=(s/10)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:108: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns0[3:0]<=s%10;\n ^~\n%Error: Exiting due to 4 error(s), 9 warning(s)\n' | 304,645 | module | module saver(saved_s3,saved_s2,saved_s1,saved_s0,save,s3,s2,s1,s0);
input save;
input [3:0] s3;
input [3:0] s2;
input [3:0] s1;
input [3:0] s0;
output reg [3:0] saved_s3;
output reg [3:0] saved_s2;
output reg [3:0] saved_s1;
output reg [3:0] saved_s0;
always @*
begin
if(~save)
begin
saved_s3<=s3;
saved_s2<=s2;
saved_s1<=s1;
saved_s0<=s0;
end
end
endmodule | module saver(saved_s3,saved_s2,saved_s1,saved_s0,save,s3,s2,s1,s0); |
input save;
input [3:0] s3;
input [3:0] s2;
input [3:0] s1;
input [3:0] s0;
output reg [3:0] saved_s3;
output reg [3:0] saved_s2;
output reg [3:0] saved_s1;
output reg [3:0] saved_s0;
always @*
begin
if(~save)
begin
saved_s3<=s3;
saved_s2<=s2;
saved_s1<=s1;
saved_s0<=s0;
end
end
endmodule | 0 |
139,363 | data/full_repos/permissive/87161578/exp3freq/src/control_signal.v | 87,161,578 | control_signal.v | v | 201 | 68 | [] | [] | [] | null | line:7: before: "=" | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:21: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hertz_clk_generation\'\nmodule hertz_clk_generation(hz_clk,system_clk);\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'thousand_hertz_clk_generation\'\nmodule thousand_hertz_clk_generation(hz_clk,system_clk);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'range_switch\'\nmodule range_switch(otput,iput,modecontrol);\n ^~~~~~~~~~~~\n : ... Top module \'control_signal\'\nmodule control_signal(save,enable,reset,hz_clk);\n ^~~~~~~~~~~~~~\n : ... Top module \'decimal_counter\'\nmodule decimal_counter(s3,s2,s1,s0,iput,enable,reset);\n ^~~~~~~~~~~~~~~\n : ... Top module \'saver\'\nmodule saver(saved_s3,saved_s2,saved_s1,saved_s0,save,s3,s2,s1,s0);\n ^~~~~\n : ... Top module \'show\'\nmodule show(dout,an3,an2,an1,an0,th_hz_clk,s3,s2,s1,s0);\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:62: Signal definition not found, creating implicitly: \'ten_otput\'\nten_frequency_divider tn_freq_div(.otput(ten_otput),.iput(iput));\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\ns<=4\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:54: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\ns<=4\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:52: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h4\' generates 4 bits.\n : ... In instance range_switch.tn_freq_div\nif (s==4\'d4)\n ^~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:155: Cannot find file containing module: \'BCD7\'\nBCD7 bcd1(.din(s0),.dout(d0));\n^~~~\n ... Looked in:\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7.v\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/BCD7.sv\n BCD7\n BCD7.v\n BCD7.sv\n obj_dir/BCD7\n obj_dir/BCD7.v\n obj_dir/BCD7.sv\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:156: Cannot find file containing module: \'BCD7\'\nBCD7 bcd2(.din(s1),.dout(d1));\n^~~~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:157: Cannot find file containing module: \'BCD7\'\nBCD7 bcd3(.din(s2),.dout(d2));\n^~~~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:158: Cannot find file containing module: \'BCD7\'\nBCD7 bcd4(.din(s3),.dout(d3));\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:105: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns3[3:0]<=(s/1000)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:106: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns2[3:0]<=(s/100)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:107: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns1[3:0]<=(s/10)%10;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/control_signal.v:108: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 16 bits.\n : ... In instance decimal_counter\ns0[3:0]<=s%10;\n ^~\n%Error: Exiting due to 4 error(s), 9 warning(s)\n' | 304,645 | module | module show(dout,an3,an2,an1,an0,th_hz_clk,s3,s2,s1,s0);
input [3:0] s3;
input [3:0] s2;
input [3:0] s1;
input [3:0] s0;
input th_hz_clk;
output reg [7:0] dout;
output reg an3,an2,an1,an0;
wire [6:0] d0;
wire [6:0] d1;
wire [6:0] d2;
wire [6:0] d3;
BCD7 bcd1(.din(s0),.dout(d0));
BCD7 bcd2(.din(s1),.dout(d1));
BCD7 bcd3(.din(s2),.dout(d2));
BCD7 bcd4(.din(s3),.dout(d3));
reg [1:0] choice;
initial begin
choice<=0;
dout[7]<=1;
end
always@ (posedge th_hz_clk)
begin
choice<=choice+1;
if(choice==0)
begin
an0<=0;
an1<=1;
an2<=1;
an3<=1;
dout[6:0]<=d0;
end
else if (choice==1)
begin
an0<=1;
an1<=0;
an2<=1;
an3<=1;
dout[6:0]<=d1;
end
else if (choice==2)
begin
an0<=1;
an1<=1;
an2<=0;
an3<=1;
dout[6:0]<=d2;
end
else if (choice==3)
begin
an0<=1;
an1<=1;
an2<=1;
an3<=0;
dout[6:0]<=d3;
end
end
endmodule | module show(dout,an3,an2,an1,an0,th_hz_clk,s3,s2,s1,s0); |
input [3:0] s3;
input [3:0] s2;
input [3:0] s1;
input [3:0] s0;
input th_hz_clk;
output reg [7:0] dout;
output reg an3,an2,an1,an0;
wire [6:0] d0;
wire [6:0] d1;
wire [6:0] d2;
wire [6:0] d3;
BCD7 bcd1(.din(s0),.dout(d0));
BCD7 bcd2(.din(s1),.dout(d1));
BCD7 bcd3(.din(s2),.dout(d2));
BCD7 bcd4(.din(s3),.dout(d3));
reg [1:0] choice;
initial begin
choice<=0;
dout[7]<=1;
end
always@ (posedge th_hz_clk)
begin
choice<=choice+1;
if(choice==0)
begin
an0<=0;
an1<=1;
an2<=1;
an3<=1;
dout[6:0]<=d0;
end
else if (choice==1)
begin
an0<=1;
an1<=0;
an2<=1;
an3<=1;
dout[6:0]<=d1;
end
else if (choice==2)
begin
an0<=1;
an1<=1;
an2<=0;
an3<=1;
dout[6:0]<=d2;
end
else if (choice==3)
begin
an0<=1;
an1<=1;
an2<=1;
an3<=0;
dout[6:0]<=d3;
end
end
endmodule | 0 |
139,364 | data/full_repos/permissive/87161578/exp3freq/src/frequency.v | 87,161,578 | frequency.v | v | 29 | 152 | [] | [] | [] | [(1, 29)] | null | null | 1: b"%Error: data/full_repos/permissive/87161578/exp3freq/src/frequency.v:19: Cannot find file containing module: 'hertz_clk_generation'\nhertz_clk_generation hz_clk_gn(.hz_clk(hz_clk),.system_clk(sysclk));\n^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/hertz_clk_generation\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/hertz_clk_generation.v\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/hertz_clk_generation.sv\n hertz_clk_generation\n hertz_clk_generation.v\n hertz_clk_generation.sv\n obj_dir/hertz_clk_generation\n obj_dir/hertz_clk_generation.v\n obj_dir/hertz_clk_generation.sv\n%Error: data/full_repos/permissive/87161578/exp3freq/src/frequency.v:20: Cannot find file containing module: 'thousand_hertz_clk_generation'\nthousand_hertz_clk_generation th_hz_clk_gn(.hz_clk(th_hz_clk),.system_clk(sysclk));\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/frequency.v:21: Cannot find file containing module: 'range_switch'\nrange_switch rg_sw(.otput(otput),.iput(sigin),.modecontrol(modecontrol));\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/frequency.v:22: Cannot find file containing module: 'control_signal'\ncontrol_signal ct_sg(.save(save),.enable(enable),.reset(reset),.hz_clk(hz_clk));\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/frequency.v:23: Cannot find file containing module: 'decimal_counter'\ndecimal_counter dcm_ct(.s3(s3),.s2(s2),.s1(s1),.s0(s0),.iput(otput),.enable(enable),.reset(reset));\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/frequency.v:24: Cannot find file containing module: 'saver'\nsaver svr(.saved_s3(saved_s3),.saved_s2(saved_s2),.saved_s1(saved_s1),.saved_s0(saved_s0),.save(save),.s3(s3),.s2(s2),.s1(s1),.s0(s0));\n^~~~~\n%Error: data/full_repos/permissive/87161578/exp3freq/src/frequency.v:25: Cannot find file containing module: 'show'\nshow sh(.dout(cathodes),.an3(AN[3]),.an2(AN[2]),.an1(AN[1]),.an0(AN[0]),.th_hz_clk(th_hz_clk),.s3(saved_s3),.s2(saved_s2),.s1(saved_s1),.s0(saved_s0));\n^~~~\n%Error: Exiting due to 7 error(s)\n" | 304,646 | module | module frequency (sigin,sysclk,modecontrol,highfreq,cathodes,AN);
input sigin,sysclk,modecontrol;
output [7:0] cathodes;
output [3:0] AN;
output reg highfreq;
always @*
begin
highfreq<=modecontrol;
end
wire [3:0] s3;
wire [3:0] s2;
wire [3:0] s1;
wire [3:0] s0;
wire [3:0] saved_s3;
wire [3:0] saved_s2;
wire [3:0] saved_s1;
wire [3:0] saved_s0;
hertz_clk_generation hz_clk_gn(.hz_clk(hz_clk),.system_clk(sysclk));
thousand_hertz_clk_generation th_hz_clk_gn(.hz_clk(th_hz_clk),.system_clk(sysclk));
range_switch rg_sw(.otput(otput),.iput(sigin),.modecontrol(modecontrol));
control_signal ct_sg(.save(save),.enable(enable),.reset(reset),.hz_clk(hz_clk));
decimal_counter dcm_ct(.s3(s3),.s2(s2),.s1(s1),.s0(s0),.iput(otput),.enable(enable),.reset(reset));
saver svr(.saved_s3(saved_s3),.saved_s2(saved_s2),.saved_s1(saved_s1),.saved_s0(saved_s0),.save(save),.s3(s3),.s2(s2),.s1(s1),.s0(s0));
show sh(.dout(cathodes),.an3(AN[3]),.an2(AN[2]),.an1(AN[1]),.an0(AN[0]),.th_hz_clk(th_hz_clk),.s3(saved_s3),.s2(saved_s2),.s1(saved_s1),.s0(saved_s0));
endmodule | module frequency (sigin,sysclk,modecontrol,highfreq,cathodes,AN); |
input sigin,sysclk,modecontrol;
output [7:0] cathodes;
output [3:0] AN;
output reg highfreq;
always @*
begin
highfreq<=modecontrol;
end
wire [3:0] s3;
wire [3:0] s2;
wire [3:0] s1;
wire [3:0] s0;
wire [3:0] saved_s3;
wire [3:0] saved_s2;
wire [3:0] saved_s1;
wire [3:0] saved_s0;
hertz_clk_generation hz_clk_gn(.hz_clk(hz_clk),.system_clk(sysclk));
thousand_hertz_clk_generation th_hz_clk_gn(.hz_clk(th_hz_clk),.system_clk(sysclk));
range_switch rg_sw(.otput(otput),.iput(sigin),.modecontrol(modecontrol));
control_signal ct_sg(.save(save),.enable(enable),.reset(reset),.hz_clk(hz_clk));
decimal_counter dcm_ct(.s3(s3),.s2(s2),.s1(s1),.s0(s0),.iput(otput),.enable(enable),.reset(reset));
saver svr(.saved_s3(saved_s3),.saved_s2(saved_s2),.saved_s1(saved_s1),.saved_s0(saved_s0),.save(save),.s3(s3),.s2(s2),.s1(s1),.s0(s0));
show sh(.dout(cathodes),.an3(AN[3]),.an2(AN[2]),.an1(AN[1]),.an0(AN[0]),.th_hz_clk(th_hz_clk),.s3(saved_s3),.s2(saved_s2),.s1(saved_s1),.s0(saved_s0));
endmodule | 0 |
139,365 | data/full_repos/permissive/87161578/exp3freq/src/signalinput.v | 87,161,578 | signalinput.v | v | 35 | 69 | [] | [] | [] | [(1, 34)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/87161578/exp3freq/src/signalinput.v:32: Operator ASSIGN expects 21 bits on the Assign RHS, but Assign RHS\'s CONST \'27\'h0\' generates 27 bits.\n : ... In instance signalinput\nstate=27\'b000_0000_0000_0000_0000_0000_0000;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 304,647 | module | module signalinput(
input [1:0] testmode,
input sysclk,
output sigin1
);
reg[20:0] state;
reg[20:0] divide;
reg sigin;
assign sigin1=sigin;
initial
begin
sigin=0;
state=21'b000000000000000000000;
divide=21'b000000_1111_1010_0000000;
end
always@(testmode)
begin
case(testmode[1:0])
2'b00:divide=21'b000000_1111_1010_0000000;
2'b01:divide=21'b0000000_1111_1010_000000;
2'b10:divide=21'b1111_0100_0010_0100_00000;
2'b11:divide=21'b00000000_1111_1010_00000;
endcase
end
always@(posedge sysclk)
begin
if(state==0)
sigin=~sigin;
state=state+21'b0_00__0000_0000_0000_0000_10;
if(state==divide)
state=27'b000_0000_0000_0000_0000_0000_0000;
end
endmodule | module signalinput(
input [1:0] testmode,
input sysclk,
output sigin1
); |
reg[20:0] state;
reg[20:0] divide;
reg sigin;
assign sigin1=sigin;
initial
begin
sigin=0;
state=21'b000000000000000000000;
divide=21'b000000_1111_1010_0000000;
end
always@(testmode)
begin
case(testmode[1:0])
2'b00:divide=21'b000000_1111_1010_0000000;
2'b01:divide=21'b0000000_1111_1010_000000;
2'b10:divide=21'b1111_0100_0010_0100_00000;
2'b11:divide=21'b00000000_1111_1010_00000;
endcase
end
always@(posedge sysclk)
begin
if(state==0)
sigin=~sigin;
state=state+21'b0_00__0000_0000_0000_0000_10;
if(state==divide)
state=27'b000_0000_0000_0000_0000_0000_0000;
end
endmodule | 0 |
139,366 | data/full_repos/permissive/87161578/exp3freq/src/top_exp3.v | 87,161,578 | top_exp3.v | v | 13 | 63 | [] | [] | [] | null | line:13: before: "/" | null | 1: b"%Error: data/full_repos/permissive/87161578/exp3freq/src/top_exp3.v:10: Cannot find file containing module: 'signalinput'\nsignalinput signalin(testmode,sysclk,sigin);\n^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/signalinput\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/signalinput.v\n data/full_repos/permissive/87161578/exp3freq/src,data/full_repos/permissive/87161578/signalinput.sv\n signalinput\n signalinput.v\n signalinput.sv\n obj_dir/signalinput\n obj_dir/signalinput.v\n obj_dir/signalinput.sv\n%Error: data/full_repos/permissive/87161578/exp3freq/src/top_exp3.v:11: Cannot find file containing module: 'frequency'\nfrequency freq(sigin,sysclk,modecontrol,highfreq,Cathodes,AN);\n^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 304,648 | module | module test(
input [1:0] testmode,
input sysclk,
input modecontrol,
output highfreq,
output [7:0]Cathodes,
output[3:0] AN
);
wire sigin;
signalinput signalin(testmode,sysclk,sigin);
frequency freq(sigin,sysclk,modecontrol,highfreq,Cathodes,AN);
endmodule | module test(
input [1:0] testmode,
input sysclk,
input modecontrol,
output highfreq,
output [7:0]Cathodes,
output[3:0] AN
); |
wire sigin;
signalinput signalin(testmode,sysclk,sigin);
frequency freq(sigin,sysclk,modecontrol,highfreq,Cathodes,AN);
endmodule | 0 |
139,367 | data/full_repos/permissive/87161578/exp3freq/src/top_exp3_tb.v | 87,161,578 | top_exp3_tb.v | v | 17 | 60 | [] | [] | [] | [(2, 17)] | null | null | 1: b'%Error: data/full_repos/permissive/87161578/exp3freq/src/top_exp3_tb.v:9: Unsupported: fork statements\ninitial fork\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp3freq/src/top_exp3_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\nforever #2 sysclk<=~sysclk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,649 | module | module exp3_tb;
reg [1:0] testmode;
reg sysclk,modecontrol;
wire highfreq;
wire [7:0] Cathodes;
wire [3:0] AN;
test tst(testmode,sysclk,modecontrol,highfreq,Cathodes,AN);
initial fork
sysclk<=0;
testmode<=1;
modecontrol<=0;
forever #2 sysclk<=~sysclk;
join
endmodule | module exp3_tb; |
reg [1:0] testmode;
reg sysclk,modecontrol;
wire highfreq;
wire [7:0] Cathodes;
wire [3:0] AN;
test tst(testmode,sysclk,modecontrol,highfreq,Cathodes,AN);
initial fork
sysclk<=0;
testmode<=1;
modecontrol<=0;
forever #2 sysclk<=~sysclk;
join
endmodule | 0 |
139,368 | data/full_repos/permissive/87161578/exp4uart/src/component.v | 87,161,578 | component.v | v | 276 | 80 | [] | [] | [] | [(1, 37), (39, 100), (102, 180), (182, 276)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/87161578/exp4uart/src/component.v:39: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'baud_rate_generation\'\nmodule baud_rate_generation(baud,sysclk,reset); \n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'receiver\'\nmodule receiver(rx_data,rx_status,baud,rxd,reset);\n ^~~~~~~~\n : ... Top module \'controller\'\nmodule controller(tx_data,tx_en,baud,tx_status,rx_status,rx_data,reset,sysclk);\n ^~~~~~~~~~\n : ... Top module \'sender\'\nmodule sender(txd,tx_status,tx_en,tx_data,reset,baud,sysclk);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 304,650 | module | module baud_rate_generation(baud,sysclk,reset);
input sysclk,reset;
output reg baud;
reg [17:0] s;
initial begin
s<=1;
baud<=0;
end
always @(posedge sysclk)
begin
if (reset)
begin
s<=1;
baud<=0;
end
s<=s+1;
if(s==18'd326)
baud<=~baud;
else if(s==18'd651)
baud<=~baud;
else if(s==18'd977)
baud<=~baud;
else if(s==18'd1302)
baud<=~baud;
else if(s==18'd1628)
baud<=~baud;
else if (s==18'd1953)
baud<=~baud;
else if(s==18'd2279)
baud<=~baud;
else if (s==18'd2604)
begin
baud<=~baud;
s<=1;
end
end
endmodule | module baud_rate_generation(baud,sysclk,reset); |
input sysclk,reset;
output reg baud;
reg [17:0] s;
initial begin
s<=1;
baud<=0;
end
always @(posedge sysclk)
begin
if (reset)
begin
s<=1;
baud<=0;
end
s<=s+1;
if(s==18'd326)
baud<=~baud;
else if(s==18'd651)
baud<=~baud;
else if(s==18'd977)
baud<=~baud;
else if(s==18'd1302)
baud<=~baud;
else if(s==18'd1628)
baud<=~baud;
else if (s==18'd1953)
baud<=~baud;
else if(s==18'd2279)
baud<=~baud;
else if (s==18'd2604)
begin
baud<=~baud;
s<=1;
end
end
endmodule | 0 |
139,369 | data/full_repos/permissive/87161578/exp4uart/src/component.v | 87,161,578 | component.v | v | 276 | 80 | [] | [] | [] | [(1, 37), (39, 100), (102, 180), (182, 276)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/87161578/exp4uart/src/component.v:39: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'baud_rate_generation\'\nmodule baud_rate_generation(baud,sysclk,reset); \n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'receiver\'\nmodule receiver(rx_data,rx_status,baud,rxd,reset);\n ^~~~~~~~\n : ... Top module \'controller\'\nmodule controller(tx_data,tx_en,baud,tx_status,rx_status,rx_data,reset,sysclk);\n ^~~~~~~~~~\n : ... Top module \'sender\'\nmodule sender(txd,tx_status,tx_en,tx_data,reset,baud,sysclk);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 304,650 | module | module receiver(rx_data,rx_status,baud,rxd,reset);
output reg [7:0] rx_data;
reg [7:0] new_rx_data;
output reg rx_status;
input baud,rxd,reset;
reg started;
reg [7:0] count;
initial begin
started<=0;
rx_data<=8'b0;
new_rx_data<=8'b0;
rx_status<=0;
count<=0;
end
always @(posedge baud)
begin
if (reset)
begin
started<=0;
rx_data<=8'b0;
new_rx_data<=8'b0;
rx_status<=0;
count<=0;
end
else if (~rxd && ~started)
started<=1;
if (started)
count<=count+1;
if (count==8'd160)
begin
count<=0;
started<=0;
end
if (count==8'd24)
new_rx_data[0]<=rxd;
else if (count==8'd40)
new_rx_data[1]<=rxd;
else if (count==8'd56)
new_rx_data[2]<=rxd;
else if (count==8'd72)
new_rx_data[3]<=rxd;
else if (count==8'd88)
new_rx_data[4]<=rxd;
else if (count==8'd104)
new_rx_data[5]<=rxd;
else if (count==8'd120)
new_rx_data[6]<=rxd;
else if (count==8'd136)
new_rx_data[7]<=rxd;
else if (count==8'd152)
begin
rx_data<=new_rx_data;
rx_status<=1;
end
else if (count==8'd154)
rx_status<=0;
end
endmodule | module receiver(rx_data,rx_status,baud,rxd,reset); |
output reg [7:0] rx_data;
reg [7:0] new_rx_data;
output reg rx_status;
input baud,rxd,reset;
reg started;
reg [7:0] count;
initial begin
started<=0;
rx_data<=8'b0;
new_rx_data<=8'b0;
rx_status<=0;
count<=0;
end
always @(posedge baud)
begin
if (reset)
begin
started<=0;
rx_data<=8'b0;
new_rx_data<=8'b0;
rx_status<=0;
count<=0;
end
else if (~rxd && ~started)
started<=1;
if (started)
count<=count+1;
if (count==8'd160)
begin
count<=0;
started<=0;
end
if (count==8'd24)
new_rx_data[0]<=rxd;
else if (count==8'd40)
new_rx_data[1]<=rxd;
else if (count==8'd56)
new_rx_data[2]<=rxd;
else if (count==8'd72)
new_rx_data[3]<=rxd;
else if (count==8'd88)
new_rx_data[4]<=rxd;
else if (count==8'd104)
new_rx_data[5]<=rxd;
else if (count==8'd120)
new_rx_data[6]<=rxd;
else if (count==8'd136)
new_rx_data[7]<=rxd;
else if (count==8'd152)
begin
rx_data<=new_rx_data;
rx_status<=1;
end
else if (count==8'd154)
rx_status<=0;
end
endmodule | 0 |
139,370 | data/full_repos/permissive/87161578/exp4uart/src/component.v | 87,161,578 | component.v | v | 276 | 80 | [] | [] | [] | [(1, 37), (39, 100), (102, 180), (182, 276)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/87161578/exp4uart/src/component.v:39: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'baud_rate_generation\'\nmodule baud_rate_generation(baud,sysclk,reset); \n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'receiver\'\nmodule receiver(rx_data,rx_status,baud,rxd,reset);\n ^~~~~~~~\n : ... Top module \'controller\'\nmodule controller(tx_data,tx_en,baud,tx_status,rx_status,rx_data,reset,sysclk);\n ^~~~~~~~~~\n : ... Top module \'sender\'\nmodule sender(txd,tx_status,tx_en,tx_data,reset,baud,sysclk);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 304,650 | module | module controller(tx_data,tx_en,baud,tx_status,rx_status,rx_data,reset,sysclk);
input [7:0] rx_data;
reg [7:0] data;
reg ready,ready2,rx_high,rx_negedge,rx_negedge2;
input rx_status,tx_status,baud,sysclk;
input reset;
output reg tx_en;
output reg [7:0] tx_data;
initial begin
tx_en<=0;
tx_data<=8'b0;
data<=8'b0;
ready<=0;
ready2<=0;
rx_high<=0;
rx_negedge2<=0;
rx_negedge<=0;
end
always @(posedge baud)
begin
if (rx_status)
rx_high<=1;
else if(rx_negedge2)
begin
rx_negedge2<=0;
rx_negedge<=0;
end
else if(rx_negedge)
begin
rx_negedge2<=1;
end
else if(~rx_status && rx_high)
begin
rx_negedge<=1;
rx_high<=0;
end
end
always @(posedge sysclk)
begin
if (rx_negedge)
begin
if (rx_data[7]==1)
data<=~rx_data;
else
data<=rx_data;
end
end
always @(posedge baud)
begin
if (reset)
begin
tx_en<=0;
tx_data<=8'b0;
end
if (ready && tx_status)
begin
tx_en<=1;
ready2<=1;
end
else if (ready2)
begin
ready2<=0;
ready<=0;
end
else if (~ready)
begin
tx_en<=0;
end
if (rx_negedge)
begin
ready<=1;
tx_data<=data;
end
end
endmodule | module controller(tx_data,tx_en,baud,tx_status,rx_status,rx_data,reset,sysclk); |
input [7:0] rx_data;
reg [7:0] data;
reg ready,ready2,rx_high,rx_negedge,rx_negedge2;
input rx_status,tx_status,baud,sysclk;
input reset;
output reg tx_en;
output reg [7:0] tx_data;
initial begin
tx_en<=0;
tx_data<=8'b0;
data<=8'b0;
ready<=0;
ready2<=0;
rx_high<=0;
rx_negedge2<=0;
rx_negedge<=0;
end
always @(posedge baud)
begin
if (rx_status)
rx_high<=1;
else if(rx_negedge2)
begin
rx_negedge2<=0;
rx_negedge<=0;
end
else if(rx_negedge)
begin
rx_negedge2<=1;
end
else if(~rx_status && rx_high)
begin
rx_negedge<=1;
rx_high<=0;
end
end
always @(posedge sysclk)
begin
if (rx_negedge)
begin
if (rx_data[7]==1)
data<=~rx_data;
else
data<=rx_data;
end
end
always @(posedge baud)
begin
if (reset)
begin
tx_en<=0;
tx_data<=8'b0;
end
if (ready && tx_status)
begin
tx_en<=1;
ready2<=1;
end
else if (ready2)
begin
ready2<=0;
ready<=0;
end
else if (~ready)
begin
tx_en<=0;
end
if (rx_negedge)
begin
ready<=1;
tx_data<=data;
end
end
endmodule | 0 |
139,371 | data/full_repos/permissive/87161578/exp4uart/src/component.v | 87,161,578 | component.v | v | 276 | 80 | [] | [] | [] | [(1, 37), (39, 100), (102, 180), (182, 276)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/87161578/exp4uart/src/component.v:39: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'baud_rate_generation\'\nmodule baud_rate_generation(baud,sysclk,reset); \n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'receiver\'\nmodule receiver(rx_data,rx_status,baud,rxd,reset);\n ^~~~~~~~\n : ... Top module \'controller\'\nmodule controller(tx_data,tx_en,baud,tx_status,rx_status,rx_data,reset,sysclk);\n ^~~~~~~~~~\n : ... Top module \'sender\'\nmodule sender(txd,tx_status,tx_en,tx_data,reset,baud,sysclk);\n ^~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 304,650 | module | module sender(txd,tx_status,tx_en,tx_data,reset,baud,sysclk);
output reg txd;
output reg tx_status;
input tx_en,reset,baud,sysclk;
input [7:0] tx_data;
reg [7:0] data;
reg [7:0] count;
reg enabled,stop,started;
initial begin
txd<=1;
tx_status<=1;
enabled<=0;
stop<=0;
started<=0;
data<=8'b0;
count<=0;
end
always @(posedge sysclk)
begin
if (reset)
tx_status<=1;
else if (stop)
begin
tx_status<=1;
end
else if (tx_en)
begin
tx_status<=0;
end
end
always @(posedge baud)
begin
if (reset)
begin
started<=0;
data<=8'b0;
end
else if (tx_en)
enabled<=1;
else if (~tx_en && enabled)
begin
enabled<=0;
started<=1;
data<=tx_data;
end
if (baud)
begin
if (started)
begin
count<=count+1;
if (count==8'd160)
begin
stop<=1;
end
else if (count==8'd161)
begin
count<=0;
stop<=0;
started<=0;
end
if (count==8'd0)
txd<=0;
else if (count==8'd16)
txd<=data[0];
else if (count==8'd32)
txd<=data[1];
else if (count==8'd48)
txd<=data[2];
else if (count==8'd64)
txd<=data[3];
else if (count==8'd80)
txd<=data[4];
else if (count==8'd96)
txd<=data[5];
else if (count==8'd112)
txd<=data[6];
else if (count==8'd128)
txd<=data[7];
else if (count==8'd144)
begin
txd<=1;
end
end
end
end
endmodule | module sender(txd,tx_status,tx_en,tx_data,reset,baud,sysclk); |
output reg txd;
output reg tx_status;
input tx_en,reset,baud,sysclk;
input [7:0] tx_data;
reg [7:0] data;
reg [7:0] count;
reg enabled,stop,started;
initial begin
txd<=1;
tx_status<=1;
enabled<=0;
stop<=0;
started<=0;
data<=8'b0;
count<=0;
end
always @(posedge sysclk)
begin
if (reset)
tx_status<=1;
else if (stop)
begin
tx_status<=1;
end
else if (tx_en)
begin
tx_status<=0;
end
end
always @(posedge baud)
begin
if (reset)
begin
started<=0;
data<=8'b0;
end
else if (tx_en)
enabled<=1;
else if (~tx_en && enabled)
begin
enabled<=0;
started<=1;
data<=tx_data;
end
if (baud)
begin
if (started)
begin
count<=count+1;
if (count==8'd160)
begin
stop<=1;
end
else if (count==8'd161)
begin
count<=0;
stop<=0;
started<=0;
end
if (count==8'd0)
txd<=0;
else if (count==8'd16)
txd<=data[0];
else if (count==8'd32)
txd<=data[1];
else if (count==8'd48)
txd<=data[2];
else if (count==8'd64)
txd<=data[3];
else if (count==8'd80)
txd<=data[4];
else if (count==8'd96)
txd<=data[5];
else if (count==8'd112)
txd<=data[6];
else if (count==8'd128)
txd<=data[7];
else if (count==8'd144)
begin
txd<=1;
end
end
end
end
endmodule | 0 |
139,372 | data/full_repos/permissive/87161578/exp4uart/src/top_uart.v | 87,161,578 | top_uart.v | v | 13 | 154 | [] | [] | [] | [(1, 12)] | null | null | 1: b"%Error: data/full_repos/permissive/87161578/exp4uart/src/top_uart.v:6: Cannot find file containing module: 'baud_rate_generation'\nbaud_rate_generation baud_gen(.baud(baud),.sysclk(sysclk),.reset(reset));\n^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87161578/exp4uart/src,data/full_repos/permissive/87161578/baud_rate_generation\n data/full_repos/permissive/87161578/exp4uart/src,data/full_repos/permissive/87161578/baud_rate_generation.v\n data/full_repos/permissive/87161578/exp4uart/src,data/full_repos/permissive/87161578/baud_rate_generation.sv\n baud_rate_generation\n baud_rate_generation.v\n baud_rate_generation.sv\n obj_dir/baud_rate_generation\n obj_dir/baud_rate_generation.v\n obj_dir/baud_rate_generation.sv\n%Error: data/full_repos/permissive/87161578/exp4uart/src/top_uart.v:8: Cannot find file containing module: 'receiver'\nreceiver recv(.rx_data(rx_data),.rx_status(rx_status),.baud(baud),.rxd(rxd),.reset(reset));\n^~~~~~~~\n%Error: data/full_repos/permissive/87161578/exp4uart/src/top_uart.v:9: Cannot find file containing module: 'controller'\ncontroller cont(.tx_data(tx_data),.tx_en(tx_en),.baud(baud),.tx_status(tx_status),.rx_status(rx_status),.rx_data(rx_data),.reset(reset),.sysclk(sysclk));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/87161578/exp4uart/src/top_uart.v:10: Cannot find file containing module: 'sender'\nsender send(.txd(txd),.tx_status(tx_status),.tx_en(tx_en),.tx_data(tx_data),.reset(reset),.baud(baud),.sysclk(sysclk));\n^~~~~~\n%Error: Exiting due to 4 error(s)\n" | 304,651 | module | module uart(txd,rxd,sysclk,reset);
output txd;
input rxd;
input sysclk,reset;
wire [7:0] tx_data,rx_data;
baud_rate_generation baud_gen(.baud(baud),.sysclk(sysclk),.reset(reset));
receiver recv(.rx_data(rx_data),.rx_status(rx_status),.baud(baud),.rxd(rxd),.reset(reset));
controller cont(.tx_data(tx_data),.tx_en(tx_en),.baud(baud),.tx_status(tx_status),.rx_status(rx_status),.rx_data(rx_data),.reset(reset),.sysclk(sysclk));
sender send(.txd(txd),.tx_status(tx_status),.tx_en(tx_en),.tx_data(tx_data),.reset(reset),.baud(baud),.sysclk(sysclk));
endmodule | module uart(txd,rxd,sysclk,reset); |
output txd;
input rxd;
input sysclk,reset;
wire [7:0] tx_data,rx_data;
baud_rate_generation baud_gen(.baud(baud),.sysclk(sysclk),.reset(reset));
receiver recv(.rx_data(rx_data),.rx_status(rx_status),.baud(baud),.rxd(rxd),.reset(reset));
controller cont(.tx_data(tx_data),.tx_en(tx_en),.baud(baud),.tx_status(tx_status),.rx_status(rx_status),.rx_data(rx_data),.reset(reset),.sysclk(sysclk));
sender send(.txd(txd),.tx_status(tx_status),.tx_en(tx_en),.tx_data(tx_data),.reset(reset),.baud(baud),.sysclk(sysclk));
endmodule | 0 |
Subsets and Splits
No saved queries yet
Save your SQL queries to embed, download, and access them later. Queries will appear here once saved.