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139,373 | data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v | 87,161,578 | uart_tb.v | v | 91 | 71 | [] | [] | [] | null | line:22: before: "," | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #5 clk=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #2000 inverse<=~inverse;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #2400000 reset<=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #1000 rx=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n #2400000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n #2400000\n ^\n%Warning-IMPLICIT: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:83: Signal definition not found, creating implicitly: \'baud_base\'\nbaud_base bd_base(.baud_base(baud_base),.baud(baud));\n ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:83: Signal definition not found, creating implicitly: \'baud\'\nbaud_base bd_base(.baud_base(baud_base),.baud(baud));\n ^~~~\n%Error: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:81: Cannot find file containing module: \'baud_rate_generation\'\nbaud_rate_generation baud_gen(.baud(baud),.sysclk(clk),.reset(reset));\n^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87161578/exp4uart/src,data/full_repos/permissive/87161578/baud_rate_generation\n data/full_repos/permissive/87161578/exp4uart/src,data/full_repos/permissive/87161578/baud_rate_generation.v\n data/full_repos/permissive/87161578/exp4uart/src,data/full_repos/permissive/87161578/baud_rate_generation.sv\n baud_rate_generation\n baud_rate_generation.v\n baud_rate_generation.sv\n obj_dir/baud_rate_generation\n obj_dir/baud_rate_generation.v\n obj_dir/baud_rate_generation.sv\n%Error: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:84: Cannot find file containing module: \'uart\'\nuart uart\n^~~~\n%Error: Exiting due to 2 error(s), 47 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,652 | module | module baud_base(baud_base,baud);
input baud;
output reg baud_base;
reg [3:0] s;
initial begin
s<=0;
baud_base<=0;
end
always @(posedge baud)
begin
s<=s+1;
if (s==4'd15)
begin
baud_base<=~baud_base;
end
end
endmodule | module baud_base(baud_base,baud); |
input baud;
output reg baud_base;
reg [3:0] s;
initial begin
s<=0;
baud_base<=0;
end
always @(posedge baud)
begin
s<=s+1;
if (s==4'd15)
begin
baud_base<=~baud_base;
end
end
endmodule | 0 |
139,374 | data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v | 87,161,578 | uart_tb.v | v | 91 | 71 | [] | [] | [] | null | line:22: before: "," | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #5 clk=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #2000 inverse<=~inverse;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #2400000 reset<=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #1000 rx=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n #2400000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n #104166.667 rx=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n #2400000\n ^\n%Warning-IMPLICIT: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:83: Signal definition not found, creating implicitly: \'baud_base\'\nbaud_base bd_base(.baud_base(baud_base),.baud(baud));\n ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:83: Signal definition not found, creating implicitly: \'baud\'\nbaud_base bd_base(.baud_base(baud_base),.baud(baud));\n ^~~~\n%Error: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:81: Cannot find file containing module: \'baud_rate_generation\'\nbaud_rate_generation baud_gen(.baud(baud),.sysclk(clk),.reset(reset));\n^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87161578/exp4uart/src,data/full_repos/permissive/87161578/baud_rate_generation\n data/full_repos/permissive/87161578/exp4uart/src,data/full_repos/permissive/87161578/baud_rate_generation.v\n data/full_repos/permissive/87161578/exp4uart/src,data/full_repos/permissive/87161578/baud_rate_generation.sv\n baud_rate_generation\n baud_rate_generation.v\n baud_rate_generation.sv\n obj_dir/baud_rate_generation\n obj_dir/baud_rate_generation.v\n obj_dir/baud_rate_generation.sv\n%Error: data/full_repos/permissive/87161578/exp4uart/src/uart_tb.v:84: Cannot find file containing module: \'uart\'\nuart uart\n^~~~\n%Error: Exiting due to 2 error(s), 47 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,652 | module | module uart_test;
reg [4:0] inverse=5'b10011;
reg clk=0,reset=0,rx=1;
wire tx;
always
begin
#5 clk=~clk;
end
initial
begin
#2000 inverse<=~inverse;
reset<=1;
#2400000 reset<=0;
#1000 rx=0;
#104166.667 rx=1;
#104166.667 rx=0;
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=1;
#104166.667 rx=1;
#104166.667 rx=1;
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=0;
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=1;
#104166.667 rx=1;
#104166.667 rx=1;
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=0;
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=1;
#104166.667 rx=1;
#104166.667 rx=1;
#2400000
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=0;
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=1;
#104166.667 rx=1;
#104166.667 rx=1;
#2400000
$stop;
end
baud_rate_generation baud_gen(.baud(baud),.sysclk(clk),.reset(reset));
baud_base bd_base(.baud_base(baud_base),.baud(baud));
uart uart
(
.txd(tx),
.rxd(rx),
.sysclk(clk),
.reset(reset)
);
endmodule | module uart_test; |
reg [4:0] inverse=5'b10011;
reg clk=0,reset=0,rx=1;
wire tx;
always
begin
#5 clk=~clk;
end
initial
begin
#2000 inverse<=~inverse;
reset<=1;
#2400000 reset<=0;
#1000 rx=0;
#104166.667 rx=1;
#104166.667 rx=0;
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=1;
#104166.667 rx=1;
#104166.667 rx=1;
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=0;
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=1;
#104166.667 rx=1;
#104166.667 rx=1;
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=0;
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=1;
#104166.667 rx=1;
#104166.667 rx=1;
#2400000
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=0;
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=0;
#104166.667 rx=1;
#104166.667 rx=1;
#104166.667 rx=1;
#104166.667 rx=1;
#2400000
$stop;
end
baud_rate_generation baud_gen(.baud(baud),.sysclk(clk),.reset(reset));
baud_base bd_base(.baud_base(baud_base),.baud(baud));
uart uart
(
.txd(tx),
.rxd(rx),
.sysclk(clk),
.reset(reset)
);
endmodule | 0 |
139,386 | data/full_repos/permissive/87244188/src/lc4_decoder.v | 87,244,188 | lc4_decoder.v | v | 91 | 106 | [] | [] | [] | [(3, 90)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/87244188/src/lc4_decoder.v:38: Operator COND expects 5 bits on the Conditional True, but Conditional True\'s CONST \'4\'h7\' generates 4 bits.\n : ... In instance lc4_decoder\n assign r1sel = (opcode == 5\'b01010) ? 4\'d7 : insn[9:5]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 304,655 | module | module lc4_decoder(insn,
r1sel,
r1re,
r2sel,
r2re,
wsel,
regfile_we,
nzp_we,
select_pc_plus_one,
is_branch,
is_control_insn);
input [19:0] insn;
output [4:0] r1sel;
output r1re;
output [4:0] r2sel;
output r2re;
output [4:0] wsel;
output regfile_we;
output nzp_we;
output select_pc_plus_one;
output is_branch;
output is_control_insn;
wire [4:0] opcode = insn[19:15];
assign is_branch = opcode == 5'b00000 |
opcode == 5'b00001 |
opcode == 5'b00010 |
opcode == 5'b00011 |
opcode == 5'b00100;
assign r1sel = (opcode == 5'b01010) ? 4'd7 : insn[9:5];
assign r1re = opcode == 5'b00101 |
opcode == 5'b00110 |
opcode == 5'b00111 |
opcode == 5'b01001 |
opcode == 5'b01100 |
opcode == 5'b01101 |
opcode == 5'b01110 |
opcode == 5'b01111 |
opcode == 5'b10000 |
opcode == 5'b10010 |
opcode == 5'b10011 |
opcode == 5'b10100 |
opcode == 5'b10101 |
opcode == 5'b10110 |
opcode == 5'b11001;
assign r2sel = insn[4:0];
assign r2re = opcode == 5'b00101 |
opcode == 5'b00110 |
opcode == 5'b01100 |
opcode == 5'b01101 |
opcode == 5'b01110 |
opcode == 5'b01111 |
opcode == 5'b10010 |
opcode == 5'b10100 |
opcode == 5'b10101 ;
assign wsel = (opcode == 5'b01000)
? 5'd7 : insn[14:10];
assign nzp_we = r1re |
opcode == 5'b01011 |
opcode == 5'b01000 |
opcode == 5'b10111 |
opcode == 5'b11000 |
opcode == 5'b11001;
assign regfile_we = nzp_we &
(opcode != 5'b10000 &
opcode != 5'b10011 &
opcode != 5'b11000 &
opcode != 5'b11001);
assign select_pc_plus_one = opcode == 5'b01000;
assign is_control_insn = opcode == 5'b01000 |
opcode == 5'b01010;
endmodule | module lc4_decoder(insn,
r1sel,
r1re,
r2sel,
r2re,
wsel,
regfile_we,
nzp_we,
select_pc_plus_one,
is_branch,
is_control_insn); |
input [19:0] insn;
output [4:0] r1sel;
output r1re;
output [4:0] r2sel;
output r2re;
output [4:0] wsel;
output regfile_we;
output nzp_we;
output select_pc_plus_one;
output is_branch;
output is_control_insn;
wire [4:0] opcode = insn[19:15];
assign is_branch = opcode == 5'b00000 |
opcode == 5'b00001 |
opcode == 5'b00010 |
opcode == 5'b00011 |
opcode == 5'b00100;
assign r1sel = (opcode == 5'b01010) ? 4'd7 : insn[9:5];
assign r1re = opcode == 5'b00101 |
opcode == 5'b00110 |
opcode == 5'b00111 |
opcode == 5'b01001 |
opcode == 5'b01100 |
opcode == 5'b01101 |
opcode == 5'b01110 |
opcode == 5'b01111 |
opcode == 5'b10000 |
opcode == 5'b10010 |
opcode == 5'b10011 |
opcode == 5'b10100 |
opcode == 5'b10101 |
opcode == 5'b10110 |
opcode == 5'b11001;
assign r2sel = insn[4:0];
assign r2re = opcode == 5'b00101 |
opcode == 5'b00110 |
opcode == 5'b01100 |
opcode == 5'b01101 |
opcode == 5'b01110 |
opcode == 5'b01111 |
opcode == 5'b10010 |
opcode == 5'b10100 |
opcode == 5'b10101 ;
assign wsel = (opcode == 5'b01000)
? 5'd7 : insn[14:10];
assign nzp_we = r1re |
opcode == 5'b01011 |
opcode == 5'b01000 |
opcode == 5'b10111 |
opcode == 5'b11000 |
opcode == 5'b11001;
assign regfile_we = nzp_we &
(opcode != 5'b10000 &
opcode != 5'b10011 &
opcode != 5'b11000 &
opcode != 5'b11001);
assign select_pc_plus_one = opcode == 5'b01000;
assign is_control_insn = opcode == 5'b01000 |
opcode == 5'b01010;
endmodule | 2 |
139,394 | data/full_repos/permissive/87244188/src/Nbit_reg.v | 87,244,188 | Nbit_reg.v | v | 34 | 82 | [] | [] | [] | [(11, 33)] | null | data/verilator_xmls/6760019c-a6c9-452d-b047-48386159676a.xml | null | 304,658 | module | module Nbit_reg(in, out, clk, we, gwe, rst);
parameter n = 1;
parameter r = 0;
output [n-1:0] out;
input [n-1:0] in;
input clk;
input we;
input gwe;
input rst;
reg [n-1:0] state;
assign #(1) out = state;
always @(posedge clk)
begin
if (gwe & rst)
state = r;
else if (gwe & we)
state = in;
end
endmodule | module Nbit_reg(in, out, clk, we, gwe, rst); |
parameter n = 1;
parameter r = 0;
output [n-1:0] out;
input [n-1:0] in;
input clk;
input we;
input gwe;
input rst;
reg [n-1:0] state;
assign #(1) out = state;
always @(posedge clk)
begin
if (gwe & rst)
state = r;
else if (gwe & we)
state = in;
end
endmodule | 2 |
139,395 | data/full_repos/permissive/87244188/src/system.v | 87,244,188 | system.v | v | 164 | 99 | [] | [] | [] | null | line:18: before: ")" | null | 1: b"%Error: data/full_repos/permissive/87244188/src/system.v:18: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/87244188/src/system.v:22: syntax error, unexpected input\n input CLK; \n ^~~~~\n%Error: data/full_repos/permissive/87244188/src/system.v:34: syntax error, unexpected output\n output [7:0] led_data;\n ^~~~~~\n%Error: data/full_repos/permissive/87244188/src/system.v:47: syntax error, unexpected assign\n assign RST_BTN_IN = SWITCH_IN[0];\n ^~~~~~\n%Error: data/full_repos/permissive/87244188/src/system.v:55: syntax error, unexpected IDENTIFIER\n one_pulse clk_pulse(.clk( proc_clk ),\n ^~~~~~~~~\n%Error: data/full_repos/permissive/87244188/src/system.v:63: syntax error, unexpected IDENTIFIER\n Nbit_reg #(1, 0) gwe_cleaner(.in(SWITCH_IN[7]), \n ^~~~~~~~\n%Error: data/full_repos/permissive/87244188/src/system.v:72: syntax error, unexpected IDENTIFIER\n lc4_we_gen we_gen(.clk(proc_clk),\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/87244188/src/system.v:86: syntax error, unexpected IDENTIFIER\n Nbit_reg #(1, 0) reset_cleaner(.in( RST_BTN_IN ),\n ^~~~~~~~\n%Error: data/full_repos/permissive/87244188/src/system.v:116: syntax error, unexpected IDENTIFIER\n lc4_processor #(.WORD_SIZE(WORD_SIZE))\n ^~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n" | 304,659 | module | module lc4_system(
CLK,
RS232_Rx,
SWITCH1, SWITCH2, SWITCH3, SWITCH4, SWITCH5, SWITCH6, SWITCH7, SWITCH8,
RS232_Tx,
LED1,
LED2,
LED3,
LED4,
led_data,
dmem_mout_out,
);
parameter WORD_SIZE = 256;
parameter REG_ADDR_BITS = 3;
input CLK;
input RS232_Rx;
input SWITCH1, SWITCH2, SWITCH3, SWITCH4, SWITCH5, SWITCH6, SWITCH7, SWITCH8;
output RS232_Tx;
output LED1;
output LED2;
output LED3;
output LED4;
output [15:0] dmem_mout_out;
assign dmem_mout_out = dmem_mout;
wire [15:0] seven_segment_data;
output [7:0] led_data;
wire GLOBAL_RST = 0;
wire GLOBAL_WE;
wire dcm_reset_1 = 1'b0;
wire dcm_reset_2 = 1'b0;
wire proc_clk = CLK;
wire pixel_clk = CLK;
wire [7:0] SWITCH_IN = {SWITCH1, SWITCH2, SWITCH3, SWITCH4, SWITCH5, SWITCH6, SWITCH7, SWITCH8};
wire RST_BTN_IN;
wire GWE_BTN_IN;
assign RST_BTN_IN = SWITCH_IN[0];
assign GWE_BTN_IN = 1'b0;
wire global_we_pulse;
one_pulse clk_pulse(.clk( proc_clk ),
.rst( dcm_reset_1 | dcm_reset_2 ),
.btn( GWE_BTN_IN ),
.pulse_out( global_we_pulse ));
wire global_we_switch;
Nbit_reg #(1, 0) gwe_cleaner(.in(SWITCH_IN[7]),
.out( global_we_switch ),
.clk( proc_clk ),
.we( 1'b1 ),
.gwe( 1'b1 ),
.rst( GLOBAL_RST ));
wire i1re, i2re, dre, gwe_out;
lc4_we_gen we_gen(.clk(proc_clk),
.i1re(i1re),
.i2re(i2re),
.dre(dre),
.gwe(gwe_out));
assign GLOBAL_WE = global_we_pulse | (gwe_out & global_we_switch);
wire rst_btn;
Nbit_reg #(1, 0) reset_cleaner(.in( RST_BTN_IN ),
.out( rst_btn ),
.clk( proc_clk ),
.we( 1'b1 ),
.gwe( 1'b1 ),
.rst( dcm_reset_1 | dcm_reset_2 ));
or( GLOBAL_RST, dcm_reset_1, dcm_reset_2, rst_btn );
wire [15:0] imem1_addr, imem2_addr;
wire [15:0] imem1_out, imem2_out;
wire [REG_ADDR_BITS-1:0] dmem_raddr;
wire [REG_ADDR_BITS-1:0] dmem_waddr;
wire [WORD_SIZE-1:0] dmem_in;
wire dmem_we;
wire [WORD_SIZE-1:0] dmem_mout;
lc4_processor #(.WORD_SIZE(WORD_SIZE))
proc_inst(.clk(proc_clk),
.rst(GLOBAL_RST),
.gwe(GLOBAL_WE),
.o_cur_pc(imem1_addr),
.i_cur_insn(imem1_out),
.o_dmem_raddr(dmem_raddr),
.o_dmem_waddr(dmem_waddr),
.i_cur_dmem_data(dmem_mout),
.o_dmem_we(dmem_we),
.o_dmem_towrite(dmem_in),
);
assign imem2_addr = 16'd0;
assign RS232_Tx = led_data[0];
assign LED1 = led_data[1];
assign LED2 = led_data[2];
assign LED3 = led_data[3];
assign LED4 = led_data[4];
lc4_memory
#(.WORD_SIZE(WORD_SIZE))
memory (.idclk(proc_clk),
.i1re(i1re),
.i2re(i2re),
.dre(dre),
.gwe(GLOBAL_WE),
.rst(GLOBAL_RST),
.i1addr(imem1_addr),
.i2addr(imem2_addr),
.i1out(imem1_out),
.i2out(imem2_out),
.draddr(dmem_raddr),
.dwaddr(dmem_waddr),
.din(dmem_in),
.dout(dmem_mout),
.dwe(dmem_we)
);
endmodule | module lc4_system(
CLK,
RS232_Rx,
SWITCH1, SWITCH2, SWITCH3, SWITCH4, SWITCH5, SWITCH6, SWITCH7, SWITCH8,
RS232_Tx,
LED1,
LED2,
LED3,
LED4,
led_data,
dmem_mout_out,
); |
parameter WORD_SIZE = 256;
parameter REG_ADDR_BITS = 3;
input CLK;
input RS232_Rx;
input SWITCH1, SWITCH2, SWITCH3, SWITCH4, SWITCH5, SWITCH6, SWITCH7, SWITCH8;
output RS232_Tx;
output LED1;
output LED2;
output LED3;
output LED4;
output [15:0] dmem_mout_out;
assign dmem_mout_out = dmem_mout;
wire [15:0] seven_segment_data;
output [7:0] led_data;
wire GLOBAL_RST = 0;
wire GLOBAL_WE;
wire dcm_reset_1 = 1'b0;
wire dcm_reset_2 = 1'b0;
wire proc_clk = CLK;
wire pixel_clk = CLK;
wire [7:0] SWITCH_IN = {SWITCH1, SWITCH2, SWITCH3, SWITCH4, SWITCH5, SWITCH6, SWITCH7, SWITCH8};
wire RST_BTN_IN;
wire GWE_BTN_IN;
assign RST_BTN_IN = SWITCH_IN[0];
assign GWE_BTN_IN = 1'b0;
wire global_we_pulse;
one_pulse clk_pulse(.clk( proc_clk ),
.rst( dcm_reset_1 | dcm_reset_2 ),
.btn( GWE_BTN_IN ),
.pulse_out( global_we_pulse ));
wire global_we_switch;
Nbit_reg #(1, 0) gwe_cleaner(.in(SWITCH_IN[7]),
.out( global_we_switch ),
.clk( proc_clk ),
.we( 1'b1 ),
.gwe( 1'b1 ),
.rst( GLOBAL_RST ));
wire i1re, i2re, dre, gwe_out;
lc4_we_gen we_gen(.clk(proc_clk),
.i1re(i1re),
.i2re(i2re),
.dre(dre),
.gwe(gwe_out));
assign GLOBAL_WE = global_we_pulse | (gwe_out & global_we_switch);
wire rst_btn;
Nbit_reg #(1, 0) reset_cleaner(.in( RST_BTN_IN ),
.out( rst_btn ),
.clk( proc_clk ),
.we( 1'b1 ),
.gwe( 1'b1 ),
.rst( dcm_reset_1 | dcm_reset_2 ));
or( GLOBAL_RST, dcm_reset_1, dcm_reset_2, rst_btn );
wire [15:0] imem1_addr, imem2_addr;
wire [15:0] imem1_out, imem2_out;
wire [REG_ADDR_BITS-1:0] dmem_raddr;
wire [REG_ADDR_BITS-1:0] dmem_waddr;
wire [WORD_SIZE-1:0] dmem_in;
wire dmem_we;
wire [WORD_SIZE-1:0] dmem_mout;
lc4_processor #(.WORD_SIZE(WORD_SIZE))
proc_inst(.clk(proc_clk),
.rst(GLOBAL_RST),
.gwe(GLOBAL_WE),
.o_cur_pc(imem1_addr),
.i_cur_insn(imem1_out),
.o_dmem_raddr(dmem_raddr),
.o_dmem_waddr(dmem_waddr),
.i_cur_dmem_data(dmem_mout),
.o_dmem_we(dmem_we),
.o_dmem_towrite(dmem_in),
);
assign imem2_addr = 16'd0;
assign RS232_Tx = led_data[0];
assign LED1 = led_data[1];
assign LED2 = led_data[2];
assign LED3 = led_data[3];
assign LED4 = led_data[4];
lc4_memory
#(.WORD_SIZE(WORD_SIZE))
memory (.idclk(proc_clk),
.i1re(i1re),
.i2re(i2re),
.dre(dre),
.gwe(GLOBAL_WE),
.rst(GLOBAL_RST),
.i1addr(imem1_addr),
.i2addr(imem2_addr),
.i1out(imem1_out),
.i2out(imem2_out),
.draddr(dmem_raddr),
.dwaddr(dmem_waddr),
.din(dmem_in),
.dout(dmem_mout),
.dwe(dmem_we)
);
endmodule | 2 |
139,396 | data/full_repos/permissive/87244188/src/test_lc4_processor_tb.v | 87,244,188 | test_lc4_processor_tb.v | v | 298 | 103 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/87244188/src/test_lc4_processor_tb.v:8: Cannot find include file: src/include/set_testcase.v\n`include "src/include/set_testcase.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87244188/src,data/full_repos/permissive/87244188/src/include/set_testcase.v\n data/full_repos/permissive/87244188/src,data/full_repos/permissive/87244188/src/include/set_testcase.v.v\n data/full_repos/permissive/87244188/src,data/full_repos/permissive/87244188/src/include/set_testcase.v.sv\n src/include/set_testcase.v\n src/include/set_testcase.v.v\n src/include/set_testcase.v.sv\n obj_dir/src/include/set_testcase.v\n obj_dir/src/include/set_testcase.v.v\n obj_dir/src/include/set_testcase.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/87244188/src/test_lc4_processor_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk <= ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/87244188/src/test_lc4_processor_tb.v:133: Define or directive not defined: \'`INPUT_FILE\'\n input_file = $fopen(`INPUT_FILE, "r");\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/87244188/src/test_lc4_processor_tb.v:133: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n input_file = $fopen(`INPUT_FILE, "r");\n ^\n%Error: data/full_repos/permissive/87244188/src/test_lc4_processor_tb.v:135: Define or directive not defined: \'`INPUT_FILE\'\n $display("Error opening file: %s", `INPUT_FILE);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/87244188/src/test_lc4_processor_tb.v:135: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n $display("Error opening file: %s", `INPUT_FILE);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87244188/src/test_lc4_processor_tb.v:149: Unsupported: Ignoring delay on this delayed statement.\n #80\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87244188/src/test_lc4_processor_tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n #32;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87244188/src/test_lc4_processor_tb.v:266: Unsupported: Ignoring delay on this delayed statement.\n #40; \n ^\n%Error: data/full_repos/permissive/87244188/src/test_lc4_processor_tb.v:274: Define or directive not defined: \'`INPUT_FILE\'\n $display("Simulation finished: %d test cases %d errors [%s]", linenum, errors, `INPUT_FILE);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/87244188/src/test_lc4_processor_tb.v:274: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n $display("Simulation finished: %d test cases %d errors [%s]", linenum, errors, `INPUT_FILE);\n ^\n%Error: Exiting due to 7 error(s), 4 warning(s)\n' | 304,660 | module | module test_lc4_processor_tb();
parameter WORD_SIZE = 256;
parameter REG_ADDR_BITS = 5;
parameter INSN = 19;
parameter IADDR = 10;
integer input_file, output_file, errors, linenum;
integer num_cycles;
integer num_exec, num_cache_stall, num_branch_stall, num_load_stall;
integer next_instruction;
reg clk;
reg rst;
wire [INSN:0] cur_insn;
wire [WORD_SIZE-1:0] cur_dmem_data;
wire [IADDR:0] cur_pc;
wire [REG_ADDR_BITS-1:0] dmem_raddr;
wire [REG_ADDR_BITS-1:0] dmem_waddr;
wire [WORD_SIZE-1:0] dmem_tworite;
wire dmem_we;
wire [1:0] test_stall;
wire [IADDR:0] test_pc;
wire [INSN:0] test_insn;
wire test_regfile_we;
wire [REG_ADDR_BITS-1:0] test_wsel;
wire [WORD_SIZE-1:0] test_wdata;
wire test_nzp_we;
wire [2:0] test_nzp_new_bits;
wire test_dmem_we;
wire [REG_ADDR_BITS-1:0] test_dmem_addr;
wire [WORD_SIZE-1:0] test_dmem_data;
reg [IADDR:0] verify_pc;
reg [INSN:0] verify_insn;
reg verify_regfile_we;
reg [REG_ADDR_BITS-1:0] verify_wsel;
reg [WORD_SIZE-1:0] verify_wdata;
reg verify_nzp_we;
reg [2:0] verify_nzp_new_bits;
reg [15:0] file_status;
always #5 clk <= ~clk;
wire i1re, i2re, dre, gwe;
lc4_we_gen we_gen(.clk(clk),
.i1re(i1re),
.i2re(i2re),
.dre(dre),
.gwe(gwe));
lc4_memory #(.WORD_SIZE(WORD_SIZE)) memory (.idclk(clk),
.i1re(i1re),
.i2re(i2re),
.dre(dre),
.gwe(gwe),
.rst(rst),
.i1addr(cur_pc),
.i2addr(16'd0),
.i1out(cur_insn),
.draddr(dmem_raddr),
.dwaddr(dmem_waddr),
.din(dmem_tworite),
.dout(cur_dmem_data),
.dwe(dmem_we)
);
lc4_processor #(.WORD_SIZE(WORD_SIZE)) proc_inst (.clk(clk),
.rst(rst),
.gwe(gwe),
.o_cur_pc(cur_pc),
.i_cur_insn(cur_insn),
.o_dmem_raddr(dmem_raddr),
.o_dmem_waddr(dmem_waddr),
.o_dmem_towrite(dmem_tworite),
.i_cur_dmem_data(cur_dmem_data),
.o_dmem_we(dmem_we),
.test_pc(test_pc),
.test_insn(test_insn),
.test_regfile_we(test_regfile_we),
.test_wsel(test_wsel),
.test_wdata(test_wdata),
.test_nzp_we(test_nzp_we),
.test_nzp_new_bits(test_nzp_new_bits)
);
initial begin
clk = 0;
rst = 1;
linenum = 0;
errors = 0;
num_cycles = 0;
num_exec = 0;
num_cache_stall = 0;
num_branch_stall = 0;
num_load_stall = 0;
file_status = 10;
input_file = $fopen(`INPUT_FILE, "r");
if (input_file == `NULL) begin
$display("Error opening file: %s", `INPUT_FILE);
$finish;
end
`ifdef OUTPUT_FILE
output_file = $fopen(`OUTPUT_FILE, "w");
if (output_file == `NULL) begin
$display("Error opening file: %s", `OUTPUT_FILE);
$finish;
end
`endif
#80
rst = 0;
#32;
while (7 == $fscanf(input_file, "%h %b %h %h %b %b %b"
, verify_pc
, verify_insn
, verify_wdata
, verify_wsel
, verify_regfile_we
, verify_nzp_we
, verify_nzp_new_bits)) begin
linenum = linenum + 1;
if (linenum % 10000 == 0) begin
$display("Instruction number: %d", linenum);
end
next_instruction = 0;
while (!next_instruction) begin
next_instruction = 1;
if (next_instruction) begin
if (verify_pc !== test_pc) begin
$display( "Error at line %d: pc should be %h (but was %h)",
linenum, verify_pc, test_pc);
errors = errors + 1;
$finish;
end
if (verify_insn !== test_insn) begin
$write("Error at line %d: insn should be %h (", linenum, verify_insn);
$write(") but was %h (", test_insn);
$display(")");
errors = errors + 1;
$finish;
end
if (verify_regfile_we !== test_regfile_we) begin
$display( "Error at line %d: regfile_we should be %h (but was %h)",
linenum, verify_regfile_we, test_regfile_we);
errors = errors + 1;
$finish;
end
if (verify_regfile_we && verify_wsel !== test_wsel) begin
$display( "Error at line %d: wsel should be %h (but was %h)",
linenum, verify_wsel, test_wsel);
errors = errors + 1;
$finish;
end
if (verify_regfile_we && verify_wdata !== test_wdata) begin
$display( "Error at line %d: wdata should be %h (but was %h)",
linenum, verify_wdata, test_wdata);
errors = errors + 1;
$finish;
end
if (verify_nzp_we !== test_nzp_we) begin
$display( "Error at line %d: nzp_we should be %h (but was %h)",
linenum, verify_nzp_we, test_nzp_we);
errors = errors + 1;
$finish;
end
if (verify_nzp_we && verify_nzp_new_bits !== test_nzp_new_bits) begin
$display( "Error at line %d: nzp_new_bits should be %h (but was %h)",
linenum, verify_nzp_new_bits, test_nzp_new_bits);
errors = errors + 1;
$finish;
end
if (test_insn === 20'h88000) begin
$display("Hit done instruction");
end
end
num_cycles = num_cycles + 1;
#40;
end
end
if (input_file) $fclose(input_file);
if (output_file) $fclose(output_file);
$display("Simulation finished: %d test cases %d errors [%s]", linenum, errors, `INPUT_FILE);
if (linenum != num_cycles) begin
$display(" Instructions: %d", linenum);
$display(" Total Cycles: %d", num_cycles);
$display(" CPI x 1000: %d", 1000 * num_cycles / linenum);
$display(" IPC x 1000: %d", 1000 * linenum / num_cycles);
$display(" Execution: %d", num_exec);
if (num_cache_stall > 0) begin
$display(" Cache stalls: %d", num_cache_stall);
end
if (num_branch_stall > 0) begin
$display(" Branch stalls: %d", num_branch_stall);
end
if (num_load_stall > 0) begin
$display(" Load stalls: %d", num_load_stall);
end
end
$finish;
end
endmodule | module test_lc4_processor_tb(); |
parameter WORD_SIZE = 256;
parameter REG_ADDR_BITS = 5;
parameter INSN = 19;
parameter IADDR = 10;
integer input_file, output_file, errors, linenum;
integer num_cycles;
integer num_exec, num_cache_stall, num_branch_stall, num_load_stall;
integer next_instruction;
reg clk;
reg rst;
wire [INSN:0] cur_insn;
wire [WORD_SIZE-1:0] cur_dmem_data;
wire [IADDR:0] cur_pc;
wire [REG_ADDR_BITS-1:0] dmem_raddr;
wire [REG_ADDR_BITS-1:0] dmem_waddr;
wire [WORD_SIZE-1:0] dmem_tworite;
wire dmem_we;
wire [1:0] test_stall;
wire [IADDR:0] test_pc;
wire [INSN:0] test_insn;
wire test_regfile_we;
wire [REG_ADDR_BITS-1:0] test_wsel;
wire [WORD_SIZE-1:0] test_wdata;
wire test_nzp_we;
wire [2:0] test_nzp_new_bits;
wire test_dmem_we;
wire [REG_ADDR_BITS-1:0] test_dmem_addr;
wire [WORD_SIZE-1:0] test_dmem_data;
reg [IADDR:0] verify_pc;
reg [INSN:0] verify_insn;
reg verify_regfile_we;
reg [REG_ADDR_BITS-1:0] verify_wsel;
reg [WORD_SIZE-1:0] verify_wdata;
reg verify_nzp_we;
reg [2:0] verify_nzp_new_bits;
reg [15:0] file_status;
always #5 clk <= ~clk;
wire i1re, i2re, dre, gwe;
lc4_we_gen we_gen(.clk(clk),
.i1re(i1re),
.i2re(i2re),
.dre(dre),
.gwe(gwe));
lc4_memory #(.WORD_SIZE(WORD_SIZE)) memory (.idclk(clk),
.i1re(i1re),
.i2re(i2re),
.dre(dre),
.gwe(gwe),
.rst(rst),
.i1addr(cur_pc),
.i2addr(16'd0),
.i1out(cur_insn),
.draddr(dmem_raddr),
.dwaddr(dmem_waddr),
.din(dmem_tworite),
.dout(cur_dmem_data),
.dwe(dmem_we)
);
lc4_processor #(.WORD_SIZE(WORD_SIZE)) proc_inst (.clk(clk),
.rst(rst),
.gwe(gwe),
.o_cur_pc(cur_pc),
.i_cur_insn(cur_insn),
.o_dmem_raddr(dmem_raddr),
.o_dmem_waddr(dmem_waddr),
.o_dmem_towrite(dmem_tworite),
.i_cur_dmem_data(cur_dmem_data),
.o_dmem_we(dmem_we),
.test_pc(test_pc),
.test_insn(test_insn),
.test_regfile_we(test_regfile_we),
.test_wsel(test_wsel),
.test_wdata(test_wdata),
.test_nzp_we(test_nzp_we),
.test_nzp_new_bits(test_nzp_new_bits)
);
initial begin
clk = 0;
rst = 1;
linenum = 0;
errors = 0;
num_cycles = 0;
num_exec = 0;
num_cache_stall = 0;
num_branch_stall = 0;
num_load_stall = 0;
file_status = 10;
input_file = $fopen(`INPUT_FILE, "r");
if (input_file == `NULL) begin
$display("Error opening file: %s", `INPUT_FILE);
$finish;
end
`ifdef OUTPUT_FILE
output_file = $fopen(`OUTPUT_FILE, "w");
if (output_file == `NULL) begin
$display("Error opening file: %s", `OUTPUT_FILE);
$finish;
end
`endif
#80
rst = 0;
#32;
while (7 == $fscanf(input_file, "%h %b %h %h %b %b %b"
, verify_pc
, verify_insn
, verify_wdata
, verify_wsel
, verify_regfile_we
, verify_nzp_we
, verify_nzp_new_bits)) begin
linenum = linenum + 1;
if (linenum % 10000 == 0) begin
$display("Instruction number: %d", linenum);
end
next_instruction = 0;
while (!next_instruction) begin
next_instruction = 1;
if (next_instruction) begin
if (verify_pc !== test_pc) begin
$display( "Error at line %d: pc should be %h (but was %h)",
linenum, verify_pc, test_pc);
errors = errors + 1;
$finish;
end
if (verify_insn !== test_insn) begin
$write("Error at line %d: insn should be %h (", linenum, verify_insn);
$write(") but was %h (", test_insn);
$display(")");
errors = errors + 1;
$finish;
end
if (verify_regfile_we !== test_regfile_we) begin
$display( "Error at line %d: regfile_we should be %h (but was %h)",
linenum, verify_regfile_we, test_regfile_we);
errors = errors + 1;
$finish;
end
if (verify_regfile_we && verify_wsel !== test_wsel) begin
$display( "Error at line %d: wsel should be %h (but was %h)",
linenum, verify_wsel, test_wsel);
errors = errors + 1;
$finish;
end
if (verify_regfile_we && verify_wdata !== test_wdata) begin
$display( "Error at line %d: wdata should be %h (but was %h)",
linenum, verify_wdata, test_wdata);
errors = errors + 1;
$finish;
end
if (verify_nzp_we !== test_nzp_we) begin
$display( "Error at line %d: nzp_we should be %h (but was %h)",
linenum, verify_nzp_we, test_nzp_we);
errors = errors + 1;
$finish;
end
if (verify_nzp_we && verify_nzp_new_bits !== test_nzp_new_bits) begin
$display( "Error at line %d: nzp_new_bits should be %h (but was %h)",
linenum, verify_nzp_new_bits, test_nzp_new_bits);
errors = errors + 1;
$finish;
end
if (test_insn === 20'h88000) begin
$display("Hit done instruction");
end
end
num_cycles = num_cycles + 1;
#40;
end
end
if (input_file) $fclose(input_file);
if (output_file) $fclose(output_file);
$display("Simulation finished: %d test cases %d errors [%s]", linenum, errors, `INPUT_FILE);
if (linenum != num_cycles) begin
$display(" Instructions: %d", linenum);
$display(" Total Cycles: %d", num_cycles);
$display(" CPI x 1000: %d", 1000 * num_cycles / linenum);
$display(" IPC x 1000: %d", 1000 * linenum / num_cycles);
$display(" Execution: %d", num_exec);
if (num_cache_stall > 0) begin
$display(" Cache stalls: %d", num_cache_stall);
end
if (num_branch_stall > 0) begin
$display(" Branch stalls: %d", num_branch_stall);
end
if (num_load_stall > 0) begin
$display(" Load stalls: %d", num_load_stall);
end
end
$finish;
end
endmodule | 2 |
139,401 | data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v | 87,244,188 | fake_pb_kbd.v | v | 107 | 83 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:95: Cannot find file containing module: \'Nbit_reg\'\n Nbit_reg #(2,0) state_reg(.in(next_state), .out(state),\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87244188/src/include,data/full_repos/permissive/87244188/Nbit_reg\n data/full_repos/permissive/87244188/src/include,data/full_repos/permissive/87244188/Nbit_reg.v\n data/full_repos/permissive/87244188/src/include,data/full_repos/permissive/87244188/Nbit_reg.sv\n Nbit_reg\n Nbit_reg.v\n Nbit_reg.sv\n obj_dir/Nbit_reg\n obj_dir/Nbit_reg.v\n obj_dir/Nbit_reg.sv\n%Warning-WIDTH: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:99: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h0\' generates 2 bits.\n : ... In instance fake_pb_kbd.op_c\n assign next_state = (state == 2\'b00 && I == 1\'b1) ? 2\'b01 :\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:100: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h1\' generates 2 bits.\n : ... In instance fake_pb_kbd.op_c\n (state == 2\'b01) ? 2\'b10 :\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:101: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance fake_pb_kbd.op_c\n (state == 2\'b10 && I == 1\'b0) ? 2\'b00 :\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:99: Operator COND expects 3 bits on the Conditional True, but Conditional True\'s CONST \'2\'h1\' generates 2 bits.\n : ... In instance fake_pb_kbd.op_c\n assign next_state = (state == 2\'b00 && I == 1\'b1) ? 2\'b01 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:100: Operator COND expects 3 bits on the Conditional True, but Conditional True\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance fake_pb_kbd.op_c\n (state == 2\'b01) ? 2\'b10 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:101: Operator COND expects 3 bits on the Conditional True, but Conditional True\'s CONST \'2\'h0\' generates 2 bits.\n : ... In instance fake_pb_kbd.op_c\n (state == 2\'b10 && I == 1\'b0) ? 2\'b00 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:101: Operator COND expects 3 bits on the Conditional False, but Conditional False\'s CONST \'2\'h0\' generates 2 bits.\n : ... In instance fake_pb_kbd.op_c\n (state == 2\'b10 && I == 1\'b0) ? 2\'b00 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:104: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance fake_pb_kbd.op_c\n assign O = (state == 2\'b10 && I == 1\'b0) ? 1\'b1 : 1\'b0;\n ^~\n%Error: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:61: Cannot find file containing module: \'Nbit_reg\'\n Nbit_reg #(1,0) kbsr_reg(.in(kbsr_in), .out(kbsr), .clk(proc_clk),\n ^~~~~~~~\n%Error: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:76: Cannot find file containing module: \'Nbit_reg\'\n Nbit_reg #(8,0) kbdr_reg(.in(kbdr_in), .out(kbdr), .clk(proc_clk),\n ^~~~~~~~\n%Error: Exiting due to 3 error(s), 8 warning(s)\n' | 304,667 | module | module fake_pb_kbd(
read_kbsr,
kbsr,
read_kbdr,
kbdr,
proc_clk,
reset,
ZED_PB
);
input read_kbsr;
output kbsr;
input read_kbdr;
output [7:0] kbdr;
input proc_clk;
input reset;
input [4:0] ZED_PB;
wire [4:0] zed_pb_op;
onepulse_fsm op_u(.I(ZED_PB[4]), .O(zed_pb_op[4]), .clk(proc_clk),
.reset(reset));
onepulse_fsm op_l(.I(ZED_PB[3]), .O(zed_pb_op[3]), .clk(proc_clk),
.reset(reset));
onepulse_fsm op_d(.I(ZED_PB[2]), .O(zed_pb_op[2]), .clk(proc_clk),
.reset(reset));
onepulse_fsm op_r(.I(ZED_PB[1]), .O(zed_pb_op[1]), .clk(proc_clk),
.reset(reset));
onepulse_fsm op_c(.I(ZED_PB[0]), .O(zed_pb_op[0]), .clk(proc_clk),
.reset(reset));
wire key_pressed = zed_pb_op[4] | zed_pb_op[3] | zed_pb_op[2] |
zed_pb_op[1] | zed_pb_op[0];
wire kbsr_in;
assign kbsr_in = read_kbdr ? 1'b0 : key_pressed | kbsr;
Nbit_reg #(1,0) kbsr_reg(.in(kbsr_in), .out(kbsr), .clk(proc_clk),
.we(1'b1), .gwe(1'b1), .rst(reset));
wire [7:0] kbdr_in, kbdr;
assign kbdr_in = (key_pressed == 1'b0) ? kbdr :
(zed_pb_op[4]) ? 8'h69 :
(zed_pb_op[3]) ? 8'h6A :
(zed_pb_op[2]) ? 8'h6B :
(zed_pb_op[1]) ? 8'h6C :
(zed_pb_op[0]) ? 8'h20 :
8'h00;
Nbit_reg #(8,0) kbdr_reg(.in(kbdr_in), .out(kbdr), .clk(proc_clk),
.we(1'b1), .gwe(1'b1), .rst(reset));
endmodule | module fake_pb_kbd(
read_kbsr,
kbsr,
read_kbdr,
kbdr,
proc_clk,
reset,
ZED_PB
); |
input read_kbsr;
output kbsr;
input read_kbdr;
output [7:0] kbdr;
input proc_clk;
input reset;
input [4:0] ZED_PB;
wire [4:0] zed_pb_op;
onepulse_fsm op_u(.I(ZED_PB[4]), .O(zed_pb_op[4]), .clk(proc_clk),
.reset(reset));
onepulse_fsm op_l(.I(ZED_PB[3]), .O(zed_pb_op[3]), .clk(proc_clk),
.reset(reset));
onepulse_fsm op_d(.I(ZED_PB[2]), .O(zed_pb_op[2]), .clk(proc_clk),
.reset(reset));
onepulse_fsm op_r(.I(ZED_PB[1]), .O(zed_pb_op[1]), .clk(proc_clk),
.reset(reset));
onepulse_fsm op_c(.I(ZED_PB[0]), .O(zed_pb_op[0]), .clk(proc_clk),
.reset(reset));
wire key_pressed = zed_pb_op[4] | zed_pb_op[3] | zed_pb_op[2] |
zed_pb_op[1] | zed_pb_op[0];
wire kbsr_in;
assign kbsr_in = read_kbdr ? 1'b0 : key_pressed | kbsr;
Nbit_reg #(1,0) kbsr_reg(.in(kbsr_in), .out(kbsr), .clk(proc_clk),
.we(1'b1), .gwe(1'b1), .rst(reset));
wire [7:0] kbdr_in, kbdr;
assign kbdr_in = (key_pressed == 1'b0) ? kbdr :
(zed_pb_op[4]) ? 8'h69 :
(zed_pb_op[3]) ? 8'h6A :
(zed_pb_op[2]) ? 8'h6B :
(zed_pb_op[1]) ? 8'h6C :
(zed_pb_op[0]) ? 8'h20 :
8'h00;
Nbit_reg #(8,0) kbdr_reg(.in(kbdr_in), .out(kbdr), .clk(proc_clk),
.we(1'b1), .gwe(1'b1), .rst(reset));
endmodule | 2 |
139,402 | data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v | 87,244,188 | fake_pb_kbd.v | v | 107 | 83 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:95: Cannot find file containing module: \'Nbit_reg\'\n Nbit_reg #(2,0) state_reg(.in(next_state), .out(state),\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87244188/src/include,data/full_repos/permissive/87244188/Nbit_reg\n data/full_repos/permissive/87244188/src/include,data/full_repos/permissive/87244188/Nbit_reg.v\n data/full_repos/permissive/87244188/src/include,data/full_repos/permissive/87244188/Nbit_reg.sv\n Nbit_reg\n Nbit_reg.v\n Nbit_reg.sv\n obj_dir/Nbit_reg\n obj_dir/Nbit_reg.v\n obj_dir/Nbit_reg.sv\n%Warning-WIDTH: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:99: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h0\' generates 2 bits.\n : ... In instance fake_pb_kbd.op_c\n assign next_state = (state == 2\'b00 && I == 1\'b1) ? 2\'b01 :\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:100: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h1\' generates 2 bits.\n : ... In instance fake_pb_kbd.op_c\n (state == 2\'b01) ? 2\'b10 :\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:101: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance fake_pb_kbd.op_c\n (state == 2\'b10 && I == 1\'b0) ? 2\'b00 :\n ^~\n%Warning-WIDTH: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:99: Operator COND expects 3 bits on the Conditional True, but Conditional True\'s CONST \'2\'h1\' generates 2 bits.\n : ... In instance fake_pb_kbd.op_c\n assign next_state = (state == 2\'b00 && I == 1\'b1) ? 2\'b01 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:100: Operator COND expects 3 bits on the Conditional True, but Conditional True\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance fake_pb_kbd.op_c\n (state == 2\'b01) ? 2\'b10 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:101: Operator COND expects 3 bits on the Conditional True, but Conditional True\'s CONST \'2\'h0\' generates 2 bits.\n : ... In instance fake_pb_kbd.op_c\n (state == 2\'b10 && I == 1\'b0) ? 2\'b00 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:101: Operator COND expects 3 bits on the Conditional False, but Conditional False\'s CONST \'2\'h0\' generates 2 bits.\n : ... In instance fake_pb_kbd.op_c\n (state == 2\'b10 && I == 1\'b0) ? 2\'b00 :\n ^\n%Warning-WIDTH: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:104: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance fake_pb_kbd.op_c\n assign O = (state == 2\'b10 && I == 1\'b0) ? 1\'b1 : 1\'b0;\n ^~\n%Error: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:61: Cannot find file containing module: \'Nbit_reg\'\n Nbit_reg #(1,0) kbsr_reg(.in(kbsr_in), .out(kbsr), .clk(proc_clk),\n ^~~~~~~~\n%Error: data/full_repos/permissive/87244188/src/include/fake_pb_kbd.v:76: Cannot find file containing module: \'Nbit_reg\'\n Nbit_reg #(8,0) kbdr_reg(.in(kbdr_in), .out(kbdr), .clk(proc_clk),\n ^~~~~~~~\n%Error: Exiting due to 3 error(s), 8 warning(s)\n' | 304,667 | module | module onepulse_fsm(
I,
O,
clk,
reset
);
input I;
output O;
input clk;
input reset;
wire [2:0] state, next_state;
Nbit_reg #(2,0) state_reg(.in(next_state), .out(state),
.clk(clk), .we(1'b1),
.gwe(1'b1), .rst(reset));
assign next_state = (state == 2'b00 && I == 1'b1) ? 2'b01 :
(state == 2'b01) ? 2'b10 :
(state == 2'b10 && I == 1'b0) ? 2'b00 :
2'b00;
assign O = (state == 2'b10 && I == 1'b0) ? 1'b1 : 1'b0;
endmodule | module onepulse_fsm(
I,
O,
clk,
reset
); |
input I;
output O;
input clk;
input reset;
wire [2:0] state, next_state;
Nbit_reg #(2,0) state_reg(.in(next_state), .out(state),
.clk(clk), .we(1'b1),
.gwe(1'b1), .rst(reset));
assign next_state = (state == 2'b00 && I == 1'b1) ? 2'b01 :
(state == 2'b01) ? 2'b10 :
(state == 2'b10 && I == 1'b0) ? 2'b00 :
2'b00;
assign O = (state == 2'b10 && I == 1'b0) ? 1'b1 : 1'b0;
endmodule | 2 |
139,404 | data/full_repos/permissive/87244188/src/include/one_pulse.v | 87,244,188 | one_pulse.v | v | 33 | 75 | [] | [] | [] | [(16, 30)] | null | null | 1: b"%Error: data/full_repos/permissive/87244188/src/include/one_pulse.v:23: Cannot find file containing module: 'Nbit_reg'\n Nbit_reg #(8, 0) pulse_reg (.clk(clk), .rst(rst), .we(1'b1), .gwe(1'b1),\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87244188/src/include,data/full_repos/permissive/87244188/Nbit_reg\n data/full_repos/permissive/87244188/src/include,data/full_repos/permissive/87244188/Nbit_reg.v\n data/full_repos/permissive/87244188/src/include,data/full_repos/permissive/87244188/Nbit_reg.sv\n Nbit_reg\n Nbit_reg.v\n Nbit_reg.sv\n obj_dir/Nbit_reg\n obj_dir/Nbit_reg.v\n obj_dir/Nbit_reg.sv\n%Error: Exiting due to 1 error(s)\n" | 304,670 | module | module one_pulse(clk, rst, btn, pulse_out);
input clk, rst, btn;
output pulse_out;
wire [7:0] counter, counter_in;
Nbit_reg #(8, 0) pulse_reg (.clk(clk), .rst(rst), .we(1'b1), .gwe(1'b1),
.in(counter_in), .out(counter));
assign counter_in = (btn) ? 8'd255 :
(counter != 8'd0) ? counter - 8'd1 : counter;
assign pulse_out = ~btn & (counter == 8'd1);
endmodule | module one_pulse(clk, rst, btn, pulse_out); |
input clk, rst, btn;
output pulse_out;
wire [7:0] counter, counter_in;
Nbit_reg #(8, 0) pulse_reg (.clk(clk), .rst(rst), .we(1'b1), .gwe(1'b1),
.in(counter_in), .out(counter));
assign counter_in = (btn) ? 8'd255 :
(counter != 8'd0) ? counter - 8'd1 : counter;
assign pulse_out = ~btn & (counter == 8'd1);
endmodule | 2 |
139,406 | data/full_repos/permissive/87244188/src/include/timer.v | 87,244,188 | timer.v | v | 45 | 124 | [] | [] | [] | [(4, 44)] | null | null | 1: b"%Error: data/full_repos/permissive/87244188/src/include/timer.v:23: Cannot find file containing module: 'Nbit_reg'\n Nbit_reg #(16, 0) interval_reg (.in(interval_in), .out(interval), .we(write_interval), .clk(CLK), .gwe(GWE), .rst(RST));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87244188/src/include,data/full_repos/permissive/87244188/Nbit_reg\n data/full_repos/permissive/87244188/src/include,data/full_repos/permissive/87244188/Nbit_reg.v\n data/full_repos/permissive/87244188/src/include,data/full_repos/permissive/87244188/Nbit_reg.sv\n Nbit_reg\n Nbit_reg.v\n Nbit_reg.sv\n obj_dir/Nbit_reg\n obj_dir/Nbit_reg.v\n obj_dir/Nbit_reg.sv\n%Error: data/full_repos/permissive/87244188/src/include/timer.v:26: Cannot find file containing module: 'Nbit_reg'\n Nbit_reg #(32, 0) counter_reg (.in(counter_in), .out(counter), .we( 1'b1 ), .clk(CLK), .gwe( GWE ), .rst(RST));\n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 304,674 | module | module timer_device ( write_interval,
interval_in,
read_status,
status_out,
GWE,
RST,
CLK);
input write_interval;
input [15:0] interval_in;
input read_status;
output status_out;
input GWE, RST, CLK;
wire [15:0] interval;
wire [31:0] counter, counter_in;
Nbit_reg #(16, 0) interval_reg (.in(interval_in), .out(interval), .we(write_interval), .clk(CLK), .gwe(GWE), .rst(RST));
Nbit_reg #(32, 0) counter_reg (.in(counter_in), .out(counter), .we( 1'b1 ), .clk(CLK), .gwe( GWE ), .rst(RST));
assign counter_in =
(counter[31] == 1'b0) ? counter - 1 :
(counter[31] == 1'b1 & read_status) ? {{3{1'b0}}, interval, {13{1'b0}}} :
counter;
assign status_out = counter[31];
endmodule | module timer_device ( write_interval,
interval_in,
read_status,
status_out,
GWE,
RST,
CLK); |
input write_interval;
input [15:0] interval_in;
input read_status;
output status_out;
input GWE, RST, CLK;
wire [15:0] interval;
wire [31:0] counter, counter_in;
Nbit_reg #(16, 0) interval_reg (.in(interval_in), .out(interval), .we(write_interval), .clk(CLK), .gwe(GWE), .rst(RST));
Nbit_reg #(32, 0) counter_reg (.in(counter_in), .out(counter), .we( 1'b1 ), .clk(CLK), .gwe( GWE ), .rst(RST));
assign counter_in =
(counter[31] == 1'b0) ? counter - 1 :
(counter[31] == 1'b1 & read_status) ? {{3{1'b0}}, interval, {13{1'b0}}} :
counter;
assign status_out = counter[31];
endmodule | 2 |
139,407 | data/full_repos/permissive/87244188/src/include/vga_controller.v | 87,244,188 | vga_controller.v | v | 100 | 80 | [] | [] | [] | [(32, 97)] | null | null | 1: b"%Error: data/full_repos/permissive/87244188/src/include/vga_controller.v:68: Cannot find file containing module: 'video_out'\n video_out v_out_inst(\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87244188/src/include,data/full_repos/permissive/87244188/video_out\n data/full_repos/permissive/87244188/src/include,data/full_repos/permissive/87244188/video_out.v\n data/full_repos/permissive/87244188/src/include,data/full_repos/permissive/87244188/video_out.sv\n video_out\n video_out.v\n video_out.sv\n obj_dir/video_out\n obj_dir/video_out.v\n obj_dir/video_out.sv\n%Error: data/full_repos/permissive/87244188/src/include/vga_controller.v:87: Cannot find file containing module: 'svga_timing_generation'\n svga_timing_generation svga_t_g(\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 304,675 | module | module vga_controller(
PIXEL_CLK,
RESET,
VGA_HSYNCH,
VGA_VSYNCH,
VGA_OUT_RED,
VGA_OUT_GREEN,
VGA_OUT_BLUE,
VGA_ADDR,
VGA_DATA
);
input PIXEL_CLK;
input RESET;
output VGA_HSYNCH;
output VGA_VSYNCH;
output [3:0] VGA_OUT_RED;
output [3:0] VGA_OUT_GREEN;
output [3:0] VGA_OUT_BLUE;
output [13:0] VGA_ADDR;
input [14:0] VGA_DATA;
wire h_synch_delay;
wire v_synch_delay;
wire blank;
wire [10:0] pixel_count;
wire [9:0] line_count;
video_out v_out_inst(
.PIXEL_CLOCK(PIXEL_CLK),
.RESET(RESET),
.VGA_HSYNCH(VGA_HSYNCH),
.VGA_VSYNCH(VGA_VSYNCH),
.VGA_OUT_RED(VGA_OUT_RED),
.VGA_OUT_GREEN(VGA_OUT_GREEN),
.VGA_OUT_BLUE(VGA_OUT_BLUE),
.H_SYNCH_DELAY(h_synch_delay),
.V_SYNCH_DELAY(v_synch_delay),
.BLANK(blank),
.PIXEL_COUNT(pixel_count),
.LINE_COUNT(line_count),
.VGA_ADDR(VGA_ADDR),
.VGA_DATA(VGA_DATA[14:0])
);
svga_timing_generation svga_t_g(
.PIXEL_CLOCK(PIXEL_CLK),
.RESET(RESET),
.H_SYNCH_DELAY(h_synch_delay),
.V_SYNCH_DELAY(v_synch_delay),
.BLANK(blank),
.PIXEL_COUNT(pixel_count),
.LINE_COUNT(line_count)
);
endmodule | module vga_controller(
PIXEL_CLK,
RESET,
VGA_HSYNCH,
VGA_VSYNCH,
VGA_OUT_RED,
VGA_OUT_GREEN,
VGA_OUT_BLUE,
VGA_ADDR,
VGA_DATA
); |
input PIXEL_CLK;
input RESET;
output VGA_HSYNCH;
output VGA_VSYNCH;
output [3:0] VGA_OUT_RED;
output [3:0] VGA_OUT_GREEN;
output [3:0] VGA_OUT_BLUE;
output [13:0] VGA_ADDR;
input [14:0] VGA_DATA;
wire h_synch_delay;
wire v_synch_delay;
wire blank;
wire [10:0] pixel_count;
wire [9:0] line_count;
video_out v_out_inst(
.PIXEL_CLOCK(PIXEL_CLK),
.RESET(RESET),
.VGA_HSYNCH(VGA_HSYNCH),
.VGA_VSYNCH(VGA_VSYNCH),
.VGA_OUT_RED(VGA_OUT_RED),
.VGA_OUT_GREEN(VGA_OUT_GREEN),
.VGA_OUT_BLUE(VGA_OUT_BLUE),
.H_SYNCH_DELAY(h_synch_delay),
.V_SYNCH_DELAY(v_synch_delay),
.BLANK(blank),
.PIXEL_COUNT(pixel_count),
.LINE_COUNT(line_count),
.VGA_ADDR(VGA_ADDR),
.VGA_DATA(VGA_DATA[14:0])
);
svga_timing_generation svga_t_g(
.PIXEL_CLOCK(PIXEL_CLK),
.RESET(RESET),
.H_SYNCH_DELAY(h_synch_delay),
.V_SYNCH_DELAY(v_synch_delay),
.BLANK(blank),
.PIXEL_COUNT(pixel_count),
.LINE_COUNT(line_count)
);
endmodule | 2 |
139,408 | data/full_repos/permissive/87371240/SimulatorVerilog.sv | 87,371,240 | SimulatorVerilog.sv | sv | 105 | 50 | [] | [] | [] | null | line:4: before: "real" | null | 1: b"%Error: data/full_repos/permissive/87371240/SimulatorVerilog.sv:10: syntax error, unexpected real, expecting IDENTIFIER or '=' or do or final\n reg real alpha [0:15];\n ^~~~\n%Error: data/full_repos/permissive/87371240/SimulatorVerilog.sv:14: syntax error, unexpected real, expecting IDENTIFIER or '=' or do or final\n reg real AG_CONST, AG;\n ^~~~\n%Error: Exiting due to 2 error(s)\n" | 304,678 | module | module cordic(
input real z,
input [2:0] dummy,
output sin,
output cos
);
reg [31:0] x, y, newx;
reg real alpha [0:15];
reg real powers [0:16];
reg real x_out, y_out, e_x, currangle;
integer i;
reg real AG_CONST, AG;
initial begin
AG_CONST = 1.20;
AG = 2458;
x = AG;
y = 0;
alpha[0] = 0;
alpha[1] = 31.47292;
alpha[2] = 14.63407;
alpha[3] = 7.19962;
alpha[4] = 3.58565;
alpha[5] = 1.79107;
alpha[6] = 0.89531;
alpha[7] = 0.44763;
alpha[8] = 0.22381;
alpha[9] = 0.11190;
alpha[10] = 0.05595;
alpha[11] = 0.02797;
alpha[12] = 0.01398;
alpha[13] = 0.00699;
alpha[14] = 0.00349;
alpha[15] = 0.00174;
powers[0] = 0.00048828125;
powers[1] = 0.0009765625;
powers[2] = 0.001953125;
powers[3] = 0.00390625;
powers[4] = 0.0078125;
powers[5] = 0.015625;
powers[6] = 0.03125;
powers[7] = 0.0625;
powers[8] = 0.125;
powers[9] = 0.25;
powers[10] = 0.5;
powers[11] = 1.0;
powers[12] = 2.0;
powers[13] = 4.0;
powers[14] = 8.0;
powers[15] = 16.0;
powers[16] = 32.0;
currangle = 30.0;
$display("%f\t%f\n",currangle, z);
$display("DUMMY %b", dummy);
for (i = 1; i < 15; i = i + 1) begin
if (currangle > 0) begin
while(currangle >= alpha[i]) begin
newx = x + (y>>i);
y = y+ (x >> i);
x = newx;
currangle = currangle - alpha[i];
end
end else begin
while(currangle <= alpha[i]) begin
newx = x - (y>>i);
y = y- (x >> i);
x = newx;
currangle = currangle + alpha[i];
end
end
end
$display("x %f\n", x/2048.0);
$display("y %f\n", y/2048.0);
x_out = 0;
y_out = 0;
for (i = 0; i < 17; i = i + 1) begin
x_out = (x[i]) ? x_out + powers[i] : x_out;
y_out = (y[i]) ? y_out + powers[i] : y_out;
end
e_x = x_out+y_out;
$display("x %f\n", x_out);
$display("y %f\n", y_out);
$display("e %f\n", e_x);
end
assign sin = y_out;
assign cos = x_out;
endmodule | module cordic(
input real z,
input [2:0] dummy,
output sin,
output cos
); |
reg [31:0] x, y, newx;
reg real alpha [0:15];
reg real powers [0:16];
reg real x_out, y_out, e_x, currangle;
integer i;
reg real AG_CONST, AG;
initial begin
AG_CONST = 1.20;
AG = 2458;
x = AG;
y = 0;
alpha[0] = 0;
alpha[1] = 31.47292;
alpha[2] = 14.63407;
alpha[3] = 7.19962;
alpha[4] = 3.58565;
alpha[5] = 1.79107;
alpha[6] = 0.89531;
alpha[7] = 0.44763;
alpha[8] = 0.22381;
alpha[9] = 0.11190;
alpha[10] = 0.05595;
alpha[11] = 0.02797;
alpha[12] = 0.01398;
alpha[13] = 0.00699;
alpha[14] = 0.00349;
alpha[15] = 0.00174;
powers[0] = 0.00048828125;
powers[1] = 0.0009765625;
powers[2] = 0.001953125;
powers[3] = 0.00390625;
powers[4] = 0.0078125;
powers[5] = 0.015625;
powers[6] = 0.03125;
powers[7] = 0.0625;
powers[8] = 0.125;
powers[9] = 0.25;
powers[10] = 0.5;
powers[11] = 1.0;
powers[12] = 2.0;
powers[13] = 4.0;
powers[14] = 8.0;
powers[15] = 16.0;
powers[16] = 32.0;
currangle = 30.0;
$display("%f\t%f\n",currangle, z);
$display("DUMMY %b", dummy);
for (i = 1; i < 15; i = i + 1) begin
if (currangle > 0) begin
while(currangle >= alpha[i]) begin
newx = x + (y>>i);
y = y+ (x >> i);
x = newx;
currangle = currangle - alpha[i];
end
end else begin
while(currangle <= alpha[i]) begin
newx = x - (y>>i);
y = y- (x >> i);
x = newx;
currangle = currangle + alpha[i];
end
end
end
$display("x %f\n", x/2048.0);
$display("y %f\n", y/2048.0);
x_out = 0;
y_out = 0;
for (i = 0; i < 17; i = i + 1) begin
x_out = (x[i]) ? x_out + powers[i] : x_out;
y_out = (y[i]) ? y_out + powers[i] : y_out;
end
e_x = x_out+y_out;
$display("x %f\n", x_out);
$display("y %f\n", y_out);
$display("e %f\n", e_x);
end
assign sin = y_out;
assign cos = x_out;
endmodule | 1 |
139,410 | data/full_repos/permissive/87371240/cordic_alg/cordic_LUT.v | 87,371,240 | cordic_LUT.v | v | 60 | 83 | [] | [] | [] | null | line:24: before: "reg" | null | 1: b"%Error: data/full_repos/permissive/87371240/cordic_alg/cordic_LUT.v:24: syntax error, unexpected reg, expecting IDENTIFIER or '[' or do or final\n output [32:0] reg k_out,\n ^~~\n%Error: data/full_repos/permissive/87371240/cordic_alg/cordic_LUT.v:25: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n output [32:0] reg e_k_out,\n ^~~~~~\n%Error: data/full_repos/permissive/87371240/cordic_alg/cordic_LUT.v:26: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n output [4:0] reg addr_out,\n ^~~~~~\n%Error: data/full_repos/permissive/87371240/cordic_alg/cordic_LUT.v:27: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n input CE\n ^~~~~\n%Error: data/full_repos/permissive/87371240/cordic_alg/cordic_LUT.v:35: syntax error, unexpected initial\n initial begin\n ^~~~~~~\n%Error: Exiting due to 5 error(s)\n" | 304,680 | module | module cordic_LUT(
input [32:0] x_in,
input [4:0] addr,
output [32:0] reg k_out,
output [32:0] reg e_k_out,
output [4:0] reg addr_out,
input CE
);
reg [31:0] LUT_k [0:31];
reg [31:0] LUT_e_k [0:31];
parameter LAST = 32;
initial begin
$readmemh("", LUT_k);
$readmemh("", LUT_e_k);
end
always @ (posedge CE) begin
if (addr == LAST) begin
k_out <= LUT_k[addr];
e_k_out <= LUT_e_k[addr];
addr_out <= addr;
end else begin
if (LUT_k[addr] <= x_in) begin
k_out <= LUT_k[addr];
e_k_out <= LUT_e_k[addr];
addr_out <= addr;
end else
addr <= addr + 1;
end
end
end
endmodule | module cordic_LUT(
input [32:0] x_in,
input [4:0] addr,
output [32:0] reg k_out,
output [32:0] reg e_k_out,
output [4:0] reg addr_out,
input CE
); |
reg [31:0] LUT_k [0:31];
reg [31:0] LUT_e_k [0:31];
parameter LAST = 32;
initial begin
$readmemh("", LUT_k);
$readmemh("", LUT_e_k);
end
always @ (posedge CE) begin
if (addr == LAST) begin
k_out <= LUT_k[addr];
e_k_out <= LUT_e_k[addr];
addr_out <= addr;
end else begin
if (LUT_k[addr] <= x_in) begin
k_out <= LUT_k[addr];
e_k_out <= LUT_e_k[addr];
addr_out <= addr;
end else
addr <= addr + 1;
end
end
end
endmodule | 1 |
139,411 | data/full_repos/permissive/87632970/FlipFlop.v | 87,632,970 | FlipFlop.v | v | 42 | 83 | [] | [] | [] | [(22, 41)] | null | data/verilator_xmls/0204d43f-a6ee-4311-a36d-f6dd900192cc.xml | null | 304,771 | module | module FF(
input clk,
input D,
output reg Q,
output wire Qbar
);
parameter init = 0;
initial
Q = init;
assign Qbar = ~Q;
always@(posedge clk)
begin
Q = D;
end
endmodule | module FF(
input clk,
input D,
output reg Q,
output wire Qbar
); |
parameter init = 0;
initial
Q = init;
assign Qbar = ~Q;
always@(posedge clk)
begin
Q = D;
end
endmodule | 0 |
139,412 | data/full_repos/permissive/87632970/Generation.v | 87,632,970 | Generation.v | v | 53 | 83 | [] | [] | [] | [(21, 52)] | null | null | 1: b"%Error: data/full_repos/permissive/87632970/Generation.v:34: Cannot find file containing module: 'FF'\nFF #(key[0]) FF0(clk,D[0],Q[0],Qbar[0]);\n^~\n ... Looked in:\n data/full_repos/permissive/87632970,data/full_repos/permissive/87632970/FF\n data/full_repos/permissive/87632970,data/full_repos/permissive/87632970/FF.v\n data/full_repos/permissive/87632970,data/full_repos/permissive/87632970/FF.sv\n FF\n FF.v\n FF.sv\n obj_dir/FF\n obj_dir/FF.v\n obj_dir/FF.sv\n%Error: data/full_repos/permissive/87632970/Generation.v:35: Cannot find file containing module: 'FF'\nFF #(key[1]) FF1(clk,D[1],Q[1],Qbar[1]);\n^~\n%Error: data/full_repos/permissive/87632970/Generation.v:36: Cannot find file containing module: 'FF'\nFF #(key[2]) FF2(clk,D[2],Q[2],Qbar[2]);\n^~\n%Error: data/full_repos/permissive/87632970/Generation.v:37: Cannot find file containing module: 'FF'\nFF #(key[3]) FF3(clk,D[3],Q[3],Qbar[3]);\n^~\n%Error: data/full_repos/permissive/87632970/Generation.v:38: Cannot find file containing module: 'FF'\nFF #(key[4]) FF4(clk,D[4],Q[4],Qbar[4]);\n^~\n%Error: data/full_repos/permissive/87632970/Generation.v:39: Cannot find file containing module: 'FF'\nFF #(key[5]) FF5(clk,D[5],Q[5],Qbar[5]);\n^~\n%Error: data/full_repos/permissive/87632970/Generation.v:40: Cannot find file containing module: 'FF'\nFF #(key[6]) FF6(clk,D[6],Q[6],Qbar[6]);\n^~\n%Error: data/full_repos/permissive/87632970/Generation.v:41: Cannot find file containing module: 'FF'\nFF #(key[7]) FF7(clk,D[7],Q[7],Qbar[7]);\n^~\n%Error: Exiting due to 8 error(s)\n" | 304,772 | module | module Generation(
input clk,
output [1:0] WM_Data
);
parameter key = 8'b01101010;
wire [7:0] Q, Qbar;
wire [7:0] D;
assign WM_Data[1] = Q[1]^Q[0];
assign WM_Data[0] = (WM_Data[1]==1)? 0 : Q[0];
FF #(key[0]) FF0(clk,D[0],Q[0],Qbar[0]);
FF #(key[1]) FF1(clk,D[1],Q[1],Qbar[1]);
FF #(key[2]) FF2(clk,D[2],Q[2],Qbar[2]);
FF #(key[3]) FF3(clk,D[3],Q[3],Qbar[3]);
FF #(key[4]) FF4(clk,D[4],Q[4],Qbar[4]);
FF #(key[5]) FF5(clk,D[5],Q[5],Qbar[5]);
FF #(key[6]) FF6(clk,D[6],Q[6],Qbar[6]);
FF #(key[7]) FF7(clk,D[7],Q[7],Qbar[7]);
assign D[0]=Q[7]^(~((D[4]|D[5]|D[6]|D[7])|(D[1]|D[2]|D[3])));
assign D[1]=Q[0];
assign D[2]=Q[1]^D[0];
assign D[3]=Q[2]^D[0];
assign D[4]=Q[3]^D[0];
assign D[5]=Q[4];
assign D[6]=Q[5];
assign D[7]=Q[6];
endmodule | module Generation(
input clk,
output [1:0] WM_Data
); |
parameter key = 8'b01101010;
wire [7:0] Q, Qbar;
wire [7:0] D;
assign WM_Data[1] = Q[1]^Q[0];
assign WM_Data[0] = (WM_Data[1]==1)? 0 : Q[0];
FF #(key[0]) FF0(clk,D[0],Q[0],Qbar[0]);
FF #(key[1]) FF1(clk,D[1],Q[1],Qbar[1]);
FF #(key[2]) FF2(clk,D[2],Q[2],Qbar[2]);
FF #(key[3]) FF3(clk,D[3],Q[3],Qbar[3]);
FF #(key[4]) FF4(clk,D[4],Q[4],Qbar[4]);
FF #(key[5]) FF5(clk,D[5],Q[5],Qbar[5]);
FF #(key[6]) FF6(clk,D[6],Q[6],Qbar[6]);
FF #(key[7]) FF7(clk,D[7],Q[7],Qbar[7]);
assign D[0]=Q[7]^(~((D[4]|D[5]|D[6]|D[7])|(D[1]|D[2]|D[3])));
assign D[1]=Q[0];
assign D[2]=Q[1]^D[0];
assign D[3]=Q[2]^D[0];
assign D[4]=Q[3]^D[0];
assign D[5]=Q[4];
assign D[6]=Q[5];
assign D[7]=Q[6];
endmodule | 0 |
139,413 | data/full_repos/permissive/87632970/Insertion.v | 87,632,970 | Insertion.v | v | 53 | 83 | [] | [] | [] | [(22, 52)] | null | null | 1: b"%Error: data/full_repos/permissive/87632970/Insertion.v:36: Cannot find file containing module: 'adder8'\nadder8 A1(.a(Data2), .b(Data4), .add(1), .s(Adder1));\n^~~~~~\n ... Looked in:\n data/full_repos/permissive/87632970,data/full_repos/permissive/87632970/adder8\n data/full_repos/permissive/87632970,data/full_repos/permissive/87632970/adder8.v\n data/full_repos/permissive/87632970,data/full_repos/permissive/87632970/adder8.sv\n adder8\n adder8.v\n adder8.sv\n obj_dir/adder8\n obj_dir/adder8.v\n obj_dir/adder8.sv\n%Error: data/full_repos/permissive/87632970/Insertion.v:39: Cannot find file containing module: 'adder8'\nadder8 A2(.a(Data3), .b(shiftedAdder1), .add(1), .s(Adder2));\n^~~~~~\n%Error: data/full_repos/permissive/87632970/Insertion.v:42: Cannot find file containing module: 'Amul'\nAmul mul2(.a(shiftedAdder2), .clk(clk), .p(m2));\n^~~~\n%Error: data/full_repos/permissive/87632970/Insertion.v:43: Cannot find file containing module: 'Cmul'\nCmul mul1(.a(Data1), .p(m11));\n^~~~\n%Error: data/full_repos/permissive/87632970/Insertion.v:44: Cannot find file containing module: 'Bmul'\nBmul mul3(.a(Data1), .p(m12));\n^~~~\n%Error: data/full_repos/permissive/87632970/Insertion.v:48: Cannot find file containing module: 'adder8'\nadder8 A3(.a(m1), .b(m2), .add(1), .s(Adder));\n^~~~~~\n%Error: Exiting due to 6 error(s)\n" | 304,773 | module | module Insertion(
input clk,
input [7:0]Data1,
input [7:0]Data2,
input [7:0]Data3,
input [7:0]Data4,
input [1:0]WM_Data,
output [7:0]WM_IM_Data
);
wire [8:0] Adder1, Adder2, Adder;
wire [7:0] m1, m11, m2, m12;
reg [7:0] temp;
adder8 A1(.a(Data2), .b(Data4), .add(1), .s(Adder1));
wire [7:0] shiftedAdder1 = Adder1[8:1];
adder8 A2(.a(Data3), .b(shiftedAdder1), .add(1), .s(Adder2));
wire [7:0] shiftedAdder2 = Adder2[8:1];
Amul mul2(.a(shiftedAdder2), .clk(clk), .p(m2));
Cmul mul1(.a(Data1), .p(m11));
Bmul mul3(.a(Data1), .p(m12));
assign m1 = (WM_Data == 2'b01)? m11 : ((WM_Data == 2'b10)? m12 : 0);
adder8 A3(.a(m1), .b(m2), .add(1), .s(Adder));
assign WM_IM_Data = (WM_Data== 2'b00 | WM_Data == 2'b11)? Data1 : Adder[7:0];
endmodule | module Insertion(
input clk,
input [7:0]Data1,
input [7:0]Data2,
input [7:0]Data3,
input [7:0]Data4,
input [1:0]WM_Data,
output [7:0]WM_IM_Data
); |
wire [8:0] Adder1, Adder2, Adder;
wire [7:0] m1, m11, m2, m12;
reg [7:0] temp;
adder8 A1(.a(Data2), .b(Data4), .add(1), .s(Adder1));
wire [7:0] shiftedAdder1 = Adder1[8:1];
adder8 A2(.a(Data3), .b(shiftedAdder1), .add(1), .s(Adder2));
wire [7:0] shiftedAdder2 = Adder2[8:1];
Amul mul2(.a(shiftedAdder2), .clk(clk), .p(m2));
Cmul mul1(.a(Data1), .p(m11));
Bmul mul3(.a(Data1), .p(m12));
assign m1 = (WM_Data == 2'b01)? m11 : ((WM_Data == 2'b10)? m12 : 0);
adder8 A3(.a(m1), .b(m2), .add(1), .s(Adder));
assign WM_IM_Data = (WM_Data== 2'b00 | WM_Data == 2'b11)? Data1 : Adder[7:0];
endmodule | 0 |
139,414 | data/full_repos/permissive/87632970/main.v | 87,632,970 | main.v | v | 38 | 84 | [] | [] | [] | [(22, 37)] | null | null | 1: b"%Error: data/full_repos/permissive/87632970/main.v:33: Cannot find file containing module: 'Generation'\nGeneration G( .clk(clk), .WM_Data(WM_Data));\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87632970,data/full_repos/permissive/87632970/Generation\n data/full_repos/permissive/87632970,data/full_repos/permissive/87632970/Generation.v\n data/full_repos/permissive/87632970,data/full_repos/permissive/87632970/Generation.sv\n Generation\n Generation.v\n Generation.sv\n obj_dir/Generation\n obj_dir/Generation.v\n obj_dir/Generation.sv\n%Error: data/full_repos/permissive/87632970/main.v:34: Cannot find file containing module: 'Insertion'\nInsertion I( .clk(clk), .Data1(Data1), .Data2(Data2), .Data3(Data3), .Data4(Data4),\n^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 304,774 | module | module main(
input clk,
input [7:0] Data1,
input [7:0] Data2,
input [7:0] Data3,
input [7:0] Data4,
output [7:0] IM_Data_out
);
wire [1:0] WM_Data;
Generation G( .clk(clk), .WM_Data(WM_Data));
Insertion I( .clk(clk), .Data1(Data1), .Data2(Data2), .Data3(Data3), .Data4(Data4),
.WM_Data(WM_Data), .WM_IM_Data(IM_Data_out));
endmodule | module main(
input clk,
input [7:0] Data1,
input [7:0] Data2,
input [7:0] Data3,
input [7:0] Data4,
output [7:0] IM_Data_out
); |
wire [1:0] WM_Data;
Generation G( .clk(clk), .WM_Data(WM_Data));
Insertion I( .clk(clk), .Data1(Data1), .Data2(Data2), .Data3(Data3), .Data4(Data4),
.WM_Data(WM_Data), .WM_IM_Data(IM_Data_out));
endmodule | 0 |
139,415 | data/full_repos/permissive/87632970/main_test.v | 87,632,970 | main_test.v | v | 79 | 81 | [] | [] | [] | [(25, 77)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/87632970/main_test.v:51: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87632970/main_test.v:57: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87632970/main_test.v:63: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87632970/main_test.v:74: Unsupported: Ignoring delay on this delayed statement.\n #5 clk=~clk;\n ^\n%Error: data/full_repos/permissive/87632970/main_test.v:36: Cannot find file containing module: \'main\'\n main uut (\n ^~~~\n ... Looked in:\n data/full_repos/permissive/87632970,data/full_repos/permissive/87632970/main\n data/full_repos/permissive/87632970,data/full_repos/permissive/87632970/main.v\n data/full_repos/permissive/87632970,data/full_repos/permissive/87632970/main.sv\n main\n main.v\n main.sv\n obj_dir/main\n obj_dir/main.v\n obj_dir/main.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,775 | module | module main_test;
reg clk;
wire [7:0] IM_Data_out;
reg [7:0] Data1, Data2, Data3, Data4;
main uut (
.clk(clk),
.Data1(Data1),
.Data2(Data2),
.Data3(Data3),
.Data4(Data4),
.IM_Data_out(IM_Data_out)
);
initial begin
clk = 0;
#100
Data1 = 8'b10000000;
Data2 = 8'b00001000;
Data3 = 8'b00100000;
Data4 = 8'b00000010;
#100
Data1 = 8'b11000000;
Data2 = 8'b00001100;
Data3 = 8'b00110000;
Data4 = 8'b00000011;
#100
Data1 = 8'b01101010;
Data2 = 8'b01110010;
Data3 = 8'b01101011;
Data4 = 8'b10101010;
end
always begin
#5 clk=~clk;
end
endmodule | module main_test; |
reg clk;
wire [7:0] IM_Data_out;
reg [7:0] Data1, Data2, Data3, Data4;
main uut (
.clk(clk),
.Data1(Data1),
.Data2(Data2),
.Data3(Data3),
.Data4(Data4),
.IM_Data_out(IM_Data_out)
);
initial begin
clk = 0;
#100
Data1 = 8'b10000000;
Data2 = 8'b00001000;
Data3 = 8'b00100000;
Data4 = 8'b00000010;
#100
Data1 = 8'b11000000;
Data2 = 8'b00001100;
Data3 = 8'b00110000;
Data4 = 8'b00000011;
#100
Data1 = 8'b01101010;
Data2 = 8'b01110010;
Data3 = 8'b01101011;
Data4 = 8'b10101010;
end
always begin
#5 clk=~clk;
end
endmodule | 0 |
139,416 | data/full_repos/permissive/87689974/fpga/src/clk_rst.v | 87,689,974 | clk_rst.v | v | 45 | 67 | [] | [] | [] | [(10, 44)] | null | data/verilator_xmls/391a1b8e-8d38-4231-b171-6d9d439eadc7.xml | null | 304,780 | module | module clk_rst(clk_in, rst_in_n,
clk, rst);
input clk_in;
input rst_in_n;
output clk;
output rst;
reg rst_p_n;
reg rst_s_n;
reg [23:0] rst_counter;
wire rst_counting;
assign clk = clk_in;
assign rst_counting = (rst_counter == 24'hFFFFFF) ? 1'b0 : 1'b1;
always @(posedge clk_in) begin
rst_p_n <= rst_in_n;
rst_s_n <= rst_p_n;
if (~rst_s_n) begin
rst_counter <= 24'h000000;
end else begin
if (rst_counting) begin
rst_counter <= rst_counter + 24'h000001;
end
end
end
assign rst = rst_counting;
endmodule | module clk_rst(clk_in, rst_in_n,
clk, rst); |
input clk_in;
input rst_in_n;
output clk;
output rst;
reg rst_p_n;
reg rst_s_n;
reg [23:0] rst_counter;
wire rst_counting;
assign clk = clk_in;
assign rst_counting = (rst_counter == 24'hFFFFFF) ? 1'b0 : 1'b1;
always @(posedge clk_in) begin
rst_p_n <= rst_in_n;
rst_s_n <= rst_p_n;
if (~rst_s_n) begin
rst_counter <= 24'h000000;
end else begin
if (rst_counting) begin
rst_counter <= rst_counter + 24'h000001;
end
end
end
assign rst = rst_counting;
endmodule | 0 |
139,417 | data/full_repos/permissive/87689974/fpga/src/flashprog.v | 87,689,974 | flashprog.v | v | 585 | 69 | [] | [] | [] | [(10, 555), (558, 584)] | null | null | 1: b"%Error: data/full_repos/permissive/87689974/fpga/src/flashprog.v:94: Cannot find file containing module: 'clk_rst'\n clk_rst clk_rst_1(\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/87689974/fpga/src,data/full_repos/permissive/87689974/clk_rst\n data/full_repos/permissive/87689974/fpga/src,data/full_repos/permissive/87689974/clk_rst.v\n data/full_repos/permissive/87689974/fpga/src,data/full_repos/permissive/87689974/clk_rst.sv\n clk_rst\n clk_rst.v\n clk_rst.sv\n obj_dir/clk_rst\n obj_dir/clk_rst.v\n obj_dir/clk_rst.sv\n%Error: data/full_repos/permissive/87689974/fpga/src/flashprog.v:101: Cannot find file containing module: 'rcvbuf'\n rcvbuf rcvbuf_1(\n ^~~~~~\n%Error: data/full_repos/permissive/87689974/fpga/src/flashprog.v:110: Cannot find file containing module: 'xmtbuf'\n xmtbuf xmtbuf_1(\n ^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 304,781 | module | module flashprog(clk_in,
rst_in_n,
rs232_rxd,
rs232_txd,
fl_addr,
fl_dq,
fl_ce_n,
fl_oe_n,
fl_we_n,
fl_wp_n,
fl_rst_n,
fl_ry,
led_g,
led_r,
hex7_n,
hex6_n,
hex5_n,
hex4_n,
hex3_n,
hex2_n,
hex1_n,
hex0_n);
input clk_in;
input rst_in_n;
input rs232_rxd;
output rs232_txd;
output [22:0] fl_addr;
inout [7:0] fl_dq;
output fl_ce_n;
output fl_oe_n;
output fl_we_n;
output fl_wp_n;
output fl_rst_n;
input fl_ry;
output [8:0] led_g;
output [17:0] led_r;
output [6:0] hex7_n;
output [6:0] hex6_n;
output [6:0] hex5_n;
output [6:0] hex4_n;
output [6:0] hex3_n;
output [6:0] hex2_n;
output [6:0] hex1_n;
output [6:0] hex0_n;
wire clk;
wire rst;
reg [22:0] addr;
reg [7:0] data;
reg [3:0] ctrl;
wire [7:0] dat;
wire rdy;
wire cmd_rdy;
wire [7:0] cmd_data;
wire [7:0] snd_data;
reg [3:0] state;
reg [3:0] next_state;
reg ack_data;
reg ld_addr_0;
reg ld_addr_1;
reg ld_addr_2;
reg ld_addr_3;
reg ld_addr_4;
reg ld_addr_5;
reg ld_data_0;
reg ld_data_1;
reg ld_ctrl;
reg snd_stb;
reg snd_mux;
wire [23:20] aux_addr;
clk_rst clk_rst_1(
.clk_in(clk_in),
.rst_in_n(rst_in_n),
.clk(clk),
.rst(rst)
);
rcvbuf rcvbuf_1(
.clk(clk),
.reset(rst),
.read(ack_data),
.ready(cmd_rdy),
.data_out(cmd_data[7:0]),
.serial_in(rs232_rxd)
);
xmtbuf xmtbuf_1(
.clk(clk),
.reset(rst),
.write(snd_stb),
.ready(),
.data_in(snd_data[7:0]),
.serial_out(rs232_txd)
);
assign fl_addr[22:0] = addr[22:0];
assign fl_dq[7:0] = (~ctrl[3] & ~ctrl[2]) ? 8'hzz : data[7:0];
assign fl_ce_n = ctrl[3];
assign fl_oe_n = ctrl[2];
assign fl_we_n = ctrl[1];
assign fl_wp_n = 1'b1;
assign fl_rst_n = ctrl[0];
assign dat[7:0] = fl_dq[7:0];
assign rdy = fl_ry;
`define WT_CMD 4'd0
`define RD_CMD 4'd1
`define SET_ADDR_0 4'd2
`define SET_ADDR_1 4'd3
`define SET_ADDR_2 4'd4
`define SET_ADDR_3 4'd5
`define SET_ADDR_4 4'd6
`define SET_ADDR_5 4'd7
`define SET_DATA_0 4'd8
`define SET_DATA_1 4'd9
`define SET_CTRL 4'd10
`define GET_DATA 4'd11
`define GET_READY 4'd12
always @(posedge clk) begin
if (rst) begin
state[3:0] <= `WT_CMD;
end else begin
state[3:0] <= next_state[3:0];
end
end
always @(*) begin
case (state[3:0])
`WT_CMD:
begin
if (~cmd_rdy) begin
next_state = `WT_CMD;
end else begin
next_state = `RD_CMD;
end
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`RD_CMD:
begin
case (cmd_data[7:4])
4'h0: next_state = `SET_ADDR_0;
4'h1: next_state = `SET_ADDR_1;
4'h2: next_state = `SET_ADDR_2;
4'h3: next_state = `SET_ADDR_3;
4'h4: next_state = `SET_ADDR_4;
4'h5: next_state = `SET_ADDR_5;
4'h6: next_state = `SET_DATA_0;
4'h7: next_state = `SET_DATA_1;
4'h8: next_state = `SET_CTRL;
4'h9: next_state = `GET_DATA;
4'hA: next_state = `GET_READY;
4'hB: next_state = `WT_CMD;
4'hC: next_state = `WT_CMD;
4'hD: next_state = `WT_CMD;
4'hE: next_state = `WT_CMD;
4'hF: next_state = `WT_CMD;
endcase
ack_data = 1'b1;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`SET_ADDR_0:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b1;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`SET_ADDR_1:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b1;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`SET_ADDR_2:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b1;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`SET_ADDR_3:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b1;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`SET_ADDR_4:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b1;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`SET_ADDR_5:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b1;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`SET_DATA_0:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b1;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`SET_DATA_1:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b1;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`SET_CTRL:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b1;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`GET_DATA:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b1;
snd_mux = 1'b0;
end
`GET_READY:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b1;
snd_mux = 1'b1;
end
default:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
addr[3:0] <= 4'h0;
end else begin
if (ld_addr_0) begin
addr[3:0] <= cmd_data[3:0];
end
end
end
always @(posedge clk) begin
if (rst) begin
addr[7:4] <= 4'h0;
end else begin
if (ld_addr_1) begin
addr[7:4] <= cmd_data[3:0];
end
end
end
always @(posedge clk) begin
if (rst) begin
addr[11:8] <= 4'h0;
end else begin
if (ld_addr_2) begin
addr[11:8] <= cmd_data[3:0];
end
end
end
always @(posedge clk) begin
if (rst) begin
addr[15:12] <= 4'h0;
end else begin
if (ld_addr_3) begin
addr[15:12] <= cmd_data[3:0];
end
end
end
always @(posedge clk) begin
if (rst) begin
addr[19:16] <= 4'h0;
end else begin
if (ld_addr_4) begin
addr[19:16] <= cmd_data[3:0];
end
end
end
always @(posedge clk) begin
if (rst) begin
addr[22:20] <= 3'h0;
end else begin
if (ld_addr_5) begin
addr[22:20] <= cmd_data[2:0];
end
end
end
always @(posedge clk) begin
if (rst) begin
data[3:0] <= 4'h0;
end else begin
if (ld_data_0) begin
data[3:0] <= cmd_data[3:0];
end
end
end
always @(posedge clk) begin
if (rst) begin
data[7:4] <= 4'h0;
end else begin
if (ld_data_1) begin
data[7:4] <= cmd_data[3:0];
end
end
end
always @(posedge clk) begin
if (rst) begin
ctrl[3:0] <= { 1'b1, 1'b1, 1'b1, 1'b1 };
end else begin
if (ld_ctrl) begin
ctrl[3:0] <= cmd_data[3:0];
end
end
end
assign snd_data[7:0] =
(snd_mux == 1'b0) ? dat[7:0] : { 7'b0, rdy };
assign led_g[8:1] = 8'h00;
assign led_g[0] = rdy;
assign led_r[17:4] = 14'h0000;
assign led_r[3:0] = ctrl[3:0];
hexdrv hexdrv_0(
.in(addr[3:0]),
.out(hex0_n[6:0])
);
hexdrv hexdrv_1(
.in(addr[7:4]),
.out(hex1_n[6:0])
);
hexdrv hexdrv_2(
.in(addr[11:8]),
.out(hex2_n[6:0])
);
hexdrv hexdrv_3(
.in(addr[15:12]),
.out(hex3_n[6:0])
);
hexdrv hexdrv_4(
.in(addr[19:16]),
.out(hex4_n[6:0])
);
assign aux_addr[23:20] = { 1'b0, addr[22:20] };
hexdrv hexdrv_5(
.in(aux_addr[23:20]),
.out(hex5_n[6:0])
);
hexdrv hexdrv_6(
.in(data[3:0]),
.out(hex6_n[6:0])
);
hexdrv hexdrv_7(
.in(data[7:4]),
.out(hex7_n[6:0])
);
endmodule | module flashprog(clk_in,
rst_in_n,
rs232_rxd,
rs232_txd,
fl_addr,
fl_dq,
fl_ce_n,
fl_oe_n,
fl_we_n,
fl_wp_n,
fl_rst_n,
fl_ry,
led_g,
led_r,
hex7_n,
hex6_n,
hex5_n,
hex4_n,
hex3_n,
hex2_n,
hex1_n,
hex0_n); |
input clk_in;
input rst_in_n;
input rs232_rxd;
output rs232_txd;
output [22:0] fl_addr;
inout [7:0] fl_dq;
output fl_ce_n;
output fl_oe_n;
output fl_we_n;
output fl_wp_n;
output fl_rst_n;
input fl_ry;
output [8:0] led_g;
output [17:0] led_r;
output [6:0] hex7_n;
output [6:0] hex6_n;
output [6:0] hex5_n;
output [6:0] hex4_n;
output [6:0] hex3_n;
output [6:0] hex2_n;
output [6:0] hex1_n;
output [6:0] hex0_n;
wire clk;
wire rst;
reg [22:0] addr;
reg [7:0] data;
reg [3:0] ctrl;
wire [7:0] dat;
wire rdy;
wire cmd_rdy;
wire [7:0] cmd_data;
wire [7:0] snd_data;
reg [3:0] state;
reg [3:0] next_state;
reg ack_data;
reg ld_addr_0;
reg ld_addr_1;
reg ld_addr_2;
reg ld_addr_3;
reg ld_addr_4;
reg ld_addr_5;
reg ld_data_0;
reg ld_data_1;
reg ld_ctrl;
reg snd_stb;
reg snd_mux;
wire [23:20] aux_addr;
clk_rst clk_rst_1(
.clk_in(clk_in),
.rst_in_n(rst_in_n),
.clk(clk),
.rst(rst)
);
rcvbuf rcvbuf_1(
.clk(clk),
.reset(rst),
.read(ack_data),
.ready(cmd_rdy),
.data_out(cmd_data[7:0]),
.serial_in(rs232_rxd)
);
xmtbuf xmtbuf_1(
.clk(clk),
.reset(rst),
.write(snd_stb),
.ready(),
.data_in(snd_data[7:0]),
.serial_out(rs232_txd)
);
assign fl_addr[22:0] = addr[22:0];
assign fl_dq[7:0] = (~ctrl[3] & ~ctrl[2]) ? 8'hzz : data[7:0];
assign fl_ce_n = ctrl[3];
assign fl_oe_n = ctrl[2];
assign fl_we_n = ctrl[1];
assign fl_wp_n = 1'b1;
assign fl_rst_n = ctrl[0];
assign dat[7:0] = fl_dq[7:0];
assign rdy = fl_ry;
`define WT_CMD 4'd0
`define RD_CMD 4'd1
`define SET_ADDR_0 4'd2
`define SET_ADDR_1 4'd3
`define SET_ADDR_2 4'd4
`define SET_ADDR_3 4'd5
`define SET_ADDR_4 4'd6
`define SET_ADDR_5 4'd7
`define SET_DATA_0 4'd8
`define SET_DATA_1 4'd9
`define SET_CTRL 4'd10
`define GET_DATA 4'd11
`define GET_READY 4'd12
always @(posedge clk) begin
if (rst) begin
state[3:0] <= `WT_CMD;
end else begin
state[3:0] <= next_state[3:0];
end
end
always @(*) begin
case (state[3:0])
`WT_CMD:
begin
if (~cmd_rdy) begin
next_state = `WT_CMD;
end else begin
next_state = `RD_CMD;
end
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`RD_CMD:
begin
case (cmd_data[7:4])
4'h0: next_state = `SET_ADDR_0;
4'h1: next_state = `SET_ADDR_1;
4'h2: next_state = `SET_ADDR_2;
4'h3: next_state = `SET_ADDR_3;
4'h4: next_state = `SET_ADDR_4;
4'h5: next_state = `SET_ADDR_5;
4'h6: next_state = `SET_DATA_0;
4'h7: next_state = `SET_DATA_1;
4'h8: next_state = `SET_CTRL;
4'h9: next_state = `GET_DATA;
4'hA: next_state = `GET_READY;
4'hB: next_state = `WT_CMD;
4'hC: next_state = `WT_CMD;
4'hD: next_state = `WT_CMD;
4'hE: next_state = `WT_CMD;
4'hF: next_state = `WT_CMD;
endcase
ack_data = 1'b1;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`SET_ADDR_0:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b1;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`SET_ADDR_1:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b1;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`SET_ADDR_2:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b1;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`SET_ADDR_3:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b1;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`SET_ADDR_4:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b1;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`SET_ADDR_5:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b1;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`SET_DATA_0:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b1;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`SET_DATA_1:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b1;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`SET_CTRL:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b1;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
`GET_DATA:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b1;
snd_mux = 1'b0;
end
`GET_READY:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b1;
snd_mux = 1'b1;
end
default:
begin
next_state = `WT_CMD;
ack_data = 1'b0;
ld_addr_0 = 1'b0;
ld_addr_1 = 1'b0;
ld_addr_2 = 1'b0;
ld_addr_3 = 1'b0;
ld_addr_4 = 1'b0;
ld_addr_5 = 1'b0;
ld_data_0 = 1'b0;
ld_data_1 = 1'b0;
ld_ctrl = 1'b0;
snd_stb = 1'b0;
snd_mux = 1'b0;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
addr[3:0] <= 4'h0;
end else begin
if (ld_addr_0) begin
addr[3:0] <= cmd_data[3:0];
end
end
end
always @(posedge clk) begin
if (rst) begin
addr[7:4] <= 4'h0;
end else begin
if (ld_addr_1) begin
addr[7:4] <= cmd_data[3:0];
end
end
end
always @(posedge clk) begin
if (rst) begin
addr[11:8] <= 4'h0;
end else begin
if (ld_addr_2) begin
addr[11:8] <= cmd_data[3:0];
end
end
end
always @(posedge clk) begin
if (rst) begin
addr[15:12] <= 4'h0;
end else begin
if (ld_addr_3) begin
addr[15:12] <= cmd_data[3:0];
end
end
end
always @(posedge clk) begin
if (rst) begin
addr[19:16] <= 4'h0;
end else begin
if (ld_addr_4) begin
addr[19:16] <= cmd_data[3:0];
end
end
end
always @(posedge clk) begin
if (rst) begin
addr[22:20] <= 3'h0;
end else begin
if (ld_addr_5) begin
addr[22:20] <= cmd_data[2:0];
end
end
end
always @(posedge clk) begin
if (rst) begin
data[3:0] <= 4'h0;
end else begin
if (ld_data_0) begin
data[3:0] <= cmd_data[3:0];
end
end
end
always @(posedge clk) begin
if (rst) begin
data[7:4] <= 4'h0;
end else begin
if (ld_data_1) begin
data[7:4] <= cmd_data[3:0];
end
end
end
always @(posedge clk) begin
if (rst) begin
ctrl[3:0] <= { 1'b1, 1'b1, 1'b1, 1'b1 };
end else begin
if (ld_ctrl) begin
ctrl[3:0] <= cmd_data[3:0];
end
end
end
assign snd_data[7:0] =
(snd_mux == 1'b0) ? dat[7:0] : { 7'b0, rdy };
assign led_g[8:1] = 8'h00;
assign led_g[0] = rdy;
assign led_r[17:4] = 14'h0000;
assign led_r[3:0] = ctrl[3:0];
hexdrv hexdrv_0(
.in(addr[3:0]),
.out(hex0_n[6:0])
);
hexdrv hexdrv_1(
.in(addr[7:4]),
.out(hex1_n[6:0])
);
hexdrv hexdrv_2(
.in(addr[11:8]),
.out(hex2_n[6:0])
);
hexdrv hexdrv_3(
.in(addr[15:12]),
.out(hex3_n[6:0])
);
hexdrv hexdrv_4(
.in(addr[19:16]),
.out(hex4_n[6:0])
);
assign aux_addr[23:20] = { 1'b0, addr[22:20] };
hexdrv hexdrv_5(
.in(aux_addr[23:20]),
.out(hex5_n[6:0])
);
hexdrv hexdrv_6(
.in(data[3:0]),
.out(hex6_n[6:0])
);
hexdrv hexdrv_7(
.in(data[7:4]),
.out(hex7_n[6:0])
);
endmodule | 0 |
139,418 | data/full_repos/permissive/87689974/fpga/src/flashprog.v | 87,689,974 | flashprog.v | v | 585 | 69 | [] | [] | [] | [(10, 555), (558, 584)] | null | null | 1: b"%Error: data/full_repos/permissive/87689974/fpga/src/flashprog.v:94: Cannot find file containing module: 'clk_rst'\n clk_rst clk_rst_1(\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/87689974/fpga/src,data/full_repos/permissive/87689974/clk_rst\n data/full_repos/permissive/87689974/fpga/src,data/full_repos/permissive/87689974/clk_rst.v\n data/full_repos/permissive/87689974/fpga/src,data/full_repos/permissive/87689974/clk_rst.sv\n clk_rst\n clk_rst.v\n clk_rst.sv\n obj_dir/clk_rst\n obj_dir/clk_rst.v\n obj_dir/clk_rst.sv\n%Error: data/full_repos/permissive/87689974/fpga/src/flashprog.v:101: Cannot find file containing module: 'rcvbuf'\n rcvbuf rcvbuf_1(\n ^~~~~~\n%Error: data/full_repos/permissive/87689974/fpga/src/flashprog.v:110: Cannot find file containing module: 'xmtbuf'\n xmtbuf xmtbuf_1(\n ^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 304,781 | module | module hexdrv(in, out);
input [3:0] in;
output reg [6:0] out;
always @(*) begin
case (in[3:0])
4'h0: out[6:0] = ~7'b0111111;
4'h1: out[6:0] = ~7'b0000110;
4'h2: out[6:0] = ~7'b1011011;
4'h3: out[6:0] = ~7'b1001111;
4'h4: out[6:0] = ~7'b1100110;
4'h5: out[6:0] = ~7'b1101101;
4'h6: out[6:0] = ~7'b1111101;
4'h7: out[6:0] = ~7'b0000111;
4'h8: out[6:0] = ~7'b1111111;
4'h9: out[6:0] = ~7'b1100111;
4'hA: out[6:0] = ~7'b1110111;
4'hB: out[6:0] = ~7'b1111100;
4'hC: out[6:0] = ~7'b0111001;
4'hD: out[6:0] = ~7'b1011110;
4'hE: out[6:0] = ~7'b1111001;
4'hF: out[6:0] = ~7'b1110001;
endcase
end
endmodule | module hexdrv(in, out); |
input [3:0] in;
output reg [6:0] out;
always @(*) begin
case (in[3:0])
4'h0: out[6:0] = ~7'b0111111;
4'h1: out[6:0] = ~7'b0000110;
4'h2: out[6:0] = ~7'b1011011;
4'h3: out[6:0] = ~7'b1001111;
4'h4: out[6:0] = ~7'b1100110;
4'h5: out[6:0] = ~7'b1101101;
4'h6: out[6:0] = ~7'b1111101;
4'h7: out[6:0] = ~7'b0000111;
4'h8: out[6:0] = ~7'b1111111;
4'h9: out[6:0] = ~7'b1100111;
4'hA: out[6:0] = ~7'b1110111;
4'hB: out[6:0] = ~7'b1111100;
4'hC: out[6:0] = ~7'b0111001;
4'hD: out[6:0] = ~7'b1011110;
4'hE: out[6:0] = ~7'b1111001;
4'hF: out[6:0] = ~7'b1110001;
endcase
end
endmodule | 0 |
139,419 | data/full_repos/permissive/87689974/fpga/src/rcv.v | 87,689,974 | rcv.v | v | 58 | 55 | [] | [] | [] | [(10, 57)] | null | data/verilator_xmls/03ca0671-269c-4be0-81fb-f6ff5680ac8a.xml | null | 304,782 | module | module rcv(clk, reset, full, parallel_out, serial_in);
input clk;
input reset;
output reg full;
output [7:0] parallel_out;
input serial_in;
reg serial_p;
reg serial_s;
reg [3:0] state;
reg [8:0] shift;
reg [10:0] count;
assign parallel_out[7:0] = shift[7:0];
always @(posedge clk) begin
serial_p <= serial_in;
serial_s <= serial_p;
end
always @(posedge clk) begin
if (reset) begin
state <= 4'h0;
full <= 1'b0;
end else begin
if (state == 4'h0) begin
full <= 1'b0;
if (serial_s == 1'b0) begin
state <= 4'h1;
count <= 11'd651;
end
end else
if (state == 4'hb) begin
state <= 4'h0;
full <= 1'b1;
end else begin
if (count == 11'd0) begin
state <= state + 4'h1;
shift[8:0] <= { serial_s, shift[8:1] };
count <= 11'd1302;
end else begin
count <= count - 11'd1;
end
end
end
end
endmodule | module rcv(clk, reset, full, parallel_out, serial_in); |
input clk;
input reset;
output reg full;
output [7:0] parallel_out;
input serial_in;
reg serial_p;
reg serial_s;
reg [3:0] state;
reg [8:0] shift;
reg [10:0] count;
assign parallel_out[7:0] = shift[7:0];
always @(posedge clk) begin
serial_p <= serial_in;
serial_s <= serial_p;
end
always @(posedge clk) begin
if (reset) begin
state <= 4'h0;
full <= 1'b0;
end else begin
if (state == 4'h0) begin
full <= 1'b0;
if (serial_s == 1'b0) begin
state <= 4'h1;
count <= 11'd651;
end
end else
if (state == 4'hb) begin
state <= 4'h0;
full <= 1'b1;
end else begin
if (count == 11'd0) begin
state <= state + 4'h1;
shift[8:0] <= { serial_s, shift[8:1] };
count <= 11'd1302;
end else begin
count <= count - 11'd1;
end
end
end
end
endmodule | 0 |
139,420 | data/full_repos/permissive/87689974/fpga/src/rcvbuf.v | 87,689,974 | rcvbuf.v | v | 37 | 61 | [] | [] | [] | [(10, 36)] | null | null | 1: b"%Error: data/full_repos/permissive/87689974/fpga/src/rcvbuf.v:21: Cannot find file containing module: 'rcv'\n rcv rcv_1(clk, reset, full, parallel_out, serial_in);\n ^~~\n ... Looked in:\n data/full_repos/permissive/87689974/fpga/src,data/full_repos/permissive/87689974/rcv\n data/full_repos/permissive/87689974/fpga/src,data/full_repos/permissive/87689974/rcv.v\n data/full_repos/permissive/87689974/fpga/src,data/full_repos/permissive/87689974/rcv.sv\n rcv\n rcv.v\n rcv.sv\n obj_dir/rcv\n obj_dir/rcv.v\n obj_dir/rcv.sv\n%Error: Exiting due to 1 error(s)\n" | 304,783 | module | module rcvbuf(clk, reset, read, ready, data_out, serial_in);
input clk;
input reset;
input read;
output reg ready;
output reg [7:0] data_out;
input serial_in;
wire full;
wire [7:0] parallel_out;
rcv rcv_1(clk, reset, full, parallel_out, serial_in);
always @(posedge clk) begin
if (reset) begin
ready <= 1'b0;
end else begin
if (full) begin
data_out <= parallel_out;
end
if (full | read) begin
ready <= full;
end
end
end
endmodule | module rcvbuf(clk, reset, read, ready, data_out, serial_in); |
input clk;
input reset;
input read;
output reg ready;
output reg [7:0] data_out;
input serial_in;
wire full;
wire [7:0] parallel_out;
rcv rcv_1(clk, reset, full, parallel_out, serial_in);
always @(posedge clk) begin
if (reset) begin
ready <= 1'b0;
end else begin
if (full) begin
data_out <= parallel_out;
end
if (full | read) begin
ready <= full;
end
end
end
endmodule | 0 |
139,421 | data/full_repos/permissive/87689974/fpga/src/xmt.v | 87,689,974 | xmt.v | v | 54 | 62 | [] | [] | [] | [(10, 53)] | null | data/verilator_xmls/1e803a2c-5c2c-4a35-af29-f742270cb692.xml | null | 304,784 | module | module xmt(clk, reset, load, empty, parallel_in, serial_out);
input clk;
input reset;
input load;
output reg empty;
input [7:0] parallel_in;
output serial_out;
reg [3:0] state;
reg [8:0] shift;
reg [10:0] count;
assign serial_out = shift[0];
always @(posedge clk) begin
if (reset) begin
state <= 4'h0;
shift <= 9'b111111111;
empty <= 1'b1;
end else begin
if (state == 4'h0) begin
if (load) begin
state <= 4'h1;
shift <= { parallel_in, 1'b0 };
count <= 11'd1302;
empty <= 1'b0;
end
end else
if (state == 4'hb) begin
state <= 4'h0;
empty <= 1'b1;
end else begin
if (count == 11'd0) begin
state <= state + 4'h1;
shift[8:0] <= { 1'b1, shift[8:1] };
count <= 11'd1302;
end else begin
count <= count - 11'd1;
end
end
end
end
endmodule | module xmt(clk, reset, load, empty, parallel_in, serial_out); |
input clk;
input reset;
input load;
output reg empty;
input [7:0] parallel_in;
output serial_out;
reg [3:0] state;
reg [8:0] shift;
reg [10:0] count;
assign serial_out = shift[0];
always @(posedge clk) begin
if (reset) begin
state <= 4'h0;
shift <= 9'b111111111;
empty <= 1'b1;
end else begin
if (state == 4'h0) begin
if (load) begin
state <= 4'h1;
shift <= { parallel_in, 1'b0 };
count <= 11'd1302;
empty <= 1'b0;
end
end else
if (state == 4'hb) begin
state <= 4'h0;
empty <= 1'b1;
end else begin
if (count == 11'd0) begin
state <= state + 4'h1;
shift[8:0] <= { 1'b1, shift[8:1] };
count <= 11'd1302;
end else begin
count <= count - 11'd1;
end
end
end
end
endmodule | 0 |
139,422 | data/full_repos/permissive/87689974/fpga/src/xmtbuf.v | 87,689,974 | xmtbuf.v | v | 80 | 62 | [] | [] | [] | [(10, 79)] | null | null | 1: b"%Error: data/full_repos/permissive/87689974/fpga/src/xmtbuf.v:23: Cannot find file containing module: 'xmt'\n xmt xmt_1(clk, reset, load, empty, data_hold, serial_out);\n ^~~\n ... Looked in:\n data/full_repos/permissive/87689974/fpga/src,data/full_repos/permissive/87689974/xmt\n data/full_repos/permissive/87689974/fpga/src,data/full_repos/permissive/87689974/xmt.v\n data/full_repos/permissive/87689974/fpga/src,data/full_repos/permissive/87689974/xmt.sv\n xmt\n xmt.v\n xmt.sv\n obj_dir/xmt\n obj_dir/xmt.v\n obj_dir/xmt.sv\n%Error: Exiting due to 1 error(s)\n" | 304,785 | module | module xmtbuf(clk, reset, write, ready, data_in, serial_out);
input clk;
input reset;
input write;
output reg ready;
input [7:0] data_in;
output serial_out;
reg [1:0] state;
reg [7:0] data_hold;
reg load;
wire empty;
xmt xmt_1(clk, reset, load, empty, data_hold, serial_out);
always @(posedge clk) begin
if (reset) begin
state <= 2'b00;
ready <= 1'b1;
load <= 1'b0;
end else begin
case (state)
2'b00:
begin
if (write) begin
state <= 2'b01;
data_hold <= data_in;
ready <= 1'b0;
load <= 1'b1;
end
end
2'b01:
begin
state <= 2'b10;
ready <= 1'b1;
load <= 1'b0;
end
2'b10:
begin
if (empty & ~write) begin
state <= 2'b00;
ready <= 1'b1;
load <= 1'b0;
end else
if (empty & write) begin
state <= 2'b01;
data_hold <= data_in;
ready <= 1'b0;
load <= 1'b1;
end else
if (~empty & write) begin
state <= 2'b11;
data_hold <= data_in;
ready <= 1'b0;
load <= 1'b0;
end
end
2'b11:
begin
if (empty) begin
state <= 2'b01;
ready <= 1'b0;
load <= 1'b1;
end
end
endcase
end
end
endmodule | module xmtbuf(clk, reset, write, ready, data_in, serial_out); |
input clk;
input reset;
input write;
output reg ready;
input [7:0] data_in;
output serial_out;
reg [1:0] state;
reg [7:0] data_hold;
reg load;
wire empty;
xmt xmt_1(clk, reset, load, empty, data_hold, serial_out);
always @(posedge clk) begin
if (reset) begin
state <= 2'b00;
ready <= 1'b1;
load <= 1'b0;
end else begin
case (state)
2'b00:
begin
if (write) begin
state <= 2'b01;
data_hold <= data_in;
ready <= 1'b0;
load <= 1'b1;
end
end
2'b01:
begin
state <= 2'b10;
ready <= 1'b1;
load <= 1'b0;
end
2'b10:
begin
if (empty & ~write) begin
state <= 2'b00;
ready <= 1'b1;
load <= 1'b0;
end else
if (empty & write) begin
state <= 2'b01;
data_hold <= data_in;
ready <= 1'b0;
load <= 1'b1;
end else
if (~empty & write) begin
state <= 2'b11;
data_hold <= data_in;
ready <= 1'b0;
load <= 1'b0;
end
end
2'b11:
begin
if (empty) begin
state <= 2'b01;
ready <= 1'b0;
load <= 1'b1;
end
end
endcase
end
end
endmodule | 0 |
139,423 | data/full_repos/permissive/87695634/adder16.v | 87,695,634 | adder16.v | v | 77 | 83 | [] | [] | [] | [(49, 76)] | null | null | 1: b"%Error: data/full_repos/permissive/87695634/adder16.v:60: Cannot find file containing module: 'Full_Adder'\n Full_Adder f(A[0],B[0],s,out[0],Cout[0]); \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/Full_Adder\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/Full_Adder.v\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/Full_Adder.sv\n Full_Adder\n Full_Adder.v\n Full_Adder.sv\n obj_dir/Full_Adder\n obj_dir/Full_Adder.v\n obj_dir/Full_Adder.sv\n%Error: data/full_repos/permissive/87695634/adder16.v:66: Cannot find file containing module: 'Full_Adder'\n Full_Adder f(A[i],B[i],Cout[i-1],out[i],Cout[i]); \n ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 304,786 | module | module adder16(
input [15:0] A,
input [15:0] B,
output [15:0] out,
output Co
);
wire [15:0] Cout ;
localparam s = 1'b0;
Full_Adder f(A[0],B[0],s,out[0],Cout[0]);
generate
genvar i;
for (i=1; i < 16; i=i+1) begin: r
Full_Adder f(A[i],B[i],Cout[i-1],out[i],Cout[i]);
end
endgenerate
assign Co = Cout[15];
endmodule | module adder16(
input [15:0] A,
input [15:0] B,
output [15:0] out,
output Co
); |
wire [15:0] Cout ;
localparam s = 1'b0;
Full_Adder f(A[0],B[0],s,out[0],Cout[0]);
generate
genvar i;
for (i=1; i < 16; i=i+1) begin: r
Full_Adder f(A[i],B[i],Cout[i-1],out[i],Cout[i]);
end
endgenerate
assign Co = Cout[15];
endmodule | 0 |
139,424 | data/full_repos/permissive/87695634/button_reader.v | 87,695,634 | button_reader.v | v | 40 | 83 | [] | [] | [] | [(21, 39)] | null | null | 1: b"%Error: data/full_repos/permissive/87695634/button_reader.v:31: Cannot find file containing module: 'Debouncer'\n Debouncer d1(clk,b_in[0],right);\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/Debouncer\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/Debouncer.v\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/Debouncer.sv\n Debouncer\n Debouncer.v\n Debouncer.sv\n obj_dir/Debouncer\n obj_dir/Debouncer.v\n obj_dir/Debouncer.sv\n%Error: data/full_repos/permissive/87695634/button_reader.v:32: Cannot find file containing module: 'Debouncer'\n Debouncer d2(clk,b_in[1],down);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/87695634/button_reader.v:33: Cannot find file containing module: 'Debouncer'\n Debouncer d3(clk,b_in[2],left);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/87695634/button_reader.v:34: Cannot find file containing module: 'Debouncer'\n Debouncer d4(clk,b_in[3],up);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/87695634/button_reader.v:35: Cannot find file containing module: 'Debouncer'\n Debouncer d5(clk,b_in[4],center);\n ^~~~~~~~~\n%Error: Exiting due to 5 error(s)\n" | 304,787 | module | module button_reader(
input [4:0] b_in,
input clk,
output right,
output down,
output left,
output up,
output center
);
Debouncer d1(clk,b_in[0],right);
Debouncer d2(clk,b_in[1],down);
Debouncer d3(clk,b_in[2],left);
Debouncer d4(clk,b_in[3],up);
Debouncer d5(clk,b_in[4],center);
endmodule | module button_reader(
input [4:0] b_in,
input clk,
output right,
output down,
output left,
output up,
output center
); |
Debouncer d1(clk,b_in[0],right);
Debouncer d2(clk,b_in[1],down);
Debouncer d3(clk,b_in[2],left);
Debouncer d4(clk,b_in[3],up);
Debouncer d5(clk,b_in[4],center);
endmodule | 0 |
139,425 | data/full_repos/permissive/87695634/combinational_pc.v | 87,695,634 | combinational_pc.v | v | 74 | 83 | [] | [] | [] | null | line:59: before: ")" | null | 1: b'%Error: data/full_repos/permissive/87695634/combinational_pc.v:58: Cannot find file containing module: \'Reg_Cell\'\n Reg_Cell PC(Rout , clk , En , PCout);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/Reg_Cell\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/Reg_Cell.v\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/Reg_Cell.sv\n Reg_Cell\n Reg_Cell.v\n Reg_Cell.sv\n obj_dir/Reg_Cell\n obj_dir/Reg_Cell.v\n obj_dir/Reg_Cell.sv\n%Error: data/full_repos/permissive/87695634/combinational_pc.v:59: Cannot find file containing module: \'adder16\'\n adder16 Add(BRout , PCout , prev ,);\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/87695634/combinational_pc.v:61: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'disp\' generates 8 bits.\n : ... In instance combinational_pc\n assign padded = disp ;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 304,788 | module | module MUX2 (
output reg [15:0] out,
input [15:0] in1,
input [15:0] in0,
input sel
);
always @(*)
begin
if(sel)
out = in1 ;
else
out = in0 ;
end
endmodule | module MUX2 (
output reg [15:0] out,
input [15:0] in1,
input [15:0] in0,
input sel
); |
always @(*)
begin
if(sel)
out = in1 ;
else
out = in0 ;
end
endmodule | 0 |
139,426 | data/full_repos/permissive/87695634/combinational_pc.v | 87,695,634 | combinational_pc.v | v | 74 | 83 | [] | [] | [] | null | line:59: before: ")" | null | 1: b'%Error: data/full_repos/permissive/87695634/combinational_pc.v:58: Cannot find file containing module: \'Reg_Cell\'\n Reg_Cell PC(Rout , clk , En , PCout);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/Reg_Cell\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/Reg_Cell.v\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/Reg_Cell.sv\n Reg_Cell\n Reg_Cell.v\n Reg_Cell.sv\n obj_dir/Reg_Cell\n obj_dir/Reg_Cell.v\n obj_dir/Reg_Cell.sv\n%Error: data/full_repos/permissive/87695634/combinational_pc.v:59: Cannot find file containing module: \'adder16\'\n adder16 Add(BRout , PCout , prev ,);\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/87695634/combinational_pc.v:61: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'disp\' generates 8 bits.\n : ... In instance combinational_pc\n assign padded = disp ;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 304,788 | module | module combinational_pc(
input [15:0] Rdest,
input jump,
input reset,
input clk ,
input En ,
input branch,
input [7:0] disp,
output [15:0] next_adress
);
localparam ZERO = 16'b0 , ONE = 16'b1;
wire [15:0] Jout , Rout , PCout , BRout , padded ;
wire[15:0] prev;
MUX2 m1(Jout,Rdest, prev , jump) ;
MUX2 m2(Rout,ZERO, Jout , reset) ;
Reg_Cell PC(Rout , clk , En , PCout);
adder16 Add(BRout , PCout , prev ,);
assign padded = disp ;
MUX2 m3(BRout, padded , ONE ,branch) ;
assign next_adress = prev ;
endmodule | module combinational_pc(
input [15:0] Rdest,
input jump,
input reset,
input clk ,
input En ,
input branch,
input [7:0] disp,
output [15:0] next_adress
); |
localparam ZERO = 16'b0 , ONE = 16'b1;
wire [15:0] Jout , Rout , PCout , BRout , padded ;
wire[15:0] prev;
MUX2 m1(Jout,Rdest, prev , jump) ;
MUX2 m2(Rout,ZERO, Jout , reset) ;
Reg_Cell PC(Rout , clk , En , PCout);
adder16 Add(BRout , PCout , prev ,);
assign padded = disp ;
MUX2 m3(BRout, padded , ONE ,branch) ;
assign next_adress = prev ;
endmodule | 0 |
139,427 | data/full_repos/permissive/87695634/Debouncer.v | 87,695,634 | Debouncer.v | v | 51 | 83 | [] | [] | [] | [(21, 31), (33, 50)] | null | data/verilator_xmls/c4b0f70c-390e-4391-b99a-65013d2093e0.xml | null | 304,789 | module | module Beh_DF (
input clk,
input button,
output reg out
);
always @(posedge clk )
begin
out = button ;
end
endmodule | module Beh_DF (
input clk,
input button,
output reg out
); |
always @(posedge clk )
begin
out = button ;
end
endmodule | 0 |
139,428 | data/full_repos/permissive/87695634/Debouncer.v | 87,695,634 | Debouncer.v | v | 51 | 83 | [] | [] | [] | [(21, 31), (33, 50)] | null | data/verilator_xmls/c4b0f70c-390e-4391-b99a-65013d2093e0.xml | null | 304,789 | module | module Debouncer(
input clk,
input button,
output out
);
wire [18:0] w;
Beh_DF df(clk,button,w[0]);
generate
genvar i;
for (i=1; i < 19; i=i+1) begin: d
Beh_DF df(clk,w[i-1],w[i]);
end
endgenerate
assign out = &w ;
endmodule | module Debouncer(
input clk,
input button,
output out
); |
wire [18:0] w;
Beh_DF df(clk,button,w[0]);
generate
genvar i;
for (i=1; i < 19; i=i+1) begin: d
Beh_DF df(clk,w[i-1],w[i]);
end
endgenerate
assign out = &w ;
endmodule | 0 |
139,429 | data/full_repos/permissive/87695634/freq_divider.v | 87,695,634 | freq_divider.v | v | 47 | 83 | [] | [] | [] | [(21, 46)] | null | data/verilator_xmls/9f55ca4a-ada8-47b4-8a34-af21196123e3.xml | null | 304,791 | module | module freq_divider_1Hz(
input in_clk,
output out_clk
);
reg out = 0 ;
integer counter = 0 ;
always @(posedge in_clk)
begin
counter = counter + 1 ;
if(counter == 100000000)
begin
counter = 0;
out = ~out;
end
else if(out === 1'bx )
begin
out = 0 ;
counter = 0 ;
end
end
assign out_clk = out;
endmodule | module freq_divider_1Hz(
input in_clk,
output out_clk
); |
reg out = 0 ;
integer counter = 0 ;
always @(posedge in_clk)
begin
counter = counter + 1 ;
if(counter == 100000000)
begin
counter = 0;
out = ~out;
end
else if(out === 1'bx )
begin
out = 0 ;
counter = 0 ;
end
end
assign out_clk = out;
endmodule | 0 |
139,430 | data/full_repos/permissive/87695634/main.v | 87,695,634 | main.v | v | 99 | 107 | [] | [] | [] | [(21, 98)] | null | null | 1: b"%Error: data/full_repos/permissive/87695634/main.v:43: Cannot find file containing module: 'button_reader'\n button_reader q(BTN,board_clk,down_par_load,stop,up_par_load,count,reset) ;\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/button_reader\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/button_reader.v\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/button_reader.sv\n button_reader\n button_reader.v\n button_reader.sv\n obj_dir/button_reader\n obj_dir/button_reader.v\n obj_dir/button_reader.sv\n%Error: data/full_repos/permissive/87695634/main.v:45: Cannot find file containing module: 'freq_divider_1Hz'\n freq_divider_1Hz f(board_clk, clk_1Hz);\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/87695634/main.v:47: Cannot find file containing module: 'combinational_pc'\n combinational_pc cmb( Rdest, jump, reset, clk_1Hz , En , branch, disp, next_adress ) ;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/87695634/main.v:49: Cannot find file containing module: 'Nexys3_sseg_writer'\n Nexys3_sseg_writer n(board_clk,n_add[3:0] ,n_add[7 :4],n_add[11 : 8],n_add[15:12],SSEG_CA,SSEG_AN );\n ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 304,794 | module | module main(
input board_clk,
input [4:0] BTN,
input [7:0] SW,
output [7:0] SSEG_CA,
output [3:0] SSEG_AN
);
wire count,stop , up_par_load , down_par_load , reset ;
wire clk_1Hz,jump ;
localparam branch = 1'b0 ;
localparam disp = 8'b0;
reg active = 1'b0;
reg r = 1'b1;
wire [15:0] n_add;
wire [15:0] next_adress;
reg [15:0] Rdest = 16'b0;
wire En;
button_reader q(BTN,board_clk,down_par_load,stop,up_par_load,count,reset) ;
freq_divider_1Hz f(board_clk, clk_1Hz);
assign En = (active & r)| jump | reset ;
combinational_pc cmb( Rdest, jump, reset, clk_1Hz , En , branch, disp, next_adress ) ;
assign n_add = next_adress - 16'b1 ;
Nexys3_sseg_writer n(board_clk,n_add[3:0] ,n_add[7 :4],n_add[11 : 8],n_add[15:12],SSEG_CA,SSEG_AN );
wire change = count | reset ;
always @(posedge count or negedge stop ) begin
if (count)
active <= 1'b1;
else
active <= 1'b0;
end
always @(posedge count or negedge reset ) begin
if (count)
r <= 1'b1;
else
r <= 1'b0;
end
assign jump = down_par_load | up_par_load;
always@( down_par_load , up_par_load)
begin
if(down_par_load)
begin
Rdest = {n_add[15:8], SW[7:0]} ;
end
else if(up_par_load)
begin
Rdest = { SW[7:0], n_add[7:0]} ;
end
end
endmodule | module main(
input board_clk,
input [4:0] BTN,
input [7:0] SW,
output [7:0] SSEG_CA,
output [3:0] SSEG_AN
); |
wire count,stop , up_par_load , down_par_load , reset ;
wire clk_1Hz,jump ;
localparam branch = 1'b0 ;
localparam disp = 8'b0;
reg active = 1'b0;
reg r = 1'b1;
wire [15:0] n_add;
wire [15:0] next_adress;
reg [15:0] Rdest = 16'b0;
wire En;
button_reader q(BTN,board_clk,down_par_load,stop,up_par_load,count,reset) ;
freq_divider_1Hz f(board_clk, clk_1Hz);
assign En = (active & r)| jump | reset ;
combinational_pc cmb( Rdest, jump, reset, clk_1Hz , En , branch, disp, next_adress ) ;
assign n_add = next_adress - 16'b1 ;
Nexys3_sseg_writer n(board_clk,n_add[3:0] ,n_add[7 :4],n_add[11 : 8],n_add[15:12],SSEG_CA,SSEG_AN );
wire change = count | reset ;
always @(posedge count or negedge stop ) begin
if (count)
active <= 1'b1;
else
active <= 1'b0;
end
always @(posedge count or negedge reset ) begin
if (count)
r <= 1'b1;
else
r <= 1'b0;
end
assign jump = down_par_load | up_par_load;
always@( down_par_load , up_par_load)
begin
if(down_par_load)
begin
Rdest = {n_add[15:8], SW[7:0]} ;
end
else if(up_par_load)
begin
Rdest = { SW[7:0], n_add[7:0]} ;
end
end
endmodule | 0 |
139,431 | data/full_repos/permissive/87695634/Nexys3_sseg_writer.v | 87,695,634 | Nexys3_sseg_writer.v | v | 120 | 83 | [] | [] | [] | [(21, 52), (57, 118)] | null | null | 1: b'%Error: data/full_repos/permissive/87695634/Nexys3_sseg_writer.v:74: Cannot find file containing module: \'freq_divider_60hz\'\n freq_divider_60hz f(clk,clk_16m) ;\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/freq_divider_60hz\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/freq_divider_60hz.v\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/freq_divider_60hz.sv\n freq_divider_60hz\n freq_divider_60hz.v\n freq_divider_60hz.sv\n obj_dir/freq_divider_60hz\n obj_dir/freq_divider_60hz.v\n obj_dir/freq_divider_60hz.sv\n%Warning-WIDTH: data/full_repos/permissive/87695634/Nexys3_sseg_writer.v:94: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance Nexys3_sseg_writer\n case(count)\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/87695634/Nexys3_sseg_writer.v:94: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h1\' generates 4 bits.\n : ... In instance Nexys3_sseg_writer\n case(count)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/87695634/Nexys3_sseg_writer.v:94: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h2\' generates 4 bits.\n : ... In instance Nexys3_sseg_writer\n case(count)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/87695634/Nexys3_sseg_writer.v:94: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h3\' generates 4 bits.\n : ... In instance Nexys3_sseg_writer\n case(count)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/87695634/Nexys3_sseg_writer.v:107: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance Nexys3_sseg_writer\n case(count)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/87695634/Nexys3_sseg_writer.v:107: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h1\' generates 4 bits.\n : ... In instance Nexys3_sseg_writer\n case(count)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/87695634/Nexys3_sseg_writer.v:107: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h2\' generates 4 bits.\n : ... In instance Nexys3_sseg_writer\n case(count)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/87695634/Nexys3_sseg_writer.v:107: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h3\' generates 4 bits.\n : ... In instance Nexys3_sseg_writer\n case(count)\n ^~~~\n%Error: Exiting due to 1 error(s), 8 warning(s)\n' | 304,795 | module | module digit_to_led(
input [3:0 ] DIGIT,
output [7:0] LED
);
reg [7:0 ] sseg_temp ;
always @ (*)
begin
case(DIGIT)
4'd0 : sseg_temp = 8'b11000000;
4'd1 : sseg_temp = 8'b11111001;
4'd2 : sseg_temp = 8'b10100100;
4'd3 : sseg_temp = 8'b10110000;
4'd4 : sseg_temp = 8'b10011001;
4'd5 : sseg_temp = 8'b10010010;
4'd6 : sseg_temp = 8'b10000010;
4'd7 : sseg_temp = 8'b11111000;
4'd8 : sseg_temp = 8'b10000000;
4'd9 : sseg_temp = 8'b10010000;
4'd10 : sseg_temp = 8'b10001000;
4'd11 : sseg_temp = 8'b10000011;
4'd12 : sseg_temp = 8'b11000110;
4'd13 : sseg_temp = 8'b10100001;
4'd14 : sseg_temp = 8'b10000110;
4'd15 : sseg_temp = 8'b10001110;
default : sseg_temp = 8'b11111111;
endcase
end
assign LED = sseg_temp ;
endmodule | module digit_to_led(
input [3:0 ] DIGIT,
output [7:0] LED
); |
reg [7:0 ] sseg_temp ;
always @ (*)
begin
case(DIGIT)
4'd0 : sseg_temp = 8'b11000000;
4'd1 : sseg_temp = 8'b11111001;
4'd2 : sseg_temp = 8'b10100100;
4'd3 : sseg_temp = 8'b10110000;
4'd4 : sseg_temp = 8'b10011001;
4'd5 : sseg_temp = 8'b10010010;
4'd6 : sseg_temp = 8'b10000010;
4'd7 : sseg_temp = 8'b11111000;
4'd8 : sseg_temp = 8'b10000000;
4'd9 : sseg_temp = 8'b10010000;
4'd10 : sseg_temp = 8'b10001000;
4'd11 : sseg_temp = 8'b10000011;
4'd12 : sseg_temp = 8'b11000110;
4'd13 : sseg_temp = 8'b10100001;
4'd14 : sseg_temp = 8'b10000110;
4'd15 : sseg_temp = 8'b10001110;
default : sseg_temp = 8'b11111111;
endcase
end
assign LED = sseg_temp ;
endmodule | 0 |
139,432 | data/full_repos/permissive/87695634/Nexys3_sseg_writer.v | 87,695,634 | Nexys3_sseg_writer.v | v | 120 | 83 | [] | [] | [] | [(21, 52), (57, 118)] | null | null | 1: b'%Error: data/full_repos/permissive/87695634/Nexys3_sseg_writer.v:74: Cannot find file containing module: \'freq_divider_60hz\'\n freq_divider_60hz f(clk,clk_16m) ;\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/freq_divider_60hz\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/freq_divider_60hz.v\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/freq_divider_60hz.sv\n freq_divider_60hz\n freq_divider_60hz.v\n freq_divider_60hz.sv\n obj_dir/freq_divider_60hz\n obj_dir/freq_divider_60hz.v\n obj_dir/freq_divider_60hz.sv\n%Warning-WIDTH: data/full_repos/permissive/87695634/Nexys3_sseg_writer.v:94: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance Nexys3_sseg_writer\n case(count)\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/87695634/Nexys3_sseg_writer.v:94: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h1\' generates 4 bits.\n : ... In instance Nexys3_sseg_writer\n case(count)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/87695634/Nexys3_sseg_writer.v:94: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h2\' generates 4 bits.\n : ... In instance Nexys3_sseg_writer\n case(count)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/87695634/Nexys3_sseg_writer.v:94: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h3\' generates 4 bits.\n : ... In instance Nexys3_sseg_writer\n case(count)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/87695634/Nexys3_sseg_writer.v:107: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance Nexys3_sseg_writer\n case(count)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/87695634/Nexys3_sseg_writer.v:107: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h1\' generates 4 bits.\n : ... In instance Nexys3_sseg_writer\n case(count)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/87695634/Nexys3_sseg_writer.v:107: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h2\' generates 4 bits.\n : ... In instance Nexys3_sseg_writer\n case(count)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/87695634/Nexys3_sseg_writer.v:107: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h3\' generates 4 bits.\n : ... In instance Nexys3_sseg_writer\n case(count)\n ^~~~\n%Error: Exiting due to 1 error(s), 8 warning(s)\n' | 304,795 | module | module Nexys3_sseg_writer(
input clk,
input [3:0] digit0,
input [3:0] digit1,
input [3:0] digit2,
input [3:0] digit3,
output reg [7:0] SSEG_CA,
output reg [3:0] SSEG_AN
);
wire [7 : 0] led0 , led1 , led2, led3 ;
wire clk_16m;
integer count = 0;
freq_divider_60hz f(clk,clk_16m) ;
(*KEEP = "TRUE"*)digit_to_led d0(digit0, led0 ) ;
(*KEEP = "TRUE"*)digit_to_led d1(digit1, led1 ) ;
(*KEEP = "TRUE"*)digit_to_led d2(digit2, led2 ) ;
(*KEEP = "TRUE"*)digit_to_led d3(digit3, led3 ) ;
always @ (posedge clk_16m)
begin
if (count < 4)
begin
count = count + 1;
end
else
begin count = 0 ; end
end
always @ (*)
begin
case(count)
4'd0 : SSEG_AN = 4'b0111;
4'd1 : SSEG_AN = 4'b1011;
4'd2 : SSEG_AN = 4'b1101;
4'd3 : SSEG_AN = 4'b1110;
default: SSEG_AN = 4'b1111;
endcase
end
always @ (*)
begin
case(count)
4'd0 : SSEG_CA = led0;
4'd1 : SSEG_CA = led1;
4'd2 : SSEG_CA = led2;
4'd3 : SSEG_CA = led3;
endcase
end
endmodule | module Nexys3_sseg_writer(
input clk,
input [3:0] digit0,
input [3:0] digit1,
input [3:0] digit2,
input [3:0] digit3,
output reg [7:0] SSEG_CA,
output reg [3:0] SSEG_AN
); |
wire [7 : 0] led0 , led1 , led2, led3 ;
wire clk_16m;
integer count = 0;
freq_divider_60hz f(clk,clk_16m) ;
(*KEEP = "TRUE"*)digit_to_led d0(digit0, led0 ) ;
(*KEEP = "TRUE"*)digit_to_led d1(digit1, led1 ) ;
(*KEEP = "TRUE"*)digit_to_led d2(digit2, led2 ) ;
(*KEEP = "TRUE"*)digit_to_led d3(digit3, led3 ) ;
always @ (posedge clk_16m)
begin
if (count < 4)
begin
count = count + 1;
end
else
begin count = 0 ; end
end
always @ (*)
begin
case(count)
4'd0 : SSEG_AN = 4'b0111;
4'd1 : SSEG_AN = 4'b1011;
4'd2 : SSEG_AN = 4'b1101;
4'd3 : SSEG_AN = 4'b1110;
default: SSEG_AN = 4'b1111;
endcase
end
always @ (*)
begin
case(count)
4'd0 : SSEG_CA = led0;
4'd1 : SSEG_CA = led1;
4'd2 : SSEG_CA = led2;
4'd3 : SSEG_CA = led3;
endcase
end
endmodule | 0 |
139,433 | data/full_repos/permissive/87695634/Reg_Cell.v | 87,695,634 | Reg_Cell.v | v | 37 | 83 | [] | [] | [] | [(21, 36)] | null | null | 1: b"%Error: data/full_repos/permissive/87695634/Reg_Cell.v:31: Cannot find file containing module: 'DFF'\n DFF df(clk,En,in[i],out[i]);\n ^~~\n ... Looked in:\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/DFF\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/DFF.v\n data/full_repos/permissive/87695634,data/full_repos/permissive/87695634/DFF.sv\n DFF\n DFF.v\n DFF.sv\n obj_dir/DFF\n obj_dir/DFF.v\n obj_dir/DFF.sv\n%Error: Exiting due to 1 error(s)\n" | 304,796 | module | module Reg_Cell(
input [15:0] in,
input clk,
input En,
output [15:0] out
);
generate
genvar i;
for (i=0; i < 16; i=i+1) begin: d
DFF df(clk,En,in[i],out[i]);
end
endgenerate
endmodule | module Reg_Cell(
input [15:0] in,
input clk,
input En,
output [15:0] out
); |
generate
genvar i;
for (i=0; i < 16; i=i+1) begin: d
DFF df(clk,En,in[i],out[i]);
end
endgenerate
endmodule | 0 |
139,434 | data/full_repos/permissive/87695634/Shift16.v | 87,695,634 | Shift16.v | v | 58 | 83 | [] | [] | [] | [(23, 56)] | null | data/verilator_xmls/697a0aa2-1826-4bb9-998b-54cd969c80fc.xml | null | 304,797 | module | module Shift16(
input [15:0] num,
input [5:0] count,
input op_type,
output reg[15:0] o
);
reg[15:0] out = 16'h0000;
reg[5:0] lim = 6'b0 ;
integer k;
always @ (*)
begin : a
integer i;
if(count[5])
begin
lim = ~count+ 6'b1 ;
if(op_type)
out = num>>lim ;
else
out = $signed(num)>>>lim;
end
else
begin
if(op_type)
out = num<< count;
else
out = $signed(num) <<< count;
end
o = out ;
end
endmodule | module Shift16(
input [15:0] num,
input [5:0] count,
input op_type,
output reg[15:0] o
); |
reg[15:0] out = 16'h0000;
reg[5:0] lim = 6'b0 ;
integer k;
always @ (*)
begin : a
integer i;
if(count[5])
begin
lim = ~count+ 6'b1 ;
if(op_type)
out = num>>lim ;
else
out = $signed(num)>>>lim;
end
else
begin
if(op_type)
out = num<< count;
else
out = $signed(num) <<< count;
end
o = out ;
end
endmodule | 0 |
139,435 | data/full_repos/permissive/87695634/test_PC.v | 87,695,634 | test_PC.v | v | 114 | 137 | [] | [] | [] | [(25, 112)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/87695634/test_PC.v:54: Unsupported: Ignoring delay on this delayed statement.\n #0.5; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/87695634/test_PC.v:71: Unsupported or unknown PLI call: $monitor\n $monitor( "%g jump= %b reset= %b clk= %b Rdest = %h branch = %b disp = %h ", $time, jump, reset,clk, Rdest , branch , disp );\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_PC.v:72: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_PC.v:75: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_PC.v:78: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_PC.v:82: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_PC.v:86: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_PC.v:90: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_PC.v:93: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_PC.v:97: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_PC.v:101: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_PC.v:105: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: Exiting due to 1 error(s), 11 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,798 | module | module test_PC;
reg [15:0] Rdest;
reg jump;
reg reset;
reg clk;
reg En;
reg branch;
reg [7:0] disp;
wire [15:0] next_adress;
combinational_pc uut (
.Rdest(Rdest),
.jump(jump),
.reset(reset),
.clk(clk),
.En(En),
.branch(branch),
.disp(disp),
.next_adress(next_adress)
);
always begin
clk = ~clk ;
#0.5;
if (clk == 0)
$display("next_adress = %h ", next_adress);
end
initial begin
Rdest = 0;
jump = 0;
reset = 0;
clk = 0;
En = 1;
branch = 0;
disp = 0;
$display("Enable is always one" );
$monitor( "%g jump= %b reset= %b clk= %b Rdest = %h branch = %b disp = %h ", $time, jump, reset,clk, Rdest , branch , disp );
#1;
reset = 1;
$display("First reset" );
#1;
reset = 0;
Rdest = 16'hF02A;
#10;
$display("Try jump" );
jump = 1;
#1;
jump = 0;
disp = 8'h05;
#10;
$display("Try branch" );
branch = 1;
#5;
branch = 0;
#10;
$display("Try reset " );
reset = 1;
#1;
reset = 0;
Rdest = 16'hAAAA;
#10;
$display("Try jump again" );
jump = 1;
#1;
jump = 0;
end
endmodule | module test_PC; |
reg [15:0] Rdest;
reg jump;
reg reset;
reg clk;
reg En;
reg branch;
reg [7:0] disp;
wire [15:0] next_adress;
combinational_pc uut (
.Rdest(Rdest),
.jump(jump),
.reset(reset),
.clk(clk),
.En(En),
.branch(branch),
.disp(disp),
.next_adress(next_adress)
);
always begin
clk = ~clk ;
#0.5;
if (clk == 0)
$display("next_adress = %h ", next_adress);
end
initial begin
Rdest = 0;
jump = 0;
reset = 0;
clk = 0;
En = 1;
branch = 0;
disp = 0;
$display("Enable is always one" );
$monitor( "%g jump= %b reset= %b clk= %b Rdest = %h branch = %b disp = %h ", $time, jump, reset,clk, Rdest , branch , disp );
#1;
reset = 1;
$display("First reset" );
#1;
reset = 0;
Rdest = 16'hF02A;
#10;
$display("Try jump" );
jump = 1;
#1;
jump = 0;
disp = 8'h05;
#10;
$display("Try branch" );
branch = 1;
#5;
branch = 0;
#10;
$display("Try reset " );
reset = 1;
#1;
reset = 0;
Rdest = 16'hAAAA;
#10;
$display("Try jump again" );
jump = 1;
#1;
jump = 0;
end
endmodule | 0 |
139,436 | data/full_repos/permissive/87695634/test_shifter.v | 87,695,634 | test_shifter.v | v | 259 | 110 | [] | [] | [] | [(25, 257)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:50: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/87695634/test_shifter.v:51: Unsupported or unknown PLI call: $monitor\n $monitor( "%g num= %b count= %d o= %b optype =%d ", $time, num, $signed(count),o , op_type);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:54: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:60: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:63: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:66: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:69: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:72: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:75: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:78: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:81: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:84: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:87: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:90: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:93: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:96: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:99: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:102: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:105: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:108: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:111: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:114: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:117: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:120: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:123: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:126: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:129: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:132: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:135: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:138: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:141: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:144: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:147: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:150: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:155: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:161: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:164: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:167: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:170: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:173: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:176: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:179: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:182: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:185: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:188: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:191: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:194: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:197: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:200: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:203: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:206: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:209: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:212: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:215: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:218: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:221: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:224: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:227: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:230: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:233: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:236: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:239: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:242: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:245: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:248: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/87695634/test_shifter.v:251: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Error: Exiting due to 1 error(s), 65 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,799 | module | module test_shifter;
reg [15:0] num;
reg [5:0] count;
reg op_type;
wire [15:0] o;
Shift16 uut (
.num(num),
.count(count),
.op_type(op_type),
.o(o)
);
initial begin
num = 0;
count = 0;
op_type = 0;
#100;
$monitor( "%g num= %b count= %d o= %b optype =%d ", $time, num, $signed(count),o , op_type);
$display("Arithmatic Shifter" );
#200;
num = 16'b1101001010110110;
count =-16 ;
#200;
count =-15 ;
#200;
count= -14 ;
#200;
count =-13 ;
#200;
count =-12 ;
#200;
count =-11 ;
#200;
count= -10 ;
#200;
count= -9 ;
#200;
count= -8 ;
#200;
count= -7 ;
#200;
count= -6 ;
#200;
count= -5 ;
#200;
count= -4 ;
#200;
count= -3 ;
#200;
count= -2 ;
#200;
count= -1 ;
#200;
count= 0;
#200;
count= 1;
#200;
count= 2;
#200;
count= 3 ;
#200;
count= 4 ;
#200;
count= 5 ;
#200;
count= 6 ;
#200;
count= 7 ;
#200;
count= 8 ;
#200;
count= 9 ;
#200;
count= 10 ;
#200;
count= 11 ;
#200;
count= 12 ;
#200;
count= 13 ;
#200;
count= 14 ;
#200;
count= 15 ;
#200;
$display("Logical Shifter" );
num = 16'b1101001010110110;
op_type = 1'b1;
count =-16 ;
#200;
count =-15 ;
#200;
count= -14 ;
#200;
count =-13 ;
#200;
count =-12 ;
#200;
count =-11 ;
#200;
count= -10 ;
#200;
count= -9 ;
#200;
count= -8 ;
#200;
count= -7 ;
#200;
count= -6 ;
#200;
count= -5 ;
#200;
count= -4 ;
#200;
count= -3 ;
#200;
count= -2 ;
#200;
count= -1 ;
#200;
count= 0;
#200;
count= 1;
#200;
count= 2;
#200;
count= 3 ;
#200;
count= 4 ;
#200;
count= 5 ;
#200;
count= 6 ;
#200;
count= 7 ;
#200;
count= 8 ;
#200;
count= 9 ;
#200;
count= 10 ;
#200;
count= 11 ;
#200;
count= 12 ;
#200;
count= 13 ;
#200;
count= 14 ;
#200;
count= 15 ;
end
endmodule | module test_shifter; |
reg [15:0] num;
reg [5:0] count;
reg op_type;
wire [15:0] o;
Shift16 uut (
.num(num),
.count(count),
.op_type(op_type),
.o(o)
);
initial begin
num = 0;
count = 0;
op_type = 0;
#100;
$monitor( "%g num= %b count= %d o= %b optype =%d ", $time, num, $signed(count),o , op_type);
$display("Arithmatic Shifter" );
#200;
num = 16'b1101001010110110;
count =-16 ;
#200;
count =-15 ;
#200;
count= -14 ;
#200;
count =-13 ;
#200;
count =-12 ;
#200;
count =-11 ;
#200;
count= -10 ;
#200;
count= -9 ;
#200;
count= -8 ;
#200;
count= -7 ;
#200;
count= -6 ;
#200;
count= -5 ;
#200;
count= -4 ;
#200;
count= -3 ;
#200;
count= -2 ;
#200;
count= -1 ;
#200;
count= 0;
#200;
count= 1;
#200;
count= 2;
#200;
count= 3 ;
#200;
count= 4 ;
#200;
count= 5 ;
#200;
count= 6 ;
#200;
count= 7 ;
#200;
count= 8 ;
#200;
count= 9 ;
#200;
count= 10 ;
#200;
count= 11 ;
#200;
count= 12 ;
#200;
count= 13 ;
#200;
count= 14 ;
#200;
count= 15 ;
#200;
$display("Logical Shifter" );
num = 16'b1101001010110110;
op_type = 1'b1;
count =-16 ;
#200;
count =-15 ;
#200;
count= -14 ;
#200;
count =-13 ;
#200;
count =-12 ;
#200;
count =-11 ;
#200;
count= -10 ;
#200;
count= -9 ;
#200;
count= -8 ;
#200;
count= -7 ;
#200;
count= -6 ;
#200;
count= -5 ;
#200;
count= -4 ;
#200;
count= -3 ;
#200;
count= -2 ;
#200;
count= -1 ;
#200;
count= 0;
#200;
count= 1;
#200;
count= 2;
#200;
count= 3 ;
#200;
count= 4 ;
#200;
count= 5 ;
#200;
count= 6 ;
#200;
count= 7 ;
#200;
count= 8 ;
#200;
count= 9 ;
#200;
count= 10 ;
#200;
count= 11 ;
#200;
count= 12 ;
#200;
count= 13 ;
#200;
count= 14 ;
#200;
count= 15 ;
end
endmodule | 0 |
139,437 | data/full_repos/permissive/87717764/tp/references/arquivos/displayDecoder.v | 87,717,764 | displayDecoder.v | v | 22 | 52 | [] | [] | [] | [(1, 21)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/87717764/tp/references/arquivos/displayDecoder.v:4: Little bit endian vector: MSB < LSB of bit range: 0:6\n output reg [0:6] saida\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 304,800 | module | module displayDecoder(
input[2:0] entrada,
output reg [0:6] saida
);
always@(entrada)begin
case(entrada[2:0])
3'b000:saida = 7'b0000001;
3'b001:saida = 7'b1001111;
3'b010:saida = 7'b0010010;
3'b011:saida = 7'b0000110;
3'b100:saida = 7'b1001100;
3'b101:saida = 7'b0100100;
3'b110:saida = 7'b0100000;
3'b111:saida = 7'b0001111;
default: saida = 7'b0000000;
endcase
end
endmodule | module displayDecoder(
input[2:0] entrada,
output reg [0:6] saida
); |
always@(entrada)begin
case(entrada[2:0])
3'b000:saida = 7'b0000001;
3'b001:saida = 7'b1001111;
3'b010:saida = 7'b0010010;
3'b011:saida = 7'b0000110;
3'b100:saida = 7'b1001100;
3'b101:saida = 7'b0100100;
3'b110:saida = 7'b0100000;
3'b111:saida = 7'b0001111;
default: saida = 7'b0000000;
endcase
end
endmodule | 0 |
139,438 | data/full_repos/permissive/87717764/tp/references/arquivos/mips32.v | 87,717,764 | mips32.v | v | 169 | 67 | [] | [] | [] | [(3, 125)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/87717764/tp/references/arquivos/mips32.v:9: Little bit endian vector: MSB < LSB of bit range: 0:6\n output[0:6] HEX0, \n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/87717764/tp/references/arquivos/mips32.v:10: Little bit endian vector: MSB < LSB of bit range: 0:6\n output[0:6] HEX1 \n ^\n%Error: data/full_repos/permissive/87717764/tp/references/arquivos/mips32.v:34: Cannot find file containing module: \'mem_inst\'\nmem_inst mem_i(.address(PC),.clock(clk[25]),.q(out_mem_inst));\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87717764/tp/references/arquivos,data/full_repos/permissive/87717764/mem_inst\n data/full_repos/permissive/87717764/tp/references/arquivos,data/full_repos/permissive/87717764/mem_inst.v\n data/full_repos/permissive/87717764/tp/references/arquivos,data/full_repos/permissive/87717764/mem_inst.sv\n mem_inst\n mem_inst.v\n mem_inst.sv\n obj_dir/mem_inst\n obj_dir/mem_inst.v\n obj_dir/mem_inst.sv\n%Error: data/full_repos/permissive/87717764/tp/references/arquivos/mips32.v:36: Cannot find file containing module: \'displayDecoder\'\ndisplayDecoder DP7_0(.entrada(registers[0][2:0]),.saida(HEX0));\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/87717764/tp/references/arquivos/mips32.v:37: Cannot find file containing module: \'displayDecoder\'\ndisplayDecoder DP7_1(.entrada(FSM),.saida(HEX1));\n^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/references/arquivos/mips32.v:57: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance mips32\n FSM2 = 4\'h0000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/references/arquivos/mips32.v:67: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n : ... In instance mips32\n registers[0] = 4\'h0001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/references/arquivos/mips32.v:77: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance mips32\n FSM2 = 4\'h0000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/references/arquivos/mips32.v:85: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n : ... In instance mips32\n FSM2 = 4\'h0001; \n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/references/arquivos/mips32.v:95: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n : ... In instance mips32\n if(FSM2 == 4\'h0001) \n ^~\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/references/arquivos/mips32.v:112: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n : ... In instance mips32\n if(FSM2 == 4\'h0001) \n ^~\n%Error: Exiting due to 3 error(s), 8 warning(s)\n' | 304,802 | module | module mips32(
input CLOCK_50,
input[3:0] KEY,
output[8:0] LEDG,
output[0:6] HEX0,
output[0:6] HEX1
);
reg [31:0] clk;
reg [2:0] FSM;
reg [31:0] FSM2;
integer i;
reg [9:0] PC;
reg [31:0] IR;
reg [31:0] registers [31:0];
reg [31:0] saida_ula;
reg [31:0] A;
reg [31:0] B;
wire [31:0] out_mem_inst;
mem_inst mem_i(.address(PC),.clock(clk[25]),.q(out_mem_inst));
displayDecoder DP7_0(.entrada(registers[0][2:0]),.saida(HEX0));
displayDecoder DP7_1(.entrada(FSM),.saida(HEX1));
assign LEDG[0] = clk[25];
always@(posedge CLOCK_50)begin
clk = clk + 1;
end
always@(posedge clk[25])begin
if(KEY[0] == 0)
begin
FSM = 3'b001;
FSM2 = 4'h0000;
PC = 10'b0;
IR = 32'b0;
for(i = 0; i < 32; i = i + 1)
begin
registers[i] = 32'b0;
end
registers[0] = 4'h0001;
end
else
begin
if(FSM == 3'b001)
begin
PC = PC + 1;
IR = out_mem_inst;
FSM = 3'b010;
FSM2 = 4'h0000;
end
else if(FSM == 3'b010)
begin
if(IR[31:26] == 6'b000000 && IR[5:0] == 6'b100000)
begin
FSM2 = 4'h0001;
end
A = registers[IR[25:21]];
B = registers[IR[20:16]];
FSM = 3'b011;
end
else if(FSM == 3'b011)
begin
if(FSM2 == 4'h0001)
begin
saida_ula = A + B;
end
FSM = 3'b100;
end
else if(FSM == 3'b100)
begin
FSM = 3'b101;
end
else if(FSM == 3'b101)
begin
if(FSM2 == 4'h0001)
begin
registers[IR[15:11]] = saida_ula;
end
FSM = 3'b001;
end
end
end
endmodule | module mips32(
input CLOCK_50,
input[3:0] KEY,
output[8:0] LEDG,
output[0:6] HEX0,
output[0:6] HEX1
); |
reg [31:0] clk;
reg [2:0] FSM;
reg [31:0] FSM2;
integer i;
reg [9:0] PC;
reg [31:0] IR;
reg [31:0] registers [31:0];
reg [31:0] saida_ula;
reg [31:0] A;
reg [31:0] B;
wire [31:0] out_mem_inst;
mem_inst mem_i(.address(PC),.clock(clk[25]),.q(out_mem_inst));
displayDecoder DP7_0(.entrada(registers[0][2:0]),.saida(HEX0));
displayDecoder DP7_1(.entrada(FSM),.saida(HEX1));
assign LEDG[0] = clk[25];
always@(posedge CLOCK_50)begin
clk = clk + 1;
end
always@(posedge clk[25])begin
if(KEY[0] == 0)
begin
FSM = 3'b001;
FSM2 = 4'h0000;
PC = 10'b0;
IR = 32'b0;
for(i = 0; i < 32; i = i + 1)
begin
registers[i] = 32'b0;
end
registers[0] = 4'h0001;
end
else
begin
if(FSM == 3'b001)
begin
PC = PC + 1;
IR = out_mem_inst;
FSM = 3'b010;
FSM2 = 4'h0000;
end
else if(FSM == 3'b010)
begin
if(IR[31:26] == 6'b000000 && IR[5:0] == 6'b100000)
begin
FSM2 = 4'h0001;
end
A = registers[IR[25:21]];
B = registers[IR[20:16]];
FSM = 3'b011;
end
else if(FSM == 3'b011)
begin
if(FSM2 == 4'h0001)
begin
saida_ula = A + B;
end
FSM = 3'b100;
end
else if(FSM == 3'b100)
begin
FSM = 3'b101;
end
else if(FSM == 3'b101)
begin
if(FSM2 == 4'h0001)
begin
registers[IR[15:11]] = saida_ula;
end
FSM = 3'b001;
end
end
end
endmodule | 0 |
139,439 | data/full_repos/permissive/87717764/tp/references/mips/displayDecoder.v | 87,717,764 | displayDecoder.v | v | 84 | 82 | [] | [] | [] | [(1, 69)] | null | data/verilator_xmls/d3f30e60-8dd0-400e-9e5d-d57776407e4f.xml | null | 304,803 | module | module displayDecoder(
input[31:0] entrada,
input zero,
output reg [6:0] saida0, saida1, saida2, saida3, saida4, saida5, saida6, saida7
);
always@(entrada)
begin
saida0[5] = ~(entrada[0]);
saida0[0] = ~(entrada[1]);
saida0[1] = ~(entrada[2]);
saida0[2] = ~(entrada[3]);
saida0[3] = ~(entrada[4]);
saida0[4] = ~(entrada[5]);
saida0[6] = ~(entrada[6]);
saida1[5] = ~(entrada[7]);
saida1[0] = ~(entrada[8]);
saida1[1] = ~(entrada[9]);
saida1[2] = ~(entrada[10]);
saida1[3] = ~(entrada[11]);
saida1[4] = ~(entrada[12]);
saida1[6] = ~(entrada[13]);
saida2[5] = ~(entrada[14]);
saida2[0] = ~(entrada[15]);
saida2[1] = ~(entrada[16]);
saida2[2] = ~(entrada[17]);
saida2[3] = ~(entrada[18]);
saida2[4] = ~(entrada[19]);
saida2[6] = ~(entrada[20]);
saida3[5] = ~(entrada[21]);
saida3[0] = ~(entrada[22]);
saida3[1] = ~(entrada[23]);
saida3[2] = ~(entrada[24]);
saida3[3] = ~(entrada[25]);
saida3[4] = ~(entrada[26]);
saida3[6] = ~(entrada[27]);
saida4[5] = ~(entrada[28]);
saida4[0] = ~(entrada[29]);
saida4[1] = ~(entrada[30]);
saida4[2] = ~(entrada[31]);
saida4[3] = ~(zero);
saida4[4] = 1'b1;
saida4[6] = 1'b1;
saida5[5] = 1'b1;
saida5[0] = 1'b1;
saida5[1] = 1'b1;
saida5[2] = 1'b1;
saida5[3] = 1'b1;
saida5[4] = 1'b1;
saida5[6] = 1'b1;
saida6[5] = 1'b1;
saida6[0] = 1'b1;
saida6[1] = 1'b1;
saida6[2] = 1'b1;
saida6[3] = 1'b1;
saida6[4] = 1'b1;
saida6[6] = 1'b1;
saida7[5] = 1'b1;
saida7[0] = 1'b1;
saida7[1] = 1'b1;
saida7[2] = 1'b1;
saida7[3] = 1'b1;
saida7[4] = 1'b1;
saida7[6] = 1'b1;
end
endmodule | module displayDecoder(
input[31:0] entrada,
input zero,
output reg [6:0] saida0, saida1, saida2, saida3, saida4, saida5, saida6, saida7
); |
always@(entrada)
begin
saida0[5] = ~(entrada[0]);
saida0[0] = ~(entrada[1]);
saida0[1] = ~(entrada[2]);
saida0[2] = ~(entrada[3]);
saida0[3] = ~(entrada[4]);
saida0[4] = ~(entrada[5]);
saida0[6] = ~(entrada[6]);
saida1[5] = ~(entrada[7]);
saida1[0] = ~(entrada[8]);
saida1[1] = ~(entrada[9]);
saida1[2] = ~(entrada[10]);
saida1[3] = ~(entrada[11]);
saida1[4] = ~(entrada[12]);
saida1[6] = ~(entrada[13]);
saida2[5] = ~(entrada[14]);
saida2[0] = ~(entrada[15]);
saida2[1] = ~(entrada[16]);
saida2[2] = ~(entrada[17]);
saida2[3] = ~(entrada[18]);
saida2[4] = ~(entrada[19]);
saida2[6] = ~(entrada[20]);
saida3[5] = ~(entrada[21]);
saida3[0] = ~(entrada[22]);
saida3[1] = ~(entrada[23]);
saida3[2] = ~(entrada[24]);
saida3[3] = ~(entrada[25]);
saida3[4] = ~(entrada[26]);
saida3[6] = ~(entrada[27]);
saida4[5] = ~(entrada[28]);
saida4[0] = ~(entrada[29]);
saida4[1] = ~(entrada[30]);
saida4[2] = ~(entrada[31]);
saida4[3] = ~(zero);
saida4[4] = 1'b1;
saida4[6] = 1'b1;
saida5[5] = 1'b1;
saida5[0] = 1'b1;
saida5[1] = 1'b1;
saida5[2] = 1'b1;
saida5[3] = 1'b1;
saida5[4] = 1'b1;
saida5[6] = 1'b1;
saida6[5] = 1'b1;
saida6[0] = 1'b1;
saida6[1] = 1'b1;
saida6[2] = 1'b1;
saida6[3] = 1'b1;
saida6[4] = 1'b1;
saida6[6] = 1'b1;
saida7[5] = 1'b1;
saida7[0] = 1'b1;
saida7[1] = 1'b1;
saida7[2] = 1'b1;
saida7[3] = 1'b1;
saida7[4] = 1'b1;
saida7[6] = 1'b1;
end
endmodule | 0 |
139,440 | data/full_repos/permissive/87717764/tp/src/entrega1/TP-OC2_Entrega1_Grupo3/teste-modelsim/code/tp.v | 87,717,764 | tp.v | v | 377 | 100 | [] | [] | [] | [(1, 376)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega1/TP-OC2_Entrega1_Grupo3/teste-modelsim/code/tp.v:9: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance tp\nreg [3:0] KEY = 3\'b000; \n ^~~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/87717764/tp/src/entrega1/TP-OC2_Entrega1_Grupo3/teste-modelsim/code/tp.v:28: Cannot find file containing module: \'mem_inst\'\nmem_inst mem_i(.address(pc),.clock(clk[0]),.q(out_mem_inst));\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87717764/tp/src/entrega1/TP-OC2_Entrega1_Grupo3/teste-modelsim/code,data/full_repos/permissive/87717764/mem_inst\n data/full_repos/permissive/87717764/tp/src/entrega1/TP-OC2_Entrega1_Grupo3/teste-modelsim/code,data/full_repos/permissive/87717764/mem_inst.v\n data/full_repos/permissive/87717764/tp/src/entrega1/TP-OC2_Entrega1_Grupo3/teste-modelsim/code,data/full_repos/permissive/87717764/mem_inst.sv\n mem_inst\n mem_inst.v\n mem_inst.sv\n obj_dir/mem_inst\n obj_dir/mem_inst.v\n obj_dir/mem_inst.sv\n%Error: data/full_repos/permissive/87717764/tp/src/entrega1/TP-OC2_Entrega1_Grupo3/teste-modelsim/code/tp.v:30: Cannot find file containing module: \'displayDecoder\'\ndisplayDecoder DP7_0(.entrada(registers[0][2:0]),.saida(HEX0));\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/87717764/tp/src/entrega1/TP-OC2_Entrega1_Grupo3/teste-modelsim/code/tp.v:31: Cannot find file containing module: \'displayDecoder\'\ndisplayDecoder DP7_1(.entrada(FSM),.saida(HEX1));\n^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega1/TP-OC2_Entrega1_Grupo3/teste-modelsim/code/tp.v:273: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'imm\' generates 16 bits.\n : ... In instance tp\n aluOutput = A + imm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega1/TP-OC2_Entrega1_Grupo3/teste-modelsim/code/tp.v:278: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'imm\' generates 16 bits.\n : ... In instance tp\n aluOutput = A + imm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega1/TP-OC2_Entrega1_Grupo3/teste-modelsim/code/tp.v:288: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'imm\' generates 16 bits.\n : ... In instance tp\n aluOutput = A + imm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega1/TP-OC2_Entrega1_Grupo3/teste-modelsim/code/tp.v:298: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'imm\' generates 16 bits.\n : ... In instance tp\n aluOutput = A & imm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega1/TP-OC2_Entrega1_Grupo3/teste-modelsim/code/tp.v:308: Operator OR expects 32 bits on the RHS, but RHS\'s VARREF \'imm\' generates 16 bits.\n : ... In instance tp\n aluOutput = A | imm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega1/TP-OC2_Entrega1_Grupo3/teste-modelsim/code/tp.v:334: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'pc\' generates 10 bits.\n : ... In instance tp\n aluOutput = (pc + 1) + imm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega1/TP-OC2_Entrega1_Grupo3/teste-modelsim/code/tp.v:334: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'imm\' generates 16 bits.\n : ... In instance tp\n aluOutput = (pc + 1) + imm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega1/TP-OC2_Entrega1_Grupo3/teste-modelsim/code/tp.v:349: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'pc\' generates 10 bits.\n : ... In instance tp\n aluOutput = (pc + 1) + imm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega1/TP-OC2_Entrega1_Grupo3/teste-modelsim/code/tp.v:349: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'imm\' generates 16 bits.\n : ... In instance tp\n aluOutput = (pc + 1) + imm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega1/TP-OC2_Entrega1_Grupo3/teste-modelsim/code/tp.v:361: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'jmem\' generates 26 bits.\n : ... In instance tp\n aluOutput = jmem << 2;\n ^~\n%Error: Exiting due to 3 error(s), 11 warning(s)\n' | 304,816 | module | module tp(
input CLOCK_50,
output [8:0] LEDG,
output [6:0] HEX0,
output [6:0] HEX1
);
reg [3:0] KEY = 3'b000;
reg [31:0] clk = 32'd0;
reg [2:0] FSM;
reg [15:0] FSM2;
integer i;
reg [9:0] pc;
reg [31:0] instruction;
reg [31:0] registers [31:0];
reg [31:0] aluOutput;
reg Zero;
reg [31:0] A;
reg [31:0] B;
reg [15:0] imm;
reg [25:0] jmem;
wire [31:0] out_mem_inst;
mem_inst mem_i(.address(pc),.clock(clk[0]),.q(out_mem_inst));
displayDecoder DP7_0(.entrada(registers[0][2:0]),.saida(HEX0));
displayDecoder DP7_1(.entrada(FSM),.saida(HEX1));
assign LEDG[0] = clk[1];
always@(posedge CLOCK_50)
begin
clk = clk + 1;
end
always@(posedge clk[1])
begin
if(KEY[0] == 0)
begin
FSM = 3'b001;
FSM2 = 16'h0000;
aluOutput = 32'd0;
Zero = 1'b0;
pc = 10'd0;
instruction = 32'd0;
for(i = 0; i < 32; i = i + 1)
begin
registers[i] = i;
end
KEY[0] = 1;
end
else
begin
if(FSM == 3'b001)
begin
pc = pc + 1;
instruction = out_mem_inst;
FSM = 3'd2;
FSM2 = 16'h0000;
end
else if(FSM == 3'b010)
begin
if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100000)
begin
FSM2 = 16'h0001;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100010)
begin
FSM2 = 16'h0002;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100100)
begin
FSM2 = 16'h0003;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100111)
begin
FSM2 = 16'h0004;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100110)
begin
FSM2 = 16'h0005;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b101010)
begin
FSM2 = 16'h0006;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b000000)
begin
FSM2 = 16'h0007;
A = registers[instruction[25:21]];
B = registers[instruction[10:6]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b000010)
begin
FSM2 = 16'h0008;
A = registers[instruction[25:21]];
B = registers[instruction[10:6]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100101)
begin
FSM2 = 16'h0009;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b001000)
begin
FSM2 = 16'h000A;
A = registers[instruction[25:21]];
imm = instruction[15:0];
end
else if(instruction[31:26] == 6'b100011)
begin
FSM2 = 16'h000B;
A = registers[instruction[25:21]];
imm = instruction[15:0];
end
else if(instruction[31:26] == 6'b101011)
begin
FSM2 = 16'h000C;
A = registers[instruction[20:16]];
imm = instruction[15:0];
end
else if(instruction[31:26] == 6'b001100)
begin
FSM2 = 16'h000D;
A = registers[instruction[25:21]];
imm = instruction[15:0];
end
else if(instruction[31:26] == 6'b001101)
begin
FSM2 = 16'h000E;
A = registers[instruction[25:21]];
imm = instruction[15:0];
end
else if(instruction[31:26] == 6'b001010)
begin
FSM2 = 16'h000F;
A = registers[instruction[25:21]];
imm = instruction[15:0];
end
else if(instruction[31:26] == 6'b000100)
begin
FSM2 = 16'h0010;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
imm = instruction[15:0];
end
else if(instruction[31:26] == 6'b000101)
begin
FSM2 = 16'h0011;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
imm = instruction[15:0];
end
else if(instruction[31:26] == 6'b000010)
begin
FSM2 = 16'h0012;
jmem = instruction[25:0];
end
FSM = 3'b011;
end
else if(FSM == 3'b011)
begin
if(FSM2 == 16'h0001)
begin
aluOutput = A + B;
end
if(FSM2 == 16'h0002)
begin
aluOutput = A - B;
end
if(FSM2 == 16'h0003)
begin
aluOutput = A & B;
end
if(FSM2 == 16'h0004)
begin
aluOutput = ~(A | B);
end
if(FSM2 == 16'h0005)
begin
aluOutput = A ^ B;
end
if(FSM2 == 16'h0006)
begin
if(A < B)
begin
aluOutput = 32'd1;
end
else
begin
aluOutput = 32'd0;
end
end
if(FSM2 == 16'h0007)
begin
aluOutput = A << B;
end
if(FSM2 == 16'h0008)
begin
aluOutput = A >> B;
end
if(FSM2 == 16'h0009)
begin
aluOutput = A | B;
end
if(FSM2 == 16'h000A)
begin
aluOutput = A + imm;
end
if(FSM2 == 16'h000B)
begin
aluOutput = A + imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000C)
begin
aluOutput = A + imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000D)
begin
aluOutput = A & imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000E)
begin
aluOutput = A | imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000F)
begin
if(A < imm)
begin
aluOutput = 32'd1;
end
else
begin
aluOutput = 32'd0;
end
end
if(FSM2 == 16'h0010)
begin
if((A - B) == 0)
begin
Zero = 1'b1;
aluOutput = (pc + 1) + imm;
end
else
begin
Zero = 1'b0;
aluOutput = 0;
end
end
if(FSM2 == 16'h0011)
begin
if((A - B) != 0)
begin
Zero = 1'b1;
aluOutput = (pc + 1) + imm;
end
else
begin
Zero = 1'b0;
aluOutput = 0;
end
end
if(FSM2 == 16'h0012)
begin
aluOutput = jmem << 2;
pc = pc + 1;
aluOutput[28] = pc[6];
aluOutput[29] = pc[7];
aluOutput[30] = pc[8];
aluOutput[31] = pc[9];
pc = pc - 1;
end
FSM = 3'b001;
end
end
end
endmodule | module tp(
input CLOCK_50,
output [8:0] LEDG,
output [6:0] HEX0,
output [6:0] HEX1
); |
reg [3:0] KEY = 3'b000;
reg [31:0] clk = 32'd0;
reg [2:0] FSM;
reg [15:0] FSM2;
integer i;
reg [9:0] pc;
reg [31:0] instruction;
reg [31:0] registers [31:0];
reg [31:0] aluOutput;
reg Zero;
reg [31:0] A;
reg [31:0] B;
reg [15:0] imm;
reg [25:0] jmem;
wire [31:0] out_mem_inst;
mem_inst mem_i(.address(pc),.clock(clk[0]),.q(out_mem_inst));
displayDecoder DP7_0(.entrada(registers[0][2:0]),.saida(HEX0));
displayDecoder DP7_1(.entrada(FSM),.saida(HEX1));
assign LEDG[0] = clk[1];
always@(posedge CLOCK_50)
begin
clk = clk + 1;
end
always@(posedge clk[1])
begin
if(KEY[0] == 0)
begin
FSM = 3'b001;
FSM2 = 16'h0000;
aluOutput = 32'd0;
Zero = 1'b0;
pc = 10'd0;
instruction = 32'd0;
for(i = 0; i < 32; i = i + 1)
begin
registers[i] = i;
end
KEY[0] = 1;
end
else
begin
if(FSM == 3'b001)
begin
pc = pc + 1;
instruction = out_mem_inst;
FSM = 3'd2;
FSM2 = 16'h0000;
end
else if(FSM == 3'b010)
begin
if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100000)
begin
FSM2 = 16'h0001;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100010)
begin
FSM2 = 16'h0002;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100100)
begin
FSM2 = 16'h0003;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100111)
begin
FSM2 = 16'h0004;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100110)
begin
FSM2 = 16'h0005;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b101010)
begin
FSM2 = 16'h0006;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b000000)
begin
FSM2 = 16'h0007;
A = registers[instruction[25:21]];
B = registers[instruction[10:6]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b000010)
begin
FSM2 = 16'h0008;
A = registers[instruction[25:21]];
B = registers[instruction[10:6]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100101)
begin
FSM2 = 16'h0009;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b001000)
begin
FSM2 = 16'h000A;
A = registers[instruction[25:21]];
imm = instruction[15:0];
end
else if(instruction[31:26] == 6'b100011)
begin
FSM2 = 16'h000B;
A = registers[instruction[25:21]];
imm = instruction[15:0];
end
else if(instruction[31:26] == 6'b101011)
begin
FSM2 = 16'h000C;
A = registers[instruction[20:16]];
imm = instruction[15:0];
end
else if(instruction[31:26] == 6'b001100)
begin
FSM2 = 16'h000D;
A = registers[instruction[25:21]];
imm = instruction[15:0];
end
else if(instruction[31:26] == 6'b001101)
begin
FSM2 = 16'h000E;
A = registers[instruction[25:21]];
imm = instruction[15:0];
end
else if(instruction[31:26] == 6'b001010)
begin
FSM2 = 16'h000F;
A = registers[instruction[25:21]];
imm = instruction[15:0];
end
else if(instruction[31:26] == 6'b000100)
begin
FSM2 = 16'h0010;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
imm = instruction[15:0];
end
else if(instruction[31:26] == 6'b000101)
begin
FSM2 = 16'h0011;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
imm = instruction[15:0];
end
else if(instruction[31:26] == 6'b000010)
begin
FSM2 = 16'h0012;
jmem = instruction[25:0];
end
FSM = 3'b011;
end
else if(FSM == 3'b011)
begin
if(FSM2 == 16'h0001)
begin
aluOutput = A + B;
end
if(FSM2 == 16'h0002)
begin
aluOutput = A - B;
end
if(FSM2 == 16'h0003)
begin
aluOutput = A & B;
end
if(FSM2 == 16'h0004)
begin
aluOutput = ~(A | B);
end
if(FSM2 == 16'h0005)
begin
aluOutput = A ^ B;
end
if(FSM2 == 16'h0006)
begin
if(A < B)
begin
aluOutput = 32'd1;
end
else
begin
aluOutput = 32'd0;
end
end
if(FSM2 == 16'h0007)
begin
aluOutput = A << B;
end
if(FSM2 == 16'h0008)
begin
aluOutput = A >> B;
end
if(FSM2 == 16'h0009)
begin
aluOutput = A | B;
end
if(FSM2 == 16'h000A)
begin
aluOutput = A + imm;
end
if(FSM2 == 16'h000B)
begin
aluOutput = A + imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000C)
begin
aluOutput = A + imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000D)
begin
aluOutput = A & imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000E)
begin
aluOutput = A | imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000F)
begin
if(A < imm)
begin
aluOutput = 32'd1;
end
else
begin
aluOutput = 32'd0;
end
end
if(FSM2 == 16'h0010)
begin
if((A - B) == 0)
begin
Zero = 1'b1;
aluOutput = (pc + 1) + imm;
end
else
begin
Zero = 1'b0;
aluOutput = 0;
end
end
if(FSM2 == 16'h0011)
begin
if((A - B) != 0)
begin
Zero = 1'b1;
aluOutput = (pc + 1) + imm;
end
else
begin
Zero = 1'b0;
aluOutput = 0;
end
end
if(FSM2 == 16'h0012)
begin
aluOutput = jmem << 2;
pc = pc + 1;
aluOutput[28] = pc[6];
aluOutput[29] = pc[7];
aluOutput[30] = pc[8];
aluOutput[31] = pc[9];
pc = pc - 1;
end
FSM = 3'b001;
end
end
end
endmodule | 0 |
139,441 | data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-fpga/mips/mips32.v | 87,717,764 | mips32.v | v | 513 | 366 | [] | [] | [] | [(1, 512)] | null | null | 1: b'%Error: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-fpga/mips/mips32.v:39: Cannot find file containing module: \'mem_inst\'\nmem_inst mem_i(.address(pc), .clock(clk[24]), .q(out_mem_inst));\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-fpga/mips,data/full_repos/permissive/87717764/mem_inst\n data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-fpga/mips,data/full_repos/permissive/87717764/mem_inst.v\n data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-fpga/mips,data/full_repos/permissive/87717764/mem_inst.sv\n mem_inst\n mem_inst.v\n mem_inst.sv\n obj_dir/mem_inst\n obj_dir/mem_inst.v\n obj_dir/mem_inst.sv\n%Error: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-fpga/mips/mips32.v:41: Cannot find file containing module: \'mem_data\'\nmem_data mem_d(.address(aluOutput[9:0]), .clock(clk[24]), .data(registers[instruction[20:16]]), .wren(writeEnable), .q(out_mem_data));\n^~~~~~~~\n%Error: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-fpga/mips/mips32.v:43: Cannot find file containing module: \'displayDecoder\'\ndisplayDecoder DP7(.entrada(hexInput[31:0]),.zero(Zero),.saida0(HEX0),.saida1(HEX1),.saida2(HEX2),.saida3(HEX3),.saida4(HEX4),.saida5(HEX5),.saida6(HEX6),.saida7(HEX7));\n^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-fpga/mips/mips32.v:185: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n : ... In instance mips32\n imm[31:16] = instruction[15]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-fpga/mips/mips32.v:193: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n : ... In instance mips32\n imm[31:16] = instruction[15]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-fpga/mips/mips32.v:201: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n : ... In instance mips32\n imm[31:16] = instruction[15]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-fpga/mips/mips32.v:209: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n : ... In instance mips32\n imm[31:16] = instruction[15]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-fpga/mips/mips32.v:217: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n : ... In instance mips32\n imm[31:16] = instruction[15]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-fpga/mips/mips32.v:225: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n : ... In instance mips32\n imm[31:16] = instruction[15]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-fpga/mips/mips32.v:234: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n : ... In instance mips32\n imm[31:16] = instruction[15]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-fpga/mips/mips32.v:243: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n : ... In instance mips32\n imm[31:16] = instruction[15]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-fpga/mips/mips32.v:387: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'pc\' generates 10 bits.\n : ... In instance mips32\n aluOutput[9:0] = pc + imm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-fpga/mips/mips32.v:387: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance mips32\n aluOutput[9:0] = pc + imm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-fpga/mips/mips32.v:412: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'pc\' generates 10 bits.\n : ... In instance mips32\n aluOutput[9:0] = pc + imm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-fpga/mips/mips32.v:412: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance mips32\n aluOutput[9:0] = pc + imm;\n ^\n%Error: Exiting due to 3 error(s), 12 warning(s)\n' | 304,820 | module | module mips32(
input CLOCK_50,
input [3:0] KEY,
input [1:0] SW,
output [7:0] LEDG,
output [31:0] LEDR,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [6:0] HEX6,
output [6:0] HEX7
);
reg [31:0] clk = 32'd0;
reg [2:0] FSM = 3'b001;
reg [15:0] FSM2;
integer i;
reg [9:0] pc;
reg [31:0] instruction;
reg [31:0] registers [31:0];
reg [31:0] aluOutput;
reg [31:0] auxMem;
reg writeEnable;
reg Zero;
reg [31:0] A;
reg [31:0] B;
reg [31:0] imm;
reg [25:0] jmem;
reg [31:0] hexInput;
wire [31:0] out_mem_inst;
wire [31:0] out_mem_data;
mem_inst mem_i(.address(pc), .clock(clk[24]), .q(out_mem_inst));
mem_data mem_d(.address(aluOutput[9:0]), .clock(clk[24]), .data(registers[instruction[20:16]]), .wren(writeEnable), .q(out_mem_data));
displayDecoder DP7(.entrada(hexInput[31:0]),.zero(Zero),.saida0(HEX0),.saida1(HEX1),.saida2(HEX2),.saida3(HEX3),.saida4(HEX4),.saida5(HEX5),.saida6(HEX6),.saida7(HEX7));
assign LEDG[0] = clk[25];
always@(posedge CLOCK_50)
begin
clk = clk + 1;
end
always@(posedge clk[24])
begin
if(SW == 2'b00 && instruction[31:26] == 6'b000000)
begin
hexInput <= registers[instruction[15:11]];
end
else if(SW == 2'b00 && (instruction[31:26] == 6'b001000 || instruction[31:26] == 6'b100011 || instruction[31:26] == 6'b101011 || instruction[31:26] == 6'b001100 || instruction[31:26] == 6'b001101 || instruction[31:26] == 6'b001010 || instruction[31:26] == 6'b000100 || instruction[31:26] == 6'b000101))
begin
hexInput <= registers[instruction[20:16]];
end
else if(SW == 2'b00 && instruction[31:26] == 6'b000010)
begin
hexInput[31:10] <= 22'b0000000000000000000000;
hexInput[9:0] <= pc[9:0];
end
else if(SW == 2'b01)
begin
hexInput <= aluOutput;
end
else if(SW == 2'b10)
begin
hexInput[31:10] <= 22'b0000000000000000000000;
hexInput[9:0] <= pc[9:0];
end
end
always@(posedge clk[25])
begin
if(KEY[0] == 0)
begin
FSM = 3'b001;
FSM2 = 16'h0000;
aluOutput = 32'd0;
Zero = 1'b0;
pc = 10'd0;
instruction = 32'd0;
for(i = 0; i < 32; i = i + 1)
begin
registers[i] = i;
end
end
else
begin
if(FSM == 3'b001)
begin
pc = pc + 1;
instruction = out_mem_inst;
FSM <= 3'b010;
FSM2 = 16'h0000;
end
else if(FSM == 3'b010)
begin
if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100000)
begin
FSM2 = 16'h0001;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100010)
begin
FSM2 = 16'h0002;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100100)
begin
FSM2 = 16'h0003;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100111)
begin
FSM2 = 16'h0004;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100110)
begin
FSM2 = 16'h0005;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b101010)
begin
FSM2 = 16'h0006;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b000000)
begin
FSM2 = 16'h0007;
A = registers[instruction[25:21]];
B = registers[instruction[10:6]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b000010)
begin
FSM2 = 16'h0008;
A = registers[instruction[25:21]];
B = registers[instruction[10:6]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100101)
begin
FSM2 = 16'h0009;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b001000)
begin
FSM2 = 16'h000A;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b100011)
begin
FSM2 = 16'h000B;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b101011)
begin
FSM2 = 16'h000C;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b001100)
begin
FSM2 = 16'h000D;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b001101)
begin
FSM2 = 16'h000E;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b001010)
begin
FSM2 = 16'h000F;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b000100)
begin
FSM2 = 16'h0010;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b000101)
begin
FSM2 = 16'h0011;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b000010)
begin
FSM2 = 16'h0012;
imm[25:0] = instruction[25:0];
end
FSM <= 3'b011;
end
else if(FSM == 3'b011)
begin
if(FSM2 == 16'h0001)
begin
aluOutput = A + B;
end
if(FSM2 == 16'h0002)
begin
aluOutput = A - B;
end
if(FSM2 == 16'h0003)
begin
aluOutput = A & B;
end
if(FSM2 == 16'h0004)
begin
aluOutput = ~(A | B);
end
if(FSM2 == 16'h0005)
begin
aluOutput = A ^ B;
end
if(FSM2 == 16'h0006)
begin
if(A < B)
begin
aluOutput = 32'd1;
end
else
begin
aluOutput = 32'd0;
end
end
if(FSM2 == 16'h0007)
begin
aluOutput = A << B;
end
if(FSM2 == 16'h0008)
begin
aluOutput = A >> B;
end
if(FSM2 == 16'h0009)
begin
aluOutput = A | B;
end
if(FSM2 == 16'h000A)
begin
aluOutput = A + imm;
end
if(FSM2 == 16'h000B)
begin
aluOutput = A + imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000C)
begin
aluOutput = A + imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000D)
begin
aluOutput = A & imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000E)
begin
aluOutput = A | imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000F)
begin
if(A < imm)
begin
aluOutput = 32'd1;
end
else
begin
aluOutput = 32'd0;
end
end
if(FSM2 == 16'h0010)
begin
if(A >= B)
begin
aluOutput = A - B;
end
else
begin
aluOutput = B - A;
end
if(aluOutput == 32'd0)
begin
Zero = 1'b1;
aluOutput[31:10] = 22'd0;
aluOutput[9:0] = pc + imm;
end
else
begin
Zero = 1'b0;
end
end
if(FSM2 == 16'h0011)
begin
if(A >= B)
begin
aluOutput = A - B;
end
else
begin
aluOutput = B - A;
end
if(aluOutput != 32'd0)
begin
Zero = 1'b0;
aluOutput[31:10] = 22'd0;
aluOutput[9:0] = pc + imm;
end
else
begin
Zero = 1'b1;
end
end
if(FSM2 == 16'h0012)
begin
aluOutput[25:0] = imm[25:0];
aluOutput[31:26] = pc[9:4];
end
FSM <= 3'b100;
end
if(FSM == 3'b100)
begin
if(FSM2 == 16'h000B)
begin
auxMem = out_mem_data;
end
else if(FSM2 == 16'h000C)
begin
writeEnable = 1'b1;
end
FSM <= 3'b101;
end
if(FSM == 3'b101)
begin
if(instruction[31:26] == 6'b000000)
begin
registers[instruction[15:11]] = aluOutput;
end
else if(instruction[31:26] == 6'b001000)
begin
registers[instruction[20:16]] = aluOutput;
end
else if(instruction[31:26] == 6'b100011)
begin
registers[instruction[20:16]] = auxMem;
end
else if(instruction[31:26] == 6'b101011)
begin
writeEnable = 1'b0;
end
else if(instruction[31:26] == 6'b001100)
begin
registers[instruction[20:16]] = aluOutput;
end
else if(instruction[31:26] == 6'b001101)
begin
registers[instruction[20:16]] = aluOutput;
end
else if(instruction[31:26] == 6'b001010)
begin
registers[instruction[20:16]] = aluOutput;
end
else if(instruction[31:26] == 6'b000100)
begin
if(Zero == 1'b1)
begin
pc[9:0] = aluOutput[9:0];
end
end
else if(instruction[31:26] == 6'b000101)
begin
if(Zero == 1'b0)
begin
pc[9:0] = aluOutput[9:0];
end
end
else if(instruction[31:26] == 6'b000010)
begin
pc[9:0] = aluOutput[9:0];
end
FSM <= 3'b001;
end
end
end
endmodule | module mips32(
input CLOCK_50,
input [3:0] KEY,
input [1:0] SW,
output [7:0] LEDG,
output [31:0] LEDR,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [6:0] HEX6,
output [6:0] HEX7
); |
reg [31:0] clk = 32'd0;
reg [2:0] FSM = 3'b001;
reg [15:0] FSM2;
integer i;
reg [9:0] pc;
reg [31:0] instruction;
reg [31:0] registers [31:0];
reg [31:0] aluOutput;
reg [31:0] auxMem;
reg writeEnable;
reg Zero;
reg [31:0] A;
reg [31:0] B;
reg [31:0] imm;
reg [25:0] jmem;
reg [31:0] hexInput;
wire [31:0] out_mem_inst;
wire [31:0] out_mem_data;
mem_inst mem_i(.address(pc), .clock(clk[24]), .q(out_mem_inst));
mem_data mem_d(.address(aluOutput[9:0]), .clock(clk[24]), .data(registers[instruction[20:16]]), .wren(writeEnable), .q(out_mem_data));
displayDecoder DP7(.entrada(hexInput[31:0]),.zero(Zero),.saida0(HEX0),.saida1(HEX1),.saida2(HEX2),.saida3(HEX3),.saida4(HEX4),.saida5(HEX5),.saida6(HEX6),.saida7(HEX7));
assign LEDG[0] = clk[25];
always@(posedge CLOCK_50)
begin
clk = clk + 1;
end
always@(posedge clk[24])
begin
if(SW == 2'b00 && instruction[31:26] == 6'b000000)
begin
hexInput <= registers[instruction[15:11]];
end
else if(SW == 2'b00 && (instruction[31:26] == 6'b001000 || instruction[31:26] == 6'b100011 || instruction[31:26] == 6'b101011 || instruction[31:26] == 6'b001100 || instruction[31:26] == 6'b001101 || instruction[31:26] == 6'b001010 || instruction[31:26] == 6'b000100 || instruction[31:26] == 6'b000101))
begin
hexInput <= registers[instruction[20:16]];
end
else if(SW == 2'b00 && instruction[31:26] == 6'b000010)
begin
hexInput[31:10] <= 22'b0000000000000000000000;
hexInput[9:0] <= pc[9:0];
end
else if(SW == 2'b01)
begin
hexInput <= aluOutput;
end
else if(SW == 2'b10)
begin
hexInput[31:10] <= 22'b0000000000000000000000;
hexInput[9:0] <= pc[9:0];
end
end
always@(posedge clk[25])
begin
if(KEY[0] == 0)
begin
FSM = 3'b001;
FSM2 = 16'h0000;
aluOutput = 32'd0;
Zero = 1'b0;
pc = 10'd0;
instruction = 32'd0;
for(i = 0; i < 32; i = i + 1)
begin
registers[i] = i;
end
end
else
begin
if(FSM == 3'b001)
begin
pc = pc + 1;
instruction = out_mem_inst;
FSM <= 3'b010;
FSM2 = 16'h0000;
end
else if(FSM == 3'b010)
begin
if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100000)
begin
FSM2 = 16'h0001;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100010)
begin
FSM2 = 16'h0002;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100100)
begin
FSM2 = 16'h0003;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100111)
begin
FSM2 = 16'h0004;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100110)
begin
FSM2 = 16'h0005;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b101010)
begin
FSM2 = 16'h0006;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b000000)
begin
FSM2 = 16'h0007;
A = registers[instruction[25:21]];
B = registers[instruction[10:6]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b000010)
begin
FSM2 = 16'h0008;
A = registers[instruction[25:21]];
B = registers[instruction[10:6]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100101)
begin
FSM2 = 16'h0009;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b001000)
begin
FSM2 = 16'h000A;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b100011)
begin
FSM2 = 16'h000B;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b101011)
begin
FSM2 = 16'h000C;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b001100)
begin
FSM2 = 16'h000D;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b001101)
begin
FSM2 = 16'h000E;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b001010)
begin
FSM2 = 16'h000F;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b000100)
begin
FSM2 = 16'h0010;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b000101)
begin
FSM2 = 16'h0011;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b000010)
begin
FSM2 = 16'h0012;
imm[25:0] = instruction[25:0];
end
FSM <= 3'b011;
end
else if(FSM == 3'b011)
begin
if(FSM2 == 16'h0001)
begin
aluOutput = A + B;
end
if(FSM2 == 16'h0002)
begin
aluOutput = A - B;
end
if(FSM2 == 16'h0003)
begin
aluOutput = A & B;
end
if(FSM2 == 16'h0004)
begin
aluOutput = ~(A | B);
end
if(FSM2 == 16'h0005)
begin
aluOutput = A ^ B;
end
if(FSM2 == 16'h0006)
begin
if(A < B)
begin
aluOutput = 32'd1;
end
else
begin
aluOutput = 32'd0;
end
end
if(FSM2 == 16'h0007)
begin
aluOutput = A << B;
end
if(FSM2 == 16'h0008)
begin
aluOutput = A >> B;
end
if(FSM2 == 16'h0009)
begin
aluOutput = A | B;
end
if(FSM2 == 16'h000A)
begin
aluOutput = A + imm;
end
if(FSM2 == 16'h000B)
begin
aluOutput = A + imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000C)
begin
aluOutput = A + imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000D)
begin
aluOutput = A & imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000E)
begin
aluOutput = A | imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000F)
begin
if(A < imm)
begin
aluOutput = 32'd1;
end
else
begin
aluOutput = 32'd0;
end
end
if(FSM2 == 16'h0010)
begin
if(A >= B)
begin
aluOutput = A - B;
end
else
begin
aluOutput = B - A;
end
if(aluOutput == 32'd0)
begin
Zero = 1'b1;
aluOutput[31:10] = 22'd0;
aluOutput[9:0] = pc + imm;
end
else
begin
Zero = 1'b0;
end
end
if(FSM2 == 16'h0011)
begin
if(A >= B)
begin
aluOutput = A - B;
end
else
begin
aluOutput = B - A;
end
if(aluOutput != 32'd0)
begin
Zero = 1'b0;
aluOutput[31:10] = 22'd0;
aluOutput[9:0] = pc + imm;
end
else
begin
Zero = 1'b1;
end
end
if(FSM2 == 16'h0012)
begin
aluOutput[25:0] = imm[25:0];
aluOutput[31:26] = pc[9:4];
end
FSM <= 3'b100;
end
if(FSM == 3'b100)
begin
if(FSM2 == 16'h000B)
begin
auxMem = out_mem_data;
end
else if(FSM2 == 16'h000C)
begin
writeEnable = 1'b1;
end
FSM <= 3'b101;
end
if(FSM == 3'b101)
begin
if(instruction[31:26] == 6'b000000)
begin
registers[instruction[15:11]] = aluOutput;
end
else if(instruction[31:26] == 6'b001000)
begin
registers[instruction[20:16]] = aluOutput;
end
else if(instruction[31:26] == 6'b100011)
begin
registers[instruction[20:16]] = auxMem;
end
else if(instruction[31:26] == 6'b101011)
begin
writeEnable = 1'b0;
end
else if(instruction[31:26] == 6'b001100)
begin
registers[instruction[20:16]] = aluOutput;
end
else if(instruction[31:26] == 6'b001101)
begin
registers[instruction[20:16]] = aluOutput;
end
else if(instruction[31:26] == 6'b001010)
begin
registers[instruction[20:16]] = aluOutput;
end
else if(instruction[31:26] == 6'b000100)
begin
if(Zero == 1'b1)
begin
pc[9:0] = aluOutput[9:0];
end
end
else if(instruction[31:26] == 6'b000101)
begin
if(Zero == 1'b0)
begin
pc[9:0] = aluOutput[9:0];
end
end
else if(instruction[31:26] == 6'b000010)
begin
pc[9:0] = aluOutput[9:0];
end
FSM <= 3'b001;
end
end
end
endmodule | 0 |
139,442 | data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-modelsim/code/tp.v | 87,717,764 | tp.v | v | 479 | 134 | [] | [] | [] | [(1, 478)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-modelsim/code/tp.v:9: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance tp\nreg [3:0] KEY = 3\'b000; \n ^~~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-modelsim/code/tp.v:31: Cannot find file containing module: \'mem_inst\'\nmem_inst mem_i(.address(pc), .clock(clk[0]), .q(out_mem_inst));\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-modelsim/code,data/full_repos/permissive/87717764/mem_inst\n data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-modelsim/code,data/full_repos/permissive/87717764/mem_inst.v\n data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-modelsim/code,data/full_repos/permissive/87717764/mem_inst.sv\n mem_inst\n mem_inst.v\n mem_inst.sv\n obj_dir/mem_inst\n obj_dir/mem_inst.v\n obj_dir/mem_inst.sv\n%Error: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-modelsim/code/tp.v:33: Cannot find file containing module: \'mem_data\'\nmem_data mem_d(.address(aluOutput[9:0]), .clock(clk[0]), .data(registers[instruction[20:16]]), .wren(writeEnable), .q(out_mem_data));\n^~~~~~~~\n%Error: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-modelsim/code/tp.v:35: Cannot find file containing module: \'displayDecoder\'\ndisplayDecoder DP7_0(.entrada(registers[0][2:0]), .saida(HEX0));\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-modelsim/code/tp.v:36: Cannot find file containing module: \'displayDecoder\'\ndisplayDecoder DP7_1(.entrada(FSM), .saida(HEX1));\n^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-modelsim/code/tp.v:151: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n : ... In instance tp\n imm[31:16] = instruction[15]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-modelsim/code/tp.v:159: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n : ... In instance tp\n imm[31:16] = instruction[15]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-modelsim/code/tp.v:167: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n : ... In instance tp\n imm[31:16] = instruction[15]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-modelsim/code/tp.v:175: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n : ... In instance tp\n imm[31:16] = instruction[15]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-modelsim/code/tp.v:183: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n : ... In instance tp\n imm[31:16] = instruction[15]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-modelsim/code/tp.v:191: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n : ... In instance tp\n imm[31:16] = instruction[15]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-modelsim/code/tp.v:200: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n : ... In instance tp\n imm[31:16] = instruction[15]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-modelsim/code/tp.v:209: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n : ... In instance tp\n imm[31:16] = instruction[15]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-modelsim/code/tp.v:353: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'pc\' generates 10 bits.\n : ... In instance tp\n aluOutput[9:0] = pc + imm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-modelsim/code/tp.v:353: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance tp\n aluOutput[9:0] = pc + imm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-modelsim/code/tp.v:378: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'pc\' generates 10 bits.\n : ... In instance tp\n aluOutput[9:0] = pc + imm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87717764/tp/src/entrega2/TP-OC2_Entrega2_Grupo3/teste-modelsim/code/tp.v:378: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n : ... In instance tp\n aluOutput[9:0] = pc + imm;\n ^\n%Error: Exiting due to 4 error(s), 13 warning(s)\n' | 304,822 | module | module tp(
input CLOCK_50,
output [8:0] LEDG,
output [6:0] HEX0,
output [6:0] HEX1
);
reg [3:0] KEY = 3'b000;
reg [31:0] clk = 32'd0;
reg [2:0] FSM;
reg [15:0] FSM2;
integer i;
reg [9:0] pc;
reg [31:0] instruction;
reg [31:0] registers [31:0];
reg [31:0] aluOutput;
reg [31:0] auxMem;
reg writeEnable;
reg Zero;
reg [31:0] A;
reg [31:0] B;
reg [31:0] imm;
reg [25:0] jmem;
wire [31:0] out_mem_inst;
wire [31:0] out_mem_data;
mem_inst mem_i(.address(pc), .clock(clk[0]), .q(out_mem_inst));
mem_data mem_d(.address(aluOutput[9:0]), .clock(clk[0]), .data(registers[instruction[20:16]]), .wren(writeEnable), .q(out_mem_data));
displayDecoder DP7_0(.entrada(registers[0][2:0]), .saida(HEX0));
displayDecoder DP7_1(.entrada(FSM), .saida(HEX1));
assign LEDG[0] = clk[1];
always@(posedge CLOCK_50)
begin
clk = clk + 1;
end
always@(posedge clk[1])
begin
if(KEY[0] == 0)
begin
FSM = 3'b001;
FSM2 = 16'h0000;
aluOutput = 32'd0;
Zero = 1'b0;
writeEnable = 1'b0;
pc = 10'd0;
instruction = 32'd0;
for(i = 0; i < 32; i = i + 1)
begin
registers[i] = i;
end
KEY[0] = 1;
end
else
begin
if(FSM == 3'b001)
begin
pc = pc + 1;
instruction = out_mem_inst;
FSM <= 3'b010;
FSM2 = 16'h0000;
end
else if(FSM == 3'b010)
begin
if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100000)
begin
FSM2 = 16'h0001;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100010)
begin
FSM2 = 16'h0002;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100100)
begin
FSM2 = 16'h0003;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100111)
begin
FSM2 = 16'h0004;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100110)
begin
FSM2 = 16'h0005;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b101010)
begin
FSM2 = 16'h0006;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b000000)
begin
FSM2 = 16'h0007;
A = registers[instruction[25:21]];
B = registers[instruction[10:6]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b000010)
begin
FSM2 = 16'h0008;
A = registers[instruction[25:21]];
B = registers[instruction[10:6]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100101)
begin
FSM2 = 16'h0009;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b001000)
begin
FSM2 = 16'h000A;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b100011)
begin
FSM2 = 16'h000B;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b101011)
begin
FSM2 = 16'h000C;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b001100)
begin
FSM2 = 16'h000D;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b001101)
begin
FSM2 = 16'h000E;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b001010)
begin
FSM2 = 16'h000F;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b000100)
begin
FSM2 = 16'h0010;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b000101)
begin
FSM2 = 16'h0011;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b000010)
begin
FSM2 = 16'h0012;
imm[25:0] = instruction[25:0];
end
FSM <= 3'b011;
end
else if(FSM == 3'b011)
begin
if(FSM2 == 16'h0001)
begin
aluOutput = A + B;
end
if(FSM2 == 16'h0002)
begin
aluOutput = A - B;
end
if(FSM2 == 16'h0003)
begin
aluOutput = A & B;
end
if(FSM2 == 16'h0004)
begin
aluOutput = ~(A | B);
end
if(FSM2 == 16'h0005)
begin
aluOutput = A ^ B;
end
if(FSM2 == 16'h0006)
begin
if(A < B)
begin
aluOutput = 32'd1;
end
else
begin
aluOutput = 32'd0;
end
end
if(FSM2 == 16'h0007)
begin
aluOutput = A << B;
end
if(FSM2 == 16'h0008)
begin
aluOutput = A >> B;
end
if(FSM2 == 16'h0009)
begin
aluOutput = A | B;
end
if(FSM2 == 16'h000A)
begin
aluOutput = A + imm;
end
if(FSM2 == 16'h000B)
begin
aluOutput = A + imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000C)
begin
aluOutput = A + imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000D)
begin
aluOutput = A & imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000E)
begin
aluOutput = A | imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000F)
begin
if(A < imm)
begin
aluOutput = 32'd1;
end
else
begin
aluOutput = 32'd0;
end
end
if(FSM2 == 16'h0010)
begin
if(A >= B)
begin
aluOutput = A - B;
end
else
begin
aluOutput = B - A;
end
if(aluOutput == 32'd0)
begin
Zero = 1'b1;
aluOutput[31:10] = 22'd0;
aluOutput[9:0] = pc + imm;
end
else
begin
Zero = 1'b0;
end
end
if(FSM2 == 16'h0011)
begin
if(A >= B)
begin
aluOutput = A - B;
end
else
begin
aluOutput = B - A;
end
if(aluOutput != 32'd0)
begin
Zero = 1'b0;
aluOutput[31:10] = 22'd0;
aluOutput[9:0] = pc + imm;
end
else
begin
Zero = 1'b1;
end
end
if(FSM2 == 16'h0012)
begin
aluOutput[25:0] = imm[25:0];
aluOutput[31:26] = pc[9:4];
end
FSM <= 3'b100;
end
if(FSM == 3'b100)
begin
if(FSM2 == 16'h000B)
begin
auxMem = out_mem_data;
end
else if(FSM2 == 16'h000C)
begin
writeEnable = 1'b1;
end
FSM <= 3'b101;
end
if(FSM == 3'b101)
begin
if(instruction[31:26] == 6'b000000)
begin
registers[instruction[15:11]] = aluOutput;
end
else if(instruction[31:26] == 6'b001000)
begin
registers[instruction[20:16]] = aluOutput;
end
else if(instruction[31:26] == 6'b100011)
begin
registers[instruction[20:16]] = auxMem;
end
else if(instruction[31:26] == 6'b101011)
begin
writeEnable = 1'b0;
end
else if(instruction[31:26] == 6'b001100)
begin
registers[instruction[20:16]] = aluOutput;
end
else if(instruction[31:26] == 6'b001101)
begin
registers[instruction[20:16]] = aluOutput;
end
else if(instruction[31:26] == 6'b001010)
begin
registers[instruction[20:16]] = aluOutput;
end
else if(instruction[31:26] == 6'b000100)
begin
if(Zero == 1'b1)
begin
pc[9:0] = aluOutput[9:0];
end
end
else if(instruction[31:26] == 6'b000101)
begin
if(Zero == 1'b0)
begin
pc[9:0] = aluOutput[9:0];
end
end
else if(instruction[31:26] == 6'b000010)
begin
pc[9:0] = aluOutput[9:0];
end
FSM <= 3'b001;
end
end
end
endmodule | module tp(
input CLOCK_50,
output [8:0] LEDG,
output [6:0] HEX0,
output [6:0] HEX1
); |
reg [3:0] KEY = 3'b000;
reg [31:0] clk = 32'd0;
reg [2:0] FSM;
reg [15:0] FSM2;
integer i;
reg [9:0] pc;
reg [31:0] instruction;
reg [31:0] registers [31:0];
reg [31:0] aluOutput;
reg [31:0] auxMem;
reg writeEnable;
reg Zero;
reg [31:0] A;
reg [31:0] B;
reg [31:0] imm;
reg [25:0] jmem;
wire [31:0] out_mem_inst;
wire [31:0] out_mem_data;
mem_inst mem_i(.address(pc), .clock(clk[0]), .q(out_mem_inst));
mem_data mem_d(.address(aluOutput[9:0]), .clock(clk[0]), .data(registers[instruction[20:16]]), .wren(writeEnable), .q(out_mem_data));
displayDecoder DP7_0(.entrada(registers[0][2:0]), .saida(HEX0));
displayDecoder DP7_1(.entrada(FSM), .saida(HEX1));
assign LEDG[0] = clk[1];
always@(posedge CLOCK_50)
begin
clk = clk + 1;
end
always@(posedge clk[1])
begin
if(KEY[0] == 0)
begin
FSM = 3'b001;
FSM2 = 16'h0000;
aluOutput = 32'd0;
Zero = 1'b0;
writeEnable = 1'b0;
pc = 10'd0;
instruction = 32'd0;
for(i = 0; i < 32; i = i + 1)
begin
registers[i] = i;
end
KEY[0] = 1;
end
else
begin
if(FSM == 3'b001)
begin
pc = pc + 1;
instruction = out_mem_inst;
FSM <= 3'b010;
FSM2 = 16'h0000;
end
else if(FSM == 3'b010)
begin
if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100000)
begin
FSM2 = 16'h0001;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100010)
begin
FSM2 = 16'h0002;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100100)
begin
FSM2 = 16'h0003;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100111)
begin
FSM2 = 16'h0004;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100110)
begin
FSM2 = 16'h0005;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b101010)
begin
FSM2 = 16'h0006;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b000000)
begin
FSM2 = 16'h0007;
A = registers[instruction[25:21]];
B = registers[instruction[10:6]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b000010)
begin
FSM2 = 16'h0008;
A = registers[instruction[25:21]];
B = registers[instruction[10:6]];
end
else if(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b100101)
begin
FSM2 = 16'h0009;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
end
else if(instruction[31:26] == 6'b001000)
begin
FSM2 = 16'h000A;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b100011)
begin
FSM2 = 16'h000B;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b101011)
begin
FSM2 = 16'h000C;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b001100)
begin
FSM2 = 16'h000D;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b001101)
begin
FSM2 = 16'h000E;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b001010)
begin
FSM2 = 16'h000F;
A = registers[instruction[25:21]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b000100)
begin
FSM2 = 16'h0010;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b000101)
begin
FSM2 = 16'h0011;
A = registers[instruction[25:21]];
B = registers[instruction[20:16]];
imm[15:0] = instruction[15:0];
imm[31:16] = instruction[15];
end
else if(instruction[31:26] == 6'b000010)
begin
FSM2 = 16'h0012;
imm[25:0] = instruction[25:0];
end
FSM <= 3'b011;
end
else if(FSM == 3'b011)
begin
if(FSM2 == 16'h0001)
begin
aluOutput = A + B;
end
if(FSM2 == 16'h0002)
begin
aluOutput = A - B;
end
if(FSM2 == 16'h0003)
begin
aluOutput = A & B;
end
if(FSM2 == 16'h0004)
begin
aluOutput = ~(A | B);
end
if(FSM2 == 16'h0005)
begin
aluOutput = A ^ B;
end
if(FSM2 == 16'h0006)
begin
if(A < B)
begin
aluOutput = 32'd1;
end
else
begin
aluOutput = 32'd0;
end
end
if(FSM2 == 16'h0007)
begin
aluOutput = A << B;
end
if(FSM2 == 16'h0008)
begin
aluOutput = A >> B;
end
if(FSM2 == 16'h0009)
begin
aluOutput = A | B;
end
if(FSM2 == 16'h000A)
begin
aluOutput = A + imm;
end
if(FSM2 == 16'h000B)
begin
aluOutput = A + imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000C)
begin
aluOutput = A + imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000D)
begin
aluOutput = A & imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000E)
begin
aluOutput = A | imm;
for(i = 16; i < 32; i = i + 1)
begin
aluOutput[i] = aluOutput[15];
end
end
if(FSM2 == 16'h000F)
begin
if(A < imm)
begin
aluOutput = 32'd1;
end
else
begin
aluOutput = 32'd0;
end
end
if(FSM2 == 16'h0010)
begin
if(A >= B)
begin
aluOutput = A - B;
end
else
begin
aluOutput = B - A;
end
if(aluOutput == 32'd0)
begin
Zero = 1'b1;
aluOutput[31:10] = 22'd0;
aluOutput[9:0] = pc + imm;
end
else
begin
Zero = 1'b0;
end
end
if(FSM2 == 16'h0011)
begin
if(A >= B)
begin
aluOutput = A - B;
end
else
begin
aluOutput = B - A;
end
if(aluOutput != 32'd0)
begin
Zero = 1'b0;
aluOutput[31:10] = 22'd0;
aluOutput[9:0] = pc + imm;
end
else
begin
Zero = 1'b1;
end
end
if(FSM2 == 16'h0012)
begin
aluOutput[25:0] = imm[25:0];
aluOutput[31:26] = pc[9:4];
end
FSM <= 3'b100;
end
if(FSM == 3'b100)
begin
if(FSM2 == 16'h000B)
begin
auxMem = out_mem_data;
end
else if(FSM2 == 16'h000C)
begin
writeEnable = 1'b1;
end
FSM <= 3'b101;
end
if(FSM == 3'b101)
begin
if(instruction[31:26] == 6'b000000)
begin
registers[instruction[15:11]] = aluOutput;
end
else if(instruction[31:26] == 6'b001000)
begin
registers[instruction[20:16]] = aluOutput;
end
else if(instruction[31:26] == 6'b100011)
begin
registers[instruction[20:16]] = auxMem;
end
else if(instruction[31:26] == 6'b101011)
begin
writeEnable = 1'b0;
end
else if(instruction[31:26] == 6'b001100)
begin
registers[instruction[20:16]] = aluOutput;
end
else if(instruction[31:26] == 6'b001101)
begin
registers[instruction[20:16]] = aluOutput;
end
else if(instruction[31:26] == 6'b001010)
begin
registers[instruction[20:16]] = aluOutput;
end
else if(instruction[31:26] == 6'b000100)
begin
if(Zero == 1'b1)
begin
pc[9:0] = aluOutput[9:0];
end
end
else if(instruction[31:26] == 6'b000101)
begin
if(Zero == 1'b0)
begin
pc[9:0] = aluOutput[9:0];
end
end
else if(instruction[31:26] == 6'b000010)
begin
pc[9:0] = aluOutput[9:0];
end
FSM <= 3'b001;
end
end
end
endmodule | 0 |
139,443 | data/full_repos/permissive/87735149/src/rtl/blabla_qr.v | 87,735,149 | blabla_qr.v | v | 115 | 73 | [] | ['redistribution and use in source and binary forms, with or without modification, are permitted'] | ['all rights reserved'] | [(42, 110)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/87735149/src/rtl/blabla_qr.v:94: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n : ... In instance blabla_qr\n d1 = {d0[15 : 0], d0[31 : 16]};\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/87735149/src/rtl/blabla_qr.v:97: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n : ... In instance blabla_qr\n b1 = {b0[19 : 0], b0[31 : 20]};\n ^\n%Warning-WIDTH: data/full_repos/permissive/87735149/src/rtl/blabla_qr.v:100: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n : ... In instance blabla_qr\n d3 = {d2[23 : 0], d2[31 : 24]};\n ^\n%Warning-WIDTH: data/full_repos/permissive/87735149/src/rtl/blabla_qr.v:103: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n : ... In instance blabla_qr\n b3 = {b2[24 : 0], b2[31 : 25]};\n ^\n%Error: Exiting due to 4 warning(s)\n' | 304,842 | module | module blabla_qr(
input wire [63 : 0] a,
input wire [63 : 0] b,
input wire [63 : 0] c,
input wire [63 : 0] d,
output wire [63 : 0] a_prim,
output wire [63 : 0] b_prim,
output wire [63 : 0] c_prim,
output wire [63 : 0] d_prim
);
reg [63 : 0] internal_a_prim;
reg [63 : 0] internal_b_prim;
reg [63 : 0] internal_c_prim;
reg [63 : 0] internal_d_prim;
assign a_prim = internal_a_prim;
assign b_prim = internal_b_prim;
assign c_prim = internal_c_prim;
assign d_prim = internal_d_prim;
always @*
begin : qr
reg [63 : 0] a0;
reg [63 : 0] a1;
reg [63 : 0] b0;
reg [63 : 0] b1;
reg [63 : 0] b2;
reg [63 : 0] b3;
reg [63 : 0] c0;
reg [63 : 0] c1;
reg [63 : 0] d0;
reg [63 : 0] d1;
reg [63 : 0] d2;
reg [63 : 0] d3;
a0 = a + b;
d0 = d ^ a0;
d1 = {d0[15 : 0], d0[31 : 16]};
c0 = c + d1;
b0 = b ^ c0;
b1 = {b0[19 : 0], b0[31 : 20]};
a1 = a0 + b1;
d2 = d1 ^ a1;
d3 = {d2[23 : 0], d2[31 : 24]};
c1 = c0 + d3;
b2 = b1 ^ c1;
b3 = {b2[24 : 0], b2[31 : 25]};
internal_a_prim = a1;
internal_b_prim = b3;
internal_c_prim = c1;
internal_d_prim = d3;
end
endmodule | module blabla_qr(
input wire [63 : 0] a,
input wire [63 : 0] b,
input wire [63 : 0] c,
input wire [63 : 0] d,
output wire [63 : 0] a_prim,
output wire [63 : 0] b_prim,
output wire [63 : 0] c_prim,
output wire [63 : 0] d_prim
); |
reg [63 : 0] internal_a_prim;
reg [63 : 0] internal_b_prim;
reg [63 : 0] internal_c_prim;
reg [63 : 0] internal_d_prim;
assign a_prim = internal_a_prim;
assign b_prim = internal_b_prim;
assign c_prim = internal_c_prim;
assign d_prim = internal_d_prim;
always @*
begin : qr
reg [63 : 0] a0;
reg [63 : 0] a1;
reg [63 : 0] b0;
reg [63 : 0] b1;
reg [63 : 0] b2;
reg [63 : 0] b3;
reg [63 : 0] c0;
reg [63 : 0] c1;
reg [63 : 0] d0;
reg [63 : 0] d1;
reg [63 : 0] d2;
reg [63 : 0] d3;
a0 = a + b;
d0 = d ^ a0;
d1 = {d0[15 : 0], d0[31 : 16]};
c0 = c + d1;
b0 = b ^ c0;
b1 = {b0[19 : 0], b0[31 : 20]};
a1 = a0 + b1;
d2 = d1 ^ a1;
d3 = {d2[23 : 0], d2[31 : 24]};
c1 = c0 + d3;
b2 = b1 ^ c1;
b3 = {b2[24 : 0], b2[31 : 25]};
internal_a_prim = a1;
internal_b_prim = b3;
internal_c_prim = c1;
internal_d_prim = d3;
end
endmodule | 1 |
139,444 | data/full_repos/permissive/87854528/mriscv_vivado.srcs/sources_1/imports/verilog/AXI_SP32B1024.v | 87,854,528 | AXI_SP32B1024.v | v | 148 | 95 | [] | [] | [] | [(1, 147)] | null | data/verilator_xmls/7b43efcd-8118-44aa-b89d-a139f289fdf3.xml | null | 304,865 | module | module AXI_SP32B1024(
input CLK,
input RST,
input axi_awvalid,
output axi_awready,
input [32-1:0] axi_awaddr,
input [3-1:0] axi_awprot,
input axi_wvalid,
output axi_wready,
input [32-1:0] axi_wdata,
input [4-1:0] axi_wstrb,
output axi_bvalid,
input axi_bready,
input axi_arvalid,
output axi_arready,
input [32-1:0] axi_araddr,
input [3-1:0] axi_arprot,
output axi_rvalid,
input axi_rready,
output [32-1:0] axi_rdata,
input [31:0] Q,
output reg CEN,
output reg WEN,
output reg [9:0] A,
output [31:0] D
);
assign axi_awready = 1'b1;
assign axi_arready = 1'b1;
assign axi_wready = 1'b1;
reg [31:0] DP;
assign axi_rdata = Q;
always @(negedge CLK) begin
if (RST==1'b0) begin
A <= {10{1'b0}};
DP <= {32{1'b0}};
end else begin
if(axi_awvalid == 1'b1) begin
A <= axi_awaddr[9:0];
end else if(axi_arvalid == 1'b1) begin
A <= axi_araddr[9:0];
end
if(axi_wvalid == 1'b1) begin
DP <= axi_wdata;
end
end
end
reg reading1, reading2;
assign axi_rvalid = reading2;
always @(posedge CLK) begin
if (RST==1'b0) begin
reading1 <= 1'b0;
reading2 <= 1'b0;
end else begin
if(axi_rready == 1'b1 && reading1 == 1'b1 && reading2 == 1'b1) begin
reading1 <= 1'b0;
end else if(axi_arvalid == 1'b1) begin
reading1 <= 1'b1;
end
if(axi_rready == 1'b1 && reading1 == 1'b1 && reading2 == 1'b1) begin
reading2 <= 1'b0;
end else if(reading1 == 1'b1) begin
reading2 <= 1'b1;
end
end
end
reg writting1, writting2, writting3;
assign axi_bvalid = writting3;
always @(posedge CLK) begin
if (RST==1'b0) begin
writting1 <= 1'b0;
writting2 <= 1'b0;
writting3 <= 1'b0;
end else begin
if(axi_bready == 1'b1 && writting1 == 1'b1 && writting2 == 1'b1 && writting3 == 1'b1) begin
writting3 <= 1'b0;
end else if(writting2 == 1'b1) begin
writting3 <= 1'b1;
end else begin
writting3 <= writting3;
end
if(axi_bready == 1'b1 && writting1 == 1'b1 && writting2 == 1'b1 && writting3 == 1'b1) begin
writting1 <= 1'b0;
end else if(axi_awvalid == 1'b1) begin
writting1 <= 1'b1;
end else begin
writting1 <= writting1;
end
if(axi_bready == 1'b1 && writting1 == 1'b1 && writting2 == 1'b1 && writting3 == 1'b1) begin
writting2 <= 1'b0;
end else if(axi_wvalid == 1'b1) begin
writting2 <= 1'b1;
end else begin
writting2 <= writting2;
end
end
end
always @(negedge CLK) begin
if (RST==1'b0) begin
CEN <= 1'b1;
WEN <= 1'b1;
end else begin
CEN <= ~(reading1 | writting1);
WEN <= ~writting2;
end
end
assign D[7:0] = axi_wstrb[0]?DP[7:0] :Q[7:0];
assign D[15:8] = axi_wstrb[1]?DP[15:8] :Q[15:8];
assign D[23:16] = axi_wstrb[2]?DP[23:16]:Q[23:16];
assign D[31:24] = axi_wstrb[3]?DP[31:24]:Q[31:24];
endmodule | module AXI_SP32B1024(
input CLK,
input RST,
input axi_awvalid,
output axi_awready,
input [32-1:0] axi_awaddr,
input [3-1:0] axi_awprot,
input axi_wvalid,
output axi_wready,
input [32-1:0] axi_wdata,
input [4-1:0] axi_wstrb,
output axi_bvalid,
input axi_bready,
input axi_arvalid,
output axi_arready,
input [32-1:0] axi_araddr,
input [3-1:0] axi_arprot,
output axi_rvalid,
input axi_rready,
output [32-1:0] axi_rdata,
input [31:0] Q,
output reg CEN,
output reg WEN,
output reg [9:0] A,
output [31:0] D
); |
assign axi_awready = 1'b1;
assign axi_arready = 1'b1;
assign axi_wready = 1'b1;
reg [31:0] DP;
assign axi_rdata = Q;
always @(negedge CLK) begin
if (RST==1'b0) begin
A <= {10{1'b0}};
DP <= {32{1'b0}};
end else begin
if(axi_awvalid == 1'b1) begin
A <= axi_awaddr[9:0];
end else if(axi_arvalid == 1'b1) begin
A <= axi_araddr[9:0];
end
if(axi_wvalid == 1'b1) begin
DP <= axi_wdata;
end
end
end
reg reading1, reading2;
assign axi_rvalid = reading2;
always @(posedge CLK) begin
if (RST==1'b0) begin
reading1 <= 1'b0;
reading2 <= 1'b0;
end else begin
if(axi_rready == 1'b1 && reading1 == 1'b1 && reading2 == 1'b1) begin
reading1 <= 1'b0;
end else if(axi_arvalid == 1'b1) begin
reading1 <= 1'b1;
end
if(axi_rready == 1'b1 && reading1 == 1'b1 && reading2 == 1'b1) begin
reading2 <= 1'b0;
end else if(reading1 == 1'b1) begin
reading2 <= 1'b1;
end
end
end
reg writting1, writting2, writting3;
assign axi_bvalid = writting3;
always @(posedge CLK) begin
if (RST==1'b0) begin
writting1 <= 1'b0;
writting2 <= 1'b0;
writting3 <= 1'b0;
end else begin
if(axi_bready == 1'b1 && writting1 == 1'b1 && writting2 == 1'b1 && writting3 == 1'b1) begin
writting3 <= 1'b0;
end else if(writting2 == 1'b1) begin
writting3 <= 1'b1;
end else begin
writting3 <= writting3;
end
if(axi_bready == 1'b1 && writting1 == 1'b1 && writting2 == 1'b1 && writting3 == 1'b1) begin
writting1 <= 1'b0;
end else if(axi_awvalid == 1'b1) begin
writting1 <= 1'b1;
end else begin
writting1 <= writting1;
end
if(axi_bready == 1'b1 && writting1 == 1'b1 && writting2 == 1'b1 && writting3 == 1'b1) begin
writting2 <= 1'b0;
end else if(axi_wvalid == 1'b1) begin
writting2 <= 1'b1;
end else begin
writting2 <= writting2;
end
end
end
always @(negedge CLK) begin
if (RST==1'b0) begin
CEN <= 1'b1;
WEN <= 1'b1;
end else begin
CEN <= ~(reading1 | writting1);
WEN <= ~writting2;
end
end
assign D[7:0] = axi_wstrb[0]?DP[7:0] :Q[7:0];
assign D[15:8] = axi_wstrb[1]?DP[15:8] :Q[15:8];
assign D[23:16] = axi_wstrb[2]?DP[23:16]:Q[23:16];
assign D[31:24] = axi_wstrb[3]?DP[31:24]:Q[31:24];
endmodule | 0 |
139,445 | data/full_repos/permissive/87881270/hw1/clkrst.v | 87,881,270 | clkrst.v | v | 49 | 71 | [] | [] | [] | null | line:30: before: "begin" | null | 1: b'%Error: data/full_repos/permissive/87881270/hw1/clkrst.v:23: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87881270/hw1/clkrst.v:27: Unsupported: Ignoring delay on this delayed statement.\n #201 rst = 0; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87881270/hw1/clkrst.v:30: Unsupported: Ignoring delay on this delayed statement.\n always #50 begin \n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,905 | module | module clkrst (clk, rst, err);
output clk;
output rst;
input err;
reg clk;
reg rst;
integer cycle_count;
initial begin
$dumpvars;
cycle_count = 0;
rst = 1;
clk = 1;
#201 rst = 0;
end
always #50 begin
clk = ~clk;
if (clk & err) begin
$display("Error signal asserted");
$stop;
end
end
always @(posedge clk) begin
cycle_count = cycle_count + 1;
if (cycle_count > 100000) begin
$display("hmm....more than 100000 cycles of simulation...error?\n");
$finish;
end
end
endmodule | module clkrst (clk, rst, err); |
output clk;
output rst;
input err;
reg clk;
reg rst;
integer cycle_count;
initial begin
$dumpvars;
cycle_count = 0;
rst = 1;
clk = 1;
#201 rst = 0;
end
always #50 begin
clk = ~clk;
if (clk & err) begin
$display("Error signal asserted");
$stop;
end
end
always @(posedge clk) begin
cycle_count = cycle_count + 1;
if (cycle_count > 100000) begin
$display("hmm....more than 100000 cycles of simulation...error?\n");
$finish;
end
end
endmodule | 0 |
139,446 | data/full_repos/permissive/87881270/hw1/dff.v | 87,881,270 | dff.v | v | 23 | 71 | [] | [] | [] | [(6, 21)] | null | data/verilator_xmls/998fb9a8-bb05-4f10-961e-1b07cf24c7b1.xml | null | 304,906 | module | module dff (q, d, clk, rst);
output q;
input d;
input clk;
input rst;
reg state;
assign #(1) q = state;
always @(posedge clk) begin
state = rst? 0 : d;
end
endmodule | module dff (q, d, clk, rst); |
output q;
input d;
input clk;
input rst;
reg state;
assign #(1) q = state;
always @(posedge clk) begin
state = rst? 0 : d;
end
endmodule | 0 |
139,447 | data/full_repos/permissive/87881270/hw1/fulladd_16.v | 87,881,270 | fulladd_16.v | v | 12 | 38 | [] | [] | [] | [(2, 9)] | null | data/verilator_xmls/9b40d825-0d1b-439f-bc77-39bd43970cd6.xml | null | 304,907 | module | module fulladd_16 (input [15:0] A, B,
output [15:0] SUM,
output CO);
assign {CO, SUM} = A + B;
endmodule | module fulladd_16 (input [15:0] A, B,
output [15:0] SUM,
output CO); |
assign {CO, SUM} = A + B;
endmodule | 0 |
139,448 | data/full_repos/permissive/87881270/hw1/seqdec.v | 87,881,270 | seqdec.v | v | 60 | 58 | [] | [] | [] | [(1, 59)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/hw1/seqdec.v:14: Cannot find file containing module: 'dff'\n dff curr_state[1:0] (\n ^~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw1,data/full_repos/permissive/87881270/dff\n data/full_repos/permissive/87881270/hw1,data/full_repos/permissive/87881270/dff.v\n data/full_repos/permissive/87881270/hw1,data/full_repos/permissive/87881270/dff.sv\n dff\n dff.v\n dff.sv\n obj_dir/dff\n obj_dir/dff.v\n obj_dir/dff.sv\n%Error: data/full_repos/permissive/87881270/hw1/seqdec.v:40: Cannot find file containing module: 'dff'\n dff counter [15:0] (\n ^~~\n%Error: data/full_repos/permissive/87881270/hw1/seqdec.v:48: Cannot find file containing module: 'fulladd_16'\n fulladd_16 adder (\n ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 304,908 | module | module seqdec (
input Clk,
input Reset,
input InA,
output [15:0] Out
) ;
wire [1:0] state;
reg [1:0] next_state;
wire [15:0] count, new_count, increment;
dff curr_state[1:0] (
.q (state),
.d (next_state),
.clk (Clk),
.rst (Reset));
always @ (*) begin
case (state)
2'h0: begin
next_state = InA ? 2'h1 : 2'h0;
end
2'h1: begin
next_state = InA ? 2'h2 : 2'h0;
end
2'h2: begin
next_state = InA ? 2'h2 : 2'h0;
end
default: begin
next_state = 2'h0;
end
endcase
end
dff counter [15:0] (
.q (count),
.d (new_count),
.clk (Clk),
.rst (Reset));
fulladd_16 adder (
.SUM (new_count),
.CO (),
.A (count),
.B (increment));
assign increment = (state == 2'h2) ? 1 : 0;
assign Out = count;
endmodule | module seqdec (
input Clk,
input Reset,
input InA,
output [15:0] Out
) ; |
wire [1:0] state;
reg [1:0] next_state;
wire [15:0] count, new_count, increment;
dff curr_state[1:0] (
.q (state),
.d (next_state),
.clk (Clk),
.rst (Reset));
always @ (*) begin
case (state)
2'h0: begin
next_state = InA ? 2'h1 : 2'h0;
end
2'h1: begin
next_state = InA ? 2'h2 : 2'h0;
end
2'h2: begin
next_state = InA ? 2'h2 : 2'h0;
end
default: begin
next_state = 2'h0;
end
endcase
end
dff counter [15:0] (
.q (count),
.d (new_count),
.clk (Clk),
.rst (Reset));
fulladd_16 adder (
.SUM (new_count),
.CO (),
.A (count),
.B (increment));
assign increment = (state == 2'h2) ? 1 : 0;
assign Out = count;
endmodule | 0 |
139,449 | data/full_repos/permissive/87881270/hw1/seqdec_bench.v | 87,881,270 | seqdec_bench.v | v | 61 | 113 | [] | [] | [] | [(1, 60)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/hw1/seqdec_bench.v:16: Cannot find file containing module: 'seqdec'\n seqdec DUT (.InA(InA),.Clk(Clk),.Reset(Reset),.Out(Out));\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw1,data/full_repos/permissive/87881270/seqdec\n data/full_repos/permissive/87881270/hw1,data/full_repos/permissive/87881270/seqdec.v\n data/full_repos/permissive/87881270/hw1,data/full_repos/permissive/87881270/seqdec.sv\n seqdec\n seqdec.v\n seqdec.sv\n obj_dir/seqdec\n obj_dir/seqdec.v\n obj_dir/seqdec.sv\n%Error: data/full_repos/permissive/87881270/hw1/seqdec_bench.v:17: Cannot find file containing module: 'clkrst'\n clkrst my_ckrst ( .clk(Clk), .rst(Reset), .err(err));\n ^~~~~~\n%Error: Exiting due to 2 error(s)\n" | 304,909 | module | module seqdec_bench;
reg InA;
wire Clk;
wire Reset;
wire [15:0] Out;
reg [127:0] sequenc;
integer k;
reg [1:0] seq;
reg [1:0] seqp1;
reg [15:0] count;
wire err;
assign err = 1'b0;
seqdec DUT (.InA(InA),.Clk(Clk),.Reset(Reset),.Out(Out));
clkrst my_ckrst ( .clk(Clk), .rst(Reset), .err(err));
always@(posedge Clk)
begin
if (Reset == 1'b1)
begin
InA = 1'b0;
k = 0;
sequenc = 128'h0028_850A_972E_4284_5353_28A0_8597_4253;
seq = 2'h0;
seqp1 = 2'h0;
end
else
begin
InA = sequenc[127-k];
k = k + 1;
seq[1] <= seq[0];
seq[0] <= InA;
seqp1 <= seq;
if (k == 128) $finish;
end
end
always @ (posedge Clk ) begin
if (Reset == 1'b1) begin
count = 0;
end else begin
if (seqp1 === 2'h3) begin
count = count + 1;
end
end
end
always@(negedge Clk)
begin
if (count !== Out)
$display("ERRORCHECK :: Output mismatch got: %d, expoected: %d", Out, count);
end
endmodule | module seqdec_bench; |
reg InA;
wire Clk;
wire Reset;
wire [15:0] Out;
reg [127:0] sequenc;
integer k;
reg [1:0] seq;
reg [1:0] seqp1;
reg [15:0] count;
wire err;
assign err = 1'b0;
seqdec DUT (.InA(InA),.Clk(Clk),.Reset(Reset),.Out(Out));
clkrst my_ckrst ( .clk(Clk), .rst(Reset), .err(err));
always@(posedge Clk)
begin
if (Reset == 1'b1)
begin
InA = 1'b0;
k = 0;
sequenc = 128'h0028_850A_972E_4284_5353_28A0_8597_4253;
seq = 2'h0;
seqp1 = 2'h0;
end
else
begin
InA = sequenc[127-k];
k = k + 1;
seq[1] <= seq[0];
seq[0] <= InA;
seqp1 <= seq;
if (k == 128) $finish;
end
end
always @ (posedge Clk ) begin
if (Reset == 1'b1) begin
count = 0;
end else begin
if (seqp1 === 2'h3) begin
count = count + 1;
end
end
end
always@(negedge Clk)
begin
if (count !== Out)
$display("ERRORCHECK :: Output mismatch got: %d, expoected: %d", Out, count);
end
endmodule | 0 |
139,450 | data/full_repos/permissive/87881270/hw1/hw1_1/bit1in2to1mux.v | 87,881,270 | bit1in2to1mux.v | v | 16 | 41 | [] | [] | [] | [(1, 15)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/hw1/hw1_1/bit1in2to1mux.v:10: Cannot find file containing module: 'not1'\n not1 c1(S, w1);\n ^~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw1/hw1_1,data/full_repos/permissive/87881270/not1\n data/full_repos/permissive/87881270/hw1/hw1_1,data/full_repos/permissive/87881270/not1.v\n data/full_repos/permissive/87881270/hw1/hw1_1,data/full_repos/permissive/87881270/not1.sv\n not1\n not1.v\n not1.sv\n obj_dir/not1\n obj_dir/not1.v\n obj_dir/not1.sv\n%Error: data/full_repos/permissive/87881270/hw1/hw1_1/bit1in2to1mux.v:11: Cannot find file containing module: 'nand2'\n nand2 c2(lnA, w1, w2);\n ^~~~~\n%Error: data/full_repos/permissive/87881270/hw1/hw1_1/bit1in2to1mux.v:12: Cannot find file containing module: 'nand2'\n nand2 c3(lnB, S, w3);\n ^~~~~\n%Error: data/full_repos/permissive/87881270/hw1/hw1_1/bit1in2to1mux.v:13: Cannot find file containing module: 'nand2'\n nand2 c4(w2, w3, Out);\n ^~~~~\n%Error: Exiting due to 4 error(s)\n" | 304,910 | module | module bit1in2to1mux (lnA, lnB, S, Out);
input lnA;
input lnB;
input S;
output Out;
wire w1;
wire w2;
wire w3;
not1 c1(S, w1);
nand2 c2(lnA, w1, w2);
nand2 c3(lnB, S, w3);
nand2 c4(w2, w3, Out);
endmodule | module bit1in2to1mux (lnA, lnB, S, Out); |
input lnA;
input lnB;
input S;
output Out;
wire w1;
wire w2;
wire w3;
not1 c1(S, w1);
nand2 c2(lnA, w1, w2);
nand2 c3(lnB, S, w3);
nand2 c4(w2, w3, Out);
endmodule | 0 |
139,451 | data/full_repos/permissive/87881270/hw1/hw1_1/fourto1u2to1.v | 87,881,270 | fourto1u2to1.v | v | 19 | 49 | [] | [] | [] | [(1, 19)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/hw1/hw1_1/fourto1u2to1.v:15: Cannot find file containing module: 'bit1in2to1mux'\n bit1in2to1mux b1(lnA, lnB, S[0], w1);\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw1/hw1_1,data/full_repos/permissive/87881270/bit1in2to1mux\n data/full_repos/permissive/87881270/hw1/hw1_1,data/full_repos/permissive/87881270/bit1in2to1mux.v\n data/full_repos/permissive/87881270/hw1/hw1_1,data/full_repos/permissive/87881270/bit1in2to1mux.sv\n bit1in2to1mux\n bit1in2to1mux.v\n bit1in2to1mux.sv\n obj_dir/bit1in2to1mux\n obj_dir/bit1in2to1mux.v\n obj_dir/bit1in2to1mux.sv\n%Error: data/full_repos/permissive/87881270/hw1/hw1_1/fourto1u2to1.v:16: Cannot find file containing module: 'bit1in2to1mux'\n bit1in2to1mux b2(lnC, lnD, S[0], w2);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/87881270/hw1/hw1_1/fourto1u2to1.v:17: Cannot find file containing module: 'bit1in2to1mux'\n bit1in2to1mux b3(w1, w2, S[1], Out);\n ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 304,912 | module | module fourto1u2to1(lnA, lnB, lnC, lnD, S, Out);
input lnA;
input lnB;
input lnC;
input lnD;
input [1:0] S;
output Out;
wire w1;
wire w2;
wire w3;
bit1in2to1mux b1(lnA, lnB, S[0], w1);
bit1in2to1mux b2(lnC, lnD, S[0], w2);
bit1in2to1mux b3(w1, w2, S[1], Out);
endmodule | module fourto1u2to1(lnA, lnB, lnC, lnD, S, Out); |
input lnA;
input lnB;
input lnC;
input lnD;
input [1:0] S;
output Out;
wire w1;
wire w2;
wire w3;
bit1in2to1mux b1(lnA, lnB, S[0], w1);
bit1in2to1mux b2(lnC, lnD, S[0], w2);
bit1in2to1mux b3(w1, w2, S[1], Out);
endmodule | 0 |
139,452 | data/full_repos/permissive/87881270/hw1/hw1_1/nand2.v | 87,881,270 | nand2.v | v | 5 | 28 | [] | [] | [] | [(1, 5)] | null | data/verilator_xmls/dcca2f7c-3f30-4f95-95d6-ae078a950903.xml | null | 304,913 | module | module nand2 (in1,in2,out);
input in1,in2;
output out;
assign out = ~(in1 & in2);
endmodule | module nand2 (in1,in2,out); |
input in1,in2;
output out;
assign out = ~(in1 & in2);
endmodule | 0 |
139,453 | data/full_repos/permissive/87881270/hw1/hw1_1/nand3.v | 87,881,270 | nand3.v | v | 6 | 36 | [] | [] | [] | [(1, 5)] | null | data/verilator_xmls/714af2ae-c874-437a-b09f-abebf488f321.xml | null | 304,914 | module | module nand3 (in1,in2,in3,out);
input in1,in2,in3;
output out;
assign out = ~(in1 & in2 & in3);
endmodule | module nand3 (in1,in2,in3,out); |
input in1,in2,in3;
output out;
assign out = ~(in1 & in2 & in3);
endmodule | 0 |
139,454 | data/full_repos/permissive/87881270/hw1/hw1_1/nor2.v | 87,881,270 | nor2.v | v | 6 | 27 | [] | [] | [] | [(1, 5)] | null | data/verilator_xmls/8012aa32-10e3-4505-a3a5-d180eaee3bec.xml | null | 304,915 | module | module nor2 (in1,in2,out);
input in1,in2;
output out;
assign out = ~(in1 | in2);
endmodule | module nor2 (in1,in2,out); |
input in1,in2;
output out;
assign out = ~(in1 | in2);
endmodule | 0 |
139,455 | data/full_repos/permissive/87881270/hw1/hw1_1/nor3.v | 87,881,270 | nor3.v | v | 5 | 33 | [] | [] | [] | null | None: at end of input | data/verilator_xmls/c98a8299-1cfc-4147-bd51-cd9fe89432ab.xml | null | 304,916 | module | module nor3 (in1,in2,in3,out);
input in1,in2,in3;
output out;
assign out = ~(in1 | in2 | in3);
endmodule | module nor3 (in1,in2,in3,out); |
input in1,in2,in3;
output out;
assign out = ~(in1 | in2 | in3);
endmodule | 0 |
139,456 | data/full_repos/permissive/87881270/hw1/hw1_1/not1.v | 87,881,270 | not1.v | v | 5 | 23 | [] | [] | [] | [(1, 5)] | null | data/verilator_xmls/e1f4f01d-ad19-4f32-8a81-b20ffaf4c536.xml | null | 304,917 | module | module not1 (in1,out);
input in1;
output out;
assign out = ~in1;
endmodule | module not1 (in1,out); |
input in1;
output out;
assign out = ~in1;
endmodule | 0 |
139,457 | data/full_repos/permissive/87881270/hw1/hw1_1/quadmux4_1.v | 87,881,270 | quadmux4_1.v | v | 11 | 77 | [] | [] | [] | [(1, 11)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/hw1/hw1_1/quadmux4_1.v:9: Cannot find file containing module: 'fourto1u2to1'\n fourto1u2to1 a1 [3:0](InA[3:0], InB[3:0], InC[3:0], InD[3:0], S, Out[3:0]);\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw1/hw1_1,data/full_repos/permissive/87881270/fourto1u2to1\n data/full_repos/permissive/87881270/hw1/hw1_1,data/full_repos/permissive/87881270/fourto1u2to1.v\n data/full_repos/permissive/87881270/hw1/hw1_1,data/full_repos/permissive/87881270/fourto1u2to1.sv\n fourto1u2to1\n fourto1u2to1.v\n fourto1u2to1.sv\n obj_dir/fourto1u2to1\n obj_dir/fourto1u2to1.v\n obj_dir/fourto1u2to1.sv\n%Error: Exiting due to 1 error(s)\n" | 304,918 | module | module quadmux4_1(InA, InB, InC, InD, S, Out);
input [3:0] InA;
input [3:0] InB;
input [3:0] InC;
input [3:0] InD;
input [1:0] S;
output [3:0] Out;
fourto1u2to1 a1 [3:0](InA[3:0], InB[3:0], InC[3:0], InD[3:0], S, Out[3:0]);
endmodule | module quadmux4_1(InA, InB, InC, InD, S, Out); |
input [3:0] InA;
input [3:0] InB;
input [3:0] InC;
input [3:0] InD;
input [1:0] S;
output [3:0] Out;
fourto1u2to1 a1 [3:0](InA[3:0], InB[3:0], InC[3:0], InD[3:0], S, Out[3:0]);
endmodule | 0 |
139,458 | data/full_repos/permissive/87881270/hw1/hw1_1/quadmux4_1_bench.v | 87,881,270 | quadmux4_1_bench.v | v | 86 | 151 | [] | [] | [] | null | line:47: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/87881270/hw1/hw1_1/quadmux4_1_bench.v:47: Unsupported: Ignoring delay on this delayed statement.\n #3200 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/87881270/hw1/hw1_1/quadmux4_1_bench.v:24: Cannot find file containing module: \'clkrst\'\nclkrst my_clkrst( .clk(Clk), .rst(rst), .err(err));\n^~~~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw1/hw1_1,data/full_repos/permissive/87881270/clkrst\n data/full_repos/permissive/87881270/hw1/hw1_1,data/full_repos/permissive/87881270/clkrst.v\n data/full_repos/permissive/87881270/hw1/hw1_1,data/full_repos/permissive/87881270/clkrst.sv\n clkrst\n clkrst.v\n clkrst.sv\n obj_dir/clkrst\n obj_dir/clkrst.v\n obj_dir/clkrst.sv\n%Error: data/full_repos/permissive/87881270/hw1/hw1_1/quadmux4_1_bench.v:27: Cannot find file containing module: \'quadmux4_1\'\n quadmux4_1 DUT (.InA(InA), .InB(InB),.InC(InC),.InD(InD), .S(S), .Out(Out));\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/87881270/hw1/hw1_1/quadmux4_1_bench.v:56: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance quadmux4_1_bench\n InA = $random;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87881270/hw1/hw1_1/quadmux4_1_bench.v:57: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance quadmux4_1_bench\n InB = $random;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87881270/hw1/hw1_1/quadmux4_1_bench.v:58: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance quadmux4_1_bench\n InC = $random;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87881270/hw1/hw1_1/quadmux4_1_bench.v:59: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance quadmux4_1_bench\n InD = $random;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87881270/hw1/hw1_1/quadmux4_1_bench.v:60: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance quadmux4_1_bench\n S = $random;\n ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,919 | module | module quadmux4_1_bench;
reg [3:0] InA;
reg [3:0] InB;
reg [3:0] InC;
reg [3:0] InD;
reg [1:0] S;
wire [3:0] Out;
wire Clk;
wire rst;
wire err;
clkrst my_clkrst( .clk(Clk), .rst(rst), .err(err));
quadmux4_1 DUT (.InA(InA), .InB(InB),.InC(InC),.InD(InD), .S(S), .Out(Out));
initial
begin
InA = 4'b0001;
InB = 4'b1000;
InC = 4'b1010;
InD = 4'b0101;
S = 2'b00;
#3200 $finish;
end
always@(posedge Clk)
begin
InA = $random;
InB = $random;
InC = $random;
InD = $random;
S = $random;
end
always@(negedge Clk)
begin
case (S)
2'b00 :
if (Out !== InA) $display ("ERRORCHECK InA S=0");
2'b01 :
if (Out !== InB) $display ("ERRORCHECK InB S=1");
2'b10 :
if (Out !== InC) $display ("ERRORCHECK InC S=2");
2'b11 :
if (Out !== InD) $display ("ERRORCHECK InD S=3");
endcase
end
endmodule | module quadmux4_1_bench; |
reg [3:0] InA;
reg [3:0] InB;
reg [3:0] InC;
reg [3:0] InD;
reg [1:0] S;
wire [3:0] Out;
wire Clk;
wire rst;
wire err;
clkrst my_clkrst( .clk(Clk), .rst(rst), .err(err));
quadmux4_1 DUT (.InA(InA), .InB(InB),.InC(InC),.InD(InD), .S(S), .Out(Out));
initial
begin
InA = 4'b0001;
InB = 4'b1000;
InC = 4'b1010;
InD = 4'b0101;
S = 2'b00;
#3200 $finish;
end
always@(posedge Clk)
begin
InA = $random;
InB = $random;
InC = $random;
InD = $random;
S = $random;
end
always@(negedge Clk)
begin
case (S)
2'b00 :
if (Out !== InA) $display ("ERRORCHECK InA S=0");
2'b01 :
if (Out !== InB) $display ("ERRORCHECK InB S=1");
2'b10 :
if (Out !== InC) $display ("ERRORCHECK InC S=2");
2'b11 :
if (Out !== InD) $display ("ERRORCHECK InD S=3");
endcase
end
endmodule | 0 |
139,459 | data/full_repos/permissive/87881270/hw1/hw1_2/fadd1bit.v | 87,881,270 | fadd1bit.v | v | 17 | 38 | [] | [] | [] | [(1, 17)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/hw1/hw1_2/fadd1bit.v:11: Cannot find file containing module: 'xor2'\n xor2 c1(A, B, w1);\n ^~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw1/hw1_2,data/full_repos/permissive/87881270/xor2\n data/full_repos/permissive/87881270/hw1/hw1_2,data/full_repos/permissive/87881270/xor2.v\n data/full_repos/permissive/87881270/hw1/hw1_2,data/full_repos/permissive/87881270/xor2.sv\n xor2\n xor2.v\n xor2.sv\n obj_dir/xor2\n obj_dir/xor2.v\n obj_dir/xor2.sv\n%Error: data/full_repos/permissive/87881270/hw1/hw1_2/fadd1bit.v:12: Cannot find file containing module: 'nand2'\n nand2 c2(A, B, w2);\n ^~~~~\n%Error: data/full_repos/permissive/87881270/hw1/hw1_2/fadd1bit.v:13: Cannot find file containing module: 'nand2'\n nand2 c3(Cin, w1, w3);\n ^~~~~\n%Error: data/full_repos/permissive/87881270/hw1/hw1_2/fadd1bit.v:14: Cannot find file containing module: 'nand2'\n nand2 c4(w2, w3, Cout);\n ^~~~~\n%Error: data/full_repos/permissive/87881270/hw1/hw1_2/fadd1bit.v:15: Cannot find file containing module: 'xor2'\n xor2 c5(w1, Cin, S);\n ^~~~\n%Error: Exiting due to 5 error(s)\n" | 304,921 | module | module fadd1bit (A, B, Cin, S, Cout);
input A;
input B;
input Cin;
output S;
output Cout;
wire w1;
wire w2;
wire w3;
xor2 c1(A, B, w1);
nand2 c2(A, B, w2);
nand2 c3(Cin, w1, w3);
nand2 c4(w2, w3, Cout);
xor2 c5(w1, Cin, S);
endmodule | module fadd1bit (A, B, Cin, S, Cout); |
input A;
input B;
input Cin;
output S;
output Cout;
wire w1;
wire w2;
wire w3;
xor2 c1(A, B, w1);
nand2 c2(A, B, w2);
nand2 c3(Cin, w1, w3);
nand2 c4(w2, w3, Cout);
xor2 c5(w1, Cin, S);
endmodule | 0 |
139,460 | data/full_repos/permissive/87881270/hw1/hw1_2/fulladder16.v | 87,881,270 | fulladder16.v | v | 16 | 60 | [] | [] | [] | [(1, 16)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/hw1/hw1_2/fulladder16.v:11: Cannot find file containing module: 'rippleadd4bit'\n rippleadd4bit c1( 1'b0, A[3:0], B[3:0], w1, SUM[3:0]);\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw1/hw1_2,data/full_repos/permissive/87881270/rippleadd4bit\n data/full_repos/permissive/87881270/hw1/hw1_2,data/full_repos/permissive/87881270/rippleadd4bit.v\n data/full_repos/permissive/87881270/hw1/hw1_2,data/full_repos/permissive/87881270/rippleadd4bit.sv\n rippleadd4bit\n rippleadd4bit.v\n rippleadd4bit.sv\n obj_dir/rippleadd4bit\n obj_dir/rippleadd4bit.v\n obj_dir/rippleadd4bit.sv\n%Error: data/full_repos/permissive/87881270/hw1/hw1_2/fulladder16.v:12: Cannot find file containing module: 'rippleadd4bit'\n rippleadd4bit c2( w1, A[7:4], B[7:4], w2, SUM[7:4]);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/87881270/hw1/hw1_2/fulladder16.v:13: Cannot find file containing module: 'rippleadd4bit'\n rippleadd4bit c3( w2, A[11:8], B[11:8], w3, SUM[11:8]);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/87881270/hw1/hw1_2/fulladder16.v:14: Cannot find file containing module: 'rippleadd4bit'\n rippleadd4bit c4( w3, A[15:12], B[15:12], CO, SUM[15:12]);\n ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 304,922 | module | module fulladder16 (A,B,SUM,CO);
input [15:0]A;
input [15:0]B;
output CO;
output [15:0]SUM;
wire w1;
wire w2;
wire w3;
rippleadd4bit c1( 1'b0, A[3:0], B[3:0], w1, SUM[3:0]);
rippleadd4bit c2( w1, A[7:4], B[7:4], w2, SUM[7:4]);
rippleadd4bit c3( w2, A[11:8], B[11:8], w3, SUM[11:8]);
rippleadd4bit c4( w3, A[15:12], B[15:12], CO, SUM[15:12]);
endmodule | module fulladder16 (A,B,SUM,CO); |
input [15:0]A;
input [15:0]B;
output CO;
output [15:0]SUM;
wire w1;
wire w2;
wire w3;
rippleadd4bit c1( 1'b0, A[3:0], B[3:0], w1, SUM[3:0]);
rippleadd4bit c2( w1, A[7:4], B[7:4], w2, SUM[7:4]);
rippleadd4bit c3( w2, A[11:8], B[11:8], w3, SUM[11:8]);
rippleadd4bit c4( w3, A[15:12], B[15:12], CO, SUM[15:12]);
endmodule | 0 |
139,461 | data/full_repos/permissive/87881270/hw1/hw1_2/fulladder_bench.v | 87,881,270 | fulladder_bench.v | v | 40 | 67 | [] | [] | [] | null | line:21: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/87881270/hw1/hw1_2/fulladder_bench.v:21: Unsupported: Ignoring delay on this delayed statement.\n #3200 $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/87881270/hw1/hw1_2/fulladder_bench.v:13: Cannot find file containing module: \'clkrst\'\n clkrst my_clkrst( .clk(Clk), .rst(rst), .err(err));\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw1/hw1_2,data/full_repos/permissive/87881270/clkrst\n data/full_repos/permissive/87881270/hw1/hw1_2,data/full_repos/permissive/87881270/clkrst.v\n data/full_repos/permissive/87881270/hw1/hw1_2,data/full_repos/permissive/87881270/clkrst.sv\n clkrst\n clkrst.v\n clkrst.sv\n obj_dir/clkrst\n obj_dir/clkrst.v\n obj_dir/clkrst.sv\n%Error: data/full_repos/permissive/87881270/hw1/hw1_2/fulladder_bench.v:14: Cannot find file containing module: \'fulladder16\'\n fulladder16 DUT (.A(A[15:0]), .B(B[15:0]), .SUM(SUM), .CO(CO));\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/87881270/hw1/hw1_2/fulladder_bench.v:26: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance fulladder_bench\n A[15:0] = $random;\n ^\n%Warning-WIDTH: data/full_repos/permissive/87881270/hw1/hw1_2/fulladder_bench.v:27: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance fulladder_bench\n B[15:0] = $random;\n ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,923 | module | module fulladder_bench;
reg [16:0] A;
reg [16:0] B;
reg [16:0] Sumcalc;
wire [15:0] SUM;
wire CO;
wire Clk;
wire rst;
wire err;
clkrst my_clkrst( .clk(Clk), .rst(rst), .err(err));
fulladder16 DUT (.A(A[15:0]), .B(B[15:0]), .SUM(SUM), .CO(CO));
initial
begin
A = 17'b0_0000_0000_0000_0000;
B = 17'b0_0000_0000_0000_0000;
#3200 $finish;
end
always@(posedge Clk)
begin
A[15:0] = $random;
B[15:0] = $random;
end
always@(negedge Clk)
begin
Sumcalc = A+B;
$display("A : %x, B%x, Sum %x", A, B, SUM);
if (Sumcalc[15:0] !== SUM) $display ("ERRORCHECK Sum error");
if (Sumcalc[16] !== CO) $display ("ERRORCHECK CO error");
end
endmodule | module fulladder_bench; |
reg [16:0] A;
reg [16:0] B;
reg [16:0] Sumcalc;
wire [15:0] SUM;
wire CO;
wire Clk;
wire rst;
wire err;
clkrst my_clkrst( .clk(Clk), .rst(rst), .err(err));
fulladder16 DUT (.A(A[15:0]), .B(B[15:0]), .SUM(SUM), .CO(CO));
initial
begin
A = 17'b0_0000_0000_0000_0000;
B = 17'b0_0000_0000_0000_0000;
#3200 $finish;
end
always@(posedge Clk)
begin
A[15:0] = $random;
B[15:0] = $random;
end
always@(negedge Clk)
begin
Sumcalc = A+B;
$display("A : %x, B%x, Sum %x", A, B, SUM);
if (Sumcalc[15:0] !== SUM) $display ("ERRORCHECK Sum error");
if (Sumcalc[16] !== CO) $display ("ERRORCHECK CO error");
end
endmodule | 0 |
139,462 | data/full_repos/permissive/87881270/hw1/hw1_2/rippleadd4bit.v | 87,881,270 | rippleadd4bit.v | v | 12 | 44 | [] | [] | [] | null | line:1: before: "[" | null | 1: b"%Error: data/full_repos/permissive/87881270/hw1/hw1_2/rippleadd4bit.v:7: Cannot find file containing module: 'fadd1bit'\n fadd1bit c1(A[0], B[0], CI, SUM[0], w1);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw1/hw1_2,data/full_repos/permissive/87881270/fadd1bit\n data/full_repos/permissive/87881270/hw1/hw1_2,data/full_repos/permissive/87881270/fadd1bit.v\n data/full_repos/permissive/87881270/hw1/hw1_2,data/full_repos/permissive/87881270/fadd1bit.sv\n fadd1bit\n fadd1bit.v\n fadd1bit.sv\n obj_dir/fadd1bit\n obj_dir/fadd1bit.v\n obj_dir/fadd1bit.sv\n%Error: data/full_repos/permissive/87881270/hw1/hw1_2/rippleadd4bit.v:8: Cannot find file containing module: 'fadd1bit'\n fadd1bit c2(A[1], B[1], w1, SUM[1], w2);\n ^~~~~~~~\n%Error: data/full_repos/permissive/87881270/hw1/hw1_2/rippleadd4bit.v:9: Cannot find file containing module: 'fadd1bit'\n fadd1bit c3(A[2], B[2], w2, SUM[2], w3);\n ^~~~~~~~\n%Error: data/full_repos/permissive/87881270/hw1/hw1_2/rippleadd4bit.v:10: Cannot find file containing module: 'fadd1bit'\n fadd1bit c4(A[3], B[3], w3, SUM[3], CO);\n ^~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 304,929 | module | module rippleadd4bit (input CI, [3:0] A, B,
output CO, [3:0]SUM);
wire w1;
wire w2;
wire w3;
fadd1bit c1(A[0], B[0], CI, SUM[0], w1);
fadd1bit c2(A[1], B[1], w1, SUM[1], w2);
fadd1bit c3(A[2], B[2], w2, SUM[2], w3);
fadd1bit c4(A[3], B[3], w3, SUM[3], CO);
endmodule | module rippleadd4bit (input CI, [3:0] A, B,
output CO, [3:0]SUM); |
wire w1;
wire w2;
wire w3;
fadd1bit c1(A[0], B[0], CI, SUM[0], w1);
fadd1bit c2(A[1], B[1], w1, SUM[1], w2);
fadd1bit c3(A[2], B[2], w2, SUM[2], w3);
fadd1bit c4(A[3], B[3], w3, SUM[3], CO);
endmodule | 0 |
139,463 | data/full_repos/permissive/87881270/hw1/hw1_2/xor2.v | 87,881,270 | xor2.v | v | 7 | 27 | [] | [] | [] | [(1, 5)] | null | data/verilator_xmls/a8801298-50cf-4ddf-9fd5-49857693513d.xml | null | 304,930 | module | module xor2 (in1,in2,out);
input in1,in2;
output out;
assign out = in1 ^ in2;
endmodule | module xor2 (in1,in2,out); |
input in1,in2;
output out;
assign out = in1 ^ in2;
endmodule | 0 |
139,464 | data/full_repos/permissive/87881270/hw1/hw1_2/xor3.v | 87,881,270 | xor3.v | v | 7 | 33 | [] | [] | [] | [(1, 6)] | null | data/verilator_xmls/6744a3b7-27cb-4a7f-869b-3e25a04ee333.xml | null | 304,931 | module | module xor3 (in1,in2,in3,out);
input in1,in2,in3;
output out;
assign out = in1 ^ in2 ^ in3;
endmodule | module xor3 (in1,in2,in3,out); |
input in1,in2,in3;
output out;
assign out = in1 ^ in2 ^ in3;
endmodule | 0 |
139,465 | data/full_repos/permissive/87881270/hw1/hw1_3/seqdec_28_bench.v | 87,881,270 | seqdec_28_bench.v | v | 50 | 113 | [] | [] | [] | [(1, 49)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/hw1/hw1_3/seqdec_28_bench.v:14: Cannot find file containing module: 'seqdec_28'\n seqdec_28 DUT (.InA(InA),.Clk(Clk),.Reset(Reset),.Out(Out));\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw1/hw1_3,data/full_repos/permissive/87881270/seqdec_28\n data/full_repos/permissive/87881270/hw1/hw1_3,data/full_repos/permissive/87881270/seqdec_28.v\n data/full_repos/permissive/87881270/hw1/hw1_3,data/full_repos/permissive/87881270/seqdec_28.sv\n seqdec_28\n seqdec_28.v\n seqdec_28.sv\n obj_dir/seqdec_28\n obj_dir/seqdec_28.v\n obj_dir/seqdec_28.sv\n%Error: data/full_repos/permissive/87881270/hw1/hw1_3/seqdec_28_bench.v:15: Cannot find file containing module: 'clkrst'\n clkrst my_ckrst ( .clk(Clk), .rst(Reset), .err(err));\n ^~~~~~\n%Error: Exiting due to 2 error(s)\n" | 304,939 | module | module seqdec_28_bench;
reg InA;
wire Clk;
wire Reset;
wire Out;
reg [127:0] sequenc;
integer k;
reg [7:0] seq;
reg [7:0] seqp1;
wire err;
assign err = 1'b0;
seqdec_28 DUT (.InA(InA),.Clk(Clk),.Reset(Reset),.Out(Out));
clkrst my_ckrst ( .clk(Clk), .rst(Reset), .err(err));
always@(posedge Clk)
begin
if (Reset == 1'b1)
begin
InA = 1'b0;
k = 0;
sequenc = 128'h0028_850A_972E_4284_5353_28A0_8597_4253;
seq = 8'h00;
seqp1 = 8'h00;
end
else
begin
InA = sequenc[127-k];
k = k + 1;
seq[7:1] <= seq[6:0];
seq[0] <= InA;
seqp1 <= seq;
if (k == 128) $finish;
end
end
always@(negedge Clk)
begin
if ((Out !== 1'b1) && (seqp1 === 8'h28))
$display("ERRORCHECK :: Out not going to 1 as expected");
if ((Out === 1'b1) && (seqp1 !== 8'h28))
$display("ERRORCHECK :: Out going to 1 unnexpected");
end
endmodule | module seqdec_28_bench; |
reg InA;
wire Clk;
wire Reset;
wire Out;
reg [127:0] sequenc;
integer k;
reg [7:0] seq;
reg [7:0] seqp1;
wire err;
assign err = 1'b0;
seqdec_28 DUT (.InA(InA),.Clk(Clk),.Reset(Reset),.Out(Out));
clkrst my_ckrst ( .clk(Clk), .rst(Reset), .err(err));
always@(posedge Clk)
begin
if (Reset == 1'b1)
begin
InA = 1'b0;
k = 0;
sequenc = 128'h0028_850A_972E_4284_5353_28A0_8597_4253;
seq = 8'h00;
seqp1 = 8'h00;
end
else
begin
InA = sequenc[127-k];
k = k + 1;
seq[7:1] <= seq[6:0];
seq[0] <= InA;
seqp1 <= seq;
if (k == 128) $finish;
end
end
always@(negedge Clk)
begin
if ((Out !== 1'b1) && (seqp1 === 8'h28))
$display("ERRORCHECK :: Out not going to 1 as expected");
if ((Out === 1'b1) && (seqp1 !== 8'h28))
$display("ERRORCHECK :: Out going to 1 unnexpected");
end
endmodule | 0 |
139,466 | data/full_repos/permissive/87881270/hw1/hw1_3/seqdec_42.v | 87,881,270 | seqdec_42.v | v | 59 | 54 | [] | [] | [] | [(3, 59)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/hw1/hw1_3/seqdec_42.v:13: Cannot find file containing module: 'dff'\n dff curr_state[3:0] (\n ^~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw1/hw1_3,data/full_repos/permissive/87881270/dff\n data/full_repos/permissive/87881270/hw1/hw1_3,data/full_repos/permissive/87881270/dff.v\n data/full_repos/permissive/87881270/hw1/hw1_3,data/full_repos/permissive/87881270/dff.sv\n dff\n dff.v\n dff.sv\n obj_dir/dff\n obj_dir/dff.v\n obj_dir/dff.sv\n%Error: Exiting due to 1 error(s)\n" | 304,940 | module | module seqdec_42 (
input InA,
input Clk,
input Reset,
output Out
) ;
wire [3:0] state;
reg [3:0] next_state;
dff curr_state[3:0] (
.q (state),
.d (next_state),
.clk (Clk),
.rst (Reset));
always @ (*) begin
case (state)
4'h0: begin
next_state = InA ? 4'h0 : 4'h1;
end
4'h1: begin
next_state = InA ? 4'h2 : 4'h1;
end
4'h2: begin
next_state = InA ? 4'h0 : 4'h3;
end
4'h3: begin
next_state = InA ? 4'h1 : 4'h4;
end
4'h4: begin
next_state = InA ? 4'h1 : 4'h5;
end
4'h5: begin
next_state = InA ? 4'h1 : 4'h6;
end
4'h6: begin
next_state = InA ? 4'h7 : 4'h1;
end
4'h7: begin
next_state = InA ? 4'h0 : 4'h8;
end
4'h8: begin
next_state = InA ? 4'h2 : 4'h4;
end
default: begin
next_state = 4'h0;
end
endcase
end
assign Out = (state==4'h8)?1:0;
endmodule | module seqdec_42 (
input InA,
input Clk,
input Reset,
output Out
) ; |
wire [3:0] state;
reg [3:0] next_state;
dff curr_state[3:0] (
.q (state),
.d (next_state),
.clk (Clk),
.rst (Reset));
always @ (*) begin
case (state)
4'h0: begin
next_state = InA ? 4'h0 : 4'h1;
end
4'h1: begin
next_state = InA ? 4'h2 : 4'h1;
end
4'h2: begin
next_state = InA ? 4'h0 : 4'h3;
end
4'h3: begin
next_state = InA ? 4'h1 : 4'h4;
end
4'h4: begin
next_state = InA ? 4'h1 : 4'h5;
end
4'h5: begin
next_state = InA ? 4'h1 : 4'h6;
end
4'h6: begin
next_state = InA ? 4'h7 : 4'h1;
end
4'h7: begin
next_state = InA ? 4'h0 : 4'h8;
end
4'h8: begin
next_state = InA ? 4'h2 : 4'h4;
end
default: begin
next_state = 4'h0;
end
endcase
end
assign Out = (state==4'h8)?1:0;
endmodule | 0 |
139,467 | data/full_repos/permissive/87881270/hw2/hw2_1/shifter_hier.v | 87,881,270 | shifter_hier.v | v | 32 | 47 | [] | [] | [] | [(1, 31)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/hw2/hw2_1/shifter_hier.v:14: Cannot find file containing module: 'clkrst'\n clkrst c0(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw2/hw2_1,data/full_repos/permissive/87881270/clkrst\n data/full_repos/permissive/87881270/hw2/hw2_1,data/full_repos/permissive/87881270/clkrst.v\n data/full_repos/permissive/87881270/hw2/hw2_1,data/full_repos/permissive/87881270/clkrst.sv\n clkrst\n clkrst.v\n clkrst.sv\n obj_dir/clkrst\n obj_dir/clkrst.v\n obj_dir/clkrst.sv\n%Error: data/full_repos/permissive/87881270/hw2/hw2_1/shifter_hier.v:22: Cannot find file containing module: 'shifter'\n shifter s0(\n ^~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 304,949 | module | module shifter_hier(In, Cnt, Op, Out);
input [15:0] In;
input [3:0] Cnt;
input [1:0] Op;
output [15:0] Out;
wire clk;
wire rst;
wire err;
assign err = 1'b0;
clkrst c0(
.clk (clk),
.rst (rst),
.err (err)
);
shifter s0(
.Out (Out),
.In (In),
.Cnt (Cnt),
.Op (Op)
);
endmodule | module shifter_hier(In, Cnt, Op, Out); |
input [15:0] In;
input [3:0] Cnt;
input [1:0] Op;
output [15:0] Out;
wire clk;
wire rst;
wire err;
assign err = 1'b0;
clkrst c0(
.clk (clk),
.rst (rst),
.err (err)
);
shifter s0(
.Out (Out),
.In (In),
.Cnt (Cnt),
.Op (Op)
);
endmodule | 0 |
139,468 | data/full_repos/permissive/87881270/hw2/hw2_1/shifter_hier_bench.v | 87,881,270 | shifter_hier_bench.v | v | 86 | 136 | [] | [] | [] | [(1, 85)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/87881270/hw2/hw2_1/shifter_hier_bench.v:22: Unsupported: Ignoring delay on this delayed statement.\n #5000;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/87881270/hw2/hw2_1/shifter_hier_bench.v:30: Can\'t find definition of \'clk\' in dotted variable: \'DUT.clk\'\n always@(posedge DUT.clk)\n ^~~\n%Error: data/full_repos/permissive/87881270/hw2/hw2_1/shifter_hier_bench.v:39: Can\'t find definition of \'clk\' in dotted variable: \'DUT.clk\'\n always@(negedge DUT.clk)\n ^~~\n%Error: data/full_repos/permissive/87881270/hw2/hw2_1/shifter_hier_bench.v:30: Unsupported: Complex statement in sensitivity list\n always@(posedge DUT.clk)\n ^~~~~~~\n%Error: data/full_repos/permissive/87881270/hw2/hw2_1/shifter_hier_bench.v:39: Unsupported: Complex statement in sensitivity list\n always@(negedge DUT.clk)\n ^~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,950 | module | module shifter_hier_bench;
reg [15:0] In;
reg [3:0] Cnt;
reg [1:0] Op;
wire [15:0] Out;
reg fail;
reg [31:0] Expected;
integer idx;
shifter_hier DUT (.In(In), .Cnt(Cnt), .Op(Op), .Out(Out));
initial
begin
In = 16'h0000;
Cnt = 4'b0000;
Op = 2'b00;
fail = 0;
#5000;
if (fail)
$display("TEST FAILED");
else
$display("TEST PASSED");
$finish;
end
always@(posedge DUT.clk)
begin
In[15:0] = $random;
Cnt[3:0] = $random;
Op[1:0] = $random;
end
always@(negedge DUT.clk)
begin
case (Op)
2'b00 :
begin
Expected = In << Cnt | In >> 16-Cnt;
if (Expected[15:0] !== Out) begin
$display("ERRORCHECK :: Shifter :: Rotate Left : Count : %d, In = %x ; Expected : %x, Got %x", Cnt, In, Expected[15:0], Out);
fail = 1;
end
end
2'b01 :
begin
Expected = In << Cnt;
if (Expected[15:0] !== Out) begin
$display("ERRORCHECK :: Shifter :: Shift Left : Count : %d, In = %x ; Expected : %x, Got %x", Cnt, In, Expected[15:0], Out);
fail = 1;
end
end
2'b10 :
begin
for(idx = 31; idx > 15 ; idx = idx - 1)
Expected[idx] = In[15];
Expected[15:0] = In[15:0];
Expected[15:0] = Expected >> Cnt;
if (Expected[15:0] !== Out) begin
$display("ERRORCHECK :: Shifter :: Shift Right Arith : Count : %d, In = %x ; Expected : %x, Got %x", Cnt, In, Expected[15:0], Out);
fail = 1;
end
end
2'b11 :
begin
Expected = In >> Cnt;
if (Expected[15:0] !== Out) begin
$display("ERRORCHECK :: Shifter :: Shift Right Logic : Count : %d, In = %x ; Expected : %x, Got %x", Cnt, In, Expected[15:0], Out);
fail = 1;
end
end
endcase
end
endmodule | module shifter_hier_bench; |
reg [15:0] In;
reg [3:0] Cnt;
reg [1:0] Op;
wire [15:0] Out;
reg fail;
reg [31:0] Expected;
integer idx;
shifter_hier DUT (.In(In), .Cnt(Cnt), .Op(Op), .Out(Out));
initial
begin
In = 16'h0000;
Cnt = 4'b0000;
Op = 2'b00;
fail = 0;
#5000;
if (fail)
$display("TEST FAILED");
else
$display("TEST PASSED");
$finish;
end
always@(posedge DUT.clk)
begin
In[15:0] = $random;
Cnt[3:0] = $random;
Op[1:0] = $random;
end
always@(negedge DUT.clk)
begin
case (Op)
2'b00 :
begin
Expected = In << Cnt | In >> 16-Cnt;
if (Expected[15:0] !== Out) begin
$display("ERRORCHECK :: Shifter :: Rotate Left : Count : %d, In = %x ; Expected : %x, Got %x", Cnt, In, Expected[15:0], Out);
fail = 1;
end
end
2'b01 :
begin
Expected = In << Cnt;
if (Expected[15:0] !== Out) begin
$display("ERRORCHECK :: Shifter :: Shift Left : Count : %d, In = %x ; Expected : %x, Got %x", Cnt, In, Expected[15:0], Out);
fail = 1;
end
end
2'b10 :
begin
for(idx = 31; idx > 15 ; idx = idx - 1)
Expected[idx] = In[15];
Expected[15:0] = In[15:0];
Expected[15:0] = Expected >> Cnt;
if (Expected[15:0] !== Out) begin
$display("ERRORCHECK :: Shifter :: Shift Right Arith : Count : %d, In = %x ; Expected : %x, Got %x", Cnt, In, Expected[15:0], Out);
fail = 1;
end
end
2'b11 :
begin
Expected = In >> Cnt;
if (Expected[15:0] !== Out) begin
$display("ERRORCHECK :: Shifter :: Shift Right Logic : Count : %d, In = %x ; Expected : %x, Got %x", Cnt, In, Expected[15:0], Out);
fail = 1;
end
end
endcase
end
endmodule | 0 |
139,469 | data/full_repos/permissive/87881270/hw2/hw2_2/alu.v | 87,881,270 | alu.v | v | 56 | 88 | [] | [] | [] | null | line:34: before: "assign" | null | 1: b"%Error: data/full_repos/permissive/87881270/hw2/hw2_2/alu.v:23: Cannot find file containing module: 'carry_lookahead_16bit'\n carry_lookahead_16bit a1(sA,sB,Cin,cout,w5);\n ^~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw2/hw2_2,data/full_repos/permissive/87881270/carry_lookahead_16bit\n data/full_repos/permissive/87881270/hw2/hw2_2,data/full_repos/permissive/87881270/carry_lookahead_16bit.v\n data/full_repos/permissive/87881270/hw2/hw2_2,data/full_repos/permissive/87881270/carry_lookahead_16bit.sv\n carry_lookahead_16bit\n carry_lookahead_16bit.v\n carry_lookahead_16bit.sv\n obj_dir/carry_lookahead_16bit\n obj_dir/carry_lookahead_16bit.v\n obj_dir/carry_lookahead_16bit.sv\n%Error: data/full_repos/permissive/87881270/hw2/hw2_2/alu.v:25: Cannot find file containing module: 'shifter'\n shifter s1(sA, sB[3:0], Op[1:0], w1);\n ^~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 304,951 | module | module alu (A, B, Cin, Op, invA, invB, sign, Out, Ofl, Z);
input [15:0] A;
input [15:0] B;
input Cin;
input [2:0] Op;
input invA;
input invB;
input sign;
output [15:0] Out;
output Ofl;
output Z;
reg [15:0]value;
wire [15:0]sA,sB,w1,w5;
wire cout;
reg ofl = 1'b0;
assign sA = invA? ~A:A;
assign sB = invB? ~B:B;
carry_lookahead_16bit a1(sA,sB,Cin,cout,w5);
shifter s1(sA, sB[3:0], Op[1:0], w1);
always @ (*) begin
casex(Op)
3'b0??:begin
value = w1;
end
3'o4:begin
value = w5;
assign ofl = sign?(((sA[15]~^sB[15])&(cout^sB[15]))? 1'b1:1'b0 ):(cout? 1'b1:1'b0 );
end
3'o5:begin
value = sA|sB;
end
3'o6:begin
value = sA^sB;
end
3'o7:begin
value = sA&sB;
end
default: begin
$display("Error");
end
endcase
end
assign Ofl = ofl;
assign Out=value;
assign Z=&value;
endmodule | module alu (A, B, Cin, Op, invA, invB, sign, Out, Ofl, Z); |
input [15:0] A;
input [15:0] B;
input Cin;
input [2:0] Op;
input invA;
input invB;
input sign;
output [15:0] Out;
output Ofl;
output Z;
reg [15:0]value;
wire [15:0]sA,sB,w1,w5;
wire cout;
reg ofl = 1'b0;
assign sA = invA? ~A:A;
assign sB = invB? ~B:B;
carry_lookahead_16bit a1(sA,sB,Cin,cout,w5);
shifter s1(sA, sB[3:0], Op[1:0], w1);
always @ (*) begin
casex(Op)
3'b0??:begin
value = w1;
end
3'o4:begin
value = w5;
assign ofl = sign?(((sA[15]~^sB[15])&(cout^sB[15]))? 1'b1:1'b0 ):(cout? 1'b1:1'b0 );
end
3'o5:begin
value = sA|sB;
end
3'o6:begin
value = sA^sB;
end
3'o7:begin
value = sA&sB;
end
default: begin
$display("Error");
end
endcase
end
assign Ofl = ofl;
assign Out=value;
assign Z=&value;
endmodule | 0 |
139,470 | data/full_repos/permissive/87881270/hw2/hw2_2/alu_hier.v | 87,881,270 | alu_hier.v | v | 43 | 63 | [] | [] | [] | [(1, 42)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/hw2/hw2_2/alu_hier.v:20: Cannot find file containing module: 'clkrst'\n clkrst c0(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw2/hw2_2,data/full_repos/permissive/87881270/clkrst\n data/full_repos/permissive/87881270/hw2/hw2_2,data/full_repos/permissive/87881270/clkrst.v\n data/full_repos/permissive/87881270/hw2/hw2_2,data/full_repos/permissive/87881270/clkrst.sv\n clkrst\n clkrst.v\n clkrst.sv\n obj_dir/clkrst\n obj_dir/clkrst.v\n obj_dir/clkrst.sv\n%Error: data/full_repos/permissive/87881270/hw2/hw2_2/alu_hier.v:28: Cannot find file containing module: 'alu'\n alu a0(\n ^~~\n%Error: Exiting due to 2 error(s)\n" | 304,952 | module | module alu_hier(A, B, Cin, Op, invA, invB, sign, Out, Ofl, Z);
input [15:0] A;
input [15:0] B;
input Cin;
input [2:0] Op;
input invA;
input invB;
input sign;
output [15:0] Out;
output Ofl;
output Z;
wire clk;
wire rst;
wire err;
assign err = 1'b0;
clkrst c0(
.clk (clk),
.rst (rst),
.err (err)
);
alu a0(
.Out (Out[15:0]),
.Ofl (Ofl),
.Z (Z),
.A (A[15:0]),
.B (B[15:0]),
.Cin (Cin),
.Op (Op[2:0]),
.invA (invA),
.invB (invB),
.sign (sign)
);
endmodule | module alu_hier(A, B, Cin, Op, invA, invB, sign, Out, Ofl, Z); |
input [15:0] A;
input [15:0] B;
input Cin;
input [2:0] Op;
input invA;
input invB;
input sign;
output [15:0] Out;
output Ofl;
output Z;
wire clk;
wire rst;
wire err;
assign err = 1'b0;
clkrst c0(
.clk (clk),
.rst (rst),
.err (err)
);
alu a0(
.Out (Out[15:0]),
.Ofl (Ofl),
.Z (Z),
.A (A[15:0]),
.B (B[15:0]),
.Cin (Cin),
.Op (Op[2:0]),
.invA (invA),
.invB (invB),
.sign (sign)
);
endmodule | 0 |
139,471 | data/full_repos/permissive/87881270/hw2/hw2_2/alu_hier_bench.v | 87,881,270 | alu_hier_bench.v | v | 151 | 285 | [] | [] | [] | [(1, 150)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/87881270/hw2/hw2_2/alu_hier_bench.v:37: Unsupported: Ignoring delay on this delayed statement.\n #5000;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/87881270/hw2/hw2_2/alu_hier_bench.v:48: Can\'t find definition of \'clk\' in dotted variable: \'DUT.clk\'\n always@(posedge DUT.clk)\n ^~~\n%Error: data/full_repos/permissive/87881270/hw2/hw2_2/alu_hier_bench.v:61: Can\'t find definition of \'clk\' in dotted variable: \'DUT.clk\'\n always@(negedge DUT.clk)\n ^~~\n%Error: data/full_repos/permissive/87881270/hw2/hw2_2/alu_hier_bench.v:48: Unsupported: Complex statement in sensitivity list\n always@(posedge DUT.clk)\n ^~~~~~~\n%Error: data/full_repos/permissive/87881270/hw2/hw2_2/alu_hier_bench.v:61: Unsupported: Complex statement in sensitivity list\n always@(negedge DUT.clk)\n ^~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,953 | module | module alu_hier_bench;
reg [15:0] A_pre_inv;
reg [15:0] B_pre_inv;
wire [15:0] A;
wire [15:0] B;
reg Cin;
reg [2:0] Op;
reg invA;
reg invB;
reg sign;
wire [15:0] Out;
wire Ofl;
wire Z;
reg fail;
reg cerror;
reg [31:0] ExOut;
reg ExOfl;
reg ExZ;
integer idx;
alu_hier DUT (.A(A_pre_inv), .B(B_pre_inv), .Cin(Cin), .Op(Op), .invA(invA), .invB(invB), .sign(sign), .Out(Out), .Ofl(Ofl), .Z(Z));
initial
begin
A_pre_inv = 16'b0000;
B_pre_inv = 16'b0000;
Cin = 1'b0;
Op = 3'b000;
invA = 1'b0;
invB = 1'b0;
sign = 1'b0;
fail = 0;
#5000;
if (fail)
$display("TEST FAILED");
else
$display("TEST PASSED");
$finish;
end
assign A = invA ? ~A_pre_inv : A_pre_inv;
assign B = invB ? ~B_pre_inv : B_pre_inv;
always@(posedge DUT.clk)
begin
A_pre_inv = $random;
B_pre_inv = $random;
Cin = $random;
Op = $random;
invA = $random;
invB = $random;
sign = $random;
end
always@(negedge DUT.clk)
begin
cerror = 1'b0;
ExOut = 32'h0000_0000;
ExZ = 1'b0;
ExOfl = 1'b0;
case (Op)
3'b000 :
begin
ExOut = A << B[3:0] | A >> 16-B[3:0];
if (ExOut[15:0] !== Out)
cerror = 1'b1;
end
3'b001 :
begin
ExOut = A << B[3:0];
if (ExOut[15:0] !== Out)
cerror = 1'b1;
end
3'b010 :
begin
for(idx = 31; idx > 15 ; idx = idx - 1)
ExOut[idx] = A[15];
ExOut[15:0] = A[15:0];
ExOut[15:0] = ExOut >> B[3:0];
if (ExOut[15:0] !== Out)
cerror = 1'b1;
end
3'b011 :
begin
ExOut = A >> B[3:0];
if (ExOut[15:0] !== Out)
cerror = 1'b1;
end
3'b100 :
begin
ExOut = A + B + Cin;
if (ExOut[15:0] == 16'h0000)
ExZ = 1'b1;
if (sign == 1'b1)
ExOfl = ExOut[15]^A[15]^B[15]^ExOut[16];
else
ExOfl = ExOut[16];
if ((ExOut[15:0] !== Out) || (ExZ !== Z) || (ExOfl !== Ofl))
cerror = 1'b1;
end
3'b101 :
begin
ExOut = A | B;
if (ExOut[15:0] !== Out)
cerror = 1'b1;
end
3'b110 :
begin
ExOut = A ^ B;
if (ExOut[15:0] !== Out)
cerror = 1'b1;
end
3'b111 :
begin
ExOut = A & B;
if (ExOut[15:0] !== Out)
cerror = 1'b1;
end
endcase
if (cerror == 1'b1) begin
$display("ERRORCHECK :: ALU :: Inputs :: Op = %d , A = %x, B = %x, Cin = %x, invA = %x, invB = %x, sign = %x :: Outputs :: Out = %x, Ofl = %x, Z = %z :: Expected :: Out = %x, Ofl = %x, Z = %x", Op, A_pre_inv, B_pre_inv, Cin, invA, invB, sign, Out, Ofl, Z, ExOut[15:0], ExOfl, ExZ);
fail = 1;
end
end
endmodule | module alu_hier_bench; |
reg [15:0] A_pre_inv;
reg [15:0] B_pre_inv;
wire [15:0] A;
wire [15:0] B;
reg Cin;
reg [2:0] Op;
reg invA;
reg invB;
reg sign;
wire [15:0] Out;
wire Ofl;
wire Z;
reg fail;
reg cerror;
reg [31:0] ExOut;
reg ExOfl;
reg ExZ;
integer idx;
alu_hier DUT (.A(A_pre_inv), .B(B_pre_inv), .Cin(Cin), .Op(Op), .invA(invA), .invB(invB), .sign(sign), .Out(Out), .Ofl(Ofl), .Z(Z));
initial
begin
A_pre_inv = 16'b0000;
B_pre_inv = 16'b0000;
Cin = 1'b0;
Op = 3'b000;
invA = 1'b0;
invB = 1'b0;
sign = 1'b0;
fail = 0;
#5000;
if (fail)
$display("TEST FAILED");
else
$display("TEST PASSED");
$finish;
end
assign A = invA ? ~A_pre_inv : A_pre_inv;
assign B = invB ? ~B_pre_inv : B_pre_inv;
always@(posedge DUT.clk)
begin
A_pre_inv = $random;
B_pre_inv = $random;
Cin = $random;
Op = $random;
invA = $random;
invB = $random;
sign = $random;
end
always@(negedge DUT.clk)
begin
cerror = 1'b0;
ExOut = 32'h0000_0000;
ExZ = 1'b0;
ExOfl = 1'b0;
case (Op)
3'b000 :
begin
ExOut = A << B[3:0] | A >> 16-B[3:0];
if (ExOut[15:0] !== Out)
cerror = 1'b1;
end
3'b001 :
begin
ExOut = A << B[3:0];
if (ExOut[15:0] !== Out)
cerror = 1'b1;
end
3'b010 :
begin
for(idx = 31; idx > 15 ; idx = idx - 1)
ExOut[idx] = A[15];
ExOut[15:0] = A[15:0];
ExOut[15:0] = ExOut >> B[3:0];
if (ExOut[15:0] !== Out)
cerror = 1'b1;
end
3'b011 :
begin
ExOut = A >> B[3:0];
if (ExOut[15:0] !== Out)
cerror = 1'b1;
end
3'b100 :
begin
ExOut = A + B + Cin;
if (ExOut[15:0] == 16'h0000)
ExZ = 1'b1;
if (sign == 1'b1)
ExOfl = ExOut[15]^A[15]^B[15]^ExOut[16];
else
ExOfl = ExOut[16];
if ((ExOut[15:0] !== Out) || (ExZ !== Z) || (ExOfl !== Ofl))
cerror = 1'b1;
end
3'b101 :
begin
ExOut = A | B;
if (ExOut[15:0] !== Out)
cerror = 1'b1;
end
3'b110 :
begin
ExOut = A ^ B;
if (ExOut[15:0] !== Out)
cerror = 1'b1;
end
3'b111 :
begin
ExOut = A & B;
if (ExOut[15:0] !== Out)
cerror = 1'b1;
end
endcase
if (cerror == 1'b1) begin
$display("ERRORCHECK :: ALU :: Inputs :: Op = %d , A = %x, B = %x, Cin = %x, invA = %x, invB = %x, sign = %x :: Outputs :: Out = %x, Ofl = %x, Z = %z :: Expected :: Out = %x, Ofl = %x, Z = %x", Op, A_pre_inv, B_pre_inv, Cin, invA, invB, sign, Out, Ofl, Z, ExOut[15:0], ExOfl, ExZ);
fail = 1;
end
end
endmodule | 0 |
139,472 | data/full_repos/permissive/87881270/hw2/hw2_2/carry_lookahead_16bit.v | 87,881,270 | carry_lookahead_16bit.v | v | 12 | 71 | [] | [] | [] | null | line:1: before: "[" | null | 1: b"%Error: data/full_repos/permissive/87881270/hw2/hw2_2/carry_lookahead_16bit.v:6: Cannot find file containing module: 'carry_lookahead_4bit'\n carry_lookahead_4bit a1(A[3:0], B[3:0], Cin, cout[0], S[3:0]);\n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw2/hw2_2,data/full_repos/permissive/87881270/carry_lookahead_4bit\n data/full_repos/permissive/87881270/hw2/hw2_2,data/full_repos/permissive/87881270/carry_lookahead_4bit.v\n data/full_repos/permissive/87881270/hw2/hw2_2,data/full_repos/permissive/87881270/carry_lookahead_4bit.sv\n carry_lookahead_4bit\n carry_lookahead_4bit.v\n carry_lookahead_4bit.sv\n obj_dir/carry_lookahead_4bit\n obj_dir/carry_lookahead_4bit.v\n obj_dir/carry_lookahead_4bit.sv\n%Error: data/full_repos/permissive/87881270/hw2/hw2_2/carry_lookahead_16bit.v:7: Cannot find file containing module: 'carry_lookahead_4bit'\n carry_lookahead_4bit a2(A[7:4], B[7:4], cout[0], cout[1], S[7:4]);\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/87881270/hw2/hw2_2/carry_lookahead_16bit.v:8: Cannot find file containing module: 'carry_lookahead_4bit'\n carry_lookahead_4bit a3(A[11:8], B[11:8], cout[1], cout[2], S[11:8]);\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/87881270/hw2/hw2_2/carry_lookahead_16bit.v:9: Cannot find file containing module: 'carry_lookahead_4bit'\n carry_lookahead_4bit a4(A[15:12], B[15:12], cout[2], Cout, S[15:12]);\n ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 304,954 | module | module carry_lookahead_16bit(input [15:0] A,B,[0:0]Cin,
output Cout, [15:0] S);
wire cout[2:0];
carry_lookahead_4bit a1(A[3:0], B[3:0], Cin, cout[0], S[3:0]);
carry_lookahead_4bit a2(A[7:4], B[7:4], cout[0], cout[1], S[7:4]);
carry_lookahead_4bit a3(A[11:8], B[11:8], cout[1], cout[2], S[11:8]);
carry_lookahead_4bit a4(A[15:12], B[15:12], cout[2], Cout, S[15:12]);
endmodule | module carry_lookahead_16bit(input [15:0] A,B,[0:0]Cin,
output Cout, [15:0] S); |
wire cout[2:0];
carry_lookahead_4bit a1(A[3:0], B[3:0], Cin, cout[0], S[3:0]);
carry_lookahead_4bit a2(A[7:4], B[7:4], cout[0], cout[1], S[7:4]);
carry_lookahead_4bit a3(A[11:8], B[11:8], cout[1], cout[2], S[11:8]);
carry_lookahead_4bit a4(A[15:12], B[15:12], cout[2], Cout, S[15:12]);
endmodule | 0 |
139,473 | data/full_repos/permissive/87881270/hw2/hw2_2/carry_lookahead_4bit.v | 87,881,270 | carry_lookahead_4bit.v | v | 18 | 53 | [] | [] | [] | null | line:1: before: "[" | null | 1: b"%Error: data/full_repos/permissive/87881270/hw2/hw2_2/carry_lookahead_4bit.v:8: Cannot find file containing module: 'fadd1bit'\n fadd1bit a1(A[0], B[0], Cin, S[0], p[0], g[0]);\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw2/hw2_2,data/full_repos/permissive/87881270/fadd1bit\n data/full_repos/permissive/87881270/hw2/hw2_2,data/full_repos/permissive/87881270/fadd1bit.v\n data/full_repos/permissive/87881270/hw2/hw2_2,data/full_repos/permissive/87881270/fadd1bit.sv\n fadd1bit\n fadd1bit.v\n fadd1bit.sv\n obj_dir/fadd1bit\n obj_dir/fadd1bit.v\n obj_dir/fadd1bit.sv\n%Error: data/full_repos/permissive/87881270/hw2/hw2_2/carry_lookahead_4bit.v:10: Cannot find file containing module: 'fadd1bit'\n fadd1bit a2(A[1], B[1], cout1, S[1], p[1], g[1]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/87881270/hw2/hw2_2/carry_lookahead_4bit.v:12: Cannot find file containing module: 'fadd1bit'\n fadd1bit a3(A[2], B[2], cout2, S[2], p[2], g[2]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/87881270/hw2/hw2_2/carry_lookahead_4bit.v:14: Cannot find file containing module: 'fadd1bit'\n fadd1bit a4(A[3], B[3], cout3, S[3], p[3], g[3]);\n ^~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 304,955 | module | module carry_lookahead_4bit(input [3:0]A,B,[0:0]Cin,
output Cout, [3:0]S);
wire cout1,cout2,cout3;
wire p[3:0];
wire g[3:0];
fadd1bit a1(A[0], B[0], Cin, S[0], p[0], g[0]);
assign cout1 = g[0]|(Cin&p[0]);
fadd1bit a2(A[1], B[1], cout1, S[1], p[1], g[1]);
assign cout2 = g[1]|(cout1&p[1]);
fadd1bit a3(A[2], B[2], cout2, S[2], p[2], g[2]);
assign cout3 = g[2]|(cout2&p[2]);
fadd1bit a4(A[3], B[3], cout3, S[3], p[3], g[3]);
assign Cout = g[3]|(cout3&p[3]);
endmodule | module carry_lookahead_4bit(input [3:0]A,B,[0:0]Cin,
output Cout, [3:0]S); |
wire cout1,cout2,cout3;
wire p[3:0];
wire g[3:0];
fadd1bit a1(A[0], B[0], Cin, S[0], p[0], g[0]);
assign cout1 = g[0]|(Cin&p[0]);
fadd1bit a2(A[1], B[1], cout1, S[1], p[1], g[1]);
assign cout2 = g[1]|(cout1&p[1]);
fadd1bit a3(A[2], B[2], cout2, S[2], p[2], g[2]);
assign cout3 = g[2]|(cout2&p[2]);
fadd1bit a4(A[3], B[3], cout3, S[3], p[3], g[3]);
assign Cout = g[3]|(cout3&p[3]);
endmodule | 0 |
139,474 | data/full_repos/permissive/87881270/hw2/hw2_2/fadd1bit.v | 87,881,270 | fadd1bit.v | v | 20 | 37 | [] | [] | [] | [(1, 19)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/hw2/hw2_2/fadd1bit.v:12: Cannot find file containing module: 'xor2'\n xor2 c1(A, B, w1);\n ^~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw2/hw2_2,data/full_repos/permissive/87881270/xor2\n data/full_repos/permissive/87881270/hw2/hw2_2,data/full_repos/permissive/87881270/xor2.v\n data/full_repos/permissive/87881270/hw2/hw2_2,data/full_repos/permissive/87881270/xor2.sv\n xor2\n xor2.v\n xor2.sv\n obj_dir/xor2\n obj_dir/xor2.v\n obj_dir/xor2.sv\n%Error: data/full_repos/permissive/87881270/hw2/hw2_2/fadd1bit.v:13: Cannot find file containing module: 'nand2'\n nand2 c2(A, B, w2);\n ^~~~~\n%Error: data/full_repos/permissive/87881270/hw2/hw2_2/fadd1bit.v:14: Cannot find file containing module: 'nand2'\n nand2 c3(Cin, w1, w3);\n ^~~~~\n%Error: data/full_repos/permissive/87881270/hw2/hw2_2/fadd1bit.v:15: Cannot find file containing module: 'xor2'\n xor2 c5(w1, Cin, S);\n ^~~~\n%Error: Exiting due to 4 error(s)\n" | 304,957 | module | module fadd1bit (A, B, Cin, S, p,g);
input A;
input B;
input Cin;
output S;
output p;
output g;
wire w1;
wire w2;
wire w3;
xor2 c1(A, B, w1);
nand2 c2(A, B, w2);
nand2 c3(Cin, w1, w3);
xor2 c5(w1, Cin, S);
assign p = w1;
assign g = ~w2;
endmodule | module fadd1bit (A, B, Cin, S, p,g); |
input A;
input B;
input Cin;
output S;
output p;
output g;
wire w1;
wire w2;
wire w3;
xor2 c1(A, B, w1);
nand2 c2(A, B, w2);
nand2 c3(Cin, w1, w3);
xor2 c5(w1, Cin, S);
assign p = w1;
assign g = ~w2;
endmodule | 0 |
139,475 | data/full_repos/permissive/87881270/hw2/hw2_2/shifter.v | 87,881,270 | shifter.v | v | 45 | 53 | [] | [] | [] | [(1, 43)] | null | data/verilator_xmls/ef1e7a0e-eb8b-4849-994f-54f12f40fd8b.xml | null | 304,959 | module | module shifter (In, Cnt, Op, Out);
input [15:0] In;
input [3:0] Cnt;
input [1:0] Op;
output [15:0] Out;
reg [15:0]value;
always @ (*) begin
case(Op)
2'b00:begin
value =Cnt[3]?{In[7:0],In[15:8]}:In;
value =Cnt[2]?{value[11:0],value[15:12]}:value;
value =Cnt[1]?{value[13:0],value[15:14]}:value;
value =Cnt[0]?{value[14:0],value[15]}:value;
end
2'b01:begin
value =Cnt[3]?{In[7:0],8'b00000000}:In;
value =Cnt[2]?{value[11:0],4'b0000}:value;
value =Cnt[1]?{value[13:0],2'b00}:value;
value =Cnt[0]?{value[14:0],1'b0}:value;
end
2'b10:begin
value =Cnt[3]?{{8{In[15]}},In[15:8]}:In;
value =Cnt[2]?{{4{value[15]}},value[15:4]}:value;
value =Cnt[1]?{{2{value[15]}},value[15:2]}:value;
value =Cnt[0]?{{1{value[15]}},value[15:1]}:value;
end
2'b11:begin
value =Cnt[3]?{8'b00000000,In[15:8]}:In;
value =Cnt[2]?{4'b0000,value[15:4]}:value;
value =Cnt[1]?{2'b00,value[15:2]}:value;
value =Cnt[0]?{1'b0,value[15:1]}:value;
end
default: begin
value =In;
end
endcase
end
assign Out=value;
endmodule | module shifter (In, Cnt, Op, Out); |
input [15:0] In;
input [3:0] Cnt;
input [1:0] Op;
output [15:0] Out;
reg [15:0]value;
always @ (*) begin
case(Op)
2'b00:begin
value =Cnt[3]?{In[7:0],In[15:8]}:In;
value =Cnt[2]?{value[11:0],value[15:12]}:value;
value =Cnt[1]?{value[13:0],value[15:14]}:value;
value =Cnt[0]?{value[14:0],value[15]}:value;
end
2'b01:begin
value =Cnt[3]?{In[7:0],8'b00000000}:In;
value =Cnt[2]?{value[11:0],4'b0000}:value;
value =Cnt[1]?{value[13:0],2'b00}:value;
value =Cnt[0]?{value[14:0],1'b0}:value;
end
2'b10:begin
value =Cnt[3]?{{8{In[15]}},In[15:8]}:In;
value =Cnt[2]?{{4{value[15]}},value[15:4]}:value;
value =Cnt[1]?{{2{value[15]}},value[15:2]}:value;
value =Cnt[0]?{{1{value[15]}},value[15:1]}:value;
end
2'b11:begin
value =Cnt[3]?{8'b00000000,In[15:8]}:In;
value =Cnt[2]?{4'b0000,value[15:4]}:value;
value =Cnt[1]?{2'b00,value[15:2]}:value;
value =Cnt[0]?{1'b0,value[15:1]}:value;
end
default: begin
value =In;
end
endcase
end
assign Out=value;
endmodule | 0 |
139,476 | data/full_repos/permissive/87881270/hw2 q1doubt/bit16_2to1mux.v | 87,881,270 | bit16_2to1mux.v | v | 22 | 44 | [] | [] | [] | null | line:1: before: "[" | null | 1: b'%Error: Cannot find file containing module: q1doubt,data/full_repos/permissive/87881270\n ... Looked in:\n data/full_repos/permissive/87881270/hw2/q1doubt,data/full_repos/permissive/87881270\n data/full_repos/permissive/87881270/hw2/q1doubt,data/full_repos/permissive/87881270.v\n data/full_repos/permissive/87881270/hw2/q1doubt,data/full_repos/permissive/87881270.sv\n q1doubt,data/full_repos/permissive/87881270\n q1doubt,data/full_repos/permissive/87881270.v\n q1doubt,data/full_repos/permissive/87881270.sv\n obj_dir/q1doubt,data/full_repos/permissive/87881270\n obj_dir/q1doubt,data/full_repos/permissive/87881270.v\n obj_dir/q1doubt,data/full_repos/permissive/87881270.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/87881270/hw2\n%Error: Cannot find file containing module: q1doubt/bit16_2to1mux.v\n%Error: Exiting due to 3 error(s)\n' | 304,961 | module | module bit16_2to1mux (input S,[15:0]A,B,
output [15:0]Out);
bit1in2to1mux a1(A[0],B[0],S, Out[0]);
bit1in2to1mux a2(A[1],B[1],S, Out[1]);
bit1in2to1mux a3(A[2],B[2],S, Out[2]);
bit1in2to1mux a4(A[3],B[3],S, Out[3]);
bit1in2to1mux a5(A[4],B[4],S, Out[4]);
bit1in2to1mux a6(A[5],B[5],S, Out[5]);
bit1in2to1mux a7(A[6],B[6],S, Out[6]);
bit1in2to1mux a8(A[7],B[7],S, Out[7]);
bit1in2to1mux a9(A[8],B[8],S, Out[8]);
bit1in2to1mux a10(A[9],B[9],S, Out[9]);
bit1in2to1mux a11(A[10],B[10],S, Out[10]);
bit1in2to1mux a12(A[11],B[11],S, Out[11]);
bit1in2to1mux a13(A[12],B[12],S, Out[12]);
bit1in2to1mux a14(A[13],B[13],S, Out[13]);
bit1in2to1mux a15(A[14],B[14],S, Out[14]);
bit1in2to1mux a16(A[15],B[15],S, Out[15]);
endmodule | module bit16_2to1mux (input S,[15:0]A,B,
output [15:0]Out); |
bit1in2to1mux a1(A[0],B[0],S, Out[0]);
bit1in2to1mux a2(A[1],B[1],S, Out[1]);
bit1in2to1mux a3(A[2],B[2],S, Out[2]);
bit1in2to1mux a4(A[3],B[3],S, Out[3]);
bit1in2to1mux a5(A[4],B[4],S, Out[4]);
bit1in2to1mux a6(A[5],B[5],S, Out[5]);
bit1in2to1mux a7(A[6],B[6],S, Out[6]);
bit1in2to1mux a8(A[7],B[7],S, Out[7]);
bit1in2to1mux a9(A[8],B[8],S, Out[8]);
bit1in2to1mux a10(A[9],B[9],S, Out[9]);
bit1in2to1mux a11(A[10],B[10],S, Out[10]);
bit1in2to1mux a12(A[11],B[11],S, Out[11]);
bit1in2to1mux a13(A[12],B[12],S, Out[12]);
bit1in2to1mux a14(A[13],B[13],S, Out[13]);
bit1in2to1mux a15(A[14],B[14],S, Out[14]);
bit1in2to1mux a16(A[15],B[15],S, Out[15]);
endmodule | 0 |
139,477 | data/full_repos/permissive/87881270/hw2 q1doubt/rotate_left.v | 87,881,270 | rotate_left.v | v | 12 | 48 | [] | [] | [] | null | line:1: before: "[" | null | 1: b'%Error: Cannot find file containing module: q1doubt,data/full_repos/permissive/87881270\n ... Looked in:\n data/full_repos/permissive/87881270/hw2/q1doubt,data/full_repos/permissive/87881270\n data/full_repos/permissive/87881270/hw2/q1doubt,data/full_repos/permissive/87881270.v\n data/full_repos/permissive/87881270/hw2/q1doubt,data/full_repos/permissive/87881270.sv\n q1doubt,data/full_repos/permissive/87881270\n q1doubt,data/full_repos/permissive/87881270.v\n q1doubt,data/full_repos/permissive/87881270.sv\n obj_dir/q1doubt,data/full_repos/permissive/87881270\n obj_dir/q1doubt,data/full_repos/permissive/87881270.v\n obj_dir/q1doubt,data/full_repos/permissive/87881270.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/87881270/hw2\n%Error: Cannot find file containing module: q1doubt/rotate_left.v\n%Error: Exiting due to 3 error(s)\n' | 304,965 | module | module rotate_left(input [3:0]S,[15:0]A,B,
output [15:0]Out);
bit16_2to1mux a1(S[3],A,{A[7:0],A[15:8]},A);
bit16_2to1mux a2(S[2],A,{A[11:0],A[15:12]},A);
bit16_2to1mux a3(S[1],A,{A[13:0],A[15:14]},A);
bit16_2to1mux a4(S[0],A,{A[14:0],A[15]},A);
endmodule | module rotate_left(input [3:0]S,[15:0]A,B,
output [15:0]Out); |
bit16_2to1mux a1(S[3],A,{A[7:0],A[15:8]},A);
bit16_2to1mux a2(S[2],A,{A[11:0],A[15:12]},A);
bit16_2to1mux a3(S[1],A,{A[13:0],A[15:14]},A);
bit16_2to1mux a4(S[0],A,{A[14:0],A[15]},A);
endmodule | 0 |
139,478 | data/full_repos/permissive/87881270/hw2 q1doubt/shift_right_arithmetic.v | 87,881,270 | shift_right_arithmetic.v | v | 10 | 54 | [] | [] | [] | null | line:1: before: "[" | null | 1: b'%Error: Cannot find file containing module: q1doubt,data/full_repos/permissive/87881270\n ... Looked in:\n data/full_repos/permissive/87881270/hw2/q1doubt,data/full_repos/permissive/87881270\n data/full_repos/permissive/87881270/hw2/q1doubt,data/full_repos/permissive/87881270.v\n data/full_repos/permissive/87881270/hw2/q1doubt,data/full_repos/permissive/87881270.sv\n q1doubt,data/full_repos/permissive/87881270\n q1doubt,data/full_repos/permissive/87881270.v\n q1doubt,data/full_repos/permissive/87881270.sv\n obj_dir/q1doubt,data/full_repos/permissive/87881270\n obj_dir/q1doubt,data/full_repos/permissive/87881270.v\n obj_dir/q1doubt,data/full_repos/permissive/87881270.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/87881270/hw2\n%Error: Cannot find file containing module: q1doubt/shift_right_arithmetic.v\n%Error: Exiting due to 3 error(s)\n' | 304,968 | module | module shift_right_arithmetic(input [3:0]S,[15:0]A,B,
output [15:0]Out);
bit16_2to1mux a1(S[3],A,{{8{A[15]}},A[15:8]},A);
bit16_2to1mux a2(S[2],A,{{4{A[15]}},A[15:4]},A);
bit16_2to1mux a3(S[1],A,{{2{A[15]}},A[15:2]},A);
bit16_2to1mux a4(S[0],A,{{1{A[15]}},A[15:1]},A);
endmodule | module shift_right_arithmetic(input [3:0]S,[15:0]A,B,
output [15:0]Out); |
bit16_2to1mux a1(S[3],A,{{8{A[15]}},A[15:8]},A);
bit16_2to1mux a2(S[2],A,{{4{A[15]}},A[15:4]},A);
bit16_2to1mux a3(S[1],A,{{2{A[15]}},A[15:2]},A);
bit16_2to1mux a4(S[0],A,{{1{A[15]}},A[15:1]},A);
endmodule | 0 |
139,479 | data/full_repos/permissive/87881270/hw2 q1doubt/shift_right_logical.v | 87,881,270 | shift_right_logical.v | v | 10 | 51 | [] | [] | [] | null | line:1: before: "[" | null | 1: b'%Error: Cannot find file containing module: q1doubt,data/full_repos/permissive/87881270\n ... Looked in:\n data/full_repos/permissive/87881270/hw2/q1doubt,data/full_repos/permissive/87881270\n data/full_repos/permissive/87881270/hw2/q1doubt,data/full_repos/permissive/87881270.v\n data/full_repos/permissive/87881270/hw2/q1doubt,data/full_repos/permissive/87881270.sv\n q1doubt,data/full_repos/permissive/87881270\n q1doubt,data/full_repos/permissive/87881270.v\n q1doubt,data/full_repos/permissive/87881270.sv\n obj_dir/q1doubt,data/full_repos/permissive/87881270\n obj_dir/q1doubt,data/full_repos/permissive/87881270.v\n obj_dir/q1doubt,data/full_repos/permissive/87881270.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/87881270/hw2\n%Error: Cannot find file containing module: q1doubt/shift_right_logical.v\n%Error: Exiting due to 3 error(s)\n' | 304,969 | module | module shift_right_logical(input [3:0]S,[15:0]A,B,
output [15:0]Out);
bit16_2to1mux a1(S[3],A,{8'b00000000,A[15:8]},A);
bit16_2to1mux a2(S[2],A,{4'b0000,A[15:4]},A);
bit16_2to1mux a3(S[1],A,{2'b00,A[15:2]},A);
bit16_2to1mux a4(S[0],A,{1'b0,A[15:1]},A);
endmodule | module shift_right_logical(input [3:0]S,[15:0]A,B,
output [15:0]Out); |
bit16_2to1mux a1(S[3],A,{8'b00000000,A[15:8]},A);
bit16_2to1mux a2(S[2],A,{4'b0000,A[15:4]},A);
bit16_2to1mux a3(S[1],A,{2'b00,A[15:2]},A);
bit16_2to1mux a4(S[0],A,{1'b0,A[15:1]},A);
endmodule | 0 |
139,480 | data/full_repos/permissive/87881270/hw3/hw3_1/reg16bit.v | 87,881,270 | reg16bit.v | v | 15 | 50 | [] | [] | [] | null | line:1: before: "[" | null | 1: b"%Error: data/full_repos/permissive/87881270/hw3/hw3_1/reg16bit.v:6: Cannot find file containing module: 'dff'\n dff outp[15:0] (\n ^~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw3/hw3_1,data/full_repos/permissive/87881270/dff\n data/full_repos/permissive/87881270/hw3/hw3_1,data/full_repos/permissive/87881270/dff.v\n data/full_repos/permissive/87881270/hw3/hw3_1,data/full_repos/permissive/87881270/dff.sv\n dff\n dff.v\n dff.sv\n obj_dir/dff\n obj_dir/dff.v\n obj_dir/dff.sv\n%Error: Exiting due to 1 error(s)\n" | 304,972 | module | module reg16bit( input clk, reset,[15:0]in,
output [15:0]out);
wire [15:0]w1;
dff outp[15:0] (
.q (w1),
.d (in),
.clk (clk),
.rst (reset));
assign out = w1;
endmodule | module reg16bit( input clk, reset,[15:0]in,
output [15:0]out); |
wire [15:0]w1;
dff outp[15:0] (
.q (w1),
.d (in),
.clk (clk),
.rst (reset));
assign out = w1;
endmodule | 0 |
139,481 | data/full_repos/permissive/87881270/hw3/hw3_1/rf.v | 87,881,270 | rf.v | v | 186 | 77 | [] | [] | [] | [(4, 184)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/hw3/hw3_1/rf.v:29: Cannot find file containing module: 'reg16bit'\n reg16bit reg1 (\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw3/hw3_1,data/full_repos/permissive/87881270/reg16bit\n data/full_repos/permissive/87881270/hw3/hw3_1,data/full_repos/permissive/87881270/reg16bit.v\n data/full_repos/permissive/87881270/hw3/hw3_1,data/full_repos/permissive/87881270/reg16bit.sv\n reg16bit\n reg16bit.v\n reg16bit.sv\n obj_dir/reg16bit\n obj_dir/reg16bit.v\n obj_dir/reg16bit.sv\n%Error: data/full_repos/permissive/87881270/hw3/hw3_1/rf.v:36: Cannot find file containing module: 'reg16bit'\n reg16bit reg2 (\n ^~~~~~~~\n%Error: data/full_repos/permissive/87881270/hw3/hw3_1/rf.v:43: Cannot find file containing module: 'reg16bit'\n reg16bit reg3 (\n ^~~~~~~~\n%Error: data/full_repos/permissive/87881270/hw3/hw3_1/rf.v:50: Cannot find file containing module: 'reg16bit'\n reg16bit reg4 (\n ^~~~~~~~\n%Error: data/full_repos/permissive/87881270/hw3/hw3_1/rf.v:57: Cannot find file containing module: 'reg16bit'\n reg16bit reg5 (\n ^~~~~~~~\n%Error: data/full_repos/permissive/87881270/hw3/hw3_1/rf.v:64: Cannot find file containing module: 'reg16bit'\n reg16bit reg6 (\n ^~~~~~~~\n%Error: data/full_repos/permissive/87881270/hw3/hw3_1/rf.v:71: Cannot find file containing module: 'reg16bit'\n reg16bit reg7 (\n ^~~~~~~~\n%Error: data/full_repos/permissive/87881270/hw3/hw3_1/rf.v:78: Cannot find file containing module: 'reg16bit'\n reg16bit reg8 (\n ^~~~~~~~\n%Error: Exiting due to 8 error(s)\n" | 304,973 | module | module rf (
read1data, read2data, err,
clk, rst, read1regsel, read2regsel, writeregsel, writedata, write
);
input clk, rst;
input [2:0] read1regsel;
input [2:0] read2regsel;
input [2:0] writeregsel;
input [15:0] writedata;
input write;
output [15:0] read1data;
output [15:0] read2data;
output err;
reg [15:0]writein0,writein1,read1,writein2,read2,
writein3,writein4,
writein5,writein6,
writein7;
wire[15:0] readout0,readout1,
readout2,readout3,
readout4,readout5,
readout6,readout7;
reg16bit reg1 (
.out (readout0),
.in (writein0),
.clk (clk),
.reset (rst));
reg16bit reg2 (
.out (readoutt),
.in (writein1),
.clk (clk),
.reset (rst));
reg16bit reg3 (
.out (readout2),
.in (writein2),
.clk (clk),
.reset (rst));
reg16bit reg4 (
.out (readout3),
.in (writein3),
.clk (clk),
.reset (rst));
reg16bit reg5 (
.out (readout4),
.in (writein4),
.clk (clk),
.reset (rst));
reg16bit reg6 (
.out (readout5),
.in (writein5),
.clk (clk),
.reset (rst));
reg16bit reg7 (
.out (readout6),
.in (writein6),
.clk (clk),
.reset (rst));
reg16bit reg8 (
.out (readout7),
.in (writein7),
.clk (clk),
.reset (rst));
always@(*)
begin
case (writeregsel)
3'b000:begin
writein0=write?writedata:readout0;
end
3'b001:begin
writein1=write?writedata:readout1;
end
3'b010:begin
writein2=write?writedata:readout2;
end
3'b011:begin
writein3=write?writedata:readout3;
end
3'b100:begin
writein4=write?writedata:readout4;
end
3'b101:begin
writein5=write?writedata:readout5;
end
3'b110:begin
writein6=write?writedata:readout6;
end
3'b111:begin
writein7=write?writedata:readout7;
end
default:
$display("error");
endcase
end
always@(*)
begin
case (read1regsel)
3'b000:begin
read1=readout0;
end
3'b001:begin
read1=readout1;
end
3'b010:begin
read1=readout2;
end
3'b011:begin
read1=readout3;
end
3'b100:begin
read1=readout4;
end
3'b101:begin
read1=readout5;
end
3'b110:begin
read1=readout6;
end
3'b111:begin
read1=readout7;
end
default:
$display("error");
endcase
case (read2regsel)
3'b000:begin
read2=readout0;
end
3'b001:begin
read2=readout1;
end
3'b010:begin
read2=readout2;
end
3'b011:begin
read2=readout3;
end
3'b100:begin
read2=readout4;
end
3'b101:begin
read2=readout5;
end
3'b110:begin
read2=readout6;
end
3'b111:begin
read2=readout7;
end
default:
$display("error");
endcase
end
assign read2data = read2;
assign read1data = read1;
endmodule | module rf (
read1data, read2data, err,
clk, rst, read1regsel, read2regsel, writeregsel, writedata, write
); |
input clk, rst;
input [2:0] read1regsel;
input [2:0] read2regsel;
input [2:0] writeregsel;
input [15:0] writedata;
input write;
output [15:0] read1data;
output [15:0] read2data;
output err;
reg [15:0]writein0,writein1,read1,writein2,read2,
writein3,writein4,
writein5,writein6,
writein7;
wire[15:0] readout0,readout1,
readout2,readout3,
readout4,readout5,
readout6,readout7;
reg16bit reg1 (
.out (readout0),
.in (writein0),
.clk (clk),
.reset (rst));
reg16bit reg2 (
.out (readoutt),
.in (writein1),
.clk (clk),
.reset (rst));
reg16bit reg3 (
.out (readout2),
.in (writein2),
.clk (clk),
.reset (rst));
reg16bit reg4 (
.out (readout3),
.in (writein3),
.clk (clk),
.reset (rst));
reg16bit reg5 (
.out (readout4),
.in (writein4),
.clk (clk),
.reset (rst));
reg16bit reg6 (
.out (readout5),
.in (writein5),
.clk (clk),
.reset (rst));
reg16bit reg7 (
.out (readout6),
.in (writein6),
.clk (clk),
.reset (rst));
reg16bit reg8 (
.out (readout7),
.in (writein7),
.clk (clk),
.reset (rst));
always@(*)
begin
case (writeregsel)
3'b000:begin
writein0=write?writedata:readout0;
end
3'b001:begin
writein1=write?writedata:readout1;
end
3'b010:begin
writein2=write?writedata:readout2;
end
3'b011:begin
writein3=write?writedata:readout3;
end
3'b100:begin
writein4=write?writedata:readout4;
end
3'b101:begin
writein5=write?writedata:readout5;
end
3'b110:begin
writein6=write?writedata:readout6;
end
3'b111:begin
writein7=write?writedata:readout7;
end
default:
$display("error");
endcase
end
always@(*)
begin
case (read1regsel)
3'b000:begin
read1=readout0;
end
3'b001:begin
read1=readout1;
end
3'b010:begin
read1=readout2;
end
3'b011:begin
read1=readout3;
end
3'b100:begin
read1=readout4;
end
3'b101:begin
read1=readout5;
end
3'b110:begin
read1=readout6;
end
3'b111:begin
read1=readout7;
end
default:
$display("error");
endcase
case (read2regsel)
3'b000:begin
read2=readout0;
end
3'b001:begin
read2=readout1;
end
3'b010:begin
read2=readout2;
end
3'b011:begin
read2=readout3;
end
3'b100:begin
read2=readout4;
end
3'b101:begin
read2=readout5;
end
3'b110:begin
read2=readout6;
end
3'b111:begin
read2=readout7;
end
default:
$display("error");
endcase
end
assign read2data = read2;
assign read1data = read1;
endmodule | 0 |
139,482 | data/full_repos/permissive/87881270/hw3/hw3_1/rf1.v | 87,881,270 | rf1.v | v | 117 | 94 | [] | [] | [] | [(4, 115)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/hw3/hw3_1/rf1.v:27: Cannot find file containing module: 'reg16bit'\n reg16bit reg0 (.out(readout0), .in(in0), .clk(clk), .reset(rst));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw3/hw3_1,data/full_repos/permissive/87881270/reg16bit\n data/full_repos/permissive/87881270/hw3/hw3_1,data/full_repos/permissive/87881270/reg16bit.v\n data/full_repos/permissive/87881270/hw3/hw3_1,data/full_repos/permissive/87881270/reg16bit.sv\n reg16bit\n reg16bit.v\n reg16bit.sv\n obj_dir/reg16bit\n obj_dir/reg16bit.v\n obj_dir/reg16bit.sv\n%Error: data/full_repos/permissive/87881270/hw3/hw3_1/rf1.v:28: Cannot find file containing module: 'reg16bit'\n reg16bit reg1 (.out(readout1), .in(in1), .clk(clk), .reset(rst));\n ^~~~~~~~\n%Error: data/full_repos/permissive/87881270/hw3/hw3_1/rf1.v:29: Cannot find file containing module: 'reg16bit'\n reg16bit reg2 (.out(readout2), .in(in2), .clk(clk), .reset(rst));\n ^~~~~~~~\n%Error: data/full_repos/permissive/87881270/hw3/hw3_1/rf1.v:30: Cannot find file containing module: 'reg16bit'\n reg16bit reg3 (.out(readout3), .in(in3), .clk(clk), .reset(rst));\n ^~~~~~~~\n%Error: data/full_repos/permissive/87881270/hw3/hw3_1/rf1.v:31: Cannot find file containing module: 'reg16bit'\n reg16bit reg4 (.out(readout4), .in(in4), .clk(clk), .reset(rst));\n ^~~~~~~~\n%Error: data/full_repos/permissive/87881270/hw3/hw3_1/rf1.v:32: Cannot find file containing module: 'reg16bit'\n reg16bit reg5 (.out(readout5), .in(in5), .clk(clk), .reset(rst));\n ^~~~~~~~\n%Error: data/full_repos/permissive/87881270/hw3/hw3_1/rf1.v:33: Cannot find file containing module: 'reg16bit'\n reg16bit reg6 (.out(readout6), .in(in6), .clk(clk), .reset(rst));\n ^~~~~~~~\n%Error: data/full_repos/permissive/87881270/hw3/hw3_1/rf1.v:34: Cannot find file containing module: 'reg16bit'\n reg16bit reg7 (.out(readout7), .in(in7), .clk(clk), .reset(rst));\n ^~~~~~~~\n%Error: Exiting due to 8 error(s)\n" | 304,974 | module | module rf (
read1data, read2data, err,
clk, rst, read1regsel, read2regsel, writeregsel, writedata, write
);
input clk, rst;
input [2:0] read1regsel;
input [2:0] read2regsel;
input [2:0] writeregsel;
input [15:0] writedata;
input write;
output [15:0] read1data;
output [15:0] read2data;
output err;
wire [15:0] in0, in1, in2, in3, in4, in5, in6, in7;
wire[15:0] readout0, readout1, readout2, readout3, readout4, readout5, readout6, readout7;
reg[15:0] read1, read2;
reg[15:0] temp;
reg16bit reg0 (.out(readout0), .in(in0), .clk(clk), .reset(rst));
reg16bit reg1 (.out(readout1), .in(in1), .clk(clk), .reset(rst));
reg16bit reg2 (.out(readout2), .in(in2), .clk(clk), .reset(rst));
reg16bit reg3 (.out(readout3), .in(in3), .clk(clk), .reset(rst));
reg16bit reg4 (.out(readout4), .in(in4), .clk(clk), .reset(rst));
reg16bit reg5 (.out(readout5), .in(in5), .clk(clk), .reset(rst));
reg16bit reg6 (.out(readout6), .in(in6), .clk(clk), .reset(rst));
reg16bit reg7 (.out(readout7), .in(in7), .clk(clk), .reset(rst));
assign in0 = ((writeregsel == 3'b000) & write) ? writedata : readout0;
assign in1 = ((writeregsel == 3'b001) & write) ? writedata : readout1;
assign in2 = ((writeregsel == 3'b010) & write) ? writedata : readout2;
assign in3 = ((writeregsel == 3'b011) & write) ? writedata : readout3;
assign in4 = ((writeregsel == 3'b100) & write) ? writedata : readout4;
assign in5 = ((writeregsel == 3'b101) & write) ? writedata : readout5;
assign in6 = ((writeregsel == 3'b110) & write) ? writedata : readout6;
assign in7 = ((writeregsel == 3'b111) & write) ? writedata : readout7;
always@(*)
begin
case (read1regsel)
3'b000:begin
read1 = readout0;
end
3'b001:begin
read1 = readout1;
end
3'b010:begin
read1 = readout2;
end
3'b011:begin
read1 = readout3;
end
3'b100:begin
read1 = readout4;
end
3'b101:begin
read1 = readout5;
end
3'b110:begin
read1 = readout6;
end
3'b111:begin
read1 = readout7;
end
default:
$display("error");
endcase
end
always@(*)
begin
case (read2regsel)
3'b000:begin
read2 = readout0;
end
3'b001:begin
read2 = readout1;
end
3'b010:begin
read2 = readout2;
end
3'b011:begin
read2 = readout3;
end
3'b100:begin
read2 = readout4;
end
3'b101:begin
read2 = readout5;
end
3'b110:begin
read2 = readout6;
end
3'b111:begin
read2 = readout7;
end
default:
$display("error");
endcase
end
assign read2data = read2;
assign read1data = read1;
endmodule | module rf (
read1data, read2data, err,
clk, rst, read1regsel, read2regsel, writeregsel, writedata, write
); |
input clk, rst;
input [2:0] read1regsel;
input [2:0] read2regsel;
input [2:0] writeregsel;
input [15:0] writedata;
input write;
output [15:0] read1data;
output [15:0] read2data;
output err;
wire [15:0] in0, in1, in2, in3, in4, in5, in6, in7;
wire[15:0] readout0, readout1, readout2, readout3, readout4, readout5, readout6, readout7;
reg[15:0] read1, read2;
reg[15:0] temp;
reg16bit reg0 (.out(readout0), .in(in0), .clk(clk), .reset(rst));
reg16bit reg1 (.out(readout1), .in(in1), .clk(clk), .reset(rst));
reg16bit reg2 (.out(readout2), .in(in2), .clk(clk), .reset(rst));
reg16bit reg3 (.out(readout3), .in(in3), .clk(clk), .reset(rst));
reg16bit reg4 (.out(readout4), .in(in4), .clk(clk), .reset(rst));
reg16bit reg5 (.out(readout5), .in(in5), .clk(clk), .reset(rst));
reg16bit reg6 (.out(readout6), .in(in6), .clk(clk), .reset(rst));
reg16bit reg7 (.out(readout7), .in(in7), .clk(clk), .reset(rst));
assign in0 = ((writeregsel == 3'b000) & write) ? writedata : readout0;
assign in1 = ((writeregsel == 3'b001) & write) ? writedata : readout1;
assign in2 = ((writeregsel == 3'b010) & write) ? writedata : readout2;
assign in3 = ((writeregsel == 3'b011) & write) ? writedata : readout3;
assign in4 = ((writeregsel == 3'b100) & write) ? writedata : readout4;
assign in5 = ((writeregsel == 3'b101) & write) ? writedata : readout5;
assign in6 = ((writeregsel == 3'b110) & write) ? writedata : readout6;
assign in7 = ((writeregsel == 3'b111) & write) ? writedata : readout7;
always@(*)
begin
case (read1regsel)
3'b000:begin
read1 = readout0;
end
3'b001:begin
read1 = readout1;
end
3'b010:begin
read1 = readout2;
end
3'b011:begin
read1 = readout3;
end
3'b100:begin
read1 = readout4;
end
3'b101:begin
read1 = readout5;
end
3'b110:begin
read1 = readout6;
end
3'b111:begin
read1 = readout7;
end
default:
$display("error");
endcase
end
always@(*)
begin
case (read2regsel)
3'b000:begin
read2 = readout0;
end
3'b001:begin
read2 = readout1;
end
3'b010:begin
read2 = readout2;
end
3'b011:begin
read2 = readout3;
end
3'b100:begin
read2 = readout4;
end
3'b101:begin
read2 = readout5;
end
3'b110:begin
read2 = readout6;
end
3'b111:begin
read2 = readout7;
end
default:
$display("error");
endcase
end
assign read2data = read2;
assign read1data = read1;
endmodule | 0 |
139,483 | data/full_repos/permissive/87881270/hw3/hw3_1/rf_bench.v | 87,881,270 | rf_bench.v | v | 120 | 100 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/87881270/hw3/hw3_1/rf_bench.v:63: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87881270/hw3/hw3_1/rf_bench.v:93: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,975 | module | module rf_bench();
wire [15:0] read1data;
wire [15:0] read2data;
reg [2:0] read1regsel;
reg [2:0] read2regsel;
reg write;
reg [15:0] writedata;
reg [2:0] writeregsel;
integer cycle_count;
wire clk;
wire rst;
reg fail;
rf_hier DUT(
.read1data (read1data[15:0]),
.read2data (read2data[15:0]),
.read1regsel (read1regsel[2:0]),
.read2regsel (read2regsel[2:0]),
.writeregsel (writeregsel[2:0]),
.writedata (writedata[15:0]),
.write (write));
assign clk = DUT.clk_generator.clk;
assign rst = DUT.clk_generator.rst;
reg [15:0] ref_rf[7:0];
reg [15:0] ref_r1data;
reg [15:0] ref_r2data;
initial begin
cycle_count = 0;
ref_rf[0] = 0;
ref_rf[1] = 0;
ref_rf[2] = 0;
ref_rf[3] = 0;
ref_rf[4] = 0;
ref_rf[5] = 0;
ref_rf[6] = 0;
ref_rf[7] = 0;
ref_r1data = 0;
ref_r2data = 0;
write = 0;
fail = 0;
$dumpvars;
end
always @ (posedge clk)begin
read1regsel = $random % 8;
read2regsel = $random % 8;
writedata = $random % 65536;
writeregsel = $random % 8;
write = $random % 2;
ref_r1data = ref_rf[ read1regsel ];
ref_r2data = ref_rf[ read2regsel ];
if ((cycle_count >= 2) && write) begin
ref_rf[ writeregsel ] = writedata;
end
#10
$display("Cycle: %d R1: %d Sim: %d Exp: %d R2: %d Sim: %d Exp: %d W: %d data: %d enable: %d",
cycle_count,
read1regsel, read1data, ref_r1data,
read2regsel, read2data, ref_r2data,
writeregsel, writedata, write );
if ( !rst && ( (ref_r1data !== read1data)
|| (ref_r2data !== read2data) ) ) begin
$display("ERRORCHECK: Incorrect read data");
fail = 1;
end
cycle_count = cycle_count + 1;
if (cycle_count > 50) begin
if (fail)
$display("TEST FAILED");
else
$display("TEST PASSED");
$finish;
end
end
endmodule | module rf_bench(); |
wire [15:0] read1data;
wire [15:0] read2data;
reg [2:0] read1regsel;
reg [2:0] read2regsel;
reg write;
reg [15:0] writedata;
reg [2:0] writeregsel;
integer cycle_count;
wire clk;
wire rst;
reg fail;
rf_hier DUT(
.read1data (read1data[15:0]),
.read2data (read2data[15:0]),
.read1regsel (read1regsel[2:0]),
.read2regsel (read2regsel[2:0]),
.writeregsel (writeregsel[2:0]),
.writedata (writedata[15:0]),
.write (write));
assign clk = DUT.clk_generator.clk;
assign rst = DUT.clk_generator.rst;
reg [15:0] ref_rf[7:0];
reg [15:0] ref_r1data;
reg [15:0] ref_r2data;
initial begin
cycle_count = 0;
ref_rf[0] = 0;
ref_rf[1] = 0;
ref_rf[2] = 0;
ref_rf[3] = 0;
ref_rf[4] = 0;
ref_rf[5] = 0;
ref_rf[6] = 0;
ref_rf[7] = 0;
ref_r1data = 0;
ref_r2data = 0;
write = 0;
fail = 0;
$dumpvars;
end
always @ (posedge clk)begin
read1regsel = $random % 8;
read2regsel = $random % 8;
writedata = $random % 65536;
writeregsel = $random % 8;
write = $random % 2;
ref_r1data = ref_rf[ read1regsel ];
ref_r2data = ref_rf[ read2regsel ];
if ((cycle_count >= 2) && write) begin
ref_rf[ writeregsel ] = writedata;
end
#10
$display("Cycle: %d R1: %d Sim: %d Exp: %d R2: %d Sim: %d Exp: %d W: %d data: %d enable: %d",
cycle_count,
read1regsel, read1data, ref_r1data,
read2regsel, read2data, ref_r2data,
writeregsel, writedata, write );
if ( !rst && ( (ref_r1data !== read1data)
|| (ref_r2data !== read2data) ) ) begin
$display("ERRORCHECK: Incorrect read data");
fail = 1;
end
cycle_count = cycle_count + 1;
if (cycle_count > 50) begin
if (fail)
$display("TEST FAILED");
else
$display("TEST PASSED");
$finish;
end
end
endmodule | 0 |
139,484 | data/full_repos/permissive/87881270/hw3/hw3_1/rf_hier.v | 87,881,270 | rf_hier.v | v | 44 | 72 | [] | [] | [] | [(7, 42)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/hw3/hw3_1/rf_hier.v:27: Cannot find file containing module: 'clkrst'\n clkrst clk_generator(.clk(clk), .rst(rst), .err(err) );\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw3/hw3_1,data/full_repos/permissive/87881270/clkrst\n data/full_repos/permissive/87881270/hw3/hw3_1,data/full_repos/permissive/87881270/clkrst.v\n data/full_repos/permissive/87881270/hw3/hw3_1,data/full_repos/permissive/87881270/clkrst.sv\n clkrst\n clkrst.v\n clkrst.sv\n obj_dir/clkrst\n obj_dir/clkrst.v\n obj_dir/clkrst.sv\n%Error: data/full_repos/permissive/87881270/hw3/hw3_1/rf_hier.v:28: Cannot find file containing module: 'rf'\n rf rf0(\n ^~\n%Error: Exiting due to 2 error(s)\n" | 304,976 | module | module rf_hier (
read1data, read2data,
read1regsel, read2regsel, writeregsel, writedata, write
);
input [2:0] read1regsel;
input [2:0] read2regsel;
input [2:0] writeregsel;
input [15:0] writedata;
input write;
output [15:0] read1data;
output [15:0] read2data;
wire clk, rst;
wire err;
clkrst clk_generator(.clk(clk), .rst(rst), .err(err) );
rf rf0(
.read1data (read1data[15:0]),
.read2data (read2data[15:0]),
.err (err),
.clk (clk),
.rst (rst),
.read1regsel (read1regsel[2:0]),
.read2regsel (read2regsel[2:0]),
.writeregsel (writeregsel[2:0]),
.writedata (writedata[15:0]),
.write (write));
endmodule | module rf_hier (
read1data, read2data,
read1regsel, read2regsel, writeregsel, writedata, write
); |
input [2:0] read1regsel;
input [2:0] read2regsel;
input [2:0] writeregsel;
input [15:0] writedata;
input write;
output [15:0] read1data;
output [15:0] read2data;
wire clk, rst;
wire err;
clkrst clk_generator(.clk(clk), .rst(rst), .err(err) );
rf rf0(
.read1data (read1data[15:0]),
.read2data (read2data[15:0]),
.err (err),
.clk (clk),
.rst (rst),
.read1regsel (read1regsel[2:0]),
.read2regsel (read2regsel[2:0]),
.writeregsel (writeregsel[2:0]),
.writedata (writedata[15:0]),
.write (write));
endmodule | 0 |
139,485 | data/full_repos/permissive/87881270/hw3/hw3_2/sc.v | 87,881,270 | sc.v | v | 51 | 71 | [] | [] | [] | [(5, 48)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/hw3/hw3_2/sc.v:15: Cannot find file containing module: 'dff'\ndff curr_state[2:0] (\n^~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw3/hw3_2,data/full_repos/permissive/87881270/dff\n data/full_repos/permissive/87881270/hw3/hw3_2,data/full_repos/permissive/87881270/dff.v\n data/full_repos/permissive/87881270/hw3/hw3_2,data/full_repos/permissive/87881270/dff.sv\n dff\n dff.v\n dff.sv\n obj_dir/dff\n obj_dir/dff.v\n obj_dir/dff.sv\n%Error: Exiting due to 1 error(s)\n" | 304,979 | module | module sc( clk, rst, ctr_rst, out, err);
input clk;
input rst;
input ctr_rst;
output [2:0] out;
output err;
wire [2:0] state;
reg [2:0] next_state;
dff curr_state[2:0] (
.q (state),
.d (next_state),
.clk (clk),
.rst (rst));
always@(*)begin
casex(state)
3'b000:begin
next_state = rst?3'b000:(ctr_rst?3'b000:3'b001);
end
3'b001:begin
next_state = rst?3'b000:(ctr_rst?3'b000:3'b010);
end
3'b010:begin
next_state = rst?3'b000:(ctr_rst?3'b000:3'b011);
end
3'b011:begin
next_state = rst?3'b000:(ctr_rst?3'b000:3'b100);
end
3'b1??:begin
next_state = rst?3'b000:(ctr_rst?3'b000:3'b101);
end
default:begin
$display("error");
end
endcase
end
assign out = state;
endmodule | module sc( clk, rst, ctr_rst, out, err); |
input clk;
input rst;
input ctr_rst;
output [2:0] out;
output err;
wire [2:0] state;
reg [2:0] next_state;
dff curr_state[2:0] (
.q (state),
.d (next_state),
.clk (clk),
.rst (rst));
always@(*)begin
casex(state)
3'b000:begin
next_state = rst?3'b000:(ctr_rst?3'b000:3'b001);
end
3'b001:begin
next_state = rst?3'b000:(ctr_rst?3'b000:3'b010);
end
3'b010:begin
next_state = rst?3'b000:(ctr_rst?3'b000:3'b011);
end
3'b011:begin
next_state = rst?3'b000:(ctr_rst?3'b000:3'b100);
end
3'b1??:begin
next_state = rst?3'b000:(ctr_rst?3'b000:3'b101);
end
default:begin
$display("error");
end
endcase
end
assign out = state;
endmodule | 0 |
139,486 | data/full_repos/permissive/87881270/hw3/hw3_2/sc_bench.v | 87,881,270 | sc_bench.v | v | 75 | 105 | [] | [] | [] | [(5, 73)] | null | null | 1: b'%Error: data/full_repos/permissive/87881270/hw3/hw3_2/sc_bench.v:24: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87881270/hw3/hw3_2/sc_bench.v:26: Unsupported: Ignoring delay on this delayed statement.\n #4800\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87881270/hw3/hw3_2/sc_bench.v:64: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,980 | module | module sc_bench();
reg ctr_rst;
wire [2:0] out;
wire err;
wire clk;
wire rst;
reg [3:0] random_gen;
reg [2:0] expected_out;
reg fail;
sc_hier DUT (.ctr_rst(ctr_rst), .out(out));
assign clk = DUT.clk_generator.clk;
assign rst = DUT.clk_generator.rst;
initial begin
fail = 0;
$dumpvars;
ctr_rst = 1'b0;
#4800
if (fail)
$display("TEST FAILED");
else
$display("TEST PASSED");
$finish;
end
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
begin
expected_out <= 3'b000;
end
else
if (ctr_rst == 1'b1)
begin
expected_out <= 3'b000;
end
else
begin
if (expected_out != 3'b101)
begin
expected_out <= expected_out + 1;
end
end
end
always @ (posedge clk) begin
random_gen = $random %2;
if (random_gen == 1)
ctr_rst = 1'b1;
else
ctr_rst = 1'b0;
end
always @ (posedge clk) begin
#10;
if ((expected_out !== out)) begin
$display("ERRORCHECK :: ctr_rst = %d : out = %d : expected_out = %d", ctr_rst, out, expected_out);
fail = 1;
end
else begin
$display("OKAY :: ctr_rst = %d : out = expected_out = %d", ctr_rst, out);
end
end
endmodule | module sc_bench(); |
reg ctr_rst;
wire [2:0] out;
wire err;
wire clk;
wire rst;
reg [3:0] random_gen;
reg [2:0] expected_out;
reg fail;
sc_hier DUT (.ctr_rst(ctr_rst), .out(out));
assign clk = DUT.clk_generator.clk;
assign rst = DUT.clk_generator.rst;
initial begin
fail = 0;
$dumpvars;
ctr_rst = 1'b0;
#4800
if (fail)
$display("TEST FAILED");
else
$display("TEST PASSED");
$finish;
end
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
begin
expected_out <= 3'b000;
end
else
if (ctr_rst == 1'b1)
begin
expected_out <= 3'b000;
end
else
begin
if (expected_out != 3'b101)
begin
expected_out <= expected_out + 1;
end
end
end
always @ (posedge clk) begin
random_gen = $random %2;
if (random_gen == 1)
ctr_rst = 1'b1;
else
ctr_rst = 1'b0;
end
always @ (posedge clk) begin
#10;
if ((expected_out !== out)) begin
$display("ERRORCHECK :: ctr_rst = %d : out = %d : expected_out = %d", ctr_rst, out, expected_out);
fail = 1;
end
else begin
$display("OKAY :: ctr_rst = %d : out = expected_out = %d", ctr_rst, out);
end
end
endmodule | 0 |
139,487 | data/full_repos/permissive/87881270/hw3/hw3_2/sc_hier.v | 87,881,270 | sc_hier.v | v | 34 | 71 | [] | [] | [] | [(7, 32)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/hw3/hw3_2/sc_hier.v:22: Cannot find file containing module: 'clkrst'\n clkrst clk_generator(.clk(clk), .rst(rst), .err(err) );\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw3/hw3_2,data/full_repos/permissive/87881270/clkrst\n data/full_repos/permissive/87881270/hw3/hw3_2,data/full_repos/permissive/87881270/clkrst.v\n data/full_repos/permissive/87881270/hw3/hw3_2,data/full_repos/permissive/87881270/clkrst.sv\n clkrst\n clkrst.v\n clkrst.sv\n obj_dir/clkrst\n obj_dir/clkrst.v\n obj_dir/clkrst.sv\n%Error: data/full_repos/permissive/87881270/hw3/hw3_2/sc_hier.v:23: Cannot find file containing module: 'sc'\n sc sc0( \n ^~\n%Error: Exiting due to 2 error(s)\n" | 304,981 | module | module sc_hier (
out,
ctr_rst
);
input ctr_rst;
output [2:0] out;
wire err;
wire clk;
wire rst;
clkrst clk_generator(.clk(clk), .rst(rst), .err(err) );
sc sc0(
.out (out[2:0]),
.err (err),
.clk (clk),
.rst (rst),
.ctr_rst (ctr_rst));
endmodule | module sc_hier (
out,
ctr_rst
); |
input ctr_rst;
output [2:0] out;
wire err;
wire clk;
wire rst;
clkrst clk_generator(.clk(clk), .rst(rst), .err(err) );
sc sc0(
.out (out[2:0]),
.err (err),
.clk (clk),
.rst (rst),
.ctr_rst (ctr_rst));
endmodule | 0 |
139,488 | data/full_repos/permissive/87881270/hw3/hw3_3/rf_bypass.v | 87,881,270 | rf_bypass.v | v | 26 | 95 | [] | [] | [] | [(4, 24)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/hw3/hw3_3/rf_bypass.v:21: Cannot find file containing module: 'rf'\n rf r1(read1data,read2data,err,clk,rst,read1regsel,read2regsel,writeregsel,writedata,write);\n ^~\n ... Looked in:\n data/full_repos/permissive/87881270/hw3/hw3_3,data/full_repos/permissive/87881270/rf\n data/full_repos/permissive/87881270/hw3/hw3_3,data/full_repos/permissive/87881270/rf.v\n data/full_repos/permissive/87881270/hw3/hw3_3,data/full_repos/permissive/87881270/rf.sv\n rf\n rf.v\n rf.sv\n obj_dir/rf\n obj_dir/rf.v\n obj_dir/rf.sv\n%Error: Exiting due to 1 error(s)\n" | 304,985 | module | module rf_bypass (
read1data, read2data, err,
clk, rst, read1regsel, read2regsel, writeregsel, writedata, write
);
input clk, rst;
input [2:0] read1regsel;
input [2:0] read2regsel;
input [2:0] writeregsel;
input [15:0] writedata;
input write;
output [15:0] read1data;
output [15:0] read2data;
output err;
rf r1(read1data,read2data,err,clk,rst,read1regsel,read2regsel,writeregsel,writedata,write);
endmodule | module rf_bypass (
read1data, read2data, err,
clk, rst, read1regsel, read2regsel, writeregsel, writedata, write
); |
input clk, rst;
input [2:0] read1regsel;
input [2:0] read2regsel;
input [2:0] writeregsel;
input [15:0] writedata;
input write;
output [15:0] read1data;
output [15:0] read2data;
output err;
rf r1(read1data,read2data,err,clk,rst,read1regsel,read2regsel,writeregsel,writedata,write);
endmodule | 0 |
139,489 | data/full_repos/permissive/87881270/hw3/hw3_3/rf_bypass_hier.v | 87,881,270 | rf_bypass_hier.v | v | 44 | 72 | [] | [] | [] | [(7, 42)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/hw3/hw3_3/rf_bypass_hier.v:27: Cannot find file containing module: 'clkrst'\n clkrst clk_generator(.clk(clk), .rst(rst), .err(err) );\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw3/hw3_3,data/full_repos/permissive/87881270/clkrst\n data/full_repos/permissive/87881270/hw3/hw3_3,data/full_repos/permissive/87881270/clkrst.v\n data/full_repos/permissive/87881270/hw3/hw3_3,data/full_repos/permissive/87881270/clkrst.sv\n clkrst\n clkrst.v\n clkrst.sv\n obj_dir/clkrst\n obj_dir/clkrst.v\n obj_dir/clkrst.sv\n%Error: data/full_repos/permissive/87881270/hw3/hw3_3/rf_bypass_hier.v:28: Cannot find file containing module: 'rf_bypass'\n rf_bypass rf_b_0(\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 304,986 | module | module rf_bypass_hier (
read1data, read2data,
read1regsel, read2regsel, writeregsel, writedata, write
);
input [2:0] read1regsel;
input [2:0] read2regsel;
input [2:0] writeregsel;
input [15:0] writedata;
input write;
output [15:0] read1data;
output [15:0] read2data;
wire clk, rst;
wire err;
clkrst clk_generator(.clk(clk), .rst(rst), .err(err) );
rf_bypass rf_b_0(
.read1data (read1data[15:0]),
.read2data (read2data[15:0]),
.err (err),
.clk (clk),
.rst (rst),
.read1regsel (read1regsel[2:0]),
.read2regsel (read2regsel[2:0]),
.writeregsel (writeregsel[2:0]),
.writedata (writedata[15:0]),
.write (write));
endmodule | module rf_bypass_hier (
read1data, read2data,
read1regsel, read2regsel, writeregsel, writedata, write
); |
input [2:0] read1regsel;
input [2:0] read2regsel;
input [2:0] writeregsel;
input [15:0] writedata;
input write;
output [15:0] read1data;
output [15:0] read2data;
wire clk, rst;
wire err;
clkrst clk_generator(.clk(clk), .rst(rst), .err(err) );
rf_bypass rf_b_0(
.read1data (read1data[15:0]),
.read2data (read2data[15:0]),
.err (err),
.clk (clk),
.rst (rst),
.read1regsel (read1regsel[2:0]),
.read2regsel (read2regsel[2:0]),
.writeregsel (writeregsel[2:0]),
.writedata (writedata[15:0]),
.write (write));
endmodule | 0 |
139,490 | data/full_repos/permissive/87881270/hw3/hw3_3/rf_bypass_hier_bench.v | 87,881,270 | rf_bypass_hier_bench.v | v | 129 | 151 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/87881270/hw3/hw3_3/rf_bypass_hier_bench.v:62: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/87881270/hw3/hw3_3/rf_bypass_hier_bench.v:94: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,987 | module | module rf_bypass_hier_bench();
wire [15:0] read1data;
wire [15:0] read2data;
reg [2:0] read1regsel;
reg [2:0] read2regsel;
reg write;
reg [15:0] writedata;
reg [2:0] writeregsel;
integer cycle_count;
integer n_errors;
wire clk;
wire rst;
rf_bypass_hier DUT(
.read1data (read1data[15:0]),
.read2data (read2data[15:0]),
.read1regsel (read1regsel[2:0]),
.read2regsel (read2regsel[2:0]),
.writeregsel (writeregsel[2:0]),
.writedata (writedata[15:0]),
.write (write));
assign clk = DUT.clk_generator.clk;
assign rst = DUT.clk_generator.rst;
reg [15:0] ref_rf[7:0];
reg [15:0] ref_r1data;
reg [15:0] ref_r2data;
initial begin
cycle_count = 0;
n_errors = 0;
ref_rf[0] = 0;
ref_rf[1] = 0;
ref_rf[2] = 0;
ref_rf[3] = 0;
ref_rf[4] = 0;
ref_rf[5] = 0;
ref_rf[6] = 0;
ref_rf[7] = 0;
ref_r1data = 0;
ref_r2data = 0;
write = 0;
$dumpvars;
$display("Simulation 1000 cycles");
end
always @ (posedge clk)begin
read1regsel = $random % 8;
read2regsel = $random % 8;
writedata = $random % 65536;
writeregsel = $random % 8;
write = $random % 2;
if ((cycle_count >= 2) && write) begin
ref_rf[ writeregsel ] = writedata;
end
ref_r1data = ref_rf[ read1regsel ];
ref_r2data = ref_rf[ read2regsel ];
#10
$display("Cycle: %4d R1 Sel: %d R1 Data: %d Expected R1 Data: %d R2 Sel: %d R2 Data: %d Expected R2 data: %d W Sel: %d W Data: %d W Enable: %d",
cycle_count,
read1regsel, read1data, ref_r1data,
read2regsel, read2data, ref_r2data,
writeregsel, writedata, write );
if ( !rst && ( (ref_r1data !== read1data)
|| (ref_r2data !== read2data) ) ) begin
$display("ERRORCHECK: Read data incorrect in cycle %4d", cycle_count);
n_errors = n_errors + 1;
end
if ( !rst && ( (read1regsel === read2regsel) ) ) begin
$display("FYI: Both read ports are same in cycle %4d", cycle_count);
end
if ( !rst && ( (read1regsel === writeregsel) || (read2regsel === writeregsel) ) && (write) ) begin
$display("FYI: Read/write of same port in cycle %4d", cycle_count);
end
cycle_count = cycle_count + 1;
if (cycle_count > 1000) begin
if (n_errors > 0)
$display("\nTEST FAILED WITH %2d ERRORS\n", n_errors);
else
$display("\nTEST PASSED\n");
$stop;
end
end
endmodule | module rf_bypass_hier_bench(); |
wire [15:0] read1data;
wire [15:0] read2data;
reg [2:0] read1regsel;
reg [2:0] read2regsel;
reg write;
reg [15:0] writedata;
reg [2:0] writeregsel;
integer cycle_count;
integer n_errors;
wire clk;
wire rst;
rf_bypass_hier DUT(
.read1data (read1data[15:0]),
.read2data (read2data[15:0]),
.read1regsel (read1regsel[2:0]),
.read2regsel (read2regsel[2:0]),
.writeregsel (writeregsel[2:0]),
.writedata (writedata[15:0]),
.write (write));
assign clk = DUT.clk_generator.clk;
assign rst = DUT.clk_generator.rst;
reg [15:0] ref_rf[7:0];
reg [15:0] ref_r1data;
reg [15:0] ref_r2data;
initial begin
cycle_count = 0;
n_errors = 0;
ref_rf[0] = 0;
ref_rf[1] = 0;
ref_rf[2] = 0;
ref_rf[3] = 0;
ref_rf[4] = 0;
ref_rf[5] = 0;
ref_rf[6] = 0;
ref_rf[7] = 0;
ref_r1data = 0;
ref_r2data = 0;
write = 0;
$dumpvars;
$display("Simulation 1000 cycles");
end
always @ (posedge clk)begin
read1regsel = $random % 8;
read2regsel = $random % 8;
writedata = $random % 65536;
writeregsel = $random % 8;
write = $random % 2;
if ((cycle_count >= 2) && write) begin
ref_rf[ writeregsel ] = writedata;
end
ref_r1data = ref_rf[ read1regsel ];
ref_r2data = ref_rf[ read2regsel ];
#10
$display("Cycle: %4d R1 Sel: %d R1 Data: %d Expected R1 Data: %d R2 Sel: %d R2 Data: %d Expected R2 data: %d W Sel: %d W Data: %d W Enable: %d",
cycle_count,
read1regsel, read1data, ref_r1data,
read2regsel, read2data, ref_r2data,
writeregsel, writedata, write );
if ( !rst && ( (ref_r1data !== read1data)
|| (ref_r2data !== read2data) ) ) begin
$display("ERRORCHECK: Read data incorrect in cycle %4d", cycle_count);
n_errors = n_errors + 1;
end
if ( !rst && ( (read1regsel === read2regsel) ) ) begin
$display("FYI: Both read ports are same in cycle %4d", cycle_count);
end
if ( !rst && ( (read1regsel === writeregsel) || (read2regsel === writeregsel) ) && (write) ) begin
$display("FYI: Read/write of same port in cycle %4d", cycle_count);
end
cycle_count = cycle_count + 1;
if (cycle_count > 1000) begin
if (n_errors > 0)
$display("\nTEST FAILED WITH %2d ERRORS\n", n_errors);
else
$display("\nTEST PASSED\n");
$stop;
end
end
endmodule | 0 |
139,491 | data/full_repos/permissive/87881270/hw4/hw4_1/fifo.v | 87,881,270 | fifo.v | v | 143 | 104 | [] | [] | [] | [(4, 141)] | null | null | 1: b'%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo.v:35: Cannot find file containing module: \'dff\'\ndff curr_state[2:0] (\n^~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw4/hw4_1,data/full_repos/permissive/87881270/dff\n data/full_repos/permissive/87881270/hw4/hw4_1,data/full_repos/permissive/87881270/dff.v\n data/full_repos/permissive/87881270/hw4/hw4_1,data/full_repos/permissive/87881270/dff.sv\n dff\n dff.v\n dff.sv\n obj_dir/dff\n obj_dir/dff.v\n obj_dir/dff.sv\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo.v:43: Cannot find file containing module: \'dff\'\ndff fifo1[63:0] (\n^~~\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo.v:51: Cannot find file containing module: \'dff\'\ndff fifo2[63:0] (\n^~~\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo.v:59: Cannot find file containing module: \'dff\'\ndff fifo3[63:0] (\n^~~\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo.v:67: Cannot find file containing module: \'dff\'\ndff fifo4[63:0] (\n^~~\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo.v:75: Cannot find file containing module: \'dff\'\ndff outputdff[63:0] (\n^~~\n%Warning-WIDTH: data/full_repos/permissive/87881270/hw4/hw4_1/fifo.v:87: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance fifo\n dataIn1 = rst?3\'b000:(data_in_valid?data_in:dataOut1);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/87881270/hw4/hw4_1/fifo.v:94: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance fifo\n dataIn1 = rst?3\'b000:(data_in_valid?data_in:dataOut1);\n ^\n%Warning-WIDTH: data/full_repos/permissive/87881270/hw4/hw4_1/fifo.v:95: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance fifo\n dataIn2 = rst?3\'b000:(data_in_valid?dataOut1:dataOut2);\n ^\n%Warning-WIDTH: data/full_repos/permissive/87881270/hw4/hw4_1/fifo.v:102: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance fifo\n dataIn1 = rst?3\'b000:(data_in_valid?data_in:dataOut1);\n ^\n%Warning-WIDTH: data/full_repos/permissive/87881270/hw4/hw4_1/fifo.v:103: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance fifo\n dataIn2 = rst?3\'b000:(data_in_valid?dataOut1:dataOut2);\n ^\n%Warning-WIDTH: data/full_repos/permissive/87881270/hw4/hw4_1/fifo.v:104: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance fifo\n dataIn3 = rst?3\'b000:(data_in_valid?dataOut2:dataOut3);\n ^\n%Warning-WIDTH: data/full_repos/permissive/87881270/hw4/hw4_1/fifo.v:111: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance fifo\n dataIn1 = rst?3\'b000:(data_in_valid?data_in:dataOut1);\n ^\n%Warning-WIDTH: data/full_repos/permissive/87881270/hw4/hw4_1/fifo.v:112: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance fifo\n dataIn2 = rst?3\'b000:(data_in_valid?dataOut1:dataOut2);\n ^\n%Warning-WIDTH: data/full_repos/permissive/87881270/hw4/hw4_1/fifo.v:113: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance fifo\n dataIn3 = rst?3\'b000:(data_in_valid?dataOut2:dataOut3);\n ^\n%Warning-WIDTH: data/full_repos/permissive/87881270/hw4/hw4_1/fifo.v:114: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance fifo\n dataIn4 = rst?3\'b000:(data_in_valid?dataOut3:dataOut4);\n ^\n%Warning-WIDTH: data/full_repos/permissive/87881270/hw4/hw4_1/fifo.v:121: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance fifo\n dataIn1 = rst?3\'b000:(data_in_valid?dataOut1:dataOut1);\n ^\n%Warning-WIDTH: data/full_repos/permissive/87881270/hw4/hw4_1/fifo.v:122: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance fifo\n dataIn2 = rst?3\'b000:(data_in_valid?dataOut2:dataOut2);\n ^\n%Warning-WIDTH: data/full_repos/permissive/87881270/hw4/hw4_1/fifo.v:123: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance fifo\n dataIn3 = rst?3\'b000:(data_in_valid?dataOut3:dataOut3);\n ^\n%Warning-WIDTH: data/full_repos/permissive/87881270/hw4/hw4_1/fifo.v:124: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance fifo\n dataIn4 = rst?3\'b000:(data_in_valid?dataOut4:dataOut4);\n ^\n%Error: Exiting due to 6 error(s), 14 warning(s)\n' | 304,990 | module | module fifo(
data_out, fifo_empty, fifo_full, err,
data_in, data_in_valid, pop_fifo, clk, rst
);
input [63:0] data_in;
input data_in_valid;
input pop_fifo;
input clk;
input rst;
output [63:0] data_out;
output fifo_empty;
output fifo_full;
output err;
wire [2:0] state;
reg full, empty, error;
reg [2:0] next_state;
reg [63:0] outi,
dataIn1,
dataIn2,
dataIn3,
dataIn4;
wire [63:0] out,
dataOut1,
dataOut2,
dataOut3,
dataOut4;
dff curr_state[2:0] (
.q (state),
.d (next_state),
.clk (clk),
.rst (rst));
dff fifo1[63:0] (
.q (dataOut1),
.d (dataIn1),
.clk (clk),
.rst (rst));
dff fifo2[63:0] (
.q (dataOut2),
.d (dataIn2),
.clk (clk),
.rst (rst));
dff fifo3[63:0] (
.q (dataOut3),
.d (dataIn3),
.clk (clk),
.rst (rst));
dff fifo4[63:0] (
.q (dataOut4),
.d (dataIn4),
.clk (clk),
.rst (rst));
dff outputdff[63:0] (
.q (out),
.d (outi),
.clk (clk),
.rst (rst));
always@(*)begin
case(state)
3'b000:begin
next_state = rst?3'b000:(data_in_valid?3'b001:3'b000);
dataIn1 = rst?3'b000:(data_in_valid?data_in:dataOut1);
outi = data_in_valid?dataIn1:0;
empty = 1;
full = 0;
end
3'b001:begin
next_state = rst?3'b000:(data_in_valid?(pop_fifo?3'b001:3'b010):(pop_fifo?3'b000:3'b001));
dataIn1 = rst?3'b000:(data_in_valid?data_in:dataOut1);
dataIn2 = rst?3'b000:(data_in_valid?dataOut1:dataOut2);
outi = data_in_valid?(pop_fifo?dataIn1:dataIn2):(pop_fifo?0:dataIn1);
empty = 0;
full = 0;
end
3'b010:begin
next_state = rst?3'b000:(data_in_valid?(pop_fifo?3'b010:3'b011):(pop_fifo?3'b001:3'b010));
dataIn1 = rst?3'b000:(data_in_valid?data_in:dataOut1);
dataIn2 = rst?3'b000:(data_in_valid?dataOut1:dataOut2);
dataIn3 = rst?3'b000:(data_in_valid?dataOut2:dataOut3);
outi = data_in_valid?(pop_fifo?dataIn2:dataIn3):(pop_fifo?dataIn1:dataIn2);
full = 0;
empty = 0;
end
3'b011:begin
next_state = rst?3'b000:(data_in_valid?(pop_fifo?3'b011:3'b100):(pop_fifo?3'b010:3'b011));
dataIn1 = rst?3'b000:(data_in_valid?data_in:dataOut1);
dataIn2 = rst?3'b000:(data_in_valid?dataOut1:dataOut2);
dataIn3 = rst?3'b000:(data_in_valid?dataOut2:dataOut3);
dataIn4 = rst?3'b000:(data_in_valid?dataOut3:dataOut4);
outi = data_in_valid?(pop_fifo?dataIn3:dataIn4):(pop_fifo?dataIn2:dataIn3);
full = 0;
empty = 0;
end
3'b100:begin
next_state = rst?3'b000:(pop_fifo?3'b011:3'b100);
dataIn1 = rst?3'b000:(data_in_valid?dataOut1:dataOut1);
dataIn2 = rst?3'b000:(data_in_valid?dataOut2:dataOut2);
dataIn3 = rst?3'b000:(data_in_valid?dataOut3:dataOut3);
dataIn4 = rst?3'b000:(data_in_valid?dataOut4:dataOut4);
outi = pop_fifo?dataIn3:dataIn4;
full = 1;
empty = 0;
end
default:begin
end
endcase
end
assign data_out = out;
assign fifo_full = full;
assign fifo_empty = empty;
assign err = error;
endmodule | module fifo(
data_out, fifo_empty, fifo_full, err,
data_in, data_in_valid, pop_fifo, clk, rst
); |
input [63:0] data_in;
input data_in_valid;
input pop_fifo;
input clk;
input rst;
output [63:0] data_out;
output fifo_empty;
output fifo_full;
output err;
wire [2:0] state;
reg full, empty, error;
reg [2:0] next_state;
reg [63:0] outi,
dataIn1,
dataIn2,
dataIn3,
dataIn4;
wire [63:0] out,
dataOut1,
dataOut2,
dataOut3,
dataOut4;
dff curr_state[2:0] (
.q (state),
.d (next_state),
.clk (clk),
.rst (rst));
dff fifo1[63:0] (
.q (dataOut1),
.d (dataIn1),
.clk (clk),
.rst (rst));
dff fifo2[63:0] (
.q (dataOut2),
.d (dataIn2),
.clk (clk),
.rst (rst));
dff fifo3[63:0] (
.q (dataOut3),
.d (dataIn3),
.clk (clk),
.rst (rst));
dff fifo4[63:0] (
.q (dataOut4),
.d (dataIn4),
.clk (clk),
.rst (rst));
dff outputdff[63:0] (
.q (out),
.d (outi),
.clk (clk),
.rst (rst));
always@(*)begin
case(state)
3'b000:begin
next_state = rst?3'b000:(data_in_valid?3'b001:3'b000);
dataIn1 = rst?3'b000:(data_in_valid?data_in:dataOut1);
outi = data_in_valid?dataIn1:0;
empty = 1;
full = 0;
end
3'b001:begin
next_state = rst?3'b000:(data_in_valid?(pop_fifo?3'b001:3'b010):(pop_fifo?3'b000:3'b001));
dataIn1 = rst?3'b000:(data_in_valid?data_in:dataOut1);
dataIn2 = rst?3'b000:(data_in_valid?dataOut1:dataOut2);
outi = data_in_valid?(pop_fifo?dataIn1:dataIn2):(pop_fifo?0:dataIn1);
empty = 0;
full = 0;
end
3'b010:begin
next_state = rst?3'b000:(data_in_valid?(pop_fifo?3'b010:3'b011):(pop_fifo?3'b001:3'b010));
dataIn1 = rst?3'b000:(data_in_valid?data_in:dataOut1);
dataIn2 = rst?3'b000:(data_in_valid?dataOut1:dataOut2);
dataIn3 = rst?3'b000:(data_in_valid?dataOut2:dataOut3);
outi = data_in_valid?(pop_fifo?dataIn2:dataIn3):(pop_fifo?dataIn1:dataIn2);
full = 0;
empty = 0;
end
3'b011:begin
next_state = rst?3'b000:(data_in_valid?(pop_fifo?3'b011:3'b100):(pop_fifo?3'b010:3'b011));
dataIn1 = rst?3'b000:(data_in_valid?data_in:dataOut1);
dataIn2 = rst?3'b000:(data_in_valid?dataOut1:dataOut2);
dataIn3 = rst?3'b000:(data_in_valid?dataOut2:dataOut3);
dataIn4 = rst?3'b000:(data_in_valid?dataOut3:dataOut4);
outi = data_in_valid?(pop_fifo?dataIn3:dataIn4):(pop_fifo?dataIn2:dataIn3);
full = 0;
empty = 0;
end
3'b100:begin
next_state = rst?3'b000:(pop_fifo?3'b011:3'b100);
dataIn1 = rst?3'b000:(data_in_valid?dataOut1:dataOut1);
dataIn2 = rst?3'b000:(data_in_valid?dataOut2:dataOut2);
dataIn3 = rst?3'b000:(data_in_valid?dataOut3:dataOut3);
dataIn4 = rst?3'b000:(data_in_valid?dataOut4:dataOut4);
outi = pop_fifo?dataIn3:dataIn4;
full = 1;
empty = 0;
end
default:begin
end
endcase
end
assign data_out = out;
assign fifo_full = full;
assign fifo_empty = empty;
assign err = error;
endmodule | 0 |
139,492 | data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v | 87,881,270 | fifo_bench.v | v | 1,421 | 141 | [] | [] | [] | null | line:54 column:19: Illegal character "'" | null | 1: b"%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:62: syntax error, unexpected '@'\n @(negedge rst);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:73: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:82: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:91: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:100: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:109: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:118: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:127: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:136: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:145: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:154: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:163: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:172: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:181: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:190: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:199: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:208: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:217: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:226: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:235: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:244: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:253: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:262: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:271: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:280: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:289: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:298: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:307: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:316: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:325: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:334: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:343: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:352: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:361: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:370: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:379: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:388: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:397: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:406: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:415: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:424: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:433: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:442: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:451: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:460: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:469: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:478: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:487: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:496: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_bench.v:505: syntax error, unexpected '@'\n @(posedge clk);\n ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n" | 304,991 | module | module fifo_bench;
reg [63:0] data_in;
reg data_in_valid;
reg pop_fifo;
wire [63:0] data_out;
wire fifo_empty;
wire fifo_full;
reg err;
wire clk;
wire rst;
integer cycle_count;
reg fail;
reg partial_fail;
reg [63:0] data_out_gold;
reg fifo_empty_gold;
reg fifo_full_gold;
reg data_out_valid_gold;
fifo_hier DUT (
data_out, fifo_empty, fifo_full,
data_in, data_in_valid, pop_fifo);
assign clk = DUT.clk_generator.clk;
assign rst = DUT.clk_generator.rst;
always @ (posedge clk)
begin
end
initial
begin
cycle_count = 0;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
data_in = '0;
fifo_empty_gold = 1;
fifo_full_gold = 0;
data_out_valid_gold = 0;
data_out_gold = '0;
fail = 0;
partial_fail = 0;
@(negedge rst);
data_in = 64'h462df78c76d457ed;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h462df78c76d457ed;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hd513d2aae2f784c5;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hd513d2aae2f784c5;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h47ecdb8f8932d612;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd513d2aae2f784c5;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'he2ca4ec5f4007ae8;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hb2a7266596ab582d;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hb2a7266596ab582d;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h10642120c03b2280;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h8983b813cb203e96;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h8983b813cb203e96;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'heaa62ad5359fdd6b;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h8983b813cb203e96;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'he7c572cf0effe91d;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h8983b813cb203e96;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h9e314c3ce5730aca;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h8983b813cb203e96;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hec4b34d820c4b341;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'he7c572cf0effe91d;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h5b0265b675c50deb;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'he7c572cf0effe91d;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h150fdd2ade7502bc;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h150fdd2ade7502bc;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h27f2554f42f24185;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h150fdd2ade7502bc;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h0aaa4b15bf23327e;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h27f2554f42f24185;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h2635fb4c31230762;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h0aaa4b15bf23327e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hdbcd60b77c6da9f8;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h0aaa4b15bf23327e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h44de3789adcbc05b;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h0aaa4b15bf23327e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'ha8c7fc51ebfec0d7;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h0aaa4b15bf23327e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b1;
data_in = 64'h6457edc8e12ccec2;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h2635fb4c31230762;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hbf05007e090cdb12;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hdbcd60b77c6da9f8;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'he9ebf6d30fd28f1f;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hdbcd60b77c6da9f8;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'h248b4b492dda595b;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hdbcd60b77c6da9f8;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'hc33f38862c156358;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hdbcd60b77c6da9f8;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b1;
data_in = 64'h937dbc267d3599fa;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h44de3789adcbc05b;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hd9d292b39799a82f;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h44de3789adcbc05b;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'he59b36cb7bf8fdf7;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h44de3789adcbc05b;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b1;
data_in = 64'hf682e2ed14cfc129;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hbf05007e090cdb12;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hefbe94dfda8ae2b5;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hbf05007e090cdb12;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'h15090b2ae8740cd0;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hbf05007e090cdb12;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b1;
data_in = 64'hcd5ebc9a6e5daddc;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'he9ebf6d30fd28f1f;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h2779e94e2b0eed56;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'he9ebf6d30fd28f1f;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'h9c0e8a385b6fb9b6;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'he9ebf6d30fd28f1f;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b1;
data_in = 64'h49c65d934a74bf94;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hd9d292b39799a82f;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'ha6fcde4d6dcb69db;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hefbe94dfda8ae2b5;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h653b49cabb45e276;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h2779e94e2b0eed56;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h02749b04a3071a46;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'ha6fcde4d6dcb69db;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h44018d88da6ebab4;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h02749b04a3071a46;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h975c9c2ee3c530c7;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h02749b04a3071a46;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h149e0729fea7a6fd;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h02749b04a3071a46;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h9eb7c63ded3408da;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h02749b04a3071a46;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h5d7199bab9f50473;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h02749b04a3071a46;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h8d24f61a6a8e05d5;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h8d24f61a6a8e05d5;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h603921c04b273796;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h8d24f61a6a8e05d5;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h6e5f0fdc3e99837d;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h8d24f61a6a8e05d5;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hed8d80db3f5a9b7e;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hed8d80db3f5a9b7e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hb0bcee61fd28e4fa;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hb0bcee61fd28e4fa;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'ha863965043779186;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'ha863965043779186;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h60b175c1949a8a29;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'ha863965043779186;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hb98c427325b27b4b;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'ha863965043779186;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hd44b80a82758d14e;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h60b175c1949a8a29;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hf33466e6070bb90e;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h60b175c1949a8a29;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hc6b5f48d155a1d2a;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h60b175c1949a8a29;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h6464e3c8bccfa879;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hd44b80a82758d14e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'he3b7aec735a0c96b;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd44b80a82758d14e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h5c8295b96216abc4;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd44b80a82758d14e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hc33390863fbb3b7f;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd44b80a82758d14e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hdece5ebd19452132;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd44b80a82758d14e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h54a879a96543cfca;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd44b80a82758d14e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h85e51e0bfd8b6afb;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hf33466e6070bb90e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hbab148751b60e536;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h54a879a96543cfca;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hd73fb4ae4465e788;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h54a879a96543cfca;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'h9684e02d1444df28;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h54a879a96543cfca;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'h06b3050d8f1cf61e;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h54a879a96543cfca;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b1;
data_in = 64'hc3761c8668ae1bd1;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h85e51e0bfd8b6afb;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h29efe9536c44f9d8;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hbab148751b60e536;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h8273e204f166fae2;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hbab148751b60e536;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hdc0344b8093e4d12;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hd73fb4ae4465e788;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h15890f2bd0c5dca1;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd73fb4ae4465e788;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'h50d5f9a113b55527;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd73fb4ae4465e788;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'hcb5c80962c2d2358;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd73fb4ae4465e788;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b1;
data_in = 64'hd8ace2b1cb227096;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h8273e204f166fae2;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h7ab11bf5158b2b2b;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hdc0344b8093e4d12;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hd3a8e4a74249ff84;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h15890f2bd0c5dca1;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h6de5bbdba4da5649;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h7ab11bf5158b2b2b;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h1546dd2ad0bc5ea1;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hd3a8e4a74249ff84;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hbe75427c41a10583;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd3a8e4a74249ff84;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hb7dfaa6fb455f268;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd3a8e4a74249ff84;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h207691401c719738;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd3a8e4a74249ff84;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h602831c0e2bf1ac5;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h6de5bbdba4da5649;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h1e1c873cd86a6ab0;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h6de5bbdba4da5649;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hf0b14ee10aec3515;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hf0b14ee10aec3515;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hc336048664b5e3c9;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hc336048664b5e3c9;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'had67e25ac69da28d;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hc336048664b5e3c9;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hb8ade671060a5d0c;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hc336048664b5e3c9;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hcf14ce9efbdfc2f7;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'had67e25ac69da28d;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hd00b12a0902a3a20;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'had67e25ac69da28d;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h86dcf00d6e8af5dd;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hb8ade671060a5d0c;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hfef064fdcf63da9e;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h86dcf00d6e8af5dd;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h71c129e381c39a03;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hfef064fdcf63da9e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hca9cbc9522119f44;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h71c129e381c39a03;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h7c1e5bf8297a1552;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h71c129e381c39a03;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h236afd464219e784;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h71c129e381c39a03;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h352d616a0beac117;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h71c129e381c39a03;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hb05202603e6f0f7c;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h7c1e5bf8297a1552;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h92831e25d31dfea6;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h7c1e5bf8297a1552;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h8a64b014a48f7c49;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h8a64b014a48f7c49;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h23907547ae68305c;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h6851e5d0da058ab4;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hb522406a03e9b707;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hb522406a03e9b707;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h39e48173a5e79e4b;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h64e165c9520eefa4;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h64e165c9520eefa4;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h33836567ea5814d4;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h64e165c9520eefa4;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h24d2bf4941103982;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h64e165c9520eefa4;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h49b16f938e054c1c;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h64e165c9520eefa4;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'haed72e5de471f8c8;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h64e165c9520eefa4;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'h1c8d7f3995a9a82b;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h64e165c9520eefa4;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b1;
data_in = 64'he82b96d02c848959;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h33836567ea5814d4;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h535277a66d8b87db;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h33836567ea5814d4;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b1;
data_in = 64'hb4e8d66987e44c0f;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h24d2bf4941103982;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h67d735cf62fd49c5;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h49b16f938e054c1c;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h3b83cd77b4f9a469;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h49b16f938e054c1c;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'he20e9ac44ddd4d9b;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h535277a66d8b87db;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h984d5a30c378ee86;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h984d5a30c378ee86;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h038787076a15f5d4;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h00f25f0145e28b8b;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h00f25f0145e28b8b;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'he2ecdac5611d9fc2;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h57fbb9afb302da66;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h57fbb9afb302da66;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hf78576ef8376ac06;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hf78576ef8376ac06;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h304e4d60f7723eee;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hf78576ef8376ac06;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h14b43729322f7d64;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h304e4d60f7723eee;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h40aaf5813715156e;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h304e4d60f7723eee;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hd57800aa786271f0;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h14b43729322f7d64;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h472e958ebe9bbc7d;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h14b43729322f7d64;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h77ebb1efd4b5e6a9;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h40aaf5813715156e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h5cd20db925029b4a;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hd57800aa786271f0;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h28c6275132dc4165;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h77ebb1efd4b5e6a9;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hb8ea3a719d12083a;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h77ebb1efd4b5e6a9;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hbeda447d1513dd2a;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h5cd20db925029b4a;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'he4a800c976de6bed;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h28c6275132dc4165;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'he696e8cdeda71cdb;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h28c6275132dc4165;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h5e983dbdd14820a2;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h28c6275132dc4165;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hbd86f47ba86c5e50;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h28c6275132dc4165;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b1;
data_in = 64'hae23ce5c7b7b89f6;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hbeda447d1513dd2a;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hddd146bb644605c8;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'he4a800c976de6bed;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'he70f98ce0671030c;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hbd86f47ba86c5e50;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hd9b8c0b35ca26fb9;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h9cfc7a39066cf10c;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h271c434e02fbf905;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h46e7538d847fb208;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h46e7538d847fb208;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h7af6abf548590990;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h12a90325a005a640;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h12a90325a005a640;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h94ded82916cbf92d;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h12a90325a005a640;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h2876695060272dc0;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h2876695060272dc0;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h7a87aff5faf32ef5;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h2876695060272dc0;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
if (fail)
$display("TEST FAILED");
else if (partial_fail)
$display("TEST FAILED WITH MINOR ERRORS");
else
$display("TEST PASSED");
$finish;
end
always @ (posedge clk)
begin
$display("\nCycle: %4d data_in: %x, data_in_valid: %b, pop_fifo: %b", cycle_count, data_in, data_in_valid, pop_fifo);
# 10;
if (data_out_valid_gold == 1'b1) begin
$display(" data_out: %x, Expected data_out: %x, fifo_empty: %b, Expected fifo_empty: %b, fifo_full: %b, Expected fifo_full: %b",
data_out, data_out_gold, fifo_empty, fifo_empty_gold, fifo_full, fifo_full_gold);
end
else begin
$display(" (data_out NOT CHECKED in this cycle) fifo_empty: %b, Expected fifo_empty: %b, fifo_full: %b, Expected fifo_full: %b",
fifo_empty, fifo_empty_gold, fifo_full, fifo_full_gold);
end
if (fifo_full !== fifo_full_gold) begin
$display("MINORCHECK : In cycle %4d - FULL logic : full = %d, expected full = %d", cycle_count, fifo_full, fifo_full_gold);
partial_fail = 1;
end
if (fifo_empty !== fifo_empty_gold) begin
$display("MINORCHECK : In cycle %4d - EMPTY logic : empty = %d, expected empty = %d", cycle_count, fifo_empty, fifo_empty_gold);
partial_fail = 1;
end
if (data_out !== data_out_gold && data_out_valid_gold === 1'b1)
begin
fail = 1;
err = 1'b1;
$display("ERRORCHECK : In cycle %4d - Data out error. data_out = %x, expcted data_out = %x", cycle_count, data_out, data_out_gold);
end
else
err = 1'b0;
cycle_count = cycle_count + 1;
end
endmodule | module fifo_bench; |
reg [63:0] data_in;
reg data_in_valid;
reg pop_fifo;
wire [63:0] data_out;
wire fifo_empty;
wire fifo_full;
reg err;
wire clk;
wire rst;
integer cycle_count;
reg fail;
reg partial_fail;
reg [63:0] data_out_gold;
reg fifo_empty_gold;
reg fifo_full_gold;
reg data_out_valid_gold;
fifo_hier DUT (
data_out, fifo_empty, fifo_full,
data_in, data_in_valid, pop_fifo);
assign clk = DUT.clk_generator.clk;
assign rst = DUT.clk_generator.rst;
always @ (posedge clk)
begin
end
initial
begin
cycle_count = 0;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
data_in = '0;
fifo_empty_gold = 1;
fifo_full_gold = 0;
data_out_valid_gold = 0;
data_out_gold = '0;
fail = 0;
partial_fail = 0;
@(negedge rst);
data_in = 64'h462df78c76d457ed;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h462df78c76d457ed;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hd513d2aae2f784c5;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hd513d2aae2f784c5;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h47ecdb8f8932d612;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd513d2aae2f784c5;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'he2ca4ec5f4007ae8;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hb2a7266596ab582d;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hb2a7266596ab582d;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h10642120c03b2280;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h8983b813cb203e96;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h8983b813cb203e96;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'heaa62ad5359fdd6b;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h8983b813cb203e96;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'he7c572cf0effe91d;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h8983b813cb203e96;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h9e314c3ce5730aca;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h8983b813cb203e96;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hec4b34d820c4b341;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'he7c572cf0effe91d;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h5b0265b675c50deb;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'he7c572cf0effe91d;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h150fdd2ade7502bc;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h150fdd2ade7502bc;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h27f2554f42f24185;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h150fdd2ade7502bc;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h0aaa4b15bf23327e;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h27f2554f42f24185;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h2635fb4c31230762;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h0aaa4b15bf23327e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hdbcd60b77c6da9f8;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h0aaa4b15bf23327e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h44de3789adcbc05b;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h0aaa4b15bf23327e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'ha8c7fc51ebfec0d7;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h0aaa4b15bf23327e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b1;
data_in = 64'h6457edc8e12ccec2;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h2635fb4c31230762;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hbf05007e090cdb12;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hdbcd60b77c6da9f8;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'he9ebf6d30fd28f1f;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hdbcd60b77c6da9f8;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'h248b4b492dda595b;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hdbcd60b77c6da9f8;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'hc33f38862c156358;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hdbcd60b77c6da9f8;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b1;
data_in = 64'h937dbc267d3599fa;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h44de3789adcbc05b;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hd9d292b39799a82f;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h44de3789adcbc05b;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'he59b36cb7bf8fdf7;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h44de3789adcbc05b;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b1;
data_in = 64'hf682e2ed14cfc129;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hbf05007e090cdb12;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hefbe94dfda8ae2b5;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hbf05007e090cdb12;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'h15090b2ae8740cd0;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hbf05007e090cdb12;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b1;
data_in = 64'hcd5ebc9a6e5daddc;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'he9ebf6d30fd28f1f;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h2779e94e2b0eed56;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'he9ebf6d30fd28f1f;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'h9c0e8a385b6fb9b6;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'he9ebf6d30fd28f1f;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b1;
data_in = 64'h49c65d934a74bf94;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hd9d292b39799a82f;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'ha6fcde4d6dcb69db;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hefbe94dfda8ae2b5;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h653b49cabb45e276;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h2779e94e2b0eed56;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h02749b04a3071a46;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'ha6fcde4d6dcb69db;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h44018d88da6ebab4;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h02749b04a3071a46;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h975c9c2ee3c530c7;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h02749b04a3071a46;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h149e0729fea7a6fd;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h02749b04a3071a46;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h9eb7c63ded3408da;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h02749b04a3071a46;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h5d7199bab9f50473;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h02749b04a3071a46;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h8d24f61a6a8e05d5;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h8d24f61a6a8e05d5;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h603921c04b273796;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h8d24f61a6a8e05d5;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h6e5f0fdc3e99837d;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h8d24f61a6a8e05d5;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hed8d80db3f5a9b7e;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hed8d80db3f5a9b7e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hb0bcee61fd28e4fa;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hb0bcee61fd28e4fa;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'ha863965043779186;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'ha863965043779186;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h60b175c1949a8a29;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'ha863965043779186;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hb98c427325b27b4b;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'ha863965043779186;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hd44b80a82758d14e;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h60b175c1949a8a29;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hf33466e6070bb90e;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h60b175c1949a8a29;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hc6b5f48d155a1d2a;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h60b175c1949a8a29;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h6464e3c8bccfa879;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hd44b80a82758d14e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'he3b7aec735a0c96b;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd44b80a82758d14e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h5c8295b96216abc4;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd44b80a82758d14e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hc33390863fbb3b7f;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd44b80a82758d14e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hdece5ebd19452132;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd44b80a82758d14e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h54a879a96543cfca;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd44b80a82758d14e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h85e51e0bfd8b6afb;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hf33466e6070bb90e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hbab148751b60e536;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h54a879a96543cfca;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hd73fb4ae4465e788;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h54a879a96543cfca;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'h9684e02d1444df28;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h54a879a96543cfca;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'h06b3050d8f1cf61e;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h54a879a96543cfca;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b1;
data_in = 64'hc3761c8668ae1bd1;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h85e51e0bfd8b6afb;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h29efe9536c44f9d8;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hbab148751b60e536;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h8273e204f166fae2;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hbab148751b60e536;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hdc0344b8093e4d12;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hd73fb4ae4465e788;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h15890f2bd0c5dca1;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd73fb4ae4465e788;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'h50d5f9a113b55527;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd73fb4ae4465e788;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'hcb5c80962c2d2358;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd73fb4ae4465e788;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b1;
data_in = 64'hd8ace2b1cb227096;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h8273e204f166fae2;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h7ab11bf5158b2b2b;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hdc0344b8093e4d12;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hd3a8e4a74249ff84;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h15890f2bd0c5dca1;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h6de5bbdba4da5649;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h7ab11bf5158b2b2b;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h1546dd2ad0bc5ea1;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hd3a8e4a74249ff84;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hbe75427c41a10583;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd3a8e4a74249ff84;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hb7dfaa6fb455f268;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd3a8e4a74249ff84;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h207691401c719738;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hd3a8e4a74249ff84;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h602831c0e2bf1ac5;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h6de5bbdba4da5649;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h1e1c873cd86a6ab0;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h6de5bbdba4da5649;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hf0b14ee10aec3515;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hf0b14ee10aec3515;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hc336048664b5e3c9;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hc336048664b5e3c9;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'had67e25ac69da28d;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hc336048664b5e3c9;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hb8ade671060a5d0c;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hc336048664b5e3c9;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hcf14ce9efbdfc2f7;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'had67e25ac69da28d;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hd00b12a0902a3a20;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'had67e25ac69da28d;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h86dcf00d6e8af5dd;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hb8ade671060a5d0c;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hfef064fdcf63da9e;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h86dcf00d6e8af5dd;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h71c129e381c39a03;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hfef064fdcf63da9e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hca9cbc9522119f44;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h71c129e381c39a03;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h7c1e5bf8297a1552;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h71c129e381c39a03;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h236afd464219e784;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h71c129e381c39a03;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h352d616a0beac117;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h71c129e381c39a03;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hb05202603e6f0f7c;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h7c1e5bf8297a1552;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h92831e25d31dfea6;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h7c1e5bf8297a1552;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h8a64b014a48f7c49;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h8a64b014a48f7c49;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h23907547ae68305c;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h6851e5d0da058ab4;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hb522406a03e9b707;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hb522406a03e9b707;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h39e48173a5e79e4b;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h64e165c9520eefa4;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h64e165c9520eefa4;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h33836567ea5814d4;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h64e165c9520eefa4;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h24d2bf4941103982;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h64e165c9520eefa4;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h49b16f938e054c1c;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h64e165c9520eefa4;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'haed72e5de471f8c8;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h64e165c9520eefa4;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b0;
data_in = 64'h1c8d7f3995a9a82b;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h64e165c9520eefa4;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b1;
data_in = 64'he82b96d02c848959;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h33836567ea5814d4;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h535277a66d8b87db;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h33836567ea5814d4;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b1;
data_in = 64'hb4e8d66987e44c0f;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h24d2bf4941103982;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h67d735cf62fd49c5;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h49b16f938e054c1c;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h3b83cd77b4f9a469;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h49b16f938e054c1c;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'he20e9ac44ddd4d9b;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h535277a66d8b87db;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h984d5a30c378ee86;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h984d5a30c378ee86;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h038787076a15f5d4;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h00f25f0145e28b8b;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h00f25f0145e28b8b;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'he2ecdac5611d9fc2;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h57fbb9afb302da66;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h57fbb9afb302da66;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hf78576ef8376ac06;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hf78576ef8376ac06;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h304e4d60f7723eee;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'hf78576ef8376ac06;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h14b43729322f7d64;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h304e4d60f7723eee;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h40aaf5813715156e;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h304e4d60f7723eee;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hd57800aa786271f0;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h14b43729322f7d64;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h472e958ebe9bbc7d;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h14b43729322f7d64;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h77ebb1efd4b5e6a9;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h40aaf5813715156e;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h5cd20db925029b4a;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hd57800aa786271f0;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h28c6275132dc4165;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h77ebb1efd4b5e6a9;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hb8ea3a719d12083a;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h77ebb1efd4b5e6a9;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hbeda447d1513dd2a;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h5cd20db925029b4a;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'he4a800c976de6bed;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h28c6275132dc4165;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'he696e8cdeda71cdb;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h28c6275132dc4165;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h5e983dbdd14820a2;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h28c6275132dc4165;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'hbd86f47ba86c5e50;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h28c6275132dc4165;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b1;
data_out_valid_gold = 1'b1;
data_in = 64'hae23ce5c7b7b89f6;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hbeda447d1513dd2a;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hddd146bb644605c8;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'he4a800c976de6bed;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'he70f98ce0671030c;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'hbd86f47ba86c5e50;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'hd9b8c0b35ca26fb9;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h9cfc7a39066cf10c;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h271c434e02fbf905;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h46e7538d847fb208;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h46e7538d847fb208;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h7af6abf548590990;
data_in_valid = 1'b0;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h0000000000000000;
fifo_empty_gold = 1'b1;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h12a90325a005a640;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h12a90325a005a640;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h94ded82916cbf92d;
data_in_valid = 1'b0;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h12a90325a005a640;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b1;
data_in = 64'h2876695060272dc0;
data_in_valid = 1'b1;
pop_fifo = 1'b1;
@(posedge clk);
data_out_gold = 64'h2876695060272dc0;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
data_in = 64'h7a87aff5faf32ef5;
data_in_valid = 1'b1;
pop_fifo = 1'b0;
@(posedge clk);
data_out_gold = 64'h2876695060272dc0;
fifo_empty_gold = 1'b0;
fifo_full_gold = 1'b0;
data_out_valid_gold = 1'b0;
if (fail)
$display("TEST FAILED");
else if (partial_fail)
$display("TEST FAILED WITH MINOR ERRORS");
else
$display("TEST PASSED");
$finish;
end
always @ (posedge clk)
begin
$display("\nCycle: %4d data_in: %x, data_in_valid: %b, pop_fifo: %b", cycle_count, data_in, data_in_valid, pop_fifo);
# 10;
if (data_out_valid_gold == 1'b1) begin
$display(" data_out: %x, Expected data_out: %x, fifo_empty: %b, Expected fifo_empty: %b, fifo_full: %b, Expected fifo_full: %b",
data_out, data_out_gold, fifo_empty, fifo_empty_gold, fifo_full, fifo_full_gold);
end
else begin
$display(" (data_out NOT CHECKED in this cycle) fifo_empty: %b, Expected fifo_empty: %b, fifo_full: %b, Expected fifo_full: %b",
fifo_empty, fifo_empty_gold, fifo_full, fifo_full_gold);
end
if (fifo_full !== fifo_full_gold) begin
$display("MINORCHECK : In cycle %4d - FULL logic : full = %d, expected full = %d", cycle_count, fifo_full, fifo_full_gold);
partial_fail = 1;
end
if (fifo_empty !== fifo_empty_gold) begin
$display("MINORCHECK : In cycle %4d - EMPTY logic : empty = %d, expected empty = %d", cycle_count, fifo_empty, fifo_empty_gold);
partial_fail = 1;
end
if (data_out !== data_out_gold && data_out_valid_gold === 1'b1)
begin
fail = 1;
err = 1'b1;
$display("ERRORCHECK : In cycle %4d - Data out error. data_out = %x, expcted data_out = %x", cycle_count, data_out, data_out_gold);
end
else
err = 1'b0;
cycle_count = cycle_count + 1;
end
endmodule | 0 |
139,493 | data/full_repos/permissive/87881270/hw4/hw4_1/fifo_hier.v | 87,881,270 | fifo_hier.v | v | 44 | 71 | [] | [] | [] | [(7, 42)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_hier.v:22: Cannot find file containing module: 'clkrst'\n clkrst clk_generator(.clk(clk),\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/87881270/hw4/hw4_1,data/full_repos/permissive/87881270/clkrst\n data/full_repos/permissive/87881270/hw4/hw4_1,data/full_repos/permissive/87881270/clkrst.v\n data/full_repos/permissive/87881270/hw4/hw4_1,data/full_repos/permissive/87881270/clkrst.sv\n clkrst\n clkrst.v\n clkrst.sv\n obj_dir/clkrst\n obj_dir/clkrst.v\n obj_dir/clkrst.sv\n%Error: data/full_repos/permissive/87881270/hw4/hw4_1/fifo_hier.v:26: Cannot find file containing module: 'fifo'\n fifo fifo0( \n ^~~~\n%Error: Exiting due to 2 error(s)\n" | 304,992 | module | module fifo_hier(
data_out, fifo_empty, fifo_full,
data_in, data_in_valid, pop_fifo
);
input [63:0] data_in;
input data_in_valid;
input pop_fifo;
output [63:0] data_out;
output fifo_empty;
output fifo_full;
clkrst clk_generator(.clk(clk),
.rst(rst),
.err(err) );
fifo fifo0(
.data_out (data_out[63:0]),
.fifo_empty (fifo_empty),
.fifo_full (fifo_full),
.err (err),
.data_in (data_in[63:0]),
.data_in_valid (data_in_valid),
.pop_fifo (pop_fifo),
.clk (clk),
.rst (rst));
endmodule | module fifo_hier(
data_out, fifo_empty, fifo_full,
data_in, data_in_valid, pop_fifo
); |
input [63:0] data_in;
input data_in_valid;
input pop_fifo;
output [63:0] data_out;
output fifo_empty;
output fifo_full;
clkrst clk_generator(.clk(clk),
.rst(rst),
.err(err) );
fifo fifo0(
.data_out (data_out[63:0]),
.fifo_empty (fifo_empty),
.fifo_full (fifo_full),
.err (err),
.data_in (data_in[63:0]),
.data_in_valid (data_in_valid),
.pop_fifo (pop_fifo),
.clk (clk),
.rst (rst));
endmodule | 0 |
139,494 | data/full_repos/permissive/87881270/project/project/cache_assoc/verilog/mem_system.v | 87,881,270 | mem_system.v | v | 428 | 174 | [] | [] | [] | [(5, 425)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/project/project/cache_assoc/verilog/mem_system.v:28: Cannot find file containing module: 'dff'\n dff curr_State[3:0] (.q(currState), .d(nextState), .clk(clk), .rst(rst));\n ^~~\n ... Looked in:\n data/full_repos/permissive/87881270/project/project/cache_assoc/verilog,data/full_repos/permissive/87881270/dff\n data/full_repos/permissive/87881270/project/project/cache_assoc/verilog,data/full_repos/permissive/87881270/dff.v\n data/full_repos/permissive/87881270/project/project/cache_assoc/verilog,data/full_repos/permissive/87881270/dff.sv\n dff\n dff.v\n dff.sv\n obj_dir/dff\n obj_dir/dff.v\n obj_dir/dff.sv\n%Error: data/full_repos/permissive/87881270/project/project/cache_assoc/verilog/mem_system.v:44: Cannot find file containing module: 'dff'\n dff hitdff(.clk(clk), .rst(rst), .q(cacheHitTemp), .d(cacheHit));\n ^~~\n%Error: data/full_repos/permissive/87881270/project/project/cache_assoc/verilog/mem_system.v:52: Cannot find file containing module: 'cache'\n cache #(0 + mem_type) c0( \n ^~~~~\n%Error: data/full_repos/permissive/87881270/project/project/cache_assoc/verilog/mem_system.v:72: Cannot find file containing module: 'cache'\n cache #(2 + mem_type) c1( \n ^~~~~\n%Error: data/full_repos/permissive/87881270/project/project/cache_assoc/verilog/mem_system.v:92: Cannot find file containing module: 'four_bank_mem'\n four_bank_mem mem( \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/87881270/project/project/cache_assoc/verilog/mem_system.v:107: Cannot find file containing module: 'dff'\n dff victimway(.q(victimOut), .d(victimIn), .clk(clk), .rst(rst));\n ^~~\n%Error: Exiting due to 6 error(s)\n" | 305,002 | module | module mem_system(
DataOut, Done, Stall, CacheHit, err,
Addr, DataIn, Rd, Wr, createdump, clk, rst
);
input [15:0] Addr;
input [15:0] DataIn;
input Rd;
input Wr;
input createdump;
input clk;
input rst;
output reg [15:0] DataOut;
output reg Done;
output reg Stall;
output CacheHit;
output err;
reg [3:0] nextState;
wire [3:0] currState;
dff curr_State[3:0] (.q(currState), .d(nextState), .clk(clk), .rst(rst));
wire dirty1, dirty0, valid1, valid0, hit1, hit0, miss, mem_stall, cacheErr1, cacheErr0, memErr, cacheHit, cacheHitTemp;
reg comp, cache_write0, cache_write1, mem_wr, mem_rd, enable0, enable1, valid_in, controlErr, retry, victim;
wire[15:0] cache_data_out1, mem_data_out, cache_data_out0;
wire[4:0] tag_out1, tag_out0;
wire[3:0] busy;
reg [15:0] cache_data_in, mem_addr, mem_data_in;
reg [7:0] index;
reg [4:0] tag_in;
reg [2:0] offset;
assign miss = (enable0 & (~hit0 | ~valid0)) & (enable1 & (~hit1 | ~valid1));
assign err = controlErr;
assign cacheHit = (hit1 | hit0) & comp & ~retry;
assign CacheHit = cacheHitTemp;
dff hitdff(.clk(clk), .rst(rst), .q(cacheHitTemp), .d(cacheHit));
wire victimIn;
wire victimOut;
parameter mem_type = 0;
cache #(0 + mem_type) c0(
.tag_out (tag_out0),
.data_out (cache_data_out0),
.hit (hit0),
.dirty (dirty0),
.valid (valid0),
.err (cacheErr0),
.enable (enable0),
.clk (clk),
.rst (rst),
.createdump (createdump),
.tag_in (tag_in),
.index (index),
.offset (offset),
.data_in (cache_data_in),
.comp (comp),
.write (cache_write0),
.valid_in (valid_in));
cache #(2 + mem_type) c1(
.tag_out (tag_out1),
.data_out (cache_data_out1),
.hit (hit1),
.dirty (dirty1),
.valid (valid1),
.err (cacheErr1),
.enable (enable1),
.clk (clk),
.rst (rst),
.createdump (createdump),
.tag_in (tag_in),
.index (index),
.offset (offset),
.data_in (cache_data_in),
.comp (comp),
.write (cache_write1),
.valid_in (valid_in));
four_bank_mem mem(
.data_out (mem_data_out),
.stall (mem_stall),
.busy (busy),
.err (memErr),
.clk (clk),
.rst (rst),
.createdump (createdump),
.addr (mem_addr),
.data_in (mem_data_in),
.wr (mem_wr),
.rd (mem_rd));
assign victimIn = (Wr | Rd) ? ~victimOut : victimOut;
dff victimway(.q(victimOut), .d(victimIn), .clk(clk), .rst(rst));
always@(*)begin case(currState)
4'h0: begin
retry = 0;
enable0 = (~Wr & ~Rd) ? 0 : 1;
enable1 = (~Wr & ~Rd) ? 0 : 1;
comp = (~Wr & ~Rd) ? 0 : 1;
index = (~Wr & ~Rd) ? 0 : Addr[10:3];
tag_in = (~Wr & ~Rd) ? 0 : Addr[15:11];
offset = (~Wr & ~Rd) ? 0 : {Addr[2:1], 1'b0};
cache_data_in = Wr ? DataIn : 0;
valid_in = 0;
mem_addr = 0;
mem_data_in = 0;
mem_wr = 0;
mem_rd = 0;
DataOut = Rd ? (((hit0 & valid0) | (hit1 & valid1) ) ? (hit0 ? cache_data_out0 : cache_data_out1) : 0) : 0;
Done = (((hit0 & valid0) | (hit1 & valid1)) & (Wr | Rd)) ? 1 : 0;
Stall = (~Wr & ~Rd) ? 0 : (((hit0 & valid0) | (hit1 & valid1)) ? 0 : 1);
victim = (valid0 & ~valid1) ? 1 : ((~valid0 & valid1) ? 0 : ((~valid0 & ~valid1) ? 0 : (victimOut ? 1 : 0)));
cache_write0 = (Wr & (hit0 & valid0)) ? 1 : 0;
cache_write1 = (Wr & (hit1 & valid1)) ? 1 : 0;
nextState = (~Wr & ~Rd) ? 0 : ((miss & (victim ? ~dirty1 : ~dirty0)) ? 4'h2 : ((miss & (victim ? (valid1 & dirty1) : (valid0 & dirty0)) ? 4'h8 : 4'h0)));
end
4'h1: begin
retry = 1;
enable0 = ~victim ? 1 : 0;
enable1 = victim ? 1 : 0;
comp = 1;
cache_write0 = (Wr & ~victim) ? 1 : 0;
cache_write1 = (Wr & victim) ? 1 : 0;
index = (~Wr & ~Rd) ? 0 : Addr[10:3];
tag_in = (~Wr & ~Rd) ? 0 : Addr[15:11];
offset = (~Wr & ~Rd) ? 0 : {Addr[2:1], 1'b0};
cache_data_in = Wr ? DataIn : 0;
valid_in = 0;
mem_addr = 0;
mem_data_in = 0;
mem_wr = 0;
mem_rd = 0;
DataOut = Rd ? (~victim ? cache_data_out0 : cache_data_out1) : 0;
Done = 0;
Stall = 1;
nextState = 4'h0;
end
4'h2: begin
retry = 0;
enable0 = 0;
enable1 = 0;
comp = 0;
cache_write0 = 0;
cache_write1 = 0;
index = 0;
tag_in = 0;
offset = 0;
cache_data_in = 0;
valid_in = 0;
mem_addr = {Addr[15:3], 3'b000};
mem_data_in = 0;
mem_wr = 0;
mem_rd = 1;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = 4'h3;
end
4'h3: begin
retry = 0;
enable0 = 0;
enable1 = 0;
comp = 0;
cache_write0 = 0;
cache_write1 = 0;
index = 0;
tag_in = 0;
offset = 0;
cache_data_in = 0;
valid_in = 0;
mem_addr = {Addr[15:3], 3'b010};
mem_data_in = 0;
mem_wr = 0;
mem_rd = 1;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'h3 : 4'h4;
end
4'h4: begin
retry = 0;
enable0 = ~victim ? 1 : 0;
enable1 = victim ? 1 : 0;
comp = 0;
cache_write0 = ~victim ? 1 : 0;
cache_write1 = victim ? 1 : 0;
index = Addr[10:3];
tag_in = Addr[15:11];
offset = 3'b000;
cache_data_in = mem_data_out;
valid_in = 0;
mem_addr = {Addr[15:3], 3'b100};
mem_data_in = 0;
mem_wr = 0;
mem_rd = 1;
DataOut = (Rd & (offset == {Addr[2:1], 1'b0})) ? mem_data_out : 0;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'h4 : 4'h5;
end
4'h5: begin
retry = 0;
enable0 = ~victim ? 1 : 0;
enable1 = victim ? 1 : 0;
comp = 0;
cache_write0 = ~victim ? 1 : 0;
cache_write1 = victim ? 1 : 0;
index = Addr[10:3];
tag_in = Addr[15:11];
offset = 3'b010;
cache_data_in = mem_data_out;
valid_in = 0;
mem_addr = {Addr[15:3], 3'b110};
mem_data_in = 0;
mem_wr = 0;
mem_rd = 1;
DataOut = (Rd & (offset == {Addr[2:1], 1'b0})) ? mem_data_out : DataOut;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'h5 : 4'h6;
end
4'h6: begin
retry = 0;
enable0 = ~victim ? 1 : 0;
enable1 = victim ? 1 : 0;
comp = 0;
cache_write0 = ~victim ? 1 : 0;
cache_write1 = victim ? 1 : 0;
index = Addr[10:3];
tag_in = Addr[15:11];
offset = 3'b100;
cache_data_in = mem_data_out;
valid_in = 0;
mem_addr = 0;
mem_data_in = 0;
mem_wr = 0;
mem_rd = 0;
DataOut = (Rd & (offset == {Addr[2:1], 1'b0})) ? mem_data_out : DataOut;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'h6 : 4'h7;
end
4'h7: begin
retry = 0;
enable0 = ~victim ? 1 : 0;
enable1 = victim ? 1 : 0;
comp = 0;
cache_write0 = ~victim ? 1 : 0;
cache_write1 = victim ? 1 : 0;
index = Addr[10:3];
tag_in = Addr[15:11];
offset = 3'b110;
cache_data_in = mem_data_out;
valid_in = 1;
mem_addr = 0;
mem_data_in = 0;
mem_wr = 0;
mem_rd = 0;
DataOut = (Rd & (offset == {Addr[2:1], 1'b0})) ? mem_data_out : DataOut;
Done = 0;
Stall = 1;
nextState = 4'h1;
end
4'h8: begin
retry = 0;
enable0 = ~victim ? 1 : 0;
enable1 = victim ? 1 : 0;
comp = 0;
cache_write0 = 0;
cache_write1 = 0;
index = Addr[10:3];
tag_in = 0;
offset = 3'b000;
cache_data_in = 0;
valid_in = 0;
mem_addr = {(~victim ? tag_out0 : tag_out1), Addr[10:3], 3'b000};
mem_data_in = ~victim ? cache_data_out0 : cache_data_out1;
mem_wr = 1;
mem_rd = 0;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = 4'h9;
end
4'h9: begin
retry = 0;
enable0 = ~victim ? 1 : 0;
enable1 = victim ? 1 : 0;
comp = 0;
cache_write0 = 0;
cache_write1 = 0;
index = Addr[10:3];
tag_in = 0;
offset = 3'b010;
cache_data_in = 0;
valid_in = 0;
mem_addr = {(~victim ? tag_out0 : tag_out1), Addr[10:3], 3'b010};
mem_data_in = ~victim ? cache_data_out0 : cache_data_out1;
mem_wr = 1;
mem_rd = 0;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'h9 : 4'hA;
end
4'hA: begin
retry = 0;
enable0 = ~victim ? 1 : 0;
enable1 = victim ? 1 : 0;
comp = 0;
cache_write0 = 0;
cache_write1 = 0;
index = Addr[10:3];
tag_in = 0;
offset = 3'b100;
cache_data_in = 0;
valid_in = 0;
mem_addr = {(~victim ? tag_out0 : tag_out1), Addr[10:3], 3'b100};
mem_data_in = ~victim ? cache_data_out0 : cache_data_out1;
mem_wr = 1;
mem_rd = 0;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'hA : 4'hB;
end
4'hB: begin
retry = 0;
enable0 = ~victim ? 1 : 0;
enable1 = victim ? 1 : 0;
comp = 0;
cache_write0 = 0;
cache_write1 = 0;
index = Addr[10:3];
tag_in = 0;
offset = 3'b110;
cache_data_in = 0;
valid_in = 0;
mem_addr = {(~victim ? tag_out0 : tag_out1), Addr[10:3], 3'b110};
mem_data_in = ~victim ? cache_data_out0 : cache_data_out1;
mem_wr = 1;
mem_rd = 0;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'hB : 4'h2;
end
4'hC: begin
Done = 1;
Stall = 0;
controlErr = 1;
nextState = 4'h0;
end
default: begin
retry = 0;
enable0 = 1;
enable1 = 1;
comp = 1;
index = (~Wr & ~Rd) ? 0 : Addr[10:3];
tag_in = (~Wr & ~Rd) ? 0 : Addr[15:11];
offset = (~Wr & ~Rd) ? 0 : {Addr[2:1], 1'b0};
cache_data_in = Wr ? DataIn : 0;
valid_in = 0;
mem_addr = 0;
mem_data_in = 0;
mem_wr = 0;
mem_rd = 0;
DataOut = Rd ? (((hit0 & valid0) | (hit1 & valid1) ) ? (hit0 ? cache_data_out0 : cache_data_out1) : 0) : 0;
Done = ((hit0 & valid0) | (hit1 & valid1)) ? 1 : 0;
Stall = (~Wr & ~Rd) ? 0 : (((hit0 & valid0) | (hit1 & valid1)) ? 0 : 1);
victim = ((~Wr & ~Rd) | ((hit0 & valid0) | (hit1 & valid1))) ? 0 : ((valid0 & ~valid1) ? 1 : ((~valid0 & valid1) ? 0 : ((~valid0 & ~valid1) ? 0 : (victimOut ? 1 : 0))));
cache_write0 = (Wr & (hit0 & valid0 & ~victim)) ? 1 : 0;
cache_write1 = (Wr & (hit1 & valid1 & victim)) ? 1 : 0;
nextState = (~Wr & ~Rd) ? 0 : ((miss & (victim ? ~dirty1 : ~dirty0)) ? 4'h2 : ((miss & (victim ? (valid1 & dirty1) : (valid0 & dirty0)) ? 4'h8 : 4'h0)));
end
endcase
end
endmodule | module mem_system(
DataOut, Done, Stall, CacheHit, err,
Addr, DataIn, Rd, Wr, createdump, clk, rst
); |
input [15:0] Addr;
input [15:0] DataIn;
input Rd;
input Wr;
input createdump;
input clk;
input rst;
output reg [15:0] DataOut;
output reg Done;
output reg Stall;
output CacheHit;
output err;
reg [3:0] nextState;
wire [3:0] currState;
dff curr_State[3:0] (.q(currState), .d(nextState), .clk(clk), .rst(rst));
wire dirty1, dirty0, valid1, valid0, hit1, hit0, miss, mem_stall, cacheErr1, cacheErr0, memErr, cacheHit, cacheHitTemp;
reg comp, cache_write0, cache_write1, mem_wr, mem_rd, enable0, enable1, valid_in, controlErr, retry, victim;
wire[15:0] cache_data_out1, mem_data_out, cache_data_out0;
wire[4:0] tag_out1, tag_out0;
wire[3:0] busy;
reg [15:0] cache_data_in, mem_addr, mem_data_in;
reg [7:0] index;
reg [4:0] tag_in;
reg [2:0] offset;
assign miss = (enable0 & (~hit0 | ~valid0)) & (enable1 & (~hit1 | ~valid1));
assign err = controlErr;
assign cacheHit = (hit1 | hit0) & comp & ~retry;
assign CacheHit = cacheHitTemp;
dff hitdff(.clk(clk), .rst(rst), .q(cacheHitTemp), .d(cacheHit));
wire victimIn;
wire victimOut;
parameter mem_type = 0;
cache #(0 + mem_type) c0(
.tag_out (tag_out0),
.data_out (cache_data_out0),
.hit (hit0),
.dirty (dirty0),
.valid (valid0),
.err (cacheErr0),
.enable (enable0),
.clk (clk),
.rst (rst),
.createdump (createdump),
.tag_in (tag_in),
.index (index),
.offset (offset),
.data_in (cache_data_in),
.comp (comp),
.write (cache_write0),
.valid_in (valid_in));
cache #(2 + mem_type) c1(
.tag_out (tag_out1),
.data_out (cache_data_out1),
.hit (hit1),
.dirty (dirty1),
.valid (valid1),
.err (cacheErr1),
.enable (enable1),
.clk (clk),
.rst (rst),
.createdump (createdump),
.tag_in (tag_in),
.index (index),
.offset (offset),
.data_in (cache_data_in),
.comp (comp),
.write (cache_write1),
.valid_in (valid_in));
four_bank_mem mem(
.data_out (mem_data_out),
.stall (mem_stall),
.busy (busy),
.err (memErr),
.clk (clk),
.rst (rst),
.createdump (createdump),
.addr (mem_addr),
.data_in (mem_data_in),
.wr (mem_wr),
.rd (mem_rd));
assign victimIn = (Wr | Rd) ? ~victimOut : victimOut;
dff victimway(.q(victimOut), .d(victimIn), .clk(clk), .rst(rst));
always@(*)begin case(currState)
4'h0: begin
retry = 0;
enable0 = (~Wr & ~Rd) ? 0 : 1;
enable1 = (~Wr & ~Rd) ? 0 : 1;
comp = (~Wr & ~Rd) ? 0 : 1;
index = (~Wr & ~Rd) ? 0 : Addr[10:3];
tag_in = (~Wr & ~Rd) ? 0 : Addr[15:11];
offset = (~Wr & ~Rd) ? 0 : {Addr[2:1], 1'b0};
cache_data_in = Wr ? DataIn : 0;
valid_in = 0;
mem_addr = 0;
mem_data_in = 0;
mem_wr = 0;
mem_rd = 0;
DataOut = Rd ? (((hit0 & valid0) | (hit1 & valid1) ) ? (hit0 ? cache_data_out0 : cache_data_out1) : 0) : 0;
Done = (((hit0 & valid0) | (hit1 & valid1)) & (Wr | Rd)) ? 1 : 0;
Stall = (~Wr & ~Rd) ? 0 : (((hit0 & valid0) | (hit1 & valid1)) ? 0 : 1);
victim = (valid0 & ~valid1) ? 1 : ((~valid0 & valid1) ? 0 : ((~valid0 & ~valid1) ? 0 : (victimOut ? 1 : 0)));
cache_write0 = (Wr & (hit0 & valid0)) ? 1 : 0;
cache_write1 = (Wr & (hit1 & valid1)) ? 1 : 0;
nextState = (~Wr & ~Rd) ? 0 : ((miss & (victim ? ~dirty1 : ~dirty0)) ? 4'h2 : ((miss & (victim ? (valid1 & dirty1) : (valid0 & dirty0)) ? 4'h8 : 4'h0)));
end
4'h1: begin
retry = 1;
enable0 = ~victim ? 1 : 0;
enable1 = victim ? 1 : 0;
comp = 1;
cache_write0 = (Wr & ~victim) ? 1 : 0;
cache_write1 = (Wr & victim) ? 1 : 0;
index = (~Wr & ~Rd) ? 0 : Addr[10:3];
tag_in = (~Wr & ~Rd) ? 0 : Addr[15:11];
offset = (~Wr & ~Rd) ? 0 : {Addr[2:1], 1'b0};
cache_data_in = Wr ? DataIn : 0;
valid_in = 0;
mem_addr = 0;
mem_data_in = 0;
mem_wr = 0;
mem_rd = 0;
DataOut = Rd ? (~victim ? cache_data_out0 : cache_data_out1) : 0;
Done = 0;
Stall = 1;
nextState = 4'h0;
end
4'h2: begin
retry = 0;
enable0 = 0;
enable1 = 0;
comp = 0;
cache_write0 = 0;
cache_write1 = 0;
index = 0;
tag_in = 0;
offset = 0;
cache_data_in = 0;
valid_in = 0;
mem_addr = {Addr[15:3], 3'b000};
mem_data_in = 0;
mem_wr = 0;
mem_rd = 1;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = 4'h3;
end
4'h3: begin
retry = 0;
enable0 = 0;
enable1 = 0;
comp = 0;
cache_write0 = 0;
cache_write1 = 0;
index = 0;
tag_in = 0;
offset = 0;
cache_data_in = 0;
valid_in = 0;
mem_addr = {Addr[15:3], 3'b010};
mem_data_in = 0;
mem_wr = 0;
mem_rd = 1;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'h3 : 4'h4;
end
4'h4: begin
retry = 0;
enable0 = ~victim ? 1 : 0;
enable1 = victim ? 1 : 0;
comp = 0;
cache_write0 = ~victim ? 1 : 0;
cache_write1 = victim ? 1 : 0;
index = Addr[10:3];
tag_in = Addr[15:11];
offset = 3'b000;
cache_data_in = mem_data_out;
valid_in = 0;
mem_addr = {Addr[15:3], 3'b100};
mem_data_in = 0;
mem_wr = 0;
mem_rd = 1;
DataOut = (Rd & (offset == {Addr[2:1], 1'b0})) ? mem_data_out : 0;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'h4 : 4'h5;
end
4'h5: begin
retry = 0;
enable0 = ~victim ? 1 : 0;
enable1 = victim ? 1 : 0;
comp = 0;
cache_write0 = ~victim ? 1 : 0;
cache_write1 = victim ? 1 : 0;
index = Addr[10:3];
tag_in = Addr[15:11];
offset = 3'b010;
cache_data_in = mem_data_out;
valid_in = 0;
mem_addr = {Addr[15:3], 3'b110};
mem_data_in = 0;
mem_wr = 0;
mem_rd = 1;
DataOut = (Rd & (offset == {Addr[2:1], 1'b0})) ? mem_data_out : DataOut;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'h5 : 4'h6;
end
4'h6: begin
retry = 0;
enable0 = ~victim ? 1 : 0;
enable1 = victim ? 1 : 0;
comp = 0;
cache_write0 = ~victim ? 1 : 0;
cache_write1 = victim ? 1 : 0;
index = Addr[10:3];
tag_in = Addr[15:11];
offset = 3'b100;
cache_data_in = mem_data_out;
valid_in = 0;
mem_addr = 0;
mem_data_in = 0;
mem_wr = 0;
mem_rd = 0;
DataOut = (Rd & (offset == {Addr[2:1], 1'b0})) ? mem_data_out : DataOut;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'h6 : 4'h7;
end
4'h7: begin
retry = 0;
enable0 = ~victim ? 1 : 0;
enable1 = victim ? 1 : 0;
comp = 0;
cache_write0 = ~victim ? 1 : 0;
cache_write1 = victim ? 1 : 0;
index = Addr[10:3];
tag_in = Addr[15:11];
offset = 3'b110;
cache_data_in = mem_data_out;
valid_in = 1;
mem_addr = 0;
mem_data_in = 0;
mem_wr = 0;
mem_rd = 0;
DataOut = (Rd & (offset == {Addr[2:1], 1'b0})) ? mem_data_out : DataOut;
Done = 0;
Stall = 1;
nextState = 4'h1;
end
4'h8: begin
retry = 0;
enable0 = ~victim ? 1 : 0;
enable1 = victim ? 1 : 0;
comp = 0;
cache_write0 = 0;
cache_write1 = 0;
index = Addr[10:3];
tag_in = 0;
offset = 3'b000;
cache_data_in = 0;
valid_in = 0;
mem_addr = {(~victim ? tag_out0 : tag_out1), Addr[10:3], 3'b000};
mem_data_in = ~victim ? cache_data_out0 : cache_data_out1;
mem_wr = 1;
mem_rd = 0;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = 4'h9;
end
4'h9: begin
retry = 0;
enable0 = ~victim ? 1 : 0;
enable1 = victim ? 1 : 0;
comp = 0;
cache_write0 = 0;
cache_write1 = 0;
index = Addr[10:3];
tag_in = 0;
offset = 3'b010;
cache_data_in = 0;
valid_in = 0;
mem_addr = {(~victim ? tag_out0 : tag_out1), Addr[10:3], 3'b010};
mem_data_in = ~victim ? cache_data_out0 : cache_data_out1;
mem_wr = 1;
mem_rd = 0;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'h9 : 4'hA;
end
4'hA: begin
retry = 0;
enable0 = ~victim ? 1 : 0;
enable1 = victim ? 1 : 0;
comp = 0;
cache_write0 = 0;
cache_write1 = 0;
index = Addr[10:3];
tag_in = 0;
offset = 3'b100;
cache_data_in = 0;
valid_in = 0;
mem_addr = {(~victim ? tag_out0 : tag_out1), Addr[10:3], 3'b100};
mem_data_in = ~victim ? cache_data_out0 : cache_data_out1;
mem_wr = 1;
mem_rd = 0;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'hA : 4'hB;
end
4'hB: begin
retry = 0;
enable0 = ~victim ? 1 : 0;
enable1 = victim ? 1 : 0;
comp = 0;
cache_write0 = 0;
cache_write1 = 0;
index = Addr[10:3];
tag_in = 0;
offset = 3'b110;
cache_data_in = 0;
valid_in = 0;
mem_addr = {(~victim ? tag_out0 : tag_out1), Addr[10:3], 3'b110};
mem_data_in = ~victim ? cache_data_out0 : cache_data_out1;
mem_wr = 1;
mem_rd = 0;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'hB : 4'h2;
end
4'hC: begin
Done = 1;
Stall = 0;
controlErr = 1;
nextState = 4'h0;
end
default: begin
retry = 0;
enable0 = 1;
enable1 = 1;
comp = 1;
index = (~Wr & ~Rd) ? 0 : Addr[10:3];
tag_in = (~Wr & ~Rd) ? 0 : Addr[15:11];
offset = (~Wr & ~Rd) ? 0 : {Addr[2:1], 1'b0};
cache_data_in = Wr ? DataIn : 0;
valid_in = 0;
mem_addr = 0;
mem_data_in = 0;
mem_wr = 0;
mem_rd = 0;
DataOut = Rd ? (((hit0 & valid0) | (hit1 & valid1) ) ? (hit0 ? cache_data_out0 : cache_data_out1) : 0) : 0;
Done = ((hit0 & valid0) | (hit1 & valid1)) ? 1 : 0;
Stall = (~Wr & ~Rd) ? 0 : (((hit0 & valid0) | (hit1 & valid1)) ? 0 : 1);
victim = ((~Wr & ~Rd) | ((hit0 & valid0) | (hit1 & valid1))) ? 0 : ((valid0 & ~valid1) ? 1 : ((~valid0 & valid1) ? 0 : ((~valid0 & ~valid1) ? 0 : (victimOut ? 1 : 0))));
cache_write0 = (Wr & (hit0 & valid0 & ~victim)) ? 1 : 0;
cache_write1 = (Wr & (hit1 & valid1 & victim)) ? 1 : 0;
nextState = (~Wr & ~Rd) ? 0 : ((miss & (victim ? ~dirty1 : ~dirty0)) ? 4'h2 : ((miss & (victim ? (valid1 & dirty1) : (valid0 & dirty0)) ? 4'h8 : 4'h0)));
end
endcase
end
endmodule | 0 |
139,495 | data/full_repos/permissive/87881270/project/project/cache_assoc/verilog/mem_system_randbench.v | 87,881,270 | mem_system_randbench.v | v | 338 | 163 | [] | [] | [] | null | line:134: before: ";" | null | 1: b'%Error: data/full_repos/permissive/87881270/project/project/cache_assoc/verilog/mem_system_randbench.v:50: syntax error, unexpected ref, expecting IDENTIFIER\n mem_system_ref ref(\n ^~~\n%Warning-STMTDLY: data/full_repos/permissive/87881270/project/project/cache_assoc/verilog/mem_system_randbench.v:87: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/87881270/project/project/cache_assoc/verilog/mem_system_randbench.v:131: Unsupported: Ignoring delay on this delayed statement.\n #85;\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 305,005 | module | module mem_system_randbench();
wire CacheHit;
wire [15:0] DataOut;
wire Done;
wire Stall;
reg [15:0] Addr;
reg [15:0] DataIn;
reg Rd;
reg Wr;
reg createdump;
wire clk;
wire rst;
assign clk = DUT.clkgen.clk;
assign rst = DUT.clkgen.rst;
mem_system_hier DUT(
.DataOut (DataOut[15:0]),
.Done (Done),
.Stall (Stall),
.CacheHit (CacheHit),
.Addr (Addr[15:0]),
.DataIn (DataIn[15:0]),
.Rd (Rd),
.Wr (Wr),
.createdump (1'b0));
wire [15:0] DataOut_ref;
wire Done_ref;
wire Stall_ref;
wire CacheHit_ref;
mem_system_ref ref(
.DataOut (DataOut_ref[15:0]),
.Done (Done_ref),
.Stall (Stall_ref),
.CacheHit (CacheHit_ref),
.Addr (Addr[15:0]),
.DataIn (DataIn[15:0]),
.Rd (Rd),
.Wr (Wr),
.clk( DUT.clkgen.clk),
.rst( DUT.clkgen.rst) );
reg reg_readorwrite;
integer n_requests;
integer n_replies;
integer n_cache_hits;
integer n_cache_hits_total;
integer req_cycle;
reg test_success;
initial begin
Rd = 1'b0;
Wr = 1'b0;
Addr = 16'd0;
DataIn = 16'd0;
reg_readorwrite = 1'b0;
n_requests = 0;
n_replies = 0;
n_cache_hits = 0;
n_cache_hits_total = 0;
test_success = 1'b1;
end
always @ (posedge clk) begin
#2;
if (Done) begin
n_replies = n_replies + 1;
if (CacheHit) begin
n_cache_hits = n_cache_hits + 1;
end
if (Rd) begin
$display("LOG: ReqNum %4d Cycle %8d ReqCycle %8d Rd Addr 0x%04x Value 0x%04x ValueRef 0x%04x Hit: %1d\n",
n_replies,
DUT.clkgen.cycle_count,
req_cycle,
Addr,
DataOut,
DataOut_ref, CacheHit);
if (DataOut != DataOut_ref) begin
$display("ERROR");
test_success = 1'b0;
end
end
if (Wr) begin
$display("LOG: ReqNum %4d Cycle %8d ReqCycle %8d Wr Addr 0x%04x Value 0x%04x ValueRef 0x%04x Hit: %1d\n",
n_replies, DUT.clkgen.cycle_count, req_cycle, Addr, DataIn, DataIn, CacheHit);
end
if (Rd | Wr) begin
if (CacheHit) begin
if ((DUT.clkgen.cycle_count - req_cycle) > 2) begin
$display("LOG: WARNING: PERFORMANCE ERROR? CacheHit Latency (%3d) greater than 2 cycles?", DUT.clkgen.cycle_count - req_cycle );
test_success = 1'b0;
end
end else begin
if ( ((DUT.clkgen.cycle_count - req_cycle) > 20) || ((DUT.clkgen.cycle_count - req_cycle) <= 2) ) begin
$display("LOG: WARNING: PERFORMANCE ERROR? CacheMiss Latency (%3d) greater than 20 or less than 2 cycles?", DUT.clkgen.cycle_count - req_cycle);
test_success = 1'b0;
end
end
end
Rd = 1'd0;
Wr = 1'd0;
end
#85;
if (!rst && (!Stall)) begin
if (n_requests < 1000) begin
full_random_addr;
end else if (n_requests == 1000) begin
Addr = 16'd0;
Rd = 1'd0;
Wr = 1'd0;
n_requests = n_requests + 1;
n_replies = n_replies + 1;
$display("LOG: Done full_random, Requests: %10d, Cycles: %10d Hits: %10d",
n_requests,
DUT.clkgen.cycle_count,
n_cache_hits );
n_cache_hits_total = n_cache_hits_total + n_cache_hits;
n_cache_hits = 0;
end else if (n_requests == 2000) begin
Addr = 16'd0;
Rd = 1'd0;
Wr = 1'd0;
n_requests = n_requests + 1;
n_replies = n_replies + 1;
$display("LOG: Done small_random, Requests: %10d, Cycles: %10d Hits: %10d",
n_requests,
DUT.clkgen.cycle_count,
n_cache_hits );
n_cache_hits_total = n_cache_hits_total + n_cache_hits;
n_cache_hits = 0;
end else if (n_requests == 3000) begin
Addr = 16'd0;
Rd = 1'd0;
Wr = 1'd0;
n_requests = n_requests + 1;
n_replies = n_replies + 1;
$display("LOG: Done sequential_addr, Requests: %10d, Cycles: %10d Hits: %10d",
n_requests,
DUT.clkgen.cycle_count,
n_cache_hits );
n_cache_hits_total = n_cache_hits_total + n_cache_hits;
n_cache_hits = 0;
end else if (n_requests == 8000) begin
Addr = 16'd0;
Rd = 1'd0;
Wr = 1'd0;
n_requests = n_requests + 1;
n_replies = n_replies + 1;
$display("LOG: Done two_sets_addr Requests: %10d, Cycles: %10d Hits: %10d",
n_requests,
DUT.clkgen.cycle_count,
n_cache_hits );
n_cache_hits_total = n_cache_hits_total + n_cache_hits;
n_cache_hits = 0;
end else if (n_requests < 2000) begin
small_random_addr;
end else if (n_requests < 3000) begin
seq_addr;
end else if (n_requests < 8000) begin
two_sets_addr;
end else begin
end_simulation;
end
if ( (Rd | Wr) && (!rst && (!Stall)) ) begin
req_cycle = DUT.clkgen.cycle_count;
end
end
end
task check_dropped_request;
begin
if (n_replies != n_requests) begin
if (Rd) begin
$display("LOG: ReqNum %4d Cycle %8d ReqCycle %8d Rd Addr 0x%04x RefValue 0x%04x\n",
n_replies, DUT.clkgen.cycle_count, req_cycle, Addr, DataOut_ref);
end
if (Wr) begin
$display("LOG: ReQNum %4d Cycle %8d ReqCycle %8d Wr Addr 0x%04x Value 0x%04x\n",
n_replies, DUT.clkgen.cycle_count, req_cycle, Addr, DataIn);
end
$display("ERROR! Request dropped");
test_success = 1'b0;
n_replies = n_requests;
end
end
endtask
reg [7:0] index = 0;
task seq_addr;
begin
if (!rst && (!Stall)) begin
check_dropped_request;
reg_readorwrite = $random % 2;
if (reg_readorwrite) begin
Wr = $random % 2;
index = (index < 8)?(index + 1):0;
Addr = {5'd0,index,2'd0,1'd0};
DataIn = $random % 16'hffff;
Rd = ~Wr;
n_requests = n_requests + 1;
end else begin
Wr = 1'd0;
Rd = 1'd0;
end
end
end
endtask
reg [4:0] tag = 0;
reg n_iter = 1;
task two_sets_addr;
begin
if (!rst && (!Stall)) begin
check_dropped_request;
reg_readorwrite = $random % 2;
if (reg_readorwrite) begin
Wr = $random % 2;
if (n_iter == 2) begin
n_iter = 1;
end else begin
n_iter = n_iter + 1;
end
if (n_iter == 1) begin
index = (index < 8)?(index + 1):0;
tag = index % 5'h1F;
end else begin
tag = tag + 1;
end
Addr = {tag,index,2'd0,1'd0};
DataIn = $random % 16'hffff;
Rd = ~Wr;
n_requests = n_requests + 1;
end else begin
Wr = 1'd0;
Rd = 1'd0;
end
end
end
endtask
task full_random_addr;
begin
if (!rst && (!Stall) && (DUT.clkgen.cycle_count > 10)) begin
check_dropped_request;
reg_readorwrite = $random % 2;
if (reg_readorwrite) begin
Wr = $random % 2;
Addr = ($random % 16'hffff) & 16'hFFFE;
DataIn = $random % 16'hffff;
Rd = ~Wr;
n_requests = n_requests + 1;
end else begin
Wr = 1'd0;
Rd = 1'd0;
end
end
end
endtask
task small_random_addr;
begin
if (!rst && (!Stall) && (DUT.clkgen.cycle_count > 10) ) begin
check_dropped_request;
reg_readorwrite = $random % 2;
if (reg_readorwrite) begin
Wr = $random % 2;
Addr = (($random % 16'hffff) & 16'h07FE) | 16'h6000;
DataIn = $random % 16'hffff;
Rd = ~Wr;
n_requests = n_requests + 1;
end else begin
Wr = 1'd0;
Rd = 1'd0;
end
end
end
endtask
task end_simulation;
begin
$display("LOG: Done Requests: %10d Replies: %10d Cycles: %10d Hits: %10d",
n_requests,
n_replies,
DUT.clkgen.cycle_count,
n_cache_hits_total );
if (!test_success) begin
$display("Test status: FAIL");
end else begin
$display("Test status: SUCCESS");
end
$finish;
end
endtask
endmodule | module mem_system_randbench(); |
wire CacheHit;
wire [15:0] DataOut;
wire Done;
wire Stall;
reg [15:0] Addr;
reg [15:0] DataIn;
reg Rd;
reg Wr;
reg createdump;
wire clk;
wire rst;
assign clk = DUT.clkgen.clk;
assign rst = DUT.clkgen.rst;
mem_system_hier DUT(
.DataOut (DataOut[15:0]),
.Done (Done),
.Stall (Stall),
.CacheHit (CacheHit),
.Addr (Addr[15:0]),
.DataIn (DataIn[15:0]),
.Rd (Rd),
.Wr (Wr),
.createdump (1'b0));
wire [15:0] DataOut_ref;
wire Done_ref;
wire Stall_ref;
wire CacheHit_ref;
mem_system_ref ref(
.DataOut (DataOut_ref[15:0]),
.Done (Done_ref),
.Stall (Stall_ref),
.CacheHit (CacheHit_ref),
.Addr (Addr[15:0]),
.DataIn (DataIn[15:0]),
.Rd (Rd),
.Wr (Wr),
.clk( DUT.clkgen.clk),
.rst( DUT.clkgen.rst) );
reg reg_readorwrite;
integer n_requests;
integer n_replies;
integer n_cache_hits;
integer n_cache_hits_total;
integer req_cycle;
reg test_success;
initial begin
Rd = 1'b0;
Wr = 1'b0;
Addr = 16'd0;
DataIn = 16'd0;
reg_readorwrite = 1'b0;
n_requests = 0;
n_replies = 0;
n_cache_hits = 0;
n_cache_hits_total = 0;
test_success = 1'b1;
end
always @ (posedge clk) begin
#2;
if (Done) begin
n_replies = n_replies + 1;
if (CacheHit) begin
n_cache_hits = n_cache_hits + 1;
end
if (Rd) begin
$display("LOG: ReqNum %4d Cycle %8d ReqCycle %8d Rd Addr 0x%04x Value 0x%04x ValueRef 0x%04x Hit: %1d\n",
n_replies,
DUT.clkgen.cycle_count,
req_cycle,
Addr,
DataOut,
DataOut_ref, CacheHit);
if (DataOut != DataOut_ref) begin
$display("ERROR");
test_success = 1'b0;
end
end
if (Wr) begin
$display("LOG: ReqNum %4d Cycle %8d ReqCycle %8d Wr Addr 0x%04x Value 0x%04x ValueRef 0x%04x Hit: %1d\n",
n_replies, DUT.clkgen.cycle_count, req_cycle, Addr, DataIn, DataIn, CacheHit);
end
if (Rd | Wr) begin
if (CacheHit) begin
if ((DUT.clkgen.cycle_count - req_cycle) > 2) begin
$display("LOG: WARNING: PERFORMANCE ERROR? CacheHit Latency (%3d) greater than 2 cycles?", DUT.clkgen.cycle_count - req_cycle );
test_success = 1'b0;
end
end else begin
if ( ((DUT.clkgen.cycle_count - req_cycle) > 20) || ((DUT.clkgen.cycle_count - req_cycle) <= 2) ) begin
$display("LOG: WARNING: PERFORMANCE ERROR? CacheMiss Latency (%3d) greater than 20 or less than 2 cycles?", DUT.clkgen.cycle_count - req_cycle);
test_success = 1'b0;
end
end
end
Rd = 1'd0;
Wr = 1'd0;
end
#85;
if (!rst && (!Stall)) begin
if (n_requests < 1000) begin
full_random_addr;
end else if (n_requests == 1000) begin
Addr = 16'd0;
Rd = 1'd0;
Wr = 1'd0;
n_requests = n_requests + 1;
n_replies = n_replies + 1;
$display("LOG: Done full_random, Requests: %10d, Cycles: %10d Hits: %10d",
n_requests,
DUT.clkgen.cycle_count,
n_cache_hits );
n_cache_hits_total = n_cache_hits_total + n_cache_hits;
n_cache_hits = 0;
end else if (n_requests == 2000) begin
Addr = 16'd0;
Rd = 1'd0;
Wr = 1'd0;
n_requests = n_requests + 1;
n_replies = n_replies + 1;
$display("LOG: Done small_random, Requests: %10d, Cycles: %10d Hits: %10d",
n_requests,
DUT.clkgen.cycle_count,
n_cache_hits );
n_cache_hits_total = n_cache_hits_total + n_cache_hits;
n_cache_hits = 0;
end else if (n_requests == 3000) begin
Addr = 16'd0;
Rd = 1'd0;
Wr = 1'd0;
n_requests = n_requests + 1;
n_replies = n_replies + 1;
$display("LOG: Done sequential_addr, Requests: %10d, Cycles: %10d Hits: %10d",
n_requests,
DUT.clkgen.cycle_count,
n_cache_hits );
n_cache_hits_total = n_cache_hits_total + n_cache_hits;
n_cache_hits = 0;
end else if (n_requests == 8000) begin
Addr = 16'd0;
Rd = 1'd0;
Wr = 1'd0;
n_requests = n_requests + 1;
n_replies = n_replies + 1;
$display("LOG: Done two_sets_addr Requests: %10d, Cycles: %10d Hits: %10d",
n_requests,
DUT.clkgen.cycle_count,
n_cache_hits );
n_cache_hits_total = n_cache_hits_total + n_cache_hits;
n_cache_hits = 0;
end else if (n_requests < 2000) begin
small_random_addr;
end else if (n_requests < 3000) begin
seq_addr;
end else if (n_requests < 8000) begin
two_sets_addr;
end else begin
end_simulation;
end
if ( (Rd | Wr) && (!rst && (!Stall)) ) begin
req_cycle = DUT.clkgen.cycle_count;
end
end
end
task check_dropped_request;
begin
if (n_replies != n_requests) begin
if (Rd) begin
$display("LOG: ReqNum %4d Cycle %8d ReqCycle %8d Rd Addr 0x%04x RefValue 0x%04x\n",
n_replies, DUT.clkgen.cycle_count, req_cycle, Addr, DataOut_ref);
end
if (Wr) begin
$display("LOG: ReQNum %4d Cycle %8d ReqCycle %8d Wr Addr 0x%04x Value 0x%04x\n",
n_replies, DUT.clkgen.cycle_count, req_cycle, Addr, DataIn);
end
$display("ERROR! Request dropped");
test_success = 1'b0;
n_replies = n_requests;
end
end
endtask
reg [7:0] index = 0;
task seq_addr;
begin
if (!rst && (!Stall)) begin
check_dropped_request;
reg_readorwrite = $random % 2;
if (reg_readorwrite) begin
Wr = $random % 2;
index = (index < 8)?(index + 1):0;
Addr = {5'd0,index,2'd0,1'd0};
DataIn = $random % 16'hffff;
Rd = ~Wr;
n_requests = n_requests + 1;
end else begin
Wr = 1'd0;
Rd = 1'd0;
end
end
end
endtask
reg [4:0] tag = 0;
reg n_iter = 1;
task two_sets_addr;
begin
if (!rst && (!Stall)) begin
check_dropped_request;
reg_readorwrite = $random % 2;
if (reg_readorwrite) begin
Wr = $random % 2;
if (n_iter == 2) begin
n_iter = 1;
end else begin
n_iter = n_iter + 1;
end
if (n_iter == 1) begin
index = (index < 8)?(index + 1):0;
tag = index % 5'h1F;
end else begin
tag = tag + 1;
end
Addr = {tag,index,2'd0,1'd0};
DataIn = $random % 16'hffff;
Rd = ~Wr;
n_requests = n_requests + 1;
end else begin
Wr = 1'd0;
Rd = 1'd0;
end
end
end
endtask
task full_random_addr;
begin
if (!rst && (!Stall) && (DUT.clkgen.cycle_count > 10)) begin
check_dropped_request;
reg_readorwrite = $random % 2;
if (reg_readorwrite) begin
Wr = $random % 2;
Addr = ($random % 16'hffff) & 16'hFFFE;
DataIn = $random % 16'hffff;
Rd = ~Wr;
n_requests = n_requests + 1;
end else begin
Wr = 1'd0;
Rd = 1'd0;
end
end
end
endtask
task small_random_addr;
begin
if (!rst && (!Stall) && (DUT.clkgen.cycle_count > 10) ) begin
check_dropped_request;
reg_readorwrite = $random % 2;
if (reg_readorwrite) begin
Wr = $random % 2;
Addr = (($random % 16'hffff) & 16'h07FE) | 16'h6000;
DataIn = $random % 16'hffff;
Rd = ~Wr;
n_requests = n_requests + 1;
end else begin
Wr = 1'd0;
Rd = 1'd0;
end
end
end
endtask
task end_simulation;
begin
$display("LOG: Done Requests: %10d Replies: %10d Cycles: %10d Hits: %10d",
n_requests,
n_replies,
DUT.clkgen.cycle_count,
n_cache_hits_total );
if (!test_success) begin
$display("Test status: FAIL");
end else begin
$display("Test status: SUCCESS");
end
$finish;
end
endtask
endmodule | 0 |
139,496 | data/full_repos/permissive/87881270/project/project/cache_direct/verilog/mem_system.v | 87,881,270 | mem_system.v | v | 376 | 125 | [] | [] | [] | [(5, 373)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/project/project/cache_direct/verilog/mem_system.v:28: Cannot find file containing module: 'dff'\n dff curr_State[3:0] (.q(currState), .d(nextState), .clk(clk), .rst(rst));\n ^~~\n ... Looked in:\n data/full_repos/permissive/87881270/project/project/cache_direct/verilog,data/full_repos/permissive/87881270/dff\n data/full_repos/permissive/87881270/project/project/cache_direct/verilog,data/full_repos/permissive/87881270/dff.v\n data/full_repos/permissive/87881270/project/project/cache_direct/verilog,data/full_repos/permissive/87881270/dff.sv\n dff\n dff.v\n dff.sv\n obj_dir/dff\n obj_dir/dff.v\n obj_dir/dff.sv\n%Error: data/full_repos/permissive/87881270/project/project/cache_direct/verilog/mem_system.v:44: Cannot find file containing module: 'dff'\n dff hitdff(.clk(clk), .rst(rst), .q(cacheHitTemp), .d(cacheHit));\n ^~~\n%Error: data/full_repos/permissive/87881270/project/project/cache_direct/verilog/mem_system.v:49: Cannot find file containing module: 'cache'\n cache #(mem_type + 0) c0( \n ^~~~~\n%Error: data/full_repos/permissive/87881270/project/project/cache_direct/verilog/mem_system.v:69: Cannot find file containing module: 'four_bank_mem'\n four_bank_mem mem( \n ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 305,017 | module | module mem_system(
DataOut, Done, Stall, CacheHit, err,
Addr, DataIn, Rd, Wr, createdump, clk, rst
);
input [15:0] Addr;
input [15:0] DataIn;
input Rd;
input Wr;
input createdump;
input clk;
input rst;
output reg [15:0] DataOut;
output reg Done;
output reg Stall;
output CacheHit;
output err;
reg [3:0] nextState;
wire [3:0] currState;
dff curr_State[3:0] (.q(currState), .d(nextState), .clk(clk), .rst(rst));
wire dirty, valid, hit, miss, mem_stall, cacheErr, memErr, cacheHit, cacheHitTemp;
reg comp, cache_write, mem_wr, mem_rd, enable, valid_in, controlErr, retry;
wire[15:0] cache_data_out, mem_data_out;
wire[4:0] tag_out;
wire[3:0] busy;
reg [15:0] cache_data_in, mem_addr, mem_data_in;
reg [7:0] index;
reg [4:0] tag_in;
reg [2:0] offset;
assign miss = enable & (~hit | ~valid);
assign err = controlErr;
assign cacheHit = hit & comp & ~retry;
assign CacheHit = cacheHitTemp;
dff hitdff(.clk(clk), .rst(rst), .q(cacheHitTemp), .d(cacheHit));
parameter mem_type = 0;
cache #(mem_type + 0) c0(
.tag_out (tag_out),
.data_out (cache_data_out),
.hit (hit),
.dirty (dirty),
.valid (valid),
.err (cacheErr),
.enable (enable),
.clk (clk),
.rst (rst),
.createdump (createdump),
.tag_in (tag_in),
.index (index),
.offset (offset),
.data_in (cache_data_in),
.comp (comp),
.write (cache_write),
.valid_in (valid_in));
four_bank_mem mem(
.data_out (mem_data_out),
.stall (mem_stall),
.busy (busy),
.err (memErr),
.clk (clk),
.rst (rst),
.createdump (createdump),
.addr (mem_addr),
.data_in (mem_data_in),
.wr (mem_wr),
.rd (mem_rd));
always@(*)begin case(currState)
4'h0: begin
retry = 0;
enable = 1;
comp = (~Wr & ~Rd) ? 0 : 1;
cache_write = Wr ? 1 : 0;
index = (~Wr & ~Rd) ? 0 : Addr[10:3];
tag_in = (~Wr & ~Rd) ? 0 : Addr[15:11];
offset = (~Wr & ~Rd) ? 0 : {Addr[2:1], 1'b0};
cache_data_in = Wr ? DataIn : 0;
valid_in = 0;
mem_addr = 0;
mem_data_in = 0;
mem_wr = 0;
mem_rd = 0;
DataOut = Rd ? (( hit & valid ) ? cache_data_out : 0) : 0;
Done = (hit & valid & (Wr | Rd)) ? 1 : 0;
Stall = (~Wr & ~Rd) ? 0 :(( hit & valid) ? 0 : 1);
nextState = (~Wr & ~Rd) ? 0 : ((miss & ~dirty) ? 4'h2 : ((miss & valid & dirty) ? 4'hD : 4'h0));
end
4'h1: begin
retry = 1;
enable = 1;
comp = 1;
cache_write = Wr ? 1 : 0;
index = (~Wr & ~Rd) ? 0 : Addr[10:3];
tag_in = (~Wr & ~Rd) ? 0 : Addr[15:11];
offset = (~Wr & ~Rd) ? 0 : {Addr[2:1], 1'b0};
cache_data_in = Wr ? DataIn : 0;
valid_in = 0;
mem_addr = 0;
mem_data_in = 0;
mem_wr = 0;
mem_rd = 0;
DataOut = Rd ? cache_data_out : 0;
Done = 0;
Stall = 1;
nextState = 4'h0;
end
4'h2: begin
retry = 0;
enable = 0;
comp = 0;
cache_write = 0;
index = 0;
tag_in = 0;
offset = 0;
cache_data_in = 0;
valid_in = 0;
mem_addr = {Addr[15:3], 3'b000};
mem_data_in = 0;
mem_wr = 0;
mem_rd = 1;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = 4'h3;
end
4'h3: begin
retry = 0;
enable = 0;
comp = 0;
cache_write = 0;
index = 0;
tag_in = 0;
offset = 0;
cache_data_in = 0;
valid_in = 0;
mem_addr = {Addr[15:3], 3'b010};
mem_data_in = 0;
mem_wr = 0;
mem_rd = 1;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'h3 : 4'h4;
end
4'h4: begin
retry = 0;
enable = 1;
comp = 0;
cache_write = 1;
index = Addr[10:3];
tag_in = Addr[15:11];
offset = 3'b000;
cache_data_in = mem_data_out;
valid_in = 0;
mem_addr = {Addr[15:3], 3'b100};
mem_data_in = 0;
mem_wr = 0;
mem_rd = 1;
DataOut = (Rd & (offset == {Addr[2:1], 1'b0})) ? mem_data_out : 0;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'h4 : 4'h5;
end
4'h5: begin
retry = 0;
enable = 1;
comp = 0;
cache_write = 1;
index = Addr[10:3];
tag_in = Addr[15:11];
offset = 3'b010;
cache_data_in = mem_data_out;
valid_in = 0;
mem_addr = {Addr[15:3], 3'b110};
mem_data_in = 0;
mem_wr = 0;
mem_rd = 1;
DataOut = (Rd & (offset == {Addr[2:1], 1'b0})) ? mem_data_out : DataOut;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'h5 : 4'h6;
end
4'h6: begin
retry = 0;
enable = 1;
comp = 0;
cache_write = 1;
index = Addr[10:3];
tag_in = Addr[15:11];
offset = 3'b100;
cache_data_in = mem_data_out;
valid_in = 0;
mem_addr = 0;
mem_data_in = 0;
mem_wr = 0;
mem_rd = 0;
DataOut = (Rd & (offset == {Addr[2:1], 1'b0})) ? mem_data_out : DataOut;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'h6 : 4'h7;
end
4'h7: begin
retry = 0;
enable = 1;
comp = 0;
cache_write = 1;
index = Addr[10:3];
tag_in = Addr[15:11];
offset = 3'b110;
cache_data_in = mem_data_out;
valid_in = 1;
mem_addr = 0;
mem_data_in = 0;
mem_wr = 0;
mem_rd = 0;
DataOut = (Rd & (offset == {Addr[2:1], 1'b0})) ? mem_data_out : DataOut;
Done = 0;
Stall = 1;
nextState = 4'h1;
end
4'h8: begin
retry = 0;
enable = 1;
comp = 0;
cache_write = 0;
index = Addr[10:3];
tag_in = 0;
offset = 3'b000;
cache_data_in = 0;
valid_in = 0;
mem_addr = {tag_out, Addr[10:3], 3'b000};
mem_data_in = cache_data_out;
mem_wr = 1;
mem_rd = 0;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = 4'h9;
end
4'h9: begin
retry = 0;
enable = 1;
comp = 0;
cache_write = 0;
index = Addr[10:3];
tag_in = 0;
offset = 3'b010;
cache_data_in = 0;
valid_in = 0;
mem_addr = {tag_out, Addr[10:3], 3'b010};
mem_data_in = cache_data_out;
mem_wr = 1;
mem_rd = 0;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'h9 : 4'hA;
end
4'hA: begin
retry = 0;
enable = 1;
comp = 0;
cache_write = 0;
index = Addr[10:3];
tag_in = 0;
offset = 3'b100;
cache_data_in = 0;
valid_in = 0;
mem_addr = {tag_out, Addr[10:3], 3'b100};
mem_data_in = cache_data_out;
mem_wr = 1;
mem_rd = 0;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'hA : 4'hB;
end
4'hB: begin
retry = 0;
enable = 1;
comp = 0;
cache_write = 0;
index = Addr[10:3];
tag_in = 0;
offset = 3'b110;
cache_data_in = 0;
valid_in = 0;
mem_addr = {tag_out, Addr[10:3], 3'b110};
mem_data_in = cache_data_out;
mem_wr = 1;
mem_rd = 0;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'hB : 4'h2;
end
4'hC: begin
Done = 1;
Stall = 0;
controlErr = 1;
nextState = 4'h0;
end
default: begin
retry = 0;
enable = 1;
comp = 1;
cache_write = Wr ? 1 : 0;
index = (~Wr & ~Rd) ? 0 : Addr[10:3];
tag_in = (~Wr & ~Rd) ? 0 : Addr[15:11];
offset = (~Wr & ~Rd) ? 0 : {Addr[2:1], 1'b0};
cache_data_in = Wr ? DataIn : 0;
valid_in = 0;
mem_addr = 0;
mem_data_in = 0;
mem_wr = 0;
mem_rd = 0;
DataOut = Rd ? (( hit & valid ) ? cache_data_out : 0) : 0;
Done = (hit & valid) ? 1 : 0;
Stall = (~Wr & ~Rd) ? 0 :(( hit & valid) ? 0 : 1);
nextState = (~Wr & ~Rd) ? 0 : ((miss & ~dirty) ? 4'h2 : ((miss & valid & dirty) ? 4'h8 : ((hit & valid) ? 4'h0 : 4'h0)));
end
endcase
end
endmodule | module mem_system(
DataOut, Done, Stall, CacheHit, err,
Addr, DataIn, Rd, Wr, createdump, clk, rst
); |
input [15:0] Addr;
input [15:0] DataIn;
input Rd;
input Wr;
input createdump;
input clk;
input rst;
output reg [15:0] DataOut;
output reg Done;
output reg Stall;
output CacheHit;
output err;
reg [3:0] nextState;
wire [3:0] currState;
dff curr_State[3:0] (.q(currState), .d(nextState), .clk(clk), .rst(rst));
wire dirty, valid, hit, miss, mem_stall, cacheErr, memErr, cacheHit, cacheHitTemp;
reg comp, cache_write, mem_wr, mem_rd, enable, valid_in, controlErr, retry;
wire[15:0] cache_data_out, mem_data_out;
wire[4:0] tag_out;
wire[3:0] busy;
reg [15:0] cache_data_in, mem_addr, mem_data_in;
reg [7:0] index;
reg [4:0] tag_in;
reg [2:0] offset;
assign miss = enable & (~hit | ~valid);
assign err = controlErr;
assign cacheHit = hit & comp & ~retry;
assign CacheHit = cacheHitTemp;
dff hitdff(.clk(clk), .rst(rst), .q(cacheHitTemp), .d(cacheHit));
parameter mem_type = 0;
cache #(mem_type + 0) c0(
.tag_out (tag_out),
.data_out (cache_data_out),
.hit (hit),
.dirty (dirty),
.valid (valid),
.err (cacheErr),
.enable (enable),
.clk (clk),
.rst (rst),
.createdump (createdump),
.tag_in (tag_in),
.index (index),
.offset (offset),
.data_in (cache_data_in),
.comp (comp),
.write (cache_write),
.valid_in (valid_in));
four_bank_mem mem(
.data_out (mem_data_out),
.stall (mem_stall),
.busy (busy),
.err (memErr),
.clk (clk),
.rst (rst),
.createdump (createdump),
.addr (mem_addr),
.data_in (mem_data_in),
.wr (mem_wr),
.rd (mem_rd));
always@(*)begin case(currState)
4'h0: begin
retry = 0;
enable = 1;
comp = (~Wr & ~Rd) ? 0 : 1;
cache_write = Wr ? 1 : 0;
index = (~Wr & ~Rd) ? 0 : Addr[10:3];
tag_in = (~Wr & ~Rd) ? 0 : Addr[15:11];
offset = (~Wr & ~Rd) ? 0 : {Addr[2:1], 1'b0};
cache_data_in = Wr ? DataIn : 0;
valid_in = 0;
mem_addr = 0;
mem_data_in = 0;
mem_wr = 0;
mem_rd = 0;
DataOut = Rd ? (( hit & valid ) ? cache_data_out : 0) : 0;
Done = (hit & valid & (Wr | Rd)) ? 1 : 0;
Stall = (~Wr & ~Rd) ? 0 :(( hit & valid) ? 0 : 1);
nextState = (~Wr & ~Rd) ? 0 : ((miss & ~dirty) ? 4'h2 : ((miss & valid & dirty) ? 4'hD : 4'h0));
end
4'h1: begin
retry = 1;
enable = 1;
comp = 1;
cache_write = Wr ? 1 : 0;
index = (~Wr & ~Rd) ? 0 : Addr[10:3];
tag_in = (~Wr & ~Rd) ? 0 : Addr[15:11];
offset = (~Wr & ~Rd) ? 0 : {Addr[2:1], 1'b0};
cache_data_in = Wr ? DataIn : 0;
valid_in = 0;
mem_addr = 0;
mem_data_in = 0;
mem_wr = 0;
mem_rd = 0;
DataOut = Rd ? cache_data_out : 0;
Done = 0;
Stall = 1;
nextState = 4'h0;
end
4'h2: begin
retry = 0;
enable = 0;
comp = 0;
cache_write = 0;
index = 0;
tag_in = 0;
offset = 0;
cache_data_in = 0;
valid_in = 0;
mem_addr = {Addr[15:3], 3'b000};
mem_data_in = 0;
mem_wr = 0;
mem_rd = 1;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = 4'h3;
end
4'h3: begin
retry = 0;
enable = 0;
comp = 0;
cache_write = 0;
index = 0;
tag_in = 0;
offset = 0;
cache_data_in = 0;
valid_in = 0;
mem_addr = {Addr[15:3], 3'b010};
mem_data_in = 0;
mem_wr = 0;
mem_rd = 1;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'h3 : 4'h4;
end
4'h4: begin
retry = 0;
enable = 1;
comp = 0;
cache_write = 1;
index = Addr[10:3];
tag_in = Addr[15:11];
offset = 3'b000;
cache_data_in = mem_data_out;
valid_in = 0;
mem_addr = {Addr[15:3], 3'b100};
mem_data_in = 0;
mem_wr = 0;
mem_rd = 1;
DataOut = (Rd & (offset == {Addr[2:1], 1'b0})) ? mem_data_out : 0;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'h4 : 4'h5;
end
4'h5: begin
retry = 0;
enable = 1;
comp = 0;
cache_write = 1;
index = Addr[10:3];
tag_in = Addr[15:11];
offset = 3'b010;
cache_data_in = mem_data_out;
valid_in = 0;
mem_addr = {Addr[15:3], 3'b110};
mem_data_in = 0;
mem_wr = 0;
mem_rd = 1;
DataOut = (Rd & (offset == {Addr[2:1], 1'b0})) ? mem_data_out : DataOut;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'h5 : 4'h6;
end
4'h6: begin
retry = 0;
enable = 1;
comp = 0;
cache_write = 1;
index = Addr[10:3];
tag_in = Addr[15:11];
offset = 3'b100;
cache_data_in = mem_data_out;
valid_in = 0;
mem_addr = 0;
mem_data_in = 0;
mem_wr = 0;
mem_rd = 0;
DataOut = (Rd & (offset == {Addr[2:1], 1'b0})) ? mem_data_out : DataOut;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'h6 : 4'h7;
end
4'h7: begin
retry = 0;
enable = 1;
comp = 0;
cache_write = 1;
index = Addr[10:3];
tag_in = Addr[15:11];
offset = 3'b110;
cache_data_in = mem_data_out;
valid_in = 1;
mem_addr = 0;
mem_data_in = 0;
mem_wr = 0;
mem_rd = 0;
DataOut = (Rd & (offset == {Addr[2:1], 1'b0})) ? mem_data_out : DataOut;
Done = 0;
Stall = 1;
nextState = 4'h1;
end
4'h8: begin
retry = 0;
enable = 1;
comp = 0;
cache_write = 0;
index = Addr[10:3];
tag_in = 0;
offset = 3'b000;
cache_data_in = 0;
valid_in = 0;
mem_addr = {tag_out, Addr[10:3], 3'b000};
mem_data_in = cache_data_out;
mem_wr = 1;
mem_rd = 0;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = 4'h9;
end
4'h9: begin
retry = 0;
enable = 1;
comp = 0;
cache_write = 0;
index = Addr[10:3];
tag_in = 0;
offset = 3'b010;
cache_data_in = 0;
valid_in = 0;
mem_addr = {tag_out, Addr[10:3], 3'b010};
mem_data_in = cache_data_out;
mem_wr = 1;
mem_rd = 0;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'h9 : 4'hA;
end
4'hA: begin
retry = 0;
enable = 1;
comp = 0;
cache_write = 0;
index = Addr[10:3];
tag_in = 0;
offset = 3'b100;
cache_data_in = 0;
valid_in = 0;
mem_addr = {tag_out, Addr[10:3], 3'b100};
mem_data_in = cache_data_out;
mem_wr = 1;
mem_rd = 0;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'hA : 4'hB;
end
4'hB: begin
retry = 0;
enable = 1;
comp = 0;
cache_write = 0;
index = Addr[10:3];
tag_in = 0;
offset = 3'b110;
cache_data_in = 0;
valid_in = 0;
mem_addr = {tag_out, Addr[10:3], 3'b110};
mem_data_in = cache_data_out;
mem_wr = 1;
mem_rd = 0;
DataOut = 0;
Done = 0;
Stall = 1;
nextState = mem_stall ? 4'hB : 4'h2;
end
4'hC: begin
Done = 1;
Stall = 0;
controlErr = 1;
nextState = 4'h0;
end
default: begin
retry = 0;
enable = 1;
comp = 1;
cache_write = Wr ? 1 : 0;
index = (~Wr & ~Rd) ? 0 : Addr[10:3];
tag_in = (~Wr & ~Rd) ? 0 : Addr[15:11];
offset = (~Wr & ~Rd) ? 0 : {Addr[2:1], 1'b0};
cache_data_in = Wr ? DataIn : 0;
valid_in = 0;
mem_addr = 0;
mem_data_in = 0;
mem_wr = 0;
mem_rd = 0;
DataOut = Rd ? (( hit & valid ) ? cache_data_out : 0) : 0;
Done = (hit & valid) ? 1 : 0;
Stall = (~Wr & ~Rd) ? 0 :(( hit & valid) ? 0 : 1);
nextState = (~Wr & ~Rd) ? 0 : ((miss & ~dirty) ? 4'h2 : ((miss & valid & dirty) ? 4'h8 : ((hit & valid) ? 4'h0 : 4'h0)));
end
endcase
end
endmodule | 0 |
139,497 | data/full_repos/permissive/87881270/project/project/demo1/verilog/additionLogic.v | 87,881,270 | additionLogic.v | v | 29 | 98 | [] | [] | [] | [(1, 29)] | null | null | 1: b"%Error: data/full_repos/permissive/87881270/project/project/demo1/verilog/additionLogic.v:12: Cannot find file containing module: 'sixteenBitCLA'\n sixteenBitCLA cla(.InA(A), .InB(B), .Out(addOut), .C0(Cin), .C12(c12), .C16(c16), .P(p), .G(g));\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/87881270/project/project/demo1/verilog,data/full_repos/permissive/87881270/sixteenBitCLA\n data/full_repos/permissive/87881270/project/project/demo1/verilog,data/full_repos/permissive/87881270/sixteenBitCLA.v\n data/full_repos/permissive/87881270/project/project/demo1/verilog,data/full_repos/permissive/87881270/sixteenBitCLA.sv\n sixteenBitCLA\n sixteenBitCLA.v\n sixteenBitCLA.sv\n obj_dir/sixteenBitCLA\n obj_dir/sixteenBitCLA.v\n obj_dir/sixteenBitCLA.sv\n%Error: Exiting due to 1 error(s)\n" | 305,022 | module | module additionLogic(A, B, Cin, sign, Op, Out, Ofl);
input [15:0] A, B;
input [1:0] Op;
input Cin, sign;
output [15:0] Out;
output Ofl;
wire c12, c16, p, g, signedOfl, unsignedOfl, neg, negOfl, posOfl;
wire[15:0] addOut, w1, w2, out1, out2, out3;
sixteenBitCLA cla(.InA(A), .InB(B), .Out(addOut), .C0(Cin), .C12(c12), .C16(c16), .P(p), .G(g));
assign out1 = A | B;
assign out2 = A ^ B;
assign out3 = A & B;
assign w1 = Op[0] ? out1 : addOut;
assign w2 = Op[0] ? out3 : out2;
assign Out = Op[1] ? w2 : w1;
assign neg = (A[15] & B[15]) ? 1 : 0;
assign negOfl = (neg & ~Out[15]) ? 1 : 0;
assign posOfl = (~neg & Out[15]) ? 1 : 0;
assign signedOfl = negOfl | posOfl;
assign unsignedOfl = c16 ? 1 : 0;
assign Ofl = sign ? signedOfl : unsignedOfl;
endmodule | module additionLogic(A, B, Cin, sign, Op, Out, Ofl); |
input [15:0] A, B;
input [1:0] Op;
input Cin, sign;
output [15:0] Out;
output Ofl;
wire c12, c16, p, g, signedOfl, unsignedOfl, neg, negOfl, posOfl;
wire[15:0] addOut, w1, w2, out1, out2, out3;
sixteenBitCLA cla(.InA(A), .InB(B), .Out(addOut), .C0(Cin), .C12(c12), .C16(c16), .P(p), .G(g));
assign out1 = A | B;
assign out2 = A ^ B;
assign out3 = A & B;
assign w1 = Op[0] ? out1 : addOut;
assign w2 = Op[0] ? out3 : out2;
assign Out = Op[1] ? w2 : w1;
assign neg = (A[15] & B[15]) ? 1 : 0;
assign negOfl = (neg & ~Out[15]) ? 1 : 0;
assign posOfl = (~neg & Out[15]) ? 1 : 0;
assign signedOfl = negOfl | posOfl;
assign unsignedOfl = c16 ? 1 : 0;
assign Ofl = sign ? signedOfl : unsignedOfl;
endmodule | 0 |
Subsets and Splits