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139,656 | data/full_repos/permissive/88762607/时序逻辑电路实验报告/project_3/project_3.3/loadsranm.srcs/sources_1/new/sramW.v | 88,762,607 | sramW.v | v | 27 | 50 | [] | [] | [] | [(2, 26)] | null | data/verilator_xmls/707a05ae-54ce-4cea-b688-0fab4f863344.xml | null | 305,498 | module | module sramWR(
input clk100mhz,
input w,ce,changeaddr,
input [15:0]number,
inout [15:0] dataBus,
output reg[15:0]LED,
output oe,lb,ub,
output reg[ 18:0]addrBus
);
reg [15:0] tDataBus;
assign oe=0;assign lb =0;assign ub =0;
assign dataBus = w ? 16'hzzzz : tDataBus;
always@(posedge clk100mhz)begin
if(w==0&&ce==0)begin
tDataBus <= number;
end
else if(w&&(ce==0))begin
LED <= dataBus;
end
case(changeaddr)
1: addrBus= 19'b100_0000_0000_0000_0000;
0: addrBus= 19'b100_0000_0000_0000_0001;
endcase
end
endmodule | module sramWR(
input clk100mhz,
input w,ce,changeaddr,
input [15:0]number,
inout [15:0] dataBus,
output reg[15:0]LED,
output oe,lb,ub,
output reg[ 18:0]addrBus
); |
reg [15:0] tDataBus;
assign oe=0;assign lb =0;assign ub =0;
assign dataBus = w ? 16'hzzzz : tDataBus;
always@(posedge clk100mhz)begin
if(w==0&&ce==0)begin
tDataBus <= number;
end
else if(w&&(ce==0))begin
LED <= dataBus;
end
case(changeaddr)
1: addrBus= 19'b100_0000_0000_0000_0000;
0: addrBus= 19'b100_0000_0000_0000_0001;
endcase
end
endmodule | 9 |
139,657 | data/full_repos/permissive/88762607/时序逻辑电路实验报告/project_3/project_3.3/loadsranm.srcs/sources_1/new/xiaodou.v | 88,762,607 | xiaodou.v | v | 18 | 50 | [] | [] | [] | [(2, 17)] | null | data/verilator_xmls/a0cf943d-0db0-448b-a7f7-9d61c0f548ff.xml | null | 305,499 | module | module xiaodou(
input clk_190Hz,
input btnIn,
output btnOut
);
reg delay1;
reg delay2;
reg delay3;
always @(posedge clk_190Hz)begin
delay3 = delay2;
delay2 = delay1;
delay1 = btnIn;
end
assign btnOut = delay1 & delay2 & delay3;
endmodule | module xiaodou(
input clk_190Hz,
input btnIn,
output btnOut
); |
reg delay1;
reg delay2;
reg delay3;
always @(posedge clk_190Hz)begin
delay3 = delay2;
delay2 = delay1;
delay1 = btnIn;
end
assign btnOut = delay1 & delay2 & delay3;
endmodule | 9 |
139,659 | data/full_repos/permissive/88762607/状态机实验报告/project_4/project_4.3 fwm_moore - 1000/fwm_moore.srcs/sim_1/new/fsm_moore_tb.v | 88,762,607 | fsm_moore_tb.v | v | 61 | 83 | [] | [] | [] | [(23, 60)] | null | null | 1: b'%Error: Invalid Option: -\n' | 305,510 | module | module fsm_moore_tb(
);
reg clk;
reg clr;
reg din;
wire dout;
parameter PERIOD=40;
fsm_moore U1(clk,clr,din,dout);
initial
begin
clk=0;
forever
begin
#(PERIOD/2) clk=1;
#(PERIOD/2) clk=0;
end
end
initial
begin
clr=1;
forever
#50 clr=0;
end
initial
begin
din=1;
#400
din=0;
#50
din=1;
#100
din=0;
#50
din=1;
end
endmodule | module fsm_moore_tb(
); |
reg clk;
reg clr;
reg din;
wire dout;
parameter PERIOD=40;
fsm_moore U1(clk,clr,din,dout);
initial
begin
clk=0;
forever
begin
#(PERIOD/2) clk=1;
#(PERIOD/2) clk=0;
end
end
initial
begin
clr=1;
forever
#50 clr=0;
end
initial
begin
din=1;
#400
din=0;
#50
din=1;
#100
din=0;
#50
din=1;
end
endmodule | 9 |
139,660 | data/full_repos/permissive/88762607/状态机实验报告/project_4/project_4.4 dianti/dianti.srcs/sources_1/new/clkdiv.v | 88,762,607 | clkdiv.v | v | 15 | 33 | [] | [] | [] | [(2, 14)] | null | null | 1: b'%Error: Cannot find file containing module: dianti/dianti.srcs/sources_1/new,data/full_repos/permissive/88762607\n ... Looked in:\n data/full_repos/permissive/88762607/\xe7\x8a\xb6\xe6\x80\x81\xe6\x9c\xba\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_4/project_4.4/dianti/dianti.srcs/sources_1/new,data/full_repos/permissive/88762607\n data/full_repos/permissive/88762607/\xe7\x8a\xb6\xe6\x80\x81\xe6\x9c\xba\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_4/project_4.4/dianti/dianti.srcs/sources_1/new,data/full_repos/permissive/88762607.v\n data/full_repos/permissive/88762607/\xe7\x8a\xb6\xe6\x80\x81\xe6\x9c\xba\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_4/project_4.4/dianti/dianti.srcs/sources_1/new,data/full_repos/permissive/88762607.sv\n dianti/dianti.srcs/sources_1/new,data/full_repos/permissive/88762607\n dianti/dianti.srcs/sources_1/new,data/full_repos/permissive/88762607.v\n dianti/dianti.srcs/sources_1/new,data/full_repos/permissive/88762607.sv\n obj_dir/dianti/dianti.srcs/sources_1/new,data/full_repos/permissive/88762607\n obj_dir/dianti/dianti.srcs/sources_1/new,data/full_repos/permissive/88762607.v\n obj_dir/dianti/dianti.srcs/sources_1/new,data/full_repos/permissive/88762607.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/88762607/\xe7\x8a\xb6\xe6\x80\x81\xe6\x9c\xba\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_4/project_4.4\n%Error: Cannot find file containing module: dianti/dianti.srcs/sources_1/new/clkdiv.v\n%Error: Exiting due to 3 error(s)\n' | 305,513 | module | module clkdiv(
input clk100mhz,
output clk1s,
output clk190hz,
output clk200ms
);
reg[31:0] count=0;
assign clk1s = count[26];
assign clk190hz = count[17];
assign clk200ms = count[24];
always @(posedge clk100mhz)
count<=count+1;
endmodule | module clkdiv(
input clk100mhz,
output clk1s,
output clk190hz,
output clk200ms
); |
reg[31:0] count=0;
assign clk1s = count[26];
assign clk190hz = count[17];
assign clk200ms = count[24];
always @(posedge clk100mhz)
count<=count+1;
endmodule | 9 |
139,662 | data/full_repos/permissive/88762607/状态机实验报告/project_4/project_4.4 dianti/dianti.srcs/sources_1/new/top.v | 88,762,607 | top.v | v | 13 | 86 | [] | [] | [] | [(2, 12)] | null | null | 1: b'%Error: Cannot find file containing module: dianti/dianti.srcs/sources_1/new,data/full_repos/permissive/88762607\n ... Looked in:\n data/full_repos/permissive/88762607/\xe7\x8a\xb6\xe6\x80\x81\xe6\x9c\xba\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_4/project_4.4/dianti/dianti.srcs/sources_1/new,data/full_repos/permissive/88762607\n data/full_repos/permissive/88762607/\xe7\x8a\xb6\xe6\x80\x81\xe6\x9c\xba\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_4/project_4.4/dianti/dianti.srcs/sources_1/new,data/full_repos/permissive/88762607.v\n data/full_repos/permissive/88762607/\xe7\x8a\xb6\xe6\x80\x81\xe6\x9c\xba\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_4/project_4.4/dianti/dianti.srcs/sources_1/new,data/full_repos/permissive/88762607.sv\n dianti/dianti.srcs/sources_1/new,data/full_repos/permissive/88762607\n dianti/dianti.srcs/sources_1/new,data/full_repos/permissive/88762607.v\n dianti/dianti.srcs/sources_1/new,data/full_repos/permissive/88762607.sv\n obj_dir/dianti/dianti.srcs/sources_1/new,data/full_repos/permissive/88762607\n obj_dir/dianti/dianti.srcs/sources_1/new,data/full_repos/permissive/88762607.v\n obj_dir/dianti/dianti.srcs/sources_1/new,data/full_repos/permissive/88762607.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/88762607/\xe7\x8a\xb6\xe6\x80\x81\xe6\x9c\xba\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_4/project_4.4\n%Error: Cannot find file containing module: dianti/dianti.srcs/sources_1/new/top.v\n%Error: Exiting due to 3 error(s)\n' | 305,515 | module | module top(
input clk,
input reset,
input up1,input up2,input up3,input dn2,input dn3,input dn4,
input d1,input d2,input d3,input d4,
output [7:0]seg,
output [3:0]pos);
wire clk1s,clk190hz,clk200ms;
clkdiv u0( clk, clk1s,clk190hz,clk200ms);
dianti u1(clk1s,clk190hz,clk200ms,reset,up1,up2,up3,dn2,dn3,dn4,d1,d2,d3,d4,seg,pos);
endmodule | module top(
input clk,
input reset,
input up1,input up2,input up3,input dn2,input dn3,input dn4,
input d1,input d2,input d3,input d4,
output [7:0]seg,
output [3:0]pos); |
wire clk1s,clk190hz,clk200ms;
clkdiv u0( clk, clk1s,clk190hz,clk200ms);
dianti u1(clk1s,clk190hz,clk200ms,reset,up1,up2,up3,dn2,dn3,dn4,d1,d2,d3,d4,seg,pos);
endmodule | 9 |
139,663 | data/full_repos/permissive/88762607/组合逻辑电路实验报告/project_2/project_2.1 mult4/mult4.srcs/sim_1/new/tb.v | 88,762,607 | tb.v | v | 25 | 34 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: Cannot find file containing module: mult4/mult4.srcs/sim_1/new,data/full_repos/permissive/88762607\n ... Looked in:\n data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.1/mult4/mult4.srcs/sim_1/new,data/full_repos/permissive/88762607\n data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.1/mult4/mult4.srcs/sim_1/new,data/full_repos/permissive/88762607.v\n data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.1/mult4/mult4.srcs/sim_1/new,data/full_repos/permissive/88762607.sv\n mult4/mult4.srcs/sim_1/new,data/full_repos/permissive/88762607\n mult4/mult4.srcs/sim_1/new,data/full_repos/permissive/88762607.v\n mult4/mult4.srcs/sim_1/new,data/full_repos/permissive/88762607.sv\n obj_dir/mult4/mult4.srcs/sim_1/new,data/full_repos/permissive/88762607\n obj_dir/mult4/mult4.srcs/sim_1/new,data/full_repos/permissive/88762607.v\n obj_dir/mult4/mult4.srcs/sim_1/new,data/full_repos/permissive/88762607.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.1\n%Error: Cannot find file containing module: mult4/mult4.srcs/sim_1/new/tb.v\n%Error: Exiting due to 3 error(s)\n' | 305,517 | module | module mult4_tb;
reg[3:0] a;
reg[3:0] b;
wire[7:0] p;
mult4 U1(.a(a),.b(b),.p(p));
initial
begin
a=0;
b=0;
repeat(8)
begin
#10 a={$random}%5;
b={$random}%5;
#10 a={$random}%10;
b={$random}%10;
#10 a={$random}%15;
b={$random}%15;
end
end
endmodule | module mult4_tb; |
reg[3:0] a;
reg[3:0] b;
wire[7:0] p;
mult4 U1(.a(a),.b(b),.p(p));
initial
begin
a=0;
b=0;
repeat(8)
begin
#10 a={$random}%5;
b={$random}%5;
#10 a={$random}%10;
b={$random}%10;
#10 a={$random}%15;
b={$random}%15;
end
end
endmodule | 9 |
139,665 | data/full_repos/permissive/88762607/组合逻辑电路实验报告/project_2/project_2.2 mult8/project_1.srcs/sim_1/new/mult8_tb.v | 88,762,607 | mult8_tb.v | v | 19 | 36 | [] | [] | [] | null | line:9: before: "(" | null | 1: b'%Error: Cannot find file containing module: mult8/project_1.srcs/sim_1/new,data/full_repos/permissive/88762607\n ... Looked in:\n data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.2/mult8/project_1.srcs/sim_1/new,data/full_repos/permissive/88762607\n data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.2/mult8/project_1.srcs/sim_1/new,data/full_repos/permissive/88762607.v\n data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.2/mult8/project_1.srcs/sim_1/new,data/full_repos/permissive/88762607.sv\n mult8/project_1.srcs/sim_1/new,data/full_repos/permissive/88762607\n mult8/project_1.srcs/sim_1/new,data/full_repos/permissive/88762607.v\n mult8/project_1.srcs/sim_1/new,data/full_repos/permissive/88762607.sv\n obj_dir/mult8/project_1.srcs/sim_1/new,data/full_repos/permissive/88762607\n obj_dir/mult8/project_1.srcs/sim_1/new,data/full_repos/permissive/88762607.v\n obj_dir/mult8/project_1.srcs/sim_1/new,data/full_repos/permissive/88762607.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.2\n%Error: Cannot find file containing module: mult8/project_1.srcs/sim_1/new/mult8_tb.v\n%Error: Exiting due to 3 error(s)\n' | 305,520 | module | module mult8_tb();
reg[7:0] a;
reg[7:0] b;
wire[15:0] p;
initial
begin
a=0;
b=0;
repeat(10)
begin
#10 a={$random}%255;
b={$random}%255;
end
#10 $stop;
end
mult8 U1(.a(a),.b(b),.p(p));
endmodule | module mult8_tb(); |
reg[7:0] a;
reg[7:0] b;
wire[15:0] p;
initial
begin
a=0;
b=0;
repeat(10)
begin
#10 a={$random}%255;
b={$random}%255;
end
#10 $stop;
end
mult8 U1(.a(a),.b(b),.p(p));
endmodule | 9 |
139,668 | data/full_repos/permissive/88762607/组合逻辑电路实验报告/project_2/project_2.3 div4/project_5.srcs/sources_1/new/div84.v | 88,762,607 | div84.v | v | 70 | 65 | [] | [] | [] | null | line:18: before: "(" | null | 1: b'%Error: Cannot find file containing module: div4/project_5.srcs/sources_1/new,data/full_repos/permissive/88762607\n ... Looked in:\n data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.3/div4/project_5.srcs/sources_1/new,data/full_repos/permissive/88762607\n data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.3/div4/project_5.srcs/sources_1/new,data/full_repos/permissive/88762607.v\n data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.3/div4/project_5.srcs/sources_1/new,data/full_repos/permissive/88762607.sv\n div4/project_5.srcs/sources_1/new,data/full_repos/permissive/88762607\n div4/project_5.srcs/sources_1/new,data/full_repos/permissive/88762607.v\n div4/project_5.srcs/sources_1/new,data/full_repos/permissive/88762607.sv\n obj_dir/div4/project_5.srcs/sources_1/new,data/full_repos/permissive/88762607\n obj_dir/div4/project_5.srcs/sources_1/new,data/full_repos/permissive/88762607.v\n obj_dir/div4/project_5.srcs/sources_1/new,data/full_repos/permissive/88762607.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.3\n%Error: Cannot find file containing module: div4/project_5.srcs/sources_1/new/div84.v\n%Error: Exiting due to 3 error(s)\n' | 305,524 | module | module div84(
input [7:0] numerator,
input [3:0] denominator,
output [7:0] quotient,
output [3:0] remainder
);
wire[7:0] numerator;
wire[3:0] denominator;
reg[7:0] quotient;
reg [3:0] remainder;
reg[3:0] remH;
reg[3:0] remL;
reg[3:0] quotH;
reg[3:0] quotL;
always@(*)
begin
div4({1'b0,numerator[7:4]},denominator,quotH,remH);
div4({remH,numerator[3:0]},denominator,quotL,remL);
quotient[7:4]=quotH;
quotient[3:0]=quotL;
remainder=remL;
end
task div4(
input[7:0] numer,
input[3:0] denom,
output[3:0] quot,
output[3:0] rem);
begin : D4
reg[4:0] d;
reg[4:0] n1;
reg[3:0] n2;
d={1'b0,denom};
n2=numer[3:0];
n1={1'b0,numer[7:4]};
repeat(4)
begin
n1={n1[3:0],n2[3]};
n2={n2[2:0],1'b0};
if(n1>=d)
begin
n1=n1-d;
n2[0]=1;
end
end
quot=n2;
rem=n1[3:0];
end
endtask
endmodule | module div84(
input [7:0] numerator,
input [3:0] denominator,
output [7:0] quotient,
output [3:0] remainder
); |
wire[7:0] numerator;
wire[3:0] denominator;
reg[7:0] quotient;
reg [3:0] remainder;
reg[3:0] remH;
reg[3:0] remL;
reg[3:0] quotH;
reg[3:0] quotL;
always@(*)
begin
div4({1'b0,numerator[7:4]},denominator,quotH,remH);
div4({remH,numerator[3:0]},denominator,quotL,remL);
quotient[7:4]=quotH;
quotient[3:0]=quotL;
remainder=remL;
end
task div4(
input[7:0] numer,
input[3:0] denom,
output[3:0] quot,
output[3:0] rem);
begin : D4
reg[4:0] d;
reg[4:0] n1;
reg[3:0] n2;
d={1'b0,denom};
n2=numer[3:0];
n1={1'b0,numer[7:4]};
repeat(4)
begin
n1={n1[3:0],n2[3]};
n2={n2[2:0],1'b0};
if(n1>=d)
begin
n1=n1-d;
n2[0]=1;
end
end
quot=n2;
rem=n1[3:0];
end
endtask
endmodule | 9 |
139,671 | data/full_repos/permissive/88762607/组合逻辑电路实验报告/project_2/project_2.5.1/project_1.srcs/sim_1/new/test.v | 88,762,607 | test.v | v | 23 | 31 | [] | [] | [] | [(1, 21)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.5.1/project_1.srcs/sim_1/new/test.v:14: Unsupported: Ignoring delay on this delayed statement.\n #20 a=2;b=3;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.5.1/project_1.srcs/sim_1/new/test.v:15: Unsupported: Ignoring delay on this delayed statement.\n #20 a=20;b=44; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.5.1/project_1.srcs/sim_1/new/test.v:16: Unsupported: Ignoring delay on this delayed statement.\n #20 a=25;b=55;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.5.1/project_1.srcs/sim_1/new/test.v:17: Unsupported: Ignoring delay on this delayed statement.\n #20 a=30;b=66;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.5.1/project_1.srcs/sim_1/new/test.v:18: Unsupported: Ignoring delay on this delayed statement.\n #20 a=35;b=77; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.5.1/project_1.srcs/sim_1/new/test.v:20: Unsupported: Ignoring delay on this delayed statement.\n always #22 cin=~cin;\n ^\n%Error: data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.5.1/project_1.srcs/sim_1/new/test.v:7: Cannot find file containing module: \'ripple\'\n ripple U1(a,b,cin,sum,cout);\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.5.1/project_1.srcs/sim_1/new,data/full_repos/permissive/88762607/ripple\n data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.5.1/project_1.srcs/sim_1/new,data/full_repos/permissive/88762607/ripple.v\n data/full_repos/permissive/88762607/\xe7\xbb\x84\xe5\x90\x88\xe9\x80\xbb\xe8\xbe\x91\xe7\x94\xb5\xe8\xb7\xaf\xe5\xae\x9e\xe9\xaa\x8c\xe6\x8a\xa5\xe5\x91\x8a/project_2/project_2.5.1/project_1.srcs/sim_1/new,data/full_repos/permissive/88762607/ripple.sv\n ripple\n ripple.v\n ripple.sv\n obj_dir/ripple\n obj_dir/ripple.v\n obj_dir/ripple.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 305,529 | module | module test;
reg [7:0] a;
reg [7:0] b;
reg cin;
wire [7:0] sum;
wire cout;
ripple U1(a,b,cin,sum,cout);
initial
begin
a=0;b=1;cin=1;
end
always
begin
#20 a=2;b=3;
#20 a=20;b=44;
#20 a=25;b=55;
#20 a=30;b=66;
#20 a=35;b=77;
end
always #22 cin=~cin;
endmodule | module test; |
reg [7:0] a;
reg [7:0] b;
reg cin;
wire [7:0] sum;
wire cout;
ripple U1(a,b,cin,sum,cout);
initial
begin
a=0;b=1;cin=1;
end
always
begin
#20 a=2;b=3;
#20 a=20;b=44;
#20 a=25;b=55;
#20 a=30;b=66;
#20 a=35;b=77;
end
always #22 cin=~cin;
endmodule | 9 |
139,678 | data/full_repos/permissive/88768920/Verilog/FD_Testbench.v | 88,768,920 | FD_Testbench.v | v | 38 | 97 | [] | [] | [] | null | line:36: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/88768920/Verilog/FD_Testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n #10 clock = ~clock;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/88768920/Verilog/FD_Testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n #100 nReset = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/88768920/Verilog/FD_Testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n #100 nReset = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/88768920/Verilog/FD_Testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n #10000000 $finish;\n ^\n%Error: data/full_repos/permissive/88768920/Verilog/FD_Testbench.v:19: Cannot find file containing module: \'FD_Top\'\n FD_Top fd(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/88768920/Verilog,data/full_repos/permissive/88768920/FD_Top\n data/full_repos/permissive/88768920/Verilog,data/full_repos/permissive/88768920/FD_Top.v\n data/full_repos/permissive/88768920/Verilog,data/full_repos/permissive/88768920/FD_Top.sv\n FD_Top\n FD_Top.v\n FD_Top.sv\n obj_dir/FD_Top\n obj_dir/FD_Top.v\n obj_dir/FD_Top.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 305,549 | module | module FD_Testbench;
reg clock;
reg nReset;
wire isCorner;
wire [14:0] refAddr;
wire [7:0] refPixel;
wire [127:0] adjPixel;
wire [7:0] thres;
wire [31:0] compare;
always begin
#10 clock = ~clock;
if (clock && isCorner)
$display($time, " isCorner: %d, refAddr: %d, refPixel: %h", isCorner, refAddr - 1, refPixel);
end
FD_Top fd(
.clock(clock),
.nReset(nReset),
.isCorner(isCorner),
.refAddr(refAddr),
.refPixel(refPixel),
.adjPixel(adjPixel),
.thres(thres),
.compare(compare)
);
initial begin
clock = 1'b0;
nReset = 1'b1;
#100 nReset = 1'b0;
#100 nReset = 1'b1;
#10000000 $finish;
end
endmodule | module FD_Testbench; |
reg clock;
reg nReset;
wire isCorner;
wire [14:0] refAddr;
wire [7:0] refPixel;
wire [127:0] adjPixel;
wire [7:0] thres;
wire [31:0] compare;
always begin
#10 clock = ~clock;
if (clock && isCorner)
$display($time, " isCorner: %d, refAddr: %d, refPixel: %h", isCorner, refAddr - 1, refPixel);
end
FD_Top fd(
.clock(clock),
.nReset(nReset),
.isCorner(isCorner),
.refAddr(refAddr),
.refPixel(refPixel),
.adjPixel(adjPixel),
.thres(thres),
.compare(compare)
);
initial begin
clock = 1'b0;
nReset = 1'b1;
#100 nReset = 1'b0;
#100 nReset = 1'b1;
#10000000 $finish;
end
endmodule | 31 |
139,679 | data/full_repos/permissive/88951410/src/quick_spi_hard.v | 88,951,410 | quick_spi_hard.v | v | 221 | 123 | [] | [] | [] | null | line:200: before: "(" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_hard.v:123: Operator FUNCREF \'put_data\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'outgoing_data\' generates 16 bits.\n : ... In instance quick_spi_hard\n intermediate_buffer = put_data(outgoing_data, BYTES_ORDER);\n ^~~~~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_hard.v:132: Bit extraction of var[1:0] requires 1 bit index, not 2 bits.\n : ... In instance quick_spi_hard\n ss_n[slave] <= 1\'b0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_hard.v:135: Bit extraction of var[1:0] requires 1 bit index, not 2 bits.\n : ... In instance quick_spi_hard\n if(ss_n[slave] == 1\'b0) \n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_hard.v:177: Bit extraction of var[1:0] requires 1 bit index, not 2 bits.\n : ... In instance quick_spi_hard\n ss_n[slave] <= 1\'b1;\n ^\n%Error: Exiting due to 4 warning(s)\n' | 305,573 | module | module quick_spi_hard #
(
parameter NUMBER_OF_SLAVES = 2,
parameter INCOMING_DATA_WIDTH = 8,
parameter OUTGOING_DATA_WIDTH = 16,
parameter BITS_ORDER = `MSB_FIRST,
parameter BYTES_ORDER = `LITTLE_ENDIAN,
parameter EXTRA_WRITE_SCLK_TOGGLES = 6,
parameter EXTRA_READ_SCLK_TOGGLES = 4,
parameter CPOL = 0,
parameter CPHA = 0,
parameter MOSI_IDLE_VALUE = 1'b0
)
(
input wire clk,
input wire reset_n,
input wire enable,
input wire start_transaction,
input wire[NUMBER_OF_SLAVES-1:0] slave,
input wire operation,
output reg end_of_transaction,
output reg[INCOMING_DATA_WIDTH-1:0] incoming_data,
input wire[OUTGOING_DATA_WIDTH-1:0] outgoing_data,
output reg mosi,
input wire miso,
output reg sclk,
output reg[NUMBER_OF_SLAVES-1:0] ss_n);
localparam READ = 1'b0;
localparam WRITE = 1'b1;
localparam READ_SCLK_TOGGLES = (INCOMING_DATA_WIDTH * 2) + 2;
localparam ALL_READ_TOGGLES = EXTRA_READ_SCLK_TOGGLES + READ_SCLK_TOGGLES;
localparam NUMBER_OF_FULL_BYTES = OUTGOING_DATA_WIDTH > 1 ? (OUTGOING_DATA_WIDTH / 8) : 0;
localparam NUMBER_OF_PARTICULAR_BITS = OUTGOING_DATA_WIDTH > (NUMBER_OF_FULL_BYTES * 8) ? 1 : 0;
localparam NUMBER_OF_BYTES = NUMBER_OF_FULL_BYTES + NUMBER_OF_PARTICULAR_BITS;
localparam MAX_BYTES_INDEX = NUMBER_OF_BYTES - 1;
integer sclk_toggle_count;
integer transaction_toggles;
reg spi_clock_phase;
reg[1:0] state;
localparam IDLE = 2'b00;
localparam ACTIVE = 2'b01;
localparam WAIT = 2'b10;
reg[INCOMING_DATA_WIDTH - 1:0] incoming_data_buffer;
reg[OUTGOING_DATA_WIDTH - 1:0] outgoing_data_buffer;
reg[`MAX_DATA_WIDTH - 1:0] intermediate_buffer;
reg[2:0] bit_counter;
reg[3:0] byte_counter;
always @ (posedge clk)
begin
if(!reset_n)
begin
end_of_transaction <= 1'b0;
mosi <= MOSI_IDLE_VALUE;
sclk <= CPOL;
ss_n <= {NUMBER_OF_SLAVES{1'b1}};
sclk_toggle_count <= 0;
transaction_toggles <= 0;
spi_clock_phase <= ~CPHA;
incoming_data <= {INCOMING_DATA_WIDTH{1'b0}};
incoming_data_buffer <= {INCOMING_DATA_WIDTH{1'b0}};
outgoing_data_buffer <= {OUTGOING_DATA_WIDTH{1'b0}};
state <= IDLE;
bit_counter <= 0;
byte_counter <= 0;
end
else begin
case(state)
IDLE:
begin
if(enable)
begin
bit_counter <= 0;
byte_counter <= 0;
if(start_transaction)
begin
transaction_toggles <= (operation == READ) ? ALL_READ_TOGGLES : EXTRA_WRITE_SCLK_TOGGLES;
intermediate_buffer = put_data(outgoing_data, BYTES_ORDER);
outgoing_data_buffer <= intermediate_buffer[15:0];
state <= ACTIVE;
end
end
end
ACTIVE:
begin
ss_n[slave] <= 1'b0;
spi_clock_phase <= ~spi_clock_phase;
if(ss_n[slave] == 1'b0)
begin
if(sclk_toggle_count < (OUTGOING_DATA_WIDTH * 2) + transaction_toggles)
begin
sclk <= ~sclk;
sclk_toggle_count <= sclk_toggle_count + 1;
end
end
if(spi_clock_phase == 1'b0)
begin
if(operation == READ)
begin
if(sclk_toggle_count > ((OUTGOING_DATA_WIDTH * 2) + EXTRA_READ_SCLK_TOGGLES)-1)
begin
incoming_data_buffer <= incoming_data_buffer >> 1;
incoming_data_buffer[INCOMING_DATA_WIDTH-1] <= miso;
end
end
end
else
begin
if(sclk_toggle_count < (OUTGOING_DATA_WIDTH * 2) - 1)
begin
if(BITS_ORDER == `LSB_FIRST)
begin
mosi <= outgoing_data_buffer[0];
outgoing_data_buffer <= outgoing_data_buffer >> 1;
end
else
begin
bit_counter <= bit_counter + 1;
mosi <= outgoing_data_buffer[7 - bit_counter];
if(bit_counter == 7)
outgoing_data_buffer <= outgoing_data_buffer >> 8;
end
end
end
if(sclk_toggle_count == (OUTGOING_DATA_WIDTH * 2) + transaction_toggles)
begin
ss_n[slave] <= 1'b1;
mosi <= MOSI_IDLE_VALUE;
incoming_data <= incoming_data_buffer;
incoming_data_buffer <= {INCOMING_DATA_WIDTH{1'b0}};
outgoing_data_buffer <= {OUTGOING_DATA_WIDTH{1'b0}};
sclk <= CPOL;
spi_clock_phase <= ~CPHA;
sclk_toggle_count <= 0;
end_of_transaction <= 1'b1;
state <= WAIT;
end
end
WAIT:
begin
incoming_data <= {INCOMING_DATA_WIDTH{1'b0}};
end_of_transaction <= 1'b0;
state <= IDLE;
end
endcase
end
end
function [`MAX_DATA_WIDTH - 1:0] put_data(input reg [`MAX_DATA_WIDTH - 1 : 0] data, input reg order);
reg [`MAX_DATA_WIDTH - 1:0] result;
reg[7:0] shift;
begin
shift = `MAX_DATA_WIDTH - NUMBER_OF_BYTES * 8;
if (order == `BIG_ENDIAN)
begin
result = {data[7:0], data[15:8], data[23:16], data[31:24], data[39:32], data[47:40], data[55:48], data[63:56]};
if(shift > 0)
put_data = result >> shift;
else put_data = result;
end
else if (order == `LITTLE_ENDIAN)
begin
put_data = data;
end
end
endfunction
endmodule | module quick_spi_hard #
(
parameter NUMBER_OF_SLAVES = 2,
parameter INCOMING_DATA_WIDTH = 8,
parameter OUTGOING_DATA_WIDTH = 16,
parameter BITS_ORDER = `MSB_FIRST,
parameter BYTES_ORDER = `LITTLE_ENDIAN,
parameter EXTRA_WRITE_SCLK_TOGGLES = 6,
parameter EXTRA_READ_SCLK_TOGGLES = 4,
parameter CPOL = 0,
parameter CPHA = 0,
parameter MOSI_IDLE_VALUE = 1'b0
)
(
input wire clk,
input wire reset_n,
input wire enable,
input wire start_transaction,
input wire[NUMBER_OF_SLAVES-1:0] slave,
input wire operation,
output reg end_of_transaction,
output reg[INCOMING_DATA_WIDTH-1:0] incoming_data,
input wire[OUTGOING_DATA_WIDTH-1:0] outgoing_data,
output reg mosi,
input wire miso,
output reg sclk,
output reg[NUMBER_OF_SLAVES-1:0] ss_n); |
localparam READ = 1'b0;
localparam WRITE = 1'b1;
localparam READ_SCLK_TOGGLES = (INCOMING_DATA_WIDTH * 2) + 2;
localparam ALL_READ_TOGGLES = EXTRA_READ_SCLK_TOGGLES + READ_SCLK_TOGGLES;
localparam NUMBER_OF_FULL_BYTES = OUTGOING_DATA_WIDTH > 1 ? (OUTGOING_DATA_WIDTH / 8) : 0;
localparam NUMBER_OF_PARTICULAR_BITS = OUTGOING_DATA_WIDTH > (NUMBER_OF_FULL_BYTES * 8) ? 1 : 0;
localparam NUMBER_OF_BYTES = NUMBER_OF_FULL_BYTES + NUMBER_OF_PARTICULAR_BITS;
localparam MAX_BYTES_INDEX = NUMBER_OF_BYTES - 1;
integer sclk_toggle_count;
integer transaction_toggles;
reg spi_clock_phase;
reg[1:0] state;
localparam IDLE = 2'b00;
localparam ACTIVE = 2'b01;
localparam WAIT = 2'b10;
reg[INCOMING_DATA_WIDTH - 1:0] incoming_data_buffer;
reg[OUTGOING_DATA_WIDTH - 1:0] outgoing_data_buffer;
reg[`MAX_DATA_WIDTH - 1:0] intermediate_buffer;
reg[2:0] bit_counter;
reg[3:0] byte_counter;
always @ (posedge clk)
begin
if(!reset_n)
begin
end_of_transaction <= 1'b0;
mosi <= MOSI_IDLE_VALUE;
sclk <= CPOL;
ss_n <= {NUMBER_OF_SLAVES{1'b1}};
sclk_toggle_count <= 0;
transaction_toggles <= 0;
spi_clock_phase <= ~CPHA;
incoming_data <= {INCOMING_DATA_WIDTH{1'b0}};
incoming_data_buffer <= {INCOMING_DATA_WIDTH{1'b0}};
outgoing_data_buffer <= {OUTGOING_DATA_WIDTH{1'b0}};
state <= IDLE;
bit_counter <= 0;
byte_counter <= 0;
end
else begin
case(state)
IDLE:
begin
if(enable)
begin
bit_counter <= 0;
byte_counter <= 0;
if(start_transaction)
begin
transaction_toggles <= (operation == READ) ? ALL_READ_TOGGLES : EXTRA_WRITE_SCLK_TOGGLES;
intermediate_buffer = put_data(outgoing_data, BYTES_ORDER);
outgoing_data_buffer <= intermediate_buffer[15:0];
state <= ACTIVE;
end
end
end
ACTIVE:
begin
ss_n[slave] <= 1'b0;
spi_clock_phase <= ~spi_clock_phase;
if(ss_n[slave] == 1'b0)
begin
if(sclk_toggle_count < (OUTGOING_DATA_WIDTH * 2) + transaction_toggles)
begin
sclk <= ~sclk;
sclk_toggle_count <= sclk_toggle_count + 1;
end
end
if(spi_clock_phase == 1'b0)
begin
if(operation == READ)
begin
if(sclk_toggle_count > ((OUTGOING_DATA_WIDTH * 2) + EXTRA_READ_SCLK_TOGGLES)-1)
begin
incoming_data_buffer <= incoming_data_buffer >> 1;
incoming_data_buffer[INCOMING_DATA_WIDTH-1] <= miso;
end
end
end
else
begin
if(sclk_toggle_count < (OUTGOING_DATA_WIDTH * 2) - 1)
begin
if(BITS_ORDER == `LSB_FIRST)
begin
mosi <= outgoing_data_buffer[0];
outgoing_data_buffer <= outgoing_data_buffer >> 1;
end
else
begin
bit_counter <= bit_counter + 1;
mosi <= outgoing_data_buffer[7 - bit_counter];
if(bit_counter == 7)
outgoing_data_buffer <= outgoing_data_buffer >> 8;
end
end
end
if(sclk_toggle_count == (OUTGOING_DATA_WIDTH * 2) + transaction_toggles)
begin
ss_n[slave] <= 1'b1;
mosi <= MOSI_IDLE_VALUE;
incoming_data <= incoming_data_buffer;
incoming_data_buffer <= {INCOMING_DATA_WIDTH{1'b0}};
outgoing_data_buffer <= {OUTGOING_DATA_WIDTH{1'b0}};
sclk <= CPOL;
spi_clock_phase <= ~CPHA;
sclk_toggle_count <= 0;
end_of_transaction <= 1'b1;
state <= WAIT;
end
end
WAIT:
begin
incoming_data <= {INCOMING_DATA_WIDTH{1'b0}};
end_of_transaction <= 1'b0;
state <= IDLE;
end
endcase
end
end
function [`MAX_DATA_WIDTH - 1:0] put_data(input reg [`MAX_DATA_WIDTH - 1 : 0] data, input reg order);
reg [`MAX_DATA_WIDTH - 1:0] result;
reg[7:0] shift;
begin
shift = `MAX_DATA_WIDTH - NUMBER_OF_BYTES * 8;
if (order == `BIG_ENDIAN)
begin
result = {data[7:0], data[15:8], data[23:16], data[31:24], data[39:32], data[47:40], data[55:48], data[63:56]};
if(shift > 0)
put_data = result >> shift;
else put_data = result;
end
else if (order == `LITTLE_ENDIAN)
begin
put_data = data;
end
end
endfunction
endmodule | 14 |
139,680 | data/full_repos/permissive/88951410/src/quick_spi_hard.v | 88,951,410 | quick_spi_hard.v | v | 221 | 123 | [] | [] | [] | null | line:200: before: "(" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_hard.v:123: Operator FUNCREF \'put_data\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'outgoing_data\' generates 16 bits.\n : ... In instance quick_spi_hard\n intermediate_buffer = put_data(outgoing_data, BYTES_ORDER);\n ^~~~~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_hard.v:132: Bit extraction of var[1:0] requires 1 bit index, not 2 bits.\n : ... In instance quick_spi_hard\n ss_n[slave] <= 1\'b0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_hard.v:135: Bit extraction of var[1:0] requires 1 bit index, not 2 bits.\n : ... In instance quick_spi_hard\n if(ss_n[slave] == 1\'b0) \n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_hard.v:177: Bit extraction of var[1:0] requires 1 bit index, not 2 bits.\n : ... In instance quick_spi_hard\n ss_n[slave] <= 1\'b1;\n ^\n%Error: Exiting due to 4 warning(s)\n' | 305,573 | function | function [`MAX_DATA_WIDTH - 1:0] put_data(input reg [`MAX_DATA_WIDTH - 1 : 0] data, input reg order);
reg [`MAX_DATA_WIDTH - 1:0] result;
reg[7:0] shift;
begin
shift = `MAX_DATA_WIDTH - NUMBER_OF_BYTES * 8;
if (order == `BIG_ENDIAN)
begin
result = {data[7:0], data[15:8], data[23:16], data[31:24], data[39:32], data[47:40], data[55:48], data[63:56]};
if(shift > 0)
put_data = result >> shift;
else put_data = result;
end
else if (order == `LITTLE_ENDIAN)
begin
put_data = data;
end
end
endfunction | function [`MAX_DATA_WIDTH - 1:0] put_data(input reg [`MAX_DATA_WIDTH - 1 : 0] data, input reg order); |
reg [`MAX_DATA_WIDTH - 1:0] result;
reg[7:0] shift;
begin
shift = `MAX_DATA_WIDTH - NUMBER_OF_BYTES * 8;
if (order == `BIG_ENDIAN)
begin
result = {data[7:0], data[15:8], data[23:16], data[31:24], data[39:32], data[47:40], data[55:48], data[63:56]};
if(shift > 0)
put_data = result >> shift;
else put_data = result;
end
else if (order == `LITTLE_ENDIAN)
begin
put_data = data;
end
end
endfunction | 14 |
139,681 | data/full_repos/permissive/88951410/src/quick_spi_soft.v | 88,951,410 | quick_spi_soft.v | v | 617 | 125 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/88951410/src/quick_spi_soft.v:29: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [C_S_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/88951410/src/quick_spi_soft.v:35: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [C_S_AXI_WUSER_WIDTH-1:0] s_axi_wuser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/88951410/src/quick_spi_soft.v:40: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [C_S_AXI_BUSER_WIDTH-1:0] s_axi_buser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/88951410/src/quick_spi_soft.v:53: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [C_S_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/88951410/src/quick_spi_soft.v:60: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [C_S_AXI_RUSER_WIDTH-1:0] s_axi_ruser,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/88951410/src/quick_spi_soft.v:74: Little bit endian vector: MSB < LSB of bit range: -1:0\nreg [C_S_AXI_BUSER_WIDTH-1:0] axi_buser;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/88951410/src/quick_spi_soft.v:81: Little bit endian vector: MSB < LSB of bit range: -1:0\nreg [C_S_AXI_RUSER_WIDTH-1:0] axi_ruser;\n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:119: Operator AND expects 32 bits on the LHS, but LHS\'s VARREF \'axi_awaddr\' generates 8 bits.\n : ... In instance quick_spi_soft\nassign aw_wrap_en = ((axi_awaddr & aw_wrap_size) == aw_wrap_size)? 1\'b1: 1\'b0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:120: Operator AND expects 32 bits on the LHS, but LHS\'s VARREF \'axi_araddr\' generates 8 bits.\n : ... In instance quick_spi_soft\nassign ar_wrap_en = ((axi_araddr & ar_wrap_size) == ar_wrap_size)? 1\'b1: 1\'b0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:176: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'axi_awaddr\' generates 8 bits.\n : ... In instance quick_spi_soft\n axi_awaddr <= (axi_awaddr - aw_wrap_size); \n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:176: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n : ... In instance quick_spi_soft\n axi_awaddr <= (axi_awaddr - aw_wrap_size); \n ^~\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:185: Operator ADD expects 32 or 8 bits on the LHS, but LHS\'s SEL generates 6 bits.\n : ... In instance quick_spi_soft\n axi_awaddr <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:284: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'axi_araddr\' generates 8 bits.\n : ... In instance quick_spi_soft\n axi_araddr <= (axi_araddr - ar_wrap_size); \n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:284: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n : ... In instance quick_spi_soft\n axi_araddr <= (axi_araddr - ar_wrap_size); \n ^~\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:292: Operator ADD expects 32 or 8 bits on the LHS, but LHS\'s SEL generates 6 bits.\n : ... In instance quick_spi_soft\n axi_araddr <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB]+1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:420: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance quick_spi_soft\n num_initial_axi_transfer_bytes_received + s_axi_wstrb[0] + s_axi_wstrb[1] + s_axi_wstrb[2] + s_axi_wstrb[3];\n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:420: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance quick_spi_soft\n num_initial_axi_transfer_bytes_received + s_axi_wstrb[0] + s_axi_wstrb[1] + s_axi_wstrb[2] + s_axi_wstrb[3];\n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:420: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance quick_spi_soft\n num_initial_axi_transfer_bytes_received + s_axi_wstrb[0] + s_axi_wstrb[1] + s_axi_wstrb[2] + s_axi_wstrb[3];\n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:420: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance quick_spi_soft\n num_initial_axi_transfer_bytes_received + s_axi_wstrb[0] + s_axi_wstrb[1] + s_axi_wstrb[2] + s_axi_wstrb[3];\n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:437: Bit extraction of var[1:0] requires 1 bit index, not 8 bits.\n : ... In instance quick_spi_soft\n ss_n[slave] <= 1\'b0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:441: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n : ... In instance quick_spi_soft\n mosi <= memory[write_buffer_start + num_bytes_written][outgoing_byte_bit];\n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:448: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'num_write_extra_toggles\' generates 16 bits.\n : ... In instance quick_spi_soft\n if(!num_write_extra_toggles) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:489: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n : ... In instance quick_spi_soft\n mosi <= memory[write_buffer_start + num_bytes_written][outgoing_byte_bit];\n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:497: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'num_write_extra_toggles\' generates 16 bits.\n : ... In instance quick_spi_soft\n if(!num_write_extra_toggles)\n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:508: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'num_write_extra_toggles\' generates 16 bits.\n : ... In instance quick_spi_soft\n if(!num_write_extra_toggles)\n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:529: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n : ... In instance quick_spi_soft\n memory[read_buffer_start + num_bytes_read][incoming_byte_bit] <= miso;\n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:533: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'num_read_extra_toggles\' generates 16 bits.\n : ... In instance quick_spi_soft\n if(!num_read_extra_toggles)\n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:569: Bit extraction of var[1:0] requires 1 bit index, not 8 bits.\n : ... In instance quick_spi_soft\n ss_n[slave] <= 1\'b1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/88951410/src/quick_spi_soft.v:425: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'num_clocks_to_skip\' generates 8 bits.\n : ... In instance quick_spi_soft\n if(clock_count == num_clocks_to_skip) begin\n ^~\n%Error: Exiting due to 29 warning(s)\n' | 305,574 | module | module quick_spi_soft #
(
parameter integer C_S_AXI_ID_WIDTH = 1,
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter integer C_S_AXI_ADDR_WIDTH = 8,
parameter integer C_S_AXI_AWUSER_WIDTH = 0,
parameter integer C_S_AXI_ARUSER_WIDTH = 0,
parameter integer C_S_AXI_WUSER_WIDTH = 0,
parameter integer C_S_AXI_RUSER_WIDTH = 0,
parameter integer C_S_AXI_BUSER_WIDTH = 0,
parameter integer MEMORY_SIZE = 64,
parameter integer NUMBER_OF_SLAVES = 2
)
(
input wire s_axi_aclk,
input wire s_axi_aresetn,
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [7:0] s_axi_awlen,
input wire [2:0] s_axi_awsize,
input wire [1:0] s_axi_awburst,
input wire s_axi_awlock,
input wire [3:0] s_axi_awcache,
input wire [2:0] s_axi_awprot,
input wire [3:0] s_axi_awqos,
input wire [3:0] s_axi_awregion,
input wire [C_S_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire s_axi_awvalid,
output wire s_axi_awready,
input wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_S_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire s_axi_wvalid,
output wire s_axi_wready,
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [1:0] s_axi_bresp,
output wire [C_S_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire s_axi_bvalid,
input wire s_axi_bready,
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [7:0] s_axi_arlen,
input wire [2:0] s_axi_arsize,
input wire [1:0] s_axi_arburst,
input wire s_axi_arlock,
input wire [3:0] s_axi_arcache,
input wire [2:0] s_axi_arprot,
input wire [3:0] s_axi_arqos,
input wire [3:0] s_axi_arregion,
input wire [C_S_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire s_axi_arvalid,
output wire s_axi_arready,
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_S_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire s_axi_rvalid,
input wire s_axi_rready,
output reg mosi,
input wire miso,
output reg sclk,
output reg[NUMBER_OF_SLAVES-1:0] ss_n,
output reg interrupt
);
reg [C_S_AXI_ADDR_WIDTH-1:0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1:0] axi_bresp;
reg [C_S_AXI_BUSER_WIDTH-1:0] axi_buser;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1:0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1:0] axi_rdata;
reg [1:0] axi_rresp;
reg axi_rlast;
reg [C_S_AXI_RUSER_WIDTH-1:0] axi_ruser;
reg axi_rvalid;
wire aw_wrap_en;
wire ar_wrap_en;
wire [31:0] aw_wrap_size;
wire [31:0] ar_wrap_size;
reg axi_awv_awr_flag;
reg axi_arv_arr_flag;
reg [7:0] axi_awlen_cntr;
reg [7:0] axi_arlen_cntr;
reg [1:0] axi_arburst;
reg [1:0] axi_awburst;
reg [7:0] axi_arlen;
reg [7:0] axi_awlen;
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32)+ 1;
localparam integer OPT_MEM_ADDR_BITS = 3;
wire [OPT_MEM_ADDR_BITS:0] memory_address;
reg [C_S_AXI_DATA_WIDTH-1:0] outgoing_data;
assign s_axi_awready = axi_awready;
assign s_axi_wready = axi_wready;
assign s_axi_bresp = axi_bresp;
assign s_axi_buser = axi_buser;
assign s_axi_bvalid = axi_bvalid;
assign s_axi_arready = axi_arready;
assign s_axi_rdata = axi_rdata;
assign s_axi_rresp = axi_rresp;
assign s_axi_rlast = axi_rlast;
assign s_axi_ruser = axi_ruser;
assign s_axi_rvalid = axi_rvalid;
assign s_axi_bid = s_axi_awid;
assign s_axi_rid = s_axi_arid;
assign aw_wrap_size = (C_S_AXI_DATA_WIDTH/8 * (axi_awlen));
assign ar_wrap_size = (C_S_AXI_DATA_WIDTH/8 * (axi_arlen));
assign aw_wrap_en = ((axi_awaddr & aw_wrap_size) == aw_wrap_size)? 1'b1: 1'b0;
assign ar_wrap_en = ((axi_araddr & ar_wrap_size) == ar_wrap_size)? 1'b1: 1'b0;
assign s_axi_buser = 0;
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
axi_awready <= 1'b0;
axi_awv_awr_flag <= 1'b0;
end
else begin
if (~axi_awready && s_axi_awvalid && ~axi_awv_awr_flag && ~axi_arv_arr_flag) begin
axi_awready <= 1'b1;
axi_awv_awr_flag <= 1'b1;
end
else if (s_axi_wlast && axi_wready) begin
axi_awv_awr_flag <= 1'b0;
end
else begin
axi_awready <= 1'b0;
end
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
axi_awaddr <= 0;
axi_awlen_cntr <= 0;
axi_awburst <= 0;
axi_awlen <= 0;
end
else begin
if (~axi_awready && s_axi_awvalid && ~axi_awv_awr_flag) begin
axi_awaddr <= s_axi_awaddr[C_S_AXI_ADDR_WIDTH-1:0];
axi_awburst <= s_axi_awburst;
axi_awlen <= s_axi_awlen;
axi_awlen_cntr <= 0;
end
else if((axi_awlen_cntr <= axi_awlen) && axi_wready && s_axi_wvalid) begin
axi_awlen_cntr <= axi_awlen_cntr + 1;
case (axi_awburst)
2'b00: begin
axi_awaddr <= axi_awaddr;
end
2'b01: begin
axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
axi_awaddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
end
2'b10:
if (aw_wrap_en) begin
axi_awaddr <= (axi_awaddr - aw_wrap_size);
end
else begin
axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
axi_awaddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
end
default: begin
axi_awaddr <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
end
endcase
end
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
axi_wready <= 1'b0;
end
else begin
if (~axi_wready && s_axi_wvalid && axi_awv_awr_flag) begin
axi_wready <= 1'b1;
end
else if (s_axi_wlast && axi_wready) begin
axi_wready <= 1'b0;
end
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else begin
if (axi_awv_awr_flag && axi_wready && s_axi_wvalid && ~axi_bvalid && s_axi_wlast) begin
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0;
end
else begin
if (s_axi_bready && axi_bvalid) begin
axi_bvalid <= 1'b0;
end
end
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
axi_arready <= 1'b0;
axi_arv_arr_flag <= 1'b0;
end
else begin
if (~axi_arready && s_axi_arvalid && ~axi_awv_awr_flag && ~axi_arv_arr_flag) begin
axi_arready <= 1'b1;
axi_arv_arr_flag <= 1'b1;
end
else if (axi_rvalid && s_axi_rready && axi_arlen_cntr == axi_arlen) begin
axi_arv_arr_flag <= 1'b0;
end
else begin
axi_arready <= 1'b0;
end
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
axi_araddr <= 0;
axi_arlen_cntr <= 0;
axi_arburst <= 0;
axi_arlen <= 0;
axi_rlast <= 1'b0;
end
else begin
if (~axi_arready && s_axi_arvalid && ~axi_arv_arr_flag) begin
axi_araddr <= s_axi_araddr[C_S_AXI_ADDR_WIDTH - 1:0];
axi_arburst <= s_axi_arburst;
axi_arlen <= s_axi_arlen;
axi_arlen_cntr <= 0;
axi_rlast <= 1'b0;
end
else if((axi_arlen_cntr <= axi_arlen) && axi_rvalid && s_axi_rready) begin
axi_arlen_cntr <= axi_arlen_cntr + 1;
axi_rlast <= 1'b0;
case (axi_arburst)
2'b00: begin
axi_araddr <= axi_araddr;
end
2'b01: begin
axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
axi_araddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
end
2'b10:
if (ar_wrap_en) begin
axi_araddr <= (axi_araddr - ar_wrap_size);
end
else begin
axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
axi_araddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
end
default: begin
axi_araddr <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB]+1;
end
endcase
end
else if((axi_arlen_cntr == axi_arlen) && ~axi_rlast && axi_arv_arr_flag) begin
axi_rlast <= 1'b1;
end
else if (s_axi_rready) begin
axi_rlast <= 1'b0;
end
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else begin
if (axi_arv_arr_flag && ~axi_rvalid) begin
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0;
end
else if (axi_rvalid && s_axi_rready) begin
axi_rvalid <= 1'b0;
end
end
end
assign memory_address =
(axi_arv_arr_flag ?
axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] :
(axi_awv_awr_flag? axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]:0));
wire memory_write_enable = axi_wready && s_axi_wvalid;
wire memory_read_enable = axi_arv_arr_flag;
reg[15:0] sclk_toggle_count;
reg spi_clock_phase;
localparam SM1_IDLE = 2'b00;
localparam SM1_SELECT_SLAVE = 2'b01;
localparam SM1_TRANSFER_DATA = 2'b10;
reg[1:0] sm1_state;
localparam SM2_WRITE = 2'b00;
localparam SM2_READ = 2'b01;
localparam SM2_WAIT = 2'b10;
localparam SM2_END_DATA_TRANSFER = 2'b11;
reg[1:0] sm2_state;
reg wait_after_read;
reg[15:0] num_toggles_to_wait;
reg [7:0] memory [0:MEMORY_SIZE-1];
wire CPOL = memory[0][0];
wire CPHA = memory[0][1];
wire burst = memory[0][3];
wire read = memory[0][4];
wire[7:0] slave = memory[1];
wire[7:0] num_clocks_to_skip = memory[2];
wire[15:0] outgoing_element_size = {memory[5], memory[4]};
wire[15:0] num_outgoing_elements = {memory[7], memory[6]};
wire[15:0] incoming_element_size = {memory[9], memory[8]};
wire[15:0] num_write_extra_toggles = {memory[11], memory[10]};
wire[15:0] num_read_extra_toggles = {memory[13], memory[12]};
reg[15:0] num_bits_read;
reg[15:0] num_bits_written;
reg[15:0] num_elements_written;
reg[3:0] incoming_byte_bit;
reg[3:0] outgoing_byte_bit;
reg[15:0] num_bytes_read;
reg[15:0] num_bytes_written;
localparam write_buffer_start = 14;
localparam read_buffer_start = 39;
localparam num_initial_axi_transfer_bytes = read_buffer_start;
reg[15:0] extra_toggle_count;
integer num_initial_axi_transfer_bytes_received;
integer i;
integer clock_count;
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
for (i = 0; i < MEMORY_SIZE - 1; i = i + 1)
memory[i] <= 0;
clock_count <= 0;
num_initial_axi_transfer_bytes_received <= 0;
num_elements_written <= 0;
num_bits_read <= 0;
num_bits_written <= 0;
incoming_byte_bit <= 0;
outgoing_byte_bit <= 0;
num_bytes_read <= 0;
num_bytes_written <= 0;
extra_toggle_count <= 0;
wait_after_read <= 1'b0;
mosi <= 1'bz;
sclk <= 0;
ss_n <= {NUMBER_OF_SLAVES{1'b1}};
sclk_toggle_count <= 0;
spi_clock_phase <= 0;
interrupt <= 1'b0;
sm1_state <= SM1_IDLE;
sm2_state <= SM2_WRITE;
end
else begin
if(memory_write_enable) begin
if (s_axi_wstrb[0])
memory[(memory_address*4) + 0] <= s_axi_wdata[(0*8+7) -: 8];
if (s_axi_wstrb[1])
memory[(memory_address*4) + 1] <= s_axi_wdata[(1*8+7) -: 8];
if (s_axi_wstrb[2])
memory[(memory_address*4) + 2] <= s_axi_wdata[(2*8+7) -: 8];
if (s_axi_wstrb[3])
memory[(memory_address*4) + 3] <= s_axi_wdata[(3*8+7) -: 8];
num_initial_axi_transfer_bytes_received <=
num_initial_axi_transfer_bytes_received + s_axi_wstrb[0] + s_axi_wstrb[1] + s_axi_wstrb[2] + s_axi_wstrb[3];
end
else begin
if(num_initial_axi_transfer_bytes_received == read_buffer_start) begin
if(clock_count == num_clocks_to_skip) begin
clock_count <= 0;
case(sm1_state)
SM1_IDLE: begin
sclk <= CPOL;
spi_clock_phase <= CPHA;
interrupt <= 1'b0;
sm1_state <= SM1_SELECT_SLAVE;
end
SM1_SELECT_SLAVE: begin
ss_n[slave] <= 1'b0;
if(!CPHA) begin
outgoing_byte_bit <= outgoing_byte_bit + 1;
mosi <= memory[write_buffer_start + num_bytes_written][outgoing_byte_bit];
num_bits_written <= num_bits_written + 1;
if(outgoing_element_size == 1) begin
num_elements_written <= 1;
if(num_outgoing_elements == 1) begin
if(!num_write_extra_toggles) begin
if(read)
sm2_state <= SM2_READ;
else
sm2_state <= SM2_END_DATA_TRANSFER;
end
else
sm2_state <= SM2_WAIT;
end
else begin
if(read)
sm2_state <= SM2_READ;
else
sm2_state <= SM2_WRITE;
end
end
else
sm2_state <= SM2_WRITE;
end
sm1_state <= SM1_TRANSFER_DATA;
end
SM1_TRANSFER_DATA: begin
sclk <= ~sclk;
spi_clock_phase <= ~spi_clock_phase;
sclk_toggle_count <= sclk_toggle_count + 1;
case(sm2_state)
SM2_WRITE: begin
if(spi_clock_phase) begin
outgoing_byte_bit <= outgoing_byte_bit + 1;
if(outgoing_byte_bit == 7) begin
num_bytes_written <= num_bytes_written + 1;
outgoing_byte_bit <= 0;
end
mosi <= memory[write_buffer_start + num_bytes_written][outgoing_byte_bit];
num_bits_written <= num_bits_written + 1;
if(num_bits_written == outgoing_element_size - 1) begin
num_elements_written <= num_elements_written + 1;
if(burst) begin
if(num_elements_written == num_outgoing_elements - 1) begin
if(!num_write_extra_toggles)
sm2_state <= SM2_END_DATA_TRANSFER;
else
sm2_state <= SM2_WAIT;
end
else
num_bits_written <= 0;
end
else begin
if(!num_write_extra_toggles)
if(read)
sm2_state <= SM2_READ;
else
sm2_state <= SM2_END_DATA_TRANSFER;
else
sm2_state <= SM2_WAIT;
end
end
end
end
SM2_READ: begin
if(!spi_clock_phase) begin
incoming_byte_bit <= incoming_byte_bit + 1;
if(incoming_byte_bit == 7) begin
num_bytes_read <= num_bytes_read + 1;
incoming_byte_bit <= 0;
end
memory[read_buffer_start + num_bytes_read][incoming_byte_bit] <= miso;
num_bits_read <= num_bits_read + 1;
if(num_bits_read == incoming_element_size - 1) begin
if(!num_read_extra_toggles)
sm2_state <= SM2_END_DATA_TRANSFER;
else begin
wait_after_read <= 1'b1;
sm2_state <= SM2_WAIT;
end
end
end
end
SM2_WAIT: begin
extra_toggle_count <= extra_toggle_count + 1;
if(wait_after_read) begin
if(extra_toggle_count == (num_read_extra_toggles - 1)) begin
extra_toggle_count <= 0;
sm2_state <= SM2_END_DATA_TRANSFER;
end
end
else begin
if(extra_toggle_count == (num_write_extra_toggles - 1)) begin
extra_toggle_count <= 0;
if(read)
sm2_state <= SM2_READ;
else
sm2_state <= SM2_END_DATA_TRANSFER;
end
end
end
SM2_END_DATA_TRANSFER: begin
sclk <= CPOL;
spi_clock_phase <= CPHA;
sclk_toggle_count <= 0;
ss_n[slave] <= 1'b1;
mosi <= 1'bz;
num_bits_read <= 0;
num_bits_written <= 0;
if(num_elements_written == num_outgoing_elements) begin
num_initial_axi_transfer_bytes_received <= 0;
interrupt <= 1'b1;
num_elements_written <= 0;
num_bytes_written <= 0;
sm1_state <= SM1_IDLE;
end
else
sm1_state <= SM1_SELECT_SLAVE;
end
endcase
end
endcase
end
else
clock_count <= clock_count + 1;
end
end
end
end
always @(posedge s_axi_aclk) begin
if (memory_read_enable) begin
outgoing_data[(0*8+7) -: 8] <= memory[(memory_address*4) + 0];
outgoing_data[(1*8+7) -: 8] <= memory[(memory_address*4) + 1];
outgoing_data[(2*8+7) -: 8] <= memory[(memory_address*4) + 2];
outgoing_data[(3*8+7) -: 8] <= memory[(memory_address*4) + 3];
end
end
always @(outgoing_data, axi_rvalid) begin
if (axi_rvalid) begin
axi_rdata <= outgoing_data;
end
else begin
axi_rdata <= 32'h00000000;
end
end
endmodule | module quick_spi_soft #
(
parameter integer C_S_AXI_ID_WIDTH = 1,
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter integer C_S_AXI_ADDR_WIDTH = 8,
parameter integer C_S_AXI_AWUSER_WIDTH = 0,
parameter integer C_S_AXI_ARUSER_WIDTH = 0,
parameter integer C_S_AXI_WUSER_WIDTH = 0,
parameter integer C_S_AXI_RUSER_WIDTH = 0,
parameter integer C_S_AXI_BUSER_WIDTH = 0,
parameter integer MEMORY_SIZE = 64,
parameter integer NUMBER_OF_SLAVES = 2
)
(
input wire s_axi_aclk,
input wire s_axi_aresetn,
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [7:0] s_axi_awlen,
input wire [2:0] s_axi_awsize,
input wire [1:0] s_axi_awburst,
input wire s_axi_awlock,
input wire [3:0] s_axi_awcache,
input wire [2:0] s_axi_awprot,
input wire [3:0] s_axi_awqos,
input wire [3:0] s_axi_awregion,
input wire [C_S_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire s_axi_awvalid,
output wire s_axi_awready,
input wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_S_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire s_axi_wvalid,
output wire s_axi_wready,
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [1:0] s_axi_bresp,
output wire [C_S_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire s_axi_bvalid,
input wire s_axi_bready,
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [7:0] s_axi_arlen,
input wire [2:0] s_axi_arsize,
input wire [1:0] s_axi_arburst,
input wire s_axi_arlock,
input wire [3:0] s_axi_arcache,
input wire [2:0] s_axi_arprot,
input wire [3:0] s_axi_arqos,
input wire [3:0] s_axi_arregion,
input wire [C_S_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire s_axi_arvalid,
output wire s_axi_arready,
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_S_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire s_axi_rvalid,
input wire s_axi_rready,
output reg mosi,
input wire miso,
output reg sclk,
output reg[NUMBER_OF_SLAVES-1:0] ss_n,
output reg interrupt
); |
reg [C_S_AXI_ADDR_WIDTH-1:0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1:0] axi_bresp;
reg [C_S_AXI_BUSER_WIDTH-1:0] axi_buser;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1:0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1:0] axi_rdata;
reg [1:0] axi_rresp;
reg axi_rlast;
reg [C_S_AXI_RUSER_WIDTH-1:0] axi_ruser;
reg axi_rvalid;
wire aw_wrap_en;
wire ar_wrap_en;
wire [31:0] aw_wrap_size;
wire [31:0] ar_wrap_size;
reg axi_awv_awr_flag;
reg axi_arv_arr_flag;
reg [7:0] axi_awlen_cntr;
reg [7:0] axi_arlen_cntr;
reg [1:0] axi_arburst;
reg [1:0] axi_awburst;
reg [7:0] axi_arlen;
reg [7:0] axi_awlen;
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32)+ 1;
localparam integer OPT_MEM_ADDR_BITS = 3;
wire [OPT_MEM_ADDR_BITS:0] memory_address;
reg [C_S_AXI_DATA_WIDTH-1:0] outgoing_data;
assign s_axi_awready = axi_awready;
assign s_axi_wready = axi_wready;
assign s_axi_bresp = axi_bresp;
assign s_axi_buser = axi_buser;
assign s_axi_bvalid = axi_bvalid;
assign s_axi_arready = axi_arready;
assign s_axi_rdata = axi_rdata;
assign s_axi_rresp = axi_rresp;
assign s_axi_rlast = axi_rlast;
assign s_axi_ruser = axi_ruser;
assign s_axi_rvalid = axi_rvalid;
assign s_axi_bid = s_axi_awid;
assign s_axi_rid = s_axi_arid;
assign aw_wrap_size = (C_S_AXI_DATA_WIDTH/8 * (axi_awlen));
assign ar_wrap_size = (C_S_AXI_DATA_WIDTH/8 * (axi_arlen));
assign aw_wrap_en = ((axi_awaddr & aw_wrap_size) == aw_wrap_size)? 1'b1: 1'b0;
assign ar_wrap_en = ((axi_araddr & ar_wrap_size) == ar_wrap_size)? 1'b1: 1'b0;
assign s_axi_buser = 0;
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
axi_awready <= 1'b0;
axi_awv_awr_flag <= 1'b0;
end
else begin
if (~axi_awready && s_axi_awvalid && ~axi_awv_awr_flag && ~axi_arv_arr_flag) begin
axi_awready <= 1'b1;
axi_awv_awr_flag <= 1'b1;
end
else if (s_axi_wlast && axi_wready) begin
axi_awv_awr_flag <= 1'b0;
end
else begin
axi_awready <= 1'b0;
end
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
axi_awaddr <= 0;
axi_awlen_cntr <= 0;
axi_awburst <= 0;
axi_awlen <= 0;
end
else begin
if (~axi_awready && s_axi_awvalid && ~axi_awv_awr_flag) begin
axi_awaddr <= s_axi_awaddr[C_S_AXI_ADDR_WIDTH-1:0];
axi_awburst <= s_axi_awburst;
axi_awlen <= s_axi_awlen;
axi_awlen_cntr <= 0;
end
else if((axi_awlen_cntr <= axi_awlen) && axi_wready && s_axi_wvalid) begin
axi_awlen_cntr <= axi_awlen_cntr + 1;
case (axi_awburst)
2'b00: begin
axi_awaddr <= axi_awaddr;
end
2'b01: begin
axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
axi_awaddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
end
2'b10:
if (aw_wrap_en) begin
axi_awaddr <= (axi_awaddr - aw_wrap_size);
end
else begin
axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
axi_awaddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
end
default: begin
axi_awaddr <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
end
endcase
end
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
axi_wready <= 1'b0;
end
else begin
if (~axi_wready && s_axi_wvalid && axi_awv_awr_flag) begin
axi_wready <= 1'b1;
end
else if (s_axi_wlast && axi_wready) begin
axi_wready <= 1'b0;
end
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else begin
if (axi_awv_awr_flag && axi_wready && s_axi_wvalid && ~axi_bvalid && s_axi_wlast) begin
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0;
end
else begin
if (s_axi_bready && axi_bvalid) begin
axi_bvalid <= 1'b0;
end
end
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
axi_arready <= 1'b0;
axi_arv_arr_flag <= 1'b0;
end
else begin
if (~axi_arready && s_axi_arvalid && ~axi_awv_awr_flag && ~axi_arv_arr_flag) begin
axi_arready <= 1'b1;
axi_arv_arr_flag <= 1'b1;
end
else if (axi_rvalid && s_axi_rready && axi_arlen_cntr == axi_arlen) begin
axi_arv_arr_flag <= 1'b0;
end
else begin
axi_arready <= 1'b0;
end
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
axi_araddr <= 0;
axi_arlen_cntr <= 0;
axi_arburst <= 0;
axi_arlen <= 0;
axi_rlast <= 1'b0;
end
else begin
if (~axi_arready && s_axi_arvalid && ~axi_arv_arr_flag) begin
axi_araddr <= s_axi_araddr[C_S_AXI_ADDR_WIDTH - 1:0];
axi_arburst <= s_axi_arburst;
axi_arlen <= s_axi_arlen;
axi_arlen_cntr <= 0;
axi_rlast <= 1'b0;
end
else if((axi_arlen_cntr <= axi_arlen) && axi_rvalid && s_axi_rready) begin
axi_arlen_cntr <= axi_arlen_cntr + 1;
axi_rlast <= 1'b0;
case (axi_arburst)
2'b00: begin
axi_araddr <= axi_araddr;
end
2'b01: begin
axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
axi_araddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
end
2'b10:
if (ar_wrap_en) begin
axi_araddr <= (axi_araddr - ar_wrap_size);
end
else begin
axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
axi_araddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
end
default: begin
axi_araddr <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB]+1;
end
endcase
end
else if((axi_arlen_cntr == axi_arlen) && ~axi_rlast && axi_arv_arr_flag) begin
axi_rlast <= 1'b1;
end
else if (s_axi_rready) begin
axi_rlast <= 1'b0;
end
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else begin
if (axi_arv_arr_flag && ~axi_rvalid) begin
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0;
end
else if (axi_rvalid && s_axi_rready) begin
axi_rvalid <= 1'b0;
end
end
end
assign memory_address =
(axi_arv_arr_flag ?
axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] :
(axi_awv_awr_flag? axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]:0));
wire memory_write_enable = axi_wready && s_axi_wvalid;
wire memory_read_enable = axi_arv_arr_flag;
reg[15:0] sclk_toggle_count;
reg spi_clock_phase;
localparam SM1_IDLE = 2'b00;
localparam SM1_SELECT_SLAVE = 2'b01;
localparam SM1_TRANSFER_DATA = 2'b10;
reg[1:0] sm1_state;
localparam SM2_WRITE = 2'b00;
localparam SM2_READ = 2'b01;
localparam SM2_WAIT = 2'b10;
localparam SM2_END_DATA_TRANSFER = 2'b11;
reg[1:0] sm2_state;
reg wait_after_read;
reg[15:0] num_toggles_to_wait;
reg [7:0] memory [0:MEMORY_SIZE-1];
wire CPOL = memory[0][0];
wire CPHA = memory[0][1];
wire burst = memory[0][3];
wire read = memory[0][4];
wire[7:0] slave = memory[1];
wire[7:0] num_clocks_to_skip = memory[2];
wire[15:0] outgoing_element_size = {memory[5], memory[4]};
wire[15:0] num_outgoing_elements = {memory[7], memory[6]};
wire[15:0] incoming_element_size = {memory[9], memory[8]};
wire[15:0] num_write_extra_toggles = {memory[11], memory[10]};
wire[15:0] num_read_extra_toggles = {memory[13], memory[12]};
reg[15:0] num_bits_read;
reg[15:0] num_bits_written;
reg[15:0] num_elements_written;
reg[3:0] incoming_byte_bit;
reg[3:0] outgoing_byte_bit;
reg[15:0] num_bytes_read;
reg[15:0] num_bytes_written;
localparam write_buffer_start = 14;
localparam read_buffer_start = 39;
localparam num_initial_axi_transfer_bytes = read_buffer_start;
reg[15:0] extra_toggle_count;
integer num_initial_axi_transfer_bytes_received;
integer i;
integer clock_count;
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
for (i = 0; i < MEMORY_SIZE - 1; i = i + 1)
memory[i] <= 0;
clock_count <= 0;
num_initial_axi_transfer_bytes_received <= 0;
num_elements_written <= 0;
num_bits_read <= 0;
num_bits_written <= 0;
incoming_byte_bit <= 0;
outgoing_byte_bit <= 0;
num_bytes_read <= 0;
num_bytes_written <= 0;
extra_toggle_count <= 0;
wait_after_read <= 1'b0;
mosi <= 1'bz;
sclk <= 0;
ss_n <= {NUMBER_OF_SLAVES{1'b1}};
sclk_toggle_count <= 0;
spi_clock_phase <= 0;
interrupt <= 1'b0;
sm1_state <= SM1_IDLE;
sm2_state <= SM2_WRITE;
end
else begin
if(memory_write_enable) begin
if (s_axi_wstrb[0])
memory[(memory_address*4) + 0] <= s_axi_wdata[(0*8+7) -: 8];
if (s_axi_wstrb[1])
memory[(memory_address*4) + 1] <= s_axi_wdata[(1*8+7) -: 8];
if (s_axi_wstrb[2])
memory[(memory_address*4) + 2] <= s_axi_wdata[(2*8+7) -: 8];
if (s_axi_wstrb[3])
memory[(memory_address*4) + 3] <= s_axi_wdata[(3*8+7) -: 8];
num_initial_axi_transfer_bytes_received <=
num_initial_axi_transfer_bytes_received + s_axi_wstrb[0] + s_axi_wstrb[1] + s_axi_wstrb[2] + s_axi_wstrb[3];
end
else begin
if(num_initial_axi_transfer_bytes_received == read_buffer_start) begin
if(clock_count == num_clocks_to_skip) begin
clock_count <= 0;
case(sm1_state)
SM1_IDLE: begin
sclk <= CPOL;
spi_clock_phase <= CPHA;
interrupt <= 1'b0;
sm1_state <= SM1_SELECT_SLAVE;
end
SM1_SELECT_SLAVE: begin
ss_n[slave] <= 1'b0;
if(!CPHA) begin
outgoing_byte_bit <= outgoing_byte_bit + 1;
mosi <= memory[write_buffer_start + num_bytes_written][outgoing_byte_bit];
num_bits_written <= num_bits_written + 1;
if(outgoing_element_size == 1) begin
num_elements_written <= 1;
if(num_outgoing_elements == 1) begin
if(!num_write_extra_toggles) begin
if(read)
sm2_state <= SM2_READ;
else
sm2_state <= SM2_END_DATA_TRANSFER;
end
else
sm2_state <= SM2_WAIT;
end
else begin
if(read)
sm2_state <= SM2_READ;
else
sm2_state <= SM2_WRITE;
end
end
else
sm2_state <= SM2_WRITE;
end
sm1_state <= SM1_TRANSFER_DATA;
end
SM1_TRANSFER_DATA: begin
sclk <= ~sclk;
spi_clock_phase <= ~spi_clock_phase;
sclk_toggle_count <= sclk_toggle_count + 1;
case(sm2_state)
SM2_WRITE: begin
if(spi_clock_phase) begin
outgoing_byte_bit <= outgoing_byte_bit + 1;
if(outgoing_byte_bit == 7) begin
num_bytes_written <= num_bytes_written + 1;
outgoing_byte_bit <= 0;
end
mosi <= memory[write_buffer_start + num_bytes_written][outgoing_byte_bit];
num_bits_written <= num_bits_written + 1;
if(num_bits_written == outgoing_element_size - 1) begin
num_elements_written <= num_elements_written + 1;
if(burst) begin
if(num_elements_written == num_outgoing_elements - 1) begin
if(!num_write_extra_toggles)
sm2_state <= SM2_END_DATA_TRANSFER;
else
sm2_state <= SM2_WAIT;
end
else
num_bits_written <= 0;
end
else begin
if(!num_write_extra_toggles)
if(read)
sm2_state <= SM2_READ;
else
sm2_state <= SM2_END_DATA_TRANSFER;
else
sm2_state <= SM2_WAIT;
end
end
end
end
SM2_READ: begin
if(!spi_clock_phase) begin
incoming_byte_bit <= incoming_byte_bit + 1;
if(incoming_byte_bit == 7) begin
num_bytes_read <= num_bytes_read + 1;
incoming_byte_bit <= 0;
end
memory[read_buffer_start + num_bytes_read][incoming_byte_bit] <= miso;
num_bits_read <= num_bits_read + 1;
if(num_bits_read == incoming_element_size - 1) begin
if(!num_read_extra_toggles)
sm2_state <= SM2_END_DATA_TRANSFER;
else begin
wait_after_read <= 1'b1;
sm2_state <= SM2_WAIT;
end
end
end
end
SM2_WAIT: begin
extra_toggle_count <= extra_toggle_count + 1;
if(wait_after_read) begin
if(extra_toggle_count == (num_read_extra_toggles - 1)) begin
extra_toggle_count <= 0;
sm2_state <= SM2_END_DATA_TRANSFER;
end
end
else begin
if(extra_toggle_count == (num_write_extra_toggles - 1)) begin
extra_toggle_count <= 0;
if(read)
sm2_state <= SM2_READ;
else
sm2_state <= SM2_END_DATA_TRANSFER;
end
end
end
SM2_END_DATA_TRANSFER: begin
sclk <= CPOL;
spi_clock_phase <= CPHA;
sclk_toggle_count <= 0;
ss_n[slave] <= 1'b1;
mosi <= 1'bz;
num_bits_read <= 0;
num_bits_written <= 0;
if(num_elements_written == num_outgoing_elements) begin
num_initial_axi_transfer_bytes_received <= 0;
interrupt <= 1'b1;
num_elements_written <= 0;
num_bytes_written <= 0;
sm1_state <= SM1_IDLE;
end
else
sm1_state <= SM1_SELECT_SLAVE;
end
endcase
end
endcase
end
else
clock_count <= clock_count + 1;
end
end
end
end
always @(posedge s_axi_aclk) begin
if (memory_read_enable) begin
outgoing_data[(0*8+7) -: 8] <= memory[(memory_address*4) + 0];
outgoing_data[(1*8+7) -: 8] <= memory[(memory_address*4) + 1];
outgoing_data[(2*8+7) -: 8] <= memory[(memory_address*4) + 2];
outgoing_data[(3*8+7) -: 8] <= memory[(memory_address*4) + 3];
end
end
always @(outgoing_data, axi_rvalid) begin
if (axi_rvalid) begin
axi_rdata <= outgoing_data;
end
else begin
axi_rdata <= 32'h00000000;
end
end
endmodule | 14 |
139,682 | data/full_repos/permissive/88951410/tests/quick_spi_hard_le_lsb_tests/quick_spi_hard_le_lsb_testbench.v | 88,951,410 | quick_spi_hard_le_lsb_testbench.v | v | 95 | 71 | [] | [] | [] | [(3, 94)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/88951410/tests/quick_spi_hard_le_lsb_tests/quick_spi_hard_le_lsb_testbench.v:92: Unsupported: Ignoring delay on this delayed statement.\nalways #25 clk <= ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/88951410/tests/quick_spi_hard_le_lsb_tests/quick_spi_hard_le_lsb_testbench.v:70: Cannot find file containing module: \'quick_spi_hard\'\nquick_spi_hard #\n^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/88951410/tests/quick_spi_hard_le_lsb_tests,data/full_repos/permissive/88951410/quick_spi_hard\n data/full_repos/permissive/88951410/tests/quick_spi_hard_le_lsb_tests,data/full_repos/permissive/88951410/quick_spi_hard.v\n data/full_repos/permissive/88951410/tests/quick_spi_hard_le_lsb_tests,data/full_repos/permissive/88951410/quick_spi_hard.sv\n quick_spi_hard\n quick_spi_hard.v\n quick_spi_hard.sv\n obj_dir/quick_spi_hard\n obj_dir/quick_spi_hard.v\n obj_dir/quick_spi_hard.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 305,577 | module | module quick_spi_hard_le_lsb_testbench;
reg clk;
reg rst_n;
wire end_of_transaction;
wire[7:0] incoming_data;
reg[15:0] outgoing_data;
wire mosi;
reg miso;
wire sclk;
wire[1:0] ss_n;
reg enable;
reg start_transaction;
reg operation;
integer sclk_toggle_count;
reg[8:0] incoming_data_buffer;
reg spi_clock_phase;
initial begin
clk <= 1'b0;
rst_n <= 1'b0;
rst_n <= #50 1'b1;
outgoing_data <= {8'b11001100, 8'b10000010};
end
always @ (posedge clk)
begin
if(!rst_n)
begin
outgoing_data <= {8'b11001100, 8'b10000010};
enable <= 1'b1;
start_transaction <= 1'b1;
operation <= 1'b0;
miso <= 1'b0;
sclk_toggle_count <= 0;
incoming_data_buffer <= {8'b10010101, 1'b1};
spi_clock_phase <= 1'b1;
end
else
begin
if(end_of_transaction)
begin
operation <= ~operation;
sclk_toggle_count <= 0;
spi_clock_phase <= 1'b1;
incoming_data_buffer <= {8'b10010101, 1'b1};
miso <= 1'b0;
end
else
begin
if(sclk_toggle_count > 36)
begin
if(!spi_clock_phase)
begin
miso <= incoming_data_buffer[0];
incoming_data_buffer <= incoming_data_buffer >> 1;
end
end
sclk_toggle_count <= sclk_toggle_count + 1;
spi_clock_phase <= ~spi_clock_phase;
end
end
end
quick_spi_hard #
(
.BYTES_ORDER(0),
.BITS_ORDER(0)
)
spi
(
.clk(clk),
.reset_n(rst_n),
.enable(enable),
.start_transaction(start_transaction),
.slave(2'b01),
.operation(operation),
.end_of_transaction(end_of_transaction),
.incoming_data(incoming_data),
.outgoing_data(outgoing_data),
.mosi(mosi),
.miso(miso),
.sclk(sclk),
.ss_n(ss_n)
);
always #25 clk <= ~clk;
endmodule | module quick_spi_hard_le_lsb_testbench; |
reg clk;
reg rst_n;
wire end_of_transaction;
wire[7:0] incoming_data;
reg[15:0] outgoing_data;
wire mosi;
reg miso;
wire sclk;
wire[1:0] ss_n;
reg enable;
reg start_transaction;
reg operation;
integer sclk_toggle_count;
reg[8:0] incoming_data_buffer;
reg spi_clock_phase;
initial begin
clk <= 1'b0;
rst_n <= 1'b0;
rst_n <= #50 1'b1;
outgoing_data <= {8'b11001100, 8'b10000010};
end
always @ (posedge clk)
begin
if(!rst_n)
begin
outgoing_data <= {8'b11001100, 8'b10000010};
enable <= 1'b1;
start_transaction <= 1'b1;
operation <= 1'b0;
miso <= 1'b0;
sclk_toggle_count <= 0;
incoming_data_buffer <= {8'b10010101, 1'b1};
spi_clock_phase <= 1'b1;
end
else
begin
if(end_of_transaction)
begin
operation <= ~operation;
sclk_toggle_count <= 0;
spi_clock_phase <= 1'b1;
incoming_data_buffer <= {8'b10010101, 1'b1};
miso <= 1'b0;
end
else
begin
if(sclk_toggle_count > 36)
begin
if(!spi_clock_phase)
begin
miso <= incoming_data_buffer[0];
incoming_data_buffer <= incoming_data_buffer >> 1;
end
end
sclk_toggle_count <= sclk_toggle_count + 1;
spi_clock_phase <= ~spi_clock_phase;
end
end
end
quick_spi_hard #
(
.BYTES_ORDER(0),
.BITS_ORDER(0)
)
spi
(
.clk(clk),
.reset_n(rst_n),
.enable(enable),
.start_transaction(start_transaction),
.slave(2'b01),
.operation(operation),
.end_of_transaction(end_of_transaction),
.incoming_data(incoming_data),
.outgoing_data(outgoing_data),
.mosi(mosi),
.miso(miso),
.sclk(sclk),
.ss_n(ss_n)
);
always #25 clk <= ~clk;
endmodule | 14 |
139,684 | data/full_repos/permissive/8896328/rtl/core/arbiter.v | 8,896,328 | arbiter.v | v | 64 | 101 | [] | ['apache license'] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/8896328/rtl/core/arbiter.v:43: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'base\' generates 4 bits.\n : ... In instance arbiter\n & ~(double_request - base);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 305,580 | module | module arbiter
#(parameter NUM_ENTRIES = 4)
(input clk,
input reset,
input[NUM_ENTRIES - 1:0] request,
output reg[NUM_ENTRIES - 1:0] grant_oh);
reg[NUM_ENTRIES - 1:0] base;
wire[NUM_ENTRIES * 2 - 1:0] double_request = { request, request };
wire[NUM_ENTRIES * 2 - 1:0] double_grant = double_request
& ~(double_request - base);
wire[NUM_ENTRIES - 1:0] grant_nxt = double_grant[NUM_ENTRIES * 2 - 1:NUM_ENTRIES]
| double_grant[NUM_ENTRIES - 1:0];
always @(posedge clk, posedge reset)
begin
if (reset)
begin
base <= 1;
grant_oh <= 0;
end
else
begin
if (grant_nxt != 0)
base <= { grant_nxt[NUM_ENTRIES - 2:0], grant_nxt[NUM_ENTRIES - 1] };
grant_oh <= grant_nxt;
end
end
endmodule | module arbiter
#(parameter NUM_ENTRIES = 4)
(input clk,
input reset,
input[NUM_ENTRIES - 1:0] request,
output reg[NUM_ENTRIES - 1:0] grant_oh); |
reg[NUM_ENTRIES - 1:0] base;
wire[NUM_ENTRIES * 2 - 1:0] double_request = { request, request };
wire[NUM_ENTRIES * 2 - 1:0] double_grant = double_request
& ~(double_request - base);
wire[NUM_ENTRIES - 1:0] grant_nxt = double_grant[NUM_ENTRIES * 2 - 1:NUM_ENTRIES]
| double_grant[NUM_ENTRIES - 1:0];
always @(posedge clk, posedge reset)
begin
if (reset)
begin
base <= 1;
grant_oh <= 0;
end
else
begin
if (grant_nxt != 0)
base <= { grant_nxt[NUM_ENTRIES - 2:0], grant_nxt[NUM_ENTRIES - 1] };
grant_oh <= grant_nxt;
end
end
endmodule | 79 |
139,685 | data/full_repos/permissive/8896328/rtl/core/axi_interface.v | 8,896,328 | axi_interface.v | v | 168 | 85 | [] | ['apache license'] | [] | [(17, 167)] | null | null | 1: b"%Error: data/full_repos/permissive/8896328/rtl/core/axi_interface.v:74: Cannot find file containing module: 'axi_slave'\n axi_slave #(\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/8896328/rtl/core,data/full_repos/permissive/8896328/axi_slave\n data/full_repos/permissive/8896328/rtl/core,data/full_repos/permissive/8896328/axi_slave.v\n data/full_repos/permissive/8896328/rtl/core,data/full_repos/permissive/8896328/axi_slave.sv\n axi_slave\n axi_slave.v\n axi_slave.sv\n obj_dir/axi_slave\n obj_dir/axi_slave.v\n obj_dir/axi_slave.sv\n%Error: data/full_repos/permissive/8896328/rtl/core/axi_interface.v:157: Cannot find file containing module: 'pasc'\n pasc #(.NUM_CORES(NUM_CORES)) pasc(\n ^~~~\n%Error: Exiting due to 2 error(s)\n" | 305,582 | module | module axi_interface
#(parameter NUM_CORES = 16,
parameter DATA_WIDTH = 32,
parameter MEMORY_MAP_SIZE = 64 * 1024,
parameter STROBE_WIDTH = (DATA_WIDTH / 8),
parameter AXI_ADDR_WIDTH = $clog2(MEMORY_MAP_SIZE * 4),
parameter SLV_ADDR_WIDTH = AXI_ADDR_WIDTH - $clog2(STROBE_WIDTH))
(input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [AXI_ADDR_WIDTH - 1: 0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [2:0] s_axi_awprot,
input [STROBE_WIDTH - 1: 0] s_axi_wstrb,
input [DATA_WIDTH - 1: 0] s_axi_wdata,
output s_axi_wready,
input s_axi_bready,
output s_axi_bvalid,
output [1:0] s_axi_bresp,
input s_axi_arvalid,
input [AXI_ADDR_WIDTH - 1: 0] s_axi_araddr,
output s_axi_arready,
input s_axi_rready,
input [2:0] s_axi_arprot,
output s_axi_rvalid,
output [1:0] s_axi_rresp,
output [DATA_WIDTH - 1: 0] s_axi_rdata);
reg unit_wack;
wire unit_invalid_waddr;
wire unit_wen;
wire [SLV_ADDR_WIDTH - 1: 0] unit_waddr;
wire [DATA_WIDTH - 1: 0] unit_wdata;
reg unit_rstrb;
wire unit_invalid_raddr;
wire unit_ren;
wire [SLV_ADDR_WIDTH - 1: 0] unit_raddr;
wire [15 : 0] axi_q;
wire [SLV_ADDR_WIDTH - 1: 0] axi_addr;
wire output_enable;
wire [$clog2(NUM_CORES) - 1:0] output_core_id;
wire [15:0] output_data_val;
axi_slave #(
.DATA_WIDTH(DATA_WIDTH),
.MEMORY_MAP_SIZE(MEMORY_MAP_SIZE),
.STROBE_WIDTH(STROBE_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.SLV_ADDR_WIDTH(SLV_ADDR_WIDTH)
) axi_slave_inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_awprot(s_axi_awprot),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bresp(s_axi_bresp),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arready(s_axi_arready),
.s_axi_rready(s_axi_rready),
.s_axi_arprot(s_axi_arprot),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rresp(s_axi_rresp),
.s_axi_rdata(s_axi_rdata),
.unit_wack(unit_wack),
.unit_invalid_waddr(unit_invalid_waddr),
.unit_wen(unit_wen),
.unit_waddr(unit_waddr),
.unit_wdata(unit_wdata),
.unit_rstrb(unit_rstrb),
.unit_invalid_raddr(unit_invalid_raddr),
.unit_rdata({16'h0, axi_q}),
.unit_ren(unit_ren),
.unit_raddr(unit_raddr));
assign axi_addr = unit_wen ? unit_waddr : unit_raddr;
assign unit_invalid_waddr = unit_waddr < (16'h4000) || (16'hFC00) <= unit_waddr;
assign unit_invalid_raddr = unit_raddr < (16'h4000) || (16'hFC00) <= unit_raddr;
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 0) begin
unit_wack <= 0;
unit_rstrb <= 0;
end
else begin
if (~unit_wack && unit_wen) begin
unit_wack <= 1;
end
else begin
unit_wack <= 0;
end
if (~unit_rstrb && unit_ren) begin
unit_rstrb <= 1;
end
else begin
unit_rstrb <= 0;
end
end
end
pasc #(.NUM_CORES(NUM_CORES)) pasc(
.clk(s_axi_aclk),
.output_enable(output_enable),
.output_core_id(output_core_id),
.output_data_val(output_data_val),
.axi_we(unit_wen),
.axi_addr(axi_addr),
.axi_data(unit_wdata[15:0]),
.axi_q(axi_q));
endmodule | module axi_interface
#(parameter NUM_CORES = 16,
parameter DATA_WIDTH = 32,
parameter MEMORY_MAP_SIZE = 64 * 1024,
parameter STROBE_WIDTH = (DATA_WIDTH / 8),
parameter AXI_ADDR_WIDTH = $clog2(MEMORY_MAP_SIZE * 4),
parameter SLV_ADDR_WIDTH = AXI_ADDR_WIDTH - $clog2(STROBE_WIDTH))
(input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [AXI_ADDR_WIDTH - 1: 0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [2:0] s_axi_awprot,
input [STROBE_WIDTH - 1: 0] s_axi_wstrb,
input [DATA_WIDTH - 1: 0] s_axi_wdata,
output s_axi_wready,
input s_axi_bready,
output s_axi_bvalid,
output [1:0] s_axi_bresp,
input s_axi_arvalid,
input [AXI_ADDR_WIDTH - 1: 0] s_axi_araddr,
output s_axi_arready,
input s_axi_rready,
input [2:0] s_axi_arprot,
output s_axi_rvalid,
output [1:0] s_axi_rresp,
output [DATA_WIDTH - 1: 0] s_axi_rdata); |
reg unit_wack;
wire unit_invalid_waddr;
wire unit_wen;
wire [SLV_ADDR_WIDTH - 1: 0] unit_waddr;
wire [DATA_WIDTH - 1: 0] unit_wdata;
reg unit_rstrb;
wire unit_invalid_raddr;
wire unit_ren;
wire [SLV_ADDR_WIDTH - 1: 0] unit_raddr;
wire [15 : 0] axi_q;
wire [SLV_ADDR_WIDTH - 1: 0] axi_addr;
wire output_enable;
wire [$clog2(NUM_CORES) - 1:0] output_core_id;
wire [15:0] output_data_val;
axi_slave #(
.DATA_WIDTH(DATA_WIDTH),
.MEMORY_MAP_SIZE(MEMORY_MAP_SIZE),
.STROBE_WIDTH(STROBE_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.SLV_ADDR_WIDTH(SLV_ADDR_WIDTH)
) axi_slave_inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_awprot(s_axi_awprot),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bresp(s_axi_bresp),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arready(s_axi_arready),
.s_axi_rready(s_axi_rready),
.s_axi_arprot(s_axi_arprot),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rresp(s_axi_rresp),
.s_axi_rdata(s_axi_rdata),
.unit_wack(unit_wack),
.unit_invalid_waddr(unit_invalid_waddr),
.unit_wen(unit_wen),
.unit_waddr(unit_waddr),
.unit_wdata(unit_wdata),
.unit_rstrb(unit_rstrb),
.unit_invalid_raddr(unit_invalid_raddr),
.unit_rdata({16'h0, axi_q}),
.unit_ren(unit_ren),
.unit_raddr(unit_raddr));
assign axi_addr = unit_wen ? unit_waddr : unit_raddr;
assign unit_invalid_waddr = unit_waddr < (16'h4000) || (16'hFC00) <= unit_waddr;
assign unit_invalid_raddr = unit_raddr < (16'h4000) || (16'hFC00) <= unit_raddr;
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 0) begin
unit_wack <= 0;
unit_rstrb <= 0;
end
else begin
if (~unit_wack && unit_wen) begin
unit_wack <= 1;
end
else begin
unit_wack <= 0;
end
if (~unit_rstrb && unit_ren) begin
unit_rstrb <= 1;
end
else begin
unit_rstrb <= 0;
end
end
end
pasc #(.NUM_CORES(NUM_CORES)) pasc(
.clk(s_axi_aclk),
.output_enable(output_enable),
.output_core_id(output_core_id),
.output_data_val(output_data_val),
.axi_we(unit_wen),
.axi_addr(axi_addr),
.axi_data(unit_wdata[15:0]),
.axi_q(axi_q));
endmodule | 79 |
139,686 | data/full_repos/permissive/8896328/rtl/core/axi_slave.v | 8,896,328 | axi_slave.v | v | 211 | 104 | [] | ['mit license'] | [] | [(109, 296)] | null | null | 1: b'%Error: data/full_repos/permissive/8896328/rtl/core/axi_slave.v:21: Cannot find include file: axi_defines.v\n`include "axi_defines.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/8896328/rtl/core,data/full_repos/permissive/8896328/axi_defines.v\n data/full_repos/permissive/8896328/rtl/core,data/full_repos/permissive/8896328/axi_defines.v.v\n data/full_repos/permissive/8896328/rtl/core,data/full_repos/permissive/8896328/axi_defines.v.sv\n axi_defines.v\n axi_defines.v.v\n axi_defines.v.sv\n obj_dir/axi_defines.v\n obj_dir/axi_defines.v.v\n obj_dir/axi_defines.v.sv\n%Error: data/full_repos/permissive/8896328/rtl/core/axi_slave.v:139: Define or directive not defined: \'`AXI_RESP_DECERR\'\n s_axi_bresp <= `AXI_RESP_DECERR;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/8896328/rtl/core/axi_slave.v:139: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n s_axi_bresp <= `AXI_RESP_DECERR;\n ^\n%Error: data/full_repos/permissive/8896328/rtl/core/axi_slave.v:142: Define or directive not defined: \'`AXI_RESP_OKAY\'\n s_axi_bresp <= `AXI_RESP_OKAY;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/8896328/rtl/core/axi_slave.v:142: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n s_axi_bresp <= `AXI_RESP_OKAY;\n ^\n%Error: data/full_repos/permissive/8896328/rtl/core/axi_slave.v:191: Define or directive not defined: \'`AXI_RESP_DECERR\'\n s_axi_rresp <= `AXI_RESP_DECERR;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/8896328/rtl/core/axi_slave.v:191: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n s_axi_rresp <= `AXI_RESP_DECERR;\n ^\n%Error: data/full_repos/permissive/8896328/rtl/core/axi_slave.v:194: Define or directive not defined: \'`AXI_RESP_OKAY\'\n s_axi_rresp <= `AXI_RESP_OKAY;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/8896328/rtl/core/axi_slave.v:194: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n s_axi_rresp <= `AXI_RESP_OKAY;\n ^\n%Error: Exiting due to 9 error(s)\n' | 305,583 | module | module axi_slave
#(parameter DATA_WIDTH = 32,
parameter MEMORY_MAP_SIZE = 64 * 1024,
parameter STROBE_WIDTH = (DATA_WIDTH / 8),
parameter AXI_ADDR_WIDTH = $clog2(MEMORY_MAP_SIZE * 4),
parameter SLV_ADDR_WIDTH = AXI_ADDR_WIDTH - $clog2(STROBE_WIDTH))
(input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [AXI_ADDR_WIDTH - 1: 0] s_axi_awaddr,
output reg s_axi_awready,
input s_axi_wvalid,
input [2:0] s_axi_awprot,
input [STROBE_WIDTH - 1:0] s_axi_wstrb,
input [DATA_WIDTH - 1: 0] s_axi_wdata,
output reg s_axi_wready,
input s_axi_bready,
output reg s_axi_bvalid,
output reg [1:0] s_axi_bresp,
input s_axi_arvalid,
input [AXI_ADDR_WIDTH - 1: 0] s_axi_araddr,
output reg s_axi_arready,
input s_axi_rready,
input [2:0] s_axi_arprot,
output reg s_axi_rvalid,
output reg [1:0] s_axi_rresp,
output reg [DATA_WIDTH - 1: 0] s_axi_rdata,
input unit_wack,
input unit_invalid_waddr,
output reg unit_wen,
output reg [SLV_ADDR_WIDTH - 1: 0] unit_waddr,
output reg [DATA_WIDTH - 1: 0] unit_wdata,
input unit_rstrb,
input unit_invalid_raddr,
input [DATA_WIDTH - 1: 0] unit_rdata,
output reg unit_ren,
output reg [SLV_ADDR_WIDTH - 1: 0] unit_raddr);
localparam WRITE_IDLE = 2'h0;
localparam WRITE_WAIT = 2'h1;
localparam WRITE_SENT_RESP = 2'h2;
localparam READ_IDLE = 2'h0;
localparam READ_WAIT = 2'h1;
localparam READ_SENT_DATA = 2'h2;
reg [1:0] state_write;
reg [1:0] state_read;
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 0) begin
s_axi_wready <= 0;
s_axi_awready <= 0;
s_axi_bresp <= 0;
s_axi_bvalid <= 0;
unit_wen <= 0;
unit_waddr <= 0;
unit_wdata <= 0;
state_write <= WRITE_IDLE;
end
else begin
case (state_write)
WRITE_IDLE: begin
if (~s_axi_awready && ~s_axi_wready && s_axi_awvalid && s_axi_wvalid) begin
s_axi_awready <= 1;
s_axi_wready <= 1;
unit_wen <= 1;
unit_wdata <= s_axi_wdata;
unit_waddr <= s_axi_awaddr[AXI_ADDR_WIDTH - 1: $clog2(STROBE_WIDTH)];
state_write <= WRITE_WAIT;
end
else begin
s_axi_awready <= 0;
s_axi_wready <= 0;
end
end
WRITE_WAIT: begin
s_axi_wready <= 0;
s_axi_awready <= 0;
if (unit_wack && ~s_axi_bvalid) begin
s_axi_bvalid <= 1;
unit_wen <= 0;
state_write <= WRITE_SENT_RESP;
if (unit_invalid_waddr) begin
s_axi_bresp <= `AXI_RESP_DECERR;
end
else begin
s_axi_bresp <= `AXI_RESP_OKAY;
end
end
end
WRITE_SENT_RESP: begin
if (s_axi_bready && s_axi_bvalid) begin
s_axi_bvalid <= 0;
state_write <= WRITE_IDLE;
end
end
default: begin
$display("AXI Lite Slave: Shouldn't have gotten here!");
end
endcase
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 0) begin
s_axi_arready <= 0;
s_axi_rvalid <= 0;
s_axi_rdata <= 0;
s_axi_rresp <= 0;
unit_ren <= 0;
unit_raddr <= 0;
state_read <= READ_IDLE;
end
else begin
case (state_read)
READ_IDLE: begin
if (~s_axi_arready && s_axi_arvalid) begin
s_axi_arready <= 1;
unit_ren <= 1;
unit_raddr <= s_axi_araddr[AXI_ADDR_WIDTH - 1: $clog2(STROBE_WIDTH)];
state_read <= READ_WAIT;
end
end
READ_WAIT: begin
s_axi_arready <= 0;
if (unit_rstrb && ~s_axi_rvalid) begin
s_axi_rvalid <= 1;
s_axi_rdata <= unit_rdata;
unit_ren <= 0;
state_read <= READ_SENT_DATA;
if (unit_invalid_raddr) begin
s_axi_rresp <= `AXI_RESP_DECERR;
end
else begin
s_axi_rresp <= `AXI_RESP_OKAY;
end
end
end
READ_SENT_DATA: begin
if (s_axi_rready && s_axi_rvalid) begin
s_axi_rvalid <= 0;
state_read <= READ_IDLE;
end
end
default: begin
$display("AXI Lite Slave: Shouldn't have gotten here!");
end
endcase
end
end
endmodule | module axi_slave
#(parameter DATA_WIDTH = 32,
parameter MEMORY_MAP_SIZE = 64 * 1024,
parameter STROBE_WIDTH = (DATA_WIDTH / 8),
parameter AXI_ADDR_WIDTH = $clog2(MEMORY_MAP_SIZE * 4),
parameter SLV_ADDR_WIDTH = AXI_ADDR_WIDTH - $clog2(STROBE_WIDTH))
(input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [AXI_ADDR_WIDTH - 1: 0] s_axi_awaddr,
output reg s_axi_awready,
input s_axi_wvalid,
input [2:0] s_axi_awprot,
input [STROBE_WIDTH - 1:0] s_axi_wstrb,
input [DATA_WIDTH - 1: 0] s_axi_wdata,
output reg s_axi_wready,
input s_axi_bready,
output reg s_axi_bvalid,
output reg [1:0] s_axi_bresp,
input s_axi_arvalid,
input [AXI_ADDR_WIDTH - 1: 0] s_axi_araddr,
output reg s_axi_arready,
input s_axi_rready,
input [2:0] s_axi_arprot,
output reg s_axi_rvalid,
output reg [1:0] s_axi_rresp,
output reg [DATA_WIDTH - 1: 0] s_axi_rdata,
input unit_wack,
input unit_invalid_waddr,
output reg unit_wen,
output reg [SLV_ADDR_WIDTH - 1: 0] unit_waddr,
output reg [DATA_WIDTH - 1: 0] unit_wdata,
input unit_rstrb,
input unit_invalid_raddr,
input [DATA_WIDTH - 1: 0] unit_rdata,
output reg unit_ren,
output reg [SLV_ADDR_WIDTH - 1: 0] unit_raddr); |
localparam WRITE_IDLE = 2'h0;
localparam WRITE_WAIT = 2'h1;
localparam WRITE_SENT_RESP = 2'h2;
localparam READ_IDLE = 2'h0;
localparam READ_WAIT = 2'h1;
localparam READ_SENT_DATA = 2'h2;
reg [1:0] state_write;
reg [1:0] state_read;
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 0) begin
s_axi_wready <= 0;
s_axi_awready <= 0;
s_axi_bresp <= 0;
s_axi_bvalid <= 0;
unit_wen <= 0;
unit_waddr <= 0;
unit_wdata <= 0;
state_write <= WRITE_IDLE;
end
else begin
case (state_write)
WRITE_IDLE: begin
if (~s_axi_awready && ~s_axi_wready && s_axi_awvalid && s_axi_wvalid) begin
s_axi_awready <= 1;
s_axi_wready <= 1;
unit_wen <= 1;
unit_wdata <= s_axi_wdata;
unit_waddr <= s_axi_awaddr[AXI_ADDR_WIDTH - 1: $clog2(STROBE_WIDTH)];
state_write <= WRITE_WAIT;
end
else begin
s_axi_awready <= 0;
s_axi_wready <= 0;
end
end
WRITE_WAIT: begin
s_axi_wready <= 0;
s_axi_awready <= 0;
if (unit_wack && ~s_axi_bvalid) begin
s_axi_bvalid <= 1;
unit_wen <= 0;
state_write <= WRITE_SENT_RESP;
if (unit_invalid_waddr) begin
s_axi_bresp <= `AXI_RESP_DECERR;
end
else begin
s_axi_bresp <= `AXI_RESP_OKAY;
end
end
end
WRITE_SENT_RESP: begin
if (s_axi_bready && s_axi_bvalid) begin
s_axi_bvalid <= 0;
state_write <= WRITE_IDLE;
end
end
default: begin
$display("AXI Lite Slave: Shouldn't have gotten here!");
end
endcase
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 0) begin
s_axi_arready <= 0;
s_axi_rvalid <= 0;
s_axi_rdata <= 0;
s_axi_rresp <= 0;
unit_ren <= 0;
unit_raddr <= 0;
state_read <= READ_IDLE;
end
else begin
case (state_read)
READ_IDLE: begin
if (~s_axi_arready && s_axi_arvalid) begin
s_axi_arready <= 1;
unit_ren <= 1;
unit_raddr <= s_axi_araddr[AXI_ADDR_WIDTH - 1: $clog2(STROBE_WIDTH)];
state_read <= READ_WAIT;
end
end
READ_WAIT: begin
s_axi_arready <= 0;
if (unit_rstrb && ~s_axi_rvalid) begin
s_axi_rvalid <= 1;
s_axi_rdata <= unit_rdata;
unit_ren <= 0;
state_read <= READ_SENT_DATA;
if (unit_invalid_raddr) begin
s_axi_rresp <= `AXI_RESP_DECERR;
end
else begin
s_axi_rresp <= `AXI_RESP_OKAY;
end
end
end
READ_SENT_DATA: begin
if (s_axi_rready && s_axi_rvalid) begin
s_axi_rvalid <= 0;
state_read <= READ_IDLE;
end
end
default: begin
$display("AXI Lite Slave: Shouldn't have gotten here!");
end
endcase
end
end
endmodule | 79 |
139,690 | data/full_repos/permissive/8896328/rtl/core/pasc.v | 8,896,328 | pasc.v | v | 145 | 86 | [] | ['apache license'] | [] | [(17, 144)] | null | null | 1: b'%Error: data/full_repos/permissive/8896328/rtl/core/pasc.v:38: Cannot find file containing module: \'cluster\'\n cluster #(.NUM_CORES(NUM_CORES)) cluster(\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/8896328/rtl/core,data/full_repos/permissive/8896328/cluster\n data/full_repos/permissive/8896328/rtl/core,data/full_repos/permissive/8896328/cluster.v\n data/full_repos/permissive/8896328/rtl/core,data/full_repos/permissive/8896328/cluster.sv\n cluster\n cluster.v\n cluster.sv\n obj_dir/cluster\n obj_dir/cluster.v\n obj_dir/cluster.sv\n%Warning-WIDTH: data/full_repos/permissive/8896328/rtl/core/pasc.v:68: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance pasc\n reset_count <= axi_we ? 1\'b0 : { reset_count[6:0], 1\'b1 };\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/8896328/rtl/core/pasc.v:107: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s VARREF \'device_data_out\' generates 16 bits.\n : ... In instance pasc\n else if (device_data_out && !sem_held0)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/8896328/rtl/core/pasc.v:117: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s LOGAND generates 1 bits.\n : ... In instance pasc\n device_data_in <= sem_held0 && sem_holder0 == device_core_id;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/8896328/rtl/core/pasc.v:128: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s VARREF \'device_data_out\' generates 16 bits.\n : ... In instance pasc\n else if (device_data_out && !sem_held1)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/8896328/rtl/core/pasc.v:138: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s LOGAND generates 1 bits.\n : ... In instance pasc\n device_data_in <= sem_held1 && sem_holder1 == device_core_id;\n ^~\n%Error: Exiting due to 1 error(s), 5 warning(s)\n' | 305,588 | module | module pasc
#(parameter NUM_CORES = 16)
(input clk,
output reg output_enable,
output reg [$clog2(NUM_CORES) - 1:0] output_core_id,
output reg [15:0] output_data_val,
input axi_we,
input [15:0] axi_addr,
input [15:0] axi_data,
output [15:0] axi_q);
reg reset;
wire[$clog2(NUM_CORES) - 1:0] device_core_id;
wire device_write_en;
wire device_read_en;
wire[9:0] device_addr;
wire[15:0] device_data_out;
reg[15:0] device_data_in;
cluster #(.NUM_CORES(NUM_CORES)) cluster(
.clk(clk),
.reset(reset),
.device_core_id(device_core_id),
.device_write_en(device_write_en),
.device_read_en(device_read_en),
.device_addr(device_addr),
.device_data_out(device_data_out),
.device_data_in(device_data_in),
.axi_we(axi_we),
.axi_addr(axi_addr),
.axi_data(axi_data),
.axi_q(axi_q));
reg[$clog2(NUM_CORES) - 1:0] sem_holder0;
reg sem_held0;
reg[$clog2(NUM_CORES) - 1:0] sem_holder1;
reg sem_held1;
reg[7:0] reset_count;
initial
begin
reset = 1;
reset_count = 0;
end
always @(posedge clk)
begin
reset <= axi_we ? 1'h1 : reset;
reset_count <= axi_we ? 1'b0 : { reset_count[6:0], 1'b1 };
if (reset_count == 8'b11111111)
reset <= 0;
end
always @(posedge clk, posedge reset)
begin
if (reset)
begin
device_data_in <= 0;
sem_holder0 <= 0;
sem_held0 <= 0;
sem_holder1 <= 0;
sem_held1 <= 0;
output_enable <= 0;
output_core_id <= 0;
output_data_val <= 0;
end
else
begin
if (device_addr == 'h3ff && device_write_en)
begin
output_enable <= 1;
output_core_id <= device_core_id;
output_data_val <= device_data_out;
end
else
output_enable <= 0;
case (device_addr)
'h3fe:
begin
if (device_write_en)
begin
if (device_data_out == 0 && sem_holder0 == device_core_id)
sem_held0 <= 0;
else if (device_data_out && !sem_held0)
begin
sem_held0 <= 1;
sem_holder0 <= device_core_id;
end
end
else
begin
device_data_in <= sem_held0 && sem_holder0 == device_core_id;
end
end
'h3fd:
begin
if (device_write_en)
begin
if (device_data_out == 0 && sem_holder1 == device_core_id)
sem_held1 <= 0;
else if (device_data_out && !sem_held1)
begin
sem_held1 <= 1;
sem_holder1 <= device_core_id;
end
end
else
begin
device_data_in <= sem_held1 && sem_holder1 == device_core_id;
end
end
endcase
end
end
endmodule | module pasc
#(parameter NUM_CORES = 16)
(input clk,
output reg output_enable,
output reg [$clog2(NUM_CORES) - 1:0] output_core_id,
output reg [15:0] output_data_val,
input axi_we,
input [15:0] axi_addr,
input [15:0] axi_data,
output [15:0] axi_q); |
reg reset;
wire[$clog2(NUM_CORES) - 1:0] device_core_id;
wire device_write_en;
wire device_read_en;
wire[9:0] device_addr;
wire[15:0] device_data_out;
reg[15:0] device_data_in;
cluster #(.NUM_CORES(NUM_CORES)) cluster(
.clk(clk),
.reset(reset),
.device_core_id(device_core_id),
.device_write_en(device_write_en),
.device_read_en(device_read_en),
.device_addr(device_addr),
.device_data_out(device_data_out),
.device_data_in(device_data_in),
.axi_we(axi_we),
.axi_addr(axi_addr),
.axi_data(axi_data),
.axi_q(axi_q));
reg[$clog2(NUM_CORES) - 1:0] sem_holder0;
reg sem_held0;
reg[$clog2(NUM_CORES) - 1:0] sem_holder1;
reg sem_held1;
reg[7:0] reset_count;
initial
begin
reset = 1;
reset_count = 0;
end
always @(posedge clk)
begin
reset <= axi_we ? 1'h1 : reset;
reset_count <= axi_we ? 1'b0 : { reset_count[6:0], 1'b1 };
if (reset_count == 8'b11111111)
reset <= 0;
end
always @(posedge clk, posedge reset)
begin
if (reset)
begin
device_data_in <= 0;
sem_holder0 <= 0;
sem_held0 <= 0;
sem_holder1 <= 0;
sem_held1 <= 0;
output_enable <= 0;
output_core_id <= 0;
output_data_val <= 0;
end
else
begin
if (device_addr == 'h3ff && device_write_en)
begin
output_enable <= 1;
output_core_id <= device_core_id;
output_data_val <= device_data_out;
end
else
output_enable <= 0;
case (device_addr)
'h3fe:
begin
if (device_write_en)
begin
if (device_data_out == 0 && sem_holder0 == device_core_id)
sem_held0 <= 0;
else if (device_data_out && !sem_held0)
begin
sem_held0 <= 1;
sem_holder0 <= device_core_id;
end
end
else
begin
device_data_in <= sem_held0 && sem_holder0 == device_core_id;
end
end
'h3fd:
begin
if (device_write_en)
begin
if (device_data_out == 0 && sem_holder1 == device_core_id)
sem_held1 <= 0;
else if (device_data_out && !sem_held1)
begin
sem_held1 <= 1;
sem_holder1 <= device_core_id;
end
end
else
begin
device_data_in <= sem_held1 && sem_holder1 == device_core_id;
end
end
endcase
end
end
endmodule | 79 |
139,692 | data/full_repos/permissive/8896328/rtl/core/spsram.v | 8,896,328 | spsram.v | v | 60 | 76 | [] | ['apache license'] | [] | [(21, 59)] | null | data/verilator_xmls/8d6dafd2-afe4-49b8-bae2-7bb9d85ab960.xml | null | 305,590 | module | module spsram
#(parameter SIZE=4096,
parameter DATA_WIDTH=16,
parameter ADDR_WIDTH=$clog2(SIZE),
parameter ENABLE_INIT = 0,
parameter INIT_FILE="")
(input clk,
input[ADDR_WIDTH - 1:0] addr_a,
output reg[DATA_WIDTH - 1:0] q_a,
input we_a,
input[DATA_WIDTH - 1:0] data_a);
reg[DATA_WIDTH - 1:0] data[0:SIZE - 1];
integer i;
initial
begin
for (i = 0; i < SIZE; i = i + 1)
data[i] = 0;
q_a = 0;
if (ENABLE_INIT)
$readmemh(INIT_FILE, data);
end
always @(posedge clk)
begin
if (we_a)
begin
data[addr_a] <= data_a;
q_a <= data_a;
end
else
q_a <= data[addr_a];
end
endmodule | module spsram
#(parameter SIZE=4096,
parameter DATA_WIDTH=16,
parameter ADDR_WIDTH=$clog2(SIZE),
parameter ENABLE_INIT = 0,
parameter INIT_FILE="")
(input clk,
input[ADDR_WIDTH - 1:0] addr_a,
output reg[DATA_WIDTH - 1:0] q_a,
input we_a,
input[DATA_WIDTH - 1:0] data_a); |
reg[DATA_WIDTH - 1:0] data[0:SIZE - 1];
integer i;
initial
begin
for (i = 0; i < SIZE; i = i + 1)
data[i] = 0;
q_a = 0;
if (ENABLE_INIT)
$readmemh(INIT_FILE, data);
end
always @(posedge clk)
begin
if (we_a)
begin
data[addr_a] <= data_a;
q_a <= data_a;
end
else
q_a <= data[addr_a];
end
endmodule | 79 |
139,694 | data/full_repos/permissive/89087448/fpga/mem.v | 89,087,448 | mem.v | v | 43 | 55 | [] | [] | [] | null | line:9: before: "=" | null | 1: b"%Error: data/full_repos/permissive/89087448/fpga/mem.v:9: syntax error, unexpected '=', expecting ')' or ','\n output [0:DATA_WIDTH-1] com_data = 0,\n ^\n%Error: data/full_repos/permissive/89087448/fpga/mem.v:20: syntax error, unexpected always\nalways @ (posedge clk & oe_c)\n^~~~~~\n%Error: Exiting due to 2 error(s)\n" | 305,592 | module | module memory (
input oe_c,
input oe_d,
input clk,
input we,
input [0:ADDR_WIDTH-1] com_addr,
input [0:ADDR_WIDTH-1] data_addr,
output [0:DATA_WIDTH-1] com_data = 0,
output [0:DATA_WIDTH-1] data_read = 0,
input [0:DATA_WIDTH-1] data_write
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 10;
parameter MEM_SIZE = 1 << ADDR_WIDTH;
reg [0:DATA_WIDTH-1] mem [0:MEM_SIZE-1];
always @ (posedge clk & oe_c)
begin
if (!we)
begin
#5 com_data <= mem[com_addr];
end
end
always @ (posedge clk & oe_d)
begin
if (we)
begin
#5 mem[data_addr] <= data_write;
$display("data write\n");
end
if (!we)
begin
#5 data_read <= mem[data_addr];
$display("data read\n");
end
end
endmodule | module memory (
input oe_c,
input oe_d,
input clk,
input we,
input [0:ADDR_WIDTH-1] com_addr,
input [0:ADDR_WIDTH-1] data_addr,
output [0:DATA_WIDTH-1] com_data = 0,
output [0:DATA_WIDTH-1] data_read = 0,
input [0:DATA_WIDTH-1] data_write
); |
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 10;
parameter MEM_SIZE = 1 << ADDR_WIDTH;
reg [0:DATA_WIDTH-1] mem [0:MEM_SIZE-1];
always @ (posedge clk & oe_c)
begin
if (!we)
begin
#5 com_data <= mem[com_addr];
end
end
always @ (posedge clk & oe_d)
begin
if (we)
begin
#5 mem[data_addr] <= data_write;
$display("data write\n");
end
if (!we)
begin
#5 data_read <= mem[data_addr];
$display("data read\n");
end
end
endmodule | 1 |
139,697 | data/full_repos/permissive/89087448/fpga/test.v | 89,087,448 | test.v | v | 32 | 52 | [] | [] | [] | null | line:21: before: "$" | null | 1: b'%Error: data/full_repos/permissive/89087448/fpga/test.v:7: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("test.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/89087448/fpga/test.v:8: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, test);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/89087448/fpga/test.v:9: Unsupported: Ignoring delay on this delayed statement.\n#17 but1 = 1;\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/89087448/fpga/test.v:10: Unsupported: Ignoring delay on this delayed statement.\n#11 but2 = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/89087448/fpga/test.v:11: Unsupported: Ignoring delay on this delayed statement.\n#29 but2 = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/89087448/fpga/test.v:12: Unsupported: Ignoring delay on this delayed statement.\n#5 but1 = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/89087448/fpga/test.v:13: Unsupported: Ignoring delay on this delayed statement.\n#6 but2 = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/89087448/fpga/test.v:14: Unsupported: Ignoring delay on this delayed statement.\n#5 but2 = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/89087448/fpga/test.v:15: Unsupported: Ignoring delay on this delayed statement.\n#5 but2 = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/89087448/fpga/test.v:16: Unsupported: Ignoring delay on this delayed statement.\n#5 but1 = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/89087448/fpga/test.v:17: Unsupported: Ignoring delay on this delayed statement.\n#5 but2 = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/89087448/fpga/test.v:18: Unsupported: Ignoring delay on this delayed statement.\n#5 but2 = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/89087448/fpga/test.v:19: Unsupported: Ignoring delay on this delayed statement.\n#5 but2 = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/89087448/fpga/test.v:20: Unsupported: Ignoring delay on this delayed statement.\n#5 but2 = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/89087448/fpga/test.v:21: Unsupported: Ignoring delay on this delayed statement.\n#513 $finish;\n^\n%Error: data/full_repos/permissive/89087448/fpga/test.v:27: Unsupported or unknown PLI call: $monitor\n $monitor("At time %t, value = %h (%0d)",\n ^~~~~~~~\n%Error: Exiting due to 3 error(s), 13 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 305,595 | module | module test();
wire [7:0] value;
reg but1 = 0;
reg but2 = 0;
initial begin
$dumpfile("test.vcd");
$dumpvars(0, test);
#17 but1 = 1;
#11 but2 = 1;
#29 but2 = 0;
#5 but1 = 0;
#6 but2 = 1;
#5 but2 = 0;
#5 but2 = 1;
#5 but1 = 1;
#5 but2 = 0;
#5 but2 = 1;
#5 but2 = 0;
#5 but2 = 1;
#513 $finish;
end
top tp (but1, but2, value);
initial begin
$monitor("At time %t, value = %h (%0d)",
$time, value, value);
end
endmodule | module test(); |
wire [7:0] value;
reg but1 = 0;
reg but2 = 0;
initial begin
$dumpfile("test.vcd");
$dumpvars(0, test);
#17 but1 = 1;
#11 but2 = 1;
#29 but2 = 0;
#5 but1 = 0;
#6 but2 = 1;
#5 but2 = 0;
#5 but2 = 1;
#5 but1 = 1;
#5 but2 = 0;
#5 but2 = 1;
#5 but2 = 0;
#5 but2 = 1;
#513 $finish;
end
top tp (but1, but2, value);
initial begin
$monitor("At time %t, value = %h (%0d)",
$time, value, value);
end
endmodule | 1 |
139,698 | data/full_repos/permissive/89087448/fpga/top.v | 89,087,448 | top.v | v | 9 | 62 | [] | [] | [] | [(1, 8)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/89087448/fpga/top.v:4: Little bit endian vector: MSB < LSB of bit range: 0:7\n output [0:7] leds\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/89087448/fpga/top.v:7: Cannot find file containing module: \'shift_reg\'\nshift_reg sreg (.clk(~but2 | ~but1), .out(leds), .in(~but1));\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89087448/fpga,data/full_repos/permissive/89087448/shift_reg\n data/full_repos/permissive/89087448/fpga,data/full_repos/permissive/89087448/shift_reg.v\n data/full_repos/permissive/89087448/fpga,data/full_repos/permissive/89087448/shift_reg.sv\n shift_reg\n shift_reg.v\n shift_reg.sv\n obj_dir/shift_reg\n obj_dir/shift_reg.v\n obj_dir/shift_reg.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 305,596 | module | module top (
input but1,
input but2,
output [0:7] leds
);
shift_reg sreg (.clk(~but2 | ~but1), .out(leds), .in(~but1));
endmodule | module top (
input but1,
input but2,
output [0:7] leds
); |
shift_reg sreg (.clk(~but2 | ~but1), .out(leds), .in(~but1));
endmodule | 1 |
139,706 | data/full_repos/permissive/89151225/rtl/mem.v | 89,151,225 | mem.v | v | 86 | 86 | [] | [] | [] | null | line:54: before: "." | null | 1: b"%Error: data/full_repos/permissive/89151225/rtl/mem.v:23: Cannot find file containing module: 'altsyncram'\naltsyncram altsyncram_component (\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89151225/rtl,data/full_repos/permissive/89151225/altsyncram\n data/full_repos/permissive/89151225/rtl,data/full_repos/permissive/89151225/altsyncram.v\n data/full_repos/permissive/89151225/rtl,data/full_repos/permissive/89151225/altsyncram.sv\n altsyncram\n altsyncram.v\n altsyncram.sv\n obj_dir/altsyncram\n obj_dir/altsyncram.v\n obj_dir/altsyncram.sv\n%Error: Exiting due to 1 error(s)\n" | 305,982 | module | module mem #(
parameter WIDTH_SIZE = 256,
parameter NUM_WORDS_WIDTH = 8
) (
input clock,
input aclr,
input [NUM_WORDS_WIDTH - 1:0] address_a,
input [WIDTH_SIZE - 1:0] data_a,
input wren_a,
input rden_a,
output [WIDTH_SIZE - 1:0] q_a,
input [NUM_WORDS_WIDTH - 1:0] address_b,
input [WIDTH_SIZE - 1:0] data_b,
input wren_b,
input rden_b,
output [WIDTH_SIZE - 1:0] q_b
);
localparam NUM_WORDS_SIZE = 1 << NUM_WORDS_WIDTH;
altsyncram altsyncram_component (
.clock0 ( clock ),
.aclr0 ( aclr ),
.clock1 ( 1'b1 ),
.aclr1 ( 1'b0 ),
.address_a ( address_a ),
.wren_a ( wren_a ),
.rden_a ( rden_a ),
.data_a ( data_a ),
.q_a ( q_a ),
.address_b ( address_b ),
.wren_b ( wren_b ),
.rden_b ( rden_b ),
.data_b ( data_b ),
.q_b ( q_b ),
.addressstall_a ( 1'b0 ),
.addressstall_b ( 1'b0 ),
.byteena_a ( 1'b1 ),
.byteena_b ( 1'b1 ),
.clocken0 ( 1'b1 ),
.clocken1 ( 1'b1 ),
.clocken2 ( 1'b1 ),
.clocken3 ( 1'b1 ),
.eccstatus ( )
);
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "UNUSED",
altsyncram_component.intended_device_family = "Stratix V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = NUM_WORDS_SIZE,
altsyncram_component.numwords_b = NUM_WORDS_SIZE,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_a = "CLEAR0",
altsyncram_component.outdata_aclr_b = "CLEAR0",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = NUM_WORDS_WIDTH,
altsyncram_component.widthad_b = NUM_WORDS_WIDTH,
altsyncram_component.width_a = WIDTH_SIZE,
altsyncram_component.width_b = WIDTH_SIZE,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.rdcontrol_reg_b = "CLOCK0";
endmodule | module mem #(
parameter WIDTH_SIZE = 256,
parameter NUM_WORDS_WIDTH = 8
) (
input clock,
input aclr,
input [NUM_WORDS_WIDTH - 1:0] address_a,
input [WIDTH_SIZE - 1:0] data_a,
input wren_a,
input rden_a,
output [WIDTH_SIZE - 1:0] q_a,
input [NUM_WORDS_WIDTH - 1:0] address_b,
input [WIDTH_SIZE - 1:0] data_b,
input wren_b,
input rden_b,
output [WIDTH_SIZE - 1:0] q_b
); |
localparam NUM_WORDS_SIZE = 1 << NUM_WORDS_WIDTH;
altsyncram altsyncram_component (
.clock0 ( clock ),
.aclr0 ( aclr ),
.clock1 ( 1'b1 ),
.aclr1 ( 1'b0 ),
.address_a ( address_a ),
.wren_a ( wren_a ),
.rden_a ( rden_a ),
.data_a ( data_a ),
.q_a ( q_a ),
.address_b ( address_b ),
.wren_b ( wren_b ),
.rden_b ( rden_b ),
.data_b ( data_b ),
.q_b ( q_b ),
.addressstall_a ( 1'b0 ),
.addressstall_b ( 1'b0 ),
.byteena_a ( 1'b1 ),
.byteena_b ( 1'b1 ),
.clocken0 ( 1'b1 ),
.clocken1 ( 1'b1 ),
.clocken2 ( 1'b1 ),
.clocken3 ( 1'b1 ),
.eccstatus ( )
);
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "UNUSED",
altsyncram_component.intended_device_family = "Stratix V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = NUM_WORDS_SIZE,
altsyncram_component.numwords_b = NUM_WORDS_SIZE,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_a = "CLEAR0",
altsyncram_component.outdata_aclr_b = "CLEAR0",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = NUM_WORDS_WIDTH,
altsyncram_component.widthad_b = NUM_WORDS_WIDTH,
altsyncram_component.width_a = WIDTH_SIZE,
altsyncram_component.width_b = WIDTH_SIZE,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.rdcontrol_reg_b = "CLOCK0";
endmodule | 0 |
139,707 | data/full_repos/permissive/89151225/rtl/ram_test.sv | 89,151,225 | ram_test.sv | sv | 65 | 65 | [] | [] | [] | null | line:12: before: "[" | null | 1: b'%Error: data/full_repos/permissive/89151225/rtl/ram_test.sv:18: Cannot find file containing module: \'mem\'\nmem #(\n^~~\n ... Looked in:\n data/full_repos/permissive/89151225/rtl,data/full_repos/permissive/89151225/mem\n data/full_repos/permissive/89151225/rtl,data/full_repos/permissive/89151225/mem.v\n data/full_repos/permissive/89151225/rtl,data/full_repos/permissive/89151225/mem.sv\n mem\n mem.v\n mem.sv\n obj_dir/mem\n obj_dir/mem.v\n obj_dir/mem.sv\n%Warning-WIDTH: data/full_repos/permissive/89151225/rtl/ram_test.sv:52: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'wr_addr\' generates 8 bits.\n : ... In instance ram_test\n assign wr_data[g] = rd_data[g] + wr_addr + MAGIC;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 305,983 | module | module ram_test #(
parameter RAM_ADDR_W = 8,
parameter CHUNK_W = 32,
parameter CHUNK_CNT = 4,
parameter MAGIC = 0
) (
input clk_i,
input rst_i
);
logic [CHUNK_CNT-1:0][CHUNK_W-1:0] wr_data;
logic [CHUNK_CNT-1:0][CHUNK_W-1:0] rd_data;
logic [RAM_ADDR_W-1:0] wr_addr;
logic [RAM_ADDR_W-1:0] rd_addr;
mem #(
.WIDTH_SIZE ( $bits(wr_data) ),
.NUM_WORDS_WIDTH ( RAM_ADDR_W )
) mem (
.clock ( clk_i ),
.aclr ( 1'b0 ),
.address_b ( rd_addr ),
.data_b ( ),
.wren_b ( 1'b0 ),
.rden_b ( 1'b1 ),
.q_b ( rd_data ),
.address_a ( wr_addr ),
.data_a ( wr_data ),
.wren_a ( 1'b1 ),
.rden_a ( 1'b0 ),
.q_a ( )
);
always_ff @( posedge clk_i or posedge rst_i )
if( rst_i )
rd_addr <= MAGIC;
else
rd_addr <= rd_addr + 1'd1;
always_ff @( posedge clk_i )
wr_addr <= rd_addr;
genvar g;
generate
for( g = 0; g < CHUNK_CNT; g++ ) begin : g_logic
assign wr_data[g] = rd_data[g] + wr_addr + MAGIC;
end
endgenerate
logic [CHUNK_CNT*CHUNK_W-1:0] rd_data_w;
logic dummy_reg;
assign rd_data_w = rd_data;
always_ff @( posedge clk_i )
dummy_reg <= ^rd_data_w;
endmodule | module ram_test #(
parameter RAM_ADDR_W = 8,
parameter CHUNK_W = 32,
parameter CHUNK_CNT = 4,
parameter MAGIC = 0
) (
input clk_i,
input rst_i
); |
logic [CHUNK_CNT-1:0][CHUNK_W-1:0] wr_data;
logic [CHUNK_CNT-1:0][CHUNK_W-1:0] rd_data;
logic [RAM_ADDR_W-1:0] wr_addr;
logic [RAM_ADDR_W-1:0] rd_addr;
mem #(
.WIDTH_SIZE ( $bits(wr_data) ),
.NUM_WORDS_WIDTH ( RAM_ADDR_W )
) mem (
.clock ( clk_i ),
.aclr ( 1'b0 ),
.address_b ( rd_addr ),
.data_b ( ),
.wren_b ( 1'b0 ),
.rden_b ( 1'b1 ),
.q_b ( rd_data ),
.address_a ( wr_addr ),
.data_a ( wr_data ),
.wren_a ( 1'b1 ),
.rden_a ( 1'b0 ),
.q_a ( )
);
always_ff @( posedge clk_i or posedge rst_i )
if( rst_i )
rd_addr <= MAGIC;
else
rd_addr <= rd_addr + 1'd1;
always_ff @( posedge clk_i )
wr_addr <= rd_addr;
genvar g;
generate
for( g = 0; g < CHUNK_CNT; g++ ) begin : g_logic
assign wr_data[g] = rd_data[g] + wr_addr + MAGIC;
end
endgenerate
logic [CHUNK_CNT*CHUNK_W-1:0] rd_data_w;
logic dummy_reg;
assign rd_data_w = rd_data;
always_ff @( posedge clk_i )
dummy_reg <= ^rd_data_w;
endmodule | 0 |
139,708 | data/full_repos/permissive/89151225/rtl/top.sv | 89,151,225 | top.sv | sv | 29 | 53 | [] | [] | [] | null | line:13: before: "+" | null | 1: b"%Error: data/full_repos/permissive/89151225/rtl/top.sv:14: Cannot find file containing module: 'ram_test'\n ram_test #(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89151225/rtl,data/full_repos/permissive/89151225/ram_test\n data/full_repos/permissive/89151225/rtl,data/full_repos/permissive/89151225/ram_test.v\n data/full_repos/permissive/89151225/rtl,data/full_repos/permissive/89151225/ram_test.sv\n ram_test\n ram_test.v\n ram_test.sv\n obj_dir/ram_test\n obj_dir/ram_test.v\n obj_dir/ram_test.sv\n%Error: Exiting due to 1 error(s)\n" | 305,984 | module | module top(
input clk_i,
input rst_i
);
localparam RAM_ADDR_W = 8;
localparam CHUNK_W = 32;
localparam CHUNK_CNT = 1;
genvar g;
generate
for( g = 0; g < 1; g++ ) begin : g_ram_test_engine
ram_test #(
.RAM_ADDR_W ( RAM_ADDR_W ),
.CHUNK_W ( CHUNK_W ),
.CHUNK_CNT ( CHUNK_CNT ),
.MAGIC ( g )
) ram_test_engine (
.clk_i ( clk_i ),
.rst_i ( rst_i )
);
end
endgenerate
endmodule | module top(
input clk_i,
input rst_i
); |
localparam RAM_ADDR_W = 8;
localparam CHUNK_W = 32;
localparam CHUNK_CNT = 1;
genvar g;
generate
for( g = 0; g < 1; g++ ) begin : g_ram_test_engine
ram_test #(
.RAM_ADDR_W ( RAM_ADDR_W ),
.CHUNK_W ( CHUNK_W ),
.CHUNK_CNT ( CHUNK_CNT ),
.MAGIC ( g )
) ram_test_engine (
.clk_i ( clk_i ),
.rst_i ( rst_i )
);
end
endgenerate
endmodule | 0 |
139,714 | data/full_repos/permissive/89163277/counter/counter.v | 89,163,277 | counter.v | v | 10 | 38 | [] | [] | [] | [(1, 10)] | null | data/verilator_xmls/30fdf7f0-d567-4c4e-a44e-99c13faa172e.xml | null | 305,990 | module | module counter (out, clear, control);
input clear, control;
output [1:0]out;
reg [1:0]out;
always @ (*)
if (clear == 1 && control == 0)
out=0;
else
out=out+1;
endmodule | module counter (out, clear, control); |
input clear, control;
output [1:0]out;
reg [1:0]out;
always @ (*)
if (clear == 1 && control == 0)
out=0;
else
out=out+1;
endmodule | 1 |
139,715 | data/full_repos/permissive/89163277/mealy_machine/Mealy_Machine.v | 89,163,277 | Mealy_Machine.v | v | 79 | 50 | [] | [] | [] | [(8, 78)] | null | data/verilator_xmls/51fdaf27-ba48-42da-a5b6-dccd48ccc9f3.xml | null | 305,991 | module | module Mealy_Machine(clock, reset, x, y);
input clock, reset, x;
output y;
reg [1:0] state;
reg y;
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;
always @(posedge clock, posedge reset)
begin
if(reset)
begin
state <= S0;
y <= 0;
end
else
begin
case(state)
S0:
begin
if(x)
begin
state <= S1;
y <= 0;
end
else
begin
state <= S2;
y <= 0;
end
end
S1:
begin
if(x)
begin
state <= S0;
y <= 1;
end
else
begin
state <= S2;
y <= 0;
end
end
S2:
begin
if(x)
begin
state <= S1;
y <= 0;
end
else
begin
state <= S0;
y <= 1;
end
end
default:
begin
state <= S0;
y <= 0;
end
endcase
end
end
endmodule | module Mealy_Machine(clock, reset, x, y); |
input clock, reset, x;
output y;
reg [1:0] state;
reg y;
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;
always @(posedge clock, posedge reset)
begin
if(reset)
begin
state <= S0;
y <= 0;
end
else
begin
case(state)
S0:
begin
if(x)
begin
state <= S1;
y <= 0;
end
else
begin
state <= S2;
y <= 0;
end
end
S1:
begin
if(x)
begin
state <= S0;
y <= 1;
end
else
begin
state <= S2;
y <= 0;
end
end
S2:
begin
if(x)
begin
state <= S1;
y <= 0;
end
else
begin
state <= S0;
y <= 1;
end
end
default:
begin
state <= S0;
y <= 0;
end
endcase
end
end
endmodule | 1 |
139,720 | data/full_repos/permissive/89163277/universal_shift_register/universal_shift_register.v | 89,163,277 | universal_shift_register.v | v | 26 | 63 | [] | [] | [] | [(1, 26)] | null | data/verilator_xmls/b3df0110-47ca-4350-abe5-bfee6a198c44.xml | null | 305,996 | module | module universal_shift_register(clk,in,out,reset,control,inn);
input clk, reset,in;
input [3:0] inn;
input [1:0] control;
output [3:0] out;
reg [3:0] r_reg,r_next;
always @ (posedge clk or posedge reset)
begin
if(reset)
r_reg <=0;
else
r_reg <= r_next;
end
always @ (*)
begin
if (control [0])
r_next = {in,r_reg[3:1]};
else if (control [1])
r_next = {r_reg[2:0],in};
else if (control[0]&control[1])
r_next = inn;
else
r_next=r_reg;
end
assign out=r_reg;
endmodule | module universal_shift_register(clk,in,out,reset,control,inn); |
input clk, reset,in;
input [3:0] inn;
input [1:0] control;
output [3:0] out;
reg [3:0] r_reg,r_next;
always @ (posedge clk or posedge reset)
begin
if(reset)
r_reg <=0;
else
r_reg <= r_next;
end
always @ (*)
begin
if (control [0])
r_next = {in,r_reg[3:1]};
else if (control [1])
r_next = {r_reg[2:0],in};
else if (control[0]&control[1])
r_next = inn;
else
r_next=r_reg;
end
assign out=r_reg;
endmodule | 1 |
139,722 | data/full_repos/permissive/89163277/up_down_counter/seven_segment_disp_two.v | 89,163,277 | seven_segment_disp_two.v | v | 24 | 39 | [] | [] | [] | [(1, 24)] | null | data/verilator_xmls/44025514-19ef-4c26-b487-6a1d72543f18.xml | null | 305,999 | module | module seven_segment_disp_two(in,out);
input [3:0]in;
output [6:0]out;
reg [6:0]out;
always@(in)
case(in)
4'h0:out=~7'h3F;
4'h1:out=~7'h3F;
4'h2:out=~7'h3F;
4'h3:out=~7'h3F;
4'h4:out=~7'h3F;
4'h5:out=~7'h3F;
4'h6:out=~7'h3F;
4'h7:out=~7'h3F;
4'h8:out=~7'h3F;
4'h9:out=~7'h3F;
4'ha:out=~7'h06;
4'hb:out=~7'h06;
4'hc:out=~7'h06;
4'hd:out=~7'h06;
4'he:out=~7'h06;
4'hf:out=~7'h06;
endcase
endmodule | module seven_segment_disp_two(in,out); |
input [3:0]in;
output [6:0]out;
reg [6:0]out;
always@(in)
case(in)
4'h0:out=~7'h3F;
4'h1:out=~7'h3F;
4'h2:out=~7'h3F;
4'h3:out=~7'h3F;
4'h4:out=~7'h3F;
4'h5:out=~7'h3F;
4'h6:out=~7'h3F;
4'h7:out=~7'h3F;
4'h8:out=~7'h3F;
4'h9:out=~7'h3F;
4'ha:out=~7'h06;
4'hb:out=~7'h06;
4'hc:out=~7'h06;
4'hd:out=~7'h06;
4'he:out=~7'h06;
4'hf:out=~7'h06;
endcase
endmodule | 1 |
139,723 | data/full_repos/permissive/89163277/up_down_counter/t_flipflop.v | 89,163,277 | t_flipflop.v | v | 15 | 42 | [] | [] | [] | null | line:5: before: "(" | data/verilator_xmls/8dc8f5fd-2061-4db2-a87d-dbfd066740c8.xml | null | 306,000 | module | module t_flipflop(q,t,clk,clr,control);
input t,clk,clr,control;
output q;
reg q;
always @ (negedge (clk) or negedge (clr))
begin
if(clr == 0)
q = 0;
else if (t == 1)
q = ~q;
else
q = q;
end
endmodule | module t_flipflop(q,t,clk,clr,control); |
input t,clk,clr,control;
output q;
reg q;
always @ (negedge (clk) or negedge (clr))
begin
if(clr == 0)
q = 0;
else if (t == 1)
q = ~q;
else
q = q;
end
endmodule | 1 |
139,725 | data/full_repos/permissive/89514111/verilog/dot11.v | 89,514,111 | dot11.v | v | 1,084 | 174 | [] | [] | [] | [(11, 1165)] | null | null | 1: b'%Error: data/full_repos/permissive/89514111/verilog/dot11.v:1: Cannot find include file: common_defs.v\n`include "common_defs.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89514111/verilog,data/full_repos/permissive/89514111/common_defs.v\n data/full_repos/permissive/89514111/verilog,data/full_repos/permissive/89514111/common_defs.v.v\n data/full_repos/permissive/89514111/verilog,data/full_repos/permissive/89514111/common_defs.v.sv\n common_defs.v\n common_defs.v.v\n common_defs.v.sv\n obj_dir/common_defs.v\n obj_dir/common_defs.v.v\n obj_dir/common_defs.v.sv\n%Error: data/full_repos/permissive/89514111/verilog/dot11.v:120: Cannot find include file: common_params.v\n`include "common_params.v" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89514111/verilog/dot11.v:147: Define or directive not defined: \'`ROTATE_LUT_LEN_SHIFT\'\nwire [`ROTATE_LUT_LEN_SHIFT-1:0] sync_long_rot_addr;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89514111/verilog/dot11.v:150: Define or directive not defined: \'`ROTATE_LUT_LEN_SHIFT\'\nwire [`ROTATE_LUT_LEN_SHIFT-1:0] eq_rot_addr;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89514111/verilog/dot11.v:447: syntax error, unexpected bit\n .bit(crc_in),\n ^~~\n%Error: Exiting due to 5 error(s)\n' | 306,538 | module | module dot11 (
input clock,
input enable,
input reset,
input [10:0] power_thres,
input [31:0] min_plateau,
input [10:0] rssi_half_db,
input [31:0] sample_in,
input sample_in_strobe,
input soft_decoding,
input wire force_ht_smoothing,
input wire disable_all_smoothing,
output reg demod_is_ongoing,
output reg pkt_begin,
output reg pkt_ht,
output reg pkt_header_valid,
output reg pkt_header_valid_strobe,
output reg ht_unsupport,
output reg [7:0] pkt_rate,
output reg [15:0] pkt_len,
output reg [15:0] pkt_len_total,
output byte_out_strobe,
output [7:0] byte_out,
output reg [15:0] byte_count_total,
output reg [15:0] byte_count,
output reg fcs_out_strobe,
output reg fcs_ok,
output reg [4:0] state,
output reg [3:0] status_code,
output state_changed,
output reg [31:0] state_history,
output power_trigger,
output short_preamble_detected,
output [15:0] phase_offset,
output [31:0] sync_long_metric,
output sync_long_metric_stb,
output long_preamble_detected,
output [31:0] sync_long_out,
output sync_long_out_strobe,
output wire signed [31:0] phase_offset_taken,
output [2:0] sync_long_state,
output [31:0] equalizer_out,
output equalizer_out_strobe,
output [3:0] equalizer_state,
output wire ofdm_symbol_eq_out_pulse,
output reg legacy_sig_stb,
output [3:0] legacy_rate,
output legacy_sig_rsvd,
output [11:0] legacy_len,
output legacy_sig_parity,
output legacy_sig_parity_ok,
output [5:0] legacy_sig_tail,
output reg ht_sig_stb,
output [6:0] ht_mcs,
output ht_cbw,
output [15:0] ht_len,
output ht_smoothing,
output ht_not_sounding,
output ht_aggr,
output reg ht_aggr_last,
output [1:0] ht_stbc,
output ht_fec_coding,
output ht_sgi,
output [1:0] ht_num_ext,
output reg ht_sig_crc_ok,
output [5:0] demod_out,
output [5:0] demod_soft_bits,
output [3:0] demod_soft_bits_pos,
output demod_out_strobe,
output [7:0] deinterleave_erase_out,
output deinterleave_erase_out_strobe,
output conv_decoder_out,
output conv_decoder_out_stb,
output descramble_out,
output descramble_out_strobe,
output wire [31:0] csi,
output wire csi_valid
);
`include "common_params.v"
reg [3:0] equalizer_state_reg;
assign ofdm_symbol_eq_out_pulse = (equalizer_state==4 && equalizer_state_reg==7);
always @(posedge clock) begin
if (reset==1) begin
state_history <= 0;
equalizer_state_reg <= 0;
end else begin
equalizer_state_reg <= equalizer_state;
if (state_changed) begin
state_history[3:0] <= state;
state_history[31:4] <= state_history[27:0];
end
end
end
wire [`ROTATE_LUT_LEN_SHIFT-1:0] sync_long_rot_addr;
wire [31:0] sync_long_rot_data;
wire [`ROTATE_LUT_LEN_SHIFT-1:0] eq_rot_addr;
wire [31:0] eq_rot_data;
rot_lut rot_lut_inst (
.clka(clock),
.addra(sync_long_rot_addr),
.douta(sync_long_rot_data),
.clkb(clock),
.addrb(eq_rot_addr),
.doutb(eq_rot_data)
);
wire [31:0] sync_short_phase_in_i;
wire [31:0] sync_short_phase_in_q;
wire sync_short_phase_in_stb;
wire [15:0] sync_short_phase_out;
wire sync_short_phase_out_stb;
wire [31:0] eq_phase_in_i;
wire [31:0] eq_phase_in_q;
wire eq_phase_in_stb;
wire [15:0] eq_phase_out;
wire eq_phase_out_stb;
wire[31:0] phase_in_i = state == S_SYNC_SHORT?
sync_short_phase_in_i: eq_phase_in_i;
wire[31:0] phase_in_q = state == S_SYNC_SHORT?
sync_short_phase_in_q: eq_phase_in_q;
wire phase_in_stb = state == S_SYNC_SHORT?
sync_short_phase_in_stb: eq_phase_in_stb;
wire [15:0] phase_out;
wire phase_out_stb;
assign sync_short_phase_out = phase_out;
assign sync_short_phase_out_stb = phase_out_stb;
assign eq_phase_out = phase_out;
assign eq_phase_out_stb = phase_out_stb;
phase phase_inst (
.clock(clock),
.reset(reset),
.enable(enable),
.in_i(phase_in_i),
.in_q(phase_in_q),
.input_strobe(phase_in_stb),
.phase(phase_out),
.output_strobe(phase_out_stb)
);
reg sync_short_reset;
reg sync_long_reset;
wire sync_short_enable = state == S_SYNC_SHORT;
reg sync_long_enable;
wire [15:0] num_ofdm_symbol;
reg equalizer_reset;
reg equalizer_enable;
reg ht_next;
wire eq_out_stb_delayed;
wire [15:0] eq_out_i = equalizer_out[31:16];
wire [15:0] eq_out_q = equalizer_out[15:0];
wire [15:0] eq_out_i_delayed;
wire [15:0] eq_out_q_delayed;
reg [15:0] abs_eq_i;
reg [15:0] abs_eq_q;
reg [3:0] rot_eq_count;
reg [3:0] normal_eq_count;
reg ofdm_reset;
reg ofdm_enable;
reg ofdm_in_stb;
reg [15:0] ofdm_in_i;
reg [15:0] ofdm_in_q;
reg do_descramble;
reg [31:0] num_bits_to_decode;
reg short_gi;
reg [4:0] old_state;
assign power_trigger = (rssi_half_db>=power_thres? 1: 0);
assign state_changed = state != old_state;
reg [23:0] signal_bits;
assign legacy_rate = signal_bits[3:0];
assign legacy_sig_rsvd = signal_bits[4];
assign legacy_len = signal_bits[16:5];
assign legacy_sig_parity = signal_bits[17];
assign legacy_sig_tail = signal_bits[23:18];
assign legacy_sig_parity_ok = ~^signal_bits[17:0];
reg [23:0] ht_sig1;
reg [23:0] ht_sig2;
assign ht_mcs = ht_sig1[6:0];
assign ht_cbw = ht_sig1[7];
assign ht_len = ht_sig1[23:8];
assign ht_smoothing = ht_sig2[0];
assign ht_not_sounding = ht_sig2[1];
assign ht_aggr = ht_sig2[3];
assign ht_stbc = ht_sig2[5:4];
assign ht_fec_coding = ht_sig2[6];
assign ht_sgi = ht_sig2[7];
assign ht_num_ext = ht_sig2[9:8];
wire ht_rsvd = ht_sig2[2];
wire [7:0] crc = ht_sig2[17:10];
wire [5:0] ht_sig_tail = ht_sig2[23:18];
reg [15:0] pkt_len_rem;
reg [7:0] mpdu_del_crc;
reg [1:0] mpdu_pad;
reg crc_in_stb;
reg crc_in;
reg [7:0] crc_count;
reg crc_reset;
wire [7:0] crc_out;
reg [31:0] sample_count;
wire fcs_enable = state == S_DECODE_DATA && byte_out_strobe;
wire fcs_reset = state_changed && state == S_DECODE_DATA;
wire [7:0] byte_reversed;
wire [31:0] pkt_fcs;
assign byte_reversed[0] = byte_out[7];
assign byte_reversed[1] = byte_out[6];
assign byte_reversed[2] = byte_out[5];
assign byte_reversed[3] = byte_out[4];
assign byte_reversed[4] = byte_out[3];
assign byte_reversed[5] = byte_out[2];
assign byte_reversed[6] = byte_out[1];
assign byte_reversed[7] = byte_out[0];
reg [15:0] sync_long_out_count;
sync_short sync_short_inst (
.clock(clock),
.reset(reset | sync_short_reset),
.enable(enable & sync_short_enable),
.min_plateau(min_plateau),
.sample_in(sample_in),
.sample_in_strobe(sample_in_strobe),
.phase_in_i(sync_short_phase_in_i),
.phase_in_q(sync_short_phase_in_q),
.phase_in_stb(sync_short_phase_in_stb),
.phase_out(sync_short_phase_out),
.phase_out_stb(sync_short_phase_out_stb),
.short_preamble_detected(short_preamble_detected),
.phase_offset(phase_offset)
);
sync_long sync_long_inst (
.clock(clock),
.reset(reset | sync_long_reset),
.enable(enable & sync_long_enable),
.sample_in(sample_in),
.sample_in_strobe(sample_in_strobe),
.phase_offset(phase_offset),
.short_gi(short_gi),
.rot_addr(sync_long_rot_addr),
.rot_data(sync_long_rot_data),
.metric(sync_long_metric),
.metric_stb(sync_long_metric_stb),
.long_preamble_detected(long_preamble_detected),
.phase_offset_taken(phase_offset_taken),
.state(sync_long_state),
.sample_out(sync_long_out),
.sample_out_strobe(sync_long_out_strobe),
.num_ofdm_symbol(num_ofdm_symbol)
);
equalizer equalizer_inst (
.clock(clock),
.reset(reset | equalizer_reset),
.enable(enable & equalizer_enable),
.sample_in(sync_long_out),
.sample_in_strobe(sync_long_out_strobe && !(state==S_HT_SIGNAL && num_ofdm_symbol==6)),
.ht_next(ht_next),
.pkt_ht(pkt_ht),
.ht_smoothing(ht_smoothing|force_ht_smoothing),
.disable_all_smoothing(disable_all_smoothing),
.phase_in_i(eq_phase_in_i),
.phase_in_q(eq_phase_in_q),
.phase_in_stb(eq_phase_in_stb),
.phase_out(eq_phase_out),
.phase_out_stb(eq_phase_out_stb),
.rot_addr(eq_rot_addr),
.rot_data(eq_rot_data),
.sample_out(equalizer_out),
.sample_out_strobe(equalizer_out_strobe),
.state(equalizer_state),
.csi(csi),
.csi_valid(csi_valid)
);
delayT #(.DATA_WIDTH(33), .DELAY(9)) eq_delay_inst (
.clock(clock),
.reset(reset),
.data_in({equalizer_out_strobe, equalizer_out}),
.data_out({eq_out_stb_delayed, eq_out_i_delayed, eq_out_q_delayed})
);
ofdm_decoder ofdm_decoder_inst (
.clock(clock),
.reset(reset|ofdm_reset),
.enable(enable & ofdm_enable),
.sample_in({ofdm_in_i, ofdm_in_q}),
.sample_in_strobe(ofdm_in_stb),
.soft_decoding(soft_decoding),
.do_descramble(do_descramble),
.num_bits_to_decode(num_bits_to_decode),
.rate(pkt_rate),
.byte_out(byte_out),
.byte_out_strobe(byte_out_strobe),
.demod_out(demod_out),
.demod_soft_bits(demod_soft_bits),
.demod_soft_bits_pos(demod_soft_bits_pos),
.demod_out_strobe(demod_out_strobe),
.deinterleave_erase_out(deinterleave_erase_out),
.deinterleave_erase_out_strobe(deinterleave_erase_out_strobe),
.conv_decoder_out(conv_decoder_out),
.conv_decoder_out_stb(conv_decoder_out_stb),
.descramble_out(descramble_out),
.descramble_out_strobe(descramble_out_strobe)
);
ht_sig_crc crc_inst (
.clock(clock),
.enable(enable),
.reset(reset | crc_reset),
.bit(crc_in),
.input_strobe(crc_in_stb),
.crc(crc_out)
);
crc32 fcs_inst (
.clk(clock),
.crc_en(enable & fcs_enable),
.rst(reset | fcs_reset),
.data_in(byte_reversed),
.crc_out(pkt_fcs)
);
always @(posedge clock) begin
if (reset) begin
status_code <= E_OK;
state <= S_WAIT_POWER_TRIGGER;
old_state <= 0;
sync_short_reset <= 0;
sync_long_reset <= 0;
sync_long_enable <= 0;
byte_count <= 0;
byte_count_total <= 0;
demod_is_ongoing <= 0;
pkt_begin <= 0;
pkt_ht <= 0;
pkt_header_valid <= 0;
pkt_header_valid_strobe <= 0;
ht_unsupport <= 0;
rot_eq_count <= 0;
normal_eq_count <= 0;
abs_eq_i <= 0;
abs_eq_q <= 0;
do_descramble <= 0;
num_bits_to_decode <= 0;
short_gi <= 0;
pkt_rate <= 0;
equalizer_reset <= 0;
equalizer_enable <= 0;
ht_next <= 0;
pkt_len_rem <= 0;
mpdu_del_crc <= 0;
mpdu_pad <= 0;
pkt_len <= 0;
pkt_len_total <= 0;
ofdm_reset <= 0;
ofdm_enable <= 0;
ofdm_in_stb <= 0;
ofdm_in_i <= 0;
ofdm_in_q <= 0;
sample_count <= 0;
sync_long_out_count <= 0;
signal_bits <= 0;
legacy_sig_stb <= 0;
ht_sig1 <= 0;
ht_sig2 <= 0;
crc_in_stb <= 0;
crc_in <= 0;
crc_count <= 0;
crc_reset <= 0;
ht_sig_crc_ok <= 0;
ht_sig_stb <= 0;
ht_aggr_last <= 0;
fcs_out_strobe <= 0;
fcs_ok <= 0;
end else if (enable) begin
old_state <= state;
case(state)
S_WAIT_POWER_TRIGGER: begin
pkt_begin <= 0;
pkt_ht <= 0;
crc_reset <= 0;
short_gi <= 0;
demod_is_ongoing <= 0;
sync_long_enable <= 0;
equalizer_enable <= 0;
ofdm_enable <= 0;
ofdm_reset <= 0;
pkt_len_total <= 16'hffff;
ht_sig1 <= 0;
ht_sig2 <= 0;
pkt_len_rem <= 0;
if (power_trigger) begin
`ifdef DEBUG_PRINT
$display("Power triggered.");
`endif
sync_short_reset <= 1;
state <= S_SYNC_SHORT;
end
end
S_SYNC_SHORT: begin
if (sync_short_reset) begin
sync_short_reset <= 0;
end
if (~power_trigger) begin
state <= S_WAIT_POWER_TRIGGER;
end
if (short_preamble_detected) begin
`ifdef DEBUG_PRINT
$display("Short preamble detected");
`endif
sync_long_reset <= 1;
sync_long_enable <= 1;
sample_count <= 0;
state <= S_SYNC_LONG;
end
end
S_SYNC_LONG: begin
if (sync_long_reset) begin
sync_long_reset <= 0;
end
if (sample_in_strobe) begin
sample_count <= sample_count + 1;
end
if (sample_count > 320) begin
state <= S_WAIT_POWER_TRIGGER;
end
if (~power_trigger) begin
state <= S_WAIT_POWER_TRIGGER;
end
if (long_preamble_detected) begin
demod_is_ongoing <= 1;
pkt_rate <= {1'b0, 3'b0, 4'b1011};
do_descramble <= 0;
num_bits_to_decode <= 48;
ofdm_reset <= 1;
ofdm_enable <= 1;
equalizer_enable <= 1;
equalizer_reset <= 1;
byte_count <= 0;
byte_count_total <= 0;
state <= S_DECODE_SIGNAL;
end
end
S_DECODE_SIGNAL: begin
ofdm_reset <= 0;
if (equalizer_reset) begin
equalizer_reset <= 0;
end
ofdm_in_stb <= equalizer_out_strobe;
ofdm_in_i <= eq_out_i;
ofdm_in_q <= eq_out_q;
if (byte_out_strobe) begin
signal_bits <= {byte_out, signal_bits[23:8]};
byte_count <= byte_count + 1;
byte_count_total <= byte_count_total + 1;
end
if (byte_count == 3) begin
byte_count <= 0;
`ifdef DEBUG_PRINT
$display("[SIGNAL] rate = %04b, ", legacy_rate,
"length = %012b (%d), ", legacy_len, legacy_len,
"parity = %b, ", legacy_sig_parity,
"tail = %6b", legacy_sig_tail);
`endif
num_bits_to_decode <= (22+(legacy_len<<3))<<1;
pkt_rate <= {1'b0, 3'b0, legacy_rate};
pkt_len <= legacy_len;
pkt_len_total <= legacy_len+3;
ofdm_reset <= 1;
state <= S_CHECK_SIGNAL;
end
end
S_CHECK_SIGNAL: begin
if (~legacy_sig_parity_ok) begin
pkt_header_valid_strobe <= 1;
status_code <= E_PARITY_FAIL;
state <= S_SIGNAL_ERROR;
end else if (legacy_sig_rsvd) begin
pkt_header_valid_strobe <= 1;
status_code <= E_WRONG_RSVD;
state <= S_SIGNAL_ERROR;
end else if (|legacy_sig_tail) begin
pkt_header_valid_strobe <= 1;
status_code <= E_WRONG_TAIL;
state <= S_SIGNAL_ERROR;
end else if (legacy_rate[3]==0) begin
pkt_header_valid_strobe <= 1;
status_code <= E_UNSUPPORTED_RATE;
state <= S_SIGNAL_ERROR;
end else begin
legacy_sig_stb <= 1;
status_code <= E_OK;
if (legacy_rate == 4'b1011) begin
abs_eq_i <= 0;
abs_eq_q <= 0;
rot_eq_count <= 0;
normal_eq_count <= 0;
state <= S_DETECT_HT;
end else begin
do_descramble <= 1;
ofdm_reset <= 1;
pkt_header_valid <= 1;
pkt_header_valid_strobe <= 1;
pkt_begin <= 1;
state <= S_DECODE_DATA;
end
end
end
S_SIGNAL_ERROR: begin
pkt_header_valid_strobe <= 0;
byte_count <= 0;
byte_count_total <= 0;
state <= S_WAIT_POWER_TRIGGER;
end
S_DETECT_HT: begin
legacy_sig_stb <= 0;
ofdm_reset <= 1;
if (equalizer_out_strobe) begin
abs_eq_i <= eq_out_i[15]? ~eq_out_i+1: eq_out_i;
abs_eq_q <= eq_out_q[15]? ~eq_out_q+1: eq_out_q;
if (abs_eq_q > abs_eq_i) begin
rot_eq_count <= rot_eq_count + 1;
end else if (abs_eq_q < abs_eq_i) begin
normal_eq_count <= normal_eq_count + 1;
end
end
if (rot_eq_count >= 4) begin
num_bits_to_decode <= 96;
do_descramble <= 0;
state <= S_HT_SIGNAL;
end else if (normal_eq_count > 4) begin
do_descramble <= 1;
pkt_header_valid <= 1;
pkt_header_valid_strobe <= 1;
pkt_begin <= 1;
state <= S_DECODE_DATA;
end
end
S_HT_SIGNAL: begin
ofdm_reset <= 0;
ofdm_in_stb <= eq_out_stb_delayed;
ofdm_in_i <= eq_out_q_delayed;
ofdm_in_q <= ~eq_out_i_delayed+1;
if (byte_out_strobe) begin
if (byte_count < 3) begin
ht_sig1 <= {byte_out, ht_sig1[23:8]};
end else begin
ht_sig2 <= {byte_out, ht_sig2[23:8]};
end
byte_count <= byte_count + 1;
byte_count_total <= byte_count_total + 1;
end
if (byte_count == 6) begin
byte_count <= 0;
`ifdef DEBUG_PRINT
$display("[HT SIGNAL] mcs = %07b (%d), ", ht_mcs, ht_mcs,
"CBW: %d, ", ht_cbw? 40: 20,
"length = %012b (%d), ", ht_len, ht_len,
"rsvd = %d, ", ht_rsvd,
"aggr = %d, ", ht_aggr,
"aggr_last = %d, ", ht_aggr_last,
"stbd = %02b, ", ht_stbc,
"fec = %d, ", ht_fec_coding,
"sgi = %d, ", ht_sgi,
"num_ext = %d, ", ht_num_ext,
"crc = %08b, ", crc,
"tail = %06b", ht_sig_tail);
`endif
num_bits_to_decode <= (22+(ht_len<<3))<<1;
pkt_rate <= {1'b1, ht_mcs};
pkt_len_rem <= ht_len;
pkt_len <= ht_len;
pkt_len_total <= ht_len+3+6;
crc_count <= 0;
crc_reset <= 1;
crc_in_stb <= 0;
ht_sig_crc_ok <= 0;
state <= S_CHECK_HT_SIG_CRC;
end
end
S_CHECK_HT_SIG_CRC: begin
ofdm_reset <= 1;
crc_reset <= 0;
crc_count <= crc_count + 1;
if (crc_count < 24) begin
crc_in_stb <= 1;
crc_in <= ht_sig1[crc_count];
end else if (crc_count < 34) begin
crc_in_stb <= 1;
crc_in <= ht_sig2[crc_count-24];
end else if (crc_count == 34) begin
crc_in_stb <= 0;
end else if (crc_count == 35) begin
ht_sig_stb <= 1;
pkt_ht <= 1;
if (crc_out ^ crc) begin
pkt_header_valid_strobe <= 1;
status_code <= E_WRONG_CRC;
state <= S_HT_SIG_ERROR;
end else begin
`ifdef DEBUG_PRINT
$display("[HT SIGNAL] CRC OK");
`endif
ht_sig_crc_ok <= 1;
state <= S_CHECK_HT_SIG;
end
end
end
S_CHECK_HT_SIG: begin
ofdm_reset <= 1;
ht_sig_stb <= 0;
ht_aggr_last <= 0;
if (ht_mcs > 7) begin
ht_unsupport <= 1;
status_code <= E_UNSUPPORTED_MCS;
state <= S_HT_SIG_ERROR;
end else if (ht_cbw) begin
ht_unsupport <= 1;
status_code <= E_UNSUPPORTED_CBW;
state <= S_HT_SIG_ERROR;
end else if (ht_rsvd == 0) begin
ht_unsupport <= 1;
status_code <= E_HT_WRONG_RSVD;
state <= S_HT_SIG_ERROR;
end else if (ht_stbc != 0) begin
ht_unsupport <= 1;
status_code <= E_UNSUPPORTED_STBC;
state <= S_HT_SIG_ERROR;
end else if (ht_fec_coding) begin
ht_unsupport <= 1;
status_code <= E_UNSUPPORTED_FEC;
state <= S_HT_SIG_ERROR;
end else if (ht_num_ext != 0) begin
ht_unsupport <= 1;
status_code <= E_UNSUPPORTED_SPATIAL;
state <= S_HT_SIG_ERROR;
end else if (ht_sig_tail != 0) begin
ht_unsupport <= 1;
status_code <= E_HT_WRONG_TAIL;
state <= S_HT_SIG_ERROR;
end else begin
sync_long_out_count <= 0;
if (num_ofdm_symbol == 5) begin
state <= S_HT_STS;
end else begin
ht_next <= 1;
state <= S_HT_LTS;
end
end
end
S_HT_SIG_ERROR: begin
ht_unsupport <= 0;
pkt_header_valid <= 0;
pkt_header_valid_strobe <= 0;
byte_count <= 0;
byte_count_total <= 0;
ht_sig_stb <= 0;
state <= S_WAIT_POWER_TRIGGER;
end
S_HT_STS: begin
if (sync_long_out_strobe) begin
sync_long_out_count <= sync_long_out_count + 1;
end
if (sync_long_out_count == 64) begin
sync_long_out_count <= 0;
ht_next <= 1;
state <= S_HT_LTS;
end
end
S_HT_LTS: begin
short_gi <= ht_sgi;
if (sync_long_out_strobe) begin
sync_long_out_count <= sync_long_out_count + 1;
end
if (sync_long_out_count == 64) begin
ht_next <= 0;
do_descramble <= 1;
ofdm_reset <= 1;
if(ht_aggr) begin
crc_reset <= 1;
crc_count <= 0;
state <= S_MPDU_DELIM;
end else begin
pkt_header_valid <= 1;
pkt_header_valid_strobe <= 1;
pkt_begin <= 1;
pkt_len_rem <= 0;
state <= S_DECODE_DATA;
end
end
end
S_MPDU_DELIM: begin
crc_reset <= 0;
ofdm_reset <= 0;
ofdm_in_stb <= eq_out_stb_delayed;
ofdm_in_i <= eq_out_i_delayed;
ofdm_in_q <= eq_out_q_delayed;
if(byte_out_strobe) begin
if(byte_count == 3) begin
byte_count <= 0;
byte_count_total <= 3+6;
if(crc_out == mpdu_del_crc && byte_out == 8'h4e) begin
if(pkt_len == 0) begin
pkt_len_rem <= pkt_len_rem - 4;
crc_reset <= 1;
crc_count <= 0;
state <= S_MPDU_DELIM;
end else begin
pkt_header_valid <= 1;
pkt_header_valid_strobe <= 1;
pkt_len_total <= pkt_len+3+6;
pkt_begin <= 1;
state <= S_DECODE_DATA;
if((pkt_len_rem-pkt_len-mpdu_pad) > 4) begin
ht_aggr_last <= 0;
pkt_len_rem <= pkt_len_rem - (4 + pkt_len + mpdu_pad);
end else begin
ht_aggr_last <= 1;
pkt_len_rem <= 0;
end
end
end else if(|pkt_len_rem[15:3] == 0) begin
ht_aggr_last <= 1;
fcs_out_strobe <= 1;
fcs_ok <= 0;
status_code <= E_HT_AMPDU_ERROR;
state <= S_DECODE_DONE;
end else begin
pkt_len_rem <= pkt_len_rem - 4;
crc_reset <= 1;
crc_count <= 0;
status_code <= E_HT_AMPDU_WARN;
state <= S_MPDU_DELIM;
end
end else begin
byte_count <= byte_count + 1;
byte_count_total <= byte_count_total + 1;
if(byte_count == 0) begin
pkt_len[3:0] <= byte_out[7:4];
end else if(byte_count == 1) begin
pkt_len[11:4] <= byte_out;
end else if(byte_count == 2) begin
pkt_len[15:12] <= 0;
mpdu_del_crc <= byte_out;
if(pkt_len[1:0] == 0)
mpdu_pad <= 0;
else if(pkt_len[1:0] == 1)
mpdu_pad <= 3;
else if(pkt_len[1:0] == 2)
mpdu_pad <= 2;
else
mpdu_pad <= 1;
end
if(crc_count[4] == 0) begin
crc_in <= byte_out[crc_count[2:0]];
crc_in_stb <= 1;
crc_count <= crc_count + 1;
end else begin
crc_in_stb <= 0;
end
end
end else if((^byte_count[1:0] == 1) && (|crc_count[2:0] == 1)) begin
crc_in <= byte_out[crc_count[2:0]];
crc_in_stb <= 1;
crc_count <= crc_count + 1;
end else begin
crc_in_stb <= 0;
end
end
S_DECODE_DATA: begin
pkt_begin <= 0;
legacy_sig_stb <= 0;
pkt_header_valid <= 0;
pkt_header_valid_strobe <= 0;
ofdm_reset <= 0;
ofdm_in_stb <= eq_out_stb_delayed;
ofdm_in_i <= eq_out_i_delayed;
ofdm_in_q <= eq_out_q_delayed;
if (byte_out_strobe) begin
`ifdef DEBUG_PRINT
$display("[BYTE] [%4d / %-4d] %02x", byte_count+1, pkt_len,
byte_out);
`endif
byte_count <= byte_count + 1;
byte_count_total <= byte_count_total + 1;
end
if (byte_count >= pkt_len) begin
fcs_out_strobe <= 1;
byte_count <= 0;
byte_count_total <= 0;
if (pkt_fcs == EXPECTED_FCS) begin
fcs_ok <= 1;
status_code <= E_OK;
end else begin
fcs_ok <= 0;
status_code <= E_WRONG_FCS;
end
if(|pkt_len_rem[15:2] == 1) begin
state <= S_MPDU_PAD;
end else begin
state <= S_DECODE_DONE;
end
end
end
S_MPDU_PAD: begin
fcs_out_strobe <= 0;
fcs_ok <= 0;
ofdm_in_stb <= eq_out_stb_delayed;
ofdm_in_i <= eq_out_i_delayed;
ofdm_in_q <= eq_out_q_delayed;
if (byte_out_strobe)
mpdu_pad <= mpdu_pad - 1;
if (mpdu_pad == 0) begin
crc_reset <= 1;
crc_count <= 0;
state <= S_MPDU_DELIM;
end
end
S_DECODE_DONE: begin
`ifdef DEBUG_PRINT
$display("===== PACKET DECODE DONE =====");
if (status_code == E_OK) begin
$display("FCS CORRECT");
end else begin
$display("FCS WRONG");
end
`endif
ht_aggr_last <= 0;
fcs_out_strobe <= 0;
fcs_ok <= 0;
state <= S_WAIT_POWER_TRIGGER;
end
default: begin
byte_count <= 0;
byte_count_total <= 0;
state <= S_WAIT_POWER_TRIGGER;
end
endcase
end
end
endmodule | module dot11 (
input clock,
input enable,
input reset,
input [10:0] power_thres,
input [31:0] min_plateau,
input [10:0] rssi_half_db,
input [31:0] sample_in,
input sample_in_strobe,
input soft_decoding,
input wire force_ht_smoothing,
input wire disable_all_smoothing,
output reg demod_is_ongoing,
output reg pkt_begin,
output reg pkt_ht,
output reg pkt_header_valid,
output reg pkt_header_valid_strobe,
output reg ht_unsupport,
output reg [7:0] pkt_rate,
output reg [15:0] pkt_len,
output reg [15:0] pkt_len_total,
output byte_out_strobe,
output [7:0] byte_out,
output reg [15:0] byte_count_total,
output reg [15:0] byte_count,
output reg fcs_out_strobe,
output reg fcs_ok,
output reg [4:0] state,
output reg [3:0] status_code,
output state_changed,
output reg [31:0] state_history,
output power_trigger,
output short_preamble_detected,
output [15:0] phase_offset,
output [31:0] sync_long_metric,
output sync_long_metric_stb,
output long_preamble_detected,
output [31:0] sync_long_out,
output sync_long_out_strobe,
output wire signed [31:0] phase_offset_taken,
output [2:0] sync_long_state,
output [31:0] equalizer_out,
output equalizer_out_strobe,
output [3:0] equalizer_state,
output wire ofdm_symbol_eq_out_pulse,
output reg legacy_sig_stb,
output [3:0] legacy_rate,
output legacy_sig_rsvd,
output [11:0] legacy_len,
output legacy_sig_parity,
output legacy_sig_parity_ok,
output [5:0] legacy_sig_tail,
output reg ht_sig_stb,
output [6:0] ht_mcs,
output ht_cbw,
output [15:0] ht_len,
output ht_smoothing,
output ht_not_sounding,
output ht_aggr,
output reg ht_aggr_last,
output [1:0] ht_stbc,
output ht_fec_coding,
output ht_sgi,
output [1:0] ht_num_ext,
output reg ht_sig_crc_ok,
output [5:0] demod_out,
output [5:0] demod_soft_bits,
output [3:0] demod_soft_bits_pos,
output demod_out_strobe,
output [7:0] deinterleave_erase_out,
output deinterleave_erase_out_strobe,
output conv_decoder_out,
output conv_decoder_out_stb,
output descramble_out,
output descramble_out_strobe,
output wire [31:0] csi,
output wire csi_valid
); |
`include "common_params.v"
reg [3:0] equalizer_state_reg;
assign ofdm_symbol_eq_out_pulse = (equalizer_state==4 && equalizer_state_reg==7);
always @(posedge clock) begin
if (reset==1) begin
state_history <= 0;
equalizer_state_reg <= 0;
end else begin
equalizer_state_reg <= equalizer_state;
if (state_changed) begin
state_history[3:0] <= state;
state_history[31:4] <= state_history[27:0];
end
end
end
wire [`ROTATE_LUT_LEN_SHIFT-1:0] sync_long_rot_addr;
wire [31:0] sync_long_rot_data;
wire [`ROTATE_LUT_LEN_SHIFT-1:0] eq_rot_addr;
wire [31:0] eq_rot_data;
rot_lut rot_lut_inst (
.clka(clock),
.addra(sync_long_rot_addr),
.douta(sync_long_rot_data),
.clkb(clock),
.addrb(eq_rot_addr),
.doutb(eq_rot_data)
);
wire [31:0] sync_short_phase_in_i;
wire [31:0] sync_short_phase_in_q;
wire sync_short_phase_in_stb;
wire [15:0] sync_short_phase_out;
wire sync_short_phase_out_stb;
wire [31:0] eq_phase_in_i;
wire [31:0] eq_phase_in_q;
wire eq_phase_in_stb;
wire [15:0] eq_phase_out;
wire eq_phase_out_stb;
wire[31:0] phase_in_i = state == S_SYNC_SHORT?
sync_short_phase_in_i: eq_phase_in_i;
wire[31:0] phase_in_q = state == S_SYNC_SHORT?
sync_short_phase_in_q: eq_phase_in_q;
wire phase_in_stb = state == S_SYNC_SHORT?
sync_short_phase_in_stb: eq_phase_in_stb;
wire [15:0] phase_out;
wire phase_out_stb;
assign sync_short_phase_out = phase_out;
assign sync_short_phase_out_stb = phase_out_stb;
assign eq_phase_out = phase_out;
assign eq_phase_out_stb = phase_out_stb;
phase phase_inst (
.clock(clock),
.reset(reset),
.enable(enable),
.in_i(phase_in_i),
.in_q(phase_in_q),
.input_strobe(phase_in_stb),
.phase(phase_out),
.output_strobe(phase_out_stb)
);
reg sync_short_reset;
reg sync_long_reset;
wire sync_short_enable = state == S_SYNC_SHORT;
reg sync_long_enable;
wire [15:0] num_ofdm_symbol;
reg equalizer_reset;
reg equalizer_enable;
reg ht_next;
wire eq_out_stb_delayed;
wire [15:0] eq_out_i = equalizer_out[31:16];
wire [15:0] eq_out_q = equalizer_out[15:0];
wire [15:0] eq_out_i_delayed;
wire [15:0] eq_out_q_delayed;
reg [15:0] abs_eq_i;
reg [15:0] abs_eq_q;
reg [3:0] rot_eq_count;
reg [3:0] normal_eq_count;
reg ofdm_reset;
reg ofdm_enable;
reg ofdm_in_stb;
reg [15:0] ofdm_in_i;
reg [15:0] ofdm_in_q;
reg do_descramble;
reg [31:0] num_bits_to_decode;
reg short_gi;
reg [4:0] old_state;
assign power_trigger = (rssi_half_db>=power_thres? 1: 0);
assign state_changed = state != old_state;
reg [23:0] signal_bits;
assign legacy_rate = signal_bits[3:0];
assign legacy_sig_rsvd = signal_bits[4];
assign legacy_len = signal_bits[16:5];
assign legacy_sig_parity = signal_bits[17];
assign legacy_sig_tail = signal_bits[23:18];
assign legacy_sig_parity_ok = ~^signal_bits[17:0];
reg [23:0] ht_sig1;
reg [23:0] ht_sig2;
assign ht_mcs = ht_sig1[6:0];
assign ht_cbw = ht_sig1[7];
assign ht_len = ht_sig1[23:8];
assign ht_smoothing = ht_sig2[0];
assign ht_not_sounding = ht_sig2[1];
assign ht_aggr = ht_sig2[3];
assign ht_stbc = ht_sig2[5:4];
assign ht_fec_coding = ht_sig2[6];
assign ht_sgi = ht_sig2[7];
assign ht_num_ext = ht_sig2[9:8];
wire ht_rsvd = ht_sig2[2];
wire [7:0] crc = ht_sig2[17:10];
wire [5:0] ht_sig_tail = ht_sig2[23:18];
reg [15:0] pkt_len_rem;
reg [7:0] mpdu_del_crc;
reg [1:0] mpdu_pad;
reg crc_in_stb;
reg crc_in;
reg [7:0] crc_count;
reg crc_reset;
wire [7:0] crc_out;
reg [31:0] sample_count;
wire fcs_enable = state == S_DECODE_DATA && byte_out_strobe;
wire fcs_reset = state_changed && state == S_DECODE_DATA;
wire [7:0] byte_reversed;
wire [31:0] pkt_fcs;
assign byte_reversed[0] = byte_out[7];
assign byte_reversed[1] = byte_out[6];
assign byte_reversed[2] = byte_out[5];
assign byte_reversed[3] = byte_out[4];
assign byte_reversed[4] = byte_out[3];
assign byte_reversed[5] = byte_out[2];
assign byte_reversed[6] = byte_out[1];
assign byte_reversed[7] = byte_out[0];
reg [15:0] sync_long_out_count;
sync_short sync_short_inst (
.clock(clock),
.reset(reset | sync_short_reset),
.enable(enable & sync_short_enable),
.min_plateau(min_plateau),
.sample_in(sample_in),
.sample_in_strobe(sample_in_strobe),
.phase_in_i(sync_short_phase_in_i),
.phase_in_q(sync_short_phase_in_q),
.phase_in_stb(sync_short_phase_in_stb),
.phase_out(sync_short_phase_out),
.phase_out_stb(sync_short_phase_out_stb),
.short_preamble_detected(short_preamble_detected),
.phase_offset(phase_offset)
);
sync_long sync_long_inst (
.clock(clock),
.reset(reset | sync_long_reset),
.enable(enable & sync_long_enable),
.sample_in(sample_in),
.sample_in_strobe(sample_in_strobe),
.phase_offset(phase_offset),
.short_gi(short_gi),
.rot_addr(sync_long_rot_addr),
.rot_data(sync_long_rot_data),
.metric(sync_long_metric),
.metric_stb(sync_long_metric_stb),
.long_preamble_detected(long_preamble_detected),
.phase_offset_taken(phase_offset_taken),
.state(sync_long_state),
.sample_out(sync_long_out),
.sample_out_strobe(sync_long_out_strobe),
.num_ofdm_symbol(num_ofdm_symbol)
);
equalizer equalizer_inst (
.clock(clock),
.reset(reset | equalizer_reset),
.enable(enable & equalizer_enable),
.sample_in(sync_long_out),
.sample_in_strobe(sync_long_out_strobe && !(state==S_HT_SIGNAL && num_ofdm_symbol==6)),
.ht_next(ht_next),
.pkt_ht(pkt_ht),
.ht_smoothing(ht_smoothing|force_ht_smoothing),
.disable_all_smoothing(disable_all_smoothing),
.phase_in_i(eq_phase_in_i),
.phase_in_q(eq_phase_in_q),
.phase_in_stb(eq_phase_in_stb),
.phase_out(eq_phase_out),
.phase_out_stb(eq_phase_out_stb),
.rot_addr(eq_rot_addr),
.rot_data(eq_rot_data),
.sample_out(equalizer_out),
.sample_out_strobe(equalizer_out_strobe),
.state(equalizer_state),
.csi(csi),
.csi_valid(csi_valid)
);
delayT #(.DATA_WIDTH(33), .DELAY(9)) eq_delay_inst (
.clock(clock),
.reset(reset),
.data_in({equalizer_out_strobe, equalizer_out}),
.data_out({eq_out_stb_delayed, eq_out_i_delayed, eq_out_q_delayed})
);
ofdm_decoder ofdm_decoder_inst (
.clock(clock),
.reset(reset|ofdm_reset),
.enable(enable & ofdm_enable),
.sample_in({ofdm_in_i, ofdm_in_q}),
.sample_in_strobe(ofdm_in_stb),
.soft_decoding(soft_decoding),
.do_descramble(do_descramble),
.num_bits_to_decode(num_bits_to_decode),
.rate(pkt_rate),
.byte_out(byte_out),
.byte_out_strobe(byte_out_strobe),
.demod_out(demod_out),
.demod_soft_bits(demod_soft_bits),
.demod_soft_bits_pos(demod_soft_bits_pos),
.demod_out_strobe(demod_out_strobe),
.deinterleave_erase_out(deinterleave_erase_out),
.deinterleave_erase_out_strobe(deinterleave_erase_out_strobe),
.conv_decoder_out(conv_decoder_out),
.conv_decoder_out_stb(conv_decoder_out_stb),
.descramble_out(descramble_out),
.descramble_out_strobe(descramble_out_strobe)
);
ht_sig_crc crc_inst (
.clock(clock),
.enable(enable),
.reset(reset | crc_reset),
.bit(crc_in),
.input_strobe(crc_in_stb),
.crc(crc_out)
);
crc32 fcs_inst (
.clk(clock),
.crc_en(enable & fcs_enable),
.rst(reset | fcs_reset),
.data_in(byte_reversed),
.crc_out(pkt_fcs)
);
always @(posedge clock) begin
if (reset) begin
status_code <= E_OK;
state <= S_WAIT_POWER_TRIGGER;
old_state <= 0;
sync_short_reset <= 0;
sync_long_reset <= 0;
sync_long_enable <= 0;
byte_count <= 0;
byte_count_total <= 0;
demod_is_ongoing <= 0;
pkt_begin <= 0;
pkt_ht <= 0;
pkt_header_valid <= 0;
pkt_header_valid_strobe <= 0;
ht_unsupport <= 0;
rot_eq_count <= 0;
normal_eq_count <= 0;
abs_eq_i <= 0;
abs_eq_q <= 0;
do_descramble <= 0;
num_bits_to_decode <= 0;
short_gi <= 0;
pkt_rate <= 0;
equalizer_reset <= 0;
equalizer_enable <= 0;
ht_next <= 0;
pkt_len_rem <= 0;
mpdu_del_crc <= 0;
mpdu_pad <= 0;
pkt_len <= 0;
pkt_len_total <= 0;
ofdm_reset <= 0;
ofdm_enable <= 0;
ofdm_in_stb <= 0;
ofdm_in_i <= 0;
ofdm_in_q <= 0;
sample_count <= 0;
sync_long_out_count <= 0;
signal_bits <= 0;
legacy_sig_stb <= 0;
ht_sig1 <= 0;
ht_sig2 <= 0;
crc_in_stb <= 0;
crc_in <= 0;
crc_count <= 0;
crc_reset <= 0;
ht_sig_crc_ok <= 0;
ht_sig_stb <= 0;
ht_aggr_last <= 0;
fcs_out_strobe <= 0;
fcs_ok <= 0;
end else if (enable) begin
old_state <= state;
case(state)
S_WAIT_POWER_TRIGGER: begin
pkt_begin <= 0;
pkt_ht <= 0;
crc_reset <= 0;
short_gi <= 0;
demod_is_ongoing <= 0;
sync_long_enable <= 0;
equalizer_enable <= 0;
ofdm_enable <= 0;
ofdm_reset <= 0;
pkt_len_total <= 16'hffff;
ht_sig1 <= 0;
ht_sig2 <= 0;
pkt_len_rem <= 0;
if (power_trigger) begin
`ifdef DEBUG_PRINT
$display("Power triggered.");
`endif
sync_short_reset <= 1;
state <= S_SYNC_SHORT;
end
end
S_SYNC_SHORT: begin
if (sync_short_reset) begin
sync_short_reset <= 0;
end
if (~power_trigger) begin
state <= S_WAIT_POWER_TRIGGER;
end
if (short_preamble_detected) begin
`ifdef DEBUG_PRINT
$display("Short preamble detected");
`endif
sync_long_reset <= 1;
sync_long_enable <= 1;
sample_count <= 0;
state <= S_SYNC_LONG;
end
end
S_SYNC_LONG: begin
if (sync_long_reset) begin
sync_long_reset <= 0;
end
if (sample_in_strobe) begin
sample_count <= sample_count + 1;
end
if (sample_count > 320) begin
state <= S_WAIT_POWER_TRIGGER;
end
if (~power_trigger) begin
state <= S_WAIT_POWER_TRIGGER;
end
if (long_preamble_detected) begin
demod_is_ongoing <= 1;
pkt_rate <= {1'b0, 3'b0, 4'b1011};
do_descramble <= 0;
num_bits_to_decode <= 48;
ofdm_reset <= 1;
ofdm_enable <= 1;
equalizer_enable <= 1;
equalizer_reset <= 1;
byte_count <= 0;
byte_count_total <= 0;
state <= S_DECODE_SIGNAL;
end
end
S_DECODE_SIGNAL: begin
ofdm_reset <= 0;
if (equalizer_reset) begin
equalizer_reset <= 0;
end
ofdm_in_stb <= equalizer_out_strobe;
ofdm_in_i <= eq_out_i;
ofdm_in_q <= eq_out_q;
if (byte_out_strobe) begin
signal_bits <= {byte_out, signal_bits[23:8]};
byte_count <= byte_count + 1;
byte_count_total <= byte_count_total + 1;
end
if (byte_count == 3) begin
byte_count <= 0;
`ifdef DEBUG_PRINT
$display("[SIGNAL] rate = %04b, ", legacy_rate,
"length = %012b (%d), ", legacy_len, legacy_len,
"parity = %b, ", legacy_sig_parity,
"tail = %6b", legacy_sig_tail);
`endif
num_bits_to_decode <= (22+(legacy_len<<3))<<1;
pkt_rate <= {1'b0, 3'b0, legacy_rate};
pkt_len <= legacy_len;
pkt_len_total <= legacy_len+3;
ofdm_reset <= 1;
state <= S_CHECK_SIGNAL;
end
end
S_CHECK_SIGNAL: begin
if (~legacy_sig_parity_ok) begin
pkt_header_valid_strobe <= 1;
status_code <= E_PARITY_FAIL;
state <= S_SIGNAL_ERROR;
end else if (legacy_sig_rsvd) begin
pkt_header_valid_strobe <= 1;
status_code <= E_WRONG_RSVD;
state <= S_SIGNAL_ERROR;
end else if (|legacy_sig_tail) begin
pkt_header_valid_strobe <= 1;
status_code <= E_WRONG_TAIL;
state <= S_SIGNAL_ERROR;
end else if (legacy_rate[3]==0) begin
pkt_header_valid_strobe <= 1;
status_code <= E_UNSUPPORTED_RATE;
state <= S_SIGNAL_ERROR;
end else begin
legacy_sig_stb <= 1;
status_code <= E_OK;
if (legacy_rate == 4'b1011) begin
abs_eq_i <= 0;
abs_eq_q <= 0;
rot_eq_count <= 0;
normal_eq_count <= 0;
state <= S_DETECT_HT;
end else begin
do_descramble <= 1;
ofdm_reset <= 1;
pkt_header_valid <= 1;
pkt_header_valid_strobe <= 1;
pkt_begin <= 1;
state <= S_DECODE_DATA;
end
end
end
S_SIGNAL_ERROR: begin
pkt_header_valid_strobe <= 0;
byte_count <= 0;
byte_count_total <= 0;
state <= S_WAIT_POWER_TRIGGER;
end
S_DETECT_HT: begin
legacy_sig_stb <= 0;
ofdm_reset <= 1;
if (equalizer_out_strobe) begin
abs_eq_i <= eq_out_i[15]? ~eq_out_i+1: eq_out_i;
abs_eq_q <= eq_out_q[15]? ~eq_out_q+1: eq_out_q;
if (abs_eq_q > abs_eq_i) begin
rot_eq_count <= rot_eq_count + 1;
end else if (abs_eq_q < abs_eq_i) begin
normal_eq_count <= normal_eq_count + 1;
end
end
if (rot_eq_count >= 4) begin
num_bits_to_decode <= 96;
do_descramble <= 0;
state <= S_HT_SIGNAL;
end else if (normal_eq_count > 4) begin
do_descramble <= 1;
pkt_header_valid <= 1;
pkt_header_valid_strobe <= 1;
pkt_begin <= 1;
state <= S_DECODE_DATA;
end
end
S_HT_SIGNAL: begin
ofdm_reset <= 0;
ofdm_in_stb <= eq_out_stb_delayed;
ofdm_in_i <= eq_out_q_delayed;
ofdm_in_q <= ~eq_out_i_delayed+1;
if (byte_out_strobe) begin
if (byte_count < 3) begin
ht_sig1 <= {byte_out, ht_sig1[23:8]};
end else begin
ht_sig2 <= {byte_out, ht_sig2[23:8]};
end
byte_count <= byte_count + 1;
byte_count_total <= byte_count_total + 1;
end
if (byte_count == 6) begin
byte_count <= 0;
`ifdef DEBUG_PRINT
$display("[HT SIGNAL] mcs = %07b (%d), ", ht_mcs, ht_mcs,
"CBW: %d, ", ht_cbw? 40: 20,
"length = %012b (%d), ", ht_len, ht_len,
"rsvd = %d, ", ht_rsvd,
"aggr = %d, ", ht_aggr,
"aggr_last = %d, ", ht_aggr_last,
"stbd = %02b, ", ht_stbc,
"fec = %d, ", ht_fec_coding,
"sgi = %d, ", ht_sgi,
"num_ext = %d, ", ht_num_ext,
"crc = %08b, ", crc,
"tail = %06b", ht_sig_tail);
`endif
num_bits_to_decode <= (22+(ht_len<<3))<<1;
pkt_rate <= {1'b1, ht_mcs};
pkt_len_rem <= ht_len;
pkt_len <= ht_len;
pkt_len_total <= ht_len+3+6;
crc_count <= 0;
crc_reset <= 1;
crc_in_stb <= 0;
ht_sig_crc_ok <= 0;
state <= S_CHECK_HT_SIG_CRC;
end
end
S_CHECK_HT_SIG_CRC: begin
ofdm_reset <= 1;
crc_reset <= 0;
crc_count <= crc_count + 1;
if (crc_count < 24) begin
crc_in_stb <= 1;
crc_in <= ht_sig1[crc_count];
end else if (crc_count < 34) begin
crc_in_stb <= 1;
crc_in <= ht_sig2[crc_count-24];
end else if (crc_count == 34) begin
crc_in_stb <= 0;
end else if (crc_count == 35) begin
ht_sig_stb <= 1;
pkt_ht <= 1;
if (crc_out ^ crc) begin
pkt_header_valid_strobe <= 1;
status_code <= E_WRONG_CRC;
state <= S_HT_SIG_ERROR;
end else begin
`ifdef DEBUG_PRINT
$display("[HT SIGNAL] CRC OK");
`endif
ht_sig_crc_ok <= 1;
state <= S_CHECK_HT_SIG;
end
end
end
S_CHECK_HT_SIG: begin
ofdm_reset <= 1;
ht_sig_stb <= 0;
ht_aggr_last <= 0;
if (ht_mcs > 7) begin
ht_unsupport <= 1;
status_code <= E_UNSUPPORTED_MCS;
state <= S_HT_SIG_ERROR;
end else if (ht_cbw) begin
ht_unsupport <= 1;
status_code <= E_UNSUPPORTED_CBW;
state <= S_HT_SIG_ERROR;
end else if (ht_rsvd == 0) begin
ht_unsupport <= 1;
status_code <= E_HT_WRONG_RSVD;
state <= S_HT_SIG_ERROR;
end else if (ht_stbc != 0) begin
ht_unsupport <= 1;
status_code <= E_UNSUPPORTED_STBC;
state <= S_HT_SIG_ERROR;
end else if (ht_fec_coding) begin
ht_unsupport <= 1;
status_code <= E_UNSUPPORTED_FEC;
state <= S_HT_SIG_ERROR;
end else if (ht_num_ext != 0) begin
ht_unsupport <= 1;
status_code <= E_UNSUPPORTED_SPATIAL;
state <= S_HT_SIG_ERROR;
end else if (ht_sig_tail != 0) begin
ht_unsupport <= 1;
status_code <= E_HT_WRONG_TAIL;
state <= S_HT_SIG_ERROR;
end else begin
sync_long_out_count <= 0;
if (num_ofdm_symbol == 5) begin
state <= S_HT_STS;
end else begin
ht_next <= 1;
state <= S_HT_LTS;
end
end
end
S_HT_SIG_ERROR: begin
ht_unsupport <= 0;
pkt_header_valid <= 0;
pkt_header_valid_strobe <= 0;
byte_count <= 0;
byte_count_total <= 0;
ht_sig_stb <= 0;
state <= S_WAIT_POWER_TRIGGER;
end
S_HT_STS: begin
if (sync_long_out_strobe) begin
sync_long_out_count <= sync_long_out_count + 1;
end
if (sync_long_out_count == 64) begin
sync_long_out_count <= 0;
ht_next <= 1;
state <= S_HT_LTS;
end
end
S_HT_LTS: begin
short_gi <= ht_sgi;
if (sync_long_out_strobe) begin
sync_long_out_count <= sync_long_out_count + 1;
end
if (sync_long_out_count == 64) begin
ht_next <= 0;
do_descramble <= 1;
ofdm_reset <= 1;
if(ht_aggr) begin
crc_reset <= 1;
crc_count <= 0;
state <= S_MPDU_DELIM;
end else begin
pkt_header_valid <= 1;
pkt_header_valid_strobe <= 1;
pkt_begin <= 1;
pkt_len_rem <= 0;
state <= S_DECODE_DATA;
end
end
end
S_MPDU_DELIM: begin
crc_reset <= 0;
ofdm_reset <= 0;
ofdm_in_stb <= eq_out_stb_delayed;
ofdm_in_i <= eq_out_i_delayed;
ofdm_in_q <= eq_out_q_delayed;
if(byte_out_strobe) begin
if(byte_count == 3) begin
byte_count <= 0;
byte_count_total <= 3+6;
if(crc_out == mpdu_del_crc && byte_out == 8'h4e) begin
if(pkt_len == 0) begin
pkt_len_rem <= pkt_len_rem - 4;
crc_reset <= 1;
crc_count <= 0;
state <= S_MPDU_DELIM;
end else begin
pkt_header_valid <= 1;
pkt_header_valid_strobe <= 1;
pkt_len_total <= pkt_len+3+6;
pkt_begin <= 1;
state <= S_DECODE_DATA;
if((pkt_len_rem-pkt_len-mpdu_pad) > 4) begin
ht_aggr_last <= 0;
pkt_len_rem <= pkt_len_rem - (4 + pkt_len + mpdu_pad);
end else begin
ht_aggr_last <= 1;
pkt_len_rem <= 0;
end
end
end else if(|pkt_len_rem[15:3] == 0) begin
ht_aggr_last <= 1;
fcs_out_strobe <= 1;
fcs_ok <= 0;
status_code <= E_HT_AMPDU_ERROR;
state <= S_DECODE_DONE;
end else begin
pkt_len_rem <= pkt_len_rem - 4;
crc_reset <= 1;
crc_count <= 0;
status_code <= E_HT_AMPDU_WARN;
state <= S_MPDU_DELIM;
end
end else begin
byte_count <= byte_count + 1;
byte_count_total <= byte_count_total + 1;
if(byte_count == 0) begin
pkt_len[3:0] <= byte_out[7:4];
end else if(byte_count == 1) begin
pkt_len[11:4] <= byte_out;
end else if(byte_count == 2) begin
pkt_len[15:12] <= 0;
mpdu_del_crc <= byte_out;
if(pkt_len[1:0] == 0)
mpdu_pad <= 0;
else if(pkt_len[1:0] == 1)
mpdu_pad <= 3;
else if(pkt_len[1:0] == 2)
mpdu_pad <= 2;
else
mpdu_pad <= 1;
end
if(crc_count[4] == 0) begin
crc_in <= byte_out[crc_count[2:0]];
crc_in_stb <= 1;
crc_count <= crc_count + 1;
end else begin
crc_in_stb <= 0;
end
end
end else if((^byte_count[1:0] == 1) && (|crc_count[2:0] == 1)) begin
crc_in <= byte_out[crc_count[2:0]];
crc_in_stb <= 1;
crc_count <= crc_count + 1;
end else begin
crc_in_stb <= 0;
end
end
S_DECODE_DATA: begin
pkt_begin <= 0;
legacy_sig_stb <= 0;
pkt_header_valid <= 0;
pkt_header_valid_strobe <= 0;
ofdm_reset <= 0;
ofdm_in_stb <= eq_out_stb_delayed;
ofdm_in_i <= eq_out_i_delayed;
ofdm_in_q <= eq_out_q_delayed;
if (byte_out_strobe) begin
`ifdef DEBUG_PRINT
$display("[BYTE] [%4d / %-4d] %02x", byte_count+1, pkt_len,
byte_out);
`endif
byte_count <= byte_count + 1;
byte_count_total <= byte_count_total + 1;
end
if (byte_count >= pkt_len) begin
fcs_out_strobe <= 1;
byte_count <= 0;
byte_count_total <= 0;
if (pkt_fcs == EXPECTED_FCS) begin
fcs_ok <= 1;
status_code <= E_OK;
end else begin
fcs_ok <= 0;
status_code <= E_WRONG_FCS;
end
if(|pkt_len_rem[15:2] == 1) begin
state <= S_MPDU_PAD;
end else begin
state <= S_DECODE_DONE;
end
end
end
S_MPDU_PAD: begin
fcs_out_strobe <= 0;
fcs_ok <= 0;
ofdm_in_stb <= eq_out_stb_delayed;
ofdm_in_i <= eq_out_i_delayed;
ofdm_in_q <= eq_out_q_delayed;
if (byte_out_strobe)
mpdu_pad <= mpdu_pad - 1;
if (mpdu_pad == 0) begin
crc_reset <= 1;
crc_count <= 0;
state <= S_MPDU_DELIM;
end
end
S_DECODE_DONE: begin
`ifdef DEBUG_PRINT
$display("===== PACKET DECODE DONE =====");
if (status_code == E_OK) begin
$display("FCS CORRECT");
end else begin
$display("FCS WRONG");
end
`endif
ht_aggr_last <= 0;
fcs_out_strobe <= 0;
fcs_ok <= 0;
state <= S_WAIT_POWER_TRIGGER;
end
default: begin
byte_count <= 0;
byte_count_total <= 0;
state <= S_WAIT_POWER_TRIGGER;
end
endcase
end
end
endmodule | 230 |
139,728 | data/full_repos/permissive/89514111/verilog/dot11_tb.v | 89,514,111 | dot11_tb.v | v | 440 | 295 | [] | [] | [] | [(3, 513)] | null | null | 1: b'%Error: data/full_repos/permissive/89514111/verilog/dot11_tb.v:4: Cannot find include file: common_params.v\n`include "common_params.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89514111/verilog,data/full_repos/permissive/89514111/common_params.v\n data/full_repos/permissive/89514111/verilog,data/full_repos/permissive/89514111/common_params.v.v\n data/full_repos/permissive/89514111/verilog,data/full_repos/permissive/89514111/common_params.v.sv\n common_params.v\n common_params.v.v\n common_params.v.sv\n obj_dir/common_params.v\n obj_dir/common_params.v.v\n obj_dir/common_params.v.sv\n%Error: data/full_repos/permissive/89514111/verilog/dot11_tb.v:144: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("dot11.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/89514111/verilog/dot11_tb.v:145: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/89514111/verilog/dot11_tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n # 20 reset = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/89514111/verilog/dot11_tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n # 20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/89514111/verilog/dot11_tb.v:162: Unsupported: Ignoring delay on this delayed statement.\n # 20 set_stb = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/89514111/verilog/dot11_tb.v:196: Unsupported: Ignoring delay on this delayed statement.\n #5 clock = !clock;\n ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n' | 306,540 | module | module dot11_tb;
`include "common_params.v"
reg clock;
reg reset;
reg enable;
reg [10:0] rssi_half_db;
reg[31:0] sample_in;
reg sample_in_strobe;
reg [15:0] clk_count;
wire [31:0] sync_short_metric;
wire short_preamble_detected;
wire power_trigger;
wire [31:0] sync_long_out;
wire sync_long_out_strobe;
wire [31:0] sync_long_metric;
wire sync_long_metric_stb;
wire long_preamble_detected;
wire [31:0] equalizer_out;
wire equalizer_out_strobe;
wire [5:0] demod_out;
wire [5:0] demod_soft_bits;
wire [3:0] demod_soft_bits_pos;
wire demod_out_strobe;
wire [7:0] deinterleave_erase_out;
wire deinterleave_erase_out_strobe;
wire conv_decoder_out;
wire conv_decoder_out_stb;
wire descramble_out;
wire descramble_out_strobe;
wire [3:0] legacy_rate;
wire legacy_sig_rsvd;
wire [11:0] legacy_len;
wire legacy_sig_parity;
wire [5:0] legacy_sig_tail;
wire legacy_sig_stb;
reg signal_done;
wire [3:0] dot11_state;
wire pkt_header_valid;
wire pkt_header_valid_strobe;
wire [7:0] byte_out;
wire byte_out_strobe;
wire [15:0] byte_count_total;
wire [15:0] byte_count;
wire [15:0] pkt_len_total;
wire [15:0] pkt_len;
reg set_stb;
reg [7:0] set_addr;
reg [31:0] set_data;
wire fcs_out_strobe, fcs_ok;
wire demod_is_ongoing;
wire receiver_rst;
wire sig_valid = (pkt_header_valid_strobe&pkt_header_valid);
integer addr;
integer bb_sample_fd;
integer power_trigger_fd;
integer short_preamble_detected_fd;
integer long_preamble_detected_fd;
integer sync_long_metric_fd;
integer sync_long_out_fd;
integer equalizer_out_fd;
integer demod_out_fd;
integer demod_soft_bits_fd;
integer demod_soft_bits_pos_fd;
integer deinterleave_erase_out_fd;
integer conv_out_fd;
integer descramble_out_fd;
integer signal_fd;
integer byte_out_fd;
integer file_i, file_q, file_rssi_half_db, iq_sample_file;
`define CLK_SPEED_100M
`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs7_gi1_aggr0_len1537_pre100_post200_openwifi.txt"
`define NUM_SAMPLE 118560
initial begin
$dumpfile("dot11.vcd");
$dumpvars;
clock = 0;
reset = 1;
enable = 0;
signal_done <= 0;
# 20 reset = 0;
enable = 1;
set_stb = 1;
# 20
set_addr = SR_SKIP_SAMPLE;
set_data = 0;
# 20 set_stb = 0;
end
integer file_open_trigger = 0;
always @(posedge clock) begin
file_open_trigger = file_open_trigger + 1;
if (file_open_trigger==1) begin
iq_sample_file = $fopen(`SAMPLE_FILE, "r");
bb_sample_fd = $fopen("./sample_in.txt", "w");
power_trigger_fd = $fopen("./power_trigger.txt", "w");
short_preamble_detected_fd = $fopen("./short_preamble_detected.txt", "w");
sync_long_metric_fd = $fopen("./sync_long_metric.txt", "w");
long_preamble_detected_fd = $fopen("./sync_long_frame_detected.txt", "w");
sync_long_out_fd = $fopen("./sync_long_out.txt", "w");
equalizer_out_fd = $fopen("./equalizer_out.txt", "w");
demod_out_fd = $fopen("./demod_out.txt", "w");
demod_soft_bits_fd = $fopen("./demod_soft_bits.txt", "w");
demod_soft_bits_pos_fd = $fopen("./demod_soft_bits_pos.txt", "w");
deinterleave_erase_out_fd = $fopen("./deinterleave_erase_out.txt", "w");
conv_out_fd = $fopen("./conv_out.txt", "w");
descramble_out_fd = $fopen("./descramble_out.txt", "w");
signal_fd = $fopen("./signal_out.txt", "w");
byte_out_fd = $fopen("./byte_out.txt", "w");
end
end
always begin
`ifdef CLK_SPEED_100M
#5 clock = !clock;
`elsif CLK_SPEED_200M
#2.5 clock = !clock;
`elsif CLK_SPEED_240M
#2.0833333333 clock = !clock;
`elsif CLK_SPEED_400M
#1.25 clock = !clock;
`endif
end
always @(posedge clock) begin
if (reset) begin
sample_in <= 0;
clk_count <= 0;
sample_in_strobe <= 0;
addr <= 0;
end else if (enable) begin
`ifdef CLK_SPEED_100M
if (clk_count == 4) begin
`elsif CLK_SPEED_200M
if (clk_count == 9) begin
`elsif CLK_SPEED_240M
if (clk_count == 11) begin
`elsif CLK_SPEED_400M
if (clk_count == 19) begin
`endif
sample_in_strobe <= 1;
$fscanf(iq_sample_file, "%d %d", file_i, file_q);
sample_in[15:0] <= file_q;
sample_in[31:16]<= file_i;
rssi_half_db <= 0;
addr <= addr + 1;
clk_count <= 0;
end else begin
sample_in_strobe <= 0;
clk_count <= clk_count + 1;
end
if (legacy_sig_stb) begin
end
if (sample_in_strobe) begin
$fwrite(bb_sample_fd, "%d %d %d\n", $time/2, $signed(sample_in[31:16]), $signed(sample_in[15:0]));
$fwrite(power_trigger_fd, "%d %d\n", $time/2, power_trigger);
$fwrite(short_preamble_detected_fd, "%d %d\n", $time/2, short_preamble_detected);
$fwrite(long_preamble_detected_fd, "%d %d\n", $time/2, long_preamble_detected);
$fflush(bb_sample_fd);
$fflush(power_trigger_fd);
$fflush(short_preamble_detected_fd);
$fflush(long_preamble_detected_fd);
if ((addr % 100) == 0) begin
$display("%d", addr);
end
if (addr == `NUM_SAMPLE) begin
$fclose(iq_sample_file);
$fclose(bb_sample_fd);
$fclose(power_trigger_fd);
$fclose(short_preamble_detected_fd);
$fclose(sync_long_metric_fd);
$fclose(long_preamble_detected_fd);
$fclose(sync_long_out_fd);
$fclose(equalizer_out_fd);
$fclose(demod_out_fd);
$fclose(demod_soft_bits_fd);
$fclose(demod_soft_bits_pos_fd);
$fclose(deinterleave_erase_out_fd);
$fclose(conv_out_fd);
$fclose(descramble_out_fd);
$fclose(signal_fd);
$fclose(byte_out_fd);
$finish;
end
end
if (sync_long_metric_stb) begin
$fwrite(sync_long_metric_fd, "%d %d\n", $time/2, sync_long_metric);
$fflush(sync_long_metric_fd);
end
if (sync_long_out_strobe) begin
$fwrite(sync_long_out_fd, "%d %d\n", $signed(sync_long_out[31:16]), $signed(sync_long_out[15:0]));
$fflush(sync_long_out_fd);
end
if (equalizer_out_strobe) begin
$fwrite(equalizer_out_fd, "%d %d\n", $signed(equalizer_out[31:16]), $signed(equalizer_out[15:0]));
$fflush(equalizer_out_fd);
end
if (legacy_sig_stb) begin
signal_done <= 1;
$fwrite(signal_fd, "%04b %b %012b %b %06b", legacy_rate, legacy_sig_rsvd, legacy_len, legacy_sig_parity, legacy_sig_tail);
$fflush(signal_fd);
end
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && demod_out_strobe) begin
$fwrite(demod_out_fd, "%b %b %b %b %b %b\n",demod_out[0],demod_out[1],demod_out[2],demod_out[3],demod_out[4],demod_out[5]);
$fwrite(demod_soft_bits_fd, "%b %b %b %b %b %b\n",demod_soft_bits[0],demod_soft_bits[1],demod_soft_bits[2],demod_soft_bits[3],demod_soft_bits[4],demod_soft_bits[5]);
$fwrite(demod_soft_bits_pos_fd, "%b %b %b %b\n",demod_soft_bits_pos[0],demod_soft_bits_pos[1],demod_soft_bits_pos[2],demod_soft_bits_pos[3]);
$fflush(demod_out_fd);
$fflush(demod_soft_bits_fd);
$fflush(demod_soft_bits_pos_fd);
end
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && deinterleave_erase_out_strobe) begin
$fwrite(deinterleave_erase_out_fd, "%b %b %b %b %b %b %b %b\n", deinterleave_erase_out[0], deinterleave_erase_out[1], deinterleave_erase_out[2], deinterleave_erase_out[3], deinterleave_erase_out[4], deinterleave_erase_out[5], deinterleave_erase_out[6], deinterleave_erase_out[7]);
$fflush(deinterleave_erase_out_fd);
end
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && conv_decoder_out_stb) begin
$fwrite(conv_out_fd, "%b\n", conv_decoder_out);
$fflush(conv_out_fd);
end
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && descramble_out_strobe) begin
$fwrite(descramble_out_fd, "%b\n", descramble_out);
$fflush(descramble_out_fd);
end
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && byte_out_strobe) begin
$fwrite(byte_out_fd, "%02x\n", byte_out);
$fflush(byte_out_fd);
end
end
end
signal_watchdog signal_watchdog_inst (
.clk(clock),
.rstn(~reset),
.enable(~demod_is_ongoing),
.i_data(sample_in[31:16]),
.q_data(sample_in[15:0]),
.iq_valid(sample_in_strobe),
.signal_len(pkt_len),
.sig_valid(sig_valid),
.max_signal_len_th(4095),
.dc_running_sum_th(64),
.receiver_rst(receiver_rst)
);
dot11 dot11_inst (
.clock(clock),
.enable(enable),
.reset(reset|receiver_rst),
.power_thres(11'd0),
.min_plateau(32'd100),
.rssi_half_db(rssi_half_db),
.sample_in(sample_in),
.sample_in_strobe(sample_in_strobe),
.soft_decoding(1'b1),
.demod_is_ongoing(demod_is_ongoing),
.pkt_header_valid(pkt_header_valid),
.pkt_header_valid_strobe(pkt_header_valid_strobe),
.pkt_len(pkt_len),
.pkt_len_total(pkt_len_total),
.byte_out_strobe(byte_out_strobe),
.byte_out(byte_out),
.byte_count_total(byte_count_total),
.byte_count(byte_count),
.fcs_out_strobe(fcs_out_strobe),
.fcs_ok(fcs_ok),
.state(dot11_state),
.power_trigger(power_trigger),
.short_preamble_detected(short_preamble_detected),
.sync_long_metric(sync_long_metric),
.sync_long_metric_stb(sync_long_metric_stb),
.long_preamble_detected(long_preamble_detected),
.sync_long_out(sync_long_out),
.sync_long_out_strobe(sync_long_out_strobe),
.equalizer_out(equalizer_out),
.equalizer_out_strobe(equalizer_out_strobe),
.legacy_sig_stb(legacy_sig_stb),
.legacy_rate(legacy_rate),
.legacy_sig_rsvd(legacy_sig_rsvd),
.legacy_len(legacy_len),
.legacy_sig_parity(legacy_sig_parity),
.legacy_sig_tail(legacy_sig_tail),
.demod_out(demod_out),
.demod_soft_bits(demod_soft_bits),
.demod_soft_bits_pos(demod_soft_bits_pos),
.demod_out_strobe(demod_out_strobe),
.deinterleave_erase_out(deinterleave_erase_out),
.deinterleave_erase_out_strobe(deinterleave_erase_out_strobe),
.conv_decoder_out(conv_decoder_out),
.conv_decoder_out_stb(conv_decoder_out_stb),
.descramble_out(descramble_out),
.descramble_out_strobe(descramble_out_strobe)
);
endmodule | module dot11_tb; |
`include "common_params.v"
reg clock;
reg reset;
reg enable;
reg [10:0] rssi_half_db;
reg[31:0] sample_in;
reg sample_in_strobe;
reg [15:0] clk_count;
wire [31:0] sync_short_metric;
wire short_preamble_detected;
wire power_trigger;
wire [31:0] sync_long_out;
wire sync_long_out_strobe;
wire [31:0] sync_long_metric;
wire sync_long_metric_stb;
wire long_preamble_detected;
wire [31:0] equalizer_out;
wire equalizer_out_strobe;
wire [5:0] demod_out;
wire [5:0] demod_soft_bits;
wire [3:0] demod_soft_bits_pos;
wire demod_out_strobe;
wire [7:0] deinterleave_erase_out;
wire deinterleave_erase_out_strobe;
wire conv_decoder_out;
wire conv_decoder_out_stb;
wire descramble_out;
wire descramble_out_strobe;
wire [3:0] legacy_rate;
wire legacy_sig_rsvd;
wire [11:0] legacy_len;
wire legacy_sig_parity;
wire [5:0] legacy_sig_tail;
wire legacy_sig_stb;
reg signal_done;
wire [3:0] dot11_state;
wire pkt_header_valid;
wire pkt_header_valid_strobe;
wire [7:0] byte_out;
wire byte_out_strobe;
wire [15:0] byte_count_total;
wire [15:0] byte_count;
wire [15:0] pkt_len_total;
wire [15:0] pkt_len;
reg set_stb;
reg [7:0] set_addr;
reg [31:0] set_data;
wire fcs_out_strobe, fcs_ok;
wire demod_is_ongoing;
wire receiver_rst;
wire sig_valid = (pkt_header_valid_strobe&pkt_header_valid);
integer addr;
integer bb_sample_fd;
integer power_trigger_fd;
integer short_preamble_detected_fd;
integer long_preamble_detected_fd;
integer sync_long_metric_fd;
integer sync_long_out_fd;
integer equalizer_out_fd;
integer demod_out_fd;
integer demod_soft_bits_fd;
integer demod_soft_bits_pos_fd;
integer deinterleave_erase_out_fd;
integer conv_out_fd;
integer descramble_out_fd;
integer signal_fd;
integer byte_out_fd;
integer file_i, file_q, file_rssi_half_db, iq_sample_file;
`define CLK_SPEED_100M
`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs7_gi1_aggr0_len1537_pre100_post200_openwifi.txt"
`define NUM_SAMPLE 118560
initial begin
$dumpfile("dot11.vcd");
$dumpvars;
clock = 0;
reset = 1;
enable = 0;
signal_done <= 0;
# 20 reset = 0;
enable = 1;
set_stb = 1;
# 20
set_addr = SR_SKIP_SAMPLE;
set_data = 0;
# 20 set_stb = 0;
end
integer file_open_trigger = 0;
always @(posedge clock) begin
file_open_trigger = file_open_trigger + 1;
if (file_open_trigger==1) begin
iq_sample_file = $fopen(`SAMPLE_FILE, "r");
bb_sample_fd = $fopen("./sample_in.txt", "w");
power_trigger_fd = $fopen("./power_trigger.txt", "w");
short_preamble_detected_fd = $fopen("./short_preamble_detected.txt", "w");
sync_long_metric_fd = $fopen("./sync_long_metric.txt", "w");
long_preamble_detected_fd = $fopen("./sync_long_frame_detected.txt", "w");
sync_long_out_fd = $fopen("./sync_long_out.txt", "w");
equalizer_out_fd = $fopen("./equalizer_out.txt", "w");
demod_out_fd = $fopen("./demod_out.txt", "w");
demod_soft_bits_fd = $fopen("./demod_soft_bits.txt", "w");
demod_soft_bits_pos_fd = $fopen("./demod_soft_bits_pos.txt", "w");
deinterleave_erase_out_fd = $fopen("./deinterleave_erase_out.txt", "w");
conv_out_fd = $fopen("./conv_out.txt", "w");
descramble_out_fd = $fopen("./descramble_out.txt", "w");
signal_fd = $fopen("./signal_out.txt", "w");
byte_out_fd = $fopen("./byte_out.txt", "w");
end
end
always begin
`ifdef CLK_SPEED_100M
#5 clock = !clock;
`elsif CLK_SPEED_200M
#2.5 clock = !clock;
`elsif CLK_SPEED_240M
#2.0833333333 clock = !clock;
`elsif CLK_SPEED_400M
#1.25 clock = !clock;
`endif
end
always @(posedge clock) begin
if (reset) begin
sample_in <= 0;
clk_count <= 0;
sample_in_strobe <= 0;
addr <= 0;
end else if (enable) begin
`ifdef CLK_SPEED_100M
if (clk_count == 4) begin
`elsif CLK_SPEED_200M
if (clk_count == 9) begin
`elsif CLK_SPEED_240M
if (clk_count == 11) begin
`elsif CLK_SPEED_400M
if (clk_count == 19) begin
`endif
sample_in_strobe <= 1;
$fscanf(iq_sample_file, "%d %d", file_i, file_q);
sample_in[15:0] <= file_q;
sample_in[31:16]<= file_i;
rssi_half_db <= 0;
addr <= addr + 1;
clk_count <= 0;
end else begin
sample_in_strobe <= 0;
clk_count <= clk_count + 1;
end
if (legacy_sig_stb) begin
end
if (sample_in_strobe) begin
$fwrite(bb_sample_fd, "%d %d %d\n", $time/2, $signed(sample_in[31:16]), $signed(sample_in[15:0]));
$fwrite(power_trigger_fd, "%d %d\n", $time/2, power_trigger);
$fwrite(short_preamble_detected_fd, "%d %d\n", $time/2, short_preamble_detected);
$fwrite(long_preamble_detected_fd, "%d %d\n", $time/2, long_preamble_detected);
$fflush(bb_sample_fd);
$fflush(power_trigger_fd);
$fflush(short_preamble_detected_fd);
$fflush(long_preamble_detected_fd);
if ((addr % 100) == 0) begin
$display("%d", addr);
end
if (addr == `NUM_SAMPLE) begin
$fclose(iq_sample_file);
$fclose(bb_sample_fd);
$fclose(power_trigger_fd);
$fclose(short_preamble_detected_fd);
$fclose(sync_long_metric_fd);
$fclose(long_preamble_detected_fd);
$fclose(sync_long_out_fd);
$fclose(equalizer_out_fd);
$fclose(demod_out_fd);
$fclose(demod_soft_bits_fd);
$fclose(demod_soft_bits_pos_fd);
$fclose(deinterleave_erase_out_fd);
$fclose(conv_out_fd);
$fclose(descramble_out_fd);
$fclose(signal_fd);
$fclose(byte_out_fd);
$finish;
end
end
if (sync_long_metric_stb) begin
$fwrite(sync_long_metric_fd, "%d %d\n", $time/2, sync_long_metric);
$fflush(sync_long_metric_fd);
end
if (sync_long_out_strobe) begin
$fwrite(sync_long_out_fd, "%d %d\n", $signed(sync_long_out[31:16]), $signed(sync_long_out[15:0]));
$fflush(sync_long_out_fd);
end
if (equalizer_out_strobe) begin
$fwrite(equalizer_out_fd, "%d %d\n", $signed(equalizer_out[31:16]), $signed(equalizer_out[15:0]));
$fflush(equalizer_out_fd);
end
if (legacy_sig_stb) begin
signal_done <= 1;
$fwrite(signal_fd, "%04b %b %012b %b %06b", legacy_rate, legacy_sig_rsvd, legacy_len, legacy_sig_parity, legacy_sig_tail);
$fflush(signal_fd);
end
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && demod_out_strobe) begin
$fwrite(demod_out_fd, "%b %b %b %b %b %b\n",demod_out[0],demod_out[1],demod_out[2],demod_out[3],demod_out[4],demod_out[5]);
$fwrite(demod_soft_bits_fd, "%b %b %b %b %b %b\n",demod_soft_bits[0],demod_soft_bits[1],demod_soft_bits[2],demod_soft_bits[3],demod_soft_bits[4],demod_soft_bits[5]);
$fwrite(demod_soft_bits_pos_fd, "%b %b %b %b\n",demod_soft_bits_pos[0],demod_soft_bits_pos[1],demod_soft_bits_pos[2],demod_soft_bits_pos[3]);
$fflush(demod_out_fd);
$fflush(demod_soft_bits_fd);
$fflush(demod_soft_bits_pos_fd);
end
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && deinterleave_erase_out_strobe) begin
$fwrite(deinterleave_erase_out_fd, "%b %b %b %b %b %b %b %b\n", deinterleave_erase_out[0], deinterleave_erase_out[1], deinterleave_erase_out[2], deinterleave_erase_out[3], deinterleave_erase_out[4], deinterleave_erase_out[5], deinterleave_erase_out[6], deinterleave_erase_out[7]);
$fflush(deinterleave_erase_out_fd);
end
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && conv_decoder_out_stb) begin
$fwrite(conv_out_fd, "%b\n", conv_decoder_out);
$fflush(conv_out_fd);
end
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && descramble_out_strobe) begin
$fwrite(descramble_out_fd, "%b\n", descramble_out);
$fflush(descramble_out_fd);
end
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && byte_out_strobe) begin
$fwrite(byte_out_fd, "%02x\n", byte_out);
$fflush(byte_out_fd);
end
end
end
signal_watchdog signal_watchdog_inst (
.clk(clock),
.rstn(~reset),
.enable(~demod_is_ongoing),
.i_data(sample_in[31:16]),
.q_data(sample_in[15:0]),
.iq_valid(sample_in_strobe),
.signal_len(pkt_len),
.sig_valid(sig_valid),
.max_signal_len_th(4095),
.dc_running_sum_th(64),
.receiver_rst(receiver_rst)
);
dot11 dot11_inst (
.clock(clock),
.enable(enable),
.reset(reset|receiver_rst),
.power_thres(11'd0),
.min_plateau(32'd100),
.rssi_half_db(rssi_half_db),
.sample_in(sample_in),
.sample_in_strobe(sample_in_strobe),
.soft_decoding(1'b1),
.demod_is_ongoing(demod_is_ongoing),
.pkt_header_valid(pkt_header_valid),
.pkt_header_valid_strobe(pkt_header_valid_strobe),
.pkt_len(pkt_len),
.pkt_len_total(pkt_len_total),
.byte_out_strobe(byte_out_strobe),
.byte_out(byte_out),
.byte_count_total(byte_count_total),
.byte_count(byte_count),
.fcs_out_strobe(fcs_out_strobe),
.fcs_ok(fcs_ok),
.state(dot11_state),
.power_trigger(power_trigger),
.short_preamble_detected(short_preamble_detected),
.sync_long_metric(sync_long_metric),
.sync_long_metric_stb(sync_long_metric_stb),
.long_preamble_detected(long_preamble_detected),
.sync_long_out(sync_long_out),
.sync_long_out_strobe(sync_long_out_strobe),
.equalizer_out(equalizer_out),
.equalizer_out_strobe(equalizer_out_strobe),
.legacy_sig_stb(legacy_sig_stb),
.legacy_rate(legacy_rate),
.legacy_sig_rsvd(legacy_sig_rsvd),
.legacy_len(legacy_len),
.legacy_sig_parity(legacy_sig_parity),
.legacy_sig_tail(legacy_sig_tail),
.demod_out(demod_out),
.demod_soft_bits(demod_soft_bits),
.demod_soft_bits_pos(demod_soft_bits_pos),
.demod_out_strobe(demod_out_strobe),
.deinterleave_erase_out(deinterleave_erase_out),
.deinterleave_erase_out_strobe(deinterleave_erase_out_strobe),
.conv_decoder_out(conv_decoder_out),
.conv_decoder_out_stb(conv_decoder_out_stb),
.descramble_out(descramble_out),
.descramble_out_strobe(descramble_out_strobe)
);
endmodule | 230 |
139,731 | data/full_repos/permissive/89514111/verilog/last_sym_indicator.v | 89,514,111 | last_sym_indicator.v | v | 126 | 180 | [] | [] | [] | [(4, 125)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/89514111/verilog/last_sym_indicator.v:29: Operator ADD expects 17 bits on the LHS, but LHS\'s VARREF \'n_ofdm_sym\' generates 8 bits.\n : ... In instance last_sym_indicator\nassign n_bit = n_dbps*(n_ofdm_sym+ht_correction);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/89514111/verilog/last_sym_indicator.v:29: Operator ADD expects 17 bits on the RHS, but RHS\'s VARREF \'ht_correction\' generates 1 bits.\n : ... In instance last_sym_indicator\nassign n_bit = n_dbps*(n_ofdm_sym+ht_correction);\n ^\n%Warning-WIDTH: data/full_repos/permissive/89514111/verilog/last_sym_indicator.v:108: Operator LTE expects 17 bits on the RHS, but RHS\'s VARREF \'n_dbps\' generates 9 bits.\n : ... In instance last_sym_indicator\n if ( (n_bit_target-n_bit)<=n_dbps ) begin\n ^~\n%Error: Exiting due to 3 warning(s)\n' | 306,544 | module | module last_sym_indicator
(
input clock,
input reset,
input enable,
input ofdm_sym_valid,
input [7:0] pkt_rate,
input [15:0] pkt_len,
input ht_correction,
output reg last_sym_flag
);
localparam S_WAIT_FOR_ALL_SYM = 0;
localparam S_ALL_SYM_RECEIVED = 1;
reg state;
reg ofdm_sym_valid_reg;
reg [8:0] n_dbps;
reg [7:0] n_ofdm_sym;
wire [16:0] n_bit;
wire [16:0] n_bit_target;
assign n_bit = n_dbps*(n_ofdm_sym+ht_correction);
assign n_bit_target = (({1'b0,pkt_len}<<3) + 16 + 6);
always @( pkt_rate[7],pkt_rate[3:0] )
begin
case ({pkt_rate[7],pkt_rate[3:0]})
5'b01011 : begin
n_dbps = 24;
end
5'b01111 : begin
n_dbps = 36;
end
5'b01010 : begin
n_dbps = 48;
end
5'b01110 : begin
n_dbps = 72;
end
5'b01001 : begin
n_dbps = 96;
end
5'b01101 : begin
n_dbps = 144;
end
5'b01000 : begin
n_dbps = 192;
end
5'b01100 : begin
n_dbps = 216;
end
5'b10000 : begin
n_dbps = 26;
end
5'b10001 : begin
n_dbps = 52;
end
5'b10010 : begin
n_dbps = 78;
end
5'b10011 : begin
n_dbps = 104;
end
5'b10100 : begin
n_dbps = 156;
end
5'b10101 : begin
n_dbps = 208;
end
5'b10110 : begin
n_dbps = 234;
end
5'b10111 : begin
n_dbps = 260;
end
default: begin
n_dbps = 0;
end
endcase
end
always @(posedge clock) begin
if (reset) begin
ofdm_sym_valid_reg <= 0;
end else begin
ofdm_sym_valid_reg <= ofdm_sym_valid;
end
end
always @(posedge clock) begin
if (reset) begin
n_ofdm_sym <= 0;
last_sym_flag <= 0;
state <= S_WAIT_FOR_ALL_SYM;
end else if (ofdm_sym_valid==0 && ofdm_sym_valid_reg==1) begin
n_ofdm_sym <= n_ofdm_sym + 1;
if (enable) begin
case(state)
S_WAIT_FOR_ALL_SYM: begin
if ( (n_bit_target-n_bit)<=n_dbps ) begin
last_sym_flag <= 0;
state <= S_ALL_SYM_RECEIVED;
end
end
S_ALL_SYM_RECEIVED: begin
last_sym_flag <= 1;
state <= S_ALL_SYM_RECEIVED;
end
default: begin
end
endcase
end
end
end
endmodule | module last_sym_indicator
(
input clock,
input reset,
input enable,
input ofdm_sym_valid,
input [7:0] pkt_rate,
input [15:0] pkt_len,
input ht_correction,
output reg last_sym_flag
); |
localparam S_WAIT_FOR_ALL_SYM = 0;
localparam S_ALL_SYM_RECEIVED = 1;
reg state;
reg ofdm_sym_valid_reg;
reg [8:0] n_dbps;
reg [7:0] n_ofdm_sym;
wire [16:0] n_bit;
wire [16:0] n_bit_target;
assign n_bit = n_dbps*(n_ofdm_sym+ht_correction);
assign n_bit_target = (({1'b0,pkt_len}<<3) + 16 + 6);
always @( pkt_rate[7],pkt_rate[3:0] )
begin
case ({pkt_rate[7],pkt_rate[3:0]})
5'b01011 : begin
n_dbps = 24;
end
5'b01111 : begin
n_dbps = 36;
end
5'b01010 : begin
n_dbps = 48;
end
5'b01110 : begin
n_dbps = 72;
end
5'b01001 : begin
n_dbps = 96;
end
5'b01101 : begin
n_dbps = 144;
end
5'b01000 : begin
n_dbps = 192;
end
5'b01100 : begin
n_dbps = 216;
end
5'b10000 : begin
n_dbps = 26;
end
5'b10001 : begin
n_dbps = 52;
end
5'b10010 : begin
n_dbps = 78;
end
5'b10011 : begin
n_dbps = 104;
end
5'b10100 : begin
n_dbps = 156;
end
5'b10101 : begin
n_dbps = 208;
end
5'b10110 : begin
n_dbps = 234;
end
5'b10111 : begin
n_dbps = 260;
end
default: begin
n_dbps = 0;
end
endcase
end
always @(posedge clock) begin
if (reset) begin
ofdm_sym_valid_reg <= 0;
end else begin
ofdm_sym_valid_reg <= ofdm_sym_valid;
end
end
always @(posedge clock) begin
if (reset) begin
n_ofdm_sym <= 0;
last_sym_flag <= 0;
state <= S_WAIT_FOR_ALL_SYM;
end else if (ofdm_sym_valid==0 && ofdm_sym_valid_reg==1) begin
n_ofdm_sym <= n_ofdm_sym + 1;
if (enable) begin
case(state)
S_WAIT_FOR_ALL_SYM: begin
if ( (n_bit_target-n_bit)<=n_dbps ) begin
last_sym_flag <= 0;
state <= S_ALL_SYM_RECEIVED;
end
end
S_ALL_SYM_RECEIVED: begin
last_sym_flag <= 1;
state <= S_ALL_SYM_RECEIVED;
end
default: begin
end
endcase
end
end
end
endmodule | 230 |
139,734 | data/full_repos/permissive/89514111/verilog/rotate.v | 89,514,111 | rotate.v | v | 164 | 72 | [] | [] | [] | [(11, 245)] | null | null | 1: b'%Error: data/full_repos/permissive/89514111/verilog/rotate.v:1: Cannot find include file: common_defs.v\n`include "common_defs.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89514111/verilog,data/full_repos/permissive/89514111/common_defs.v\n data/full_repos/permissive/89514111/verilog,data/full_repos/permissive/89514111/common_defs.v.v\n data/full_repos/permissive/89514111/verilog,data/full_repos/permissive/89514111/common_defs.v.sv\n common_defs.v\n common_defs.v.v\n common_defs.v.sv\n obj_dir/common_defs.v\n obj_dir/common_defs.v.v\n obj_dir/common_defs.v.sv\n%Error: data/full_repos/permissive/89514111/verilog/rotate.v:23: Cannot find include file: common_params.v\n`include "common_params.v" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89514111/verilog/rotate.v:16: Define or directive not defined: \'`ROTATE_LUT_LEN_SHIFT\'\n output [`ROTATE_LUT_LEN_SHIFT-1:0] rot_addr,\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89514111/verilog/rotate.v:45: Define or directive not defined: \'`ROTATE_LUT_SCALE_SHIFT\'\nassign out_i = p_i[`ROTATE_LUT_SCALE_SHIFT+15:`ROTATE_LUT_SCALE_SHIFT];\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89514111/verilog/rotate.v:45: Define or directive not defined: \'`ROTATE_LUT_SCALE_SHIFT\'\nassign out_i = p_i[`ROTATE_LUT_SCALE_SHIFT+15:`ROTATE_LUT_SCALE_SHIFT];\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89514111/verilog/rotate.v:45: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign out_i = p_i[`ROTATE_LUT_SCALE_SHIFT+15:`ROTATE_LUT_SCALE_SHIFT];\n ^\n%Error: data/full_repos/permissive/89514111/verilog/rotate.v:46: Define or directive not defined: \'`ROTATE_LUT_SCALE_SHIFT\'\nassign out_q = p_q[`ROTATE_LUT_SCALE_SHIFT+15:`ROTATE_LUT_SCALE_SHIFT];\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89514111/verilog/rotate.v:46: Define or directive not defined: \'`ROTATE_LUT_SCALE_SHIFT\'\nassign out_q = p_q[`ROTATE_LUT_SCALE_SHIFT+15:`ROTATE_LUT_SCALE_SHIFT];\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89514111/verilog/rotate.v:46: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign out_q = p_q[`ROTATE_LUT_SCALE_SHIFT+15:`ROTATE_LUT_SCALE_SHIFT];\n ^\n%Error: data/full_repos/permissive/89514111/verilog/rotate.v:48: Define or directive not defined: \'`ROTATE_LUT_LEN_SHIFT\'\nassign rot_addr = actual_phase[`ROTATE_LUT_LEN_SHIFT-1:0];\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n' | 306,554 | module | module rotate
(
input clock,
input enable,
input reset,
input [15:0] in_i,
input [15:0] in_q,
input signed [15:0] phase,
input input_strobe,
output [`ROTATE_LUT_LEN_SHIFT-1:0] rot_addr,
input [31:0] rot_data,
output signed [15:0] out_i,
output signed [15:0] out_q,
output output_strobe
);
`include "common_params.v"
reg [15:0] phase_delayed;
reg [15:0] phase_abs;
reg [2:0] quadrant;
reg [2:0] quadrant_delayed;
wire [15:0] in_i_delayed;
wire [15:0] in_q_delayed;
reg [15:0] actual_phase;
wire [15:0] raw_rot_i;
wire [15:0] raw_rot_q;
reg [15:0] rot_i;
reg [15:0] rot_q;
wire mult_in_stb;
wire [31:0] p_i;
wire [31:0] p_q;
assign out_i = p_i[`ROTATE_LUT_SCALE_SHIFT+15:`ROTATE_LUT_SCALE_SHIFT];
assign out_q = p_q[`ROTATE_LUT_SCALE_SHIFT+15:`ROTATE_LUT_SCALE_SHIFT];
assign rot_addr = actual_phase[`ROTATE_LUT_LEN_SHIFT-1:0];
assign raw_rot_i = rot_data[31:16];
assign raw_rot_q = rot_data[15:0];
delayT #(.DATA_WIDTH(32), .DELAY(4)) in_delay_inst (
.clock(clock),
.reset(reset),
.data_in({in_i, in_q}),
.data_out({in_i_delayed, in_q_delayed})
);
delayT #(.DATA_WIDTH(1), .DELAY(4)) mult_delay_inst (
.clock(clock),
.reset(reset),
.data_in(input_strobe),
.data_out(mult_in_stb)
);
complex_mult mult_inst (
.clock(clock),
.enable(enable),
.reset(reset),
.a_i(in_i_delayed),
.a_q(in_q_delayed),
.b_i(rot_i),
.b_q(rot_q),
.input_strobe(mult_in_stb),
.p_i(p_i),
.p_q(p_q),
.output_strobe(output_strobe)
);
integer i;
always @(posedge clock) begin
if (reset) begin
actual_phase <= 0;
rot_i <= 0;
rot_q <= 0;
phase_abs <= 0;
phase_delayed <= 0;
end else if (enable) begin
`ifdef DEBUG_PRINT
if (phase > PI || phase < -PI) begin
$display("[WARN] phase overflow: %d\n", phase);
end
`endif
phase_abs <= phase[15]? ~phase+1: phase;
phase_delayed <= phase;
if (phase_abs <= PI_4) begin
quadrant <= {phase_delayed[15], 2'b00};
actual_phase <= phase_abs;
end else if (phase_abs <= PI_2) begin
quadrant <= {phase_delayed[15], 2'b01};
actual_phase <= PI_2 - phase_abs;
end else if (phase_abs <= PI_3_4) begin
quadrant <= {phase_delayed[15], 2'b10};
actual_phase <= phase_abs - PI_2;
end else begin
quadrant <= {phase_delayed[15], 2'b11};
actual_phase <= PI - phase_abs;
end
quadrant_delayed <= quadrant;
case(quadrant_delayed)
3'b000: begin
rot_i <= raw_rot_i;
rot_q <= raw_rot_q;
end
3'b001: begin
rot_i <= raw_rot_q;
rot_q <= raw_rot_i;
end
3'b010: begin
rot_i <= ~raw_rot_q+1;
rot_q <= raw_rot_i;
end
3'b011: begin
rot_i <= ~raw_rot_i+1;
rot_q <= raw_rot_q;
end
3'b100: begin
rot_i <= raw_rot_i;
rot_q <= ~raw_rot_q+1;
end
3'b101: begin
rot_i <= raw_rot_q;
rot_q <= ~raw_rot_i+1;
end
3'b110: begin
rot_i <= ~raw_rot_q+1;
rot_q <= ~raw_rot_i+1;
end
3'b111: begin
rot_i <= ~raw_rot_i+1;
rot_q <= ~raw_rot_q+1;
end
endcase
end
end
endmodule | module rotate
(
input clock,
input enable,
input reset,
input [15:0] in_i,
input [15:0] in_q,
input signed [15:0] phase,
input input_strobe,
output [`ROTATE_LUT_LEN_SHIFT-1:0] rot_addr,
input [31:0] rot_data,
output signed [15:0] out_i,
output signed [15:0] out_q,
output output_strobe
); |
`include "common_params.v"
reg [15:0] phase_delayed;
reg [15:0] phase_abs;
reg [2:0] quadrant;
reg [2:0] quadrant_delayed;
wire [15:0] in_i_delayed;
wire [15:0] in_q_delayed;
reg [15:0] actual_phase;
wire [15:0] raw_rot_i;
wire [15:0] raw_rot_q;
reg [15:0] rot_i;
reg [15:0] rot_q;
wire mult_in_stb;
wire [31:0] p_i;
wire [31:0] p_q;
assign out_i = p_i[`ROTATE_LUT_SCALE_SHIFT+15:`ROTATE_LUT_SCALE_SHIFT];
assign out_q = p_q[`ROTATE_LUT_SCALE_SHIFT+15:`ROTATE_LUT_SCALE_SHIFT];
assign rot_addr = actual_phase[`ROTATE_LUT_LEN_SHIFT-1:0];
assign raw_rot_i = rot_data[31:16];
assign raw_rot_q = rot_data[15:0];
delayT #(.DATA_WIDTH(32), .DELAY(4)) in_delay_inst (
.clock(clock),
.reset(reset),
.data_in({in_i, in_q}),
.data_out({in_i_delayed, in_q_delayed})
);
delayT #(.DATA_WIDTH(1), .DELAY(4)) mult_delay_inst (
.clock(clock),
.reset(reset),
.data_in(input_strobe),
.data_out(mult_in_stb)
);
complex_mult mult_inst (
.clock(clock),
.enable(enable),
.reset(reset),
.a_i(in_i_delayed),
.a_q(in_q_delayed),
.b_i(rot_i),
.b_q(rot_q),
.input_strobe(mult_in_stb),
.p_i(p_i),
.p_q(p_q),
.output_strobe(output_strobe)
);
integer i;
always @(posedge clock) begin
if (reset) begin
actual_phase <= 0;
rot_i <= 0;
rot_q <= 0;
phase_abs <= 0;
phase_delayed <= 0;
end else if (enable) begin
`ifdef DEBUG_PRINT
if (phase > PI || phase < -PI) begin
$display("[WARN] phase overflow: %d\n", phase);
end
`endif
phase_abs <= phase[15]? ~phase+1: phase;
phase_delayed <= phase;
if (phase_abs <= PI_4) begin
quadrant <= {phase_delayed[15], 2'b00};
actual_phase <= phase_abs;
end else if (phase_abs <= PI_2) begin
quadrant <= {phase_delayed[15], 2'b01};
actual_phase <= PI_2 - phase_abs;
end else if (phase_abs <= PI_3_4) begin
quadrant <= {phase_delayed[15], 2'b10};
actual_phase <= phase_abs - PI_2;
end else begin
quadrant <= {phase_delayed[15], 2'b11};
actual_phase <= PI - phase_abs;
end
quadrant_delayed <= quadrant;
case(quadrant_delayed)
3'b000: begin
rot_i <= raw_rot_i;
rot_q <= raw_rot_q;
end
3'b001: begin
rot_i <= raw_rot_q;
rot_q <= raw_rot_i;
end
3'b010: begin
rot_i <= ~raw_rot_q+1;
rot_q <= raw_rot_i;
end
3'b011: begin
rot_i <= ~raw_rot_i+1;
rot_q <= raw_rot_q;
end
3'b100: begin
rot_i <= raw_rot_i;
rot_q <= ~raw_rot_q+1;
end
3'b101: begin
rot_i <= raw_rot_q;
rot_q <= ~raw_rot_i+1;
end
3'b110: begin
rot_i <= ~raw_rot_q+1;
rot_q <= ~raw_rot_i+1;
end
3'b111: begin
rot_i <= ~raw_rot_i+1;
rot_q <= ~raw_rot_q+1;
end
endcase
end
end
endmodule | 230 |
139,735 | data/full_repos/permissive/89514111/verilog/running_sum.v | 89,514,111 | running_sum.v | v | 94 | 106 | [] | [] | [] | [(3, 93)] | null | null | 1: b"%Error: data/full_repos/permissive/89514111/verilog/running_sum.v:31: Cannot find file containing module: 'xpm_fifo_sync'\nxpm_fifo_sync #(\n^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89514111/verilog,data/full_repos/permissive/89514111/xpm_fifo_sync\n data/full_repos/permissive/89514111/verilog,data/full_repos/permissive/89514111/xpm_fifo_sync.v\n data/full_repos/permissive/89514111/verilog,data/full_repos/permissive/89514111/xpm_fifo_sync.sv\n xpm_fifo_sync\n xpm_fifo_sync.v\n xpm_fifo_sync.sv\n obj_dir/xpm_fifo_sync\n obj_dir/xpm_fifo_sync.v\n obj_dir/xpm_fifo_sync.sv\n%Error: Exiting due to 1 error(s)\n" | 306,555 | module | module running_sum
#(
parameter DATA_WIDTH = 16,
parameter LOG2_SUM_LEN = 6
)
(
input clk,
input rstn,
input signed [DATA_WIDTH-1:0] data_in,
input data_in_valid,
output reg signed [(DATA_WIDTH + LOG2_SUM_LEN-1):0] running_sum_result,
output reg data_out_valid
);
localparam FIFO_SIZE = 1<<LOG2_SUM_LEN;
localparam TOTAL_WIDTH = DATA_WIDTH + LOG2_SUM_LEN;
wire signed [DATA_WIDTH-1:0] data_in_old;
wire signed [TOTAL_WIDTH-1:0] ext_data_in_old = {{LOG2_SUM_LEN{data_in_old[DATA_WIDTH-1]}}, data_in_old};
wire signed [TOTAL_WIDTH-1:0] ext_data_in = {{LOG2_SUM_LEN{data_in[DATA_WIDTH-1]}}, data_in };
reg data_in_valid_reg;
reg rd_en, rd_en_start;
wire [LOG2_SUM_LEN:0] wr_data_count;
xpm_fifo_sync #(
.DOUT_RESET_VALUE("0"),
.ECC_MODE("no_ecc"),
.FIFO_MEMORY_TYPE("auto"),
.FIFO_READ_LATENCY(0),
.FIFO_WRITE_DEPTH(FIFO_SIZE),
.FULL_RESET_VALUE(0),
.PROG_EMPTY_THRESH(10),
.PROG_FULL_THRESH(10),
.RD_DATA_COUNT_WIDTH(LOG2_SUM_LEN+1),
.READ_DATA_WIDTH(DATA_WIDTH),
.READ_MODE("fwft"),
.USE_ADV_FEATURES("0404"),
.WAKEUP_TIME(0),
.WRITE_DATA_WIDTH(DATA_WIDTH),
.WR_DATA_COUNT_WIDTH(LOG2_SUM_LEN+1)
) fifo_1clk_for_mv_avg_i (
.almost_empty(),
.almost_full(),
.data_valid(),
.dbiterr(),
.dout(data_in_old),
.empty(empty),
.full(full),
.overflow(),
.prog_empty(),
.prog_full(),
.rd_data_count(),
.rd_rst_busy(),
.sbiterr(),
.underflow(),
.wr_ack(),
.wr_data_count(wr_data_count),
.wr_rst_busy(),
.din(data_in),
.injectdbiterr(),
.injectsbiterr(),
.rd_en(rd_en),
.rst(~rstn),
.sleep(),
.wr_clk(clk),
.wr_en(data_in_valid)
);
always @(posedge clk) begin
if (~rstn) begin
data_in_valid_reg <= 0;
running_sum_result <= 0;
data_out_valid <= 0;
rd_en <= 0;
rd_en_start <= 0;
end else begin
data_in_valid_reg <= data_in_valid;
data_out_valid <= data_in_valid_reg;
rd_en_start <= ((wr_data_count == FIFO_SIZE)?1:rd_en_start);
rd_en <= (rd_en_start?data_in_valid:rd_en);
if (data_in_valid) begin
running_sum_result <= running_sum_result + ext_data_in - (rd_en_start?ext_data_in_old:0);
end
end
end
endmodule | module running_sum
#(
parameter DATA_WIDTH = 16,
parameter LOG2_SUM_LEN = 6
)
(
input clk,
input rstn,
input signed [DATA_WIDTH-1:0] data_in,
input data_in_valid,
output reg signed [(DATA_WIDTH + LOG2_SUM_LEN-1):0] running_sum_result,
output reg data_out_valid
); |
localparam FIFO_SIZE = 1<<LOG2_SUM_LEN;
localparam TOTAL_WIDTH = DATA_WIDTH + LOG2_SUM_LEN;
wire signed [DATA_WIDTH-1:0] data_in_old;
wire signed [TOTAL_WIDTH-1:0] ext_data_in_old = {{LOG2_SUM_LEN{data_in_old[DATA_WIDTH-1]}}, data_in_old};
wire signed [TOTAL_WIDTH-1:0] ext_data_in = {{LOG2_SUM_LEN{data_in[DATA_WIDTH-1]}}, data_in };
reg data_in_valid_reg;
reg rd_en, rd_en_start;
wire [LOG2_SUM_LEN:0] wr_data_count;
xpm_fifo_sync #(
.DOUT_RESET_VALUE("0"),
.ECC_MODE("no_ecc"),
.FIFO_MEMORY_TYPE("auto"),
.FIFO_READ_LATENCY(0),
.FIFO_WRITE_DEPTH(FIFO_SIZE),
.FULL_RESET_VALUE(0),
.PROG_EMPTY_THRESH(10),
.PROG_FULL_THRESH(10),
.RD_DATA_COUNT_WIDTH(LOG2_SUM_LEN+1),
.READ_DATA_WIDTH(DATA_WIDTH),
.READ_MODE("fwft"),
.USE_ADV_FEATURES("0404"),
.WAKEUP_TIME(0),
.WRITE_DATA_WIDTH(DATA_WIDTH),
.WR_DATA_COUNT_WIDTH(LOG2_SUM_LEN+1)
) fifo_1clk_for_mv_avg_i (
.almost_empty(),
.almost_full(),
.data_valid(),
.dbiterr(),
.dout(data_in_old),
.empty(empty),
.full(full),
.overflow(),
.prog_empty(),
.prog_full(),
.rd_data_count(),
.rd_rst_busy(),
.sbiterr(),
.underflow(),
.wr_ack(),
.wr_data_count(wr_data_count),
.wr_rst_busy(),
.din(data_in),
.injectdbiterr(),
.injectsbiterr(),
.rd_en(rd_en),
.rst(~rstn),
.sleep(),
.wr_clk(clk),
.wr_en(data_in_valid)
);
always @(posedge clk) begin
if (~rstn) begin
data_in_valid_reg <= 0;
running_sum_result <= 0;
data_out_valid <= 0;
rd_en <= 0;
rd_en_start <= 0;
end else begin
data_in_valid_reg <= data_in_valid;
data_out_valid <= data_in_valid_reg;
rd_en_start <= ((wr_data_count == FIFO_SIZE)?1:rd_en_start);
rd_en <= (rd_en_start?data_in_valid:rd_en);
if (data_in_valid) begin
running_sum_result <= running_sum_result + ext_data_in - (rd_en_start?ext_data_in_old:0);
end
end
end
endmodule | 230 |
139,736 | data/full_repos/permissive/89514111/verilog/signal_watchdog.v | 89,514,111 | signal_watchdog.v | v | 69 | 138 | [] | [] | [] | [(3, 68)] | null | null | 1: b"%Error: data/full_repos/permissive/89514111/verilog/signal_watchdog.v:56: Cannot find file containing module: 'running_sum_dual_ch'\n running_sum_dual_ch #(.DATA_WIDTH0(2), .DATA_WIDTH1(2), .LOG2_SUM_LEN(LOG2_SUM_LEN)) signal_watchdog_running_sum_inst (\n ^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89514111/verilog,data/full_repos/permissive/89514111/running_sum_dual_ch\n data/full_repos/permissive/89514111/verilog,data/full_repos/permissive/89514111/running_sum_dual_ch.v\n data/full_repos/permissive/89514111/verilog,data/full_repos/permissive/89514111/running_sum_dual_ch.sv\n running_sum_dual_ch\n running_sum_dual_ch.v\n running_sum_dual_ch.sv\n obj_dir/running_sum_dual_ch\n obj_dir/running_sum_dual_ch.v\n obj_dir/running_sum_dual_ch.sv\n%Error: Exiting due to 1 error(s)\n" | 306,557 | module | module signal_watchdog
#(
parameter integer IQ_DATA_WIDTH = 16,
parameter LOG2_SUM_LEN = 6
)
(
input clk,
input rstn,
input enable,
input signed [(IQ_DATA_WIDTH-1):0] i_data,
input signed [(IQ_DATA_WIDTH-1):0] q_data,
input iq_valid,
input [15:0] signal_len,
input sig_valid,
input [15:0] max_signal_len_th,
input signed [(LOG2_SUM_LEN+2-1):0] dc_running_sum_th,
output receiver_rst
);
wire signed [1:0] i_sign;
wire signed [1:0] q_sign;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_i;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_q;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_i_abs;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_q_abs;
wire receiver_rst_internal;
reg receiver_rst_reg;
wire receiver_rst_pulse;
assign i_sign = (i_data[(IQ_DATA_WIDTH-1)] ? -1 : 1);
assign q_sign = (q_data[(IQ_DATA_WIDTH-1)] ? -1 : 1);
assign running_sum_result_i_abs = (running_sum_result_i[LOG2_SUM_LEN+2-1]?(-running_sum_result_i):running_sum_result_i);
assign running_sum_result_q_abs = (running_sum_result_q[LOG2_SUM_LEN+2-1]?(-running_sum_result_q):running_sum_result_q);
assign receiver_rst_internal = (enable&(running_sum_result_i_abs>=dc_running_sum_th || running_sum_result_q_abs>=dc_running_sum_th));
assign receiver_rst_pulse = (receiver_rst_internal&&(~receiver_rst_reg));
assign receiver_rst = ( receiver_rst_reg | (sig_valid && (signal_len<14 || signal_len>max_signal_len_th)) );
always @(posedge clk) begin
if (~rstn) begin
receiver_rst_reg <= 0;
end else begin
receiver_rst_reg <= receiver_rst_internal;
end
end
running_sum_dual_ch #(.DATA_WIDTH0(2), .DATA_WIDTH1(2), .LOG2_SUM_LEN(LOG2_SUM_LEN)) signal_watchdog_running_sum_inst (
.clk(clk),
.rstn(rstn),
.data_in0(i_sign),
.data_in1(q_sign),
.data_in_valid(iq_valid),
.running_sum_result0(running_sum_result_i),
.running_sum_result1(running_sum_result_q),
.data_out_valid()
);
endmodule | module signal_watchdog
#(
parameter integer IQ_DATA_WIDTH = 16,
parameter LOG2_SUM_LEN = 6
)
(
input clk,
input rstn,
input enable,
input signed [(IQ_DATA_WIDTH-1):0] i_data,
input signed [(IQ_DATA_WIDTH-1):0] q_data,
input iq_valid,
input [15:0] signal_len,
input sig_valid,
input [15:0] max_signal_len_th,
input signed [(LOG2_SUM_LEN+2-1):0] dc_running_sum_th,
output receiver_rst
); |
wire signed [1:0] i_sign;
wire signed [1:0] q_sign;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_i;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_q;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_i_abs;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_q_abs;
wire receiver_rst_internal;
reg receiver_rst_reg;
wire receiver_rst_pulse;
assign i_sign = (i_data[(IQ_DATA_WIDTH-1)] ? -1 : 1);
assign q_sign = (q_data[(IQ_DATA_WIDTH-1)] ? -1 : 1);
assign running_sum_result_i_abs = (running_sum_result_i[LOG2_SUM_LEN+2-1]?(-running_sum_result_i):running_sum_result_i);
assign running_sum_result_q_abs = (running_sum_result_q[LOG2_SUM_LEN+2-1]?(-running_sum_result_q):running_sum_result_q);
assign receiver_rst_internal = (enable&(running_sum_result_i_abs>=dc_running_sum_th || running_sum_result_q_abs>=dc_running_sum_th));
assign receiver_rst_pulse = (receiver_rst_internal&&(~receiver_rst_reg));
assign receiver_rst = ( receiver_rst_reg | (sig_valid && (signal_len<14 || signal_len>max_signal_len_th)) );
always @(posedge clk) begin
if (~rstn) begin
receiver_rst_reg <= 0;
end else begin
receiver_rst_reg <= receiver_rst_internal;
end
end
running_sum_dual_ch #(.DATA_WIDTH0(2), .DATA_WIDTH1(2), .LOG2_SUM_LEN(LOG2_SUM_LEN)) signal_watchdog_running_sum_inst (
.clk(clk),
.rstn(rstn),
.data_in0(i_sign),
.data_in1(q_sign),
.data_in_valid(iq_valid),
.running_sum_result0(running_sum_result_i),
.running_sum_result1(running_sum_result_q),
.data_out_valid()
);
endmodule | 230 |
139,737 | data/full_repos/permissive/89514111/verilog/stage_mult.v | 89,514,111 | stage_mult.v | v | 206 | 57 | [] | [] | [] | [(1, 205)] | null | null | 1: b"%Error: data/full_repos/permissive/89514111/verilog/stage_mult.v:82: Cannot find file containing module: 'complex_multiplier'\ncomplex_multiplier mult_inst1 (\n^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89514111/verilog,data/full_repos/permissive/89514111/complex_multiplier\n data/full_repos/permissive/89514111/verilog,data/full_repos/permissive/89514111/complex_multiplier.v\n data/full_repos/permissive/89514111/verilog,data/full_repos/permissive/89514111/complex_multiplier.sv\n complex_multiplier\n complex_multiplier.v\n complex_multiplier.sv\n obj_dir/complex_multiplier\n obj_dir/complex_multiplier.v\n obj_dir/complex_multiplier.sv\n%Error: data/full_repos/permissive/89514111/verilog/stage_mult.v:92: Cannot find file containing module: 'complex_multiplier'\ncomplex_multiplier mult_inst2 (\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89514111/verilog/stage_mult.v:102: Cannot find file containing module: 'complex_multiplier'\ncomplex_multiplier mult_inst3 (\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89514111/verilog/stage_mult.v:112: Cannot find file containing module: 'complex_multiplier'\ncomplex_multiplier mult_inst4 (\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89514111/verilog/stage_mult.v:122: Cannot find file containing module: 'complex_multiplier'\ncomplex_multiplier mult_inst5 (\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89514111/verilog/stage_mult.v:132: Cannot find file containing module: 'complex_multiplier'\ncomplex_multiplier mult_inst6 (\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89514111/verilog/stage_mult.v:142: Cannot find file containing module: 'complex_multiplier'\ncomplex_multiplier mult_inst7 (\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89514111/verilog/stage_mult.v:152: Cannot find file containing module: 'complex_multiplier'\ncomplex_multiplier mult_inst8 (\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89514111/verilog/stage_mult.v:171: Cannot find file containing module: 'delayT'\ndelayT #(.DATA_WIDTH(1), .DELAY(5)) sum_delay_inst (\n^~~~~~\n%Error: Exiting due to 9 error(s)\n" | 306,558 | module | module stage_mult
(
input clock,
input enable,
input reset,
input signed [31:0] X0,
input signed [31:0] X1,
input signed [31:0] X2,
input signed [31:0] X3,
input signed [31:0] X4,
input signed [31:0] X5,
input signed [31:0] X6,
input signed [31:0] X7,
input signed [31:0] Y0,
input signed [31:0] Y1,
input signed [31:0] Y2,
input signed [31:0] Y3,
input signed [31:0] Y4,
input signed [31:0] Y5,
input signed [31:0] Y6,
input signed [31:0] Y7,
input input_strobe,
output reg [63:0] sum,
output output_strobe
);
wire signed [15:0] X0_q = X0[31:16];
wire signed [15:0] X0_i = X0[15:0];
wire signed [15:0] X1_q = X1[31:16];
wire signed [15:0] X1_i = X1[15:0];
wire signed [15:0] X2_q = X2[31:16];
wire signed [15:0] X2_i = X2[15:0];
wire signed [15:0] X3_q = X3[31:16];
wire signed [15:0] X3_i = X3[15:0];
wire signed [15:0] X4_q = X4[31:16];
wire signed [15:0] X4_i = X4[15:0];
wire signed [15:0] X5_q = X5[31:16];
wire signed [15:0] X5_i = X5[15:0];
wire signed [15:0] X6_q = X6[31:16];
wire signed [15:0] X6_i = X6[15:0];
wire signed [15:0] X7_q = X7[31:16];
wire signed [15:0] X7_i = X7[15:0];
wire signed [15:0] Y0_q = Y0[31:16];
wire signed [15:0] Y0_i = Y0[15:0];
wire signed [15:0] Y1_q = Y1[31:16];
wire signed [15:0] Y1_i = Y1[15:0];
wire signed [15:0] Y2_q = Y2[31:16];
wire signed [15:0] Y2_i = Y2[15:0];
wire signed [15:0] Y3_q = Y3[31:16];
wire signed [15:0] Y3_i = Y3[15:0];
wire signed [15:0] Y4_q = Y4[31:16];
wire signed [15:0] Y4_i = Y4[15:0];
wire signed [15:0] Y5_q = Y5[31:16];
wire signed [15:0] Y5_i = Y5[15:0];
wire signed [15:0] Y6_q = Y6[31:16];
wire signed [15:0] Y6_i = Y6[15:0];
wire signed [15:0] Y7_q = Y7[31:16];
wire signed [15:0] Y7_i = Y7[15:0];
wire signed [31:0] prod_0_i;
wire signed [31:0] prod_0_q;
wire signed [31:0] prod_1_i;
wire signed [31:0] prod_1_q;
wire signed [31:0] prod_2_i;
wire signed [31:0] prod_2_q;
wire signed [31:0] prod_3_i;
wire signed [31:0] prod_3_q;
wire signed [31:0] prod_4_i;
wire signed [31:0] prod_4_q;
wire signed [31:0] prod_5_i;
wire signed [31:0] prod_5_q;
wire signed [31:0] prod_6_i;
wire signed [31:0] prod_6_q;
wire signed [31:0] prod_7_i;
wire signed [31:0] prod_7_q;
complex_multiplier mult_inst1 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X0_i,X0_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y0_i,Y0_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_0_q,prod_0_i})
);
complex_multiplier mult_inst2 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X1_i,X1_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y1_i,Y1_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_1_q,prod_1_i})
);
complex_multiplier mult_inst3 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X2_i,X2_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y2_i,Y2_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_2_q,prod_2_i})
);
complex_multiplier mult_inst4 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X3_i,X3_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y3_i,Y3_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_3_q,prod_3_i})
);
complex_multiplier mult_inst5 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X4_i,X4_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y4_i,Y4_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_4_q,prod_4_i})
);
complex_multiplier mult_inst6 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X5_i,X5_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y5_i,Y5_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_5_q,prod_5_i})
);
complex_multiplier mult_inst7 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X6_i,X6_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y6_i,Y6_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_6_q,prod_6_i})
);
complex_multiplier mult_inst8 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X7_i,X7_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y7_i,Y7_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_7_q,prod_7_i})
);
reg signed [31:0] sum_i1;
reg signed [31:0] sum_i2;
reg signed [31:0] sum_i3;
reg signed [31:0] sum_i4;
reg signed [31:0] sum_q1;
reg signed [31:0] sum_q2;
reg signed [31:0] sum_q3;
reg signed [31:0] sum_q4;
delayT #(.DATA_WIDTH(1), .DELAY(5)) sum_delay_inst (
.clock(clock),
.reset(reset),
.data_in(input_strobe),
.data_out(output_strobe)
);
always @(posedge clock) begin
if (reset) begin
sum <= 0;
sum_i1 <= 0;
sum_i2 <= 0;
sum_i3 <= 0;
sum_i4 <= 0;
sum_q1 <= 0;
sum_q2 <= 0;
sum_q3 <= 0;
sum_q4 <= 0;
end else if (enable) begin
sum_i1 <= prod_0_i + prod_1_i;
sum_i2 <= prod_2_i + prod_3_i;
sum_i3 <= prod_4_i + prod_5_i;
sum_i4 <= prod_6_i + prod_7_i;
sum_q1 <= prod_0_q + prod_1_q;
sum_q2 <= prod_2_q + prod_3_q;
sum_q3 <= prod_4_q + prod_5_q;
sum_q4 <= prod_6_q + prod_7_q;
sum[63:32] <= sum_i1 + sum_i2 + sum_i3 + sum_i4;
sum[31:0] <= sum_q1 + sum_q2 + sum_q3 + sum_q4;
end
end
endmodule | module stage_mult
(
input clock,
input enable,
input reset,
input signed [31:0] X0,
input signed [31:0] X1,
input signed [31:0] X2,
input signed [31:0] X3,
input signed [31:0] X4,
input signed [31:0] X5,
input signed [31:0] X6,
input signed [31:0] X7,
input signed [31:0] Y0,
input signed [31:0] Y1,
input signed [31:0] Y2,
input signed [31:0] Y3,
input signed [31:0] Y4,
input signed [31:0] Y5,
input signed [31:0] Y6,
input signed [31:0] Y7,
input input_strobe,
output reg [63:0] sum,
output output_strobe
); |
wire signed [15:0] X0_q = X0[31:16];
wire signed [15:0] X0_i = X0[15:0];
wire signed [15:0] X1_q = X1[31:16];
wire signed [15:0] X1_i = X1[15:0];
wire signed [15:0] X2_q = X2[31:16];
wire signed [15:0] X2_i = X2[15:0];
wire signed [15:0] X3_q = X3[31:16];
wire signed [15:0] X3_i = X3[15:0];
wire signed [15:0] X4_q = X4[31:16];
wire signed [15:0] X4_i = X4[15:0];
wire signed [15:0] X5_q = X5[31:16];
wire signed [15:0] X5_i = X5[15:0];
wire signed [15:0] X6_q = X6[31:16];
wire signed [15:0] X6_i = X6[15:0];
wire signed [15:0] X7_q = X7[31:16];
wire signed [15:0] X7_i = X7[15:0];
wire signed [15:0] Y0_q = Y0[31:16];
wire signed [15:0] Y0_i = Y0[15:0];
wire signed [15:0] Y1_q = Y1[31:16];
wire signed [15:0] Y1_i = Y1[15:0];
wire signed [15:0] Y2_q = Y2[31:16];
wire signed [15:0] Y2_i = Y2[15:0];
wire signed [15:0] Y3_q = Y3[31:16];
wire signed [15:0] Y3_i = Y3[15:0];
wire signed [15:0] Y4_q = Y4[31:16];
wire signed [15:0] Y4_i = Y4[15:0];
wire signed [15:0] Y5_q = Y5[31:16];
wire signed [15:0] Y5_i = Y5[15:0];
wire signed [15:0] Y6_q = Y6[31:16];
wire signed [15:0] Y6_i = Y6[15:0];
wire signed [15:0] Y7_q = Y7[31:16];
wire signed [15:0] Y7_i = Y7[15:0];
wire signed [31:0] prod_0_i;
wire signed [31:0] prod_0_q;
wire signed [31:0] prod_1_i;
wire signed [31:0] prod_1_q;
wire signed [31:0] prod_2_i;
wire signed [31:0] prod_2_q;
wire signed [31:0] prod_3_i;
wire signed [31:0] prod_3_q;
wire signed [31:0] prod_4_i;
wire signed [31:0] prod_4_q;
wire signed [31:0] prod_5_i;
wire signed [31:0] prod_5_q;
wire signed [31:0] prod_6_i;
wire signed [31:0] prod_6_q;
wire signed [31:0] prod_7_i;
wire signed [31:0] prod_7_q;
complex_multiplier mult_inst1 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X0_i,X0_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y0_i,Y0_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_0_q,prod_0_i})
);
complex_multiplier mult_inst2 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X1_i,X1_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y1_i,Y1_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_1_q,prod_1_i})
);
complex_multiplier mult_inst3 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X2_i,X2_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y2_i,Y2_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_2_q,prod_2_i})
);
complex_multiplier mult_inst4 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X3_i,X3_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y3_i,Y3_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_3_q,prod_3_i})
);
complex_multiplier mult_inst5 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X4_i,X4_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y4_i,Y4_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_4_q,prod_4_i})
);
complex_multiplier mult_inst6 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X5_i,X5_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y5_i,Y5_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_5_q,prod_5_i})
);
complex_multiplier mult_inst7 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X6_i,X6_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y6_i,Y6_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_6_q,prod_6_i})
);
complex_multiplier mult_inst8 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X7_i,X7_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y7_i,Y7_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_7_q,prod_7_i})
);
reg signed [31:0] sum_i1;
reg signed [31:0] sum_i2;
reg signed [31:0] sum_i3;
reg signed [31:0] sum_i4;
reg signed [31:0] sum_q1;
reg signed [31:0] sum_q2;
reg signed [31:0] sum_q3;
reg signed [31:0] sum_q4;
delayT #(.DATA_WIDTH(1), .DELAY(5)) sum_delay_inst (
.clock(clock),
.reset(reset),
.data_in(input_strobe),
.data_out(output_strobe)
);
always @(posedge clock) begin
if (reset) begin
sum <= 0;
sum_i1 <= 0;
sum_i2 <= 0;
sum_i3 <= 0;
sum_i4 <= 0;
sum_q1 <= 0;
sum_q2 <= 0;
sum_q3 <= 0;
sum_q4 <= 0;
end else if (enable) begin
sum_i1 <= prod_0_i + prod_1_i;
sum_i2 <= prod_2_i + prod_3_i;
sum_i3 <= prod_4_i + prod_5_i;
sum_i4 <= prod_6_i + prod_7_i;
sum_q1 <= prod_0_q + prod_1_q;
sum_q2 <= prod_2_q + prod_3_q;
sum_q3 <= prod_4_q + prod_5_q;
sum_q4 <= prod_6_q + prod_7_q;
sum[63:32] <= sum_i1 + sum_i2 + sum_i3 + sum_i4;
sum[31:0] <= sum_q1 + sum_q2 + sum_q3 + sum_q4;
end
end
endmodule | 230 |
139,739 | data/full_repos/permissive/89524778/sim/ascii_4_ints_tb.v | 89,524,778 | ascii_4_ints_tb.v | v | 45 | 37 | [] | [] | [] | [(3, 44)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/89524778/sim/ascii_4_ints_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #50 tb_clk <= ~tb_clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/89524778/sim/ascii_4_ints_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n #100 tb_next <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/89524778/sim/ascii_4_ints_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #10 tb_next <= 1\'b0;\n ^\n%Error: data/full_repos/permissive/89524778/sim/ascii_4_ints_tb.v:15: Cannot find file containing module: \'ascii_4_ints\'\nascii_4_ints ai4i(\n^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89524778/sim,data/full_repos/permissive/89524778/ascii_4_ints\n data/full_repos/permissive/89524778/sim,data/full_repos/permissive/89524778/ascii_4_ints.v\n data/full_repos/permissive/89524778/sim,data/full_repos/permissive/89524778/ascii_4_ints.sv\n ascii_4_ints\n ascii_4_ints.v\n ascii_4_ints.sv\n obj_dir/ascii_4_ints\n obj_dir/ascii_4_ints.v\n obj_dir/ascii_4_ints.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 307,779 | module | module ascii_4_ints_tb();
reg tb_clk;
reg tb_rst;
reg tb_next;
wire tb_overflow;
wire [7:0] tb_value_0;
wire [7:0] tb_value_1;
wire [7:0] tb_value_2;
wire [7:0] tb_value_3;
ascii_4_ints ai4i(
.rst(tb_rst),
.next(tb_next),
.overflow(tb_overflow),
.value0(tb_value_0),
.value1(tb_value_1),
.value2(tb_value_2),
.value3(tb_value_3)
);
initial
begin
tb_clk <= 1'b0;
tb_rst <= 1'b0;
tb_next <= 1'b0;
end
always
begin
#50 tb_clk <= ~tb_clk;
end
always
begin
#100 tb_next <= 1'b1;
#10 tb_next <= 1'b0;
end
endmodule | module ascii_4_ints_tb(); |
reg tb_clk;
reg tb_rst;
reg tb_next;
wire tb_overflow;
wire [7:0] tb_value_0;
wire [7:0] tb_value_1;
wire [7:0] tb_value_2;
wire [7:0] tb_value_3;
ascii_4_ints ai4i(
.rst(tb_rst),
.next(tb_next),
.overflow(tb_overflow),
.value0(tb_value_0),
.value1(tb_value_1),
.value2(tb_value_2),
.value3(tb_value_3)
);
initial
begin
tb_clk <= 1'b0;
tb_rst <= 1'b0;
tb_next <= 1'b0;
end
always
begin
#50 tb_clk <= ~tb_clk;
end
always
begin
#100 tb_next <= 1'b1;
#10 tb_next <= 1'b0;
end
endmodule | 0 |
139,740 | data/full_repos/permissive/89524778/sim/ascii_int_tb.v | 89,524,778 | ascii_int_tb.v | v | 72 | 37 | [] | [] | [] | [(3, 71)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/89524778/sim/ascii_int_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #50 tb_clk <= ~tb_clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/89524778/sim/ascii_int_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n #100 tb_next_0 <= 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/89524778/sim/ascii_int_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #10 tb_next_0 <= 1\'b0;\n ^\n%Warning-IMPLICIT: data/full_repos/permissive/89524778/sim/ascii_int_tb.v:19: Signal definition not found, creating implicitly: \'tb_next_1\'\n : ... Suggested alternative: \'tb_next_0\'\nassign tb_next_1 = tb_overflow_0;\n ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89524778/sim/ascii_int_tb.v:30: Signal definition not found, creating implicitly: \'tb_next_2\'\n : ... Suggested alternative: \'tb_next_0\'\nassign tb_next_2 = tb_overflow_1;\n ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89524778/sim/ascii_int_tb.v:41: Signal definition not found, creating implicitly: \'tb_next_3\'\n : ... Suggested alternative: \'tb_next_0\'\nassign tb_next_3 = tb_overflow_2;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/89524778/sim/ascii_int_tb.v:12: Cannot find file containing module: \'ascii_int\'\nascii_int aii_0(\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89524778/sim,data/full_repos/permissive/89524778/ascii_int\n data/full_repos/permissive/89524778/sim,data/full_repos/permissive/89524778/ascii_int.v\n data/full_repos/permissive/89524778/sim,data/full_repos/permissive/89524778/ascii_int.sv\n ascii_int\n ascii_int.v\n ascii_int.sv\n obj_dir/ascii_int\n obj_dir/ascii_int.v\n obj_dir/ascii_int.sv\n%Error: data/full_repos/permissive/89524778/sim/ascii_int_tb.v:23: Cannot find file containing module: \'ascii_int\'\nascii_int aii_1(\n^~~~~~~~~\n%Error: data/full_repos/permissive/89524778/sim/ascii_int_tb.v:34: Cannot find file containing module: \'ascii_int\'\nascii_int aii_2(\n^~~~~~~~~\n%Error: data/full_repos/permissive/89524778/sim/ascii_int_tb.v:45: Cannot find file containing module: \'ascii_int\'\nascii_int aii_3(\n^~~~~~~~~\n%Error: Exiting due to 4 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 307,780 | module | module ascii_int_tb();
reg tb_clk;
reg tb_rst;
reg tb_next_0;
wire tb_overflow_0;
wire [7:0] tb_value_0;
ascii_int aii_0(
.rst(tb_rst),
.next(tb_next_0),
.overflow(tb_overflow_0),
.value(tb_value_0)
);
assign tb_next_1 = tb_overflow_0;
wire tb_overflow_1;
wire [7:0] tb_value_1;
ascii_int aii_1(
.rst(tb_rst),
.next(tb_next_1),
.overflow(tb_overflow_1),
.value(tb_value_1)
);
assign tb_next_2 = tb_overflow_1;
wire tb_overflow_2;
wire [7:0] tb_value_2;
ascii_int aii_2(
.rst(tb_rst),
.next(tb_next_2),
.overflow(tb_overflow_2),
.value(tb_value_2)
);
assign tb_next_3 = tb_overflow_2;
wire tb_overflow_3;
wire [7:0] tb_value_3;
ascii_int aii_3(
.rst(tb_rst),
.next(tb_next_3),
.overflow(tb_overflow_3),
.value(tb_value_3)
);
initial
begin
tb_clk <= 1'b0;
tb_rst <= 1'b0;
tb_next_0 <= 1'b0;
end
always
begin
#50 tb_clk <= ~tb_clk;
end
always
begin
#100 tb_next_0 <= 1'b1;
#10 tb_next_0 <= 1'b0;
end
endmodule | module ascii_int_tb(); |
reg tb_clk;
reg tb_rst;
reg tb_next_0;
wire tb_overflow_0;
wire [7:0] tb_value_0;
ascii_int aii_0(
.rst(tb_rst),
.next(tb_next_0),
.overflow(tb_overflow_0),
.value(tb_value_0)
);
assign tb_next_1 = tb_overflow_0;
wire tb_overflow_1;
wire [7:0] tb_value_1;
ascii_int aii_1(
.rst(tb_rst),
.next(tb_next_1),
.overflow(tb_overflow_1),
.value(tb_value_1)
);
assign tb_next_2 = tb_overflow_1;
wire tb_overflow_2;
wire [7:0] tb_value_2;
ascii_int aii_2(
.rst(tb_rst),
.next(tb_next_2),
.overflow(tb_overflow_2),
.value(tb_value_2)
);
assign tb_next_3 = tb_overflow_2;
wire tb_overflow_3;
wire [7:0] tb_value_3;
ascii_int aii_3(
.rst(tb_rst),
.next(tb_next_3),
.overflow(tb_overflow_3),
.value(tb_value_3)
);
initial
begin
tb_clk <= 1'b0;
tb_rst <= 1'b0;
tb_next_0 <= 1'b0;
end
always
begin
#50 tb_clk <= ~tb_clk;
end
always
begin
#100 tb_next_0 <= 1'b1;
#10 tb_next_0 <= 1'b0;
end
endmodule | 0 |
139,741 | data/full_repos/permissive/89524778/src/ascii_4_ints.v | 89,524,778 | ascii_4_ints.v | v | 67 | 37 | [] | [] | [] | null | line:5: before: "=" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89524778/src/ascii_4_ints.v:22: Signal definition not found, creating implicitly: \'next_1\'\n : ... Suggested alternative: \'next\'\nassign next_1 = overflow_0;\n ^~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/89524778/src/ascii_4_ints.v:33: Signal definition not found, creating implicitly: \'next_2\'\n : ... Suggested alternative: \'next_1\'\nassign next_2 = overflow_1;\n ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89524778/src/ascii_4_ints.v:44: Signal definition not found, creating implicitly: \'next_3\'\n : ... Suggested alternative: \'next_1\'\nassign next_3 = overflow_2;\n ^~~~~~\n%Error: data/full_repos/permissive/89524778/src/ascii_4_ints.v:15: Cannot find file containing module: \'ascii_int\'\nascii_int aii_0(\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89524778/src,data/full_repos/permissive/89524778/ascii_int\n data/full_repos/permissive/89524778/src,data/full_repos/permissive/89524778/ascii_int.v\n data/full_repos/permissive/89524778/src,data/full_repos/permissive/89524778/ascii_int.sv\n ascii_int\n ascii_int.v\n ascii_int.sv\n obj_dir/ascii_int\n obj_dir/ascii_int.v\n obj_dir/ascii_int.sv\n%Error: data/full_repos/permissive/89524778/src/ascii_4_ints.v:26: Cannot find file containing module: \'ascii_int\'\nascii_int aii_1(\n^~~~~~~~~\n%Error: data/full_repos/permissive/89524778/src/ascii_4_ints.v:37: Cannot find file containing module: \'ascii_int\'\nascii_int aii_2(\n^~~~~~~~~\n%Error: data/full_repos/permissive/89524778/src/ascii_4_ints.v:48: Cannot find file containing module: \'ascii_int\'\nascii_int aii_3(\n^~~~~~~~~\n%Error: Exiting due to 4 error(s), 3 warning(s)\n' | 307,781 | module | module ascii_4_ints (
input wire rst,
input wire next,
output reg overflow = 1'b0,
output reg [7:0] value0 = 8'h30,
output reg [7:0] value1 = 8'h30,
output reg [7:0] value2 = 8'h30,
output reg [7:0] value3 = 8'h30
);
wire overflow_0;
wire [7:0] value_0;
ascii_int aii_0(
.rst(rst),
.next(next),
.overflow(overflow_0),
.value(value_0)
);
assign next_1 = overflow_0;
wire overflow_1;
wire [7:0] value_1;
ascii_int aii_1(
.rst(rst),
.next(next_1),
.overflow(overflow_1),
.value(value_1)
);
assign next_2 = overflow_1;
wire overflow_2;
wire [7:0] value_2;
ascii_int aii_2(
.rst(rst),
.next(next_2),
.overflow(overflow_2),
.value(value_2)
);
assign next_3 = overflow_2;
wire overflow_3;
wire [7:0] value_3;
ascii_int aii_3(
.rst(rst),
.next(next_3),
.overflow(overflow_3),
.value(value_3)
);
always @(posedge next)
begin
overflow <= overflow_3;
value0 <= value_0;
value1 <= value_1;
value2 <= value_2;
value3 <= value_3;
end
endmodule | module ascii_4_ints (
input wire rst,
input wire next,
output reg overflow = 1'b0,
output reg [7:0] value0 = 8'h30,
output reg [7:0] value1 = 8'h30,
output reg [7:0] value2 = 8'h30,
output reg [7:0] value3 = 8'h30
); |
wire overflow_0;
wire [7:0] value_0;
ascii_int aii_0(
.rst(rst),
.next(next),
.overflow(overflow_0),
.value(value_0)
);
assign next_1 = overflow_0;
wire overflow_1;
wire [7:0] value_1;
ascii_int aii_1(
.rst(rst),
.next(next_1),
.overflow(overflow_1),
.value(value_1)
);
assign next_2 = overflow_1;
wire overflow_2;
wire [7:0] value_2;
ascii_int aii_2(
.rst(rst),
.next(next_2),
.overflow(overflow_2),
.value(value_2)
);
assign next_3 = overflow_2;
wire overflow_3;
wire [7:0] value_3;
ascii_int aii_3(
.rst(rst),
.next(next_3),
.overflow(overflow_3),
.value(value_3)
);
always @(posedge next)
begin
overflow <= overflow_3;
value0 <= value_0;
value1 <= value_1;
value2 <= value_2;
value3 <= value_3;
end
endmodule | 0 |
139,742 | data/full_repos/permissive/89524778/src/ascii_int.v | 89,524,778 | ascii_int.v | v | 37 | 39 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/e8ebf308-9ab9-4a26-9530-eaa9aebb8df6.xml | null | 307,782 | module | module ascii_int (
input wire rst,
input wire next,
output reg overflow = 1'b0,
output reg [7:0] value = 8'h30
);
always @(posedge next)
begin
overflow <= overflow;
value <= value;
if (rst)
begin
value <= 8'h30;
end
else
begin
if (next)
begin
if (value == 8'h39)
begin
value <= 8'h30;
overflow <= 1'b1;
end
else
begin
value <= value + 8'h1;
overflow <= 1'b0;
end
end
end
end
endmodule | module ascii_int (
input wire rst,
input wire next,
output reg overflow = 1'b0,
output reg [7:0] value = 8'h30
); |
always @(posedge next)
begin
overflow <= overflow;
value <= value;
if (rst)
begin
value <= 8'h30;
end
else
begin
if (next)
begin
if (value == 8'h39)
begin
value <= 8'h30;
overflow <= 1'b1;
end
else
begin
value <= value + 8'h1;
overflow <= 1'b0;
end
end
end
end
endmodule | 0 |
139,743 | data/full_repos/permissive/89699825/single_cycle_cpu/mips_cpu_fpga.v | 89,699,825 | mips_cpu_fpga.v | v | 166 | 67 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/89699825/single_cycle_cpu/mips_cpu_fpga.v:83: Cannot find file containing module: 'zynq_soc_wrapper'\n zynq_soc_wrapper u_zynq_soc_wrapper (\n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89699825/single_cycle_cpu,data/full_repos/permissive/89699825/zynq_soc_wrapper\n data/full_repos/permissive/89699825/single_cycle_cpu,data/full_repos/permissive/89699825/zynq_soc_wrapper.v\n data/full_repos/permissive/89699825/single_cycle_cpu,data/full_repos/permissive/89699825/zynq_soc_wrapper.sv\n zynq_soc_wrapper\n zynq_soc_wrapper.v\n zynq_soc_wrapper.sv\n obj_dir/zynq_soc_wrapper\n obj_dir/zynq_soc_wrapper.v\n obj_dir/zynq_soc_wrapper.sv\n%Error: data/full_repos/permissive/89699825/single_cycle_cpu/mips_cpu_fpga.v:141: Cannot find file containing module: 'mips_cpu_top'\n mips_cpu_top u_mips_cpu_top (\n ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 307,783 | module | module mips_cpu_fpga (
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb
);
inout [14:0] DDR_addr;
inout [2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0] DDR_dm;
inout [31:0] DDR_dq;
inout [3:0] DDR_dqs_n;
inout [3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire mips_cpu_clk;
reg [1:0] mips_cpu_reset_n_i = 2'b00;
wire mips_cpu_reset_n;
wire ps_user_reset_n;
wire [31:0] mips_cpu_axi_if_araddr;
wire mips_cpu_axi_if_arready;
wire mips_cpu_axi_if_arvalid;
wire [31:0] mips_cpu_axi_if_awaddr;
wire mips_cpu_axi_if_awready;
wire mips_cpu_axi_if_awvalid;
wire mips_cpu_axi_if_bready;
wire [1:0] mips_cpu_axi_if_bresp;
wire mips_cpu_axi_if_bvalid;
wire [31:0] mips_cpu_axi_if_rdata;
wire mips_cpu_axi_if_rready;
wire [1:0] mips_cpu_axi_if_rresp;
wire mips_cpu_axi_if_rvalid;
wire [31:0] mips_cpu_axi_if_wdata;
wire mips_cpu_axi_if_wready;
wire [3:0] mips_cpu_axi_if_wstrb;
wire mips_cpu_axi_if_wvalid;
zynq_soc_wrapper u_zynq_soc_wrapper (
.DDR_addr (DDR_addr[14:0]),
.DDR_ba (DDR_ba[2:0]),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm[3:0]),
.DDR_dq (DDR_dq[31:0]),
.DDR_dqs_p (DDR_dqs_p[3:0]),
.DDR_dqs_n (DDR_dqs_n[3:0]),
.DDR_reset_n (DDR_reset_n),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio[53:0]),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk ),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.mips_cpu_axi_if_araddr (mips_cpu_axi_if_araddr),
.mips_cpu_axi_if_arprot (),
.mips_cpu_axi_if_arready (mips_cpu_axi_if_arready),
.mips_cpu_axi_if_arvalid (mips_cpu_axi_if_arvalid),
.mips_cpu_axi_if_awaddr (mips_cpu_axi_if_awaddr),
.mips_cpu_axi_if_awprot (),
.mips_cpu_axi_if_awready (mips_cpu_axi_if_awready),
.mips_cpu_axi_if_awvalid (mips_cpu_axi_if_awvalid),
.mips_cpu_axi_if_bready (mips_cpu_axi_if_bready),
.mips_cpu_axi_if_bresp (mips_cpu_axi_if_bresp),
.mips_cpu_axi_if_bvalid (mips_cpu_axi_if_bvalid),
.mips_cpu_axi_if_rdata (mips_cpu_axi_if_rdata),
.mips_cpu_axi_if_rready (mips_cpu_axi_if_rready),
.mips_cpu_axi_if_rresp (mips_cpu_axi_if_rresp),
.mips_cpu_axi_if_rvalid (mips_cpu_axi_if_rvalid),
.mips_cpu_axi_if_wdata (mips_cpu_axi_if_wdata),
.mips_cpu_axi_if_wready (mips_cpu_axi_if_wready),
.mips_cpu_axi_if_wstrb (mips_cpu_axi_if_wstrb),
.mips_cpu_axi_if_wvalid (mips_cpu_axi_if_wvalid),
.ps_fclk_clk0 (mips_cpu_clk),
.ps_user_reset_n (ps_user_reset_n),
.mips_cpu_reset_n (mips_cpu_reset_n)
);
always @ (posedge mips_cpu_clk)
mips_cpu_reset_n_i <= {mips_cpu_reset_n_i[0], ps_user_reset_n};
assign mips_cpu_reset_n = mips_cpu_reset_n_i[1];
mips_cpu_top u_mips_cpu_top (
.mips_cpu_clk (mips_cpu_clk),
.mips_cpu_reset (~mips_cpu_reset_n),
.mips_cpu_axi_if_araddr (mips_cpu_axi_if_araddr[13:0]),
.mips_cpu_axi_if_arready (mips_cpu_axi_if_arready),
.mips_cpu_axi_if_arvalid (mips_cpu_axi_if_arvalid),
.mips_cpu_axi_if_awaddr (mips_cpu_axi_if_awaddr[13:0]),
.mips_cpu_axi_if_awready (mips_cpu_axi_if_awready),
.mips_cpu_axi_if_awvalid (mips_cpu_axi_if_awvalid),
.mips_cpu_axi_if_bready (mips_cpu_axi_if_bready),
.mips_cpu_axi_if_bresp (mips_cpu_axi_if_bresp),
.mips_cpu_axi_if_bvalid (mips_cpu_axi_if_bvalid),
.mips_cpu_axi_if_rdata (mips_cpu_axi_if_rdata),
.mips_cpu_axi_if_rready (mips_cpu_axi_if_rready),
.mips_cpu_axi_if_rresp (mips_cpu_axi_if_rresp),
.mips_cpu_axi_if_rvalid (mips_cpu_axi_if_rvalid),
.mips_cpu_axi_if_wdata (mips_cpu_axi_if_wdata),
.mips_cpu_axi_if_wready (mips_cpu_axi_if_wready),
.mips_cpu_axi_if_wstrb (mips_cpu_axi_if_wstrb),
.mips_cpu_axi_if_wvalid (mips_cpu_axi_if_wvalid)
);
endmodule | module mips_cpu_fpga (
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb
); |
inout [14:0] DDR_addr;
inout [2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0] DDR_dm;
inout [31:0] DDR_dq;
inout [3:0] DDR_dqs_n;
inout [3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire mips_cpu_clk;
reg [1:0] mips_cpu_reset_n_i = 2'b00;
wire mips_cpu_reset_n;
wire ps_user_reset_n;
wire [31:0] mips_cpu_axi_if_araddr;
wire mips_cpu_axi_if_arready;
wire mips_cpu_axi_if_arvalid;
wire [31:0] mips_cpu_axi_if_awaddr;
wire mips_cpu_axi_if_awready;
wire mips_cpu_axi_if_awvalid;
wire mips_cpu_axi_if_bready;
wire [1:0] mips_cpu_axi_if_bresp;
wire mips_cpu_axi_if_bvalid;
wire [31:0] mips_cpu_axi_if_rdata;
wire mips_cpu_axi_if_rready;
wire [1:0] mips_cpu_axi_if_rresp;
wire mips_cpu_axi_if_rvalid;
wire [31:0] mips_cpu_axi_if_wdata;
wire mips_cpu_axi_if_wready;
wire [3:0] mips_cpu_axi_if_wstrb;
wire mips_cpu_axi_if_wvalid;
zynq_soc_wrapper u_zynq_soc_wrapper (
.DDR_addr (DDR_addr[14:0]),
.DDR_ba (DDR_ba[2:0]),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm[3:0]),
.DDR_dq (DDR_dq[31:0]),
.DDR_dqs_p (DDR_dqs_p[3:0]),
.DDR_dqs_n (DDR_dqs_n[3:0]),
.DDR_reset_n (DDR_reset_n),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio[53:0]),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk ),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.mips_cpu_axi_if_araddr (mips_cpu_axi_if_araddr),
.mips_cpu_axi_if_arprot (),
.mips_cpu_axi_if_arready (mips_cpu_axi_if_arready),
.mips_cpu_axi_if_arvalid (mips_cpu_axi_if_arvalid),
.mips_cpu_axi_if_awaddr (mips_cpu_axi_if_awaddr),
.mips_cpu_axi_if_awprot (),
.mips_cpu_axi_if_awready (mips_cpu_axi_if_awready),
.mips_cpu_axi_if_awvalid (mips_cpu_axi_if_awvalid),
.mips_cpu_axi_if_bready (mips_cpu_axi_if_bready),
.mips_cpu_axi_if_bresp (mips_cpu_axi_if_bresp),
.mips_cpu_axi_if_bvalid (mips_cpu_axi_if_bvalid),
.mips_cpu_axi_if_rdata (mips_cpu_axi_if_rdata),
.mips_cpu_axi_if_rready (mips_cpu_axi_if_rready),
.mips_cpu_axi_if_rresp (mips_cpu_axi_if_rresp),
.mips_cpu_axi_if_rvalid (mips_cpu_axi_if_rvalid),
.mips_cpu_axi_if_wdata (mips_cpu_axi_if_wdata),
.mips_cpu_axi_if_wready (mips_cpu_axi_if_wready),
.mips_cpu_axi_if_wstrb (mips_cpu_axi_if_wstrb),
.mips_cpu_axi_if_wvalid (mips_cpu_axi_if_wvalid),
.ps_fclk_clk0 (mips_cpu_clk),
.ps_user_reset_n (ps_user_reset_n),
.mips_cpu_reset_n (mips_cpu_reset_n)
);
always @ (posedge mips_cpu_clk)
mips_cpu_reset_n_i <= {mips_cpu_reset_n_i[0], ps_user_reset_n};
assign mips_cpu_reset_n = mips_cpu_reset_n_i[1];
mips_cpu_top u_mips_cpu_top (
.mips_cpu_clk (mips_cpu_clk),
.mips_cpu_reset (~mips_cpu_reset_n),
.mips_cpu_axi_if_araddr (mips_cpu_axi_if_araddr[13:0]),
.mips_cpu_axi_if_arready (mips_cpu_axi_if_arready),
.mips_cpu_axi_if_arvalid (mips_cpu_axi_if_arvalid),
.mips_cpu_axi_if_awaddr (mips_cpu_axi_if_awaddr[13:0]),
.mips_cpu_axi_if_awready (mips_cpu_axi_if_awready),
.mips_cpu_axi_if_awvalid (mips_cpu_axi_if_awvalid),
.mips_cpu_axi_if_bready (mips_cpu_axi_if_bready),
.mips_cpu_axi_if_bresp (mips_cpu_axi_if_bresp),
.mips_cpu_axi_if_bvalid (mips_cpu_axi_if_bvalid),
.mips_cpu_axi_if_rdata (mips_cpu_axi_if_rdata),
.mips_cpu_axi_if_rready (mips_cpu_axi_if_rready),
.mips_cpu_axi_if_rresp (mips_cpu_axi_if_rresp),
.mips_cpu_axi_if_rvalid (mips_cpu_axi_if_rvalid),
.mips_cpu_axi_if_wdata (mips_cpu_axi_if_wdata),
.mips_cpu_axi_if_wready (mips_cpu_axi_if_wready),
.mips_cpu_axi_if_wstrb (mips_cpu_axi_if_wstrb),
.mips_cpu_axi_if_wvalid (mips_cpu_axi_if_wvalid)
);
endmodule | 0 |
139,744 | data/full_repos/permissive/89699825/single_cycle_cpu/mips_core/alu.v | 89,699,825 | alu.v | v | 59 | 93 | [] | [] | [] | [(8, 42)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/89699825/single_cycle_cpu/mips_core/alu.v:29: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'OF\' generates 1 bits.\n : ... In instance alu\n 3\'b111: Result<=OF;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/89699825/single_cycle_cpu/mips_core/alu.v:37: Operator ADD expects 34 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance alu\n assign {CF, OF, Result_PLUS}={A[32-1], A}+{B_OP[32-1], B_OP}+ALUop[2];\n ^\n%Error: Exiting due to 2 warning(s)\n' | 307,785 | module | module alu(
input [`DATA_WIDTH - 1:0] A,
input [`DATA_WIDTH - 1:0] B,
input [2:0] ALUop,
output Overflow,
output CarryOut,
output Zero,
output reg [`DATA_WIDTH - 1:0] Result
);
wire OF, CF;
wire [`DATA_WIDTH - 1:0] B_OP, Result_AND, Result_OR, Result_PLUS;
always@(*)
begin
case(ALUop)
3'b000: Result<=Result_AND;
3'b001: Result<=Result_OR;
3'b010, 3'b110: Result<=Result_PLUS;
3'b111: Result<=OF;
default: Result<=`DATA_WIDTH'b0;
endcase
end
assign Result_AND=A&B;
assign Result_OR=A|B;
assign B_OP=B^{`DATA_WIDTH{ALUop[2]}};
assign {CF, OF, Result_PLUS}={A[`DATA_WIDTH-1], A}+{B_OP[`DATA_WIDTH-1], B_OP}+ALUop[2];
assign Overflow=OF^Result_PLUS[`DATA_WIDTH-1];
assign CarryOut=CF^ALUop[2];
assign Zero=~|Result_PLUS;
endmodule | module alu(
input [`DATA_WIDTH - 1:0] A,
input [`DATA_WIDTH - 1:0] B,
input [2:0] ALUop,
output Overflow,
output CarryOut,
output Zero,
output reg [`DATA_WIDTH - 1:0] Result
); |
wire OF, CF;
wire [`DATA_WIDTH - 1:0] B_OP, Result_AND, Result_OR, Result_PLUS;
always@(*)
begin
case(ALUop)
3'b000: Result<=Result_AND;
3'b001: Result<=Result_OR;
3'b010, 3'b110: Result<=Result_PLUS;
3'b111: Result<=OF;
default: Result<=`DATA_WIDTH'b0;
endcase
end
assign Result_AND=A&B;
assign Result_OR=A|B;
assign B_OP=B^{`DATA_WIDTH{ALUop[2]}};
assign {CF, OF, Result_PLUS}={A[`DATA_WIDTH-1], A}+{B_OP[`DATA_WIDTH-1], B_OP}+ALUop[2];
assign Overflow=OF^Result_PLUS[`DATA_WIDTH-1];
assign CarryOut=CF^ALUop[2];
assign Zero=~|Result_PLUS;
endmodule | 0 |
139,745 | data/full_repos/permissive/89699825/single_cycle_cpu/mips_core/mips_cpu.v | 89,699,825 | mips_cpu.v | v | 149 | 274 | [] | [] | [] | [(1, 80), (82, 111), (113, 128), (130, 148)] | null | null | 1: b"%Error: data/full_repos/permissive/89699825/single_cycle_cpu/mips_core/mips_cpu.v:49: Cannot find file containing module: 'alu'\n alu alu_i(.A(alu_in_A), .B(alu_in_B), .ALUop(alu_in_ALUop), .Overflow(alu_out_Overflow), .CarryOut(alu_out_CarryOut), .Zero(alu_out_Zero), .Result(alu_out_Result));\n ^~~\n ... Looked in:\n data/full_repos/permissive/89699825/single_cycle_cpu/mips_core,data/full_repos/permissive/89699825/alu\n data/full_repos/permissive/89699825/single_cycle_cpu/mips_core,data/full_repos/permissive/89699825/alu.v\n data/full_repos/permissive/89699825/single_cycle_cpu/mips_core,data/full_repos/permissive/89699825/alu.sv\n alu\n alu.v\n alu.sv\n obj_dir/alu\n obj_dir/alu.v\n obj_dir/alu.sv\n%Error: data/full_repos/permissive/89699825/single_cycle_cpu/mips_core/mips_cpu.v:50: Cannot find file containing module: 'reg_file'\n reg_file rf_i(.rst(rst), .clk(clk), .waddr(rf_in_waddr), .raddr1(rf_in_raddr1), .raddr2(rf_in_raddr2), .wen(rf_in_wen), .wdata(rf_in_wdata), .rdata1(rf_out_rdata1), .rdata2(rf_out_rdata2));\n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 307,786 | module | module mips_cpu(
input rst,
input clk,
output reg [31:0] PC,
input [31:0] Instruction,
output [31:0] Address,
output MemWrite,
output [31:0] Write_data,
input [31:0] Read_data,
output MemRead
);
wire [31:0] alu_in_A, alu_in_B;
wire [2:0] alu_in_ALUop;
wire alu_out_Overflow, alu_out_CarryOut, alu_out_Zero;
wire [31:0] alu_out_Result;
wire [4:0] rf_in_waddr, rf_in_raddr1, rf_in_raddr2;
wire rf_in_wen;
wire [31:0] rf_in_wdata;
wire [31:0] rf_out_rdata1, rf_out_rdata2;
wire [5:0] cu_in_Opcode;
wire cu_out_RegDst, cu_out_ALUSrc, cu_out_MemtoReg, cu_out_RegWrite, cu_out_MemRead, cu_out_MemWrite, cu_out_Branch, cu_out_ALUop1, cu_out_ALUop0;
wire [5:0] ac_in_Funct;
wire ac_in_ALUop1, ac_in_ALUop0;
wire [2:0] ac_out_ALUop;
wire [5:0] bc_in_Opcode;
wire [31:0] bc_in_ALUResult;
wire bc_in_Overflow, bc_in_CarryOut, bc_in_Zero;
wire bc_out_Result;
wire [31:0] PC_next;
wire [31:0] Sign_extend;
always @(posedge clk)
if(rst)
PC<=0;
else
PC<=PC_next;
alu alu_i(.A(alu_in_A), .B(alu_in_B), .ALUop(alu_in_ALUop), .Overflow(alu_out_Overflow), .CarryOut(alu_out_CarryOut), .Zero(alu_out_Zero), .Result(alu_out_Result));
reg_file rf_i(.rst(rst), .clk(clk), .waddr(rf_in_waddr), .raddr1(rf_in_raddr1), .raddr2(rf_in_raddr2), .wen(rf_in_wen), .wdata(rf_in_wdata), .rdata1(rf_out_rdata1), .rdata2(rf_out_rdata2));
control_unit cu(.Opcode(cu_in_Opcode), .RegDst(cu_out_RegDst), .ALUSrc(cu_out_ALUSrc), .MemtoReg(cu_out_MemtoReg), .RegWrite(cu_out_RegWrite), .MemRead(cu_out_MemRead), .MemWrite(cu_out_MemWrite), .Branch(cu_out_Branch), .ALUop1(cu_out_ALUop1), .ALUop0(cu_out_ALUop0));
alu_control ac(.Funct(ac_in_Funct), .ALUop1(ac_in_ALUop1), .ALUop0(ac_in_ALUop0), .ALUop(ac_out_ALUop));
branch_control bc(.Opcode(bc_in_Opcode), .ALUResult(bc_in_ALUResult), .Overflow(bc_in_Overflow), .CarryOut(bc_in_CarryOut), .Zero(bc_in_Zero), .BranchResult(bc_out_Result));
assign cu_in_Opcode=Instruction[31:26];
assign rf_in_raddr1=Instruction[25:21];
assign rf_in_raddr2=Instruction[20:16];
assign rf_in_waddr=cu_out_RegDst?Instruction[15:11]:Instruction[20:16];
assign rf_in_wdata=cu_out_MemtoReg?Read_data:alu_out_Result;
assign rf_in_wen=cu_out_RegWrite;
assign alu_in_A=rf_out_rdata1;
assign alu_in_B=cu_out_ALUSrc?Sign_extend:rf_out_rdata2;
assign alu_in_ALUop=ac_out_ALUop;
assign ac_in_Funct=Instruction[5:0];
assign ac_in_ALUop1=cu_out_ALUop1;
assign ac_in_ALUop0=cu_out_ALUop0;
assign bc_in_Opcode=Instruction[31:26];
assign bc_in_ALUResult=alu_out_Result;
assign bc_in_Overflow=alu_out_Overflow;
assign bc_in_CarryOut=alu_out_CarryOut;
assign bc_in_Zero=alu_out_Zero;
assign Sign_extend={{16{Instruction[15]}}, Instruction[15:0]};
assign PC_next=(cu_out_Branch&&bc_out_Result)?PC+32'd4+(Sign_extend<<2):PC+32'd4;
assign Address=alu_out_Result;
assign MemWrite=cu_out_MemWrite;
assign Write_data=rf_out_rdata2;
assign MemRead=cu_out_MemRead;
endmodule | module mips_cpu(
input rst,
input clk,
output reg [31:0] PC,
input [31:0] Instruction,
output [31:0] Address,
output MemWrite,
output [31:0] Write_data,
input [31:0] Read_data,
output MemRead
); |
wire [31:0] alu_in_A, alu_in_B;
wire [2:0] alu_in_ALUop;
wire alu_out_Overflow, alu_out_CarryOut, alu_out_Zero;
wire [31:0] alu_out_Result;
wire [4:0] rf_in_waddr, rf_in_raddr1, rf_in_raddr2;
wire rf_in_wen;
wire [31:0] rf_in_wdata;
wire [31:0] rf_out_rdata1, rf_out_rdata2;
wire [5:0] cu_in_Opcode;
wire cu_out_RegDst, cu_out_ALUSrc, cu_out_MemtoReg, cu_out_RegWrite, cu_out_MemRead, cu_out_MemWrite, cu_out_Branch, cu_out_ALUop1, cu_out_ALUop0;
wire [5:0] ac_in_Funct;
wire ac_in_ALUop1, ac_in_ALUop0;
wire [2:0] ac_out_ALUop;
wire [5:0] bc_in_Opcode;
wire [31:0] bc_in_ALUResult;
wire bc_in_Overflow, bc_in_CarryOut, bc_in_Zero;
wire bc_out_Result;
wire [31:0] PC_next;
wire [31:0] Sign_extend;
always @(posedge clk)
if(rst)
PC<=0;
else
PC<=PC_next;
alu alu_i(.A(alu_in_A), .B(alu_in_B), .ALUop(alu_in_ALUop), .Overflow(alu_out_Overflow), .CarryOut(alu_out_CarryOut), .Zero(alu_out_Zero), .Result(alu_out_Result));
reg_file rf_i(.rst(rst), .clk(clk), .waddr(rf_in_waddr), .raddr1(rf_in_raddr1), .raddr2(rf_in_raddr2), .wen(rf_in_wen), .wdata(rf_in_wdata), .rdata1(rf_out_rdata1), .rdata2(rf_out_rdata2));
control_unit cu(.Opcode(cu_in_Opcode), .RegDst(cu_out_RegDst), .ALUSrc(cu_out_ALUSrc), .MemtoReg(cu_out_MemtoReg), .RegWrite(cu_out_RegWrite), .MemRead(cu_out_MemRead), .MemWrite(cu_out_MemWrite), .Branch(cu_out_Branch), .ALUop1(cu_out_ALUop1), .ALUop0(cu_out_ALUop0));
alu_control ac(.Funct(ac_in_Funct), .ALUop1(ac_in_ALUop1), .ALUop0(ac_in_ALUop0), .ALUop(ac_out_ALUop));
branch_control bc(.Opcode(bc_in_Opcode), .ALUResult(bc_in_ALUResult), .Overflow(bc_in_Overflow), .CarryOut(bc_in_CarryOut), .Zero(bc_in_Zero), .BranchResult(bc_out_Result));
assign cu_in_Opcode=Instruction[31:26];
assign rf_in_raddr1=Instruction[25:21];
assign rf_in_raddr2=Instruction[20:16];
assign rf_in_waddr=cu_out_RegDst?Instruction[15:11]:Instruction[20:16];
assign rf_in_wdata=cu_out_MemtoReg?Read_data:alu_out_Result;
assign rf_in_wen=cu_out_RegWrite;
assign alu_in_A=rf_out_rdata1;
assign alu_in_B=cu_out_ALUSrc?Sign_extend:rf_out_rdata2;
assign alu_in_ALUop=ac_out_ALUop;
assign ac_in_Funct=Instruction[5:0];
assign ac_in_ALUop1=cu_out_ALUop1;
assign ac_in_ALUop0=cu_out_ALUop0;
assign bc_in_Opcode=Instruction[31:26];
assign bc_in_ALUResult=alu_out_Result;
assign bc_in_Overflow=alu_out_Overflow;
assign bc_in_CarryOut=alu_out_CarryOut;
assign bc_in_Zero=alu_out_Zero;
assign Sign_extend={{16{Instruction[15]}}, Instruction[15:0]};
assign PC_next=(cu_out_Branch&&bc_out_Result)?PC+32'd4+(Sign_extend<<2):PC+32'd4;
assign Address=alu_out_Result;
assign MemWrite=cu_out_MemWrite;
assign Write_data=rf_out_rdata2;
assign MemRead=cu_out_MemRead;
endmodule | 0 |
139,746 | data/full_repos/permissive/89699825/single_cycle_cpu/mips_core/mips_cpu.v | 89,699,825 | mips_cpu.v | v | 149 | 274 | [] | [] | [] | [(1, 80), (82, 111), (113, 128), (130, 148)] | null | null | 1: b"%Error: data/full_repos/permissive/89699825/single_cycle_cpu/mips_core/mips_cpu.v:49: Cannot find file containing module: 'alu'\n alu alu_i(.A(alu_in_A), .B(alu_in_B), .ALUop(alu_in_ALUop), .Overflow(alu_out_Overflow), .CarryOut(alu_out_CarryOut), .Zero(alu_out_Zero), .Result(alu_out_Result));\n ^~~\n ... Looked in:\n data/full_repos/permissive/89699825/single_cycle_cpu/mips_core,data/full_repos/permissive/89699825/alu\n data/full_repos/permissive/89699825/single_cycle_cpu/mips_core,data/full_repos/permissive/89699825/alu.v\n data/full_repos/permissive/89699825/single_cycle_cpu/mips_core,data/full_repos/permissive/89699825/alu.sv\n alu\n alu.v\n alu.sv\n obj_dir/alu\n obj_dir/alu.v\n obj_dir/alu.sv\n%Error: data/full_repos/permissive/89699825/single_cycle_cpu/mips_core/mips_cpu.v:50: Cannot find file containing module: 'reg_file'\n reg_file rf_i(.rst(rst), .clk(clk), .waddr(rf_in_waddr), .raddr1(rf_in_raddr1), .raddr2(rf_in_raddr2), .wen(rf_in_wen), .wdata(rf_in_wdata), .rdata1(rf_out_rdata1), .rdata2(rf_out_rdata2));\n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 307,786 | module | module control_unit(
input [5:0] Opcode,
output RegDst,
output ALUSrc,
output MemtoReg,
output RegWrite,
output MemRead,
output MemWrite,
output Branch,
output ALUop1,
output ALUop0
);
reg [8:0] CtrlResult;
always@(*)
begin
case(Opcode)
6'b001001: CtrlResult<=9'b010100000;
6'b000000: CtrlResult<=9'b100100010;
6'b100011: CtrlResult<=9'b011110000;
6'b101011: CtrlResult<=9'b010001000;
6'b000100, 6'b000101: CtrlResult<=9'b000000101;
default: CtrlResult<=9'b0;
endcase
end
assign {RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, ALUop1, ALUop0}=CtrlResult;
endmodule | module control_unit(
input [5:0] Opcode,
output RegDst,
output ALUSrc,
output MemtoReg,
output RegWrite,
output MemRead,
output MemWrite,
output Branch,
output ALUop1,
output ALUop0
); |
reg [8:0] CtrlResult;
always@(*)
begin
case(Opcode)
6'b001001: CtrlResult<=9'b010100000;
6'b000000: CtrlResult<=9'b100100010;
6'b100011: CtrlResult<=9'b011110000;
6'b101011: CtrlResult<=9'b010001000;
6'b000100, 6'b000101: CtrlResult<=9'b000000101;
default: CtrlResult<=9'b0;
endcase
end
assign {RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, ALUop1, ALUop0}=CtrlResult;
endmodule | 0 |
139,747 | data/full_repos/permissive/89699825/single_cycle_cpu/mips_core/mips_cpu.v | 89,699,825 | mips_cpu.v | v | 149 | 274 | [] | [] | [] | [(1, 80), (82, 111), (113, 128), (130, 148)] | null | null | 1: b"%Error: data/full_repos/permissive/89699825/single_cycle_cpu/mips_core/mips_cpu.v:49: Cannot find file containing module: 'alu'\n alu alu_i(.A(alu_in_A), .B(alu_in_B), .ALUop(alu_in_ALUop), .Overflow(alu_out_Overflow), .CarryOut(alu_out_CarryOut), .Zero(alu_out_Zero), .Result(alu_out_Result));\n ^~~\n ... Looked in:\n data/full_repos/permissive/89699825/single_cycle_cpu/mips_core,data/full_repos/permissive/89699825/alu\n data/full_repos/permissive/89699825/single_cycle_cpu/mips_core,data/full_repos/permissive/89699825/alu.v\n data/full_repos/permissive/89699825/single_cycle_cpu/mips_core,data/full_repos/permissive/89699825/alu.sv\n alu\n alu.v\n alu.sv\n obj_dir/alu\n obj_dir/alu.v\n obj_dir/alu.sv\n%Error: data/full_repos/permissive/89699825/single_cycle_cpu/mips_core/mips_cpu.v:50: Cannot find file containing module: 'reg_file'\n reg_file rf_i(.rst(rst), .clk(clk), .waddr(rf_in_waddr), .raddr1(rf_in_raddr1), .raddr2(rf_in_raddr2), .wen(rf_in_wen), .wdata(rf_in_wdata), .rdata1(rf_out_rdata1), .rdata2(rf_out_rdata2));\n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 307,786 | module | module alu_control(
input [5:0] Funct,
input ALUop1,
input ALUop0,
output [2:0] ALUop
);
assign ALUop[2]=ALUop0|(ALUop1&Funct[1]);
assign ALUop[1]=(~ALUop1)|(~Funct[2]);
assign ALUop[0]=ALUop1&(Funct[3]|Funct[0]);
endmodule | module alu_control(
input [5:0] Funct,
input ALUop1,
input ALUop0,
output [2:0] ALUop
); |
assign ALUop[2]=ALUop0|(ALUop1&Funct[1]);
assign ALUop[1]=(~ALUop1)|(~Funct[2]);
assign ALUop[0]=ALUop1&(Funct[3]|Funct[0]);
endmodule | 0 |
139,748 | data/full_repos/permissive/89699825/single_cycle_cpu/mips_core/mips_cpu.v | 89,699,825 | mips_cpu.v | v | 149 | 274 | [] | [] | [] | [(1, 80), (82, 111), (113, 128), (130, 148)] | null | null | 1: b"%Error: data/full_repos/permissive/89699825/single_cycle_cpu/mips_core/mips_cpu.v:49: Cannot find file containing module: 'alu'\n alu alu_i(.A(alu_in_A), .B(alu_in_B), .ALUop(alu_in_ALUop), .Overflow(alu_out_Overflow), .CarryOut(alu_out_CarryOut), .Zero(alu_out_Zero), .Result(alu_out_Result));\n ^~~\n ... Looked in:\n data/full_repos/permissive/89699825/single_cycle_cpu/mips_core,data/full_repos/permissive/89699825/alu\n data/full_repos/permissive/89699825/single_cycle_cpu/mips_core,data/full_repos/permissive/89699825/alu.v\n data/full_repos/permissive/89699825/single_cycle_cpu/mips_core,data/full_repos/permissive/89699825/alu.sv\n alu\n alu.v\n alu.sv\n obj_dir/alu\n obj_dir/alu.v\n obj_dir/alu.sv\n%Error: data/full_repos/permissive/89699825/single_cycle_cpu/mips_core/mips_cpu.v:50: Cannot find file containing module: 'reg_file'\n reg_file rf_i(.rst(rst), .clk(clk), .waddr(rf_in_waddr), .raddr1(rf_in_raddr1), .raddr2(rf_in_raddr2), .wen(rf_in_wen), .wdata(rf_in_wdata), .rdata1(rf_out_rdata1), .rdata2(rf_out_rdata2));\n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 307,786 | module | module branch_control(
input [5:0] Opcode,
input [31:0] ALUResult,
input Overflow,
input CarryOut,
input Zero,
output reg BranchResult
);
always@(*)
begin
case(Opcode)
6'b000100: BranchResult<=Zero;
6'b000101: BranchResult<=~Zero;
default: BranchResult<=1'b0;
endcase
end
endmodule | module branch_control(
input [5:0] Opcode,
input [31:0] ALUResult,
input Overflow,
input CarryOut,
input Zero,
output reg BranchResult
); |
always@(*)
begin
case(Opcode)
6'b000100: BranchResult<=Zero;
6'b000101: BranchResult<=~Zero;
default: BranchResult<=1'b0;
endcase
end
endmodule | 0 |
139,749 | data/full_repos/permissive/89699825/single_cycle_cpu/mips_core/reg_file.v | 89,699,825 | reg_file.v | v | 69 | 81 | [] | [] | [] | [(10, 68)] | null | data/verilator_xmls/1acd5c65-bdce-4623-b849-92d3005d33e6.xml | null | 307,787 | module | module reg_file(
input clk,
input rst,
input [`ADDR_WIDTH - 1:0] waddr,
input [`ADDR_WIDTH - 1:0] raddr1,
input [`ADDR_WIDTH - 1:0] raddr2,
input wen,
input [`DATA_WIDTH - 1:0] wdata,
output [`DATA_WIDTH - 1:0] rdata1,
output [`DATA_WIDTH - 1:0] rdata2
);
reg [`DATA_WIDTH - 1:0] mem [0:(1<<`ADDR_WIDTH) - 1];
always@(posedge clk)
begin
if(wen)
mem[waddr]<=wdata;
end
assign rdata1={`DATA_WIDTH{|raddr1}}&mem[raddr1];
assign rdata2={`DATA_WIDTH{|raddr2}}&mem[raddr2];
endmodule | module reg_file(
input clk,
input rst,
input [`ADDR_WIDTH - 1:0] waddr,
input [`ADDR_WIDTH - 1:0] raddr1,
input [`ADDR_WIDTH - 1:0] raddr2,
input wen,
input [`DATA_WIDTH - 1:0] wdata,
output [`DATA_WIDTH - 1:0] rdata1,
output [`DATA_WIDTH - 1:0] rdata2
); |
reg [`DATA_WIDTH - 1:0] mem [0:(1<<`ADDR_WIDTH) - 1];
always@(posedge clk)
begin
if(wen)
mem[waddr]<=wdata;
end
assign rdata1={`DATA_WIDTH{|raddr1}}&mem[raddr1];
assign rdata2={`DATA_WIDTH{|raddr2}}&mem[raddr2];
endmodule | 0 |
139,750 | data/full_repos/permissive/89699825/single_cycle_cpu/mips_core_top/axi_lite_if.v | 89,699,825 | axi_lite_if.v | v | 277 | 87 | [] | [] | [] | [(18, 276)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89699825/single_cycle_cpu/mips_core_top/axi_lite_if.v:146: Signal definition not found, creating implicitly: \'wren\'\n assign wren = ~axi_awready & ~axi_wready & S_AXI_AWVALID & S_AXI_WVALID;\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 307,788 | module | module axi_lite_if (
input wire S_AXI_ACLK,
input wire S_AXI_ARESETN,
input wire [`C_S_AXI_ADDR_WIDTH - 1:0] S_AXI_AWADDR,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire [`C_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [`C_S_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [1:0] S_AXI_BRESP,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [`C_S_AXI_ADDR_WIDTH - 1:0] S_AXI_ARADDR,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [`C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [1:0] S_AXI_RRESP,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
output wire [10:0] Address,
output wire [31:0] Write_data,
output wire MemWrite,
output wire MemRead,
input wire [31:0] Read_data,
output reg mips_rst
);
reg axi_rvalid;
reg [`C_S_AXI_DATA_WIDTH-1:0] axi_rdata;
reg [1:0] axi_rresp;
reg axi_bvalid;
reg [1:0] axi_bresp;
reg axi_awready;
reg axi_wready;
reg axi_arready;
wire [10:0] wr_addr;
wire [10:0] rd_addr;
wire mips_rst_sel;
wire mips_rst_wdata;
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RVALID = axi_rvalid;
assign S_AXI_RRESP = axi_rresp;
always @( posedge S_AXI_ACLK )
begin
if(S_AXI_ARESETN == 1'b0)
axi_awready <= 1'b0;
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
axi_awready <= 1'b1;
else
axi_awready <= 1'b0;
end
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
axi_wready <= 1'b0;
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
axi_wready <= 1'b1;
else
axi_wready <= 1'b0;
end
end
assign wren = ~axi_awready & ~axi_wready & S_AXI_AWVALID & S_AXI_WVALID;
assign MemWrite = ~S_AXI_AWADDR[13] & wren;
assign Write_data = {32{MemWrite}} & S_AXI_WDATA;
assign wr_addr = {11{MemWrite}} & S_AXI_AWADDR[12:2];
assign mips_rst_sel = S_AXI_AWADDR[13] & (~|S_AXI_AWADDR[12:2]) & wren;
assign mips_rst_wdata = ~S_AXI_WDATA[0];
always @( posedge S_AXI_ACLK )
begin
if (S_AXI_ARESETN == 1'b0)
mips_rst <= 1'b1;
else if (mips_rst_sel)
mips_rst <= mips_rst_wdata;
else
mips_rst <= mips_rst;
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0;
end
else
begin
if (S_AXI_BREADY && axi_bvalid)
begin
axi_bvalid <= 1'b0;
end
end
end
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
axi_arready <= 1'b0;
else
begin
if (~axi_arready && S_AXI_ARVALID)
axi_arready <= 1'b1;
else
axi_arready <= 1'b0;
end
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 1'd0;
axi_rresp <= 2'd0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
axi_rvalid <= 1'b1;
axi_rresp <= 2'b00;
end
else if (axi_rvalid && S_AXI_RREADY)
axi_rvalid <= 1'b0;
end
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
axi_rdata <= {`C_S_AXI_DATA_WIDTH{1'b0}};
else if(MemRead)
axi_rdata <= Read_data;
else
axi_rdata <= axi_rdata;
end
assign MemRead = ~S_AXI_ARADDR[13] && ~axi_arready && S_AXI_ARVALID;
assign rd_addr = {11{MemRead}} & S_AXI_ARADDR[12:2];
assign Address = wr_addr | rd_addr;
endmodule | module axi_lite_if (
input wire S_AXI_ACLK,
input wire S_AXI_ARESETN,
input wire [`C_S_AXI_ADDR_WIDTH - 1:0] S_AXI_AWADDR,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire [`C_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [`C_S_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [1:0] S_AXI_BRESP,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [`C_S_AXI_ADDR_WIDTH - 1:0] S_AXI_ARADDR,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [`C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [1:0] S_AXI_RRESP,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
output wire [10:0] Address,
output wire [31:0] Write_data,
output wire MemWrite,
output wire MemRead,
input wire [31:0] Read_data,
output reg mips_rst
); |
reg axi_rvalid;
reg [`C_S_AXI_DATA_WIDTH-1:0] axi_rdata;
reg [1:0] axi_rresp;
reg axi_bvalid;
reg [1:0] axi_bresp;
reg axi_awready;
reg axi_wready;
reg axi_arready;
wire [10:0] wr_addr;
wire [10:0] rd_addr;
wire mips_rst_sel;
wire mips_rst_wdata;
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RVALID = axi_rvalid;
assign S_AXI_RRESP = axi_rresp;
always @( posedge S_AXI_ACLK )
begin
if(S_AXI_ARESETN == 1'b0)
axi_awready <= 1'b0;
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
axi_awready <= 1'b1;
else
axi_awready <= 1'b0;
end
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
axi_wready <= 1'b0;
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
axi_wready <= 1'b1;
else
axi_wready <= 1'b0;
end
end
assign wren = ~axi_awready & ~axi_wready & S_AXI_AWVALID & S_AXI_WVALID;
assign MemWrite = ~S_AXI_AWADDR[13] & wren;
assign Write_data = {32{MemWrite}} & S_AXI_WDATA;
assign wr_addr = {11{MemWrite}} & S_AXI_AWADDR[12:2];
assign mips_rst_sel = S_AXI_AWADDR[13] & (~|S_AXI_AWADDR[12:2]) & wren;
assign mips_rst_wdata = ~S_AXI_WDATA[0];
always @( posedge S_AXI_ACLK )
begin
if (S_AXI_ARESETN == 1'b0)
mips_rst <= 1'b1;
else if (mips_rst_sel)
mips_rst <= mips_rst_wdata;
else
mips_rst <= mips_rst;
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0;
end
else
begin
if (S_AXI_BREADY && axi_bvalid)
begin
axi_bvalid <= 1'b0;
end
end
end
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
axi_arready <= 1'b0;
else
begin
if (~axi_arready && S_AXI_ARVALID)
axi_arready <= 1'b1;
else
axi_arready <= 1'b0;
end
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 1'd0;
axi_rresp <= 2'd0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
axi_rvalid <= 1'b1;
axi_rresp <= 2'b00;
end
else if (axi_rvalid && S_AXI_RREADY)
axi_rvalid <= 1'b0;
end
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
axi_rdata <= {`C_S_AXI_DATA_WIDTH{1'b0}};
else if(MemRead)
axi_rdata <= Read_data;
else
axi_rdata <= axi_rdata;
end
assign MemRead = ~S_AXI_ARADDR[13] && ~axi_arready && S_AXI_ARVALID;
assign rd_addr = {11{MemRead}} & S_AXI_ARADDR[12:2];
assign Address = wr_addr | rd_addr;
endmodule | 0 |
139,751 | data/full_repos/permissive/89699825/single_cycle_cpu/mips_core_top/ideal_mem.v | 89,699,825 | ideal_mem.v | v | 109 | 86 | [] | [] | [] | [(14, 108)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/89699825/single_cycle_cpu/mips_core_top/ideal_mem.v:102: Bit extraction of array[255:0] requires 8 bit index, not 10 bits.\n : ... In instance ideal_mem\n mem[Waddr] <= Wdata;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/89699825/single_cycle_cpu/mips_core_top/ideal_mem.v:105: Bit extraction of array[255:0] requires 8 bit index, not 10 bits.\n : ... In instance ideal_mem\nassign Rdata1 = {32{Rden1}} & mem[Raddr1];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89699825/single_cycle_cpu/mips_core_top/ideal_mem.v:106: Bit extraction of array[255:0] requires 8 bit index, not 10 bits.\n : ... In instance ideal_mem\nassign Rdata2 = {32{Rden2}} & mem[Raddr2];\n ^\n%Error: Exiting due to 3 warning(s)\n' | 307,789 | module | module ideal_mem #(
parameter ADDR_WIDTH = 10,
parameter MEM_WIDTH = 2 ** (ADDR_WIDTH - 2)
) (
input clk,
input [ADDR_WIDTH - 1:0] Waddr,
input [ADDR_WIDTH - 1:0] Raddr1,
input [ADDR_WIDTH - 1:0] Raddr2,
input Wren,
input Rden1,
input Rden2,
input [31:0] Wdata,
output [31:0] Rdata1,
output [31:0] Rdata2
);
reg [31:0] mem [MEM_WIDTH - 1:0];
`define ADDIU(rt, rs, imm) {6'b001001, rs, rt, imm}
`define LW(base, rt, offset) {6'b100011, base, rt, offset}
`define SW(base, rt, offset) {6'b101011, base, rt, offset}
`define BEQ(rs, rt, offset) {6'b000100, rs, rt, offset}
`define BNE(rs, rt, offset) {6'b000101, rs, rt, offset}
`define NOP 32'd0;
`ifdef MIPS_CPU_SIM
initial begin
mem[0] <= 32'h241a0001;
mem[1] <= 32'h17400002;
mem[2] <= 32'h00000000;
mem[3] <= 32'hffffffff;
mem[4] <= 32'h24040000;
mem[5] <= 32'h24050064;
mem[6] <= 32'hac8400c8;
mem[7] <= 32'h24840004;
mem[8] <= 32'h1485fffd;
mem[9] <= 32'h00000000;
mem[10] <= 32'h24040000;
mem[11] <= 32'h8c8600c8;
mem[12] <= 32'hac86012c;
mem[13] <= 32'h24840004;
mem[14] <= 32'h1485fffc;
mem[15] <= 32'h00000000;
mem[16] <= 32'h24040000;
mem[17] <= 32'h8c86012c;
mem[18] <= 32'h14c40007;
mem[19] <= 32'h00000000;
mem[20] <= 32'h24840004;
mem[21] <= 32'h1485fffb;
mem[22] <= 32'h00000000;
mem[23] <= 32'h241a0001;
mem[24] <= 32'h17400005;
mem[25] <= 32'h00000000;
mem[26] <= 32'h24040001;
mem[27] <= 32'h241a0001;
mem[28] <= 32'h17400002;
mem[29] <= 32'h00000000;
mem[30] <= 32'h24040000;
mem[31] <= 32'hac04000c;
mem[32] <= 32'h241a0001;
mem[33] <= 32'h1740fffe;
mem[34] <= 32'h00000000;
end
`endif
always @ (posedge clk)
begin
if (Wren)
mem[Waddr] <= Wdata;
end
assign Rdata1 = {32{Rden1}} & mem[Raddr1];
assign Rdata2 = {32{Rden2}} & mem[Raddr2];
endmodule | module ideal_mem #(
parameter ADDR_WIDTH = 10,
parameter MEM_WIDTH = 2 ** (ADDR_WIDTH - 2)
) (
input clk,
input [ADDR_WIDTH - 1:0] Waddr,
input [ADDR_WIDTH - 1:0] Raddr1,
input [ADDR_WIDTH - 1:0] Raddr2,
input Wren,
input Rden1,
input Rden2,
input [31:0] Wdata,
output [31:0] Rdata1,
output [31:0] Rdata2
); |
reg [31:0] mem [MEM_WIDTH - 1:0];
`define ADDIU(rt, rs, imm) {6'b001001, rs, rt, imm}
`define LW(base, rt, offset) {6'b100011, base, rt, offset}
`define SW(base, rt, offset) {6'b101011, base, rt, offset}
`define BEQ(rs, rt, offset) {6'b000100, rs, rt, offset}
`define BNE(rs, rt, offset) {6'b000101, rs, rt, offset}
`define NOP 32'd0;
`ifdef MIPS_CPU_SIM
initial begin
mem[0] <= 32'h241a0001;
mem[1] <= 32'h17400002;
mem[2] <= 32'h00000000;
mem[3] <= 32'hffffffff;
mem[4] <= 32'h24040000;
mem[5] <= 32'h24050064;
mem[6] <= 32'hac8400c8;
mem[7] <= 32'h24840004;
mem[8] <= 32'h1485fffd;
mem[9] <= 32'h00000000;
mem[10] <= 32'h24040000;
mem[11] <= 32'h8c8600c8;
mem[12] <= 32'hac86012c;
mem[13] <= 32'h24840004;
mem[14] <= 32'h1485fffc;
mem[15] <= 32'h00000000;
mem[16] <= 32'h24040000;
mem[17] <= 32'h8c86012c;
mem[18] <= 32'h14c40007;
mem[19] <= 32'h00000000;
mem[20] <= 32'h24840004;
mem[21] <= 32'h1485fffb;
mem[22] <= 32'h00000000;
mem[23] <= 32'h241a0001;
mem[24] <= 32'h17400005;
mem[25] <= 32'h00000000;
mem[26] <= 32'h24040001;
mem[27] <= 32'h241a0001;
mem[28] <= 32'h17400002;
mem[29] <= 32'h00000000;
mem[30] <= 32'h24040000;
mem[31] <= 32'hac04000c;
mem[32] <= 32'h241a0001;
mem[33] <= 32'h1740fffe;
mem[34] <= 32'h00000000;
end
`endif
always @ (posedge clk)
begin
if (Wren)
mem[Waddr] <= Wdata;
end
assign Rdata1 = {32{Rden1}} & mem[Raddr1];
assign Rdata2 = {32{Rden2}} & mem[Raddr2];
endmodule | 0 |
139,752 | data/full_repos/permissive/89699825/single_cycle_cpu/mips_core_top/mips_cpu_top.v | 89,699,825 | mips_cpu_top.v | v | 188 | 110 | [] | [] | [] | [(13, 186)] | null | null | 1: b"%Error: data/full_repos/permissive/89699825/single_cycle_cpu/mips_core_top/mips_cpu_top.v:81: Cannot find file containing module: 'axi_lite_if'\n axi_lite_if u_axi_lite_slave (\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89699825/single_cycle_cpu/mips_core_top,data/full_repos/permissive/89699825/axi_lite_if\n data/full_repos/permissive/89699825/single_cycle_cpu/mips_core_top,data/full_repos/permissive/89699825/axi_lite_if.v\n data/full_repos/permissive/89699825/single_cycle_cpu/mips_core_top,data/full_repos/permissive/89699825/axi_lite_if.sv\n axi_lite_if\n axi_lite_if.v\n axi_lite_if.sv\n obj_dir/axi_lite_if\n obj_dir/axi_lite_if.v\n obj_dir/axi_lite_if.sv\n%Error: data/full_repos/permissive/89699825/single_cycle_cpu/mips_core_top/mips_cpu_top.v:124: Cannot find file containing module: 'mips_cpu'\n mips_cpu u_mips_cpu ( \n ^~~~~~~~\n%Error: data/full_repos/permissive/89699825/single_cycle_cpu/mips_core_top/mips_cpu_top.v:170: Cannot find file containing module: 'ideal_mem'\n ideal_mem u_ideal_mem (\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 307,790 | module | module mips_cpu_top (
`ifndef MIPS_CPU_SIM
input [13:0] mips_cpu_axi_if_araddr,
output mips_cpu_axi_if_arready,
input mips_cpu_axi_if_arvalid,
input [13:0] mips_cpu_axi_if_awaddr,
output mips_cpu_axi_if_awready,
input mips_cpu_axi_if_awvalid,
input mips_cpu_axi_if_bready,
output [1:0] mips_cpu_axi_if_bresp,
output mips_cpu_axi_if_bvalid,
output [31:0] mips_cpu_axi_if_rdata,
input mips_cpu_axi_if_rready,
output [1:0] mips_cpu_axi_if_rresp,
output mips_cpu_axi_if_rvalid,
input [31:0] mips_cpu_axi_if_wdata,
output mips_cpu_axi_if_wready,
input [3:0] mips_cpu_axi_if_wstrb,
input mips_cpu_axi_if_wvalid,
`endif
input mips_cpu_clk,
input mips_cpu_reset
);
wire [10:0] axi_lite_mem_addr;
wire [31:0] axi_lite_mem_wdata;
wire axi_lite_mem_wren;
wire axi_lite_mem_rden;
wire [31:0] axi_lite_mem_rdata;
wire [31:0] mips_mem_addr;
wire mips_mem_wren;
wire mips_mem_rden;
wire [31:0] mips_mem_wdata;
wire [31:0] mips_mem_rdata;
wire mips_mem_rd;
wire axi_lite_mem_rd;
wire [10:0] Waddr;
wire [31:0] Raddr1;
wire [10:0] Raddr2;
wire Wren;
wire Rden2;
wire [31:0] Wdata;
wire [31:0] Rdata1;
wire [31:0] Rdata2;
wire mips_rst;
`ifndef MIPS_CPU_SIM
axi_lite_if u_axi_lite_slave (
.S_AXI_ACLK (mips_cpu_clk),
.S_AXI_ARESETN (~mips_cpu_reset),
.S_AXI_ARADDR (mips_cpu_axi_if_araddr),
.S_AXI_ARREADY (mips_cpu_axi_if_arready),
.S_AXI_ARVALID (mips_cpu_axi_if_arvalid),
.S_AXI_AWADDR (mips_cpu_axi_if_awaddr),
.S_AXI_AWREADY (mips_cpu_axi_if_awready),
.S_AXI_AWVALID (mips_cpu_axi_if_awvalid),
.S_AXI_BREADY (mips_cpu_axi_if_bready),
.S_AXI_BRESP (mips_cpu_axi_if_bresp),
.S_AXI_BVALID (mips_cpu_axi_if_bvalid),
.S_AXI_RDATA (mips_cpu_axi_if_rdata),
.S_AXI_RREADY (mips_cpu_axi_if_rready),
.S_AXI_RRESP (mips_cpu_axi_if_rresp),
.S_AXI_RVALID (mips_cpu_axi_if_rvalid),
.S_AXI_WDATA (mips_cpu_axi_if_wdata),
.S_AXI_WREADY (mips_cpu_axi_if_wready),
.S_AXI_WSTRB (mips_cpu_axi_if_wstrb),
.S_AXI_WVALID (mips_cpu_axi_if_wvalid),
.Address (axi_lite_mem_addr),
.MemRead (axi_lite_mem_rden),
.MemWrite (axi_lite_mem_wren),
.Read_data (axi_lite_mem_rdata),
.Write_data (axi_lite_mem_wdata),
.mips_rst (mips_rst)
);
`else
assign axi_lite_mem_addr = 'd0;
assign axi_lite_mem_rden = 'd0;
assign axi_lite_mem_wren = 'd0;
assign axi_lite_mem_wdata = 'd0;
assign mips_rst = mips_cpu_reset;
`endif
mips_cpu u_mips_cpu (
.clk (mips_cpu_clk),
.rst (mips_rst),
.PC (Raddr1),
.Instruction (Rdata1),
.Address (mips_mem_addr),
.MemWrite (mips_mem_wren),
.Write_data (mips_mem_wdata),
.MemRead (mips_mem_rden),
.Read_data (mips_mem_rdata)
);
assign mips_mem_rd = mips_mem_rden & (~mips_rst);
assign axi_lite_mem_rd = axi_lite_mem_rden & (mips_rst | (~mips_mem_rden));
assign Rden2 = mips_mem_rd | axi_lite_mem_rd;
assign axi_lite_mem_rdata = ({32{axi_lite_mem_rd}} & Rdata2) | ({32{~axi_lite_mem_rd}});
assign mips_mem_rdata = {32{mips_mem_rd}} & Rdata2;
assign Raddr2 = ({11{mips_mem_rd}} & mips_mem_addr[12:2]) | ({11{axi_lite_mem_rd}} & axi_lite_mem_addr);
assign Wren = mips_mem_wren | axi_lite_mem_wren;
assign Wdata = ({32{mips_mem_wren}} & mips_mem_wdata) | ({32{axi_lite_mem_wren}} & axi_lite_mem_wdata);
assign Waddr = ({11{mips_mem_wren}} & mips_mem_addr[12:2]) | ({11{axi_lite_mem_wren}} & axi_lite_mem_addr);
ideal_mem u_ideal_mem (
.clk (mips_cpu_clk),
.Waddr (Waddr[9:0]),
.Raddr1 (Raddr1[11:2]),
.Raddr2 (Raddr2[9:0]),
.Wren (Wren),
.Rden1 (1'b1),
.Rden2 (Rden2),
.Wdata (Wdata),
.Rdata1 (Rdata1),
.Rdata2 (Rdata2)
);
endmodule | module mips_cpu_top (
`ifndef MIPS_CPU_SIM
input [13:0] mips_cpu_axi_if_araddr,
output mips_cpu_axi_if_arready,
input mips_cpu_axi_if_arvalid,
input [13:0] mips_cpu_axi_if_awaddr,
output mips_cpu_axi_if_awready,
input mips_cpu_axi_if_awvalid,
input mips_cpu_axi_if_bready,
output [1:0] mips_cpu_axi_if_bresp,
output mips_cpu_axi_if_bvalid,
output [31:0] mips_cpu_axi_if_rdata,
input mips_cpu_axi_if_rready,
output [1:0] mips_cpu_axi_if_rresp,
output mips_cpu_axi_if_rvalid,
input [31:0] mips_cpu_axi_if_wdata,
output mips_cpu_axi_if_wready,
input [3:0] mips_cpu_axi_if_wstrb,
input mips_cpu_axi_if_wvalid,
`endif
input mips_cpu_clk,
input mips_cpu_reset
); |
wire [10:0] axi_lite_mem_addr;
wire [31:0] axi_lite_mem_wdata;
wire axi_lite_mem_wren;
wire axi_lite_mem_rden;
wire [31:0] axi_lite_mem_rdata;
wire [31:0] mips_mem_addr;
wire mips_mem_wren;
wire mips_mem_rden;
wire [31:0] mips_mem_wdata;
wire [31:0] mips_mem_rdata;
wire mips_mem_rd;
wire axi_lite_mem_rd;
wire [10:0] Waddr;
wire [31:0] Raddr1;
wire [10:0] Raddr2;
wire Wren;
wire Rden2;
wire [31:0] Wdata;
wire [31:0] Rdata1;
wire [31:0] Rdata2;
wire mips_rst;
`ifndef MIPS_CPU_SIM
axi_lite_if u_axi_lite_slave (
.S_AXI_ACLK (mips_cpu_clk),
.S_AXI_ARESETN (~mips_cpu_reset),
.S_AXI_ARADDR (mips_cpu_axi_if_araddr),
.S_AXI_ARREADY (mips_cpu_axi_if_arready),
.S_AXI_ARVALID (mips_cpu_axi_if_arvalid),
.S_AXI_AWADDR (mips_cpu_axi_if_awaddr),
.S_AXI_AWREADY (mips_cpu_axi_if_awready),
.S_AXI_AWVALID (mips_cpu_axi_if_awvalid),
.S_AXI_BREADY (mips_cpu_axi_if_bready),
.S_AXI_BRESP (mips_cpu_axi_if_bresp),
.S_AXI_BVALID (mips_cpu_axi_if_bvalid),
.S_AXI_RDATA (mips_cpu_axi_if_rdata),
.S_AXI_RREADY (mips_cpu_axi_if_rready),
.S_AXI_RRESP (mips_cpu_axi_if_rresp),
.S_AXI_RVALID (mips_cpu_axi_if_rvalid),
.S_AXI_WDATA (mips_cpu_axi_if_wdata),
.S_AXI_WREADY (mips_cpu_axi_if_wready),
.S_AXI_WSTRB (mips_cpu_axi_if_wstrb),
.S_AXI_WVALID (mips_cpu_axi_if_wvalid),
.Address (axi_lite_mem_addr),
.MemRead (axi_lite_mem_rden),
.MemWrite (axi_lite_mem_wren),
.Read_data (axi_lite_mem_rdata),
.Write_data (axi_lite_mem_wdata),
.mips_rst (mips_rst)
);
`else
assign axi_lite_mem_addr = 'd0;
assign axi_lite_mem_rden = 'd0;
assign axi_lite_mem_wren = 'd0;
assign axi_lite_mem_wdata = 'd0;
assign mips_rst = mips_cpu_reset;
`endif
mips_cpu u_mips_cpu (
.clk (mips_cpu_clk),
.rst (mips_rst),
.PC (Raddr1),
.Instruction (Rdata1),
.Address (mips_mem_addr),
.MemWrite (mips_mem_wren),
.Write_data (mips_mem_wdata),
.MemRead (mips_mem_rden),
.Read_data (mips_mem_rdata)
);
assign mips_mem_rd = mips_mem_rden & (~mips_rst);
assign axi_lite_mem_rd = axi_lite_mem_rden & (mips_rst | (~mips_mem_rden));
assign Rden2 = mips_mem_rd | axi_lite_mem_rd;
assign axi_lite_mem_rdata = ({32{axi_lite_mem_rd}} & Rdata2) | ({32{~axi_lite_mem_rd}});
assign mips_mem_rdata = {32{mips_mem_rd}} & Rdata2;
assign Raddr2 = ({11{mips_mem_rd}} & mips_mem_addr[12:2]) | ({11{axi_lite_mem_rd}} & axi_lite_mem_addr);
assign Wren = mips_mem_wren | axi_lite_mem_wren;
assign Wdata = ({32{mips_mem_wren}} & mips_mem_wdata) | ({32{axi_lite_mem_wren}} & axi_lite_mem_wdata);
assign Waddr = ({11{mips_mem_wren}} & mips_mem_addr[12:2]) | ({11{axi_lite_mem_wren}} & axi_lite_mem_addr);
ideal_mem u_ideal_mem (
.clk (mips_cpu_clk),
.Waddr (Waddr[9:0]),
.Raddr1 (Raddr1[11:2]),
.Raddr2 (Raddr2[9:0]),
.Wren (Wren),
.Rden1 (1'b1),
.Rden2 (Rden2),
.Wdata (Wdata),
.Rdata1 (Rdata1),
.Rdata2 (Rdata2)
);
endmodule | 0 |
139,753 | data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v | 89,709,715 | test_bench.v | v | 132 | 116 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb3 in position 44: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:1: Cannot find include file: ../../sources_1/new/defines.v\n`include "../../sources_1/new/defines.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new,data/full_repos/permissive/89709715/../../sources_1/new/defines.v\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new,data/full_repos/permissive/89709715/../../sources_1/new/defines.v.v\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new,data/full_repos/permissive/89709715/../../sources_1/new/defines.v.sv\n ../../sources_1/new/defines.v\n ../../sources_1/new/defines.v.v\n ../../sources_1/new/defines.v.sv\n obj_dir/../../sources_1/new/defines.v\n obj_dir/../../sources_1/new/defines.v.v\n obj_dir/../../sources_1/new/defines.v.sv\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:29: Define or directive not defined: \'`m300\'\n parameter CENA_OP1 = `m300; \n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:29: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CENA_OP1 = `m300; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:30: Define or directive not defined: \'`m500\'\n parameter CENA_OP2 = `m500; \n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:30: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CENA_OP2 = `m500; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:31: Define or directive not defined: \'`m750\'\n parameter CENA_OP3 = `m750; \n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:31: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CENA_OP3 = `m750; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:89: Define or directive not defined: \'`CMD_RESET\'\n : ... Suggested alternative: \'`SV_COV_RESET\'\n panel_przyciskow = `CMD_RESET; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:89: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n panel_przyciskow = `CMD_RESET; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:96: Define or directive not defined: \'`z0g00\'\n monety_in = `z0g00;\n ^~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:96: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n monety_in = `z0g00;\n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:98: Define or directive not defined: \'`z0g50\'\n #(tick_every*10) monety_in <= `z0g50; \n ^~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:98: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #(tick_every*10) monety_in <= `z0g50; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:98: Unsupported: Ignoring delay on this delayed statement.\n #(tick_every*10) monety_in <= `z0g50; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:99: Define or directive not defined: \'`z1g00\'\n #(tick_every*10) monety_in <= `z1g00; \n ^~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:99: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #(tick_every*10) monety_in <= `z1g00; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:99: Unsupported: Ignoring delay on this delayed statement.\n #(tick_every*10) monety_in <= `z1g00; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:100: Define or directive not defined: \'`z2g00\'\n #(tick_every*10) monety_in <= `z2g00; \n ^~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:100: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #(tick_every*10) monety_in <= `z2g00; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:100: Unsupported: Ignoring delay on this delayed statement.\n #(tick_every*10) monety_in <= `z2g00; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:101: Define or directive not defined: \'`z5g00\'\n #(tick_every*10) monety_in <= `z5g00; \n ^~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:101: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #(tick_every*10) monety_in <= `z5g00; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:101: Unsupported: Ignoring delay on this delayed statement.\n #(tick_every*10) monety_in <= `z5g00; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:102: Define or directive not defined: \'`CMD_OP1\'\n #(tick_every*10) panel_przyciskow <= `CMD_OP1; \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:102: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #(tick_every*10) panel_przyciskow <= `CMD_OP1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:102: Unsupported: Ignoring delay on this delayed statement.\n #(tick_every*10) panel_przyciskow <= `CMD_OP1; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:103: Define or directive not defined: \'`CMD_OP2\'\n #(tick_every*10) panel_przyciskow <= `CMD_OP2; \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:103: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #(tick_every*10) panel_przyciskow <= `CMD_OP2; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:103: Unsupported: Ignoring delay on this delayed statement.\n #(tick_every*10) panel_przyciskow <= `CMD_OP2; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:104: Define or directive not defined: \'`z2g00\'\n #(tick_every*10) monety_in <= `z2g00; \n ^~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:104: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #(tick_every*10) monety_in <= `z2g00; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:104: Unsupported: Ignoring delay on this delayed statement.\n #(tick_every*10) monety_in <= `z2g00; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:105: Define or directive not defined: \'`z0g50\'\n #(tick_every*10) monety_in <= `z0g50; \n ^~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:105: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #(tick_every*10) monety_in <= `z0g50; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:105: Unsupported: Ignoring delay on this delayed statement.\n #(tick_every*10) monety_in <= `z0g50; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:106: Define or directive not defined: \'`CMD_RESET\'\n : ... Suggested alternative: \'`SV_COV_RESET\'\n #(tick_every*10) panel_przyciskow = `CMD_RESET; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:106: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #(tick_every*10) panel_przyciskow = `CMD_RESET; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:106: Unsupported: Ignoring delay on this delayed statement.\n #(tick_every*10) panel_przyciskow = `CMD_RESET; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:107: Define or directive not defined: \'`z5g00\'\n #(tick_every*2) monety_in <= `z5g00; \n ^~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:107: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #(tick_every*2) monety_in <= `z5g00; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:107: Unsupported: Ignoring delay on this delayed statement.\n #(tick_every*2) monety_in <= `z5g00; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:109: Define or directive not defined: \'`CMD_OP3\'\n #(tick_every*30) panel_przyciskow <= `CMD_OP3; \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:109: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #(tick_every*30) panel_przyciskow <= `CMD_OP3; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:109: Unsupported: Ignoring delay on this delayed statement.\n #(tick_every*30) panel_przyciskow <= `CMD_OP3; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:110: Define or directive not defined: \'`z2g00\'\n #(tick_every*10) monety_in <= `z2g00; \n ^~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:110: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #(tick_every*10) monety_in <= `z2g00; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:110: Unsupported: Ignoring delay on this delayed statement.\n #(tick_every*10) monety_in <= `z2g00; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:111: Define or directive not defined: \'`z0g50\'\n #(tick_every*10) monety_in <= `z0g50; \n ^~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:111: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #(tick_every*10) monety_in <= `z0g50; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:111: Unsupported: Ignoring delay on this delayed statement.\n #(tick_every*10) monety_in <= `z0g50; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:112: Define or directive not defined: \'`z2g00\'\n #(tick_every*10) monety_in <= `z2g00; \n ^~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:112: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #(tick_every*10) monety_in <= `z2g00; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:112: Unsupported: Ignoring delay on this delayed statement.\n #(tick_every*10) monety_in <= `z2g00; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:113: Define or directive not defined: \'`z5g00\'\n #(tick_every*10) monety_in <= `z5g00; \n ^~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:113: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #(tick_every*10) monety_in <= `z5g00; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:113: Unsupported: Ignoring delay on this delayed statement.\n #(tick_every*10) monety_in <= `z5g00; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:118: Unsupported: Ignoring delay on this delayed statement.\n #(tick_every/2)\n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:125: Define or directive not defined: \'`z0g00\'\n if (monety_in != `z0g00)\n ^~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:125: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (monety_in != `z0g00)\n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:126: Define or directive not defined: \'`z0g00\'\n #(tick_every*4) monety_in <= `z0g00; \n ^~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:128: Define or directive not defined: \'`CMD_NIC\'\n #(tick_every*4) panel_przyciskow <= `CMD_NIC; \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:128: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #(tick_every*4) panel_przyciskow <= `CMD_NIC; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sim_1/new/test_bench.v:128: Unsupported: Ignoring delay on this delayed statement.\n #(tick_every*4) panel_przyciskow <= `CMD_NIC; \n ^\n%Error: Exiting due to 46 error(s), 17 warning(s)\n' | 307,791 | module | module test_bench();
reg clk;
reg [2:0]panel_przyciskow;
parameter CENA_OP1 = `m300;
parameter CENA_OP2 = `m500;
parameter CENA_OP3 = `m750;
parameter tick_every = 20;
parameter speed_up = 50000;
reg [2:0]monety_in;
wire [2:0]monety_out;
reg kubki, kawa, woda, mleko, bilon;
top #(.CENA_OP1(CENA_OP1), .CENA_OP2(CENA_OP2), .CENA_OP3(CENA_OP3), .tick_every(tick_every*speed_up))
uut(.clk(clk), .mon_in(monety_in), .panel_przyciskow_in(panel_przyciskow), .mon_out(monety_out),
.c_k(kubki), .i_k(kawa), .p_w(woda), .i_m(mleko), .p_b(bilon));
wire clk_div;
wire [3:0]stan_top;
assign clk_div = top.clk_div;
assign stan_top = top.old_top.stan_top;
wire [1:0]cmd_out_mm;
wire [4:0]stan_mm;
assign stan_mm = top.wrzut_zwrot.stan;
assign cmd_out_mm = top.cmd_out;
wire sprawnosc;
assign sprawnosc = top.sprawnosc_out;
wire [3:0]seg_out;
wire seg_dl, seg_dm, seg_dot, seg_dr, seg_mm, seg_ul, seg_um, seg_ur;
assign seg_um = top.seg_um;
assign seg_ul = top.seg_ul;
assign seg_ur = top.seg_ur;
assign seg_mm = top.seg_mm;
assign seg_dl = top.seg_dl;
assign seg_dr = top.seg_dr;
assign seg_dm = top.seg_dm;
assign seg_dot = top.seg_dot;
assign seg_out = top.segment_out;
wire [6:0] count_secs;
wire count_out;
assign count_secs = top.count_secs;
assign count_out = top.licz_in;
initial
begin
clk = 1'b0;
panel_przyciskow = `CMD_RESET;
kubki <= 1'b0;
kawa <= 1'b0;
woda <= 1'b0;
mleko <= 1'b0;
bilon <= 1'b0;
monety_in = `z0g00;
#(tick_every*10) monety_in <= `z0g50;
#(tick_every*10) monety_in <= `z1g00;
#(tick_every*10) monety_in <= `z2g00;
#(tick_every*10) monety_in <= `z5g00;
#(tick_every*10) panel_przyciskow <= `CMD_OP1;
#(tick_every*10) panel_przyciskow <= `CMD_OP2;
#(tick_every*10) monety_in <= `z2g00;
#(tick_every*10) monety_in <= `z0g50;
#(tick_every*10) panel_przyciskow = `CMD_RESET;
#(tick_every*2) monety_in <= `z5g00;
#(tick_every*30) panel_przyciskow <= `CMD_OP3;
#(tick_every*10) monety_in <= `z2g00;
#(tick_every*10) monety_in <= `z0g50;
#(tick_every*10) monety_in <= `z2g00;
#(tick_every*10) monety_in <= `z5g00;
end
always
begin
#(tick_every/2)
begin
clk <= ~clk;
end
end
always @(clk)
begin
if (monety_in != `z0g00)
#(tick_every*4) monety_in <= `z0g00;
if (panel_przyciskow != 1'b0)
#(tick_every*4) panel_przyciskow <= `CMD_NIC;
end
endmodule | module test_bench(); |
reg clk;
reg [2:0]panel_przyciskow;
parameter CENA_OP1 = `m300;
parameter CENA_OP2 = `m500;
parameter CENA_OP3 = `m750;
parameter tick_every = 20;
parameter speed_up = 50000;
reg [2:0]monety_in;
wire [2:0]monety_out;
reg kubki, kawa, woda, mleko, bilon;
top #(.CENA_OP1(CENA_OP1), .CENA_OP2(CENA_OP2), .CENA_OP3(CENA_OP3), .tick_every(tick_every*speed_up))
uut(.clk(clk), .mon_in(monety_in), .panel_przyciskow_in(panel_przyciskow), .mon_out(monety_out),
.c_k(kubki), .i_k(kawa), .p_w(woda), .i_m(mleko), .p_b(bilon));
wire clk_div;
wire [3:0]stan_top;
assign clk_div = top.clk_div;
assign stan_top = top.old_top.stan_top;
wire [1:0]cmd_out_mm;
wire [4:0]stan_mm;
assign stan_mm = top.wrzut_zwrot.stan;
assign cmd_out_mm = top.cmd_out;
wire sprawnosc;
assign sprawnosc = top.sprawnosc_out;
wire [3:0]seg_out;
wire seg_dl, seg_dm, seg_dot, seg_dr, seg_mm, seg_ul, seg_um, seg_ur;
assign seg_um = top.seg_um;
assign seg_ul = top.seg_ul;
assign seg_ur = top.seg_ur;
assign seg_mm = top.seg_mm;
assign seg_dl = top.seg_dl;
assign seg_dr = top.seg_dr;
assign seg_dm = top.seg_dm;
assign seg_dot = top.seg_dot;
assign seg_out = top.segment_out;
wire [6:0] count_secs;
wire count_out;
assign count_secs = top.count_secs;
assign count_out = top.licz_in;
initial
begin
clk = 1'b0;
panel_przyciskow = `CMD_RESET;
kubki <= 1'b0;
kawa <= 1'b0;
woda <= 1'b0;
mleko <= 1'b0;
bilon <= 1'b0;
monety_in = `z0g00;
#(tick_every*10) monety_in <= `z0g50;
#(tick_every*10) monety_in <= `z1g00;
#(tick_every*10) monety_in <= `z2g00;
#(tick_every*10) monety_in <= `z5g00;
#(tick_every*10) panel_przyciskow <= `CMD_OP1;
#(tick_every*10) panel_przyciskow <= `CMD_OP2;
#(tick_every*10) monety_in <= `z2g00;
#(tick_every*10) monety_in <= `z0g50;
#(tick_every*10) panel_przyciskow = `CMD_RESET;
#(tick_every*2) monety_in <= `z5g00;
#(tick_every*30) panel_przyciskow <= `CMD_OP3;
#(tick_every*10) monety_in <= `z2g00;
#(tick_every*10) monety_in <= `z0g50;
#(tick_every*10) monety_in <= `z2g00;
#(tick_every*10) monety_in <= `z5g00;
end
always
begin
#(tick_every/2)
begin
clk <= ~clk;
end
end
always @(clk)
begin
if (monety_in != `z0g00)
#(tick_every*4) monety_in <= `z0g00;
if (panel_przyciskow != 1'b0)
#(tick_every*4) panel_przyciskow <= `CMD_NIC;
end
endmodule | 0 |
139,754 | data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v | 89,709,715 | counter.v | v | 94 | 119 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb3 in position 44: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:1: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v.v\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:27: Define or directive not defined: \'`LICZNIK_RESET\'\n `LICZNIK_RESET: \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:27: syntax error, unexpected \':\', expecting endcase\n `LICZNIK_RESET: \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:29: Define or directive not defined: \'`NIC_NIE_ODLICZAM\'\n count_out <= `NIC_NIE_ODLICZAM;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:32: Define or directive not defined: \'`ODLICZ_KUBEK\'\n `ODLICZ_KUBEK: \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:33: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n begin\n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:34: Define or directive not defined: \'`ODLICZAM\'\n count_out = `ODLICZAM;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:35: Define or directive not defined: \'`CZAS_KUBEK\'\n count_to_0 = `CZAS_KUBEK*mc;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:35: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n count_to_0 = `CZAS_KUBEK*mc;\n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:37: Define or directive not defined: \'`ODLICZ_KAWA_OP1\'\n `ODLICZ_KAWA_OP1: \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:38: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n begin\n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:39: Define or directive not defined: \'`ODLICZAM\'\n count_out = `ODLICZAM;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:40: Define or directive not defined: \'`CZAS_KAWA_OPCJA1\'\n count_to_0 = `CZAS_KAWA_OPCJA1*mc;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:40: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n count_to_0 = `CZAS_KAWA_OPCJA1*mc;\n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:42: Define or directive not defined: \'`ODLICZ_KAWA_OP2\'\n `ODLICZ_KAWA_OP2: \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:43: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n begin\n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:44: Define or directive not defined: \'`ODLICZAM\'\n count_out = `ODLICZAM;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:45: Define or directive not defined: \'`CZAS_KAWA_OPCJA2\'\n count_to_0 = `CZAS_KAWA_OPCJA2*mc;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:45: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n count_to_0 = `CZAS_KAWA_OPCJA2*mc;\n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:47: Define or directive not defined: \'`ODLICZ_KAWA_OP3\'\n `ODLICZ_KAWA_OP3: \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:48: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n begin\n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:49: Define or directive not defined: \'`ODLICZAM\'\n count_out = `ODLICZAM;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:50: Define or directive not defined: \'`CZAS_KAWA_OPCJA3\'\n count_to_0 = `CZAS_KAWA_OPCJA3*mc;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:50: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n count_to_0 = `CZAS_KAWA_OPCJA3*mc;\n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:52: Define or directive not defined: \'`ODLICZ_WODA_OP1\'\n `ODLICZ_WODA_OP1: \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:53: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n begin\n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:54: Define or directive not defined: \'`ODLICZAM\'\n count_out = `ODLICZAM;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:55: Define or directive not defined: \'`CZAS_WODA_OPCJA1\'\n count_to_0 = `CZAS_WODA_OPCJA1*mc; \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:55: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n count_to_0 = `CZAS_WODA_OPCJA1*mc; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:57: Define or directive not defined: \'`ODLICZ_WODA_OP2\'\n `ODLICZ_WODA_OP2: \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:58: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n begin\n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:59: Define or directive not defined: \'`ODLICZAM\'\n count_out = `ODLICZAM;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:60: Define or directive not defined: \'`CZAS_WODA_OPCJA2\'\n count_to_0 = `CZAS_WODA_OPCJA2*mc;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:60: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n count_to_0 = `CZAS_WODA_OPCJA2*mc;\n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:62: Define or directive not defined: \'`ODLICZ_WODA_OP3\'\n `ODLICZ_WODA_OP3: \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:63: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n begin\n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:64: Define or directive not defined: \'`ODLICZAM\'\n count_out = `ODLICZAM;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:65: Define or directive not defined: \'`CZAS_WODA_OPCJA3\'\n count_to_0 = `CZAS_WODA_OPCJA3*mc;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:65: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n count_to_0 = `CZAS_WODA_OPCJA3*mc;\n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:67: Define or directive not defined: \'`ODLICZ_MLEKO\'\n `ODLICZ_MLEKO: \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:68: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n begin\n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:69: Define or directive not defined: \'`ODLICZAM\'\n count_out = `ODLICZAM;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:70: Define or directive not defined: \'`CZAS_MLEKO\'\n count_to_0 = `CZAS_MLEKO*mc;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:70: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n count_to_0 = `CZAS_MLEKO*mc;\n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:72: Define or directive not defined: \'`ODLICZ_NAPELN\'\n `ODLICZ_NAPELN: \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:73: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n begin\n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:74: Define or directive not defined: \'`ODLICZAM\'\n count_out <= `ODLICZAM;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:75: Define or directive not defined: \'`CZAS_NAPELN\'\n count_to_0 <= `CZAS_NAPELN*mc;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:75: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n count_to_0 <= `CZAS_NAPELN*mc;\n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/counter.v:77: Define or directive not defined: \'`ODLICZ_CZYSC\'\n `ODLICZ_CZYSC: \n ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 307,792 | module | module counter(clk, count_in, count_out, count_secs);
input clk;
input [3:0] count_in;
output reg count_out;
output wire [6:0]count_secs;
reg [22:0] count_to_0 = 0;
parameter tick_every = 20;
integer mc = 1000000/tick_every;
assign count_secs = count_to_0/mc;
always @(count_in)
begin
case (count_in)
`LICZNIK_RESET:
begin
count_out <= `NIC_NIE_ODLICZAM;
count_to_0 <= 0;
end
`ODLICZ_KUBEK:
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_KUBEK*mc;
end
`ODLICZ_KAWA_OP1:
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_KAWA_OPCJA1*mc;
end
`ODLICZ_KAWA_OP2:
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_KAWA_OPCJA2*mc;
end
`ODLICZ_KAWA_OP3:
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_KAWA_OPCJA3*mc;
end
`ODLICZ_WODA_OP1:
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_WODA_OPCJA1*mc;
end
`ODLICZ_WODA_OP2:
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_WODA_OPCJA2*mc;
end
`ODLICZ_WODA_OP3:
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_WODA_OPCJA3*mc;
end
`ODLICZ_MLEKO:
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_MLEKO*mc;
end
`ODLICZ_NAPELN:
begin
count_out <= `ODLICZAM;
count_to_0 <= `CZAS_NAPELN*mc;
end
`ODLICZ_CZYSC:
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_CZYSC*mc;
end
endcase;
end
always @(negedge clk)
begin
if(count_out == `ODLICZAM && count_to_0 > 0)
count_to_0 <= count_to_0 - 1;
else
count_out <= `SKONCZYLEM_ODLICZAC;
end
endmodule | module counter(clk, count_in, count_out, count_secs); |
input clk;
input [3:0] count_in;
output reg count_out;
output wire [6:0]count_secs;
reg [22:0] count_to_0 = 0;
parameter tick_every = 20;
integer mc = 1000000/tick_every;
assign count_secs = count_to_0/mc;
always @(count_in)
begin
case (count_in)
`LICZNIK_RESET:
begin
count_out <= `NIC_NIE_ODLICZAM;
count_to_0 <= 0;
end
`ODLICZ_KUBEK:
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_KUBEK*mc;
end
`ODLICZ_KAWA_OP1:
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_KAWA_OPCJA1*mc;
end
`ODLICZ_KAWA_OP2:
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_KAWA_OPCJA2*mc;
end
`ODLICZ_KAWA_OP3:
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_KAWA_OPCJA3*mc;
end
`ODLICZ_WODA_OP1:
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_WODA_OPCJA1*mc;
end
`ODLICZ_WODA_OP2:
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_WODA_OPCJA2*mc;
end
`ODLICZ_WODA_OP3:
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_WODA_OPCJA3*mc;
end
`ODLICZ_MLEKO:
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_MLEKO*mc;
end
`ODLICZ_NAPELN:
begin
count_out <= `ODLICZAM;
count_to_0 <= `CZAS_NAPELN*mc;
end
`ODLICZ_CZYSC:
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_CZYSC*mc;
end
endcase;
end
always @(negedge clk)
begin
if(count_out == `ODLICZAM && count_to_0 > 0)
count_to_0 <= count_to_0 - 1;
else
count_out <= `SKONCZYLEM_ODLICZAC;
end
endmodule | 0 |
139,755 | data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/divider.v | 89,709,715 | divider.v | v | 42 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb3 in position 149: invalid start byte | data/verilator_xmls/c02dd8ff-d32b-4901-90e3-09c455e3e723.xml | null | 307,794 | module | module divider(
input wire clk,
output reg clk_div
);
parameter div = 1;
reg [div:0] c = 0;
always @(negedge c)
begin
clk_div <= (clk_div === 1'bX ? 1'b0 : ~clk_div);
end
always @(posedge clk)
begin
c <= c + 1;
end
endmodule | module divider(
input wire clk,
output reg clk_div
); |
parameter div = 1;
reg [div:0] c = 0;
always @(negedge c)
begin
clk_div <= (clk_div === 1'bX ? 1'b0 : ~clk_div);
end
always @(posedge clk)
begin
c <= c + 1;
end
endmodule | 0 |
139,756 | data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v | 89,709,715 | mdk.v | v | 295 | 168 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0x9c in position 5713: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:1: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v.v\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:54: Define or directive not defined: \'`m300\'\n parameter CENA_OP1 = `m300; \n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:54: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CENA_OP1 = `m300; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:55: Define or directive not defined: \'`m500\'\n parameter CENA_OP2 = `m500; \n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:55: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CENA_OP2 = `m500; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:56: Define or directive not defined: \'`m750\'\n parameter CENA_OP3 = `m750; \n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:56: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CENA_OP3 = `m750; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:81: Unsupported or unknown PLI call: $strobe\n $strobe("strobe count_secs:%b(%0d) a:%b(%0d) b:%b(%0d) @ %0t", count_secs, count_secs, b[4:0], b[4:0], a[4:0], a[4:0], $time);\n ^~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:88: Define or directive not defined: \'`CMD_RESET\'\n : ... Suggested alternative: \'`SV_COV_RESET\'\n if (panel_przyciskow_in == `CMD_RESET && cmd_in === 2\'bXX) \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:88: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n if (panel_przyciskow_in == `CMD_RESET && cmd_in === 2\'bXX) \n ^~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:93: Define or directive not defined: \'`NIC\'\n urzadzenia = `NIC;\n ^~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:93: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n urzadzenia = `NIC;\n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:94: Define or directive not defined: \'`CMD_RESET\'\n : ... Suggested alternative: \'`SV_COV_RESET\'\n cmd_out = `CMD_RESET; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:94: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n cmd_out = `CMD_RESET; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:95: Define or directive not defined: \'`LICZNIK_RESET\'\n licz_out = `LICZNIK_RESET; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:95: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n licz_out = `LICZNIK_RESET; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:87: Unsupported: Ignoring delay on this delayed statement.\n #1 begin\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:104: Define or directive not defined: \'`CMD_OP1\'\n `CMD_OP1: \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:104: syntax error, unexpected \':\', expecting endcase\n `CMD_OP1: \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:105: Define or directive not defined: \'`ODP_NIC\'\n if(cmd_in == `ODP_NIC) \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:107: Define or directive not defined: \'`CMD_OP1\'\n cmd_out = `CMD_OP1; \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:108: Define or directive not defined: \'`POBIERAM\'\n stan_n = `POBIERAM;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:110: Define or directive not defined: \'`CMD_OP2\'\n `CMD_OP2: \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:111: Define or directive not defined: \'`ODP_NIC\'\n if(cmd_in == `ODP_NIC) \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:113: Define or directive not defined: \'`CMD_OP2\'\n cmd_out = `CMD_OP2; \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:114: Define or directive not defined: \'`POBIERAM\'\n stan_n = `POBIERAM;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:116: Define or directive not defined: \'`CMD_OP3\'\n `CMD_OP3: \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:117: Define or directive not defined: \'`ODP_NIC\'\n if(cmd_in == `ODP_NIC) \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:119: Define or directive not defined: \'`CMD_OP3\'\n cmd_out = `CMD_OP3; \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:120: Define or directive not defined: \'`POBIERAM\'\n stan_n = `POBIERAM;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:122: Define or directive not defined: \'`CMD_RESET\'\n : ... Suggested alternative: \'`SV_COV_RESET\'\n `CMD_RESET:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:124: Define or directive not defined: \'`PODSTAW_KUBEK\'\n if (stan_top < `PODSTAW_KUBEK) \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:127: Define or directive not defined: \'`CMD_OP1\'\n `CMD_OP1:\n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:129: Define or directive not defined: \'`CMD_RESET1\'\n cmd_out = `CMD_RESET1;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:130: Define or directive not defined: \'`ZWRACAM\'\n stan_n = `ZWRACAM;\n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:132: Define or directive not defined: \'`CMD_OP2\'\n `CMD_OP2:\n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:134: Define or directive not defined: \'`CMD_RESET2\'\n cmd_out = `CMD_RESET2;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:135: Define or directive not defined: \'`ZWRACAM\'\n stan_n = `ZWRACAM;\n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:137: Define or directive not defined: \'`CMD_OP3\'\n `CMD_OP3:\n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:139: Define or directive not defined: \'`CMD_RESET3\'\n cmd_out = `CMD_RESET3;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:140: Define or directive not defined: \'`ZWRACAM\'\n stan_n = `ZWRACAM;\n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:151: Define or directive not defined: \'`SKONCZYLEM_ODLICZAC\'\n if (licz_in == `SKONCZYLEM_ODLICZAC)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:154: Define or directive not defined: \'`NAPELNIJ_PRZEWODY\'\n `NAPELNIJ_PRZEWODY: begin stan_n = `PODSTAW_KUBEK; licz_out <= `ODLICZ_KUBEK; urzadzenia <= `CMD_PODSTAW_KUBEK; end\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:154: Define or directive not defined: \'`PODSTAW_KUBEK\'\n `NAPELNIJ_PRZEWODY: begin stan_n = `PODSTAW_KUBEK; licz_out <= `ODLICZ_KUBEK; urzadzenia <= `CMD_PODSTAW_KUBEK; end\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:154: Define or directive not defined: \'`ODLICZ_KUBEK\'\n `NAPELNIJ_PRZEWODY: begin stan_n = `PODSTAW_KUBEK; licz_out <= `ODLICZ_KUBEK; urzadzenia <= `CMD_PODSTAW_KUBEK; end\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:154: Define or directive not defined: \'`CMD_PODSTAW_KUBEK\'\n `NAPELNIJ_PRZEWODY: begin stan_n = `PODSTAW_KUBEK; licz_out <= `ODLICZ_KUBEK; urzadzenia <= `CMD_PODSTAW_KUBEK; end\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:155: Define or directive not defined: \'`PODSTAW_KUBEK\'\n `PODSTAW_KUBEK: \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:157: Define or directive not defined: \'`ZMIEL_KAWE\'\n stan_n = `ZMIEL_KAWE;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:159: Define or directive not defined: \'`CMD_OP1\'\n `CMD_OP1: begin licz_out <= `ODLICZ_KAWA_OP1; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:159: syntax error, unexpected \':\', expecting endcase\n `CMD_OP1: begin licz_out <= `ODLICZ_KAWA_OP1; end\n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:159: Define or directive not defined: \'`ODLICZ_KAWA_OP1\'\n `CMD_OP1: begin licz_out <= `ODLICZ_KAWA_OP1; end\n ^~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 307,795 | module | module mdk_top(
input wire clk_div,
input wire [2:0]panel_przyciskow_in,
input wire sprawnosc_in,
input wire licz_in,
input wire [6:0] count_secs,
output reg [3:0] licz_out,
input wire[1:0]cmd_in,
input wire[4:0]stan_mm,
output reg [2:0]cmd_out,
output reg [4:0] L_1,
output reg [4:0] L_2,
output reg [4:0] L_3,
output reg [4:0] L_4,
output reg [2:0]urzadzenia
);
parameter CENA_OP1 = `m300;
parameter CENA_OP2 = `m500;
parameter CENA_OP3 = `m750;
parameter tick_every = 20;
reg [3:0]stan_top, stan_n;
function [9:0]licznikNaLiczby;
input reg [6:0] count_secs;
integer a,b;
begin
b = count_secs / 10;
a = count_secs - (b*10);
licznikNaLiczby = {b[4:0],a[4:0]};
$strobe("strobe count_secs:%b(%0d) a:%b(%0d) b:%b(%0d) @ %0t", count_secs, count_secs, b[4:0], b[4:0], a[4:0], a[4:0], $time);
end
endfunction
always @(panel_przyciskow_in)
#1 begin
if (panel_przyciskow_in == `CMD_RESET && cmd_in === 2'bXX)
begin
stan_top = 0;
stan_n = 0;
urzadzenia = `NIC;
cmd_out = `CMD_RESET;
licz_out = `LICZNIK_RESET;
L_1 = 5'b00000;
L_2 = 5'b00000;
L_3 = 5'b00000;
L_4 = 5'b00000;
end
if (sprawnosc_in == 1'b0) begin
case (panel_przyciskow_in)
`CMD_OP1:
if(cmd_in == `ODP_NIC)
begin
cmd_out = `CMD_OP1;
stan_n = `POBIERAM;
end
`CMD_OP2:
if(cmd_in == `ODP_NIC)
begin
cmd_out = `CMD_OP2;
stan_n = `POBIERAM;
end
`CMD_OP3:
if(cmd_in == `ODP_NIC)
begin
cmd_out = `CMD_OP3;
stan_n = `POBIERAM;
end
`CMD_RESET:
begin
if (stan_top < `PODSTAW_KUBEK)
begin
case(cmd_out)
`CMD_OP1:
begin
cmd_out = `CMD_RESET1;
stan_n = `ZWRACAM;
end
`CMD_OP2:
begin
cmd_out = `CMD_RESET2;
stan_n = `ZWRACAM;
end
`CMD_OP3:
begin
cmd_out = `CMD_RESET3;
stan_n = `ZWRACAM;
end
endcase
end
end
endcase
end
stan_top <= stan_n;
end
always @(licz_in)
begin
if (licz_in == `SKONCZYLEM_ODLICZAC)
begin
case (stan_top)
`NAPELNIJ_PRZEWODY: begin stan_n = `PODSTAW_KUBEK; licz_out <= `ODLICZ_KUBEK; urzadzenia <= `CMD_PODSTAW_KUBEK; end
`PODSTAW_KUBEK:
begin
stan_n = `ZMIEL_KAWE;
case(cmd_out)
`CMD_OP1: begin licz_out <= `ODLICZ_KAWA_OP1; end
`CMD_OP2: begin licz_out <= `ODLICZ_KAWA_OP2; end
`CMD_OP3: begin licz_out <= `ODLICZ_KAWA_OP3; end
endcase
urzadzenia <= `CMD_ZMIEL_KAWE;
end
`ZMIEL_KAWE:
begin
stan_n = `DODAJ_WODE;
case(cmd_out)
`CMD_OP1: begin licz_out <= `ODLICZ_WODA_OP1; end
`CMD_OP2: begin licz_out <= `ODLICZ_WODA_OP2; end
`CMD_OP3: begin licz_out <= `ODLICZ_WODA_OP3; end
endcase
urzadzenia <= `CMD_DODAJ_WODE;
end
`DODAJ_WODE:
begin
case(cmd_out)
`CMD_OP1: begin stan_n = `CZYSC_MASZYNE; licz_out <= `ODLICZ_CZYSC; urzadzenia <= `CMD_CZYSC_MASZYNE; end
`CMD_OP2: begin stan_n = `CZYSC_MASZYNE; licz_out <= `ODLICZ_CZYSC; urzadzenia <= `CMD_CZYSC_MASZYNE; end
`CMD_OP3: begin stan_n = `SPIENIAJ_MLEKO; licz_out <= `ODLICZ_MLEKO; urzadzenia <= `CMD_SPIENIAJ_MLEKO; end
endcase
end
`SPIENIAJ_MLEKO:
begin
stan_n = `CZYSC_MASZYNE;
licz_out <= `ODLICZ_CZYSC;
urzadzenia <= `CMD_CZYSC_MASZYNE;
end
`CZYSC_MASZYNE:
begin
stan_n = `CZEKAM;
licz_out <= `LICZNIK_NULL;
urzadzenia <= `CMD_ZERO;
end
endcase
end
stan_top <= stan_n;
end
always @(cmd_in)
begin
stan_n = stan_top;
case (stan_top)
`POBIERAM:
begin
if ( cmd_in == `ODP_OK)
begin
stan_n <= `NAPELNIJ_PRZEWODY;
licz_out <= `ODLICZ_NAPELN;
urzadzenia <= `CMD_NAPELNIJ_PRZEWODY;
end
end
endcase
end
always @(posedge clk_div)
begin
stan_n <= stan_top;
case (stan_top)
`CZEKAM:
begin
{L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b0,`W_NULL,1'b0,`W_NULL,1'b0,`W_NULL};
end
`POBIERAM:
begin
case(stan_mm)
`NIC: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_0,1'b0,`W_0,1'b0,`W_0};
`m050: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_0,1'b0,`W_5,1'b0,`W_0};
`m100: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_1,1'b0,`W_0,1'b0,`W_0};
`m150: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_1,1'b0,`W_5,1'b0,`W_0};
`m200: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_2,1'b0,`W_0,1'b0,`W_0};
`m250: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_2,1'b0,`W_5,1'b0,`W_0};
`m300: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_3,1'b0,`W_0,1'b0,`W_0};
`m350: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_3,1'b0,`W_5,1'b0,`W_0};
`m400: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_4,1'b0,`W_0,1'b0,`W_0};
`m450: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_4,1'b0,`W_5,1'b0,`W_0};
`m500: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_5,1'b0,`W_0,1'b0,`W_0};
`m550: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_5,1'b0,`W_5,1'b0,`W_0};
`m600: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_6,1'b0,`W_0,1'b0,`W_0};
`m650: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_6,1'b0,`W_5,1'b0,`W_0};
`m700: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_7,1'b0,`W_0,1'b0,`W_0};
`m750: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_7,1'b0,`W_5,1'b0,`W_0};
`m800: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_8,1'b0,`W_0,1'b0,`W_0};
`m850: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_8,1'b0,`W_5,1'b0,`W_0};
`m900: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_9,1'b0,`W_0,1'b0,`W_0};
`m950: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_9,1'b0,`W_5,1'b0,`W_0};
`m1000: {L_1,L_2,L_3,L_4} <= {1'b0,`W_1,1'b1,`W_0,1'b0,`W_0,1'b0,`W_0};
endcase
end
`ZWRACAM:
begin
case (L_1)
default: {L_1,L_2,L_3,L_4} <= {1'b0,`W_UM,1'b0,`W_MM,1'b0,`W_UM,1'b0,`W_MM};
`W_UM: {L_1,L_2,L_3,L_4} <= {1'b0,`W_UL,1'b0,`W_UR,1'b0,`W_UL,1'b0,`W_UR};
`W_UL: {L_1,L_2,L_3,L_4} <= {1'b0,`W_MM,1'b0,`W_UM,1'b0,`W_MM,1'b0,`W_UM};
`W_MM: {L_1,L_2,L_3,L_4} <= {1'b0,`W_UR,1'b0,`W_UL,1'b0,`W_UR,1'b0,`W_UL};
endcase
end
`NAPELNIJ_PRZEWODY:
begin
{L_1,L_2,L_3,L_4} <= {1'b0,`W_MM,1'b0,`W_MM,licznikNaLiczby(count_secs)};
end
`PODSTAW_KUBEK:
begin
{L_1,L_2,L_3,L_4} <= {1'b0,`W_1,1'b0,`W_MM,licznikNaLiczby(count_secs)};
end
`ZMIEL_KAWE:
begin
{L_1,L_2,L_3,L_4} <= {1'b0,`W_2,1'b0,`W_MM,licznikNaLiczby(count_secs)};
end
`DODAJ_WODE:
begin
{L_1,L_2,L_3,L_4} <= {1'b0,`W_3,1'b0,`W_MM,licznikNaLiczby(count_secs)};
end
`SPIENIAJ_MLEKO:
begin
{L_1,L_2,L_3,L_4} <= {1'b0,`W_4,1'b0,`W_MM,licznikNaLiczby(count_secs)};
end
`CZYSC_MASZYNE:
begin
{L_1,L_2,L_3,L_4} <= {1'b0,`W_MM,1'b0,`W_MM,licznikNaLiczby(count_secs)};
end
endcase
end
always @(negedge clk_div)
begin
if ((cmd_out == `CMD_RESET || cmd_out == `CMD_RESET1 || cmd_out == `CMD_RESET2 || cmd_out == `CMD_RESET3) && cmd_in == `ODP_NIC)
begin
cmd_out <= `CMD_NIC;
licz_out <= `LICZNIK_NULL;
stan_n = `CZEKAM;
end
if (cmd_out == `CMD_NIC && stan_top != `CZEKAM)
stan_n = `CZEKAM;
stan_top <= stan_n;
end
endmodule | module mdk_top(
input wire clk_div,
input wire [2:0]panel_przyciskow_in,
input wire sprawnosc_in,
input wire licz_in,
input wire [6:0] count_secs,
output reg [3:0] licz_out,
input wire[1:0]cmd_in,
input wire[4:0]stan_mm,
output reg [2:0]cmd_out,
output reg [4:0] L_1,
output reg [4:0] L_2,
output reg [4:0] L_3,
output reg [4:0] L_4,
output reg [2:0]urzadzenia
); |
parameter CENA_OP1 = `m300;
parameter CENA_OP2 = `m500;
parameter CENA_OP3 = `m750;
parameter tick_every = 20;
reg [3:0]stan_top, stan_n;
function [9:0]licznikNaLiczby;
input reg [6:0] count_secs;
integer a,b;
begin
b = count_secs / 10;
a = count_secs - (b*10);
licznikNaLiczby = {b[4:0],a[4:0]};
$strobe("strobe count_secs:%b(%0d) a:%b(%0d) b:%b(%0d) @ %0t", count_secs, count_secs, b[4:0], b[4:0], a[4:0], a[4:0], $time);
end
endfunction
always @(panel_przyciskow_in)
#1 begin
if (panel_przyciskow_in == `CMD_RESET && cmd_in === 2'bXX)
begin
stan_top = 0;
stan_n = 0;
urzadzenia = `NIC;
cmd_out = `CMD_RESET;
licz_out = `LICZNIK_RESET;
L_1 = 5'b00000;
L_2 = 5'b00000;
L_3 = 5'b00000;
L_4 = 5'b00000;
end
if (sprawnosc_in == 1'b0) begin
case (panel_przyciskow_in)
`CMD_OP1:
if(cmd_in == `ODP_NIC)
begin
cmd_out = `CMD_OP1;
stan_n = `POBIERAM;
end
`CMD_OP2:
if(cmd_in == `ODP_NIC)
begin
cmd_out = `CMD_OP2;
stan_n = `POBIERAM;
end
`CMD_OP3:
if(cmd_in == `ODP_NIC)
begin
cmd_out = `CMD_OP3;
stan_n = `POBIERAM;
end
`CMD_RESET:
begin
if (stan_top < `PODSTAW_KUBEK)
begin
case(cmd_out)
`CMD_OP1:
begin
cmd_out = `CMD_RESET1;
stan_n = `ZWRACAM;
end
`CMD_OP2:
begin
cmd_out = `CMD_RESET2;
stan_n = `ZWRACAM;
end
`CMD_OP3:
begin
cmd_out = `CMD_RESET3;
stan_n = `ZWRACAM;
end
endcase
end
end
endcase
end
stan_top <= stan_n;
end
always @(licz_in)
begin
if (licz_in == `SKONCZYLEM_ODLICZAC)
begin
case (stan_top)
`NAPELNIJ_PRZEWODY: begin stan_n = `PODSTAW_KUBEK; licz_out <= `ODLICZ_KUBEK; urzadzenia <= `CMD_PODSTAW_KUBEK; end
`PODSTAW_KUBEK:
begin
stan_n = `ZMIEL_KAWE;
case(cmd_out)
`CMD_OP1: begin licz_out <= `ODLICZ_KAWA_OP1; end
`CMD_OP2: begin licz_out <= `ODLICZ_KAWA_OP2; end
`CMD_OP3: begin licz_out <= `ODLICZ_KAWA_OP3; end
endcase
urzadzenia <= `CMD_ZMIEL_KAWE;
end
`ZMIEL_KAWE:
begin
stan_n = `DODAJ_WODE;
case(cmd_out)
`CMD_OP1: begin licz_out <= `ODLICZ_WODA_OP1; end
`CMD_OP2: begin licz_out <= `ODLICZ_WODA_OP2; end
`CMD_OP3: begin licz_out <= `ODLICZ_WODA_OP3; end
endcase
urzadzenia <= `CMD_DODAJ_WODE;
end
`DODAJ_WODE:
begin
case(cmd_out)
`CMD_OP1: begin stan_n = `CZYSC_MASZYNE; licz_out <= `ODLICZ_CZYSC; urzadzenia <= `CMD_CZYSC_MASZYNE; end
`CMD_OP2: begin stan_n = `CZYSC_MASZYNE; licz_out <= `ODLICZ_CZYSC; urzadzenia <= `CMD_CZYSC_MASZYNE; end
`CMD_OP3: begin stan_n = `SPIENIAJ_MLEKO; licz_out <= `ODLICZ_MLEKO; urzadzenia <= `CMD_SPIENIAJ_MLEKO; end
endcase
end
`SPIENIAJ_MLEKO:
begin
stan_n = `CZYSC_MASZYNE;
licz_out <= `ODLICZ_CZYSC;
urzadzenia <= `CMD_CZYSC_MASZYNE;
end
`CZYSC_MASZYNE:
begin
stan_n = `CZEKAM;
licz_out <= `LICZNIK_NULL;
urzadzenia <= `CMD_ZERO;
end
endcase
end
stan_top <= stan_n;
end
always @(cmd_in)
begin
stan_n = stan_top;
case (stan_top)
`POBIERAM:
begin
if ( cmd_in == `ODP_OK)
begin
stan_n <= `NAPELNIJ_PRZEWODY;
licz_out <= `ODLICZ_NAPELN;
urzadzenia <= `CMD_NAPELNIJ_PRZEWODY;
end
end
endcase
end
always @(posedge clk_div)
begin
stan_n <= stan_top;
case (stan_top)
`CZEKAM:
begin
{L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b0,`W_NULL,1'b0,`W_NULL,1'b0,`W_NULL};
end
`POBIERAM:
begin
case(stan_mm)
`NIC: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_0,1'b0,`W_0,1'b0,`W_0};
`m050: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_0,1'b0,`W_5,1'b0,`W_0};
`m100: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_1,1'b0,`W_0,1'b0,`W_0};
`m150: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_1,1'b0,`W_5,1'b0,`W_0};
`m200: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_2,1'b0,`W_0,1'b0,`W_0};
`m250: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_2,1'b0,`W_5,1'b0,`W_0};
`m300: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_3,1'b0,`W_0,1'b0,`W_0};
`m350: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_3,1'b0,`W_5,1'b0,`W_0};
`m400: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_4,1'b0,`W_0,1'b0,`W_0};
`m450: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_4,1'b0,`W_5,1'b0,`W_0};
`m500: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_5,1'b0,`W_0,1'b0,`W_0};
`m550: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_5,1'b0,`W_5,1'b0,`W_0};
`m600: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_6,1'b0,`W_0,1'b0,`W_0};
`m650: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_6,1'b0,`W_5,1'b0,`W_0};
`m700: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_7,1'b0,`W_0,1'b0,`W_0};
`m750: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_7,1'b0,`W_5,1'b0,`W_0};
`m800: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_8,1'b0,`W_0,1'b0,`W_0};
`m850: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_8,1'b0,`W_5,1'b0,`W_0};
`m900: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_9,1'b0,`W_0,1'b0,`W_0};
`m950: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_9,1'b0,`W_5,1'b0,`W_0};
`m1000: {L_1,L_2,L_3,L_4} <= {1'b0,`W_1,1'b1,`W_0,1'b0,`W_0,1'b0,`W_0};
endcase
end
`ZWRACAM:
begin
case (L_1)
default: {L_1,L_2,L_3,L_4} <= {1'b0,`W_UM,1'b0,`W_MM,1'b0,`W_UM,1'b0,`W_MM};
`W_UM: {L_1,L_2,L_3,L_4} <= {1'b0,`W_UL,1'b0,`W_UR,1'b0,`W_UL,1'b0,`W_UR};
`W_UL: {L_1,L_2,L_3,L_4} <= {1'b0,`W_MM,1'b0,`W_UM,1'b0,`W_MM,1'b0,`W_UM};
`W_MM: {L_1,L_2,L_3,L_4} <= {1'b0,`W_UR,1'b0,`W_UL,1'b0,`W_UR,1'b0,`W_UL};
endcase
end
`NAPELNIJ_PRZEWODY:
begin
{L_1,L_2,L_3,L_4} <= {1'b0,`W_MM,1'b0,`W_MM,licznikNaLiczby(count_secs)};
end
`PODSTAW_KUBEK:
begin
{L_1,L_2,L_3,L_4} <= {1'b0,`W_1,1'b0,`W_MM,licznikNaLiczby(count_secs)};
end
`ZMIEL_KAWE:
begin
{L_1,L_2,L_3,L_4} <= {1'b0,`W_2,1'b0,`W_MM,licznikNaLiczby(count_secs)};
end
`DODAJ_WODE:
begin
{L_1,L_2,L_3,L_4} <= {1'b0,`W_3,1'b0,`W_MM,licznikNaLiczby(count_secs)};
end
`SPIENIAJ_MLEKO:
begin
{L_1,L_2,L_3,L_4} <= {1'b0,`W_4,1'b0,`W_MM,licznikNaLiczby(count_secs)};
end
`CZYSC_MASZYNE:
begin
{L_1,L_2,L_3,L_4} <= {1'b0,`W_MM,1'b0,`W_MM,licznikNaLiczby(count_secs)};
end
endcase
end
always @(negedge clk_div)
begin
if ((cmd_out == `CMD_RESET || cmd_out == `CMD_RESET1 || cmd_out == `CMD_RESET2 || cmd_out == `CMD_RESET3) && cmd_in == `ODP_NIC)
begin
cmd_out <= `CMD_NIC;
licz_out <= `LICZNIK_NULL;
stan_n = `CZEKAM;
end
if (cmd_out == `CMD_NIC && stan_top != `CZEKAM)
stan_n = `CZEKAM;
stan_top <= stan_n;
end
endmodule | 0 |
139,757 | data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v | 89,709,715 | mdk.v | v | 295 | 168 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0x9c in position 5713: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:1: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v.v\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:54: Define or directive not defined: \'`m300\'\n parameter CENA_OP1 = `m300; \n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:54: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CENA_OP1 = `m300; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:55: Define or directive not defined: \'`m500\'\n parameter CENA_OP2 = `m500; \n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:55: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CENA_OP2 = `m500; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:56: Define or directive not defined: \'`m750\'\n parameter CENA_OP3 = `m750; \n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:56: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CENA_OP3 = `m750; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:81: Unsupported or unknown PLI call: $strobe\n $strobe("strobe count_secs:%b(%0d) a:%b(%0d) b:%b(%0d) @ %0t", count_secs, count_secs, b[4:0], b[4:0], a[4:0], a[4:0], $time);\n ^~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:88: Define or directive not defined: \'`CMD_RESET\'\n : ... Suggested alternative: \'`SV_COV_RESET\'\n if (panel_przyciskow_in == `CMD_RESET && cmd_in === 2\'bXX) \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:88: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n if (panel_przyciskow_in == `CMD_RESET && cmd_in === 2\'bXX) \n ^~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:93: Define or directive not defined: \'`NIC\'\n urzadzenia = `NIC;\n ^~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:93: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n urzadzenia = `NIC;\n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:94: Define or directive not defined: \'`CMD_RESET\'\n : ... Suggested alternative: \'`SV_COV_RESET\'\n cmd_out = `CMD_RESET; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:94: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n cmd_out = `CMD_RESET; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:95: Define or directive not defined: \'`LICZNIK_RESET\'\n licz_out = `LICZNIK_RESET; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:95: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n licz_out = `LICZNIK_RESET; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:87: Unsupported: Ignoring delay on this delayed statement.\n #1 begin\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:104: Define or directive not defined: \'`CMD_OP1\'\n `CMD_OP1: \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:104: syntax error, unexpected \':\', expecting endcase\n `CMD_OP1: \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:105: Define or directive not defined: \'`ODP_NIC\'\n if(cmd_in == `ODP_NIC) \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:107: Define or directive not defined: \'`CMD_OP1\'\n cmd_out = `CMD_OP1; \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:108: Define or directive not defined: \'`POBIERAM\'\n stan_n = `POBIERAM;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:110: Define or directive not defined: \'`CMD_OP2\'\n `CMD_OP2: \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:111: Define or directive not defined: \'`ODP_NIC\'\n if(cmd_in == `ODP_NIC) \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:113: Define or directive not defined: \'`CMD_OP2\'\n cmd_out = `CMD_OP2; \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:114: Define or directive not defined: \'`POBIERAM\'\n stan_n = `POBIERAM;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:116: Define or directive not defined: \'`CMD_OP3\'\n `CMD_OP3: \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:117: Define or directive not defined: \'`ODP_NIC\'\n if(cmd_in == `ODP_NIC) \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:119: Define or directive not defined: \'`CMD_OP3\'\n cmd_out = `CMD_OP3; \n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:120: Define or directive not defined: \'`POBIERAM\'\n stan_n = `POBIERAM;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:122: Define or directive not defined: \'`CMD_RESET\'\n : ... Suggested alternative: \'`SV_COV_RESET\'\n `CMD_RESET:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:124: Define or directive not defined: \'`PODSTAW_KUBEK\'\n if (stan_top < `PODSTAW_KUBEK) \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:127: Define or directive not defined: \'`CMD_OP1\'\n `CMD_OP1:\n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:129: Define or directive not defined: \'`CMD_RESET1\'\n cmd_out = `CMD_RESET1;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:130: Define or directive not defined: \'`ZWRACAM\'\n stan_n = `ZWRACAM;\n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:132: Define or directive not defined: \'`CMD_OP2\'\n `CMD_OP2:\n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:134: Define or directive not defined: \'`CMD_RESET2\'\n cmd_out = `CMD_RESET2;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:135: Define or directive not defined: \'`ZWRACAM\'\n stan_n = `ZWRACAM;\n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:137: Define or directive not defined: \'`CMD_OP3\'\n `CMD_OP3:\n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:139: Define or directive not defined: \'`CMD_RESET3\'\n cmd_out = `CMD_RESET3;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:140: Define or directive not defined: \'`ZWRACAM\'\n stan_n = `ZWRACAM;\n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:151: Define or directive not defined: \'`SKONCZYLEM_ODLICZAC\'\n if (licz_in == `SKONCZYLEM_ODLICZAC)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:154: Define or directive not defined: \'`NAPELNIJ_PRZEWODY\'\n `NAPELNIJ_PRZEWODY: begin stan_n = `PODSTAW_KUBEK; licz_out <= `ODLICZ_KUBEK; urzadzenia <= `CMD_PODSTAW_KUBEK; end\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:154: Define or directive not defined: \'`PODSTAW_KUBEK\'\n `NAPELNIJ_PRZEWODY: begin stan_n = `PODSTAW_KUBEK; licz_out <= `ODLICZ_KUBEK; urzadzenia <= `CMD_PODSTAW_KUBEK; end\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:154: Define or directive not defined: \'`ODLICZ_KUBEK\'\n `NAPELNIJ_PRZEWODY: begin stan_n = `PODSTAW_KUBEK; licz_out <= `ODLICZ_KUBEK; urzadzenia <= `CMD_PODSTAW_KUBEK; end\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:154: Define or directive not defined: \'`CMD_PODSTAW_KUBEK\'\n `NAPELNIJ_PRZEWODY: begin stan_n = `PODSTAW_KUBEK; licz_out <= `ODLICZ_KUBEK; urzadzenia <= `CMD_PODSTAW_KUBEK; end\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:155: Define or directive not defined: \'`PODSTAW_KUBEK\'\n `PODSTAW_KUBEK: \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:157: Define or directive not defined: \'`ZMIEL_KAWE\'\n stan_n = `ZMIEL_KAWE;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:159: Define or directive not defined: \'`CMD_OP1\'\n `CMD_OP1: begin licz_out <= `ODLICZ_KAWA_OP1; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:159: syntax error, unexpected \':\', expecting endcase\n `CMD_OP1: begin licz_out <= `ODLICZ_KAWA_OP1; end\n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/mdk.v:159: Define or directive not defined: \'`ODLICZ_KAWA_OP1\'\n `CMD_OP1: begin licz_out <= `ODLICZ_KAWA_OP1; end\n ^~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 307,795 | function | function [9:0]licznikNaLiczby;
input reg [6:0] count_secs;
integer a,b;
begin
b = count_secs / 10;
a = count_secs - (b*10);
licznikNaLiczby = {b[4:0],a[4:0]};
$strobe("strobe count_secs:%b(%0d) a:%b(%0d) b:%b(%0d) @ %0t", count_secs, count_secs, b[4:0], b[4:0], a[4:0], a[4:0], $time);
end
endfunction | function [9:0]licznikNaLiczby; |
input reg [6:0] count_secs;
integer a,b;
begin
b = count_secs / 10;
a = count_secs - (b*10);
licznikNaLiczby = {b[4:0],a[4:0]};
$strobe("strobe count_secs:%b(%0d) a:%b(%0d) b:%b(%0d) @ %0t", count_secs, count_secs, b[4:0], b[4:0], a[4:0], a[4:0], $time);
end
endfunction | 0 |
139,758 | data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v | 89,709,715 | modul_monet.v | v | 203 | 132 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0x9c in position 5239: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:1: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v.v\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:62: Define or directive not defined: \'`m300\'\n parameter CENA_OP1 = `m300; \n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:62: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CENA_OP1 = `m300; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:63: Define or directive not defined: \'`m500\'\n parameter CENA_OP2 = `m500; \n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:63: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CENA_OP2 = `m500; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:64: Define or directive not defined: \'`m750\'\n parameter CENA_OP3 = `m750; \n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:64: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CENA_OP3 = `m750; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:75: Define or directive not defined: \'`CMD_OP1\'\n `CMD_OP1:\n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:75: syntax error, unexpected \':\', expecting endcase\n `CMD_OP1:\n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:78: Define or directive not defined: \'`ODP_W_TOKU\'\n cmd_out <= `ODP_W_TOKU;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:78: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n cmd_out <= `ODP_W_TOKU;\n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:80: Define or directive not defined: \'`CMD_OP2\'\n `CMD_OP2:\n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:81: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n begin\n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:83: Define or directive not defined: \'`ODP_W_TOKU\'\n cmd_out <= `ODP_W_TOKU;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n cmd_out <= `ODP_W_TOKU;\n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:85: Define or directive not defined: \'`CMD_OP3\'\n `CMD_OP3:\n ^~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:86: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n begin\n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:88: Define or directive not defined: \'`ODP_W_TOKU\'\n cmd_out <= `ODP_W_TOKU;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:88: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n cmd_out <= `ODP_W_TOKU;\n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:90: Define or directive not defined: \'`CMD_RESET1\'\n `CMD_RESET1: \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:91: syntax error, unexpected if, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n if (cmd_out == `ODP_W_TOKU) \n ^~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:91: Define or directive not defined: \'`ODP_W_TOKU\'\n if (cmd_out == `ODP_W_TOKU) \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:93: Define or directive not defined: \'`ODP_ZWROT\'\n cmd_out <= `ODP_ZWROT; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:96: Define or directive not defined: \'`CMD_RESET2\'\n `CMD_RESET2: \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:97: syntax error, unexpected if, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n if (cmd_out == `ODP_W_TOKU) \n ^~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:97: Define or directive not defined: \'`ODP_W_TOKU\'\n if (cmd_out == `ODP_W_TOKU) \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:99: Define or directive not defined: \'`ODP_ZWROT\'\n cmd_out <= `ODP_ZWROT; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:102: Define or directive not defined: \'`CMD_RESET3\'\n `CMD_RESET3: \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:103: syntax error, unexpected if, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n if (cmd_out == `ODP_W_TOKU) \n ^~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:103: Define or directive not defined: \'`ODP_W_TOKU\'\n if (cmd_out == `ODP_W_TOKU) \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:105: Define or directive not defined: \'`ODP_ZWROT\'\n cmd_out <= `ODP_ZWROT; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:108: Define or directive not defined: \'`CMD_RESET\'\n : ... Suggested alternative: \'`SV_COV_RESET\'\n `CMD_RESET: \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:109: syntax error, unexpected if, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n if (cmd_out === 2\'bxx) \n ^~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:111: Define or directive not defined: \'`NIC\'\n stan = `NIC;\n ^~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:112: Define or directive not defined: \'`NIC\'\n n_stan = `NIC;\n ^~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:112: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n n_stan = `NIC;\n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:115: Define or directive not defined: \'`NIC\'\n tmp = `NIC;\n ^~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:115: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n tmp = `NIC;\n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:122: Define or directive not defined: \'`ODP_ZWROT\'\n `ODP_ZWROT: \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:123: Define or directive not defined: \'`z0g00\'\n if (mon_in != `z0g00) \n ^~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:129: Define or directive not defined: \'`m500\'\n if (stan>`m500) begin \n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:130: Define or directive not defined: \'`z5g00\'\n mon_out <= `z5g00; \n ^~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:131: Define or directive not defined: \'`m500\'\n n_stan <= stan - `m500; \n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:133: Define or directive not defined: \'`m500\'\n else if (stan==`m500) begin \n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:134: Define or directive not defined: \'`z5g00\'\n mon_out <= `z5g00; \n ^~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:135: Define or directive not defined: \'`NIC\'\n n_stan <= `NIC; \n ^~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:136: Define or directive not defined: \'`ODP_OK\'\n cmd_out <= `ODP_OK; \n ^~~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:138: Define or directive not defined: \'`m200\'\n else if (stan>`m200) begin \n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:139: Define or directive not defined: \'`z2g00\'\n mon_out <= `z2g00; \n ^~~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/modul_monet.v:140: Define or directive not defined: \'`m200\'\n n_stan <= stan - `m200; \n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 307,796 | module | module modul_monet(
input wire clk,
input wire [2:0] mon_in,
output reg [2:0] mon_out,
input wire [2:0] cmd_in,
output reg [1:0] cmd_out,
output wire [4:0] stan_mm
);
parameter CENA_OP1 = `m300;
parameter CENA_OP2 = `m500;
parameter CENA_OP3 = `m750;
reg [4:0]stan;
reg [4:0]n_stan;
reg [4:0]tmp;
assign stan_mm = stan;
always @(cmd_in)
begin
n_stan = stan;
case (cmd_in)
`CMD_OP1:
begin
n_stan <= CENA_OP1;
cmd_out <= `ODP_W_TOKU;
end
`CMD_OP2:
begin
n_stan <= CENA_OP2;
cmd_out <= `ODP_W_TOKU;
end
`CMD_OP3:
begin
n_stan <= CENA_OP3;
cmd_out <= `ODP_W_TOKU;
end
`CMD_RESET1:
if (cmd_out == `ODP_W_TOKU)
begin
cmd_out <= `ODP_ZWROT;
n_stan <= CENA_OP1-stan;
end
`CMD_RESET2:
if (cmd_out == `ODP_W_TOKU)
begin
cmd_out <= `ODP_ZWROT;
n_stan <= CENA_OP2-stan;
end
`CMD_RESET3:
if (cmd_out == `ODP_W_TOKU)
begin
cmd_out <= `ODP_ZWROT;
n_stan <= CENA_OP3-stan;
end
`CMD_RESET:
if (cmd_out === 2'bxx)
begin
stan = `NIC;
n_stan = `NIC;
cmd_out = 2'b00;
mon_out = 3'b000;
tmp = `NIC;
end
endcase
end
always @(posedge clk)
begin
case (cmd_out)
`ODP_ZWROT:
if (mon_in != `z0g00)
begin
n_stan <= stan;
mon_out <= mon_in;
end
else begin
if (stan>`m500) begin
mon_out <= `z5g00;
n_stan <= stan - `m500;
end
else if (stan==`m500) begin
mon_out <= `z5g00;
n_stan <= `NIC;
cmd_out <= `ODP_OK;
end
else if (stan>`m200) begin
mon_out <= `z2g00;
n_stan <= stan - `m200;
end
else if (stan == `m200) begin
mon_out <= `z2g00;
n_stan <= `NIC;
cmd_out <= `ODP_OK;
end
else if (stan == `m150) begin
mon_out <= `z1g00;
n_stan <= `m050;
end
else begin
case (stan)
`m050: mon_out <= `z0g50;
`m100: mon_out <= `z1g00;
endcase
n_stan <= `NIC;
cmd_out <= `ODP_OK;
end
end
`ODP_W_TOKU:
begin
case (mon_in)
default: tmp = `NIC;
`z0g50: tmp = `m050;
`z1g00: tmp = `m100;
`z2g00: tmp = `m200;
`z5g00: tmp = `m500;
endcase
if (stan > tmp)
n_stan <= stan - tmp;
else if (stan == tmp)
begin
n_stan <= `NIC;
cmd_out <= `ODP_OK;
end
else
begin
n_stan <= tmp - stan;
cmd_out <= `ODP_ZWROT;
end
end
`ODP_NIC:
if (mon_in != `z0g00)
begin
n_stan <= stan;
mon_out <= mon_in;
end
endcase
end
always @(negedge clk)
begin
#10 begin
if (cmd_out == `ODP_OK) cmd_out <= `ODP_NIC;
if (mon_out != `z0g00) mon_out <= `z0g00;
end
end
always @(*)
#1 begin
stan = n_stan;
end
endmodule | module modul_monet(
input wire clk,
input wire [2:0] mon_in,
output reg [2:0] mon_out,
input wire [2:0] cmd_in,
output reg [1:0] cmd_out,
output wire [4:0] stan_mm
); |
parameter CENA_OP1 = `m300;
parameter CENA_OP2 = `m500;
parameter CENA_OP3 = `m750;
reg [4:0]stan;
reg [4:0]n_stan;
reg [4:0]tmp;
assign stan_mm = stan;
always @(cmd_in)
begin
n_stan = stan;
case (cmd_in)
`CMD_OP1:
begin
n_stan <= CENA_OP1;
cmd_out <= `ODP_W_TOKU;
end
`CMD_OP2:
begin
n_stan <= CENA_OP2;
cmd_out <= `ODP_W_TOKU;
end
`CMD_OP3:
begin
n_stan <= CENA_OP3;
cmd_out <= `ODP_W_TOKU;
end
`CMD_RESET1:
if (cmd_out == `ODP_W_TOKU)
begin
cmd_out <= `ODP_ZWROT;
n_stan <= CENA_OP1-stan;
end
`CMD_RESET2:
if (cmd_out == `ODP_W_TOKU)
begin
cmd_out <= `ODP_ZWROT;
n_stan <= CENA_OP2-stan;
end
`CMD_RESET3:
if (cmd_out == `ODP_W_TOKU)
begin
cmd_out <= `ODP_ZWROT;
n_stan <= CENA_OP3-stan;
end
`CMD_RESET:
if (cmd_out === 2'bxx)
begin
stan = `NIC;
n_stan = `NIC;
cmd_out = 2'b00;
mon_out = 3'b000;
tmp = `NIC;
end
endcase
end
always @(posedge clk)
begin
case (cmd_out)
`ODP_ZWROT:
if (mon_in != `z0g00)
begin
n_stan <= stan;
mon_out <= mon_in;
end
else begin
if (stan>`m500) begin
mon_out <= `z5g00;
n_stan <= stan - `m500;
end
else if (stan==`m500) begin
mon_out <= `z5g00;
n_stan <= `NIC;
cmd_out <= `ODP_OK;
end
else if (stan>`m200) begin
mon_out <= `z2g00;
n_stan <= stan - `m200;
end
else if (stan == `m200) begin
mon_out <= `z2g00;
n_stan <= `NIC;
cmd_out <= `ODP_OK;
end
else if (stan == `m150) begin
mon_out <= `z1g00;
n_stan <= `m050;
end
else begin
case (stan)
`m050: mon_out <= `z0g50;
`m100: mon_out <= `z1g00;
endcase
n_stan <= `NIC;
cmd_out <= `ODP_OK;
end
end
`ODP_W_TOKU:
begin
case (mon_in)
default: tmp = `NIC;
`z0g50: tmp = `m050;
`z1g00: tmp = `m100;
`z2g00: tmp = `m200;
`z5g00: tmp = `m500;
endcase
if (stan > tmp)
n_stan <= stan - tmp;
else if (stan == tmp)
begin
n_stan <= `NIC;
cmd_out <= `ODP_OK;
end
else
begin
n_stan <= tmp - stan;
cmd_out <= `ODP_ZWROT;
end
end
`ODP_NIC:
if (mon_in != `z0g00)
begin
n_stan <= stan;
mon_out <= mon_in;
end
endcase
end
always @(negedge clk)
begin
#10 begin
if (cmd_out == `ODP_OK) cmd_out <= `ODP_NIC;
if (mon_out != `z0g00) mon_out <= `z0g00;
end
end
always @(*)
#1 begin
stan = n_stan;
end
endmodule | 0 |
139,759 | data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/sprawnosc.v | 89,709,715 | sprawnosc.v | v | 19 | 53 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb3 in position 44: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/sprawnosc.v:1: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v.v\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: Exiting due to 1 error(s)\n' | 307,797 | module | module sprawnosc(c_k, p_w, i_k, i_m, p_b, signal_s);
output signal_s;
input c_k, p_w, i_k, i_m, p_b;
assign signal_s = c_k | p_w | i_k | i_m | p_b;
endmodule | module sprawnosc(c_k, p_w, i_k, i_m, p_b, signal_s); |
output signal_s;
input c_k, p_w, i_k, i_m, p_b;
assign signal_s = c_k | p_w | i_k | i_m | p_b;
endmodule | 0 |
139,760 | data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/top.v | 89,709,715 | top.v | v | 84 | 140 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb3 in position 65: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/top.v:2: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v.v\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/top.v:52: Define or directive not defined: \'`m300\'\n parameter CENA_OP1 = `m300; \n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/top.v:52: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CENA_OP1 = `m300; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/top.v:53: Define or directive not defined: \'`m500\'\n parameter CENA_OP2 = `m500; \n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/top.v:53: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CENA_OP2 = `m500; \n ^\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/top.v:54: Define or directive not defined: \'`m750\'\n parameter CENA_OP3 = `m750; \n ^~~~~\n%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/top.v:54: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CENA_OP3 = `m750; \n ^\n%Error: Exiting due to 7 error(s)\n' | 307,798 | module | module top(
input wire [2:0]mon_in,
input wire [2:0]panel_przyciskow_in,
input wire c_k, p_w, i_k, i_m, p_b,
input wire clk,
output wire [2:0] mon_out,
output wire [2:0] urzadzenia,
output wire [3:0] segment_out,
output wire seg_um,
output wire seg_ul,
output wire seg_ur,
output wire seg_mm,
output wire seg_dl,
output wire seg_dr,
output wire seg_dm,
output wire seg_dot
);
wire sprawnosc_out;
sprawnosc spr_test(.c_k(c_k), .p_w(p_w), .i_k(i_k), .i_m(i_m), .p_b(p_b), .signal_s(sprawnosc_out));
wire clk_div;
divider #(1) div(.clk(clk), .clk_div(clk_div));
parameter CENA_OP1 = `m300;
parameter CENA_OP2 = `m500;
parameter CENA_OP3 = `m750;
wire [2:0]cmd_out;
wire [1:0]cmd_in;
wire [4:0]stan_mm;
modul_monet #(.CENA_OP1(CENA_OP1), .CENA_OP2(CENA_OP2), .CENA_OP3(CENA_OP3)) wrzut_zwrot(.clk(clk_div), .cmd_in(cmd_out),
.cmd_out(cmd_in), .stan_mm(stan_mm), .mon_in(mon_in), .mon_out(mon_out));
parameter tick_every = 20;
wire licz_in;
wire [3:0]licz_out;
wire [6:0]count_secs;
counter #(.tick_every(tick_every)) licznik(.clk(clk_div), .count_out(licz_in), .count_in(licz_out), .count_secs(count_secs));
wire [4:0]L_1, L_2, L_3, L_4;
wyswietlacz_4x7seg wys_pan(.clk(clk), .L_1(L_1), .L_2(L_2), .L_3(L_3), .L_4(L_4),
.seg_um(seg_um), .seg_ul(seg_ul), .seg_ur(seg_ur), .seg_mm(seg_mm),
.seg_dm(seg_dm), .seg_dl(seg_dl), .seg_dr(seg_dr), .seg_dot(seg_dot), .segment_out(segment_out));
wire [2:0]u;
mdk_top old_top(.sprawnosc_in(sprawnosc_out), .panel_przyciskow_in(panel_przyciskow_in), .clk_div(clk_div),
.cmd_out(cmd_out), .cmd_in(cmd_in), .stan_mm(stan_mm), .licz_in(licz_in), .licz_out(licz_out), .count_secs(count_secs),
.L_1(L_1), .L_2(L_2), .L_3(L_3), .L_4(L_4),
.urzadzenia(urzadzenia) );
endmodule | module top(
input wire [2:0]mon_in,
input wire [2:0]panel_przyciskow_in,
input wire c_k, p_w, i_k, i_m, p_b,
input wire clk,
output wire [2:0] mon_out,
output wire [2:0] urzadzenia,
output wire [3:0] segment_out,
output wire seg_um,
output wire seg_ul,
output wire seg_ur,
output wire seg_mm,
output wire seg_dl,
output wire seg_dr,
output wire seg_dm,
output wire seg_dot
); |
wire sprawnosc_out;
sprawnosc spr_test(.c_k(c_k), .p_w(p_w), .i_k(i_k), .i_m(i_m), .p_b(p_b), .signal_s(sprawnosc_out));
wire clk_div;
divider #(1) div(.clk(clk), .clk_div(clk_div));
parameter CENA_OP1 = `m300;
parameter CENA_OP2 = `m500;
parameter CENA_OP3 = `m750;
wire [2:0]cmd_out;
wire [1:0]cmd_in;
wire [4:0]stan_mm;
modul_monet #(.CENA_OP1(CENA_OP1), .CENA_OP2(CENA_OP2), .CENA_OP3(CENA_OP3)) wrzut_zwrot(.clk(clk_div), .cmd_in(cmd_out),
.cmd_out(cmd_in), .stan_mm(stan_mm), .mon_in(mon_in), .mon_out(mon_out));
parameter tick_every = 20;
wire licz_in;
wire [3:0]licz_out;
wire [6:0]count_secs;
counter #(.tick_every(tick_every)) licznik(.clk(clk_div), .count_out(licz_in), .count_in(licz_out), .count_secs(count_secs));
wire [4:0]L_1, L_2, L_3, L_4;
wyswietlacz_4x7seg wys_pan(.clk(clk), .L_1(L_1), .L_2(L_2), .L_3(L_3), .L_4(L_4),
.seg_um(seg_um), .seg_ul(seg_ul), .seg_ur(seg_ur), .seg_mm(seg_mm),
.seg_dm(seg_dm), .seg_dl(seg_dl), .seg_dr(seg_dr), .seg_dot(seg_dot), .segment_out(segment_out));
wire [2:0]u;
mdk_top old_top(.sprawnosc_in(sprawnosc_out), .panel_przyciskow_in(panel_przyciskow_in), .clk_div(clk_div),
.cmd_out(cmd_out), .cmd_in(cmd_in), .stan_mm(stan_mm), .licz_in(licz_in), .licz_out(licz_out), .count_secs(count_secs),
.L_1(L_1), .L_2(L_2), .L_3(L_3), .L_4(L_4),
.urzadzenia(urzadzenia) );
endmodule | 0 |
139,761 | data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/wyswietlacz_4x7seg.v | 89,709,715 | wyswietlacz_4x7seg.v | v | 83 | 200 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb3 in position 44: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/wyswietlacz_4x7seg.v:1: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v.v\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: Exiting due to 1 error(s)\n' | 307,799 | module | module wyswietlacz_4x7seg(
input wire clk,
input wire [4:0] L_1,
input wire [4:0] L_2,
input wire [4:0] L_3,
input wire [4:0] L_4,
output reg [3:0] segment_out,
output reg seg_um,
output reg seg_ul,
output reg seg_ur,
output reg seg_mm,
output reg seg_dl,
output reg seg_dr,
output reg seg_dm,
output reg seg_dot
);
function [7:0]liczbaNAsygnaly;
input [4:0]liczba;
begin
case (liczba[3:0])
default: liczbaNAsygnaly = ~8'b00000000;
4'b0000: liczbaNAsygnaly = ~{liczba[4:4],7'b1110111};
4'b0001: liczbaNAsygnaly = ~{liczba[4:4],7'b0010010};
4'b0010: liczbaNAsygnaly = ~{liczba[4:4],7'b1011101};
4'b0011: liczbaNAsygnaly = ~{liczba[4:4],7'b1011011};
4'b0100: liczbaNAsygnaly = ~{liczba[4:4],7'b0111010};
4'b0101: liczbaNAsygnaly = ~{liczba[4:4],7'b1101011};
4'b0110: liczbaNAsygnaly = ~{liczba[4:4],7'b1101111};
4'b0111: liczbaNAsygnaly = ~{liczba[4:4],7'b1010010};
4'b1000: liczbaNAsygnaly = ~{liczba[4:4],7'b1111111};
4'b1001: liczbaNAsygnaly = ~{liczba[4:4],7'b1111011};
4'b1010: liczbaNAsygnaly = ~{liczba[4:4],7'b0001000};
4'b1011: liczbaNAsygnaly = ~{liczba[4:4],7'b1000000};
4'b1100: liczbaNAsygnaly = ~{liczba[4:4],7'b0010000};
4'b1101: liczbaNAsygnaly = ~{liczba[4:4],7'b0001000};
4'b1110: liczbaNAsygnaly = ~{liczba[4:4],7'b0100000};
4'b1111: liczbaNAsygnaly = ~{liczba[4:4],7'b0000000};
endcase
end
endfunction
always @(negedge clk)
begin
case (segment_out)
default: begin segment_out <= ~4'b0001; {seg_dot,seg_um,seg_ul,seg_ur,seg_mm,seg_dl,seg_dr,seg_dm} <= liczbaNAsygnaly(L_1); end
4'b1110: begin segment_out <= ~4'b0010; {seg_dot,seg_um,seg_ul,seg_ur,seg_mm,seg_dl,seg_dr,seg_dm} <= liczbaNAsygnaly(L_2); end
4'b1101: begin segment_out <= ~4'b0100; {seg_dot,seg_um,seg_ul,seg_ur,seg_mm,seg_dl,seg_dr,seg_dm} <= liczbaNAsygnaly(L_3); end
4'b1011: begin segment_out <= ~4'b1000; {seg_dot,seg_um,seg_ul,seg_ur,seg_mm,seg_dl,seg_dr,seg_dm} <= liczbaNAsygnaly(L_4); end
4'b0111: begin segment_out <= ~4'b0001; {seg_dot,seg_um,seg_ul,seg_ur,seg_mm,seg_dl,seg_dr,seg_dm} <= liczbaNAsygnaly(L_1); end
endcase
end
endmodule | module wyswietlacz_4x7seg(
input wire clk,
input wire [4:0] L_1,
input wire [4:0] L_2,
input wire [4:0] L_3,
input wire [4:0] L_4,
output reg [3:0] segment_out,
output reg seg_um,
output reg seg_ul,
output reg seg_ur,
output reg seg_mm,
output reg seg_dl,
output reg seg_dr,
output reg seg_dm,
output reg seg_dot
); |
function [7:0]liczbaNAsygnaly;
input [4:0]liczba;
begin
case (liczba[3:0])
default: liczbaNAsygnaly = ~8'b00000000;
4'b0000: liczbaNAsygnaly = ~{liczba[4:4],7'b1110111};
4'b0001: liczbaNAsygnaly = ~{liczba[4:4],7'b0010010};
4'b0010: liczbaNAsygnaly = ~{liczba[4:4],7'b1011101};
4'b0011: liczbaNAsygnaly = ~{liczba[4:4],7'b1011011};
4'b0100: liczbaNAsygnaly = ~{liczba[4:4],7'b0111010};
4'b0101: liczbaNAsygnaly = ~{liczba[4:4],7'b1101011};
4'b0110: liczbaNAsygnaly = ~{liczba[4:4],7'b1101111};
4'b0111: liczbaNAsygnaly = ~{liczba[4:4],7'b1010010};
4'b1000: liczbaNAsygnaly = ~{liczba[4:4],7'b1111111};
4'b1001: liczbaNAsygnaly = ~{liczba[4:4],7'b1111011};
4'b1010: liczbaNAsygnaly = ~{liczba[4:4],7'b0001000};
4'b1011: liczbaNAsygnaly = ~{liczba[4:4],7'b1000000};
4'b1100: liczbaNAsygnaly = ~{liczba[4:4],7'b0010000};
4'b1101: liczbaNAsygnaly = ~{liczba[4:4],7'b0001000};
4'b1110: liczbaNAsygnaly = ~{liczba[4:4],7'b0100000};
4'b1111: liczbaNAsygnaly = ~{liczba[4:4],7'b0000000};
endcase
end
endfunction
always @(negedge clk)
begin
case (segment_out)
default: begin segment_out <= ~4'b0001; {seg_dot,seg_um,seg_ul,seg_ur,seg_mm,seg_dl,seg_dr,seg_dm} <= liczbaNAsygnaly(L_1); end
4'b1110: begin segment_out <= ~4'b0010; {seg_dot,seg_um,seg_ul,seg_ur,seg_mm,seg_dl,seg_dr,seg_dm} <= liczbaNAsygnaly(L_2); end
4'b1101: begin segment_out <= ~4'b0100; {seg_dot,seg_um,seg_ul,seg_ur,seg_mm,seg_dl,seg_dr,seg_dm} <= liczbaNAsygnaly(L_3); end
4'b1011: begin segment_out <= ~4'b1000; {seg_dot,seg_um,seg_ul,seg_ur,seg_mm,seg_dl,seg_dr,seg_dm} <= liczbaNAsygnaly(L_4); end
4'b0111: begin segment_out <= ~4'b0001; {seg_dot,seg_um,seg_ul,seg_ur,seg_mm,seg_dl,seg_dr,seg_dm} <= liczbaNAsygnaly(L_1); end
endcase
end
endmodule | 0 |
139,762 | data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/wyswietlacz_4x7seg.v | 89,709,715 | wyswietlacz_4x7seg.v | v | 83 | 200 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb3 in position 44: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new/wyswietlacz_4x7seg.v:1: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v.v\n data/full_repos/permissive/89709715/Maszyna_do_kawy.srcs/sources_1/new,data/full_repos/permissive/89709715/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: Exiting due to 1 error(s)\n' | 307,799 | function | function [7:0]liczbaNAsygnaly;
input [4:0]liczba;
begin
case (liczba[3:0])
default: liczbaNAsygnaly = ~8'b00000000;
4'b0000: liczbaNAsygnaly = ~{liczba[4:4],7'b1110111};
4'b0001: liczbaNAsygnaly = ~{liczba[4:4],7'b0010010};
4'b0010: liczbaNAsygnaly = ~{liczba[4:4],7'b1011101};
4'b0011: liczbaNAsygnaly = ~{liczba[4:4],7'b1011011};
4'b0100: liczbaNAsygnaly = ~{liczba[4:4],7'b0111010};
4'b0101: liczbaNAsygnaly = ~{liczba[4:4],7'b1101011};
4'b0110: liczbaNAsygnaly = ~{liczba[4:4],7'b1101111};
4'b0111: liczbaNAsygnaly = ~{liczba[4:4],7'b1010010};
4'b1000: liczbaNAsygnaly = ~{liczba[4:4],7'b1111111};
4'b1001: liczbaNAsygnaly = ~{liczba[4:4],7'b1111011};
4'b1010: liczbaNAsygnaly = ~{liczba[4:4],7'b0001000};
4'b1011: liczbaNAsygnaly = ~{liczba[4:4],7'b1000000};
4'b1100: liczbaNAsygnaly = ~{liczba[4:4],7'b0010000};
4'b1101: liczbaNAsygnaly = ~{liczba[4:4],7'b0001000};
4'b1110: liczbaNAsygnaly = ~{liczba[4:4],7'b0100000};
4'b1111: liczbaNAsygnaly = ~{liczba[4:4],7'b0000000};
endcase
end
endfunction | function [7:0]liczbaNAsygnaly; |
input [4:0]liczba;
begin
case (liczba[3:0])
default: liczbaNAsygnaly = ~8'b00000000;
4'b0000: liczbaNAsygnaly = ~{liczba[4:4],7'b1110111};
4'b0001: liczbaNAsygnaly = ~{liczba[4:4],7'b0010010};
4'b0010: liczbaNAsygnaly = ~{liczba[4:4],7'b1011101};
4'b0011: liczbaNAsygnaly = ~{liczba[4:4],7'b1011011};
4'b0100: liczbaNAsygnaly = ~{liczba[4:4],7'b0111010};
4'b0101: liczbaNAsygnaly = ~{liczba[4:4],7'b1101011};
4'b0110: liczbaNAsygnaly = ~{liczba[4:4],7'b1101111};
4'b0111: liczbaNAsygnaly = ~{liczba[4:4],7'b1010010};
4'b1000: liczbaNAsygnaly = ~{liczba[4:4],7'b1111111};
4'b1001: liczbaNAsygnaly = ~{liczba[4:4],7'b1111011};
4'b1010: liczbaNAsygnaly = ~{liczba[4:4],7'b0001000};
4'b1011: liczbaNAsygnaly = ~{liczba[4:4],7'b1000000};
4'b1100: liczbaNAsygnaly = ~{liczba[4:4],7'b0010000};
4'b1101: liczbaNAsygnaly = ~{liczba[4:4],7'b0001000};
4'b1110: liczbaNAsygnaly = ~{liczba[4:4],7'b0100000};
4'b1111: liczbaNAsygnaly = ~{liczba[4:4],7'b0000000};
endcase
end
endfunction | 0 |
139,763 | data/full_repos/permissive/89791545/sim/detect_button_tb.v | 89,791,545 | detect_button_tb.v | v | 37 | 36 | [] | [] | [] | [(3, 36)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/89791545/sim/detect_button_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #5 tb_clk <= ~tb_clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/89791545/sim/detect_button_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #100 tb_button <= ~tb_button;\n ^\n%Error: data/full_repos/permissive/89791545/sim/detect_button_tb.v:11: Cannot find file containing module: \'detect_button\'\ndetect_button dbi_0(\n^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89791545/sim,data/full_repos/permissive/89791545/detect_button\n data/full_repos/permissive/89791545/sim,data/full_repos/permissive/89791545/detect_button.v\n data/full_repos/permissive/89791545/sim,data/full_repos/permissive/89791545/detect_button.sv\n detect_button\n detect_button.v\n detect_button.sv\n obj_dir/detect_button\n obj_dir/detect_button.v\n obj_dir/detect_button.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 307,800 | module | module detect_button_tb();
reg tb_clk;
reg tb_rst;
reg tb_button;
wire tb_pressed;
detect_button dbi_0(
.clk(tb_clk),
.init(1'b1),
.button(tb_button),
.pressed(tb_pressed)
);
initial
begin
tb_clk <= 1'b0;
tb_rst <= 1'b0;
tb_button <= 1'b0;
end
always
begin
#5 tb_clk <= ~tb_clk;
end
always
begin
#100 tb_button <= ~tb_button;
end
endmodule | module detect_button_tb(); |
reg tb_clk;
reg tb_rst;
reg tb_button;
wire tb_pressed;
detect_button dbi_0(
.clk(tb_clk),
.init(1'b1),
.button(tb_button),
.pressed(tb_pressed)
);
initial
begin
tb_clk <= 1'b0;
tb_rst <= 1'b0;
tb_button <= 1'b0;
end
always
begin
#5 tb_clk <= ~tb_clk;
end
always
begin
#100 tb_button <= ~tb_button;
end
endmodule | 0 |
139,764 | data/full_repos/permissive/89791545/sim/toggle_led_tb.v | 89,791,545 | toggle_led_tb.v | v | 37 | 36 | [] | [] | [] | [(3, 36)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/89791545/sim/toggle_led_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #5 tb_clk <= ~tb_clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/89791545/sim/toggle_led_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #100 tb_toggle <= ~tb_toggle;\n ^\n%Error: data/full_repos/permissive/89791545/sim/toggle_led_tb.v:11: Cannot find file containing module: \'toggle_led\'\ntoggle_led tli_0(\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89791545/sim,data/full_repos/permissive/89791545/toggle_led\n data/full_repos/permissive/89791545/sim,data/full_repos/permissive/89791545/toggle_led.v\n data/full_repos/permissive/89791545/sim,data/full_repos/permissive/89791545/toggle_led.sv\n toggle_led\n toggle_led.v\n toggle_led.sv\n obj_dir/toggle_led\n obj_dir/toggle_led.v\n obj_dir/toggle_led.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 307,801 | module | module toggle_led_tb();
reg tb_clk;
reg tb_rst;
reg tb_toggle;
wire tb_value;
toggle_led tli_0(
.clk(tb_clk),
.rst(tb_rst),
.toggle(tb_toggle),
.value(tb_value)
);
initial
begin
tb_clk <= 1'b0;
tb_rst <= 1'b0;
tb_toggle <= 1'b0;
end
always
begin
#5 tb_clk <= ~tb_clk;
end
always
begin
#100 tb_toggle <= ~tb_toggle;
end
endmodule | module toggle_led_tb(); |
reg tb_clk;
reg tb_rst;
reg tb_toggle;
wire tb_value;
toggle_led tli_0(
.clk(tb_clk),
.rst(tb_rst),
.toggle(tb_toggle),
.value(tb_value)
);
initial
begin
tb_clk <= 1'b0;
tb_rst <= 1'b0;
tb_toggle <= 1'b0;
end
always
begin
#5 tb_clk <= ~tb_clk;
end
always
begin
#100 tb_toggle <= ~tb_toggle;
end
endmodule | 0 |
139,765 | data/full_repos/permissive/89791545/sim/top_tb.v | 89,791,545 | top_tb.v | v | 50 | 36 | [] | [] | [] | [(3, 49)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/89791545/sim/top_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #5 tb_clk <= ~tb_clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/89791545/sim/top_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #100 tb_button <= ~tb_button;\n ^\n%Error: data/full_repos/permissive/89791545/sim/top_tb.v:11: Cannot find file containing module: \'detect_button\'\ndetect_button dbi_0(\n^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89791545/sim,data/full_repos/permissive/89791545/detect_button\n data/full_repos/permissive/89791545/sim,data/full_repos/permissive/89791545/detect_button.v\n data/full_repos/permissive/89791545/sim,data/full_repos/permissive/89791545/detect_button.sv\n detect_button\n detect_button.v\n detect_button.sv\n obj_dir/detect_button\n obj_dir/detect_button.v\n obj_dir/detect_button.sv\n%Error: data/full_repos/permissive/89791545/sim/top_tb.v:21: Cannot find file containing module: \'toggle_led\'\ntoggle_led tli_0(\n^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 307,802 | module | module ledgame_tb();
reg tb_clk;
reg tb_rst;
reg tb_button;
wire tb_pressed;
detect_button dbi_0(
.clk(tb_clk),
.button(tb_button),
.pressed(tb_pressed)
);
wire tb_toggle;
wire tb_value;
toggle_led tli_0(
.clk(tb_clk),
.rst(tb_rst),
.toggle(tb_toggle),
.value(tb_value)
);
assign tb_toggle = tb_pressed;
initial
begin
tb_clk <= 1'b0;
tb_rst <= 1'b0;
tb_button <= 1'b0;
end
always
begin
#5 tb_clk <= ~tb_clk;
end
always
begin
#100 tb_button <= ~tb_button;
end
endmodule | module ledgame_tb(); |
reg tb_clk;
reg tb_rst;
reg tb_button;
wire tb_pressed;
detect_button dbi_0(
.clk(tb_clk),
.button(tb_button),
.pressed(tb_pressed)
);
wire tb_toggle;
wire tb_value;
toggle_led tli_0(
.clk(tb_clk),
.rst(tb_rst),
.toggle(tb_toggle),
.value(tb_value)
);
assign tb_toggle = tb_pressed;
initial
begin
tb_clk <= 1'b0;
tb_rst <= 1'b0;
tb_button <= 1'b0;
end
always
begin
#5 tb_clk <= ~tb_clk;
end
always
begin
#100 tb_button <= ~tb_button;
end
endmodule | 0 |
139,766 | data/full_repos/permissive/89791545/src/detect_button.v | 89,791,545 | detect_button.v | v | 31 | 29 | [] | [] | [] | [(2, 30)] | null | data/verilator_xmls/2fa84659-9a3e-4490-ada2-1a0e05d3eff5.xml | null | 307,803 | module | module detect_button (
input wire clk,
input wire init,
input wire button,
output reg [0:0] pressed
);
reg [0:0] updown = 1'b0;
reg [0:0] start = 1'b1;
always @(posedge clk)
begin
pressed <= 1'b0;
start <= 1'b0;
if (start == 1'b1)
begin
updown <= init;
pressed <= init;
end
if (button != updown)
begin
updown <= button;
pressed <= button;
end
end
endmodule | module detect_button (
input wire clk,
input wire init,
input wire button,
output reg [0:0] pressed
); |
reg [0:0] updown = 1'b0;
reg [0:0] start = 1'b1;
always @(posedge clk)
begin
pressed <= 1'b0;
start <= 1'b0;
if (start == 1'b1)
begin
updown <= init;
pressed <= init;
end
if (button != updown)
begin
updown <= button;
pressed <= button;
end
end
endmodule | 0 |
139,767 | data/full_repos/permissive/89791545/src/toggle_led.v | 89,791,545 | toggle_led.v | v | 26 | 27 | [] | [] | [] | null | line:6: before: "=" | data/verilator_xmls/37fa9cd1-af7c-43a1-bb4b-386551c6316b.xml | null | 307,804 | module | module toggle_led (
input wire clk,
input wire rst,
input wire toggle,
output reg value= 1'b0
);
reg led = 1'b0;
always @(posedge clk)
begin
value <= led;
if (rst)
begin
led <= 1'b0;
end
else if (toggle)
begin
led <= ~led;
end
end
endmodule | module toggle_led (
input wire clk,
input wire rst,
input wire toggle,
output reg value= 1'b0
); |
reg led = 1'b0;
always @(posedge clk)
begin
value <= led;
if (rst)
begin
led <= 1'b0;
end
else if (toggle)
begin
led <= ~led;
end
end
endmodule | 0 |
139,768 | data/full_repos/permissive/89791545/src/top.v | 89,791,545 | top.v | v | 92 | 80 | [] | ['mit license'] | [] | [(10, 91)] | null | null | 1: b"%Error: data/full_repos/permissive/89791545/src/top.v:29: Cannot find file containing module: 'detect_button'\ndetect_button dbi_0(\n^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89791545/src,data/full_repos/permissive/89791545/detect_button\n data/full_repos/permissive/89791545/src,data/full_repos/permissive/89791545/detect_button.v\n data/full_repos/permissive/89791545/src,data/full_repos/permissive/89791545/detect_button.sv\n detect_button\n detect_button.v\n detect_button.sv\n obj_dir/detect_button\n obj_dir/detect_button.v\n obj_dir/detect_button.sv\n%Error: data/full_repos/permissive/89791545/src/top.v:36: Cannot find file containing module: 'detect_button'\ndetect_button dbi_1(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89791545/src/top.v:43: Cannot find file containing module: 'detect_button'\ndetect_button dbi_2(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89791545/src/top.v:50: Cannot find file containing module: 'detect_button'\ndetect_button dbi_3(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/89791545/src/top.v:57: Cannot find file containing module: 'toggle_led'\ntoggle_led tli_0(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/89791545/src/top.v:64: Cannot find file containing module: 'toggle_led'\ntoggle_led tli_1(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/89791545/src/top.v:71: Cannot find file containing module: 'toggle_led'\ntoggle_led tli_2(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/89791545/src/top.v:78: Cannot find file containing module: 'toggle_led'\ntoggle_led tli_3(\n^~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n" | 307,805 | module | module ledgame(
input wire clk,
input wire [3:0] btn,
output wire [3:0] led
);
wire [3:0] pressed;
wire [3:0] toggle;
assign toggle[0] = pressed[0] || pressed[1];
assign toggle[1] = pressed[1] || pressed[2];
assign toggle[2] = pressed[2] || pressed[3];
assign toggle[3] = pressed[3] || pressed[0];
detect_button dbi_0(
.clk(clk),
.init(1'b0),
.button(btn[0]),
.pressed(pressed[0])
);
detect_button dbi_1(
.clk(clk),
.init(1'b1),
.button(btn[1]),
.pressed(pressed[1])
);
detect_button dbi_2(
.clk(clk),
.init(1'b1),
.button(btn[2]),
.pressed(pressed[2])
);
detect_button dbi_3(
.clk(clk),
.init(1'b0),
.button(btn[3]),
.pressed(pressed[3])
);
toggle_led tli_0(
.clk(clk),
.rst(rst),
.toggle(toggle[0]),
.value(led[0])
);
toggle_led tli_1(
.clk(clk),
.rst(rst),
.toggle(toggle[1]),
.value(led[1])
);
toggle_led tli_2(
.clk(clk),
.rst(rst),
.toggle(toggle[2]),
.value(led[2])
);
toggle_led tli_3(
.clk(clk),
.rst(rst),
.toggle(toggle[3]),
.value(led[3])
);
always @(posedge clk)
begin
end
endmodule | module ledgame(
input wire clk,
input wire [3:0] btn,
output wire [3:0] led
); |
wire [3:0] pressed;
wire [3:0] toggle;
assign toggle[0] = pressed[0] || pressed[1];
assign toggle[1] = pressed[1] || pressed[2];
assign toggle[2] = pressed[2] || pressed[3];
assign toggle[3] = pressed[3] || pressed[0];
detect_button dbi_0(
.clk(clk),
.init(1'b0),
.button(btn[0]),
.pressed(pressed[0])
);
detect_button dbi_1(
.clk(clk),
.init(1'b1),
.button(btn[1]),
.pressed(pressed[1])
);
detect_button dbi_2(
.clk(clk),
.init(1'b1),
.button(btn[2]),
.pressed(pressed[2])
);
detect_button dbi_3(
.clk(clk),
.init(1'b0),
.button(btn[3]),
.pressed(pressed[3])
);
toggle_led tli_0(
.clk(clk),
.rst(rst),
.toggle(toggle[0]),
.value(led[0])
);
toggle_led tli_1(
.clk(clk),
.rst(rst),
.toggle(toggle[1]),
.value(led[1])
);
toggle_led tli_2(
.clk(clk),
.rst(rst),
.toggle(toggle[2]),
.value(led[2])
);
toggle_led tli_3(
.clk(clk),
.rst(rst),
.toggle(toggle[3]),
.value(led[3])
);
always @(posedge clk)
begin
end
endmodule | 0 |
139,769 | data/full_repos/permissive/89810125/system.v | 89,810,125 | system.v | v | 492 | 96 | [] | [] | [] | [(7, 491)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/system.v:490: Signal definition not found, creating implicitly: \'led1\'\n : ... Suggested alternative: \'led\'\nassign led = led1;\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/89810125/system.v:151: Cannot find file containing module: \'wb_conbus_top\'\nwb_conbus_top #(\n^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/89810125,data/full_repos/permissive/89810125/wb_conbus_top\n data/full_repos/permissive/89810125,data/full_repos/permissive/89810125/wb_conbus_top.v\n data/full_repos/permissive/89810125,data/full_repos/permissive/89810125/wb_conbus_top.sv\n wb_conbus_top\n wb_conbus_top.v\n wb_conbus_top.sv\n obj_dir/wb_conbus_top\n obj_dir/wb_conbus_top.v\n obj_dir/wb_conbus_top.sv\n%Error: data/full_repos/permissive/89810125/system.v:313: Cannot find file containing module: \'lm32_cpu\'\nlm32_cpu lm0 (\n^~~~~~~~\n%Error: data/full_repos/permissive/89810125/system.v:350: Cannot find file containing module: \'wb_bram\'\nwb_bram #(\n^~~~~~~\n%Error: data/full_repos/permissive/89810125/system.v:396: Cannot find file containing module: \'wb_timer\'\nwb_timer #(\n^~~~~~~~\n%Error: data/full_repos/permissive/89810125/system.v:419: Cannot find file containing module: \'wb_gpion\'\nwb_gpion gpion0 (\n^~~~~~~~\n%Error: data/full_repos/permissive/89810125/system.v:441: Cannot find file containing module: \'wb_lcd\'\nwb_lcd lcd0 (\n^~~~~~\n%Error: data/full_repos/permissive/89810125/system.v:463: Cannot find file containing module: \'wb_sintesis\'\nwb_sintesis sintesis0 (\n^~~~~~~~~~~\n%Error: Exiting due to 7 error(s), 1 warning(s)\n' | 307,806 | module | module system
#(
parameter bootram_file = "../firmware/hw-test/image.ram",
parameter clk_freq = 50000000,
parameter uart_baud_rate = 57600
) (
input clk,
output led,
input rst,
input uart_rxd,
output uart_txd,
input [10:0] gpio_entrada,
output [6:0] gpio_salida,
input [12:0] addr,
input [7:0] sram_data,
input nwe,
input noe,
input ncs
);
wire gnd = 1'b0;
wire [3:0] gnd4 = 4'h0;
wire [31:0] gnd32 = 32'h00000000;
wire [31:0] lm32i_adr,
lm32d_adr,
uart0_adr,
timer0_adr,
gpion0_adr,
bram0_adr,
sram0_adr,
lcd0_adr,
sintesis0_adr;
wire [31:0] lm32i_dat_r,
lm32i_dat_w,
lm32d_dat_r,
lm32d_dat_w,
uart0_dat_r,
uart0_dat_w,
timer0_dat_r,
timer0_dat_w,
gpion0_dat_r,
gpion0_dat_w,
bram0_dat_r,
bram0_dat_w,
sram0_dat_w,
sram0_dat_r,
lcd0_dat_w,
lcd0_dat_r,
sintesis0_dat_w,
sintesis0_dat_r;
wire [3:0] lm32i_sel,
lm32d_sel,
uart0_sel,
timer0_sel,
gpion0_sel,
bram0_sel,
sram0_sel,
lcd0_sel,
sintesis0_sel;
wire lm32i_we,
lm32d_we,
uart0_we,
timer0_we,
gpion0_we,
bram0_we,
sram0_we,
lcd0_we,
sintesis0_we;
wire lm32i_cyc,
lm32d_cyc,
uart0_cyc,
timer0_cyc,
gpion0_cyc,
bram0_cyc,
sram0_cyc,
lcd0_cyc,
sintesis0_cyc;
wire lm32i_stb,
lm32d_stb,
uart0_stb,
timer0_stb,
gpion0_stb,
bram0_stb,
sram0_stb,
lcd0_stb,
sintesis0_stb;
wire lm32i_ack,
lm32d_ack,
uart0_ack,
timer0_ack,
gpion0_ack,
bram0_ack,
sram0_ack,
lcd0_ack,
sintesis0_ack;
wire lm32i_rty,
lm32d_rty;
wire lm32i_err,
lm32d_err;
wire lm32i_lock,
lm32d_lock;
wire [2:0] lm32i_cti,
lm32d_cti;
wire [1:0] lm32i_bte,
lm32d_bte;
wire [31:0] intr_n;
wire uart0_intr = 0;
wire [1:0] timer0_intr;
wire gpion0_intr;
assign intr_n = { 28'hFFFFFFF, ~timer0_intr[1], ~uart0_intr, ~timer0_intr[0], ~gpion0_intr };
wb_conbus_top #(
.s0_addr_w ( 3 ),
.s0_addr ( 3'h4 ),
.s1_addr_w ( 3 ),
.s1_addr ( 3'h5 ),
.s27_addr_w( 15 ),
.s2_addr ( 15'h0000 ),
.s3_addr ( 15'h7000 ),
.s4_addr ( 15'h7001 ),
.s5_addr ( 15'h7002 ),
.s6_addr ( 15'h7003 ),
.s7_addr ( 15'h7004 )
) conmax0 (
.clk_i( clk ),
.rst_i( ~rst ),
.m0_dat_i( lm32i_dat_w ),
.m0_dat_o( lm32i_dat_r ),
.m0_adr_i( lm32i_adr ),
.m0_we_i ( lm32i_we ),
.m0_sel_i( lm32i_sel ),
.m0_cyc_i( lm32i_cyc ),
.m0_stb_i( lm32i_stb ),
.m0_ack_o( lm32i_ack ),
.m0_rty_o( lm32i_rty ),
.m0_err_o( lm32i_err ),
.m1_dat_i( lm32d_dat_w ),
.m1_dat_o( lm32d_dat_r ),
.m1_adr_i( lm32d_adr ),
.m1_we_i ( lm32d_we ),
.m1_sel_i( lm32d_sel ),
.m1_cyc_i( lm32d_cyc ),
.m1_stb_i( lm32d_stb ),
.m1_ack_o( lm32d_ack ),
.m1_rty_o( lm32d_rty ),
.m1_err_o( lm32d_err ),
.m2_dat_i( gnd32 ),
.m2_adr_i( gnd32 ),
.m2_sel_i( gnd4 ),
.m2_cyc_i( gnd ),
.m2_stb_i( gnd ),
.m3_dat_i( gnd32 ),
.m3_adr_i( gnd32 ),
.m3_sel_i( gnd4 ),
.m3_cyc_i( gnd ),
.m3_stb_i( gnd ),
.m4_dat_i( gnd32 ),
.m4_adr_i( gnd32 ),
.m4_sel_i( gnd4 ),
.m4_cyc_i( gnd ),
.m4_stb_i( gnd ),
.m5_dat_i( gnd32 ),
.m5_adr_i( gnd32 ),
.m5_sel_i( gnd4 ),
.m5_cyc_i( gnd ),
.m5_stb_i( gnd ),
.m6_dat_i( gnd32 ),
.m6_adr_i( gnd32 ),
.m6_sel_i( gnd4 ),
.m6_cyc_i( gnd ),
.m6_stb_i( gnd ),
.m7_dat_i( gnd32 ),
.m7_adr_i( gnd32 ),
.m7_sel_i( gnd4 ),
.m7_cyc_i( gnd ),
.m7_stb_i( gnd ),
.s0_dat_i( sram0_dat_r ),
.s0_dat_o( sram0_dat_w ),
.s0_adr_o( sram0_adr ),
.s0_sel_o( sram0_sel ),
.s0_we_o( sram0_we ),
.s0_cyc_o( sram0_cyc ),
.s0_stb_o( sram0_stb ),
.s0_ack_i( sram0_ack ),
.s0_err_i( gnd ),
.s0_rty_i( gnd ),
.s1_dat_i( gnd32 ),
.s1_ack_i( gnd ),
.s1_err_i( gnd ),
.s1_rty_i( gnd ),
.s2_dat_i( bram0_dat_r ),
.s2_dat_o( bram0_dat_w ),
.s2_adr_o( bram0_adr ),
.s2_sel_o( bram0_sel ),
.s2_we_o( bram0_we ),
.s2_cyc_o( bram0_cyc ),
.s2_stb_o( bram0_stb ),
.s2_ack_i( bram0_ack ),
.s2_err_i( gnd ),
.s2_rty_i( gnd ),
.s3_dat_i( uart0_dat_r ),
.s3_dat_o( uart0_dat_w ),
.s3_adr_o( uart0_adr ),
.s3_sel_o( uart0_sel ),
.s3_we_o( uart0_we ),
.s3_cyc_o( uart0_cyc ),
.s3_stb_o( uart0_stb ),
.s3_ack_i( uart0_ack ),
.s3_err_i( gnd ),
.s3_rty_i( gnd ),
.s4_dat_i( timer0_dat_r ),
.s4_dat_o( timer0_dat_w ),
.s4_adr_o( timer0_adr ),
.s4_sel_o( timer0_sel ),
.s4_we_o( timer0_we ),
.s4_cyc_o( timer0_cyc ),
.s4_stb_o( timer0_stb ),
.s4_ack_i( timer0_ack ),
.s4_err_i( gnd ),
.s4_rty_i( gnd ),
.s5_dat_i( gpion0_dat_r ),
.s5_dat_o( gpion0_dat_w ),
.s5_adr_o( gpion0_adr ),
.s5_sel_o( gpion0_sel ),
.s5_we_o( gpion0_we ),
.s5_cyc_o( gpion0_cyc ),
.s5_stb_o( gpion0_stb ),
.s5_ack_i( gpion0_ack ),
.s5_err_i( gnd ),
.s5_rty_i( gnd ),
.s6_dat_i( lcd0_dat_r ),
.s6_dat_o( lcd0_dat_w ),
.s6_adr_o( lcd0_adr ),
.s6_sel_o( lcd0_sel ),
.s6_we_o( lcd0_we ),
.s6_cyc_o( lcd0_cyc ),
.s6_stb_o( lcd0_stb ),
.s6_ack_i( lcd0_ack ),
.s6_err_i( gnd ),
.s6_rty_i( gnd ),
.s7_dat_i( sintesis0_dat_r ),
.s7_dat_o( sintesis0_dat_w ),
.s7_adr_o( sintesis0_adr ),
.s7_sel_o( sintesis0_sel ),
.s7_we_o( sintesis0_we ),
.s7_cyc_o( sintesis0_cyc ),
.s7_stb_o( sintesis0_stb ),
.s7_ack_i( sintesis0_ack ),
.s7_err_i( gnd ),
.s7_rty_i( gnd )
);
lm32_cpu lm0 (
.clk_i( clk ),
.rst_i( ~rst ),
.interrupt_n( intr_n ),
.I_ADR_O( lm32i_adr ),
.I_DAT_I( lm32i_dat_r ),
.I_DAT_O( lm32i_dat_w ),
.I_SEL_O( lm32i_sel ),
.I_CYC_O( lm32i_cyc ),
.I_STB_O( lm32i_stb ),
.I_ACK_I( lm32i_ack ),
.I_WE_O ( lm32i_we ),
.I_CTI_O( lm32i_cti ),
.I_LOCK_O( lm32i_lock ),
.I_BTE_O( lm32i_bte ),
.I_ERR_I( lm32i_err ),
.I_RTY_I( lm32i_rty ),
.D_ADR_O( lm32d_adr ),
.D_DAT_I( lm32d_dat_r ),
.D_DAT_O( lm32d_dat_w ),
.D_SEL_O( lm32d_sel ),
.D_CYC_O( lm32d_cyc ),
.D_STB_O( lm32d_stb ),
.D_ACK_I( lm32d_ack ),
.D_WE_O ( lm32d_we ),
.D_CTI_O( lm32d_cti ),
.D_LOCK_O( lm32d_lock ),
.D_BTE_O( lm32d_bte ),
.D_ERR_I( lm32d_err ),
.D_RTY_I( lm32d_rty )
);
wb_bram #(
.adr_width( 12 ),
.mem_file_name( bootram_file )
) bram0 (
.clk_i( clk ),
.rst_i( ~rst ),
.wb_adr_i( bram0_adr ),
.wb_dat_o( bram0_dat_r ),
.wb_dat_i( bram0_dat_w ),
.wb_sel_i( bram0_sel ),
.wb_stb_i( bram0_stb ),
.wb_cyc_i( bram0_cyc ),
.wb_ack_o( bram0_ack ),
.wb_we_i( bram0_we )
);
wb_timer #(
.clk_freq( clk_freq )
) timer0 (
.clk( clk ),
.reset( ~rst ),
.wb_adr_i( timer0_adr ),
.wb_dat_i( timer0_dat_w ),
.wb_dat_o( timer0_dat_r ),
.wb_stb_i( timer0_stb ),
.wb_cyc_i( timer0_cyc ),
.wb_we_i( timer0_we ),
.wb_sel_i( timer0_sel ),
.wb_ack_o( timer0_ack ),
.intr( timer0_intr )
);
wire [12:0] gpio0_entrada;
wire [6:0] gpio0_salida;
wb_gpion gpion0 (
.clk( clk ),
.reset( rst ),
.wb_adr_i( gpion0_adr ),
.wb_dat_i( gpion0_dat_w ),
.wb_dat_o( gpion0_dat_r ),
.wb_stb_i( gpion0_stb ),
.wb_cyc_i( gpion0_cyc ),
.wb_we_i( gpion0_we ),
.wb_sel_i( gpion0_sel ),
.wb_ack_o( gpion0_ack ),
.intr( gpion0_intr ),
.gpio_entrada( gpio0_entrada),
.gpio_salida( gpio0_salida)
);
wire [5:0] bus_salida;
wb_lcd lcd0 (
.clk( clk ),
.reset( rst ),
.wb_adr_i( lcd0_adr ),
.wb_dat_i( lcd0_dat_w ),
.wb_dat_o( lcd0_dat_r ),
.wb_stb_i( lcd0_stb ),
.wb_cyc_i( lcd0_cyc ),
.wb_we_i( lcd0_we ),
.wb_sel_i( lcd0_sel ),
.wb_ack_o( lcd0_ack ),
.bus_salida(bus_salida)
);
wire pulse_data;
wire [10:0] teclado;
wb_sintesis sintesis0 (
.clk( clk ),
.reset( rst ),
.wb_adr_i( sintesis0_adr ),
.wb_dat_i( sintesis0_dat_w ),
.wb_dat_o( sintesis0_dat_r ),
.wb_stb_i( sintesis0_stb ),
.wb_cyc_i( sintesis0_cyc ),
.wb_we_i( sintesis0_we ),
.wb_sel_i( sintesis0_sel ),
.wb_ack_o( sintesis0_ack ),
.teclado(teclado),
.led1(led1),
.pulse_data(pulse_data)
);
assign teclado = gpio_entrada;
assign gpio_salida = {bus_salida, pulse_data};
assign led = led1;
endmodule | module system
#(
parameter bootram_file = "../firmware/hw-test/image.ram",
parameter clk_freq = 50000000,
parameter uart_baud_rate = 57600
) (
input clk,
output led,
input rst,
input uart_rxd,
output uart_txd,
input [10:0] gpio_entrada,
output [6:0] gpio_salida,
input [12:0] addr,
input [7:0] sram_data,
input nwe,
input noe,
input ncs
); |
wire gnd = 1'b0;
wire [3:0] gnd4 = 4'h0;
wire [31:0] gnd32 = 32'h00000000;
wire [31:0] lm32i_adr,
lm32d_adr,
uart0_adr,
timer0_adr,
gpion0_adr,
bram0_adr,
sram0_adr,
lcd0_adr,
sintesis0_adr;
wire [31:0] lm32i_dat_r,
lm32i_dat_w,
lm32d_dat_r,
lm32d_dat_w,
uart0_dat_r,
uart0_dat_w,
timer0_dat_r,
timer0_dat_w,
gpion0_dat_r,
gpion0_dat_w,
bram0_dat_r,
bram0_dat_w,
sram0_dat_w,
sram0_dat_r,
lcd0_dat_w,
lcd0_dat_r,
sintesis0_dat_w,
sintesis0_dat_r;
wire [3:0] lm32i_sel,
lm32d_sel,
uart0_sel,
timer0_sel,
gpion0_sel,
bram0_sel,
sram0_sel,
lcd0_sel,
sintesis0_sel;
wire lm32i_we,
lm32d_we,
uart0_we,
timer0_we,
gpion0_we,
bram0_we,
sram0_we,
lcd0_we,
sintesis0_we;
wire lm32i_cyc,
lm32d_cyc,
uart0_cyc,
timer0_cyc,
gpion0_cyc,
bram0_cyc,
sram0_cyc,
lcd0_cyc,
sintesis0_cyc;
wire lm32i_stb,
lm32d_stb,
uart0_stb,
timer0_stb,
gpion0_stb,
bram0_stb,
sram0_stb,
lcd0_stb,
sintesis0_stb;
wire lm32i_ack,
lm32d_ack,
uart0_ack,
timer0_ack,
gpion0_ack,
bram0_ack,
sram0_ack,
lcd0_ack,
sintesis0_ack;
wire lm32i_rty,
lm32d_rty;
wire lm32i_err,
lm32d_err;
wire lm32i_lock,
lm32d_lock;
wire [2:0] lm32i_cti,
lm32d_cti;
wire [1:0] lm32i_bte,
lm32d_bte;
wire [31:0] intr_n;
wire uart0_intr = 0;
wire [1:0] timer0_intr;
wire gpion0_intr;
assign intr_n = { 28'hFFFFFFF, ~timer0_intr[1], ~uart0_intr, ~timer0_intr[0], ~gpion0_intr };
wb_conbus_top #(
.s0_addr_w ( 3 ),
.s0_addr ( 3'h4 ),
.s1_addr_w ( 3 ),
.s1_addr ( 3'h5 ),
.s27_addr_w( 15 ),
.s2_addr ( 15'h0000 ),
.s3_addr ( 15'h7000 ),
.s4_addr ( 15'h7001 ),
.s5_addr ( 15'h7002 ),
.s6_addr ( 15'h7003 ),
.s7_addr ( 15'h7004 )
) conmax0 (
.clk_i( clk ),
.rst_i( ~rst ),
.m0_dat_i( lm32i_dat_w ),
.m0_dat_o( lm32i_dat_r ),
.m0_adr_i( lm32i_adr ),
.m0_we_i ( lm32i_we ),
.m0_sel_i( lm32i_sel ),
.m0_cyc_i( lm32i_cyc ),
.m0_stb_i( lm32i_stb ),
.m0_ack_o( lm32i_ack ),
.m0_rty_o( lm32i_rty ),
.m0_err_o( lm32i_err ),
.m1_dat_i( lm32d_dat_w ),
.m1_dat_o( lm32d_dat_r ),
.m1_adr_i( lm32d_adr ),
.m1_we_i ( lm32d_we ),
.m1_sel_i( lm32d_sel ),
.m1_cyc_i( lm32d_cyc ),
.m1_stb_i( lm32d_stb ),
.m1_ack_o( lm32d_ack ),
.m1_rty_o( lm32d_rty ),
.m1_err_o( lm32d_err ),
.m2_dat_i( gnd32 ),
.m2_adr_i( gnd32 ),
.m2_sel_i( gnd4 ),
.m2_cyc_i( gnd ),
.m2_stb_i( gnd ),
.m3_dat_i( gnd32 ),
.m3_adr_i( gnd32 ),
.m3_sel_i( gnd4 ),
.m3_cyc_i( gnd ),
.m3_stb_i( gnd ),
.m4_dat_i( gnd32 ),
.m4_adr_i( gnd32 ),
.m4_sel_i( gnd4 ),
.m4_cyc_i( gnd ),
.m4_stb_i( gnd ),
.m5_dat_i( gnd32 ),
.m5_adr_i( gnd32 ),
.m5_sel_i( gnd4 ),
.m5_cyc_i( gnd ),
.m5_stb_i( gnd ),
.m6_dat_i( gnd32 ),
.m6_adr_i( gnd32 ),
.m6_sel_i( gnd4 ),
.m6_cyc_i( gnd ),
.m6_stb_i( gnd ),
.m7_dat_i( gnd32 ),
.m7_adr_i( gnd32 ),
.m7_sel_i( gnd4 ),
.m7_cyc_i( gnd ),
.m7_stb_i( gnd ),
.s0_dat_i( sram0_dat_r ),
.s0_dat_o( sram0_dat_w ),
.s0_adr_o( sram0_adr ),
.s0_sel_o( sram0_sel ),
.s0_we_o( sram0_we ),
.s0_cyc_o( sram0_cyc ),
.s0_stb_o( sram0_stb ),
.s0_ack_i( sram0_ack ),
.s0_err_i( gnd ),
.s0_rty_i( gnd ),
.s1_dat_i( gnd32 ),
.s1_ack_i( gnd ),
.s1_err_i( gnd ),
.s1_rty_i( gnd ),
.s2_dat_i( bram0_dat_r ),
.s2_dat_o( bram0_dat_w ),
.s2_adr_o( bram0_adr ),
.s2_sel_o( bram0_sel ),
.s2_we_o( bram0_we ),
.s2_cyc_o( bram0_cyc ),
.s2_stb_o( bram0_stb ),
.s2_ack_i( bram0_ack ),
.s2_err_i( gnd ),
.s2_rty_i( gnd ),
.s3_dat_i( uart0_dat_r ),
.s3_dat_o( uart0_dat_w ),
.s3_adr_o( uart0_adr ),
.s3_sel_o( uart0_sel ),
.s3_we_o( uart0_we ),
.s3_cyc_o( uart0_cyc ),
.s3_stb_o( uart0_stb ),
.s3_ack_i( uart0_ack ),
.s3_err_i( gnd ),
.s3_rty_i( gnd ),
.s4_dat_i( timer0_dat_r ),
.s4_dat_o( timer0_dat_w ),
.s4_adr_o( timer0_adr ),
.s4_sel_o( timer0_sel ),
.s4_we_o( timer0_we ),
.s4_cyc_o( timer0_cyc ),
.s4_stb_o( timer0_stb ),
.s4_ack_i( timer0_ack ),
.s4_err_i( gnd ),
.s4_rty_i( gnd ),
.s5_dat_i( gpion0_dat_r ),
.s5_dat_o( gpion0_dat_w ),
.s5_adr_o( gpion0_adr ),
.s5_sel_o( gpion0_sel ),
.s5_we_o( gpion0_we ),
.s5_cyc_o( gpion0_cyc ),
.s5_stb_o( gpion0_stb ),
.s5_ack_i( gpion0_ack ),
.s5_err_i( gnd ),
.s5_rty_i( gnd ),
.s6_dat_i( lcd0_dat_r ),
.s6_dat_o( lcd0_dat_w ),
.s6_adr_o( lcd0_adr ),
.s6_sel_o( lcd0_sel ),
.s6_we_o( lcd0_we ),
.s6_cyc_o( lcd0_cyc ),
.s6_stb_o( lcd0_stb ),
.s6_ack_i( lcd0_ack ),
.s6_err_i( gnd ),
.s6_rty_i( gnd ),
.s7_dat_i( sintesis0_dat_r ),
.s7_dat_o( sintesis0_dat_w ),
.s7_adr_o( sintesis0_adr ),
.s7_sel_o( sintesis0_sel ),
.s7_we_o( sintesis0_we ),
.s7_cyc_o( sintesis0_cyc ),
.s7_stb_o( sintesis0_stb ),
.s7_ack_i( sintesis0_ack ),
.s7_err_i( gnd ),
.s7_rty_i( gnd )
);
lm32_cpu lm0 (
.clk_i( clk ),
.rst_i( ~rst ),
.interrupt_n( intr_n ),
.I_ADR_O( lm32i_adr ),
.I_DAT_I( lm32i_dat_r ),
.I_DAT_O( lm32i_dat_w ),
.I_SEL_O( lm32i_sel ),
.I_CYC_O( lm32i_cyc ),
.I_STB_O( lm32i_stb ),
.I_ACK_I( lm32i_ack ),
.I_WE_O ( lm32i_we ),
.I_CTI_O( lm32i_cti ),
.I_LOCK_O( lm32i_lock ),
.I_BTE_O( lm32i_bte ),
.I_ERR_I( lm32i_err ),
.I_RTY_I( lm32i_rty ),
.D_ADR_O( lm32d_adr ),
.D_DAT_I( lm32d_dat_r ),
.D_DAT_O( lm32d_dat_w ),
.D_SEL_O( lm32d_sel ),
.D_CYC_O( lm32d_cyc ),
.D_STB_O( lm32d_stb ),
.D_ACK_I( lm32d_ack ),
.D_WE_O ( lm32d_we ),
.D_CTI_O( lm32d_cti ),
.D_LOCK_O( lm32d_lock ),
.D_BTE_O( lm32d_bte ),
.D_ERR_I( lm32d_err ),
.D_RTY_I( lm32d_rty )
);
wb_bram #(
.adr_width( 12 ),
.mem_file_name( bootram_file )
) bram0 (
.clk_i( clk ),
.rst_i( ~rst ),
.wb_adr_i( bram0_adr ),
.wb_dat_o( bram0_dat_r ),
.wb_dat_i( bram0_dat_w ),
.wb_sel_i( bram0_sel ),
.wb_stb_i( bram0_stb ),
.wb_cyc_i( bram0_cyc ),
.wb_ack_o( bram0_ack ),
.wb_we_i( bram0_we )
);
wb_timer #(
.clk_freq( clk_freq )
) timer0 (
.clk( clk ),
.reset( ~rst ),
.wb_adr_i( timer0_adr ),
.wb_dat_i( timer0_dat_w ),
.wb_dat_o( timer0_dat_r ),
.wb_stb_i( timer0_stb ),
.wb_cyc_i( timer0_cyc ),
.wb_we_i( timer0_we ),
.wb_sel_i( timer0_sel ),
.wb_ack_o( timer0_ack ),
.intr( timer0_intr )
);
wire [12:0] gpio0_entrada;
wire [6:0] gpio0_salida;
wb_gpion gpion0 (
.clk( clk ),
.reset( rst ),
.wb_adr_i( gpion0_adr ),
.wb_dat_i( gpion0_dat_w ),
.wb_dat_o( gpion0_dat_r ),
.wb_stb_i( gpion0_stb ),
.wb_cyc_i( gpion0_cyc ),
.wb_we_i( gpion0_we ),
.wb_sel_i( gpion0_sel ),
.wb_ack_o( gpion0_ack ),
.intr( gpion0_intr ),
.gpio_entrada( gpio0_entrada),
.gpio_salida( gpio0_salida)
);
wire [5:0] bus_salida;
wb_lcd lcd0 (
.clk( clk ),
.reset( rst ),
.wb_adr_i( lcd0_adr ),
.wb_dat_i( lcd0_dat_w ),
.wb_dat_o( lcd0_dat_r ),
.wb_stb_i( lcd0_stb ),
.wb_cyc_i( lcd0_cyc ),
.wb_we_i( lcd0_we ),
.wb_sel_i( lcd0_sel ),
.wb_ack_o( lcd0_ack ),
.bus_salida(bus_salida)
);
wire pulse_data;
wire [10:0] teclado;
wb_sintesis sintesis0 (
.clk( clk ),
.reset( rst ),
.wb_adr_i( sintesis0_adr ),
.wb_dat_i( sintesis0_dat_w ),
.wb_dat_o( sintesis0_dat_r ),
.wb_stb_i( sintesis0_stb ),
.wb_cyc_i( sintesis0_cyc ),
.wb_we_i( sintesis0_we ),
.wb_sel_i( sintesis0_sel ),
.wb_ack_o( sintesis0_ack ),
.teclado(teclado),
.led1(led1),
.pulse_data(pulse_data)
);
assign teclado = gpio_entrada;
assign gpio_salida = {bus_salida, pulse_data};
assign led = led1;
endmodule | 1 |
139,770 | data/full_repos/permissive/89810125/system_tb.v | 89,810,125 | system_tb.v | v | 75 | 79 | [] | [] | [] | null | line:28: before: "initial" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/89810125/system_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\nalways #(tck/2) clk <= ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/89810125/system_tb.v:58: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("system_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/89810125/system_tb.v:60: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(-1, dut);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/89810125/system_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #0 rst <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/89810125/system_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #80 rst <= 1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/89810125/system_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_entrada <= 13\'b1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/89810125/system_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n #100000 gpio_entrada <= 13\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/89810125/system_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n #100000 gpio_entrada <= 13\'b101;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/89810125/system_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #100000 gpio_entrada <= 13\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/89810125/system_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n #(tck*50000) $finish;\n ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 307,808 | module | module system_tb;
parameter tck = 20;
parameter uart_baud_rate = 1152000;
parameter clk_freq = 1000000000 / tck;
reg clk;
reg rst;
wire led;
wire uart_rxd;
wire uart_txd;
reg [12:0] gpio_entrada;
wire [6:0] gpio_salida;
system #(
.clk_freq( clk_freq ),
.uart_baud_rate( uart_baud_rate )
) dut (
.clk( clk ),
.rst( rst ),
.led( led ),
.uart_rxd( uart_rxd ),
.uart_txd( uart_txd ),
.gpio_entrada (gpio_entrada),
.gpio_salida (gpio_salida)
);
initial clk <= 0;
always #(tck/2) clk <= ~clk;
initial begin
$dumpfile("system_tb.vcd");
$dumpvars(-1, dut);
#0 rst <= 0;
#80 rst <= 1;
#10 gpio_entrada <= 13'b1;
#100000 gpio_entrada <= 13'b0;
#100000 gpio_entrada <= 13'b101;
#100000 gpio_entrada <= 13'b0;
#(tck*50000) $finish;
end
endmodule | module system_tb; |
parameter tck = 20;
parameter uart_baud_rate = 1152000;
parameter clk_freq = 1000000000 / tck;
reg clk;
reg rst;
wire led;
wire uart_rxd;
wire uart_txd;
reg [12:0] gpio_entrada;
wire [6:0] gpio_salida;
system #(
.clk_freq( clk_freq ),
.uart_baud_rate( uart_baud_rate )
) dut (
.clk( clk ),
.rst( rst ),
.led( led ),
.uart_rxd( uart_rxd ),
.uart_txd( uart_txd ),
.gpio_entrada (gpio_entrada),
.gpio_salida (gpio_salida)
);
initial clk <= 0;
always #(tck/2) clk <= ~clk;
initial begin
$dumpfile("system_tb.vcd");
$dumpvars(-1, dut);
#0 rst <= 0;
#80 rst <= 1;
#10 gpio_entrada <= 13'b1;
#100000 gpio_entrada <= 13'b0;
#100000 gpio_entrada <= 13'b101;
#100000 gpio_entrada <= 13'b0;
#(tck*50000) $finish;
end
endmodule | 1 |
139,772 | data/full_repos/permissive/89810125/archivos/karplus.v | 89,810,125 | karplus.v | v | 342 | 100 | [] | [] | [] | [(9, 341)] | null | null | 1: b'%Error: data/full_repos/permissive/89810125/archivos/karplus.v:122: Cannot find file containing module: \'shifter\'\nshifter testShift ( .clock(audiolrclk),\n^~~~~~~\n ... Looked in:\n data/full_repos/permissive/89810125/archivos,data/full_repos/permissive/89810125/shifter\n data/full_repos/permissive/89810125/archivos,data/full_repos/permissive/89810125/shifter.v\n data/full_repos/permissive/89810125/archivos,data/full_repos/permissive/89810125/shifter.sv\n shifter\n shifter.v\n shifter.sv\n obj_dir/shifter\n obj_dir/shifter.v\n obj_dir/shifter.sv\n%Warning-WIDTH: data/full_repos/permissive/89810125/archivos/karplus.v:153: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h1\' generates 12 bits.\n : ... In instance karplus\n ptr_out <= 12\'h1 ; \n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/89810125/archivos/karplus.v:154: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n : ... In instance karplus\n ptr_in <= 12\'h0 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/archivos/karplus.v:156: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h1\' generates 12 bits.\n : ... In instance karplus\n ptr_outP <= 12\'h1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/archivos/karplus.v:157: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n : ... In instance karplus\n ptr_outP <= 12\'h0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/archivos/karplus.v:229: Operator LT expects 12 bits on the RHS, but RHS\'s VARREF \'note\' generates 9 bits.\n : ... In instance karplus\n else if (pluck_count<note)\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/archivos/karplus.v:246: Operator LT expects 12 bits on the RHS, but RHS\'s VARREF \'noteP\' generates 9 bits.\n : ... In instance karplus\n else if (pluck_countP < noteP)\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/archivos/karplus.v:272: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n : ... In instance karplus\n ptr_in <= 12\'h0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/archivos/karplus.v:274: Operator ADD expects 12 bits on the LHS, but LHS\'s VARREF \'ptr_in\' generates 9 bits.\n : ... In instance karplus\n ptr_in <= ptr_in + 12\'h1 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/archivos/karplus.v:274: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s ADD generates 12 bits.\n : ... In instance karplus\n ptr_in <= ptr_in + 12\'h1 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/archivos/karplus.v:277: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n : ... In instance karplus\n ptr_out <= 12\'h0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/archivos/karplus.v:279: Operator ADD expects 12 bits on the LHS, but LHS\'s VARREF \'ptr_out\' generates 9 bits.\n : ... In instance karplus\n ptr_out <= ptr_out + 12\'h1 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/archivos/karplus.v:279: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s ADD generates 12 bits.\n : ... In instance karplus\n ptr_out <= ptr_out + 12\'h1 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/archivos/karplus.v:282: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n : ... In instance karplus\n ptr_inP <= 12\'h0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/archivos/karplus.v:284: Operator ADD expects 12 bits on the LHS, but LHS\'s VARREF \'ptr_inP\' generates 9 bits.\n : ... In instance karplus\n ptr_inP <= ptr_inP + 12\'h1 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/archivos/karplus.v:284: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s ADD generates 12 bits.\n : ... In instance karplus\n ptr_inP <= ptr_inP + 12\'h1 ;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/archivos/karplus.v:287: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n : ... In instance karplus\n ptr_outP <= 12\'h0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/archivos/karplus.v:289: Operator ADD expects 12 bits on the LHS, but LHS\'s VARREF \'ptr_outP\' generates 9 bits.\n : ... In instance karplus\n ptr_outP <= ptr_outP + 12\'h1 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/archivos/karplus.v:289: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s ADD generates 12 bits.\n : ... In instance karplus\n ptr_outP <= ptr_outP + 12\'h1 ;\n ^~\n%Error: data/full_repos/permissive/89810125/archivos/karplus.v:315: Cannot find file containing module: \'ourM4\'\nourM4 testNote ( .address_a(addrA_reg),\n^~~~~\n%Error: data/full_repos/permissive/89810125/archivos/karplus.v:325: Cannot find file containing module: \'ourM4\'\nourM4 testNoteP ( .address_a(addrA_regP),\n^~~~~\n%Error: data/full_repos/permissive/89810125/archivos/karplus.v:337: Cannot find file containing module: \'signed_mult\'\nsigned_mult gainfactor(new_out, gain, (out_data + in_data));\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/89810125/archivos/karplus.v:339: Cannot find file containing module: \'signed_mult\'\nsigned_mult gainfactorP(new_outP, gain, (out_dataP + in_dataP));\n^~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 18 warning(s)\n' | 307,810 | module | module karplus(clock50,
m4Clock,
audiolrclk,
reset,
noteIn,
gain,
pluck,
audioOut,
alpha,
count,
vel_en
);
input wire [8:0] noteIn ;
wire [8:0] note, noteP ;
assign note = noteIn[8:0] - 9'b1;
assign noteP = noteIn[8:0] + 9'd1;
input wire reset;
input wire [17:0] gain ;
input wire clock50;
input wire m4Clock;
input wire audiolrclk;
input wire pluck;
input wire [2:0] alpha;
input wire [25:0] count;
input wire vel_en;
output reg [17:0] audioOut;
reg last_pluck;
reg [11:0] pluck_count, pluck_countP;
reg [3:0] state ;
reg last_clk ;
reg [8:0] ptr_in, ptr_out;
reg [8:0] ptr_inP, ptr_outP;
reg weA, weB;
wire [17:0] dataOutA, dataOutB;
reg [17:0] write_dataA, write_dataB;
reg [8:0] addrA_reg, addrB_reg;
reg weAP, weBP;
wire [17:0] dataOutAP, dataOutBP;
reg [17:0] write_dataAP, write_dataBP;
reg [8:0] addrA_regP, addrB_regP;
reg [17:0] out, in_data, out_data ;
wire [17:0] new_out;
reg [17:0] outP, in_dataP, out_dataP ;
wire [17:0] new_outP;
wire x_low_bit ;
reg [30:0] x_rand ;
wire [17:0] new_lopass, new_lopassD, new_lopass2, new_lopass3, new_lopassSum ;
reg [17:0] lopass, lopassDelay, lopass2, lopassDelay2, lopass3, lopassSum ;
assign x_low_bit = x_rand[8] ^ x_rand[30];
assign new_lopass = lopass + ((( (x_low_bit)?18'h1_0000:18'h3_0000) - lopass)>>>alpha[2:0]);
assign new_lopass2 = lopass2 + ((( new_lopassD ) - lopass2)>>>alpha[2:0]);
assign new_lopassSum = ((new_lopass + new_lopass2)>>>1);
shifter testShift ( .clock(audiolrclk),
.shiftin(new_lopass),
.shiftout(new_lopassD),
.taps());
always @ (posedge audiolrclk)
begin
if (reset)
begin
lopass <= 18'h0 ;
lopassDelay <= 18'h0;
lopass2 <= 18'h0;
lopassDelay2 <= 18'h0;
end
else begin
lopass <= new_lopass ;
lopassDelay <= lopass;
lopass2 <= new_lopass2;
lopassSum <= new_lopassSum;
end
end
always @ (posedge clock50)
begin
if (reset)
begin
x_rand <= 31'h55555555;
ptr_out <= 12'h1 ;
ptr_in <= 12'h0 ;
ptr_outP <= 12'h1;
ptr_outP <= 12'h0;
weA <= 1'h0 ;
weB <= 1'h0;
weAP <= 1'h0;
weBP <= 1'h0;
state <= 4'd9 ;
last_clk <= 1'h1;
end
else begin
x_rand <= {x_rand[29:0], x_low_bit} ;
case (state)
1:
begin
addrA_reg <= ptr_in;
addrB_reg <= ptr_out;
weA <= 1'h0;
weB <= 1'h0;
addrA_regP <= ptr_inP;
addrB_regP <= ptr_outP;
weAP <= 1'h0;
weBP <= 1'h0;
state <= 4'd2;
end
2:
begin
in_data <= dataOutA;
out_data <= dataOutB;
in_dataP <= dataOutAP;
out_dataP <= dataOutBP;
state <= 4'd4;
end
4:
begin
out <= new_out;
outP <= new_outP;
audioOut <= outP + out;
addrA_reg <= ptr_in;
weA <= 1'h1 ;
weAP <= 1'h1;
if (pluck)
begin
if (last_pluck==0)
begin
pluck_count <= 12'd0;
last_pluck <= 1'd1;
write_dataA <= lopassSum ;
end
else if (pluck_count<note)
begin
pluck_count <= pluck_count + 12'd1 ;
write_dataA <= lopassSum ;
end
else
write_dataA <= out ;
if (last_pluck==0)
begin
pluck_countP <= 12'd0;
write_dataAP <= lopassSum;
end
else if (pluck_countP < noteP)
begin
pluck_countP <= pluck_countP + 12'd1;
write_dataAP <= lopassSum;
end
else
write_dataAP <= outP ;
end
else begin
last_pluck = 1'h0;
write_dataA <= out ;
write_dataAP <= outP ;
end
state <= 4'd5;
end
5:
begin
weA <= 0;
weAP <= 0;
if (ptr_in == note)
ptr_in <= 12'h0;
else
ptr_in <= ptr_in + 12'h1 ;
if (ptr_out == note)
ptr_out <= 12'h0;
else
ptr_out <= ptr_out + 12'h1 ;
if (ptr_inP == noteP)
ptr_inP <= 12'h0;
else
ptr_inP <= ptr_inP + 12'h1 ;
if (ptr_outP == note)
ptr_outP <= 12'h0;
else
ptr_outP <= ptr_outP + 12'h1 ;
state <= 4'd9;
end
9:
begin
if (audiolrclk && last_clk)
begin
state <= 4'd1 ;
last_clk <= 1'h0 ;
end
else if (~audiolrclk)
begin
last_clk <= 1'h1 ;
end
end
endcase
end
end
ourM4 testNote ( .address_a(addrA_reg),
.address_b(addrB_reg),
.clock(m4Clock),
.data_a(write_dataA),
.data_b(write_dataB),
.wren_a(weA),
.wren_b(weB),
.q_a(dataOutA),
.q_b(dataOutB) );
ourM4 testNoteP ( .address_a(addrA_regP),
.address_b(addrB_regP),
.clock(m4Clock),
.data_a(write_dataAP),
.data_b(write_dataBP),
.wren_a(weAP),
.wren_b(weBP),
.q_a(dataOutAP),
.q_b(dataOutBP) );
signed_mult gainfactor(new_out, gain, (out_data + in_data));
signed_mult gainfactorP(new_outP, gain, (out_dataP + in_dataP));
endmodule | module karplus(clock50,
m4Clock,
audiolrclk,
reset,
noteIn,
gain,
pluck,
audioOut,
alpha,
count,
vel_en
); |
input wire [8:0] noteIn ;
wire [8:0] note, noteP ;
assign note = noteIn[8:0] - 9'b1;
assign noteP = noteIn[8:0] + 9'd1;
input wire reset;
input wire [17:0] gain ;
input wire clock50;
input wire m4Clock;
input wire audiolrclk;
input wire pluck;
input wire [2:0] alpha;
input wire [25:0] count;
input wire vel_en;
output reg [17:0] audioOut;
reg last_pluck;
reg [11:0] pluck_count, pluck_countP;
reg [3:0] state ;
reg last_clk ;
reg [8:0] ptr_in, ptr_out;
reg [8:0] ptr_inP, ptr_outP;
reg weA, weB;
wire [17:0] dataOutA, dataOutB;
reg [17:0] write_dataA, write_dataB;
reg [8:0] addrA_reg, addrB_reg;
reg weAP, weBP;
wire [17:0] dataOutAP, dataOutBP;
reg [17:0] write_dataAP, write_dataBP;
reg [8:0] addrA_regP, addrB_regP;
reg [17:0] out, in_data, out_data ;
wire [17:0] new_out;
reg [17:0] outP, in_dataP, out_dataP ;
wire [17:0] new_outP;
wire x_low_bit ;
reg [30:0] x_rand ;
wire [17:0] new_lopass, new_lopassD, new_lopass2, new_lopass3, new_lopassSum ;
reg [17:0] lopass, lopassDelay, lopass2, lopassDelay2, lopass3, lopassSum ;
assign x_low_bit = x_rand[8] ^ x_rand[30];
assign new_lopass = lopass + ((( (x_low_bit)?18'h1_0000:18'h3_0000) - lopass)>>>alpha[2:0]);
assign new_lopass2 = lopass2 + ((( new_lopassD ) - lopass2)>>>alpha[2:0]);
assign new_lopassSum = ((new_lopass + new_lopass2)>>>1);
shifter testShift ( .clock(audiolrclk),
.shiftin(new_lopass),
.shiftout(new_lopassD),
.taps());
always @ (posedge audiolrclk)
begin
if (reset)
begin
lopass <= 18'h0 ;
lopassDelay <= 18'h0;
lopass2 <= 18'h0;
lopassDelay2 <= 18'h0;
end
else begin
lopass <= new_lopass ;
lopassDelay <= lopass;
lopass2 <= new_lopass2;
lopassSum <= new_lopassSum;
end
end
always @ (posedge clock50)
begin
if (reset)
begin
x_rand <= 31'h55555555;
ptr_out <= 12'h1 ;
ptr_in <= 12'h0 ;
ptr_outP <= 12'h1;
ptr_outP <= 12'h0;
weA <= 1'h0 ;
weB <= 1'h0;
weAP <= 1'h0;
weBP <= 1'h0;
state <= 4'd9 ;
last_clk <= 1'h1;
end
else begin
x_rand <= {x_rand[29:0], x_low_bit} ;
case (state)
1:
begin
addrA_reg <= ptr_in;
addrB_reg <= ptr_out;
weA <= 1'h0;
weB <= 1'h0;
addrA_regP <= ptr_inP;
addrB_regP <= ptr_outP;
weAP <= 1'h0;
weBP <= 1'h0;
state <= 4'd2;
end
2:
begin
in_data <= dataOutA;
out_data <= dataOutB;
in_dataP <= dataOutAP;
out_dataP <= dataOutBP;
state <= 4'd4;
end
4:
begin
out <= new_out;
outP <= new_outP;
audioOut <= outP + out;
addrA_reg <= ptr_in;
weA <= 1'h1 ;
weAP <= 1'h1;
if (pluck)
begin
if (last_pluck==0)
begin
pluck_count <= 12'd0;
last_pluck <= 1'd1;
write_dataA <= lopassSum ;
end
else if (pluck_count<note)
begin
pluck_count <= pluck_count + 12'd1 ;
write_dataA <= lopassSum ;
end
else
write_dataA <= out ;
if (last_pluck==0)
begin
pluck_countP <= 12'd0;
write_dataAP <= lopassSum;
end
else if (pluck_countP < noteP)
begin
pluck_countP <= pluck_countP + 12'd1;
write_dataAP <= lopassSum;
end
else
write_dataAP <= outP ;
end
else begin
last_pluck = 1'h0;
write_dataA <= out ;
write_dataAP <= outP ;
end
state <= 4'd5;
end
5:
begin
weA <= 0;
weAP <= 0;
if (ptr_in == note)
ptr_in <= 12'h0;
else
ptr_in <= ptr_in + 12'h1 ;
if (ptr_out == note)
ptr_out <= 12'h0;
else
ptr_out <= ptr_out + 12'h1 ;
if (ptr_inP == noteP)
ptr_inP <= 12'h0;
else
ptr_inP <= ptr_inP + 12'h1 ;
if (ptr_outP == note)
ptr_outP <= 12'h0;
else
ptr_outP <= ptr_outP + 12'h1 ;
state <= 4'd9;
end
9:
begin
if (audiolrclk && last_clk)
begin
state <= 4'd1 ;
last_clk <= 1'h0 ;
end
else if (~audiolrclk)
begin
last_clk <= 1'h1 ;
end
end
endcase
end
end
ourM4 testNote ( .address_a(addrA_reg),
.address_b(addrB_reg),
.clock(m4Clock),
.data_a(write_dataA),
.data_b(write_dataB),
.wren_a(weA),
.wren_b(weB),
.q_a(dataOutA),
.q_b(dataOutB) );
ourM4 testNoteP ( .address_a(addrA_regP),
.address_b(addrB_regP),
.clock(m4Clock),
.data_a(write_dataAP),
.data_b(write_dataBP),
.wren_a(weAP),
.wren_b(weBP),
.q_a(dataOutAP),
.q_b(dataOutBP) );
signed_mult gainfactor(new_out, gain, (out_data + in_data));
signed_mult gainfactorP(new_outP, gain, (out_dataP + in_dataP));
endmodule | 1 |
139,773 | data/full_repos/permissive/89810125/rtl/wb_sintesis.v | 89,810,125 | wb_sintesis.v | v | 848 | 155 | [] | [] | [] | null | line:342: before: "coeff" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:152: Signal definition not found, creating implicitly: \'led1\'\n assign led1 = | en_osc;\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:153: Signal definition not found, creating implicitly: \'led2\'\n : ... Suggested alternative: \'led1\'\n assign led2 = | teclas;\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:796: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:799: Signal definition not found, creating implicitly: \'sel\'\nassign sel = teclado[12];\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:677: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:679: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:663: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:665: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:650: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:652: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:636: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:638: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:744: Operator LT expects 7 bits on the LHS, but LHS\'s VARREF \'cont\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.pwm0\n if (cont<sint_data)\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:692: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.suma1\n reg [6:0] rp = 6\'b0; \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:709: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:713: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:712: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:306: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 16 bits.\n : ... In instance wb_sintesis.sint0.filtro11\n data_f <= (multi0+multi1+multi2+multi3+multi4+multi5+multi6+multi7+multi8+multi9+multi10)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:231: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:31: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'14\'h3fff\' generates 14 bits.\n : ... In instance wb_sintesis.sint0.deb0\n if (cont== 14\'d16383)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:106: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o0 (en_osc[0],clk_fm, 59, 138, amp0,done_osc[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:107: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o1 (en_osc[1],clk_fm, 55, 148, amp1,done_osc[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:108: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o2 (en_osc[2],clk_fm, 52, 157, amp2,done_osc[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:109: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o3 (en_osc[3],clk_fm, 49, 167, amp3,done_osc[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:110: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o4 (en_osc[4],clk_fm, 46, 178, amp4,done_osc[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:111: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o5 (en_osc[5],clk_fm, 44, 186, amp5,done_osc[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:112: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o6 (en_osc[6],clk_fm, 41, 199, amp6,done_osc[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:113: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o7 (en_osc[7],clk_fm, 39, 210, amp7,done_osc[7]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:114: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o8 (en_osc[8],clk_fm, 37, 221, amp8,done_osc[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:115: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o9 (en_osc[9],clk_fm, 35, 234, amp9,done_osc[9]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:116: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o10 (en_osc[10],clk_fm, 33, 248, amp10,done_osc[10]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:117: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o11 (en_osc[11],clk_fm, 31, 264, amp11,done_osc[11]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:119: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro0 (clk_fm,done_osc[0],teclas,amp0,amp_fir0,done_filtro[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:120: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro1 (clk_fm,done_osc[1],teclas,amp1,amp_fir1,done_filtro[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:121: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro2 (clk_fm,done_osc[2],teclas,amp2,amp_fir2,done_filtro[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:122: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro3 (clk_fm,done_osc[3],teclas,amp3,amp_fir3,done_filtro[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:123: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro4 (clk_fm,done_osc[4],teclas,amp4,amp_fir4,done_filtro[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:124: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro5 (clk_fm,done_osc[5],teclas,amp5,amp_fir5,done_filtro[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:125: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro6 (clk_fm,done_osc[6],teclas,amp6,amp_fir6,done_filtro[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:126: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro7 (clk_fm,done_osc[7],teclas,amp7,amp_fir7,done_filtro[7]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:127: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro8 (clk_fm,done_osc[8],teclas,amp8,amp_fir8,done_filtro[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:128: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro9 (clk_fm,done_osc[9],teclas,amp9,amp_fir9,done_filtro[9]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:129: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro10 (clk_fm,done_osc[10],teclas,amp10,amp_fir10,done_filtro[10]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:130: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro11 (clk_fm,done_osc[11],teclas,amp11,amp_fir11,done_filtro[11]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 69 warning(s)\n' | 307,811 | module | module debouncer(
input clk,
input key,
output deb_key
);
reg [15:0] cont=0;
reg key_status=0;
reg key_pressed0;
reg key_pressed1;
always @(posedge clk)begin
key_pressed0<=key;
end
always @(posedge clk)begin
key_pressed1<=key_pressed0;
end
always @(posedge clk)begin
case(key_status)
1'b0: begin
if (key_pressed1==1)begin
cont<=0;
key_status<=1;end
end
1'b1:begin
cont<=cont+1;
if (cont== 14'd16383)
key_status<=0;
end
endcase
end
assign deb_key=key_status;
endmodule | module debouncer(
input clk,
input key,
output deb_key
); |
reg [15:0] cont=0;
reg key_status=0;
reg key_pressed0;
reg key_pressed1;
always @(posedge clk)begin
key_pressed0<=key;
end
always @(posedge clk)begin
key_pressed1<=key_pressed0;
end
always @(posedge clk)begin
case(key_status)
1'b0: begin
if (key_pressed1==1)begin
cont<=0;
key_status<=1;end
end
1'b1:begin
cont<=cont+1;
if (cont== 14'd16383)
key_status<=0;
end
endcase
end
assign deb_key=key_status;
endmodule | 1 |
139,774 | data/full_repos/permissive/89810125/rtl/wb_sintesis.v | 89,810,125 | wb_sintesis.v | v | 848 | 155 | [] | [] | [] | null | line:342: before: "coeff" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:152: Signal definition not found, creating implicitly: \'led1\'\n assign led1 = | en_osc;\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:153: Signal definition not found, creating implicitly: \'led2\'\n : ... Suggested alternative: \'led1\'\n assign led2 = | teclas;\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:796: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:799: Signal definition not found, creating implicitly: \'sel\'\nassign sel = teclado[12];\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:677: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:679: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:663: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:665: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:650: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:652: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:636: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:638: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:744: Operator LT expects 7 bits on the LHS, but LHS\'s VARREF \'cont\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.pwm0\n if (cont<sint_data)\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:692: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.suma1\n reg [6:0] rp = 6\'b0; \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:709: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:713: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:712: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:306: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 16 bits.\n : ... In instance wb_sintesis.sint0.filtro11\n data_f <= (multi0+multi1+multi2+multi3+multi4+multi5+multi6+multi7+multi8+multi9+multi10)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:231: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:31: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'14\'h3fff\' generates 14 bits.\n : ... In instance wb_sintesis.sint0.deb0\n if (cont== 14\'d16383)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:106: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o0 (en_osc[0],clk_fm, 59, 138, amp0,done_osc[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:107: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o1 (en_osc[1],clk_fm, 55, 148, amp1,done_osc[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:108: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o2 (en_osc[2],clk_fm, 52, 157, amp2,done_osc[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:109: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o3 (en_osc[3],clk_fm, 49, 167, amp3,done_osc[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:110: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o4 (en_osc[4],clk_fm, 46, 178, amp4,done_osc[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:111: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o5 (en_osc[5],clk_fm, 44, 186, amp5,done_osc[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:112: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o6 (en_osc[6],clk_fm, 41, 199, amp6,done_osc[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:113: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o7 (en_osc[7],clk_fm, 39, 210, amp7,done_osc[7]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:114: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o8 (en_osc[8],clk_fm, 37, 221, amp8,done_osc[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:115: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o9 (en_osc[9],clk_fm, 35, 234, amp9,done_osc[9]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:116: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o10 (en_osc[10],clk_fm, 33, 248, amp10,done_osc[10]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:117: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o11 (en_osc[11],clk_fm, 31, 264, amp11,done_osc[11]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:119: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro0 (clk_fm,done_osc[0],teclas,amp0,amp_fir0,done_filtro[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:120: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro1 (clk_fm,done_osc[1],teclas,amp1,amp_fir1,done_filtro[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:121: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro2 (clk_fm,done_osc[2],teclas,amp2,amp_fir2,done_filtro[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:122: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro3 (clk_fm,done_osc[3],teclas,amp3,amp_fir3,done_filtro[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:123: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro4 (clk_fm,done_osc[4],teclas,amp4,amp_fir4,done_filtro[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:124: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro5 (clk_fm,done_osc[5],teclas,amp5,amp_fir5,done_filtro[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:125: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro6 (clk_fm,done_osc[6],teclas,amp6,amp_fir6,done_filtro[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:126: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro7 (clk_fm,done_osc[7],teclas,amp7,amp_fir7,done_filtro[7]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:127: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro8 (clk_fm,done_osc[8],teclas,amp8,amp_fir8,done_filtro[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:128: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro9 (clk_fm,done_osc[9],teclas,amp9,amp_fir9,done_filtro[9]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:129: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro10 (clk_fm,done_osc[10],teclas,amp10,amp_fir10,done_filtro[10]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:130: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro11 (clk_fm,done_osc[11],teclas,amp11,amp_fir11,done_filtro[11]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 69 warning(s)\n' | 307,811 | module | module sintesis(
input [12:0] teclado,
input clk,
output pulse_data,
output busy_pwm
);
wire debtecla1;
wire debtecla2;
wire debtecla3;
wire debtecla4;
debouncer deb0 (clk,teclado[0],debtecla1);
wire [11:0] teclas;
assign teclas[1]= 0;
assign teclas[2]= 0;
assign teclas[3]= 0;
assign teclas[4]= 0;
assign teclas[5]= 0;
assign teclas[6]= 0;
assign teclas[7]= 0;
assign teclas[8]= 0;
assign teclas[9]= 0;
assign teclas[10]= 0;
assign teclas[11]= 0;
assign teclas[0]=debtecla1;
wire sel, start;
assign sel = 0;
assign start = 1;
wire clk_fm;
clkg clk_fm0 (clk,1600,clk_fm);
wire clk_1u;
clkg clk_1u0 (clk,25,clk_1u);
wire [11:0] en_osc;
wire [11:0] done_osc;
wire [11:0] done_filtro;
wire [11:0] start_env;
wire [11:0] busyf;
wire [11:0] done_env;
wire reset;
assign reset=sel;
wire [6:0] amp_final;
wire [6:0] amp0,amp1,amp2,amp3,amp4,amp5,amp6,amp7,amp8,amp9,amp10,amp11;
wire [6:0] amp_fir0,amp_fir1,amp_fir2,amp_fir3,amp_fir4,amp_fir5,amp_fir6,amp_fir7,amp_fir8,amp_fir9,amp_fir10,amp_fir11;
wire [6:0] aenv0,aenv1,aenv2,aenv3,aenv4,aenv5,aenv6,aenv7,aenv8,aenv9,aenv10,aenv11;
wire [13:0] tiempo0,tiempo1,tiempo2,tiempo3,tiempo4,tiempo5,tiempo6,tiempo7,tiempo8,tiempo9,tiempo10,tiempo11;
wire [9:0] amp_env_total;
wire done_suma, start_suma;
assign start_env = done_filtro;
seleccion s0 (clk_fm, teclas[0], start, tiempo0, en_osc[0], busyf[0]);
seleccion s1 (clk_fm, teclas[1], start, tiempo1, en_osc[1], busyf[1]);
seleccion s2 (clk_fm, teclas[2], start, tiempo2, en_osc[2], busyf[2]);
seleccion s3 (clk_fm, teclas[3], start, tiempo3, en_osc[3], busyf[3]);
seleccion s4 (clk_fm, teclas[4], start, tiempo4, en_osc[4], busyf[4]);
seleccion s5 (clk_fm, teclas[5], start, tiempo5, en_osc[5], busyf[5]);
seleccion s6 (clk_fm, teclas[6], start, tiempo6, en_osc[6], busyf[6]);
seleccion s7 (clk_fm, teclas[7], start, tiempo7, en_osc[7], busyf[7]);
seleccion s8 (clk_fm, teclas[8], start, tiempo8, en_osc[8], busyf[8]);
seleccion s9 (clk_fm, teclas[9], start, tiempo9, en_osc[9], busyf[9]);
seleccion s10 (clk_fm, teclas[10], start, tiempo10, en_osc[10], busyf[10]);
seleccion s11 (clk_fm, teclas[11], start, tiempo11, en_osc[11], busyf[11]);
oscilador o0 (en_osc[0],clk_fm, 59, 138, amp0,done_osc[0]);
oscilador o1 (en_osc[1],clk_fm, 55, 148, amp1,done_osc[1]);
oscilador o2 (en_osc[2],clk_fm, 52, 157, amp2,done_osc[2]);
oscilador o3 (en_osc[3],clk_fm, 49, 167, amp3,done_osc[3]);
oscilador o4 (en_osc[4],clk_fm, 46, 178, amp4,done_osc[4]);
oscilador o5 (en_osc[5],clk_fm, 44, 186, amp5,done_osc[5]);
oscilador o6 (en_osc[6],clk_fm, 41, 199, amp6,done_osc[6]);
oscilador o7 (en_osc[7],clk_fm, 39, 210, amp7,done_osc[7]);
oscilador o8 (en_osc[8],clk_fm, 37, 221, amp8,done_osc[8]);
oscilador o9 (en_osc[9],clk_fm, 35, 234, amp9,done_osc[9]);
oscilador o10 (en_osc[10],clk_fm, 33, 248, amp10,done_osc[10]);
oscilador o11 (en_osc[11],clk_fm, 31, 264, amp11,done_osc[11]);
FIR filtro0 (clk_fm,done_osc[0],teclas,amp0,amp_fir0,done_filtro[0]);
FIR filtro1 (clk_fm,done_osc[1],teclas,amp1,amp_fir1,done_filtro[1]);
FIR filtro2 (clk_fm,done_osc[2],teclas,amp2,amp_fir2,done_filtro[2]);
FIR filtro3 (clk_fm,done_osc[3],teclas,amp3,amp_fir3,done_filtro[3]);
FIR filtro4 (clk_fm,done_osc[4],teclas,amp4,amp_fir4,done_filtro[4]);
FIR filtro5 (clk_fm,done_osc[5],teclas,amp5,amp_fir5,done_filtro[5]);
FIR filtro6 (clk_fm,done_osc[6],teclas,amp6,amp_fir6,done_filtro[6]);
FIR filtro7 (clk_fm,done_osc[7],teclas,amp7,amp_fir7,done_filtro[7]);
FIR filtro8 (clk_fm,done_osc[8],teclas,amp8,amp_fir8,done_filtro[8]);
FIR filtro9 (clk_fm,done_osc[9],teclas,amp9,amp_fir9,done_filtro[9]);
FIR filtro10 (clk_fm,done_osc[10],teclas,amp10,amp_fir10,done_filtro[10]);
FIR filtro11 (clk_fm,done_osc[11],teclas,amp11,amp_fir11,done_filtro[11]);
envolvente env0 (tiempo0,clk_fm,start_env[0],reset,amp_fir0,done_env[0],aenv0);
envolvente env1 (tiempo1,clk_fm,start_env[1],reset,amp_fir1,done_env[1],aenv1);
envolvente env2 (tiempo2,clk_fm,start_env[2],reset,amp_fir2,done_env[2],aenv2);
envolvente env3 (tiempo3,clk_fm,start_env[3],reset,amp_fir3,done_env[3],aenv3);
envolvente env4 (tiempo4,clk_fm,start_env[4],reset,amp_fir4,done_env[4],aenv4);
envolvente env5 (tiempo5,clk_fm,start_env[5],reset,amp_fir5,done_env[5],aenv5);
envolvente env6 (tiempo6,clk_fm,start_env[6],reset,amp_fir6,done_env[6],aenv6);
envolvente env7 (tiempo7,clk_fm,start_env[7],reset,amp_fir7,done_env[7],aenv7);
envolvente env8 (tiempo8,clk_fm,start_env[8],reset,amp_fir8,done_env[8],aenv8);
envolvente env9 (tiempo9,clk_fm,start_env[9],reset,amp_fir9,done_env[9],aenv9);
envolvente env10 (tiempo10,clk_fm,start_env[10],reset,amp_fir10,done_env[10],aenv10);
envolvente env11 (tiempo11,clk_fm,start_env[11],reset,amp_fir11,done_env[11],aenv11);
assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11;
assign start_suma = | done_env;
suma_amp suma1 (clk_1u,start_suma,amp_env_total,en_osc,done_suma,amp_final);
assign done_suma =1;
pwm pwm0 (amp_final,done_suma,clk_1u,pulse_data,busy_pwm);
assign led1 = | en_osc;
assign led2 = | teclas;
endmodule | module sintesis(
input [12:0] teclado,
input clk,
output pulse_data,
output busy_pwm
); |
wire debtecla1;
wire debtecla2;
wire debtecla3;
wire debtecla4;
debouncer deb0 (clk,teclado[0],debtecla1);
wire [11:0] teclas;
assign teclas[1]= 0;
assign teclas[2]= 0;
assign teclas[3]= 0;
assign teclas[4]= 0;
assign teclas[5]= 0;
assign teclas[6]= 0;
assign teclas[7]= 0;
assign teclas[8]= 0;
assign teclas[9]= 0;
assign teclas[10]= 0;
assign teclas[11]= 0;
assign teclas[0]=debtecla1;
wire sel, start;
assign sel = 0;
assign start = 1;
wire clk_fm;
clkg clk_fm0 (clk,1600,clk_fm);
wire clk_1u;
clkg clk_1u0 (clk,25,clk_1u);
wire [11:0] en_osc;
wire [11:0] done_osc;
wire [11:0] done_filtro;
wire [11:0] start_env;
wire [11:0] busyf;
wire [11:0] done_env;
wire reset;
assign reset=sel;
wire [6:0] amp_final;
wire [6:0] amp0,amp1,amp2,amp3,amp4,amp5,amp6,amp7,amp8,amp9,amp10,amp11;
wire [6:0] amp_fir0,amp_fir1,amp_fir2,amp_fir3,amp_fir4,amp_fir5,amp_fir6,amp_fir7,amp_fir8,amp_fir9,amp_fir10,amp_fir11;
wire [6:0] aenv0,aenv1,aenv2,aenv3,aenv4,aenv5,aenv6,aenv7,aenv8,aenv9,aenv10,aenv11;
wire [13:0] tiempo0,tiempo1,tiempo2,tiempo3,tiempo4,tiempo5,tiempo6,tiempo7,tiempo8,tiempo9,tiempo10,tiempo11;
wire [9:0] amp_env_total;
wire done_suma, start_suma;
assign start_env = done_filtro;
seleccion s0 (clk_fm, teclas[0], start, tiempo0, en_osc[0], busyf[0]);
seleccion s1 (clk_fm, teclas[1], start, tiempo1, en_osc[1], busyf[1]);
seleccion s2 (clk_fm, teclas[2], start, tiempo2, en_osc[2], busyf[2]);
seleccion s3 (clk_fm, teclas[3], start, tiempo3, en_osc[3], busyf[3]);
seleccion s4 (clk_fm, teclas[4], start, tiempo4, en_osc[4], busyf[4]);
seleccion s5 (clk_fm, teclas[5], start, tiempo5, en_osc[5], busyf[5]);
seleccion s6 (clk_fm, teclas[6], start, tiempo6, en_osc[6], busyf[6]);
seleccion s7 (clk_fm, teclas[7], start, tiempo7, en_osc[7], busyf[7]);
seleccion s8 (clk_fm, teclas[8], start, tiempo8, en_osc[8], busyf[8]);
seleccion s9 (clk_fm, teclas[9], start, tiempo9, en_osc[9], busyf[9]);
seleccion s10 (clk_fm, teclas[10], start, tiempo10, en_osc[10], busyf[10]);
seleccion s11 (clk_fm, teclas[11], start, tiempo11, en_osc[11], busyf[11]);
oscilador o0 (en_osc[0],clk_fm, 59, 138, amp0,done_osc[0]);
oscilador o1 (en_osc[1],clk_fm, 55, 148, amp1,done_osc[1]);
oscilador o2 (en_osc[2],clk_fm, 52, 157, amp2,done_osc[2]);
oscilador o3 (en_osc[3],clk_fm, 49, 167, amp3,done_osc[3]);
oscilador o4 (en_osc[4],clk_fm, 46, 178, amp4,done_osc[4]);
oscilador o5 (en_osc[5],clk_fm, 44, 186, amp5,done_osc[5]);
oscilador o6 (en_osc[6],clk_fm, 41, 199, amp6,done_osc[6]);
oscilador o7 (en_osc[7],clk_fm, 39, 210, amp7,done_osc[7]);
oscilador o8 (en_osc[8],clk_fm, 37, 221, amp8,done_osc[8]);
oscilador o9 (en_osc[9],clk_fm, 35, 234, amp9,done_osc[9]);
oscilador o10 (en_osc[10],clk_fm, 33, 248, amp10,done_osc[10]);
oscilador o11 (en_osc[11],clk_fm, 31, 264, amp11,done_osc[11]);
FIR filtro0 (clk_fm,done_osc[0],teclas,amp0,amp_fir0,done_filtro[0]);
FIR filtro1 (clk_fm,done_osc[1],teclas,amp1,amp_fir1,done_filtro[1]);
FIR filtro2 (clk_fm,done_osc[2],teclas,amp2,amp_fir2,done_filtro[2]);
FIR filtro3 (clk_fm,done_osc[3],teclas,amp3,amp_fir3,done_filtro[3]);
FIR filtro4 (clk_fm,done_osc[4],teclas,amp4,amp_fir4,done_filtro[4]);
FIR filtro5 (clk_fm,done_osc[5],teclas,amp5,amp_fir5,done_filtro[5]);
FIR filtro6 (clk_fm,done_osc[6],teclas,amp6,amp_fir6,done_filtro[6]);
FIR filtro7 (clk_fm,done_osc[7],teclas,amp7,amp_fir7,done_filtro[7]);
FIR filtro8 (clk_fm,done_osc[8],teclas,amp8,amp_fir8,done_filtro[8]);
FIR filtro9 (clk_fm,done_osc[9],teclas,amp9,amp_fir9,done_filtro[9]);
FIR filtro10 (clk_fm,done_osc[10],teclas,amp10,amp_fir10,done_filtro[10]);
FIR filtro11 (clk_fm,done_osc[11],teclas,amp11,amp_fir11,done_filtro[11]);
envolvente env0 (tiempo0,clk_fm,start_env[0],reset,amp_fir0,done_env[0],aenv0);
envolvente env1 (tiempo1,clk_fm,start_env[1],reset,amp_fir1,done_env[1],aenv1);
envolvente env2 (tiempo2,clk_fm,start_env[2],reset,amp_fir2,done_env[2],aenv2);
envolvente env3 (tiempo3,clk_fm,start_env[3],reset,amp_fir3,done_env[3],aenv3);
envolvente env4 (tiempo4,clk_fm,start_env[4],reset,amp_fir4,done_env[4],aenv4);
envolvente env5 (tiempo5,clk_fm,start_env[5],reset,amp_fir5,done_env[5],aenv5);
envolvente env6 (tiempo6,clk_fm,start_env[6],reset,amp_fir6,done_env[6],aenv6);
envolvente env7 (tiempo7,clk_fm,start_env[7],reset,amp_fir7,done_env[7],aenv7);
envolvente env8 (tiempo8,clk_fm,start_env[8],reset,amp_fir8,done_env[8],aenv8);
envolvente env9 (tiempo9,clk_fm,start_env[9],reset,amp_fir9,done_env[9],aenv9);
envolvente env10 (tiempo10,clk_fm,start_env[10],reset,amp_fir10,done_env[10],aenv10);
envolvente env11 (tiempo11,clk_fm,start_env[11],reset,amp_fir11,done_env[11],aenv11);
assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11;
assign start_suma = | done_env;
suma_amp suma1 (clk_1u,start_suma,amp_env_total,en_osc,done_suma,amp_final);
assign done_suma =1;
pwm pwm0 (amp_final,done_suma,clk_1u,pulse_data,busy_pwm);
assign led1 = | en_osc;
assign led2 = | teclas;
endmodule | 1 |
139,775 | data/full_repos/permissive/89810125/rtl/wb_sintesis.v | 89,810,125 | wb_sintesis.v | v | 848 | 155 | [] | [] | [] | null | line:342: before: "coeff" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:152: Signal definition not found, creating implicitly: \'led1\'\n assign led1 = | en_osc;\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:153: Signal definition not found, creating implicitly: \'led2\'\n : ... Suggested alternative: \'led1\'\n assign led2 = | teclas;\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:796: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:799: Signal definition not found, creating implicitly: \'sel\'\nassign sel = teclado[12];\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:677: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:679: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:663: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:665: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:650: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:652: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:636: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:638: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:744: Operator LT expects 7 bits on the LHS, but LHS\'s VARREF \'cont\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.pwm0\n if (cont<sint_data)\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:692: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.suma1\n reg [6:0] rp = 6\'b0; \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:709: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:713: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:712: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:306: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 16 bits.\n : ... In instance wb_sintesis.sint0.filtro11\n data_f <= (multi0+multi1+multi2+multi3+multi4+multi5+multi6+multi7+multi8+multi9+multi10)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:231: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:31: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'14\'h3fff\' generates 14 bits.\n : ... In instance wb_sintesis.sint0.deb0\n if (cont== 14\'d16383)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:106: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o0 (en_osc[0],clk_fm, 59, 138, amp0,done_osc[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:107: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o1 (en_osc[1],clk_fm, 55, 148, amp1,done_osc[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:108: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o2 (en_osc[2],clk_fm, 52, 157, amp2,done_osc[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:109: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o3 (en_osc[3],clk_fm, 49, 167, amp3,done_osc[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:110: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o4 (en_osc[4],clk_fm, 46, 178, amp4,done_osc[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:111: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o5 (en_osc[5],clk_fm, 44, 186, amp5,done_osc[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:112: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o6 (en_osc[6],clk_fm, 41, 199, amp6,done_osc[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:113: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o7 (en_osc[7],clk_fm, 39, 210, amp7,done_osc[7]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:114: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o8 (en_osc[8],clk_fm, 37, 221, amp8,done_osc[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:115: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o9 (en_osc[9],clk_fm, 35, 234, amp9,done_osc[9]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:116: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o10 (en_osc[10],clk_fm, 33, 248, amp10,done_osc[10]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:117: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o11 (en_osc[11],clk_fm, 31, 264, amp11,done_osc[11]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:119: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro0 (clk_fm,done_osc[0],teclas,amp0,amp_fir0,done_filtro[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:120: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro1 (clk_fm,done_osc[1],teclas,amp1,amp_fir1,done_filtro[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:121: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro2 (clk_fm,done_osc[2],teclas,amp2,amp_fir2,done_filtro[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:122: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro3 (clk_fm,done_osc[3],teclas,amp3,amp_fir3,done_filtro[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:123: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro4 (clk_fm,done_osc[4],teclas,amp4,amp_fir4,done_filtro[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:124: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro5 (clk_fm,done_osc[5],teclas,amp5,amp_fir5,done_filtro[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:125: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro6 (clk_fm,done_osc[6],teclas,amp6,amp_fir6,done_filtro[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:126: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro7 (clk_fm,done_osc[7],teclas,amp7,amp_fir7,done_filtro[7]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:127: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro8 (clk_fm,done_osc[8],teclas,amp8,amp_fir8,done_filtro[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:128: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro9 (clk_fm,done_osc[9],teclas,amp9,amp_fir9,done_filtro[9]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:129: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro10 (clk_fm,done_osc[10],teclas,amp10,amp_fir10,done_filtro[10]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:130: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro11 (clk_fm,done_osc[11],teclas,amp11,amp_fir11,done_filtro[11]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 69 warning(s)\n' | 307,811 | module | module clkg(
input clk,
input [14:0] factor,
output clkp
);
reg clkpr=1'b0;
reg [14:0] cont=15'b0;
always @ (posedge clk) begin
if(cont==factor) begin
cont<=1;
clkpr=~clkpr;
end
else cont<=cont+1;
end
assign clkp=clkpr;
endmodule | module clkg(
input clk,
input [14:0] factor,
output clkp
); |
reg clkpr=1'b0;
reg [14:0] cont=15'b0;
always @ (posedge clk) begin
if(cont==factor) begin
cont<=1;
clkpr=~clkpr;
end
else cont<=cont+1;
end
assign clkp=clkpr;
endmodule | 1 |
139,776 | data/full_repos/permissive/89810125/rtl/wb_sintesis.v | 89,810,125 | wb_sintesis.v | v | 848 | 155 | [] | [] | [] | null | line:342: before: "coeff" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:152: Signal definition not found, creating implicitly: \'led1\'\n assign led1 = | en_osc;\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:153: Signal definition not found, creating implicitly: \'led2\'\n : ... Suggested alternative: \'led1\'\n assign led2 = | teclas;\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:796: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:799: Signal definition not found, creating implicitly: \'sel\'\nassign sel = teclado[12];\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:677: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:679: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:663: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:665: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:650: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:652: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:636: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:638: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:744: Operator LT expects 7 bits on the LHS, but LHS\'s VARREF \'cont\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.pwm0\n if (cont<sint_data)\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:692: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.suma1\n reg [6:0] rp = 6\'b0; \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:709: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:713: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:712: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:306: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 16 bits.\n : ... In instance wb_sintesis.sint0.filtro11\n data_f <= (multi0+multi1+multi2+multi3+multi4+multi5+multi6+multi7+multi8+multi9+multi10)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:231: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:31: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'14\'h3fff\' generates 14 bits.\n : ... In instance wb_sintesis.sint0.deb0\n if (cont== 14\'d16383)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:106: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o0 (en_osc[0],clk_fm, 59, 138, amp0,done_osc[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:107: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o1 (en_osc[1],clk_fm, 55, 148, amp1,done_osc[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:108: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o2 (en_osc[2],clk_fm, 52, 157, amp2,done_osc[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:109: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o3 (en_osc[3],clk_fm, 49, 167, amp3,done_osc[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:110: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o4 (en_osc[4],clk_fm, 46, 178, amp4,done_osc[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:111: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o5 (en_osc[5],clk_fm, 44, 186, amp5,done_osc[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:112: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o6 (en_osc[6],clk_fm, 41, 199, amp6,done_osc[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:113: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o7 (en_osc[7],clk_fm, 39, 210, amp7,done_osc[7]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:114: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o8 (en_osc[8],clk_fm, 37, 221, amp8,done_osc[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:115: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o9 (en_osc[9],clk_fm, 35, 234, amp9,done_osc[9]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:116: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o10 (en_osc[10],clk_fm, 33, 248, amp10,done_osc[10]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:117: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o11 (en_osc[11],clk_fm, 31, 264, amp11,done_osc[11]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:119: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro0 (clk_fm,done_osc[0],teclas,amp0,amp_fir0,done_filtro[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:120: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro1 (clk_fm,done_osc[1],teclas,amp1,amp_fir1,done_filtro[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:121: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro2 (clk_fm,done_osc[2],teclas,amp2,amp_fir2,done_filtro[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:122: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro3 (clk_fm,done_osc[3],teclas,amp3,amp_fir3,done_filtro[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:123: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro4 (clk_fm,done_osc[4],teclas,amp4,amp_fir4,done_filtro[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:124: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro5 (clk_fm,done_osc[5],teclas,amp5,amp_fir5,done_filtro[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:125: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro6 (clk_fm,done_osc[6],teclas,amp6,amp_fir6,done_filtro[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:126: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro7 (clk_fm,done_osc[7],teclas,amp7,amp_fir7,done_filtro[7]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:127: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro8 (clk_fm,done_osc[8],teclas,amp8,amp_fir8,done_filtro[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:128: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro9 (clk_fm,done_osc[9],teclas,amp9,amp_fir9,done_filtro[9]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:129: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro10 (clk_fm,done_osc[10],teclas,amp10,amp_fir10,done_filtro[10]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:130: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro11 (clk_fm,done_osc[11],teclas,amp11,amp_fir11,done_filtro[11]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 69 warning(s)\n' | 307,811 | module | module seleccion (
input clk,
input tecla,
input start,
output [13:0] cont,
output reg en,
output busyf
);
reg [13:0] cont0 = 14'b0;
reg busy1 = 1'b0;
reg busy2 = 1'b0;
wire busyr;
assign busyr = busy1 ^ busy2;
always @ (posedge clk) begin
if (start) begin
if (busyr == 1'b0) begin
en <= tecla;
if (en) busy1 <= ~busy1;
end
else begin
if (cont0<14'd15625)
cont0<=cont+1;
else begin
cont0<=14'b0;
busy2<=~busy2;
end
end
end
end
assign cont = cont0;
assign busyf = busyr;
endmodule | module seleccion (
input clk,
input tecla,
input start,
output [13:0] cont,
output reg en,
output busyf
); |
reg [13:0] cont0 = 14'b0;
reg busy1 = 1'b0;
reg busy2 = 1'b0;
wire busyr;
assign busyr = busy1 ^ busy2;
always @ (posedge clk) begin
if (start) begin
if (busyr == 1'b0) begin
en <= tecla;
if (en) busy1 <= ~busy1;
end
else begin
if (cont0<14'd15625)
cont0<=cont+1;
else begin
cont0<=14'b0;
busy2<=~busy2;
end
end
end
end
assign cont = cont0;
assign busyf = busyr;
endmodule | 1 |
139,777 | data/full_repos/permissive/89810125/rtl/wb_sintesis.v | 89,810,125 | wb_sintesis.v | v | 848 | 155 | [] | [] | [] | null | line:342: before: "coeff" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:152: Signal definition not found, creating implicitly: \'led1\'\n assign led1 = | en_osc;\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:153: Signal definition not found, creating implicitly: \'led2\'\n : ... Suggested alternative: \'led1\'\n assign led2 = | teclas;\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:796: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:799: Signal definition not found, creating implicitly: \'sel\'\nassign sel = teclado[12];\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:677: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:679: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:663: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:665: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:650: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:652: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:636: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:638: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:744: Operator LT expects 7 bits on the LHS, but LHS\'s VARREF \'cont\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.pwm0\n if (cont<sint_data)\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:692: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.suma1\n reg [6:0] rp = 6\'b0; \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:709: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:713: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:712: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:306: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 16 bits.\n : ... In instance wb_sintesis.sint0.filtro11\n data_f <= (multi0+multi1+multi2+multi3+multi4+multi5+multi6+multi7+multi8+multi9+multi10)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:231: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:31: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'14\'h3fff\' generates 14 bits.\n : ... In instance wb_sintesis.sint0.deb0\n if (cont== 14\'d16383)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:106: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o0 (en_osc[0],clk_fm, 59, 138, amp0,done_osc[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:107: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o1 (en_osc[1],clk_fm, 55, 148, amp1,done_osc[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:108: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o2 (en_osc[2],clk_fm, 52, 157, amp2,done_osc[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:109: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o3 (en_osc[3],clk_fm, 49, 167, amp3,done_osc[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:110: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o4 (en_osc[4],clk_fm, 46, 178, amp4,done_osc[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:111: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o5 (en_osc[5],clk_fm, 44, 186, amp5,done_osc[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:112: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o6 (en_osc[6],clk_fm, 41, 199, amp6,done_osc[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:113: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o7 (en_osc[7],clk_fm, 39, 210, amp7,done_osc[7]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:114: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o8 (en_osc[8],clk_fm, 37, 221, amp8,done_osc[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:115: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o9 (en_osc[9],clk_fm, 35, 234, amp9,done_osc[9]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:116: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o10 (en_osc[10],clk_fm, 33, 248, amp10,done_osc[10]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:117: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o11 (en_osc[11],clk_fm, 31, 264, amp11,done_osc[11]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:119: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro0 (clk_fm,done_osc[0],teclas,amp0,amp_fir0,done_filtro[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:120: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro1 (clk_fm,done_osc[1],teclas,amp1,amp_fir1,done_filtro[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:121: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro2 (clk_fm,done_osc[2],teclas,amp2,amp_fir2,done_filtro[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:122: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro3 (clk_fm,done_osc[3],teclas,amp3,amp_fir3,done_filtro[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:123: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro4 (clk_fm,done_osc[4],teclas,amp4,amp_fir4,done_filtro[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:124: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro5 (clk_fm,done_osc[5],teclas,amp5,amp_fir5,done_filtro[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:125: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro6 (clk_fm,done_osc[6],teclas,amp6,amp_fir6,done_filtro[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:126: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro7 (clk_fm,done_osc[7],teclas,amp7,amp_fir7,done_filtro[7]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:127: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro8 (clk_fm,done_osc[8],teclas,amp8,amp_fir8,done_filtro[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:128: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro9 (clk_fm,done_osc[9],teclas,amp9,amp_fir9,done_filtro[9]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:129: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro10 (clk_fm,done_osc[10],teclas,amp10,amp_fir10,done_filtro[10]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:130: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro11 (clk_fm,done_osc[11],teclas,amp11,amp_fir11,done_filtro[11]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 69 warning(s)\n' | 307,811 | module | module oscilador(
input en,
input clk,
input [5:0] nmuestras,
input [8:0] factor,
output [5:0] amp1,
output reg done_osc
);
reg [5:0] amp;
reg [5:0] cont=0;
always @ (posedge clk) begin
if (en==1) begin
amp<=factor*cont/128;
cont<=cont+1;
done_osc <= 1;
if (cont==nmuestras)
cont<=0;
end
else begin
amp<=0;
done_osc <= 0;
end
end
assign amp1=amp;
endmodule | module oscilador(
input en,
input clk,
input [5:0] nmuestras,
input [8:0] factor,
output [5:0] amp1,
output reg done_osc
); |
reg [5:0] amp;
reg [5:0] cont=0;
always @ (posedge clk) begin
if (en==1) begin
amp<=factor*cont/128;
cont<=cont+1;
done_osc <= 1;
if (cont==nmuestras)
cont<=0;
end
else begin
amp<=0;
done_osc <= 0;
end
end
assign amp1=amp;
endmodule | 1 |
139,778 | data/full_repos/permissive/89810125/rtl/wb_sintesis.v | 89,810,125 | wb_sintesis.v | v | 848 | 155 | [] | [] | [] | null | line:342: before: "coeff" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:152: Signal definition not found, creating implicitly: \'led1\'\n assign led1 = | en_osc;\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:153: Signal definition not found, creating implicitly: \'led2\'\n : ... Suggested alternative: \'led1\'\n assign led2 = | teclas;\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:796: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:799: Signal definition not found, creating implicitly: \'sel\'\nassign sel = teclado[12];\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:677: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:679: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:663: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:665: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:650: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:652: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:636: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:638: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:744: Operator LT expects 7 bits on the LHS, but LHS\'s VARREF \'cont\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.pwm0\n if (cont<sint_data)\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:692: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.suma1\n reg [6:0] rp = 6\'b0; \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:709: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:713: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:712: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:306: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 16 bits.\n : ... In instance wb_sintesis.sint0.filtro11\n data_f <= (multi0+multi1+multi2+multi3+multi4+multi5+multi6+multi7+multi8+multi9+multi10)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:231: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:31: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'14\'h3fff\' generates 14 bits.\n : ... In instance wb_sintesis.sint0.deb0\n if (cont== 14\'d16383)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:106: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o0 (en_osc[0],clk_fm, 59, 138, amp0,done_osc[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:107: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o1 (en_osc[1],clk_fm, 55, 148, amp1,done_osc[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:108: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o2 (en_osc[2],clk_fm, 52, 157, amp2,done_osc[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:109: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o3 (en_osc[3],clk_fm, 49, 167, amp3,done_osc[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:110: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o4 (en_osc[4],clk_fm, 46, 178, amp4,done_osc[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:111: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o5 (en_osc[5],clk_fm, 44, 186, amp5,done_osc[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:112: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o6 (en_osc[6],clk_fm, 41, 199, amp6,done_osc[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:113: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o7 (en_osc[7],clk_fm, 39, 210, amp7,done_osc[7]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:114: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o8 (en_osc[8],clk_fm, 37, 221, amp8,done_osc[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:115: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o9 (en_osc[9],clk_fm, 35, 234, amp9,done_osc[9]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:116: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o10 (en_osc[10],clk_fm, 33, 248, amp10,done_osc[10]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:117: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o11 (en_osc[11],clk_fm, 31, 264, amp11,done_osc[11]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:119: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro0 (clk_fm,done_osc[0],teclas,amp0,amp_fir0,done_filtro[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:120: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro1 (clk_fm,done_osc[1],teclas,amp1,amp_fir1,done_filtro[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:121: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro2 (clk_fm,done_osc[2],teclas,amp2,amp_fir2,done_filtro[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:122: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro3 (clk_fm,done_osc[3],teclas,amp3,amp_fir3,done_filtro[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:123: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro4 (clk_fm,done_osc[4],teclas,amp4,amp_fir4,done_filtro[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:124: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro5 (clk_fm,done_osc[5],teclas,amp5,amp_fir5,done_filtro[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:125: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro6 (clk_fm,done_osc[6],teclas,amp6,amp_fir6,done_filtro[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:126: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro7 (clk_fm,done_osc[7],teclas,amp7,amp_fir7,done_filtro[7]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:127: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro8 (clk_fm,done_osc[8],teclas,amp8,amp_fir8,done_filtro[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:128: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro9 (clk_fm,done_osc[9],teclas,amp9,amp_fir9,done_filtro[9]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:129: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro10 (clk_fm,done_osc[10],teclas,amp10,amp_fir10,done_filtro[10]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:130: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro11 (clk_fm,done_osc[11],teclas,amp11,amp_fir11,done_filtro[11]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 69 warning(s)\n' | 307,811 | module | module FIR(
input clk,
input en_f,
input [11:0] tecla,
input [5:0] amp_o,
output reg [6:0] data_f,
output reg en_env
);
reg [5:0] amp_0, amp_1, amp_2, amp_3, amp_4, amp_5, amp_6, amp_7, amp_8, amp_9, amp_10;
reg [15:0] multi0, multi1, multi2, multi3, multi4, multi5, multi6, multi7, multi8, multi9, multi10;
wire [8:0] v_coeff0, v_coeff1, v_coeff2, v_coeff3, v_coeff4, v_coeff5, v_coeff6, v_coeff7, v_coeff8, v_coeff9, v_coeff10;
rom rom0(tecla,0,v_coeff0); rom rom1(tecla,1,v_coeff1); rom rom2(tecla,2,v_coeff2);
rom rom3(tecla,3,v_coeff3); rom rom4(tecla,4,v_coeff4); rom rom5(tecla,5,v_coeff5);
rom rom6(tecla,6,v_coeff6); rom rom7(tecla,7,v_coeff7); rom rom8(tecla,8,v_coeff8);
rom rom9(tecla,9,v_coeff9); rom rom10(tecla,10,v_coeff10);
initial begin
amp_0=0;
amp_1=0;
amp_2=0;
amp_3=0;
amp_4=0;
amp_5=0;
amp_6=0;
amp_7=0;
amp_8=0;
amp_9=0;
amp_10=0;
end
always @ (posedge clk) begin
if (en_f)begin
amp_0 <= amp_o;
amp_1 <= amp_0;
amp_2 <= amp_1;
amp_3 <= amp_2;
amp_4 <= amp_3;
amp_5 <= amp_4;
amp_6 <= amp_5;
amp_7 <= amp_6;
amp_8 <= amp_7;
amp_9 <= amp_8;
amp_10 <= amp_9;
multi0<= amp_0*v_coeff0;
multi1<= amp_1*v_coeff1;
multi2<= amp_2*v_coeff2;
multi3<= amp_3*v_coeff3;
multi4<= amp_4*v_coeff4;
multi5<= amp_5*v_coeff5;
multi6<= amp_6*v_coeff6;
multi7<= amp_7*v_coeff7;
multi8<= amp_8*v_coeff8;
multi9<= amp_9*v_coeff9;
multi10<= amp_10*v_coeff10;
en_env<=1;
data_f <= (multi0+multi1+multi2+multi3+multi4+multi5+multi6+multi7+multi8+multi9+multi10)/1024;
end
else begin
data_f <= 0;
en_env<=0;
end
end
endmodule | module FIR(
input clk,
input en_f,
input [11:0] tecla,
input [5:0] amp_o,
output reg [6:0] data_f,
output reg en_env
); |
reg [5:0] amp_0, amp_1, amp_2, amp_3, amp_4, amp_5, amp_6, amp_7, amp_8, amp_9, amp_10;
reg [15:0] multi0, multi1, multi2, multi3, multi4, multi5, multi6, multi7, multi8, multi9, multi10;
wire [8:0] v_coeff0, v_coeff1, v_coeff2, v_coeff3, v_coeff4, v_coeff5, v_coeff6, v_coeff7, v_coeff8, v_coeff9, v_coeff10;
rom rom0(tecla,0,v_coeff0); rom rom1(tecla,1,v_coeff1); rom rom2(tecla,2,v_coeff2);
rom rom3(tecla,3,v_coeff3); rom rom4(tecla,4,v_coeff4); rom rom5(tecla,5,v_coeff5);
rom rom6(tecla,6,v_coeff6); rom rom7(tecla,7,v_coeff7); rom rom8(tecla,8,v_coeff8);
rom rom9(tecla,9,v_coeff9); rom rom10(tecla,10,v_coeff10);
initial begin
amp_0=0;
amp_1=0;
amp_2=0;
amp_3=0;
amp_4=0;
amp_5=0;
amp_6=0;
amp_7=0;
amp_8=0;
amp_9=0;
amp_10=0;
end
always @ (posedge clk) begin
if (en_f)begin
amp_0 <= amp_o;
amp_1 <= amp_0;
amp_2 <= amp_1;
amp_3 <= amp_2;
amp_4 <= amp_3;
amp_5 <= amp_4;
amp_6 <= amp_5;
amp_7 <= amp_6;
amp_8 <= amp_7;
amp_9 <= amp_8;
amp_10 <= amp_9;
multi0<= amp_0*v_coeff0;
multi1<= amp_1*v_coeff1;
multi2<= amp_2*v_coeff2;
multi3<= amp_3*v_coeff3;
multi4<= amp_4*v_coeff4;
multi5<= amp_5*v_coeff5;
multi6<= amp_6*v_coeff6;
multi7<= amp_7*v_coeff7;
multi8<= amp_8*v_coeff8;
multi9<= amp_9*v_coeff9;
multi10<= amp_10*v_coeff10;
en_env<=1;
data_f <= (multi0+multi1+multi2+multi3+multi4+multi5+multi6+multi7+multi8+multi9+multi10)/1024;
end
else begin
data_f <= 0;
en_env<=0;
end
end
endmodule | 1 |
139,779 | data/full_repos/permissive/89810125/rtl/wb_sintesis.v | 89,810,125 | wb_sintesis.v | v | 848 | 155 | [] | [] | [] | null | line:342: before: "coeff" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:152: Signal definition not found, creating implicitly: \'led1\'\n assign led1 = | en_osc;\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:153: Signal definition not found, creating implicitly: \'led2\'\n : ... Suggested alternative: \'led1\'\n assign led2 = | teclas;\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:796: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:799: Signal definition not found, creating implicitly: \'sel\'\nassign sel = teclado[12];\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:677: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:679: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:663: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:665: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:650: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:652: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:636: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:638: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:744: Operator LT expects 7 bits on the LHS, but LHS\'s VARREF \'cont\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.pwm0\n if (cont<sint_data)\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:692: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.suma1\n reg [6:0] rp = 6\'b0; \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:709: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:713: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:712: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:306: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 16 bits.\n : ... In instance wb_sintesis.sint0.filtro11\n data_f <= (multi0+multi1+multi2+multi3+multi4+multi5+multi6+multi7+multi8+multi9+multi10)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:231: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:31: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'14\'h3fff\' generates 14 bits.\n : ... In instance wb_sintesis.sint0.deb0\n if (cont== 14\'d16383)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:106: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o0 (en_osc[0],clk_fm, 59, 138, amp0,done_osc[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:107: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o1 (en_osc[1],clk_fm, 55, 148, amp1,done_osc[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:108: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o2 (en_osc[2],clk_fm, 52, 157, amp2,done_osc[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:109: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o3 (en_osc[3],clk_fm, 49, 167, amp3,done_osc[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:110: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o4 (en_osc[4],clk_fm, 46, 178, amp4,done_osc[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:111: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o5 (en_osc[5],clk_fm, 44, 186, amp5,done_osc[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:112: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o6 (en_osc[6],clk_fm, 41, 199, amp6,done_osc[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:113: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o7 (en_osc[7],clk_fm, 39, 210, amp7,done_osc[7]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:114: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o8 (en_osc[8],clk_fm, 37, 221, amp8,done_osc[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:115: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o9 (en_osc[9],clk_fm, 35, 234, amp9,done_osc[9]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:116: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o10 (en_osc[10],clk_fm, 33, 248, amp10,done_osc[10]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:117: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o11 (en_osc[11],clk_fm, 31, 264, amp11,done_osc[11]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:119: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro0 (clk_fm,done_osc[0],teclas,amp0,amp_fir0,done_filtro[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:120: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro1 (clk_fm,done_osc[1],teclas,amp1,amp_fir1,done_filtro[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:121: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro2 (clk_fm,done_osc[2],teclas,amp2,amp_fir2,done_filtro[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:122: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro3 (clk_fm,done_osc[3],teclas,amp3,amp_fir3,done_filtro[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:123: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro4 (clk_fm,done_osc[4],teclas,amp4,amp_fir4,done_filtro[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:124: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro5 (clk_fm,done_osc[5],teclas,amp5,amp_fir5,done_filtro[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:125: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro6 (clk_fm,done_osc[6],teclas,amp6,amp_fir6,done_filtro[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:126: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro7 (clk_fm,done_osc[7],teclas,amp7,amp_fir7,done_filtro[7]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:127: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro8 (clk_fm,done_osc[8],teclas,amp8,amp_fir8,done_filtro[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:128: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro9 (clk_fm,done_osc[9],teclas,amp9,amp_fir9,done_filtro[9]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:129: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro10 (clk_fm,done_osc[10],teclas,amp10,amp_fir10,done_filtro[10]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:130: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro11 (clk_fm,done_osc[11],teclas,amp11,amp_fir11,done_filtro[11]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 69 warning(s)\n' | 307,811 | module | module rom (
input [11:0]sel,
input [3:0]adr,
output reg [8:0] coeff
);
always@(*)begin
case (sel)
12'd1:begin
case(adr)
4'b0000:coeff<=9'd10;
4'b0001:coeff<=9'd26;
4'b0010:coeff<=9'd72;
4'b0011:coeff<=9'd137;
4'b0100:coeff<=9'd193;
4'b0101:coeff<=9'd216;
4'b0110:coeff<=9'd193;
4'b0111:coeff<=9'd137;
4'b1000:coeff<=9'd72;
4'b1001:coeff<=9'd26;
4'b1010:coeff<=9'd10;
default coeff<=9'd0;
endcase
end
12'd2:begin
case(adr)
4'b0000:coeff<=9'd9;
4'b0001:coeff<=9'd26;
4'b0010:coeff<=9'd72;
4'b0011:coeff<=9'd137;
4'b0100:coeff<=9'd195;
4'b0101:coeff<=9'd218;
4'b0110:coeff<=9'd195;
4'b0111:coeff<=9'd137;
4'b1000:coeff<=9'd72;
4'b1001:coeff<=9'd26;
4'b1010:coeff<=9'd9;
default coeff<=9'd0;
endcase
end
12'd4:begin
case(adr)
4'b0000:coeff<=9'd9;
4'b0001:coeff<=9'd25;
4'b0010:coeff<=9'd72;
4'b0011:coeff<=9'd138;
4'b0100:coeff<=9'd198;
4'b0101:coeff<=9'd221;
4'b0110:coeff<=9'd198;
4'b0111:coeff<=9'd138;
4'b1000:coeff<=9'd72;
4'b1001:coeff<=9'd25;
4'b1010:coeff<=9'd9;
default coeff<=9'd0;
endcase
end
12'd8:begin
case(adr)
4'b0000:coeff<=9'd8;
4'b0001:coeff<=9'd24;
4'b0010:coeff<=9'd71;
4'b0011:coeff<=9'd139;
4'b0100:coeff<=9'd200;
4'b0101:coeff<=9'd225;
4'b0110:coeff<=9'd200;
4'b0111:coeff<=9'd139;
4'b1000:coeff<=9'd71;
4'b1001:coeff<=9'd24;
4'b1010:coeff<=9'd8;
default coeff<=9'd0;
endcase
end
12'd16:begin
case(adr)
4'b0000:coeff<=9'd7;
4'b0001:coeff<=9'd23;
4'b0010:coeff<=9'd70;
4'b0011:coeff<=9'd140;
4'b0100:coeff<=9'd204;
4'b0101:coeff<=9'd230;
4'b0110:coeff<=9'd204;
4'b0111:coeff<=9'd140;
4'b1000:coeff<=9'd70;
4'b1001:coeff<=9'd23;
4'b1010:coeff<=9'd7;
default coeff<=9'd0;
endcase
end
12'd32:begin
case(adr)
4'b0000:coeff<=9'd6;
4'b0001:coeff<=9'd22;
4'b0010:coeff<=9'd69;
4'b0011:coeff<=9'd141;
4'b0100:coeff<=9'd207;
4'b0101:coeff<=9'd234;
4'b0110:coeff<=9'd207;
4'b0111:coeff<=9'd141;
4'b1000:coeff<=9'd69;
4'b1001:coeff<=9'd22;
4'b1010:coeff<=9'd6;
default coeff<=9'd0;
endcase
end
12'd64:begin
case(adr)
4'b0000:coeff<=9'd5;
4'b0001:coeff<=9'd20;
4'b0010:coeff<=9'd68;
4'b0011:coeff<=9'd143;
4'b0100:coeff<=9'd212;
4'b0101:coeff<=9'd241;
4'b0110:coeff<=9'd212;
4'b0111:coeff<=9'd143;
4'b1000:coeff<=9'd68;
4'b1001:coeff<=9'd20;
4'b1010:coeff<=9'd5;
default coeff<=9'd0;
endcase
end
12'd128:begin
case(adr)
4'b0000:coeff<=9'd3;
4'b0001:coeff<=9'd18;
4'b0010:coeff<=9'd67;
4'b0011:coeff<=9'd144;
4'b0100:coeff<=9'd218;
4'b0101:coeff<=9'd248;
4'b0110:coeff<=9'd218;
4'b0111:coeff<=9'd144;
4'b1000:coeff<=9'd67;
4'b1001:coeff<=9'd18;
4'b1010:coeff<=9'd3;
default coeff<=9'd0;
endcase
end
12'd256:begin
case(adr)
4'b0000:coeff<=9'd2;
4'b0001:coeff<=9'd16;
4'b0010:coeff<=9'd65;
4'b0011:coeff<=9'd145;
4'b0100:coeff<=9'd223;
4'b0101:coeff<=9'd255;
4'b0110:coeff<=9'd233;
4'b0111:coeff<=9'd145;
4'b1000:coeff<=9'd65;
4'b1001:coeff<=9'd16;
4'b1010:coeff<=9'd2;
default coeff<=9'd0;
endcase
end
12'd512:begin
case(adr)
4'b0000:coeff<=9'd1;
4'b0001:coeff<=9'd14;
4'b0010:coeff<=9'd63;
4'b0011:coeff<=9'd146;
4'b0100:coeff<=9'd228;
4'b0101:coeff<=9'd263;
4'b0110:coeff<=9'd228;
4'b0111:coeff<=9'd146;
4'b1000:coeff<=9'd63;
4'b1001:coeff<=9'd14;
4'b1010:coeff<=9'd1;
default coeff<=9'd0;
endcase
end
12'd1024:begin
case(adr)
4'b0000:coeff<=9'd0;
4'b0001:coeff<=9'd11;
4'b0010:coeff<=9'd60;
4'b0011:coeff<=9'd147;
4'b0100:coeff<=9'd235;
4'b0101:coeff<=9'd272;
4'b0110:coeff<=9'd235;
4'b0111:coeff<=9'd147;
4'b1000:coeff<=9'd60;
4'b1001:coeff<=9'd11;
4'b1010:coeff<=9'd0;
default coeff<=9'd0;
endcase
end
12'd2048:begin
case(adr)
4'b0000:coeff<=9'd0;
4'b0001:coeff<=9'd8;
4'b0010:coeff<=9'd56;
4'b0011:coeff<=9'd147;
4'b0100:coeff<=9'd241;
4'b0101:coeff<=9'd281;
4'b0110:coeff<=9'd241;
4'b0111:coeff<=9'd147;
4'b1000:coeff<=9'd56;
4'b1001:coeff<=9'd8;
4'b1010:coeff<=9'd0;
default coeff<=9'd0;
endcase
end
default coeff<=9'd0;
endcase
end
endmodule | module rom (
input [11:0]sel,
input [3:0]adr,
output reg [8:0] coeff
); |
always@(*)begin
case (sel)
12'd1:begin
case(adr)
4'b0000:coeff<=9'd10;
4'b0001:coeff<=9'd26;
4'b0010:coeff<=9'd72;
4'b0011:coeff<=9'd137;
4'b0100:coeff<=9'd193;
4'b0101:coeff<=9'd216;
4'b0110:coeff<=9'd193;
4'b0111:coeff<=9'd137;
4'b1000:coeff<=9'd72;
4'b1001:coeff<=9'd26;
4'b1010:coeff<=9'd10;
default coeff<=9'd0;
endcase
end
12'd2:begin
case(adr)
4'b0000:coeff<=9'd9;
4'b0001:coeff<=9'd26;
4'b0010:coeff<=9'd72;
4'b0011:coeff<=9'd137;
4'b0100:coeff<=9'd195;
4'b0101:coeff<=9'd218;
4'b0110:coeff<=9'd195;
4'b0111:coeff<=9'd137;
4'b1000:coeff<=9'd72;
4'b1001:coeff<=9'd26;
4'b1010:coeff<=9'd9;
default coeff<=9'd0;
endcase
end
12'd4:begin
case(adr)
4'b0000:coeff<=9'd9;
4'b0001:coeff<=9'd25;
4'b0010:coeff<=9'd72;
4'b0011:coeff<=9'd138;
4'b0100:coeff<=9'd198;
4'b0101:coeff<=9'd221;
4'b0110:coeff<=9'd198;
4'b0111:coeff<=9'd138;
4'b1000:coeff<=9'd72;
4'b1001:coeff<=9'd25;
4'b1010:coeff<=9'd9;
default coeff<=9'd0;
endcase
end
12'd8:begin
case(adr)
4'b0000:coeff<=9'd8;
4'b0001:coeff<=9'd24;
4'b0010:coeff<=9'd71;
4'b0011:coeff<=9'd139;
4'b0100:coeff<=9'd200;
4'b0101:coeff<=9'd225;
4'b0110:coeff<=9'd200;
4'b0111:coeff<=9'd139;
4'b1000:coeff<=9'd71;
4'b1001:coeff<=9'd24;
4'b1010:coeff<=9'd8;
default coeff<=9'd0;
endcase
end
12'd16:begin
case(adr)
4'b0000:coeff<=9'd7;
4'b0001:coeff<=9'd23;
4'b0010:coeff<=9'd70;
4'b0011:coeff<=9'd140;
4'b0100:coeff<=9'd204;
4'b0101:coeff<=9'd230;
4'b0110:coeff<=9'd204;
4'b0111:coeff<=9'd140;
4'b1000:coeff<=9'd70;
4'b1001:coeff<=9'd23;
4'b1010:coeff<=9'd7;
default coeff<=9'd0;
endcase
end
12'd32:begin
case(adr)
4'b0000:coeff<=9'd6;
4'b0001:coeff<=9'd22;
4'b0010:coeff<=9'd69;
4'b0011:coeff<=9'd141;
4'b0100:coeff<=9'd207;
4'b0101:coeff<=9'd234;
4'b0110:coeff<=9'd207;
4'b0111:coeff<=9'd141;
4'b1000:coeff<=9'd69;
4'b1001:coeff<=9'd22;
4'b1010:coeff<=9'd6;
default coeff<=9'd0;
endcase
end
12'd64:begin
case(adr)
4'b0000:coeff<=9'd5;
4'b0001:coeff<=9'd20;
4'b0010:coeff<=9'd68;
4'b0011:coeff<=9'd143;
4'b0100:coeff<=9'd212;
4'b0101:coeff<=9'd241;
4'b0110:coeff<=9'd212;
4'b0111:coeff<=9'd143;
4'b1000:coeff<=9'd68;
4'b1001:coeff<=9'd20;
4'b1010:coeff<=9'd5;
default coeff<=9'd0;
endcase
end
12'd128:begin
case(adr)
4'b0000:coeff<=9'd3;
4'b0001:coeff<=9'd18;
4'b0010:coeff<=9'd67;
4'b0011:coeff<=9'd144;
4'b0100:coeff<=9'd218;
4'b0101:coeff<=9'd248;
4'b0110:coeff<=9'd218;
4'b0111:coeff<=9'd144;
4'b1000:coeff<=9'd67;
4'b1001:coeff<=9'd18;
4'b1010:coeff<=9'd3;
default coeff<=9'd0;
endcase
end
12'd256:begin
case(adr)
4'b0000:coeff<=9'd2;
4'b0001:coeff<=9'd16;
4'b0010:coeff<=9'd65;
4'b0011:coeff<=9'd145;
4'b0100:coeff<=9'd223;
4'b0101:coeff<=9'd255;
4'b0110:coeff<=9'd233;
4'b0111:coeff<=9'd145;
4'b1000:coeff<=9'd65;
4'b1001:coeff<=9'd16;
4'b1010:coeff<=9'd2;
default coeff<=9'd0;
endcase
end
12'd512:begin
case(adr)
4'b0000:coeff<=9'd1;
4'b0001:coeff<=9'd14;
4'b0010:coeff<=9'd63;
4'b0011:coeff<=9'd146;
4'b0100:coeff<=9'd228;
4'b0101:coeff<=9'd263;
4'b0110:coeff<=9'd228;
4'b0111:coeff<=9'd146;
4'b1000:coeff<=9'd63;
4'b1001:coeff<=9'd14;
4'b1010:coeff<=9'd1;
default coeff<=9'd0;
endcase
end
12'd1024:begin
case(adr)
4'b0000:coeff<=9'd0;
4'b0001:coeff<=9'd11;
4'b0010:coeff<=9'd60;
4'b0011:coeff<=9'd147;
4'b0100:coeff<=9'd235;
4'b0101:coeff<=9'd272;
4'b0110:coeff<=9'd235;
4'b0111:coeff<=9'd147;
4'b1000:coeff<=9'd60;
4'b1001:coeff<=9'd11;
4'b1010:coeff<=9'd0;
default coeff<=9'd0;
endcase
end
12'd2048:begin
case(adr)
4'b0000:coeff<=9'd0;
4'b0001:coeff<=9'd8;
4'b0010:coeff<=9'd56;
4'b0011:coeff<=9'd147;
4'b0100:coeff<=9'd241;
4'b0101:coeff<=9'd281;
4'b0110:coeff<=9'd241;
4'b0111:coeff<=9'd147;
4'b1000:coeff<=9'd56;
4'b1001:coeff<=9'd8;
4'b1010:coeff<=9'd0;
default coeff<=9'd0;
endcase
end
default coeff<=9'd0;
endcase
end
endmodule | 1 |
139,780 | data/full_repos/permissive/89810125/rtl/wb_sintesis.v | 89,810,125 | wb_sintesis.v | v | 848 | 155 | [] | [] | [] | null | line:342: before: "coeff" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:152: Signal definition not found, creating implicitly: \'led1\'\n assign led1 = | en_osc;\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:153: Signal definition not found, creating implicitly: \'led2\'\n : ... Suggested alternative: \'led1\'\n assign led2 = | teclas;\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:796: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:799: Signal definition not found, creating implicitly: \'sel\'\nassign sel = teclado[12];\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:677: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:679: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:663: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:665: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:650: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:652: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:636: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:638: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:744: Operator LT expects 7 bits on the LHS, but LHS\'s VARREF \'cont\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.pwm0\n if (cont<sint_data)\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:692: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.suma1\n reg [6:0] rp = 6\'b0; \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:709: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:713: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:712: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:306: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 16 bits.\n : ... In instance wb_sintesis.sint0.filtro11\n data_f <= (multi0+multi1+multi2+multi3+multi4+multi5+multi6+multi7+multi8+multi9+multi10)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:231: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:31: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'14\'h3fff\' generates 14 bits.\n : ... In instance wb_sintesis.sint0.deb0\n if (cont== 14\'d16383)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:106: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o0 (en_osc[0],clk_fm, 59, 138, amp0,done_osc[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:107: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o1 (en_osc[1],clk_fm, 55, 148, amp1,done_osc[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:108: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o2 (en_osc[2],clk_fm, 52, 157, amp2,done_osc[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:109: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o3 (en_osc[3],clk_fm, 49, 167, amp3,done_osc[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:110: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o4 (en_osc[4],clk_fm, 46, 178, amp4,done_osc[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:111: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o5 (en_osc[5],clk_fm, 44, 186, amp5,done_osc[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:112: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o6 (en_osc[6],clk_fm, 41, 199, amp6,done_osc[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:113: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o7 (en_osc[7],clk_fm, 39, 210, amp7,done_osc[7]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:114: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o8 (en_osc[8],clk_fm, 37, 221, amp8,done_osc[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:115: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o9 (en_osc[9],clk_fm, 35, 234, amp9,done_osc[9]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:116: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o10 (en_osc[10],clk_fm, 33, 248, amp10,done_osc[10]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:117: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o11 (en_osc[11],clk_fm, 31, 264, amp11,done_osc[11]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:119: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro0 (clk_fm,done_osc[0],teclas,amp0,amp_fir0,done_filtro[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:120: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro1 (clk_fm,done_osc[1],teclas,amp1,amp_fir1,done_filtro[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:121: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro2 (clk_fm,done_osc[2],teclas,amp2,amp_fir2,done_filtro[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:122: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro3 (clk_fm,done_osc[3],teclas,amp3,amp_fir3,done_filtro[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:123: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro4 (clk_fm,done_osc[4],teclas,amp4,amp_fir4,done_filtro[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:124: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro5 (clk_fm,done_osc[5],teclas,amp5,amp_fir5,done_filtro[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:125: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro6 (clk_fm,done_osc[6],teclas,amp6,amp_fir6,done_filtro[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:126: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro7 (clk_fm,done_osc[7],teclas,amp7,amp_fir7,done_filtro[7]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:127: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro8 (clk_fm,done_osc[8],teclas,amp8,amp_fir8,done_filtro[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:128: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro9 (clk_fm,done_osc[9],teclas,amp9,amp_fir9,done_filtro[9]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:129: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro10 (clk_fm,done_osc[10],teclas,amp10,amp_fir10,done_filtro[10]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:130: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro11 (clk_fm,done_osc[11],teclas,amp11,amp_fir11,done_filtro[11]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 69 warning(s)\n' | 307,811 | module | module envolvente(
input [13:0] tiempo,
input clk,
input start,
input reset,
input [6:0] amp,
output done,
output [6:0] amp_res
);
wire en_a, en_d, en_s, en_r;
wire [6:0] amp_a, amp_d, amp_s, amp_r;
control_envolvente control_env0 (tiempo,start,clk,reset,done,en_a,en_d,en_s,en_r);
attack attack0 (tiempo,en_a,amp_a);
decay decay0 (tiempo,en_d,amp_d);
sustain sustain0 (en_s,amp_s);
releasee releasee0 (tiempo,en_r,amp_r);
assign amp_res = ((amp_a + amp_d + amp_s + amp_r)*amp)/64;
endmodule | module envolvente(
input [13:0] tiempo,
input clk,
input start,
input reset,
input [6:0] amp,
output done,
output [6:0] amp_res
); |
wire en_a, en_d, en_s, en_r;
wire [6:0] amp_a, amp_d, amp_s, amp_r;
control_envolvente control_env0 (tiempo,start,clk,reset,done,en_a,en_d,en_s,en_r);
attack attack0 (tiempo,en_a,amp_a);
decay decay0 (tiempo,en_d,amp_d);
sustain sustain0 (en_s,amp_s);
releasee releasee0 (tiempo,en_r,amp_r);
assign amp_res = ((amp_a + amp_d + amp_s + amp_r)*amp)/64;
endmodule | 1 |
139,781 | data/full_repos/permissive/89810125/rtl/wb_sintesis.v | 89,810,125 | wb_sintesis.v | v | 848 | 155 | [] | [] | [] | null | line:342: before: "coeff" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:152: Signal definition not found, creating implicitly: \'led1\'\n assign led1 = | en_osc;\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:153: Signal definition not found, creating implicitly: \'led2\'\n : ... Suggested alternative: \'led1\'\n assign led2 = | teclas;\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:796: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:799: Signal definition not found, creating implicitly: \'sel\'\nassign sel = teclado[12];\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:677: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:679: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:663: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:665: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:650: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:652: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:636: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:638: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:744: Operator LT expects 7 bits on the LHS, but LHS\'s VARREF \'cont\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.pwm0\n if (cont<sint_data)\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:692: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.suma1\n reg [6:0] rp = 6\'b0; \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:709: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:713: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:712: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:306: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 16 bits.\n : ... In instance wb_sintesis.sint0.filtro11\n data_f <= (multi0+multi1+multi2+multi3+multi4+multi5+multi6+multi7+multi8+multi9+multi10)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:231: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:31: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'14\'h3fff\' generates 14 bits.\n : ... In instance wb_sintesis.sint0.deb0\n if (cont== 14\'d16383)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:106: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o0 (en_osc[0],clk_fm, 59, 138, amp0,done_osc[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:107: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o1 (en_osc[1],clk_fm, 55, 148, amp1,done_osc[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:108: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o2 (en_osc[2],clk_fm, 52, 157, amp2,done_osc[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:109: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o3 (en_osc[3],clk_fm, 49, 167, amp3,done_osc[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:110: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o4 (en_osc[4],clk_fm, 46, 178, amp4,done_osc[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:111: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o5 (en_osc[5],clk_fm, 44, 186, amp5,done_osc[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:112: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o6 (en_osc[6],clk_fm, 41, 199, amp6,done_osc[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:113: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o7 (en_osc[7],clk_fm, 39, 210, amp7,done_osc[7]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:114: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o8 (en_osc[8],clk_fm, 37, 221, amp8,done_osc[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:115: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o9 (en_osc[9],clk_fm, 35, 234, amp9,done_osc[9]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:116: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o10 (en_osc[10],clk_fm, 33, 248, amp10,done_osc[10]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:117: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o11 (en_osc[11],clk_fm, 31, 264, amp11,done_osc[11]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:119: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro0 (clk_fm,done_osc[0],teclas,amp0,amp_fir0,done_filtro[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:120: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro1 (clk_fm,done_osc[1],teclas,amp1,amp_fir1,done_filtro[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:121: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro2 (clk_fm,done_osc[2],teclas,amp2,amp_fir2,done_filtro[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:122: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro3 (clk_fm,done_osc[3],teclas,amp3,amp_fir3,done_filtro[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:123: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro4 (clk_fm,done_osc[4],teclas,amp4,amp_fir4,done_filtro[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:124: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro5 (clk_fm,done_osc[5],teclas,amp5,amp_fir5,done_filtro[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:125: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro6 (clk_fm,done_osc[6],teclas,amp6,amp_fir6,done_filtro[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:126: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro7 (clk_fm,done_osc[7],teclas,amp7,amp_fir7,done_filtro[7]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:127: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro8 (clk_fm,done_osc[8],teclas,amp8,amp_fir8,done_filtro[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:128: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro9 (clk_fm,done_osc[9],teclas,amp9,amp_fir9,done_filtro[9]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:129: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro10 (clk_fm,done_osc[10],teclas,amp10,amp_fir10,done_filtro[10]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:130: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro11 (clk_fm,done_osc[11],teclas,amp11,amp_fir11,done_filtro[11]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 69 warning(s)\n' | 307,811 | module | module control_envolvente(
input [13:0] tiempo,
input start,
input clk,
input reset,
output reg done,
output reg en_a,
output reg en_d,
output reg en_s,
output reg en_r
);
parameter S0 = 3'h0;
parameter S1 = 3'h1;
parameter S2 = 3'h2;
parameter S3 = 3'h3;
parameter S4 = 3'h4;
reg [2:0] state = S0;
reg [2:0] nextstate = S0;
always @ (posedge clk) begin
if (reset) state <= S0;
else state <= nextstate;
end
always @ (*) begin
case (state)
S0: if (start) nextstate <= S1;
else nextstate <= S0;
S1: if (tiempo <= 14'd3125) nextstate <= S1;
else nextstate <= S2;
S2: if (tiempo <= 14'd9375) nextstate <= S2;
else nextstate <= S3;
S3: if (tiempo <= 14'd12500) nextstate <= S3;
else nextstate <= S4;
S4: if (tiempo <= 14'd15625) nextstate <= S4;
else nextstate <= S0;
endcase
end
always @ (*) begin
case (state)
S0: begin
en_a <= 1'b0;
en_d <= 1'b0;
en_s <= 1'b0;
en_r <= 1'b0;
done <= 1'b0;
end
S1: begin
en_a <= 1'b1;
en_d <= 1'b0;
en_s <= 1'b0;
en_r <= 1'b0;
done <= 1'b1;
end
S2: begin
en_a <= 1'b0;
en_d <= 1'b1;
en_s <= 1'b0;
en_r <= 1'b0;
done <= 1'b1;
end
S3: begin
en_a <= 1'b0;
en_d <= 1'b0;
en_s <= 1'b1;
en_r <= 1'b0;
done <= 1'b1;
end
S4: begin
en_a <= 1'b0;
en_d <= 1'b0;
en_s <= 1'b0;
en_r <= 1'b1;
done <= 1'b1;
end
endcase
end
endmodule | module control_envolvente(
input [13:0] tiempo,
input start,
input clk,
input reset,
output reg done,
output reg en_a,
output reg en_d,
output reg en_s,
output reg en_r
); |
parameter S0 = 3'h0;
parameter S1 = 3'h1;
parameter S2 = 3'h2;
parameter S3 = 3'h3;
parameter S4 = 3'h4;
reg [2:0] state = S0;
reg [2:0] nextstate = S0;
always @ (posedge clk) begin
if (reset) state <= S0;
else state <= nextstate;
end
always @ (*) begin
case (state)
S0: if (start) nextstate <= S1;
else nextstate <= S0;
S1: if (tiempo <= 14'd3125) nextstate <= S1;
else nextstate <= S2;
S2: if (tiempo <= 14'd9375) nextstate <= S2;
else nextstate <= S3;
S3: if (tiempo <= 14'd12500) nextstate <= S3;
else nextstate <= S4;
S4: if (tiempo <= 14'd15625) nextstate <= S4;
else nextstate <= S0;
endcase
end
always @ (*) begin
case (state)
S0: begin
en_a <= 1'b0;
en_d <= 1'b0;
en_s <= 1'b0;
en_r <= 1'b0;
done <= 1'b0;
end
S1: begin
en_a <= 1'b1;
en_d <= 1'b0;
en_s <= 1'b0;
en_r <= 1'b0;
done <= 1'b1;
end
S2: begin
en_a <= 1'b0;
en_d <= 1'b1;
en_s <= 1'b0;
en_r <= 1'b0;
done <= 1'b1;
end
S3: begin
en_a <= 1'b0;
en_d <= 1'b0;
en_s <= 1'b1;
en_r <= 1'b0;
done <= 1'b1;
end
S4: begin
en_a <= 1'b0;
en_d <= 1'b0;
en_s <= 1'b0;
en_r <= 1'b1;
done <= 1'b1;
end
endcase
end
endmodule | 1 |
139,782 | data/full_repos/permissive/89810125/rtl/wb_sintesis.v | 89,810,125 | wb_sintesis.v | v | 848 | 155 | [] | [] | [] | null | line:342: before: "coeff" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:152: Signal definition not found, creating implicitly: \'led1\'\n assign led1 = | en_osc;\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:153: Signal definition not found, creating implicitly: \'led2\'\n : ... Suggested alternative: \'led1\'\n assign led2 = | teclas;\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:796: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:799: Signal definition not found, creating implicitly: \'sel\'\nassign sel = teclado[12];\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:677: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:679: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:663: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:665: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:650: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:652: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:636: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:638: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:744: Operator LT expects 7 bits on the LHS, but LHS\'s VARREF \'cont\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.pwm0\n if (cont<sint_data)\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:692: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.suma1\n reg [6:0] rp = 6\'b0; \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:709: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:713: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:712: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:306: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 16 bits.\n : ... In instance wb_sintesis.sint0.filtro11\n data_f <= (multi0+multi1+multi2+multi3+multi4+multi5+multi6+multi7+multi8+multi9+multi10)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:231: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:31: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'14\'h3fff\' generates 14 bits.\n : ... In instance wb_sintesis.sint0.deb0\n if (cont== 14\'d16383)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:106: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o0 (en_osc[0],clk_fm, 59, 138, amp0,done_osc[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:107: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o1 (en_osc[1],clk_fm, 55, 148, amp1,done_osc[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:108: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o2 (en_osc[2],clk_fm, 52, 157, amp2,done_osc[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:109: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o3 (en_osc[3],clk_fm, 49, 167, amp3,done_osc[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:110: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o4 (en_osc[4],clk_fm, 46, 178, amp4,done_osc[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:111: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o5 (en_osc[5],clk_fm, 44, 186, amp5,done_osc[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:112: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o6 (en_osc[6],clk_fm, 41, 199, amp6,done_osc[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:113: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o7 (en_osc[7],clk_fm, 39, 210, amp7,done_osc[7]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:114: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o8 (en_osc[8],clk_fm, 37, 221, amp8,done_osc[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:115: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o9 (en_osc[9],clk_fm, 35, 234, amp9,done_osc[9]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:116: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o10 (en_osc[10],clk_fm, 33, 248, amp10,done_osc[10]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:117: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o11 (en_osc[11],clk_fm, 31, 264, amp11,done_osc[11]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:119: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro0 (clk_fm,done_osc[0],teclas,amp0,amp_fir0,done_filtro[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:120: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro1 (clk_fm,done_osc[1],teclas,amp1,amp_fir1,done_filtro[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:121: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro2 (clk_fm,done_osc[2],teclas,amp2,amp_fir2,done_filtro[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:122: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro3 (clk_fm,done_osc[3],teclas,amp3,amp_fir3,done_filtro[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:123: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro4 (clk_fm,done_osc[4],teclas,amp4,amp_fir4,done_filtro[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:124: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro5 (clk_fm,done_osc[5],teclas,amp5,amp_fir5,done_filtro[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:125: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro6 (clk_fm,done_osc[6],teclas,amp6,amp_fir6,done_filtro[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:126: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro7 (clk_fm,done_osc[7],teclas,amp7,amp_fir7,done_filtro[7]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:127: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro8 (clk_fm,done_osc[8],teclas,amp8,amp_fir8,done_filtro[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:128: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro9 (clk_fm,done_osc[9],teclas,amp9,amp_fir9,done_filtro[9]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:129: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro10 (clk_fm,done_osc[10],teclas,amp10,amp_fir10,done_filtro[10]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:130: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro11 (clk_fm,done_osc[11],teclas,amp11,amp_fir11,done_filtro[11]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 69 warning(s)\n' | 307,811 | module | module attack (
input [13:0] tiempo,
input en,
output reg [6:0] amp_env
);
always @ (tiempo,en) begin
if (en)
amp_env <= 6'd32;
else
amp_env <= 6'b0;
end
endmodule | module attack (
input [13:0] tiempo,
input en,
output reg [6:0] amp_env
); |
always @ (tiempo,en) begin
if (en)
amp_env <= 6'd32;
else
amp_env <= 6'b0;
end
endmodule | 1 |
139,783 | data/full_repos/permissive/89810125/rtl/wb_sintesis.v | 89,810,125 | wb_sintesis.v | v | 848 | 155 | [] | [] | [] | null | line:342: before: "coeff" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:152: Signal definition not found, creating implicitly: \'led1\'\n assign led1 = | en_osc;\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:153: Signal definition not found, creating implicitly: \'led2\'\n : ... Suggested alternative: \'led1\'\n assign led2 = | teclas;\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:796: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:799: Signal definition not found, creating implicitly: \'sel\'\nassign sel = teclado[12];\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:677: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:679: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:663: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:665: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:650: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:652: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:636: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:638: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:744: Operator LT expects 7 bits on the LHS, but LHS\'s VARREF \'cont\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.pwm0\n if (cont<sint_data)\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:692: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.suma1\n reg [6:0] rp = 6\'b0; \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:709: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:713: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:712: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:306: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 16 bits.\n : ... In instance wb_sintesis.sint0.filtro11\n data_f <= (multi0+multi1+multi2+multi3+multi4+multi5+multi6+multi7+multi8+multi9+multi10)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:231: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:31: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'14\'h3fff\' generates 14 bits.\n : ... In instance wb_sintesis.sint0.deb0\n if (cont== 14\'d16383)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:106: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o0 (en_osc[0],clk_fm, 59, 138, amp0,done_osc[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:107: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o1 (en_osc[1],clk_fm, 55, 148, amp1,done_osc[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:108: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o2 (en_osc[2],clk_fm, 52, 157, amp2,done_osc[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:109: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o3 (en_osc[3],clk_fm, 49, 167, amp3,done_osc[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:110: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o4 (en_osc[4],clk_fm, 46, 178, amp4,done_osc[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:111: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o5 (en_osc[5],clk_fm, 44, 186, amp5,done_osc[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:112: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o6 (en_osc[6],clk_fm, 41, 199, amp6,done_osc[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:113: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o7 (en_osc[7],clk_fm, 39, 210, amp7,done_osc[7]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:114: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o8 (en_osc[8],clk_fm, 37, 221, amp8,done_osc[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:115: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o9 (en_osc[9],clk_fm, 35, 234, amp9,done_osc[9]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:116: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o10 (en_osc[10],clk_fm, 33, 248, amp10,done_osc[10]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:117: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o11 (en_osc[11],clk_fm, 31, 264, amp11,done_osc[11]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:119: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro0 (clk_fm,done_osc[0],teclas,amp0,amp_fir0,done_filtro[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:120: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro1 (clk_fm,done_osc[1],teclas,amp1,amp_fir1,done_filtro[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:121: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro2 (clk_fm,done_osc[2],teclas,amp2,amp_fir2,done_filtro[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:122: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro3 (clk_fm,done_osc[3],teclas,amp3,amp_fir3,done_filtro[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:123: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro4 (clk_fm,done_osc[4],teclas,amp4,amp_fir4,done_filtro[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:124: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro5 (clk_fm,done_osc[5],teclas,amp5,amp_fir5,done_filtro[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:125: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro6 (clk_fm,done_osc[6],teclas,amp6,amp_fir6,done_filtro[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:126: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro7 (clk_fm,done_osc[7],teclas,amp7,amp_fir7,done_filtro[7]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:127: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro8 (clk_fm,done_osc[8],teclas,amp8,amp_fir8,done_filtro[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:128: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro9 (clk_fm,done_osc[9],teclas,amp9,amp_fir9,done_filtro[9]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:129: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro10 (clk_fm,done_osc[10],teclas,amp10,amp_fir10,done_filtro[10]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:130: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro11 (clk_fm,done_osc[11],teclas,amp11,amp_fir11,done_filtro[11]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 69 warning(s)\n' | 307,811 | module | module releasee(
input [13:0] tiempo,
input en,
output reg [6:0] amp_env
);
always @ (tiempo,en) begin
if (en)
amp_env <= 153 - (10*tiempo)/1024;
else
amp_env <= 6'b0;
end
endmodule | module releasee(
input [13:0] tiempo,
input en,
output reg [6:0] amp_env
); |
always @ (tiempo,en) begin
if (en)
amp_env <= 153 - (10*tiempo)/1024;
else
amp_env <= 6'b0;
end
endmodule | 1 |
139,784 | data/full_repos/permissive/89810125/rtl/wb_sintesis.v | 89,810,125 | wb_sintesis.v | v | 848 | 155 | [] | [] | [] | null | line:342: before: "coeff" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:152: Signal definition not found, creating implicitly: \'led1\'\n assign led1 = | en_osc;\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:153: Signal definition not found, creating implicitly: \'led2\'\n : ... Suggested alternative: \'led1\'\n assign led2 = | teclas;\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:796: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:799: Signal definition not found, creating implicitly: \'sel\'\nassign sel = teclado[12];\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:677: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:679: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:663: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:665: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:650: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:652: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:636: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:638: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:744: Operator LT expects 7 bits on the LHS, but LHS\'s VARREF \'cont\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.pwm0\n if (cont<sint_data)\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:692: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.suma1\n reg [6:0] rp = 6\'b0; \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:709: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:713: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:712: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:306: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 16 bits.\n : ... In instance wb_sintesis.sint0.filtro11\n data_f <= (multi0+multi1+multi2+multi3+multi4+multi5+multi6+multi7+multi8+multi9+multi10)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:231: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:31: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'14\'h3fff\' generates 14 bits.\n : ... In instance wb_sintesis.sint0.deb0\n if (cont== 14\'d16383)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:106: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o0 (en_osc[0],clk_fm, 59, 138, amp0,done_osc[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:107: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o1 (en_osc[1],clk_fm, 55, 148, amp1,done_osc[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:108: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o2 (en_osc[2],clk_fm, 52, 157, amp2,done_osc[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:109: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o3 (en_osc[3],clk_fm, 49, 167, amp3,done_osc[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:110: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o4 (en_osc[4],clk_fm, 46, 178, amp4,done_osc[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:111: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o5 (en_osc[5],clk_fm, 44, 186, amp5,done_osc[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:112: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o6 (en_osc[6],clk_fm, 41, 199, amp6,done_osc[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:113: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o7 (en_osc[7],clk_fm, 39, 210, amp7,done_osc[7]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:114: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o8 (en_osc[8],clk_fm, 37, 221, amp8,done_osc[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:115: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o9 (en_osc[9],clk_fm, 35, 234, amp9,done_osc[9]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:116: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o10 (en_osc[10],clk_fm, 33, 248, amp10,done_osc[10]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:117: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o11 (en_osc[11],clk_fm, 31, 264, amp11,done_osc[11]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:119: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro0 (clk_fm,done_osc[0],teclas,amp0,amp_fir0,done_filtro[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:120: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro1 (clk_fm,done_osc[1],teclas,amp1,amp_fir1,done_filtro[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:121: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro2 (clk_fm,done_osc[2],teclas,amp2,amp_fir2,done_filtro[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:122: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro3 (clk_fm,done_osc[3],teclas,amp3,amp_fir3,done_filtro[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:123: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro4 (clk_fm,done_osc[4],teclas,amp4,amp_fir4,done_filtro[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:124: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro5 (clk_fm,done_osc[5],teclas,amp5,amp_fir5,done_filtro[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:125: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro6 (clk_fm,done_osc[6],teclas,amp6,amp_fir6,done_filtro[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:126: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro7 (clk_fm,done_osc[7],teclas,amp7,amp_fir7,done_filtro[7]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:127: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro8 (clk_fm,done_osc[8],teclas,amp8,amp_fir8,done_filtro[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:128: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro9 (clk_fm,done_osc[9],teclas,amp9,amp_fir9,done_filtro[9]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:129: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro10 (clk_fm,done_osc[10],teclas,amp10,amp_fir10,done_filtro[10]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:130: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro11 (clk_fm,done_osc[11],teclas,amp11,amp_fir11,done_filtro[11]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 69 warning(s)\n' | 307,811 | module | module sustain(
input en,
output reg [6:0] amp_env
);
always @ (en) begin
if (en)
amp_env <= 6'd32;
else
amp_env <= 6'b0;
end
endmodule | module sustain(
input en,
output reg [6:0] amp_env
); |
always @ (en) begin
if (en)
amp_env <= 6'd32;
else
amp_env <= 6'b0;
end
endmodule | 1 |
139,785 | data/full_repos/permissive/89810125/rtl/wb_sintesis.v | 89,810,125 | wb_sintesis.v | v | 848 | 155 | [] | [] | [] | null | line:342: before: "coeff" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:152: Signal definition not found, creating implicitly: \'led1\'\n assign led1 = | en_osc;\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:153: Signal definition not found, creating implicitly: \'led2\'\n : ... Suggested alternative: \'led1\'\n assign led2 = | teclas;\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:796: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:799: Signal definition not found, creating implicitly: \'sel\'\nassign sel = teclado[12];\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:677: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:679: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:663: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:665: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:650: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:652: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:636: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:638: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:744: Operator LT expects 7 bits on the LHS, but LHS\'s VARREF \'cont\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.pwm0\n if (cont<sint_data)\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:692: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.suma1\n reg [6:0] rp = 6\'b0; \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:709: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:713: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:712: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:306: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 16 bits.\n : ... In instance wb_sintesis.sint0.filtro11\n data_f <= (multi0+multi1+multi2+multi3+multi4+multi5+multi6+multi7+multi8+multi9+multi10)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:231: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:31: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'14\'h3fff\' generates 14 bits.\n : ... In instance wb_sintesis.sint0.deb0\n if (cont== 14\'d16383)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:106: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o0 (en_osc[0],clk_fm, 59, 138, amp0,done_osc[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:107: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o1 (en_osc[1],clk_fm, 55, 148, amp1,done_osc[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:108: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o2 (en_osc[2],clk_fm, 52, 157, amp2,done_osc[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:109: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o3 (en_osc[3],clk_fm, 49, 167, amp3,done_osc[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:110: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o4 (en_osc[4],clk_fm, 46, 178, amp4,done_osc[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:111: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o5 (en_osc[5],clk_fm, 44, 186, amp5,done_osc[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:112: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o6 (en_osc[6],clk_fm, 41, 199, amp6,done_osc[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:113: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o7 (en_osc[7],clk_fm, 39, 210, amp7,done_osc[7]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:114: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o8 (en_osc[8],clk_fm, 37, 221, amp8,done_osc[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:115: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o9 (en_osc[9],clk_fm, 35, 234, amp9,done_osc[9]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:116: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o10 (en_osc[10],clk_fm, 33, 248, amp10,done_osc[10]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:117: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o11 (en_osc[11],clk_fm, 31, 264, amp11,done_osc[11]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:119: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro0 (clk_fm,done_osc[0],teclas,amp0,amp_fir0,done_filtro[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:120: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro1 (clk_fm,done_osc[1],teclas,amp1,amp_fir1,done_filtro[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:121: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro2 (clk_fm,done_osc[2],teclas,amp2,amp_fir2,done_filtro[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:122: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro3 (clk_fm,done_osc[3],teclas,amp3,amp_fir3,done_filtro[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:123: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro4 (clk_fm,done_osc[4],teclas,amp4,amp_fir4,done_filtro[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:124: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro5 (clk_fm,done_osc[5],teclas,amp5,amp_fir5,done_filtro[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:125: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro6 (clk_fm,done_osc[6],teclas,amp6,amp_fir6,done_filtro[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:126: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro7 (clk_fm,done_osc[7],teclas,amp7,amp_fir7,done_filtro[7]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:127: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro8 (clk_fm,done_osc[8],teclas,amp8,amp_fir8,done_filtro[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:128: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro9 (clk_fm,done_osc[9],teclas,amp9,amp_fir9,done_filtro[9]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:129: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro10 (clk_fm,done_osc[10],teclas,amp10,amp_fir10,done_filtro[10]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:130: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro11 (clk_fm,done_osc[11],teclas,amp11,amp_fir11,done_filtro[11]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 69 warning(s)\n' | 307,811 | module | module decay(
input [13:0] tiempo,
input en,
output reg [6:0] amp_env
);
always @ (tiempo,en) begin
if (en)
amp_env <= 78 - (5*tiempo)/1024;
else
amp_env <= 6'b0;
end
endmodule | module decay(
input [13:0] tiempo,
input en,
output reg [6:0] amp_env
); |
always @ (tiempo,en) begin
if (en)
amp_env <= 78 - (5*tiempo)/1024;
else
amp_env <= 6'b0;
end
endmodule | 1 |
139,786 | data/full_repos/permissive/89810125/rtl/wb_sintesis.v | 89,810,125 | wb_sintesis.v | v | 848 | 155 | [] | [] | [] | null | line:342: before: "coeff" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:152: Signal definition not found, creating implicitly: \'led1\'\n assign led1 = | en_osc;\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:153: Signal definition not found, creating implicitly: \'led2\'\n : ... Suggested alternative: \'led1\'\n assign led2 = | teclas;\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:796: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:799: Signal definition not found, creating implicitly: \'sel\'\nassign sel = teclado[12];\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:677: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:679: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:663: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:665: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:650: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:652: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:636: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:638: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:744: Operator LT expects 7 bits on the LHS, but LHS\'s VARREF \'cont\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.pwm0\n if (cont<sint_data)\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:692: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.suma1\n reg [6:0] rp = 6\'b0; \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:709: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:713: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:712: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:306: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 16 bits.\n : ... In instance wb_sintesis.sint0.filtro11\n data_f <= (multi0+multi1+multi2+multi3+multi4+multi5+multi6+multi7+multi8+multi9+multi10)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:231: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:31: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'14\'h3fff\' generates 14 bits.\n : ... In instance wb_sintesis.sint0.deb0\n if (cont== 14\'d16383)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:106: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o0 (en_osc[0],clk_fm, 59, 138, amp0,done_osc[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:107: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o1 (en_osc[1],clk_fm, 55, 148, amp1,done_osc[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:108: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o2 (en_osc[2],clk_fm, 52, 157, amp2,done_osc[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:109: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o3 (en_osc[3],clk_fm, 49, 167, amp3,done_osc[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:110: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o4 (en_osc[4],clk_fm, 46, 178, amp4,done_osc[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:111: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o5 (en_osc[5],clk_fm, 44, 186, amp5,done_osc[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:112: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o6 (en_osc[6],clk_fm, 41, 199, amp6,done_osc[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:113: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o7 (en_osc[7],clk_fm, 39, 210, amp7,done_osc[7]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:114: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o8 (en_osc[8],clk_fm, 37, 221, amp8,done_osc[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:115: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o9 (en_osc[9],clk_fm, 35, 234, amp9,done_osc[9]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:116: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o10 (en_osc[10],clk_fm, 33, 248, amp10,done_osc[10]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:117: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o11 (en_osc[11],clk_fm, 31, 264, amp11,done_osc[11]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:119: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro0 (clk_fm,done_osc[0],teclas,amp0,amp_fir0,done_filtro[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:120: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro1 (clk_fm,done_osc[1],teclas,amp1,amp_fir1,done_filtro[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:121: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro2 (clk_fm,done_osc[2],teclas,amp2,amp_fir2,done_filtro[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:122: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro3 (clk_fm,done_osc[3],teclas,amp3,amp_fir3,done_filtro[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:123: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro4 (clk_fm,done_osc[4],teclas,amp4,amp_fir4,done_filtro[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:124: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro5 (clk_fm,done_osc[5],teclas,amp5,amp_fir5,done_filtro[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:125: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro6 (clk_fm,done_osc[6],teclas,amp6,amp_fir6,done_filtro[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:126: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro7 (clk_fm,done_osc[7],teclas,amp7,amp_fir7,done_filtro[7]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:127: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro8 (clk_fm,done_osc[8],teclas,amp8,amp_fir8,done_filtro[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:128: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro9 (clk_fm,done_osc[9],teclas,amp9,amp_fir9,done_filtro[9]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:129: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro10 (clk_fm,done_osc[10],teclas,amp10,amp_fir10,done_filtro[10]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:130: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro11 (clk_fm,done_osc[11],teclas,amp11,amp_fir11,done_filtro[11]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 69 warning(s)\n' | 307,811 | module | module suma_amp(
input clk,
input start,
input [9:0] a,
input [11:0] en,
output done,
output reg [6:0] result
);
reg [6:0] rp = 6'b0;
reg [9:0] c,d;
reg load = 1'b1;
reg done1 = 1'b1;
reg loaden;
wire [3:0] b,num_teclas;
assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];
assign b = num_teclas;
always @ (posedge clk) begin
loaden <= load & start;
if(loaden) begin
c<=a;
d<=a;
load<=1'b0;
rp<=1'b0;
end
else if (c>=b) begin
c<=c-b;
rp<=rp+1;
done1<=0;
end
else begin
done1<=1;
result<=rp;
if (a!=d)
load<=1;
end
end
assign done = done1;
endmodule | module suma_amp(
input clk,
input start,
input [9:0] a,
input [11:0] en,
output done,
output reg [6:0] result
); |
reg [6:0] rp = 6'b0;
reg [9:0] c,d;
reg load = 1'b1;
reg done1 = 1'b1;
reg loaden;
wire [3:0] b,num_teclas;
assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];
assign b = num_teclas;
always @ (posedge clk) begin
loaden <= load & start;
if(loaden) begin
c<=a;
d<=a;
load<=1'b0;
rp<=1'b0;
end
else if (c>=b) begin
c<=c-b;
rp<=rp+1;
done1<=0;
end
else begin
done1<=1;
result<=rp;
if (a!=d)
load<=1;
end
end
assign done = done1;
endmodule | 1 |
139,787 | data/full_repos/permissive/89810125/rtl/wb_sintesis.v | 89,810,125 | wb_sintesis.v | v | 848 | 155 | [] | [] | [] | null | line:342: before: "coeff" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:152: Signal definition not found, creating implicitly: \'led1\'\n assign led1 = | en_osc;\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:153: Signal definition not found, creating implicitly: \'led2\'\n : ... Suggested alternative: \'led1\'\n assign led2 = | teclas;\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:796: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:799: Signal definition not found, creating implicitly: \'sel\'\nassign sel = teclado[12];\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:677: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:679: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:663: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:665: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:650: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:652: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:636: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:638: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:744: Operator LT expects 7 bits on the LHS, but LHS\'s VARREF \'cont\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.pwm0\n if (cont<sint_data)\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:692: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.suma1\n reg [6:0] rp = 6\'b0; \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:709: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:713: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:712: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:306: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 16 bits.\n : ... In instance wb_sintesis.sint0.filtro11\n data_f <= (multi0+multi1+multi2+multi3+multi4+multi5+multi6+multi7+multi8+multi9+multi10)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:231: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:31: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'14\'h3fff\' generates 14 bits.\n : ... In instance wb_sintesis.sint0.deb0\n if (cont== 14\'d16383)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:106: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o0 (en_osc[0],clk_fm, 59, 138, amp0,done_osc[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:107: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o1 (en_osc[1],clk_fm, 55, 148, amp1,done_osc[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:108: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o2 (en_osc[2],clk_fm, 52, 157, amp2,done_osc[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:109: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o3 (en_osc[3],clk_fm, 49, 167, amp3,done_osc[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:110: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o4 (en_osc[4],clk_fm, 46, 178, amp4,done_osc[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:111: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o5 (en_osc[5],clk_fm, 44, 186, amp5,done_osc[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:112: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o6 (en_osc[6],clk_fm, 41, 199, amp6,done_osc[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:113: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o7 (en_osc[7],clk_fm, 39, 210, amp7,done_osc[7]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:114: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o8 (en_osc[8],clk_fm, 37, 221, amp8,done_osc[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:115: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o9 (en_osc[9],clk_fm, 35, 234, amp9,done_osc[9]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:116: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o10 (en_osc[10],clk_fm, 33, 248, amp10,done_osc[10]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:117: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o11 (en_osc[11],clk_fm, 31, 264, amp11,done_osc[11]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:119: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro0 (clk_fm,done_osc[0],teclas,amp0,amp_fir0,done_filtro[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:120: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro1 (clk_fm,done_osc[1],teclas,amp1,amp_fir1,done_filtro[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:121: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro2 (clk_fm,done_osc[2],teclas,amp2,amp_fir2,done_filtro[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:122: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro3 (clk_fm,done_osc[3],teclas,amp3,amp_fir3,done_filtro[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:123: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro4 (clk_fm,done_osc[4],teclas,amp4,amp_fir4,done_filtro[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:124: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro5 (clk_fm,done_osc[5],teclas,amp5,amp_fir5,done_filtro[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:125: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro6 (clk_fm,done_osc[6],teclas,amp6,amp_fir6,done_filtro[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:126: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro7 (clk_fm,done_osc[7],teclas,amp7,amp_fir7,done_filtro[7]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:127: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro8 (clk_fm,done_osc[8],teclas,amp8,amp_fir8,done_filtro[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:128: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro9 (clk_fm,done_osc[9],teclas,amp9,amp_fir9,done_filtro[9]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:129: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro10 (clk_fm,done_osc[10],teclas,amp10,amp_fir10,done_filtro[10]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:130: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro11 (clk_fm,done_osc[11],teclas,amp11,amp_fir11,done_filtro[11]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 69 warning(s)\n' | 307,811 | module | module pwm(
input [6:0] sint_data,
input en,
input clk,
output pulse_data,
output busy_pwm
);
reg pulse_reg;
reg [5:0] cont=6'd63;
reg [6:0] pwm_in=0;
always @ (posedge clk) begin
if (cont==6'd63) begin
pwm_in<=sint_data;
cont=0;
end
else cont=cont+1;
if (cont<sint_data)
pulse_reg=1;
else pulse_reg=0;
end
assign pulse_data=pulse_reg;
assign busy_pwm = en;
endmodule | module pwm(
input [6:0] sint_data,
input en,
input clk,
output pulse_data,
output busy_pwm
); |
reg pulse_reg;
reg [5:0] cont=6'd63;
reg [6:0] pwm_in=0;
always @ (posedge clk) begin
if (cont==6'd63) begin
pwm_in<=sint_data;
cont=0;
end
else cont=cont+1;
if (cont<sint_data)
pulse_reg=1;
else pulse_reg=0;
end
assign pulse_data=pulse_reg;
assign busy_pwm = en;
endmodule | 1 |
139,788 | data/full_repos/permissive/89810125/rtl/wb_sintesis.v | 89,810,125 | wb_sintesis.v | v | 848 | 155 | [] | [] | [] | null | line:342: before: "coeff" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:152: Signal definition not found, creating implicitly: \'led1\'\n assign led1 = | en_osc;\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:153: Signal definition not found, creating implicitly: \'led2\'\n : ... Suggested alternative: \'led1\'\n assign led2 = | teclas;\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:796: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:799: Signal definition not found, creating implicitly: \'sel\'\nassign sel = teclado[12];\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:677: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:679: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:663: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:665: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.sustain0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:650: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:652: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:636: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h20\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'d32;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:638: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= 6\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:744: Operator LT expects 7 bits on the LHS, but LHS\'s VARREF \'cont\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.pwm0\n if (cont<sint_data)\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:692: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0.suma1\n reg [6:0] rp = 6\'b0; \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:699: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:709: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:713: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:712: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:306: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 16 bits.\n : ... In instance wb_sintesis.sint0.filtro11\n data_f <= (multi0+multi1+multi2+multi3+multi4+multi5+multi6+multi7+multi8+multi9+multi10)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:231: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:31: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'14\'h3fff\' generates 14 bits.\n : ... In instance wb_sintesis.sint0.deb0\n if (cont== 14\'d16383)\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:106: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o0 (en_osc[0],clk_fm, 59, 138, amp0,done_osc[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:107: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o1 (en_osc[1],clk_fm, 55, 148, amp1,done_osc[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:108: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o2 (en_osc[2],clk_fm, 52, 157, amp2,done_osc[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:109: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o3 (en_osc[3],clk_fm, 49, 167, amp3,done_osc[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:110: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o4 (en_osc[4],clk_fm, 46, 178, amp4,done_osc[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:111: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o5 (en_osc[5],clk_fm, 44, 186, amp5,done_osc[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:112: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o6 (en_osc[6],clk_fm, 41, 199, amp6,done_osc[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:113: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o7 (en_osc[7],clk_fm, 39, 210, amp7,done_osc[7]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:114: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o8 (en_osc[8],clk_fm, 37, 221, amp8,done_osc[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:115: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o9 (en_osc[9],clk_fm, 35, 234, amp9,done_osc[9]); \n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:116: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o10 (en_osc[10],clk_fm, 33, 248, amp10,done_osc[10]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:117: Output port connection \'amp1\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n oscilador o11 (en_osc[11],clk_fm, 31, 264, amp11,done_osc[11]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:119: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro0 (clk_fm,done_osc[0],teclas,amp0,amp_fir0,done_filtro[0]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:120: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro1 (clk_fm,done_osc[1],teclas,amp1,amp_fir1,done_filtro[1]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:121: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro2 (clk_fm,done_osc[2],teclas,amp2,amp_fir2,done_filtro[2]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:122: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro3 (clk_fm,done_osc[3],teclas,amp3,amp_fir3,done_filtro[3]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:123: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro4 (clk_fm,done_osc[4],teclas,amp4,amp_fir4,done_filtro[4]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:124: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro5 (clk_fm,done_osc[5],teclas,amp5,amp_fir5,done_filtro[5]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:125: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro6 (clk_fm,done_osc[6],teclas,amp6,amp_fir6,done_filtro[6]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:126: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro7 (clk_fm,done_osc[7],teclas,amp7,amp_fir7,done_filtro[7]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:127: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro8 (clk_fm,done_osc[8],teclas,amp8,amp_fir8,done_filtro[8]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:128: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro9 (clk_fm,done_osc[9],teclas,amp9,amp_fir9,done_filtro[9]);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:129: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro10 (clk_fm,done_osc[10],teclas,amp10,amp_fir10,done_filtro[10]);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:130: Input port connection \'amp_o\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'amp11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n FIR filtro11 (clk_fm,done_osc[11],teclas,amp11,amp_fir11,done_filtro[11]); \n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis.v:144: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 7 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 69 warning(s)\n' | 307,811 | module | module wb_sintesis (
input clk,
input reset,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
input wb_we_i,
input [31:0] wb_adr_i,
input [3:0] wb_sel_i,
input [31:0] wb_dat_i,
output reg [31:0] wb_dat_o,
input [12:0] teclado,
output pulse_data
);
wire [11:0] teclas;
wire busy_pwm;
sintesis sint0 (
.teclado(teclado),
.clk(clk),
.pulse_data(pulse_data),
.busy_pwm(busy_busy)
);
assign teclas = teclado[11:0];
assign sel = teclado[12];
wire [31:0] teclasw = {20'b0, teclas};
wire [31:0] data = { 30'b0, pulse_data, sel};
wire [31:0] cs = { 30'b0, busy_pwm, 1'b1};
wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i;
wire wb_wr = wb_stb_i & wb_cyc_i & wb_we_i;
reg ack;
assign wb_ack_o = wb_stb_i & wb_cyc_i & ack;
always @(posedge clk)
begin
if (~reset) begin
wb_dat_o[31:0] <= 32'b0;
ack <= 0;
end else begin
wb_dat_o[31:0] <= 32'b0;
ack <= 0;
if (wb_rd & ~ack) begin
ack <= 1;
case (wb_adr_i[3:0])
'h00: wb_dat_o <= 32'b0;
'h04: wb_dat_o[0] <= data[1];
'h08: wb_dat_o[0] <= cs[1];
default: wb_dat_o <= 32'b0;
endcase
end else if (wb_wr & ~ack ) begin
ack <= 1;
end
end
end
endmodule | module wb_sintesis (
input clk,
input reset,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
input wb_we_i,
input [31:0] wb_adr_i,
input [3:0] wb_sel_i,
input [31:0] wb_dat_i,
output reg [31:0] wb_dat_o,
input [12:0] teclado,
output pulse_data
); |
wire [11:0] teclas;
wire busy_pwm;
sintesis sint0 (
.teclado(teclado),
.clk(clk),
.pulse_data(pulse_data),
.busy_pwm(busy_busy)
);
assign teclas = teclado[11:0];
assign sel = teclado[12];
wire [31:0] teclasw = {20'b0, teclas};
wire [31:0] data = { 30'b0, pulse_data, sel};
wire [31:0] cs = { 30'b0, busy_pwm, 1'b1};
wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i;
wire wb_wr = wb_stb_i & wb_cyc_i & wb_we_i;
reg ack;
assign wb_ack_o = wb_stb_i & wb_cyc_i & ack;
always @(posedge clk)
begin
if (~reset) begin
wb_dat_o[31:0] <= 32'b0;
ack <= 0;
end else begin
wb_dat_o[31:0] <= 32'b0;
ack <= 0;
if (wb_rd & ~ack) begin
ack <= 1;
case (wb_adr_i[3:0])
'h00: wb_dat_o <= 32'b0;
'h04: wb_dat_o[0] <= data[1];
'h08: wb_dat_o[0] <= cs[1];
default: wb_dat_o <= 32'b0;
endcase
end else if (wb_wr & ~ack ) begin
ack <= 1;
end
end
end
endmodule | 1 |
139,789 | data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v | 89,810,125 | wb_sintesis_sinFIR.v | v | 471 | 155 | [] | [] | [] | [(1, 16), (18, 49), (51, 78), (80, 92), (94, 106), (108, 119), (121, 133), (135, 211), (213, 230), (232, 273), (276, 298), (300, 374), (388, 467)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:419: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:129: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:102: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:88: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= (tiempo*5)/256;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:257: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:261: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:260: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:229: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 7 bits.\n : ... In instance wb_sintesis.sint0.env11\n assign amp_res = ((amp_a + amp_d + amp_s + amp_r)*amp)/64;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:66: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 34 warning(s)\n' | 307,812 | module | module clkg(
input clk,
input [14:0] factor,
output clkp
);
reg clkpr=1'b0;
reg [14:0] cont=15'b0;
always @ (posedge clk) begin
if(cont==factor) begin
cont<=1;
clkpr=~clkpr;
end
else cont<=cont+1;
end
assign clkp=clkpr;
endmodule | module clkg(
input clk,
input [14:0] factor,
output clkp
); |
reg clkpr=1'b0;
reg [14:0] cont=15'b0;
always @ (posedge clk) begin
if(cont==factor) begin
cont<=1;
clkpr=~clkpr;
end
else cont<=cont+1;
end
assign clkp=clkpr;
endmodule | 1 |
139,790 | data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v | 89,810,125 | wb_sintesis_sinFIR.v | v | 471 | 155 | [] | [] | [] | [(1, 16), (18, 49), (51, 78), (80, 92), (94, 106), (108, 119), (121, 133), (135, 211), (213, 230), (232, 273), (276, 298), (300, 374), (388, 467)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:419: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:129: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:102: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:88: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= (tiempo*5)/256;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:257: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:261: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:260: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:229: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 7 bits.\n : ... In instance wb_sintesis.sint0.env11\n assign amp_res = ((amp_a + amp_d + amp_s + amp_r)*amp)/64;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:66: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 34 warning(s)\n' | 307,812 | module | module seleccion (
input clk,
input tecla,
input start,
output [13:0] cont,
output reg en,
output busyf
);
reg [13:0] cont0 = 14'b0;
reg busy1 = 1'b0;
reg busy2 = 1'b0;
wire busyr;
assign busyr = busy1 ^ busy2;
always @ (posedge clk) begin
if (start) begin
if (busyr == 1'b0) begin
en <= tecla;
if (en) busy1 <= ~busy1;
end
else begin
if (cont0<14'd15625)
cont0<=cont+1;
else begin
cont0<=14'b0;
busy2<=~busy2;
end
end
end
end
assign cont = cont0;
assign busyf = busyr;
endmodule | module seleccion (
input clk,
input tecla,
input start,
output [13:0] cont,
output reg en,
output busyf
); |
reg [13:0] cont0 = 14'b0;
reg busy1 = 1'b0;
reg busy2 = 1'b0;
wire busyr;
assign busyr = busy1 ^ busy2;
always @ (posedge clk) begin
if (start) begin
if (busyr == 1'b0) begin
en <= tecla;
if (en) busy1 <= ~busy1;
end
else begin
if (cont0<14'd15625)
cont0<=cont+1;
else begin
cont0<=14'b0;
busy2<=~busy2;
end
end
end
end
assign cont = cont0;
assign busyf = busyr;
endmodule | 1 |
139,791 | data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v | 89,810,125 | wb_sintesis_sinFIR.v | v | 471 | 155 | [] | [] | [] | [(1, 16), (18, 49), (51, 78), (80, 92), (94, 106), (108, 119), (121, 133), (135, 211), (213, 230), (232, 273), (276, 298), (300, 374), (388, 467)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:419: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:129: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:102: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:88: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= (tiempo*5)/256;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:257: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:261: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:260: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:229: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 7 bits.\n : ... In instance wb_sintesis.sint0.env11\n assign amp_res = ((amp_a + amp_d + amp_s + amp_r)*amp)/64;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:66: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 34 warning(s)\n' | 307,812 | module | module oscilador(
input en,
input clk,
input [5:0] nmuestras,
input [8:0] factor,
output [5:0] amp1,
output reg done_osc
);
reg [5:0] amp;
reg [5:0] cont=0;
always @ (posedge clk) begin
if (en==1) begin
amp<=factor*cont/128;
cont<=cont+1;
done_osc <= 1;
if (cont==nmuestras)
cont<=0;
end
else begin
amp<=0;
done_osc <= 0;
end
end
assign amp1=amp;
endmodule | module oscilador(
input en,
input clk,
input [5:0] nmuestras,
input [8:0] factor,
output [5:0] amp1,
output reg done_osc
); |
reg [5:0] amp;
reg [5:0] cont=0;
always @ (posedge clk) begin
if (en==1) begin
amp<=factor*cont/128;
cont<=cont+1;
done_osc <= 1;
if (cont==nmuestras)
cont<=0;
end
else begin
amp<=0;
done_osc <= 0;
end
end
assign amp1=amp;
endmodule | 1 |
139,792 | data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v | 89,810,125 | wb_sintesis_sinFIR.v | v | 471 | 155 | [] | [] | [] | [(1, 16), (18, 49), (51, 78), (80, 92), (94, 106), (108, 119), (121, 133), (135, 211), (213, 230), (232, 273), (276, 298), (300, 374), (388, 467)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:419: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:129: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:102: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:88: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= (tiempo*5)/256;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:257: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:261: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:260: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:229: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 7 bits.\n : ... In instance wb_sintesis.sint0.env11\n assign amp_res = ((amp_a + amp_d + amp_s + amp_r)*amp)/64;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:66: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 34 warning(s)\n' | 307,812 | module | module attack (
input [13:0] tiempo,
input en,
output reg [5:0] amp_env
);
always @ (tiempo,en) begin
if (en)
amp_env <= (tiempo*5)/256;
else
amp_env <= 6'b0;
end
endmodule | module attack (
input [13:0] tiempo,
input en,
output reg [5:0] amp_env
); |
always @ (tiempo,en) begin
if (en)
amp_env <= (tiempo*5)/256;
else
amp_env <= 6'b0;
end
endmodule | 1 |
139,793 | data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v | 89,810,125 | wb_sintesis_sinFIR.v | v | 471 | 155 | [] | [] | [] | [(1, 16), (18, 49), (51, 78), (80, 92), (94, 106), (108, 119), (121, 133), (135, 211), (213, 230), (232, 273), (276, 298), (300, 374), (388, 467)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:419: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:129: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:102: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:88: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= (tiempo*5)/256;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:257: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:261: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:260: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:229: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 7 bits.\n : ... In instance wb_sintesis.sint0.env11\n assign amp_res = ((amp_a + amp_d + amp_s + amp_r)*amp)/64;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:66: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 34 warning(s)\n' | 307,812 | module | module decay(
input [13:0] tiempo,
input en,
output reg [5:0] amp_env
);
always @ (tiempo,en) begin
if (en)
amp_env <= 78 - (5*tiempo)/1024;
else
amp_env <= 6'b0;
end
endmodule | module decay(
input [13:0] tiempo,
input en,
output reg [5:0] amp_env
); |
always @ (tiempo,en) begin
if (en)
amp_env <= 78 - (5*tiempo)/1024;
else
amp_env <= 6'b0;
end
endmodule | 1 |
139,794 | data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v | 89,810,125 | wb_sintesis_sinFIR.v | v | 471 | 155 | [] | [] | [] | [(1, 16), (18, 49), (51, 78), (80, 92), (94, 106), (108, 119), (121, 133), (135, 211), (213, 230), (232, 273), (276, 298), (300, 374), (388, 467)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:419: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:129: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:102: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:88: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= (tiempo*5)/256;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:257: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:261: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:260: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:229: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 7 bits.\n : ... In instance wb_sintesis.sint0.env11\n assign amp_res = ((amp_a + amp_d + amp_s + amp_r)*amp)/64;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:66: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 34 warning(s)\n' | 307,812 | module | module sustain(
input en,
output reg [5:0] amp_env
);
always @ (en) begin
if (en)
amp_env <= 6'd32;
else
amp_env <= 6'b0;
end
endmodule | module sustain(
input en,
output reg [5:0] amp_env
); |
always @ (en) begin
if (en)
amp_env <= 6'd32;
else
amp_env <= 6'b0;
end
endmodule | 1 |
139,795 | data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v | 89,810,125 | wb_sintesis_sinFIR.v | v | 471 | 155 | [] | [] | [] | [(1, 16), (18, 49), (51, 78), (80, 92), (94, 106), (108, 119), (121, 133), (135, 211), (213, 230), (232, 273), (276, 298), (300, 374), (388, 467)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:419: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:129: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:102: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:88: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= (tiempo*5)/256;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:257: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:261: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:260: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:229: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 7 bits.\n : ... In instance wb_sintesis.sint0.env11\n assign amp_res = ((amp_a + amp_d + amp_s + amp_r)*amp)/64;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:66: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 34 warning(s)\n' | 307,812 | module | module releasee(
input [13:0] tiempo,
input en,
output reg [5:0] amp_env
);
always @ (tiempo,en) begin
if (en)
amp_env <= 153 - (10*tiempo)/1024;
else
amp_env <= 6'b0;
end
endmodule | module releasee(
input [13:0] tiempo,
input en,
output reg [5:0] amp_env
); |
always @ (tiempo,en) begin
if (en)
amp_env <= 153 - (10*tiempo)/1024;
else
amp_env <= 6'b0;
end
endmodule | 1 |
139,796 | data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v | 89,810,125 | wb_sintesis_sinFIR.v | v | 471 | 155 | [] | [] | [] | [(1, 16), (18, 49), (51, 78), (80, 92), (94, 106), (108, 119), (121, 133), (135, 211), (213, 230), (232, 273), (276, 298), (300, 374), (388, 467)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:419: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:129: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:102: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:88: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= (tiempo*5)/256;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:257: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:261: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:260: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:229: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 7 bits.\n : ... In instance wb_sintesis.sint0.env11\n assign amp_res = ((amp_a + amp_d + amp_s + amp_r)*amp)/64;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:66: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 34 warning(s)\n' | 307,812 | module | module control_envolvente(
input [13:0] tiempo,
input start,
input clk,
input reset,
output reg done,
output reg en_a,
output reg en_d,
output reg en_s,
output reg en_r
);
parameter S0 = 3'h0;
parameter S1 = 3'h1;
parameter S2 = 3'h2;
parameter S3 = 3'h3;
parameter S4 = 3'h4;
reg [2:0] state = S0;
reg [2:0] nextstate = S0;
always @ (posedge clk) begin
if (reset) state <= S0;
else state <= nextstate;
end
always @ (*) begin
case (state)
S0: if (start) nextstate <= S1;
else nextstate <= S0;
S1: if (tiempo <= 14'd3125) nextstate <= S1;
else nextstate <= S2;
S2: if (tiempo <= 14'd9375) nextstate <= S2;
else nextstate <= S3;
S3: if (tiempo <= 14'd12500) nextstate <= S3;
else nextstate <= S4;
S4: if (tiempo <= 14'd15625) nextstate <= S4;
else nextstate <= S0;
endcase
end
always @ (*) begin
case (state)
S0: begin
en_a <= 1'b0;
en_d <= 1'b0;
en_s <= 1'b0;
en_r <= 1'b0;
done <= 1'b0;
end
S1: begin
en_a <= 1'b1;
en_d <= 1'b0;
en_s <= 1'b0;
en_r <= 1'b0;
done <= 1'b1;
end
S2: begin
en_a <= 1'b0;
en_d <= 1'b1;
en_s <= 1'b0;
en_r <= 1'b0;
done <= 1'b1;
end
S3: begin
en_a <= 1'b0;
en_d <= 1'b0;
en_s <= 1'b1;
en_r <= 1'b0;
done <= 1'b1;
end
S4: begin
en_a <= 1'b0;
en_d <= 1'b0;
en_s <= 1'b0;
en_r <= 1'b1;
done <= 1'b1;
end
endcase
end
endmodule | module control_envolvente(
input [13:0] tiempo,
input start,
input clk,
input reset,
output reg done,
output reg en_a,
output reg en_d,
output reg en_s,
output reg en_r
); |
parameter S0 = 3'h0;
parameter S1 = 3'h1;
parameter S2 = 3'h2;
parameter S3 = 3'h3;
parameter S4 = 3'h4;
reg [2:0] state = S0;
reg [2:0] nextstate = S0;
always @ (posedge clk) begin
if (reset) state <= S0;
else state <= nextstate;
end
always @ (*) begin
case (state)
S0: if (start) nextstate <= S1;
else nextstate <= S0;
S1: if (tiempo <= 14'd3125) nextstate <= S1;
else nextstate <= S2;
S2: if (tiempo <= 14'd9375) nextstate <= S2;
else nextstate <= S3;
S3: if (tiempo <= 14'd12500) nextstate <= S3;
else nextstate <= S4;
S4: if (tiempo <= 14'd15625) nextstate <= S4;
else nextstate <= S0;
endcase
end
always @ (*) begin
case (state)
S0: begin
en_a <= 1'b0;
en_d <= 1'b0;
en_s <= 1'b0;
en_r <= 1'b0;
done <= 1'b0;
end
S1: begin
en_a <= 1'b1;
en_d <= 1'b0;
en_s <= 1'b0;
en_r <= 1'b0;
done <= 1'b1;
end
S2: begin
en_a <= 1'b0;
en_d <= 1'b1;
en_s <= 1'b0;
en_r <= 1'b0;
done <= 1'b1;
end
S3: begin
en_a <= 1'b0;
en_d <= 1'b0;
en_s <= 1'b1;
en_r <= 1'b0;
done <= 1'b1;
end
S4: begin
en_a <= 1'b0;
en_d <= 1'b0;
en_s <= 1'b0;
en_r <= 1'b1;
done <= 1'b1;
end
endcase
end
endmodule | 1 |
139,797 | data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v | 89,810,125 | wb_sintesis_sinFIR.v | v | 471 | 155 | [] | [] | [] | [(1, 16), (18, 49), (51, 78), (80, 92), (94, 106), (108, 119), (121, 133), (135, 211), (213, 230), (232, 273), (276, 298), (300, 374), (388, 467)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:419: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:129: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:102: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:88: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= (tiempo*5)/256;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:257: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:261: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:260: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:229: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 7 bits.\n : ... In instance wb_sintesis.sint0.env11\n assign amp_res = ((amp_a + amp_d + amp_s + amp_r)*amp)/64;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:66: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 34 warning(s)\n' | 307,812 | module | module envolvente(
input [13:0] tiempo,
input clk,
input start,
input reset,
input [5:0] amp,
output done,
output [5:0] amp_res
);
wire en_a, en_d, en_s, en_r;
wire [5:0] amp_a, amp_d, amp_s, amp_r;
control_envolvente control_env0 (tiempo,start,clk,reset,done,en_a,en_d,en_s,en_r);
attack attack0 (tiempo,en_a,amp_a);
decay decay0 (tiempo,en_d,amp_d);
sustain sustain0 (en_s,amp_s);
releasee releasee0 (tiempo,en_r,amp_r);
assign amp_res = ((amp_a + amp_d + amp_s + amp_r)*amp)/64;
endmodule | module envolvente(
input [13:0] tiempo,
input clk,
input start,
input reset,
input [5:0] amp,
output done,
output [5:0] amp_res
); |
wire en_a, en_d, en_s, en_r;
wire [5:0] amp_a, amp_d, amp_s, amp_r;
control_envolvente control_env0 (tiempo,start,clk,reset,done,en_a,en_d,en_s,en_r);
attack attack0 (tiempo,en_a,amp_a);
decay decay0 (tiempo,en_d,amp_d);
sustain sustain0 (en_s,amp_s);
releasee releasee0 (tiempo,en_r,amp_r);
assign amp_res = ((amp_a + amp_d + amp_s + amp_r)*amp)/64;
endmodule | 1 |
139,798 | data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v | 89,810,125 | wb_sintesis_sinFIR.v | v | 471 | 155 | [] | [] | [] | [(1, 16), (18, 49), (51, 78), (80, 92), (94, 106), (108, 119), (121, 133), (135, 211), (213, 230), (232, 273), (276, 298), (300, 374), (388, 467)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:419: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:129: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:102: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:88: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= (tiempo*5)/256;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:257: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:261: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:260: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:229: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 7 bits.\n : ... In instance wb_sintesis.sint0.env11\n assign amp_res = ((amp_a + amp_d + amp_s + amp_r)*amp)/64;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:66: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 34 warning(s)\n' | 307,812 | module | module suma_amp(
input clk,
input start,
input [9:0] a,
input [11:0] en,
output done,
output reg [5:0] result
);
reg [5:0] rp = 6'b0;
reg [9:0] c,d;
reg load = 1'b1;
reg done1 = 1'b1;
reg loaden;
wire [3:0] b,num_teclas;
assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];
assign b = num_teclas;
always @ (posedge clk) begin
loaden <= load & start;
if(loaden) begin
c<=a;
d<=a;
load<=1'b0;
rp<=1'b0;
end
else if (c>=b) begin
c<=c-b;
rp<=rp+1;
done1<=0;
end
else begin
done1<=1;
result<=rp;
if (a!=d)
load<=1;
end
end
assign done = done1;
endmodule | module suma_amp(
input clk,
input start,
input [9:0] a,
input [11:0] en,
output done,
output reg [5:0] result
); |
reg [5:0] rp = 6'b0;
reg [9:0] c,d;
reg load = 1'b1;
reg done1 = 1'b1;
reg loaden;
wire [3:0] b,num_teclas;
assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];
assign b = num_teclas;
always @ (posedge clk) begin
loaden <= load & start;
if(loaden) begin
c<=a;
d<=a;
load<=1'b0;
rp<=1'b0;
end
else if (c>=b) begin
c<=c-b;
rp<=rp+1;
done1<=0;
end
else begin
done1<=1;
result<=rp;
if (a!=d)
load<=1;
end
end
assign done = done1;
endmodule | 1 |
139,799 | data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v | 89,810,125 | wb_sintesis_sinFIR.v | v | 471 | 155 | [] | [] | [] | [(1, 16), (18, 49), (51, 78), (80, 92), (94, 106), (108, 119), (121, 133), (135, 211), (213, 230), (232, 273), (276, 298), (300, 374), (388, 467)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:419: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:129: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:102: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:88: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= (tiempo*5)/256;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:257: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:261: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:260: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:229: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 7 bits.\n : ... In instance wb_sintesis.sint0.env11\n assign amp_res = ((amp_a + amp_d + amp_s + amp_r)*amp)/64;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:66: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 34 warning(s)\n' | 307,812 | module | module pwm(
input [5:0] sint_data,
input en,
input clk,
output pulse_data,
output busy_pwm
);
reg pulse_reg;
reg [5:0] cont=6'd63;
reg [5:0] pwm_in=0;
always @ (posedge clk) begin
if (cont==6'd63) begin
pwm_in<=sint_data;
cont=0;
end
else cont=cont+1;
if (cont<sint_data)
pulse_reg=1;
else pulse_reg=0;
end
assign pulse_data=pulse_reg;
assign busy_pwm = en;
endmodule | module pwm(
input [5:0] sint_data,
input en,
input clk,
output pulse_data,
output busy_pwm
); |
reg pulse_reg;
reg [5:0] cont=6'd63;
reg [5:0] pwm_in=0;
always @ (posedge clk) begin
if (cont==6'd63) begin
pwm_in<=sint_data;
cont=0;
end
else cont=cont+1;
if (cont<sint_data)
pulse_reg=1;
else pulse_reg=0;
end
assign pulse_data=pulse_reg;
assign busy_pwm = en;
endmodule | 1 |
139,800 | data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v | 89,810,125 | wb_sintesis_sinFIR.v | v | 471 | 155 | [] | [] | [] | [(1, 16), (18, 49), (51, 78), (80, 92), (94, 106), (108, 119), (121, 133), (135, 211), (213, 230), (232, 273), (276, 298), (300, 374), (388, 467)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:419: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:129: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:102: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:88: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= (tiempo*5)/256;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:257: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:261: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:260: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:229: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 7 bits.\n : ... In instance wb_sintesis.sint0.env11\n assign amp_res = ((amp_a + amp_d + amp_s + amp_r)*amp)/64;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:66: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 34 warning(s)\n' | 307,812 | module | module sintesis(
input sel,
input [11:0] teclas,
input clk,
input start,
output pulse_data,
output busy_pwm
);
wire clk_fm;
clkg clk_fm0 (clk,1600,clk_fm);
wire clk_1u;
clkg clk_1u0 (clk,25,clk_1u);
wire [11:0] en_osc;
wire [11:0] done_osc;
wire [11:0] start_env;
wire [11:0] busyf;
wire [11:0] done_env;
wire reset;
assign reset=sel;
wire [5:0] amp_final;
wire [5:0] amp0,amp1,amp2,amp3,amp4,amp5,amp6,amp7,amp8,amp9,amp10,amp11;
wire [5:0] aenv0,aenv1,aenv2,aenv3,aenv4,aenv5,aenv6,aenv7,aenv8,aenv9,aenv10,aenv11;
wire [13:0] tiempo0,tiempo1,tiempo2,tiempo3,tiempo4,tiempo5,tiempo6,tiempo7,tiempo8,tiempo9,tiempo10,tiempo11;
wire [9:0] amp_env_total;
wire done_suma, start_suma;
assign start_env = done_osc;
seleccion s0 (clk_fm, teclas[0], start, tiempo0, en_osc[0], busyf[0]);
seleccion s1 (clk_fm, teclas[1], start, tiempo1, en_osc[1], busyf[1]);
seleccion s2 (clk_fm, teclas[2], start, tiempo2, en_osc[2], busyf[2]);
seleccion s3 (clk_fm, teclas[3], start, tiempo3, en_osc[3], busyf[3]);
seleccion s4 (clk_fm, teclas[4], start, tiempo4, en_osc[4], busyf[4]);
seleccion s5 (clk_fm, teclas[5], start, tiempo5, en_osc[5], busyf[5]);
seleccion s6 (clk_fm, teclas[6], start, tiempo6, en_osc[6], busyf[6]);
seleccion s7 (clk_fm, teclas[7], start, tiempo7, en_osc[7], busyf[7]);
seleccion s8 (clk_fm, teclas[8], start, tiempo8, en_osc[8], busyf[8]);
seleccion s9 (clk_fm, teclas[9], start, tiempo9, en_osc[9], busyf[9]);
seleccion s10 (clk_fm, teclas[10], start, tiempo10, en_osc[10], busyf[10]);
seleccion s11 (clk_fm, teclas[11], start, tiempo11, en_osc[11], busyf[11]);
oscilador o0 (en_osc[0],clk_fm, 59, 138, amp0,done_osc[0]);
oscilador o1 (en_osc[1],clk_fm, 55, 148, amp1,done_osc[1]);
oscilador o2 (en_osc[2],clk_fm, 52, 157, amp2,done_osc[2]);
oscilador o3 (en_osc[3],clk_fm, 49, 167, amp3,done_osc[3]);
oscilador o4 (en_osc[4],clk_fm, 46, 178, amp4,done_osc[4]);
oscilador o5 (en_osc[5],clk_fm, 44, 186, amp5,done_osc[5]);
oscilador o6 (en_osc[6],clk_fm, 41, 199, amp6,done_osc[6]);
oscilador o7 (en_osc[7],clk_fm, 39, 210, amp7,done_osc[7]);
oscilador o8 (en_osc[8],clk_fm, 37, 221, amp8,done_osc[8]);
oscilador o9 (en_osc[9],clk_fm, 35, 234, amp9,done_osc[9]);
oscilador o10 (en_osc[10],clk_fm, 33, 248, amp10,done_osc[10]);
oscilador o11 (en_osc[11],clk_fm, 31, 264, amp11,done_osc[11]);
envolvente env0 (tiempo0,clk_fm,start_env[0],reset,amp0,done_env[0],aenv0);
envolvente env1 (tiempo1,clk_fm,start_env[1],reset,amp1,done_env[1],aenv1);
envolvente env2 (tiempo2,clk_fm,start_env[2],reset,amp0,done_env[2],aenv2);
envolvente env3 (tiempo3,clk_fm,start_env[3],reset,amp3,done_env[3],aenv3);
envolvente env4 (tiempo4,clk_fm,start_env[4],reset,amp4,done_env[4],aenv4);
envolvente env5 (tiempo5,clk_fm,start_env[5],reset,amp5,done_env[5],aenv5);
envolvente env6 (tiempo6,clk_fm,start_env[6],reset,amp6,done_env[6],aenv6);
envolvente env7 (tiempo7,clk_fm,start_env[7],reset,amp7,done_env[7],aenv7);
envolvente env8 (tiempo8,clk_fm,start_env[8],reset,amp8,done_env[8],aenv8);
envolvente env9 (tiempo9,clk_fm,start_env[9],reset,amp9,done_env[9],aenv9);
envolvente env10 (tiempo10,clk_fm,start_env[10],reset,amp10,done_env[10],aenv10);
envolvente env11 (tiempo11,clk_fm,start_env[11],reset,amp11,done_env[11],aenv11);
assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11;
assign start_suma = | done_env;
suma_amp suma1 (clk,start_suma,amp_env_total,en_osc,done_suma,amp_final);
pwm pwm0 (amp_final,done_suma,clk_1u,pulse_data,busy_pwm);
endmodule | module sintesis(
input sel,
input [11:0] teclas,
input clk,
input start,
output pulse_data,
output busy_pwm
); |
wire clk_fm;
clkg clk_fm0 (clk,1600,clk_fm);
wire clk_1u;
clkg clk_1u0 (clk,25,clk_1u);
wire [11:0] en_osc;
wire [11:0] done_osc;
wire [11:0] start_env;
wire [11:0] busyf;
wire [11:0] done_env;
wire reset;
assign reset=sel;
wire [5:0] amp_final;
wire [5:0] amp0,amp1,amp2,amp3,amp4,amp5,amp6,amp7,amp8,amp9,amp10,amp11;
wire [5:0] aenv0,aenv1,aenv2,aenv3,aenv4,aenv5,aenv6,aenv7,aenv8,aenv9,aenv10,aenv11;
wire [13:0] tiempo0,tiempo1,tiempo2,tiempo3,tiempo4,tiempo5,tiempo6,tiempo7,tiempo8,tiempo9,tiempo10,tiempo11;
wire [9:0] amp_env_total;
wire done_suma, start_suma;
assign start_env = done_osc;
seleccion s0 (clk_fm, teclas[0], start, tiempo0, en_osc[0], busyf[0]);
seleccion s1 (clk_fm, teclas[1], start, tiempo1, en_osc[1], busyf[1]);
seleccion s2 (clk_fm, teclas[2], start, tiempo2, en_osc[2], busyf[2]);
seleccion s3 (clk_fm, teclas[3], start, tiempo3, en_osc[3], busyf[3]);
seleccion s4 (clk_fm, teclas[4], start, tiempo4, en_osc[4], busyf[4]);
seleccion s5 (clk_fm, teclas[5], start, tiempo5, en_osc[5], busyf[5]);
seleccion s6 (clk_fm, teclas[6], start, tiempo6, en_osc[6], busyf[6]);
seleccion s7 (clk_fm, teclas[7], start, tiempo7, en_osc[7], busyf[7]);
seleccion s8 (clk_fm, teclas[8], start, tiempo8, en_osc[8], busyf[8]);
seleccion s9 (clk_fm, teclas[9], start, tiempo9, en_osc[9], busyf[9]);
seleccion s10 (clk_fm, teclas[10], start, tiempo10, en_osc[10], busyf[10]);
seleccion s11 (clk_fm, teclas[11], start, tiempo11, en_osc[11], busyf[11]);
oscilador o0 (en_osc[0],clk_fm, 59, 138, amp0,done_osc[0]);
oscilador o1 (en_osc[1],clk_fm, 55, 148, amp1,done_osc[1]);
oscilador o2 (en_osc[2],clk_fm, 52, 157, amp2,done_osc[2]);
oscilador o3 (en_osc[3],clk_fm, 49, 167, amp3,done_osc[3]);
oscilador o4 (en_osc[4],clk_fm, 46, 178, amp4,done_osc[4]);
oscilador o5 (en_osc[5],clk_fm, 44, 186, amp5,done_osc[5]);
oscilador o6 (en_osc[6],clk_fm, 41, 199, amp6,done_osc[6]);
oscilador o7 (en_osc[7],clk_fm, 39, 210, amp7,done_osc[7]);
oscilador o8 (en_osc[8],clk_fm, 37, 221, amp8,done_osc[8]);
oscilador o9 (en_osc[9],clk_fm, 35, 234, amp9,done_osc[9]);
oscilador o10 (en_osc[10],clk_fm, 33, 248, amp10,done_osc[10]);
oscilador o11 (en_osc[11],clk_fm, 31, 264, amp11,done_osc[11]);
envolvente env0 (tiempo0,clk_fm,start_env[0],reset,amp0,done_env[0],aenv0);
envolvente env1 (tiempo1,clk_fm,start_env[1],reset,amp1,done_env[1],aenv1);
envolvente env2 (tiempo2,clk_fm,start_env[2],reset,amp0,done_env[2],aenv2);
envolvente env3 (tiempo3,clk_fm,start_env[3],reset,amp3,done_env[3],aenv3);
envolvente env4 (tiempo4,clk_fm,start_env[4],reset,amp4,done_env[4],aenv4);
envolvente env5 (tiempo5,clk_fm,start_env[5],reset,amp5,done_env[5],aenv5);
envolvente env6 (tiempo6,clk_fm,start_env[6],reset,amp6,done_env[6],aenv6);
envolvente env7 (tiempo7,clk_fm,start_env[7],reset,amp7,done_env[7],aenv7);
envolvente env8 (tiempo8,clk_fm,start_env[8],reset,amp8,done_env[8],aenv8);
envolvente env9 (tiempo9,clk_fm,start_env[9],reset,amp9,done_env[9],aenv9);
envolvente env10 (tiempo10,clk_fm,start_env[10],reset,amp10,done_env[10],aenv10);
envolvente env11 (tiempo11,clk_fm,start_env[11],reset,amp11,done_env[11],aenv11);
assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11;
assign start_suma = | done_env;
suma_amp suma1 (clk,start_suma,amp_env_total,en_osc,done_suma,amp_final);
pwm pwm0 (amp_final,done_suma,clk_1u,pulse_data,busy_pwm);
endmodule | 1 |
139,801 | data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v | 89,810,125 | wb_sintesis_sinFIR.v | v | 471 | 155 | [] | [] | [] | [(1, 16), (18, 49), (51, 78), (80, 92), (94, 106), (108, 119), (121, 133), (135, 211), (213, 230), (232, 273), (276, 298), (300, 374), (388, 467)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:419: Signal definition not found, creating implicitly: \'busy_busy\'\n .busy_pwm(busy_busy)\n ^~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:129: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.releasee0\n amp_env <= 153 - (10*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:102: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.decay0\n amp_env <= 78 - (5*tiempo)/1024;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:88: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 14 bits.\n : ... In instance wb_sintesis.sint0.env11.attack0\n amp_env <= (tiempo*5)/256;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:247: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n assign num_teclas = en[0]+en[1]+en[2]+en[3]+en[4]+en[5]+en[5]+en[6]+en[7]+en[8]+en[9]+en[10]+en[11];\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:257: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance wb_sintesis.sint0.suma1\n rp<=1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:261: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n c<=c-b;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:260: Operator GTE expects 10 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n : ... In instance wb_sintesis.sint0.suma1\n else if (c>=b) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:229: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 7 bits.\n : ... In instance wb_sintesis.sint0.env11\n assign amp_res = ((amp_a + amp_d + amp_s + amp_r)*amp)/64;\n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:66: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 9 bits.\n : ... In instance wb_sintesis.sint0.o11\n amp<=factor*cont/128; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'aenv0\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv1\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv2\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv3\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv4\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv5\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv6\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv7\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv8\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv9\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv10\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Warning-WIDTH: data/full_repos/permissive/89810125/rtl/wb_sintesis_sinFIR.v:365: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'aenv11\' generates 6 bits.\n : ... In instance wb_sintesis.sint0\n assign amp_env_total = aenv0+aenv1+aenv2+aenv3+aenv4+aenv5+aenv6+aenv7+aenv8+aenv9+aenv10+aenv11; \n ^\n%Error: Exiting due to 34 warning(s)\n' | 307,812 | module | module wb_sintesis (
input clk,
input reset,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
input wb_we_i,
input [31:0] wb_adr_i,
input [3:0] wb_sel_i,
input [31:0] wb_dat_i,
output reg [31:0] wb_dat_o,
input [12:0] teclado,
output pulse_data
);
wire sel;
wire [11:0] teclas;
wire busy_pwm;
reg start;
sintesis sint0 (
.sel(sel),
.teclas(teclas),
.clk(clk),
.start(start),
.pulse_data(pulse_data),
.busy_pwm(busy_busy)
);
assign teclas = teclado[11:0];
assign sel = teclado[12];
wire [31:0] teclasw = {20'b0, teclas};
wire [31:0] data = { 30'b0, pulse_data, sel};
wire [31:0] cs = { 30'b0, busy_pwm, start};
wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i;
wire wb_wr = wb_stb_i & wb_cyc_i & wb_we_i;
reg ack;
assign wb_ack_o = wb_stb_i & wb_cyc_i & ack;
always @(posedge clk)
begin
if (~reset) begin
wb_dat_o[31:0] <= 32'b0;
ack <= 0;
end else begin
wb_dat_o[31:0] <= 32'b0;
ack <= 0;
if (wb_rd & ~ack) begin
ack <= 1;
case (wb_adr_i[3:0])
'h00: wb_dat_o <= 32'b0;
'h04: wb_dat_o[0] <= data[1];
'h08: wb_dat_o[0] <= cs[1];
default: wb_dat_o <= 32'b0;
endcase
end else if (wb_wr & ~ack ) begin
ack <= 1;
case (wb_adr_i[3:2])
'h02: start <= wb_dat_i[0];
endcase
end
end
end
endmodule | module wb_sintesis (
input clk,
input reset,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
input wb_we_i,
input [31:0] wb_adr_i,
input [3:0] wb_sel_i,
input [31:0] wb_dat_i,
output reg [31:0] wb_dat_o,
input [12:0] teclado,
output pulse_data
); |
wire sel;
wire [11:0] teclas;
wire busy_pwm;
reg start;
sintesis sint0 (
.sel(sel),
.teclas(teclas),
.clk(clk),
.start(start),
.pulse_data(pulse_data),
.busy_pwm(busy_busy)
);
assign teclas = teclado[11:0];
assign sel = teclado[12];
wire [31:0] teclasw = {20'b0, teclas};
wire [31:0] data = { 30'b0, pulse_data, sel};
wire [31:0] cs = { 30'b0, busy_pwm, start};
wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i;
wire wb_wr = wb_stb_i & wb_cyc_i & wb_we_i;
reg ack;
assign wb_ack_o = wb_stb_i & wb_cyc_i & ack;
always @(posedge clk)
begin
if (~reset) begin
wb_dat_o[31:0] <= 32'b0;
ack <= 0;
end else begin
wb_dat_o[31:0] <= 32'b0;
ack <= 0;
if (wb_rd & ~ack) begin
ack <= 1;
case (wb_adr_i[3:0])
'h00: wb_dat_o <= 32'b0;
'h04: wb_dat_o[0] <= data[1];
'h08: wb_dat_o[0] <= cs[1];
default: wb_dat_o <= 32'b0;
endcase
end else if (wb_wr & ~ack ) begin
ack <= 1;
case (wb_adr_i[3:2])
'h02: start <= wb_dat_i[0];
endcase
end
end
end
endmodule | 1 |
139,803 | data/full_repos/permissive/89810125/rtl/lac/lac.v | 89,810,125 | lac.v | v | 263 | 88 | [] | [] | [] | [(5, 262)] | null | null | 1: b"%Error: data/full_repos/permissive/89810125/rtl/lac/lac.v:40: Cannot find file containing module: 'uart'\nuart #(\n^~~~\n ... Looked in:\n data/full_repos/permissive/89810125/rtl/lac,data/full_repos/permissive/89810125/uart\n data/full_repos/permissive/89810125/rtl/lac,data/full_repos/permissive/89810125/uart.v\n data/full_repos/permissive/89810125/rtl/lac,data/full_repos/permissive/89810125/uart.sv\n uart\n uart.v\n uart.sv\n obj_dir/uart\n obj_dir/uart.v\n obj_dir/uart.sv\n%Error: data/full_repos/permissive/89810125/rtl/lac/lac.v:247: Cannot find file containing module: 'dp_ram'\ndp_ram #(\n^~~~~~\n%Error: Exiting due to 2 error(s)\n" | 307,814 | module | module lac #(
parameter uart_freq_hz = 100000000,
parameter uart_baud = 115200,
parameter adr_width = 11,
parameter width = 8
) (
input reset,
input uart_clk,
input uart_rxd,
output uart_cts,
output uart_txd,
input uart_rts,
input probe_clk,
input [width-1:0] probe,
output reg [7:0] select
);
parameter cmd_nop = 8'h20;
parameter cmd_arm = 8'h01;
parameter cmd_disarm = 8'h02;
assign uart_cts = 1;
reg tx_wr;
wire tx_busy;
reg [7:0] tx_data;
wire [7:0] rx_data;
wire rx_avail;
reg rx_ack;
uart #(
.freq_hz( uart_freq_hz ),
.baud( uart_baud )
) uart0 (
.reset( reset ),
.clk( uart_clk ),
.uart_txd( uart_txd ),
.uart_rxd( uart_rxd ),
.rx_data( rx_data ),
.rx_avail( rx_avail ),
.rx_error( rx_error ),
.rx_ack( rx_ack ),
.tx_data( tx_data ),
.tx_wr( tx_wr ),
.tx_busy( tx_busy )
);
reg [7:0] trig_mask;
reg [7:0] trig_cond;
reg [7:0] trig_pre;
reg [adr_width-1:0] start_adr;
reg armed;
reg triggered;
wire rx_req;
assign rx_req = rx_avail & ~rx_ack;
reg triggered_synced;
wire [width-1:0] read_dat;
reg [adr_width-1:0] read_adr;
wire [adr_width-1:0] read_adr_next;
assign read_adr_next = read_adr + 1;
reg [2:0] state;
parameter s_idle = 0;
parameter s_read_select= 1;
parameter s_read_mask = 2;
parameter s_read_comp = 3;
parameter s_read_pre = 4;
parameter s_triggered = 5;
parameter s_send_byte = 6;
always @(posedge uart_clk)
begin
if (reset) begin
state <= s_idle;
select <= 0;
armed <= 0;
tx_wr <= 0;
end else begin
triggered_synced <= triggered;
rx_ack <= 0;
tx_wr <= 0;
case (state)
s_idle: begin
if (rx_req) begin
case (rx_data)
cmd_arm: begin
rx_ack <= 1;
state <= s_read_select;
end
cmd_disarm: begin
rx_ack <= 1;
armed <= 0;
end
default: begin
rx_ack <= 1;
end
endcase
end
if (~rx_req && triggered_synced) begin
state <= s_triggered;
end
end
s_read_select: begin
if (rx_req) begin
rx_ack <= 1;
select <= rx_data;
state <= s_read_mask;
end
end
s_read_mask: begin
if (rx_req) begin
rx_ack <= 1;
trig_mask <= rx_data;
state <= s_read_comp;
end
end
s_read_comp: begin
if (rx_req) begin
rx_ack <= 1;
trig_cond <= rx_data;
armed <= 1;
state <= s_read_pre;
end
end
s_read_pre: begin
if (rx_req) begin
rx_ack <= 1;
trig_pre <= rx_data;
armed <= 1;
state <= s_idle;
end
end
s_triggered: begin
armed <= 0;
read_adr <= start_adr;
tx_data <= adr_width;
tx_wr <= 1;
state <= s_send_byte;
end
s_send_byte: begin
tx_wr <= 0;
if (~tx_busy & ~tx_wr) begin
if (read_adr_next == start_adr)
state <= s_idle;
read_adr <= read_adr_next;
tx_data <= read_dat;
tx_wr <= 1;
end
end
default:
state <= s_idle;
endcase
end
end
reg [width-1:0] probe_r;
always @(posedge probe_clk)
probe_r <= probe;
reg armed_synced;
reg armed_synced2;
reg sampling;
reg [adr_width-1:0] write_adr;
wire [adr_width-1:0] next_adr;
assign next_adr = write_adr + 1;
wire cond_match;
assign cond_match = (probe_r & trig_mask) == (trig_cond & trig_mask) && armed_synced2;
always @(posedge probe_clk)
begin
if (reset) begin
armed_synced <= 0;
armed_synced2 <= 0;
sampling <= 0;
triggered <= 0;
write_adr <= 0;
end else begin
armed_synced <= armed;
armed_synced2 <= armed_synced;
if (armed_synced2 || sampling) begin
write_adr <= next_adr;
end
if (~triggered && armed_synced2) begin
if (cond_match) begin
sampling <= 1;
triggered <= 1;
start_adr <= write_adr;
end
end
if (sampling && next_adr == start_adr) begin
sampling <= 0;
end
if (~sampling && ~armed_synced2 && triggered)
triggered <= 0;
end
end
wire write_en;
assign write_en = sampling || cond_match;
dp_ram #(
.adr_width( adr_width ),
.dat_width( width )
) ram0 (
.clk_a( uart_clk ),
.adr_a( read_adr ),
.dat_a( read_dat ),
.clk_b( probe_clk ),
.adr_b( write_adr ),
.dat_b( probe_r ),
.we_b( write_en )
);
endmodule | module lac #(
parameter uart_freq_hz = 100000000,
parameter uart_baud = 115200,
parameter adr_width = 11,
parameter width = 8
) (
input reset,
input uart_clk,
input uart_rxd,
output uart_cts,
output uart_txd,
input uart_rts,
input probe_clk,
input [width-1:0] probe,
output reg [7:0] select
); |
parameter cmd_nop = 8'h20;
parameter cmd_arm = 8'h01;
parameter cmd_disarm = 8'h02;
assign uart_cts = 1;
reg tx_wr;
wire tx_busy;
reg [7:0] tx_data;
wire [7:0] rx_data;
wire rx_avail;
reg rx_ack;
uart #(
.freq_hz( uart_freq_hz ),
.baud( uart_baud )
) uart0 (
.reset( reset ),
.clk( uart_clk ),
.uart_txd( uart_txd ),
.uart_rxd( uart_rxd ),
.rx_data( rx_data ),
.rx_avail( rx_avail ),
.rx_error( rx_error ),
.rx_ack( rx_ack ),
.tx_data( tx_data ),
.tx_wr( tx_wr ),
.tx_busy( tx_busy )
);
reg [7:0] trig_mask;
reg [7:0] trig_cond;
reg [7:0] trig_pre;
reg [adr_width-1:0] start_adr;
reg armed;
reg triggered;
wire rx_req;
assign rx_req = rx_avail & ~rx_ack;
reg triggered_synced;
wire [width-1:0] read_dat;
reg [adr_width-1:0] read_adr;
wire [adr_width-1:0] read_adr_next;
assign read_adr_next = read_adr + 1;
reg [2:0] state;
parameter s_idle = 0;
parameter s_read_select= 1;
parameter s_read_mask = 2;
parameter s_read_comp = 3;
parameter s_read_pre = 4;
parameter s_triggered = 5;
parameter s_send_byte = 6;
always @(posedge uart_clk)
begin
if (reset) begin
state <= s_idle;
select <= 0;
armed <= 0;
tx_wr <= 0;
end else begin
triggered_synced <= triggered;
rx_ack <= 0;
tx_wr <= 0;
case (state)
s_idle: begin
if (rx_req) begin
case (rx_data)
cmd_arm: begin
rx_ack <= 1;
state <= s_read_select;
end
cmd_disarm: begin
rx_ack <= 1;
armed <= 0;
end
default: begin
rx_ack <= 1;
end
endcase
end
if (~rx_req && triggered_synced) begin
state <= s_triggered;
end
end
s_read_select: begin
if (rx_req) begin
rx_ack <= 1;
select <= rx_data;
state <= s_read_mask;
end
end
s_read_mask: begin
if (rx_req) begin
rx_ack <= 1;
trig_mask <= rx_data;
state <= s_read_comp;
end
end
s_read_comp: begin
if (rx_req) begin
rx_ack <= 1;
trig_cond <= rx_data;
armed <= 1;
state <= s_read_pre;
end
end
s_read_pre: begin
if (rx_req) begin
rx_ack <= 1;
trig_pre <= rx_data;
armed <= 1;
state <= s_idle;
end
end
s_triggered: begin
armed <= 0;
read_adr <= start_adr;
tx_data <= adr_width;
tx_wr <= 1;
state <= s_send_byte;
end
s_send_byte: begin
tx_wr <= 0;
if (~tx_busy & ~tx_wr) begin
if (read_adr_next == start_adr)
state <= s_idle;
read_adr <= read_adr_next;
tx_data <= read_dat;
tx_wr <= 1;
end
end
default:
state <= s_idle;
endcase
end
end
reg [width-1:0] probe_r;
always @(posedge probe_clk)
probe_r <= probe;
reg armed_synced;
reg armed_synced2;
reg sampling;
reg [adr_width-1:0] write_adr;
wire [adr_width-1:0] next_adr;
assign next_adr = write_adr + 1;
wire cond_match;
assign cond_match = (probe_r & trig_mask) == (trig_cond & trig_mask) && armed_synced2;
always @(posedge probe_clk)
begin
if (reset) begin
armed_synced <= 0;
armed_synced2 <= 0;
sampling <= 0;
triggered <= 0;
write_adr <= 0;
end else begin
armed_synced <= armed;
armed_synced2 <= armed_synced;
if (armed_synced2 || sampling) begin
write_adr <= next_adr;
end
if (~triggered && armed_synced2) begin
if (cond_match) begin
sampling <= 1;
triggered <= 1;
start_adr <= write_adr;
end
end
if (sampling && next_adr == start_adr) begin
sampling <= 0;
end
if (~sampling && ~armed_synced2 && triggered)
triggered <= 0;
end
end
wire write_en;
assign write_en = sampling || cond_match;
dp_ram #(
.adr_width( adr_width ),
.dat_width( width )
) ram0 (
.clk_a( uart_clk ),
.adr_a( read_adr ),
.dat_a( read_dat ),
.clk_b( probe_clk ),
.adr_b( write_adr ),
.dat_b( probe_r ),
.we_b( write_en )
);
endmodule | 1 |
Subsets and Splits