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138,945 | data/full_repos/permissive/86540631/MUX/mux_testbench.v | 86,540,631 | mux_testbench.v | v | 29 | 56 | [] | [] | [] | null | line:26: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86540631/MUX/mux_testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86540631/MUX/mux_testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86540631/MUX/mux_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86540631/MUX/mux_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86540631/MUX/mux_testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Error: data/full_repos/permissive/86540631/MUX/mux_testbench.v:9: Cannot find file containing module: \'mux_structural\'\n mux_structural U0(out, in0, in1, in2, in3, sel); \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86540631/MUX,data/full_repos/permissive/86540631/mux_structural\n data/full_repos/permissive/86540631/MUX,data/full_repos/permissive/86540631/mux_structural.v\n data/full_repos/permissive/86540631/MUX,data/full_repos/permissive/86540631/mux_structural.sv\n mux_structural\n mux_structural.v\n mux_structural.sv\n obj_dir/mux_structural\n obj_dir/mux_structural.v\n obj_dir/mux_structural.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,081 | module | module test_mux;
reg in0;
reg in1;
reg in2;
reg in3;
reg [1:0] sel;
wire out;
mux_structural U0(out, in0, in1, in2, in3, sel);
initial begin
#100
sel = 2'b00;
in0 = 1'b1; in1 = 1'b0; in2 = 1'b0; in3 = 1'b0;
#100
sel = 2'b01;
in0 = 1'b0; in1 = 1'b1; in2 = 1'b0; in3 = 1'b0;
#100
sel = 2'b10;
in0 = 1'b0; in1 = 1'b0; in2 = 1'b0; in3 = 1'b1;
#100
sel = 2'b11;
in0 = 1'b0; in1 = 1'b0; in2 = 1'b0; in3 = 1'b1;
#100
$finish;
end
endmodule | module test_mux; |
reg in0;
reg in1;
reg in2;
reg in3;
reg [1:0] sel;
wire out;
mux_structural U0(out, in0, in1, in2, in3, sel);
initial begin
#100
sel = 2'b00;
in0 = 1'b1; in1 = 1'b0; in2 = 1'b0; in3 = 1'b0;
#100
sel = 2'b01;
in0 = 1'b0; in1 = 1'b1; in2 = 1'b0; in3 = 1'b0;
#100
sel = 2'b10;
in0 = 1'b0; in1 = 1'b0; in2 = 1'b0; in3 = 1'b1;
#100
sel = 2'b11;
in0 = 1'b0; in1 = 1'b0; in2 = 1'b0; in3 = 1'b1;
#100
$finish;
end
endmodule | 1 |
138,946 | data/full_repos/permissive/86540631/SAD Matching/Accelerator_Top.v | 86,540,631 | Accelerator_Top.v | v | 25 | 62 | [] | [] | [] | [(1, 25)] | null | null | 1: b'%Error: Cannot find file containing module: Matching,data/full_repos/permissive/86540631\n ... Looked in:\n data/full_repos/permissive/86540631/SAD/Matching,data/full_repos/permissive/86540631\n data/full_repos/permissive/86540631/SAD/Matching,data/full_repos/permissive/86540631.v\n data/full_repos/permissive/86540631/SAD/Matching,data/full_repos/permissive/86540631.sv\n Matching,data/full_repos/permissive/86540631\n Matching,data/full_repos/permissive/86540631.v\n Matching,data/full_repos/permissive/86540631.sv\n obj_dir/Matching,data/full_repos/permissive/86540631\n obj_dir/Matching,data/full_repos/permissive/86540631.v\n obj_dir/Matching,data/full_repos/permissive/86540631.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86540631/SAD\n%Error: Cannot find file containing module: Matching/Accelerator_Top.v\n%Error: Exiting due to 3 error(s)\n' | 304,084 | module | module Accelerator_Top (clock, nReset, position, isMatching);
input clock;
input nReset;
output [239:0] position;
output isMatching;
wire [14:0] outAddr;
wire [7:0] outPixel;
FAST9_Top fast9(
.clock(clock),
.nReset(nReset),
.refAddr(outAddr),
.outPixel(outPixel)
);
Mat_Top matching(
.clock(clock),
.nReset(nReset),
.refAddr(outAddr),
.isFeature(outPixel),
.position(position),
.isMatching(isMatching)
);
endmodule | module Accelerator_Top (clock, nReset, position, isMatching); |
input clock;
input nReset;
output [239:0] position;
output isMatching;
wire [14:0] outAddr;
wire [7:0] outPixel;
FAST9_Top fast9(
.clock(clock),
.nReset(nReset),
.refAddr(outAddr),
.outPixel(outPixel)
);
Mat_Top matching(
.clock(clock),
.nReset(nReset),
.refAddr(outAddr),
.isFeature(outPixel),
.position(position),
.isMatching(isMatching)
);
endmodule | 1 |
138,947 | data/full_repos/permissive/86540631/SAD Matching/Addr_Reg.v | 86,540,631 | Addr_Reg.v | v | 102 | 106 | [] | [] | [] | [(1, 102)] | null | null | 1: b'%Error: Cannot find file containing module: Matching,data/full_repos/permissive/86540631\n ... Looked in:\n data/full_repos/permissive/86540631/SAD/Matching,data/full_repos/permissive/86540631\n data/full_repos/permissive/86540631/SAD/Matching,data/full_repos/permissive/86540631.v\n data/full_repos/permissive/86540631/SAD/Matching,data/full_repos/permissive/86540631.sv\n Matching,data/full_repos/permissive/86540631\n Matching,data/full_repos/permissive/86540631.v\n Matching,data/full_repos/permissive/86540631.sv\n obj_dir/Matching,data/full_repos/permissive/86540631\n obj_dir/Matching,data/full_repos/permissive/86540631.v\n obj_dir/Matching,data/full_repos/permissive/86540631.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86540631/SAD\n%Error: Cannot find file containing module: Matching/Addr_Reg.v\n%Error: Exiting due to 3 error(s)\n' | 304,085 | module | module Addr_Reg (refAddr, posAddr, posReaden, position, isMatching);
input [14:0] refAddr;
input [3:0] posAddr;
input posReaden;
output [239:0] position;
output isMatching;
reg [14:0] r1, r2, r3, r4, r5, r6, r7, r8, r9;
reg [14:0] r10, r11, r12, r13, r14, r15, r16;
wire [15:0] decoder;
assign decoder =
(posAddr == 4'd0) ? 16'd1 :
(posAddr == 4'd1) ? 16'd2 :
(posAddr == 4'd2) ? 16'd4 :
(posAddr == 4'd3) ? 16'd8 :
(posAddr == 4'd4) ? 16'd16 :
(posAddr == 4'd5) ? 16'd32 :
(posAddr == 4'd6) ? 16'd64 :
(posAddr == 4'd7) ? 16'd128 :
(posAddr == 4'd8) ? 16'd256 :
(posAddr == 4'd9) ? 16'd512 :
(posAddr == 4'd10) ? 16'd1024 :
(posAddr == 4'd11) ? 16'd2048 :
(posAddr == 4'd12) ? 16'd4096 :
(posAddr == 4'd13) ? 16'd8192 :
(posAddr == 4'd14) ? 16'd16384 :
(posAddr == 4'd15) ? 16'd32768 : 4'bx;
always @(posAddr)
if (decoder[0])
r1 <= refAddr;
always @(posAddr)
if (decoder[1])
r2 <= refAddr;
always @(posAddr)
if (decoder[2])
r3 <= refAddr;
always @(posAddr)
if (decoder[3])
r4 <= refAddr;
always @(posAddr)
if (decoder[4])
r5 <= refAddr;
always @(posAddr)
if (decoder[5])
r6 <= refAddr;
always @(posAddr)
if (decoder[6])
r7 <= refAddr;
always @(posAddr)
if (decoder[7])
r8 <= refAddr;
always @(posAddr)
if (decoder[8])
r9 <= refAddr;
always @(posAddr)
if (decoder[9])
r10 <= refAddr;
always @(posAddr)
if (decoder[10])
r11 <= refAddr;
always @(posAddr)
if (decoder[11])
r12 <= refAddr;
always @(posAddr)
if (decoder[12])
r13 <= refAddr;
always @(posAddr)
if (decoder[13])
r14 <= refAddr;
always @(posAddr)
if (decoder[14])
r15 <= refAddr;
always @(posAddr)
if (decoder[15])
r16 <= refAddr;
assign position =
(posReaden == 1'b1) ? {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, r16} : 240'bx;
assign isMatching = (posReaden == 1'b1) ? 1'b1 : 1'b0;
endmodule | module Addr_Reg (refAddr, posAddr, posReaden, position, isMatching); |
input [14:0] refAddr;
input [3:0] posAddr;
input posReaden;
output [239:0] position;
output isMatching;
reg [14:0] r1, r2, r3, r4, r5, r6, r7, r8, r9;
reg [14:0] r10, r11, r12, r13, r14, r15, r16;
wire [15:0] decoder;
assign decoder =
(posAddr == 4'd0) ? 16'd1 :
(posAddr == 4'd1) ? 16'd2 :
(posAddr == 4'd2) ? 16'd4 :
(posAddr == 4'd3) ? 16'd8 :
(posAddr == 4'd4) ? 16'd16 :
(posAddr == 4'd5) ? 16'd32 :
(posAddr == 4'd6) ? 16'd64 :
(posAddr == 4'd7) ? 16'd128 :
(posAddr == 4'd8) ? 16'd256 :
(posAddr == 4'd9) ? 16'd512 :
(posAddr == 4'd10) ? 16'd1024 :
(posAddr == 4'd11) ? 16'd2048 :
(posAddr == 4'd12) ? 16'd4096 :
(posAddr == 4'd13) ? 16'd8192 :
(posAddr == 4'd14) ? 16'd16384 :
(posAddr == 4'd15) ? 16'd32768 : 4'bx;
always @(posAddr)
if (decoder[0])
r1 <= refAddr;
always @(posAddr)
if (decoder[1])
r2 <= refAddr;
always @(posAddr)
if (decoder[2])
r3 <= refAddr;
always @(posAddr)
if (decoder[3])
r4 <= refAddr;
always @(posAddr)
if (decoder[4])
r5 <= refAddr;
always @(posAddr)
if (decoder[5])
r6 <= refAddr;
always @(posAddr)
if (decoder[6])
r7 <= refAddr;
always @(posAddr)
if (decoder[7])
r8 <= refAddr;
always @(posAddr)
if (decoder[8])
r9 <= refAddr;
always @(posAddr)
if (decoder[9])
r10 <= refAddr;
always @(posAddr)
if (decoder[10])
r11 <= refAddr;
always @(posAddr)
if (decoder[11])
r12 <= refAddr;
always @(posAddr)
if (decoder[12])
r13 <= refAddr;
always @(posAddr)
if (decoder[13])
r14 <= refAddr;
always @(posAddr)
if (decoder[14])
r15 <= refAddr;
always @(posAddr)
if (decoder[15])
r16 <= refAddr;
assign position =
(posReaden == 1'b1) ? {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, r16} : 240'bx;
assign isMatching = (posReaden == 1'b1) ? 1'b1 : 1'b0;
endmodule | 1 |
138,952 | data/full_repos/permissive/86540631/SAD Matching/Mat_Datapath.v | 86,540,631 | Mat_Datapath.v | v | 61 | 57 | [] | [] | [] | [(1, 61)] | null | null | 1: b'%Error: Cannot find file containing module: Matching,data/full_repos/permissive/86540631\n ... Looked in:\n data/full_repos/permissive/86540631/SAD/Matching,data/full_repos/permissive/86540631\n data/full_repos/permissive/86540631/SAD/Matching,data/full_repos/permissive/86540631.v\n data/full_repos/permissive/86540631/SAD/Matching,data/full_repos/permissive/86540631.sv\n Matching,data/full_repos/permissive/86540631\n Matching,data/full_repos/permissive/86540631.v\n Matching,data/full_repos/permissive/86540631.sv\n obj_dir/Matching,data/full_repos/permissive/86540631\n obj_dir/Matching,data/full_repos/permissive/86540631.v\n obj_dir/Matching,data/full_repos/permissive/86540631.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/86540631/SAD\n%Error: Cannot find file containing module: Matching/Mat_Datapath.v\n%Error: Exiting due to 3 error(s)\n' | 304,091 | module | module Mat_Datapath (adjFBPixel, dbValue, matPoint);
input [63:0] adjFBPixel;
input [287:0] dbValue;
output matPoint;
wire [7:0] refAvg;
wire [7:0] threshold;
assign threshold = 8'd30;
assign refAvg =
(adjFBPixel[7:0] +
adjFBPixel[15:8] +
adjFBPixel[23:16] +
adjFBPixel[31:24] +
adjFBPixel[39:32] +
adjFBPixel[47:40] +
adjFBPixel[55:48] +
adjFBPixel[63:56]) / 8;
assign matPoint =
(dbValue[7:0] - refAvg < threshold) ? 1'b1 :
(dbValue[15:8] - refAvg < threshold) ? 1'b1 :
(dbValue[23:16] - refAvg < threshold) ? 1'b1 :
(dbValue[31:24] - refAvg < threshold) ? 1'b1 :
(dbValue[39:32] - refAvg < threshold) ? 1'b1 :
(dbValue[47:40] - refAvg < threshold) ? 1'b1 :
(dbValue[55:48] - refAvg < threshold) ? 1'b1 :
(dbValue[63:56] - refAvg < threshold) ? 1'b1 :
(dbValue[71:64] - refAvg < threshold) ? 1'b1 :
(dbValue[79:72] - refAvg < threshold) ? 1'b1 :
(dbValue[87:80] - refAvg < threshold) ? 1'b1 :
(dbValue[95:88] - refAvg < threshold) ? 1'b1 :
(dbValue[103:96] - refAvg < threshold) ? 1'b1 :
(dbValue[111:104] - refAvg < threshold) ? 1'b1 :
(dbValue[119:112] - refAvg < threshold) ? 1'b1 :
(dbValue[127:120] - refAvg < threshold) ? 1'b1 :
(dbValue[135:128] - refAvg < threshold) ? 1'b1 :
(dbValue[143:136] - refAvg < threshold) ? 1'b1 :
(dbValue[151:144] - refAvg < threshold) ? 1'b1 :
(dbValue[159:152] - refAvg < threshold) ? 1'b1 :
(dbValue[167:160] - refAvg < threshold) ? 1'b1 :
(dbValue[175:168] - refAvg < threshold) ? 1'b1 :
(dbValue[183:176] - refAvg < threshold) ? 1'b1 :
(dbValue[191:184] - refAvg < threshold) ? 1'b1 :
(dbValue[199:192] - refAvg < threshold) ? 1'b1 :
(dbValue[207:200] - refAvg < threshold) ? 1'b1 :
(dbValue[215:208] - refAvg < threshold) ? 1'b1 :
(dbValue[223:216] - refAvg < threshold) ? 1'b1 :
(dbValue[231:224] - refAvg < threshold) ? 1'b1 :
(dbValue[239:232] - refAvg < threshold) ? 1'b1 :
(dbValue[247:240] - refAvg < threshold) ? 1'b1 :
(dbValue[255:248] - refAvg < threshold) ? 1'b1 :
(dbValue[263:256] - refAvg < threshold) ? 1'b1 :
(dbValue[271:264] - refAvg < threshold) ? 1'b1 :
(dbValue[279:272] - refAvg < threshold) ? 1'b1 :
(dbValue[287:280] - refAvg < threshold) ? 1'b1 : 1'b0;
endmodule | module Mat_Datapath (adjFBPixel, dbValue, matPoint); |
input [63:0] adjFBPixel;
input [287:0] dbValue;
output matPoint;
wire [7:0] refAvg;
wire [7:0] threshold;
assign threshold = 8'd30;
assign refAvg =
(adjFBPixel[7:0] +
adjFBPixel[15:8] +
adjFBPixel[23:16] +
adjFBPixel[31:24] +
adjFBPixel[39:32] +
adjFBPixel[47:40] +
adjFBPixel[55:48] +
adjFBPixel[63:56]) / 8;
assign matPoint =
(dbValue[7:0] - refAvg < threshold) ? 1'b1 :
(dbValue[15:8] - refAvg < threshold) ? 1'b1 :
(dbValue[23:16] - refAvg < threshold) ? 1'b1 :
(dbValue[31:24] - refAvg < threshold) ? 1'b1 :
(dbValue[39:32] - refAvg < threshold) ? 1'b1 :
(dbValue[47:40] - refAvg < threshold) ? 1'b1 :
(dbValue[55:48] - refAvg < threshold) ? 1'b1 :
(dbValue[63:56] - refAvg < threshold) ? 1'b1 :
(dbValue[71:64] - refAvg < threshold) ? 1'b1 :
(dbValue[79:72] - refAvg < threshold) ? 1'b1 :
(dbValue[87:80] - refAvg < threshold) ? 1'b1 :
(dbValue[95:88] - refAvg < threshold) ? 1'b1 :
(dbValue[103:96] - refAvg < threshold) ? 1'b1 :
(dbValue[111:104] - refAvg < threshold) ? 1'b1 :
(dbValue[119:112] - refAvg < threshold) ? 1'b1 :
(dbValue[127:120] - refAvg < threshold) ? 1'b1 :
(dbValue[135:128] - refAvg < threshold) ? 1'b1 :
(dbValue[143:136] - refAvg < threshold) ? 1'b1 :
(dbValue[151:144] - refAvg < threshold) ? 1'b1 :
(dbValue[159:152] - refAvg < threshold) ? 1'b1 :
(dbValue[167:160] - refAvg < threshold) ? 1'b1 :
(dbValue[175:168] - refAvg < threshold) ? 1'b1 :
(dbValue[183:176] - refAvg < threshold) ? 1'b1 :
(dbValue[191:184] - refAvg < threshold) ? 1'b1 :
(dbValue[199:192] - refAvg < threshold) ? 1'b1 :
(dbValue[207:200] - refAvg < threshold) ? 1'b1 :
(dbValue[215:208] - refAvg < threshold) ? 1'b1 :
(dbValue[223:216] - refAvg < threshold) ? 1'b1 :
(dbValue[231:224] - refAvg < threshold) ? 1'b1 :
(dbValue[239:232] - refAvg < threshold) ? 1'b1 :
(dbValue[247:240] - refAvg < threshold) ? 1'b1 :
(dbValue[255:248] - refAvg < threshold) ? 1'b1 :
(dbValue[263:256] - refAvg < threshold) ? 1'b1 :
(dbValue[271:264] - refAvg < threshold) ? 1'b1 :
(dbValue[279:272] - refAvg < threshold) ? 1'b1 :
(dbValue[287:280] - refAvg < threshold) ? 1'b1 : 1'b0;
endmodule | 1 |
138,955 | data/full_repos/permissive/86541458/QRSolver_Parametric.v | 86,541,458 | QRSolver_Parametric.v | v | 417 | 83 | [] | [] | [] | [(23, 416)] | null | null | 1: b'%Error: data/full_repos/permissive/86541458/QRSolver_Parametric.v:123: Cannot find file containing module: \'GivensCordicQR_Parametric\'\nGivensCordicQR_Parametric\n^~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86541458,data/full_repos/permissive/86541458/GivensCordicQR_Parametric\n data/full_repos/permissive/86541458,data/full_repos/permissive/86541458/GivensCordicQR_Parametric.v\n data/full_repos/permissive/86541458,data/full_repos/permissive/86541458/GivensCordicQR_Parametric.sv\n GivensCordicQR_Parametric\n GivensCordicQR_Parametric.v\n GivensCordicQR_Parametric.sv\n obj_dir/GivensCordicQR_Parametric\n obj_dir/GivensCordicQR_Parametric.v\n obj_dir/GivensCordicQR_Parametric.sv\n%Error: data/full_repos/permissive/86541458/QRSolver_Parametric.v:149: Cannot find file containing module: \'KnMultiplierCore_Parametric\'\n KnMultiplierCore_Parametric\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:332: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputMatrix[addrIndex] <= inputRowR;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:333: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n matrixQ[addrIndex] <= inputColumnQ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:336: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputX <= inputMatrix[row];\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:337: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputY <= inputMatrix[column];\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:338: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputU <= matrixQ[row];\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:339: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputV <= matrixQ[column];\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:343: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputX <= inputMatrix[row];\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:344: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputY <= inputMatrix[column];\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:345: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputU <= matrixQ[row];\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:346: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputV <= matrixQ[column];\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:362: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputMatrix[row] <= mulOutputX;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:363: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputMatrix[column] <= mulOutputY;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:364: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n matrixQ[row] <= mulOutputU;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:365: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n matrixQ[column] <= mulOutputV;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:390: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n outputRowR <= inputMatrix[rd_addr]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:391: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n outputColumnQ <= matrixQ[rd_addr];\n ^\n%Error: Exiting due to 2 error(s), 16 warning(s)\n' | 304,095 | module | module QRSolver_Parametric
#(parameter intLenIn = 5,
fracLenIn = 19,
intLenOut = 5,
fracLenOut = 19,
noIteration = 10,
matrixSize = 4,
KnInt = 1,
KnFrac = 15,
addrWidthKnLUT = 4)
(input clk,nRst,
input inputValid,
input [KnInt+KnFrac-1:0] valueKn,
input [matrixSize*(intLenIn + fracLenIn) - 1 :0] inputRowR,
input [matrixSize*(intLenIn + fracLenIn) - 1 :0] inputColumnQ,
output reg qrCoreStarted,
output transferValid,
output reg qrDecompDone,
output reg [matrixSize*(intLenIn + fracLenIn) - 1 :0] outputRowR,
output reg [matrixSize*(intLenIn + fracLenIn) - 1 :0] outputColumnQ);
localparam stateBitWidth = 3;
localparam addrWidth = clogb2(matrixSize);
reg [addrWidth-1:0] rd_addr;
reg [addrWidth-1:0] row;
reg [addrWidth-1:0] column;
reg [addrWidth-1:0] addrIndex;
reg [stateBitWidth - 1:0] state;
localparam storeData = 0 ;
localparam getData = 1 ;
localparam processData = 2;
localparam scaledData = 3;
localparam putData = 4;
localparam dataTransfer = 5;
reg startQRDecomp;
reg dataValid;
reg processStarted;
reg transferStarted;
reg transferFinished;
reg [1:0] waitFor3Clockcycle;
reg [addrWidthKnLUT-1:0] addr;
reg [matrixSize-1:0] disableCore;
reg [matrixSize-1:0] signDictator;
reg signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] inputX;
reg signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] inputY;
reg signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] inputU;
reg signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] inputV;
reg inputValid_Kn;
reg signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] mulInputX;
reg signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] mulInputY;
reg signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] mulInputU;
reg signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] mulInputV;
wire processDone;
wire signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] outputX;
wire signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] outputY;
wire signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] outputU;
wire signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] outputV;
wire outValid_Kn;
wire signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] mulOutputX;
wire signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] mulOutputY;
wire signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] mulOutputU;
wire signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] mulOutputV;
reg [matrixSize*(intLenIn + fracLenIn) - 1 :0] inputMatrix [0:matrixSize-1];
reg [matrixSize*(intLenIn + fracLenIn) - 1 :0] matrixQ [0:matrixSize-1];
GivensCordicQR_Parametric
#(.intLenIn(intLenIn),
.fracLenIn(fracLenIn),
.intLenOut(intLenOut),
.fracLenOut(fracLenOut),
.noIteration(noIteration),
.matrixSize(matrixSize))
GivensCordicQRCore00
(.clk(clk),
.nRst(nRst),
.disableCore(disableCore),
.dataValid(dataValid),
.signDictator(signDictator),
.inputVectorX(inputX),
.inputVectorY(inputY),
.inputVectorU(inputU),
.inputVectorV(inputV),
.processDone(processDone),
.outputVectorX(outputX),
.outputVectorY(outputY),
.outputVectorU(outputU),
.outputVectorV(outputV));
KnMultiplierCore_Parametric
#(.intLen(intLenIn),
.fracLen(fracLenIn),
.noIteration(noIteration),
.matrixSize(matrixSize),
.KnInt(KnInt),
.KnFrac(KnFrac))
KnMultiplierCore00
(.clk(clk),
.nRst(nRst),
.inputValid(inputValid_Kn),
.valueKn(valueKn),
.inputX(mulInputX),
.inputY(mulInputY),
.inputU(mulInputU),
.inputV(mulInputV),
.outValid(outValid_Kn),
.outputX(mulOutputX),
.outputY(mulOutputY),
.outputU(mulOutputU),
.outputV(mulOutputV));
assign transferValid = transferStarted;
always @(posedge clk) begin
if (!nRst) begin
dataValid <= 1'b0;
processStarted <= 1'b0;
qrDecompDone <= 1'b0;
disableCore <= {(matrixSize){1'b0}};
waitFor3Clockcycle <= 2'b00;
row <= {(addrWidth){1'b0}};
column <= {{(addrWidth-1){1'b0}}, 1'b1};
rd_addr <= 0;
qrCoreStarted <= 1'b0;
startQRDecomp <= 1'b0;
signDictator <= {(matrixSize){1'b0}};
addrIndex <= 0;
inputValid_Kn <= 1'b0;
state <= storeData;
end
else begin
case (state)
storeData: begin :putInputInMemory
transferFinished <= 1'b0;
qrDecompDone <= 1'b0;
if (addrIndex < matrixSize) begin
if (inputValid && !startQRDecomp) begin
qrCoreStarted <= 1'b1;
addrIndex <= addrIndex + 1'b1;
end
state <= storeData;
end
else begin
addrIndex <= 0;
startQRDecomp <= 1'b1;
state <= getData;
end
end
getData: begin :fetchInput
if (startQRDecomp && !processStarted) begin
dataValid <= 1'b1;
processStarted <= 1'b1;
disableCore <= {(matrixSize){1'b0}};
signDictator <= {{(matrixSize-1){1'b0}},1'b1};
startQRDecomp <= 1'b0;
state <= processData;
end
else if (processStarted && !startQRDecomp) begin
if (row < matrixSize-1) begin
dataValid <= 1'b1;
addr <= 4'b0000;
state <= processData;
end
else begin
dataValid <= 1'b0;
processStarted <= 1'b0;
disableCore <= {(matrixSize){1'b0}};
signDictator <= {{(matrixSize-1){1'b0}},1'b1};
row <= {(addrWidth){1'b0}};
column <= {{(addrWidth-1){1'b0}}, 1'b1};
state <= dataTransfer;
end
end
else begin
dataValid <= 1'b0;
qrDecompDone <= 1'b0;
row <= {(addrWidth){1'b0}};
column <= {{(addrWidth-1){1'b0}}, 1'b1};
state <= getData;
qrDecompDone <= qrDecompDone;
transferFinished <= 1'b0;
end
end
processData: begin: processingInput
if (!processDone) begin
dataValid <= 0;
state <= processData;
end
else begin
state <= scaledData;
end
end
scaledData: begin: scalingOfOutput
if (!inputValid_Kn) begin
inputValid_Kn <= 1'b1;
end
else begin
state <= putData;
inputValid_Kn <= 1'b0;
end
end
putData: begin :putOutput
if (outValid_Kn) begin
if (column == matrixSize-1) begin
disableCore <= (disableCore << 1) + 1'b1;
signDictator <= signDictator << 1;
row <= row + 1'b1;
column <= row + 2'b10;
end
else begin
column <= column+1;
end
state <= getData;
end
else begin
state <= putData;
end
end
dataTransfer : begin
if (rd_addr < matrixSize) begin
rd_addr <= rd_addr + 1'b1;
state <= dataTransfer;
end
else begin
state <= storeData;
rd_addr <= 0;
qrDecompDone <= 1'b1;
transferFinished <= 1'b1;
qrCoreStarted <= 1'b0;
end
end
default : state <= storeData;
endcase
end
end
always @(posedge clk) begin
if (~nRst) begin
inputX <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
inputY <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
inputU <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
inputV <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
end
else begin
if (state == storeData && inputValid) begin
inputMatrix[addrIndex] <= inputRowR;
matrixQ[addrIndex] <= inputColumnQ;
end
else if (state == getData && startQRDecomp) begin
inputX <= inputMatrix[row];
inputY <= inputMatrix[column];
inputU <= matrixQ[row];
inputV <= matrixQ[column];
end
else if (state == getData && processStarted) begin
if (column < matrixSize) begin
inputX <= inputMatrix[row];
inputY <= inputMatrix[column];
inputU <= matrixQ[row];
inputV <= matrixQ[column];
end
else begin
inputX <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
inputY <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
inputU <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
inputV <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
end
end
else if (state == scaledData) begin
mulInputX <= outputX;
mulInputY <= outputY;
mulInputU <= outputU;
mulInputV <= outputV;
end
else if (state == putData && outValid_Kn) begin
inputMatrix[row] <= mulOutputX;
inputMatrix[column] <= mulOutputY;
matrixQ[row] <= mulOutputU;
matrixQ[column] <= mulOutputV;
end
else begin
inputX <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
inputY <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
inputU <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
inputV <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
mulInputX <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
mulInputY <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
mulInputU <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
mulInputV <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
end
end
end
always @(posedge clk) begin
if (~nRst) begin
outputRowR <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
outputColumnQ <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
transferStarted <= 1'b0;
end
else begin
if (state == dataTransfer) begin
if (rd_addr < matrixSize) begin
transferStarted <= 1'b1;
outputRowR <= inputMatrix[rd_addr];
outputColumnQ <= matrixQ[rd_addr];
end
else begin
transferStarted <= 1'b0;
outputRowR <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
outputColumnQ <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
end
end
else begin
transferStarted <= transferStarted;
outputRowR <= outputRowR;
outputColumnQ <= outputColumnQ;
end
end
end
function integer clogb2;
input [31:0] value;
begin
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin
value = value >> 1;
end
end
endfunction
endmodule | module QRSolver_Parametric
#(parameter intLenIn = 5,
fracLenIn = 19,
intLenOut = 5,
fracLenOut = 19,
noIteration = 10,
matrixSize = 4,
KnInt = 1,
KnFrac = 15,
addrWidthKnLUT = 4)
(input clk,nRst,
input inputValid,
input [KnInt+KnFrac-1:0] valueKn,
input [matrixSize*(intLenIn + fracLenIn) - 1 :0] inputRowR,
input [matrixSize*(intLenIn + fracLenIn) - 1 :0] inputColumnQ,
output reg qrCoreStarted,
output transferValid,
output reg qrDecompDone,
output reg [matrixSize*(intLenIn + fracLenIn) - 1 :0] outputRowR,
output reg [matrixSize*(intLenIn + fracLenIn) - 1 :0] outputColumnQ); |
localparam stateBitWidth = 3;
localparam addrWidth = clogb2(matrixSize);
reg [addrWidth-1:0] rd_addr;
reg [addrWidth-1:0] row;
reg [addrWidth-1:0] column;
reg [addrWidth-1:0] addrIndex;
reg [stateBitWidth - 1:0] state;
localparam storeData = 0 ;
localparam getData = 1 ;
localparam processData = 2;
localparam scaledData = 3;
localparam putData = 4;
localparam dataTransfer = 5;
reg startQRDecomp;
reg dataValid;
reg processStarted;
reg transferStarted;
reg transferFinished;
reg [1:0] waitFor3Clockcycle;
reg [addrWidthKnLUT-1:0] addr;
reg [matrixSize-1:0] disableCore;
reg [matrixSize-1:0] signDictator;
reg signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] inputX;
reg signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] inputY;
reg signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] inputU;
reg signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] inputV;
reg inputValid_Kn;
reg signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] mulInputX;
reg signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] mulInputY;
reg signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] mulInputU;
reg signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] mulInputV;
wire processDone;
wire signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] outputX;
wire signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] outputY;
wire signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] outputU;
wire signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] outputV;
wire outValid_Kn;
wire signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] mulOutputX;
wire signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] mulOutputY;
wire signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] mulOutputU;
wire signed [matrixSize*(intLenIn + fracLenIn) - 1 :0] mulOutputV;
reg [matrixSize*(intLenIn + fracLenIn) - 1 :0] inputMatrix [0:matrixSize-1];
reg [matrixSize*(intLenIn + fracLenIn) - 1 :0] matrixQ [0:matrixSize-1];
GivensCordicQR_Parametric
#(.intLenIn(intLenIn),
.fracLenIn(fracLenIn),
.intLenOut(intLenOut),
.fracLenOut(fracLenOut),
.noIteration(noIteration),
.matrixSize(matrixSize))
GivensCordicQRCore00
(.clk(clk),
.nRst(nRst),
.disableCore(disableCore),
.dataValid(dataValid),
.signDictator(signDictator),
.inputVectorX(inputX),
.inputVectorY(inputY),
.inputVectorU(inputU),
.inputVectorV(inputV),
.processDone(processDone),
.outputVectorX(outputX),
.outputVectorY(outputY),
.outputVectorU(outputU),
.outputVectorV(outputV));
KnMultiplierCore_Parametric
#(.intLen(intLenIn),
.fracLen(fracLenIn),
.noIteration(noIteration),
.matrixSize(matrixSize),
.KnInt(KnInt),
.KnFrac(KnFrac))
KnMultiplierCore00
(.clk(clk),
.nRst(nRst),
.inputValid(inputValid_Kn),
.valueKn(valueKn),
.inputX(mulInputX),
.inputY(mulInputY),
.inputU(mulInputU),
.inputV(mulInputV),
.outValid(outValid_Kn),
.outputX(mulOutputX),
.outputY(mulOutputY),
.outputU(mulOutputU),
.outputV(mulOutputV));
assign transferValid = transferStarted;
always @(posedge clk) begin
if (!nRst) begin
dataValid <= 1'b0;
processStarted <= 1'b0;
qrDecompDone <= 1'b0;
disableCore <= {(matrixSize){1'b0}};
waitFor3Clockcycle <= 2'b00;
row <= {(addrWidth){1'b0}};
column <= {{(addrWidth-1){1'b0}}, 1'b1};
rd_addr <= 0;
qrCoreStarted <= 1'b0;
startQRDecomp <= 1'b0;
signDictator <= {(matrixSize){1'b0}};
addrIndex <= 0;
inputValid_Kn <= 1'b0;
state <= storeData;
end
else begin
case (state)
storeData: begin :putInputInMemory
transferFinished <= 1'b0;
qrDecompDone <= 1'b0;
if (addrIndex < matrixSize) begin
if (inputValid && !startQRDecomp) begin
qrCoreStarted <= 1'b1;
addrIndex <= addrIndex + 1'b1;
end
state <= storeData;
end
else begin
addrIndex <= 0;
startQRDecomp <= 1'b1;
state <= getData;
end
end
getData: begin :fetchInput
if (startQRDecomp && !processStarted) begin
dataValid <= 1'b1;
processStarted <= 1'b1;
disableCore <= {(matrixSize){1'b0}};
signDictator <= {{(matrixSize-1){1'b0}},1'b1};
startQRDecomp <= 1'b0;
state <= processData;
end
else if (processStarted && !startQRDecomp) begin
if (row < matrixSize-1) begin
dataValid <= 1'b1;
addr <= 4'b0000;
state <= processData;
end
else begin
dataValid <= 1'b0;
processStarted <= 1'b0;
disableCore <= {(matrixSize){1'b0}};
signDictator <= {{(matrixSize-1){1'b0}},1'b1};
row <= {(addrWidth){1'b0}};
column <= {{(addrWidth-1){1'b0}}, 1'b1};
state <= dataTransfer;
end
end
else begin
dataValid <= 1'b0;
qrDecompDone <= 1'b0;
row <= {(addrWidth){1'b0}};
column <= {{(addrWidth-1){1'b0}}, 1'b1};
state <= getData;
qrDecompDone <= qrDecompDone;
transferFinished <= 1'b0;
end
end
processData: begin: processingInput
if (!processDone) begin
dataValid <= 0;
state <= processData;
end
else begin
state <= scaledData;
end
end
scaledData: begin: scalingOfOutput
if (!inputValid_Kn) begin
inputValid_Kn <= 1'b1;
end
else begin
state <= putData;
inputValid_Kn <= 1'b0;
end
end
putData: begin :putOutput
if (outValid_Kn) begin
if (column == matrixSize-1) begin
disableCore <= (disableCore << 1) + 1'b1;
signDictator <= signDictator << 1;
row <= row + 1'b1;
column <= row + 2'b10;
end
else begin
column <= column+1;
end
state <= getData;
end
else begin
state <= putData;
end
end
dataTransfer : begin
if (rd_addr < matrixSize) begin
rd_addr <= rd_addr + 1'b1;
state <= dataTransfer;
end
else begin
state <= storeData;
rd_addr <= 0;
qrDecompDone <= 1'b1;
transferFinished <= 1'b1;
qrCoreStarted <= 1'b0;
end
end
default : state <= storeData;
endcase
end
end
always @(posedge clk) begin
if (~nRst) begin
inputX <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
inputY <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
inputU <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
inputV <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
end
else begin
if (state == storeData && inputValid) begin
inputMatrix[addrIndex] <= inputRowR;
matrixQ[addrIndex] <= inputColumnQ;
end
else if (state == getData && startQRDecomp) begin
inputX <= inputMatrix[row];
inputY <= inputMatrix[column];
inputU <= matrixQ[row];
inputV <= matrixQ[column];
end
else if (state == getData && processStarted) begin
if (column < matrixSize) begin
inputX <= inputMatrix[row];
inputY <= inputMatrix[column];
inputU <= matrixQ[row];
inputV <= matrixQ[column];
end
else begin
inputX <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
inputY <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
inputU <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
inputV <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
end
end
else if (state == scaledData) begin
mulInputX <= outputX;
mulInputY <= outputY;
mulInputU <= outputU;
mulInputV <= outputV;
end
else if (state == putData && outValid_Kn) begin
inputMatrix[row] <= mulOutputX;
inputMatrix[column] <= mulOutputY;
matrixQ[row] <= mulOutputU;
matrixQ[column] <= mulOutputV;
end
else begin
inputX <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
inputY <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
inputU <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
inputV <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
mulInputX <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
mulInputY <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
mulInputU <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
mulInputV <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
end
end
end
always @(posedge clk) begin
if (~nRst) begin
outputRowR <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
outputColumnQ <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
transferStarted <= 1'b0;
end
else begin
if (state == dataTransfer) begin
if (rd_addr < matrixSize) begin
transferStarted <= 1'b1;
outputRowR <= inputMatrix[rd_addr];
outputColumnQ <= matrixQ[rd_addr];
end
else begin
transferStarted <= 1'b0;
outputRowR <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
outputColumnQ <= {(matrixSize*(intLenIn + fracLenIn)){1'b0}};
end
end
else begin
transferStarted <= transferStarted;
outputRowR <= outputRowR;
outputColumnQ <= outputColumnQ;
end
end
end
function integer clogb2;
input [31:0] value;
begin
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin
value = value >> 1;
end
end
endfunction
endmodule | 1 |
138,956 | data/full_repos/permissive/86541458/QRSolver_Parametric.v | 86,541,458 | QRSolver_Parametric.v | v | 417 | 83 | [] | [] | [] | [(23, 416)] | null | null | 1: b'%Error: data/full_repos/permissive/86541458/QRSolver_Parametric.v:123: Cannot find file containing module: \'GivensCordicQR_Parametric\'\nGivensCordicQR_Parametric\n^~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86541458,data/full_repos/permissive/86541458/GivensCordicQR_Parametric\n data/full_repos/permissive/86541458,data/full_repos/permissive/86541458/GivensCordicQR_Parametric.v\n data/full_repos/permissive/86541458,data/full_repos/permissive/86541458/GivensCordicQR_Parametric.sv\n GivensCordicQR_Parametric\n GivensCordicQR_Parametric.v\n GivensCordicQR_Parametric.sv\n obj_dir/GivensCordicQR_Parametric\n obj_dir/GivensCordicQR_Parametric.v\n obj_dir/GivensCordicQR_Parametric.sv\n%Error: data/full_repos/permissive/86541458/QRSolver_Parametric.v:149: Cannot find file containing module: \'KnMultiplierCore_Parametric\'\n KnMultiplierCore_Parametric\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:332: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputMatrix[addrIndex] <= inputRowR;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:333: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n matrixQ[addrIndex] <= inputColumnQ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:336: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputX <= inputMatrix[row];\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:337: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputY <= inputMatrix[column];\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:338: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputU <= matrixQ[row];\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:339: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputV <= matrixQ[column];\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:343: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputX <= inputMatrix[row];\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:344: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputY <= inputMatrix[column];\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:345: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputU <= matrixQ[row];\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:346: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputV <= matrixQ[column];\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:362: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputMatrix[row] <= mulOutputX;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:363: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n inputMatrix[column] <= mulOutputY;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:364: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n matrixQ[row] <= mulOutputU;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:365: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n matrixQ[column] <= mulOutputV;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:390: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n outputRowR <= inputMatrix[rd_addr]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/86541458/QRSolver_Parametric.v:391: Bit extraction of array[3:0] requires 2 bit index, not 3 bits.\n : ... In instance QRSolver_Parametric\n outputColumnQ <= matrixQ[rd_addr];\n ^\n%Error: Exiting due to 2 error(s), 16 warning(s)\n' | 304,095 | function | function integer clogb2;
input [31:0] value;
begin
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin
value = value >> 1;
end
end
endfunction | function integer clogb2; |
input [31:0] value;
begin
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin
value = value >> 1;
end
end
endfunction | 1 |
138,957 | data/full_repos/permissive/86658573/project.v | 86,658,573 | project.v | v | 360 | 358 | [] | [] | [] | null | line:61: before: "." | null | 1: b'%Error: data/full_repos/permissive/86658573/project.v:214: syntax error, unexpected if, expecting \';\'\n if (height == 2\'b00) \n ^~\n%Error: data/full_repos/permissive/86658573/project.v:218: syntax error, unexpected else\n else\n ^~~~\n%Error: data/full_repos/permissive/86658573/project.v:254: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:266: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [7:0] x_init=8\'d2;\n ^~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:267: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [6:0] y_init = 7\'d80;\n ^~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:268: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [2:0] count = 3\'b000;\n ^~~~~\n%Error: data/full_repos/permissive/86658573/project.v:269: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [10:0] counter = 11\'b0;\n ^~~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:272: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [4:0] runner_count; = 5\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:273: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [2:0] runner_height = 3\'b0;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:276: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [159:0] local_draw;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:287: syntax error, unexpected else\n else begin\n ^~~~\n%Error: data/full_repos/permissive/86658573/project.v:303: syntax error, unexpected \'=\', expecting IDENTIFIER\n colour = 3\'b110;\n ^\n%Error: data/full_repos/permissive/86658573/project.v:306: syntax error, unexpected \'=\', expecting IDENTIFIER\n colour = 3\'b000;\n ^\n%Error: data/full_repos/permissive/86658573/project.v:309: syntax error, unexpected \'=\', expecting IDENTIFIER\n colour = 3\'b101;\n ^\n%Error: data/full_repos/permissive/86658573/project.v:319: syntax error, unexpected <=, expecting IDENTIFIER\n colour <= 3\'b110;\n ^~\n%Error: data/full_repos/permissive/86658573/project.v:336: syntax error, unexpected \'=\', expecting IDENTIFIER\n colour = 3\'b000;\n ^\n%Error: data/full_repos/permissive/86658573/project.v:338: syntax error, unexpected \'=\', expecting IDENTIFIER\n colour = 3\'b011;\n ^\n%Error: data/full_repos/permissive/86658573/project.v:344: syntax error, unexpected <=, expecting IDENTIFIER\n x_init <= x_init + 2;\n ^~\n%Error: Cannot continue\n' | 304,096 | module | module project(
CLOCK_50,
KEY,
SW,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B,
LEDR
);
input CLOCK_50;
input [9:0] SW;
input [3:0] KEY;
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
output [9:0] LEDR;
wire [2:0] colour;
wire [7:0] x;
wire [6:0] y;
wire resetn = KEY[0];
vga_adapter VGA(
.resetn(resetn),
.clock(CLOCK_50),
.colour(colour),
.x(x),
.y(y),
.plot(1),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK));
defparam VGA.RESOLUTION = "160x120";
defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
defparam VGA.BACKGROUND_IMAGE = "black.mif";
wire [27:0] rate = 28'b0000001011011100011011000000;
wire [159:0] draw;
wire start, move;
control c(
.clk(CLOCK_50),
.go(~KEY[2]),
.stop(~KEY[1]),
.start(start),
.resetn(resetn),
.move(move)
);
datapath d(
.clk(CLOCK_50),
.start(start),
.move(move),
.jump(~KEY[3]),
.rate(rate),
.resetn(resetn),
.draw(draw),
.LEDR(LEDR[9:0])
);
display d0(
.floor(draw),
.clk(CLOCK_50),
.resetn(resetn),
.x(x),
.y(y),
.colour(colour)
);
endmodule | module project(
CLOCK_50,
KEY,
SW,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B,
LEDR
); |
input CLOCK_50;
input [9:0] SW;
input [3:0] KEY;
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
output [9:0] LEDR;
wire [2:0] colour;
wire [7:0] x;
wire [6:0] y;
wire resetn = KEY[0];
vga_adapter VGA(
.resetn(resetn),
.clock(CLOCK_50),
.colour(colour),
.x(x),
.y(y),
.plot(1),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK));
defparam VGA.RESOLUTION = "160x120";
defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
defparam VGA.BACKGROUND_IMAGE = "black.mif";
wire [27:0] rate = 28'b0000001011011100011011000000;
wire [159:0] draw;
wire start, move;
control c(
.clk(CLOCK_50),
.go(~KEY[2]),
.stop(~KEY[1]),
.start(start),
.resetn(resetn),
.move(move)
);
datapath d(
.clk(CLOCK_50),
.start(start),
.move(move),
.jump(~KEY[3]),
.rate(rate),
.resetn(resetn),
.draw(draw),
.LEDR(LEDR[9:0])
);
display d0(
.floor(draw),
.clk(CLOCK_50),
.resetn(resetn),
.x(x),
.y(y),
.colour(colour)
);
endmodule | 0 |
138,958 | data/full_repos/permissive/86658573/project.v | 86,658,573 | project.v | v | 360 | 358 | [] | [] | [] | null | line:61: before: "." | null | 1: b'%Error: data/full_repos/permissive/86658573/project.v:214: syntax error, unexpected if, expecting \';\'\n if (height == 2\'b00) \n ^~\n%Error: data/full_repos/permissive/86658573/project.v:218: syntax error, unexpected else\n else\n ^~~~\n%Error: data/full_repos/permissive/86658573/project.v:254: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:266: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [7:0] x_init=8\'d2;\n ^~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:267: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [6:0] y_init = 7\'d80;\n ^~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:268: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [2:0] count = 3\'b000;\n ^~~~~\n%Error: data/full_repos/permissive/86658573/project.v:269: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [10:0] counter = 11\'b0;\n ^~~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:272: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [4:0] runner_count; = 5\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:273: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [2:0] runner_height = 3\'b0;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:276: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [159:0] local_draw;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:287: syntax error, unexpected else\n else begin\n ^~~~\n%Error: data/full_repos/permissive/86658573/project.v:303: syntax error, unexpected \'=\', expecting IDENTIFIER\n colour = 3\'b110;\n ^\n%Error: data/full_repos/permissive/86658573/project.v:306: syntax error, unexpected \'=\', expecting IDENTIFIER\n colour = 3\'b000;\n ^\n%Error: data/full_repos/permissive/86658573/project.v:309: syntax error, unexpected \'=\', expecting IDENTIFIER\n colour = 3\'b101;\n ^\n%Error: data/full_repos/permissive/86658573/project.v:319: syntax error, unexpected <=, expecting IDENTIFIER\n colour <= 3\'b110;\n ^~\n%Error: data/full_repos/permissive/86658573/project.v:336: syntax error, unexpected \'=\', expecting IDENTIFIER\n colour = 3\'b000;\n ^\n%Error: data/full_repos/permissive/86658573/project.v:338: syntax error, unexpected \'=\', expecting IDENTIFIER\n colour = 3\'b011;\n ^\n%Error: data/full_repos/permissive/86658573/project.v:344: syntax error, unexpected <=, expecting IDENTIFIER\n x_init <= x_init + 2;\n ^~\n%Error: Cannot continue\n' | 304,096 | module | module control(
input clk,
input go,
input stop,
input resetn,
output reg start,
output reg move
);
reg [5:0] cur, next;
localparam S_READY = 5'd0,
S_READY_WAIT = 5'd1,
S_MOVE = 5'd2,
S_STOP = 5'd3;
always@(*)
begin: state_table
case (cur)
S_READY: next = go ? S_READY_WAIT : S_READY;
S_READY_WAIT: next = S_MOVE;
S_MOVE: next = stop ? S_STOP : S_MOVE;
S_STOP: next = S_READY;
default: next = S_READY;
endcase
end
always @(*)
begin: enable_signals
start = 1'b0;
move = 1'b0;
case (cur)
S_READY: begin
start = 1'b1;
end
S_MOVE: begin
move = 1'b1;
end
default: begin
end
endcase
end
always@(posedge clk)
begin: state_FFs
if (!resetn)
cur <= S_READY;
else
cur <= next;
end
endmodule | module control(
input clk,
input go,
input stop,
input resetn,
output reg start,
output reg move
); |
reg [5:0] cur, next;
localparam S_READY = 5'd0,
S_READY_WAIT = 5'd1,
S_MOVE = 5'd2,
S_STOP = 5'd3;
always@(*)
begin: state_table
case (cur)
S_READY: next = go ? S_READY_WAIT : S_READY;
S_READY_WAIT: next = S_MOVE;
S_MOVE: next = stop ? S_STOP : S_MOVE;
S_STOP: next = S_READY;
default: next = S_READY;
endcase
end
always @(*)
begin: enable_signals
start = 1'b0;
move = 1'b0;
case (cur)
S_READY: begin
start = 1'b1;
end
S_MOVE: begin
move = 1'b1;
end
default: begin
end
endcase
end
always@(posedge clk)
begin: state_FFs
if (!resetn)
cur <= S_READY;
else
cur <= next;
end
endmodule | 0 |
138,959 | data/full_repos/permissive/86658573/project.v | 86,658,573 | project.v | v | 360 | 358 | [] | [] | [] | null | line:61: before: "." | null | 1: b'%Error: data/full_repos/permissive/86658573/project.v:214: syntax error, unexpected if, expecting \';\'\n if (height == 2\'b00) \n ^~\n%Error: data/full_repos/permissive/86658573/project.v:218: syntax error, unexpected else\n else\n ^~~~\n%Error: data/full_repos/permissive/86658573/project.v:254: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:266: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [7:0] x_init=8\'d2;\n ^~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:267: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [6:0] y_init = 7\'d80;\n ^~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:268: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [2:0] count = 3\'b000;\n ^~~~~\n%Error: data/full_repos/permissive/86658573/project.v:269: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [10:0] counter = 11\'b0;\n ^~~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:272: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [4:0] runner_count; = 5\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:273: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [2:0] runner_height = 3\'b0;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:276: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [159:0] local_draw;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:287: syntax error, unexpected else\n else begin\n ^~~~\n%Error: data/full_repos/permissive/86658573/project.v:303: syntax error, unexpected \'=\', expecting IDENTIFIER\n colour = 3\'b110;\n ^\n%Error: data/full_repos/permissive/86658573/project.v:306: syntax error, unexpected \'=\', expecting IDENTIFIER\n colour = 3\'b000;\n ^\n%Error: data/full_repos/permissive/86658573/project.v:309: syntax error, unexpected \'=\', expecting IDENTIFIER\n colour = 3\'b101;\n ^\n%Error: data/full_repos/permissive/86658573/project.v:319: syntax error, unexpected <=, expecting IDENTIFIER\n colour <= 3\'b110;\n ^~\n%Error: data/full_repos/permissive/86658573/project.v:336: syntax error, unexpected \'=\', expecting IDENTIFIER\n colour = 3\'b000;\n ^\n%Error: data/full_repos/permissive/86658573/project.v:338: syntax error, unexpected \'=\', expecting IDENTIFIER\n colour = 3\'b011;\n ^\n%Error: data/full_repos/permissive/86658573/project.v:344: syntax error, unexpected <=, expecting IDENTIFIER\n x_init <= x_init + 2;\n ^~\n%Error: Cannot continue\n' | 304,096 | module | module datapath (
input clk,
input start,
input move,
input jump,
input [27:0] rate,
input resetn,
output reg [159:0] draw,
output [9:0] LEDR
);
reg [27:0] count;
reg [319:0] obstacles;
reg [1:0] height = 2'b00;
reg jumpOnce = 1'b0;
reg going_up = 1'b1;
always@(posedge clk) begin
if (!resetn) begin
count <= rate;
height <= 2'b00;
going_up <= 1'b1;
jumpOnce <= 1'b0;
end
else if (start) begin
count <= rate;
height <= 2'b00;
draw <= 160'b0;
obstacles[319:0] <= 320'b00000000000000000100000000000100000000001000000000000000001000000000000000000100000000000000010000000000110000000000000000010000000000000000010000000000000001000000000001000000000000100000000000000001000000000000000011000000000000000010000000000000000001000000000000110000000000001100000000000000000100000000000000001100;
going_up <= 1'b1;
end
else begin
if (count == 28'b0) begin
count <= rate;
draw = draw << 2;
draw[1:0] = obstacles[319:318];
obstacles[319:0] = {obstacles[317:0], obstacles[319:318]};
if (jump || (height) != 2'b00) begin
if (height == 2'b11)
going_up = 1'b0;
if (going_up)
height += 1;
else
height -= 1
if (height == 2'b00)
going_up = 1'b1;
end
draw[159:158] = height;
else
count <= count - 1;
end
end
assign LEDR[4] = jumpOnce;
assign LEDR[6] = going_up;
assign LEDR[9:8] = height;
endmodule | module datapath (
input clk,
input start,
input move,
input jump,
input [27:0] rate,
input resetn,
output reg [159:0] draw,
output [9:0] LEDR
); |
reg [27:0] count;
reg [319:0] obstacles;
reg [1:0] height = 2'b00;
reg jumpOnce = 1'b0;
reg going_up = 1'b1;
always@(posedge clk) begin
if (!resetn) begin
count <= rate;
height <= 2'b00;
going_up <= 1'b1;
jumpOnce <= 1'b0;
end
else if (start) begin
count <= rate;
height <= 2'b00;
draw <= 160'b0;
obstacles[319:0] <= 320'b00000000000000000100000000000100000000001000000000000000001000000000000000000100000000000000010000000000110000000000000000010000000000000000010000000000000001000000000001000000000000100000000000000001000000000000000011000000000000000010000000000000000001000000000000110000000000001100000000000000000100000000000000001100;
going_up <= 1'b1;
end
else begin
if (count == 28'b0) begin
count <= rate;
draw = draw << 2;
draw[1:0] = obstacles[319:318];
obstacles[319:0] = {obstacles[317:0], obstacles[319:318]};
if (jump || (height) != 2'b00) begin
if (height == 2'b11)
going_up = 1'b0;
if (going_up)
height += 1;
else
height -= 1
if (height == 2'b00)
going_up = 1'b1;
end
draw[159:158] = height;
else
count <= count - 1;
end
end
assign LEDR[4] = jumpOnce;
assign LEDR[6] = going_up;
assign LEDR[9:8] = height;
endmodule | 0 |
138,960 | data/full_repos/permissive/86658573/project.v | 86,658,573 | project.v | v | 360 | 358 | [] | [] | [] | null | line:61: before: "." | null | 1: b'%Error: data/full_repos/permissive/86658573/project.v:214: syntax error, unexpected if, expecting \';\'\n if (height == 2\'b00) \n ^~\n%Error: data/full_repos/permissive/86658573/project.v:218: syntax error, unexpected else\n else\n ^~~~\n%Error: data/full_repos/permissive/86658573/project.v:254: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:266: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [7:0] x_init=8\'d2;\n ^~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:267: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [6:0] y_init = 7\'d80;\n ^~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:268: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [2:0] count = 3\'b000;\n ^~~~~\n%Error: data/full_repos/permissive/86658573/project.v:269: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [10:0] counter = 11\'b0;\n ^~~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:272: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [4:0] runner_count; = 5\'b0;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:273: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [2:0] runner_height = 3\'b0;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:276: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [159:0] local_draw;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/86658573/project.v:287: syntax error, unexpected else\n else begin\n ^~~~\n%Error: data/full_repos/permissive/86658573/project.v:303: syntax error, unexpected \'=\', expecting IDENTIFIER\n colour = 3\'b110;\n ^\n%Error: data/full_repos/permissive/86658573/project.v:306: syntax error, unexpected \'=\', expecting IDENTIFIER\n colour = 3\'b000;\n ^\n%Error: data/full_repos/permissive/86658573/project.v:309: syntax error, unexpected \'=\', expecting IDENTIFIER\n colour = 3\'b101;\n ^\n%Error: data/full_repos/permissive/86658573/project.v:319: syntax error, unexpected <=, expecting IDENTIFIER\n colour <= 3\'b110;\n ^~\n%Error: data/full_repos/permissive/86658573/project.v:336: syntax error, unexpected \'=\', expecting IDENTIFIER\n colour = 3\'b000;\n ^\n%Error: data/full_repos/permissive/86658573/project.v:338: syntax error, unexpected \'=\', expecting IDENTIFIER\n colour = 3\'b011;\n ^\n%Error: data/full_repos/permissive/86658573/project.v:344: syntax error, unexpected <=, expecting IDENTIFIER\n x_init <= x_init + 2;\n ^~\n%Error: Cannot continue\n' | 304,096 | module | module display (
input [159:0] floor,
input clk,
input resetn,
output reg [7:0] x,
output reg [6:0] y,
output reg [2:0] colour
);
reg [7:0] x_init=8'd2;
reg [6:0] y_init = 7'd80;
reg [2:0] count = 3'b000;
reg [10:0] counter = 11'b0;
reg [4:0] runner_count; = 5'b0;
reg [2:0] runner_height = 3'b0;
reg [159:0] local_draw;
always@(posedge clk) begin
if (!resetn) begin
x_init <= 8'd2;
y_init <= 7'd80;
count <= 3'b000;
counter <= 11'b0;
local_draw <= floor<<2;
end
else begin
if (counter < 11'd652) begin
if (counter < 11'd20) begin
if counter < 11'd10
x <= 8'd0;
else
x <= 8'd1;
runner_count = counter % 10;
y = y_init - runner_count;
runner_height = floor[159:158] * 2;
if (runner_count == 5'd0)
colour = 3'b110;
else if (runner_count < runner_height || runner_count > runner_height + 3)
colour = 3'b000;
else
colour = 3'b101;
end
else
begin
count = (counter-20) % 8;
x <= x_init + count[2];
if (count[1:0] == 2'b00) begin
colour <= 3'b110;
y <= y_init;
end
else begin
if (count[1:0] > local_draw[159:158])
colour = 3'b000;
else
colour = 3'b011;
y <= y_init - count[1:0];
end
if (count == 3'b111)
begin
x_init <= x_init + 2;
local_draw <= local_draw << 2;
end
end
counter = counter + 1;
end
else begin
x_init <= 8'd2;
y_init <= 7'd80;
count <= 3'b000;
counter <= 11'b0;
local_draw <= floor << 2;
end
end
end
endmodule | module display (
input [159:0] floor,
input clk,
input resetn,
output reg [7:0] x,
output reg [6:0] y,
output reg [2:0] colour
); |
reg [7:0] x_init=8'd2;
reg [6:0] y_init = 7'd80;
reg [2:0] count = 3'b000;
reg [10:0] counter = 11'b0;
reg [4:0] runner_count; = 5'b0;
reg [2:0] runner_height = 3'b0;
reg [159:0] local_draw;
always@(posedge clk) begin
if (!resetn) begin
x_init <= 8'd2;
y_init <= 7'd80;
count <= 3'b000;
counter <= 11'b0;
local_draw <= floor<<2;
end
else begin
if (counter < 11'd652) begin
if (counter < 11'd20) begin
if counter < 11'd10
x <= 8'd0;
else
x <= 8'd1;
runner_count = counter % 10;
y = y_init - runner_count;
runner_height = floor[159:158] * 2;
if (runner_count == 5'd0)
colour = 3'b110;
else if (runner_count < runner_height || runner_count > runner_height + 3)
colour = 3'b000;
else
colour = 3'b101;
end
else
begin
count = (counter-20) % 8;
x <= x_init + count[2];
if (count[1:0] == 2'b00) begin
colour <= 3'b110;
y <= y_init;
end
else begin
if (count[1:0] > local_draw[159:158])
colour = 3'b000;
else
colour = 3'b011;
y <= y_init - count[1:0];
end
if (count == 3'b111)
begin
x_init <= x_init + 2;
local_draw <= local_draw << 2;
end
end
counter = counter + 1;
end
else begin
x_init <= 8'd2;
y_init <= 7'd80;
count <= 3'b000;
counter <= 11'b0;
local_draw <= floor << 2;
end
end
end
endmodule | 0 |
138,961 | data/full_repos/permissive/86664697/keys/keys.v | 86,664,697 | keys.v | v | 13 | 35 | [] | [] | [] | [(1, 13)] | null | data/verilator_xmls/2a0ec017-1ea2-4fb3-9acc-ec6d4599ec95.xml | null | 304,097 | module | module keys (KEY, CLOCK_50, LEDR);
input [3:0] KEY;
input CLOCK_50;
output reg [3:0] LEDR;
always @(posedge CLOCK_50)
LEDR [3:0] <= KEY [3:0];
endmodule | module keys (KEY, CLOCK_50, LEDR); |
input [3:0] KEY;
input CLOCK_50;
output reg [3:0] LEDR;
always @(posedge CLOCK_50)
LEDR [3:0] <= KEY [3:0];
endmodule | 0 |
138,962 | data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/Basic_Organ_Solution.v | 86,664,697 | Basic_Organ_Solution.v | v | 631 | 126 | [] | [] | [] | null | line:40: before: ")" | null | 1: b"%Error: data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/Basic_Organ_Solution.v:40: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/Basic_Organ_Solution.v:89: syntax error, unexpected assign\nassign CLK_50M = CLOCK_50;\n^~~~~~\n%Error: data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/Basic_Organ_Solution.v:99: syntax error, unexpected assign\nassign GPIO_0[7:0] = LCD_DATA;\n^~~~~~\n%Error: data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/Basic_Organ_Solution.v:214: syntax error, unexpected assign\nassign do_freq = 32'h17544; \n^~~~~~\n%Error: data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/Basic_Organ_Solution.v:304: syntax error, unexpected IDENTIFIER\ndoublesync user_scope_enable_sync1(.indata(scope_enable_source),\n^~~~~~~~~~\n%Error: data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/Basic_Organ_Solution.v:323: syntax error, unexpected assign\nassign ScopeChannelASignal = Sample_Clk_Signal;\n^~~~~~\n%Error: data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/Basic_Organ_Solution.v:398: syntax error, unexpected IDENTIFIER\nclock_divider Gen_1KHz_clk(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/Basic_Organ_Solution.v:416: syntax error, unexpected IDENTIFIER\ndoublesync \n^~~~~~~~~~\n%Error: data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/Basic_Organ_Solution.v:436: syntax error, unexpected always\nalways @(posedge Clock_1KHz)\n^~~~~~\n%Error: data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/Basic_Organ_Solution.v:462: syntax error, unexpected IDENTIFIER\nasync_trap_and_reset_gen_1_pulse \n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/Basic_Organ_Solution.v:485: syntax error, unexpected IDENTIFIER\ndoublesync \n^~~~~~~~~~\n%Error: data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/Basic_Organ_Solution.v:495: syntax error, unexpected IDENTIFIER\nspeed_reg_control \n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/Basic_Organ_Solution.v:509: syntax error, unexpected always\nalways @ (posedge CLK_50M) \n^~~~~~\n%Error: data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/Basic_Organ_Solution.v:519: syntax error, unexpected IDENTIFIER\nSevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst0(.ssOut(Seven_Seg_Val[0]), .nIn(Seven_Seg_Data[0]));\n^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/Basic_Organ_Solution.v:536: syntax error, unexpected IDENTIFIER\nGenerate_Arbitrary_Divided_Clk32 \n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/Basic_Organ_Solution.v:548: syntax error, unexpected always\nalways @(posedge Clock_2Hz)\n^~~~~~\n%Error: data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/Basic_Organ_Solution.v:576: syntax error, unexpected IDENTIFIER\nto_slow_clk_interface \n^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 17 error(s)\n" | 304,104 | module | module Basic_Organ_Solution(
CLOCK_50,
LEDR,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_XCK,
FPGA_I2C_SCLK,
FPGA_I2C_SDAT,
GPIO_0,
GPIO_1,
);
input CLOCK_50;
output [9:0] LEDR;
input [3:0] KEY;
input [9:0] SW;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [6:0] HEX4;
output [6:0] HEX5;
input AUD_ADCDAT;
inout AUD_ADCLRCK;
inout AUD_BCLK;
output AUD_DACDAT;
inout AUD_DACLRCK;
output AUD_XCK;
output FPGA_I2C_SCLK;
inout FPGA_I2C_SDAT;
inout [35:0] GPIO_0;
inout [35:0] GPIO_1;
logic CLK_50M;
logic [7:0] LED;
assign CLK_50M = CLOCK_50;
assign LEDR[7:0] = LED[7:0];
wire [7:0] LCD_DATA;
wire LCD_EN;
wire LCD_ON;
wire LCD_RS;
wire LCD_RW;
assign GPIO_0[7:0] = LCD_DATA;
assign GPIO_0[8] = LCD_EN;
assign GPIO_0[9] = LCD_ON;
assign GPIO_0[10] = LCD_RS;
assign GPIO_0[11] = LCD_RS;
assign GPIO_0[12] = LCD_RW;
parameter character_0 =8'h30;
parameter character_1 =8'h31;
parameter character_2 =8'h32;
parameter character_3 =8'h33;
parameter character_4 =8'h34;
parameter character_5 =8'h35;
parameter character_6 =8'h36;
parameter character_7 =8'h37;
parameter character_8 =8'h38;
parameter character_9 =8'h39;
parameter character_A =8'h41;
parameter character_B =8'h42;
parameter character_C =8'h43;
parameter character_D =8'h44;
parameter character_E =8'h45;
parameter character_F =8'h46;
parameter character_G =8'h47;
parameter character_H =8'h48;
parameter character_I =8'h49;
parameter character_J =8'h4A;
parameter character_K =8'h4B;
parameter character_L =8'h4C;
parameter character_M =8'h4D;
parameter character_N =8'h4E;
parameter character_O =8'h4F;
parameter character_P =8'h50;
parameter character_Q =8'h51;
parameter character_R =8'h52;
parameter character_S =8'h53;
parameter character_T =8'h54;
parameter character_U =8'h55;
parameter character_V =8'h56;
parameter character_W =8'h57;
parameter character_X =8'h58;
parameter character_Y =8'h59;
parameter character_Z =8'h5A;
parameter character_lowercase_a= 8'h61;
parameter character_lowercase_b= 8'h62;
parameter character_lowercase_c= 8'h63;
parameter character_lowercase_d= 8'h64;
parameter character_lowercase_e= 8'h65;
parameter character_lowercase_f= 8'h66;
parameter character_lowercase_g= 8'h67;
parameter character_lowercase_h= 8'h68;
parameter character_lowercase_i= 8'h69;
parameter character_lowercase_j= 8'h6A;
parameter character_lowercase_k= 8'h6B;
parameter character_lowercase_l= 8'h6C;
parameter character_lowercase_m= 8'h6D;
parameter character_lowercase_n= 8'h6E;
parameter character_lowercase_o= 8'h6F;
parameter character_lowercase_p= 8'h70;
parameter character_lowercase_q= 8'h71;
parameter character_lowercase_r= 8'h72;
parameter character_lowercase_s= 8'h73;
parameter character_lowercase_t= 8'h74;
parameter character_lowercase_u= 8'h75;
parameter character_lowercase_v= 8'h76;
parameter character_lowercase_w= 8'h77;
parameter character_lowercase_x= 8'h78;
parameter character_lowercase_y= 8'h79;
parameter character_lowercase_z= 8'h7A;
parameter character_colon = 8'h3A;
parameter character_stop = 8'h2E;
parameter character_semi_colon = 8'h3B;
parameter character_minus = 8'h2D;
parameter character_divide = 8'h2F;
parameter character_plus = 8'h2B;
parameter character_comma = 8'h2C;
parameter character_less_than = 8'h3C;
parameter character_greater_than = 8'h3E;
parameter character_equals = 8'h3D;
parameter character_question = 8'h3F;
parameter character_dollar = 8'h24;
parameter character_space=8'h20;
parameter character_exclaim=8'h21;
wire Clock_1KHz, Clock_1Hz;
wire Sample_Clk_Signal;
wire [31:0] do_freq, re_freq, mi_freq, fa_freq, so_freq, la_freq, ti_freq, do2_freq;
wire [31:0] output_freq;
logic [2:0] led_position = 3'b0;
logic reached_end_flag = 1'b0;
logic octave_flag = 1'b0;
logic [7:0] char1, char2, char3;
wire note_to_play;
assign do_freq = 32'h17544;
assign re_freq = 32'h14C8B;
assign mi_freq = 32'h12843;
assign fa_freq = 32'h117A2;
assign so_freq = 32'hF91F;
assign la_freq = 32'hDDF3;
assign ti_freq = 32'hC5BB;
assign do2_freq = 32'hBAA2;
mux8_1 mux(.select(SW[3:1]),
.mux1(do_freq),
.mux2(re_freq),
.mux3(mi_freq),
.mux4(fa_freq),
.mux5(so_freq),
.mux6(la_freq),
.mux7(ti_freq),
.mux8(do2_freq),
.output_freq(output_freq),
.char1(char1),
.char2(char2),
.char3(char3));
always_ff @ (posedge Clock_1Hz) begin
begin
LED <= 10'b0;
LED[led_position] <= 1'b1;
end
begin
if (led_position >= 3'b111) begin
reached_end_flag <= 1'b1;
led_position <= led_position - 1'b1;
end
else if (led_position == 0) begin
reached_end_flag <= 1'b0;
led_position <= led_position + 1'b1;
end
else if (reached_end_flag == 0)
led_position <= led_position + 1'b1;
else
led_position <= led_position - 1'b1;
end
end
assign Sample_Clk_Signal = Clock_1KHz;
wire [7:0] audio_data = SW[0] ? ({(~Sample_Clk_Signal),{7{Sample_Clk_Signal}}}) : 8'b0;
wire allow_run_LCD_scope;
wire [15:0] scope_channelA, scope_channelB;
(* keep = 1, preserve = 1 *) wire scope_clk;
reg user_scope_enable_trigger;
wire user_scope_enable;
wire user_scope_enable_trigger_path0, user_scope_enable_trigger_path1;
wire scope_enable_source = SW[8];
wire choose_LCD_or_SCOPE = SW[9];
doublesync user_scope_enable_sync1(.indata(scope_enable_source),
.outdata(user_scope_enable),
.clk(CLK_50M),
.reset(1'b1));
Generate_Arbitrary_Divided_Clk32
Generate_LCD_scope_Clk(
.inclk(CLK_50M),
.outclk(scope_clk),
.outclk_Not(),
.div_clk_count(scope_sampling_clock_count),
.Reset(1'h1));
(* keep = 1, preserve = 1 *) logic ScopeChannelASignal;
(* keep = 1, preserve = 1 *) logic ScopeChannelBSignal;
assign ScopeChannelASignal = Sample_Clk_Signal;
assign ScopeChannelBSignal = SW[1];
scope_capture LCD_scope_channelA(
.clk(scope_clk),
.the_signal(ScopeChannelASignal),
.capture_enable(allow_run_LCD_scope & user_scope_enable),
.captured_data(scope_channelA),
.reset(1'b1));
scope_capture LCD_scope_channelB
(
.clk(scope_clk),
.the_signal(ScopeChannelBSignal),
.capture_enable(allow_run_LCD_scope & user_scope_enable),
.captured_data(scope_channelB),
.reset(1'b1));
assign LCD_ON = 1'b1;
LCD_Scope_Encapsulated_pacoblaze_wrapper LCD_LED_scope(
.lcd_d(LCD_DATA),
.lcd_rs(LCD_RS),
.lcd_rw(LCD_RW),
.lcd_e(LCD_EN),
.clk(CLK_50M),
.InH(audio_data),
.InG({4'h00,SW[3:1]}),
.InF(8'h00),
.InE(8'h00),
.InD(8'h00),
.InC(8'h00),
.InB(8'h00),
.InA(8'h00),
.InfoH({character_P,character_A}),
.InfoG({character_T,character_R}),
.InfoF({character_I,character_O}),
.InfoE({character_T,character_S}),
.InfoD({character_lowercase_v,character_F}),
.InfoC({character_A,character_L}),
.InfoB({character_C,character_O}),
.InfoA({character_N,character_S}),
.choose_scope_or_LCD(choose_LCD_or_SCOPE),
.scope_channelA(scope_channelA),
.scope_channelB(scope_channelB),
.ScopeInfoA({char1,char2,char3,character_space}),
.ScopeInfoB({char1,char2,char3,character_space}),
.enable_scope(allow_run_LCD_scope)
);
wire speed_up_event, speed_down_event;
clock_divider Gen_1KHz_clk(
.inclock(CLK_50M),
.outclock(Clock_1KHz),
.div_clock_count(output_freq),
.reset(1'h1));
wire speed_up_raw;
wire speed_down_raw;
doublesync
key0_doublsync
(.indata(!KEY[0]),
.outdata(speed_up_raw),
.clk(Clock_1KHz),
.reset(1'b1));
doublesync
key1_doublsync
(.indata(!KEY[1]),
.outdata(speed_down_raw),
.clk(Clock_1KHz),
.reset(1'b1));
parameter num_updown_events_per_sec = 10;
parameter num_1KHZ_clocks_between_updown_events = 1000/num_updown_events_per_sec;
reg [15:0] updown_counter = 0;
always @(posedge Clock_1KHz)
begin
if (updown_counter >= num_1KHZ_clocks_between_updown_events)
begin
if (speed_up_raw)
begin
speed_up_event_trigger <= 1;
end
if (speed_down_raw)
begin
speed_down_event_trigger <= 1;
end
updown_counter <= 0;
end
else
begin
updown_counter <= updown_counter + 1;
speed_up_event_trigger <=0;
speed_down_event_trigger <= 0;
end
end
wire speed_up_event_trigger;
wire speed_down_event_trigger;
async_trap_and_reset_gen_1_pulse
make_speedup_pulse
(
.async_sig(speed_up_event_trigger),
.outclk(CLK_50M),
.out_sync_sig(speed_up_event),
.auto_reset(1'b1),
.reset(1'b1)
);
async_trap_and_reset_gen_1_pulse
make_speedown_pulse
(
.async_sig(speed_down_event_trigger),
.outclk(CLK_50M),
.out_sync_sig(speed_down_event),
.auto_reset(1'b1),
.reset(1'b1)
);
wire speed_reset_event;
doublesync
key2_doublsync
(.indata(!KEY[2]),
.outdata(speed_reset_event),
.clk(CLK_50M),
.reset(1'b1));
parameter oscilloscope_speed_step = 100;
wire [15:0] speed_control_val;
speed_reg_control
speed_reg_control_inst
(
.clk(CLK_50M),
.up_event(speed_up_event),
.down_event(speed_down_event),
.reset_event(speed_reset_event),
.speed_control_val(speed_control_val)
);
logic [15:0] scope_sampling_clock_count;
parameter [15:0] default_scope_sampling_clock_count = 12499;
always @ (posedge CLK_50M)
begin
scope_sampling_clock_count <= default_scope_sampling_clock_count+{{16{speed_control_val[15]}},speed_control_val};
end
logic [7:0] Seven_Seg_Val[5:0];
logic [3:0] Seven_Seg_Data[5:0];
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst0(.ssOut(Seven_Seg_Val[0]), .nIn(Seven_Seg_Data[0]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst1(.ssOut(Seven_Seg_Val[1]), .nIn(Seven_Seg_Data[1]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst2(.ssOut(Seven_Seg_Val[2]), .nIn(Seven_Seg_Data[2]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst3(.ssOut(Seven_Seg_Val[3]), .nIn(Seven_Seg_Data[3]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst4(.ssOut(Seven_Seg_Val[4]), .nIn(Seven_Seg_Data[4]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst5(.ssOut(Seven_Seg_Val[5]), .nIn(Seven_Seg_Data[5]));
assign HEX0 = Seven_Seg_Val[0];
assign HEX1 = Seven_Seg_Val[1];
assign HEX2 = Seven_Seg_Val[2];
assign HEX3 = Seven_Seg_Val[3];
assign HEX4 = Seven_Seg_Val[4];
assign HEX5 = Seven_Seg_Val[5];
wire Clock_2Hz;
Generate_Arbitrary_Divided_Clk32
Gen_2Hz_clk
(.inclk(CLK_50M),
.outclk(Clock_2Hz),
.outclk_Not(),
.div_clk_count(32'h17D7840 >> 1),
.Reset(1'h1)
);
logic [23:0] actual_7seg_output;
reg [23:0] regd_actual_7seg_output;
always @(posedge Clock_2Hz)
begin
regd_actual_7seg_output <= actual_7seg_output;
Clock_1Hz <= ~Clock_1Hz;
end
assign Seven_Seg_Data[0] = regd_actual_7seg_output[3:0];
assign Seven_Seg_Data[1] = regd_actual_7seg_output[7:4];
assign Seven_Seg_Data[2] = regd_actual_7seg_output[11:8];
assign Seven_Seg_Data[3] = regd_actual_7seg_output[15:12];
assign Seven_Seg_Data[4] = regd_actual_7seg_output[19:16];
assign Seven_Seg_Data[5] = regd_actual_7seg_output[23:20];
assign actual_7seg_output = scope_sampling_clock_count;
wire [$size(audio_data)-1:0] actual_audio_data_left, actual_audio_data_right;
wire audio_left_clock, audio_right_clock;
to_slow_clk_interface
interface_actual_audio_data_right
(.indata(audio_data),
.outdata(actual_audio_data_right),
.inclk(CLK_50M),
.outclk(audio_right_clock));
to_slow_clk_interface
interface_actual_audio_data_left
(.indata(audio_data),
.outdata(actual_audio_data_left),
.inclk(CLK_50M),
.outclk(audio_left_clock));
audio_controller
audio_control(
.iCLK_50(CLK_50M),
.iCLK_28(),
.I2C_SDAT(FPGA_I2C_SDAT),
.oI2C_SCLK(FPGA_I2C_SCLK),
.AUD_ADCLRCK(AUD_ADCLRCK),
.iAUD_ADCDAT(AUD_ADCDAT),
.AUD_DACLRCK(AUD_DACLRCK),
.oAUD_DACDAT(AUD_DACDAT),
.AUD_BCLK(AUD_BCLK),
.oAUD_XCK(AUD_XCK),
.audio_outL({actual_audio_data_left,8'b1}),
.audio_outR({actual_audio_data_right,8'b1}),
.audio_right_clock(audio_right_clock),
.audio_left_clock(audio_left_clock)
);
endmodule | module Basic_Organ_Solution(
CLOCK_50,
LEDR,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_XCK,
FPGA_I2C_SCLK,
FPGA_I2C_SDAT,
GPIO_0,
GPIO_1,
); |
input CLOCK_50;
output [9:0] LEDR;
input [3:0] KEY;
input [9:0] SW;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [6:0] HEX4;
output [6:0] HEX5;
input AUD_ADCDAT;
inout AUD_ADCLRCK;
inout AUD_BCLK;
output AUD_DACDAT;
inout AUD_DACLRCK;
output AUD_XCK;
output FPGA_I2C_SCLK;
inout FPGA_I2C_SDAT;
inout [35:0] GPIO_0;
inout [35:0] GPIO_1;
logic CLK_50M;
logic [7:0] LED;
assign CLK_50M = CLOCK_50;
assign LEDR[7:0] = LED[7:0];
wire [7:0] LCD_DATA;
wire LCD_EN;
wire LCD_ON;
wire LCD_RS;
wire LCD_RW;
assign GPIO_0[7:0] = LCD_DATA;
assign GPIO_0[8] = LCD_EN;
assign GPIO_0[9] = LCD_ON;
assign GPIO_0[10] = LCD_RS;
assign GPIO_0[11] = LCD_RS;
assign GPIO_0[12] = LCD_RW;
parameter character_0 =8'h30;
parameter character_1 =8'h31;
parameter character_2 =8'h32;
parameter character_3 =8'h33;
parameter character_4 =8'h34;
parameter character_5 =8'h35;
parameter character_6 =8'h36;
parameter character_7 =8'h37;
parameter character_8 =8'h38;
parameter character_9 =8'h39;
parameter character_A =8'h41;
parameter character_B =8'h42;
parameter character_C =8'h43;
parameter character_D =8'h44;
parameter character_E =8'h45;
parameter character_F =8'h46;
parameter character_G =8'h47;
parameter character_H =8'h48;
parameter character_I =8'h49;
parameter character_J =8'h4A;
parameter character_K =8'h4B;
parameter character_L =8'h4C;
parameter character_M =8'h4D;
parameter character_N =8'h4E;
parameter character_O =8'h4F;
parameter character_P =8'h50;
parameter character_Q =8'h51;
parameter character_R =8'h52;
parameter character_S =8'h53;
parameter character_T =8'h54;
parameter character_U =8'h55;
parameter character_V =8'h56;
parameter character_W =8'h57;
parameter character_X =8'h58;
parameter character_Y =8'h59;
parameter character_Z =8'h5A;
parameter character_lowercase_a= 8'h61;
parameter character_lowercase_b= 8'h62;
parameter character_lowercase_c= 8'h63;
parameter character_lowercase_d= 8'h64;
parameter character_lowercase_e= 8'h65;
parameter character_lowercase_f= 8'h66;
parameter character_lowercase_g= 8'h67;
parameter character_lowercase_h= 8'h68;
parameter character_lowercase_i= 8'h69;
parameter character_lowercase_j= 8'h6A;
parameter character_lowercase_k= 8'h6B;
parameter character_lowercase_l= 8'h6C;
parameter character_lowercase_m= 8'h6D;
parameter character_lowercase_n= 8'h6E;
parameter character_lowercase_o= 8'h6F;
parameter character_lowercase_p= 8'h70;
parameter character_lowercase_q= 8'h71;
parameter character_lowercase_r= 8'h72;
parameter character_lowercase_s= 8'h73;
parameter character_lowercase_t= 8'h74;
parameter character_lowercase_u= 8'h75;
parameter character_lowercase_v= 8'h76;
parameter character_lowercase_w= 8'h77;
parameter character_lowercase_x= 8'h78;
parameter character_lowercase_y= 8'h79;
parameter character_lowercase_z= 8'h7A;
parameter character_colon = 8'h3A;
parameter character_stop = 8'h2E;
parameter character_semi_colon = 8'h3B;
parameter character_minus = 8'h2D;
parameter character_divide = 8'h2F;
parameter character_plus = 8'h2B;
parameter character_comma = 8'h2C;
parameter character_less_than = 8'h3C;
parameter character_greater_than = 8'h3E;
parameter character_equals = 8'h3D;
parameter character_question = 8'h3F;
parameter character_dollar = 8'h24;
parameter character_space=8'h20;
parameter character_exclaim=8'h21;
wire Clock_1KHz, Clock_1Hz;
wire Sample_Clk_Signal;
wire [31:0] do_freq, re_freq, mi_freq, fa_freq, so_freq, la_freq, ti_freq, do2_freq;
wire [31:0] output_freq;
logic [2:0] led_position = 3'b0;
logic reached_end_flag = 1'b0;
logic octave_flag = 1'b0;
logic [7:0] char1, char2, char3;
wire note_to_play;
assign do_freq = 32'h17544;
assign re_freq = 32'h14C8B;
assign mi_freq = 32'h12843;
assign fa_freq = 32'h117A2;
assign so_freq = 32'hF91F;
assign la_freq = 32'hDDF3;
assign ti_freq = 32'hC5BB;
assign do2_freq = 32'hBAA2;
mux8_1 mux(.select(SW[3:1]),
.mux1(do_freq),
.mux2(re_freq),
.mux3(mi_freq),
.mux4(fa_freq),
.mux5(so_freq),
.mux6(la_freq),
.mux7(ti_freq),
.mux8(do2_freq),
.output_freq(output_freq),
.char1(char1),
.char2(char2),
.char3(char3));
always_ff @ (posedge Clock_1Hz) begin
begin
LED <= 10'b0;
LED[led_position] <= 1'b1;
end
begin
if (led_position >= 3'b111) begin
reached_end_flag <= 1'b1;
led_position <= led_position - 1'b1;
end
else if (led_position == 0) begin
reached_end_flag <= 1'b0;
led_position <= led_position + 1'b1;
end
else if (reached_end_flag == 0)
led_position <= led_position + 1'b1;
else
led_position <= led_position - 1'b1;
end
end
assign Sample_Clk_Signal = Clock_1KHz;
wire [7:0] audio_data = SW[0] ? ({(~Sample_Clk_Signal),{7{Sample_Clk_Signal}}}) : 8'b0;
wire allow_run_LCD_scope;
wire [15:0] scope_channelA, scope_channelB;
(* keep = 1, preserve = 1 *) wire scope_clk;
reg user_scope_enable_trigger;
wire user_scope_enable;
wire user_scope_enable_trigger_path0, user_scope_enable_trigger_path1;
wire scope_enable_source = SW[8];
wire choose_LCD_or_SCOPE = SW[9];
doublesync user_scope_enable_sync1(.indata(scope_enable_source),
.outdata(user_scope_enable),
.clk(CLK_50M),
.reset(1'b1));
Generate_Arbitrary_Divided_Clk32
Generate_LCD_scope_Clk(
.inclk(CLK_50M),
.outclk(scope_clk),
.outclk_Not(),
.div_clk_count(scope_sampling_clock_count),
.Reset(1'h1));
(* keep = 1, preserve = 1 *) logic ScopeChannelASignal;
(* keep = 1, preserve = 1 *) logic ScopeChannelBSignal;
assign ScopeChannelASignal = Sample_Clk_Signal;
assign ScopeChannelBSignal = SW[1];
scope_capture LCD_scope_channelA(
.clk(scope_clk),
.the_signal(ScopeChannelASignal),
.capture_enable(allow_run_LCD_scope & user_scope_enable),
.captured_data(scope_channelA),
.reset(1'b1));
scope_capture LCD_scope_channelB
(
.clk(scope_clk),
.the_signal(ScopeChannelBSignal),
.capture_enable(allow_run_LCD_scope & user_scope_enable),
.captured_data(scope_channelB),
.reset(1'b1));
assign LCD_ON = 1'b1;
LCD_Scope_Encapsulated_pacoblaze_wrapper LCD_LED_scope(
.lcd_d(LCD_DATA),
.lcd_rs(LCD_RS),
.lcd_rw(LCD_RW),
.lcd_e(LCD_EN),
.clk(CLK_50M),
.InH(audio_data),
.InG({4'h00,SW[3:1]}),
.InF(8'h00),
.InE(8'h00),
.InD(8'h00),
.InC(8'h00),
.InB(8'h00),
.InA(8'h00),
.InfoH({character_P,character_A}),
.InfoG({character_T,character_R}),
.InfoF({character_I,character_O}),
.InfoE({character_T,character_S}),
.InfoD({character_lowercase_v,character_F}),
.InfoC({character_A,character_L}),
.InfoB({character_C,character_O}),
.InfoA({character_N,character_S}),
.choose_scope_or_LCD(choose_LCD_or_SCOPE),
.scope_channelA(scope_channelA),
.scope_channelB(scope_channelB),
.ScopeInfoA({char1,char2,char3,character_space}),
.ScopeInfoB({char1,char2,char3,character_space}),
.enable_scope(allow_run_LCD_scope)
);
wire speed_up_event, speed_down_event;
clock_divider Gen_1KHz_clk(
.inclock(CLK_50M),
.outclock(Clock_1KHz),
.div_clock_count(output_freq),
.reset(1'h1));
wire speed_up_raw;
wire speed_down_raw;
doublesync
key0_doublsync
(.indata(!KEY[0]),
.outdata(speed_up_raw),
.clk(Clock_1KHz),
.reset(1'b1));
doublesync
key1_doublsync
(.indata(!KEY[1]),
.outdata(speed_down_raw),
.clk(Clock_1KHz),
.reset(1'b1));
parameter num_updown_events_per_sec = 10;
parameter num_1KHZ_clocks_between_updown_events = 1000/num_updown_events_per_sec;
reg [15:0] updown_counter = 0;
always @(posedge Clock_1KHz)
begin
if (updown_counter >= num_1KHZ_clocks_between_updown_events)
begin
if (speed_up_raw)
begin
speed_up_event_trigger <= 1;
end
if (speed_down_raw)
begin
speed_down_event_trigger <= 1;
end
updown_counter <= 0;
end
else
begin
updown_counter <= updown_counter + 1;
speed_up_event_trigger <=0;
speed_down_event_trigger <= 0;
end
end
wire speed_up_event_trigger;
wire speed_down_event_trigger;
async_trap_and_reset_gen_1_pulse
make_speedup_pulse
(
.async_sig(speed_up_event_trigger),
.outclk(CLK_50M),
.out_sync_sig(speed_up_event),
.auto_reset(1'b1),
.reset(1'b1)
);
async_trap_and_reset_gen_1_pulse
make_speedown_pulse
(
.async_sig(speed_down_event_trigger),
.outclk(CLK_50M),
.out_sync_sig(speed_down_event),
.auto_reset(1'b1),
.reset(1'b1)
);
wire speed_reset_event;
doublesync
key2_doublsync
(.indata(!KEY[2]),
.outdata(speed_reset_event),
.clk(CLK_50M),
.reset(1'b1));
parameter oscilloscope_speed_step = 100;
wire [15:0] speed_control_val;
speed_reg_control
speed_reg_control_inst
(
.clk(CLK_50M),
.up_event(speed_up_event),
.down_event(speed_down_event),
.reset_event(speed_reset_event),
.speed_control_val(speed_control_val)
);
logic [15:0] scope_sampling_clock_count;
parameter [15:0] default_scope_sampling_clock_count = 12499;
always @ (posedge CLK_50M)
begin
scope_sampling_clock_count <= default_scope_sampling_clock_count+{{16{speed_control_val[15]}},speed_control_val};
end
logic [7:0] Seven_Seg_Val[5:0];
logic [3:0] Seven_Seg_Data[5:0];
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst0(.ssOut(Seven_Seg_Val[0]), .nIn(Seven_Seg_Data[0]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst1(.ssOut(Seven_Seg_Val[1]), .nIn(Seven_Seg_Data[1]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst2(.ssOut(Seven_Seg_Val[2]), .nIn(Seven_Seg_Data[2]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst3(.ssOut(Seven_Seg_Val[3]), .nIn(Seven_Seg_Data[3]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst4(.ssOut(Seven_Seg_Val[4]), .nIn(Seven_Seg_Data[4]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst5(.ssOut(Seven_Seg_Val[5]), .nIn(Seven_Seg_Data[5]));
assign HEX0 = Seven_Seg_Val[0];
assign HEX1 = Seven_Seg_Val[1];
assign HEX2 = Seven_Seg_Val[2];
assign HEX3 = Seven_Seg_Val[3];
assign HEX4 = Seven_Seg_Val[4];
assign HEX5 = Seven_Seg_Val[5];
wire Clock_2Hz;
Generate_Arbitrary_Divided_Clk32
Gen_2Hz_clk
(.inclk(CLK_50M),
.outclk(Clock_2Hz),
.outclk_Not(),
.div_clk_count(32'h17D7840 >> 1),
.Reset(1'h1)
);
logic [23:0] actual_7seg_output;
reg [23:0] regd_actual_7seg_output;
always @(posedge Clock_2Hz)
begin
regd_actual_7seg_output <= actual_7seg_output;
Clock_1Hz <= ~Clock_1Hz;
end
assign Seven_Seg_Data[0] = regd_actual_7seg_output[3:0];
assign Seven_Seg_Data[1] = regd_actual_7seg_output[7:4];
assign Seven_Seg_Data[2] = regd_actual_7seg_output[11:8];
assign Seven_Seg_Data[3] = regd_actual_7seg_output[15:12];
assign Seven_Seg_Data[4] = regd_actual_7seg_output[19:16];
assign Seven_Seg_Data[5] = regd_actual_7seg_output[23:20];
assign actual_7seg_output = scope_sampling_clock_count;
wire [$size(audio_data)-1:0] actual_audio_data_left, actual_audio_data_right;
wire audio_left_clock, audio_right_clock;
to_slow_clk_interface
interface_actual_audio_data_right
(.indata(audio_data),
.outdata(actual_audio_data_right),
.inclk(CLK_50M),
.outclk(audio_right_clock));
to_slow_clk_interface
interface_actual_audio_data_left
(.indata(audio_data),
.outdata(actual_audio_data_left),
.inclk(CLK_50M),
.outclk(audio_left_clock));
audio_controller
audio_control(
.iCLK_50(CLK_50M),
.iCLK_28(),
.I2C_SDAT(FPGA_I2C_SDAT),
.oI2C_SCLK(FPGA_I2C_SCLK),
.AUD_ADCLRCK(AUD_ADCLRCK),
.iAUD_ADCDAT(AUD_ADCDAT),
.AUD_DACLRCK(AUD_DACLRCK),
.oAUD_DACDAT(AUD_DACDAT),
.AUD_BCLK(AUD_BCLK),
.oAUD_XCK(AUD_XCK),
.audio_outL({actual_audio_data_left,8'b1}),
.audio_outR({actual_audio_data_right,8'b1}),
.audio_right_clock(audio_right_clock),
.audio_left_clock(audio_left_clock)
);
endmodule | 0 |
138,963 | data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/doublesync.v | 86,664,697 | doublesync.v | v | 27 | 39 | [] | [] | [] | [(1, 26)] | null | data/verilator_xmls/7b48dc16-ce8d-40d3-bda2-15e05a43d83d.xml | null | 304,106 | module | module doublesync(indata,
outdata,
clk,
reset);
input indata,clk,reset;
output outdata;
reg reg1, reg2;
always @(posedge clk or negedge reset)
begin
if (!reset)
begin
reg1 <= 1'b0;
reg2 <= 1'b0;
end else
begin
reg1 <= indata;
reg2 <= reg1;
end
end
assign outdata = reg2;
endmodule | module doublesync(indata,
outdata,
clk,
reset); |
input indata,clk,reset;
output outdata;
reg reg1, reg2;
always @(posedge clk or negedge reset)
begin
if (!reset)
begin
reg1 <= 1'b0;
reg2 <= 1'b0;
end else
begin
reg1 <= indata;
reg2 <= reg1;
end
end
assign outdata = reg2;
endmodule | 0 |
138,964 | data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/Generate_Arbitrary_Divided_Clk32.v | 86,664,697 | Generate_Arbitrary_Divided_Clk32.v | v | 13 | 86 | [] | [] | [] | [(2, 12)] | null | null | 1: b"%Error: data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/Generate_Arbitrary_Divided_Clk32.v:9: Cannot find file containing module: 'var_clk_div32'\n var_clk_div32 Div_Clk(.inclk(inclk),.outclk(outclk),\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc,data/full_repos/permissive/86664697/var_clk_div32\n data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc,data/full_repos/permissive/86664697/var_clk_div32.v\n data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc,data/full_repos/permissive/86664697/var_clk_div32.sv\n var_clk_div32\n var_clk_div32.v\n var_clk_div32.sv\n obj_dir/var_clk_div32\n obj_dir/var_clk_div32.v\n obj_dir/var_clk_div32.sv\n%Error: Exiting due to 1 error(s)\n" | 304,107 | module | module Generate_Arbitrary_Divided_Clk32(inclk,outclk,outclk_Not,div_clk_count,Reset);
input inclk;
input Reset;
output outclk;
output outclk_Not;
input[31:0] div_clk_count;
var_clk_div32 Div_Clk(.inclk(inclk),.outclk(outclk),
.outclk_not(outclk_Not),.clk_count(div_clk_count),.Reset(Reset));
endmodule | module Generate_Arbitrary_Divided_Clk32(inclk,outclk,outclk_Not,div_clk_count,Reset); |
input inclk;
input Reset;
output outclk;
output outclk_Not;
input[31:0] div_clk_count;
var_clk_div32 Div_Clk(.inclk(inclk),.outclk(outclk),
.outclk_not(outclk_Not),.clk_count(div_clk_count),.Reset(Reset));
endmodule | 0 |
138,965 | data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/LCD_Scope_Encapsulated_pacoblaze_wrapper.v | 86,664,697 | LCD_Scope_Encapsulated_pacoblaze_wrapper.v | v | 64 | 61 | [] | [] | [] | [(1, 62)] | null | null | 1: b"%Error: data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/LCD_Scope_Encapsulated_pacoblaze_wrapper.v:30: Cannot find file containing module: 'LCD_Scope_Encapsulated_pacoblaze'\n LCD_Scope_Encapsulated_pacoblaze\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc,data/full_repos/permissive/86664697/LCD_Scope_Encapsulated_pacoblaze\n data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc,data/full_repos/permissive/86664697/LCD_Scope_Encapsulated_pacoblaze.v\n data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc,data/full_repos/permissive/86664697/LCD_Scope_Encapsulated_pacoblaze.sv\n LCD_Scope_Encapsulated_pacoblaze\n LCD_Scope_Encapsulated_pacoblaze.v\n LCD_Scope_Encapsulated_pacoblaze.sv\n obj_dir/LCD_Scope_Encapsulated_pacoblaze\n obj_dir/LCD_Scope_Encapsulated_pacoblaze.v\n obj_dir/LCD_Scope_Encapsulated_pacoblaze.sv\n%Error: Exiting due to 1 error(s)\n" | 304,108 | module | module LCD_Scope_Encapsulated_pacoblaze_wrapper
(inout [7:0] lcd_d,
output wire lcd_rs,
output lcd_rw,
output wire lcd_e,
input clk,
input wire[7:0] InA,
input wire[7:0] InB,
input wire[7:0] InC,
input wire[7:0] InD,
input wire[7:0] InE,
input wire[7:0] InF,
input wire[7:0] InG,
input wire[7:0] InH,
input wire[15:0] InfoA,
input wire[15:0] InfoB,
input wire[15:0] InfoC,
input wire[15:0] InfoD,
input wire[15:0] InfoE,
input wire[15:0] InfoF,
input wire[15:0] InfoG,
input wire[15:0] InfoH,
input wire[31:0] ScopeInfoA,
input wire[31:0] ScopeInfoB,
input wire choose_scope_or_LCD,
input wire [15:0] scope_channelA,
input wire [15:0] scope_channelB,
output wire enable_scope);
LCD_Scope_Encapsulated_pacoblaze
LCD_Scope_Encapsulated_pacoblaze_inst
(
.lcd_d ( lcd_d ),
.lcd_rs ( lcd_rs ),
.lcd_rw ( lcd_rw ),
.lcd_e ( lcd_e ),
.clk ( clk ),
.InA ( InA ),
.InB ( InB ),
.InC ( InC ),
.InD ( InD ),
.InE ( InE ),
.InF ( InF ),
.InG ( InG ),
.InH ( InH ),
.InfoA ( InfoA ),
.InfoB ( InfoB ),
.InfoC ( InfoC ),
.InfoD ( InfoD ),
.InfoE ( InfoE ),
.InfoF ( InfoF ),
.InfoG ( InfoG ),
.InfoH ( InfoH ),
.ScopeInfoA ( ScopeInfoA ),
.ScopeInfoB ( ScopeInfoB ),
.choose_scope_or_LCD ( choose_scope_or_LCD ),
.scope_channelA ( scope_channelA ),
.scope_channelB ( scope_channelB ),
.enable_scope ( enable_scope )
);
endmodule | module LCD_Scope_Encapsulated_pacoblaze_wrapper
(inout [7:0] lcd_d,
output wire lcd_rs,
output lcd_rw,
output wire lcd_e,
input clk,
input wire[7:0] InA,
input wire[7:0] InB,
input wire[7:0] InC,
input wire[7:0] InD,
input wire[7:0] InE,
input wire[7:0] InF,
input wire[7:0] InG,
input wire[7:0] InH,
input wire[15:0] InfoA,
input wire[15:0] InfoB,
input wire[15:0] InfoC,
input wire[15:0] InfoD,
input wire[15:0] InfoE,
input wire[15:0] InfoF,
input wire[15:0] InfoG,
input wire[15:0] InfoH,
input wire[31:0] ScopeInfoA,
input wire[31:0] ScopeInfoB,
input wire choose_scope_or_LCD,
input wire [15:0] scope_channelA,
input wire [15:0] scope_channelB,
output wire enable_scope); |
LCD_Scope_Encapsulated_pacoblaze
LCD_Scope_Encapsulated_pacoblaze_inst
(
.lcd_d ( lcd_d ),
.lcd_rs ( lcd_rs ),
.lcd_rw ( lcd_rw ),
.lcd_e ( lcd_e ),
.clk ( clk ),
.InA ( InA ),
.InB ( InB ),
.InC ( InC ),
.InD ( InD ),
.InE ( InE ),
.InF ( InF ),
.InG ( InG ),
.InH ( InH ),
.InfoA ( InfoA ),
.InfoB ( InfoB ),
.InfoC ( InfoC ),
.InfoD ( InfoD ),
.InfoE ( InfoE ),
.InfoF ( InfoF ),
.InfoG ( InfoG ),
.InfoH ( InfoH ),
.ScopeInfoA ( ScopeInfoA ),
.ScopeInfoB ( ScopeInfoB ),
.choose_scope_or_LCD ( choose_scope_or_LCD ),
.scope_channelA ( scope_channelA ),
.scope_channelB ( scope_channelB ),
.enable_scope ( enable_scope )
);
endmodule | 0 |
138,966 | data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/mux.sv | 86,664,697 | mux.sv | sv | 56 | 107 | [] | [] | [] | [(1, 56)] | null | data/verilator_xmls/65a14166-ed0f-439b-937f-05bda19f71da.xml | null | 304,109 | module | module mux8_1(input logic [2:0] select, input logic [31:0] mux1, mux2, mux3, mux4, mux5, mux6, mux7, mux8,
output logic [31:0] output_freq, output logic [7:0] char1, char2, char3);
always
begin
case(select)
3'b000: begin
output_freq=mux1;
char1=8'h44;
char2=8'h6F;
char3=8'h20;
end
3'b001: begin
output_freq=mux2;
char1=8'h52;
char2=8'h65;
char3=8'h20;
end
3'b010: begin
output_freq=mux3;
char1=8'h4D;
char2=8'h69;
char3=8'h20;
end
3'b011: begin
output_freq=mux4;
char1=8'h46;
char2=8'h61;
char3=8'h20;
end
3'b100: begin
output_freq=mux5;
char1=8'h53;
char2=8'h6F;
char3=8'h20;
end
3'b101: begin
output_freq=mux6;
char1=8'h4C;
char2=8'h61;
char3=8'h20;
end
3'b110: begin
output_freq=mux7;
char1=8'h54;
char2=8'h69;
char3=8'h20;
end
3'b111: begin
output_freq=mux8;
char1=8'h44;
char2=8'h6F;
char3=8'h32;
end
endcase
end
endmodule | module mux8_1(input logic [2:0] select, input logic [31:0] mux1, mux2, mux3, mux4, mux5, mux6, mux7, mux8,
output logic [31:0] output_freq, output logic [7:0] char1, char2, char3); |
always
begin
case(select)
3'b000: begin
output_freq=mux1;
char1=8'h44;
char2=8'h6F;
char3=8'h20;
end
3'b001: begin
output_freq=mux2;
char1=8'h52;
char2=8'h65;
char3=8'h20;
end
3'b010: begin
output_freq=mux3;
char1=8'h4D;
char2=8'h69;
char3=8'h20;
end
3'b011: begin
output_freq=mux4;
char1=8'h46;
char2=8'h61;
char3=8'h20;
end
3'b100: begin
output_freq=mux5;
char1=8'h53;
char2=8'h6F;
char3=8'h20;
end
3'b101: begin
output_freq=mux6;
char1=8'h4C;
char2=8'h61;
char3=8'h20;
end
3'b110: begin
output_freq=mux7;
char1=8'h54;
char2=8'h69;
char3=8'h20;
end
3'b111: begin
output_freq=mux8;
char1=8'h44;
char2=8'h6F;
char3=8'h32;
end
endcase
end
endmodule | 0 |
138,967 | data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/scope_capture.v | 86,664,697 | scope_capture.v | v | 26 | 109 | [] | [] | [] | [(1, 25)] | null | null | 1: b"%Error: data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/scope_capture.v:7: Cannot find file containing module: 'doublesync'\ndoublesync sync_enable(.indata(capture_enable),\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc,data/full_repos/permissive/86664697/doublesync\n data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc,data/full_repos/permissive/86664697/doublesync.v\n data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc,data/full_repos/permissive/86664697/doublesync.sv\n doublesync\n doublesync.v\n doublesync.sv\n obj_dir/doublesync\n obj_dir/doublesync.v\n obj_dir/doublesync.sv\n%Error: Exiting due to 1 error(s)\n" | 304,110 | module | module scope_capture #(parameter scope_bits = 16)
(input wire clk, input wire the_signal, input wire capture_enable, output reg[scope_bits-1:0] captured_data,
input wire reset);
wire synced_capture_enable;
doublesync sync_enable(.indata(capture_enable),
.outdata(synced_capture_enable),
.clk(~clk),
.reset(1'b1));
always @ (posedge clk or negedge reset)
begin
if (~reset)
captured_data <= 0;
else
begin
if (synced_capture_enable)
begin
captured_data <= {captured_data[scope_bits-2:0],the_signal};
end
end
end
endmodule | module scope_capture #(parameter scope_bits = 16)
(input wire clk, input wire the_signal, input wire capture_enable, output reg[scope_bits-1:0] captured_data,
input wire reset); |
wire synced_capture_enable;
doublesync sync_enable(.indata(capture_enable),
.outdata(synced_capture_enable),
.clk(~clk),
.reset(1'b1));
always @ (posedge clk or negedge reset)
begin
if (~reset)
captured_data <= 0;
else
begin
if (synced_capture_enable)
begin
captured_data <= {captured_data[scope_bits-2:0],the_signal};
end
end
end
endmodule | 0 |
138,968 | data/full_repos/permissive/86664697/Lab1/lab1_template_de1soc/lab1_template_de1soc/widereg.v | 86,664,697 | widereg.v | v | 16 | 38 | [] | [] | [] | [(1, 15)] | null | data/verilator_xmls/0f150a9e-67d9-45bb-a8f6-284a086840a4.xml | null | 304,111 | module | module widereg(indata,outdata,inclk);
parameter width = 8;
input [width-1:0] indata;
output [width-1:0] outdata;
input inclk;
reg [width-1:0] outdata;
always @ (posedge inclk)
begin
outdata <= indata;
end
endmodule | module widereg(indata,outdata,inclk); |
parameter width = 8;
input [width-1:0] indata;
output [width-1:0] outdata;
input inclk;
reg [width-1:0] outdata;
always @ (posedge inclk)
begin
outdata <= indata;
end
endmodule | 0 |
138,969 | data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/clock_divider.sv | 86,664,697 | clock_divider.sv | sv | 17 | 123 | [] | [] | [] | [(1, 16)] | null | data/verilator_xmls/241ca30c-e5c3-412d-848e-e69e7cce85a8.xml | null | 304,121 | module | module clock_divider(input logic inclock,
input logic [31:0] div_clock_count,
output logic outclock);
logic [31:0] count;
always_ff @(posedge inclock)
begin
if (count > div_clock_count - 1 ) begin
count <= 32'b0;
outclock <= !outclock;
end
else
count <= count + 1'b1;
end
endmodule | module clock_divider(input logic inclock,
input logic [31:0] div_clock_count,
output logic outclock); |
logic [31:0] count;
always_ff @(posedge inclock)
begin
if (count > div_clock_count - 1 ) begin
count <= 32'b0;
outclock <= !outclock;
end
else
count <= count + 1'b1;
end
endmodule | 0 |
138,970 | data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/flash_fsm.sv | 86,664,697 | flash_fsm.sv | sv | 104 | 149 | [] | [] | [] | [(1, 104)] | null | null | 1: b"%Error: data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/flash_fsm.sv:42: Cannot find file containing module: 'generate_address'\n generate_address get_add(\n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc,data/full_repos/permissive/86664697/generate_address\n data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc,data/full_repos/permissive/86664697/generate_address.v\n data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc,data/full_repos/permissive/86664697/generate_address.sv\n generate_address\n generate_address.v\n generate_address.sv\n obj_dir/generate_address\n obj_dir/generate_address.v\n obj_dir/generate_address.sv\n%Error: Exiting due to 1 error(s)\n" | 304,123 | module | module flash_fsm (clock50MHZ, clock22KHZ, read_valid, wait_request, reset, pause, direction, read_data, read, byte_enable, data_out, address);
input logic clock50MHZ, clock22KHZ, read_valid, wait_request, reset, pause, direction;
input logic [31:0] read_data;
output logic read;
output logic [3:0] byte_enable;
output logic [15:0] data_out;
output logic [22:0] address;
logic address_enable;
logic address_ready;
logic low_data_valid;
logic high_data_valid;
logic [11:0] state;
parameter idle = 12'b1000_0000_0000;
parameter checkvalidlow = 12'b0000_0110_1111;
parameter checkvalidhigh = 12'b0000_1010_1111;
parameter clock_22_low1 = 12'b0010_0000_0000;
parameter clock_22_high1 = 12'b0011_0000_0000;
parameter clock_22_low2 = 12'b0100_0000_0000;
parameter clock_22_high2 = 12'b0101_0000_0000;
parameter get_address = 12'b0000_0001_0000;
parameter off_address = 12'b0001_0000_0000;
generate_address get_add(
.clk(clock50MHZ),
.reset(reset),
.address_en(address_enable),
.direction(direction),
.address_ready(address_ready),
.address_out(address)
);
always_ff @ (posedge clock50MHZ or posedge reset) begin
if (reset) state <= idle;
else begin
case (state)
idle: if (pause) state <= idle;
else state <= get_address;
get_address: state <= off_address;
off_address: if (address_ready) state <= checkvalidlow;
else state <= off_address;
checkvalidlow: if (read_valid) state <= clock_22_low1;
else state <= checkvalidlow;
clock_22_low1: if (!clock22KHZ) state <= clock_22_high1;
else state <= clock_22_low1;
clock_22_high1: if (clock22KHZ) state <= checkvalidhigh;
else state <= clock_22_high1;
checkvalidhigh: if (read_valid) state <= clock_22_low2;
else state <= checkvalidhigh;
clock_22_low2: if (!clock22KHZ) state <= clock_22_high2;
else state <= clock_22_low2;
clock_22_high2: if (clock22KHZ) state <= idle;
else state <= clock_22_high2;
default: state <= idle;
endcase
end
end
always_ff @(posedge read_valid) begin
if (low_data_valid)
data_out <= read_data[15:0];
else if (high_data_valid)
data_out <= read_data[31:16];
end
always_comb begin
high_data_valid <= state[7];
low_data_valid <= state[6];
read <= state[5];
address_enable <= state[4];
byte_enable <= {state [3:0]};
end
endmodule | module flash_fsm (clock50MHZ, clock22KHZ, read_valid, wait_request, reset, pause, direction, read_data, read, byte_enable, data_out, address); |
input logic clock50MHZ, clock22KHZ, read_valid, wait_request, reset, pause, direction;
input logic [31:0] read_data;
output logic read;
output logic [3:0] byte_enable;
output logic [15:0] data_out;
output logic [22:0] address;
logic address_enable;
logic address_ready;
logic low_data_valid;
logic high_data_valid;
logic [11:0] state;
parameter idle = 12'b1000_0000_0000;
parameter checkvalidlow = 12'b0000_0110_1111;
parameter checkvalidhigh = 12'b0000_1010_1111;
parameter clock_22_low1 = 12'b0010_0000_0000;
parameter clock_22_high1 = 12'b0011_0000_0000;
parameter clock_22_low2 = 12'b0100_0000_0000;
parameter clock_22_high2 = 12'b0101_0000_0000;
parameter get_address = 12'b0000_0001_0000;
parameter off_address = 12'b0001_0000_0000;
generate_address get_add(
.clk(clock50MHZ),
.reset(reset),
.address_en(address_enable),
.direction(direction),
.address_ready(address_ready),
.address_out(address)
);
always_ff @ (posedge clock50MHZ or posedge reset) begin
if (reset) state <= idle;
else begin
case (state)
idle: if (pause) state <= idle;
else state <= get_address;
get_address: state <= off_address;
off_address: if (address_ready) state <= checkvalidlow;
else state <= off_address;
checkvalidlow: if (read_valid) state <= clock_22_low1;
else state <= checkvalidlow;
clock_22_low1: if (!clock22KHZ) state <= clock_22_high1;
else state <= clock_22_low1;
clock_22_high1: if (clock22KHZ) state <= checkvalidhigh;
else state <= clock_22_high1;
checkvalidhigh: if (read_valid) state <= clock_22_low2;
else state <= checkvalidhigh;
clock_22_low2: if (!clock22KHZ) state <= clock_22_high2;
else state <= clock_22_low2;
clock_22_high2: if (clock22KHZ) state <= idle;
else state <= clock_22_high2;
default: state <= idle;
endcase
end
end
always_ff @(posedge read_valid) begin
if (low_data_valid)
data_out <= read_data[15:0];
else if (high_data_valid)
data_out <= read_data[31:16];
end
always_comb begin
high_data_valid <= state[7];
low_data_valid <= state[6];
read <= state[5];
address_enable <= state[4];
byte_enable <= {state [3:0]};
end
endmodule | 0 |
138,971 | data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/generate_address.sv | 86,664,697 | generate_address.sv | sv | 75 | 132 | [] | [] | [] | [(1, 73)] | null | data/verilator_xmls/be4cabb0-dff2-41e0-a679-625bd4cbfb6c.xml | null | 304,124 | module | module generate_address (clk, reset, address_en, direction, address_ready, address_out);
input clk, reset,
address_en,
direction;
output address_ready;
output logic [22:0] address_out;
logic [2:0] state;
logic [22:0] next_address;
logic send, next;
parameter starting_address = 23'h0;
parameter ending_address = 23'h7ffff;
parameter idle = 3'b000;
parameter send_address = 3'b010;
parameter count = 3'b001;
parameter ready = 3'b100;
assign next = state[0];
assign send = state[1];
assign address_ready = state[2];
always_ff @(posedge clk, posedge reset) begin
if(reset)
state = idle;
else
case (state)
idle: if (address_en)
state <= send_address;
else
state <= idle;
send_address : state <= count;
count: state <= ready;
ready: state <= idle;
endcase
end
always_ff @(posedge send)
address_out <= next_address;
always_ff @(posedge next, posedge reset) begin
if (reset)
next_address <= starting_address;
else if (direction)
begin
if (address_out == ending_address)
next_address <= starting_address;
else
next_address <= next_address + 1;
end
else if (!direction) begin
if (address_out == starting_address)
next_address <= ending_address;
else
next_address <= next_address - 1;
end
end
endmodule | module generate_address (clk, reset, address_en, direction, address_ready, address_out); |
input clk, reset,
address_en,
direction;
output address_ready;
output logic [22:0] address_out;
logic [2:0] state;
logic [22:0] next_address;
logic send, next;
parameter starting_address = 23'h0;
parameter ending_address = 23'h7ffff;
parameter idle = 3'b000;
parameter send_address = 3'b010;
parameter count = 3'b001;
parameter ready = 3'b100;
assign next = state[0];
assign send = state[1];
assign address_ready = state[2];
always_ff @(posedge clk, posedge reset) begin
if(reset)
state = idle;
else
case (state)
idle: if (address_en)
state <= send_address;
else
state <= idle;
send_address : state <= count;
count: state <= ready;
ready: state <= idle;
endcase
end
always_ff @(posedge send)
address_out <= next_address;
always_ff @(posedge next, posedge reset) begin
if (reset)
next_address <= starting_address;
else if (direction)
begin
if (address_out == ending_address)
next_address <= starting_address;
else
next_address <= next_address + 1;
end
else if (!direction) begin
if (address_out == starting_address)
next_address <= ending_address;
else
next_address <= next_address - 1;
end
end
endmodule | 0 |
138,972 | data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/Kbd_ctrl.v | 86,664,697 | Kbd_ctrl.v | v | 102 | 127 | [] | [] | [] | [(22, 101)] | null | null | 1: b'%Error: data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/Kbd_ctrl.v:48: Cannot find file containing module: \'async_trap_and_reset\'\n async_trap_and_reset ensure_data_ready_hold(.async_sig(~kbd_clk), .outclk(~clk), .out_sync_sig(data_ready_clk_enable), \n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc,data/full_repos/permissive/86664697/async_trap_and_reset\n data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc,data/full_repos/permissive/86664697/async_trap_and_reset.v\n data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc,data/full_repos/permissive/86664697/async_trap_and_reset.sv\n async_trap_and_reset\n async_trap_and_reset.v\n async_trap_and_reset.sv\n obj_dir/async_trap_and_reset\n obj_dir/async_trap_and_reset.v\n obj_dir/async_trap_and_reset.sv\n%Error: data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/Kbd_ctrl.v:51: Cannot find file containing module: \'async_trap_and_reset\'\n async_trap_and_reset ensure_data_ready_reset(.async_sig(~reset_kbd_reg), .outclk(~clk), .out_sync_sig(data_ready_clk_reset), \n ^~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/Kbd_ctrl.v:75: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance Kbd_ctrl\n bit_count <= 4\'h0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/Kbd_ctrl.v:78: Operator ADD expects 6 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n : ... In instance Kbd_ctrl\n bit_count <= bit_count + 4\'h1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/Kbd_ctrl.v:93: Operator EQ expects 11 bits on the RHS, but RHS\'s VARREF \'KEY_UP_SCAN_CODE\' generates 8 bits.\n : ... In instance Kbd_ctrl\n ((bit_count == 6\'h16) & ((old_kbd_reg == KEY_UP_SCAN_CODE) & (scan_code != EXTENDED_SCAN_CODE))) |\n ^~\n%Warning-WIDTH: data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/Kbd_ctrl.v:95: Operator EQ expects 11 bits on the RHS, but RHS\'s VARREF \'EXTENDED_SCAN_CODE\' generates 8 bits.\n : ... In instance Kbd_ctrl\n extended <= ((bit_count == 6\'h16) & (old_kbd_reg == EXTENDED_SCAN_CODE)) | (bit_count >= 6\'h21); \n ^~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n' | 304,126 | module | module Kbd_ctrl(kbd_clk, kbd_data, clk, received_data, reset_kbd_reg, data_ready,
old_kbd_data, very_old_kbd_data, extended, scan_code);
input kbd_clk;
input kbd_data;
input clk;
output [10:0] received_data;
input reset_kbd_reg;
output data_ready;
output [10:0] old_kbd_data;
output [10:0] very_old_kbd_data;
output [7:0] scan_code;
output extended;
parameter EXTENDED_SCAN_CODE=8'hE0;
parameter KEY_UP_SCAN_CODE=8'hF0;
wire data_ready_clk_reset, data_ready_clk_enable;
reg [10:0] kbd_reg, old_kbd_reg, very_old_kbd_reg;
reg [5:0] bit_count;
reg extended;
reg data_ready;
assign received_data = kbd_reg;
wire[7:0] scan_code;
assign scan_code[7:0] = {kbd_reg[2],kbd_reg[3],kbd_reg[4],kbd_reg[5],kbd_reg[6],kbd_reg[7],kbd_reg[8],kbd_reg[9]};
async_trap_and_reset ensure_data_ready_hold(.async_sig(~kbd_clk), .outclk(~clk), .out_sync_sig(data_ready_clk_enable),
.auto_reset(1'h1), .reset(1'h1));
async_trap_and_reset ensure_data_ready_reset(.async_sig(~reset_kbd_reg), .outclk(~clk), .out_sync_sig(data_ready_clk_reset),
.auto_reset(1'h1), .reset(1'h1));
always @ (negedge kbd_clk)
begin
kbd_reg <= {kbd_reg[9:0],kbd_data};
end
always @ (negedge kbd_clk)
begin
old_kbd_reg <= {old_kbd_reg[9:0],kbd_reg[10]};
end
always @ (negedge kbd_clk)
begin
very_old_kbd_reg <= {very_old_kbd_reg[9:0],old_kbd_reg[10]};
end
always @ (negedge kbd_clk or posedge data_ready_clk_reset)
begin
if (data_ready_clk_reset)
begin
bit_count <= 4'h0;
end else
begin
bit_count <= bit_count + 4'h1;
end
end
always @ (posedge clk or posedge data_ready_clk_reset)
begin
if (data_ready_clk_reset)
begin
data_ready<=0;
extended <= 0;
end else
if (data_ready_clk_enable)
begin
data_ready <= (((bit_count == 6'hB) & (scan_code != EXTENDED_SCAN_CODE) & (scan_code != KEY_UP_SCAN_CODE)) |
((bit_count == 6'h16) & ((old_kbd_reg == KEY_UP_SCAN_CODE) & (scan_code != EXTENDED_SCAN_CODE))) |
(bit_count >= 6'h21));
extended <= ((bit_count == 6'h16) & (old_kbd_reg == EXTENDED_SCAN_CODE)) | (bit_count >= 6'h21);
end
end
endmodule | module Kbd_ctrl(kbd_clk, kbd_data, clk, received_data, reset_kbd_reg, data_ready,
old_kbd_data, very_old_kbd_data, extended, scan_code); |
input kbd_clk;
input kbd_data;
input clk;
output [10:0] received_data;
input reset_kbd_reg;
output data_ready;
output [10:0] old_kbd_data;
output [10:0] very_old_kbd_data;
output [7:0] scan_code;
output extended;
parameter EXTENDED_SCAN_CODE=8'hE0;
parameter KEY_UP_SCAN_CODE=8'hF0;
wire data_ready_clk_reset, data_ready_clk_enable;
reg [10:0] kbd_reg, old_kbd_reg, very_old_kbd_reg;
reg [5:0] bit_count;
reg extended;
reg data_ready;
assign received_data = kbd_reg;
wire[7:0] scan_code;
assign scan_code[7:0] = {kbd_reg[2],kbd_reg[3],kbd_reg[4],kbd_reg[5],kbd_reg[6],kbd_reg[7],kbd_reg[8],kbd_reg[9]};
async_trap_and_reset ensure_data_ready_hold(.async_sig(~kbd_clk), .outclk(~clk), .out_sync_sig(data_ready_clk_enable),
.auto_reset(1'h1), .reset(1'h1));
async_trap_and_reset ensure_data_ready_reset(.async_sig(~reset_kbd_reg), .outclk(~clk), .out_sync_sig(data_ready_clk_reset),
.auto_reset(1'h1), .reset(1'h1));
always @ (negedge kbd_clk)
begin
kbd_reg <= {kbd_reg[9:0],kbd_data};
end
always @ (negedge kbd_clk)
begin
old_kbd_reg <= {old_kbd_reg[9:0],kbd_reg[10]};
end
always @ (negedge kbd_clk)
begin
very_old_kbd_reg <= {very_old_kbd_reg[9:0],old_kbd_reg[10]};
end
always @ (negedge kbd_clk or posedge data_ready_clk_reset)
begin
if (data_ready_clk_reset)
begin
bit_count <= 4'h0;
end else
begin
bit_count <= bit_count + 4'h1;
end
end
always @ (posedge clk or posedge data_ready_clk_reset)
begin
if (data_ready_clk_reset)
begin
data_ready<=0;
extended <= 0;
end else
if (data_ready_clk_enable)
begin
data_ready <= (((bit_count == 6'hB) & (scan_code != EXTENDED_SCAN_CODE) & (scan_code != KEY_UP_SCAN_CODE)) |
((bit_count == 6'h16) & ((old_kbd_reg == KEY_UP_SCAN_CODE) & (scan_code != EXTENDED_SCAN_CODE))) |
(bit_count >= 6'h21));
extended <= ((bit_count == 6'h16) & (old_kbd_reg == EXTENDED_SCAN_CODE)) | (bit_count >= 6'h21);
end
end
endmodule | 0 |
138,973 | data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/key2ascii.v | 86,664,697 | key2ascii.v | v | 67 | 52 | [] | [] | [] | [(2, 67)] | null | data/verilator_xmls/c52d07e4-62ef-48e7-8753-d1bdfcf5ebd3.xml | null | 304,127 | module | module key2ascii
(
input wire [7:0] key_code,
output reg [7:0] ascii_code,
input clk
);
always @(posedge clk)
case(key_code)
8'h45: ascii_code <= 8'h30;
8'h16: ascii_code <= 8'h31;
8'h1e: ascii_code <= 8'h32;
8'h26: ascii_code <= 8'h33;
8'h25: ascii_code <= 8'h34;
8'h2e: ascii_code <= 8'h35;
8'h36: ascii_code <= 8'h36;
8'h3d: ascii_code <= 8'h37;
8'h3e: ascii_code <= 8'h38;
8'h46: ascii_code <= 8'h39;
8'h1c: ascii_code <= 8'h41;
8'h32: ascii_code <= 8'h42;
8'h21: ascii_code <= 8'h43;
8'h23: ascii_code <= 8'h44;
8'h24: ascii_code <= 8'h45;
8'h2b: ascii_code <= 8'h46;
8'h34: ascii_code <= 8'h47;
8'h33: ascii_code <= 8'h48;
8'h43: ascii_code <= 8'h49;
8'h3b: ascii_code <= 8'h4a;
8'h42: ascii_code <= 8'h4b;
8'h4b: ascii_code <= 8'h4c;
8'h3a: ascii_code <= 8'h4d;
8'h31: ascii_code <= 8'h4e;
8'h44: ascii_code <= 8'h4f;
8'h4d: ascii_code <= 8'h50;
8'h15: ascii_code <= 8'h51;
8'h2d: ascii_code <= 8'h52;
8'h1b: ascii_code <= 8'h53;
8'h2c: ascii_code <= 8'h54;
8'h3c: ascii_code <= 8'h55;
8'h2a: ascii_code <= 8'h56;
8'h1d: ascii_code <= 8'h57;
8'h22: ascii_code <= 8'h58;
8'h35: ascii_code <= 8'h59;
8'h1a: ascii_code <= 8'h5a;
8'h0e: ascii_code <= 8'h60;
8'h4e: ascii_code <= 8'h2d;
8'h55: ascii_code <= 8'h3d;
8'h54: ascii_code <= 8'h5b;
8'h5b: ascii_code <= 8'h5d;
8'h5d: ascii_code <= 8'h5c;
8'h4c: ascii_code <= 8'h3b;
8'h52: ascii_code <= 8'h27;
8'h41: ascii_code <= 8'h2c;
8'h49: ascii_code <= 8'h2e;
8'h4a: ascii_code <= 8'h2f;
8'h29: ascii_code <= 8'h20;
8'h5a: ascii_code <= 8'h0d;
8'h66: ascii_code <= 8'h08;
default: ascii_code <= 8'h2a;
endcase
endmodule | module key2ascii
(
input wire [7:0] key_code,
output reg [7:0] ascii_code,
input clk
); |
always @(posedge clk)
case(key_code)
8'h45: ascii_code <= 8'h30;
8'h16: ascii_code <= 8'h31;
8'h1e: ascii_code <= 8'h32;
8'h26: ascii_code <= 8'h33;
8'h25: ascii_code <= 8'h34;
8'h2e: ascii_code <= 8'h35;
8'h36: ascii_code <= 8'h36;
8'h3d: ascii_code <= 8'h37;
8'h3e: ascii_code <= 8'h38;
8'h46: ascii_code <= 8'h39;
8'h1c: ascii_code <= 8'h41;
8'h32: ascii_code <= 8'h42;
8'h21: ascii_code <= 8'h43;
8'h23: ascii_code <= 8'h44;
8'h24: ascii_code <= 8'h45;
8'h2b: ascii_code <= 8'h46;
8'h34: ascii_code <= 8'h47;
8'h33: ascii_code <= 8'h48;
8'h43: ascii_code <= 8'h49;
8'h3b: ascii_code <= 8'h4a;
8'h42: ascii_code <= 8'h4b;
8'h4b: ascii_code <= 8'h4c;
8'h3a: ascii_code <= 8'h4d;
8'h31: ascii_code <= 8'h4e;
8'h44: ascii_code <= 8'h4f;
8'h4d: ascii_code <= 8'h50;
8'h15: ascii_code <= 8'h51;
8'h2d: ascii_code <= 8'h52;
8'h1b: ascii_code <= 8'h53;
8'h2c: ascii_code <= 8'h54;
8'h3c: ascii_code <= 8'h55;
8'h2a: ascii_code <= 8'h56;
8'h1d: ascii_code <= 8'h57;
8'h22: ascii_code <= 8'h58;
8'h35: ascii_code <= 8'h59;
8'h1a: ascii_code <= 8'h5a;
8'h0e: ascii_code <= 8'h60;
8'h4e: ascii_code <= 8'h2d;
8'h55: ascii_code <= 8'h3d;
8'h54: ascii_code <= 8'h5b;
8'h5b: ascii_code <= 8'h5d;
8'h5d: ascii_code <= 8'h5c;
8'h4c: ascii_code <= 8'h3b;
8'h52: ascii_code <= 8'h27;
8'h41: ascii_code <= 8'h2c;
8'h49: ascii_code <= 8'h2e;
8'h4a: ascii_code <= 8'h2f;
8'h29: ascii_code <= 8'h20;
8'h5a: ascii_code <= 8'h0d;
8'h66: ascii_code <= 8'h08;
default: ascii_code <= 8'h2a;
endcase
endmodule | 0 |
138,974 | data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/keyboard_controller.sv | 86,664,697 | keyboard_controller.sv | sv | 90 | 82 | [] | [] | [] | [(1, 90)] | null | data/verilator_xmls/045d971b-7782-4709-a5ca-9359d78352a6.xml | null | 304,128 | module | module keyboard_controller(clock, reset, pressed_key, direction, pause, restart);
input logic clock, reset;
input logic [7:0] pressed_key;
output logic direction, pause, restart;
logic [3:0] state;
parameter character_B = 8'h42;
parameter character_D = 8'h44;
parameter character_E = 8'h45;
parameter character_F = 8'h46;
parameter character_R = 8'h52;
parameter start = 4'b1000;
parameter forward_start = 4'b0001;
parameter forward_pause = 4'b0011;
parameter forward_restart = 4'b1001;
parameter backward_start = 4'b0000;
parameter backward_pause = 4'b0010;
parameter backward_restart = 4'b1000;
always_ff @(posedge clock or posedge reset) begin
if (reset)
state <= start;
else
begin
case(state)
start: if (pressed_key == character_E)
state <= forward_start;
else if (pressed_key == character_B)
state <= backward_start;
else
state <= start;
forward_start: if (pressed_key == character_D)
state <= forward_pause;
else if (pressed_key == character_R)
state <= forward_restart;
else if (pressed_key == character_B)
state <= backward_start;
else
state <= forward_start;
forward_pause: if (pressed_key == character_E)
state <= forward_start;
else if (pressed_key == character_R)
state <= forward_restart;
else if (pressed_key == character_B)
state <= backward_pause;
else
state <= forward_pause;
forward_restart: state <= forward_start;
backward_start: if (pressed_key == character_D)
state <= backward_pause;
else if (pressed_key == character_R)
state <= backward_restart;
else if (pressed_key == character_F)
state <= forward_start;
else
state <= backward_start;
backward_pause: if (pressed_key == character_E)
state <= backward_start;
else if (pressed_key == character_R)
state <= backward_restart;
else if (pressed_key == character_F)
state <= forward_pause;
else
state <= backward_pause;
backward_restart: state <= backward_start;
default: state <= start;
endcase
end
end
always_comb
begin
direction <= state[0];
pause <= state[1];
restart <= state[3];
end
endmodule | module keyboard_controller(clock, reset, pressed_key, direction, pause, restart); |
input logic clock, reset;
input logic [7:0] pressed_key;
output logic direction, pause, restart;
logic [3:0] state;
parameter character_B = 8'h42;
parameter character_D = 8'h44;
parameter character_E = 8'h45;
parameter character_F = 8'h46;
parameter character_R = 8'h52;
parameter start = 4'b1000;
parameter forward_start = 4'b0001;
parameter forward_pause = 4'b0011;
parameter forward_restart = 4'b1001;
parameter backward_start = 4'b0000;
parameter backward_pause = 4'b0010;
parameter backward_restart = 4'b1000;
always_ff @(posedge clock or posedge reset) begin
if (reset)
state <= start;
else
begin
case(state)
start: if (pressed_key == character_E)
state <= forward_start;
else if (pressed_key == character_B)
state <= backward_start;
else
state <= start;
forward_start: if (pressed_key == character_D)
state <= forward_pause;
else if (pressed_key == character_R)
state <= forward_restart;
else if (pressed_key == character_B)
state <= backward_start;
else
state <= forward_start;
forward_pause: if (pressed_key == character_E)
state <= forward_start;
else if (pressed_key == character_R)
state <= forward_restart;
else if (pressed_key == character_B)
state <= backward_pause;
else
state <= forward_pause;
forward_restart: state <= forward_start;
backward_start: if (pressed_key == character_D)
state <= backward_pause;
else if (pressed_key == character_R)
state <= backward_restart;
else if (pressed_key == character_F)
state <= forward_start;
else
state <= backward_start;
backward_pause: if (pressed_key == character_E)
state <= backward_start;
else if (pressed_key == character_R)
state <= backward_restart;
else if (pressed_key == character_F)
state <= forward_pause;
else
state <= backward_pause;
backward_restart: state <= backward_start;
default: state <= start;
endcase
end
end
always_comb
begin
direction <= state[0];
pause <= state[1];
restart <= state[3];
end
endmodule | 0 |
138,975 | data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/speed.sv | 86,664,697 | speed.sv | sv | 26 | 94 | [] | [] | [] | [(1, 20)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/speed.sv:12: Operator ADD expects 16 bits on the RHS, but RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance speed\n adjust <= adjust + 8\'h1; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/speed.sv:15: Operator SUB expects 16 bits on the RHS, but RHS\'s CONST \'8\'h1\' generates 8 bits.\n : ... In instance speed\n adjust <= adjust - 8\'h1; \n ^\n%Error: Exiting due to 2 warning(s)\n' | 304,131 | module | module speed (clock, faster, slower, default_speed, adjust);
input logic clock, faster, slower, default_speed;
output logic [15:0] adjust;
always_ff @(posedge clock) begin
if (default_speed)
adjust <= 0;
else if (faster)
adjust <= adjust + 8'h1;
else if (slower)
adjust <= adjust - 8'h1;
else
adjust <= adjust;
end
endmodule | module speed (clock, faster, slower, default_speed, adjust); |
input logic clock, faster, slower, default_speed;
output logic [15:0] adjust;
always_ff @(posedge clock) begin
if (default_speed)
adjust <= 0;
else if (faster)
adjust <= adjust + 8'h1;
else if (slower)
adjust <= adjust - 8'h1;
else
adjust <= adjust;
end
endmodule | 0 |
138,976 | data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/Write_Kbd_To_LCD.v | 86,664,697 | Write_Kbd_To_LCD.v | v | 83 | 139 | [] | [] | [] | [(21, 82)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/Write_Kbd_To_LCD.v:61: Signal definition not found, creating implicitly: \'actual_kbd_ready\'\n idle : if (actual_kbd_ready)\n ^~~~~~~~~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/Write_Kbd_To_LCD.v:50: Cannot find file containing module: \'async_trap_and_reset\'\n async_trap_and_reset make_kbd_ready_signal(.async_sig(kbd_ready), .outclk(sm_clk), .out_sync_sig(actual_kbd_ready), \n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc,data/full_repos/permissive/86664697/async_trap_and_reset\n data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc,data/full_repos/permissive/86664697/async_trap_and_reset.v\n data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc,data/full_repos/permissive/86664697/async_trap_and_reset.sv\n async_trap_and_reset\n async_trap_and_reset.v\n async_trap_and_reset.sv\n obj_dir/async_trap_and_reset\n obj_dir/async_trap_and_reset.v\n obj_dir/async_trap_and_reset.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 304,133 | module | module Write_Kbd_To_LCD(kbd_data, kbd_ready, reset_kbd_data, start_LCD_writer, LCD_writer_finished, sm_clk, DB, is_command, reset, finish);
input [10:0] kbd_data;
input kbd_ready;
output reset_kbd_data;
output start_LCD_writer;
output finish;
input LCD_writer_finished;
input sm_clk;
output [7:0] DB;
output is_command;
input reset;
assign is_command = 0;
parameter idle = 8'b0000_0000;
parameter start_write_LCD_state = 8'b0101_0001;
parameter wait_write_LCD = 8'b0100_0010;
parameter clear_kbd_data = 8'b0010_0011;
parameter finished = 8'b1000_0101;
reg[7:0] state;
assign start_LCD_writer = state[4];
assign reset_kbd_data = state[5];
assign finish = state[7];
wire DB_sel = state[6];
wire write_Yair_finish;
assign DB = DB_sel ? {kbd_data[2],kbd_data[3],kbd_data[4],kbd_data[5],kbd_data[6],kbd_data[7],kbd_data[8],kbd_data[9]} : 8'h0;
async_trap_and_reset make_kbd_ready_signal(.async_sig(kbd_ready), .outclk(sm_clk), .out_sync_sig(actual_kbd_ready),
.auto_reset(1'b1), .reset(1'b1));
always @(posedge sm_clk or negedge reset)
begin
if (!reset)
begin
state <= idle;
end else
begin
case (state)
idle : if (actual_kbd_ready)
state <= start_write_LCD_state;
else
state <= idle;
start_write_LCD_state : state <= wait_write_LCD;
wait_write_LCD : if (LCD_writer_finished)
state <= clear_kbd_data;
else
state <= wait_write_LCD;
clear_kbd_data : state <= finished;
finished : state <= idle;
endcase
end
end
endmodule | module Write_Kbd_To_LCD(kbd_data, kbd_ready, reset_kbd_data, start_LCD_writer, LCD_writer_finished, sm_clk, DB, is_command, reset, finish); |
input [10:0] kbd_data;
input kbd_ready;
output reset_kbd_data;
output start_LCD_writer;
output finish;
input LCD_writer_finished;
input sm_clk;
output [7:0] DB;
output is_command;
input reset;
assign is_command = 0;
parameter idle = 8'b0000_0000;
parameter start_write_LCD_state = 8'b0101_0001;
parameter wait_write_LCD = 8'b0100_0010;
parameter clear_kbd_data = 8'b0010_0011;
parameter finished = 8'b1000_0101;
reg[7:0] state;
assign start_LCD_writer = state[4];
assign reset_kbd_data = state[5];
assign finish = state[7];
wire DB_sel = state[6];
wire write_Yair_finish;
assign DB = DB_sel ? {kbd_data[2],kbd_data[3],kbd_data[4],kbd_data[5],kbd_data[6],kbd_data[7],kbd_data[8],kbd_data[9]} : 8'h0;
async_trap_and_reset make_kbd_ready_signal(.async_sig(kbd_ready), .outclk(sm_clk), .out_sync_sig(actual_kbd_ready),
.auto_reset(1'b1), .reset(1'b1));
always @(posedge sm_clk or negedge reset)
begin
if (!reset)
begin
state <= idle;
end else
begin
case (state)
idle : if (actual_kbd_ready)
state <= start_write_LCD_state;
else
state <= idle;
start_write_LCD_state : state <= wait_write_LCD;
wait_write_LCD : if (LCD_writer_finished)
state <= clear_kbd_data;
else
state <= wait_write_LCD;
clear_kbd_data : state <= finished;
finished : state <= idle;
endcase
end
end
endmodule | 0 |
138,977 | data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/Write_Kbd_To_Scope_LCD.v | 86,664,697 | Write_Kbd_To_Scope_LCD.v | v | 192 | 110 | [] | [] | [] | [(21, 191)] | null | null | 1: b'%Error: data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/Write_Kbd_To_Scope_LCD.v:59: Cannot find file containing module: \'async_trap_and_reset\'\n async_trap_and_reset make_kbd_ready_signal(.async_sig(kbd_ready), .outclk(sm_clk), \n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc,data/full_repos/permissive/86664697/async_trap_and_reset\n data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc,data/full_repos/permissive/86664697/async_trap_and_reset.v\n data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc,data/full_repos/permissive/86664697/async_trap_and_reset.sv\n async_trap_and_reset\n async_trap_and_reset.v\n async_trap_and_reset.sv\n obj_dir/async_trap_and_reset\n obj_dir/async_trap_and_reset.v\n obj_dir/async_trap_and_reset.sv\n%Warning-WIDTH: data/full_repos/permissive/86664697/lab2_template_de1soc/template_de1soc/Write_Kbd_To_Scope_LCD.v:104: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n : ... In instance Write_Kbd_To_Scope_LCD\n assign debug = {7\'h0,state};\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 304,134 | module | module Write_Kbd_To_Scope_LCD #(parameter scope_info_bytes = 16,
parameter scope_info_bits_per_byte = 8, parameter scope_info_counter_bits = 4)
(kbd_ascii_data,
kbd_ready, reset_kbd_data, sm_clk, reset, finish,
scope_info0, scope_info1, scope_info2,
scope_info3, scope_info4, scope_info5, scope_info6, scope_info7, scope_info8,
scope_info9, scope_info10, scope_info11, scope_info12, scope_info13,
scope_info14, scope_info15, debug, convert_now);
output wire [scope_info_bits_per_byte-1:0] scope_info0, scope_info1, scope_info2,
scope_info3, scope_info4, scope_info5, scope_info6, scope_info7, scope_info8,
scope_info9, scope_info10, scope_info11, scope_info12, scope_info13,
scope_info14, scope_info15;
output convert_now;
input [7:0] kbd_ascii_data;
input kbd_ready;
output reset_kbd_data;
output finish;
input sm_clk;
input reset;
reg [scope_info_bits_per_byte-1:0] scope_info_reg[scope_info_bytes-1:0];
output wire [15:0] debug;
parameter init_state = 10'b000000_0000;
parameter init_scope_LCD_reg = 10'b010000_0001;
parameter idle = 10'b000000_0010;
parameter convert_to_ascii_now = 10'b100000_0111;
parameter LCD_enable_change_state = 10'b000100_0011;
parameter LCD_byte_change_value_state = 10'b000001_0100;
parameter clear_kbd_data = 10'b000010_0101;
parameter finished = 10'b001000_0110;
reg [9:0] state;
wire actual_kbd_ready;
async_trap_and_reset make_kbd_ready_signal(.async_sig(kbd_ready), .outclk(sm_clk),
.out_sync_sig(actual_kbd_ready), .auto_reset(1'b1), .reset(1'b1));
always @(posedge sm_clk or negedge reset)
begin
if (!reset)
begin
state <= idle;
end else
begin
case (state)
init_state: state <= init_scope_LCD_reg;
init_scope_LCD_reg: state <= idle;
idle : if (actual_kbd_ready)
state <= convert_to_ascii_now;
else
state <= idle;
convert_to_ascii_now : state <= LCD_enable_change_state;
LCD_enable_change_state : state <= LCD_byte_change_value_state;
LCD_byte_change_value_state : state <= clear_kbd_data;
clear_kbd_data : state <= finished;
finished : state <= idle;
default: state <= init_state;
endcase
end
end
wire update_scope_LCD_reg = state[4];
assign reset_kbd_data = state[5];
wire change_clk_enable = state[6];
assign finish = state[7];
wire init_clk_enable = state[8];
assign debug = {7'h0,state};
assign convert_now = state[9];
reg [scope_info_bytes-1:0] scope_LCD_reg_clk_enable;
always @(posedge change_clk_enable or posedge init_clk_enable or negedge reset)
begin
if (~reset)
scope_LCD_reg_clk_enable <= 0;
else if (init_clk_enable)
scope_LCD_reg_clk_enable <= 2**(scope_info_bytes-1);
else
scope_LCD_reg_clk_enable <= {scope_LCD_reg_clk_enable[0],scope_LCD_reg_clk_enable[scope_info_bytes-1:1]};
end
genvar LCD_scop_reg_cnt;
generate
for (LCD_scop_reg_cnt=0; LCD_scop_reg_cnt < scope_info_bytes; LCD_scop_reg_cnt=LCD_scop_reg_cnt+1)
begin : gen1
always @ (posedge update_scope_LCD_reg)
begin
if (scope_LCD_reg_clk_enable[LCD_scop_reg_cnt])
begin
scope_info_reg[LCD_scop_reg_cnt] <= kbd_ascii_data;
end
end
end
endgenerate
assign scope_info15 = scope_info_reg[15];
assign scope_info14 = scope_info_reg[14];
assign scope_info13 = scope_info_reg[13];
assign scope_info12 = scope_info_reg[12];
assign scope_info11 = scope_info_reg[11];
assign scope_info10 = scope_info_reg[10];
assign scope_info9 = scope_info_reg[9];
assign scope_info8 = scope_info_reg[8];
assign scope_info7 = scope_info_reg[7];
assign scope_info6 = scope_info_reg[6];
assign scope_info5 = scope_info_reg[5];
assign scope_info4 = scope_info_reg[4];
assign scope_info3 = scope_info_reg[3];
assign scope_info2 = scope_info_reg[2];
assign scope_info1 = scope_info_reg[1];
assign scope_info0 = scope_info_reg[0];
endmodule | module Write_Kbd_To_Scope_LCD #(parameter scope_info_bytes = 16,
parameter scope_info_bits_per_byte = 8, parameter scope_info_counter_bits = 4)
(kbd_ascii_data,
kbd_ready, reset_kbd_data, sm_clk, reset, finish,
scope_info0, scope_info1, scope_info2,
scope_info3, scope_info4, scope_info5, scope_info6, scope_info7, scope_info8,
scope_info9, scope_info10, scope_info11, scope_info12, scope_info13,
scope_info14, scope_info15, debug, convert_now); |
output wire [scope_info_bits_per_byte-1:0] scope_info0, scope_info1, scope_info2,
scope_info3, scope_info4, scope_info5, scope_info6, scope_info7, scope_info8,
scope_info9, scope_info10, scope_info11, scope_info12, scope_info13,
scope_info14, scope_info15;
output convert_now;
input [7:0] kbd_ascii_data;
input kbd_ready;
output reset_kbd_data;
output finish;
input sm_clk;
input reset;
reg [scope_info_bits_per_byte-1:0] scope_info_reg[scope_info_bytes-1:0];
output wire [15:0] debug;
parameter init_state = 10'b000000_0000;
parameter init_scope_LCD_reg = 10'b010000_0001;
parameter idle = 10'b000000_0010;
parameter convert_to_ascii_now = 10'b100000_0111;
parameter LCD_enable_change_state = 10'b000100_0011;
parameter LCD_byte_change_value_state = 10'b000001_0100;
parameter clear_kbd_data = 10'b000010_0101;
parameter finished = 10'b001000_0110;
reg [9:0] state;
wire actual_kbd_ready;
async_trap_and_reset make_kbd_ready_signal(.async_sig(kbd_ready), .outclk(sm_clk),
.out_sync_sig(actual_kbd_ready), .auto_reset(1'b1), .reset(1'b1));
always @(posedge sm_clk or negedge reset)
begin
if (!reset)
begin
state <= idle;
end else
begin
case (state)
init_state: state <= init_scope_LCD_reg;
init_scope_LCD_reg: state <= idle;
idle : if (actual_kbd_ready)
state <= convert_to_ascii_now;
else
state <= idle;
convert_to_ascii_now : state <= LCD_enable_change_state;
LCD_enable_change_state : state <= LCD_byte_change_value_state;
LCD_byte_change_value_state : state <= clear_kbd_data;
clear_kbd_data : state <= finished;
finished : state <= idle;
default: state <= init_state;
endcase
end
end
wire update_scope_LCD_reg = state[4];
assign reset_kbd_data = state[5];
wire change_clk_enable = state[6];
assign finish = state[7];
wire init_clk_enable = state[8];
assign debug = {7'h0,state};
assign convert_now = state[9];
reg [scope_info_bytes-1:0] scope_LCD_reg_clk_enable;
always @(posedge change_clk_enable or posedge init_clk_enable or negedge reset)
begin
if (~reset)
scope_LCD_reg_clk_enable <= 0;
else if (init_clk_enable)
scope_LCD_reg_clk_enable <= 2**(scope_info_bytes-1);
else
scope_LCD_reg_clk_enable <= {scope_LCD_reg_clk_enable[0],scope_LCD_reg_clk_enable[scope_info_bytes-1:1]};
end
genvar LCD_scop_reg_cnt;
generate
for (LCD_scop_reg_cnt=0; LCD_scop_reg_cnt < scope_info_bytes; LCD_scop_reg_cnt=LCD_scop_reg_cnt+1)
begin : gen1
always @ (posedge update_scope_LCD_reg)
begin
if (scope_LCD_reg_clk_enable[LCD_scop_reg_cnt])
begin
scope_info_reg[LCD_scop_reg_cnt] <= kbd_ascii_data;
end
end
end
endgenerate
assign scope_info15 = scope_info_reg[15];
assign scope_info14 = scope_info_reg[14];
assign scope_info13 = scope_info_reg[13];
assign scope_info12 = scope_info_reg[12];
assign scope_info11 = scope_info_reg[11];
assign scope_info10 = scope_info_reg[10];
assign scope_info9 = scope_info_reg[9];
assign scope_info8 = scope_info_reg[8];
assign scope_info7 = scope_info_reg[7];
assign scope_info6 = scope_info_reg[6];
assign scope_info5 = scope_info_reg[5];
assign scope_info4 = scope_info_reg[4];
assign scope_info3 = scope_info_reg[3];
assign scope_info2 = scope_info_reg[2];
assign scope_info1 = scope_info_reg[1];
assign scope_info0 = scope_info_reg[0];
endmodule | 0 |
138,978 | data/full_repos/permissive/86664697/lab2_template_de1soc - Copy/picoblaze_activity_template_de2/template_de2/pacoblaze_instruction_memory.v | 86,664,697 | pacoblaze_instruction_memory.v | v | 17 | 48 | [] | [] | [] | null | line:7: before: "]" | null | 1: b'%Error: Invalid Option: -\n' | 304,140 | module | module pacoblaze_instruction_memory
(
input [9:0] addr,
output [17:0] outdata
);
reg [19:0] memory [1024];
integer index;
initial begin
$readmemh("pracpico.mem",memory);
end
assign outdata = memory[addr];
endmodule | module pacoblaze_instruction_memory
(
input [9:0] addr,
output [17:0] outdata
); |
reg [19:0] memory [1024];
integer index;
initial begin
$readmemh("pracpico.mem",memory);
end
assign outdata = memory[addr];
endmodule | 0 |
138,979 | data/full_repos/permissive/86664697/lab2_template_de1soc - Copy/picoblaze_activity_template_de2/template_de2/Picoblaze_Practice.v | 86,664,697 | Picoblaze_Practice.v | v | 250 | 67 | [] | [] | [] | [(2, 249)] | null | null | 1: b'%Error: Invalid Option: -\n' | 304,141 | module | module Picoblaze_Practice(
CLOCK_50,
LEDG,
LEDR,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_XCK,
I2C_SCLK,
I2C_SDAT,
GPIO_0,
GPIO_1,
LCD_DATA,
LCD_EN,
LCD_ON,
LCD_RS,
LCD_RW
);
input CLOCK_50;
output [8:0] LEDG;
output [17:0] LEDR;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [6:0] HEX4;
output [6:0] HEX5;
output [6:0] HEX6;
output [6:0] HEX7;
inout [7:0] LCD_DATA;
output LCD_EN;
output LCD_ON;
output LCD_RS;
output LCD_RW;
input AUD_ADCDAT;
inout AUD_ADCLRCK;
inout AUD_BCLK;
output AUD_DACDAT;
inout AUD_DACLRCK;
output AUD_XCK;
output I2C_SCLK;
inout I2C_SDAT;
inout [35:0] GPIO_0;
inout [35:0] GPIO_1;
logic CLK_50M;
logic [7:0] LED;
assign CLK_50M = CLOCK_50;
assign LEDG[7:0] = LED[7:0];
wire audio_enable = SW[0];
parameter character_0 =8'h30;
parameter character_1 =8'h31;
parameter character_2 =8'h32;
parameter character_3 =8'h33;
parameter character_4 =8'h34;
parameter character_5 =8'h35;
parameter character_6 =8'h36;
parameter character_7 =8'h37;
parameter character_8 =8'h38;
parameter character_9 =8'h39;
parameter character_A =8'h41;
parameter character_B =8'h42;
parameter character_C =8'h43;
parameter character_D =8'h44;
parameter character_E =8'h45;
parameter character_F =8'h46;
parameter character_G =8'h47;
parameter character_H =8'h48;
parameter character_I =8'h49;
parameter character_J =8'h4A;
parameter character_K =8'h4B;
parameter character_L =8'h4C;
parameter character_M =8'h4D;
parameter character_N =8'h4E;
parameter character_O =8'h4F;
parameter character_P =8'h50;
parameter character_Q =8'h51;
parameter character_R =8'h52;
parameter character_S =8'h53;
parameter character_T =8'h54;
parameter character_U =8'h55;
parameter character_V =8'h56;
parameter character_W =8'h57;
parameter character_X =8'h58;
parameter character_Y =8'h59;
parameter character_Z =8'h5A;
parameter character_lowercase_a= 8'h61;
parameter character_lowercase_b= 8'h62;
parameter character_lowercase_c= 8'h63;
parameter character_lowercase_d= 8'h64;
parameter character_lowercase_e= 8'h65;
parameter character_lowercase_f= 8'h66;
parameter character_lowercase_g= 8'h67;
parameter character_lowercase_h= 8'h68;
parameter character_lowercase_i= 8'h69;
parameter character_lowercase_j= 8'h6A;
parameter character_lowercase_k= 8'h6B;
parameter character_lowercase_l= 8'h6C;
parameter character_lowercase_m= 8'h6D;
parameter character_lowercase_n= 8'h6E;
parameter character_lowercase_o= 8'h6F;
parameter character_lowercase_p= 8'h70;
parameter character_lowercase_q= 8'h71;
parameter character_lowercase_r= 8'h72;
parameter character_lowercase_s= 8'h73;
parameter character_lowercase_t= 8'h74;
parameter character_lowercase_u= 8'h75;
parameter character_lowercase_v= 8'h76;
parameter character_lowercase_w= 8'h77;
parameter character_lowercase_x= 8'h78;
parameter character_lowercase_y= 8'h79;
parameter character_lowercase_z= 8'h7A;
parameter character_colon = 8'h3A;
parameter character_stop = 8'h2E;
parameter character_semi_colon = 8'h3B;
parameter character_minus = 8'h2D;
parameter character_divide = 8'h2F;
parameter character_plus = 8'h2B;
parameter character_comma = 8'h2C;
parameter character_less_than = 8'h3C;
parameter character_greater_than = 8'h3E;
parameter character_equals = 8'h3D;
parameter character_question = 8'h3F;
parameter character_dollar = 8'h24;
parameter character_space=8'h20;
parameter character_exclaim=8'h21;
wire [3:0] sync_SW;
reg CLK_25;
always @(posedge CLK_50M)
begin
CLK_25 <= !CLK_25;
end
doublesync syncsw3(.indata(SW[3]),
.outdata(sync_SW[3]),
.clk(CLK_25),
.reset(1'b1));
doublesync syncsw2(.indata(SW[2]),
.outdata(sync_SW[2]),
.clk(CLK_25),
.reset(1'b1));
doublesync syncsw1(.indata(SW[1]),
.outdata(sync_SW[1]),
.clk(CLK_25),
.reset(1'b1));
doublesync syncsw0(.indata(SW[0]),
.outdata(sync_SW[0]),
.clk(CLK_25),
.reset(1'b1));
assign LCD_ON = 1'b1;
picoblaze_template
#(
.clk_freq_in_hz(25000000)
)
picoblaze_template_inst(
.led(LED[7:0]),
.lcd_d(LCD_DATA),
.lcd_rs(LCD_RS),
.lcd_rw(LCD_RW),
.lcd_e(LCD_EN),
.clk(CLK_25),
.input_data({4'h0,sync_SW[3:0]})
);
endmodule | module Picoblaze_Practice(
CLOCK_50,
LEDG,
LEDR,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_XCK,
I2C_SCLK,
I2C_SDAT,
GPIO_0,
GPIO_1,
LCD_DATA,
LCD_EN,
LCD_ON,
LCD_RS,
LCD_RW
); |
input CLOCK_50;
output [8:0] LEDG;
output [17:0] LEDR;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [6:0] HEX4;
output [6:0] HEX5;
output [6:0] HEX6;
output [6:0] HEX7;
inout [7:0] LCD_DATA;
output LCD_EN;
output LCD_ON;
output LCD_RS;
output LCD_RW;
input AUD_ADCDAT;
inout AUD_ADCLRCK;
inout AUD_BCLK;
output AUD_DACDAT;
inout AUD_DACLRCK;
output AUD_XCK;
output I2C_SCLK;
inout I2C_SDAT;
inout [35:0] GPIO_0;
inout [35:0] GPIO_1;
logic CLK_50M;
logic [7:0] LED;
assign CLK_50M = CLOCK_50;
assign LEDG[7:0] = LED[7:0];
wire audio_enable = SW[0];
parameter character_0 =8'h30;
parameter character_1 =8'h31;
parameter character_2 =8'h32;
parameter character_3 =8'h33;
parameter character_4 =8'h34;
parameter character_5 =8'h35;
parameter character_6 =8'h36;
parameter character_7 =8'h37;
parameter character_8 =8'h38;
parameter character_9 =8'h39;
parameter character_A =8'h41;
parameter character_B =8'h42;
parameter character_C =8'h43;
parameter character_D =8'h44;
parameter character_E =8'h45;
parameter character_F =8'h46;
parameter character_G =8'h47;
parameter character_H =8'h48;
parameter character_I =8'h49;
parameter character_J =8'h4A;
parameter character_K =8'h4B;
parameter character_L =8'h4C;
parameter character_M =8'h4D;
parameter character_N =8'h4E;
parameter character_O =8'h4F;
parameter character_P =8'h50;
parameter character_Q =8'h51;
parameter character_R =8'h52;
parameter character_S =8'h53;
parameter character_T =8'h54;
parameter character_U =8'h55;
parameter character_V =8'h56;
parameter character_W =8'h57;
parameter character_X =8'h58;
parameter character_Y =8'h59;
parameter character_Z =8'h5A;
parameter character_lowercase_a= 8'h61;
parameter character_lowercase_b= 8'h62;
parameter character_lowercase_c= 8'h63;
parameter character_lowercase_d= 8'h64;
parameter character_lowercase_e= 8'h65;
parameter character_lowercase_f= 8'h66;
parameter character_lowercase_g= 8'h67;
parameter character_lowercase_h= 8'h68;
parameter character_lowercase_i= 8'h69;
parameter character_lowercase_j= 8'h6A;
parameter character_lowercase_k= 8'h6B;
parameter character_lowercase_l= 8'h6C;
parameter character_lowercase_m= 8'h6D;
parameter character_lowercase_n= 8'h6E;
parameter character_lowercase_o= 8'h6F;
parameter character_lowercase_p= 8'h70;
parameter character_lowercase_q= 8'h71;
parameter character_lowercase_r= 8'h72;
parameter character_lowercase_s= 8'h73;
parameter character_lowercase_t= 8'h74;
parameter character_lowercase_u= 8'h75;
parameter character_lowercase_v= 8'h76;
parameter character_lowercase_w= 8'h77;
parameter character_lowercase_x= 8'h78;
parameter character_lowercase_y= 8'h79;
parameter character_lowercase_z= 8'h7A;
parameter character_colon = 8'h3A;
parameter character_stop = 8'h2E;
parameter character_semi_colon = 8'h3B;
parameter character_minus = 8'h2D;
parameter character_divide = 8'h2F;
parameter character_plus = 8'h2B;
parameter character_comma = 8'h2C;
parameter character_less_than = 8'h3C;
parameter character_greater_than = 8'h3E;
parameter character_equals = 8'h3D;
parameter character_question = 8'h3F;
parameter character_dollar = 8'h24;
parameter character_space=8'h20;
parameter character_exclaim=8'h21;
wire [3:0] sync_SW;
reg CLK_25;
always @(posedge CLK_50M)
begin
CLK_25 <= !CLK_25;
end
doublesync syncsw3(.indata(SW[3]),
.outdata(sync_SW[3]),
.clk(CLK_25),
.reset(1'b1));
doublesync syncsw2(.indata(SW[2]),
.outdata(sync_SW[2]),
.clk(CLK_25),
.reset(1'b1));
doublesync syncsw1(.indata(SW[1]),
.outdata(sync_SW[1]),
.clk(CLK_25),
.reset(1'b1));
doublesync syncsw0(.indata(SW[0]),
.outdata(sync_SW[0]),
.clk(CLK_25),
.reset(1'b1));
assign LCD_ON = 1'b1;
picoblaze_template
#(
.clk_freq_in_hz(25000000)
)
picoblaze_template_inst(
.led(LED[7:0]),
.lcd_d(LCD_DATA),
.lcd_rs(LCD_RS),
.lcd_rw(LCD_RW),
.lcd_e(LCD_EN),
.clk(CLK_25),
.input_data({4'h0,sync_SW[3:0]})
);
endmodule | 0 |
138,980 | data/full_repos/permissive/86664697/lab2_template_de1soc - Copy/picoblaze_activity_template_de2/template_de2/picoblaze_template.v | 86,664,697 | picoblaze_template.v | v | 183 | 134 | [] | [] | [] | [(4, 182)] | null | null | 1: b'%Error: Invalid Option: -\n' | 304,142 | module | module
picoblaze_template
#(
parameter clk_freq_in_hz = 25000000
) (
output reg[7:0] led,
inout [7:0] lcd_d,
output reg lcd_rs,
output lcd_rw,
output reg lcd_e,
input clk,
input [7:0] input_data
);
wire[9:0] address;
wire[17:0] instruction;
wire[7:0] port_id;
wire[7:0] out_port;
reg[7:0] in_port;
wire write_strobe;
wire read_strobe;
reg interrupt;
wire interrupt_ack;
wire kcpsm3_reset;
reg[26:0] int_count;
reg event_1hz;
reg lcd_rw_control;
reg[7:0] lcd_output_data;
pacoblaze3 led_8seg_kcpsm
(
.address(address),
.instruction(instruction),
.port_id(port_id),
.write_strobe(write_strobe),
.out_port(out_port),
.read_strobe(read_strobe),
.in_port(in_port),
.interrupt(interrupt),
.interrupt_ack(interrupt_ack),
.reset(kcpsm3_reset),
.clk(clk));
wire [19:0] raw_instruction;
pacoblaze_instruction_memory
pacoblaze_instruction_memory_inst(
.addr(address),
.outdata(raw_instruction)
);
always @ (posedge clk)
begin
instruction <= raw_instruction[17:0];
end
assign kcpsm3_reset = 0;
always @ (posedge clk)
begin
if (int_count==(clk_freq_in_hz-1))
begin
int_count <= 0;
event_1hz <= 1;
end else
begin
int_count <= int_count + 1;
event_1hz <= 0;
end
end
always @ (posedge clk or posedge interrupt_ack)
begin
if (interrupt_ack)
interrupt <= 0;
else
begin
if (event_1hz)
interrupt <= 1;
else
interrupt <= interrupt;
end
end
always @ (posedge clk)
begin
case (port_id[7:0])
8'h0: in_port <= input_data;
default: in_port <= 8'bx;
endcase
end
always @ (posedge clk)
begin
if (write_strobe & port_id[7])
led <= out_port;
if (write_strobe & port_id[6])
lcd_output_data <= out_port;
if (write_strobe & port_id[5])
begin
lcd_rs <= out_port[2];
lcd_rw_control <= out_port[1];
lcd_e <= out_port[0];
end
end
assign lcd_rw = lcd_rw_control;
assign lcd_d = lcd_rw_control ? 8'bZZZZZZZZ : lcd_output_data;
endmodule | module
picoblaze_template
#(
parameter clk_freq_in_hz = 25000000
) (
output reg[7:0] led,
inout [7:0] lcd_d,
output reg lcd_rs,
output lcd_rw,
output reg lcd_e,
input clk,
input [7:0] input_data
); |
wire[9:0] address;
wire[17:0] instruction;
wire[7:0] port_id;
wire[7:0] out_port;
reg[7:0] in_port;
wire write_strobe;
wire read_strobe;
reg interrupt;
wire interrupt_ack;
wire kcpsm3_reset;
reg[26:0] int_count;
reg event_1hz;
reg lcd_rw_control;
reg[7:0] lcd_output_data;
pacoblaze3 led_8seg_kcpsm
(
.address(address),
.instruction(instruction),
.port_id(port_id),
.write_strobe(write_strobe),
.out_port(out_port),
.read_strobe(read_strobe),
.in_port(in_port),
.interrupt(interrupt),
.interrupt_ack(interrupt_ack),
.reset(kcpsm3_reset),
.clk(clk));
wire [19:0] raw_instruction;
pacoblaze_instruction_memory
pacoblaze_instruction_memory_inst(
.addr(address),
.outdata(raw_instruction)
);
always @ (posedge clk)
begin
instruction <= raw_instruction[17:0];
end
assign kcpsm3_reset = 0;
always @ (posedge clk)
begin
if (int_count==(clk_freq_in_hz-1))
begin
int_count <= 0;
event_1hz <= 1;
end else
begin
int_count <= int_count + 1;
event_1hz <= 0;
end
end
always @ (posedge clk or posedge interrupt_ack)
begin
if (interrupt_ack)
interrupt <= 0;
else
begin
if (event_1hz)
interrupt <= 1;
else
interrupt <= interrupt;
end
end
always @ (posedge clk)
begin
case (port_id[7:0])
8'h0: in_port <= input_data;
default: in_port <= 8'bx;
endcase
end
always @ (posedge clk)
begin
if (write_strobe & port_id[7])
led <= out_port;
if (write_strobe & port_id[6])
lcd_output_data <= out_port;
if (write_strobe & port_id[5])
begin
lcd_rs <= out_port[2];
lcd_rw_control <= out_port[1];
lcd_e <= out_port[0];
end
end
assign lcd_rw = lcd_rw_control;
assign lcd_d = lcd_rw_control ? 8'bZZZZZZZZ : lcd_output_data;
endmodule | 0 |
138,981 | data/full_repos/permissive/86664697/lab2_template_de1soc - Copy/template_de1soc/displaysecondshex.sv | 86,664,697 | displaysecondshex.sv | sv | 122 | 127 | [] | [] | [] | [(1, 118)] | null | null | 1: b'%Error: Invalid Option: -\n' | 304,175 | module | module displaysecondshex(input logic clk,
input logic direction,
input logic readdatavalid,
input logic [22:0] address,
output logic [6:0] HEX5, HEX4);
parameter number_0 = 7'b1000000;
parameter number_1 = 7'b1111001;
parameter number_2 = 7'b0100100;
parameter number_3 = 7'h0110000;
parameter number_4 = 7'b0011001;
parameter number_5 = 7'b1101101;
parameter number_6 = 7'b0000011;
parameter number_7 = 7'b1111000;
parameter number_8 = 7'b0000000;
parameter number_9 = 7'b0001000;
logic [3:0] sec;
logic [13:0] hex;
logic [15:0] count;
always_ff @(posedge readdatavalid) begin
if (direction) begin
if((count == 22000) && (address != 23'h7FFFF)) begin
sec <= sec + 1;
count <= 0;
end
else if (address == 23'h7FFFF)
sec <= 0;
else
count <= count + 1;
end
else begin
if ((count == 22000) && (address != 0)) begin
sec <= sec - 1;
count <= 0;
end
else if (address == 0)
sec <= 48;
else
count <= count + 1;
end
end
always_comb begin
case (sec)
0: hex = {number_0, number_0};
1: hex = {number_0, number_1};
2: hex = {number_0, number_2};
3: hex = {number_0, number_3};
4: hex = {number_0, number_4};
5: hex = {number_0, number_5};
6: hex = {number_0, number_6};
7: hex = {number_0, number_7};
8: hex = {number_0, number_8};
9: hex = {number_0, number_9};
10: hex = {number_1, number_0};
11: hex = {number_1, number_1};
12: hex = {number_1, number_2};
13: hex = {number_1, number_3};
14: hex = {number_1, number_4};
15: hex = {number_1, number_5};
16: hex = {number_1, number_6};
17: hex = {number_1, number_7};
18: hex = {number_1, number_8};
19: hex = {number_1, number_9};
20: hex = {number_2, number_0};
21: hex = {number_2, number_1};
22: hex = {number_2, number_2};
23: hex = {number_2, number_3};
24: hex = {number_2, number_4};
25: hex = {number_2, number_5};
26: hex = {number_2, number_6};
27: hex = {number_2, number_7};
28: hex = {number_2, number_8};
29: hex = {number_2, number_9};
30: hex = {number_3, number_0};
31: hex = {number_3, number_1};
32: hex = {number_3, number_2};
33: hex = {number_3, number_3};
34: hex = {number_3, number_4};
35: hex = {number_3, number_5};
36: hex = {number_3, number_6};
37: hex = {number_3, number_7};
38: hex = {number_3, number_8};
39: hex = {number_3, number_9};
40: hex = {number_4, number_0};
41: hex = {number_4, number_1};
42: hex = {number_4, number_2};
43: hex = {number_4, number_3};
44: hex = {number_4, number_4};
45: hex = {number_4, number_5};
46: hex = {number_4, number_6};
47: hex = {number_4, number_7};
48: hex = {number_4, number_8};
49: hex = {number_4, number_9};
50: hex = {number_5, number_0};
51: hex = {number_5, number_1};
52: hex = {number_5, number_2};
53: hex = {number_5, number_3};
54: hex = {number_5, number_4};
55: hex = {number_5, number_5};
56: hex = {number_5, number_6};
57: hex = {number_5, number_7};
58: hex = {number_5, number_8};
59: hex = {number_5, number_9};
default: hex = {number_0, number_0};
endcase
end
always_ff @(posedge clk) begin
{HEX5} = hex[13:7];
{HEX4} = hex[6:0];
end
endmodule | module displaysecondshex(input logic clk,
input logic direction,
input logic readdatavalid,
input logic [22:0] address,
output logic [6:0] HEX5, HEX4); |
parameter number_0 = 7'b1000000;
parameter number_1 = 7'b1111001;
parameter number_2 = 7'b0100100;
parameter number_3 = 7'h0110000;
parameter number_4 = 7'b0011001;
parameter number_5 = 7'b1101101;
parameter number_6 = 7'b0000011;
parameter number_7 = 7'b1111000;
parameter number_8 = 7'b0000000;
parameter number_9 = 7'b0001000;
logic [3:0] sec;
logic [13:0] hex;
logic [15:0] count;
always_ff @(posedge readdatavalid) begin
if (direction) begin
if((count == 22000) && (address != 23'h7FFFF)) begin
sec <= sec + 1;
count <= 0;
end
else if (address == 23'h7FFFF)
sec <= 0;
else
count <= count + 1;
end
else begin
if ((count == 22000) && (address != 0)) begin
sec <= sec - 1;
count <= 0;
end
else if (address == 0)
sec <= 48;
else
count <= count + 1;
end
end
always_comb begin
case (sec)
0: hex = {number_0, number_0};
1: hex = {number_0, number_1};
2: hex = {number_0, number_2};
3: hex = {number_0, number_3};
4: hex = {number_0, number_4};
5: hex = {number_0, number_5};
6: hex = {number_0, number_6};
7: hex = {number_0, number_7};
8: hex = {number_0, number_8};
9: hex = {number_0, number_9};
10: hex = {number_1, number_0};
11: hex = {number_1, number_1};
12: hex = {number_1, number_2};
13: hex = {number_1, number_3};
14: hex = {number_1, number_4};
15: hex = {number_1, number_5};
16: hex = {number_1, number_6};
17: hex = {number_1, number_7};
18: hex = {number_1, number_8};
19: hex = {number_1, number_9};
20: hex = {number_2, number_0};
21: hex = {number_2, number_1};
22: hex = {number_2, number_2};
23: hex = {number_2, number_3};
24: hex = {number_2, number_4};
25: hex = {number_2, number_5};
26: hex = {number_2, number_6};
27: hex = {number_2, number_7};
28: hex = {number_2, number_8};
29: hex = {number_2, number_9};
30: hex = {number_3, number_0};
31: hex = {number_3, number_1};
32: hex = {number_3, number_2};
33: hex = {number_3, number_3};
34: hex = {number_3, number_4};
35: hex = {number_3, number_5};
36: hex = {number_3, number_6};
37: hex = {number_3, number_7};
38: hex = {number_3, number_8};
39: hex = {number_3, number_9};
40: hex = {number_4, number_0};
41: hex = {number_4, number_1};
42: hex = {number_4, number_2};
43: hex = {number_4, number_3};
44: hex = {number_4, number_4};
45: hex = {number_4, number_5};
46: hex = {number_4, number_6};
47: hex = {number_4, number_7};
48: hex = {number_4, number_8};
49: hex = {number_4, number_9};
50: hex = {number_5, number_0};
51: hex = {number_5, number_1};
52: hex = {number_5, number_2};
53: hex = {number_5, number_3};
54: hex = {number_5, number_4};
55: hex = {number_5, number_5};
56: hex = {number_5, number_6};
57: hex = {number_5, number_7};
58: hex = {number_5, number_8};
59: hex = {number_5, number_9};
default: hex = {number_0, number_0};
endcase
end
always_ff @(posedge clk) begin
{HEX5} = hex[13:7];
{HEX4} = hex[6:0];
end
endmodule | 0 |
138,982 | data/full_repos/permissive/86664697/lab2_template_de1soc - Copy/template_de1soc/fill_led.sv | 86,664,697 | fill_led.sv | sv | 34 | 44 | [] | [] | [] | [(1, 34)] | null | null | 1: b'%Error: Invalid Option: -\n' | 304,177 | module | module fill_led(input logic [7:0] inputled,
output logic [7:0] outled);
logic [3:0] number;
always
begin
case(inputled)
8'b1XXXXXXX : number = 8;
8'b01XXXXXX : number = 7;
8'b001XXXXX : number = 6;
8'b0001XXXX : number = 5;
8'b00001XXX : number = 4;
8'b000001XX : number = 3;
8'b0000001X : number = 2;
8'b00000001 : number = 1;
default: number = 0;
endcase
end
always
begin
case(number)
8 : outled = 8'b11111111;
7 : outled = 8'b11111110;
6 : outled = 8'b11111100;
5 : outled = 8'b11111000;
4 : outled = 8'b11110000;
3 : outled = 8'b11100000;
2 : outled = 8'b11000000;
1 : outled = 8'b10000000;
default: outled = 8'b00000000;
endcase
end
endmodule | module fill_led(input logic [7:0] inputled,
output logic [7:0] outled); |
logic [3:0] number;
always
begin
case(inputled)
8'b1XXXXXXX : number = 8;
8'b01XXXXXX : number = 7;
8'b001XXXXX : number = 6;
8'b0001XXXX : number = 5;
8'b00001XXX : number = 4;
8'b000001XX : number = 3;
8'b0000001X : number = 2;
8'b00000001 : number = 1;
default: number = 0;
endcase
end
always
begin
case(number)
8 : outled = 8'b11111111;
7 : outled = 8'b11111110;
6 : outled = 8'b11111100;
5 : outled = 8'b11111000;
4 : outled = 8'b11110000;
3 : outled = 8'b11100000;
2 : outled = 8'b11000000;
1 : outled = 8'b10000000;
default: outled = 8'b00000000;
endcase
end
endmodule | 0 |
138,983 | data/full_repos/permissive/86664697/lab2_template_de1soc - Copy/template_de1soc/simple_ipod_solution.v | 86,664,697 | simple_ipod_solution.v | v | 736 | 134 | [] | [] | [] | null | line:417: before: "," | null | 1: b'%Error: Invalid Option: -\n' | 304,187 | module | module simple_ipod_solution(
CLOCK_50,
LEDR,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_XCK,
FPGA_I2C_SCLK,
FPGA_I2C_SDAT,
PS2_CLK,
PS2_DAT,
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_LDQM,
DRAM_UDQM,
DRAM_RAS_N,
DRAM_WE_N,
GPIO_0,
GPIO_1
);
`define zero_pad(width,signal) {{((width)-$size(signal)){1'b0}},(signal)}
input CLOCK_50;
output [9:0] LEDR;
input [3:0] KEY;
input [9:0] SW;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [6:0] HEX4;
output [6:0] HEX5;
input AUD_ADCDAT;
inout AUD_ADCLRCK;
inout AUD_BCLK;
output AUD_DACDAT;
inout AUD_DACLRCK;
output AUD_XCK;
output FPGA_I2C_SCLK;
inout FPGA_I2C_SDAT;
inout PS2_CLK;
inout PS2_DAT;
inout [35:0] GPIO_0;
inout [35:0] GPIO_1;
output [12:0] DRAM_ADDR;
output [1:0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [15:0] DRAM_DQ;
output DRAM_LDQM;
output DRAM_UDQM;
output DRAM_RAS_N;
output DRAM_WE_N;
logic CLK_50M;
logic [9:0] LED;
assign CLK_50M = CLOCK_50;
assign LEDR[9:0] = LED[9:0];
parameter character_0 =8'h30;
parameter character_1 =8'h31;
parameter character_2 =8'h32;
parameter character_3 =8'h33;
parameter character_4 =8'h34;
parameter character_5 =8'h35;
parameter character_6 =8'h36;
parameter character_7 =8'h37;
parameter character_8 =8'h38;
parameter character_9 =8'h39;
parameter character_A =8'h41;
parameter character_B =8'h42;
parameter character_C =8'h43;
parameter character_D =8'h44;
parameter character_E =8'h45;
parameter character_F =8'h46;
parameter character_G =8'h47;
parameter character_H =8'h48;
parameter character_I =8'h49;
parameter character_J =8'h4A;
parameter character_K =8'h4B;
parameter character_L =8'h4C;
parameter character_M =8'h4D;
parameter character_N =8'h4E;
parameter character_O =8'h4F;
parameter character_P =8'h50;
parameter character_Q =8'h51;
parameter character_R =8'h52;
parameter character_S =8'h53;
parameter character_T =8'h54;
parameter character_U =8'h55;
parameter character_V =8'h56;
parameter character_W =8'h57;
parameter character_X =8'h58;
parameter character_Y =8'h59;
parameter character_Z =8'h5A;
parameter character_lowercase_a= 8'h61;
parameter character_lowercase_b= 8'h62;
parameter character_lowercase_c= 8'h63;
parameter character_lowercase_d= 8'h64;
parameter character_lowercase_e= 8'h65;
parameter character_lowercase_f= 8'h66;
parameter character_lowercase_g= 8'h67;
parameter character_lowercase_h= 8'h68;
parameter character_lowercase_i= 8'h69;
parameter character_lowercase_j= 8'h6A;
parameter character_lowercase_k= 8'h6B;
parameter character_lowercase_l= 8'h6C;
parameter character_lowercase_m= 8'h6D;
parameter character_lowercase_n= 8'h6E;
parameter character_lowercase_o= 8'h6F;
parameter character_lowercase_p= 8'h70;
parameter character_lowercase_q= 8'h71;
parameter character_lowercase_r= 8'h72;
parameter character_lowercase_s= 8'h73;
parameter character_lowercase_t= 8'h74;
parameter character_lowercase_u= 8'h75;
parameter character_lowercase_v= 8'h76;
parameter character_lowercase_w= 8'h77;
parameter character_lowercase_x= 8'h78;
parameter character_lowercase_y= 8'h79;
parameter character_lowercase_z= 8'h7A;
parameter character_colon = 8'h3A;
parameter character_stop = 8'h2E;
parameter character_semi_colon = 8'h3B;
parameter character_minus = 8'h2D;
parameter character_divide = 8'h2F;
parameter character_plus = 8'h2B;
parameter character_comma = 8'h2C;
parameter character_less_than = 8'h3C;
parameter character_greater_than = 8'h3E;
parameter character_equals = 8'h3D;
parameter character_question = 8'h3F;
parameter character_dollar = 8'h24;
parameter character_space=8'h20;
parameter character_exclaim=8'h21;
wire Clock_1KHz, Clock_1Hz;
wire Sample_Clk_Signal;
wire [8:0] speed_adjust;
wire [15:0] data;
wire reset, direction, pause, clock_22KHZ;
clock_divider clock22Khz(
.inclock(CLK_50M),
.div_clock_count(1136 + speed_adjust),
.outclock(clock_22KHZ)
);
flash_fsm flash(
.clock50MHZ(CLK_50M),
.clock22KHZ(clock_22KHZ),
.read_valid(flash_mem_readdatavalid),
.wait_request(),
.reset(reset),
.pause(pause),
.direction(direction),
.read_data(flash_mem_readdata),
.read(flash_mem_read),
.byte_enable(flash_mem_byteenable),
.data_out(data),
.address(flash_mem_address)
);
keyboard_controller keyboard(
.clock(CLK_50M),
.reset(SW[0]),
.pressed_key(kbd_received_ascii_code),
.direction(direction),
.pause(pause),
.restart(reset)
);
speed change_speed(
.clock(CLK_50M),
.faster(speed_down_event),
.slower(speed_up_event),
.default_speed(speed_reset_event),
.adjust(speed_adjust)
);
wire CLK_25;
always @(posedge CLK_50M)
begin
CLK_25 <= !CLK_25;
end
picoblaze_template
#(
.clk_freq_in_hz(25000000)
)
picoblaze_template_inst(
.led({LED[2], LED[3], LED[4], LED[5], LED[6] ,LED[7], LED[8], LED[9]}),
.led0(LED[0]),
.clk(CLK_25),
.input_data(data[15:8]),
.interrup(flash_mem_readdatavalid)
);
displaysecondshex hexx(.clk(CLK_50M),
.direction(direction),
.readdatavalid(flash_mem_readdatavalid),
.address(flash_mem_address),
.HEX5(HEX5),
.HEX4(HEX4)
);
wire flash_mem_read;
wire flash_mem_waitrequest;
wire [22:0] flash_mem_address;
wire [31:0] flash_mem_readdata;
wire flash_mem_readdatavalid;
wire [3:0] flash_mem_byteenable;
flash flash_inst (
.clk_clk (CLK_50M),
.reset_reset_n (1'b1),
.flash_mem_write (1'b0),
.flash_mem_burstcount (1'b1),
.flash_mem_waitrequest (flash_mem_waitrequest),
.flash_mem_read (flash_mem_read),
.flash_mem_address (flash_mem_address),
.flash_mem_writedata (32'b0),
.flash_mem_readdata (flash_mem_readdata),
.flash_mem_readdatavalid (flash_mem_readdatavalid),
.flash_mem_byteenable (flash_mem_byteenable)
);
assign Sample_Clk_Signal = Clock_1KHz;
wire [7:0] audio_data = data[15:8];
wire ps2c, ps2d;
wire kbd_data_ready, Kbd_to_LCD_finish;
doublesync ps2c_doublsync
(.indata(PS2_CLK),
.outdata(ps2c),
.clk(CLK_50M),
.reset(1'b1));
doublesync ps2d_doublsync
(.indata(PS2_DAT),
.outdata(ps2d),
.clk(CLK_50M),
.reset(1'b1));
wire reset_kbd_data;
(* KEEP = "TRUE" *) wire conv_now_ignore_timing;
wire [7:0] kbd_received_ascii_code, kbd_scan_code;
Kbd_ctrl Kbd_Controller(
.kbd_clk(ps2c),
.kbd_data(ps2d),
.clk(CLK_50M),
.scan_code(kbd_scan_code),
.reset_kbd_reg(~reset_kbd_data),
.data_ready(kbd_data_ready)
);
key2ascii kbd2ascii(
.key_code(kbd_scan_code),
.ascii_code(kbd_received_ascii_code),
.clk(conv_now_ignore_timing)
);
parameter scope_info_bytes = 16;
parameter scope_info_bits_per_byte = 8;
wire [15:0] write_kbd_debug;
wire [scope_info_bits_per_byte-1:0] scope_info0, scope_info1, scope_info2,
scope_info3, scope_info4, scope_info5, scope_info6, scope_info7, scope_info8,
scope_info9, scope_info10, scope_info11, scope_info12, scope_info13,
scope_info14, scope_info15;
Write_Kbd_To_Scope_LCD Write_Kbd_To_LCD1
(.kbd_ascii_data(kbd_received_ascii_code),
.kbd_ready(kbd_data_ready), .reset_kbd_data(reset_kbd_data),
.sm_clk(CLK_50M), .reset(1'b1),
.finish(Kbd_to_LCD_finish),
.scope_info0(scope_info0),
.scope_info1(scope_info1),
.scope_info2(scope_info2),
.scope_info3(scope_info3),
.scope_info4(scope_info4),
.scope_info5(scope_info5),
.scope_info6(scope_info6),
.scope_info7(scope_info7),
.scope_info8(scope_info8),
.scope_info9(scope_info9),
.scope_info10(scope_info10),
.scope_info11(scope_info11),
.scope_info12(scope_info12),
.scope_info13(scope_info13),
.scope_info14(scope_info14),
.scope_info15(scope_info15),
.debug(write_kbd_debug),
.convert_now(conv_now_ignore_timing)
);
wire allow_run_LCD_scope;
wire [15:0] scope_channelA, scope_channelB;
(* keep = 1, preserve = 1 *)wire scope_clk;
reg user_scope_enable_trigger;
wire user_scope_enable;
wire user_scope_enable_trigger_path0, user_scope_enable_trigger_path1;
wire scope_enable_source = SW[8];
wire choose_LCD_or_SCOPE = SW[9];
doublesync user_scope_enable_sync1(.indata(scope_enable_source),
.outdata(user_scope_enable),
.clk(CLK_50M),
.reset(1'b1));
Generate_Arbitrary_Divided_Clk32
Generate_LCD_scope_Clk(
.inclk(CLK_50M),
.outclk(scope_clk),
.outclk_Not(),
.div_clk_count(scope_sampling_clock_count),
.Reset(1'h1));
(* keep = 1, preserve = 1 *) logic ScopeChannelASignal;
(* keep = 1, preserve = 1 *) logic ScopeChannelBSignal;
assign ScopeChannelASignal = Sample_Clk_Signal;
assign ScopeChannelBSignal = SW[1];
scope_capture LCD_scope_channelA(
.clk(scope_clk),
.the_signal(ScopeChannelASignal),
.capture_enable(allow_run_LCD_scope & user_scope_enable),
.captured_data(scope_channelA),
.reset(1'b1));
scope_capture LCD_scope_channelB
(
.clk(scope_clk),
.the_signal(ScopeChannelBSignal),
.capture_enable(allow_run_LCD_scope & user_scope_enable),
.captured_data(scope_channelB),
.reset(1'b1));
LCD_Scope_Encapsulated_pacoblaze_wrapper LCD_LED_scope(
.lcd_d(GPIO_0[7:0]),
.lcd_rs(GPIO_0[8]),
.lcd_rw(GPIO_0[9]),
.lcd_e(GPIO_0[10]),
.clk(CLK_50M),
.InH(8'hAA),
.InG(8'hBB),
.InF(8'h01),
.InE(8'h23),
.InD(8'h45),
.InC(8'h67),
.InB(8'h89),
.InA(8'h00),
.InfoH({scope_info15,scope_info14}),
.InfoG({scope_info13,scope_info12}),
.InfoF({scope_info11,scope_info10}),
.InfoE({scope_info9,scope_info8}),
.InfoD({scope_info7,scope_info6}),
.InfoC({scope_info5,scope_info4}),
.InfoB({scope_info3,scope_info2}),
.InfoA({scope_info1,scope_info0}),
.choose_scope_or_LCD(choose_LCD_or_SCOPE),
.scope_channelA(scope_channelA),
.scope_channelB(scope_channelB),
.ScopeInfoA({character_1,character_K,character_H,character_lowercase_z}),
.ScopeInfoB({character_S,character_W,character_1,character_space}),
.enable_scope(allow_run_LCD_scope)
);
wire speed_up_event, speed_down_event;
Generate_Arbitrary_Divided_Clk32
Gen_1KHz_clk
(
.inclk(CLK_50M),
.outclk(Clock_1KHz),
.outclk_Not(),
.div_clk_count(32'h61A6),
.Reset(1'h1));
wire speed_up_raw;
wire speed_down_raw;
doublesync
key0_doublsync
(.indata(!KEY[0]),
.outdata(speed_up_raw),
.clk(Clock_1KHz),
.reset(1'b1));
doublesync
key1_doublsync
(.indata(!KEY[1]),
.outdata(speed_down_raw),
.clk(Clock_1KHz),
.reset(1'b1));
parameter num_updown_events_per_sec = 10;
parameter num_1KHZ_clocks_between_updown_events = 1000/num_updown_events_per_sec;
reg [15:0] updown_counter = 0;
always @(posedge Clock_1KHz)
begin
if (updown_counter >= num_1KHZ_clocks_between_updown_events)
begin
if (speed_up_raw)
begin
speed_up_event_trigger <= 1;
end
if (speed_down_raw)
begin
speed_down_event_trigger <= 1;
end
updown_counter <= 0;
end
else
begin
updown_counter <= updown_counter + 1;
speed_up_event_trigger <=0;
speed_down_event_trigger <= 0;
end
end
wire speed_up_event_trigger;
wire speed_down_event_trigger;
async_trap_and_reset_gen_1_pulse
make_speedup_pulse
(
.async_sig(speed_up_event_trigger),
.outclk(CLK_50M),
.out_sync_sig(speed_up_event),
.auto_reset(1'b1),
.reset(1'b1)
);
async_trap_and_reset_gen_1_pulse
make_speedown_pulse
(
.async_sig(speed_down_event_trigger),
.outclk(CLK_50M),
.out_sync_sig(speed_down_event),
.auto_reset(1'b1),
.reset(1'b1)
);
wire speed_reset_event;
doublesync
key2_doublsync
(.indata(!KEY[2]),
.outdata(speed_reset_event),
.clk(CLK_50M),
.reset(1'b1));
parameter oscilloscope_speed_step = 100;
wire [15:0] speed_control_val;
speed_reg_control
speed_reg_control_inst
(
.clk(CLK_50M),
.up_event(speed_up_event),
.down_event(speed_down_event),
.reset_event(speed_reset_event),
.speed_control_val(speed_control_val)
);
logic [15:0] scope_sampling_clock_count;
parameter [15:0] default_scope_sampling_clock_count = 12499;
always @ (posedge CLK_50M)
begin
scope_sampling_clock_count <= default_scope_sampling_clock_count+{{16{speed_control_val[15]}},speed_control_val};
end
logic [7:0] Seven_Seg_Val[5:0];
logic [3:0] Seven_Seg_Data[5:0];
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst0(.ssOut(Seven_Seg_Val[0]), .nIn(Seven_Seg_Data[0]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst1(.ssOut(Seven_Seg_Val[1]), .nIn(Seven_Seg_Data[1]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst2(.ssOut(Seven_Seg_Val[2]), .nIn(Seven_Seg_Data[2]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst3(.ssOut(Seven_Seg_Val[3]), .nIn(Seven_Seg_Data[3]));
assign HEX0 = Seven_Seg_Val[0];
assign HEX1 = Seven_Seg_Val[1];
assign HEX2 = Seven_Seg_Val[2];
assign HEX3 = Seven_Seg_Val[3];
wire Clock_2Hz;
Generate_Arbitrary_Divided_Clk32
Gen_2Hz_clk
(.inclk(CLK_50M),
.outclk(Clock_2Hz),
.outclk_Not(),
.div_clk_count(32'h17D7840 >> 1),
.Reset(1'h1)
);
logic [23:0] actual_7seg_output;
reg [23:0] regd_actual_7seg_output;
always @(posedge Clock_2Hz)
begin
regd_actual_7seg_output <= actual_7seg_output;
Clock_1Hz <= ~Clock_1Hz;
end
assign Seven_Seg_Data[0] = regd_actual_7seg_output[3:0];
assign Seven_Seg_Data[1] = regd_actual_7seg_output[7:4];
assign Seven_Seg_Data[2] = regd_actual_7seg_output[11:8];
assign Seven_Seg_Data[3] = regd_actual_7seg_output[15:12];
assign Seven_Seg_Data[4] = regd_actual_7seg_output[19:16];
assign Seven_Seg_Data[5] = regd_actual_7seg_output[23:20];
assign actual_7seg_output = scope_sampling_clock_count;
wire [$size(audio_data)-1:0] actual_audio_data_left, actual_audio_data_right;
wire audio_left_clock, audio_right_clock;
to_slow_clk_interface
interface_actual_audio_data_right
(.indata(audio_data),
.outdata(actual_audio_data_right),
.inclk(CLK_50M),
.outclk(audio_right_clock));
to_slow_clk_interface
interface_actual_audio_data_left
(.indata(audio_data),
.outdata(actual_audio_data_left),
.inclk(CLK_50M),
.outclk(audio_left_clock));
audio_controller
audio_control(
.iCLK_50(CLK_50M),
.iCLK_28(),
.I2C_SDAT(FPGA_I2C_SDAT),
.oI2C_SCLK(FPGA_I2C_SCLK),
.AUD_ADCLRCK(AUD_ADCLRCK),
.iAUD_ADCDAT(AUD_ADCDAT),
.AUD_DACLRCK(AUD_DACLRCK),
.oAUD_DACDAT(AUD_DACDAT),
.AUD_BCLK(AUD_BCLK),
.oAUD_XCK(AUD_XCK),
.audio_outL({actual_audio_data_left,8'b1}),
.audio_outR({actual_audio_data_right,8'b1}),
.audio_right_clock(audio_right_clock),
.audio_left_clock(audio_left_clock)
);
endmodule | module simple_ipod_solution(
CLOCK_50,
LEDR,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_XCK,
FPGA_I2C_SCLK,
FPGA_I2C_SDAT,
PS2_CLK,
PS2_DAT,
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_LDQM,
DRAM_UDQM,
DRAM_RAS_N,
DRAM_WE_N,
GPIO_0,
GPIO_1
); |
`define zero_pad(width,signal) {{((width)-$size(signal)){1'b0}},(signal)}
input CLOCK_50;
output [9:0] LEDR;
input [3:0] KEY;
input [9:0] SW;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [6:0] HEX4;
output [6:0] HEX5;
input AUD_ADCDAT;
inout AUD_ADCLRCK;
inout AUD_BCLK;
output AUD_DACDAT;
inout AUD_DACLRCK;
output AUD_XCK;
output FPGA_I2C_SCLK;
inout FPGA_I2C_SDAT;
inout PS2_CLK;
inout PS2_DAT;
inout [35:0] GPIO_0;
inout [35:0] GPIO_1;
output [12:0] DRAM_ADDR;
output [1:0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [15:0] DRAM_DQ;
output DRAM_LDQM;
output DRAM_UDQM;
output DRAM_RAS_N;
output DRAM_WE_N;
logic CLK_50M;
logic [9:0] LED;
assign CLK_50M = CLOCK_50;
assign LEDR[9:0] = LED[9:0];
parameter character_0 =8'h30;
parameter character_1 =8'h31;
parameter character_2 =8'h32;
parameter character_3 =8'h33;
parameter character_4 =8'h34;
parameter character_5 =8'h35;
parameter character_6 =8'h36;
parameter character_7 =8'h37;
parameter character_8 =8'h38;
parameter character_9 =8'h39;
parameter character_A =8'h41;
parameter character_B =8'h42;
parameter character_C =8'h43;
parameter character_D =8'h44;
parameter character_E =8'h45;
parameter character_F =8'h46;
parameter character_G =8'h47;
parameter character_H =8'h48;
parameter character_I =8'h49;
parameter character_J =8'h4A;
parameter character_K =8'h4B;
parameter character_L =8'h4C;
parameter character_M =8'h4D;
parameter character_N =8'h4E;
parameter character_O =8'h4F;
parameter character_P =8'h50;
parameter character_Q =8'h51;
parameter character_R =8'h52;
parameter character_S =8'h53;
parameter character_T =8'h54;
parameter character_U =8'h55;
parameter character_V =8'h56;
parameter character_W =8'h57;
parameter character_X =8'h58;
parameter character_Y =8'h59;
parameter character_Z =8'h5A;
parameter character_lowercase_a= 8'h61;
parameter character_lowercase_b= 8'h62;
parameter character_lowercase_c= 8'h63;
parameter character_lowercase_d= 8'h64;
parameter character_lowercase_e= 8'h65;
parameter character_lowercase_f= 8'h66;
parameter character_lowercase_g= 8'h67;
parameter character_lowercase_h= 8'h68;
parameter character_lowercase_i= 8'h69;
parameter character_lowercase_j= 8'h6A;
parameter character_lowercase_k= 8'h6B;
parameter character_lowercase_l= 8'h6C;
parameter character_lowercase_m= 8'h6D;
parameter character_lowercase_n= 8'h6E;
parameter character_lowercase_o= 8'h6F;
parameter character_lowercase_p= 8'h70;
parameter character_lowercase_q= 8'h71;
parameter character_lowercase_r= 8'h72;
parameter character_lowercase_s= 8'h73;
parameter character_lowercase_t= 8'h74;
parameter character_lowercase_u= 8'h75;
parameter character_lowercase_v= 8'h76;
parameter character_lowercase_w= 8'h77;
parameter character_lowercase_x= 8'h78;
parameter character_lowercase_y= 8'h79;
parameter character_lowercase_z= 8'h7A;
parameter character_colon = 8'h3A;
parameter character_stop = 8'h2E;
parameter character_semi_colon = 8'h3B;
parameter character_minus = 8'h2D;
parameter character_divide = 8'h2F;
parameter character_plus = 8'h2B;
parameter character_comma = 8'h2C;
parameter character_less_than = 8'h3C;
parameter character_greater_than = 8'h3E;
parameter character_equals = 8'h3D;
parameter character_question = 8'h3F;
parameter character_dollar = 8'h24;
parameter character_space=8'h20;
parameter character_exclaim=8'h21;
wire Clock_1KHz, Clock_1Hz;
wire Sample_Clk_Signal;
wire [8:0] speed_adjust;
wire [15:0] data;
wire reset, direction, pause, clock_22KHZ;
clock_divider clock22Khz(
.inclock(CLK_50M),
.div_clock_count(1136 + speed_adjust),
.outclock(clock_22KHZ)
);
flash_fsm flash(
.clock50MHZ(CLK_50M),
.clock22KHZ(clock_22KHZ),
.read_valid(flash_mem_readdatavalid),
.wait_request(),
.reset(reset),
.pause(pause),
.direction(direction),
.read_data(flash_mem_readdata),
.read(flash_mem_read),
.byte_enable(flash_mem_byteenable),
.data_out(data),
.address(flash_mem_address)
);
keyboard_controller keyboard(
.clock(CLK_50M),
.reset(SW[0]),
.pressed_key(kbd_received_ascii_code),
.direction(direction),
.pause(pause),
.restart(reset)
);
speed change_speed(
.clock(CLK_50M),
.faster(speed_down_event),
.slower(speed_up_event),
.default_speed(speed_reset_event),
.adjust(speed_adjust)
);
wire CLK_25;
always @(posedge CLK_50M)
begin
CLK_25 <= !CLK_25;
end
picoblaze_template
#(
.clk_freq_in_hz(25000000)
)
picoblaze_template_inst(
.led({LED[2], LED[3], LED[4], LED[5], LED[6] ,LED[7], LED[8], LED[9]}),
.led0(LED[0]),
.clk(CLK_25),
.input_data(data[15:8]),
.interrup(flash_mem_readdatavalid)
);
displaysecondshex hexx(.clk(CLK_50M),
.direction(direction),
.readdatavalid(flash_mem_readdatavalid),
.address(flash_mem_address),
.HEX5(HEX5),
.HEX4(HEX4)
);
wire flash_mem_read;
wire flash_mem_waitrequest;
wire [22:0] flash_mem_address;
wire [31:0] flash_mem_readdata;
wire flash_mem_readdatavalid;
wire [3:0] flash_mem_byteenable;
flash flash_inst (
.clk_clk (CLK_50M),
.reset_reset_n (1'b1),
.flash_mem_write (1'b0),
.flash_mem_burstcount (1'b1),
.flash_mem_waitrequest (flash_mem_waitrequest),
.flash_mem_read (flash_mem_read),
.flash_mem_address (flash_mem_address),
.flash_mem_writedata (32'b0),
.flash_mem_readdata (flash_mem_readdata),
.flash_mem_readdatavalid (flash_mem_readdatavalid),
.flash_mem_byteenable (flash_mem_byteenable)
);
assign Sample_Clk_Signal = Clock_1KHz;
wire [7:0] audio_data = data[15:8];
wire ps2c, ps2d;
wire kbd_data_ready, Kbd_to_LCD_finish;
doublesync ps2c_doublsync
(.indata(PS2_CLK),
.outdata(ps2c),
.clk(CLK_50M),
.reset(1'b1));
doublesync ps2d_doublsync
(.indata(PS2_DAT),
.outdata(ps2d),
.clk(CLK_50M),
.reset(1'b1));
wire reset_kbd_data;
(* KEEP = "TRUE" *) wire conv_now_ignore_timing;
wire [7:0] kbd_received_ascii_code, kbd_scan_code;
Kbd_ctrl Kbd_Controller(
.kbd_clk(ps2c),
.kbd_data(ps2d),
.clk(CLK_50M),
.scan_code(kbd_scan_code),
.reset_kbd_reg(~reset_kbd_data),
.data_ready(kbd_data_ready)
);
key2ascii kbd2ascii(
.key_code(kbd_scan_code),
.ascii_code(kbd_received_ascii_code),
.clk(conv_now_ignore_timing)
);
parameter scope_info_bytes = 16;
parameter scope_info_bits_per_byte = 8;
wire [15:0] write_kbd_debug;
wire [scope_info_bits_per_byte-1:0] scope_info0, scope_info1, scope_info2,
scope_info3, scope_info4, scope_info5, scope_info6, scope_info7, scope_info8,
scope_info9, scope_info10, scope_info11, scope_info12, scope_info13,
scope_info14, scope_info15;
Write_Kbd_To_Scope_LCD Write_Kbd_To_LCD1
(.kbd_ascii_data(kbd_received_ascii_code),
.kbd_ready(kbd_data_ready), .reset_kbd_data(reset_kbd_data),
.sm_clk(CLK_50M), .reset(1'b1),
.finish(Kbd_to_LCD_finish),
.scope_info0(scope_info0),
.scope_info1(scope_info1),
.scope_info2(scope_info2),
.scope_info3(scope_info3),
.scope_info4(scope_info4),
.scope_info5(scope_info5),
.scope_info6(scope_info6),
.scope_info7(scope_info7),
.scope_info8(scope_info8),
.scope_info9(scope_info9),
.scope_info10(scope_info10),
.scope_info11(scope_info11),
.scope_info12(scope_info12),
.scope_info13(scope_info13),
.scope_info14(scope_info14),
.scope_info15(scope_info15),
.debug(write_kbd_debug),
.convert_now(conv_now_ignore_timing)
);
wire allow_run_LCD_scope;
wire [15:0] scope_channelA, scope_channelB;
(* keep = 1, preserve = 1 *)wire scope_clk;
reg user_scope_enable_trigger;
wire user_scope_enable;
wire user_scope_enable_trigger_path0, user_scope_enable_trigger_path1;
wire scope_enable_source = SW[8];
wire choose_LCD_or_SCOPE = SW[9];
doublesync user_scope_enable_sync1(.indata(scope_enable_source),
.outdata(user_scope_enable),
.clk(CLK_50M),
.reset(1'b1));
Generate_Arbitrary_Divided_Clk32
Generate_LCD_scope_Clk(
.inclk(CLK_50M),
.outclk(scope_clk),
.outclk_Not(),
.div_clk_count(scope_sampling_clock_count),
.Reset(1'h1));
(* keep = 1, preserve = 1 *) logic ScopeChannelASignal;
(* keep = 1, preserve = 1 *) logic ScopeChannelBSignal;
assign ScopeChannelASignal = Sample_Clk_Signal;
assign ScopeChannelBSignal = SW[1];
scope_capture LCD_scope_channelA(
.clk(scope_clk),
.the_signal(ScopeChannelASignal),
.capture_enable(allow_run_LCD_scope & user_scope_enable),
.captured_data(scope_channelA),
.reset(1'b1));
scope_capture LCD_scope_channelB
(
.clk(scope_clk),
.the_signal(ScopeChannelBSignal),
.capture_enable(allow_run_LCD_scope & user_scope_enable),
.captured_data(scope_channelB),
.reset(1'b1));
LCD_Scope_Encapsulated_pacoblaze_wrapper LCD_LED_scope(
.lcd_d(GPIO_0[7:0]),
.lcd_rs(GPIO_0[8]),
.lcd_rw(GPIO_0[9]),
.lcd_e(GPIO_0[10]),
.clk(CLK_50M),
.InH(8'hAA),
.InG(8'hBB),
.InF(8'h01),
.InE(8'h23),
.InD(8'h45),
.InC(8'h67),
.InB(8'h89),
.InA(8'h00),
.InfoH({scope_info15,scope_info14}),
.InfoG({scope_info13,scope_info12}),
.InfoF({scope_info11,scope_info10}),
.InfoE({scope_info9,scope_info8}),
.InfoD({scope_info7,scope_info6}),
.InfoC({scope_info5,scope_info4}),
.InfoB({scope_info3,scope_info2}),
.InfoA({scope_info1,scope_info0}),
.choose_scope_or_LCD(choose_LCD_or_SCOPE),
.scope_channelA(scope_channelA),
.scope_channelB(scope_channelB),
.ScopeInfoA({character_1,character_K,character_H,character_lowercase_z}),
.ScopeInfoB({character_S,character_W,character_1,character_space}),
.enable_scope(allow_run_LCD_scope)
);
wire speed_up_event, speed_down_event;
Generate_Arbitrary_Divided_Clk32
Gen_1KHz_clk
(
.inclk(CLK_50M),
.outclk(Clock_1KHz),
.outclk_Not(),
.div_clk_count(32'h61A6),
.Reset(1'h1));
wire speed_up_raw;
wire speed_down_raw;
doublesync
key0_doublsync
(.indata(!KEY[0]),
.outdata(speed_up_raw),
.clk(Clock_1KHz),
.reset(1'b1));
doublesync
key1_doublsync
(.indata(!KEY[1]),
.outdata(speed_down_raw),
.clk(Clock_1KHz),
.reset(1'b1));
parameter num_updown_events_per_sec = 10;
parameter num_1KHZ_clocks_between_updown_events = 1000/num_updown_events_per_sec;
reg [15:0] updown_counter = 0;
always @(posedge Clock_1KHz)
begin
if (updown_counter >= num_1KHZ_clocks_between_updown_events)
begin
if (speed_up_raw)
begin
speed_up_event_trigger <= 1;
end
if (speed_down_raw)
begin
speed_down_event_trigger <= 1;
end
updown_counter <= 0;
end
else
begin
updown_counter <= updown_counter + 1;
speed_up_event_trigger <=0;
speed_down_event_trigger <= 0;
end
end
wire speed_up_event_trigger;
wire speed_down_event_trigger;
async_trap_and_reset_gen_1_pulse
make_speedup_pulse
(
.async_sig(speed_up_event_trigger),
.outclk(CLK_50M),
.out_sync_sig(speed_up_event),
.auto_reset(1'b1),
.reset(1'b1)
);
async_trap_and_reset_gen_1_pulse
make_speedown_pulse
(
.async_sig(speed_down_event_trigger),
.outclk(CLK_50M),
.out_sync_sig(speed_down_event),
.auto_reset(1'b1),
.reset(1'b1)
);
wire speed_reset_event;
doublesync
key2_doublsync
(.indata(!KEY[2]),
.outdata(speed_reset_event),
.clk(CLK_50M),
.reset(1'b1));
parameter oscilloscope_speed_step = 100;
wire [15:0] speed_control_val;
speed_reg_control
speed_reg_control_inst
(
.clk(CLK_50M),
.up_event(speed_up_event),
.down_event(speed_down_event),
.reset_event(speed_reset_event),
.speed_control_val(speed_control_val)
);
logic [15:0] scope_sampling_clock_count;
parameter [15:0] default_scope_sampling_clock_count = 12499;
always @ (posedge CLK_50M)
begin
scope_sampling_clock_count <= default_scope_sampling_clock_count+{{16{speed_control_val[15]}},speed_control_val};
end
logic [7:0] Seven_Seg_Val[5:0];
logic [3:0] Seven_Seg_Data[5:0];
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst0(.ssOut(Seven_Seg_Val[0]), .nIn(Seven_Seg_Data[0]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst1(.ssOut(Seven_Seg_Val[1]), .nIn(Seven_Seg_Data[1]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst2(.ssOut(Seven_Seg_Val[2]), .nIn(Seven_Seg_Data[2]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst3(.ssOut(Seven_Seg_Val[3]), .nIn(Seven_Seg_Data[3]));
assign HEX0 = Seven_Seg_Val[0];
assign HEX1 = Seven_Seg_Val[1];
assign HEX2 = Seven_Seg_Val[2];
assign HEX3 = Seven_Seg_Val[3];
wire Clock_2Hz;
Generate_Arbitrary_Divided_Clk32
Gen_2Hz_clk
(.inclk(CLK_50M),
.outclk(Clock_2Hz),
.outclk_Not(),
.div_clk_count(32'h17D7840 >> 1),
.Reset(1'h1)
);
logic [23:0] actual_7seg_output;
reg [23:0] regd_actual_7seg_output;
always @(posedge Clock_2Hz)
begin
regd_actual_7seg_output <= actual_7seg_output;
Clock_1Hz <= ~Clock_1Hz;
end
assign Seven_Seg_Data[0] = regd_actual_7seg_output[3:0];
assign Seven_Seg_Data[1] = regd_actual_7seg_output[7:4];
assign Seven_Seg_Data[2] = regd_actual_7seg_output[11:8];
assign Seven_Seg_Data[3] = regd_actual_7seg_output[15:12];
assign Seven_Seg_Data[4] = regd_actual_7seg_output[19:16];
assign Seven_Seg_Data[5] = regd_actual_7seg_output[23:20];
assign actual_7seg_output = scope_sampling_clock_count;
wire [$size(audio_data)-1:0] actual_audio_data_left, actual_audio_data_right;
wire audio_left_clock, audio_right_clock;
to_slow_clk_interface
interface_actual_audio_data_right
(.indata(audio_data),
.outdata(actual_audio_data_right),
.inclk(CLK_50M),
.outclk(audio_right_clock));
to_slow_clk_interface
interface_actual_audio_data_left
(.indata(audio_data),
.outdata(actual_audio_data_left),
.inclk(CLK_50M),
.outclk(audio_left_clock));
audio_controller
audio_control(
.iCLK_50(CLK_50M),
.iCLK_28(),
.I2C_SDAT(FPGA_I2C_SDAT),
.oI2C_SCLK(FPGA_I2C_SCLK),
.AUD_ADCLRCK(AUD_ADCLRCK),
.iAUD_ADCDAT(AUD_ADCDAT),
.AUD_DACLRCK(AUD_DACLRCK),
.oAUD_DACDAT(AUD_DACDAT),
.AUD_BCLK(AUD_BCLK),
.oAUD_XCK(AUD_XCK),
.audio_outL({actual_audio_data_left,8'b1}),
.audio_outR({actual_audio_data_right,8'b1}),
.audio_right_clock(audio_right_clock),
.audio_left_clock(audio_left_clock)
);
endmodule | 0 |
138,984 | data/full_repos/permissive/86664697/Lab4/template_de1soc/ksa.sv | 86,664,697 | ksa.sv | sv | 375 | 164 | [] | [] | [] | null | line:67: before: "]" | null | 1: b"%Error: data/full_repos/permissive/86664697/Lab4/template_de1soc/ksa.sv:120: Can't find definition of variable: 'keymax'\n if ( secret_key_24_bit > keymax ) state <= decryption_failed; \n ^~~~~~\n%Error: Exiting due to 1 error(s)\n" | 304,228 | module | module ksa(CLOCK_50,
KEY,
LEDR,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5);
input CLOCK_50;
input [3:0] KEY;
output logic [9:0] LEDR;
output logic [6:0] HEX0;
output logic [6:0] HEX1;
output logic [6:0] HEX2;
output logic [6:0] HEX3;
output logic [6:0] HEX4;
output logic [6:0] HEX5;
logic [4:0] state;
parameter init = 5'b0_0000;
parameter fill_S_memory = 5'b0_0001;
parameter read_SI1 = 5'b0_0010;
parameter SI_read_delay = 5'b0_0011;
parameter read_SI2 = 5'b0_0100;
parameter set_J1 = 5'b0_0101;
parameter set_J2 = 5'b0_0110;
parameter read_SJ1 = 5'b0_0111;
parameter SJ_read_delay = 5'b0_1000;
parameter read_SJ2 = 5'b0_1001;
parameter swap_SI = 5'b0_1010;
parameter swap_SJ = 5'b0_1011;
parameter wait_a_cycle = 5'b0_1100;
parameter swap1_done = 5'b0_1101;
parameter swap2_done = 5'b0_1110;
parameter reset_all = 5'b0_1111;
parameter set_read_SI1 = 5'b1_0000;
parameter set_SI_read_delay = 5'b1_0001;
parameter set_read_SI2 = 5'b1_0010;
parameter read_SF1 = 5'b1_0011;
parameter SF_read_delay = 5'b1_0100;
parameter read_SF2 = 5'b1_0101;
parameter decrypt1 = 5'b1_0110;
parameter decrypt_delay = 5'b1_0111;
parameter decrypt2 = 5'b1_1000;
parameter decrypt3 = 5'b1_1001;
parameter check_decrypt = 5'b1_1010;
parameter increment_key = 5'b1_1011;
parameter read_decryption = 5'b1_1100;
parameter read_decrypt_delay = 5'b1_1101;
parameter decryption_successful = 5'b1_1110;
parameter decryption_failed = 5'b1_1111;
logic [7:0] address, data, q;
logic [7:0] encrypted_address, encrypted_q;
logic [7:0] decrypted_address, decrypted_data, decrypted_q;
logic wren, decrypted_wren;
logic [31:0] i, j, k, f;
logic [31:0] Si_value, Sj_value, Sf_value, encrypt_k, decrypt_k;
byte secret_key [3];
logic [23:0] secret_key_24_bit;
logic decrypt_success, decrypt_failed;
s_memory S(address, CLOCK_50, data, wren, q);
e_memory E(encrypted_address, CLOCK_50, encrypted_q);
d_memory D(decrypted_address, CLOCK_50, decrypted_data, decrypted_wren, decrypted_q);
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst0(.ssOut(HEX0), .nIn(secret_key_24_bit[3:0]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst1(.ssOut(HEX1), .nIn(secret_key_24_bit[7:4]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst2(.ssOut(HEX2), .nIn(secret_key_24_bit[11:8]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst3(.ssOut(HEX3), .nIn(secret_key_24_bit[15:12]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst4(.ssOut(HEX4), .nIn(secret_key_24_bit[19:16]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst5(.ssOut(HEX5), .nIn(secret_key_24_bit[23:20]));
always_ff @(posedge CLOCK_50)
begin
if(KEY[0] == 0) begin
{i,j,k,f,Si_value,Sj_value,decrypt_success,decrypt_failed} <= {32'b0,32'b0,32'b0,32'b0,32'b0,32'b0,1'b0,1'b0};
secret_key_24_bit <= 24'b0;
secret_key[0] <= 8'd0;
secret_key[1] <= 8'd0;
secret_key[2] <= 8'd0;
state <= init;
end
else begin
case (state)
init:
begin
{i,j,k,f,Si_value,Sj_value,decrypt_success,decrypt_failed} <= {32'b0,32'b0,32'b0,32'b0,32'b0,32'b0,1'b0,1'b0};
secret_key_24_bit <= 24'b0;
secret_key[0] <= 8'd0;
secret_key[1] <= 8'd0;
secret_key[2] <= 8'd0;
state <= fill_S_memory;
end
increment_key:
begin
secret_key_24_bit = {secret_key[0], secret_key[1], secret_key[2]};
secret_key_24_bit = secret_key_24_bit + 1'b1;
secret_key[0] <= {2'b00, secret_key_24_bit[21:16]};
secret_key[1] <= secret_key_24_bit[15:8];
secret_key[2] <= secret_key_24_bit[7:0];
if ( secret_key_24_bit > keymax ) state <= decryption_failed;
else state <= fill_S_memory;
end
fill_S_memory:
begin
address <= i;
data <= i;
wren <= 1'b1;
i <= i + 1;
if( i > 255 ) begin
i <= 0;
state <= read_SI1;
end
else state <= fill_S_memory;
end
read_SI1:
begin
address <= i;
wren <= 1'b0;
state <= SI_read_delay;
end
SI_read_delay:
begin
state <= read_SI2;
end
read_SI2:
begin
Si_value <= q;
state <= set_J1;
end
set_J1:
begin
j <= (j + Si_value + secret_key[i % 3]) % 256;
state <= read_SJ1;
end
read_SJ1:
begin
address <= j;
wren <= 1'b0;
state <= SJ_read_delay;
end
SJ_read_delay:
begin
state <= read_SJ2;
end
read_SJ2:
begin
Sj_value <= q;
state <= swap_SJ;
end
swap_SJ:
begin
address <= i;
data <= Sj_value;
wren <= 1'b1;
if(i == 0) state <= wait_a_cycle;
else state <= swap_SI;
end
wait_a_cycle:
begin
state <= swap_SI;
end
swap_SI:
begin
if ( k == 0 )
begin
address <= j;
data <= Si_value;
wren <= 1'b1;
i = i + 1;
if ( i > 255 ) state <= reset_all;
else state <= read_SI1;
end
else if ( k >= 1 )
begin
address <= j;
data <= Si_value;
wren <= 1'b1;
state <= swap2_done;
end
end
reset_all:
begin
{i,j,k,f} <= {32'b0,32'b0,32'b0000_0000_0000_0000_0000_0000_0000_0001,32'b0};
state <= set_read_SI1;
end
set_read_SI1:
begin
i = (i + 1) % 256;
address <= i;
wren <= 1'b0;
state <= set_SI_read_delay;
end
set_SI_read_delay:
begin
state <= set_read_SI2;
end
set_read_SI2:
begin
Si_value <= q;
state <= set_J2;
end
set_J2:
begin
j <= (j + Si_value) % 256;
state <= read_SJ1;
end
swap2_done:
begin
f <= (Si_value + Sj_value) % 256;
state <= read_SF1;
end
read_SF1:
begin
address <= f;
wren <= 1'b0;
state <= SF_read_delay;
end
SF_read_delay:
begin
state <= read_SF2;
end
read_SF2:
begin
Sf_value <= q;
state <= decrypt1;
end
decrypt1:
begin
encrypted_address <= k - 1;
state <= decrypt_delay;
end
decrypt_delay:
begin
state <= decrypt2;
end
decrypt2:
begin
encrypt_k = encrypted_q;
state <= decrypt3;
end
decrypt3:
begin
decrypted_address <= k - 1;
decrypted_data <= Sf_value ^ encrypt_k;
decrypted_wren <= 1'b1;
state <= read_decryption;
end
read_decryption:
begin
decrypted_address <= k - 1;
decrypted_wren <= 1'b0;
state <= read_decrypt_delay;
end
read_decrypt_delay:
begin
state <= check_decrypt;
end
check_decrypt:
begin
if ( (decrypted_q == 8'h20) || ((decrypted_q >= 8'h61) && (decrypted_q <= 8'h7A)) ) begin
k = k + 1;
if ( k > 32 ) state <= decryption_successful;
else state <= set_read_SI1;
end
else
begin
{i,j,k,f,Si_value,Sj_value} <= {32'b0,32'b0,32'b0,32'b0,32'b0,32'b0};
state <= increment_key;
end
end
decryption_successful:
begin
decrypt_success <= 1'b1;
state <= decryption_successful;
end
decryption_failed:
begin
decrypt_failed <= 1'b1;
state <= decryption_failed;
end
endcase
end
end
always_comb
begin
LEDR[9:2] = secret_key_24_bit[23:16];
if (decrypt_success == 1'b1)
begin
LEDR = 1;
end
else
begin
LEDR = 0;
end
if (decrypt_failed == 1'b1) begin
LEDR[1] = 1;
end
else
begin
LEDR[1] = 0;
end
end
endmodule | module ksa(CLOCK_50,
KEY,
LEDR,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5); |
input CLOCK_50;
input [3:0] KEY;
output logic [9:0] LEDR;
output logic [6:0] HEX0;
output logic [6:0] HEX1;
output logic [6:0] HEX2;
output logic [6:0] HEX3;
output logic [6:0] HEX4;
output logic [6:0] HEX5;
logic [4:0] state;
parameter init = 5'b0_0000;
parameter fill_S_memory = 5'b0_0001;
parameter read_SI1 = 5'b0_0010;
parameter SI_read_delay = 5'b0_0011;
parameter read_SI2 = 5'b0_0100;
parameter set_J1 = 5'b0_0101;
parameter set_J2 = 5'b0_0110;
parameter read_SJ1 = 5'b0_0111;
parameter SJ_read_delay = 5'b0_1000;
parameter read_SJ2 = 5'b0_1001;
parameter swap_SI = 5'b0_1010;
parameter swap_SJ = 5'b0_1011;
parameter wait_a_cycle = 5'b0_1100;
parameter swap1_done = 5'b0_1101;
parameter swap2_done = 5'b0_1110;
parameter reset_all = 5'b0_1111;
parameter set_read_SI1 = 5'b1_0000;
parameter set_SI_read_delay = 5'b1_0001;
parameter set_read_SI2 = 5'b1_0010;
parameter read_SF1 = 5'b1_0011;
parameter SF_read_delay = 5'b1_0100;
parameter read_SF2 = 5'b1_0101;
parameter decrypt1 = 5'b1_0110;
parameter decrypt_delay = 5'b1_0111;
parameter decrypt2 = 5'b1_1000;
parameter decrypt3 = 5'b1_1001;
parameter check_decrypt = 5'b1_1010;
parameter increment_key = 5'b1_1011;
parameter read_decryption = 5'b1_1100;
parameter read_decrypt_delay = 5'b1_1101;
parameter decryption_successful = 5'b1_1110;
parameter decryption_failed = 5'b1_1111;
logic [7:0] address, data, q;
logic [7:0] encrypted_address, encrypted_q;
logic [7:0] decrypted_address, decrypted_data, decrypted_q;
logic wren, decrypted_wren;
logic [31:0] i, j, k, f;
logic [31:0] Si_value, Sj_value, Sf_value, encrypt_k, decrypt_k;
byte secret_key [3];
logic [23:0] secret_key_24_bit;
logic decrypt_success, decrypt_failed;
s_memory S(address, CLOCK_50, data, wren, q);
e_memory E(encrypted_address, CLOCK_50, encrypted_q);
d_memory D(decrypted_address, CLOCK_50, decrypted_data, decrypted_wren, decrypted_q);
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst0(.ssOut(HEX0), .nIn(secret_key_24_bit[3:0]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst1(.ssOut(HEX1), .nIn(secret_key_24_bit[7:4]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst2(.ssOut(HEX2), .nIn(secret_key_24_bit[11:8]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst3(.ssOut(HEX3), .nIn(secret_key_24_bit[15:12]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst4(.ssOut(HEX4), .nIn(secret_key_24_bit[19:16]));
SevenSegmentDisplayDecoder SevenSegmentDisplayDecoder_inst5(.ssOut(HEX5), .nIn(secret_key_24_bit[23:20]));
always_ff @(posedge CLOCK_50)
begin
if(KEY[0] == 0) begin
{i,j,k,f,Si_value,Sj_value,decrypt_success,decrypt_failed} <= {32'b0,32'b0,32'b0,32'b0,32'b0,32'b0,1'b0,1'b0};
secret_key_24_bit <= 24'b0;
secret_key[0] <= 8'd0;
secret_key[1] <= 8'd0;
secret_key[2] <= 8'd0;
state <= init;
end
else begin
case (state)
init:
begin
{i,j,k,f,Si_value,Sj_value,decrypt_success,decrypt_failed} <= {32'b0,32'b0,32'b0,32'b0,32'b0,32'b0,1'b0,1'b0};
secret_key_24_bit <= 24'b0;
secret_key[0] <= 8'd0;
secret_key[1] <= 8'd0;
secret_key[2] <= 8'd0;
state <= fill_S_memory;
end
increment_key:
begin
secret_key_24_bit = {secret_key[0], secret_key[1], secret_key[2]};
secret_key_24_bit = secret_key_24_bit + 1'b1;
secret_key[0] <= {2'b00, secret_key_24_bit[21:16]};
secret_key[1] <= secret_key_24_bit[15:8];
secret_key[2] <= secret_key_24_bit[7:0];
if ( secret_key_24_bit > keymax ) state <= decryption_failed;
else state <= fill_S_memory;
end
fill_S_memory:
begin
address <= i;
data <= i;
wren <= 1'b1;
i <= i + 1;
if( i > 255 ) begin
i <= 0;
state <= read_SI1;
end
else state <= fill_S_memory;
end
read_SI1:
begin
address <= i;
wren <= 1'b0;
state <= SI_read_delay;
end
SI_read_delay:
begin
state <= read_SI2;
end
read_SI2:
begin
Si_value <= q;
state <= set_J1;
end
set_J1:
begin
j <= (j + Si_value + secret_key[i % 3]) % 256;
state <= read_SJ1;
end
read_SJ1:
begin
address <= j;
wren <= 1'b0;
state <= SJ_read_delay;
end
SJ_read_delay:
begin
state <= read_SJ2;
end
read_SJ2:
begin
Sj_value <= q;
state <= swap_SJ;
end
swap_SJ:
begin
address <= i;
data <= Sj_value;
wren <= 1'b1;
if(i == 0) state <= wait_a_cycle;
else state <= swap_SI;
end
wait_a_cycle:
begin
state <= swap_SI;
end
swap_SI:
begin
if ( k == 0 )
begin
address <= j;
data <= Si_value;
wren <= 1'b1;
i = i + 1;
if ( i > 255 ) state <= reset_all;
else state <= read_SI1;
end
else if ( k >= 1 )
begin
address <= j;
data <= Si_value;
wren <= 1'b1;
state <= swap2_done;
end
end
reset_all:
begin
{i,j,k,f} <= {32'b0,32'b0,32'b0000_0000_0000_0000_0000_0000_0000_0001,32'b0};
state <= set_read_SI1;
end
set_read_SI1:
begin
i = (i + 1) % 256;
address <= i;
wren <= 1'b0;
state <= set_SI_read_delay;
end
set_SI_read_delay:
begin
state <= set_read_SI2;
end
set_read_SI2:
begin
Si_value <= q;
state <= set_J2;
end
set_J2:
begin
j <= (j + Si_value) % 256;
state <= read_SJ1;
end
swap2_done:
begin
f <= (Si_value + Sj_value) % 256;
state <= read_SF1;
end
read_SF1:
begin
address <= f;
wren <= 1'b0;
state <= SF_read_delay;
end
SF_read_delay:
begin
state <= read_SF2;
end
read_SF2:
begin
Sf_value <= q;
state <= decrypt1;
end
decrypt1:
begin
encrypted_address <= k - 1;
state <= decrypt_delay;
end
decrypt_delay:
begin
state <= decrypt2;
end
decrypt2:
begin
encrypt_k = encrypted_q;
state <= decrypt3;
end
decrypt3:
begin
decrypted_address <= k - 1;
decrypted_data <= Sf_value ^ encrypt_k;
decrypted_wren <= 1'b1;
state <= read_decryption;
end
read_decryption:
begin
decrypted_address <= k - 1;
decrypted_wren <= 1'b0;
state <= read_decrypt_delay;
end
read_decrypt_delay:
begin
state <= check_decrypt;
end
check_decrypt:
begin
if ( (decrypted_q == 8'h20) || ((decrypted_q >= 8'h61) && (decrypted_q <= 8'h7A)) ) begin
k = k + 1;
if ( k > 32 ) state <= decryption_successful;
else state <= set_read_SI1;
end
else
begin
{i,j,k,f,Si_value,Sj_value} <= {32'b0,32'b0,32'b0,32'b0,32'b0,32'b0};
state <= increment_key;
end
end
decryption_successful:
begin
decrypt_success <= 1'b1;
state <= decryption_successful;
end
decryption_failed:
begin
decrypt_failed <= 1'b1;
state <= decryption_failed;
end
endcase
end
end
always_comb
begin
LEDR[9:2] = secret_key_24_bit[23:16];
if (decrypt_success == 1'b1)
begin
LEDR = 1;
end
else
begin
LEDR = 0;
end
if (decrypt_failed == 1'b1) begin
LEDR[1] = 1;
end
else
begin
LEDR[1] = 0;
end
end
endmodule | 0 |
138,985 | data/full_repos/permissive/86664697/Lab4/template_de1soc/lab4_top.sv | 86,664,697 | lab4_top.sv | sv | 64 | 75 | [] | [] | [] | [(1, 64)] | null | null | 1: b"%Error: data/full_repos/permissive/86664697/Lab4/template_de1soc/lab4_top.sv:32: Cannot find file containing module: 'ksa'\nksa ksa1(.CLOCK_50(CLOCK_50), \n^~~\n ... Looked in:\n data/full_repos/permissive/86664697/Lab4/template_de1soc,data/full_repos/permissive/86664697/ksa\n data/full_repos/permissive/86664697/Lab4/template_de1soc,data/full_repos/permissive/86664697/ksa.v\n data/full_repos/permissive/86664697/Lab4/template_de1soc,data/full_repos/permissive/86664697/ksa.sv\n ksa\n ksa.v\n ksa.sv\n obj_dir/ksa\n obj_dir/ksa.v\n obj_dir/ksa.sv\n%Error: data/full_repos/permissive/86664697/Lab4/template_de1soc/lab4_top.sv:37: Cannot find file containing module: 'ksa'\nksa ksa2(.CLOCK_50(CLOCK_50), \n^~~\n%Error: data/full_repos/permissive/86664697/Lab4/template_de1soc/lab4_top.sv:42: Cannot find file containing module: 'ksa'\nksa ksa3(.CLOCK_50(CLOCK_50), \n^~~\n%Error: data/full_repos/permissive/86664697/Lab4/template_de1soc/lab4_top.sv:47: Cannot find file containing module: 'ksa'\nksa ksa4(.CLOCK_50(CLOCK_50), \n^~~\n%Error: Exiting due to 4 error(s)\n" | 304,229 | module | module lab4_top(CLOCK_50,
KEY,
LEDR);
input CLOCK_50;
input [3:0] KEY;
output logic [9:0] LEDR;
ksa ksa1(.CLOCK_50(CLOCK_50),
.KEY(KEY),
.keymin(24'b0),
.keymax(1048575));
ksa ksa2(.CLOCK_50(CLOCK_50),
.KEY(KEY),
.keymin(1048576),
.keymax(2097152));
ksa ksa3(.CLOCK_50(CLOCK_50),
.KEY(KEY),
.keymin(2097153),
.keymax(3145727));
ksa ksa4(.CLOCK_50(CLOCK_50),
.KEY(KEY),
.keymin(3145728),
.keymax(4194303));
endmodule | module lab4_top(CLOCK_50,
KEY,
LEDR); |
input CLOCK_50;
input [3:0] KEY;
output logic [9:0] LEDR;
ksa ksa1(.CLOCK_50(CLOCK_50),
.KEY(KEY),
.keymin(24'b0),
.keymax(1048575));
ksa ksa2(.CLOCK_50(CLOCK_50),
.KEY(KEY),
.keymin(1048576),
.keymax(2097152));
ksa ksa3(.CLOCK_50(CLOCK_50),
.KEY(KEY),
.keymin(2097153),
.keymax(3145727));
ksa ksa4(.CLOCK_50(CLOCK_50),
.KEY(KEY),
.keymin(3145728),
.keymax(4194303));
endmodule | 0 |
138,986 | data/full_repos/permissive/86664697/Lab4/template_de1soc/SevenSegmentDisplayDecoder.v | 86,664,697 | SevenSegmentDisplayDecoder.v | v | 28 | 47 | [] | [] | [] | [(1, 28)] | null | data/verilator_xmls/3e588315-6186-4c6b-a09e-c27a23a7df07.xml | null | 304,230 | module | module SevenSegmentDisplayDecoder(ssOut, nIn);
output [6:0] ssOut;
reg [6:0] ssOut_tmp;
input [3:0] nIn;
always @*
case (nIn)
4'h0: ssOut_tmp = 7'b0111111;
4'h1: ssOut_tmp = 7'b0000110;
4'h2: ssOut_tmp = 7'b1011011;
4'h3: ssOut_tmp = 7'b1001111;
4'h4: ssOut_tmp = 7'b1100110;
4'h5: ssOut_tmp = 7'b1101101;
4'h6: ssOut_tmp = 7'b1111101;
4'h7: ssOut_tmp = 7'b0000111;
4'h8: ssOut_tmp = 7'b1111111;
4'h9: ssOut_tmp = 7'b1101111;
4'hA: ssOut_tmp = 7'b1110111;
4'hB: ssOut_tmp = 7'b1111100;
4'hC: ssOut_tmp = 7'b0111001;
4'hD: ssOut_tmp = 7'b1011110;
4'hE: ssOut_tmp = 7'b1111001;
4'hF: ssOut_tmp = 7'b1110001;
endcase
assign ssOut = ~ssOut_tmp;
endmodule | module SevenSegmentDisplayDecoder(ssOut, nIn); |
output [6:0] ssOut;
reg [6:0] ssOut_tmp;
input [3:0] nIn;
always @*
case (nIn)
4'h0: ssOut_tmp = 7'b0111111;
4'h1: ssOut_tmp = 7'b0000110;
4'h2: ssOut_tmp = 7'b1011011;
4'h3: ssOut_tmp = 7'b1001111;
4'h4: ssOut_tmp = 7'b1100110;
4'h5: ssOut_tmp = 7'b1101101;
4'h6: ssOut_tmp = 7'b1111101;
4'h7: ssOut_tmp = 7'b0000111;
4'h8: ssOut_tmp = 7'b1111111;
4'h9: ssOut_tmp = 7'b1101111;
4'hA: ssOut_tmp = 7'b1110111;
4'hB: ssOut_tmp = 7'b1111100;
4'hC: ssOut_tmp = 7'b0111001;
4'hD: ssOut_tmp = 7'b1011110;
4'hE: ssOut_tmp = 7'b1111001;
4'hF: ssOut_tmp = 7'b1110001;
endcase
assign ssOut = ~ssOut_tmp;
endmodule | 0 |
138,987 | data/full_repos/permissive/86668501/Lab3-L1D/detectwin.v | 86,668,501 | detectwin.v | v | 32 | 97 | [] | [] | [] | [(16, 31)] | null | data/verilator_xmls/81c10746-74ce-49d5-9565-1dab2fb90ec5.xml | null | 304,242 | module | module DetectWinner( input [8:0] ain, bin, output [7:0] win_line );
assign win_line[0] = (ain[8] & ain[7] & ain[6]) | (bin[8] & bin[7] & bin[6]);
assign win_line[1] = (ain[5] & ain[4] & ain[3]) | (bin[5] & bin[4] & bin[3]);
assign win_line[2] = (ain[2] & ain[1] & ain[0]) | (bin[2] & bin[1] & bin[0]);
assign win_line[3] = (ain[8] & ain[5] & ain[2]) | (bin[8] & bin[5] & bin[2]);
assign win_line[4] = (ain[7] & ain[4] & ain[1]) | (bin[7] & bin[4] & bin[1]);
assign win_line[5] = (ain[6] & ain[3] & ain[0]) | (bin[6] & bin[3] & bin[0]);
assign win_line[6] = (ain[8] & ain[4] & ain[0]) | (bin[8] & bin[4] & bin[0]);
assign win_line[7] = (ain[2] & ain[4] & ain[6]) | (bin[2] & bin[4] & bin[6]);
endmodule | module DetectWinner( input [8:0] ain, bin, output [7:0] win_line ); |
assign win_line[0] = (ain[8] & ain[7] & ain[6]) | (bin[8] & bin[7] & bin[6]);
assign win_line[1] = (ain[5] & ain[4] & ain[3]) | (bin[5] & bin[4] & bin[3]);
assign win_line[2] = (ain[2] & ain[1] & ain[0]) | (bin[2] & bin[1] & bin[0]);
assign win_line[3] = (ain[8] & ain[5] & ain[2]) | (bin[8] & bin[5] & bin[2]);
assign win_line[4] = (ain[7] & ain[4] & ain[1]) | (bin[7] & bin[4] & bin[1]);
assign win_line[5] = (ain[6] & ain[3] & ain[0]) | (bin[6] & bin[3] & bin[0]);
assign win_line[6] = (ain[8] & ain[4] & ain[0]) | (bin[8] & bin[4] & bin[0]);
assign win_line[7] = (ain[2] & ain[4] & ain[6]) | (bin[2] & bin[4] & bin[6]);
endmodule | 0 |
138,988 | data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v | 86,668,501 | detectwin_tb.v | v | 90 | 97 | [] | [] | [] | null | line:86: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Error: Exiting due to 18 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,243 | module | module DetectWinner( input [8:0] ain, bin, output [7:0] win_line );
assign win_line[0] = (ain[8] & ain[7] & ain[6]) | (bin[8] & bin[7] & bin[6]);
assign win_line[1] = (ain[5] & ain[4] & ain[3]) | (bin[5] & bin[4] & bin[3]);
assign win_line[2] = (ain[2] & ain[1] & ain[0]) | (bin[2] & bin[1] & bin[0]);
assign win_line[3] = (ain[8] & ain[5] & ain[2]) | (bin[8] & bin[5] & bin[2]);
assign win_line[4] = (ain[7] & ain[4] & ain[1]) | (bin[7] & bin[4] & bin[1]);
assign win_line[5] = (ain[6] & ain[3] & ain[0]) | (bin[6] & bin[3] & bin[0]);
assign win_line[6] = (ain[8] & ain[4] & ain[0]) | (bin[8] & bin[4] & bin[0]);
assign win_line[7] = (ain[2] & ain[4] & ain[6]) | (bin[2] & bin[4] & bin[6]);
endmodule | module DetectWinner( input [8:0] ain, bin, output [7:0] win_line ); |
assign win_line[0] = (ain[8] & ain[7] & ain[6]) | (bin[8] & bin[7] & bin[6]);
assign win_line[1] = (ain[5] & ain[4] & ain[3]) | (bin[5] & bin[4] & bin[3]);
assign win_line[2] = (ain[2] & ain[1] & ain[0]) | (bin[2] & bin[1] & bin[0]);
assign win_line[3] = (ain[8] & ain[5] & ain[2]) | (bin[8] & bin[5] & bin[2]);
assign win_line[4] = (ain[7] & ain[4] & ain[1]) | (bin[7] & bin[4] & bin[1]);
assign win_line[5] = (ain[6] & ain[3] & ain[0]) | (bin[6] & bin[3] & bin[0]);
assign win_line[6] = (ain[8] & ain[4] & ain[0]) | (bin[8] & bin[4] & bin[0]);
assign win_line[7] = (ain[2] & ain[4] & ain[6]) | (bin[2] & bin[4] & bin[6]);
endmodule | 0 |
138,989 | data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v | 86,668,501 | detectwin_tb.v | v | 90 | 97 | [] | [] | [] | null | line:86: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/detectwin_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Error: Exiting due to 18 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,243 | module | module Detect_tb();
reg [8:0] ain, bin;
wire [7:0] win_line;
DetectWinner dut(ain, bin, win_line);
initial begin
ain = 9'b111000000; bin = 9'b000000000;
#100
bin = 9'b111000000; ain = 9'b000000000;
#100
ain = 9'b000111000; bin = 9'b000000000;
#100
bin = 9'b000111000; ain = 9'b000000000;
#100
ain = 9'b000000111; bin = 9'b000000000;
#100
bin = 9'b000000111; ain = 9'b000000000;
#100
ain = 9'b100100100; bin = 9'b000000000;
#100
bin = 9'b100100100; ain = 9'b000000000;
#100
ain = 9'b010010010; bin = 9'b000000000;
#100
bin = 9'b010010010; ain = 9'b000000000;
#100
ain = 9'b001001001; bin = 9'b000000000;
#100
bin = 9'b001001001; ain = 9'b000000000;
#100
ain = 9'b100010001; bin = 9'b000000000;
#100
bin = 9'b100010001; ain = 9'b000000000;
#100
ain = 9'b001010100; bin = 9'b000000000;
#100
bin = 9'b001010100; ain = 9'b000000000;
#100
ain = 9'b011000000; bin = 9'b000110101;
#100
ain = 9'b000100000; bin = 9'b000011000;
#100
$display("All tests ran successfully");
end
endmodule | module Detect_tb(); |
reg [8:0] ain, bin;
wire [7:0] win_line;
DetectWinner dut(ain, bin, win_line);
initial begin
ain = 9'b111000000; bin = 9'b000000000;
#100
bin = 9'b111000000; ain = 9'b000000000;
#100
ain = 9'b000111000; bin = 9'b000000000;
#100
bin = 9'b000111000; ain = 9'b000000000;
#100
ain = 9'b000000111; bin = 9'b000000000;
#100
bin = 9'b000000111; ain = 9'b000000000;
#100
ain = 9'b100100100; bin = 9'b000000000;
#100
bin = 9'b100100100; ain = 9'b000000000;
#100
ain = 9'b010010010; bin = 9'b000000000;
#100
bin = 9'b010010010; ain = 9'b000000000;
#100
ain = 9'b001001001; bin = 9'b000000000;
#100
bin = 9'b001001001; ain = 9'b000000000;
#100
ain = 9'b100010001; bin = 9'b000000000;
#100
bin = 9'b100010001; ain = 9'b000000000;
#100
ain = 9'b001010100; bin = 9'b000000000;
#100
bin = 9'b001010100; ain = 9'b000000000;
#100
ain = 9'b011000000; bin = 9'b000110101;
#100
ain = 9'b000100000; bin = 9'b000011000;
#100
$display("All tests ran successfully");
end
endmodule | 0 |
138,990 | data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v | 86,668,501 | tictactoe.v | v | 247 | 309 | [] | [] | [] | null | line:195: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:195: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:198: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:201: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:204: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:207: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:210: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:214: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:220: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:212: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:239: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:243: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:230: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'TestTic\'\nmodule TestTic ;\n ^~~~~~~\n : ... Top module \'TestPlayAdjacentEdge\'\nmodule TestPlayAdjacentEdge ;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 12 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,244 | module | module RArb(r, g) ;
parameter n=8 ;
input [n-1:0] r ;
output [n-1:0] g ;
wire [n-1:0] c = {1'b1,(~r[n-1:1] & c[n-1:1])} ;
assign g = r & c ;
endmodule | module RArb(r, g) ; |
parameter n=8 ;
input [n-1:0] r ;
output [n-1:0] g ;
wire [n-1:0] c = {1'b1,(~r[n-1:1] & c[n-1:1])} ;
assign g = r & c ;
endmodule | 0 |
138,991 | data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v | 86,668,501 | tictactoe.v | v | 247 | 309 | [] | [] | [] | null | line:195: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:195: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:198: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:201: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:204: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:207: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:210: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:214: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:220: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:212: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:239: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:243: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:230: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'TestTic\'\nmodule TestTic ;\n ^~~~~~~\n : ... Top module \'TestPlayAdjacentEdge\'\nmodule TestPlayAdjacentEdge ;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 12 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,244 | module | module TicTacToe(xin, oin, oout) ;
input [8:0] xin, oin ;
output [8:0] oout ;
wire [8:0] win, block, adj, empty ;
TwoInArray winx(oin, xin, win) ;
TwoInArray blockx(xin, oin, block);
PlayAdjacentEdge adjacentx(xin, oin, adj);
Empty emptyx(~(oin | xin), empty) ;
Select4 comb(win, block, adj, empty, oout) ;
endmodule | module TicTacToe(xin, oin, oout) ; |
input [8:0] xin, oin ;
output [8:0] oout ;
wire [8:0] win, block, adj, empty ;
TwoInArray winx(oin, xin, win) ;
TwoInArray blockx(xin, oin, block);
PlayAdjacentEdge adjacentx(xin, oin, adj);
Empty emptyx(~(oin | xin), empty) ;
Select4 comb(win, block, adj, empty, oout) ;
endmodule | 0 |
138,992 | data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v | 86,668,501 | tictactoe.v | v | 247 | 309 | [] | [] | [] | null | line:195: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:195: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:198: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:201: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:204: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:207: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:210: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:214: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:220: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:212: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:239: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:243: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:230: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'TestTic\'\nmodule TestTic ;\n ^~~~~~~\n : ... Top module \'TestPlayAdjacentEdge\'\nmodule TestPlayAdjacentEdge ;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 12 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,244 | module | module TwoInArray(ain, bin, cout) ;
input [8:0] ain, bin ;
output [8:0] cout ;
wire [8:0] rows, cols ;
wire [2:0] ddiag, udiag ;
TwoInRow topr(ain[2:0],bin[2:0],rows[2:0]) ;
TwoInRow midr(ain[5:3],bin[5:3],rows[5:3]) ;
TwoInRow botr(ain[8:6],bin[8:6],rows[8:6]) ;
TwoInRow leftc({ain[6],ain[3],ain[0]},
{bin[6],bin[3],bin[0]},
{cols[6],cols[3],cols[0]}) ;
TwoInRow midc({ain[7],ain[4],ain[1]},
{bin[7],bin[4],bin[1]},
{cols[7],cols[4],cols[1]}) ;
TwoInRow rightc({ain[8],ain[5],ain[2]},
{bin[8],bin[5],bin[2]},
{cols[8],cols[5],cols[2]}) ;
TwoInRow dndiagx({ain[8],ain[4],ain[0]},{bin[8],bin[4],bin[0]},ddiag) ;
TwoInRow updiagx({ain[6],ain[4],ain[2]},{bin[6],bin[4],bin[2]},udiag) ;
assign cout = rows | cols |
{ddiag[2],1'b0,1'b0,1'b0,ddiag[1],1'b0,1'b0,1'b0,ddiag[0]} |
{1'b0,1'b0,udiag[2],1'b0,udiag[1],1'b0,udiag[0],1'b0,1'b0} ;
endmodule | module TwoInArray(ain, bin, cout) ; |
input [8:0] ain, bin ;
output [8:0] cout ;
wire [8:0] rows, cols ;
wire [2:0] ddiag, udiag ;
TwoInRow topr(ain[2:0],bin[2:0],rows[2:0]) ;
TwoInRow midr(ain[5:3],bin[5:3],rows[5:3]) ;
TwoInRow botr(ain[8:6],bin[8:6],rows[8:6]) ;
TwoInRow leftc({ain[6],ain[3],ain[0]},
{bin[6],bin[3],bin[0]},
{cols[6],cols[3],cols[0]}) ;
TwoInRow midc({ain[7],ain[4],ain[1]},
{bin[7],bin[4],bin[1]},
{cols[7],cols[4],cols[1]}) ;
TwoInRow rightc({ain[8],ain[5],ain[2]},
{bin[8],bin[5],bin[2]},
{cols[8],cols[5],cols[2]}) ;
TwoInRow dndiagx({ain[8],ain[4],ain[0]},{bin[8],bin[4],bin[0]},ddiag) ;
TwoInRow updiagx({ain[6],ain[4],ain[2]},{bin[6],bin[4],bin[2]},udiag) ;
assign cout = rows | cols |
{ddiag[2],1'b0,1'b0,1'b0,ddiag[1],1'b0,1'b0,1'b0,ddiag[0]} |
{1'b0,1'b0,udiag[2],1'b0,udiag[1],1'b0,udiag[0],1'b0,1'b0} ;
endmodule | 0 |
138,993 | data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v | 86,668,501 | tictactoe.v | v | 247 | 309 | [] | [] | [] | null | line:195: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:195: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:198: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:201: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:204: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:207: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:210: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:214: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:220: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:212: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:239: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:243: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:230: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'TestTic\'\nmodule TestTic ;\n ^~~~~~~\n : ... Top module \'TestPlayAdjacentEdge\'\nmodule TestPlayAdjacentEdge ;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 12 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,244 | module | module TwoInRow(ain, bin, cout) ;
input [2:0] ain, bin ;
output [2:0] cout ;
assign cout[0] = ~bin[0] & ~ain[0] & ain[1] & ain[2] ;
assign cout[1] = ~bin[1] & ain[0] & ~ain[1] & ain[2] ;
assign cout[2] = ~bin[2] & ain[0] & ain[1] & ~ain[2] ;
endmodule | module TwoInRow(ain, bin, cout) ; |
input [2:0] ain, bin ;
output [2:0] cout ;
assign cout[0] = ~bin[0] & ~ain[0] & ain[1] & ain[2] ;
assign cout[1] = ~bin[1] & ain[0] & ~ain[1] & ain[2] ;
assign cout[2] = ~bin[2] & ain[0] & ain[1] & ~ain[2] ;
endmodule | 0 |
138,994 | data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v | 86,668,501 | tictactoe.v | v | 247 | 309 | [] | [] | [] | null | line:195: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:195: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:198: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:201: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:204: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:207: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:210: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:214: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:220: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:212: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:239: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:243: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:230: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'TestTic\'\nmodule TestTic ;\n ^~~~~~~\n : ... Top module \'TestPlayAdjacentEdge\'\nmodule TestPlayAdjacentEdge ;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 12 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,244 | module | module Empty(in, out) ;
input [8:0] in ;
output [8:0] out ;
RArb #(9) ra({in[4],in[0],in[2],in[6],in[8],in[1],in[3],in[5],in[7]},
{out[4],out[0],out[2],out[6],out[8],out[1],out[3],out[5],out[7]}) ;
endmodule | module Empty(in, out) ; |
input [8:0] in ;
output [8:0] out ;
RArb #(9) ra({in[4],in[0],in[2],in[6],in[8],in[1],in[3],in[5],in[7]},
{out[4],out[0],out[2],out[6],out[8],out[1],out[3],out[5],out[7]}) ;
endmodule | 0 |
138,995 | data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v | 86,668,501 | tictactoe.v | v | 247 | 309 | [] | [] | [] | null | line:195: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:195: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:198: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:201: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:204: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:207: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:210: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:214: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:220: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:212: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:239: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:243: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:230: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'TestTic\'\nmodule TestTic ;\n ^~~~~~~\n : ... Top module \'TestPlayAdjacentEdge\'\nmodule TestPlayAdjacentEdge ;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 12 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,244 | module | module PlayAdjacentEdge(ain, bin, dout);
input[8:0] ain,bin;
output[8:0] dout;
assign dout[5]= (ain[0]&~ain[1]&~ain[2]&~ain[3]&~ain[4]&~ain[5]&~ain[6]&~ain[7]&ain[8] & ~bin[0]&~bin[1]&~bin[2]&~bin[3]&bin[4]&~bin[5]&~bin[6]&~bin[7]&~bin[8])|(~ain[0]&~ain[1]&ain[2]&~ain[3]&~ain[4]&~ain[5]&ain[6]&~ain[7]&~ain[8] & ~bin[0]&~bin[1]&~bin[2]&~bin[3]&bin[4]&~bin[5]&~bin[6]&~bin[7]&~bin[8]);
endmodule | module PlayAdjacentEdge(ain, bin, dout); |
input[8:0] ain,bin;
output[8:0] dout;
assign dout[5]= (ain[0]&~ain[1]&~ain[2]&~ain[3]&~ain[4]&~ain[5]&~ain[6]&~ain[7]&ain[8] & ~bin[0]&~bin[1]&~bin[2]&~bin[3]&bin[4]&~bin[5]&~bin[6]&~bin[7]&~bin[8])|(~ain[0]&~ain[1]&ain[2]&~ain[3]&~ain[4]&~ain[5]&ain[6]&~ain[7]&~ain[8] & ~bin[0]&~bin[1]&~bin[2]&~bin[3]&bin[4]&~bin[5]&~bin[6]&~bin[7]&~bin[8]);
endmodule | 0 |
138,996 | data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v | 86,668,501 | tictactoe.v | v | 247 | 309 | [] | [] | [] | null | line:195: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:195: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:198: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:201: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:204: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:207: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:210: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:214: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:220: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:212: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:239: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:243: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:230: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'TestTic\'\nmodule TestTic ;\n ^~~~~~~\n : ... Top module \'TestPlayAdjacentEdge\'\nmodule TestPlayAdjacentEdge ;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 12 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,244 | module | module Select4(a, b, d, c, out) ;
input [8:0] a, b, d, c;
output [8:0] out ;
wire [35:0] x ;
RArb #(36) ra({a,b,d,c},x) ;
assign out = x[35:27] | x[26:18] | x[17:9] | x[8:0] ;
endmodule | module Select4(a, b, d, c, out) ; |
input [8:0] a, b, d, c;
output [8:0] out ;
wire [35:0] x ;
RArb #(36) ra({a,b,d,c},x) ;
assign out = x[35:27] | x[26:18] | x[17:9] | x[8:0] ;
endmodule | 0 |
138,997 | data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v | 86,668,501 | tictactoe.v | v | 247 | 309 | [] | [] | [] | null | line:195: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:195: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:198: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:201: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:204: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:207: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:210: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:214: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:220: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:212: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:239: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:243: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:230: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'TestTic\'\nmodule TestTic ;\n ^~~~~~~\n : ... Top module \'TestPlayAdjacentEdge\'\nmodule TestPlayAdjacentEdge ;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 12 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,244 | module | module TestTic ;
reg [8:0] xin, oin ;
wire [8:0] xout, oout ;
TicTacToe dut(xin, oin, oout) ;
TicTacToe opponent(oin, xin, xout) ;
initial begin
xin = 0 ; oin = 0 ;
#100 $display("%b %b -> %b", xin, oin, xout) ;
xin = 9'b101 ; oin = 0 ;
#100 $display("%b %b -> %b", xin, oin, xout) ;
xin = 9'b101 ; oin = 9'b010 ;
#100 $display("%b %b -> %b", xin, oin, xout) ;
xin = 0 ; oin = 9'b100100 ;
#100 $display("%b %b -> %b", xin, oin, xout) ;
xin = 0 ; oin = 9'b010100 ;
#100 $display("%b %b -> %b", xin, oin, xout) ;
xin = 0 ; oin = 0 ;
#100
xin = 9'b100000001; oin = 9'b000010000;
#100
repeat (7) begin
#100
$display("%h %h %h", {xin[0],oin[0]},{xin[1],oin[1]},{xin[2],oin[2]}) ;
$display("%h %h %h", {xin[3],oin[3]},{xin[4],oin[4]},{xin[5],oin[5]}) ;
$display("%h %h %h", {xin[6],oin[6]},{xin[7],oin[7]},{xin[8],oin[8]}) ;
$display(" ") ;
xin = (xout | xin) ;
#100
$display("%h %h %h", {xin[0],oin[0]},{xin[1],oin[1]},{xin[2],oin[2]}) ;
$display("%h %h %h", {xin[3],oin[3]},{xin[4],oin[4]},{xin[5],oin[5]}) ;
$display("%h %h %h", {xin[6],oin[6]},{xin[7],oin[7]},{xin[8],oin[8]}) ;
$display(" ") ;
oin = (oout | oin) ;
end
end
endmodule | module TestTic ; |
reg [8:0] xin, oin ;
wire [8:0] xout, oout ;
TicTacToe dut(xin, oin, oout) ;
TicTacToe opponent(oin, xin, xout) ;
initial begin
xin = 0 ; oin = 0 ;
#100 $display("%b %b -> %b", xin, oin, xout) ;
xin = 9'b101 ; oin = 0 ;
#100 $display("%b %b -> %b", xin, oin, xout) ;
xin = 9'b101 ; oin = 9'b010 ;
#100 $display("%b %b -> %b", xin, oin, xout) ;
xin = 0 ; oin = 9'b100100 ;
#100 $display("%b %b -> %b", xin, oin, xout) ;
xin = 0 ; oin = 9'b010100 ;
#100 $display("%b %b -> %b", xin, oin, xout) ;
xin = 0 ; oin = 0 ;
#100
xin = 9'b100000001; oin = 9'b000010000;
#100
repeat (7) begin
#100
$display("%h %h %h", {xin[0],oin[0]},{xin[1],oin[1]},{xin[2],oin[2]}) ;
$display("%h %h %h", {xin[3],oin[3]},{xin[4],oin[4]},{xin[5],oin[5]}) ;
$display("%h %h %h", {xin[6],oin[6]},{xin[7],oin[7]},{xin[8],oin[8]}) ;
$display(" ") ;
xin = (xout | xin) ;
#100
$display("%h %h %h", {xin[0],oin[0]},{xin[1],oin[1]},{xin[2],oin[2]}) ;
$display("%h %h %h", {xin[3],oin[3]},{xin[4],oin[4]},{xin[5],oin[5]}) ;
$display("%h %h %h", {xin[6],oin[6]},{xin[7],oin[7]},{xin[8],oin[8]}) ;
$display(" ") ;
oin = (oout | oin) ;
end
end
endmodule | 0 |
138,998 | data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v | 86,668,501 | tictactoe.v | v | 247 | 309 | [] | [] | [] | null | line:195: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:195: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:198: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:201: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:204: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:207: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("%b %b -> %b", xin, oin, xout) ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:210: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:214: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:220: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:212: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:239: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:243: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab3-L1D/tictactoe.v:230: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'TestTic\'\nmodule TestTic ;\n ^~~~~~~\n : ... Top module \'TestPlayAdjacentEdge\'\nmodule TestPlayAdjacentEdge ;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 12 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,244 | module | module TestPlayAdjacentEdge ;
reg [8:0] xin, oin;
wire [8:0] dout;
TicTacToe dut(xin,oin,dout);
initial begin
xin = 9'b100000001; oin = 9'b000010000;
#100
$display("the output dout=%h%h%h%h%h%h%h%h%h", dout[8],dout[7],dout[6],dout[5],dout[4],dout[3],dout[2],dout[1],dout[0]);
xin = 9'b001000100; oin = 9'b000010000;
#100
$display("the output dout=%h%h%h%h%h%h%h%h%h", dout[8],dout[7],dout[6],dout[5],dout[4],dout[3],dout[2],dout[1],dout[0]);
end
endmodule | module TestPlayAdjacentEdge ; |
reg [8:0] xin, oin;
wire [8:0] dout;
TicTacToe dut(xin,oin,dout);
initial begin
xin = 9'b100000001; oin = 9'b000010000;
#100
$display("the output dout=%h%h%h%h%h%h%h%h%h", dout[8],dout[7],dout[6],dout[5],dout[4],dout[3],dout[2],dout[1],dout[0]);
xin = 9'b001000100; oin = 9'b000010000;
#100
$display("the output dout=%h%h%h%h%h%h%h%h%h", dout[8],dout[7],dout[6],dout[5],dout[4],dout[3],dout[2],dout[1],dout[0]);
end
endmodule | 0 |
138,999 | data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v | 86,668,501 | lab4_tb.v | v | 199 | 135 | [] | [] | [] | null | line:28: before: "{" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:138: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:155: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:163: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:165: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:168: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:175: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:178: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:180: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:183: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:185: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:188: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:190: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:193: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:195: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: Exiting due to 58 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,245 | module | module lab4_top(SW,KEY,HEX0);
input [9:0] SW;
input [3:0] KEY;
output [6:0] HEX0;
reg [4:0] next_state;
reg [6:0] HEX0;
wire [4:0] reset_state, present_state;
`define HW 5
`define H0 5'b00001
`define H1 5'b00010
`define H2 5'b00100
`define H3 5'b01000
`define H4 5'b10000
vDFF #(`HW) STATE(KEY[0],reset_state,present_state);
assign reset_state= ~KEY[1] ? `H0 : next_state;
always @(*)begin
case(present_state)
`H0 : {next_state, HEX0}={(SW[0] ? `H1 : `H4),7'b0100100};
`H1 : {next_state, HEX0}={(SW[0] ? `H2 : `H0),7'b0011001};
`H2 : {next_state, HEX0}={(SW[0] ? `H3 : `H1),7'b1000000};
`H3 : {next_state, HEX0}={(SW[0] ? `H4 : `H2),7'b0110000};
`H4 : {next_state, HEX0}={(SW[0] ? `H0 : `H3),7'b1111001};
default {next_state, HEX0}={`H0,7'b0100100};
endcase
end
endmodule | module lab4_top(SW,KEY,HEX0); |
input [9:0] SW;
input [3:0] KEY;
output [6:0] HEX0;
reg [4:0] next_state;
reg [6:0] HEX0;
wire [4:0] reset_state, present_state;
`define HW 5
`define H0 5'b00001
`define H1 5'b00010
`define H2 5'b00100
`define H3 5'b01000
`define H4 5'b10000
vDFF #(`HW) STATE(KEY[0],reset_state,present_state);
assign reset_state= ~KEY[1] ? `H0 : next_state;
always @(*)begin
case(present_state)
`H0 : {next_state, HEX0}={(SW[0] ? `H1 : `H4),7'b0100100};
`H1 : {next_state, HEX0}={(SW[0] ? `H2 : `H0),7'b0011001};
`H2 : {next_state, HEX0}={(SW[0] ? `H3 : `H1),7'b1000000};
`H3 : {next_state, HEX0}={(SW[0] ? `H4 : `H2),7'b0110000};
`H4 : {next_state, HEX0}={(SW[0] ? `H0 : `H3),7'b1111001};
default {next_state, HEX0}={`H0,7'b0100100};
endcase
end
endmodule | 0 |
139,000 | data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v | 86,668,501 | lab4_tb.v | v | 199 | 135 | [] | [] | [] | null | line:28: before: "{" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:138: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:155: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:163: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:165: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:168: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:175: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:178: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:180: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:183: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:185: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:188: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:190: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:193: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:195: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: Exiting due to 58 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,245 | module | module vDFF(clk, in, out);
parameter n=1;
input clk;
input [n-1:0] in;
output [n-1:0] out;
reg [n-1:0] out;
always @(posedge clk)
out=in;
endmodule | module vDFF(clk, in, out); |
parameter n=1;
input clk;
input [n-1:0] in;
output [n-1:0] out;
reg [n-1:0] out;
always @(posedge clk)
out=in;
endmodule | 0 |
139,001 | data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v | 86,668,501 | lab4_tb.v | v | 199 | 135 | [] | [] | [] | null | line:28: before: "{" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:138: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:155: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:163: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:165: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:168: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:175: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:178: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:180: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:183: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:185: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:188: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:190: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:193: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab4-L1D/lab4_tb.v:195: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: Exiting due to 58 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,245 | module | module lab4_tb();
reg [9:0] SW;
reg [3:0] KEY;
wire [6:0] HEX0;
lab4_top dut(SW,KEY,HEX0);
initial begin
SW=10'b0000000001; KEY=4'b0011;
#10
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000000001; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000000001; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000000001; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000000001; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000000001; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000000001; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000000001; KEY=4'b0001;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b0011;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b0011;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b0011;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b0011;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b0011;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b0011;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b0011;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b0001;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b1110;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b0111;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000001; KEY=4'b0011;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b0011;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000011; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000000111; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000001111; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000011111; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000111111; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0001111111; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0011111111; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0111111111; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b1111111111; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
$display("Tests are finished.");
end
endmodule | module lab4_tb(); |
reg [9:0] SW;
reg [3:0] KEY;
wire [6:0] HEX0;
lab4_top dut(SW,KEY,HEX0);
initial begin
SW=10'b0000000001; KEY=4'b0011;
#10
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000000001; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000000001; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000000001; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000000001; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000000001; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000000001; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000000001; KEY=4'b0001;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b0011;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b0011;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b0011;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b0011;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b0011;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b0011;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b0011;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b0001;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b1110;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b0111;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000001; KEY=4'b0011;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000000; KEY=4'b0011;
#30
SW=10'b0000000000; KEY=4'b0010;
#10
SW=10'b0000000011; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000000111; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000001111; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000011111; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0000111111; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0001111111; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0011111111; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b0111111111; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
SW=10'b1111111111; KEY=4'b0011;
#30
SW=10'b0000000001; KEY=4'b0010;
#10
$display("Tests are finished.");
end
endmodule | 0 |
139,002 | data/full_repos/permissive/86668501/Lab4-L1D/lab4_top.v | 86,668,501 | lab4_top.v | v | 43 | 135 | [] | [] | [] | null | line:28: before: "{" | data/verilator_xmls/dfb1917d-784e-48aa-9b72-04424fc730e0.xml | null | 304,246 | module | module lab4_top(SW,KEY,HEX0);
input [9:0] SW;
input [3:0] KEY;
output [6:0] HEX0;
reg [4:0] next_state;
reg [6:0] HEX0;
wire [4:0] reset_state, present_state;
`define HW 5
`define H0 5'b00001
`define H1 5'b00010
`define H2 5'b00100
`define H3 5'b01000
`define H4 5'b10000
vDFF #(`HW) STATE(KEY[0],reset_state,present_state);
assign reset_state= ~KEY[1] ? `H0 : next_state;
always @(*)begin
case(present_state)
`H0 : {next_state, HEX0}={(SW[0] ? `H1 : `H4),7'b0100100};
`H1 : {next_state, HEX0}={(SW[0] ? `H2 : `H0),7'b0011001};
`H2 : {next_state, HEX0}={(SW[0] ? `H3 : `H1),7'b1000000};
`H3 : {next_state, HEX0}={(SW[0] ? `H4 : `H2),7'b0110000};
`H4 : {next_state, HEX0}={(SW[0] ? `H0 : `H3),7'b1111001};
default {next_state, HEX0}={`H0,7'b0100100};
endcase
end
endmodule | module lab4_top(SW,KEY,HEX0); |
input [9:0] SW;
input [3:0] KEY;
output [6:0] HEX0;
reg [4:0] next_state;
reg [6:0] HEX0;
wire [4:0] reset_state, present_state;
`define HW 5
`define H0 5'b00001
`define H1 5'b00010
`define H2 5'b00100
`define H3 5'b01000
`define H4 5'b10000
vDFF #(`HW) STATE(KEY[0],reset_state,present_state);
assign reset_state= ~KEY[1] ? `H0 : next_state;
always @(*)begin
case(present_state)
`H0 : {next_state, HEX0}={(SW[0] ? `H1 : `H4),7'b0100100};
`H1 : {next_state, HEX0}={(SW[0] ? `H2 : `H0),7'b0011001};
`H2 : {next_state, HEX0}={(SW[0] ? `H3 : `H1),7'b1000000};
`H3 : {next_state, HEX0}={(SW[0] ? `H4 : `H2),7'b0110000};
`H4 : {next_state, HEX0}={(SW[0] ? `H0 : `H3),7'b1111001};
default {next_state, HEX0}={`H0,7'b0100100};
endcase
end
endmodule | 0 |
139,003 | data/full_repos/permissive/86668501/Lab4-L1D/lab4_top.v | 86,668,501 | lab4_top.v | v | 43 | 135 | [] | [] | [] | null | line:28: before: "{" | data/verilator_xmls/dfb1917d-784e-48aa-9b72-04424fc730e0.xml | null | 304,246 | module | module vDFF(clk, in, out);
parameter n=1;
input clk;
input [n-1:0] in;
output [n-1:0] out;
reg [n-1:0] out;
always @(posedge clk)
out=in;
endmodule | module vDFF(clk, in, out); |
parameter n=1;
input clk;
input [n-1:0] in;
output [n-1:0] out;
reg [n-1:0] out;
always @(posedge clk)
out=in;
endmodule | 0 |
139,004 | data/full_repos/permissive/86668501/Lab5-L1D/ALU.v | 86,668,501 | ALU.v | v | 62 | 89 | [] | [] | [] | [(1, 19), (22, 61)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/ALU.v:34: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/ALU.v:39: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/ALU.v:44: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/ALU.v:49: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/ALU.v:54: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/ALU.v:59: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: Exiting due to 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,247 | module | module ALU (ain, bin, ALUop, loadc, statusout);
input [15:0] ain,bin;
input [1:0] ALUop;
output [15:0] loadc;
output statusout;
reg [15:0] loadc;
always @(*) begin
case(ALUop)
2'b00 : {loadc}={ain+bin};
2'b01 : {loadc}={ain-bin};
2'b10 : {loadc}={ain & bin};
2'b11 : {loadc}={~bin};
endcase
end
assign statusout = {~loadc[15]& ~loadc[14]& ~loadc[13]& ~loadc[12]& ~loadc[11]&
~loadc[10]& ~loadc[9]& ~loadc[8]& ~loadc[7]& ~loadc[6]& ~loadc[5]&
~loadc[4]& ~loadc[3]& ~loadc[2]& ~loadc[1]& ~loadc[0]};
endmodule | module ALU (ain, bin, ALUop, loadc, statusout); |
input [15:0] ain,bin;
input [1:0] ALUop;
output [15:0] loadc;
output statusout;
reg [15:0] loadc;
always @(*) begin
case(ALUop)
2'b00 : {loadc}={ain+bin};
2'b01 : {loadc}={ain-bin};
2'b10 : {loadc}={ain & bin};
2'b11 : {loadc}={~bin};
endcase
end
assign statusout = {~loadc[15]& ~loadc[14]& ~loadc[13]& ~loadc[12]& ~loadc[11]&
~loadc[10]& ~loadc[9]& ~loadc[8]& ~loadc[7]& ~loadc[6]& ~loadc[5]&
~loadc[4]& ~loadc[3]& ~loadc[2]& ~loadc[1]& ~loadc[0]};
endmodule | 0 |
139,005 | data/full_repos/permissive/86668501/Lab5-L1D/ALU.v | 86,668,501 | ALU.v | v | 62 | 89 | [] | [] | [] | [(1, 19), (22, 61)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/ALU.v:34: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/ALU.v:39: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/ALU.v:44: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/ALU.v:49: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/ALU.v:54: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/ALU.v:59: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: Exiting due to 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,247 | module | module ALU_tb();
reg [15:0] ain,bin;
reg [1:0] ALUop;
wire [15:0] loadc;
wire statusout;
ALU dut(ain,bin,ALUop,loadc,statusout);
initial begin
ain=16'b1000100010001001;
bin=16'b0010001000100001;
ALUop=2'b00;
#100
ain=16'b0000100001001110;
bin=16'b0000100001000111;
ALUop=2'b01;
#100
ain=16'b0111010010110011;
bin=16'b0111010100101100;
ALUop=2'b10;
#100
ain=16'b0100001010001010;
bin=16'b0100010001101100;
ALUop=2'b11;
#100
ain=16'b0100001010001010;
bin=16'b0000000000000000;
ALUop=2'b10;
#100
ain=16'b0010010010010010;
bin=16'b0010010010010010;
ALUop=2'b01;
#100;
end
endmodule | module ALU_tb(); |
reg [15:0] ain,bin;
reg [1:0] ALUop;
wire [15:0] loadc;
wire statusout;
ALU dut(ain,bin,ALUop,loadc,statusout);
initial begin
ain=16'b1000100010001001;
bin=16'b0010001000100001;
ALUop=2'b00;
#100
ain=16'b0000100001001110;
bin=16'b0000100001000111;
ALUop=2'b01;
#100
ain=16'b0111010010110011;
bin=16'b0111010100101100;
ALUop=2'b10;
#100
ain=16'b0100001010001010;
bin=16'b0100010001101100;
ALUop=2'b11;
#100
ain=16'b0100001010001010;
bin=16'b0000000000000000;
ALUop=2'b10;
#100
ain=16'b0010010010010010;
bin=16'b0010010010010010;
ALUop=2'b01;
#100;
end
endmodule | 0 |
139,006 | data/full_repos/permissive/86668501/Lab5-L1D/datapath.v | 86,668,501 | datapath.v | v | 104 | 221 | [] | [] | [] | [(1, 29), (31, 43), (45, 57), (59, 103)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:71: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:73: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:75: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:77: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:79: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:81: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:83: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:85: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:87: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:89: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:91: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:93: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:95: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:97: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:99: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:101: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:19: Cannot find file containing module: \'register_file\'\n register_file registerE(writenum, write, data_in, clk, readnum, data_out);\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86668501/Lab5-L1D,data/full_repos/permissive/86668501/register_file\n data/full_repos/permissive/86668501/Lab5-L1D,data/full_repos/permissive/86668501/register_file.v\n data/full_repos/permissive/86668501/Lab5-L1D,data/full_repos/permissive/86668501/register_file.sv\n register_file\n register_file.v\n register_file.sv\n obj_dir/register_file\n obj_dir/register_file.v\n obj_dir/register_file.sv\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:20: Cannot find file containing module: \'vDFFE\'\n vDFFE loadax(clk, loooada, data_out, loada);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:21: Cannot find file containing module: \'vDFFE\'\n vDFFE loadbx(clk, loooadb, data_out, loadb);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:22: Cannot find file containing module: \'shifter\'\n shifter shiftx(loadb, shift, newloadb);\n ^~~~~~~\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:26: Cannot find file containing module: \'ALU\'\n ALU ALUx(Ain, Bin, ALUop, loadc, statusout);\n ^~~\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:27: Cannot find file containing module: \'vDFFE\'\n vDFFE loadcx(clk, loooadc, loadc, datapath_out);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:28: Cannot find file containing module: \'vDFFE\'\n vDFFE loadsx(clk, loooadd, statusout, status10);\n ^~~~~\n%Error: Exiting due to 7 error(s), 16 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,248 | module | module datapath(datapath_in, writenum, write, readnum, clk,vsel, selecta, selectb, shift, ALUop, loooada, loooadb, loooadc, loooadd, datapath_out);
input [15:0] datapath_in;
input vsel, write,clk, selecta, selectb;
input [2:0] writenum, readnum;
input [1:0] ALUop, shift;
input loooada,loooadb,loooadc,loooadd;
output [15:0] datapath_out;
wire [15:0] data_out, loada, loadb, newloadb, Ain, Bin, loadc;
wire status10;
reg [15:0]data_in;
always @(*)begin
case(vsel)
1'b0 : data_in = datapath_out;
1'b1 : data_in = datapath_in;
endcase
end
register_file registerE(writenum, write, data_in, clk, readnum, data_out);
vDFFE loadax(clk, loooada, data_out, loada);
vDFFE loadbx(clk, loooadb, data_out, loadb);
shifter shiftx(loadb, shift, newloadb);
asel aselx(loada, selecta, Ain);
bsel bselx(newloadb, selectb, datapath_in, Bin);
ALU ALUx(Ain, Bin, ALUop, loadc, statusout);
vDFFE loadcx(clk, loooadc, loadc, datapath_out);
vDFFE loadsx(clk, loooadd, statusout, status10);
endmodule | module datapath(datapath_in, writenum, write, readnum, clk,vsel, selecta, selectb, shift, ALUop, loooada, loooadb, loooadc, loooadd, datapath_out); |
input [15:0] datapath_in;
input vsel, write,clk, selecta, selectb;
input [2:0] writenum, readnum;
input [1:0] ALUop, shift;
input loooada,loooadb,loooadc,loooadd;
output [15:0] datapath_out;
wire [15:0] data_out, loada, loadb, newloadb, Ain, Bin, loadc;
wire status10;
reg [15:0]data_in;
always @(*)begin
case(vsel)
1'b0 : data_in = datapath_out;
1'b1 : data_in = datapath_in;
endcase
end
register_file registerE(writenum, write, data_in, clk, readnum, data_out);
vDFFE loadax(clk, loooada, data_out, loada);
vDFFE loadbx(clk, loooadb, data_out, loadb);
shifter shiftx(loadb, shift, newloadb);
asel aselx(loada, selecta, Ain);
bsel bselx(newloadb, selectb, datapath_in, Bin);
ALU ALUx(Ain, Bin, ALUop, loadc, statusout);
vDFFE loadcx(clk, loooadc, loadc, datapath_out);
vDFFE loadsx(clk, loooadd, statusout, status10);
endmodule | 0 |
139,007 | data/full_repos/permissive/86668501/Lab5-L1D/datapath.v | 86,668,501 | datapath.v | v | 104 | 221 | [] | [] | [] | [(1, 29), (31, 43), (45, 57), (59, 103)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:71: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:73: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:75: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:77: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:79: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:81: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:83: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:85: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:87: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:89: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:91: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:93: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:95: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:97: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:99: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:101: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:19: Cannot find file containing module: \'register_file\'\n register_file registerE(writenum, write, data_in, clk, readnum, data_out);\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86668501/Lab5-L1D,data/full_repos/permissive/86668501/register_file\n data/full_repos/permissive/86668501/Lab5-L1D,data/full_repos/permissive/86668501/register_file.v\n data/full_repos/permissive/86668501/Lab5-L1D,data/full_repos/permissive/86668501/register_file.sv\n register_file\n register_file.v\n register_file.sv\n obj_dir/register_file\n obj_dir/register_file.v\n obj_dir/register_file.sv\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:20: Cannot find file containing module: \'vDFFE\'\n vDFFE loadax(clk, loooada, data_out, loada);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:21: Cannot find file containing module: \'vDFFE\'\n vDFFE loadbx(clk, loooadb, data_out, loadb);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:22: Cannot find file containing module: \'shifter\'\n shifter shiftx(loadb, shift, newloadb);\n ^~~~~~~\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:26: Cannot find file containing module: \'ALU\'\n ALU ALUx(Ain, Bin, ALUop, loadc, statusout);\n ^~~\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:27: Cannot find file containing module: \'vDFFE\'\n vDFFE loadcx(clk, loooadc, loadc, datapath_out);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:28: Cannot find file containing module: \'vDFFE\'\n vDFFE loadsx(clk, loooadd, statusout, status10);\n ^~~~~\n%Error: Exiting due to 7 error(s), 16 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,248 | module | module asel(loada, selecta, Ain);
input selecta;
input [15:0] loada;
output [15:0] Ain;
reg [15:0]Ain;
always@(*)begin
case(selecta)
1'b0 : Ain=loada;
1'b1 : Ain=16'b0000000000000000;
endcase
end
endmodule | module asel(loada, selecta, Ain); |
input selecta;
input [15:0] loada;
output [15:0] Ain;
reg [15:0]Ain;
always@(*)begin
case(selecta)
1'b0 : Ain=loada;
1'b1 : Ain=16'b0000000000000000;
endcase
end
endmodule | 0 |
139,008 | data/full_repos/permissive/86668501/Lab5-L1D/datapath.v | 86,668,501 | datapath.v | v | 104 | 221 | [] | [] | [] | [(1, 29), (31, 43), (45, 57), (59, 103)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:71: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:73: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:75: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:77: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:79: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:81: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:83: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:85: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:87: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:89: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:91: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:93: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:95: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:97: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:99: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:101: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:19: Cannot find file containing module: \'register_file\'\n register_file registerE(writenum, write, data_in, clk, readnum, data_out);\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86668501/Lab5-L1D,data/full_repos/permissive/86668501/register_file\n data/full_repos/permissive/86668501/Lab5-L1D,data/full_repos/permissive/86668501/register_file.v\n data/full_repos/permissive/86668501/Lab5-L1D,data/full_repos/permissive/86668501/register_file.sv\n register_file\n register_file.v\n register_file.sv\n obj_dir/register_file\n obj_dir/register_file.v\n obj_dir/register_file.sv\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:20: Cannot find file containing module: \'vDFFE\'\n vDFFE loadax(clk, loooada, data_out, loada);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:21: Cannot find file containing module: \'vDFFE\'\n vDFFE loadbx(clk, loooadb, data_out, loadb);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:22: Cannot find file containing module: \'shifter\'\n shifter shiftx(loadb, shift, newloadb);\n ^~~~~~~\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:26: Cannot find file containing module: \'ALU\'\n ALU ALUx(Ain, Bin, ALUop, loadc, statusout);\n ^~~\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:27: Cannot find file containing module: \'vDFFE\'\n vDFFE loadcx(clk, loooadc, loadc, datapath_out);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:28: Cannot find file containing module: \'vDFFE\'\n vDFFE loadsx(clk, loooadd, statusout, status10);\n ^~~~~\n%Error: Exiting due to 7 error(s), 16 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,248 | module | module bsel(newloadb, selectb, datapath_in, Bin);
input [15:0] datapath_in, newloadb;
input selectb;
output [15:0] Bin;
reg [15:0]Bin;
always@(*)begin
case(selectb)
1'b0 : Bin=newloadb;
1'b1 : {Bin}={11'b00000000000, datapath_in[4:0]};
endcase
end
endmodule | module bsel(newloadb, selectb, datapath_in, Bin); |
input [15:0] datapath_in, newloadb;
input selectb;
output [15:0] Bin;
reg [15:0]Bin;
always@(*)begin
case(selectb)
1'b0 : Bin=newloadb;
1'b1 : {Bin}={11'b00000000000, datapath_in[4:0]};
endcase
end
endmodule | 0 |
139,009 | data/full_repos/permissive/86668501/Lab5-L1D/datapath.v | 86,668,501 | datapath.v | v | 104 | 221 | [] | [] | [] | [(1, 29), (31, 43), (45, 57), (59, 103)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:71: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:73: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:75: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:77: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:79: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:81: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:83: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:85: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:87: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:89: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:91: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:93: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:95: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:97: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:99: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:101: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:19: Cannot find file containing module: \'register_file\'\n register_file registerE(writenum, write, data_in, clk, readnum, data_out);\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86668501/Lab5-L1D,data/full_repos/permissive/86668501/register_file\n data/full_repos/permissive/86668501/Lab5-L1D,data/full_repos/permissive/86668501/register_file.v\n data/full_repos/permissive/86668501/Lab5-L1D,data/full_repos/permissive/86668501/register_file.sv\n register_file\n register_file.v\n register_file.sv\n obj_dir/register_file\n obj_dir/register_file.v\n obj_dir/register_file.sv\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:20: Cannot find file containing module: \'vDFFE\'\n vDFFE loadax(clk, loooada, data_out, loada);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:21: Cannot find file containing module: \'vDFFE\'\n vDFFE loadbx(clk, loooadb, data_out, loadb);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:22: Cannot find file containing module: \'shifter\'\n shifter shiftx(loadb, shift, newloadb);\n ^~~~~~~\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:26: Cannot find file containing module: \'ALU\'\n ALU ALUx(Ain, Bin, ALUop, loadc, statusout);\n ^~~\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:27: Cannot find file containing module: \'vDFFE\'\n vDFFE loadcx(clk, loooadc, loadc, datapath_out);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab5-L1D/datapath.v:28: Cannot find file containing module: \'vDFFE\'\n vDFFE loadsx(clk, loooadd, statusout, status10);\n ^~~~~\n%Error: Exiting due to 7 error(s), 16 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,248 | module | module datapath_tb();
reg [15:0] datapath_in;
reg vsel, write, clk,selecta, selectb;
reg [2:0] writenum, readnum;
reg [1:0] ALUop, shift;
reg loooada,loooadb,loooadc,loooadd;
wire [15:0] datapath_out;
datapath dut(datapath_in, writenum, write, readnum, clk,vsel, selecta, selectb, shift, ALUop, loooada, loooadb, loooadc, loooadd, datapath_out);
initial begin
datapath_in=16'b0000000000000111 ; writenum=3'b000; write=1'b1; readnum =3'b000; clk =1'b1 ; vsel =1'b1; selecta= 1'b0; selectb=1'b0; shift=2'b00; ALUop=2'b00; loooada=1'b1;loooadb=1'b1;loooadc=1'b0;loooadd=1'b1;
#100
datapath_in=16'b0000000000000111 ; writenum=3'b000; write=1'b1; readnum =3'b000; clk =1'b0 ;
#10
datapath_in=16'b0000000000000010 ; writenum=3'b001; write=1'b1; readnum =3'b001; clk =1'b1 ; loooada=1'b0;loooadb=1'b1;loooadc=1'b0;loooadd=1'b1;
#100
datapath_in=16'b0000000000000010 ; writenum=3'b001; write=1'b1; readnum =3'b001; clk =1'b0 ;
#10
datapath_in=16'b0000000000000010 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b1 ; loooada=1'b1;loooadb=1'b0;loooadc=1'b0;loooadd=1'b1;
#100
datapath_in=16'b0000000000000010 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b0 ;
#10
datapath_in=16'b0000000001010101 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b1 ; loooada=1'b1;loooadb=1'b0;loooadc=1'b0;loooadd=1'b1;
#100
datapath_in=16'b0000000000000010 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b0 ;
#10
datapath_in=16'b1111111111111111 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b1 ; loooada=1'b1;loooadb=1'b1;loooadc=1'b1;loooadd=1'b1;
#100
datapath_in=16'b0000000000000000 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b0 ;
#10;
datapath_in=16'b0000000000000000 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b1 ; loooada=1'b1;loooadb=1'b1;loooadc=1'b1;loooadd=1'b1;
#100
datapath_in=16'b0000000000000000 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b0 ;
#10;
datapath_in=16'b0011001100110011 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b1 ; loooada=1'b1;loooadb=1'b1;loooadc=1'b1;loooadd=1'b1;
#100
datapath_in=16'b0011001100110011 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b0 ;
#10;
datapath_in=16'b0011001100110011 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b1 ; loooada=1'b1;loooadb=1'b1;loooadc=1'b1;loooadd=1'b1;
#100
datapath_in=16'b0011001100110011 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b0 ;
#10;
end
endmodule | module datapath_tb(); |
reg [15:0] datapath_in;
reg vsel, write, clk,selecta, selectb;
reg [2:0] writenum, readnum;
reg [1:0] ALUop, shift;
reg loooada,loooadb,loooadc,loooadd;
wire [15:0] datapath_out;
datapath dut(datapath_in, writenum, write, readnum, clk,vsel, selecta, selectb, shift, ALUop, loooada, loooadb, loooadc, loooadd, datapath_out);
initial begin
datapath_in=16'b0000000000000111 ; writenum=3'b000; write=1'b1; readnum =3'b000; clk =1'b1 ; vsel =1'b1; selecta= 1'b0; selectb=1'b0; shift=2'b00; ALUop=2'b00; loooada=1'b1;loooadb=1'b1;loooadc=1'b0;loooadd=1'b1;
#100
datapath_in=16'b0000000000000111 ; writenum=3'b000; write=1'b1; readnum =3'b000; clk =1'b0 ;
#10
datapath_in=16'b0000000000000010 ; writenum=3'b001; write=1'b1; readnum =3'b001; clk =1'b1 ; loooada=1'b0;loooadb=1'b1;loooadc=1'b0;loooadd=1'b1;
#100
datapath_in=16'b0000000000000010 ; writenum=3'b001; write=1'b1; readnum =3'b001; clk =1'b0 ;
#10
datapath_in=16'b0000000000000010 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b1 ; loooada=1'b1;loooadb=1'b0;loooadc=1'b0;loooadd=1'b1;
#100
datapath_in=16'b0000000000000010 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b0 ;
#10
datapath_in=16'b0000000001010101 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b1 ; loooada=1'b1;loooadb=1'b0;loooadc=1'b0;loooadd=1'b1;
#100
datapath_in=16'b0000000000000010 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b0 ;
#10
datapath_in=16'b1111111111111111 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b1 ; loooada=1'b1;loooadb=1'b1;loooadc=1'b1;loooadd=1'b1;
#100
datapath_in=16'b0000000000000000 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b0 ;
#10;
datapath_in=16'b0000000000000000 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b1 ; loooada=1'b1;loooadb=1'b1;loooadc=1'b1;loooadd=1'b1;
#100
datapath_in=16'b0000000000000000 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b0 ;
#10;
datapath_in=16'b0011001100110011 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b1 ; loooada=1'b1;loooadb=1'b1;loooadc=1'b1;loooadd=1'b1;
#100
datapath_in=16'b0011001100110011 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b0 ;
#10;
datapath_in=16'b0011001100110011 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b1 ; loooada=1'b1;loooadb=1'b1;loooadc=1'b1;loooadd=1'b1;
#100
datapath_in=16'b0011001100110011 ; writenum=3'b010; write=1'b1; readnum =3'b000; clk =1'b0 ;
#10;
end
endmodule | 0 |
139,010 | data/full_repos/permissive/86668501/Lab6-L1D/cpu.v | 86,668,501 | cpu.v | v | 161 | 128 | [] | [] | [] | [(1, 55), (57, 160)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:68: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:71: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:73: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:76: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:78: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:81: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:83: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:86: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:88: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:91: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:93: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:96: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:98: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:101: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:103: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:106: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:108: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:111: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:113: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:116: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:118: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:121: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:123: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:126: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:128: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:131: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:133: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:136: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:138: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:141: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:143: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:146: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:148: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:151: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:153: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:156: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:158: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:21: Cannot find file containing module: \'vDFFE\'\n vDFFE #(5) STATE(clk,1\'b1, next_state_reset,current_state);\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/86668501/Lab6-L1D,data/full_repos/permissive/86668501/vDFFE\n data/full_repos/permissive/86668501/Lab6-L1D,data/full_repos/permissive/86668501/vDFFE.v\n data/full_repos/permissive/86668501/Lab6-L1D,data/full_repos/permissive/86668501/vDFFE.sv\n vDFFE\n vDFFE.v\n vDFFE.sv\n obj_dir/vDFFE\n obj_dir/vDFFE.v\n obj_dir/vDFFE.sv\n%Error: Exiting due to 1 error(s), 37 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,252 | module | module cpu(clk, reset, opcode, op,loadpc, msel, mwrite, loadir, nsel, vsel, write, looada, looadb, looadc, looads, asel, bsel);
input reset, clk;
input [2:0] opcode;
input [1:0] op;
output loadir, loadpc, msel, mwrite, looada, looadb, looadc, looads, asel, bsel, write;
output [2:0] nsel;
output [1:0] vsel;
wire [4:0] current_state, next_state_reset;
reg [4:0] next_state;
reg [15:0] out;
`define HW 5
`define H0 5'b00000
`define H1 5'b00001
`define H2 5'b00010
`define H3 5'b00011
`define H4 5'b00100
`define H5 5'b00101
`define H6 5'b00110
vDFFE #(`HW) STATE(clk,1'b1, next_state_reset,current_state);
assign next_state_reset= reset ? `H0 : next_state;
always @(*) begin
casex ({current_state,opcode,op})
{`H0,3'bxxx,2'bxx} : {next_state,out} = {`H1,16'b0000000000000000};
{`H1,3'bxxx,2'bxx} : {next_state,out} = {`H2,16'b0001001000000000};
{`H2,3'bxxx,2'bxx} : {next_state,out} = {`H3,16'b1000001001000000};
{`H3,3'bxxx,2'bxx} : {next_state,out} = {`H4,16'b0000100000100000};
{`H4,3'b110,2'b10} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H5,4'b0000,3'b100,9'b001010000};
{`H5,3'b110,2'b10} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H6,4'b0000,3'b000,9'b000001100};
{`H6,3'b110,2'b10} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H1,4'b0000,3'b001,9'b100000000};
{`H4,3'b110,2'b00} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H5,4'b0000,3'b100,9'b001010000};
{`H5,3'b110,2'b00} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H6,4'b0000,3'b000,9'b000001100};
{`H6,3'b110,2'b00} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H1,4'b0000,3'b010,9'b100000000};
{`H4,3'b101,2'bx0} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H5,4'b0000,3'b100,9'b001010000};
{`H5,3'b101,2'bx0} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H6,4'b0000,3'b000,9'b000001100};
{`H6,3'b101,2'bx0} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H1,4'b0000,3'b010,9'b100000000};
{`H4,3'b101,2'b11} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H5,4'b0000,3'b100,9'b001010000};
{`H5,3'b101,2'b11} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H6,4'b0000,3'b000,9'b000001100};
{`H6,3'b101,2'b11} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H1,4'b0000,3'b010,9'b100000000};
{`H4,3'b101,2'b01} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H5,4'b0000,3'b100,9'b001010000};
{`H5,3'b101,2'b01} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H1,4'b0000,3'b010,9'b000000100};
endcase
end
assign {loadpc,msel,mwrite,loadir}={out[15:12]};
assign {nsel,vsel}={out[11:7]};
assign {write,looada,looadb,looadc,looads,asel,bsel}={out[6:0]};
endmodule | module cpu(clk, reset, opcode, op,loadpc, msel, mwrite, loadir, nsel, vsel, write, looada, looadb, looadc, looads, asel, bsel); |
input reset, clk;
input [2:0] opcode;
input [1:0] op;
output loadir, loadpc, msel, mwrite, looada, looadb, looadc, looads, asel, bsel, write;
output [2:0] nsel;
output [1:0] vsel;
wire [4:0] current_state, next_state_reset;
reg [4:0] next_state;
reg [15:0] out;
`define HW 5
`define H0 5'b00000
`define H1 5'b00001
`define H2 5'b00010
`define H3 5'b00011
`define H4 5'b00100
`define H5 5'b00101
`define H6 5'b00110
vDFFE #(`HW) STATE(clk,1'b1, next_state_reset,current_state);
assign next_state_reset= reset ? `H0 : next_state;
always @(*) begin
casex ({current_state,opcode,op})
{`H0,3'bxxx,2'bxx} : {next_state,out} = {`H1,16'b0000000000000000};
{`H1,3'bxxx,2'bxx} : {next_state,out} = {`H2,16'b0001001000000000};
{`H2,3'bxxx,2'bxx} : {next_state,out} = {`H3,16'b1000001001000000};
{`H3,3'bxxx,2'bxx} : {next_state,out} = {`H4,16'b0000100000100000};
{`H4,3'b110,2'b10} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H5,4'b0000,3'b100,9'b001010000};
{`H5,3'b110,2'b10} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H6,4'b0000,3'b000,9'b000001100};
{`H6,3'b110,2'b10} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H1,4'b0000,3'b001,9'b100000000};
{`H4,3'b110,2'b00} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H5,4'b0000,3'b100,9'b001010000};
{`H5,3'b110,2'b00} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H6,4'b0000,3'b000,9'b000001100};
{`H6,3'b110,2'b00} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H1,4'b0000,3'b010,9'b100000000};
{`H4,3'b101,2'bx0} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H5,4'b0000,3'b100,9'b001010000};
{`H5,3'b101,2'bx0} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H6,4'b0000,3'b000,9'b000001100};
{`H6,3'b101,2'bx0} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H1,4'b0000,3'b010,9'b100000000};
{`H4,3'b101,2'b11} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H5,4'b0000,3'b100,9'b001010000};
{`H5,3'b101,2'b11} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H6,4'b0000,3'b000,9'b000001100};
{`H6,3'b101,2'b11} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H1,4'b0000,3'b010,9'b100000000};
{`H4,3'b101,2'b01} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H5,4'b0000,3'b100,9'b001010000};
{`H5,3'b101,2'b01} : {next_state,out[15:12],out[11:9],out[8:0]} = {`H1,4'b0000,3'b010,9'b000000100};
endcase
end
assign {loadpc,msel,mwrite,loadir}={out[15:12]};
assign {nsel,vsel}={out[11:7]};
assign {write,looada,looadb,looadc,looads,asel,bsel}={out[6:0]};
endmodule | 0 |
139,011 | data/full_repos/permissive/86668501/Lab6-L1D/cpu.v | 86,668,501 | cpu.v | v | 161 | 128 | [] | [] | [] | [(1, 55), (57, 160)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:68: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:71: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:73: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:76: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:78: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:81: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:83: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:86: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:88: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:91: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:93: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:96: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:98: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:101: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:103: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:106: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:108: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:111: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:113: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:116: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:118: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:121: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:123: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:126: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:128: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:131: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:133: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:136: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:138: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:141: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:143: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:146: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:148: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:151: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:153: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:156: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:158: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/86668501/Lab6-L1D/cpu.v:21: Cannot find file containing module: \'vDFFE\'\n vDFFE #(5) STATE(clk,1\'b1, next_state_reset,current_state);\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/86668501/Lab6-L1D,data/full_repos/permissive/86668501/vDFFE\n data/full_repos/permissive/86668501/Lab6-L1D,data/full_repos/permissive/86668501/vDFFE.v\n data/full_repos/permissive/86668501/Lab6-L1D,data/full_repos/permissive/86668501/vDFFE.sv\n vDFFE\n vDFFE.v\n vDFFE.sv\n obj_dir/vDFFE\n obj_dir/vDFFE.v\n obj_dir/vDFFE.sv\n%Error: Exiting due to 1 error(s), 37 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,252 | module | module cpu_tb();
reg reset, clk;
reg [2:0] opcode;
reg [1:0] op;
wire loadir, loadpc, msel, mwrite, looada, looadb, looadc, looads, asel, bsel, write;
wire [2:0] nsel;
wire [1:0] vsel;
cpu dut(clk, reset, opcode, op, loadpc, msel, mwrite, loadir, nsel, vsel, write, looada, looadb, looadc, looads, asel, bsel);
initial begin
clk=1'b0;reset=1'b1;opcode=3'b110; op=2'b10;
#100
clk=1'b1;reset=1'b0;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;opcode=3'b101; op=2'b00;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;opcode=3'b101;op=2'b01;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
end
endmodule | module cpu_tb(); |
reg reset, clk;
reg [2:0] opcode;
reg [1:0] op;
wire loadir, loadpc, msel, mwrite, looada, looadb, looadc, looads, asel, bsel, write;
wire [2:0] nsel;
wire [1:0] vsel;
cpu dut(clk, reset, opcode, op, loadpc, msel, mwrite, loadir, nsel, vsel, write, looada, looadb, looadc, looads, asel, bsel);
initial begin
clk=1'b0;reset=1'b1;opcode=3'b110; op=2'b10;
#100
clk=1'b1;reset=1'b0;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;opcode=3'b101; op=2'b00;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;opcode=3'b101;op=2'b01;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
end
endmodule | 0 |
139,012 | data/full_repos/permissive/86668501/Lab6-L1D/datapath.v | 86,668,501 | datapath.v | v | 262 | 216 | [] | [] | [] | [(1, 44), (46, 61), (63, 98), (100, 120), (122, 211)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:132: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:135: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:137: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:139: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:142: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:144: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:146: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:149: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:151: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:153: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:156: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:158: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:160: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:163: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:165: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:167: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:170: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:172: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:174: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:177: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:179: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:181: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:184: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:186: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:188: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:191: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:193: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:195: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:198: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:200: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:202: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:205: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:207: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:209: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:122: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'datapath\'\nmodule datapath(clk,writenum,write,readnum,vsel,sximm5,sximm8,mdata,asel,bsel,shift,ALUop,looada,looadb,looadc,looads,datapath_out);\n ^~~~~~~~\n : ... Top module \'PC_tb\'\nmodule PC_tb();\n ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Signal definition not found, creating implicitly: \'nsel\'\n : ... Suggested alternative: \'bsel\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Signal definition not found, creating implicitly: \'opcode\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Signal definition not found, creating implicitly: \'op\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:13: Assigning to input/const variable: \'mdata\'\n Program_counter PCx(clk, reset, loadpc, loadb, loadc, msel, loadir, mwrite, PC, mdata, IR);\n ^~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'ALUop\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'readnum\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'writenum\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'shift\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'sximm8\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'sximm5\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~\n%Error: Exiting due to 7 error(s), 38 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,253 | module | module datapath(clk,writenum,write,readnum,vsel,sximm5,sximm8,mdata,asel,bsel,shift,ALUop,looada,looadb,looadc,looads,datapath_out);
input [15:0] sximm5, sximm8, mdata;
input write, clk, asel, bsel, looada, looadb, looadc, looads;
input [2:0] writenum, readnum;
input [1:0] vsel, ALUop, shift;
output [15:0] datapath_out;
wire [15:0] data_out, loada, loadb, newloadb, loadc, IR;
wire [7:0] PC;
wire [2:0] status, status_out;
wire loadpc, msel, mwrite, loadir, reset;
reg [15:0] data_in, Ain, Bin;
Program_counter PCx(clk, reset, loadpc, loadb, loadc, msel, loadir, mwrite, PC, mdata, IR);
instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);
cpu FSMx(clk, reset, opcode, op, loadpc, msel, mwrite, loadir, nsel, vsel, write, looada, looadb, looadc, looads, asel, bsel);
always @(*)begin
case(vsel)
2'b11 : data_in = mdata;
2'b10 : data_in = sximm8;
2'b01 : data_in = {8'b0,PC};
2'b00 : data_in = loadc;
endcase
end
register_file regfilex(writenum, write, data_in, clk, readnum, data_out);
vDFFE loadax(clk, looada, data_out, loada);
vDFFE loadbx(clk, looadb, data_out, loadb);
shifter shiftx(loadb, shift, newloadb);
always@(*)begin
case(asel)
1'b0 : Ain=loada;
1'b1 : Ain=16'b0000000000000000;
endcase
end
always@(*)begin
case(bsel)
1'b0 : Bin=newloadb;
1'b1 : Bin=sximm5;
endcase
end
ALU ALUx(Ain, Bin, ALUop, loadc, status);
vDFFE loadcx(clk, looadc, loadc, datapath_out);
vDFFE loadsx(clk, looads, status, status_out);
endmodule | module datapath(clk,writenum,write,readnum,vsel,sximm5,sximm8,mdata,asel,bsel,shift,ALUop,looada,looadb,looadc,looads,datapath_out); |
input [15:0] sximm5, sximm8, mdata;
input write, clk, asel, bsel, looada, looadb, looadc, looads;
input [2:0] writenum, readnum;
input [1:0] vsel, ALUop, shift;
output [15:0] datapath_out;
wire [15:0] data_out, loada, loadb, newloadb, loadc, IR;
wire [7:0] PC;
wire [2:0] status, status_out;
wire loadpc, msel, mwrite, loadir, reset;
reg [15:0] data_in, Ain, Bin;
Program_counter PCx(clk, reset, loadpc, loadb, loadc, msel, loadir, mwrite, PC, mdata, IR);
instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);
cpu FSMx(clk, reset, opcode, op, loadpc, msel, mwrite, loadir, nsel, vsel, write, looada, looadb, looadc, looads, asel, bsel);
always @(*)begin
case(vsel)
2'b11 : data_in = mdata;
2'b10 : data_in = sximm8;
2'b01 : data_in = {8'b0,PC};
2'b00 : data_in = loadc;
endcase
end
register_file regfilex(writenum, write, data_in, clk, readnum, data_out);
vDFFE loadax(clk, looada, data_out, loada);
vDFFE loadbx(clk, looadb, data_out, loadb);
shifter shiftx(loadb, shift, newloadb);
always@(*)begin
case(asel)
1'b0 : Ain=loada;
1'b1 : Ain=16'b0000000000000000;
endcase
end
always@(*)begin
case(bsel)
1'b0 : Bin=newloadb;
1'b1 : Bin=sximm5;
endcase
end
ALU ALUx(Ain, Bin, ALUop, loadc, status);
vDFFE loadcx(clk, looadc, loadc, datapath_out);
vDFFE loadsx(clk, looads, status, status_out);
endmodule | 0 |
139,013 | data/full_repos/permissive/86668501/Lab6-L1D/datapath.v | 86,668,501 | datapath.v | v | 262 | 216 | [] | [] | [] | [(1, 44), (46, 61), (63, 98), (100, 120), (122, 211)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:132: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:135: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:137: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:139: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:142: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:144: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:146: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:149: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:151: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:153: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:156: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:158: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:160: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:163: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:165: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:167: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:170: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:172: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:174: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:177: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:179: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:181: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:184: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:186: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:188: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:191: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:193: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:195: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:198: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:200: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:202: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:205: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:207: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:209: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:122: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'datapath\'\nmodule datapath(clk,writenum,write,readnum,vsel,sximm5,sximm8,mdata,asel,bsel,shift,ALUop,looada,looadb,looadc,looads,datapath_out);\n ^~~~~~~~\n : ... Top module \'PC_tb\'\nmodule PC_tb();\n ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Signal definition not found, creating implicitly: \'nsel\'\n : ... Suggested alternative: \'bsel\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Signal definition not found, creating implicitly: \'opcode\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Signal definition not found, creating implicitly: \'op\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:13: Assigning to input/const variable: \'mdata\'\n Program_counter PCx(clk, reset, loadpc, loadb, loadc, msel, loadir, mwrite, PC, mdata, IR);\n ^~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'ALUop\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'readnum\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'writenum\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'shift\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'sximm8\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'sximm5\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~\n%Error: Exiting due to 7 error(s), 38 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,253 | module | module Program_counter(clk, reset, loadpc, loadb, loadc, msel, loadir, mwrite, PC, mdata, IR);
input clk, loadpc, reset, msel, loadir, mwrite;
input [15:0] loadb, loadc;
output [15:0] IR, mdata;
output [7:0] PC;
wire [7:0] pc1, reset_wire, address;
wire [15:0] mdata,IR;
assign pc1=loadpc ? (PC+1) : PC;
assign reset_wire= ~reset ? (pc1) : 8'b00000000;
vDFFE PCx(clk, 1'b1, reset_wire, PC);
assign address=msel ? (loadc[7:0]) : PC;
RAM ramx(clk, address, address, mwrite, loadb, mdata);
vDFFE IRx(clk, loadir, mdata, IR);
endmodule | module Program_counter(clk, reset, loadpc, loadb, loadc, msel, loadir, mwrite, PC, mdata, IR); |
input clk, loadpc, reset, msel, loadir, mwrite;
input [15:0] loadb, loadc;
output [15:0] IR, mdata;
output [7:0] PC;
wire [7:0] pc1, reset_wire, address;
wire [15:0] mdata,IR;
assign pc1=loadpc ? (PC+1) : PC;
assign reset_wire= ~reset ? (pc1) : 8'b00000000;
vDFFE PCx(clk, 1'b1, reset_wire, PC);
assign address=msel ? (loadc[7:0]) : PC;
RAM ramx(clk, address, address, mwrite, loadb, mdata);
vDFFE IRx(clk, loadir, mdata, IR);
endmodule | 0 |
139,014 | data/full_repos/permissive/86668501/Lab6-L1D/datapath.v | 86,668,501 | datapath.v | v | 262 | 216 | [] | [] | [] | [(1, 44), (46, 61), (63, 98), (100, 120), (122, 211)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:132: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:135: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:137: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:139: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:142: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:144: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:146: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:149: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:151: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:153: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:156: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:158: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:160: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:163: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:165: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:167: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:170: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:172: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:174: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:177: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:179: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:181: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:184: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:186: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:188: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:191: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:193: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:195: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:198: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:200: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:202: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:205: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:207: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:209: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:122: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'datapath\'\nmodule datapath(clk,writenum,write,readnum,vsel,sximm5,sximm8,mdata,asel,bsel,shift,ALUop,looada,looadb,looadc,looads,datapath_out);\n ^~~~~~~~\n : ... Top module \'PC_tb\'\nmodule PC_tb();\n ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Signal definition not found, creating implicitly: \'nsel\'\n : ... Suggested alternative: \'bsel\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Signal definition not found, creating implicitly: \'opcode\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Signal definition not found, creating implicitly: \'op\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:13: Assigning to input/const variable: \'mdata\'\n Program_counter PCx(clk, reset, loadpc, loadb, loadc, msel, loadir, mwrite, PC, mdata, IR);\n ^~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'ALUop\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'readnum\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'writenum\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'shift\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'sximm8\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'sximm5\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~\n%Error: Exiting due to 7 error(s), 38 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,253 | module | module instruction_dec(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);
input [15:0] IR;
output [2:0] opcode, readnum, writenum, nsel;
output [1:0] ALUop, op, shift;
output [15:0] sximm8, sximm5;
wire [2:0] Rn, Rd, Rm;
reg [15:0] sximm8, sximm5;
reg [2:0] readnum, writenum;
assign opcode=IR[15:13];
assign op=IR[12:11];
assign ALUop=IR[12:11];
assign shift=IR[4:3];
assign {Rn,Rd,Rm}={IR[10:8],IR[7:5],IR[2:0]};
always @(*)begin
case (IR[7])
1'b0 : sximm8={8'b0,IR[7:0]};
1'b1 : sximm8={8'b1,IR[7:0]};
endcase
end
always @(*)begin
case(IR[4])
1'b0 : sximm5={11'b0,IR[4:0]};
1'b1 : sximm5={11'b1,IR[4:0]};
endcase
end
always @(*)begin
case(nsel)
3'b001 : {readnum,writenum}={IR[10:8],IR[10:8]};
3'b010 : {readnum,writenum}={IR[7:5],IR[7:5]};
3'b100 : {readnum,writenum}={IR[2:0],IR[2:0]};
default: {readnum,writenum}={3'b000,3'b000};
endcase
end
endmodule | module instruction_dec(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5); |
input [15:0] IR;
output [2:0] opcode, readnum, writenum, nsel;
output [1:0] ALUop, op, shift;
output [15:0] sximm8, sximm5;
wire [2:0] Rn, Rd, Rm;
reg [15:0] sximm8, sximm5;
reg [2:0] readnum, writenum;
assign opcode=IR[15:13];
assign op=IR[12:11];
assign ALUop=IR[12:11];
assign shift=IR[4:3];
assign {Rn,Rd,Rm}={IR[10:8],IR[7:5],IR[2:0]};
always @(*)begin
case (IR[7])
1'b0 : sximm8={8'b0,IR[7:0]};
1'b1 : sximm8={8'b1,IR[7:0]};
endcase
end
always @(*)begin
case(IR[4])
1'b0 : sximm5={11'b0,IR[4:0]};
1'b1 : sximm5={11'b1,IR[4:0]};
endcase
end
always @(*)begin
case(nsel)
3'b001 : {readnum,writenum}={IR[10:8],IR[10:8]};
3'b010 : {readnum,writenum}={IR[7:5],IR[7:5]};
3'b100 : {readnum,writenum}={IR[2:0],IR[2:0]};
default: {readnum,writenum}={3'b000,3'b000};
endcase
end
endmodule | 0 |
139,015 | data/full_repos/permissive/86668501/Lab6-L1D/datapath.v | 86,668,501 | datapath.v | v | 262 | 216 | [] | [] | [] | [(1, 44), (46, 61), (63, 98), (100, 120), (122, 211)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:132: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:135: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:137: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:139: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:142: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:144: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:146: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:149: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:151: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:153: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:156: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:158: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:160: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:163: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:165: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:167: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:170: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:172: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:174: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:177: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:179: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:181: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:184: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:186: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:188: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:191: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:193: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:195: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:198: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:200: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:202: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:205: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:207: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:209: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:122: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'datapath\'\nmodule datapath(clk,writenum,write,readnum,vsel,sximm5,sximm8,mdata,asel,bsel,shift,ALUop,looada,looadb,looadc,looads,datapath_out);\n ^~~~~~~~\n : ... Top module \'PC_tb\'\nmodule PC_tb();\n ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Signal definition not found, creating implicitly: \'nsel\'\n : ... Suggested alternative: \'bsel\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Signal definition not found, creating implicitly: \'opcode\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Signal definition not found, creating implicitly: \'op\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:13: Assigning to input/const variable: \'mdata\'\n Program_counter PCx(clk, reset, loadpc, loadb, loadc, msel, loadir, mwrite, PC, mdata, IR);\n ^~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'ALUop\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'readnum\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'writenum\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'shift\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'sximm8\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'sximm5\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~\n%Error: Exiting due to 7 error(s), 38 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,253 | module | module RAM(clk, read_address, write_address, write, din, dout);
parameter data_width = 16;
parameter addr_width = 8;
parameter filename = "data.txt";
input clk;
input [addr_width-1:0] read_address, write_address;
input write;
input [data_width-1:0] din;
output [data_width-1:0] dout;
reg [data_width-1:0] dout;
reg [data_width-1:0] mem [2**addr_width-1:0];
initial $readmemb(filename,mem);
always @(posedge clk) begin
if (write)
mem[write_address] <=din;
dout <= mem[read_address];
end
endmodule | module RAM(clk, read_address, write_address, write, din, dout); |
parameter data_width = 16;
parameter addr_width = 8;
parameter filename = "data.txt";
input clk;
input [addr_width-1:0] read_address, write_address;
input write;
input [data_width-1:0] din;
output [data_width-1:0] dout;
reg [data_width-1:0] dout;
reg [data_width-1:0] mem [2**addr_width-1:0];
initial $readmemb(filename,mem);
always @(posedge clk) begin
if (write)
mem[write_address] <=din;
dout <= mem[read_address];
end
endmodule | 0 |
139,016 | data/full_repos/permissive/86668501/Lab6-L1D/datapath.v | 86,668,501 | datapath.v | v | 262 | 216 | [] | [] | [] | [(1, 44), (46, 61), (63, 98), (100, 120), (122, 211)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:132: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:135: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:137: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:139: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:142: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:144: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:146: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:149: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:151: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:153: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:156: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:158: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:160: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:163: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:165: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:167: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:170: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:172: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:174: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:177: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:179: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:181: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:184: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:186: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:188: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:191: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:193: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:195: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:198: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:200: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:202: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:205: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:207: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:209: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:122: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'datapath\'\nmodule datapath(clk,writenum,write,readnum,vsel,sximm5,sximm8,mdata,asel,bsel,shift,ALUop,looada,looadb,looadc,looads,datapath_out);\n ^~~~~~~~\n : ... Top module \'PC_tb\'\nmodule PC_tb();\n ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Signal definition not found, creating implicitly: \'nsel\'\n : ... Suggested alternative: \'bsel\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Signal definition not found, creating implicitly: \'opcode\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Signal definition not found, creating implicitly: \'op\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:13: Assigning to input/const variable: \'mdata\'\n Program_counter PCx(clk, reset, loadpc, loadb, loadc, msel, loadir, mwrite, PC, mdata, IR);\n ^~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'ALUop\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'readnum\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'writenum\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'shift\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'sximm8\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/86668501/Lab6-L1D/datapath.v:14: Assigning to input/const variable: \'sximm5\'\n instruction_dec Instruc_Decx(IR, nsel, opcode, op, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~\n%Error: Exiting due to 7 error(s), 38 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,253 | module | module PC_tb();
reg clk, loadpc, reset, msel, loadir, mwrite;
reg [15:0] loadb, loadc;
wire [15:0] IR, mdata;
wire [7:0] PC;
Program_counter dut(clk, reset, loadpc, loadb, loadc, msel, loadir, mwrite,PC, mdata, IR);
initial begin
clk=1'b0; reset=1'b1; loadb=16'b1111111111111111;loadc=16'b0000000000000000; loadpc=1'b0; loadir=1'b0; msel=1'b0; mwrite=1'b0;
#20
clk=1'b1;
#10
clk=1'b1; reset=1'b0; loadpc=1'b0; loadir=1'b0; msel=1'b0; mwrite=1'b0;
#10
clk=1'b0;
#20
clk=1'b1;
#10
clk=1'b1; loadir=1'b1;
#10
clk=1'b0;
#20
clk=1'b1;
#10
clk=1'b1; loadir=1'b0; loadpc=1'b1;
#10
clk=1'b0;
#20
clk=1'b1;
#10
clk=1'b1; loadpc=1'b0;
#10
clk=1'b0;
#20
clk=1'b1;
#10
clk=1'b1; loadir=1'b1;
#10
clk=1'b0;
#20
clk=1'b1;
#10
clk=1'b1; loadir=1'b0; loadpc=1'b1;
#10
clk=1'b0;
#20
clk=1'b1;
#10
clk=1'b1; loadpc=1'b0;
#10
clk=1'b0;
#20;
clk=1'b1;
#10
clk=1'b1; loadir=1'b1;
#10
clk=1'b0;
#20
clk=1'b1;
#10
clk=1'b1; loadir=1'b0; loadpc=1'b1;
#10
clk=1'b0;
#20
clk=1'b1;
#10
clk=1'b1; loadpc=1'b0;
#10
clk=1'b0;
#20;
clk=1'b1;
#10
clk=1'b1; loadir=1'b1;
#10
clk=1'b0;
#20;
end
endmodule | module PC_tb(); |
reg clk, loadpc, reset, msel, loadir, mwrite;
reg [15:0] loadb, loadc;
wire [15:0] IR, mdata;
wire [7:0] PC;
Program_counter dut(clk, reset, loadpc, loadb, loadc, msel, loadir, mwrite,PC, mdata, IR);
initial begin
clk=1'b0; reset=1'b1; loadb=16'b1111111111111111;loadc=16'b0000000000000000; loadpc=1'b0; loadir=1'b0; msel=1'b0; mwrite=1'b0;
#20
clk=1'b1;
#10
clk=1'b1; reset=1'b0; loadpc=1'b0; loadir=1'b0; msel=1'b0; mwrite=1'b0;
#10
clk=1'b0;
#20
clk=1'b1;
#10
clk=1'b1; loadir=1'b1;
#10
clk=1'b0;
#20
clk=1'b1;
#10
clk=1'b1; loadir=1'b0; loadpc=1'b1;
#10
clk=1'b0;
#20
clk=1'b1;
#10
clk=1'b1; loadpc=1'b0;
#10
clk=1'b0;
#20
clk=1'b1;
#10
clk=1'b1; loadir=1'b1;
#10
clk=1'b0;
#20
clk=1'b1;
#10
clk=1'b1; loadir=1'b0; loadpc=1'b1;
#10
clk=1'b0;
#20
clk=1'b1;
#10
clk=1'b1; loadpc=1'b0;
#10
clk=1'b0;
#20;
clk=1'b1;
#10
clk=1'b1; loadir=1'b1;
#10
clk=1'b0;
#20
clk=1'b1;
#10
clk=1'b1; loadir=1'b0; loadpc=1'b1;
#10
clk=1'b0;
#20
clk=1'b1;
#10
clk=1'b1; loadpc=1'b0;
#10
clk=1'b0;
#20;
clk=1'b1;
#10
clk=1'b1; loadir=1'b1;
#10
clk=1'b0;
#20;
end
endmodule | 0 |
139,017 | data/full_repos/permissive/86668501/Lab6-L1D/regfile.v | 86,668,501 | regfile.v | v | 158 | 90 | [] | [] | [] | null | line:39: before: "{" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:104: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:106: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:108: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:110: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:112: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:114: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:116: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:118: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:132: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:134: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:136: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:138: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:140: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:142: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:144: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:146: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:148: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:150: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:152: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:122: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'vDFFE_tb\'\nmodule vDFFE_tb();\n ^~~~~~~~\n : ... Top module \'regfile_tb\'\nmodule regfile_tb();\n ^~~~~~~~~~\n%Error: Exiting due to 20 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,254 | module | module register_file (writenum, write, data_in, clk, readnum, data_out);
input [2:0] writenum, readnum;
input write, clk;
input [15:0] data_in;
output [15:0] data_out;
wire [7:0] hot_code_out;
reg [15:0] R0,R1,R2,R3,R4,R5,R6,R7;
wire [15:0] a0,a1,a2,a3,a4,a5,a6,a7;
Dec #(3,8) dec_write(writenum, hot_code_out);
assign a0=R0;
assign a1=R1;
assign a2=R2;
assign a3=R3;
assign a4=R4;
assign a5=R5;
assign a6=R6;
assign a7=R7;
vDFFE #(16) R0_next(clk,write,data_in,a0);
vDFFE #(16) R1_next(clk,write,data_in,a1);
vDFFE #(16) R2_next(clk,write,data_in,a2);
vDFFE #(16) R3_next(clk,write,data_in,a3);
vDFFE #(16) R4_next(clk,write,data_in,a4);
vDFFE #(16) R5_next(clk,write,data_in,a5);
vDFFE #(16) R6_next(clk,write,data_in,a6);
vDFFE #(16) R7_next(clk,write,data_in,a7);
always@(*)begin
case(hot_code_out)
8'b00000001 : {R0}={data_in};
8'b00000010 : {R1}={data_in};
8'b00000100 : {R2}={data_in};
8'b00001000 : {R3}={data_in};
8'b00010000 : {R4}={data_in};
8'b00100000 : {R5}={data_in};
8'b01000000 : {R6}={data_in};
8'b10000000 : {R7}={data_in};
default {R0,R1,R2,R3,R4,R5,R6,R7}={128'b0};
endcase
end
Mux_DEC mux_readx(R7,R6,R5,R4,R3,R2,R1,R0,readnum,data_out);
endmodule | module register_file (writenum, write, data_in, clk, readnum, data_out); |
input [2:0] writenum, readnum;
input write, clk;
input [15:0] data_in;
output [15:0] data_out;
wire [7:0] hot_code_out;
reg [15:0] R0,R1,R2,R3,R4,R5,R6,R7;
wire [15:0] a0,a1,a2,a3,a4,a5,a6,a7;
Dec #(3,8) dec_write(writenum, hot_code_out);
assign a0=R0;
assign a1=R1;
assign a2=R2;
assign a3=R3;
assign a4=R4;
assign a5=R5;
assign a6=R6;
assign a7=R7;
vDFFE #(16) R0_next(clk,write,data_in,a0);
vDFFE #(16) R1_next(clk,write,data_in,a1);
vDFFE #(16) R2_next(clk,write,data_in,a2);
vDFFE #(16) R3_next(clk,write,data_in,a3);
vDFFE #(16) R4_next(clk,write,data_in,a4);
vDFFE #(16) R5_next(clk,write,data_in,a5);
vDFFE #(16) R6_next(clk,write,data_in,a6);
vDFFE #(16) R7_next(clk,write,data_in,a7);
always@(*)begin
case(hot_code_out)
8'b00000001 : {R0}={data_in};
8'b00000010 : {R1}={data_in};
8'b00000100 : {R2}={data_in};
8'b00001000 : {R3}={data_in};
8'b00010000 : {R4}={data_in};
8'b00100000 : {R5}={data_in};
8'b01000000 : {R6}={data_in};
8'b10000000 : {R7}={data_in};
default {R0,R1,R2,R3,R4,R5,R6,R7}={128'b0};
endcase
end
Mux_DEC mux_readx(R7,R6,R5,R4,R3,R2,R1,R0,readnum,data_out);
endmodule | 0 |
139,018 | data/full_repos/permissive/86668501/Lab6-L1D/regfile.v | 86,668,501 | regfile.v | v | 158 | 90 | [] | [] | [] | null | line:39: before: "{" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:104: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:106: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:108: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:110: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:112: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:114: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:116: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:118: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:132: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:134: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:136: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:138: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:140: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:142: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:144: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:146: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:148: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:150: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:152: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:122: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'vDFFE_tb\'\nmodule vDFFE_tb();\n ^~~~~~~~\n : ... Top module \'regfile_tb\'\nmodule regfile_tb();\n ^~~~~~~~~~\n%Error: Exiting due to 20 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,254 | module | module Dec(a, b);
parameter n=3;
parameter m=8;
input[n-1:0] a;
output[m-1:0] b;
wire [m-1:0] b = 1<<a;
endmodule | module Dec(a, b); |
parameter n=3;
parameter m=8;
input[n-1:0] a;
output[m-1:0] b;
wire [m-1:0] b = 1<<a;
endmodule | 0 |
139,019 | data/full_repos/permissive/86668501/Lab6-L1D/regfile.v | 86,668,501 | regfile.v | v | 158 | 90 | [] | [] | [] | null | line:39: before: "{" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:104: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:106: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:108: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:110: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:112: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:114: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:116: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:118: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:132: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:134: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:136: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:138: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:140: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:142: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:144: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:146: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:148: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:150: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:152: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:122: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'vDFFE_tb\'\nmodule vDFFE_tb();\n ^~~~~~~~\n : ... Top module \'regfile_tb\'\nmodule regfile_tb();\n ^~~~~~~~~~\n%Error: Exiting due to 20 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,254 | module | module vDFFE (clk, write, in, out) ;
parameter n = 16;
input clk, write ;
input [n-1:0] in ;
output [n-1:0] out ;
reg [n-1:0] out ;
wire [n-1:0] next_out;
assign next_out = write ? in : out;
always @(posedge clk)
out = next_out;
endmodule | module vDFFE (clk, write, in, out) ; |
parameter n = 16;
input clk, write ;
input [n-1:0] in ;
output [n-1:0] out ;
reg [n-1:0] out ;
wire [n-1:0] next_out;
assign next_out = write ? in : out;
always @(posedge clk)
out = next_out;
endmodule | 0 |
139,020 | data/full_repos/permissive/86668501/Lab6-L1D/regfile.v | 86,668,501 | regfile.v | v | 158 | 90 | [] | [] | [] | null | line:39: before: "{" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:104: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:106: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:108: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:110: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:112: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:114: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:116: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:118: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:132: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:134: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:136: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:138: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:140: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:142: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:144: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:146: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:148: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:150: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:152: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:122: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'vDFFE_tb\'\nmodule vDFFE_tb();\n ^~~~~~~~\n : ... Top module \'regfile_tb\'\nmodule regfile_tb();\n ^~~~~~~~~~\n%Error: Exiting due to 20 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,254 | module | module Mux_DEC (a7,a6,a5,a4,a3,a2,a1,a0,readnum,data_out);
parameter j=8;
parameter k=16;
input [k-1:0] a7,a6,a5,a4,a3,a2,a1,a0;
input [2:0] readnum;
output [k-1:0] data_out;
reg [k-1:0] data_out;
wire [j-1:0] s;
Dec #(3,8) dec_read(readnum,s);
always@(*)begin
case(s)
8'b00000001 : data_out=a0;
8'b00000010 : data_out=a1;
8'b00000100 : data_out=a2;
8'b00001000 : data_out=a3;
8'b00010000 : data_out=a4;
8'b00100000 : data_out=a5;
8'b01000000 : data_out=a6;
8'b10000000 : data_out=a7;
endcase
end
endmodule | module Mux_DEC (a7,a6,a5,a4,a3,a2,a1,a0,readnum,data_out); |
parameter j=8;
parameter k=16;
input [k-1:0] a7,a6,a5,a4,a3,a2,a1,a0;
input [2:0] readnum;
output [k-1:0] data_out;
reg [k-1:0] data_out;
wire [j-1:0] s;
Dec #(3,8) dec_read(readnum,s);
always@(*)begin
case(s)
8'b00000001 : data_out=a0;
8'b00000010 : data_out=a1;
8'b00000100 : data_out=a2;
8'b00001000 : data_out=a3;
8'b00010000 : data_out=a4;
8'b00100000 : data_out=a5;
8'b01000000 : data_out=a6;
8'b10000000 : data_out=a7;
endcase
end
endmodule | 0 |
139,021 | data/full_repos/permissive/86668501/Lab6-L1D/regfile.v | 86,668,501 | regfile.v | v | 158 | 90 | [] | [] | [] | null | line:39: before: "{" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:104: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:106: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:108: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:110: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:112: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:114: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:116: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:118: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:132: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:134: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:136: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:138: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:140: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:142: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:144: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:146: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:148: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:150: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:152: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:122: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'vDFFE_tb\'\nmodule vDFFE_tb();\n ^~~~~~~~\n : ... Top module \'regfile_tb\'\nmodule regfile_tb();\n ^~~~~~~~~~\n%Error: Exiting due to 20 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,254 | module | module vDFFE_tb();
parameter n = 16;
reg clk, write ;
reg [n-1:0] in ;
wire [n-1:0] out ;
vDFFE dut(clk, write, in, out);
initial begin
clk=1'b1; write=1'b1;in=16'b0001110001110001;
#100
clk=1'b0; write=1'b0;in=16'b0001110001110001;
#100
clk=1'b1; write=1'b0;in=16'b0001110001110001;
#100
clk=1'b0; write=1'b1;in=16'b0001110001110001;
#100
clk=1'b1; write=1'b1;in=16'b0100011100101010;
#100
clk=1'b0; write=1'b1;in=16'b0100011100101010;
#100
clk=1'b1; write=1'b1;in=16'b0001110001110001;
#100
clk=1'b0; write=1'b1;in=16'b0001110001110001;
#100;
end
endmodule | module vDFFE_tb(); |
parameter n = 16;
reg clk, write ;
reg [n-1:0] in ;
wire [n-1:0] out ;
vDFFE dut(clk, write, in, out);
initial begin
clk=1'b1; write=1'b1;in=16'b0001110001110001;
#100
clk=1'b0; write=1'b0;in=16'b0001110001110001;
#100
clk=1'b1; write=1'b0;in=16'b0001110001110001;
#100
clk=1'b0; write=1'b1;in=16'b0001110001110001;
#100
clk=1'b1; write=1'b1;in=16'b0100011100101010;
#100
clk=1'b0; write=1'b1;in=16'b0100011100101010;
#100
clk=1'b1; write=1'b1;in=16'b0001110001110001;
#100
clk=1'b0; write=1'b1;in=16'b0001110001110001;
#100;
end
endmodule | 0 |
139,022 | data/full_repos/permissive/86668501/Lab6-L1D/regfile.v | 86,668,501 | regfile.v | v | 158 | 90 | [] | [] | [] | null | line:39: before: "{" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:104: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:106: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:108: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:110: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:112: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:114: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:116: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:118: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:132: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:134: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:136: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:138: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:140: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:142: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:144: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:146: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:148: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:150: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:152: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab6-L1D/regfile.v:122: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'vDFFE_tb\'\nmodule vDFFE_tb();\n ^~~~~~~~\n : ... Top module \'regfile_tb\'\nmodule regfile_tb();\n ^~~~~~~~~~\n%Error: Exiting due to 20 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,254 | module | module regfile_tb();
reg [2:0] writenum, readnum;
reg write, clk;
reg [15:0] data_in;
wire [15:0] data_out;
register_file dut(writenum, write, data_in, clk, readnum, data_out);
initial begin
writenum=3'b010; write=1'b1; data_in=16'b1111000000000000; clk=1'b1; readnum=3'b010;
#100
writenum=3'b010; write=1'b1; data_in=16'b0000111100000000; clk=1'b1; readnum=3'b010;
#100
writenum=3'b100; write=1'b1; data_in=16'b0000000011110000; clk=1'b1; readnum=3'b100;
#100
writenum=3'b001; write=1'b1; data_in=16'b0000000000001111; clk=1'b1; readnum=3'b001;
#100
writenum=3'b110; write=1'b1; data_in=16'b0000000011111111; clk=1'b1; readnum=3'b111;
#100
writenum=3'b000; write=1'b1; data_in=16'b0000111111111111; clk=1'b1; readnum=3'b000;
#100
writenum=3'b110; write=1'b1; data_in=16'b1111111111111111; clk=1'b1; readnum=3'b000;
#100
writenum=3'b001; write=1'b1; data_in=16'b0000111111111111; clk=1'b1; readnum=3'b001;
#100
writenum=3'b011; write=1'b1; data_in=16'b0000000011111111; clk=1'b1; readnum=3'b011;
#100;
writenum=3'b110; write=1'b1; data_in=16'b0000000000001111; clk=1'b1; readnum=3'b110;
#100
writenum=3'b100; write=1'b1; data_in=16'b0000000000000000; clk=1'b1; readnum=3'b100;
#100;
end
endmodule | module regfile_tb(); |
reg [2:0] writenum, readnum;
reg write, clk;
reg [15:0] data_in;
wire [15:0] data_out;
register_file dut(writenum, write, data_in, clk, readnum, data_out);
initial begin
writenum=3'b010; write=1'b1; data_in=16'b1111000000000000; clk=1'b1; readnum=3'b010;
#100
writenum=3'b010; write=1'b1; data_in=16'b0000111100000000; clk=1'b1; readnum=3'b010;
#100
writenum=3'b100; write=1'b1; data_in=16'b0000000011110000; clk=1'b1; readnum=3'b100;
#100
writenum=3'b001; write=1'b1; data_in=16'b0000000000001111; clk=1'b1; readnum=3'b001;
#100
writenum=3'b110; write=1'b1; data_in=16'b0000000011111111; clk=1'b1; readnum=3'b111;
#100
writenum=3'b000; write=1'b1; data_in=16'b0000111111111111; clk=1'b1; readnum=3'b000;
#100
writenum=3'b110; write=1'b1; data_in=16'b1111111111111111; clk=1'b1; readnum=3'b000;
#100
writenum=3'b001; write=1'b1; data_in=16'b0000111111111111; clk=1'b1; readnum=3'b001;
#100
writenum=3'b011; write=1'b1; data_in=16'b0000000011111111; clk=1'b1; readnum=3'b011;
#100;
writenum=3'b110; write=1'b1; data_in=16'b0000000000001111; clk=1'b1; readnum=3'b110;
#100
writenum=3'b100; write=1'b1; data_in=16'b0000000000000000; clk=1'b1; readnum=3'b100;
#100;
end
endmodule | 0 |
139,023 | data/full_repos/permissive/86668501/Lab6-L1D/shifter.v | 86,668,501 | shifter.v | v | 45 | 71 | [] | [] | [] | [(1, 16), (19, 44)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/shifter.v:28: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/shifter.v:30: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/shifter.v:32: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/shifter.v:34: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/shifter.v:36: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/shifter.v:38: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/shifter.v:40: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/shifter.v:42: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: Exiting due to 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,255 | module | module shifter (loadb, shift, newloadb);
parameter n=16;
input [n-1:0] loadb;
input [1:0] shift;
output [n-1:0] newloadb;
reg [n-1:0] newloadb;
always @(*) begin
case(shift)
2'b00 : {newloadb}={loadb};
2'b01 : {newloadb[n-1:1],newloadb[0]}={loadb[n-2:0],1'b0};
2'b10 : {newloadb[n-2:0],newloadb[n-1]}={loadb[n-1:1],1'b0};
2'b11 : {newloadb[n-2:0],newloadb[n-1]}={loadb[n-1:1],loadb[n-1]};
endcase
end
endmodule | module shifter (loadb, shift, newloadb); |
parameter n=16;
input [n-1:0] loadb;
input [1:0] shift;
output [n-1:0] newloadb;
reg [n-1:0] newloadb;
always @(*) begin
case(shift)
2'b00 : {newloadb}={loadb};
2'b01 : {newloadb[n-1:1],newloadb[0]}={loadb[n-2:0],1'b0};
2'b10 : {newloadb[n-2:0],newloadb[n-1]}={loadb[n-1:1],1'b0};
2'b11 : {newloadb[n-2:0],newloadb[n-1]}={loadb[n-1:1],loadb[n-1]};
endcase
end
endmodule | 0 |
139,024 | data/full_repos/permissive/86668501/Lab6-L1D/shifter.v | 86,668,501 | shifter.v | v | 45 | 71 | [] | [] | [] | [(1, 16), (19, 44)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/shifter.v:28: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/shifter.v:30: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/shifter.v:32: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/shifter.v:34: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/shifter.v:36: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/shifter.v:38: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/shifter.v:40: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab6-L1D/shifter.v:42: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: Exiting due to 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,255 | module | module shifter_tb();
reg [15:0] loadb;
reg [1:0] shift;
wire [15:0] newloadb;
shifter #(16) dut(loadb,shift,newloadb);
initial begin
loadb=16'b0000100001000111; shift=2'b00;
#100
loadb=16'b1110001000100011; shift=2'b01;
#100
loadb=16'b1110000111011101; shift=2'b10;
#100
loadb=16'b1110100001000100; shift=2'b11;
#100
loadb=16'b0110100001000100; shift=2'b11;
#100;
loadb=16'b1111111111111111; shift=2'b10;
#100;
loadb=16'b1111111111111111; shift=2'b01;
#100;
loadb=16'b1110100001000101; shift=2'b11;
#100;
end
endmodule | module shifter_tb(); |
reg [15:0] loadb;
reg [1:0] shift;
wire [15:0] newloadb;
shifter #(16) dut(loadb,shift,newloadb);
initial begin
loadb=16'b0000100001000111; shift=2'b00;
#100
loadb=16'b1110001000100011; shift=2'b01;
#100
loadb=16'b1110000111011101; shift=2'b10;
#100
loadb=16'b1110100001000100; shift=2'b11;
#100
loadb=16'b0110100001000100; shift=2'b11;
#100;
loadb=16'b1111111111111111; shift=2'b10;
#100;
loadb=16'b1111111111111111; shift=2'b01;
#100;
loadb=16'b1110100001000101; shift=2'b11;
#100;
end
endmodule | 0 |
139,025 | data/full_repos/permissive/86668501/Lab7-L1D/ALU.v | 86,668,501 | ALU.v | v | 63 | 54 | [] | [] | [] | [(1, 21), (24, 62)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/ALU.v:35: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/ALU.v:40: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/ALU.v:45: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/ALU.v:50: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/ALU.v:55: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/ALU.v:60: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-PINMISSING: data/full_repos/permissive/86668501/Lab7-L1D/ALU.v:29: Cell has missing pin: \'status\'\n ALU dut(ain,bin,ALUop,loadc);\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/ALU.v:19: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ALUout\' generates 16 bits.\n : ... In instance ALU_tb.dut\n assign status[1] = ALUout ? 0 : 1; \n ^\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/ALU.v:20: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s XOR generates 16 bits.\n : ... In instance ALU_tb.dut\n assign status[2] = Ain ^ Bin; \n ^\n%Error: Exiting due to 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,256 | module | module ALU (Ain, Bin, ALUop, ALUout, status);
parameter n=16;
input [n-1:0] Ain,Bin;
input [1:0] ALUop;
output [n-1:0] ALUout;
output [2:0] status;
reg [n-1:0] ALUout;
always @(*) begin
case(ALUop)
2'b00 : {ALUout}={Ain+Bin};
2'b01 : {ALUout}={Ain-Bin};
2'b10 : {ALUout}={Ain & Bin};
2'b11 : {ALUout}={~Bin};
endcase
end
assign status[0] = ALUout[15];
assign status[1] = ALUout ? 0 : 1;
assign status[2] = Ain ^ Bin;
endmodule | module ALU (Ain, Bin, ALUop, ALUout, status); |
parameter n=16;
input [n-1:0] Ain,Bin;
input [1:0] ALUop;
output [n-1:0] ALUout;
output [2:0] status;
reg [n-1:0] ALUout;
always @(*) begin
case(ALUop)
2'b00 : {ALUout}={Ain+Bin};
2'b01 : {ALUout}={Ain-Bin};
2'b10 : {ALUout}={Ain & Bin};
2'b11 : {ALUout}={~Bin};
endcase
end
assign status[0] = ALUout[15];
assign status[1] = ALUout ? 0 : 1;
assign status[2] = Ain ^ Bin;
endmodule | 0 |
139,026 | data/full_repos/permissive/86668501/Lab7-L1D/ALU.v | 86,668,501 | ALU.v | v | 63 | 54 | [] | [] | [] | [(1, 21), (24, 62)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/ALU.v:35: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/ALU.v:40: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/ALU.v:45: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/ALU.v:50: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/ALU.v:55: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/ALU.v:60: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-PINMISSING: data/full_repos/permissive/86668501/Lab7-L1D/ALU.v:29: Cell has missing pin: \'status\'\n ALU dut(ain,bin,ALUop,loadc);\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/ALU.v:19: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ALUout\' generates 16 bits.\n : ... In instance ALU_tb.dut\n assign status[1] = ALUout ? 0 : 1; \n ^\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/ALU.v:20: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s XOR generates 16 bits.\n : ... In instance ALU_tb.dut\n assign status[2] = Ain ^ Bin; \n ^\n%Error: Exiting due to 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,256 | module | module ALU_tb();
reg [15:0] ain,bin;
reg [1:0] ALUop;
wire [15:0] loadc;
ALU dut(ain,bin,ALUop,loadc);
initial begin
ain=16'b1000100010001001;
bin=16'b0010001000100001;
ALUop=2'b00;
#100
ain=16'b0000100001001110;
bin=16'b0000100001000111;
ALUop=2'b01;
#100
ain=16'b0111010010110011;
bin=16'b0111010100101100;
ALUop=2'b10;
#100
ain=16'b0100001010001010;
bin=16'b0100010001101100;
ALUop=2'b11;
#100
ain=16'b0100001010001010;
bin=16'b0000000000000000;
ALUop=2'b10;
#100
ain=16'b0010010010010010;
bin=16'b0010010010010010;
ALUop=2'b01;
#100;
end
endmodule | module ALU_tb(); |
reg [15:0] ain,bin;
reg [1:0] ALUop;
wire [15:0] loadc;
ALU dut(ain,bin,ALUop,loadc);
initial begin
ain=16'b1000100010001001;
bin=16'b0010001000100001;
ALUop=2'b00;
#100
ain=16'b0000100001001110;
bin=16'b0000100001000111;
ALUop=2'b01;
#100
ain=16'b0111010010110011;
bin=16'b0111010100101100;
ALUop=2'b10;
#100
ain=16'b0100001010001010;
bin=16'b0100010001101100;
ALUop=2'b11;
#100
ain=16'b0100001010001010;
bin=16'b0000000000000000;
ALUop=2'b10;
#100
ain=16'b0010010010010010;
bin=16'b0010010010010010;
ALUop=2'b01;
#100;
end
endmodule | 0 |
139,027 | data/full_repos/permissive/86668501/Lab7-L1D/controller.v | 86,668,501 | controller.v | v | 303 | 145 | [] | [] | [] | [(93, 189), (199, 302)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:210: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:213: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:215: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:218: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:220: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:223: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:225: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:228: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:230: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:233: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:235: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:238: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:240: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:243: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:245: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:248: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:250: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:253: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:255: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:258: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:260: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:263: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:265: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:268: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:270: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:273: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:275: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:278: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:280: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:283: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:285: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:288: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:290: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:293: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:295: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:298: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:300: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-PINMISSING: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:206: Cell has missing pin: \'vsel\'\n controller dut(clk, reset, opcode, op, loadpc, msel, mwrite, loadir, nsel, vsel, write, looada, looadb, looadc, looads, asel, bsel);\n ^~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:188: Cannot find file containing module: \'vDFFE\'\n vDFFE #(5) stateDFF(clk, 1\'b1, next_state_reset, state);\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/vDFFE\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/vDFFE.v\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/vDFFE.sv\n vDFFE\n vDFFE.v\n vDFFE.sv\n obj_dir/vDFFE\n obj_dir/vDFFE.v\n obj_dir/vDFFE.sv\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:206: Output port connection \'mwrite\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'nsel\' generates 3 bits.\n : ... In instance controller_tb\n controller dut(clk, reset, opcode, op, loadpc, msel, mwrite, loadir, nsel, vsel, write, looada, looadb, looadc, looads, asel, bsel);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:206: Output port connection \'loada\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'vsel\' generates 2 bits.\n : ... In instance controller_tb\n controller dut(clk, reset, opcode, op, loadpc, msel, mwrite, loadir, nsel, vsel, write, looada, looadb, looadc, looads, asel, bsel);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:206: Output port connection \'nsel\' expects 2 bits on the pin connection, but pin connection\'s VARREF \'bsel\' generates 1 bits.\n : ... In instance controller_tb\n controller dut(clk, reset, opcode, op, loadpc, msel, mwrite, loadir, nsel, vsel, write, looada, looadb, looadc, looads, asel, bsel);\n ^~~~\n%Error: Exiting due to 1 error(s), 41 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,257 | module | module controller(clk, reset, opcode, op, loadir, incp, execb, msel, mwrite, loada, loadb,
asel, bsel, loadc, loads, write, nsel, vsel);
input clk, reset;
input [2:0] opcode;
input [1:0] op;
output loadir, incp, execb, msel, mwrite, loada, loadb, asel, bsel, loadc, loads, write;
reg loadir, incp, execb, msel, mwrite, loada, loadb, asel, bsel, loadc, loads, write;
output [1:0] nsel, vsel;
reg [1:0] nsel, vsel;
wire [4:0] state;
reg [4:0] next_state;
wire [4:0] next_state_reset;
always @(*) begin
casex({state, opcode, op})
{`SET_PC1, 5'bxxxxx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`SET_PC2, 16'b0000000000000000};
{`SET_PC2, 5'bxxxxx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`L_IR, 16'b0000000000000000};
{`L_IR, 5'bxxxxx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`UPDATE_PC1, 16'b1000000000000000};
{`UPDATE_PC1, 5'bxxxxx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`UPDATE_PC2, 16'b0100000000000000};
{`UPDATE_PC2, 5'bxxxxx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`DEC_READ_RN, 16'b0000000000000000};
{`DEC_READ_RN, 5'b110x0}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MOV1, 16'b0000000000000000};
{`DEC_READ_RN, 5'b101xx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU1, 16'b0000000000000000};
{`DEC_READ_RN, 5'b01100}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MEM1a, 16'b0000000000000000};
{`DEC_READ_RN, 5'b10000}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MEM1b, 16'b0000000000000000};
{`DEC_READ_RN, 5'b001xx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`BRN1, 16'b0000000000000000};
{`MOV1, 5'bxxx10}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`L_IR, 16'b0000010100000001};
{`MOV1, 5'bxxx00}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MOV2, 16'b0000000000100000};
{`MOV2, 5'bxxx00}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MOV3, 16'b0000000000010100};
{`MOV3, 5'bxxx00}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`L_IR, 16'b0000001000000001};
{`ALU1, 5'bxxx00}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU2, 16'b0000000000100000};
{`ALU2, 5'bxxx00}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU3, 16'b0000010001000000};
{`ALU3, 5'bxxx00}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU4, 16'b0000000000000100};
{`ALU4, 5'bxxx00}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`L_IR, 16'b0000001000000001};
{`ALU1, 5'bxxx01}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU2, 16'b0000000000100000};
{`ALU2, 5'bxxx01}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU3, 16'b0000010001000000};
{`ALU3, 5'bxxx01}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`L_IR, 16'b0000000000000010};
{`ALU1, 5'bxxx10}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU2, 16'b0000000000100000};
{`ALU2, 5'bxxx10}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU3, 16'b0000010001000000};
{`ALU3, 5'bxxx10}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU4, 16'b0000000000000100};
{`ALU4, 5'bxxx10}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`L_IR, 16'b0000001000000001};
{`ALU1, 5'bxxx11}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU2, 16'b0000000000100000};
{`ALU2, 5'bxxx11}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU3, 16'b0000000000010100};
{`ALU3, 5'bxxx11}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`L_IR, 16'b0000001000000001};
{`MEM1a, 5'b011xx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MEM2a, 16'b0000010001000000};
{`MEM2a, 5'b011xx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MEM3a, 16'b0000000000001100};
{`MEM3a, 5'b011xx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MEM4a, 16'b0001000000000000};
{`MEM4a, 5'b011xx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`L_IR, 16'b0001001110000001};
{`MEM1b, 5'b100xx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MEM2b, 16'b0000010001000000};
{`MEM2b, 5'b100xx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MEM3b, 16'b0000000000001100};
{`MEM3b, 5'b100xx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MEM4b, 16'b0000001000100000};
{`MEM4b, 5'b100xx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`L_IR, 16'b0001100000000000};
{`BRN1,5'b001xx} : {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`BRN2, 16'b0010000000000000};
{`BRN2,5'b001xx} : {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`L_IR, 16'b0010000000000000};
default: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} = {21{1'bx}};
endcase
end
assign next_state_reset = reset ? `SET_PC1 : next_state;
vDFFE #(5) stateDFF(clk, 1'b1, next_state_reset, state);
endmodule | module controller(clk, reset, opcode, op, loadir, incp, execb, msel, mwrite, loada, loadb,
asel, bsel, loadc, loads, write, nsel, vsel); |
input clk, reset;
input [2:0] opcode;
input [1:0] op;
output loadir, incp, execb, msel, mwrite, loada, loadb, asel, bsel, loadc, loads, write;
reg loadir, incp, execb, msel, mwrite, loada, loadb, asel, bsel, loadc, loads, write;
output [1:0] nsel, vsel;
reg [1:0] nsel, vsel;
wire [4:0] state;
reg [4:0] next_state;
wire [4:0] next_state_reset;
always @(*) begin
casex({state, opcode, op})
{`SET_PC1, 5'bxxxxx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`SET_PC2, 16'b0000000000000000};
{`SET_PC2, 5'bxxxxx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`L_IR, 16'b0000000000000000};
{`L_IR, 5'bxxxxx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`UPDATE_PC1, 16'b1000000000000000};
{`UPDATE_PC1, 5'bxxxxx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`UPDATE_PC2, 16'b0100000000000000};
{`UPDATE_PC2, 5'bxxxxx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`DEC_READ_RN, 16'b0000000000000000};
{`DEC_READ_RN, 5'b110x0}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MOV1, 16'b0000000000000000};
{`DEC_READ_RN, 5'b101xx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU1, 16'b0000000000000000};
{`DEC_READ_RN, 5'b01100}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MEM1a, 16'b0000000000000000};
{`DEC_READ_RN, 5'b10000}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MEM1b, 16'b0000000000000000};
{`DEC_READ_RN, 5'b001xx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`BRN1, 16'b0000000000000000};
{`MOV1, 5'bxxx10}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`L_IR, 16'b0000010100000001};
{`MOV1, 5'bxxx00}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MOV2, 16'b0000000000100000};
{`MOV2, 5'bxxx00}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MOV3, 16'b0000000000010100};
{`MOV3, 5'bxxx00}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`L_IR, 16'b0000001000000001};
{`ALU1, 5'bxxx00}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU2, 16'b0000000000100000};
{`ALU2, 5'bxxx00}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU3, 16'b0000010001000000};
{`ALU3, 5'bxxx00}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU4, 16'b0000000000000100};
{`ALU4, 5'bxxx00}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`L_IR, 16'b0000001000000001};
{`ALU1, 5'bxxx01}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU2, 16'b0000000000100000};
{`ALU2, 5'bxxx01}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU3, 16'b0000010001000000};
{`ALU3, 5'bxxx01}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`L_IR, 16'b0000000000000010};
{`ALU1, 5'bxxx10}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU2, 16'b0000000000100000};
{`ALU2, 5'bxxx10}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU3, 16'b0000010001000000};
{`ALU3, 5'bxxx10}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU4, 16'b0000000000000100};
{`ALU4, 5'bxxx10}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`L_IR, 16'b0000001000000001};
{`ALU1, 5'bxxx11}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU2, 16'b0000000000100000};
{`ALU2, 5'bxxx11}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`ALU3, 16'b0000000000010100};
{`ALU3, 5'bxxx11}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`L_IR, 16'b0000001000000001};
{`MEM1a, 5'b011xx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MEM2a, 16'b0000010001000000};
{`MEM2a, 5'b011xx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MEM3a, 16'b0000000000001100};
{`MEM3a, 5'b011xx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MEM4a, 16'b0001000000000000};
{`MEM4a, 5'b011xx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`L_IR, 16'b0001001110000001};
{`MEM1b, 5'b100xx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MEM2b, 16'b0000010001000000};
{`MEM2b, 5'b100xx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MEM3b, 16'b0000000000001100};
{`MEM3b, 5'b100xx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`MEM4b, 16'b0000001000100000};
{`MEM4b, 5'b100xx}: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`L_IR, 16'b0001100000000000};
{`BRN1,5'b001xx} : {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`BRN2, 16'b0010000000000000};
{`BRN2,5'b001xx} : {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} =
{`L_IR, 16'b0010000000000000};
default: {next_state, loadir, incp, execb, msel, mwrite, nsel, vsel, loada, loadb, asel, bsel, loadc, loads, write} = {21{1'bx}};
endcase
end
assign next_state_reset = reset ? `SET_PC1 : next_state;
vDFFE #(5) stateDFF(clk, 1'b1, next_state_reset, state);
endmodule | 0 |
139,028 | data/full_repos/permissive/86668501/Lab7-L1D/controller.v | 86,668,501 | controller.v | v | 303 | 145 | [] | [] | [] | [(93, 189), (199, 302)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:210: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:213: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:215: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:218: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:220: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:223: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:225: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:228: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:230: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:233: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:235: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:238: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:240: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:243: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:245: Unsupported: Ignoring delay on this delayed statement.\n #100 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:248: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:250: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:253: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:255: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:258: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:260: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:263: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:265: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:268: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:270: Unsupported: Ignoring delay on this delayed statement.\n #100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:273: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:275: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:278: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:280: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:283: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:285: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:288: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:290: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:293: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:295: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:298: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:300: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-PINMISSING: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:206: Cell has missing pin: \'vsel\'\n controller dut(clk, reset, opcode, op, loadpc, msel, mwrite, loadir, nsel, vsel, write, looada, looadb, looadc, looads, asel, bsel);\n ^~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:188: Cannot find file containing module: \'vDFFE\'\n vDFFE #(5) stateDFF(clk, 1\'b1, next_state_reset, state);\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/vDFFE\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/vDFFE.v\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/vDFFE.sv\n vDFFE\n vDFFE.v\n vDFFE.sv\n obj_dir/vDFFE\n obj_dir/vDFFE.v\n obj_dir/vDFFE.sv\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:206: Output port connection \'mwrite\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'nsel\' generates 3 bits.\n : ... In instance controller_tb\n controller dut(clk, reset, opcode, op, loadpc, msel, mwrite, loadir, nsel, vsel, write, looada, looadb, looadc, looads, asel, bsel);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:206: Output port connection \'loada\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'vsel\' generates 2 bits.\n : ... In instance controller_tb\n controller dut(clk, reset, opcode, op, loadpc, msel, mwrite, loadir, nsel, vsel, write, looada, looadb, looadc, looads, asel, bsel);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/controller.v:206: Output port connection \'nsel\' expects 2 bits on the pin connection, but pin connection\'s VARREF \'bsel\' generates 1 bits.\n : ... In instance controller_tb\n controller dut(clk, reset, opcode, op, loadpc, msel, mwrite, loadir, nsel, vsel, write, looada, looadb, looadc, looads, asel, bsel);\n ^~~~\n%Error: Exiting due to 1 error(s), 41 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,257 | module | module controller_tb();
reg reset, clk;
reg [2:0] opcode;
reg [1:0] op;
wire loadir, loadpc, msel, mwrite, looada, looadb, looadc, looads, asel, bsel, write;
wire [2:0] nsel;
wire [1:0] vsel;
controller dut(clk, reset, opcode, op, loadpc, msel, mwrite, loadir, nsel, vsel, write, looada, looadb, looadc, looads, asel, bsel);
initial begin
clk=1'b0;reset=1'b1;opcode=3'b110; op=2'b10;
#100
clk=1'b1;reset=1'b0;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;opcode=3'b101; op=2'b00;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;opcode=3'b101;op=2'b01;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
end
endmodule | module controller_tb(); |
reg reset, clk;
reg [2:0] opcode;
reg [1:0] op;
wire loadir, loadpc, msel, mwrite, looada, looadb, looadc, looads, asel, bsel, write;
wire [2:0] nsel;
wire [1:0] vsel;
controller dut(clk, reset, opcode, op, loadpc, msel, mwrite, loadir, nsel, vsel, write, looada, looadb, looadc, looads, asel, bsel);
initial begin
clk=1'b0;reset=1'b1;opcode=3'b110; op=2'b10;
#100
clk=1'b1;reset=1'b0;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;opcode=3'b101; op=2'b00;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;opcode=3'b101;op=2'b01;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
end
endmodule | 0 |
139,029 | data/full_repos/permissive/86668501/Lab7-L1D/cpu.v | 86,668,501 | cpu.v | v | 64 | 125 | [] | [] | [] | null | line:52: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:47: Unsupported: Ignoring delay on this delayed statement.\n clk = 1\'b0; #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:48: Unsupported: Ignoring delay on this delayed statement.\n reset = 1\'b1; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:49: Unsupported: Ignoring delay on this delayed statement.\n clk = 1\'b1; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:51: Unsupported: Ignoring delay on this delayed statement.\n reset = 1\'b0; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:53: Unsupported: Ignoring delay on this delayed statement.\n clk = 1\'b1; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:54: Unsupported: Ignoring delay on this delayed statement.\n clk = 1\'b0; #5;\n ^\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:44: Pin not found: \'__pinNumber4\'\n cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:44: Pin not found: \'__pinNumber5\'\n cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:44: Pin not found: \'__pinNumber6\'\n cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:44: Pin not found: \'__pinNumber7\'\n cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:44: Pin not found: \'__pinNumber8\'\n cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);\n ^~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:44: Pin not found: \'__pinNumber9\'\n cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:44: Pin not found: \'__pinNumber10\'\n cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);\n ^~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:44: Pin not found: \'__pinNumber11\'\n cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);\n ^~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:44: Pin not found: \'__pinNumber12\'\n cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:44: Pin not found: \'__pinNumber13\'\n cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);\n ^~~~~~\n%Error: Exiting due to 10 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,258 | module | module cpu(clk, reset, Cout);
input clk,reset;
output [15:0] Cout;
wire mwrite, msel, execb, incp, loadir;
wire asel, bsel, loada, loadb, loadc, loads, write;
wire [1:0] op, ALUop, shift, vsel, nsel;
wire [2:0] opcode, readnum, writenum, status, cond;
wire [15:0] Bout, sximm5, sximm8, mdata, IR;
wire [7:0] PC;
datapath datapathx (clk, writenum, write, readnum, vsel, sximm5, sximm8, mdata, asel, bsel, shift, ALUop, loada,
loadb, loadc, loads, status, Bout, Cout, PC);
Program_counter PCx (clk, reset, sximm8, incp, execb, status, cond, msel, Bout, Cout, mwrite, loadir, PC, mdata, IR);
controller controllerx (clk, reset, opcode, op, loadir, incp, execb, msel, mwrite, loada, loadb, asel, bsel, loadc, loads,
write, nsel, vsel);
instruction_dec instruction_decx (IR, nsel, opcode, op, cond, ALUop, readnum, writenum, shift, sximm8, sximm5);
endmodule | module cpu(clk, reset, Cout); |
input clk,reset;
output [15:0] Cout;
wire mwrite, msel, execb, incp, loadir;
wire asel, bsel, loada, loadb, loadc, loads, write;
wire [1:0] op, ALUop, shift, vsel, nsel;
wire [2:0] opcode, readnum, writenum, status, cond;
wire [15:0] Bout, sximm5, sximm8, mdata, IR;
wire [7:0] PC;
datapath datapathx (clk, writenum, write, readnum, vsel, sximm5, sximm8, mdata, asel, bsel, shift, ALUop, loada,
loadb, loadc, loads, status, Bout, Cout, PC);
Program_counter PCx (clk, reset, sximm8, incp, execb, status, cond, msel, Bout, Cout, mwrite, loadir, PC, mdata, IR);
controller controllerx (clk, reset, opcode, op, loadir, incp, execb, msel, mwrite, loada, loadb, asel, bsel, loadc, loads,
write, nsel, vsel);
instruction_dec instruction_decx (IR, nsel, opcode, op, cond, ALUop, readnum, writenum, shift, sximm8, sximm5);
endmodule | 0 |
139,030 | data/full_repos/permissive/86668501/Lab7-L1D/cpu.v | 86,668,501 | cpu.v | v | 64 | 125 | [] | [] | [] | null | line:52: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:47: Unsupported: Ignoring delay on this delayed statement.\n clk = 1\'b0; #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:48: Unsupported: Ignoring delay on this delayed statement.\n reset = 1\'b1; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:49: Unsupported: Ignoring delay on this delayed statement.\n clk = 1\'b1; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:51: Unsupported: Ignoring delay on this delayed statement.\n reset = 1\'b0; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:53: Unsupported: Ignoring delay on this delayed statement.\n clk = 1\'b1; #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:54: Unsupported: Ignoring delay on this delayed statement.\n clk = 1\'b0; #5;\n ^\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:44: Pin not found: \'__pinNumber4\'\n cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:44: Pin not found: \'__pinNumber5\'\n cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:44: Pin not found: \'__pinNumber6\'\n cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:44: Pin not found: \'__pinNumber7\'\n cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:44: Pin not found: \'__pinNumber8\'\n cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);\n ^~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:44: Pin not found: \'__pinNumber9\'\n cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:44: Pin not found: \'__pinNumber10\'\n cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);\n ^~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:44: Pin not found: \'__pinNumber11\'\n cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);\n ^~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:44: Pin not found: \'__pinNumber12\'\n cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/cpu.v:44: Pin not found: \'__pinNumber13\'\n cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);\n ^~~~~~\n%Error: Exiting due to 10 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,258 | module | module cpu_tb();
reg clk, reset;
wire loada,loadb,loadc,loads;
wire [7:0] PC;
wire [15:0] mdata, IR, Cout;
wire [1:0] vsel;
wire execb;
wire [2:0] status;
cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);
initial begin
clk = 1'b0; #5;
reset = 1'b1; #5;
clk = 1'b1; #5;
clk = 1'b0;
reset = 1'b0; #5;
repeat (80) begin
clk = 1'b1; #5;
clk = 1'b0; #5;
end
end
endmodule | module cpu_tb(); |
reg clk, reset;
wire loada,loadb,loadc,loads;
wire [7:0] PC;
wire [15:0] mdata, IR, Cout;
wire [1:0] vsel;
wire execb;
wire [2:0] status;
cpu DUT(clk, reset, Cout, loada,loadb,loadc,loads,PC,mdata,IR,vsel,execb,status);
initial begin
clk = 1'b0; #5;
reset = 1'b1; #5;
clk = 1'b1; #5;
clk = 1'b0;
reset = 1'b0; #5;
repeat (80) begin
clk = 1'b1; #5;
clk = 1'b0; #5;
end
end
endmodule | 0 |
139,031 | data/full_repos/permissive/86668501/Lab7-L1D/datapath.v | 86,668,501 | datapath.v | v | 147 | 184 | [] | [] | [] | [(1, 32), (34, 46), (48, 60), (64, 100), (102, 145)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:116: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:118: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:120: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:122: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:125: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:127: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:129: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:131: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:133: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:135: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:137: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:139: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:141: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:102: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'instruction_dec\'\nmodule instruction_dec(IR, nsel, opcode, op, cond, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~~~~~~~~~~\n : ... Top module \'datapath_tb\'\nmodule datapath_tb();\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:21: Cannot find file containing module: \'register_file\'\n register_file regfilex (writenum, write, data_in, clk, readnum, data_out);\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/register_file\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/register_file.v\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/register_file.sv\n register_file\n register_file.v\n register_file.sv\n obj_dir/register_file\n obj_dir/register_file.v\n obj_dir/register_file.sv\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:22: Cannot find file containing module: \'vDFFE\'\n vDFFE #(16) loadax (clk, loada, data_out, Aout);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:23: Cannot find file containing module: \'vDFFE\'\n vDFFE #(16) loadbx (clk, loadb, data_out, Bout);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:26: Cannot find file containing module: \'shifter\'\n shifter shiftx (Bout, shift, shiftedB);\n ^~~~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:29: Cannot find file containing module: \'ALU\'\n ALU ALUx (Ain, Bin, ALUop, ALUout, status_in);\n ^~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:30: Cannot find file containing module: \'vDFFE\'\n vDFFE #(16) loadcx (clk, loadc, ALUout, Cout);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:31: Cannot find file containing module: \'vDFFE\'\n vDFFE #(3) loadsx (clk, loads, status_in, status);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:97: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n : ... In instance instruction_dec\n default: {readnum,writenum}={2\'bxx,2\'bxx};\n ^\n%Error: Exiting due to 7 error(s), 15 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,259 | module | module datapath(clk,writenum,write,readnum,vsel,sximm5,sximm8,mdata,asel,bsel,shift,ALUop,loada,loadb,loadc,loads,status,Bout,Cout,PC, data_out, ALUout, Aout);
input [15:0] sximm5, sximm8, mdata;
input clk, write, asel, bsel, loada, loadb, loadc, loads;
input [2:0] writenum, readnum;
input [1:0] vsel, ALUop, shift;
input [7:0] PC;
output [15:0] Bout, Cout, data_out, ALUout ,Aout;
output [2:0] status;
wire [15:0] data_out, Aout, Bout, shiftedB,Ain,Bin, ALUout;
wire [2:0] status_in, writenum, readnum;
reg [15:0] data_in;
always @(*)begin
case(vsel)
2'b11 : data_in = mdata;
2'b10 : data_in = sximm8;
2'b01 : data_in = {8'b00000000,PC};
2'b00 : data_in = Cout;
endcase
end
register_file regfilex (writenum, write, data_in, clk, readnum, data_out);
vDFFE #(16) loadax (clk, loada, data_out, Aout);
vDFFE #(16) loadbx (clk, loadb, data_out, Bout);
amux amuxx(asel, Aout, Ain);
shifter shiftx (Bout, shift, shiftedB);
bmux bmuxx(bsel,shiftedB, sximm5, Bin);
ALU ALUx (Ain, Bin, ALUop, ALUout, status_in);
vDFFE #(16) loadcx (clk, loadc, ALUout, Cout);
vDFFE #(3) loadsx (clk, loads, status_in, status);
endmodule | module datapath(clk,writenum,write,readnum,vsel,sximm5,sximm8,mdata,asel,bsel,shift,ALUop,loada,loadb,loadc,loads,status,Bout,Cout,PC, data_out, ALUout, Aout); |
input [15:0] sximm5, sximm8, mdata;
input clk, write, asel, bsel, loada, loadb, loadc, loads;
input [2:0] writenum, readnum;
input [1:0] vsel, ALUop, shift;
input [7:0] PC;
output [15:0] Bout, Cout, data_out, ALUout ,Aout;
output [2:0] status;
wire [15:0] data_out, Aout, Bout, shiftedB,Ain,Bin, ALUout;
wire [2:0] status_in, writenum, readnum;
reg [15:0] data_in;
always @(*)begin
case(vsel)
2'b11 : data_in = mdata;
2'b10 : data_in = sximm8;
2'b01 : data_in = {8'b00000000,PC};
2'b00 : data_in = Cout;
endcase
end
register_file regfilex (writenum, write, data_in, clk, readnum, data_out);
vDFFE #(16) loadax (clk, loada, data_out, Aout);
vDFFE #(16) loadbx (clk, loadb, data_out, Bout);
amux amuxx(asel, Aout, Ain);
shifter shiftx (Bout, shift, shiftedB);
bmux bmuxx(bsel,shiftedB, sximm5, Bin);
ALU ALUx (Ain, Bin, ALUop, ALUout, status_in);
vDFFE #(16) loadcx (clk, loadc, ALUout, Cout);
vDFFE #(3) loadsx (clk, loads, status_in, status);
endmodule | 0 |
139,032 | data/full_repos/permissive/86668501/Lab7-L1D/datapath.v | 86,668,501 | datapath.v | v | 147 | 184 | [] | [] | [] | [(1, 32), (34, 46), (48, 60), (64, 100), (102, 145)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:116: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:118: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:120: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:122: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:125: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:127: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:129: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:131: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:133: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:135: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:137: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:139: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:141: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:102: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'instruction_dec\'\nmodule instruction_dec(IR, nsel, opcode, op, cond, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~~~~~~~~~~\n : ... Top module \'datapath_tb\'\nmodule datapath_tb();\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:21: Cannot find file containing module: \'register_file\'\n register_file regfilex (writenum, write, data_in, clk, readnum, data_out);\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/register_file\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/register_file.v\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/register_file.sv\n register_file\n register_file.v\n register_file.sv\n obj_dir/register_file\n obj_dir/register_file.v\n obj_dir/register_file.sv\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:22: Cannot find file containing module: \'vDFFE\'\n vDFFE #(16) loadax (clk, loada, data_out, Aout);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:23: Cannot find file containing module: \'vDFFE\'\n vDFFE #(16) loadbx (clk, loadb, data_out, Bout);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:26: Cannot find file containing module: \'shifter\'\n shifter shiftx (Bout, shift, shiftedB);\n ^~~~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:29: Cannot find file containing module: \'ALU\'\n ALU ALUx (Ain, Bin, ALUop, ALUout, status_in);\n ^~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:30: Cannot find file containing module: \'vDFFE\'\n vDFFE #(16) loadcx (clk, loadc, ALUout, Cout);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:31: Cannot find file containing module: \'vDFFE\'\n vDFFE #(3) loadsx (clk, loads, status_in, status);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:97: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n : ... In instance instruction_dec\n default: {readnum,writenum}={2\'bxx,2\'bxx};\n ^\n%Error: Exiting due to 7 error(s), 15 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,259 | module | module amux(asel, Aout, Ain);
input asel;
input [15:0] Aout;
output [15:0] Ain;
reg [15:0]Ain;
always@(*)begin
case(asel)
1'b0 : Ain=Aout;
1'b1 : Ain=16'b0000000000000000;
endcase
end
endmodule | module amux(asel, Aout, Ain); |
input asel;
input [15:0] Aout;
output [15:0] Ain;
reg [15:0]Ain;
always@(*)begin
case(asel)
1'b0 : Ain=Aout;
1'b1 : Ain=16'b0000000000000000;
endcase
end
endmodule | 0 |
139,033 | data/full_repos/permissive/86668501/Lab7-L1D/datapath.v | 86,668,501 | datapath.v | v | 147 | 184 | [] | [] | [] | [(1, 32), (34, 46), (48, 60), (64, 100), (102, 145)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:116: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:118: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:120: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:122: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:125: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:127: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:129: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:131: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:133: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:135: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:137: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:139: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:141: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:102: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'instruction_dec\'\nmodule instruction_dec(IR, nsel, opcode, op, cond, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~~~~~~~~~~\n : ... Top module \'datapath_tb\'\nmodule datapath_tb();\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:21: Cannot find file containing module: \'register_file\'\n register_file regfilex (writenum, write, data_in, clk, readnum, data_out);\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/register_file\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/register_file.v\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/register_file.sv\n register_file\n register_file.v\n register_file.sv\n obj_dir/register_file\n obj_dir/register_file.v\n obj_dir/register_file.sv\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:22: Cannot find file containing module: \'vDFFE\'\n vDFFE #(16) loadax (clk, loada, data_out, Aout);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:23: Cannot find file containing module: \'vDFFE\'\n vDFFE #(16) loadbx (clk, loadb, data_out, Bout);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:26: Cannot find file containing module: \'shifter\'\n shifter shiftx (Bout, shift, shiftedB);\n ^~~~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:29: Cannot find file containing module: \'ALU\'\n ALU ALUx (Ain, Bin, ALUop, ALUout, status_in);\n ^~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:30: Cannot find file containing module: \'vDFFE\'\n vDFFE #(16) loadcx (clk, loadc, ALUout, Cout);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:31: Cannot find file containing module: \'vDFFE\'\n vDFFE #(3) loadsx (clk, loads, status_in, status);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:97: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n : ... In instance instruction_dec\n default: {readnum,writenum}={2\'bxx,2\'bxx};\n ^\n%Error: Exiting due to 7 error(s), 15 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,259 | module | module bmux(bsel, shiftedB, sximm5, Bin);
input [15:0] shiftedB, sximm5;
input bsel;
output [15:0] Bin;
reg [15:0]Bin;
always@(*)begin
case(bsel)
1'b0 : Bin=shiftedB;
1'b1 : Bin=sximm5;
endcase
end
endmodule | module bmux(bsel, shiftedB, sximm5, Bin); |
input [15:0] shiftedB, sximm5;
input bsel;
output [15:0] Bin;
reg [15:0]Bin;
always@(*)begin
case(bsel)
1'b0 : Bin=shiftedB;
1'b1 : Bin=sximm5;
endcase
end
endmodule | 0 |
139,034 | data/full_repos/permissive/86668501/Lab7-L1D/datapath.v | 86,668,501 | datapath.v | v | 147 | 184 | [] | [] | [] | [(1, 32), (34, 46), (48, 60), (64, 100), (102, 145)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:116: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:118: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:120: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:122: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:125: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:127: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:129: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:131: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:133: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:135: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:137: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:139: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:141: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:102: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'instruction_dec\'\nmodule instruction_dec(IR, nsel, opcode, op, cond, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~~~~~~~~~~\n : ... Top module \'datapath_tb\'\nmodule datapath_tb();\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:21: Cannot find file containing module: \'register_file\'\n register_file regfilex (writenum, write, data_in, clk, readnum, data_out);\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/register_file\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/register_file.v\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/register_file.sv\n register_file\n register_file.v\n register_file.sv\n obj_dir/register_file\n obj_dir/register_file.v\n obj_dir/register_file.sv\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:22: Cannot find file containing module: \'vDFFE\'\n vDFFE #(16) loadax (clk, loada, data_out, Aout);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:23: Cannot find file containing module: \'vDFFE\'\n vDFFE #(16) loadbx (clk, loadb, data_out, Bout);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:26: Cannot find file containing module: \'shifter\'\n shifter shiftx (Bout, shift, shiftedB);\n ^~~~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:29: Cannot find file containing module: \'ALU\'\n ALU ALUx (Ain, Bin, ALUop, ALUout, status_in);\n ^~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:30: Cannot find file containing module: \'vDFFE\'\n vDFFE #(16) loadcx (clk, loadc, ALUout, Cout);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:31: Cannot find file containing module: \'vDFFE\'\n vDFFE #(3) loadsx (clk, loads, status_in, status);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:97: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n : ... In instance instruction_dec\n default: {readnum,writenum}={2\'bxx,2\'bxx};\n ^\n%Error: Exiting due to 7 error(s), 15 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,259 | module | module instruction_dec(IR, nsel, opcode, op, cond, ALUop, readnum, writenum, shift, sximm8, sximm5);
input [15:0] IR;
output [2:0] opcode, cond, readnum, writenum;
output [1:0] ALUop, op, shift, nsel;
output [15:0] sximm8, sximm5;
wire [2:0] Rn, Rd, Rm;
reg [15:0] sximm8, sximm5;
reg [2:0] readnum, writenum;
assign opcode=IR[15:13];
assign op=IR[12:11];
assign ALUop=IR[12:11];
assign shift=IR[4:3];
assign cond=IR[10:8];
assign {Rn,Rd,Rm}={IR[10:8],IR[7:5],IR[2:0]};
always @(*)begin
case (IR[7])
1'b0 : sximm8={8'b0,IR[7:0]};
1'b1 : sximm8={8'b1,IR[7:0]};
endcase
end
always @(*)begin
case(IR[4])
1'b0 : sximm5={11'b0,IR[4:0]};
1'b1 : sximm5={11'b1,IR[4:0]};
endcase
end
always @(*)begin
case(nsel)
2'b00 : {readnum,writenum}={IR[2:0],IR[2:0]};
2'b01 : {readnum,writenum}={IR[7:5],IR[7:5]};
2'b10 : {readnum,writenum}={IR[10:8],IR[10:8]};
default: {readnum,writenum}={2'bxx,2'bxx};
endcase
end
endmodule | module instruction_dec(IR, nsel, opcode, op, cond, ALUop, readnum, writenum, shift, sximm8, sximm5); |
input [15:0] IR;
output [2:0] opcode, cond, readnum, writenum;
output [1:0] ALUop, op, shift, nsel;
output [15:0] sximm8, sximm5;
wire [2:0] Rn, Rd, Rm;
reg [15:0] sximm8, sximm5;
reg [2:0] readnum, writenum;
assign opcode=IR[15:13];
assign op=IR[12:11];
assign ALUop=IR[12:11];
assign shift=IR[4:3];
assign cond=IR[10:8];
assign {Rn,Rd,Rm}={IR[10:8],IR[7:5],IR[2:0]};
always @(*)begin
case (IR[7])
1'b0 : sximm8={8'b0,IR[7:0]};
1'b1 : sximm8={8'b1,IR[7:0]};
endcase
end
always @(*)begin
case(IR[4])
1'b0 : sximm5={11'b0,IR[4:0]};
1'b1 : sximm5={11'b1,IR[4:0]};
endcase
end
always @(*)begin
case(nsel)
2'b00 : {readnum,writenum}={IR[2:0],IR[2:0]};
2'b01 : {readnum,writenum}={IR[7:5],IR[7:5]};
2'b10 : {readnum,writenum}={IR[10:8],IR[10:8]};
default: {readnum,writenum}={2'bxx,2'bxx};
endcase
end
endmodule | 0 |
139,035 | data/full_repos/permissive/86668501/Lab7-L1D/datapath.v | 86,668,501 | datapath.v | v | 147 | 184 | [] | [] | [] | [(1, 32), (34, 46), (48, 60), (64, 100), (102, 145)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:116: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:118: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:120: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:122: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:125: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:127: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:129: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:131: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:133: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:135: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:137: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:139: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:141: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:102: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'instruction_dec\'\nmodule instruction_dec(IR, nsel, opcode, op, cond, ALUop, readnum, writenum, shift, sximm8, sximm5);\n ^~~~~~~~~~~~~~~\n : ... Top module \'datapath_tb\'\nmodule datapath_tb();\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:21: Cannot find file containing module: \'register_file\'\n register_file regfilex (writenum, write, data_in, clk, readnum, data_out);\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/register_file\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/register_file.v\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/register_file.sv\n register_file\n register_file.v\n register_file.sv\n obj_dir/register_file\n obj_dir/register_file.v\n obj_dir/register_file.sv\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:22: Cannot find file containing module: \'vDFFE\'\n vDFFE #(16) loadax (clk, loada, data_out, Aout);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:23: Cannot find file containing module: \'vDFFE\'\n vDFFE #(16) loadbx (clk, loadb, data_out, Bout);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:26: Cannot find file containing module: \'shifter\'\n shifter shiftx (Bout, shift, shiftedB);\n ^~~~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:29: Cannot find file containing module: \'ALU\'\n ALU ALUx (Ain, Bin, ALUop, ALUout, status_in);\n ^~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:30: Cannot find file containing module: \'vDFFE\'\n vDFFE #(16) loadcx (clk, loadc, ALUout, Cout);\n ^~~~~\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:31: Cannot find file containing module: \'vDFFE\'\n vDFFE #(3) loadsx (clk, loads, status_in, status);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/datapath.v:97: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n : ... In instance instruction_dec\n default: {readnum,writenum}={2\'bxx,2\'bxx};\n ^\n%Error: Exiting due to 7 error(s), 15 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,259 | module | module datapath_tb();
reg clk, write, loada, loadb, loadc, loads, asel, bsel;
reg [15:0] mdata,sximm5,sximm8;
reg [7:0] PC;
reg [2:0] writenum, readnum;
reg [1:0] shift, ALUop, vsel;
wire [15:0] Bout, Cout, data_out, ALUout,Aout;
wire [2:0] status;
datapath dut (clk,writenum,write,readnum,vsel,sximm5,sximm8,mdata,asel,bsel,shift,ALUop,loada,loadb,loadc,loads,status,Bout,Cout,PC,data_out,ALUout,Aout);
initial begin
clk = 1'b0; write = 1'b1; loada = 1'b1; loadb = 1'b0; loadc = 1'b0; loads = 1'b0; asel = 1'b0; bsel = 1'b0; mdata = 16'b0000000000100000; sximm5 = {16{1'b0}}; sximm8 = {16{1'b0}};
PC = {8{1'b0}}; writenum = 3'b000; readnum = 3'b000; shift = 2'b00; ALUop = 2'b00; vsel = 2'b11;
#100
clk=1'b1;
#100
clk = 1'b0; write = 1'b0; loada = 1'b1; mdata = {16{1'b0}}; vsel=2'b00;
#100
clk=1'b1; loada = 1'b0;
#100
clk = 1'b0; write = 1'b1; loada = 1'b0; sximm8 = 16'b0010111111100000;
writenum = 3'b001; readnum = 3'b001; vsel = 2'b10; loadb = 1'b1;
#100
clk=1'b1;
#100
clk = 1'b0; write = 1'b0; loadb = 1'b1; sximm8 = {16{1'b0}}; vsel = 2'b00; loadc = 1'b1;
#100
clk = 1'b1; loadb = 1'b0;
#100
clk = 1'b0; ALUop = 2'b00; loadb = 1'b0; loadc = 1'b1;
#100
clk = 1'b1;
#100
clk = 1'b0; write = 1'b0; writenum = 3'b010; loadc = 1'b1; ALUop = 2'b00;
#100
clk = 1'b1;
#100
clk = 1'b0; loadc=1'b0;
#100;
$display("All tests work!");
end
endmodule | module datapath_tb(); |
reg clk, write, loada, loadb, loadc, loads, asel, bsel;
reg [15:0] mdata,sximm5,sximm8;
reg [7:0] PC;
reg [2:0] writenum, readnum;
reg [1:0] shift, ALUop, vsel;
wire [15:0] Bout, Cout, data_out, ALUout,Aout;
wire [2:0] status;
datapath dut (clk,writenum,write,readnum,vsel,sximm5,sximm8,mdata,asel,bsel,shift,ALUop,loada,loadb,loadc,loads,status,Bout,Cout,PC,data_out,ALUout,Aout);
initial begin
clk = 1'b0; write = 1'b1; loada = 1'b1; loadb = 1'b0; loadc = 1'b0; loads = 1'b0; asel = 1'b0; bsel = 1'b0; mdata = 16'b0000000000100000; sximm5 = {16{1'b0}}; sximm8 = {16{1'b0}};
PC = {8{1'b0}}; writenum = 3'b000; readnum = 3'b000; shift = 2'b00; ALUop = 2'b00; vsel = 2'b11;
#100
clk=1'b1;
#100
clk = 1'b0; write = 1'b0; loada = 1'b1; mdata = {16{1'b0}}; vsel=2'b00;
#100
clk=1'b1; loada = 1'b0;
#100
clk = 1'b0; write = 1'b1; loada = 1'b0; sximm8 = 16'b0010111111100000;
writenum = 3'b001; readnum = 3'b001; vsel = 2'b10; loadb = 1'b1;
#100
clk=1'b1;
#100
clk = 1'b0; write = 1'b0; loadb = 1'b1; sximm8 = {16{1'b0}}; vsel = 2'b00; loadc = 1'b1;
#100
clk = 1'b1; loadb = 1'b0;
#100
clk = 1'b0; ALUop = 2'b00; loadb = 1'b0; loadc = 1'b1;
#100
clk = 1'b1;
#100
clk = 1'b0; write = 1'b0; writenum = 3'b010; loadc = 1'b1; ALUop = 2'b00;
#100
clk = 1'b1;
#100
clk = 1'b0; loadc=1'b0;
#100;
$display("All tests work!");
end
endmodule | 0 |
139,036 | data/full_repos/permissive/86668501/Lab7-L1D/lab7_top.v | 86,668,501 | lab7_top.v | v | 49 | 69 | [] | [] | [] | [(1, 20), (22, 48)] | null | null | 1: b"%Error: data/full_repos/permissive/86668501/Lab7-L1D/lab7_top.v:12: Cannot find file containing module: 'cpu'\n cpu CPU1(CLOCK_50, reset, Cout);\n ^~~\n ... Looked in:\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/cpu\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/cpu.v\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/cpu.sv\n cpu\n cpu.v\n cpu.sv\n obj_dir/cpu\n obj_dir/cpu.v\n obj_dir/cpu.sv\n%Error: Exiting due to 1 error(s)\n" | 304,260 | module | module lab7_top(KEY,SW,LEDR,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,CLOCK_50);
input [3:0] KEY;
input [9:0] SW;
output [9:0] LEDR;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
input CLOCK_50;
wire [15:0] Cout;
wire clk, reset;
cpu CPU1(CLOCK_50, reset, Cout);
sseg seg0(Cout[3:0], HEX0);
sseg seg1(Cout[7:4], HEX1);
sseg seg2(Cout[11:8], HEX2);
sseg seg3(Cout[15:12], HEX3);
sseg seg4(4'b0000, HEX4);
sseg seg5(4'b0000, HEX5);
endmodule | module lab7_top(KEY,SW,LEDR,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,CLOCK_50); |
input [3:0] KEY;
input [9:0] SW;
output [9:0] LEDR;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
input CLOCK_50;
wire [15:0] Cout;
wire clk, reset;
cpu CPU1(CLOCK_50, reset, Cout);
sseg seg0(Cout[3:0], HEX0);
sseg seg1(Cout[7:4], HEX1);
sseg seg2(Cout[11:8], HEX2);
sseg seg3(Cout[15:12], HEX3);
sseg seg4(4'b0000, HEX4);
sseg seg5(4'b0000, HEX5);
endmodule | 0 |
139,037 | data/full_repos/permissive/86668501/Lab7-L1D/lab7_top.v | 86,668,501 | lab7_top.v | v | 49 | 69 | [] | [] | [] | [(1, 20), (22, 48)] | null | null | 1: b"%Error: data/full_repos/permissive/86668501/Lab7-L1D/lab7_top.v:12: Cannot find file containing module: 'cpu'\n cpu CPU1(CLOCK_50, reset, Cout);\n ^~~\n ... Looked in:\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/cpu\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/cpu.v\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/cpu.sv\n cpu\n cpu.v\n cpu.sv\n obj_dir/cpu\n obj_dir/cpu.v\n obj_dir/cpu.sv\n%Error: Exiting due to 1 error(s)\n" | 304,260 | module | module sseg(in,segs);
input [3:0] in;
output [6:0] segs;
reg [6:0] segs;
always @(*) begin
case(in)
0: segs = 7'b1000000;
1: segs = 7'b1111001;
2: segs = 7'b0100100;
3: segs = 7'b0110000;
4: segs = 7'b0011001;
5: segs = 7'b0010010;
6: segs = 7'b0000010;
7: segs = 7'b1111000;
8: segs = 7'b0000000;
9: segs = 7'b0010000;
10: segs = 7'b0001000;
11: segs = 7'b0000011;
12: segs = 7'b1000110;
13: segs = 7'b0100001;
14: segs = 7'b0000110;
15: segs = 7'b0001110;
endcase
end
endmodule | module sseg(in,segs); |
input [3:0] in;
output [6:0] segs;
reg [6:0] segs;
always @(*) begin
case(in)
0: segs = 7'b1000000;
1: segs = 7'b1111001;
2: segs = 7'b0100100;
3: segs = 7'b0110000;
4: segs = 7'b0011001;
5: segs = 7'b0010010;
6: segs = 7'b0000010;
7: segs = 7'b1111000;
8: segs = 7'b0000000;
9: segs = 7'b0010000;
10: segs = 7'b0001000;
11: segs = 7'b0000011;
12: segs = 7'b1000110;
13: segs = 7'b0100001;
14: segs = 7'b0000110;
15: segs = 7'b0001110;
endcase
end
endmodule | 0 |
139,038 | data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v | 86,668,501 | pccontroller.v | v | 136 | 160 | [] | [] | [] | [(1, 26), (29, 135)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:43: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:46: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:48: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:51: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:53: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:56: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:58: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:61: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:63: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:66: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:68: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:71: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:73: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:76: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:78: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:81: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:83: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:86: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:88: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:91: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:93: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:96: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:98: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:101: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:103: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:106: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:108: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:111: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:113: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:116: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:118: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:121: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:123: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:126: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:128: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:131: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:133: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:21: Cannot find file containing module: \'Program_counter\'\n Program_counter pcx(clk, reset, sximm8, incp, execb, status, cond, msel, Bout, Cout, mwrite, loadir, PC, mdata, IR);\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/Program_counter\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/Program_counter.v\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/Program_counter.sv\n Program_counter\n Program_counter.v\n Program_counter.sv\n obj_dir/Program_counter\n obj_dir/Program_counter.v\n obj_dir/Program_counter.sv\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:23: Cannot find file containing module: \'controller\'\n controller controlx(clk, reset, opcode, op, loadir, incp, execb, msel, mwrite, loada, loadb,\n ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 37 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,261 | module | module pccontroller(clk,reset, opcode, op, cond, Bout, Cout, sximm8, status, IR, PC);
input clk;
input reset;
input [2:0] opcode, cond;
input [1:0] op;
input [15:0] Bout, Cout, sximm8;
input [2:0] status;
output [15:0] IR;
output [7:0] PC;
wire mwrite, msel, execb, incp, loadir;
wire asel, bsel, loada, loadb, loadc, loads, write;
wire [1:0] op, ALUop, shift, vsel, nsel;
wire [2:0] opcode, readnum, writenum, status, cond;
wire [15:0] Bout, sximm5, sximm8, mdata, IR;
wire [7:0] PC;
Program_counter pcx(clk, reset, sximm8, incp, execb, status, cond, msel, Bout, Cout, mwrite, loadir, PC, mdata, IR);
controller controlx(clk, reset, opcode, op, loadir, incp, execb, msel, mwrite, loada, loadb,
asel, bsel, loadc, loads, write, nsel, vsel);
endmodule | module pccontroller(clk,reset, opcode, op, cond, Bout, Cout, sximm8, status, IR, PC); |
input clk;
input reset;
input [2:0] opcode, cond;
input [1:0] op;
input [15:0] Bout, Cout, sximm8;
input [2:0] status;
output [15:0] IR;
output [7:0] PC;
wire mwrite, msel, execb, incp, loadir;
wire asel, bsel, loada, loadb, loadc, loads, write;
wire [1:0] op, ALUop, shift, vsel, nsel;
wire [2:0] opcode, readnum, writenum, status, cond;
wire [15:0] Bout, sximm5, sximm8, mdata, IR;
wire [7:0] PC;
Program_counter pcx(clk, reset, sximm8, incp, execb, status, cond, msel, Bout, Cout, mwrite, loadir, PC, mdata, IR);
controller controlx(clk, reset, opcode, op, loadir, incp, execb, msel, mwrite, loada, loadb,
asel, bsel, loadc, loads, write, nsel, vsel);
endmodule | 0 |
139,039 | data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v | 86,668,501 | pccontroller.v | v | 136 | 160 | [] | [] | [] | [(1, 26), (29, 135)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:43: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:46: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:48: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:51: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:53: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:56: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:58: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:61: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:63: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:66: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:68: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:71: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:73: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:76: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:78: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:81: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:83: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:86: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:88: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:91: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:93: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:96: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:98: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:101: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:103: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:106: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:108: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:111: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:113: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:116: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:118: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:121: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:123: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:126: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:128: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:131: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:133: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:21: Cannot find file containing module: \'Program_counter\'\n Program_counter pcx(clk, reset, sximm8, incp, execb, status, cond, msel, Bout, Cout, mwrite, loadir, PC, mdata, IR);\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/Program_counter\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/Program_counter.v\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/Program_counter.sv\n Program_counter\n Program_counter.v\n Program_counter.sv\n obj_dir/Program_counter\n obj_dir/Program_counter.v\n obj_dir/Program_counter.sv\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/pccontroller.v:23: Cannot find file containing module: \'controller\'\n controller controlx(clk, reset, opcode, op, loadir, incp, execb, msel, mwrite, loada, loadb,\n ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 37 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,261 | module | module pccontroller_tb();
reg clk;
reg reset;
reg [2:0] opcode, cond;
reg [1:0] op;
reg [15:0] Bout, Cout, sximm8;
reg [2:0] status;
wire [15:0] IR;
wire [7:0] PC;
pccontroller dut (clk, reset, opcode, op, cond, Bout, Cout, sximm8, status, IR, PC);
initial begin
clk=1'b0;reset=1'b1;opcode=3'b001; op=2'b00; cond=3'b000; Bout=16'b0000000000000000; Cout=16'b1100110011001100; sximm8=16'b0111111111111111; status=3'b111;
#100
clk=1'b1;reset=1'b0;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
end
endmodule | module pccontroller_tb(); |
reg clk;
reg reset;
reg [2:0] opcode, cond;
reg [1:0] op;
reg [15:0] Bout, Cout, sximm8;
reg [2:0] status;
wire [15:0] IR;
wire [7:0] PC;
pccontroller dut (clk, reset, opcode, op, cond, Bout, Cout, sximm8, status, IR, PC);
initial begin
clk=1'b0;reset=1'b1;opcode=3'b001; op=2'b00; cond=3'b000; Bout=16'b0000000000000000; Cout=16'b1100110011001100; sximm8=16'b0111111111111111; status=3'b111;
#100
clk=1'b1;reset=1'b0;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
clk=1'b1;
#100
clk=1'b0;
#100;
end
endmodule | 0 |
139,040 | data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v | 86,668,501 | Program_counter.v | v | 134 | 120 | [] | [] | [] | [(1, 35), (37, 57), (59, 133)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:71: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:73: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:75: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:78: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:80: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:83: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:85: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:88: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:90: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:93: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:95: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:98: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:100: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:103: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:105: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:108: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:110: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:113: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:115: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:118: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:120: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:123: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:125: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:128: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:130: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:25: Operator OR expects 8 bits on the LHS, but LHS\'s VARREF \'taken\' generates 1 bits.\n : ... In instance PC_tb.dut\n assign loadpc = taken | incp;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:25: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'incp\' generates 1 bits.\n : ... In instance PC_tb.dut\n assign loadpc = taken | incp;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:28: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'loadpc\' generates 8 bits.\n : ... In instance PC_tb.dut\n assign loadpc_out = loadpc ? pc_next : PC;\n ^\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:30: Cannot find file containing module: \'vDFFE\'\n vDFFE #(8) PCx (clk, 1\'b1, reset_out, PC);\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/vDFFE\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/vDFFE.v\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/vDFFE.sv\n vDFFE\n vDFFE.v\n vDFFE.sv\n obj_dir/vDFFE\n obj_dir/vDFFE.v\n obj_dir/vDFFE.sv\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:34: Cannot find file containing module: \'vDFFE\'\n vDFFE #(16) IRx (clk, loadir, mdata, IR);\n ^~~~~\n%Error: Exiting due to 2 error(s), 28 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,262 | module | module Program_counter(clk, reset, sximm8, incp, execb, status, cond, msel, Bout, Cout, mwrite, loadir, PC, mdata, IR);
input clk, reset, incp, execb, msel, loadir, mwrite;
input [2:0] status, cond;
input [15:0] sximm8, Bout, Cout;
output [15:0] IR, mdata;
output [7:0] PC;
wire [7:0] pc1, loadpc, reset_out, address, pctgt, pc_next, loadpc_out;
wire [15:0] mdata,IR;
reg taken;
always @(*) begin
casex({execb, status, cond})
{1'b1, 3'bxxx, 3'b000} : {taken} = {1'b1};
{1'b1, 3'bx1x, 3'b001} : {taken} = {1'b1};
{1'b1, 3'bx0x, 3'b010} : {taken} = {1'b1};
{1'b1, 3'b1x0, 3'b011} : {taken} = {1'b1};
{1'b1, 3'b0x1, 3'b011} : {taken} = {1'b1};
{1'b1, 3'b0x1, 3'b100} : {taken} = {1'b1};
{1'b1, 3'b1x0, 3'b100} : {taken} = {1'b1};
{1'b1, 3'bx1x, 3'b100} : {taken} = {1'b1};
default : {taken} = {1'b0};
endcase
end
assign pctgt = sximm8[7:0] + PC;
assign loadpc = taken | incp;
assign pc_next = incp ? (PC + 1) : pctgt;
assign loadpc_out = loadpc ? pc_next : PC;
assign reset_out = ~reset ? (loadpc_out) : 8'b00000000;
vDFFE #(8) PCx (clk, 1'b1, reset_out, PC);
assign address = msel ? (Cout[7:0]) : PC;
RAM #(16,8) ramx (clk, address, address, mwrite, Bout, mdata);
vDFFE #(16) IRx (clk, loadir, mdata, IR);
endmodule | module Program_counter(clk, reset, sximm8, incp, execb, status, cond, msel, Bout, Cout, mwrite, loadir, PC, mdata, IR); |
input clk, reset, incp, execb, msel, loadir, mwrite;
input [2:0] status, cond;
input [15:0] sximm8, Bout, Cout;
output [15:0] IR, mdata;
output [7:0] PC;
wire [7:0] pc1, loadpc, reset_out, address, pctgt, pc_next, loadpc_out;
wire [15:0] mdata,IR;
reg taken;
always @(*) begin
casex({execb, status, cond})
{1'b1, 3'bxxx, 3'b000} : {taken} = {1'b1};
{1'b1, 3'bx1x, 3'b001} : {taken} = {1'b1};
{1'b1, 3'bx0x, 3'b010} : {taken} = {1'b1};
{1'b1, 3'b1x0, 3'b011} : {taken} = {1'b1};
{1'b1, 3'b0x1, 3'b011} : {taken} = {1'b1};
{1'b1, 3'b0x1, 3'b100} : {taken} = {1'b1};
{1'b1, 3'b1x0, 3'b100} : {taken} = {1'b1};
{1'b1, 3'bx1x, 3'b100} : {taken} = {1'b1};
default : {taken} = {1'b0};
endcase
end
assign pctgt = sximm8[7:0] + PC;
assign loadpc = taken | incp;
assign pc_next = incp ? (PC + 1) : pctgt;
assign loadpc_out = loadpc ? pc_next : PC;
assign reset_out = ~reset ? (loadpc_out) : 8'b00000000;
vDFFE #(8) PCx (clk, 1'b1, reset_out, PC);
assign address = msel ? (Cout[7:0]) : PC;
RAM #(16,8) ramx (clk, address, address, mwrite, Bout, mdata);
vDFFE #(16) IRx (clk, loadir, mdata, IR);
endmodule | 0 |
139,041 | data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v | 86,668,501 | Program_counter.v | v | 134 | 120 | [] | [] | [] | [(1, 35), (37, 57), (59, 133)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:71: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:73: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:75: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:78: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:80: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:83: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:85: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:88: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:90: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:93: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:95: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:98: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:100: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:103: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:105: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:108: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:110: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:113: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:115: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:118: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:120: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:123: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:125: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:128: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:130: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:25: Operator OR expects 8 bits on the LHS, but LHS\'s VARREF \'taken\' generates 1 bits.\n : ... In instance PC_tb.dut\n assign loadpc = taken | incp;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:25: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'incp\' generates 1 bits.\n : ... In instance PC_tb.dut\n assign loadpc = taken | incp;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:28: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'loadpc\' generates 8 bits.\n : ... In instance PC_tb.dut\n assign loadpc_out = loadpc ? pc_next : PC;\n ^\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:30: Cannot find file containing module: \'vDFFE\'\n vDFFE #(8) PCx (clk, 1\'b1, reset_out, PC);\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/vDFFE\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/vDFFE.v\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/vDFFE.sv\n vDFFE\n vDFFE.v\n vDFFE.sv\n obj_dir/vDFFE\n obj_dir/vDFFE.v\n obj_dir/vDFFE.sv\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:34: Cannot find file containing module: \'vDFFE\'\n vDFFE #(16) IRx (clk, loadir, mdata, IR);\n ^~~~~\n%Error: Exiting due to 2 error(s), 28 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,262 | module | module RAM(clk, read_address, write_address, write, din, dout);
parameter data_width = 16;
parameter addr_width = 8;
parameter filename = "data.txt";
input clk;
input [addr_width-1:0] read_address, write_address;
input write;
input [data_width-1:0] din;
output [data_width-1:0] dout;
reg [data_width-1:0] dout;
reg [data_width-1:0] mem [2**addr_width-1:0];
initial $readmemb(filename,mem);
always @(posedge clk) begin
if (write)
mem[write_address] <=din;
dout <= mem[read_address];
end
endmodule | module RAM(clk, read_address, write_address, write, din, dout); |
parameter data_width = 16;
parameter addr_width = 8;
parameter filename = "data.txt";
input clk;
input [addr_width-1:0] read_address, write_address;
input write;
input [data_width-1:0] din;
output [data_width-1:0] dout;
reg [data_width-1:0] dout;
reg [data_width-1:0] mem [2**addr_width-1:0];
initial $readmemb(filename,mem);
always @(posedge clk) begin
if (write)
mem[write_address] <=din;
dout <= mem[read_address];
end
endmodule | 0 |
139,042 | data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v | 86,668,501 | Program_counter.v | v | 134 | 120 | [] | [] | [] | [(1, 35), (37, 57), (59, 133)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:71: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:73: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:75: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:78: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:80: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:83: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:85: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:88: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:90: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:93: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:95: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:98: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:100: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:103: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:105: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:108: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:110: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:113: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:115: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:118: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:120: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:123: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:125: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:128: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:130: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:25: Operator OR expects 8 bits on the LHS, but LHS\'s VARREF \'taken\' generates 1 bits.\n : ... In instance PC_tb.dut\n assign loadpc = taken | incp;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:25: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'incp\' generates 1 bits.\n : ... In instance PC_tb.dut\n assign loadpc = taken | incp;\n ^\n%Warning-WIDTH: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:28: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'loadpc\' generates 8 bits.\n : ... In instance PC_tb.dut\n assign loadpc_out = loadpc ? pc_next : PC;\n ^\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:30: Cannot find file containing module: \'vDFFE\'\n vDFFE #(8) PCx (clk, 1\'b1, reset_out, PC);\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/vDFFE\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/vDFFE.v\n data/full_repos/permissive/86668501/Lab7-L1D,data/full_repos/permissive/86668501/vDFFE.sv\n vDFFE\n vDFFE.v\n vDFFE.sv\n obj_dir/vDFFE\n obj_dir/vDFFE.v\n obj_dir/vDFFE.sv\n%Error: data/full_repos/permissive/86668501/Lab7-L1D/Program_counter.v:34: Cannot find file containing module: \'vDFFE\'\n vDFFE #(16) IRx (clk, loadir, mdata, IR);\n ^~~~~\n%Error: Exiting due to 2 error(s), 28 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,262 | module | module PC_tb();
reg clk, reset, incp, execb, msel, loadir, mwrite;
reg [2:0] status, cond;
reg [15:0] sximm8, Bout, Cout;
wire [15:0] IR, mdata;
wire [7:0] PC;
Program_counter dut(clk, reset, sximm8, incp, execb, status, cond, msel, Bout, Cout, mwrite, loadir, PC, mdata, IR);
initial begin
clk=1'b0; reset=1'b1; incp=1'b0; execb=1'b1; loadir=1'b1; mwrite=1'b0; status=3'b111; cond=3'b000; msel=1'b0;
sximm8=16'b1110001110001110; Bout=16'b0000111100001111; Cout=16'b1100110011001100;
#10
clk=1'b1;
#10
clk=1'b0; reset=1'b0;
#10
clk=1'b1;
#10
clk=1'b0;
#10
clk=1'b1;
#10
clk=1'b0;
#10
clk=1'b1; status=3'b111; cond=3'b001;
#10
clk=1'b0;
#10
clk=1'b1;
#10
clk=1'b0;
#10
clk=1'b1; status=3'b101; cond=3'b010;
#10
clk=1'b0;
#10
clk=1'b1; reset=1'b1;
#10
clk=1'b0;
#10
clk=1'b1; status=3'b110; cond=3'b011;
#10
clk=1'b0; reset=1'b0;
#10;
clk=1'b1;
#10
clk=1'b0;
#10;
clk=1'b1; status=3'b001; cond=3'b100;
#10
clk=1'b0;
#10;
clk=1'b1;
#10
clk=1'b0;
#10;
clk=1'b1; status=3'b111; cond=3'b100;
#10
clk=1'b0;
#10;
end
endmodule | module PC_tb(); |
reg clk, reset, incp, execb, msel, loadir, mwrite;
reg [2:0] status, cond;
reg [15:0] sximm8, Bout, Cout;
wire [15:0] IR, mdata;
wire [7:0] PC;
Program_counter dut(clk, reset, sximm8, incp, execb, status, cond, msel, Bout, Cout, mwrite, loadir, PC, mdata, IR);
initial begin
clk=1'b0; reset=1'b1; incp=1'b0; execb=1'b1; loadir=1'b1; mwrite=1'b0; status=3'b111; cond=3'b000; msel=1'b0;
sximm8=16'b1110001110001110; Bout=16'b0000111100001111; Cout=16'b1100110011001100;
#10
clk=1'b1;
#10
clk=1'b0; reset=1'b0;
#10
clk=1'b1;
#10
clk=1'b0;
#10
clk=1'b1;
#10
clk=1'b0;
#10
clk=1'b1; status=3'b111; cond=3'b001;
#10
clk=1'b0;
#10
clk=1'b1;
#10
clk=1'b0;
#10
clk=1'b1; status=3'b101; cond=3'b010;
#10
clk=1'b0;
#10
clk=1'b1; reset=1'b1;
#10
clk=1'b0;
#10
clk=1'b1; status=3'b110; cond=3'b011;
#10
clk=1'b0; reset=1'b0;
#10;
clk=1'b1;
#10
clk=1'b0;
#10;
clk=1'b1; status=3'b001; cond=3'b100;
#10
clk=1'b0;
#10;
clk=1'b1;
#10
clk=1'b0;
#10;
clk=1'b1; status=3'b111; cond=3'b100;
#10
clk=1'b0;
#10;
end
endmodule | 0 |
139,043 | data/full_repos/permissive/86668501/Lab7-L1D/shifter.v | 86,668,501 | shifter.v | v | 45 | 71 | [] | [] | [] | [(1, 16), (19, 44)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/shifter.v:28: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/shifter.v:30: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/shifter.v:32: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/shifter.v:34: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/shifter.v:36: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/shifter.v:38: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/shifter.v:40: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/shifter.v:42: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: Exiting due to 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,264 | module | module shifter (loadb, shift, shiftedB);
parameter n=16;
input [n-1:0] loadb;
input [1:0] shift;
output [n-1:0] shiftedB;
reg [n-1:0] shiftedB;
always @(*) begin
case(shift)
2'b00 : {shiftedB}={loadb};
2'b01 : {shiftedB[n-1:1],shiftedB[0]}={loadb[n-2:0],1'b0};
2'b10 : {shiftedB[n-2:0],shiftedB[n-1]}={loadb[n-1:1],1'b0};
2'b11 : {shiftedB[n-2:0],shiftedB[n-1]}={loadb[n-1:1],loadb[n-1]};
endcase
end
endmodule | module shifter (loadb, shift, shiftedB); |
parameter n=16;
input [n-1:0] loadb;
input [1:0] shift;
output [n-1:0] shiftedB;
reg [n-1:0] shiftedB;
always @(*) begin
case(shift)
2'b00 : {shiftedB}={loadb};
2'b01 : {shiftedB[n-1:1],shiftedB[0]}={loadb[n-2:0],1'b0};
2'b10 : {shiftedB[n-2:0],shiftedB[n-1]}={loadb[n-1:1],1'b0};
2'b11 : {shiftedB[n-2:0],shiftedB[n-1]}={loadb[n-1:1],loadb[n-1]};
endcase
end
endmodule | 0 |
139,044 | data/full_repos/permissive/86668501/Lab7-L1D/shifter.v | 86,668,501 | shifter.v | v | 45 | 71 | [] | [] | [] | [(1, 16), (19, 44)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/shifter.v:28: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/shifter.v:30: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/shifter.v:32: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/shifter.v:34: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/shifter.v:36: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/shifter.v:38: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/shifter.v:40: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/86668501/Lab7-L1D/shifter.v:42: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: Exiting due to 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 304,264 | module | module shifter_tb();
reg [15:0] loadb;
reg [1:0] shift;
wire [15:0] newloadb;
shifter #(16) dut(loadb,shift,newloadb);
initial begin
loadb=16'b0000100001000111; shift=2'b00;
#100
loadb=16'b1110001000100011; shift=2'b01;
#100
loadb=16'b1110000111011101; shift=2'b10;
#100
loadb=16'b1110100001000100; shift=2'b11;
#100
loadb=16'b0110100001000100; shift=2'b11;
#100;
loadb=16'b1111111111111111; shift=2'b10;
#100;
loadb=16'b1111111111111111; shift=2'b01;
#100;
loadb=16'b1110100001000101; shift=2'b11;
#100;
end
endmodule | module shifter_tb(); |
reg [15:0] loadb;
reg [1:0] shift;
wire [15:0] newloadb;
shifter #(16) dut(loadb,shift,newloadb);
initial begin
loadb=16'b0000100001000111; shift=2'b00;
#100
loadb=16'b1110001000100011; shift=2'b01;
#100
loadb=16'b1110000111011101; shift=2'b10;
#100
loadb=16'b1110100001000100; shift=2'b11;
#100
loadb=16'b0110100001000100; shift=2'b11;
#100;
loadb=16'b1111111111111111; shift=2'b10;
#100;
loadb=16'b1111111111111111; shift=2'b01;
#100;
loadb=16'b1110100001000101; shift=2'b11;
#100;
end
endmodule | 0 |
139,045 | data/full_repos/permissive/86674840/tictactoe.v | 86,674,840 | tictactoe.v | v | 302 | 115 | [] | [] | [] | null | line:110: before: ":" | null | 1: b'%Error: data/full_repos/permissive/86674840/tictactoe.v:115: syntax error, unexpected endcase\n endcase\n ^~~~~~~\n%Error: data/full_repos/permissive/86674840/tictactoe.v:147: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [8:0] x, o; \n ^\n%Error: data/full_repos/permissive/86674840/tictactoe.v:149: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [3:0] x_score, o_score, win;\n ^~~~~~~\n%Error: Exiting due to 3 error(s)\n' | 304,265 | module | module test(SW, CLOCK_50, KEY, HEX0, HEX1, HEX2, GPIO);
input [8:0] SW;
input [3:0] KEY;
input CLOCK_50;
output [6:0] HEX0, HEX1, HEX2;
output [35:0] GPIO;
wire [8:0] grd;
wire [8:0] data_in;
wire go, ld_x, ld_o;
wire reset;
wire reset_sb;
wire to_menu;
wire [3:0] win, x_score, o_score;
assign data_in = SW[8:0];
assign go = KEY[3];
assign reset = KEY[2];
assign reset_sb = KEY[1];
assign to_menu = KEY[0];
control C0(
.clk(CLOCK_50),
.reset(reset),
.go(go),
.ld_x(ld_x),
.ld_o(ld_o)
);
datapath D0(
.clk(CLOCK_50),
.reset(reset),
.ld_x(ld_x),
.ld_o(ld_o),
.data_in(data_in),
.x_score(x_score),
.o_score(o_score),
.win(win),
.reset_sb(reset_sb),
.LED_1({GPIO[0], GPIO[2], GPIO[4], GPIO[6], GPIO[8], GPIO[10], GPIO[12], GPIO[14], GPIO[16]}),
.LED_2({GPIO[18], GPIO[20], GPIO[22], GPIO[24], GPIO[26], GPIO[28], GPIO[30], GPIO[32], GPIO[34]}),
.grd(grd[8:0])
);
hex_decoder H0(
.hex_digit(o_score),
.segments(HEX0)
);
hex_decoder H1(
.hex_digit(x_score),
.segments(HEX1)
);
hex_decoder H2(
.hex_digit(win),
.segments(HEX2)
);
endmodule | module test(SW, CLOCK_50, KEY, HEX0, HEX1, HEX2, GPIO); |
input [8:0] SW;
input [3:0] KEY;
input CLOCK_50;
output [6:0] HEX0, HEX1, HEX2;
output [35:0] GPIO;
wire [8:0] grd;
wire [8:0] data_in;
wire go, ld_x, ld_o;
wire reset;
wire reset_sb;
wire to_menu;
wire [3:0] win, x_score, o_score;
assign data_in = SW[8:0];
assign go = KEY[3];
assign reset = KEY[2];
assign reset_sb = KEY[1];
assign to_menu = KEY[0];
control C0(
.clk(CLOCK_50),
.reset(reset),
.go(go),
.ld_x(ld_x),
.ld_o(ld_o)
);
datapath D0(
.clk(CLOCK_50),
.reset(reset),
.ld_x(ld_x),
.ld_o(ld_o),
.data_in(data_in),
.x_score(x_score),
.o_score(o_score),
.win(win),
.reset_sb(reset_sb),
.LED_1({GPIO[0], GPIO[2], GPIO[4], GPIO[6], GPIO[8], GPIO[10], GPIO[12], GPIO[14], GPIO[16]}),
.LED_2({GPIO[18], GPIO[20], GPIO[22], GPIO[24], GPIO[26], GPIO[28], GPIO[30], GPIO[32], GPIO[34]}),
.grd(grd[8:0])
);
hex_decoder H0(
.hex_digit(o_score),
.segments(HEX0)
);
hex_decoder H1(
.hex_digit(x_score),
.segments(HEX1)
);
hex_decoder H2(
.hex_digit(win),
.segments(HEX2)
);
endmodule | 0 |
139,046 | data/full_repos/permissive/86674840/tictactoe.v | 86,674,840 | tictactoe.v | v | 302 | 115 | [] | [] | [] | null | line:110: before: ":" | null | 1: b'%Error: data/full_repos/permissive/86674840/tictactoe.v:115: syntax error, unexpected endcase\n endcase\n ^~~~~~~\n%Error: data/full_repos/permissive/86674840/tictactoe.v:147: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [8:0] x, o; \n ^\n%Error: data/full_repos/permissive/86674840/tictactoe.v:149: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [3:0] x_score, o_score, win;\n ^~~~~~~\n%Error: Exiting due to 3 error(s)\n' | 304,265 | module | module singleledtest(l1);
output l1;
assign l1=1;
endmodule | module singleledtest(l1); |
output l1;
assign l1=1;
endmodule | 0 |
139,047 | data/full_repos/permissive/86674840/tictactoe.v | 86,674,840 | tictactoe.v | v | 302 | 115 | [] | [] | [] | null | line:110: before: ":" | null | 1: b'%Error: data/full_repos/permissive/86674840/tictactoe.v:115: syntax error, unexpected endcase\n endcase\n ^~~~~~~\n%Error: data/full_repos/permissive/86674840/tictactoe.v:147: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [8:0] x, o; \n ^\n%Error: data/full_repos/permissive/86674840/tictactoe.v:149: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [3:0] x_score, o_score, win;\n ^~~~~~~\n%Error: Exiting due to 3 error(s)\n' | 304,265 | module | module control(
input clk,
input reset,
input go,
output reg ld_x, ld_o
);
reg [3:0] current_state, next_state;
localparam S_LOAD_X = 5'd0,
S_LOAD_X_WAIT = 5'd1,
S_LOAD_O = 5'd2,
S_LOAD_O_WAIT = 5'd3;
always@(*)
begin: state_table
case (current_state)
S_LOAD_X: next_state = go ? S_LOAD_X_WAIT : S_LOAD_X;
S_LOAD_X_WAIT: next_state = go ? S_LOAD_X_WAIT : S_LOAD_O;
S_LOAD_O: next_state = go ? S_LOAD_O_WAIT : S_LOAD_O;
S_LOAD_O_WAIT: next_state = go ? S_LOAD_O_WAIT : S_LOAD_X;
default: next_state = S_LOAD_X;
endcase
end
always @(*)
begin: enable_signals
ld_x = 1'b0;
ld_o = 1'b0;
case (current_state)
S_LOAD_X: begin
ld_x = 1'b1;
end
S_LOAD_O: begin
ld_o = 1'b1;
end8:0
endcase
end
always@(posedge clk)
begin: state_FFs
if(!reset)
current_state <= S_LOAD_O_WAIT;
else
current_state <= next_state;
end
endmodule | module control(
input clk,
input reset,
input go,
output reg ld_x, ld_o
); |
reg [3:0] current_state, next_state;
localparam S_LOAD_X = 5'd0,
S_LOAD_X_WAIT = 5'd1,
S_LOAD_O = 5'd2,
S_LOAD_O_WAIT = 5'd3;
always@(*)
begin: state_table
case (current_state)
S_LOAD_X: next_state = go ? S_LOAD_X_WAIT : S_LOAD_X;
S_LOAD_X_WAIT: next_state = go ? S_LOAD_X_WAIT : S_LOAD_O;
S_LOAD_O: next_state = go ? S_LOAD_O_WAIT : S_LOAD_O;
S_LOAD_O_WAIT: next_state = go ? S_LOAD_O_WAIT : S_LOAD_X;
default: next_state = S_LOAD_X;
endcase
end
always @(*)
begin: enable_signals
ld_x = 1'b0;
ld_o = 1'b0;
case (current_state)
S_LOAD_X: begin
ld_x = 1'b1;
end
S_LOAD_O: begin
ld_o = 1'b1;
end8:0
endcase
end
always@(posedge clk)
begin: state_FFs
if(!reset)
current_state <= S_LOAD_O_WAIT;
else
current_state <= next_state;
end
endmodule | 0 |
139,048 | data/full_repos/permissive/86674840/tictactoe.v | 86,674,840 | tictactoe.v | v | 302 | 115 | [] | [] | [] | null | line:110: before: ":" | null | 1: b'%Error: data/full_repos/permissive/86674840/tictactoe.v:115: syntax error, unexpected endcase\n endcase\n ^~~~~~~\n%Error: data/full_repos/permissive/86674840/tictactoe.v:147: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [8:0] x, o; \n ^\n%Error: data/full_repos/permissive/86674840/tictactoe.v:149: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [3:0] x_score, o_score, win;\n ^~~~~~~\n%Error: Exiting due to 3 error(s)\n' | 304,265 | module | module datapath(
clk,
reset,
data_in,
ld_x, ld_o,
ld_r,
x_score, o_score, win,
LED_1, LED_2, reset_sb,
grd
);
input clk;
input reset, reset_sb;
input [8:0] data_in;
input ld_x, ld_o;
input ld_r;
output reg [0:8] LED_1, LED_2;
output reg [8:0] grd;
reg [8:0] x, o;
output [3:0] x_score, o_score, win;
reg [3:0] x_score, o_score, win;
initial begin
grd = 9'b0_0000_0000;
x = 9'b0_0000_0000;
o = 9'b0_0000_0000;
x_score = 4'h0;
o_score = 4'h0;
win = 4'h0;
end
always@(posedge clk) begin
if(!reset_sb) begin
x_score = 4'h0;
o_score = 4'h0;
end
if(!reset) begin
grd = 9'b0_0000_0000;
x = 9'b0_0000_0000;
o = 9'b0_0000_0000;
win = 4'h0;
LED_1 = 9'b0_0000_0000;
LED_2 = 9'b0_0000_0000;
end
else begin
if (ld_x && !win) begin
integer i;
reg mult_input;
mult_input = 0;
for (i=0; i<9; i=i+1) begin
if(!mult_input) begin
if (data_in[i]) begin
if (grd[i] == 1'b0 && o[i] == 1'b0 && x[i] == 1'b0) begin
grd[i] = 1'b1;
x[i] = 1'b1;
mult_input = 1;
end
end
end
end
if(x[0] && x[3] && x[6])
win = 4'h1;
else if(x[1] && x[4] && x[7])
win = 4'h1;
else if(x[2] && x[5] && x[8])
win = 4'h1;
else if(x[0] && x[1] && x[2])
win = 4'h1;
else if(x[3] && x[4] && x[5])
win = 4'h1;
else if(x[6] && x[7] && x[8])
win = 4'h1;
else if(x[0] && x[4] && x[8])
win = 4'h1;
else if(x[2] && x[4] && x[6])
win = 4'h1;
else
win = 4'h0;
LED_1 = x;
if (win == 4'h1) begin
x_score = x_score + 4'h1;
end
else begin
reg tie;
tie = 1'b1;
for (i=0; i<9; i=i+1) begin
if(grd[i] == 1'b0)
tie = 1'b0;
end
if (tie == 1'b1) begin
win = 4'he;
end
end
end
if (ld_o && !win) begin
integer i;
reg mult_input;
mult_input = 0;
for (i=0; i<9; i=i+1) begin
if(!mult_input) begin
if (data_in[i] && mult_input == 0) begin
if (grd[i] == 1'b0 && o[i] == 1'b0 && x[i] == 1'b0) begin
grd[i] = 1'b1;
o[i] = 1'b1;
mult_input = 1;
end
end
end
end
if(o[0] && o[3] && o[6])
win = 4'h2;
else if(o[1] && o[4] && o[7])
win = 4'h2;
else if(o[2] && o[5] && o[8])
win = 4'h2;
else if(o[0] && o[1] && o[2])
win = 4'h2;
else if(o[3] && o[4] && o[5])
win = 4'h2;
else if(o[6] && o[7] && o[8])
win = 4'h2;
else if(o[0] && o[4] && o[8])
win = 4'h2;
else if(o[2] && o[4] && o[6])
win = 4'h2;
else
win = 4'h0;
LED_2 = o;
if (win == 4'h2) begin
o_score = o_score + 4'h1;
end
else begin
reg tie;
tie = 1'b1;
for (i=0; i<9; i=i+1) begin
if(grd[i] == 1'b0)
tie = 1'b0;
end
if (tie == 1'b1) begin
win = 4'he;
end
end
end
end
end
endmodule | module datapath(
clk,
reset,
data_in,
ld_x, ld_o,
ld_r,
x_score, o_score, win,
LED_1, LED_2, reset_sb,
grd
); |
input clk;
input reset, reset_sb;
input [8:0] data_in;
input ld_x, ld_o;
input ld_r;
output reg [0:8] LED_1, LED_2;
output reg [8:0] grd;
reg [8:0] x, o;
output [3:0] x_score, o_score, win;
reg [3:0] x_score, o_score, win;
initial begin
grd = 9'b0_0000_0000;
x = 9'b0_0000_0000;
o = 9'b0_0000_0000;
x_score = 4'h0;
o_score = 4'h0;
win = 4'h0;
end
always@(posedge clk) begin
if(!reset_sb) begin
x_score = 4'h0;
o_score = 4'h0;
end
if(!reset) begin
grd = 9'b0_0000_0000;
x = 9'b0_0000_0000;
o = 9'b0_0000_0000;
win = 4'h0;
LED_1 = 9'b0_0000_0000;
LED_2 = 9'b0_0000_0000;
end
else begin
if (ld_x && !win) begin
integer i;
reg mult_input;
mult_input = 0;
for (i=0; i<9; i=i+1) begin
if(!mult_input) begin
if (data_in[i]) begin
if (grd[i] == 1'b0 && o[i] == 1'b0 && x[i] == 1'b0) begin
grd[i] = 1'b1;
x[i] = 1'b1;
mult_input = 1;
end
end
end
end
if(x[0] && x[3] && x[6])
win = 4'h1;
else if(x[1] && x[4] && x[7])
win = 4'h1;
else if(x[2] && x[5] && x[8])
win = 4'h1;
else if(x[0] && x[1] && x[2])
win = 4'h1;
else if(x[3] && x[4] && x[5])
win = 4'h1;
else if(x[6] && x[7] && x[8])
win = 4'h1;
else if(x[0] && x[4] && x[8])
win = 4'h1;
else if(x[2] && x[4] && x[6])
win = 4'h1;
else
win = 4'h0;
LED_1 = x;
if (win == 4'h1) begin
x_score = x_score + 4'h1;
end
else begin
reg tie;
tie = 1'b1;
for (i=0; i<9; i=i+1) begin
if(grd[i] == 1'b0)
tie = 1'b0;
end
if (tie == 1'b1) begin
win = 4'he;
end
end
end
if (ld_o && !win) begin
integer i;
reg mult_input;
mult_input = 0;
for (i=0; i<9; i=i+1) begin
if(!mult_input) begin
if (data_in[i] && mult_input == 0) begin
if (grd[i] == 1'b0 && o[i] == 1'b0 && x[i] == 1'b0) begin
grd[i] = 1'b1;
o[i] = 1'b1;
mult_input = 1;
end
end
end
end
if(o[0] && o[3] && o[6])
win = 4'h2;
else if(o[1] && o[4] && o[7])
win = 4'h2;
else if(o[2] && o[5] && o[8])
win = 4'h2;
else if(o[0] && o[1] && o[2])
win = 4'h2;
else if(o[3] && o[4] && o[5])
win = 4'h2;
else if(o[6] && o[7] && o[8])
win = 4'h2;
else if(o[0] && o[4] && o[8])
win = 4'h2;
else if(o[2] && o[4] && o[6])
win = 4'h2;
else
win = 4'h0;
LED_2 = o;
if (win == 4'h2) begin
o_score = o_score + 4'h1;
end
else begin
reg tie;
tie = 1'b1;
for (i=0; i<9; i=i+1) begin
if(grd[i] == 1'b0)
tie = 1'b0;
end
if (tie == 1'b1) begin
win = 4'he;
end
end
end
end
end
endmodule | 0 |
139,049 | data/full_repos/permissive/86674840/tictactoe.v | 86,674,840 | tictactoe.v | v | 302 | 115 | [] | [] | [] | null | line:110: before: ":" | null | 1: b'%Error: data/full_repos/permissive/86674840/tictactoe.v:115: syntax error, unexpected endcase\n endcase\n ^~~~~~~\n%Error: data/full_repos/permissive/86674840/tictactoe.v:147: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [8:0] x, o; \n ^\n%Error: data/full_repos/permissive/86674840/tictactoe.v:149: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [3:0] x_score, o_score, win;\n ^~~~~~~\n%Error: Exiting due to 3 error(s)\n' | 304,265 | module | module hex_decoder(hex_digit, segments);
input [3:0] hex_digit;
output reg [6:0] segments;
always @(*)
case (hex_digit)
4'h0: segments = 7'b100_0000;
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b011_0000;
4'h4: segments = 7'b001_1001;
4'h5: segments = 7'b001_0010;
4'h6: segments = 7'b000_0010;
4'h7: segments = 7'b111_1000;
4'h8: segments = 7'b000_0000;
4'h9: segments = 7'b001_1000;
4'hA: segments = 7'b000_1000;
4'hB: segments = 7'b000_0011;
4'hC: segments = 7'b100_0110;
4'hD: segments = 7'b010_0001;
4'hE: segments = 7'b000_0110;
4'hF: segments = 7'b000_1110;
default: segments = 7'h7f;
endcase
endmodule | module hex_decoder(hex_digit, segments); |
input [3:0] hex_digit;
output reg [6:0] segments;
always @(*)
case (hex_digit)
4'h0: segments = 7'b100_0000;
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b011_0000;
4'h4: segments = 7'b001_1001;
4'h5: segments = 7'b001_0010;
4'h6: segments = 7'b000_0010;
4'h7: segments = 7'b111_1000;
4'h8: segments = 7'b000_0000;
4'h9: segments = 7'b001_1000;
4'hA: segments = 7'b000_1000;
4'hB: segments = 7'b000_0011;
4'hC: segments = 7'b100_0110;
4'hD: segments = 7'b010_0001;
4'hE: segments = 7'b000_0110;
4'hF: segments = 7'b000_1110;
default: segments = 7'h7f;
endcase
endmodule | 0 |
139,050 | data/full_repos/permissive/86722304/src/a.v | 86,722,304 | a.v | v | 42 | 54 | [] | [] | [] | [(3, 39)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/a.v:6: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] l,\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/a.v:7: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] ic,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/a.v:8: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] ar,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/a.v:9: Little bit endian vector: MSB < LSB of bit range: 0:15\n input [0:15] ir,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/86722304/src/a.v:10: Little bit endian vector: MSB < LSB of bit range: 0:15\n output [0:15] a\n ^\n%Error: Exiting due to 5 warning(s)\n' | 304,266 | module | module bus_a(
input bac, bab, baa,
input aa, ab,
input [0:15] l,
input [0:15] ic,
input [0:15] ar,
input [0:15] ir,
output [0:15] a
);
always @ (*) begin
if (bac) a[0:7] = 8'd0;
else case ({ab, aa})
2'b00: a[0:7] = l[0:7];
2'b01: a[0:7] = ar[0:7];
2'b10: a[0:7] = ic[0:7];
2'b11: a[0:7] = l[8:15];
endcase
if (bab) a[8:9] = 2'd0;
else case ({ab, aa})
2'b00: a[8:9] = l[8:9];
2'b01: a[8:9] = ar[8:9];
2'b10: a[8:9] = ic[8:9];
2'b11: a[8:9] = ir[8:9];
endcase
if (baa) a[10:15] = 6'd0;
else case ({ab, aa})
2'b00: a[10:15] = l[10:15];
2'b01: a[10:15] = ar[10:15];
2'b10: a[10:15] = ic[10:15];
2'b11: a[10:15] = ir[10:15];
endcase
end
endmodule | module bus_a(
input bac, bab, baa,
input aa, ab,
input [0:15] l,
input [0:15] ic,
input [0:15] ar,
input [0:15] ir,
output [0:15] a
); |
always @ (*) begin
if (bac) a[0:7] = 8'd0;
else case ({ab, aa})
2'b00: a[0:7] = l[0:7];
2'b01: a[0:7] = ar[0:7];
2'b10: a[0:7] = ic[0:7];
2'b11: a[0:7] = l[8:15];
endcase
if (bab) a[8:9] = 2'd0;
else case ({ab, aa})
2'b00: a[8:9] = l[8:9];
2'b01: a[8:9] = ar[8:9];
2'b10: a[8:9] = ic[8:9];
2'b11: a[8:9] = ir[8:9];
endcase
if (baa) a[10:15] = 6'd0;
else case ({ab, aa})
2'b00: a[10:15] = l[10:15];
2'b01: a[10:15] = ar[10:15];
2'b10: a[10:15] = ic[10:15];
2'b11: a[10:15] = ir[10:15];
endcase
end
endmodule | 24 |
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