Unnamed: 0
int64 1
143k
| directory
stringlengths 39
203
| repo_id
float64 143k
552M
| file_name
stringlengths 3
107
| extension
stringclasses 6
values | no_lines
int64 5
304k
| max_line_len
int64 15
21.6k
| generation_keywords
stringclasses 3
values | license_whitelist_keywords
stringclasses 16
values | license_blacklist_keywords
stringclasses 4
values | icarus_module_spans
stringlengths 8
6.16k
⌀ | icarus_exception
stringlengths 12
124
⌀ | verilator_xml_output_path
stringlengths 60
60
⌀ | verilator_exception
stringlengths 33
1.53M
⌀ | file_index
int64 0
315k
| snippet_type
stringclasses 2
values | snippet
stringlengths 21
9.27M
| snippet_def
stringlengths 9
30.3k
| snippet_body
stringlengths 10
9.27M
| gh_stars
int64 0
1.61k
|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
138,612 | data/full_repos/permissive/85002992/mcu/state2.v | 85,002,992 | state2.v | v | 825 | 76 | [] | [] | [] | null | line:35: before: "," | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/85002992/mcu/state2.v:296: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'state2\'\nmodule state2(input CLK,\n ^~~~~~\n : ... Top module \'outputs\'\nmodule outputs(input CLK_n,\n ^~~~~~~\n : ... Top module \'clock_driver\'\nmodule clock_driver(input CLK_n,\n ^~~~~~~~~~~~\n : ... Top module \'SB_IOeg\'\nmodule SB_IOeg(inout PACKAGE_PIN,\n ^~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:34: Duplicate declaration of signal: \'COMMAND_REG\'\n reg [2:0] COMMAND_REG = 3\'b111 ;\n ^~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:29: ... Location of original declaration\n output [2:0] COMMAND_REG,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:35: Duplicate declaration of signal: \'GRANT_ACCESS_RAND\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg GRANT_ACCESS_RAND = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:16: ... Location of original declaration\n output GRANT_ACCESS_RAND,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:36: Duplicate declaration of signal: \'GRANT_ACCESS_BULK\'\n GRANT_ACCESS_BULK = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:22: ... Location of original declaration\n output GRANT_ACCESS_BULK,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:37: Duplicate declaration of signal: \'GRANT_ALIGN_BULK\'\n GRANT_ALIGN_BULK = 1\'b0,\n ^~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:24: ... Location of original declaration\n output GRANT_ALIGN_BULK,\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:38: Duplicate declaration of signal: \'INTERNAL_DATA_MUX\'\n INTERNAL_DATA_MUX = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:30: ... Location of original declaration\n output INTERNAL_DATA_MUX,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:39: Duplicate declaration of signal: \'INTERNAL_DATA_MUX_INVERT\'\n INTERNAL_DATA_MUX_INVERT = 1\'b0;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:31: ... Location of original declaration\n output INTERNAL_DATA_MUX_INVERT,\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:708: Pin not found: \'PIN_TYPE\'\n defparam driver.PIN_TYPE = 6\'b101001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:709: Pin not found: \'IO_STANDARD\'\n defparam driver.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:426: Pin not found: \'PIN_TYPE\'\n defparam DM_00.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:427: Pin not found: \'IO_STANDARD\'\n defparam DM_00.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:439: Pin not found: \'PIN_TYPE\'\n defparam DM_01.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:440: Pin not found: \'IO_STANDARD\'\n defparam DM_01.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:452: Pin not found: \'PIN_TYPE\'\n defparam DQ_00.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:453: Pin not found: \'IO_STANDARD\'\n defparam DQ_00.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:465: Pin not found: \'PIN_TYPE\'\n defparam DQ_01.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:466: Pin not found: \'IO_STANDARD\'\n defparam DQ_01.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:478: Pin not found: \'PIN_TYPE\'\n defparam DQ_02.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:479: Pin not found: \'IO_STANDARD\'\n defparam DQ_02.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:491: Pin not found: \'PIN_TYPE\'\n defparam DQ_03.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:492: Pin not found: \'IO_STANDARD\'\n defparam DQ_03.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:504: Pin not found: \'PIN_TYPE\'\n defparam DQ_04.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:505: Pin not found: \'IO_STANDARD\'\n defparam DQ_04.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:517: Pin not found: \'PIN_TYPE\'\n defparam DQ_05.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:518: Pin not found: \'IO_STANDARD\'\n defparam DQ_05.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:530: Pin not found: \'PIN_TYPE\'\n defparam DQ_06.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:531: Pin not found: \'IO_STANDARD\'\n defparam DQ_06.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:543: Pin not found: \'PIN_TYPE\'\n defparam DQ_07.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:544: Pin not found: \'IO_STANDARD\'\n defparam DQ_07.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:556: Pin not found: \'PIN_TYPE\'\n defparam DQ_08.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:557: Pin not found: \'IO_STANDARD\'\n defparam DQ_08.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:569: Pin not found: \'PIN_TYPE\'\n defparam DQ_09.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:570: Pin not found: \'IO_STANDARD\'\n defparam DQ_09.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:582: Pin not found: \'PIN_TYPE\'\n defparam DQ_10.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:583: Pin not found: \'IO_STANDARD\'\n defparam DQ_10.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:595: Pin not found: \'PIN_TYPE\'\n defparam DQ_11.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:596: Pin not found: \'IO_STANDARD\'\n defparam DQ_11.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:608: Pin not found: \'PIN_TYPE\'\n defparam DQ_12.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:609: Pin not found: \'IO_STANDARD\'\n defparam DQ_12.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:621: Pin not found: \'PIN_TYPE\'\n defparam DQ_13.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:622: Pin not found: \'IO_STANDARD\'\n defparam DQ_13.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:634: Pin not found: \'PIN_TYPE\'\n defparam DQ_14.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:635: Pin not found: \'IO_STANDARD\'\n defparam DQ_14.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:647: Pin not found: \'PIN_TYPE\'\n defparam DQ_15.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:648: Pin not found: \'IO_STANDARD\'\n defparam DQ_15.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:667: Pin not found: \'PIN_TYPE\'\n defparam CLK_POS.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:668: Pin not found: \'IO_STANDARD\'\n defparam CLK_POS.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:680: Pin not found: \'PIN_TYPE\'\n defparam CLK_NEG.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:681: Pin not found: \'IO_STANDARD\'\n defparam CLK_NEG.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: Exiting due to 48 error(s), 1 warning(s)\n' | 302,588 | module | module state2(input CLK,
input REFRESH_STROBE,
input [25:0] ADDRESS_RAND,
input port_WE_RAND,
input port_REQUEST_ACCESS_RAND,
output GRANT_ACCESS_RAND,
input [3:0] WE_ARRAY_RAND,
input [25:0] port_ADDRESS_BULK,
input port_WE_BULK,
input port_REQUEST_ACCESS_BULK,
output GRANT_ACCESS_BULK,
input port_REQUEST_ALIGN_BULK,
output GRANT_ALIGN_BULK,
input [3:0] port_WE_ARRAY_BULK,
output reg [13:0] ADDRESS_REG,
output reg [2:0] BANK_REG,
output [2:0] COMMAND_REG,
output INTERNAL_DATA_MUX,
output INTERNAL_DATA_MUX_INVERT,
output [3:0] INTERNAL_COMMAND_LATCHED,
output reg [3:0] INTERNAL_WE_ARRAY);
reg [2:0] COMMAND_REG = `NOOP;
reg GRANT_ACCESS_RAND = 1'b0,
GRANT_ACCESS_BULK = 1'b0,
GRANT_ALIGN_BULK = 1'b0,
INTERNAL_DATA_MUX = 1'b0,
INTERNAL_DATA_MUX_INVERT = 1'b0;
reg change_possible_n = 1'b0,
state_is_readwrite = 1'b0,
refresh_strobe_ack = 1'b0,
state_is_write,
SOME_PAGE_ACTIVE = 1'b0,
second_stroke = 1'b1,
refresh_time = 1'b0,
REQUEST_ALIGN_BULK_dly = 1'b0,
REQUEST_ACCESS_RAND = 1'b0,
REQUEST_ACCESS_BULK = 1'b0,
WE_RAND = 1'b0,
WE_BULK = 1'b0,
REQUEST_ALIGN_BULK = 1'b0,
correct_page_rand = 1'b0,
correct_page_algn = 1'b0,
do_extra_pass = 1'b0;
reg [2:0] command_reg2 = `NOOP,
actv_timeout = 3'h7;
reg [3:0] counter = 4'h0, WE_ARRAY_BULK;
reg [16:0] page_current;
reg [25:0] ADDRESS_BULK;
wire issue_com,
correct_page_rand_w,
correct_page_algn_w,
correct_page_rdy,
change_possible_w_n, write_match,
timeout_norm_comp_n,
timeout_dlay_comp_n,
want_PRCH_delayable,
issue_enable_override,
issue_enable_on_page;
wire [2:0] bank_request_live_bulk,
bank_request_live_rand;
wire [2:0] command, command_wr;
wire [3:0] we_array;
wire [13:0] row_request_live_bulk,
row_request_live_rand;
wire [13:0] address;
wire [16:0] page;
wire [25:0] address_in;
reg [2:0] command_non_wr;
assign INTERNAL_COMMAND_LATCHED = {second_stroke,command_reg2};
assign row_request_live_rand = ADDRESS_RAND[25:12];
assign bank_request_live_rand = ADDRESS_RAND[11:9];
assign correct_page_rand_w = ({port_REQUEST_ACCESS_RAND,
port_REQUEST_ALIGN_BULK,
refresh_time,
SOME_PAGE_ACTIVE,
row_request_live_rand,
bank_request_live_rand}
== {4'b1001,
page_current});
assign row_request_live_bulk = ADDRESS_BULK[25:12];
assign bank_request_live_bulk = ADDRESS_BULK[11:9];
assign correct_page_algn_w = ({port_REQUEST_ALIGN_BULK,
refresh_time,
SOME_PAGE_ACTIVE,
row_request_live_bulk,
bank_request_live_bulk}
== {3'b101,
page_current});
assign correct_page_rdy = correct_page_rand || correct_page_algn;
assign write_match = REQUEST_ACCESS_BULK ? WE_BULK :
(REQUEST_ACCESS_RAND && WE_RAND);
assign issue_com = (((correct_page_rand && port_REQUEST_ACCESS_RAND) ||
(correct_page_algn && REQUEST_ACCESS_BULK))
&& issue_enable_on_page) ||
issue_enable_override;
assign issue_enable_on_page = second_stroke && state_is_readwrite &&
(state_is_write ?
write_match :
(!write_match));
assign issue_enable_override = second_stroke && (!change_possible_n) &&
((REQUEST_ACCESS_RAND &&
(!(REQUEST_ACCESS_BULK ||
REQUEST_ALIGN_BULK))) ||
REQUEST_ACCESS_BULK ||
refresh_time ||
(REQUEST_ALIGN_BULK_dly &&
(!GRANT_ALIGN_BULK)));
always @(SOME_PAGE_ACTIVE or refresh_time or actv_timeout[2])
case ({SOME_PAGE_ACTIVE,refresh_time,actv_timeout[2]})
3'b101: command_non_wr <= `PRCH;
3'b111: command_non_wr <= `PRCH;
3'b010: command_non_wr <= `ARSR;
3'b011: command_non_wr <= `ARSR;
3'b000: command_non_wr <= `ACTV;
3'b001: command_non_wr <= `ACTV;
default: command_non_wr <= `NOOP;
endcase
assign want_PRCH_delayable = SOME_PAGE_ACTIVE && state_is_write;
assign command_wr = write_match ? `WRTE : `READ;
assign command = correct_page_rdy ? command_wr : command_non_wr;
assign address_in = REQUEST_ALIGN_BULK ? ADDRESS_BULK : ADDRESS_RAND;
assign address = (SOME_PAGE_ACTIVE &&
(! correct_page_rdy)) ?
14'h0400 :
(correct_page_rdy ?
{4'h0,address_in[8:0],1'b0} :
{address_in[25:12]});
assign page = correct_page_rdy ?
page_current :
address_in[25:9];
assign timeout_norm_comp_n = !((counter == 4'he) || (counter == 4'hd) ||
(counter == 4'hf) || (counter == 4'h0));
assign timeout_dlay_comp_n = !((counter == 4'he) || (counter == 4'hf) ||
(counter == 4'h0));
assign change_possible_w_n = ~second_stroke ? 1 :
correct_page_rdy ? timeout_norm_comp_n :
do_extra_pass ? 1 : (want_PRCH_delayable ?
timeout_dlay_comp_n : timeout_norm_comp_n);
assign we_array = REQUEST_ACCESS_BULK ? WE_ARRAY_BULK : WE_ARRAY_RAND;
always @(posedge CLK)
begin
REQUEST_ACCESS_RAND <= port_REQUEST_ACCESS_RAND;
REQUEST_ACCESS_BULK <= port_REQUEST_ACCESS_BULK;
REQUEST_ALIGN_BULK <= port_REQUEST_ALIGN_BULK;
WE_BULK <= port_WE_BULK;
WE_RAND <= port_WE_RAND;
ADDRESS_BULK <= port_ADDRESS_BULK;
WE_ARRAY_BULK <= port_WE_ARRAY_BULK;
correct_page_rand <= correct_page_rand_w;
correct_page_algn <= correct_page_algn_w;
REQUEST_ALIGN_BULK_dly <= REQUEST_ALIGN_BULK;
refresh_time <= refresh_strobe_ack ^ REFRESH_STROBE;
if ((!second_stroke) && (command_reg2 == `ACTV))
actv_timeout <= 3'h0;
else
if (!actv_timeout[2])
actv_timeout <= actv_timeout +1;
if (issue_com)
begin
COMMAND_REG <= command;
command_reg2 <= command;
end
else
begin
COMMAND_REG <= `NOOP;
command_reg2 <= `NOOP;
end
ADDRESS_REG <= address;
if (!(SOME_PAGE_ACTIVE &&
(! correct_page_rdy)))
BANK_REG <= address_in[11:9];
second_stroke <= ~issue_com;
if (!second_stroke)
begin
if (command_reg2 == `ACTV)
begin
SOME_PAGE_ACTIVE <= 1;
page_current <= address_in[25:9];
end
if (command_reg2 == `PRCH)
SOME_PAGE_ACTIVE <= 0;
if (command_reg2 == `WRTE)
state_is_write <= 1;
else if (command_reg2 != `NOOP)
state_is_write <= 0;
if (command_reg2 == `ARSR)
begin
refresh_strobe_ack <= REFRESH_STROBE;
do_extra_pass <= 1'b1;
end
case (command_reg2)
`ARSR: counter <= 4'h3;
`ACTV: counter <= 4'hc;
`WRTE: counter <= 4'ha;
`NOOP: counter <= 4'he;
default: counter <= 4'hb;
endcase
end
else
begin
counter <= counter + change_possible_n;
if (counter == 4'h0)
do_extra_pass <= 0;
end
if (issue_com)
begin
change_possible_n <= 1;
state_is_readwrite <= correct_page_rdy;
GRANT_ACCESS_RAND <= correct_page_rand;
GRANT_ACCESS_BULK <= correct_page_algn && REQUEST_ACCESS_BULK;
INTERNAL_WE_ARRAY <= we_array;
end
if (!issue_com)
begin
change_possible_n <= change_possible_w_n;
GRANT_ACCESS_RAND <= 0;
GRANT_ACCESS_BULK <= 0;
end
if (!change_possible_w_n)
GRANT_ALIGN_BULK <= correct_page_algn;
INTERNAL_DATA_MUX <= port_REQUEST_ALIGN_BULK;
if (issue_com)
INTERNAL_DATA_MUX_INVERT <= (port_REQUEST_ALIGN_BULK ^
REQUEST_ALIGN_BULK);
else
INTERNAL_DATA_MUX_INVERT <= 0;
end
endmodule | module state2(input CLK,
input REFRESH_STROBE,
input [25:0] ADDRESS_RAND,
input port_WE_RAND,
input port_REQUEST_ACCESS_RAND,
output GRANT_ACCESS_RAND,
input [3:0] WE_ARRAY_RAND,
input [25:0] port_ADDRESS_BULK,
input port_WE_BULK,
input port_REQUEST_ACCESS_BULK,
output GRANT_ACCESS_BULK,
input port_REQUEST_ALIGN_BULK,
output GRANT_ALIGN_BULK,
input [3:0] port_WE_ARRAY_BULK,
output reg [13:0] ADDRESS_REG,
output reg [2:0] BANK_REG,
output [2:0] COMMAND_REG,
output INTERNAL_DATA_MUX,
output INTERNAL_DATA_MUX_INVERT,
output [3:0] INTERNAL_COMMAND_LATCHED,
output reg [3:0] INTERNAL_WE_ARRAY); |
reg [2:0] COMMAND_REG = `NOOP;
reg GRANT_ACCESS_RAND = 1'b0,
GRANT_ACCESS_BULK = 1'b0,
GRANT_ALIGN_BULK = 1'b0,
INTERNAL_DATA_MUX = 1'b0,
INTERNAL_DATA_MUX_INVERT = 1'b0;
reg change_possible_n = 1'b0,
state_is_readwrite = 1'b0,
refresh_strobe_ack = 1'b0,
state_is_write,
SOME_PAGE_ACTIVE = 1'b0,
second_stroke = 1'b1,
refresh_time = 1'b0,
REQUEST_ALIGN_BULK_dly = 1'b0,
REQUEST_ACCESS_RAND = 1'b0,
REQUEST_ACCESS_BULK = 1'b0,
WE_RAND = 1'b0,
WE_BULK = 1'b0,
REQUEST_ALIGN_BULK = 1'b0,
correct_page_rand = 1'b0,
correct_page_algn = 1'b0,
do_extra_pass = 1'b0;
reg [2:0] command_reg2 = `NOOP,
actv_timeout = 3'h7;
reg [3:0] counter = 4'h0, WE_ARRAY_BULK;
reg [16:0] page_current;
reg [25:0] ADDRESS_BULK;
wire issue_com,
correct_page_rand_w,
correct_page_algn_w,
correct_page_rdy,
change_possible_w_n, write_match,
timeout_norm_comp_n,
timeout_dlay_comp_n,
want_PRCH_delayable,
issue_enable_override,
issue_enable_on_page;
wire [2:0] bank_request_live_bulk,
bank_request_live_rand;
wire [2:0] command, command_wr;
wire [3:0] we_array;
wire [13:0] row_request_live_bulk,
row_request_live_rand;
wire [13:0] address;
wire [16:0] page;
wire [25:0] address_in;
reg [2:0] command_non_wr;
assign INTERNAL_COMMAND_LATCHED = {second_stroke,command_reg2};
assign row_request_live_rand = ADDRESS_RAND[25:12];
assign bank_request_live_rand = ADDRESS_RAND[11:9];
assign correct_page_rand_w = ({port_REQUEST_ACCESS_RAND,
port_REQUEST_ALIGN_BULK,
refresh_time,
SOME_PAGE_ACTIVE,
row_request_live_rand,
bank_request_live_rand}
== {4'b1001,
page_current});
assign row_request_live_bulk = ADDRESS_BULK[25:12];
assign bank_request_live_bulk = ADDRESS_BULK[11:9];
assign correct_page_algn_w = ({port_REQUEST_ALIGN_BULK,
refresh_time,
SOME_PAGE_ACTIVE,
row_request_live_bulk,
bank_request_live_bulk}
== {3'b101,
page_current});
assign correct_page_rdy = correct_page_rand || correct_page_algn;
assign write_match = REQUEST_ACCESS_BULK ? WE_BULK :
(REQUEST_ACCESS_RAND && WE_RAND);
assign issue_com = (((correct_page_rand && port_REQUEST_ACCESS_RAND) ||
(correct_page_algn && REQUEST_ACCESS_BULK))
&& issue_enable_on_page) ||
issue_enable_override;
assign issue_enable_on_page = second_stroke && state_is_readwrite &&
(state_is_write ?
write_match :
(!write_match));
assign issue_enable_override = second_stroke && (!change_possible_n) &&
((REQUEST_ACCESS_RAND &&
(!(REQUEST_ACCESS_BULK ||
REQUEST_ALIGN_BULK))) ||
REQUEST_ACCESS_BULK ||
refresh_time ||
(REQUEST_ALIGN_BULK_dly &&
(!GRANT_ALIGN_BULK)));
always @(SOME_PAGE_ACTIVE or refresh_time or actv_timeout[2])
case ({SOME_PAGE_ACTIVE,refresh_time,actv_timeout[2]})
3'b101: command_non_wr <= `PRCH;
3'b111: command_non_wr <= `PRCH;
3'b010: command_non_wr <= `ARSR;
3'b011: command_non_wr <= `ARSR;
3'b000: command_non_wr <= `ACTV;
3'b001: command_non_wr <= `ACTV;
default: command_non_wr <= `NOOP;
endcase
assign want_PRCH_delayable = SOME_PAGE_ACTIVE && state_is_write;
assign command_wr = write_match ? `WRTE : `READ;
assign command = correct_page_rdy ? command_wr : command_non_wr;
assign address_in = REQUEST_ALIGN_BULK ? ADDRESS_BULK : ADDRESS_RAND;
assign address = (SOME_PAGE_ACTIVE &&
(! correct_page_rdy)) ?
14'h0400 :
(correct_page_rdy ?
{4'h0,address_in[8:0],1'b0} :
{address_in[25:12]});
assign page = correct_page_rdy ?
page_current :
address_in[25:9];
assign timeout_norm_comp_n = !((counter == 4'he) || (counter == 4'hd) ||
(counter == 4'hf) || (counter == 4'h0));
assign timeout_dlay_comp_n = !((counter == 4'he) || (counter == 4'hf) ||
(counter == 4'h0));
assign change_possible_w_n = ~second_stroke ? 1 :
correct_page_rdy ? timeout_norm_comp_n :
do_extra_pass ? 1 : (want_PRCH_delayable ?
timeout_dlay_comp_n : timeout_norm_comp_n);
assign we_array = REQUEST_ACCESS_BULK ? WE_ARRAY_BULK : WE_ARRAY_RAND;
always @(posedge CLK)
begin
REQUEST_ACCESS_RAND <= port_REQUEST_ACCESS_RAND;
REQUEST_ACCESS_BULK <= port_REQUEST_ACCESS_BULK;
REQUEST_ALIGN_BULK <= port_REQUEST_ALIGN_BULK;
WE_BULK <= port_WE_BULK;
WE_RAND <= port_WE_RAND;
ADDRESS_BULK <= port_ADDRESS_BULK;
WE_ARRAY_BULK <= port_WE_ARRAY_BULK;
correct_page_rand <= correct_page_rand_w;
correct_page_algn <= correct_page_algn_w;
REQUEST_ALIGN_BULK_dly <= REQUEST_ALIGN_BULK;
refresh_time <= refresh_strobe_ack ^ REFRESH_STROBE;
if ((!second_stroke) && (command_reg2 == `ACTV))
actv_timeout <= 3'h0;
else
if (!actv_timeout[2])
actv_timeout <= actv_timeout +1;
if (issue_com)
begin
COMMAND_REG <= command;
command_reg2 <= command;
end
else
begin
COMMAND_REG <= `NOOP;
command_reg2 <= `NOOP;
end
ADDRESS_REG <= address;
if (!(SOME_PAGE_ACTIVE &&
(! correct_page_rdy)))
BANK_REG <= address_in[11:9];
second_stroke <= ~issue_com;
if (!second_stroke)
begin
if (command_reg2 == `ACTV)
begin
SOME_PAGE_ACTIVE <= 1;
page_current <= address_in[25:9];
end
if (command_reg2 == `PRCH)
SOME_PAGE_ACTIVE <= 0;
if (command_reg2 == `WRTE)
state_is_write <= 1;
else if (command_reg2 != `NOOP)
state_is_write <= 0;
if (command_reg2 == `ARSR)
begin
refresh_strobe_ack <= REFRESH_STROBE;
do_extra_pass <= 1'b1;
end
case (command_reg2)
`ARSR: counter <= 4'h3;
`ACTV: counter <= 4'hc;
`WRTE: counter <= 4'ha;
`NOOP: counter <= 4'he;
default: counter <= 4'hb;
endcase
end
else
begin
counter <= counter + change_possible_n;
if (counter == 4'h0)
do_extra_pass <= 0;
end
if (issue_com)
begin
change_possible_n <= 1;
state_is_readwrite <= correct_page_rdy;
GRANT_ACCESS_RAND <= correct_page_rand;
GRANT_ACCESS_BULK <= correct_page_algn && REQUEST_ACCESS_BULK;
INTERNAL_WE_ARRAY <= we_array;
end
if (!issue_com)
begin
change_possible_n <= change_possible_w_n;
GRANT_ACCESS_RAND <= 0;
GRANT_ACCESS_BULK <= 0;
end
if (!change_possible_w_n)
GRANT_ALIGN_BULK <= correct_page_algn;
INTERNAL_DATA_MUX <= port_REQUEST_ALIGN_BULK;
if (issue_com)
INTERNAL_DATA_MUX_INVERT <= (port_REQUEST_ALIGN_BULK ^
REQUEST_ALIGN_BULK);
else
INTERNAL_DATA_MUX_INVERT <= 0;
end
endmodule | 1 |
138,613 | data/full_repos/permissive/85002992/mcu/state2.v | 85,002,992 | state2.v | v | 825 | 76 | [] | [] | [] | null | line:35: before: "," | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/85002992/mcu/state2.v:296: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'state2\'\nmodule state2(input CLK,\n ^~~~~~\n : ... Top module \'outputs\'\nmodule outputs(input CLK_n,\n ^~~~~~~\n : ... Top module \'clock_driver\'\nmodule clock_driver(input CLK_n,\n ^~~~~~~~~~~~\n : ... Top module \'SB_IOeg\'\nmodule SB_IOeg(inout PACKAGE_PIN,\n ^~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:34: Duplicate declaration of signal: \'COMMAND_REG\'\n reg [2:0] COMMAND_REG = 3\'b111 ;\n ^~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:29: ... Location of original declaration\n output [2:0] COMMAND_REG,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:35: Duplicate declaration of signal: \'GRANT_ACCESS_RAND\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg GRANT_ACCESS_RAND = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:16: ... Location of original declaration\n output GRANT_ACCESS_RAND,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:36: Duplicate declaration of signal: \'GRANT_ACCESS_BULK\'\n GRANT_ACCESS_BULK = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:22: ... Location of original declaration\n output GRANT_ACCESS_BULK,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:37: Duplicate declaration of signal: \'GRANT_ALIGN_BULK\'\n GRANT_ALIGN_BULK = 1\'b0,\n ^~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:24: ... Location of original declaration\n output GRANT_ALIGN_BULK,\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:38: Duplicate declaration of signal: \'INTERNAL_DATA_MUX\'\n INTERNAL_DATA_MUX = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:30: ... Location of original declaration\n output INTERNAL_DATA_MUX,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:39: Duplicate declaration of signal: \'INTERNAL_DATA_MUX_INVERT\'\n INTERNAL_DATA_MUX_INVERT = 1\'b0;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:31: ... Location of original declaration\n output INTERNAL_DATA_MUX_INVERT,\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:708: Pin not found: \'PIN_TYPE\'\n defparam driver.PIN_TYPE = 6\'b101001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:709: Pin not found: \'IO_STANDARD\'\n defparam driver.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:426: Pin not found: \'PIN_TYPE\'\n defparam DM_00.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:427: Pin not found: \'IO_STANDARD\'\n defparam DM_00.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:439: Pin not found: \'PIN_TYPE\'\n defparam DM_01.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:440: Pin not found: \'IO_STANDARD\'\n defparam DM_01.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:452: Pin not found: \'PIN_TYPE\'\n defparam DQ_00.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:453: Pin not found: \'IO_STANDARD\'\n defparam DQ_00.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:465: Pin not found: \'PIN_TYPE\'\n defparam DQ_01.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:466: Pin not found: \'IO_STANDARD\'\n defparam DQ_01.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:478: Pin not found: \'PIN_TYPE\'\n defparam DQ_02.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:479: Pin not found: \'IO_STANDARD\'\n defparam DQ_02.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:491: Pin not found: \'PIN_TYPE\'\n defparam DQ_03.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:492: Pin not found: \'IO_STANDARD\'\n defparam DQ_03.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:504: Pin not found: \'PIN_TYPE\'\n defparam DQ_04.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:505: Pin not found: \'IO_STANDARD\'\n defparam DQ_04.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:517: Pin not found: \'PIN_TYPE\'\n defparam DQ_05.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:518: Pin not found: \'IO_STANDARD\'\n defparam DQ_05.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:530: Pin not found: \'PIN_TYPE\'\n defparam DQ_06.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:531: Pin not found: \'IO_STANDARD\'\n defparam DQ_06.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:543: Pin not found: \'PIN_TYPE\'\n defparam DQ_07.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:544: Pin not found: \'IO_STANDARD\'\n defparam DQ_07.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:556: Pin not found: \'PIN_TYPE\'\n defparam DQ_08.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:557: Pin not found: \'IO_STANDARD\'\n defparam DQ_08.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:569: Pin not found: \'PIN_TYPE\'\n defparam DQ_09.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:570: Pin not found: \'IO_STANDARD\'\n defparam DQ_09.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:582: Pin not found: \'PIN_TYPE\'\n defparam DQ_10.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:583: Pin not found: \'IO_STANDARD\'\n defparam DQ_10.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:595: Pin not found: \'PIN_TYPE\'\n defparam DQ_11.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:596: Pin not found: \'IO_STANDARD\'\n defparam DQ_11.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:608: Pin not found: \'PIN_TYPE\'\n defparam DQ_12.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:609: Pin not found: \'IO_STANDARD\'\n defparam DQ_12.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:621: Pin not found: \'PIN_TYPE\'\n defparam DQ_13.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:622: Pin not found: \'IO_STANDARD\'\n defparam DQ_13.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:634: Pin not found: \'PIN_TYPE\'\n defparam DQ_14.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:635: Pin not found: \'IO_STANDARD\'\n defparam DQ_14.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:647: Pin not found: \'PIN_TYPE\'\n defparam DQ_15.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:648: Pin not found: \'IO_STANDARD\'\n defparam DQ_15.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:667: Pin not found: \'PIN_TYPE\'\n defparam CLK_POS.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:668: Pin not found: \'IO_STANDARD\'\n defparam CLK_POS.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:680: Pin not found: \'PIN_TYPE\'\n defparam CLK_NEG.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:681: Pin not found: \'IO_STANDARD\'\n defparam CLK_NEG.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: Exiting due to 48 error(s), 1 warning(s)\n' | 302,588 | module | module outputs(input CLK_n,
input CLK_dn,
input [3:0] COMMAND_LATCHED,
input [3:0] WE_ARRAY,
input [31:0] port_DATA_W,
inout [15:0] DQ,
inout UDQS,
inout LDQS,
output [31:0] DATA_R,
output UDM,
output LDM);
reg [31:0] data_gapholder, dq_predriver,
DATA_W;
reg [3:0] we_gapholder;
reg [1:0] dm_predriver, dqs_predriver,
active = 1'b0, we_longholder;
reg dqs_z_prectrl = 1'b0, dqs_z_ctrl = 1'b0,
dqdm_z_prectrl = 1'b0,
high_bits = 1'b0;
reg [15:0] dq_data_r = 16'd0;
wire [31:0] dq_data_w;
wire did_issue_write;
assign did_issue_write = COMMAND_LATCHED == {1'b0,`WRTE};
ddr_data_pins pins(.CLK_n(CLK_n),
.CLK_dn(CLK_dn),
.dq_predriver(dq_predriver),
.dm_predriver(dm_predriver),
.dqs_predriver(dqs_predriver),
.dqs_z_ctrl(dqs_z_ctrl),
.dqdm_z_prectrl(dqdm_z_prectrl),
.dq_data_r(dq_data_w),
.DQ(DQ),
.UDQS(UDQS),
.LDQS(LDQS),
.UDM(UDM),
.LDM(LDM));
always @(posedge CLK_n)
begin
DATA_W <= port_DATA_W;
we_gapholder <= ~WE_ARRAY;
we_longholder <= we_gapholder[1:0];
high_bits <= did_issue_write;
active <= {active[0],did_issue_write};
if ({did_issue_write,active} == 3'b000)
dqs_z_prectrl <= 0;
else
dqs_z_prectrl <= 1;
end
assign DATA_R = {dq_data_r,dq_data_w[15:0]};
always @(negedge CLK_n)
begin
dq_data_r <= dq_data_w[31:16];
end
always @(negedge CLK_dn)
begin
dqs_z_ctrl <= dqs_z_prectrl;
data_gapholder <= DATA_W;
dq_predriver[15:0] <= data_gapholder[15:0];
if (high_bits)
dm_predriver <= we_gapholder[3:2];
else
dm_predriver <= we_longholder;
if (active == 2'b00)
begin
dqdm_z_prectrl <= 0;
dqs_predriver <= 2'h0;
end
else
begin
dqdm_z_prectrl <= 1;
dqs_predriver <= 2'h2;
end
end
always @(posedge CLK_dn)
dq_predriver[31:16] <= data_gapholder[31:16];
endmodule | module outputs(input CLK_n,
input CLK_dn,
input [3:0] COMMAND_LATCHED,
input [3:0] WE_ARRAY,
input [31:0] port_DATA_W,
inout [15:0] DQ,
inout UDQS,
inout LDQS,
output [31:0] DATA_R,
output UDM,
output LDM); |
reg [31:0] data_gapholder, dq_predriver,
DATA_W;
reg [3:0] we_gapholder;
reg [1:0] dm_predriver, dqs_predriver,
active = 1'b0, we_longholder;
reg dqs_z_prectrl = 1'b0, dqs_z_ctrl = 1'b0,
dqdm_z_prectrl = 1'b0,
high_bits = 1'b0;
reg [15:0] dq_data_r = 16'd0;
wire [31:0] dq_data_w;
wire did_issue_write;
assign did_issue_write = COMMAND_LATCHED == {1'b0,`WRTE};
ddr_data_pins pins(.CLK_n(CLK_n),
.CLK_dn(CLK_dn),
.dq_predriver(dq_predriver),
.dm_predriver(dm_predriver),
.dqs_predriver(dqs_predriver),
.dqs_z_ctrl(dqs_z_ctrl),
.dqdm_z_prectrl(dqdm_z_prectrl),
.dq_data_r(dq_data_w),
.DQ(DQ),
.UDQS(UDQS),
.LDQS(LDQS),
.UDM(UDM),
.LDM(LDM));
always @(posedge CLK_n)
begin
DATA_W <= port_DATA_W;
we_gapholder <= ~WE_ARRAY;
we_longholder <= we_gapholder[1:0];
high_bits <= did_issue_write;
active <= {active[0],did_issue_write};
if ({did_issue_write,active} == 3'b000)
dqs_z_prectrl <= 0;
else
dqs_z_prectrl <= 1;
end
assign DATA_R = {dq_data_r,dq_data_w[15:0]};
always @(negedge CLK_n)
begin
dq_data_r <= dq_data_w[31:16];
end
always @(negedge CLK_dn)
begin
dqs_z_ctrl <= dqs_z_prectrl;
data_gapholder <= DATA_W;
dq_predriver[15:0] <= data_gapholder[15:0];
if (high_bits)
dm_predriver <= we_gapholder[3:2];
else
dm_predriver <= we_longholder;
if (active == 2'b00)
begin
dqdm_z_prectrl <= 0;
dqs_predriver <= 2'h0;
end
else
begin
dqdm_z_prectrl <= 1;
dqs_predriver <= 2'h2;
end
end
always @(posedge CLK_dn)
dq_predriver[31:16] <= data_gapholder[31:16];
endmodule | 1 |
138,614 | data/full_repos/permissive/85002992/mcu/state2.v | 85,002,992 | state2.v | v | 825 | 76 | [] | [] | [] | null | line:35: before: "," | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/85002992/mcu/state2.v:296: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'state2\'\nmodule state2(input CLK,\n ^~~~~~\n : ... Top module \'outputs\'\nmodule outputs(input CLK_n,\n ^~~~~~~\n : ... Top module \'clock_driver\'\nmodule clock_driver(input CLK_n,\n ^~~~~~~~~~~~\n : ... Top module \'SB_IOeg\'\nmodule SB_IOeg(inout PACKAGE_PIN,\n ^~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:34: Duplicate declaration of signal: \'COMMAND_REG\'\n reg [2:0] COMMAND_REG = 3\'b111 ;\n ^~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:29: ... Location of original declaration\n output [2:0] COMMAND_REG,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:35: Duplicate declaration of signal: \'GRANT_ACCESS_RAND\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg GRANT_ACCESS_RAND = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:16: ... Location of original declaration\n output GRANT_ACCESS_RAND,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:36: Duplicate declaration of signal: \'GRANT_ACCESS_BULK\'\n GRANT_ACCESS_BULK = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:22: ... Location of original declaration\n output GRANT_ACCESS_BULK,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:37: Duplicate declaration of signal: \'GRANT_ALIGN_BULK\'\n GRANT_ALIGN_BULK = 1\'b0,\n ^~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:24: ... Location of original declaration\n output GRANT_ALIGN_BULK,\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:38: Duplicate declaration of signal: \'INTERNAL_DATA_MUX\'\n INTERNAL_DATA_MUX = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:30: ... Location of original declaration\n output INTERNAL_DATA_MUX,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:39: Duplicate declaration of signal: \'INTERNAL_DATA_MUX_INVERT\'\n INTERNAL_DATA_MUX_INVERT = 1\'b0;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:31: ... Location of original declaration\n output INTERNAL_DATA_MUX_INVERT,\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:708: Pin not found: \'PIN_TYPE\'\n defparam driver.PIN_TYPE = 6\'b101001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:709: Pin not found: \'IO_STANDARD\'\n defparam driver.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:426: Pin not found: \'PIN_TYPE\'\n defparam DM_00.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:427: Pin not found: \'IO_STANDARD\'\n defparam DM_00.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:439: Pin not found: \'PIN_TYPE\'\n defparam DM_01.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:440: Pin not found: \'IO_STANDARD\'\n defparam DM_01.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:452: Pin not found: \'PIN_TYPE\'\n defparam DQ_00.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:453: Pin not found: \'IO_STANDARD\'\n defparam DQ_00.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:465: Pin not found: \'PIN_TYPE\'\n defparam DQ_01.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:466: Pin not found: \'IO_STANDARD\'\n defparam DQ_01.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:478: Pin not found: \'PIN_TYPE\'\n defparam DQ_02.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:479: Pin not found: \'IO_STANDARD\'\n defparam DQ_02.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:491: Pin not found: \'PIN_TYPE\'\n defparam DQ_03.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:492: Pin not found: \'IO_STANDARD\'\n defparam DQ_03.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:504: Pin not found: \'PIN_TYPE\'\n defparam DQ_04.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:505: Pin not found: \'IO_STANDARD\'\n defparam DQ_04.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:517: Pin not found: \'PIN_TYPE\'\n defparam DQ_05.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:518: Pin not found: \'IO_STANDARD\'\n defparam DQ_05.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:530: Pin not found: \'PIN_TYPE\'\n defparam DQ_06.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:531: Pin not found: \'IO_STANDARD\'\n defparam DQ_06.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:543: Pin not found: \'PIN_TYPE\'\n defparam DQ_07.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:544: Pin not found: \'IO_STANDARD\'\n defparam DQ_07.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:556: Pin not found: \'PIN_TYPE\'\n defparam DQ_08.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:557: Pin not found: \'IO_STANDARD\'\n defparam DQ_08.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:569: Pin not found: \'PIN_TYPE\'\n defparam DQ_09.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:570: Pin not found: \'IO_STANDARD\'\n defparam DQ_09.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:582: Pin not found: \'PIN_TYPE\'\n defparam DQ_10.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:583: Pin not found: \'IO_STANDARD\'\n defparam DQ_10.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:595: Pin not found: \'PIN_TYPE\'\n defparam DQ_11.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:596: Pin not found: \'IO_STANDARD\'\n defparam DQ_11.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:608: Pin not found: \'PIN_TYPE\'\n defparam DQ_12.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:609: Pin not found: \'IO_STANDARD\'\n defparam DQ_12.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:621: Pin not found: \'PIN_TYPE\'\n defparam DQ_13.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:622: Pin not found: \'IO_STANDARD\'\n defparam DQ_13.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:634: Pin not found: \'PIN_TYPE\'\n defparam DQ_14.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:635: Pin not found: \'IO_STANDARD\'\n defparam DQ_14.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:647: Pin not found: \'PIN_TYPE\'\n defparam DQ_15.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:648: Pin not found: \'IO_STANDARD\'\n defparam DQ_15.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:667: Pin not found: \'PIN_TYPE\'\n defparam CLK_POS.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:668: Pin not found: \'IO_STANDARD\'\n defparam CLK_POS.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:680: Pin not found: \'PIN_TYPE\'\n defparam CLK_NEG.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:681: Pin not found: \'IO_STANDARD\'\n defparam CLK_NEG.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: Exiting due to 48 error(s), 1 warning(s)\n' | 302,588 | module | module ddr_data_pins(input CLK_n,
input CLK_dn,
input [31:0] dq_predriver,
input [1:0] dm_predriver,
input [1:0] dqs_predriver,
input dqs_z_ctrl,
input dqdm_z_prectrl,
output [31:0] dq_data_r,
inout [15:0] DQ,
inout UDQS,
inout LDQS,
output UDM,
output LDM);
dqs_driver DQS_00(.PACKAGE_PIN(UDQS),
.PATCHTHROUGH_INPUT_CLK(),
.PATCHTHROUGH_OUTPUT_CLK(),
.LATCH_CLK(CLK_dn),
.OUTPUT_CLK(! CLK_n),
.OUTPUT_ENABLE(dqs_z_ctrl),
.D_OUT_0(dqs_predriver[1]),
.D_OUT_1(dqs_predriver[0]));
dqs_driver DQS_01(.PACKAGE_PIN(LDQS),
.PATCHTHROUGH_INPUT_CLK(),
.PATCHTHROUGH_OUTPUT_CLK(),
.LATCH_CLK(CLK_dn),
.OUTPUT_CLK(! CLK_n),
.OUTPUT_ENABLE(dqs_z_ctrl),
.D_OUT_0(dqs_predriver[1]),
.D_OUT_1(dqs_predriver[0]));
defparam DM_00.PIN_TYPE = 6'b110001;
defparam DM_00.IO_STANDARD = "SB_LVCMOS";
SB_IO DM_00(.PACKAGE_PIN(UDM),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(1'b0),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dm_predriver[1]),
.D_OUT_1(dm_predriver[0]),
.D_IN_0(),
.D_IN_1());
defparam DM_01.PIN_TYPE = 6'b110001;
defparam DM_01.IO_STANDARD = "SB_LVCMOS";
SB_IO DM_01(.PACKAGE_PIN(LDM),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(1'b0),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dm_predriver[1]),
.D_OUT_1(dm_predriver[0]),
.D_IN_0(),
.D_IN_1());
defparam DQ_00.PIN_TYPE = 6'b110000;
defparam DQ_00.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_00(.PACKAGE_PIN(DQ[15]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[31]),
.D_OUT_1(dq_predriver[15]),
.D_IN_0(dq_data_r[15]),
.D_IN_1(dq_data_r[31]));
defparam DQ_01.PIN_TYPE = 6'b110000;
defparam DQ_01.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_01(.PACKAGE_PIN(DQ[14]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[30]),
.D_OUT_1(dq_predriver[14]),
.D_IN_0(dq_data_r[14]),
.D_IN_1(dq_data_r[30]));
defparam DQ_02.PIN_TYPE = 6'b110000;
defparam DQ_02.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_02(.PACKAGE_PIN(DQ[13]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[29]),
.D_OUT_1(dq_predriver[13]),
.D_IN_0(dq_data_r[13]),
.D_IN_1(dq_data_r[29]));
defparam DQ_03.PIN_TYPE = 6'b110000;
defparam DQ_03.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_03(.PACKAGE_PIN(DQ[12]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[28]),
.D_OUT_1(dq_predriver[12]),
.D_IN_0(dq_data_r[12]),
.D_IN_1(dq_data_r[28]));
defparam DQ_04.PIN_TYPE = 6'b110000;
defparam DQ_04.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_04(.PACKAGE_PIN(DQ[11]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[27]),
.D_OUT_1(dq_predriver[11]),
.D_IN_0(dq_data_r[11]),
.D_IN_1(dq_data_r[27]));
defparam DQ_05.PIN_TYPE = 6'b110000;
defparam DQ_05.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_05(.PACKAGE_PIN(DQ[10]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[26]),
.D_OUT_1(dq_predriver[10]),
.D_IN_0(dq_data_r[10]),
.D_IN_1(dq_data_r[26]));
defparam DQ_06.PIN_TYPE = 6'b110000;
defparam DQ_06.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_06(.PACKAGE_PIN(DQ[9]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[25]),
.D_OUT_1(dq_predriver[9]),
.D_IN_0(dq_data_r[9]),
.D_IN_1(dq_data_r[25]));
defparam DQ_07.PIN_TYPE = 6'b110000;
defparam DQ_07.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_07(.PACKAGE_PIN(DQ[8]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[24]),
.D_OUT_1(dq_predriver[8]),
.D_IN_0(dq_data_r[8]),
.D_IN_1(dq_data_r[24]));
defparam DQ_08.PIN_TYPE = 6'b110000;
defparam DQ_08.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_08(.PACKAGE_PIN(DQ[7]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[23]),
.D_OUT_1(dq_predriver[7]),
.D_IN_0(dq_data_r[7]),
.D_IN_1(dq_data_r[23]));
defparam DQ_09.PIN_TYPE = 6'b110000;
defparam DQ_09.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_09(.PACKAGE_PIN(DQ[6]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[22]),
.D_OUT_1(dq_predriver[6]),
.D_IN_0(dq_data_r[6]),
.D_IN_1(dq_data_r[22]));
defparam DQ_10.PIN_TYPE = 6'b110000;
defparam DQ_10.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_10(.PACKAGE_PIN(DQ[5]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[21]),
.D_OUT_1(dq_predriver[5]),
.D_IN_0(dq_data_r[5]),
.D_IN_1(dq_data_r[21]));
defparam DQ_11.PIN_TYPE = 6'b110000;
defparam DQ_11.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_11(.PACKAGE_PIN(DQ[4]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[20]),
.D_OUT_1(dq_predriver[4]),
.D_IN_0(dq_data_r[4]),
.D_IN_1(dq_data_r[20]));
defparam DQ_12.PIN_TYPE = 6'b110000;
defparam DQ_12.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_12(.PACKAGE_PIN(DQ[3]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[19]),
.D_OUT_1(dq_predriver[3]),
.D_IN_0(dq_data_r[3]),
.D_IN_1(dq_data_r[19]));
defparam DQ_13.PIN_TYPE = 6'b110000;
defparam DQ_13.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_13(.PACKAGE_PIN(DQ[2]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[18]),
.D_OUT_1(dq_predriver[2]),
.D_IN_0(dq_data_r[2]),
.D_IN_1(dq_data_r[18]));
defparam DQ_14.PIN_TYPE = 6'b110000;
defparam DQ_14.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_14(.PACKAGE_PIN(DQ[1]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[17]),
.D_OUT_1(dq_predriver[1]),
.D_IN_0(dq_data_r[1]),
.D_IN_1(dq_data_r[17]));
defparam DQ_15.PIN_TYPE = 6'b110000;
defparam DQ_15.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_15(.PACKAGE_PIN(DQ[0]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[16]),
.D_OUT_1(dq_predriver[0]),
.D_IN_0(dq_data_r[0]),
.D_IN_1(dq_data_r[16]));
endmodule | module ddr_data_pins(input CLK_n,
input CLK_dn,
input [31:0] dq_predriver,
input [1:0] dm_predriver,
input [1:0] dqs_predriver,
input dqs_z_ctrl,
input dqdm_z_prectrl,
output [31:0] dq_data_r,
inout [15:0] DQ,
inout UDQS,
inout LDQS,
output UDM,
output LDM); |
dqs_driver DQS_00(.PACKAGE_PIN(UDQS),
.PATCHTHROUGH_INPUT_CLK(),
.PATCHTHROUGH_OUTPUT_CLK(),
.LATCH_CLK(CLK_dn),
.OUTPUT_CLK(! CLK_n),
.OUTPUT_ENABLE(dqs_z_ctrl),
.D_OUT_0(dqs_predriver[1]),
.D_OUT_1(dqs_predriver[0]));
dqs_driver DQS_01(.PACKAGE_PIN(LDQS),
.PATCHTHROUGH_INPUT_CLK(),
.PATCHTHROUGH_OUTPUT_CLK(),
.LATCH_CLK(CLK_dn),
.OUTPUT_CLK(! CLK_n),
.OUTPUT_ENABLE(dqs_z_ctrl),
.D_OUT_0(dqs_predriver[1]),
.D_OUT_1(dqs_predriver[0]));
defparam DM_00.PIN_TYPE = 6'b110001;
defparam DM_00.IO_STANDARD = "SB_LVCMOS";
SB_IO DM_00(.PACKAGE_PIN(UDM),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(1'b0),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dm_predriver[1]),
.D_OUT_1(dm_predriver[0]),
.D_IN_0(),
.D_IN_1());
defparam DM_01.PIN_TYPE = 6'b110001;
defparam DM_01.IO_STANDARD = "SB_LVCMOS";
SB_IO DM_01(.PACKAGE_PIN(LDM),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(1'b0),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dm_predriver[1]),
.D_OUT_1(dm_predriver[0]),
.D_IN_0(),
.D_IN_1());
defparam DQ_00.PIN_TYPE = 6'b110000;
defparam DQ_00.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_00(.PACKAGE_PIN(DQ[15]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[31]),
.D_OUT_1(dq_predriver[15]),
.D_IN_0(dq_data_r[15]),
.D_IN_1(dq_data_r[31]));
defparam DQ_01.PIN_TYPE = 6'b110000;
defparam DQ_01.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_01(.PACKAGE_PIN(DQ[14]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[30]),
.D_OUT_1(dq_predriver[14]),
.D_IN_0(dq_data_r[14]),
.D_IN_1(dq_data_r[30]));
defparam DQ_02.PIN_TYPE = 6'b110000;
defparam DQ_02.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_02(.PACKAGE_PIN(DQ[13]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[29]),
.D_OUT_1(dq_predriver[13]),
.D_IN_0(dq_data_r[13]),
.D_IN_1(dq_data_r[29]));
defparam DQ_03.PIN_TYPE = 6'b110000;
defparam DQ_03.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_03(.PACKAGE_PIN(DQ[12]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[28]),
.D_OUT_1(dq_predriver[12]),
.D_IN_0(dq_data_r[12]),
.D_IN_1(dq_data_r[28]));
defparam DQ_04.PIN_TYPE = 6'b110000;
defparam DQ_04.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_04(.PACKAGE_PIN(DQ[11]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[27]),
.D_OUT_1(dq_predriver[11]),
.D_IN_0(dq_data_r[11]),
.D_IN_1(dq_data_r[27]));
defparam DQ_05.PIN_TYPE = 6'b110000;
defparam DQ_05.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_05(.PACKAGE_PIN(DQ[10]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[26]),
.D_OUT_1(dq_predriver[10]),
.D_IN_0(dq_data_r[10]),
.D_IN_1(dq_data_r[26]));
defparam DQ_06.PIN_TYPE = 6'b110000;
defparam DQ_06.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_06(.PACKAGE_PIN(DQ[9]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[25]),
.D_OUT_1(dq_predriver[9]),
.D_IN_0(dq_data_r[9]),
.D_IN_1(dq_data_r[25]));
defparam DQ_07.PIN_TYPE = 6'b110000;
defparam DQ_07.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_07(.PACKAGE_PIN(DQ[8]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[24]),
.D_OUT_1(dq_predriver[8]),
.D_IN_0(dq_data_r[8]),
.D_IN_1(dq_data_r[24]));
defparam DQ_08.PIN_TYPE = 6'b110000;
defparam DQ_08.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_08(.PACKAGE_PIN(DQ[7]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[23]),
.D_OUT_1(dq_predriver[7]),
.D_IN_0(dq_data_r[7]),
.D_IN_1(dq_data_r[23]));
defparam DQ_09.PIN_TYPE = 6'b110000;
defparam DQ_09.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_09(.PACKAGE_PIN(DQ[6]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[22]),
.D_OUT_1(dq_predriver[6]),
.D_IN_0(dq_data_r[6]),
.D_IN_1(dq_data_r[22]));
defparam DQ_10.PIN_TYPE = 6'b110000;
defparam DQ_10.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_10(.PACKAGE_PIN(DQ[5]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[21]),
.D_OUT_1(dq_predriver[5]),
.D_IN_0(dq_data_r[5]),
.D_IN_1(dq_data_r[21]));
defparam DQ_11.PIN_TYPE = 6'b110000;
defparam DQ_11.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_11(.PACKAGE_PIN(DQ[4]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[20]),
.D_OUT_1(dq_predriver[4]),
.D_IN_0(dq_data_r[4]),
.D_IN_1(dq_data_r[20]));
defparam DQ_12.PIN_TYPE = 6'b110000;
defparam DQ_12.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_12(.PACKAGE_PIN(DQ[3]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[19]),
.D_OUT_1(dq_predriver[3]),
.D_IN_0(dq_data_r[3]),
.D_IN_1(dq_data_r[19]));
defparam DQ_13.PIN_TYPE = 6'b110000;
defparam DQ_13.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_13(.PACKAGE_PIN(DQ[2]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[18]),
.D_OUT_1(dq_predriver[2]),
.D_IN_0(dq_data_r[2]),
.D_IN_1(dq_data_r[18]));
defparam DQ_14.PIN_TYPE = 6'b110000;
defparam DQ_14.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_14(.PACKAGE_PIN(DQ[1]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[17]),
.D_OUT_1(dq_predriver[1]),
.D_IN_0(dq_data_r[1]),
.D_IN_1(dq_data_r[17]));
defparam DQ_15.PIN_TYPE = 6'b110000;
defparam DQ_15.IO_STANDARD = "SB_LVCMOS";
SB_IO DQ_15(.PACKAGE_PIN(DQ[0]),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_dn),
.OUTPUT_CLK(CLK_dn),
.OUTPUT_ENABLE(dqdm_z_prectrl),
.D_OUT_0(dq_predriver[16]),
.D_OUT_1(dq_predriver[0]),
.D_IN_0(dq_data_r[0]),
.D_IN_1(dq_data_r[16]));
endmodule | 1 |
138,615 | data/full_repos/permissive/85002992/mcu/state2.v | 85,002,992 | state2.v | v | 825 | 76 | [] | [] | [] | null | line:35: before: "," | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/85002992/mcu/state2.v:296: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'state2\'\nmodule state2(input CLK,\n ^~~~~~\n : ... Top module \'outputs\'\nmodule outputs(input CLK_n,\n ^~~~~~~\n : ... Top module \'clock_driver\'\nmodule clock_driver(input CLK_n,\n ^~~~~~~~~~~~\n : ... Top module \'SB_IOeg\'\nmodule SB_IOeg(inout PACKAGE_PIN,\n ^~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:34: Duplicate declaration of signal: \'COMMAND_REG\'\n reg [2:0] COMMAND_REG = 3\'b111 ;\n ^~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:29: ... Location of original declaration\n output [2:0] COMMAND_REG,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:35: Duplicate declaration of signal: \'GRANT_ACCESS_RAND\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg GRANT_ACCESS_RAND = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:16: ... Location of original declaration\n output GRANT_ACCESS_RAND,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:36: Duplicate declaration of signal: \'GRANT_ACCESS_BULK\'\n GRANT_ACCESS_BULK = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:22: ... Location of original declaration\n output GRANT_ACCESS_BULK,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:37: Duplicate declaration of signal: \'GRANT_ALIGN_BULK\'\n GRANT_ALIGN_BULK = 1\'b0,\n ^~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:24: ... Location of original declaration\n output GRANT_ALIGN_BULK,\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:38: Duplicate declaration of signal: \'INTERNAL_DATA_MUX\'\n INTERNAL_DATA_MUX = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:30: ... Location of original declaration\n output INTERNAL_DATA_MUX,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:39: Duplicate declaration of signal: \'INTERNAL_DATA_MUX_INVERT\'\n INTERNAL_DATA_MUX_INVERT = 1\'b0;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:31: ... Location of original declaration\n output INTERNAL_DATA_MUX_INVERT,\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:708: Pin not found: \'PIN_TYPE\'\n defparam driver.PIN_TYPE = 6\'b101001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:709: Pin not found: \'IO_STANDARD\'\n defparam driver.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:426: Pin not found: \'PIN_TYPE\'\n defparam DM_00.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:427: Pin not found: \'IO_STANDARD\'\n defparam DM_00.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:439: Pin not found: \'PIN_TYPE\'\n defparam DM_01.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:440: Pin not found: \'IO_STANDARD\'\n defparam DM_01.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:452: Pin not found: \'PIN_TYPE\'\n defparam DQ_00.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:453: Pin not found: \'IO_STANDARD\'\n defparam DQ_00.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:465: Pin not found: \'PIN_TYPE\'\n defparam DQ_01.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:466: Pin not found: \'IO_STANDARD\'\n defparam DQ_01.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:478: Pin not found: \'PIN_TYPE\'\n defparam DQ_02.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:479: Pin not found: \'IO_STANDARD\'\n defparam DQ_02.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:491: Pin not found: \'PIN_TYPE\'\n defparam DQ_03.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:492: Pin not found: \'IO_STANDARD\'\n defparam DQ_03.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:504: Pin not found: \'PIN_TYPE\'\n defparam DQ_04.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:505: Pin not found: \'IO_STANDARD\'\n defparam DQ_04.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:517: Pin not found: \'PIN_TYPE\'\n defparam DQ_05.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:518: Pin not found: \'IO_STANDARD\'\n defparam DQ_05.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:530: Pin not found: \'PIN_TYPE\'\n defparam DQ_06.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:531: Pin not found: \'IO_STANDARD\'\n defparam DQ_06.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:543: Pin not found: \'PIN_TYPE\'\n defparam DQ_07.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:544: Pin not found: \'IO_STANDARD\'\n defparam DQ_07.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:556: Pin not found: \'PIN_TYPE\'\n defparam DQ_08.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:557: Pin not found: \'IO_STANDARD\'\n defparam DQ_08.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:569: Pin not found: \'PIN_TYPE\'\n defparam DQ_09.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:570: Pin not found: \'IO_STANDARD\'\n defparam DQ_09.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:582: Pin not found: \'PIN_TYPE\'\n defparam DQ_10.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:583: Pin not found: \'IO_STANDARD\'\n defparam DQ_10.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:595: Pin not found: \'PIN_TYPE\'\n defparam DQ_11.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:596: Pin not found: \'IO_STANDARD\'\n defparam DQ_11.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:608: Pin not found: \'PIN_TYPE\'\n defparam DQ_12.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:609: Pin not found: \'IO_STANDARD\'\n defparam DQ_12.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:621: Pin not found: \'PIN_TYPE\'\n defparam DQ_13.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:622: Pin not found: \'IO_STANDARD\'\n defparam DQ_13.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:634: Pin not found: \'PIN_TYPE\'\n defparam DQ_14.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:635: Pin not found: \'IO_STANDARD\'\n defparam DQ_14.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:647: Pin not found: \'PIN_TYPE\'\n defparam DQ_15.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:648: Pin not found: \'IO_STANDARD\'\n defparam DQ_15.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:667: Pin not found: \'PIN_TYPE\'\n defparam CLK_POS.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:668: Pin not found: \'IO_STANDARD\'\n defparam CLK_POS.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:680: Pin not found: \'PIN_TYPE\'\n defparam CLK_NEG.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:681: Pin not found: \'IO_STANDARD\'\n defparam CLK_NEG.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: Exiting due to 48 error(s), 1 warning(s)\n' | 302,588 | module | module clock_driver(input CLK_n,
input RST,
output CLK_P,
output CLK_N);
defparam CLK_POS.PIN_TYPE = 6'b110001;
defparam CLK_POS.IO_STANDARD = "SB_LVCMOS";
SB_IO CLK_POS(.PACKAGE_PIN(CLK_P),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_n),
.OUTPUT_CLK(CLK_n),
.OUTPUT_ENABLE(RST),
.D_OUT_0(1'b0),
.D_OUT_1(1'b1),
.D_IN_0(),
.D_IN_1());
defparam CLK_NEG.PIN_TYPE = 6'b110001;
defparam CLK_NEG.IO_STANDARD = "SB_LVCMOS";
SB_IO CLK_NEG(.PACKAGE_PIN(CLK_N),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_n),
.OUTPUT_CLK(CLK_n),
.OUTPUT_ENABLE(RST),
.D_OUT_0(1'b1),
.D_OUT_1(1'b0),
.D_IN_0(),
.D_IN_1());
endmodule | module clock_driver(input CLK_n,
input RST,
output CLK_P,
output CLK_N); |
defparam CLK_POS.PIN_TYPE = 6'b110001;
defparam CLK_POS.IO_STANDARD = "SB_LVCMOS";
SB_IO CLK_POS(.PACKAGE_PIN(CLK_P),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_n),
.OUTPUT_CLK(CLK_n),
.OUTPUT_ENABLE(RST),
.D_OUT_0(1'b0),
.D_OUT_1(1'b1),
.D_IN_0(),
.D_IN_1());
defparam CLK_NEG.PIN_TYPE = 6'b110001;
defparam CLK_NEG.IO_STANDARD = "SB_LVCMOS";
SB_IO CLK_NEG(.PACKAGE_PIN(CLK_N),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(CLK_n),
.OUTPUT_CLK(CLK_n),
.OUTPUT_ENABLE(RST),
.D_OUT_0(1'b1),
.D_OUT_1(1'b0),
.D_IN_0(),
.D_IN_1());
endmodule | 1 |
138,616 | data/full_repos/permissive/85002992/mcu/state2.v | 85,002,992 | state2.v | v | 825 | 76 | [] | [] | [] | null | line:35: before: "," | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/85002992/mcu/state2.v:296: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'state2\'\nmodule state2(input CLK,\n ^~~~~~\n : ... Top module \'outputs\'\nmodule outputs(input CLK_n,\n ^~~~~~~\n : ... Top module \'clock_driver\'\nmodule clock_driver(input CLK_n,\n ^~~~~~~~~~~~\n : ... Top module \'SB_IOeg\'\nmodule SB_IOeg(inout PACKAGE_PIN,\n ^~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:34: Duplicate declaration of signal: \'COMMAND_REG\'\n reg [2:0] COMMAND_REG = 3\'b111 ;\n ^~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:29: ... Location of original declaration\n output [2:0] COMMAND_REG,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:35: Duplicate declaration of signal: \'GRANT_ACCESS_RAND\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg GRANT_ACCESS_RAND = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:16: ... Location of original declaration\n output GRANT_ACCESS_RAND,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:36: Duplicate declaration of signal: \'GRANT_ACCESS_BULK\'\n GRANT_ACCESS_BULK = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:22: ... Location of original declaration\n output GRANT_ACCESS_BULK,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:37: Duplicate declaration of signal: \'GRANT_ALIGN_BULK\'\n GRANT_ALIGN_BULK = 1\'b0,\n ^~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:24: ... Location of original declaration\n output GRANT_ALIGN_BULK,\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:38: Duplicate declaration of signal: \'INTERNAL_DATA_MUX\'\n INTERNAL_DATA_MUX = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:30: ... Location of original declaration\n output INTERNAL_DATA_MUX,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:39: Duplicate declaration of signal: \'INTERNAL_DATA_MUX_INVERT\'\n INTERNAL_DATA_MUX_INVERT = 1\'b0;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:31: ... Location of original declaration\n output INTERNAL_DATA_MUX_INVERT,\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:708: Pin not found: \'PIN_TYPE\'\n defparam driver.PIN_TYPE = 6\'b101001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:709: Pin not found: \'IO_STANDARD\'\n defparam driver.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:426: Pin not found: \'PIN_TYPE\'\n defparam DM_00.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:427: Pin not found: \'IO_STANDARD\'\n defparam DM_00.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:439: Pin not found: \'PIN_TYPE\'\n defparam DM_01.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:440: Pin not found: \'IO_STANDARD\'\n defparam DM_01.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:452: Pin not found: \'PIN_TYPE\'\n defparam DQ_00.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:453: Pin not found: \'IO_STANDARD\'\n defparam DQ_00.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:465: Pin not found: \'PIN_TYPE\'\n defparam DQ_01.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:466: Pin not found: \'IO_STANDARD\'\n defparam DQ_01.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:478: Pin not found: \'PIN_TYPE\'\n defparam DQ_02.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:479: Pin not found: \'IO_STANDARD\'\n defparam DQ_02.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:491: Pin not found: \'PIN_TYPE\'\n defparam DQ_03.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:492: Pin not found: \'IO_STANDARD\'\n defparam DQ_03.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:504: Pin not found: \'PIN_TYPE\'\n defparam DQ_04.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:505: Pin not found: \'IO_STANDARD\'\n defparam DQ_04.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:517: Pin not found: \'PIN_TYPE\'\n defparam DQ_05.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:518: Pin not found: \'IO_STANDARD\'\n defparam DQ_05.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:530: Pin not found: \'PIN_TYPE\'\n defparam DQ_06.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:531: Pin not found: \'IO_STANDARD\'\n defparam DQ_06.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:543: Pin not found: \'PIN_TYPE\'\n defparam DQ_07.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:544: Pin not found: \'IO_STANDARD\'\n defparam DQ_07.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:556: Pin not found: \'PIN_TYPE\'\n defparam DQ_08.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:557: Pin not found: \'IO_STANDARD\'\n defparam DQ_08.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:569: Pin not found: \'PIN_TYPE\'\n defparam DQ_09.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:570: Pin not found: \'IO_STANDARD\'\n defparam DQ_09.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:582: Pin not found: \'PIN_TYPE\'\n defparam DQ_10.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:583: Pin not found: \'IO_STANDARD\'\n defparam DQ_10.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:595: Pin not found: \'PIN_TYPE\'\n defparam DQ_11.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:596: Pin not found: \'IO_STANDARD\'\n defparam DQ_11.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:608: Pin not found: \'PIN_TYPE\'\n defparam DQ_12.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:609: Pin not found: \'IO_STANDARD\'\n defparam DQ_12.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:621: Pin not found: \'PIN_TYPE\'\n defparam DQ_13.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:622: Pin not found: \'IO_STANDARD\'\n defparam DQ_13.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:634: Pin not found: \'PIN_TYPE\'\n defparam DQ_14.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:635: Pin not found: \'IO_STANDARD\'\n defparam DQ_14.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:647: Pin not found: \'PIN_TYPE\'\n defparam DQ_15.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:648: Pin not found: \'IO_STANDARD\'\n defparam DQ_15.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:667: Pin not found: \'PIN_TYPE\'\n defparam CLK_POS.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:668: Pin not found: \'IO_STANDARD\'\n defparam CLK_POS.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:680: Pin not found: \'PIN_TYPE\'\n defparam CLK_NEG.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:681: Pin not found: \'IO_STANDARD\'\n defparam CLK_NEG.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: Exiting due to 48 error(s), 1 warning(s)\n' | 302,588 | module | module dqs_driver(inout PACKAGE_PIN,
input PATCHTHROUGH_INPUT_CLK,
input PATCHTHROUGH_OUTPUT_CLK,
input LATCH_CLK,
input OUTPUT_CLK,
input OUTPUT_ENABLE,
input D_OUT_0,
input D_OUT_1);
reg reg_out_0, reg_out_1;
wire out_mux;
assign out_mux = OUTPUT_CLK ? reg_out_0 : reg_out_1;
defparam driver.PIN_TYPE = 6'b101001;
defparam driver.IO_STANDARD = "SB_LVCMOS";
SB_IOtri driver(.PACKAGE_PIN(PACKAGE_PIN),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(PATCHTHROUGH_INPUT_CLK),
.OUTPUT_CLK(PATCHTHROUGH_OUTPUT_CLK),
.OUTPUT_ENABLE(OUTPUT_ENABLE),
.D_OUT_0(out_mux),
.D_OUT_1(1'b0),
.D_IN_0(),
.D_IN_1());
always @(posedge LATCH_CLK)
begin
reg_out_0 <= D_OUT_0;
end
always @(negedge LATCH_CLK)
begin
reg_out_1 <= D_OUT_1;
end
endmodule | module dqs_driver(inout PACKAGE_PIN,
input PATCHTHROUGH_INPUT_CLK,
input PATCHTHROUGH_OUTPUT_CLK,
input LATCH_CLK,
input OUTPUT_CLK,
input OUTPUT_ENABLE,
input D_OUT_0,
input D_OUT_1); |
reg reg_out_0, reg_out_1;
wire out_mux;
assign out_mux = OUTPUT_CLK ? reg_out_0 : reg_out_1;
defparam driver.PIN_TYPE = 6'b101001;
defparam driver.IO_STANDARD = "SB_LVCMOS";
SB_IOtri driver(.PACKAGE_PIN(PACKAGE_PIN),
.LATCH_INPUT_VALUE(1'b0),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(PATCHTHROUGH_INPUT_CLK),
.OUTPUT_CLK(PATCHTHROUGH_OUTPUT_CLK),
.OUTPUT_ENABLE(OUTPUT_ENABLE),
.D_OUT_0(out_mux),
.D_OUT_1(1'b0),
.D_IN_0(),
.D_IN_1());
always @(posedge LATCH_CLK)
begin
reg_out_0 <= D_OUT_0;
end
always @(negedge LATCH_CLK)
begin
reg_out_1 <= D_OUT_1;
end
endmodule | 1 |
138,617 | data/full_repos/permissive/85002992/mcu/state2.v | 85,002,992 | state2.v | v | 825 | 76 | [] | [] | [] | null | line:35: before: "," | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/85002992/mcu/state2.v:296: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'state2\'\nmodule state2(input CLK,\n ^~~~~~\n : ... Top module \'outputs\'\nmodule outputs(input CLK_n,\n ^~~~~~~\n : ... Top module \'clock_driver\'\nmodule clock_driver(input CLK_n,\n ^~~~~~~~~~~~\n : ... Top module \'SB_IOeg\'\nmodule SB_IOeg(inout PACKAGE_PIN,\n ^~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:34: Duplicate declaration of signal: \'COMMAND_REG\'\n reg [2:0] COMMAND_REG = 3\'b111 ;\n ^~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:29: ... Location of original declaration\n output [2:0] COMMAND_REG,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:35: Duplicate declaration of signal: \'GRANT_ACCESS_RAND\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg GRANT_ACCESS_RAND = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:16: ... Location of original declaration\n output GRANT_ACCESS_RAND,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:36: Duplicate declaration of signal: \'GRANT_ACCESS_BULK\'\n GRANT_ACCESS_BULK = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:22: ... Location of original declaration\n output GRANT_ACCESS_BULK,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:37: Duplicate declaration of signal: \'GRANT_ALIGN_BULK\'\n GRANT_ALIGN_BULK = 1\'b0,\n ^~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:24: ... Location of original declaration\n output GRANT_ALIGN_BULK,\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:38: Duplicate declaration of signal: \'INTERNAL_DATA_MUX\'\n INTERNAL_DATA_MUX = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:30: ... Location of original declaration\n output INTERNAL_DATA_MUX,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:39: Duplicate declaration of signal: \'INTERNAL_DATA_MUX_INVERT\'\n INTERNAL_DATA_MUX_INVERT = 1\'b0;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:31: ... Location of original declaration\n output INTERNAL_DATA_MUX_INVERT,\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:708: Pin not found: \'PIN_TYPE\'\n defparam driver.PIN_TYPE = 6\'b101001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:709: Pin not found: \'IO_STANDARD\'\n defparam driver.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:426: Pin not found: \'PIN_TYPE\'\n defparam DM_00.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:427: Pin not found: \'IO_STANDARD\'\n defparam DM_00.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:439: Pin not found: \'PIN_TYPE\'\n defparam DM_01.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:440: Pin not found: \'IO_STANDARD\'\n defparam DM_01.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:452: Pin not found: \'PIN_TYPE\'\n defparam DQ_00.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:453: Pin not found: \'IO_STANDARD\'\n defparam DQ_00.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:465: Pin not found: \'PIN_TYPE\'\n defparam DQ_01.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:466: Pin not found: \'IO_STANDARD\'\n defparam DQ_01.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:478: Pin not found: \'PIN_TYPE\'\n defparam DQ_02.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:479: Pin not found: \'IO_STANDARD\'\n defparam DQ_02.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:491: Pin not found: \'PIN_TYPE\'\n defparam DQ_03.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:492: Pin not found: \'IO_STANDARD\'\n defparam DQ_03.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:504: Pin not found: \'PIN_TYPE\'\n defparam DQ_04.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:505: Pin not found: \'IO_STANDARD\'\n defparam DQ_04.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:517: Pin not found: \'PIN_TYPE\'\n defparam DQ_05.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:518: Pin not found: \'IO_STANDARD\'\n defparam DQ_05.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:530: Pin not found: \'PIN_TYPE\'\n defparam DQ_06.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:531: Pin not found: \'IO_STANDARD\'\n defparam DQ_06.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:543: Pin not found: \'PIN_TYPE\'\n defparam DQ_07.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:544: Pin not found: \'IO_STANDARD\'\n defparam DQ_07.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:556: Pin not found: \'PIN_TYPE\'\n defparam DQ_08.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:557: Pin not found: \'IO_STANDARD\'\n defparam DQ_08.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:569: Pin not found: \'PIN_TYPE\'\n defparam DQ_09.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:570: Pin not found: \'IO_STANDARD\'\n defparam DQ_09.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:582: Pin not found: \'PIN_TYPE\'\n defparam DQ_10.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:583: Pin not found: \'IO_STANDARD\'\n defparam DQ_10.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:595: Pin not found: \'PIN_TYPE\'\n defparam DQ_11.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:596: Pin not found: \'IO_STANDARD\'\n defparam DQ_11.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:608: Pin not found: \'PIN_TYPE\'\n defparam DQ_12.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:609: Pin not found: \'IO_STANDARD\'\n defparam DQ_12.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:621: Pin not found: \'PIN_TYPE\'\n defparam DQ_13.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:622: Pin not found: \'IO_STANDARD\'\n defparam DQ_13.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:634: Pin not found: \'PIN_TYPE\'\n defparam DQ_14.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:635: Pin not found: \'IO_STANDARD\'\n defparam DQ_14.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:647: Pin not found: \'PIN_TYPE\'\n defparam DQ_15.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:648: Pin not found: \'IO_STANDARD\'\n defparam DQ_15.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:667: Pin not found: \'PIN_TYPE\'\n defparam CLK_POS.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:668: Pin not found: \'IO_STANDARD\'\n defparam CLK_POS.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:680: Pin not found: \'PIN_TYPE\'\n defparam CLK_NEG.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:681: Pin not found: \'IO_STANDARD\'\n defparam CLK_NEG.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: Exiting due to 48 error(s), 1 warning(s)\n' | 302,588 | module | module SB_IO(inout PACKAGE_PIN,
input LATCH_INPUT_VALUE,
input CLOCK_ENABLE,
input INPUT_CLK,
input OUTPUT_CLK,
input OUTPUT_ENABLE,
input D_OUT_0,
input D_OUT_1,
output reg D_IN_0,
output reg D_IN_1);
reg out_en, reg_out_0, reg_out_1;
wire out_mux;
assign PACKAGE_PIN = out_en ? out_mux : 1'bz;
assign out_mux = OUTPUT_CLK ? reg_out_0 : reg_out_1;
always @(posedge INPUT_CLK)
if (CLOCK_ENABLE)
D_IN_0 <= PACKAGE_PIN;
always @(negedge INPUT_CLK)
if (CLOCK_ENABLE)
D_IN_1 <= PACKAGE_PIN;
always @(posedge OUTPUT_CLK)
if (CLOCK_ENABLE)
begin
out_en <= OUTPUT_ENABLE;
reg_out_0 <= D_OUT_0;
end
always @(negedge OUTPUT_CLK)
if (CLOCK_ENABLE)
begin
reg_out_1 <= D_OUT_1;
end
endmodule | module SB_IO(inout PACKAGE_PIN,
input LATCH_INPUT_VALUE,
input CLOCK_ENABLE,
input INPUT_CLK,
input OUTPUT_CLK,
input OUTPUT_ENABLE,
input D_OUT_0,
input D_OUT_1,
output reg D_IN_0,
output reg D_IN_1); |
reg out_en, reg_out_0, reg_out_1;
wire out_mux;
assign PACKAGE_PIN = out_en ? out_mux : 1'bz;
assign out_mux = OUTPUT_CLK ? reg_out_0 : reg_out_1;
always @(posedge INPUT_CLK)
if (CLOCK_ENABLE)
D_IN_0 <= PACKAGE_PIN;
always @(negedge INPUT_CLK)
if (CLOCK_ENABLE)
D_IN_1 <= PACKAGE_PIN;
always @(posedge OUTPUT_CLK)
if (CLOCK_ENABLE)
begin
out_en <= OUTPUT_ENABLE;
reg_out_0 <= D_OUT_0;
end
always @(negedge OUTPUT_CLK)
if (CLOCK_ENABLE)
begin
reg_out_1 <= D_OUT_1;
end
endmodule | 1 |
138,618 | data/full_repos/permissive/85002992/mcu/state2.v | 85,002,992 | state2.v | v | 825 | 76 | [] | [] | [] | null | line:35: before: "," | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/85002992/mcu/state2.v:296: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'state2\'\nmodule state2(input CLK,\n ^~~~~~\n : ... Top module \'outputs\'\nmodule outputs(input CLK_n,\n ^~~~~~~\n : ... Top module \'clock_driver\'\nmodule clock_driver(input CLK_n,\n ^~~~~~~~~~~~\n : ... Top module \'SB_IOeg\'\nmodule SB_IOeg(inout PACKAGE_PIN,\n ^~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:34: Duplicate declaration of signal: \'COMMAND_REG\'\n reg [2:0] COMMAND_REG = 3\'b111 ;\n ^~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:29: ... Location of original declaration\n output [2:0] COMMAND_REG,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:35: Duplicate declaration of signal: \'GRANT_ACCESS_RAND\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg GRANT_ACCESS_RAND = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:16: ... Location of original declaration\n output GRANT_ACCESS_RAND,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:36: Duplicate declaration of signal: \'GRANT_ACCESS_BULK\'\n GRANT_ACCESS_BULK = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:22: ... Location of original declaration\n output GRANT_ACCESS_BULK,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:37: Duplicate declaration of signal: \'GRANT_ALIGN_BULK\'\n GRANT_ALIGN_BULK = 1\'b0,\n ^~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:24: ... Location of original declaration\n output GRANT_ALIGN_BULK,\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:38: Duplicate declaration of signal: \'INTERNAL_DATA_MUX\'\n INTERNAL_DATA_MUX = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:30: ... Location of original declaration\n output INTERNAL_DATA_MUX,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:39: Duplicate declaration of signal: \'INTERNAL_DATA_MUX_INVERT\'\n INTERNAL_DATA_MUX_INVERT = 1\'b0;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:31: ... Location of original declaration\n output INTERNAL_DATA_MUX_INVERT,\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:708: Pin not found: \'PIN_TYPE\'\n defparam driver.PIN_TYPE = 6\'b101001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:709: Pin not found: \'IO_STANDARD\'\n defparam driver.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:426: Pin not found: \'PIN_TYPE\'\n defparam DM_00.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:427: Pin not found: \'IO_STANDARD\'\n defparam DM_00.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:439: Pin not found: \'PIN_TYPE\'\n defparam DM_01.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:440: Pin not found: \'IO_STANDARD\'\n defparam DM_01.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:452: Pin not found: \'PIN_TYPE\'\n defparam DQ_00.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:453: Pin not found: \'IO_STANDARD\'\n defparam DQ_00.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:465: Pin not found: \'PIN_TYPE\'\n defparam DQ_01.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:466: Pin not found: \'IO_STANDARD\'\n defparam DQ_01.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:478: Pin not found: \'PIN_TYPE\'\n defparam DQ_02.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:479: Pin not found: \'IO_STANDARD\'\n defparam DQ_02.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:491: Pin not found: \'PIN_TYPE\'\n defparam DQ_03.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:492: Pin not found: \'IO_STANDARD\'\n defparam DQ_03.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:504: Pin not found: \'PIN_TYPE\'\n defparam DQ_04.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:505: Pin not found: \'IO_STANDARD\'\n defparam DQ_04.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:517: Pin not found: \'PIN_TYPE\'\n defparam DQ_05.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:518: Pin not found: \'IO_STANDARD\'\n defparam DQ_05.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:530: Pin not found: \'PIN_TYPE\'\n defparam DQ_06.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:531: Pin not found: \'IO_STANDARD\'\n defparam DQ_06.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:543: Pin not found: \'PIN_TYPE\'\n defparam DQ_07.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:544: Pin not found: \'IO_STANDARD\'\n defparam DQ_07.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:556: Pin not found: \'PIN_TYPE\'\n defparam DQ_08.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:557: Pin not found: \'IO_STANDARD\'\n defparam DQ_08.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:569: Pin not found: \'PIN_TYPE\'\n defparam DQ_09.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:570: Pin not found: \'IO_STANDARD\'\n defparam DQ_09.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:582: Pin not found: \'PIN_TYPE\'\n defparam DQ_10.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:583: Pin not found: \'IO_STANDARD\'\n defparam DQ_10.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:595: Pin not found: \'PIN_TYPE\'\n defparam DQ_11.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:596: Pin not found: \'IO_STANDARD\'\n defparam DQ_11.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:608: Pin not found: \'PIN_TYPE\'\n defparam DQ_12.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:609: Pin not found: \'IO_STANDARD\'\n defparam DQ_12.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:621: Pin not found: \'PIN_TYPE\'\n defparam DQ_13.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:622: Pin not found: \'IO_STANDARD\'\n defparam DQ_13.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:634: Pin not found: \'PIN_TYPE\'\n defparam DQ_14.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:635: Pin not found: \'IO_STANDARD\'\n defparam DQ_14.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:647: Pin not found: \'PIN_TYPE\'\n defparam DQ_15.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:648: Pin not found: \'IO_STANDARD\'\n defparam DQ_15.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:667: Pin not found: \'PIN_TYPE\'\n defparam CLK_POS.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:668: Pin not found: \'IO_STANDARD\'\n defparam CLK_POS.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:680: Pin not found: \'PIN_TYPE\'\n defparam CLK_NEG.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:681: Pin not found: \'IO_STANDARD\'\n defparam CLK_NEG.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: Exiting due to 48 error(s), 1 warning(s)\n' | 302,588 | module | module SB_IOeg(inout PACKAGE_PIN,
input LATCH_INPUT_VALUE,
input CLOCK_ENABLE,
input INPUT_CLK,
input OUTPUT_CLK,
input OUTPUT_ENABLE,
input D_OUT_0,
input D_OUT_1,
output reg D_IN_0,
output reg D_IN_1);
reg reg_out_0, reg_out_1;
wire out_mux;
assign PACKAGE_PIN = OUTPUT_ENABLE ? out_mux : 1'bz;
assign out_mux = OUTPUT_CLK ? reg_out_0 : reg_out_1;
always @(posedge INPUT_CLK)
if (CLOCK_ENABLE)
D_IN_0 <= PACKAGE_PIN;
always @(negedge INPUT_CLK)
if (CLOCK_ENABLE)
D_IN_1 <= PACKAGE_PIN;
always @(posedge OUTPUT_CLK)
if (CLOCK_ENABLE)
reg_out_0 <= D_OUT_0;
always @(negedge OUTPUT_CLK)
if (CLOCK_ENABLE)
reg_out_1 <= D_OUT_1;
endmodule | module SB_IOeg(inout PACKAGE_PIN,
input LATCH_INPUT_VALUE,
input CLOCK_ENABLE,
input INPUT_CLK,
input OUTPUT_CLK,
input OUTPUT_ENABLE,
input D_OUT_0,
input D_OUT_1,
output reg D_IN_0,
output reg D_IN_1); |
reg reg_out_0, reg_out_1;
wire out_mux;
assign PACKAGE_PIN = OUTPUT_ENABLE ? out_mux : 1'bz;
assign out_mux = OUTPUT_CLK ? reg_out_0 : reg_out_1;
always @(posedge INPUT_CLK)
if (CLOCK_ENABLE)
D_IN_0 <= PACKAGE_PIN;
always @(negedge INPUT_CLK)
if (CLOCK_ENABLE)
D_IN_1 <= PACKAGE_PIN;
always @(posedge OUTPUT_CLK)
if (CLOCK_ENABLE)
reg_out_0 <= D_OUT_0;
always @(negedge OUTPUT_CLK)
if (CLOCK_ENABLE)
reg_out_1 <= D_OUT_1;
endmodule | 1 |
138,619 | data/full_repos/permissive/85002992/mcu/state2.v | 85,002,992 | state2.v | v | 825 | 76 | [] | [] | [] | null | line:35: before: "," | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/85002992/mcu/state2.v:296: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'state2\'\nmodule state2(input CLK,\n ^~~~~~\n : ... Top module \'outputs\'\nmodule outputs(input CLK_n,\n ^~~~~~~\n : ... Top module \'clock_driver\'\nmodule clock_driver(input CLK_n,\n ^~~~~~~~~~~~\n : ... Top module \'SB_IOeg\'\nmodule SB_IOeg(inout PACKAGE_PIN,\n ^~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:34: Duplicate declaration of signal: \'COMMAND_REG\'\n reg [2:0] COMMAND_REG = 3\'b111 ;\n ^~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:29: ... Location of original declaration\n output [2:0] COMMAND_REG,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:35: Duplicate declaration of signal: \'GRANT_ACCESS_RAND\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg GRANT_ACCESS_RAND = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:16: ... Location of original declaration\n output GRANT_ACCESS_RAND,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:36: Duplicate declaration of signal: \'GRANT_ACCESS_BULK\'\n GRANT_ACCESS_BULK = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:22: ... Location of original declaration\n output GRANT_ACCESS_BULK,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:37: Duplicate declaration of signal: \'GRANT_ALIGN_BULK\'\n GRANT_ALIGN_BULK = 1\'b0,\n ^~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:24: ... Location of original declaration\n output GRANT_ALIGN_BULK,\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:38: Duplicate declaration of signal: \'INTERNAL_DATA_MUX\'\n INTERNAL_DATA_MUX = 1\'b0,\n ^~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:30: ... Location of original declaration\n output INTERNAL_DATA_MUX,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:39: Duplicate declaration of signal: \'INTERNAL_DATA_MUX_INVERT\'\n INTERNAL_DATA_MUX_INVERT = 1\'b0;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/mcu/state2.v:31: ... Location of original declaration\n output INTERNAL_DATA_MUX_INVERT,\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:708: Pin not found: \'PIN_TYPE\'\n defparam driver.PIN_TYPE = 6\'b101001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:709: Pin not found: \'IO_STANDARD\'\n defparam driver.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:426: Pin not found: \'PIN_TYPE\'\n defparam DM_00.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:427: Pin not found: \'IO_STANDARD\'\n defparam DM_00.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:439: Pin not found: \'PIN_TYPE\'\n defparam DM_01.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:440: Pin not found: \'IO_STANDARD\'\n defparam DM_01.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:452: Pin not found: \'PIN_TYPE\'\n defparam DQ_00.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:453: Pin not found: \'IO_STANDARD\'\n defparam DQ_00.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:465: Pin not found: \'PIN_TYPE\'\n defparam DQ_01.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:466: Pin not found: \'IO_STANDARD\'\n defparam DQ_01.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:478: Pin not found: \'PIN_TYPE\'\n defparam DQ_02.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:479: Pin not found: \'IO_STANDARD\'\n defparam DQ_02.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:491: Pin not found: \'PIN_TYPE\'\n defparam DQ_03.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:492: Pin not found: \'IO_STANDARD\'\n defparam DQ_03.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:504: Pin not found: \'PIN_TYPE\'\n defparam DQ_04.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:505: Pin not found: \'IO_STANDARD\'\n defparam DQ_04.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:517: Pin not found: \'PIN_TYPE\'\n defparam DQ_05.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:518: Pin not found: \'IO_STANDARD\'\n defparam DQ_05.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:530: Pin not found: \'PIN_TYPE\'\n defparam DQ_06.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:531: Pin not found: \'IO_STANDARD\'\n defparam DQ_06.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:543: Pin not found: \'PIN_TYPE\'\n defparam DQ_07.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:544: Pin not found: \'IO_STANDARD\'\n defparam DQ_07.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:556: Pin not found: \'PIN_TYPE\'\n defparam DQ_08.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:557: Pin not found: \'IO_STANDARD\'\n defparam DQ_08.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:569: Pin not found: \'PIN_TYPE\'\n defparam DQ_09.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:570: Pin not found: \'IO_STANDARD\'\n defparam DQ_09.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:582: Pin not found: \'PIN_TYPE\'\n defparam DQ_10.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:583: Pin not found: \'IO_STANDARD\'\n defparam DQ_10.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:595: Pin not found: \'PIN_TYPE\'\n defparam DQ_11.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:596: Pin not found: \'IO_STANDARD\'\n defparam DQ_11.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:608: Pin not found: \'PIN_TYPE\'\n defparam DQ_12.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:609: Pin not found: \'IO_STANDARD\'\n defparam DQ_12.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:621: Pin not found: \'PIN_TYPE\'\n defparam DQ_13.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:622: Pin not found: \'IO_STANDARD\'\n defparam DQ_13.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:634: Pin not found: \'PIN_TYPE\'\n defparam DQ_14.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:635: Pin not found: \'IO_STANDARD\'\n defparam DQ_14.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:647: Pin not found: \'PIN_TYPE\'\n defparam DQ_15.PIN_TYPE = 6\'b110000;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:648: Pin not found: \'IO_STANDARD\'\n defparam DQ_15.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:667: Pin not found: \'PIN_TYPE\'\n defparam CLK_POS.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:668: Pin not found: \'IO_STANDARD\'\n defparam CLK_POS.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:680: Pin not found: \'PIN_TYPE\'\n defparam CLK_NEG.PIN_TYPE = 6\'b110001;\n ^\n%Error: data/full_repos/permissive/85002992/mcu/state2.v:681: Pin not found: \'IO_STANDARD\'\n defparam CLK_NEG.IO_STANDARD = "SB_LVCMOS";\n ^\n%Error: Exiting due to 48 error(s), 1 warning(s)\n' | 302,588 | module | module SB_IOtri(inout PACKAGE_PIN,
input LATCH_INPUT_VALUE,
input CLOCK_ENABLE,
input INPUT_CLK,
input OUTPUT_CLK,
input OUTPUT_ENABLE,
input D_OUT_0,
input D_OUT_1,
output reg D_IN_0,
output reg D_IN_1);
assign PACKAGE_PIN = OUTPUT_ENABLE ? D_OUT_0 : 1'bz;
always @(posedge INPUT_CLK)
if (CLOCK_ENABLE)
D_IN_0 <= PACKAGE_PIN;
always @(negedge INPUT_CLK)
if (CLOCK_ENABLE)
D_IN_1 <= PACKAGE_PIN;
endmodule | module SB_IOtri(inout PACKAGE_PIN,
input LATCH_INPUT_VALUE,
input CLOCK_ENABLE,
input INPUT_CLK,
input OUTPUT_CLK,
input OUTPUT_ENABLE,
input D_OUT_0,
input D_OUT_1,
output reg D_IN_0,
output reg D_IN_1); |
assign PACKAGE_PIN = OUTPUT_ENABLE ? D_OUT_0 : 1'bz;
always @(posedge INPUT_CLK)
if (CLOCK_ENABLE)
D_IN_0 <= PACKAGE_PIN;
always @(negedge INPUT_CLK)
if (CLOCK_ENABLE)
D_IN_1 <= PACKAGE_PIN;
endmodule | 1 |
138,620 | data/full_repos/permissive/85002992/special_snowflake/core.v | 85,002,992 | core.v | v | 526 | 74 | [] | [] | [] | null | line:130: before: "," | null | 1: b"%Error: data/full_repos/permissive/85002992/special_snowflake/core.v:96: Duplicate declaration of signal: 'write_fifo_cr'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg [1:0] write_fifo_cr = 2'h2;\n ^~~~~~~~~~~~~\n data/full_repos/permissive/85002992/special_snowflake/core.v:36: ... Location of original declaration\n output [1:0] write_fifo_cr,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/special_snowflake/core.v:97: Duplicate declaration of signal: 'read_fifo_cw'\n reg [1:0] read_fifo_cw = 2'h0;\n ^~~~~~~~~~~~\n data/full_repos/permissive/85002992/special_snowflake/core.v:37: ... Location of original declaration\n output [1:0] read_fifo_cw,\n ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 302,589 | module | module special_snowflake_core(input RST_MASTER,
input RST_CPU_TRANS,
input CLK_n,
input CLK_dn,
input CPU_CLK,
output mem_iCLK_P,
output mem_iCLK_N,
output mem_iCKE,
inout mem_iUDQS,
inout mem_iLDQS,
inout mem_iUDM,
inout mem_iLDM,
output mem_iCS,
output [2:0] mem_iCOMMAND,
output [13:0] mem_iADDRESS,
output [2:0] mem_iBANK,
inout [15:0] mem_iDQ,
output mem_iODT,
output mem_dCLK_P,
output mem_dCLK_N,
output mem_dCKE,
inout mem_dUDQS,
inout mem_dLDQS,
inout mem_dUDM,
inout mem_dLDM,
output mem_dCS,
output [2:0] mem_dCOMMAND,
output [13:0] mem_dADDRESS,
output [2:0] mem_dBANK,
inout [15:0] mem_dDQ,
output mem_dODT,
output [1:0] write_fifo_cr,
output [1:0] read_fifo_cw,
input [31:0] data0_cr,
input [31:0] data1_cr,
input [31:0] data2_cr,
input [31:0] data3_cr,
input [24:0] ancill0_cr,
input [24:0] ancill1_cr,
input [24:0] ancill2_cr,
input [24:0] ancill3_cr,
input write0_cr,
input write1_cr,
input write2_cr,
input write3_cr,
input int0_cr,
input int1_cr,
input int2_cr,
input int3_cr,
input read0_cw,
input read1_cw,
input read2_cw,
input read3_cw,
output [31:0] data0_cw,
output [31:0] data1_cw,
output [31:0] data2_cw,
output [31:0] data3_cw,
input err0_cw,
input err1_cw,
input err2_cw,
input err3_cw,
output errack0_cw,
output errack1_cw,
output errack2_cw,
output errack3_cw,
output [23:0] ph_len_0,
output [23:0] ph_len_1,
output [23:0] ph_len_2,
output [23:0] ph_len_3,
output ph_dir_0,
output ph_dir_1,
output ph_dir_2,
output ph_dir_3,
output ph_enstb_0,
output ph_enstb_1,
output ph_enstb_2,
output ph_enstb_3);
assign mem_iODT = 1'b1;
assign mem_dODT = 1'b1;
reg rst_cpu_pre = 1'b0;
reg rst_cpu = 1'b0;
reg rst_i_mcu = 1'b0;
reg rst_d_mcu = 1'b0;
reg rst_lsab_in = 1'b0;
reg rst_lsab_out = 1'b0;
reg rst_soft_core = 1'b0;
reg [1:0] write_fifo_cr = 2'h2;
reg [1:0] read_fifo_cw = 2'h0;
wire w_read_cr, w_write_cw;
wire [1:0] w_read_fifo_cr, w_write_fifo_cw;
wire [24:0] w_anc1_0, w_anc1_1, w_anc1_2, w_anc1_3;
wire [24:0] w_ancill_cr;
wire [31:0] w_out_cr, w_in_cw;
wire w_s0_cr, w_s1_cr, w_s2_cr, w_s3_cr;
wire w_e0_cr, w_e1_cr, w_e2_cr, w_e3_cr;
wire w_i0_cr, w_i1_cr, w_i2_cr, w_i3_cr;
wire w_bfull_cw, w_err_cw, w_errack_cw;
wire [31:0] i_mcu_data_into, d_mcu_data_into;
wire [8:0] hf_coll_addr_fill, hf_coll_addr_empty, mcu_coll_addr;
wire [3:0] hf_we_array_fill;
wire i_hf_req_access_fill, d_hf_req_access_fill,
i_hf_req_access_empty, d_hf_req_access_empty;
wire w_issue, w_working_fill, w_working_empty;
wire [1:0] w_section;
wire [5:0] w_count_req, w_count_sent_fill, w_count_sent_empty;
wire [8:0] w_start_address;
wire w_irq_cr, w_abstop_cr, w_abstop_cw, w_deverr_cw;
wire [22:0] mcu_page_addr;
wire i_mcu_algn_req, i_mcu_algn_ack,
d_mcu_algn_req, d_mcu_algn_ack;
wire mvblck_RST_fill, mvblck_RST_empty;
reg i_mcu_req_access = 1'b0, d_mcu_req_access = 1'b0,
i_mcu_we = 1'b0, d_mcu_we = 1'b0;
assign mcu_coll_addr = hf_coll_addr_fill | hf_coll_addr_empty;
wire refresh_strobe;
wire w_careof_int;
wire [2:0] w_isel, w_osel;
wire res_irq;
wire [31:0] i_user_req_address;
wire i_user_req_we, i_user_req;
wire [3:0] i_user_we_array;
wire [31:0] i_user_req_datain;
wire i_user_req_ack;
wire [31:0] i_user_req_dataout;
wire [31:0] d_user_req_address;
wire d_user_req_we, d_user_req;
wire [3:0] d_user_we_array;
wire [31:0] d_user_req_datain;
wire d_user_req_ack;
wire [31:0] d_user_req_dataout;
wire cache_vmem, cache_inhibit;
wire d_dma_read, d_dma_wrte, d_dma_read_ack, d_dma_wrte_ack;
wire [31:0] d_dma_out;
reg irq_strobe = 1'b0, irq_strobe_slow = 1'b0,
irq_strobe_slow_prev = 1'b0;
ddr_memory_controler i_mcu(.CLK_n(CLK_n),
.CLK_dn(CLK_dn),
.RST_MASTER(rst_i_mcu),
.MEM_CLK_P(mem_iCLK_P),
.MEM_CLK_N(mem_iCLK_N),
.CKE(mem_iCKE),
.COMMAND(mem_iCOMMAND),
.ADDRESS(mem_iADDRESS),
.BANK(mem_iBANK),
.DQ(mem_iDQ),
.UDQS(mem_iUDQS),
.LDQS(mem_iLDQS),
.UDM(mem_iUDM),
.LDM(mem_iLDM),
.CS(mem_iCS),
.refresh_strobe(refresh_strobe),
.rand_req_address(i_user_req_address[25:0]),
.rand_req_we(i_user_req_we),
.rand_req_we_array(i_user_we_array),
.rand_req(i_user_req),
.rand_req_ack(i_user_req_ack),
.rand_req_datain(i_user_req_datain),
.bulk_req_address({mcu_page_addr[16:0],
mcu_coll_addr}),
.bulk_req_we(i_mcu_we),
.bulk_req_we_array(hf_we_array_fill),
.bulk_req(i_mcu_req_access),
.bulk_req_ack(),
.bulk_req_algn(i_mcu_algn_req),
.bulk_req_algn_ack(i_mcu_algn_ack),
.bulk_req_datain(i_mcu_data_into),
.user_req_dataout(i_user_req_dataout));
ddr_memory_controler d_mcu(.CLK_n(CLK_n),
.CLK_dn(CLK_dn),
.RST_MASTER(rst_d_mcu),
.MEM_CLK_P(mem_dCLK_P),
.MEM_CLK_N(mem_dCLK_N),
.CKE(mem_dCKE),
.COMMAND(mem_dCOMMAND),
.ADDRESS(mem_dADDRESS),
.BANK(mem_dBANK),
.DQ(mem_dDQ),
.UDQS(mem_dUDQS),
.LDQS(mem_dLDQS),
.UDM(mem_dUDM),
.LDM(mem_dLDM),
.CS(mem_dCS),
.refresh_strobe(refresh_strobe),
.rand_req_address(d_user_req_address[25:0]),
.rand_req_we(d_user_req_we),
.rand_req_we_array(d_user_we_array),
.rand_req(d_user_req),
.rand_req_ack(d_user_req_ack),
.rand_req_datain(d_user_req_datain),
.bulk_req_address({mcu_page_addr[16:0],
mcu_coll_addr}),
.bulk_req_we(d_mcu_we),
.bulk_req_we_array(hf_we_array_fill),
.bulk_req(d_mcu_req_access),
.bulk_req_ack(),
.bulk_req_algn(d_mcu_algn_req),
.bulk_req_algn_ack(d_mcu_algn_ack),
.bulk_req_datain(d_mcu_data_into),
.user_req_dataout(d_user_req_dataout));
wire i_cache_enable, d_cache_enable;
wire i_cache_busy, d_cache_busy;
wire [31:0] d_cache_datao, d_cache_datai,
i_cache_datai;
wire [31:0] i_cache_pc_addr;
wire [31:0] d_cache_pc_addr;
wire d_cache_we;
wire dcache_we_tlb, icache_we_tlb;
wire d_cache_force_miss;
snowball_cache i_cache(.CPU_CLK(CPU_CLK),
.MCU_CLK(CLK_n),
.cache_precycle_addr(i_cache_pc_addr),
.cache_datao(0),
.cache_datai(i_cache_datai),
.cache_precycle_we(1'b0),
.cache_busy(i_cache_busy),
.cache_precycle_enable(i_cache_enable),
.cache_precycle_force_miss(1'b0),
.mem_addr(i_user_req_address),
.mem_we(i_user_req_we),
.mem_we_array(i_user_we_array),
.mem_do_act(i_user_req),
.mem_dataintomem(i_user_req_datain),
.mem_ack(i_user_req_ack),
.mem_datafrommem(i_user_req_dataout),
.dma_wrte(),
.dma_read(),
.dma_wrte_ack(1'b0),
.dma_read_ack(1'b0),
.dma_data_read(32'd0),
.VMEM_ACT(cache_vmem),
.cache_inhibit(cache_inhibit),
.fake_miss(1'b0),
.MMU_FAULT(),
.WE_TLB(icache_we_tlb));
snowball_cache d_cache(.CPU_CLK(CPU_CLK),
.MCU_CLK(CLK_n),
.cache_precycle_addr(d_cache_pc_addr),
.cache_datao(d_cache_datao),
.cache_datai(d_cache_datai),
.cache_precycle_we(d_cache_we),
.cache_busy(d_cache_busy),
.cache_precycle_enable(d_cache_enable),
.cache_precycle_force_miss(d_cache_force_miss),
.mem_addr(d_user_req_address),
.mem_we(d_user_req_we),
.mem_we_array(d_user_we_array),
.mem_do_act(d_user_req),
.mem_dataintomem(d_user_req_datain),
.mem_ack(d_user_req_ack),
.mem_datafrommem(d_user_req_dataout),
.dma_wrte(d_dma_wrte),
.dma_read(d_dma_read),
.dma_wrte_ack(d_dma_wrte_ack),
.dma_read_ack(d_dma_read_ack),
.dma_data_read(d_dma_out),
.VMEM_ACT(cache_vmem),
.cache_inhibit(cache_inhibit),
.fake_miss(1'b0),
.MMU_FAULT(),
.WE_TLB(dcache_we_tlb));
aexm_edk32 cpu(.sys_clk_i(CPU_CLK),
.sys_rst_i(rst_cpu),
.sys_int_i(irq_strobe_slow ^ irq_strobe_slow_prev),
.aexm_icache_precycle_addr(i_cache_pc_addr),
.aexm_dcache_precycle_addr(d_cache_pc_addr),
.aexm_dcache_datao(d_cache_datao),
.aexm_dcache_precycle_we(d_cache_we),
.aexm_dcache_precycle_enable(d_cache_enable),
.aexm_icache_precycle_enable(i_cache_enable),
.aexm_dcache_we_tlb(dcache_we_tlb),
.aexm_icache_we_tlb(icache_we_tlb),
.aexm_dcache_force_miss(d_cache_force_miss),
.aexm_icache_datai(i_cache_datai),
.aexm_dcache_datai(d_cache_datai),
.aexm_icache_cache_busy(i_cache_busy),
.aexm_dcache_cache_busy(d_cache_busy));
trans_fast hyperfabric_switch(.CLK(CLK_n),
.out_0(i_mcu_data_into),
.out_1(d_mcu_data_into),
.out_2(w_in_cw),
.out_3(),
.out_4(), .out_5(),
.out_6(), .out_7(),
.in_0(i_user_req_dataout),
.in_1(d_user_req_dataout),
.in_2(w_out_cr),
.in_3(0),
.isel({5'h0,w_isel}),
.osel({8'hff,5'h0,w_osel}));
lsab_cr lsab_in(.CLK(CLK_n),
.RST(rst_lsab_in),
.READ(w_read_cr),
.WRITE0(write0_cr),
.WRITE1(write1_cr),
.WRITE2(write2_cr),
.WRITE3(write3_cr),
.READ_FIFO(w_read_fifo_cr),
.WRITE_FIFO(write_fifo_cr),
.IN_0(data0_cr), .IN_1(data1_cr),
.IN_2(data2_cr), .IN_3(data3_cr),
.INT_IN_0(int0_cr), .INT_IN_1(int1_cr),
.INT_IN_2(int2_cr), .INT_IN_3(int3_cr),
.CAREOF_INT_0(w_careof_int), .CAREOF_INT_1(w_careof_int),
.CAREOF_INT_2(w_careof_int), .CAREOF_INT_3(w_careof_int),
.ANCILL_IN_0(ancill0_cr), .ANCILL_IN_1(ancill1_cr),
.ANCILL_IN_2(ancill2_cr), .ANCILL_IN_3(ancill3_cr),
.OUT(w_out_cr),
.EMPTY_0(w_e0_cr), .EMPTY_1(w_e1_cr),
.EMPTY_2(w_e2_cr), .EMPTY_3(w_e3_cr),
.STOP_0(w_s0_cr), .STOP_1(w_s1_cr),
.STOP_2(w_s2_cr), .STOP_3(w_s3_cr),
.INT_OUT_0(w_i0_cr), .INT_OUT_1(w_i1_cr),
.INT_OUT_2(w_i2_cr), .INT_OUT_3(w_i3_cr),
.ANCILL_OUT_0(w_anc1_0), .ANCILL_OUT_1(w_anc1_1),
.ANCILL_OUT_2(w_anc1_2), .ANCILL_OUT_3(w_anc1_3));
hyper_mvblck_todram fill(.CLK(CLK_n),
.RST(mvblck_RST_fill),
.LSAB_0_INT(w_i0_cr),
.LSAB_1_INT(w_i1_cr),
.LSAB_2_INT(w_i2_cr),
.LSAB_3_INT(w_i3_cr),
.LSAB_0_STOP(w_s0_cr),
.LSAB_1_STOP(w_s1_cr),
.LSAB_2_STOP(w_s2_cr),
.LSAB_3_STOP(w_s3_cr),
.LSAB_0_ANCILL(w_anc1_0),
.LSAB_1_ANCILL(w_anc1_1),
.LSAB_2_ANCILL(w_anc1_2),
.LSAB_3_ANCILL(w_anc1_3),
.LSAB_READ(w_read_cr),
.LSAB_SECTION(w_read_fifo_cr),
.START_ADDRESS(w_start_address),
.COUNT_REQ(w_count_req),
.SECTION(w_section),
.DRAM_SEL({d_mcu_algn_req,i_mcu_algn_req}),
.ISSUE(w_issue),
.COUNT_SENT(w_count_sent_fill),
.WORKING(w_working_fill),
.IRQ_OUT(w_irq_cr),
.ABRUPT_STOP(w_abstop_cr),
.ANCILL_OUT(w_ancill_cr),
.MCU_COLL_ADDRESS(hf_coll_addr_fill),
.MCU_WE_ARRAY(hf_we_array_fill),
.MCU_REQUEST_ACCESS({d_hf_req_access_fill,
i_hf_req_access_fill}));
lsab_cw lsab_out(.CLK(CLK_n),
.RST(rst_lsab_out),
.READ0(read0_cw),
.READ1(read1_cw),
.READ2(read2_cw),
.READ3(read3_cw),
.WRITE(w_write_cw),
.READ_FIFO(read_fifo_cw),
.WRITE_FIFO(w_write_fifo_cw),
.IN(w_in_cw),
.OUT_0(data0_cw),
.OUT_1(data1_cw),
.OUT_2(data2_cw),
.OUT_3(data3_cw),
.BFULL(w_bfull_cw),
.DEV_0_ERR(err0_cw),
.DEV_1_ERR(err1_cw),
.DEV_2_ERR(err2_cw),
.DEV_3_ERR(err3_cw),
.DEV_0_ERR_ACK(errack0_cw),
.DEV_1_ERR_ACK(errack1_cw),
.DEV_2_ERR_ACK(errack2_cw),
.DEV_3_ERR_ACK(errack3_cw),
.DEVERR(w_err_cw),
.DEVERRACK(w_errack_cw));
hyper_mvblck_frdram empty(.CLK(CLK_n),
.RST(mvblck_RST_empty),
.LSAB_FULL(w_bfull_cw),
.LSAB_DEVERR(w_err_cw),
.LSAB_DEVERRACK(w_errack_cw),
.LSAB_WRITE(w_write_cw),
.LSAB_SECTION(w_write_fifo_cw),
.START_ADDRESS(w_start_address),
.COUNT_REQ(w_count_req),
.SECTION(w_section),
.DRAM_SEL({d_mcu_algn_req,i_mcu_algn_req}),
.ISSUE(w_issue),
.COUNT_SENT(w_count_sent_empty),
.WORKING(w_working_empty),
.ABRUPT_STOP(w_abstop_cw),
.DEVICE_ERROR(w_deverr_cw),
.MCU_COLL_ADDRESS(hf_coll_addr_empty),
.MCU_REQUEST_ACCESS({d_hf_req_access_empty,
i_hf_req_access_empty}));
Gremlin hyper_softcore(.CLK(CLK_n),
.RST(rst_soft_core),
.READ_CPU(d_dma_read),
.WRITE_CPU(d_dma_wrte),
.READ_CPU_ACK(d_dma_read_ack),
.WRITE_CPU_ACK(d_dma_wrte_ack),
.ADDR_CPU(d_user_req_address[2:0]),
.IN_CPU({d_user_req_datain,
d_user_req_address}),
.OUT_CPU(d_dma_out),
.IRQ_DESC(),
.IRQ(res_irq),
.RST_MVBLCK({mvblck_RST_fill,mvblck_RST_empty}),
.MCU_REFRESH_STROBE(refresh_strobe),
.SWCH_ISEL(w_isel),
.SWCH_OSEL(w_osel),
.CAREOF_INT(w_careof_int),
.BLCK_START(w_start_address),
.BLCK_COUNT_REQ(w_count_req),
.BLCK_ISSUE(w_issue),
.BLCK_SECTION(w_section),
.BLCK_COUNT_SENT(w_count_sent_fill |
w_count_sent_empty),
.BLCK_WORKING(w_working_fill | w_working_empty),
.BLCK_IRQ(w_irq_cr),
.BLCK_ABRUPT_STOP(w_abstop_cr || w_abstop_cw),
.BLCK_FRDRAM_DEVERR(w_deverr_cw),
.BLCK_ANCILL(w_ancill_cr),
.MCU_PAGE_ADDR(mcu_page_addr),
.MCU_REQUEST_ALIGN({d_mcu_algn_req,
i_mcu_algn_req}),
.MCU_GRANT_ALIGN({d_mcu_algn_ack,
i_mcu_algn_ack}),
.LEN_0(ph_len_0),
.DIR_0(ph_dir_0),
.EN_STB_0(ph_enstb_0),
.LEN_1(ph_len_1),
.DIR_1(ph_dir_1),
.EN_STB_1(ph_enstb_1),
.LEN_2(ph_len_2),
.DIR_2(ph_dir_2),
.EN_STB_2(ph_enstb_2),
.LEN_3(ph_len_3),
.DIR_3(ph_dir_3),
.EN_STB_3(ph_enstb_3));
assign cache_vmem = 1'b0;
assign cache_inhibit = 1'b0;
always @(posedge CLK_n)
if (RST_MASTER)
begin
write_fifo_cr <= write_fifo_cr +1;
read_fifo_cw <= read_fifo_cw +1;
if (res_irq)
irq_strobe <= !irq_strobe;
i_mcu_req_access <= i_hf_req_access_fill || i_hf_req_access_empty;
d_mcu_req_access <= d_hf_req_access_fill || d_hf_req_access_empty;
i_mcu_we <= i_hf_req_access_fill;
d_mcu_we <= d_hf_req_access_fill;
rst_i_mcu <= 1; rst_d_mcu <= 1;
rst_lsab_in <= 1; rst_lsab_out <= 1;
rst_soft_core <= 1;
end
always @(posedge CPU_CLK)
begin
rst_cpu_pre <= RST_CPU_TRANS;
rst_cpu <= rst_cpu_pre;
irq_strobe_slow <= irq_strobe;
irq_strobe_slow_prev <= irq_strobe_slow;
end
endmodule | module special_snowflake_core(input RST_MASTER,
input RST_CPU_TRANS,
input CLK_n,
input CLK_dn,
input CPU_CLK,
output mem_iCLK_P,
output mem_iCLK_N,
output mem_iCKE,
inout mem_iUDQS,
inout mem_iLDQS,
inout mem_iUDM,
inout mem_iLDM,
output mem_iCS,
output [2:0] mem_iCOMMAND,
output [13:0] mem_iADDRESS,
output [2:0] mem_iBANK,
inout [15:0] mem_iDQ,
output mem_iODT,
output mem_dCLK_P,
output mem_dCLK_N,
output mem_dCKE,
inout mem_dUDQS,
inout mem_dLDQS,
inout mem_dUDM,
inout mem_dLDM,
output mem_dCS,
output [2:0] mem_dCOMMAND,
output [13:0] mem_dADDRESS,
output [2:0] mem_dBANK,
inout [15:0] mem_dDQ,
output mem_dODT,
output [1:0] write_fifo_cr,
output [1:0] read_fifo_cw,
input [31:0] data0_cr,
input [31:0] data1_cr,
input [31:0] data2_cr,
input [31:0] data3_cr,
input [24:0] ancill0_cr,
input [24:0] ancill1_cr,
input [24:0] ancill2_cr,
input [24:0] ancill3_cr,
input write0_cr,
input write1_cr,
input write2_cr,
input write3_cr,
input int0_cr,
input int1_cr,
input int2_cr,
input int3_cr,
input read0_cw,
input read1_cw,
input read2_cw,
input read3_cw,
output [31:0] data0_cw,
output [31:0] data1_cw,
output [31:0] data2_cw,
output [31:0] data3_cw,
input err0_cw,
input err1_cw,
input err2_cw,
input err3_cw,
output errack0_cw,
output errack1_cw,
output errack2_cw,
output errack3_cw,
output [23:0] ph_len_0,
output [23:0] ph_len_1,
output [23:0] ph_len_2,
output [23:0] ph_len_3,
output ph_dir_0,
output ph_dir_1,
output ph_dir_2,
output ph_dir_3,
output ph_enstb_0,
output ph_enstb_1,
output ph_enstb_2,
output ph_enstb_3); |
assign mem_iODT = 1'b1;
assign mem_dODT = 1'b1;
reg rst_cpu_pre = 1'b0;
reg rst_cpu = 1'b0;
reg rst_i_mcu = 1'b0;
reg rst_d_mcu = 1'b0;
reg rst_lsab_in = 1'b0;
reg rst_lsab_out = 1'b0;
reg rst_soft_core = 1'b0;
reg [1:0] write_fifo_cr = 2'h2;
reg [1:0] read_fifo_cw = 2'h0;
wire w_read_cr, w_write_cw;
wire [1:0] w_read_fifo_cr, w_write_fifo_cw;
wire [24:0] w_anc1_0, w_anc1_1, w_anc1_2, w_anc1_3;
wire [24:0] w_ancill_cr;
wire [31:0] w_out_cr, w_in_cw;
wire w_s0_cr, w_s1_cr, w_s2_cr, w_s3_cr;
wire w_e0_cr, w_e1_cr, w_e2_cr, w_e3_cr;
wire w_i0_cr, w_i1_cr, w_i2_cr, w_i3_cr;
wire w_bfull_cw, w_err_cw, w_errack_cw;
wire [31:0] i_mcu_data_into, d_mcu_data_into;
wire [8:0] hf_coll_addr_fill, hf_coll_addr_empty, mcu_coll_addr;
wire [3:0] hf_we_array_fill;
wire i_hf_req_access_fill, d_hf_req_access_fill,
i_hf_req_access_empty, d_hf_req_access_empty;
wire w_issue, w_working_fill, w_working_empty;
wire [1:0] w_section;
wire [5:0] w_count_req, w_count_sent_fill, w_count_sent_empty;
wire [8:0] w_start_address;
wire w_irq_cr, w_abstop_cr, w_abstop_cw, w_deverr_cw;
wire [22:0] mcu_page_addr;
wire i_mcu_algn_req, i_mcu_algn_ack,
d_mcu_algn_req, d_mcu_algn_ack;
wire mvblck_RST_fill, mvblck_RST_empty;
reg i_mcu_req_access = 1'b0, d_mcu_req_access = 1'b0,
i_mcu_we = 1'b0, d_mcu_we = 1'b0;
assign mcu_coll_addr = hf_coll_addr_fill | hf_coll_addr_empty;
wire refresh_strobe;
wire w_careof_int;
wire [2:0] w_isel, w_osel;
wire res_irq;
wire [31:0] i_user_req_address;
wire i_user_req_we, i_user_req;
wire [3:0] i_user_we_array;
wire [31:0] i_user_req_datain;
wire i_user_req_ack;
wire [31:0] i_user_req_dataout;
wire [31:0] d_user_req_address;
wire d_user_req_we, d_user_req;
wire [3:0] d_user_we_array;
wire [31:0] d_user_req_datain;
wire d_user_req_ack;
wire [31:0] d_user_req_dataout;
wire cache_vmem, cache_inhibit;
wire d_dma_read, d_dma_wrte, d_dma_read_ack, d_dma_wrte_ack;
wire [31:0] d_dma_out;
reg irq_strobe = 1'b0, irq_strobe_slow = 1'b0,
irq_strobe_slow_prev = 1'b0;
ddr_memory_controler i_mcu(.CLK_n(CLK_n),
.CLK_dn(CLK_dn),
.RST_MASTER(rst_i_mcu),
.MEM_CLK_P(mem_iCLK_P),
.MEM_CLK_N(mem_iCLK_N),
.CKE(mem_iCKE),
.COMMAND(mem_iCOMMAND),
.ADDRESS(mem_iADDRESS),
.BANK(mem_iBANK),
.DQ(mem_iDQ),
.UDQS(mem_iUDQS),
.LDQS(mem_iLDQS),
.UDM(mem_iUDM),
.LDM(mem_iLDM),
.CS(mem_iCS),
.refresh_strobe(refresh_strobe),
.rand_req_address(i_user_req_address[25:0]),
.rand_req_we(i_user_req_we),
.rand_req_we_array(i_user_we_array),
.rand_req(i_user_req),
.rand_req_ack(i_user_req_ack),
.rand_req_datain(i_user_req_datain),
.bulk_req_address({mcu_page_addr[16:0],
mcu_coll_addr}),
.bulk_req_we(i_mcu_we),
.bulk_req_we_array(hf_we_array_fill),
.bulk_req(i_mcu_req_access),
.bulk_req_ack(),
.bulk_req_algn(i_mcu_algn_req),
.bulk_req_algn_ack(i_mcu_algn_ack),
.bulk_req_datain(i_mcu_data_into),
.user_req_dataout(i_user_req_dataout));
ddr_memory_controler d_mcu(.CLK_n(CLK_n),
.CLK_dn(CLK_dn),
.RST_MASTER(rst_d_mcu),
.MEM_CLK_P(mem_dCLK_P),
.MEM_CLK_N(mem_dCLK_N),
.CKE(mem_dCKE),
.COMMAND(mem_dCOMMAND),
.ADDRESS(mem_dADDRESS),
.BANK(mem_dBANK),
.DQ(mem_dDQ),
.UDQS(mem_dUDQS),
.LDQS(mem_dLDQS),
.UDM(mem_dUDM),
.LDM(mem_dLDM),
.CS(mem_dCS),
.refresh_strobe(refresh_strobe),
.rand_req_address(d_user_req_address[25:0]),
.rand_req_we(d_user_req_we),
.rand_req_we_array(d_user_we_array),
.rand_req(d_user_req),
.rand_req_ack(d_user_req_ack),
.rand_req_datain(d_user_req_datain),
.bulk_req_address({mcu_page_addr[16:0],
mcu_coll_addr}),
.bulk_req_we(d_mcu_we),
.bulk_req_we_array(hf_we_array_fill),
.bulk_req(d_mcu_req_access),
.bulk_req_ack(),
.bulk_req_algn(d_mcu_algn_req),
.bulk_req_algn_ack(d_mcu_algn_ack),
.bulk_req_datain(d_mcu_data_into),
.user_req_dataout(d_user_req_dataout));
wire i_cache_enable, d_cache_enable;
wire i_cache_busy, d_cache_busy;
wire [31:0] d_cache_datao, d_cache_datai,
i_cache_datai;
wire [31:0] i_cache_pc_addr;
wire [31:0] d_cache_pc_addr;
wire d_cache_we;
wire dcache_we_tlb, icache_we_tlb;
wire d_cache_force_miss;
snowball_cache i_cache(.CPU_CLK(CPU_CLK),
.MCU_CLK(CLK_n),
.cache_precycle_addr(i_cache_pc_addr),
.cache_datao(0),
.cache_datai(i_cache_datai),
.cache_precycle_we(1'b0),
.cache_busy(i_cache_busy),
.cache_precycle_enable(i_cache_enable),
.cache_precycle_force_miss(1'b0),
.mem_addr(i_user_req_address),
.mem_we(i_user_req_we),
.mem_we_array(i_user_we_array),
.mem_do_act(i_user_req),
.mem_dataintomem(i_user_req_datain),
.mem_ack(i_user_req_ack),
.mem_datafrommem(i_user_req_dataout),
.dma_wrte(),
.dma_read(),
.dma_wrte_ack(1'b0),
.dma_read_ack(1'b0),
.dma_data_read(32'd0),
.VMEM_ACT(cache_vmem),
.cache_inhibit(cache_inhibit),
.fake_miss(1'b0),
.MMU_FAULT(),
.WE_TLB(icache_we_tlb));
snowball_cache d_cache(.CPU_CLK(CPU_CLK),
.MCU_CLK(CLK_n),
.cache_precycle_addr(d_cache_pc_addr),
.cache_datao(d_cache_datao),
.cache_datai(d_cache_datai),
.cache_precycle_we(d_cache_we),
.cache_busy(d_cache_busy),
.cache_precycle_enable(d_cache_enable),
.cache_precycle_force_miss(d_cache_force_miss),
.mem_addr(d_user_req_address),
.mem_we(d_user_req_we),
.mem_we_array(d_user_we_array),
.mem_do_act(d_user_req),
.mem_dataintomem(d_user_req_datain),
.mem_ack(d_user_req_ack),
.mem_datafrommem(d_user_req_dataout),
.dma_wrte(d_dma_wrte),
.dma_read(d_dma_read),
.dma_wrte_ack(d_dma_wrte_ack),
.dma_read_ack(d_dma_read_ack),
.dma_data_read(d_dma_out),
.VMEM_ACT(cache_vmem),
.cache_inhibit(cache_inhibit),
.fake_miss(1'b0),
.MMU_FAULT(),
.WE_TLB(dcache_we_tlb));
aexm_edk32 cpu(.sys_clk_i(CPU_CLK),
.sys_rst_i(rst_cpu),
.sys_int_i(irq_strobe_slow ^ irq_strobe_slow_prev),
.aexm_icache_precycle_addr(i_cache_pc_addr),
.aexm_dcache_precycle_addr(d_cache_pc_addr),
.aexm_dcache_datao(d_cache_datao),
.aexm_dcache_precycle_we(d_cache_we),
.aexm_dcache_precycle_enable(d_cache_enable),
.aexm_icache_precycle_enable(i_cache_enable),
.aexm_dcache_we_tlb(dcache_we_tlb),
.aexm_icache_we_tlb(icache_we_tlb),
.aexm_dcache_force_miss(d_cache_force_miss),
.aexm_icache_datai(i_cache_datai),
.aexm_dcache_datai(d_cache_datai),
.aexm_icache_cache_busy(i_cache_busy),
.aexm_dcache_cache_busy(d_cache_busy));
trans_fast hyperfabric_switch(.CLK(CLK_n),
.out_0(i_mcu_data_into),
.out_1(d_mcu_data_into),
.out_2(w_in_cw),
.out_3(),
.out_4(), .out_5(),
.out_6(), .out_7(),
.in_0(i_user_req_dataout),
.in_1(d_user_req_dataout),
.in_2(w_out_cr),
.in_3(0),
.isel({5'h0,w_isel}),
.osel({8'hff,5'h0,w_osel}));
lsab_cr lsab_in(.CLK(CLK_n),
.RST(rst_lsab_in),
.READ(w_read_cr),
.WRITE0(write0_cr),
.WRITE1(write1_cr),
.WRITE2(write2_cr),
.WRITE3(write3_cr),
.READ_FIFO(w_read_fifo_cr),
.WRITE_FIFO(write_fifo_cr),
.IN_0(data0_cr), .IN_1(data1_cr),
.IN_2(data2_cr), .IN_3(data3_cr),
.INT_IN_0(int0_cr), .INT_IN_1(int1_cr),
.INT_IN_2(int2_cr), .INT_IN_3(int3_cr),
.CAREOF_INT_0(w_careof_int), .CAREOF_INT_1(w_careof_int),
.CAREOF_INT_2(w_careof_int), .CAREOF_INT_3(w_careof_int),
.ANCILL_IN_0(ancill0_cr), .ANCILL_IN_1(ancill1_cr),
.ANCILL_IN_2(ancill2_cr), .ANCILL_IN_3(ancill3_cr),
.OUT(w_out_cr),
.EMPTY_0(w_e0_cr), .EMPTY_1(w_e1_cr),
.EMPTY_2(w_e2_cr), .EMPTY_3(w_e3_cr),
.STOP_0(w_s0_cr), .STOP_1(w_s1_cr),
.STOP_2(w_s2_cr), .STOP_3(w_s3_cr),
.INT_OUT_0(w_i0_cr), .INT_OUT_1(w_i1_cr),
.INT_OUT_2(w_i2_cr), .INT_OUT_3(w_i3_cr),
.ANCILL_OUT_0(w_anc1_0), .ANCILL_OUT_1(w_anc1_1),
.ANCILL_OUT_2(w_anc1_2), .ANCILL_OUT_3(w_anc1_3));
hyper_mvblck_todram fill(.CLK(CLK_n),
.RST(mvblck_RST_fill),
.LSAB_0_INT(w_i0_cr),
.LSAB_1_INT(w_i1_cr),
.LSAB_2_INT(w_i2_cr),
.LSAB_3_INT(w_i3_cr),
.LSAB_0_STOP(w_s0_cr),
.LSAB_1_STOP(w_s1_cr),
.LSAB_2_STOP(w_s2_cr),
.LSAB_3_STOP(w_s3_cr),
.LSAB_0_ANCILL(w_anc1_0),
.LSAB_1_ANCILL(w_anc1_1),
.LSAB_2_ANCILL(w_anc1_2),
.LSAB_3_ANCILL(w_anc1_3),
.LSAB_READ(w_read_cr),
.LSAB_SECTION(w_read_fifo_cr),
.START_ADDRESS(w_start_address),
.COUNT_REQ(w_count_req),
.SECTION(w_section),
.DRAM_SEL({d_mcu_algn_req,i_mcu_algn_req}),
.ISSUE(w_issue),
.COUNT_SENT(w_count_sent_fill),
.WORKING(w_working_fill),
.IRQ_OUT(w_irq_cr),
.ABRUPT_STOP(w_abstop_cr),
.ANCILL_OUT(w_ancill_cr),
.MCU_COLL_ADDRESS(hf_coll_addr_fill),
.MCU_WE_ARRAY(hf_we_array_fill),
.MCU_REQUEST_ACCESS({d_hf_req_access_fill,
i_hf_req_access_fill}));
lsab_cw lsab_out(.CLK(CLK_n),
.RST(rst_lsab_out),
.READ0(read0_cw),
.READ1(read1_cw),
.READ2(read2_cw),
.READ3(read3_cw),
.WRITE(w_write_cw),
.READ_FIFO(read_fifo_cw),
.WRITE_FIFO(w_write_fifo_cw),
.IN(w_in_cw),
.OUT_0(data0_cw),
.OUT_1(data1_cw),
.OUT_2(data2_cw),
.OUT_3(data3_cw),
.BFULL(w_bfull_cw),
.DEV_0_ERR(err0_cw),
.DEV_1_ERR(err1_cw),
.DEV_2_ERR(err2_cw),
.DEV_3_ERR(err3_cw),
.DEV_0_ERR_ACK(errack0_cw),
.DEV_1_ERR_ACK(errack1_cw),
.DEV_2_ERR_ACK(errack2_cw),
.DEV_3_ERR_ACK(errack3_cw),
.DEVERR(w_err_cw),
.DEVERRACK(w_errack_cw));
hyper_mvblck_frdram empty(.CLK(CLK_n),
.RST(mvblck_RST_empty),
.LSAB_FULL(w_bfull_cw),
.LSAB_DEVERR(w_err_cw),
.LSAB_DEVERRACK(w_errack_cw),
.LSAB_WRITE(w_write_cw),
.LSAB_SECTION(w_write_fifo_cw),
.START_ADDRESS(w_start_address),
.COUNT_REQ(w_count_req),
.SECTION(w_section),
.DRAM_SEL({d_mcu_algn_req,i_mcu_algn_req}),
.ISSUE(w_issue),
.COUNT_SENT(w_count_sent_empty),
.WORKING(w_working_empty),
.ABRUPT_STOP(w_abstop_cw),
.DEVICE_ERROR(w_deverr_cw),
.MCU_COLL_ADDRESS(hf_coll_addr_empty),
.MCU_REQUEST_ACCESS({d_hf_req_access_empty,
i_hf_req_access_empty}));
Gremlin hyper_softcore(.CLK(CLK_n),
.RST(rst_soft_core),
.READ_CPU(d_dma_read),
.WRITE_CPU(d_dma_wrte),
.READ_CPU_ACK(d_dma_read_ack),
.WRITE_CPU_ACK(d_dma_wrte_ack),
.ADDR_CPU(d_user_req_address[2:0]),
.IN_CPU({d_user_req_datain,
d_user_req_address}),
.OUT_CPU(d_dma_out),
.IRQ_DESC(),
.IRQ(res_irq),
.RST_MVBLCK({mvblck_RST_fill,mvblck_RST_empty}),
.MCU_REFRESH_STROBE(refresh_strobe),
.SWCH_ISEL(w_isel),
.SWCH_OSEL(w_osel),
.CAREOF_INT(w_careof_int),
.BLCK_START(w_start_address),
.BLCK_COUNT_REQ(w_count_req),
.BLCK_ISSUE(w_issue),
.BLCK_SECTION(w_section),
.BLCK_COUNT_SENT(w_count_sent_fill |
w_count_sent_empty),
.BLCK_WORKING(w_working_fill | w_working_empty),
.BLCK_IRQ(w_irq_cr),
.BLCK_ABRUPT_STOP(w_abstop_cr || w_abstop_cw),
.BLCK_FRDRAM_DEVERR(w_deverr_cw),
.BLCK_ANCILL(w_ancill_cr),
.MCU_PAGE_ADDR(mcu_page_addr),
.MCU_REQUEST_ALIGN({d_mcu_algn_req,
i_mcu_algn_req}),
.MCU_GRANT_ALIGN({d_mcu_algn_ack,
i_mcu_algn_ack}),
.LEN_0(ph_len_0),
.DIR_0(ph_dir_0),
.EN_STB_0(ph_enstb_0),
.LEN_1(ph_len_1),
.DIR_1(ph_dir_1),
.EN_STB_1(ph_enstb_1),
.LEN_2(ph_len_2),
.DIR_2(ph_dir_2),
.EN_STB_2(ph_enstb_2),
.LEN_3(ph_len_3),
.DIR_3(ph_dir_3),
.EN_STB_3(ph_enstb_3));
assign cache_vmem = 1'b0;
assign cache_inhibit = 1'b0;
always @(posedge CLK_n)
if (RST_MASTER)
begin
write_fifo_cr <= write_fifo_cr +1;
read_fifo_cw <= read_fifo_cw +1;
if (res_irq)
irq_strobe <= !irq_strobe;
i_mcu_req_access <= i_hf_req_access_fill || i_hf_req_access_empty;
d_mcu_req_access <= d_hf_req_access_fill || d_hf_req_access_empty;
i_mcu_we <= i_hf_req_access_fill;
d_mcu_we <= d_hf_req_access_fill;
rst_i_mcu <= 1; rst_d_mcu <= 1;
rst_lsab_in <= 1; rst_lsab_out <= 1;
rst_soft_core <= 1;
end
always @(posedge CPU_CLK)
begin
rst_cpu_pre <= RST_CPU_TRANS;
rst_cpu <= rst_cpu_pre;
irq_strobe_slow <= irq_strobe;
irq_strobe_slow_prev <= irq_strobe_slow;
end
endmodule | 1 |
138,621 | data/full_repos/permissive/85002992/special_snowflake/core_eth.v | 85,002,992 | core_eth.v | v | 301 | 65 | [] | [] | [] | null | line:88: before: "," | null | 1: b"%Error: data/full_repos/permissive/85002992/special_snowflake/core_eth.v:85: Duplicate declaration of signal: 'SYS_RST'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg SYS_RST = 1'b0;\n ^~~~~~~\n data/full_repos/permissive/85002992/special_snowflake/core_eth.v:81: ... Location of original declaration\n output SYS_RST,\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 302,590 | module | module top_level(input REF_CLK,
output iCLK_P,
output iCLK_N,
output iCKE,
inout iUDQS,
inout iLDQS,
inout iUDM,
inout iLDM,
output iCS,
output [2:0] iCOMMAND,
output [13:0] iADDRESS,
output [2:0] iBANK,
inout [15:0] iDQ,
output iODT,
output dCLK_P,
output dCLK_N,
output dCKE,
inout dUDQS,
inout dLDQS,
inout dUDM,
inout dLDM,
output dCS,
output [2:0] dCOMMAND,
output [13:0] dADDRESS,
output [2:0] dBANK,
inout [15:0] dDQ,
output dODT,
input ETH_WIRE_RX,
output ETH_WIRE_TX);
wire SYS_RST, SYS_CLK, SYS_CLK_DELAYED, CPU_CLK;
clockblock the_clocks(.REF_CLK(REF_CLK),
.SYS_RST(SYS_RST),
.SYS_CLK(SYS_CLK),
.SYS_CLK_DELAYED(SYS_CLK_DELAYED),
.CPU_CLK(CPU_CLK));
chip the_chip(.RST(SYS_RST),
.CLK_n(SYS_CLK),
.CLK_dn(SYS_CLK_DELAYED),
.CPU_CLK(CPU_CLK),
.sampler_CLK(SYS_CLK),
.enc_CLK(REF_CLK),
.recv_CLK(REF_CLK),
.send_CLK(REF_CLK),
.iCLK_P(iCLK_P),
.iCLK_N(iCLK_N),
.iCKE(iCKE),
.iUDQS(iUDQS),
.iLDQS(iLDQS),
.iUDM(iUDM),
.iLDM(iLDM),
.iCS(iCS),
.iCOMMAND(iCOMMAND),
.iADDRESS(iADDRESS),
.iBANK(iBANK),
.iDQ(iDQ),
.iODT(iODT),
.dCLK_P(dCLK_P),
.dCLK_N(dCLK_N),
.dCKE(dCKE),
.dUDQS(dUDQS),
.dLDQS(dLDQS),
.dUDM(dUDM),
.dLDM(dLDM),
.dCS(dCS),
.dCOMMAND(dCOMMAND),
.dADDRESS(dADDRESS),
.dBANK(dBANK),
.dDQ(dDQ),
.dODT(dODT),
.ETH_WIRE_RX(ETH_WIRE_RX),
.ETH_WIRE_TX(ETH_WIRE_TX));
endmodule | module top_level(input REF_CLK,
output iCLK_P,
output iCLK_N,
output iCKE,
inout iUDQS,
inout iLDQS,
inout iUDM,
inout iLDM,
output iCS,
output [2:0] iCOMMAND,
output [13:0] iADDRESS,
output [2:0] iBANK,
inout [15:0] iDQ,
output iODT,
output dCLK_P,
output dCLK_N,
output dCKE,
inout dUDQS,
inout dLDQS,
inout dUDM,
inout dLDM,
output dCS,
output [2:0] dCOMMAND,
output [13:0] dADDRESS,
output [2:0] dBANK,
inout [15:0] dDQ,
output dODT,
input ETH_WIRE_RX,
output ETH_WIRE_TX); |
wire SYS_RST, SYS_CLK, SYS_CLK_DELAYED, CPU_CLK;
clockblock the_clocks(.REF_CLK(REF_CLK),
.SYS_RST(SYS_RST),
.SYS_CLK(SYS_CLK),
.SYS_CLK_DELAYED(SYS_CLK_DELAYED),
.CPU_CLK(CPU_CLK));
chip the_chip(.RST(SYS_RST),
.CLK_n(SYS_CLK),
.CLK_dn(SYS_CLK_DELAYED),
.CPU_CLK(CPU_CLK),
.sampler_CLK(SYS_CLK),
.enc_CLK(REF_CLK),
.recv_CLK(REF_CLK),
.send_CLK(REF_CLK),
.iCLK_P(iCLK_P),
.iCLK_N(iCLK_N),
.iCKE(iCKE),
.iUDQS(iUDQS),
.iLDQS(iLDQS),
.iUDM(iUDM),
.iLDM(iLDM),
.iCS(iCS),
.iCOMMAND(iCOMMAND),
.iADDRESS(iADDRESS),
.iBANK(iBANK),
.iDQ(iDQ),
.iODT(iODT),
.dCLK_P(dCLK_P),
.dCLK_N(dCLK_N),
.dCKE(dCKE),
.dUDQS(dUDQS),
.dLDQS(dLDQS),
.dUDM(dUDM),
.dLDM(dLDM),
.dCS(dCS),
.dCOMMAND(dCOMMAND),
.dADDRESS(dADDRESS),
.dBANK(dBANK),
.dDQ(dDQ),
.dODT(dODT),
.ETH_WIRE_RX(ETH_WIRE_RX),
.ETH_WIRE_TX(ETH_WIRE_TX));
endmodule | 1 |
138,622 | data/full_repos/permissive/85002992/special_snowflake/core_eth.v | 85,002,992 | core_eth.v | v | 301 | 65 | [] | [] | [] | null | line:88: before: "," | null | 1: b"%Error: data/full_repos/permissive/85002992/special_snowflake/core_eth.v:85: Duplicate declaration of signal: 'SYS_RST'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg SYS_RST = 1'b0;\n ^~~~~~~\n data/full_repos/permissive/85002992/special_snowflake/core_eth.v:81: ... Location of original declaration\n output SYS_RST,\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 302,590 | module | module clockblock(input REF_CLK,
output SYS_RST,
output SYS_CLK,
output SYS_CLK_DELAYED,
output CPU_CLK);
reg SYS_RST = 1'b0;
reg [7:0] long_counter_h = 8'h0, long_counter_l = 8'h0;
reg long_counter_o = 1'h0, pll_rst = 1'b0,
frst_rst_r = 1'b0, scnd_rst_r = 1'b0;
wire frst_rst, scnd_rst;
always @(posedge REF_CLK)
begin
pll_rst <= 1;
frst_rst_r <= frst_rst;
scnd_rst_r <= scnd_rst;
if (! (frst_rst_r && scnd_rst_r))
begin
long_counter_h <= 0;
long_counter_l <= 0;
long_counter_o <= 0;
end
else
begin
{long_counter_o,long_counter_l} <= long_counter_l +1;
if (long_counter_o)
long_counter_h <= long_counter_h +1;
if (long_counter_h == 8'hff)
SYS_RST <= 1;
end
end
ss_pll_0_01 pll_0(.REFERENCECLK(REF_CLK),
.PLLOUTCOREA(),
.PLLOUTCOREB(SYS_CLK_DELAYED),
.PLLOUTGLOBALA(SYS_CLK),
.PLLOUTGLOBALB(),
.RESET(pll_rst),
.LOCK(frst_rst));
ss_pll_1_03 pll_1(.REFERENCECLK(REF_CLK),
.PLLOUTCORE(CPU_CLK),
.PLLOUTGLOBAL(),
.RESET(pll_rst),
.LOCK(scnd_rst));
endmodule | module clockblock(input REF_CLK,
output SYS_RST,
output SYS_CLK,
output SYS_CLK_DELAYED,
output CPU_CLK); |
reg SYS_RST = 1'b0;
reg [7:0] long_counter_h = 8'h0, long_counter_l = 8'h0;
reg long_counter_o = 1'h0, pll_rst = 1'b0,
frst_rst_r = 1'b0, scnd_rst_r = 1'b0;
wire frst_rst, scnd_rst;
always @(posedge REF_CLK)
begin
pll_rst <= 1;
frst_rst_r <= frst_rst;
scnd_rst_r <= scnd_rst;
if (! (frst_rst_r && scnd_rst_r))
begin
long_counter_h <= 0;
long_counter_l <= 0;
long_counter_o <= 0;
end
else
begin
{long_counter_o,long_counter_l} <= long_counter_l +1;
if (long_counter_o)
long_counter_h <= long_counter_h +1;
if (long_counter_h == 8'hff)
SYS_RST <= 1;
end
end
ss_pll_0_01 pll_0(.REFERENCECLK(REF_CLK),
.PLLOUTCOREA(),
.PLLOUTCOREB(SYS_CLK_DELAYED),
.PLLOUTGLOBALA(SYS_CLK),
.PLLOUTGLOBALB(),
.RESET(pll_rst),
.LOCK(frst_rst));
ss_pll_1_03 pll_1(.REFERENCECLK(REF_CLK),
.PLLOUTCORE(CPU_CLK),
.PLLOUTGLOBAL(),
.RESET(pll_rst),
.LOCK(scnd_rst));
endmodule | 1 |
138,623 | data/full_repos/permissive/85002992/special_snowflake/core_eth.v | 85,002,992 | core_eth.v | v | 301 | 65 | [] | [] | [] | null | line:88: before: "," | null | 1: b"%Error: data/full_repos/permissive/85002992/special_snowflake/core_eth.v:85: Duplicate declaration of signal: 'SYS_RST'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg SYS_RST = 1'b0;\n ^~~~~~~\n data/full_repos/permissive/85002992/special_snowflake/core_eth.v:81: ... Location of original declaration\n output SYS_RST,\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 302,590 | module | module chip(input RST,
input CLK_n,
input CLK_dn,
input CPU_CLK,
input sampler_CLK,
input enc_CLK,
input recv_CLK,
input send_CLK,
output iCLK_P,
output iCLK_N,
output iCKE,
inout iUDQS,
inout iLDQS,
inout iUDM,
inout iLDM,
output iCS,
output [2:0] iCOMMAND,
output [13:0] iADDRESS,
output [2:0] iBANK,
inout [15:0] iDQ,
output iODT,
output dCLK_P,
output dCLK_N,
output dCKE,
inout dUDQS,
inout dLDQS,
inout dUDM,
inout dLDM,
output dCS,
output [2:0] dCOMMAND,
output [13:0] dADDRESS,
output [2:0] dBANK,
inout [15:0] dDQ,
output dODT,
input ETH_WIRE_RX,
output ETH_WIRE_TX);
reg [19:0] rst_counter = 20'h0;
wire [1:0] w_write_fifo_cr, w_read_fifo_cw;
wire RST_CPU_pre;
wire eth_read, eth_write, eth_irq, eth_irq_valid,
eth_collision, eth_collision_ack;
wire [31:0] eth_send_data, eth_recv_data;
wire eth_ctrl_enstb;
wire [31:0] eth_ctrl_dataout;
wire [23:0] eth_ctrl_datain_short;
assign RST_CPU_pre = rst_counter[19];
special_snowflake_core core(.RST_MASTER(RST),
.RST_CPU_TRANS(RST_CPU_pre),
.CLK_n(CLK_n),
.CLK_dn(CLK_dn),
.CPU_CLK(CPU_CLK),
.mem_iCLK_P(iCLK_P),
.mem_iCLK_N(iCLK_N),
.mem_iCKE(iCKE),
.mem_iUDQS(iUDQS),
.mem_iLDQS(iLDQS),
.mem_iUDM(iUDM),
.mem_iLDM(iLDM),
.mem_iCS(iCS),
.mem_iCOMMAND(iCOMMAND),
.mem_iADDRESS(iADDRESS),
.mem_iBANK(iBANK),
.mem_iDQ(iDQ),
.mem_iODT(iODT),
.mem_dCLK_P(dCLK_P),
.mem_dCLK_N(dCLK_N),
.mem_dCKE(dCKE),
.mem_dUDQS(dUDQS),
.mem_dLDQS(dLDQS),
.mem_dUDM(dUDM),
.mem_dLDM(dLDM),
.mem_dCS(dCS),
.mem_dCOMMAND(dCOMMAND),
.mem_dADDRESS(dADDRESS),
.mem_dBANK(dBANK),
.mem_dDQ(dDQ),
.mem_dODT(dODT),
.write_fifo_cr(w_write_fifo_cr),
.read_fifo_cw(w_read_fifo_cw),
.data0_cr(eth_recv_data),
.data1_cr(0),
.data2_cr(0),
.data3_cr(0),
.ancill0_cr({eth_ctrl_dataout[23:0],
eth_irq_valid}),
.ancill1_cr(0),
.ancill2_cr(0),
.ancill3_cr(0),
.write0_cr(eth_write),
.write1_cr(0),
.write2_cr(0),
.write3_cr(0),
.int0_cr(eth_irq),
.int1_cr(0),
.int2_cr(0),
.int3_cr(0),
.read0_cw(eth_read),
.read1_cw(0),
.read2_cw(0),
.read3_cw(0),
.data0_cw(eth_send_data),
.data1_cw(),
.data2_cw(),
.data3_cw(),
.err0_cw(eth_collision),
.err1_cw(0),
.err2_cw(0),
.err3_cw(0),
.errack0_cw(eth_collision_ack),
.errack1_cw(),
.errack2_cw(),
.errack3_cw(),
.ph_len_0(eth_ctrl_datain_short),
.ph_len_1(),
.ph_len_2(),
.ph_len_3(),
.ph_dir_0(),
.ph_enstb_0(eth_ctrl_enstb),
.ph_dir_1(),
.ph_enstb_1(),
.ph_dir_2(),
.ph_enstb_2(),
.ph_dir_3(),
.ph_enstb_3());
Steelhorse_Hyperfabric eth(.sampler_CLK(sampler_CLK),
.recv_CLK(recv_CLK),
.send_CLK(send_CLK),
.enc_CLK(enc_CLK),
.lsab_CLK(CLK_n),
.RST(RST),
.WIRE_RX(ETH_WIRE_RX),
.WIRE_TX(ETH_WIRE_TX),
.DATA_SEND(eth_send_data),
.LSAB_RECV_TURN(w_write_fifo_cr),
.LSAB_SEND_TURN(w_read_fifo_cw),
.DATA_RECV(eth_recv_data),
.WRITE_INTO_LSAB(eth_write),
.READ_FROM_LSAB(eth_read),
.IRQ(eth_irq),
.IRQ_VLD(eth_irq_valid),
.ERROR(eth_collision),
.ERROR_ACK(eth_collision_ack),
.RUN(eth_ctrl_enstb),
.INTRFC_DATAIN({8'h0,eth_ctrl_datain_short}),
.INTRFC_DATAOUT(eth_ctrl_dataout));
always @(posedge CPU_CLK)
if (!RST)
rst_counter <= 0;
else
if (!RST_CPU_pre)
rst_counter <= rst_counter +1;
endmodule | module chip(input RST,
input CLK_n,
input CLK_dn,
input CPU_CLK,
input sampler_CLK,
input enc_CLK,
input recv_CLK,
input send_CLK,
output iCLK_P,
output iCLK_N,
output iCKE,
inout iUDQS,
inout iLDQS,
inout iUDM,
inout iLDM,
output iCS,
output [2:0] iCOMMAND,
output [13:0] iADDRESS,
output [2:0] iBANK,
inout [15:0] iDQ,
output iODT,
output dCLK_P,
output dCLK_N,
output dCKE,
inout dUDQS,
inout dLDQS,
inout dUDM,
inout dLDM,
output dCS,
output [2:0] dCOMMAND,
output [13:0] dADDRESS,
output [2:0] dBANK,
inout [15:0] dDQ,
output dODT,
input ETH_WIRE_RX,
output ETH_WIRE_TX); |
reg [19:0] rst_counter = 20'h0;
wire [1:0] w_write_fifo_cr, w_read_fifo_cw;
wire RST_CPU_pre;
wire eth_read, eth_write, eth_irq, eth_irq_valid,
eth_collision, eth_collision_ack;
wire [31:0] eth_send_data, eth_recv_data;
wire eth_ctrl_enstb;
wire [31:0] eth_ctrl_dataout;
wire [23:0] eth_ctrl_datain_short;
assign RST_CPU_pre = rst_counter[19];
special_snowflake_core core(.RST_MASTER(RST),
.RST_CPU_TRANS(RST_CPU_pre),
.CLK_n(CLK_n),
.CLK_dn(CLK_dn),
.CPU_CLK(CPU_CLK),
.mem_iCLK_P(iCLK_P),
.mem_iCLK_N(iCLK_N),
.mem_iCKE(iCKE),
.mem_iUDQS(iUDQS),
.mem_iLDQS(iLDQS),
.mem_iUDM(iUDM),
.mem_iLDM(iLDM),
.mem_iCS(iCS),
.mem_iCOMMAND(iCOMMAND),
.mem_iADDRESS(iADDRESS),
.mem_iBANK(iBANK),
.mem_iDQ(iDQ),
.mem_iODT(iODT),
.mem_dCLK_P(dCLK_P),
.mem_dCLK_N(dCLK_N),
.mem_dCKE(dCKE),
.mem_dUDQS(dUDQS),
.mem_dLDQS(dLDQS),
.mem_dUDM(dUDM),
.mem_dLDM(dLDM),
.mem_dCS(dCS),
.mem_dCOMMAND(dCOMMAND),
.mem_dADDRESS(dADDRESS),
.mem_dBANK(dBANK),
.mem_dDQ(dDQ),
.mem_dODT(dODT),
.write_fifo_cr(w_write_fifo_cr),
.read_fifo_cw(w_read_fifo_cw),
.data0_cr(eth_recv_data),
.data1_cr(0),
.data2_cr(0),
.data3_cr(0),
.ancill0_cr({eth_ctrl_dataout[23:0],
eth_irq_valid}),
.ancill1_cr(0),
.ancill2_cr(0),
.ancill3_cr(0),
.write0_cr(eth_write),
.write1_cr(0),
.write2_cr(0),
.write3_cr(0),
.int0_cr(eth_irq),
.int1_cr(0),
.int2_cr(0),
.int3_cr(0),
.read0_cw(eth_read),
.read1_cw(0),
.read2_cw(0),
.read3_cw(0),
.data0_cw(eth_send_data),
.data1_cw(),
.data2_cw(),
.data3_cw(),
.err0_cw(eth_collision),
.err1_cw(0),
.err2_cw(0),
.err3_cw(0),
.errack0_cw(eth_collision_ack),
.errack1_cw(),
.errack2_cw(),
.errack3_cw(),
.ph_len_0(eth_ctrl_datain_short),
.ph_len_1(),
.ph_len_2(),
.ph_len_3(),
.ph_dir_0(),
.ph_enstb_0(eth_ctrl_enstb),
.ph_dir_1(),
.ph_enstb_1(),
.ph_dir_2(),
.ph_enstb_2(),
.ph_dir_3(),
.ph_enstb_3());
Steelhorse_Hyperfabric eth(.sampler_CLK(sampler_CLK),
.recv_CLK(recv_CLK),
.send_CLK(send_CLK),
.enc_CLK(enc_CLK),
.lsab_CLK(CLK_n),
.RST(RST),
.WIRE_RX(ETH_WIRE_RX),
.WIRE_TX(ETH_WIRE_TX),
.DATA_SEND(eth_send_data),
.LSAB_RECV_TURN(w_write_fifo_cr),
.LSAB_SEND_TURN(w_read_fifo_cw),
.DATA_RECV(eth_recv_data),
.WRITE_INTO_LSAB(eth_write),
.READ_FROM_LSAB(eth_read),
.IRQ(eth_irq),
.IRQ_VLD(eth_irq_valid),
.ERROR(eth_collision),
.ERROR_ACK(eth_collision_ack),
.RUN(eth_ctrl_enstb),
.INTRFC_DATAIN({8'h0,eth_ctrl_datain_short}),
.INTRFC_DATAOUT(eth_ctrl_dataout));
always @(posedge CPU_CLK)
if (!RST)
rst_counter <= 0;
else
if (!RST_CPU_pre)
rst_counter <= rst_counter +1;
endmodule | 1 |
138,645 | data/full_repos/permissive/85002992/test/sim.v | 85,002,992 | sim.v | v | 229 | 106 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/85002992/test/sim.v:4: Cannot find include file: ddr.v\n`include "ddr.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/ddr.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/ddr.v.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/ddr.v.sv\n ddr.v\n ddr.v.v\n ddr.v.sv\n obj_dir/ddr.v\n obj_dir/ddr.v.v\n obj_dir/ddr.v.sv\n%Error: data/full_repos/permissive/85002992/test/sim.v:5: Cannot find include file: ../mcu/commands.v\n`include "../mcu/commands.v" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/sim.v:6: Cannot find include file: ../mcu/state2.v\n`include "../mcu/state2.v" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/sim.v:7: Cannot find include file: ../mcu/initializer.v\n`include "../mcu/initializer.v" \n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/sim.v:8: Cannot find include file: ../mcu/integration2.v\n`include "../mcu/integration2.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/sim.v:75: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_n <= 0; CLK_p <= 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/sim.v:76: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_dp <= 1; CLK_dn <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/sim.v:77: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_n <= 1; CLK_p <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/sim.v:78: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_dp <= 0; CLK_dn <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/sim.v:92: Unsupported: Ignoring delay on this delayed statement.\n #14.875 RST <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/sim.v:94: Unsupported: Ignoring delay on this delayed statement.\n #400000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/sim.v:102: Unsupported: Ignoring delay on this delayed statement.\n #3867;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/sim.v:114: Unsupported: Ignoring delay on this delayed statement.\n #34;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/sim.v:115: Unsupported: Ignoring delay on this delayed statement.\n #32;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/sim.v:118: Unsupported: Ignoring delay on this delayed statement.\n #6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/sim.v:116: Unsupported: Ignoring delay on this delayed statement.\n#6\n^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/sim.v:120: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/sim.v:122: Unsupported: Ignoring delay on this delayed statement.\n #100 user_req_address <= 32\'h0010_1100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/sim.v:123: Unsupported: Ignoring delay on this delayed statement.\n #100 user_req_we <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/sim.v:125: Unsupported: Ignoring delay on this delayed statement.\n#100 $finish;\n^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/sim.v:126: Unsupported: Ignoring delay on this delayed statement.\n#64 $finish;\n^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/sim.v:129: Unsupported: Ignoring delay on this delayed statement.\n #20000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/sim.v:134: Unsupported: Ignoring delay on this delayed statement.\n #128;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/sim.v:137: Unsupported: Ignoring delay on this delayed statement.\n #20000;\n ^\n%Error: Exiting due to 5 error(s), 19 warning(s)\n' | 302,597 | module | module GlaDOS;
reg CLK_p, CLK_n, CLK_dp, CLK_dn, RST;
reg [31:0] counter, readcount, readcount2, readcount_r;
reg [31:0] data_read, transtest;
reg [26:0] user_req_address;
reg user_req_we, user_req;
reg [31:0] user_req_datain;
reg inhibit_ack;
wire user_req_ack;
wire [31:0] user_req_dataout;
reg rand_user_req;
wire CKE, DQS, DM, CS;
wire [2:0] COMMAND;
wire [12:0] ADDRESS;
wire [1:0] BANK;
wire [15:0] DQ;
ddr ddr_mem(.Clk(CLK_p),
.Clk_n(CLK_n),
.Cke(CKE),
.Cs_n(CS),
.Ras_n(COMMAND[2]),
.Cas_n(COMMAND[1]),
.We_n(COMMAND[0]),
.Ba(BANK),
.Addr(ADDRESS),
.Dm(DM),
.Dq(DQ),
.Dqs(DQS));
ddr_memory_controler ddr_mc(.CLK_n(CLK_n),
.CLK_p(CLK_p),
.CLK_dp(CLK_dp),
.CLK_dn(CLK_dn),
.RST(RST),
.CKE(CKE),
.COMMAND(COMMAND),
.ADDRESS(ADDRESS),
.BANK(BANK),
.DQ(DQ),
.DQS(DQS),
.DM(DM),
.CS(CS),
.rand_req_address(0),
.rand_req_we(1),
.rand_req_we_array(4'b1111),
.rand_req(rand_user_req),
.rand_req_ack(),
.bulk_req_address(user_req_address),
.bulk_req_we(user_req_we),
.bulk_req_we_array(4'b1111),
.bulk_req(user_req),
.bulk_req_ack(user_req_ack),
.bulk_req_algn(user_req),
.bulk_req_algn_ack(),
.user_req_datain(user_req_datain),
.user_req_dataout(user_req_dataout));
initial
forever
begin
#1.5 CLK_n <= 0; CLK_p <= 1;
#1.5 CLK_dp <= 1; CLK_dn <= 0;
#1.5 CLK_n <= 1; CLK_p <= 0;
#1.5 CLK_dp <= 0; CLK_dn <= 1;
end
initial
begin
RST <= 0;
inhibit_ack <= 0;
counter <= 0;
user_req_address <= 0;
user_req_we <= 1;
user_req <= 0;
user_req_datain <= 32'h5a5ab00b;
readcount_r <= 0;
rand_user_req <= 0;
#14.875 RST <= 1;
#400000;
#3867;
inhibit_ack <= 1;
user_req <= 1;
#34;
#32;
#6
#6;
user_req <= 1;
#100;
rand_user_req <= 1;
#100 user_req_address <= 32'h0010_1100;
#100 user_req_we <= 0;
#100 $finish;
#64 $finish;
#20000;
user_req <= 1;
user_req_we <= 0;
inhibit_ack <= 1;
#128;
user_req <= 0;
#20000;
$finish;
end
always @(posedge CLK_n)
begin
if (readcount || readcount2 || user_req)
if (user_req_ack)
begin
if (!inhibit_ack)
user_req <= 0;
readcount_r <= 0;
readcount <= 70;
if (readcount2 != 0)
begin
user_req <= 0;
readcount2 <= readcount -1;
end
end
else
begin
if (readcount != 0)
readcount <= readcount -1;
readcount_r <= readcount_r +1;
end
if (readcount2 != 0)
readcount2 <= readcount2 -1;
if (readcount_r == 3)
$display("__read: %x", user_req_dataout);
if ((readcount == 4) || (readcount2 == 4))
begin
$display("__read: %x", user_req_dataout);
end
end
always @(posedge CLK_dp)
transtest[31:16] <= DQ;
always @(posedge CLK_dn)
transtest[15:0] <= DQ;
endmodule | module GlaDOS; |
reg CLK_p, CLK_n, CLK_dp, CLK_dn, RST;
reg [31:0] counter, readcount, readcount2, readcount_r;
reg [31:0] data_read, transtest;
reg [26:0] user_req_address;
reg user_req_we, user_req;
reg [31:0] user_req_datain;
reg inhibit_ack;
wire user_req_ack;
wire [31:0] user_req_dataout;
reg rand_user_req;
wire CKE, DQS, DM, CS;
wire [2:0] COMMAND;
wire [12:0] ADDRESS;
wire [1:0] BANK;
wire [15:0] DQ;
ddr ddr_mem(.Clk(CLK_p),
.Clk_n(CLK_n),
.Cke(CKE),
.Cs_n(CS),
.Ras_n(COMMAND[2]),
.Cas_n(COMMAND[1]),
.We_n(COMMAND[0]),
.Ba(BANK),
.Addr(ADDRESS),
.Dm(DM),
.Dq(DQ),
.Dqs(DQS));
ddr_memory_controler ddr_mc(.CLK_n(CLK_n),
.CLK_p(CLK_p),
.CLK_dp(CLK_dp),
.CLK_dn(CLK_dn),
.RST(RST),
.CKE(CKE),
.COMMAND(COMMAND),
.ADDRESS(ADDRESS),
.BANK(BANK),
.DQ(DQ),
.DQS(DQS),
.DM(DM),
.CS(CS),
.rand_req_address(0),
.rand_req_we(1),
.rand_req_we_array(4'b1111),
.rand_req(rand_user_req),
.rand_req_ack(),
.bulk_req_address(user_req_address),
.bulk_req_we(user_req_we),
.bulk_req_we_array(4'b1111),
.bulk_req(user_req),
.bulk_req_ack(user_req_ack),
.bulk_req_algn(user_req),
.bulk_req_algn_ack(),
.user_req_datain(user_req_datain),
.user_req_dataout(user_req_dataout));
initial
forever
begin
#1.5 CLK_n <= 0; CLK_p <= 1;
#1.5 CLK_dp <= 1; CLK_dn <= 0;
#1.5 CLK_n <= 1; CLK_p <= 0;
#1.5 CLK_dp <= 0; CLK_dn <= 1;
end
initial
begin
RST <= 0;
inhibit_ack <= 0;
counter <= 0;
user_req_address <= 0;
user_req_we <= 1;
user_req <= 0;
user_req_datain <= 32'h5a5ab00b;
readcount_r <= 0;
rand_user_req <= 0;
#14.875 RST <= 1;
#400000;
#3867;
inhibit_ack <= 1;
user_req <= 1;
#34;
#32;
#6
#6;
user_req <= 1;
#100;
rand_user_req <= 1;
#100 user_req_address <= 32'h0010_1100;
#100 user_req_we <= 0;
#100 $finish;
#64 $finish;
#20000;
user_req <= 1;
user_req_we <= 0;
inhibit_ack <= 1;
#128;
user_req <= 0;
#20000;
$finish;
end
always @(posedge CLK_n)
begin
if (readcount || readcount2 || user_req)
if (user_req_ack)
begin
if (!inhibit_ack)
user_req <= 0;
readcount_r <= 0;
readcount <= 70;
if (readcount2 != 0)
begin
user_req <= 0;
readcount2 <= readcount -1;
end
end
else
begin
if (readcount != 0)
readcount <= readcount -1;
readcount_r <= readcount_r +1;
end
if (readcount2 != 0)
readcount2 <= readcount2 -1;
if (readcount_r == 3)
$display("__read: %x", user_req_dataout);
if ((readcount == 4) || (readcount2 == 4))
begin
$display("__read: %x", user_req_dataout);
end
end
always @(posedge CLK_dp)
transtest[31:16] <= DQ;
always @(posedge CLK_dn)
transtest[15:0] <= DQ;
endmodule | 1 |
138,649 | data/full_repos/permissive/85002992/test/test_cache2_continuum.v | 85,002,992 | test_cache2_continuum.v | v | 624 | 80 | [] | [] | [] | null | line:25: before: "&" | null | 1: b'%Error: data/full_repos/permissive/85002992/test/test_cache2_continuum.v:3: Cannot find include file: test_inc.v\n`include "test_inc.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/test_inc.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/test_inc.v.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/test_inc.v.sv\n test_inc.v\n test_inc.v.v\n test_inc.v.sv\n obj_dir/test_inc.v\n obj_dir/test_inc.v.v\n obj_dir/test_inc.v.sv\n%Error: data/full_repos/permissive/85002992/test/test_cache2_continuum.v:5: Cannot find include file: ../mcu/state2.v\n`include "../mcu/state2.v" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_cache2_continuum.v:6: Cannot find include file: ../mcu/initializer.v\n`include "../mcu/initializer.v" \n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_cache2_continuum.v:7: Cannot find include file: ../mcu/integration3.v\n`include "../mcu/integration3.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_cache2_continuum.v:9: Cannot find include file: ../cache/cpu_mcu2.v\n`include "../cache/cpu_mcu2.v" \n ^~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_cache2_continuum.v:442: Unsupported: Ignoring delay on this delayed statement.\n #1500 CLK_n <= 0; CLK_p <= 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_cache2_continuum.v:443: Unsupported: Ignoring delay on this delayed statement.\n #1500 CLK_dp <= 1; CLK_dn <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_cache2_continuum.v:444: Unsupported: Ignoring delay on this delayed statement.\n #1500 CLK_n <= 1; CLK_p <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_cache2_continuum.v:445: Unsupported: Ignoring delay on this delayed statement.\n #1500 CLK_dp <= 0; CLK_dn <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_cache2_continuum.v:450: Unsupported: Ignoring delay on this delayed statement.\n #1500;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_cache2_continuum.v:451: Unsupported: Ignoring delay on this delayed statement.\n #4500 CPU_CLK <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_cache2_continuum.v:452: Unsupported: Ignoring delay on this delayed statement.\n #3000 CPU_CLK <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_cache2_continuum.v:475: Unsupported: Ignoring delay on this delayed statement.\n #2304000 if (SYS_RST) refresh_strobe <= !refresh_strobe;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_cache2_continuum.v:483: Unsupported: Ignoring delay on this delayed statement.\n #14875 RST <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_cache2_continuum.v:484: Unsupported: Ignoring delay on this delayed statement.\n #400000000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_cache2_continuum.v:485: Unsupported: Ignoring delay on this delayed statement.\n #50000000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_cache2_continuum.v:486: Unsupported: Ignoring delay on this delayed statement.\n #50000000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_cache2_continuum.v:488: Unsupported: Ignoring delay on this delayed statement.\n #20000;\n ^\n%Error: Exiting due to 5 error(s), 13 warning(s)\n' | 302,605 | module | module testsuite(input CLK,
input RST,
input [31:0] counter,
input [31:0] cache_datai,
input cache_busy,
input mmu_fault,
output reg [31:0] cache_pc_addr,
output reg [31:0] cache_datao,
output reg cache_pc_we,
output reg cache_pc_en,
output reg we_tlb,
output fake_miss);
reg [31:0] test_addr[512:0], test_waittime[512:0],
test_datao[512:0], test_datai[512:0],
test_timeout[512:0],
test_fakemissb[512:0], test_fakemisse[512:0],
test_timeout_comp[512:0];
reg test_we[512:0], test_caredatai[512:0],
test_tlb[512:0];
reg [31:0] time_for_next_test, test_num, test_seen,
test_issued, test_num_delay,
fake_miss_begin, fake_miss_end;
reg just_issued_test;
wire time_to_test, waiting_for_result, fake_miss;
integer i;
initial
begin
i = 0;
test_addr[i] <= 32'h0000_0060;test_datao[i] <= 32'h5400_ff06;
test_we[i] <= 1'b1; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b0; test_datai[i] <= 32'h0000_0000;
test_timeout[i] <= 32'd20; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0030_0050;test_datao[i] <= 32'h5aff_ff05;
test_we[i] <= 1'b1; test_waittime[i] <=
(`delay + 32'h0000_0018);
test_caredatai[i] <= 1'b0; test_datai[i] <= 32'h5454_6901;
test_timeout[i] <= 32'd20; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0010;test_datao[i] <= 32'h5454_6901;
test_we[i] <= 1'b1; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b0; test_datai[i] <= 32'h0000_0000;
test_timeout[i] <= 32'd20; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0020;test_datao[i] <= 32'h5a5a_5402;
test_we[i] <= 1'b1; test_waittime[i] <=
(`delay + 32'h0000_0018);
test_caredatai[i] <= 1'b0; test_datai[i] <= 32'h5454_6901;
test_timeout[i] <= 32'd20; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0030;test_datao[i] <= 32'h5454_6903;
test_we[i] <= 1'b1; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b0; test_datai[i] <= 32'h0000_0000;
test_timeout[i] <= 32'd20; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0040;test_datao[i] <= 32'h5a5a_5404;
test_we[i] <= 1'b1; test_waittime[i] <=
(`delay + 32'h0000_0018);
test_caredatai[i] <= 1'b0; test_datai[i] <= 32'h5454_6901;
test_timeout[i] <= 32'd20; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0050;test_datao[i] <= 32'h5454_6905;
test_we[i] <= 1'b1; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b0; test_datai[i] <= 32'h0000_0000;
test_timeout[i] <= 32'd20; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0060;test_datao[i] <= 32'h5a5a_5406;
test_we[i] <= 1'b1; test_waittime[i] <=
(`delay + 32'h0000_0018);
test_caredatai[i] <= 1'b0; test_datai[i] <= 32'h5454_6901;
test_timeout[i] <= 32'd20; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0010;test_datao[i] <= 32'h5454_1400;
test_we[i] <= 1'b0; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5454_6901;
test_timeout[i] <= 32'd1; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0020;test_datao[i] <= 32'h5a5a_5402;
test_we[i] <= 1'b0; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5a5a_5402;
test_timeout[i] <= 32'd5; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0030;test_datao[i] <= 32'h5454_1400;
test_we[i] <= 1'b0; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5454_6903;
test_timeout[i] <= 32'd1; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0040;test_datao[i] <= 32'h5a5a_5402;
test_we[i] <= 1'b0; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5a5a_5404;
test_timeout[i] <= 32'd5; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0050;test_datao[i] <= 32'h5454_1400;
test_we[i] <= 1'b0; test_waittime[i] <=
(`delay);
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5454_6905;
test_timeout[i] <= 32'd3; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 0;
i = i +1;
test_addr[i] <= 32'h0000_0060;test_datao[i] <= 32'h5a5a_5402;
test_we[i] <= 1'b0; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5400_ff06;
test_timeout[i] <= 32'd14; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 0;
i = i +1;
test_addr[i] <= 32'h0020_0010;test_datao[i] <= 32'h5454_1400;
test_we[i] <= 1'b0; test_waittime[i] <=
(`delay + 32'd13);
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5454_6901;
test_timeout[i] <= 32'd14; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0020;test_datao[i] <= 32'h5a5a_5402;
test_we[i] <= 1'b0; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5a5a_5402;
test_timeout[i] <= 32'd5; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0030;test_datao[i] <= 32'h5454_1400;
test_we[i] <= 1'b0; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5454_6903;
test_timeout[i] <= 32'd1; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0040;test_datao[i] <= 32'h5a5a_5402;
test_we[i] <= 1'b0; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5a5a_5404;
test_timeout[i] <= 32'd5; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0050;test_datao[i] <= 32'h5454_1400;
test_we[i] <= 1'b0; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5454_6905;
test_timeout[i] <= 32'd1; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0060;test_datao[i] <= 32'h5a5a_5402;
test_we[i] <= 1'b0; test_waittime[i] <=
(`delay + 32'hff00_0000);
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5a5a_5406;
test_timeout[i] <= 32'd14; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
end
end
always @(posedge CLK_n)
if (!SYS_RST)
begin
minicounter <= 0;
end
else
begin
minicounter <= minicounter +1;
end
testsuite test_unit(.CLK(CPU_CLK),
.RST(RST),
.counter(counter),
.cache_datai(cache_datai),
.cache_busy(cache_busy),
.mmu_fault(),
.cache_pc_addr(test_cache_addr),
.cache_datao(test_cache_datao),
.cache_pc_we(test_cache_we),
.cache_pc_en(test_cache_en),
.we_tlb(test_cache_we_tlb),
.fake_miss(test_fake_miss));
integer i;
initial
begin
for (i=0;i<256;i=i+1)
begin
if (i == 1)
cache_under_test.cachedat.ram.r_data[i] <= 32'h5a5a0000;
else
cache_under_test.cachedat.ram.r_data[i] <= 32'h5a5adada;
cache_under_test.cachetag.ram.r_data[i] <= 0;
cache_under_test.tlb.ram.r_data[i] <= 0;
cache_under_test.tlbtag.ram.r_data[i] <= 0;
end
cache_under_test.tlbtag.ram.r_data[16] <= 16'h018f;
cache_under_test.tlbtag.ram.r_data[32] <= 16'h0178;
cache_under_test.tlbtag.ram.r_data[48] <= 16'h0282;
cache_under_test.tlbtag.ram.r_data[4] <= 16'h0100;
end
endmodule | module testsuite(input CLK,
input RST,
input [31:0] counter,
input [31:0] cache_datai,
input cache_busy,
input mmu_fault,
output reg [31:0] cache_pc_addr,
output reg [31:0] cache_datao,
output reg cache_pc_we,
output reg cache_pc_en,
output reg we_tlb,
output fake_miss); |
reg [31:0] test_addr[512:0], test_waittime[512:0],
test_datao[512:0], test_datai[512:0],
test_timeout[512:0],
test_fakemissb[512:0], test_fakemisse[512:0],
test_timeout_comp[512:0];
reg test_we[512:0], test_caredatai[512:0],
test_tlb[512:0];
reg [31:0] time_for_next_test, test_num, test_seen,
test_issued, test_num_delay,
fake_miss_begin, fake_miss_end;
reg just_issued_test;
wire time_to_test, waiting_for_result, fake_miss;
integer i;
initial
begin
i = 0;
test_addr[i] <= 32'h0000_0060;test_datao[i] <= 32'h5400_ff06;
test_we[i] <= 1'b1; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b0; test_datai[i] <= 32'h0000_0000;
test_timeout[i] <= 32'd20; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0030_0050;test_datao[i] <= 32'h5aff_ff05;
test_we[i] <= 1'b1; test_waittime[i] <=
(`delay + 32'h0000_0018);
test_caredatai[i] <= 1'b0; test_datai[i] <= 32'h5454_6901;
test_timeout[i] <= 32'd20; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0010;test_datao[i] <= 32'h5454_6901;
test_we[i] <= 1'b1; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b0; test_datai[i] <= 32'h0000_0000;
test_timeout[i] <= 32'd20; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0020;test_datao[i] <= 32'h5a5a_5402;
test_we[i] <= 1'b1; test_waittime[i] <=
(`delay + 32'h0000_0018);
test_caredatai[i] <= 1'b0; test_datai[i] <= 32'h5454_6901;
test_timeout[i] <= 32'd20; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0030;test_datao[i] <= 32'h5454_6903;
test_we[i] <= 1'b1; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b0; test_datai[i] <= 32'h0000_0000;
test_timeout[i] <= 32'd20; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0040;test_datao[i] <= 32'h5a5a_5404;
test_we[i] <= 1'b1; test_waittime[i] <=
(`delay + 32'h0000_0018);
test_caredatai[i] <= 1'b0; test_datai[i] <= 32'h5454_6901;
test_timeout[i] <= 32'd20; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0050;test_datao[i] <= 32'h5454_6905;
test_we[i] <= 1'b1; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b0; test_datai[i] <= 32'h0000_0000;
test_timeout[i] <= 32'd20; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0060;test_datao[i] <= 32'h5a5a_5406;
test_we[i] <= 1'b1; test_waittime[i] <=
(`delay + 32'h0000_0018);
test_caredatai[i] <= 1'b0; test_datai[i] <= 32'h5454_6901;
test_timeout[i] <= 32'd20; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0010;test_datao[i] <= 32'h5454_1400;
test_we[i] <= 1'b0; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5454_6901;
test_timeout[i] <= 32'd1; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0020;test_datao[i] <= 32'h5a5a_5402;
test_we[i] <= 1'b0; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5a5a_5402;
test_timeout[i] <= 32'd5; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0030;test_datao[i] <= 32'h5454_1400;
test_we[i] <= 1'b0; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5454_6903;
test_timeout[i] <= 32'd1; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0040;test_datao[i] <= 32'h5a5a_5402;
test_we[i] <= 1'b0; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5a5a_5404;
test_timeout[i] <= 32'd5; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0050;test_datao[i] <= 32'h5454_1400;
test_we[i] <= 1'b0; test_waittime[i] <=
(`delay);
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5454_6905;
test_timeout[i] <= 32'd3; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 0;
i = i +1;
test_addr[i] <= 32'h0000_0060;test_datao[i] <= 32'h5a5a_5402;
test_we[i] <= 1'b0; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5400_ff06;
test_timeout[i] <= 32'd14; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 0;
i = i +1;
test_addr[i] <= 32'h0020_0010;test_datao[i] <= 32'h5454_1400;
test_we[i] <= 1'b0; test_waittime[i] <=
(`delay + 32'd13);
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5454_6901;
test_timeout[i] <= 32'd14; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0020;test_datao[i] <= 32'h5a5a_5402;
test_we[i] <= 1'b0; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5a5a_5402;
test_timeout[i] <= 32'd5; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0030;test_datao[i] <= 32'h5454_1400;
test_we[i] <= 1'b0; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5454_6903;
test_timeout[i] <= 32'd1; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0040;test_datao[i] <= 32'h5a5a_5402;
test_we[i] <= 1'b0; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5a5a_5404;
test_timeout[i] <= 32'd5; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0050;test_datao[i] <= 32'h5454_1400;
test_we[i] <= 1'b0; test_waittime[i] <= `delay;
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5454_6905;
test_timeout[i] <= 32'd1; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
test_addr[i] <= 32'h0020_0060;test_datao[i] <= 32'h5a5a_5402;
test_we[i] <= 1'b0; test_waittime[i] <=
(`delay + 32'hff00_0000);
test_caredatai[i] <= 1'b1; test_datai[i] <= 32'h5a5a_5406;
test_timeout[i] <= 32'd14; test_tlb[i] <= 1'b0;
test_fakemissb[i] <= 32'd0; test_fakemisse[i] <= 32'd0;
i = i +1;
end
end
always @(posedge CLK_n)
if (!SYS_RST)
begin
minicounter <= 0;
end
else
begin
minicounter <= minicounter +1;
end
testsuite test_unit(.CLK(CPU_CLK),
.RST(RST),
.counter(counter),
.cache_datai(cache_datai),
.cache_busy(cache_busy),
.mmu_fault(),
.cache_pc_addr(test_cache_addr),
.cache_datao(test_cache_datao),
.cache_pc_we(test_cache_we),
.cache_pc_en(test_cache_en),
.we_tlb(test_cache_we_tlb),
.fake_miss(test_fake_miss));
integer i;
initial
begin
for (i=0;i<256;i=i+1)
begin
if (i == 1)
cache_under_test.cachedat.ram.r_data[i] <= 32'h5a5a0000;
else
cache_under_test.cachedat.ram.r_data[i] <= 32'h5a5adada;
cache_under_test.cachetag.ram.r_data[i] <= 0;
cache_under_test.tlb.ram.r_data[i] <= 0;
cache_under_test.tlbtag.ram.r_data[i] <= 0;
end
cache_under_test.tlbtag.ram.r_data[16] <= 16'h018f;
cache_under_test.tlbtag.ram.r_data[32] <= 16'h0178;
cache_under_test.tlbtag.ram.r_data[48] <= 16'h0282;
cache_under_test.tlbtag.ram.r_data[4] <= 16'h0100;
end
endmodule | 1 |
138,659 | data/full_repos/permissive/85002992/test/test_inc.v | 85,002,992 | test_inc.v | v | 98 | 49 | [] | [] | [] | null | line:23: before: "&" | null | 1: b'%Error: data/full_repos/permissive/85002992/test/test_inc.v:97: Cannot find include file: ddr2.v\n`include "ddr2.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/ddr2.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/ddr2.v.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/ddr2.v.sv\n ddr2.v\n ddr2.v.v\n ddr2.v.sv\n obj_dir/ddr2.v\n obj_dir/ddr2.v.v\n obj_dir/ddr2.v.sv\n%Error: data/full_repos/permissive/85002992/test/test_inc.v:23: syntax error, unexpected \'&\', expecting \')\' or \',\' or or\n always @(posedge ClockA & ClockEnA)\n ^\n%Error: data/full_repos/permissive/85002992/test/test_inc.v:28: syntax error, unexpected <=, expecting IDENTIFIER\n QA <= r_data[AddressA];\n ^~\n%Error: data/full_repos/permissive/85002992/test/test_inc.v:36: syntax error, unexpected <=, expecting IDENTIFIER\n QB <= r_data[AddressB];\n ^~\n%Error: Exiting due to 4 error(s)\n' | 302,620 | module | module ram_dp_true_m(input [31:0] DataInA,
input [31:0] DataInB,
input [7:0] AddressA,
input [7:0] AddressB,
input REnA,
input REnB,
input ClockA,
input ClockB,
input ClockEnA,
input ClockEnB,
input WrA,
input WrB,
output reg [31:0] QA,
output reg [31:0] QB);
reg [31:0] r_data[255:0];
always @(posedge ClockA & ClockEnA)
begin
if (WrA)
r_data[AddressA] <= DataInA;
if (REnA)
QA <= r_data[AddressA];
end
always @(posedge ClockB & ClockEnB)
begin
if (WrB)
r_data[AddressB] <= DataInB;
if (REnB)
QB <= r_data[AddressB];
end
endmodule | module ram_dp_true_m(input [31:0] DataInA,
input [31:0] DataInB,
input [7:0] AddressA,
input [7:0] AddressB,
input REnA,
input REnB,
input ClockA,
input ClockB,
input ClockEnA,
input ClockEnB,
input WrA,
input WrB,
output reg [31:0] QA,
output reg [31:0] QB); |
reg [31:0] r_data[255:0];
always @(posedge ClockA & ClockEnA)
begin
if (WrA)
r_data[AddressA] <= DataInA;
if (REnA)
QA <= r_data[AddressA];
end
always @(posedge ClockB & ClockEnB)
begin
if (WrB)
r_data[AddressB] <= DataInB;
if (REnB)
QB <= r_data[AddressB];
end
endmodule | 1 |
138,660 | data/full_repos/permissive/85002992/test/test_inc.v | 85,002,992 | test_inc.v | v | 98 | 49 | [] | [] | [] | null | line:23: before: "&" | null | 1: b'%Error: data/full_repos/permissive/85002992/test/test_inc.v:97: Cannot find include file: ddr2.v\n`include "ddr2.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/ddr2.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/ddr2.v.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/ddr2.v.sv\n ddr2.v\n ddr2.v.v\n ddr2.v.sv\n obj_dir/ddr2.v\n obj_dir/ddr2.v.v\n obj_dir/ddr2.v.sv\n%Error: data/full_repos/permissive/85002992/test/test_inc.v:23: syntax error, unexpected \'&\', expecting \')\' or \',\' or or\n always @(posedge ClockA & ClockEnA)\n ^\n%Error: data/full_repos/permissive/85002992/test/test_inc.v:28: syntax error, unexpected <=, expecting IDENTIFIER\n QA <= r_data[AddressA];\n ^~\n%Error: data/full_repos/permissive/85002992/test/test_inc.v:36: syntax error, unexpected <=, expecting IDENTIFIER\n QB <= r_data[AddressB];\n ^~\n%Error: Exiting due to 4 error(s)\n' | 302,620 | module | module iceram32(output [31:0] RDATA,
input [7:0] RADDR,
input RE,
input RCLKE,
input RCLK,
input [31:0] WDATA,
input [31:0] MASK,
input [7:0] WADDR,
input WE,
input WCLKE,
input WCLK);
ram_dp_true_m ram(.DataInA(),
.DataInB(WDATA),
.AddressA(RADDR),
.AddressB(WADDR),
.REnA(RE),
.REnB(1'b0),
.ClockA(RCLK),
.ClockB(WCLK),
.ClockEnA(RCLKE),
.ClockEnB(WCLKE),
.WrA(1'b0),
.WrB(WE),
.QA(RDATA),
.QB());
endmodule | module iceram32(output [31:0] RDATA,
input [7:0] RADDR,
input RE,
input RCLKE,
input RCLK,
input [31:0] WDATA,
input [31:0] MASK,
input [7:0] WADDR,
input WE,
input WCLKE,
input WCLK); |
ram_dp_true_m ram(.DataInA(),
.DataInB(WDATA),
.AddressA(RADDR),
.AddressB(WADDR),
.REnA(RE),
.REnB(1'b0),
.ClockA(RCLK),
.ClockB(WCLK),
.ClockEnA(RCLKE),
.ClockEnB(WCLKE),
.WrA(1'b0),
.WrB(WE),
.QA(RDATA),
.QB());
endmodule | 1 |
138,661 | data/full_repos/permissive/85002992/test/test_inc.v | 85,002,992 | test_inc.v | v | 98 | 49 | [] | [] | [] | null | line:23: before: "&" | null | 1: b'%Error: data/full_repos/permissive/85002992/test/test_inc.v:97: Cannot find include file: ddr2.v\n`include "ddr2.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/ddr2.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/ddr2.v.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/ddr2.v.sv\n ddr2.v\n ddr2.v.v\n ddr2.v.sv\n obj_dir/ddr2.v\n obj_dir/ddr2.v.v\n obj_dir/ddr2.v.sv\n%Error: data/full_repos/permissive/85002992/test/test_inc.v:23: syntax error, unexpected \'&\', expecting \')\' or \',\' or or\n always @(posedge ClockA & ClockEnA)\n ^\n%Error: data/full_repos/permissive/85002992/test/test_inc.v:28: syntax error, unexpected <=, expecting IDENTIFIER\n QA <= r_data[AddressA];\n ^~\n%Error: data/full_repos/permissive/85002992/test/test_inc.v:36: syntax error, unexpected <=, expecting IDENTIFIER\n QB <= r_data[AddressB];\n ^~\n%Error: Exiting due to 4 error(s)\n' | 302,620 | module | module iceram16(output [15:0] RDATA,
input [7:0] RADDR,
input RE,
input RCLKE,
input RCLK,
input [15:0] WDATA,
input [15:0] MASK,
input [7:0] WADDR,
input WE,
input WCLKE,
input WCLK);
wire [15:0] ignore;
ram_dp_true_m ram(.DataInA(),
.DataInB({16'd0,WDATA}),
.AddressA(RADDR),
.AddressB(WADDR),
.REnA(RE),
.REnB(1'b0),
.ClockA(RCLK),
.ClockB(WCLK),
.ClockEnA(RCLKE),
.ClockEnB(WCLKE),
.WrA(1'b0),
.WrB(WE),
.QA({ignore,RDATA}),
.QB());
endmodule | module iceram16(output [15:0] RDATA,
input [7:0] RADDR,
input RE,
input RCLKE,
input RCLK,
input [15:0] WDATA,
input [15:0] MASK,
input [7:0] WADDR,
input WE,
input WCLKE,
input WCLK); |
wire [15:0] ignore;
ram_dp_true_m ram(.DataInA(),
.DataInB({16'd0,WDATA}),
.AddressA(RADDR),
.AddressB(WADDR),
.REnA(RE),
.REnB(1'b0),
.ClockA(RCLK),
.ClockB(WCLK),
.ClockEnA(RCLKE),
.ClockEnB(WCLKE),
.WrA(1'b0),
.WrB(WE),
.QA({ignore,RDATA}),
.QB());
endmodule | 1 |
138,662 | data/full_repos/permissive/85002992/test/test_lsab_cr.v | 85,002,992 | test_lsab_cr.v | v | 428 | 71 | [] | [] | [] | null | line:25: before: "&" | null | 1: b'%Error: data/full_repos/permissive/85002992/test/test_lsab_cr.v:3: Cannot find include file: test_inc.v\n`include "test_inc.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/test_inc.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/test_inc.v.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/test_inc.v.sv\n test_inc.v\n test_inc.v.v\n test_inc.v.sv\n obj_dir/test_inc.v\n obj_dir/test_inc.v.v\n obj_dir/test_inc.v.sv\n%Error: data/full_repos/permissive/85002992/test/test_lsab_cr.v:6: Cannot find include file: ../mcu/commands.v\n`include "../mcu/commands.v" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_lsab_cr.v:7: Cannot find include file: ../mcu/state2.v\n`include "../mcu/state2.v" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_lsab_cr.v:8: Cannot find include file: ../mcu/initializer.v\n`include "../mcu/initializer.v" \n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_lsab_cr.v:9: Cannot find include file: ../mcu/integration2.v\n`include "../mcu/integration2.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_lsab_cr.v:12: Cannot find include file: ../cache/cpu_mcu2.v\n`include "../cache/cpu_mcu2.v" \n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_lsab_cr.v:15: Cannot find include file: ../hyperfabric/lsab.v\n`include "../hyperfabric/lsab.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_lsab_cr.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_n <= 0; CLK_p <= 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_lsab_cr.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_dp <= 1; CLK_dn <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_lsab_cr.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_n <= 1; CLK_p <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_lsab_cr.v:269: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_dp <= 0; CLK_dn <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_lsab_cr.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1.5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_lsab_cr.v:275: Unsupported: Ignoring delay on this delayed statement.\n #4.5 CPU_CLK <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_lsab_cr.v:276: Unsupported: Ignoring delay on this delayed statement.\n #3 CPU_CLK <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_lsab_cr.v:398: Unsupported: Ignoring delay on this delayed statement.\n #14.34 RST <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_lsab_cr.v:399: Unsupported: Ignoring delay on this delayed statement.\n #18432;\n ^\n%Error: Exiting due to 7 error(s), 9 warning(s)\n' | 302,640 | module | module test_drv(input CLK,
input RST,
output reg [31:0] DATA0,
output reg [31:0] DATA1,
output reg [31:0] DATA2,
output reg [31:0] DATA3,
output WRITE,
output [1:0] WRITE_FIFO,
output INT0,
output INT1,
output INT2,
output INT3,
output READ,
output [1:0] READ_FIFO,
output CAREOF_INT_0,
output CAREOF_INT_1,
output CAREOF_INT_2,
output CAREOF_INT_3,
input [3:0] RES_EMPTY,
input [3:0] RES_STOP,
input [31:0] RES_DATA);
reg [31:0] test_data[4095:0],
reg_data[4095:0];
reg [3:0] test_care[4095:0],
reg_empty[4095:0],
reg_stop[4095:0];
reg [2:0] reg_careof[4095:0];
reg [1:0] test_rfifo[4095:0];
reg test_we[4095:0],
test_re[4095:0],
test_int[4095:0],
r_read_0, r_read_1;
reg [1:0] fast_i;
reg [2:0] r_careof;
reg [9:0] slow_i;
reg [11:0] c, out_c_0, out_c_1;
wire [31:0] wDATA0, wDATA1, wDATA2, wDATA3;
wire [31:0] w_data;
wire [3:0] w_stop, w_empty;
wire [2:0] w_careof;
assign w_careof = reg_careof[out_c_0];
assign w_empty = reg_empty[out_c_0];
assign w_stop = reg_stop[out_c_0];
assign w_data = reg_data[out_c_1];
assign wDATA0 = test_data[{slow_i,2'h0}];
assign wDATA1 = test_data[{slow_i,2'h1}];
assign wDATA2 = test_data[{slow_i,2'h2}];
assign wDATA3 = test_data[{slow_i,2'h3}];
assign WRITE = test_we[{slow_i,fast_i}];
assign WRITE_FIFO = fast_i;
assign INT0 = test_int[{slow_i,2'h0}];
assign INT1 = test_int[{slow_i,2'h1}];
assign INT2 = test_int[{slow_i,2'h2}];
assign INT3 = test_int[{slow_i,2'h3}];
assign READ = test_re[c];
assign READ_FIFO = test_rfifo[c];
assign CAREOF_INT_0 = test_care[c][0];
assign CAREOF_INT_1 = test_care[c][1];
assign CAREOF_INT_2 = test_care[c][2];
assign CAREOF_INT_3 = test_care[c][3];
reg [31:0] l, o, v, e;
initial
begin
for (l=0; l<1024; l=l+1)
begin
for (o=0; o<4; o=o+1)
begin
test_data[{l[9:0],o[1:0]}] <= {2'h0,o[1:0],l[23:0]};
test_we[{l[9:0],o[1:0]}] <= 0;
test_int[{l[9:0],o[1:0]}] <= 0;
end
end
for (v=0; v<4096; v=v+1)
begin
test_re[v] <= 0;
test_rfifo[v] <= 0;
test_care[v] <= 0;
reg_data[v] <= 0;
reg_empty[v] <= 0;
reg_stop[v] <= 0;
reg_careof[v] <= 0;
end
test_re[2] <= 1'b1;
reg_careof[0] <= 3'h4;
reg_empty[0] <= 4'hf;
for (e=4; e<12; e=e+1)
begin
test_we[{e[9:0],2'h2}] <= 1;
reg_careof[(e-3)] <= 3;
reg_empty[(e-3)] <= 4'h9;
reg_stop[(e-3)] <= 4'h9;
reg_data[(e-3)] <= {2'h0,2'h2,e[23:0]};
end
test_int[{10'd7,2'h2}] <= 1'b1;
for (l=44; l<52; l=l+1)
begin
test_re[l] <= 1;
test_rfifo[l] <= 2'h2;
end
reg_empty[8] <= 4'hb;
reg_stop[8] <= 4'hb;
for (o=13; o<22; o=o+1)
begin
test_we[{o[9:0],2'h2}] <= 1;
reg_careof[(o-4)] <= 4'hf;
reg_empty[(o-4)] <= 4'h9;
reg_stop[(o-4)] <= 4'h9;
reg_data[(o-4)] <= {2'h0,2'h2,o[23:0]};
reg_careof[(o-1)] <= 4'hf;
reg_empty[(o-1)] <= 4'h9;
reg_stop[(o-1)] <= 4'h9;
end
for (v=15; v<22; v=v+1)
reg_data[(v-3)] <= {2'h0,2'h2,v[23:0]};
for (e=16; e<22; e=e+1)
reg_data[(e-2)] <= {2'h0,2'h2,e[23:0]};
for (l=20; l<22; l=l+1)
reg_data[(l-1)] <= {2'h0,2'h2,l[23:0]};
reg_stop[11] <= 4'hb;
reg_stop[13] <= 4'hb;
reg_stop[18] <= 4'hb;
test_int[{10'd15,2'h2}] <= 1;
test_int[{10'd16,2'h2}] <= 1;
test_int[{10'd20,2'h2}] <= 1;
for (o=96; o<108; o=o+1)
begin
test_re[o] <= 1;
test_rfifo[o] <= 2'h2;
test_care[o] <= 4'hf;
end
reg_empty[20] <= 4'hb;
reg_stop[20] <= 4'hb;
for (e=2; e<318; e=e+1)
begin
test_we[{e[9:0],2'h1}] <= 1;
end
for (l=1200; l<(1200+63+17); l=l+1)
begin
test_re[l] <= 1;
test_rfifo[l] <= 2'h1;
test_care[l] <= 4'hf;
end
for (o=2; o<65; o=o+1)
begin
reg_careof[(o+19)] <= 4'hf;
reg_empty[(o+19)] <= 4'hb;
reg_stop[(o+19)] <= 4'hb;
reg_data[(o+19)] <= {2'h0,2'h1,o[23:0]};
end
for (v=300; v<318; v=v+1)
begin
reg_careof[(v-216)] <= 4'hf;
reg_empty[(v-216)] <= 4'hb;
reg_stop[(v-216)] <= 4'hb;
reg_data[(v-216)] <= {2'h0,2'h1,v[23:0]};
end
reg_empty[101] <= 4'hf;
reg_stop[101] <= 4'hf;
end
always @(posedge CLK)
if (!RST)
begin
fast_i <= 0; slow_i <= 0; c <= 0;
out_c_0 <= 0; out_c_1 <= 0; r_read_0 <= 0; r_read_1 <= 0;
r_careof <= 0;
end
else
begin
DATA0 <= wDATA0;
DATA1 <= wDATA1;
DATA2 <= wDATA2;
DATA3 <= wDATA3;
fast_i <= fast_i +1;
if (fast_i == 2'h3)
slow_i <= slow_i +1;
c <= c +1;
r_read_0 <= READ;
r_read_1 <= r_read_0;
if (r_read_0)
out_c_0 <= out_c_0 +1;
if (r_read_1)
out_c_1 <= out_c_1 +1;
r_careof <= w_careof;
begin
if (r_read_0)
begin
if (w_careof[2])
if (RES_EMPTY != w_empty)
$display("XXX empty #%d want %x got %x @ %d",
out_c_0, w_empty, RES_EMPTY, c);
if (w_careof[1])
if (RES_STOP != w_stop)
$display("XXX stop #%d want %x got %x @ %d",
out_c_0, w_stop, RES_STOP, c);
end
if (r_read_1)
begin
if (r_careof[0])
if (RES_DATA != w_data)
$display("XXX data #%d want %x got %x @ %d",
out_c_1, w_data, RES_DATA, c);
end
end
end
endmodule | module test_drv(input CLK,
input RST,
output reg [31:0] DATA0,
output reg [31:0] DATA1,
output reg [31:0] DATA2,
output reg [31:0] DATA3,
output WRITE,
output [1:0] WRITE_FIFO,
output INT0,
output INT1,
output INT2,
output INT3,
output READ,
output [1:0] READ_FIFO,
output CAREOF_INT_0,
output CAREOF_INT_1,
output CAREOF_INT_2,
output CAREOF_INT_3,
input [3:0] RES_EMPTY,
input [3:0] RES_STOP,
input [31:0] RES_DATA); |
reg [31:0] test_data[4095:0],
reg_data[4095:0];
reg [3:0] test_care[4095:0],
reg_empty[4095:0],
reg_stop[4095:0];
reg [2:0] reg_careof[4095:0];
reg [1:0] test_rfifo[4095:0];
reg test_we[4095:0],
test_re[4095:0],
test_int[4095:0],
r_read_0, r_read_1;
reg [1:0] fast_i;
reg [2:0] r_careof;
reg [9:0] slow_i;
reg [11:0] c, out_c_0, out_c_1;
wire [31:0] wDATA0, wDATA1, wDATA2, wDATA3;
wire [31:0] w_data;
wire [3:0] w_stop, w_empty;
wire [2:0] w_careof;
assign w_careof = reg_careof[out_c_0];
assign w_empty = reg_empty[out_c_0];
assign w_stop = reg_stop[out_c_0];
assign w_data = reg_data[out_c_1];
assign wDATA0 = test_data[{slow_i,2'h0}];
assign wDATA1 = test_data[{slow_i,2'h1}];
assign wDATA2 = test_data[{slow_i,2'h2}];
assign wDATA3 = test_data[{slow_i,2'h3}];
assign WRITE = test_we[{slow_i,fast_i}];
assign WRITE_FIFO = fast_i;
assign INT0 = test_int[{slow_i,2'h0}];
assign INT1 = test_int[{slow_i,2'h1}];
assign INT2 = test_int[{slow_i,2'h2}];
assign INT3 = test_int[{slow_i,2'h3}];
assign READ = test_re[c];
assign READ_FIFO = test_rfifo[c];
assign CAREOF_INT_0 = test_care[c][0];
assign CAREOF_INT_1 = test_care[c][1];
assign CAREOF_INT_2 = test_care[c][2];
assign CAREOF_INT_3 = test_care[c][3];
reg [31:0] l, o, v, e;
initial
begin
for (l=0; l<1024; l=l+1)
begin
for (o=0; o<4; o=o+1)
begin
test_data[{l[9:0],o[1:0]}] <= {2'h0,o[1:0],l[23:0]};
test_we[{l[9:0],o[1:0]}] <= 0;
test_int[{l[9:0],o[1:0]}] <= 0;
end
end
for (v=0; v<4096; v=v+1)
begin
test_re[v] <= 0;
test_rfifo[v] <= 0;
test_care[v] <= 0;
reg_data[v] <= 0;
reg_empty[v] <= 0;
reg_stop[v] <= 0;
reg_careof[v] <= 0;
end
test_re[2] <= 1'b1;
reg_careof[0] <= 3'h4;
reg_empty[0] <= 4'hf;
for (e=4; e<12; e=e+1)
begin
test_we[{e[9:0],2'h2}] <= 1;
reg_careof[(e-3)] <= 3;
reg_empty[(e-3)] <= 4'h9;
reg_stop[(e-3)] <= 4'h9;
reg_data[(e-3)] <= {2'h0,2'h2,e[23:0]};
end
test_int[{10'd7,2'h2}] <= 1'b1;
for (l=44; l<52; l=l+1)
begin
test_re[l] <= 1;
test_rfifo[l] <= 2'h2;
end
reg_empty[8] <= 4'hb;
reg_stop[8] <= 4'hb;
for (o=13; o<22; o=o+1)
begin
test_we[{o[9:0],2'h2}] <= 1;
reg_careof[(o-4)] <= 4'hf;
reg_empty[(o-4)] <= 4'h9;
reg_stop[(o-4)] <= 4'h9;
reg_data[(o-4)] <= {2'h0,2'h2,o[23:0]};
reg_careof[(o-1)] <= 4'hf;
reg_empty[(o-1)] <= 4'h9;
reg_stop[(o-1)] <= 4'h9;
end
for (v=15; v<22; v=v+1)
reg_data[(v-3)] <= {2'h0,2'h2,v[23:0]};
for (e=16; e<22; e=e+1)
reg_data[(e-2)] <= {2'h0,2'h2,e[23:0]};
for (l=20; l<22; l=l+1)
reg_data[(l-1)] <= {2'h0,2'h2,l[23:0]};
reg_stop[11] <= 4'hb;
reg_stop[13] <= 4'hb;
reg_stop[18] <= 4'hb;
test_int[{10'd15,2'h2}] <= 1;
test_int[{10'd16,2'h2}] <= 1;
test_int[{10'd20,2'h2}] <= 1;
for (o=96; o<108; o=o+1)
begin
test_re[o] <= 1;
test_rfifo[o] <= 2'h2;
test_care[o] <= 4'hf;
end
reg_empty[20] <= 4'hb;
reg_stop[20] <= 4'hb;
for (e=2; e<318; e=e+1)
begin
test_we[{e[9:0],2'h1}] <= 1;
end
for (l=1200; l<(1200+63+17); l=l+1)
begin
test_re[l] <= 1;
test_rfifo[l] <= 2'h1;
test_care[l] <= 4'hf;
end
for (o=2; o<65; o=o+1)
begin
reg_careof[(o+19)] <= 4'hf;
reg_empty[(o+19)] <= 4'hb;
reg_stop[(o+19)] <= 4'hb;
reg_data[(o+19)] <= {2'h0,2'h1,o[23:0]};
end
for (v=300; v<318; v=v+1)
begin
reg_careof[(v-216)] <= 4'hf;
reg_empty[(v-216)] <= 4'hb;
reg_stop[(v-216)] <= 4'hb;
reg_data[(v-216)] <= {2'h0,2'h1,v[23:0]};
end
reg_empty[101] <= 4'hf;
reg_stop[101] <= 4'hf;
end
always @(posedge CLK)
if (!RST)
begin
fast_i <= 0; slow_i <= 0; c <= 0;
out_c_0 <= 0; out_c_1 <= 0; r_read_0 <= 0; r_read_1 <= 0;
r_careof <= 0;
end
else
begin
DATA0 <= wDATA0;
DATA1 <= wDATA1;
DATA2 <= wDATA2;
DATA3 <= wDATA3;
fast_i <= fast_i +1;
if (fast_i == 2'h3)
slow_i <= slow_i +1;
c <= c +1;
r_read_0 <= READ;
r_read_1 <= r_read_0;
if (r_read_0)
out_c_0 <= out_c_0 +1;
if (r_read_1)
out_c_1 <= out_c_1 +1;
r_careof <= w_careof;
begin
if (r_read_0)
begin
if (w_careof[2])
if (RES_EMPTY != w_empty)
$display("XXX empty #%d want %x got %x @ %d",
out_c_0, w_empty, RES_EMPTY, c);
if (w_careof[1])
if (RES_STOP != w_stop)
$display("XXX stop #%d want %x got %x @ %d",
out_c_0, w_stop, RES_STOP, c);
end
if (r_read_1)
begin
if (r_careof[0])
if (RES_DATA != w_data)
$display("XXX data #%d want %x got %x @ %d",
out_c_1, w_data, RES_DATA, c);
end
end
end
endmodule | 1 |
138,663 | data/full_repos/permissive/85002992/test/test_lsab_cr.v | 85,002,992 | test_lsab_cr.v | v | 428 | 71 | [] | [] | [] | null | line:25: before: "&" | null | 1: b'%Error: data/full_repos/permissive/85002992/test/test_lsab_cr.v:3: Cannot find include file: test_inc.v\n`include "test_inc.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/test_inc.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/test_inc.v.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/test_inc.v.sv\n test_inc.v\n test_inc.v.v\n test_inc.v.sv\n obj_dir/test_inc.v\n obj_dir/test_inc.v.v\n obj_dir/test_inc.v.sv\n%Error: data/full_repos/permissive/85002992/test/test_lsab_cr.v:6: Cannot find include file: ../mcu/commands.v\n`include "../mcu/commands.v" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_lsab_cr.v:7: Cannot find include file: ../mcu/state2.v\n`include "../mcu/state2.v" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_lsab_cr.v:8: Cannot find include file: ../mcu/initializer.v\n`include "../mcu/initializer.v" \n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_lsab_cr.v:9: Cannot find include file: ../mcu/integration2.v\n`include "../mcu/integration2.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_lsab_cr.v:12: Cannot find include file: ../cache/cpu_mcu2.v\n`include "../cache/cpu_mcu2.v" \n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_lsab_cr.v:15: Cannot find include file: ../hyperfabric/lsab.v\n`include "../hyperfabric/lsab.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_lsab_cr.v:266: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_n <= 0; CLK_p <= 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_lsab_cr.v:267: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_dp <= 1; CLK_dn <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_lsab_cr.v:268: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_n <= 1; CLK_p <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_lsab_cr.v:269: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_dp <= 0; CLK_dn <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_lsab_cr.v:274: Unsupported: Ignoring delay on this delayed statement.\n #1.5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_lsab_cr.v:275: Unsupported: Ignoring delay on this delayed statement.\n #4.5 CPU_CLK <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_lsab_cr.v:276: Unsupported: Ignoring delay on this delayed statement.\n #3 CPU_CLK <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_lsab_cr.v:398: Unsupported: Ignoring delay on this delayed statement.\n #14.34 RST <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_lsab_cr.v:399: Unsupported: Ignoring delay on this delayed statement.\n #18432;\n ^\n%Error: Exiting due to 7 error(s), 9 warning(s)\n' | 302,640 | module | module GlaDOS;
reg CLK_p, CLK_n, CLK_dp, CLK_dn, RST, CPU_CLK;
reg [31:0] counter, minicounter, readcount, readcount2, readcount_r;
initial
forever
begin
#1.5 CLK_n <= 0; CLK_p <= 1;
#1.5 CLK_dp <= 1; CLK_dn <= 0;
#1.5 CLK_n <= 1; CLK_p <= 0;
#1.5 CLK_dp <= 0; CLK_dn <= 1;
end
initial
forever
begin
#1.5;
#4.5 CPU_CLK <= 1;
#3 CPU_CLK <= 0;
end
wire [31:0] w_data0, w_data1, w_data2, w_data3;
wire w_write, w_read;
wire [1:0] w_write_fifo, w_read_fifo;
wire w_int0, w_int1, w_int2, w_int3,
w_care0, w_care1, w_care2, w_care3;
reg r_read;
wire [31:0] w_out;
wire w_e0, w_e1, w_e2, w_e3,
w_s0, w_s1, w_s2, w_s3;
test_drv test_driver(.CLK(CLK_n),
.RST(RST),
.DATA0(w_data0),
.DATA1(w_data1),
.DATA2(w_data2),
.DATA3(w_data3),
.WRITE(w_write),
.WRITE_FIFO(w_write_fifo),
.INT0(w_int0),
.INT1(w_int1),
.INT2(w_int2),
.INT3(w_int3),
.READ(w_read),
.READ_FIFO(w_read_fifo),
.CAREOF_INT_0(w_care0),
.CAREOF_INT_1(w_care1),
.CAREOF_INT_2(w_care2),
.CAREOF_INT_3(w_care3),
.RES_EMPTY({w_e0,w_e1,w_e2,w_e3}),
.RES_STOP({w_s0,w_s1,w_s2,w_s3}),
.RES_DATA(w_out));
lsab_cr lsab_cr_mut(.CLK(CLK_n),
.RST(RST),
.READ(w_read),
.WRITE0(w_write),
.WRITE1(w_write),
.WRITE2(w_write),
.WRITE3(w_write),
.READ_FIFO(w_read_fifo),
.WRITE_FIFO(w_write_fifo),
.IN_0(w_data0),
.IN_1(w_data1),
.IN_2(w_data2),
.IN_3(w_data3),
.INT_IN_0(w_int0),
.INT_IN_1(w_int1),
.INT_IN_2(w_int2),
.INT_IN_3(w_int3),
.CAREOF_INT_0(w_care0),
.CAREOF_INT_1(w_care1),
.CAREOF_INT_2(w_care2),
.CAREOF_INT_3(w_care3),
.OUT(w_out),
.EMPTY_0(w_e0),
.EMPTY_1(w_e1),
.EMPTY_2(w_e2),
.EMPTY_3(w_e3),
.STOP_0(w_s0),
.STOP_1(w_s1),
.STOP_2(w_s2),
.STOP_3(w_s3));
always @(posedge CLK_n)
if (!RST)
begin
end
else
begin
counter <= counter +1;
end
initial
begin
counter <= 0;
RST <= 0;
#14.34 RST <= 1;
#18432;
$finish;
end
endmodule | module GlaDOS; |
reg CLK_p, CLK_n, CLK_dp, CLK_dn, RST, CPU_CLK;
reg [31:0] counter, minicounter, readcount, readcount2, readcount_r;
initial
forever
begin
#1.5 CLK_n <= 0; CLK_p <= 1;
#1.5 CLK_dp <= 1; CLK_dn <= 0;
#1.5 CLK_n <= 1; CLK_p <= 0;
#1.5 CLK_dp <= 0; CLK_dn <= 1;
end
initial
forever
begin
#1.5;
#4.5 CPU_CLK <= 1;
#3 CPU_CLK <= 0;
end
wire [31:0] w_data0, w_data1, w_data2, w_data3;
wire w_write, w_read;
wire [1:0] w_write_fifo, w_read_fifo;
wire w_int0, w_int1, w_int2, w_int3,
w_care0, w_care1, w_care2, w_care3;
reg r_read;
wire [31:0] w_out;
wire w_e0, w_e1, w_e2, w_e3,
w_s0, w_s1, w_s2, w_s3;
test_drv test_driver(.CLK(CLK_n),
.RST(RST),
.DATA0(w_data0),
.DATA1(w_data1),
.DATA2(w_data2),
.DATA3(w_data3),
.WRITE(w_write),
.WRITE_FIFO(w_write_fifo),
.INT0(w_int0),
.INT1(w_int1),
.INT2(w_int2),
.INT3(w_int3),
.READ(w_read),
.READ_FIFO(w_read_fifo),
.CAREOF_INT_0(w_care0),
.CAREOF_INT_1(w_care1),
.CAREOF_INT_2(w_care2),
.CAREOF_INT_3(w_care3),
.RES_EMPTY({w_e0,w_e1,w_e2,w_e3}),
.RES_STOP({w_s0,w_s1,w_s2,w_s3}),
.RES_DATA(w_out));
lsab_cr lsab_cr_mut(.CLK(CLK_n),
.RST(RST),
.READ(w_read),
.WRITE0(w_write),
.WRITE1(w_write),
.WRITE2(w_write),
.WRITE3(w_write),
.READ_FIFO(w_read_fifo),
.WRITE_FIFO(w_write_fifo),
.IN_0(w_data0),
.IN_1(w_data1),
.IN_2(w_data2),
.IN_3(w_data3),
.INT_IN_0(w_int0),
.INT_IN_1(w_int1),
.INT_IN_2(w_int2),
.INT_IN_3(w_int3),
.CAREOF_INT_0(w_care0),
.CAREOF_INT_1(w_care1),
.CAREOF_INT_2(w_care2),
.CAREOF_INT_3(w_care3),
.OUT(w_out),
.EMPTY_0(w_e0),
.EMPTY_1(w_e1),
.EMPTY_2(w_e2),
.EMPTY_3(w_e3),
.STOP_0(w_s0),
.STOP_1(w_s1),
.STOP_2(w_s2),
.STOP_3(w_s3));
always @(posedge CLK_n)
if (!RST)
begin
end
else
begin
counter <= counter +1;
end
initial
begin
counter <= 0;
RST <= 0;
#14.34 RST <= 1;
#18432;
$finish;
end
endmodule | 1 |
138,666 | data/full_repos/permissive/85002992/test/test_mcu.v | 85,002,992 | test_mcu.v | v | 332 | 74 | [] | [] | [] | null | line:25: before: "&" | null | 1: b'%Error: data/full_repos/permissive/85002992/test/test_mcu.v:3: Cannot find include file: test_inc.v\n`include "test_inc.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/test_inc.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/test_inc.v.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/test_inc.v.sv\n test_inc.v\n test_inc.v.v\n test_inc.v.sv\n obj_dir/test_inc.v\n obj_dir/test_inc.v.v\n obj_dir/test_inc.v.sv\n%Error: data/full_repos/permissive/85002992/test/test_mcu.v:6: Cannot find include file: ../mcu/commands.v\n`include "../mcu/commands.v" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mcu.v:7: Cannot find include file: ../mcu/state2.v\n`include "../mcu/state2.v" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mcu.v:8: Cannot find include file: ../mcu/initializer.v\n`include "../mcu/initializer.v" \n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mcu.v:9: Cannot find include file: ../mcu/integration3.v\n`include "../mcu/integration3.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mcu.v:19: Unsupported: Ignoring delay on this delayed statement.\n #1500 CLK_n <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mcu.v:20: Unsupported: Ignoring delay on this delayed statement.\n #1500 CLK_dn <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mcu.v:21: Unsupported: Ignoring delay on this delayed statement.\n #1500 CLK_n <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mcu.v:22: Unsupported: Ignoring delay on this delayed statement.\n #1500 CLK_dn <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mcu.v:142: Unsupported: Ignoring delay on this delayed statement.\n #14875 RST <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mcu.v:143: Unsupported: Ignoring delay on this delayed statement.\n #400000000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mcu.v:145: Unsupported: Ignoring delay on this delayed statement.\n #300000000;\n ^\n%Error: Exiting due to 5 error(s), 7 warning(s)\n' | 302,642 | module | module GlaDOS;
reg CLK_n, CLK_dn, RST;
reg SYS_RST, long_counter_o;
reg [7:0] long_counter_h, long_counter_l;
initial
forever
begin
#1500 CLK_n <= 0;
#1500 CLK_dn <= 0;
#1500 CLK_n <= 1;
#1500 CLK_dn <= 1;
end
always @(posedge CLK_n)
begin
if (!RST)
begin
long_counter_h <= 0;
long_counter_l <= 0;
long_counter_o <= 0;
end
else
begin
{long_counter_o,long_counter_l} <= long_counter_l +1;
if (long_counter_o)
long_counter_h <= long_counter_h +1;
if (long_counter_h == 8'hff)
SYS_RST <= 1;
end
end
wire dCLK_P, dCLK_N, dCKE, dUDQS, dLDQS, dUDM, dLDM, dCS, dODT;
wire [2:0] dCOMMAND;
wire [13:0] dADDRESS;
wire [2:0] dBANK;
wire [15:0] dDQ;
reg [31:0] d_user_req_address;
reg d_user_req_we = 1'b0, d_user_req = 1'b0;
reg [3:0] d_user_we_array;
reg [31:0] d_user_req_datain;
wire d_user_req_ack;
reg [22:0] mcu_page_addr = 23'd0;
reg [8:0] mcu_coll_addr = 9'd0;
reg d_mcu_we = 1'b0, d_mcu_req_access = 1'b0,
d_mcu_algn_req = 1'b0;
reg [3:0] hf_we_array_fill;
wire d_mcu_req_ack, d_mcu_algn_ack;
reg [31:0] d_mcu_data_into;
wire [31:0] d_user_req_dataout;
reg refresh_strobe = 1'b0;
reg [31:0] counter_sys_rst = 0, counter_exec = 0;
reg exec = 1'b0;
ddr2 d_ddr2_mem(.ck(dCLK_P),
.ck_n(dCLK_N),
.cke(dCKE),
.cs_n(dCS),
.ras_n(dCOMMAND[2]),
.cas_n(dCOMMAND[1]),
.we_n(dCOMMAND[0]),
.dm_rdqs({dUDM,dLDM}),
.ba(dBANK),
.addr(dADDRESS[12:0]),
.dq(dDQ),
.dqs({dUDQS,dLDQS}),
.dqs_n(),
.rdqs_n(),
.odt(1'b1));
ddr_memory_controler d_mcu(.CLK_n(CLK_n),
.CLK_dn(CLK_dn),
.RST_MASTER(SYS_RST),
.MEM_CLK_P(dCLK_P),
.MEM_CLK_N(dCLK_N),
.CKE(dCKE),
.COMMAND(dCOMMAND),
.ADDRESS(dADDRESS),
.BANK(dBANK),
.DQ(dDQ),
.UDQS(dUDQS),
.LDQS(dLDQS),
.UDM(dUDM),
.LDM(dLDM),
.CS(dCS),
.refresh_strobe(refresh_strobe),
.rand_req_address(d_user_req_address[25:0]),
.rand_req_we(d_user_req_we),
.rand_req_we_array(d_user_we_array),
.rand_req(d_user_req),
.rand_req_ack(d_user_req_ack),
.rand_req_datain(d_user_req_datain),
.bulk_req_address({mcu_page_addr[16:0],
mcu_coll_addr}),
.bulk_req_we(d_mcu_we),
.bulk_req_we_array(hf_we_array_fill),
.bulk_req(d_mcu_req_access),
.bulk_req_ack(d_mcu_req_ack),
.bulk_req_algn(d_mcu_algn_req),
.bulk_req_algn_ack(d_mcu_algn_ack),
.bulk_req_datain(d_mcu_data_into),
.user_req_dataout(d_user_req_dataout));
initial
begin
RST <= 0; SYS_RST <= 0;
#14875 RST <= 1;
#400000000;
exec <= 1'b1;
#300000000;
$display("irregular finish");
$finish;
end
always @(counter_sys_rst)
d_mcu_data_into <= counter_sys_rst;
always @(counter_exec)
d_user_req_datain <= counter_exec;
always @(posedge CLK_n)
begin
counter_sys_rst <= counter_sys_rst + SYS_RST;
counter_exec <= counter_exec + exec;
if (exec)
begin
d_user_req_address <= d_user_req_address +1;
{mcu_page_addr,mcu_coll_addr} <= {mcu_page_addr,mcu_coll_addr} +1;
case (counter_exec)
32'd0: begin
d_user_req <= 1;
d_user_req_we <= 0;
end
32'd20: begin
refresh_strobe <= !refresh_strobe;
end
32'd80: begin
d_user_req_we <= 1;
end
32'd100: begin
refresh_strobe <= !refresh_strobe;
end
32'd167: begin
d_user_req_we <= 0;
end
32'd184: begin
$display("assert ALIGN %t -------------------------------",
$time);
d_mcu_algn_req <= 1;
end
32'd192: begin
d_mcu_req_access <= 1;
end
32'd210: begin
d_mcu_we <= 1;
d_user_req_we <= 1;
end
- 32'd230: begin
d_mcu_req_access <= 0;
$display("deassert ALIGN %t -------------------------------",
$time);
$display("====<<<>>> ic %x ss %x pRLB %x RLB %x IDM %x",
d_mcu.interdictor_tracker.issue_com,
d_mcu.interdictor_tracker.second_stroke,
d_mcu.interdictor_tracker.port_REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.INTERNAL_DATA_MUX);
d_mcu_algn_req <= 0;
end
32'd231: begin
$display("====<<<>>> ic %x ss %x pRLB %x RLB %x IDM %x",
d_mcu.interdictor_tracker.issue_com,
d_mcu.interdictor_tracker.second_stroke,
d_mcu.interdictor_tracker.port_REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.INTERNAL_DATA_MUX);
end
32'd232: begin
$display("====<<<>>> ic %x ss %x pRLB %x RLB %x IDM %x",
d_mcu.interdictor_tracker.issue_com,
d_mcu.interdictor_tracker.second_stroke,
d_mcu.interdictor_tracker.port_REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.INTERNAL_DATA_MUX);
end
32'd233: begin
$display("====<<<>>> ic %x ss %x pRLB %x RLB %x IDM %x",
d_mcu.interdictor_tracker.issue_com,
d_mcu.interdictor_tracker.second_stroke,
d_mcu.interdictor_tracker.port_REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.INTERNAL_DATA_MUX);
end
32'd234: begin
$display("====<<<>>> ic %x ss %x pRLB %x RLB %x IDM %x",
d_mcu.interdictor_tracker.issue_com,
d_mcu.interdictor_tracker.second_stroke,
d_mcu.interdictor_tracker.port_REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.INTERNAL_DATA_MUX);
end
32'd235: begin
$display("====<<<>>> ic %x ss %x pRLB %x RLB %x IDM %x",
d_mcu.interdictor_tracker.issue_com,
d_mcu.interdictor_tracker.second_stroke,
d_mcu.interdictor_tracker.port_REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.INTERNAL_DATA_MUX);
end
32'd236: begin
$display("====<<<>>> ic %x ss %x pRLB %x RLB %x IDM %x",
d_mcu.interdictor_tracker.issue_com,
d_mcu.interdictor_tracker.second_stroke,
d_mcu.interdictor_tracker.port_REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.INTERNAL_DATA_MUX);
end
32'd237: begin
$display("====<<<>>> ic %x ss %x pRLB %x RLB %x IDM %x",
d_mcu.interdictor_tracker.issue_com,
d_mcu.interdictor_tracker.second_stroke,
d_mcu.interdictor_tracker.port_REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.INTERNAL_DATA_MUX);
end
32'd240: begin
d_user_req_we <= 1;
end
32'd257: begin
$display("assert ALIGN %t -------------------------------",
$time);
d_mcu_algn_req <= 1;
d_mcu_we <= 1;
d_mcu_req_access <= 1;
end
32'd272: begin
$display("deassert ALIGN %t -------------------------------",
$time);
d_mcu_algn_req <= 0;
d_mcu_req_access <= 0;
end
32'd300: begin
mcu_page_addr <= 23'h200;
d_mcu_algn_req <= 1;
d_mcu_req_access <= 1;
end
32'd320: begin
d_mcu_algn_req <= 0;
d_mcu_req_access <= 0;
end
32'd350: begin
d_user_req_we <= 0;
end
32'd360: begin
$display("assert ALIGN %t -------------------------------",
$time);
d_mcu_algn_req <= 1;
d_mcu_req_access <= 1;
end
32'd366: begin
d_user_req_we <= 1;
end
32'd380: begin
d_mcu_algn_req <= 0;
d_mcu_req_access <= 0;
end
32'd400: begin
d_mcu_algn_req <= 1;
d_mcu_req_access <= 1;
end
32'd406: begin
d_user_req_we <= 0;
end
32'd430: begin
d_mcu_algn_req <= 0;
d_mcu_req_access <= 0;
end
32'd460: begin
$display("regular finish");
$finish;
end
endcase
d_user_we_array <= 4'hf;
end
else
begin
d_user_req_address <= 0;
d_user_we_array <= 4'hf;
hf_we_array_fill <= 4'hf;
end
end
endmodule | module GlaDOS; |
reg CLK_n, CLK_dn, RST;
reg SYS_RST, long_counter_o;
reg [7:0] long_counter_h, long_counter_l;
initial
forever
begin
#1500 CLK_n <= 0;
#1500 CLK_dn <= 0;
#1500 CLK_n <= 1;
#1500 CLK_dn <= 1;
end
always @(posedge CLK_n)
begin
if (!RST)
begin
long_counter_h <= 0;
long_counter_l <= 0;
long_counter_o <= 0;
end
else
begin
{long_counter_o,long_counter_l} <= long_counter_l +1;
if (long_counter_o)
long_counter_h <= long_counter_h +1;
if (long_counter_h == 8'hff)
SYS_RST <= 1;
end
end
wire dCLK_P, dCLK_N, dCKE, dUDQS, dLDQS, dUDM, dLDM, dCS, dODT;
wire [2:0] dCOMMAND;
wire [13:0] dADDRESS;
wire [2:0] dBANK;
wire [15:0] dDQ;
reg [31:0] d_user_req_address;
reg d_user_req_we = 1'b0, d_user_req = 1'b0;
reg [3:0] d_user_we_array;
reg [31:0] d_user_req_datain;
wire d_user_req_ack;
reg [22:0] mcu_page_addr = 23'd0;
reg [8:0] mcu_coll_addr = 9'd0;
reg d_mcu_we = 1'b0, d_mcu_req_access = 1'b0,
d_mcu_algn_req = 1'b0;
reg [3:0] hf_we_array_fill;
wire d_mcu_req_ack, d_mcu_algn_ack;
reg [31:0] d_mcu_data_into;
wire [31:0] d_user_req_dataout;
reg refresh_strobe = 1'b0;
reg [31:0] counter_sys_rst = 0, counter_exec = 0;
reg exec = 1'b0;
ddr2 d_ddr2_mem(.ck(dCLK_P),
.ck_n(dCLK_N),
.cke(dCKE),
.cs_n(dCS),
.ras_n(dCOMMAND[2]),
.cas_n(dCOMMAND[1]),
.we_n(dCOMMAND[0]),
.dm_rdqs({dUDM,dLDM}),
.ba(dBANK),
.addr(dADDRESS[12:0]),
.dq(dDQ),
.dqs({dUDQS,dLDQS}),
.dqs_n(),
.rdqs_n(),
.odt(1'b1));
ddr_memory_controler d_mcu(.CLK_n(CLK_n),
.CLK_dn(CLK_dn),
.RST_MASTER(SYS_RST),
.MEM_CLK_P(dCLK_P),
.MEM_CLK_N(dCLK_N),
.CKE(dCKE),
.COMMAND(dCOMMAND),
.ADDRESS(dADDRESS),
.BANK(dBANK),
.DQ(dDQ),
.UDQS(dUDQS),
.LDQS(dLDQS),
.UDM(dUDM),
.LDM(dLDM),
.CS(dCS),
.refresh_strobe(refresh_strobe),
.rand_req_address(d_user_req_address[25:0]),
.rand_req_we(d_user_req_we),
.rand_req_we_array(d_user_we_array),
.rand_req(d_user_req),
.rand_req_ack(d_user_req_ack),
.rand_req_datain(d_user_req_datain),
.bulk_req_address({mcu_page_addr[16:0],
mcu_coll_addr}),
.bulk_req_we(d_mcu_we),
.bulk_req_we_array(hf_we_array_fill),
.bulk_req(d_mcu_req_access),
.bulk_req_ack(d_mcu_req_ack),
.bulk_req_algn(d_mcu_algn_req),
.bulk_req_algn_ack(d_mcu_algn_ack),
.bulk_req_datain(d_mcu_data_into),
.user_req_dataout(d_user_req_dataout));
initial
begin
RST <= 0; SYS_RST <= 0;
#14875 RST <= 1;
#400000000;
exec <= 1'b1;
#300000000;
$display("irregular finish");
$finish;
end
always @(counter_sys_rst)
d_mcu_data_into <= counter_sys_rst;
always @(counter_exec)
d_user_req_datain <= counter_exec;
always @(posedge CLK_n)
begin
counter_sys_rst <= counter_sys_rst + SYS_RST;
counter_exec <= counter_exec + exec;
if (exec)
begin
d_user_req_address <= d_user_req_address +1;
{mcu_page_addr,mcu_coll_addr} <= {mcu_page_addr,mcu_coll_addr} +1;
case (counter_exec)
32'd0: begin
d_user_req <= 1;
d_user_req_we <= 0;
end
32'd20: begin
refresh_strobe <= !refresh_strobe;
end
32'd80: begin
d_user_req_we <= 1;
end
32'd100: begin
refresh_strobe <= !refresh_strobe;
end
32'd167: begin
d_user_req_we <= 0;
end
32'd184: begin
$display("assert ALIGN %t -------------------------------",
$time);
d_mcu_algn_req <= 1;
end
32'd192: begin
d_mcu_req_access <= 1;
end
32'd210: begin
d_mcu_we <= 1;
d_user_req_we <= 1;
end
- 32'd230: begin
d_mcu_req_access <= 0;
$display("deassert ALIGN %t -------------------------------",
$time);
$display("====<<<>>> ic %x ss %x pRLB %x RLB %x IDM %x",
d_mcu.interdictor_tracker.issue_com,
d_mcu.interdictor_tracker.second_stroke,
d_mcu.interdictor_tracker.port_REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.INTERNAL_DATA_MUX);
d_mcu_algn_req <= 0;
end
32'd231: begin
$display("====<<<>>> ic %x ss %x pRLB %x RLB %x IDM %x",
d_mcu.interdictor_tracker.issue_com,
d_mcu.interdictor_tracker.second_stroke,
d_mcu.interdictor_tracker.port_REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.INTERNAL_DATA_MUX);
end
32'd232: begin
$display("====<<<>>> ic %x ss %x pRLB %x RLB %x IDM %x",
d_mcu.interdictor_tracker.issue_com,
d_mcu.interdictor_tracker.second_stroke,
d_mcu.interdictor_tracker.port_REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.INTERNAL_DATA_MUX);
end
32'd233: begin
$display("====<<<>>> ic %x ss %x pRLB %x RLB %x IDM %x",
d_mcu.interdictor_tracker.issue_com,
d_mcu.interdictor_tracker.second_stroke,
d_mcu.interdictor_tracker.port_REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.INTERNAL_DATA_MUX);
end
32'd234: begin
$display("====<<<>>> ic %x ss %x pRLB %x RLB %x IDM %x",
d_mcu.interdictor_tracker.issue_com,
d_mcu.interdictor_tracker.second_stroke,
d_mcu.interdictor_tracker.port_REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.INTERNAL_DATA_MUX);
end
32'd235: begin
$display("====<<<>>> ic %x ss %x pRLB %x RLB %x IDM %x",
d_mcu.interdictor_tracker.issue_com,
d_mcu.interdictor_tracker.second_stroke,
d_mcu.interdictor_tracker.port_REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.INTERNAL_DATA_MUX);
end
32'd236: begin
$display("====<<<>>> ic %x ss %x pRLB %x RLB %x IDM %x",
d_mcu.interdictor_tracker.issue_com,
d_mcu.interdictor_tracker.second_stroke,
d_mcu.interdictor_tracker.port_REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.INTERNAL_DATA_MUX);
end
32'd237: begin
$display("====<<<>>> ic %x ss %x pRLB %x RLB %x IDM %x",
d_mcu.interdictor_tracker.issue_com,
d_mcu.interdictor_tracker.second_stroke,
d_mcu.interdictor_tracker.port_REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.REQUEST_ALIGN_BULK,
d_mcu.interdictor_tracker.INTERNAL_DATA_MUX);
end
32'd240: begin
d_user_req_we <= 1;
end
32'd257: begin
$display("assert ALIGN %t -------------------------------",
$time);
d_mcu_algn_req <= 1;
d_mcu_we <= 1;
d_mcu_req_access <= 1;
end
32'd272: begin
$display("deassert ALIGN %t -------------------------------",
$time);
d_mcu_algn_req <= 0;
d_mcu_req_access <= 0;
end
32'd300: begin
mcu_page_addr <= 23'h200;
d_mcu_algn_req <= 1;
d_mcu_req_access <= 1;
end
32'd320: begin
d_mcu_algn_req <= 0;
d_mcu_req_access <= 0;
end
32'd350: begin
d_user_req_we <= 0;
end
32'd360: begin
$display("assert ALIGN %t -------------------------------",
$time);
d_mcu_algn_req <= 1;
d_mcu_req_access <= 1;
end
32'd366: begin
d_user_req_we <= 1;
end
32'd380: begin
d_mcu_algn_req <= 0;
d_mcu_req_access <= 0;
end
32'd400: begin
d_mcu_algn_req <= 1;
d_mcu_req_access <= 1;
end
32'd406: begin
d_user_req_we <= 0;
end
32'd430: begin
d_mcu_algn_req <= 0;
d_mcu_req_access <= 0;
end
32'd460: begin
$display("regular finish");
$finish;
end
endcase
d_user_we_array <= 4'hf;
end
else
begin
d_user_req_address <= 0;
d_user_we_array <= 4'hf;
hf_we_array_fill <= 4'hf;
end
end
endmodule | 1 |
138,670 | data/full_repos/permissive/85002992/test/test_mvblck_todram.v | 85,002,992 | test_mvblck_todram.v | v | 487 | 73 | [] | [] | [] | null | line:25: before: "&" | null | 1: b'%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:3: Cannot find include file: test_inc.v\n`include "test_inc.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/test_inc.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/test_inc.v.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/test_inc.v.sv\n test_inc.v\n test_inc.v.v\n test_inc.v.sv\n obj_dir/test_inc.v\n obj_dir/test_inc.v.v\n obj_dir/test_inc.v.sv\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:6: Cannot find include file: ../mcu/commands.v\n`include "../mcu/commands.v" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:7: Cannot find include file: ../mcu/state2.v\n`include "../mcu/state2.v" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:8: Cannot find include file: ../mcu/initializer.v\n`include "../mcu/initializer.v" \n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:9: Cannot find include file: ../mcu/integration2.v\n`include "../mcu/integration2.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:12: Cannot find include file: ../cache/cpu_mcu2.v\n`include "../cache/cpu_mcu2.v" \n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:15: Cannot find include file: ../hyperfabric/lsab.v\n`include "../hyperfabric/lsab.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:18: Cannot find include file: ../hyperfabric/transport.v\n`include "../hyperfabric/transport.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:19: Cannot find include file: ../hyperfabric/mvblck_todram.v\n`include "../hyperfabric/mvblck_todram.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:20: Cannot find include file: ../hyperfabric/mvblck_frdram.v\n`include "../hyperfabric/mvblck_frdram.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:246: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_n <= 0; CLK_p <= 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:247: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_dp <= 1; CLK_dn <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:248: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_n <= 1; CLK_p <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:249: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_dp <= 0; CLK_dn <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:254: Unsupported: Ignoring delay on this delayed statement.\n #1.5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:255: Unsupported: Ignoring delay on this delayed statement.\n #4.5 CPU_CLK <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:256: Unsupported: Ignoring delay on this delayed statement.\n #3 CPU_CLK <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:456: Unsupported: Ignoring delay on this delayed statement.\n #14.34 RST_ddr <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:457: Unsupported: Ignoring delay on this delayed statement.\n #400000 RST <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:458: Unsupported: Ignoring delay on this delayed statement.\n #18432;\n ^\n%Error: Exiting due to 10 error(s), 10 warning(s)\n' | 302,645 | module | module test_fill_lsab(input CLK,
input RST,
output [31:0] DATA0,
output [31:0] DATA1,
output [31:0] DATA2,
output [31:0] DATA3,
output WRITE,
output [1:0] WRITE_FIFO,
output INT0,
output INT1,
output INT2,
output INT3);
reg [31:0] test_data[4095:0];
reg test_we[4095:0],
test_int[4095:0];
reg [1:0] fast_i;
reg [9:0] slow_i;
reg [11:0] c;
assign DATA0 = test_data[{slow_i,2'h0}];
assign DATA1 = test_data[{slow_i,2'h1}];
assign DATA2 = test_data[{slow_i,2'h2}];
assign DATA3 = test_data[{slow_i,2'h3}];
assign WRITE = test_we[{slow_i,fast_i}];
assign WRITE_FIFO = fast_i;
assign INT0 = test_int[{slow_i,2'h0}];
assign INT1 = test_int[{slow_i,2'h1}];
assign INT2 = test_int[{slow_i,2'h2}];
assign INT3 = test_int[{slow_i,2'h3}];
reg [31:0] l, o, v, e;
initial
begin
for (l=0; l<1024; l=l+1)
begin
for (o=0; o<4; o=o+1)
begin
test_data[{l[9:0],o[1:0]}] <= {2'h0,o[1:0],l[23:0]};
test_we[{l[9:0],o[1:0]}] <= 0;
test_int[{l[9:0],o[1:0]}] <= 0;
end
end
for (v=(0+4); v<(72+4); v=v+1)
begin
test_we[{v[9:0],2'h1}] <= 1;
end
for (e=0; e<15; e=e+1)
begin
test_we[{e[9:0],2'h2}] <= 1;
end
test_int[{10'd6,2'h2}] <= 1;
test_int[{10'd8,2'h2}] <= 1;
end
always @(posedge CLK)
if (!RST)
begin
fast_i <= 0; slow_i <= 0; c <= 0;
end
else
begin
fast_i <= fast_i +1;
if (fast_i == 2'h3)
slow_i <= slow_i +1;
c <= c +1;
end
endmodule | module test_fill_lsab(input CLK,
input RST,
output [31:0] DATA0,
output [31:0] DATA1,
output [31:0] DATA2,
output [31:0] DATA3,
output WRITE,
output [1:0] WRITE_FIFO,
output INT0,
output INT1,
output INT2,
output INT3); |
reg [31:0] test_data[4095:0];
reg test_we[4095:0],
test_int[4095:0];
reg [1:0] fast_i;
reg [9:0] slow_i;
reg [11:0] c;
assign DATA0 = test_data[{slow_i,2'h0}];
assign DATA1 = test_data[{slow_i,2'h1}];
assign DATA2 = test_data[{slow_i,2'h2}];
assign DATA3 = test_data[{slow_i,2'h3}];
assign WRITE = test_we[{slow_i,fast_i}];
assign WRITE_FIFO = fast_i;
assign INT0 = test_int[{slow_i,2'h0}];
assign INT1 = test_int[{slow_i,2'h1}];
assign INT2 = test_int[{slow_i,2'h2}];
assign INT3 = test_int[{slow_i,2'h3}];
reg [31:0] l, o, v, e;
initial
begin
for (l=0; l<1024; l=l+1)
begin
for (o=0; o<4; o=o+1)
begin
test_data[{l[9:0],o[1:0]}] <= {2'h0,o[1:0],l[23:0]};
test_we[{l[9:0],o[1:0]}] <= 0;
test_int[{l[9:0],o[1:0]}] <= 0;
end
end
for (v=(0+4); v<(72+4); v=v+1)
begin
test_we[{v[9:0],2'h1}] <= 1;
end
for (e=0; e<15; e=e+1)
begin
test_we[{e[9:0],2'h2}] <= 1;
end
test_int[{10'd6,2'h2}] <= 1;
test_int[{10'd8,2'h2}] <= 1;
end
always @(posedge CLK)
if (!RST)
begin
fast_i <= 0; slow_i <= 0; c <= 0;
end
else
begin
fast_i <= fast_i +1;
if (fast_i == 2'h3)
slow_i <= slow_i +1;
c <= c +1;
end
endmodule | 1 |
138,671 | data/full_repos/permissive/85002992/test/test_mvblck_todram.v | 85,002,992 | test_mvblck_todram.v | v | 487 | 73 | [] | [] | [] | null | line:25: before: "&" | null | 1: b'%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:3: Cannot find include file: test_inc.v\n`include "test_inc.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/test_inc.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/test_inc.v.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/test_inc.v.sv\n test_inc.v\n test_inc.v.v\n test_inc.v.sv\n obj_dir/test_inc.v\n obj_dir/test_inc.v.v\n obj_dir/test_inc.v.sv\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:6: Cannot find include file: ../mcu/commands.v\n`include "../mcu/commands.v" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:7: Cannot find include file: ../mcu/state2.v\n`include "../mcu/state2.v" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:8: Cannot find include file: ../mcu/initializer.v\n`include "../mcu/initializer.v" \n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:9: Cannot find include file: ../mcu/integration2.v\n`include "../mcu/integration2.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:12: Cannot find include file: ../cache/cpu_mcu2.v\n`include "../cache/cpu_mcu2.v" \n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:15: Cannot find include file: ../hyperfabric/lsab.v\n`include "../hyperfabric/lsab.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:18: Cannot find include file: ../hyperfabric/transport.v\n`include "../hyperfabric/transport.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:19: Cannot find include file: ../hyperfabric/mvblck_todram.v\n`include "../hyperfabric/mvblck_todram.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:20: Cannot find include file: ../hyperfabric/mvblck_frdram.v\n`include "../hyperfabric/mvblck_frdram.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:246: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_n <= 0; CLK_p <= 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:247: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_dp <= 1; CLK_dn <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:248: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_n <= 1; CLK_p <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:249: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_dp <= 0; CLK_dn <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:254: Unsupported: Ignoring delay on this delayed statement.\n #1.5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:255: Unsupported: Ignoring delay on this delayed statement.\n #4.5 CPU_CLK <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:256: Unsupported: Ignoring delay on this delayed statement.\n #3 CPU_CLK <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:456: Unsupported: Ignoring delay on this delayed statement.\n #14.34 RST_ddr <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:457: Unsupported: Ignoring delay on this delayed statement.\n #400000 RST <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:458: Unsupported: Ignoring delay on this delayed statement.\n #18432;\n ^\n%Error: Exiting due to 10 error(s), 10 warning(s)\n' | 302,645 | module | module test_mvblck(input CLK,
input RST,
output reg mvblck_RST,
output [11:0] START_ADDRESS,
output [5:0] COUNT_REQ,
output [1:0] SECTION,
output reg ISSUE,
input [5:0] COUNT_SENT,
input WORKING);
reg [31:0] c;
reg [11:0] test_addr[255:0];
reg [7:0] testno, maxtests;
reg [5:0] test_count[255:0];
reg [1:0] test_section[255:0];
reg working_prev;
wire trigger, trigger_all;
assign trigger = working_prev && !WORKING;
assign trigger_all = (c == 32'd256) || trigger;
assign START_ADDRESS = test_addr[testno];
assign COUNT_REQ = test_count[testno];
assign SECTION = test_section[testno];
reg [31:0] l, o, v, e;
initial
begin
for (l=0; l<256; l=l+1)
begin
test_addr[l] <= 0;
test_count[l] <= 0;
test_section[l] <= 2'h1;
end
test_addr[1] <= 12'h000;
test_count[1] <= 6'd1;
test_addr[2] <= 12'h010;
test_count[2] <= 6'd2;
test_addr[3] <= 12'h020;
test_count[3] <= 6'd3;
test_addr[4] <= 12'h030;
test_count[4] <= 6'd4;
test_addr[5] <= 12'h040;
test_count[5] <= 6'd5;
test_addr[6] <= 12'h050;
test_count[6] <= 6'd6;
test_addr[7] <= 12'h060;
test_count[7] <= 6'd7;
test_addr[8] <= 12'h070;
test_count[8] <= 6'd8;
test_addr[9] <= 12'h101;
test_count[9] <= 6'd1;
test_addr[10] <= 12'h111;
test_count[10] <= 6'd2;
test_addr[11] <= 12'h121;
test_count[11] <= 6'd3;
test_addr[12] <= 12'h131;
test_count[12] <= 6'd4;
test_addr[13] <= 12'h141;
test_count[13] <= 6'd5;
test_addr[14] <= 12'h151;
test_count[14] <= 6'd6;
test_addr[15] <= 12'h161;
test_count[15] <= 6'd7;
test_addr[16] <= 12'h171;
test_count[16] <= 6'd8;
test_addr[17] <= 12'h180;
test_count[17] <= 6'd15;
test_section[17] <= 2'h2;
test_addr[18] <= 12'h190;
test_count[18] <= 6'd1;
test_section[18] <= 2'h2;
test_addr[19] <= 12'h1a0;
test_count[19] <= 6'd2;
test_section[19] <= 2'h2;
test_addr[20] <= 12'h1b0;
test_count[20] <= 6'd6;
test_section[20] <= 2'h2;
end
always @(posedge CLK)
if (!RST)
begin
c <= 0; mvblck_RST <= 0; working_prev <= 0; ISSUE <= 0;
testno <= 8'h00; maxtests <= 1+ 20;
end
else
begin
c <= c+1;
if (c == 32'd256)
mvblck_RST <= 1;
working_prev <= WORKING;
if (trigger)
begin
if (COUNT_SENT != COUNT_REQ)
$display("XXX count of sent #%d got %x want %x @ %d",
testno, COUNT_SENT, COUNT_REQ, c);
end
if (trigger_all && (testno < maxtests))
begin
testno <= testno +1;
$display("TEST #%d", testno+1);
ISSUE <= 1;
end
else
if (WORKING)
ISSUE <= 0;
end
endmodule | module test_mvblck(input CLK,
input RST,
output reg mvblck_RST,
output [11:0] START_ADDRESS,
output [5:0] COUNT_REQ,
output [1:0] SECTION,
output reg ISSUE,
input [5:0] COUNT_SENT,
input WORKING); |
reg [31:0] c;
reg [11:0] test_addr[255:0];
reg [7:0] testno, maxtests;
reg [5:0] test_count[255:0];
reg [1:0] test_section[255:0];
reg working_prev;
wire trigger, trigger_all;
assign trigger = working_prev && !WORKING;
assign trigger_all = (c == 32'd256) || trigger;
assign START_ADDRESS = test_addr[testno];
assign COUNT_REQ = test_count[testno];
assign SECTION = test_section[testno];
reg [31:0] l, o, v, e;
initial
begin
for (l=0; l<256; l=l+1)
begin
test_addr[l] <= 0;
test_count[l] <= 0;
test_section[l] <= 2'h1;
end
test_addr[1] <= 12'h000;
test_count[1] <= 6'd1;
test_addr[2] <= 12'h010;
test_count[2] <= 6'd2;
test_addr[3] <= 12'h020;
test_count[3] <= 6'd3;
test_addr[4] <= 12'h030;
test_count[4] <= 6'd4;
test_addr[5] <= 12'h040;
test_count[5] <= 6'd5;
test_addr[6] <= 12'h050;
test_count[6] <= 6'd6;
test_addr[7] <= 12'h060;
test_count[7] <= 6'd7;
test_addr[8] <= 12'h070;
test_count[8] <= 6'd8;
test_addr[9] <= 12'h101;
test_count[9] <= 6'd1;
test_addr[10] <= 12'h111;
test_count[10] <= 6'd2;
test_addr[11] <= 12'h121;
test_count[11] <= 6'd3;
test_addr[12] <= 12'h131;
test_count[12] <= 6'd4;
test_addr[13] <= 12'h141;
test_count[13] <= 6'd5;
test_addr[14] <= 12'h151;
test_count[14] <= 6'd6;
test_addr[15] <= 12'h161;
test_count[15] <= 6'd7;
test_addr[16] <= 12'h171;
test_count[16] <= 6'd8;
test_addr[17] <= 12'h180;
test_count[17] <= 6'd15;
test_section[17] <= 2'h2;
test_addr[18] <= 12'h190;
test_count[18] <= 6'd1;
test_section[18] <= 2'h2;
test_addr[19] <= 12'h1a0;
test_count[19] <= 6'd2;
test_section[19] <= 2'h2;
test_addr[20] <= 12'h1b0;
test_count[20] <= 6'd6;
test_section[20] <= 2'h2;
end
always @(posedge CLK)
if (!RST)
begin
c <= 0; mvblck_RST <= 0; working_prev <= 0; ISSUE <= 0;
testno <= 8'h00; maxtests <= 1+ 20;
end
else
begin
c <= c+1;
if (c == 32'd256)
mvblck_RST <= 1;
working_prev <= WORKING;
if (trigger)
begin
if (COUNT_SENT != COUNT_REQ)
$display("XXX count of sent #%d got %x want %x @ %d",
testno, COUNT_SENT, COUNT_REQ, c);
end
if (trigger_all && (testno < maxtests))
begin
testno <= testno +1;
$display("TEST #%d", testno+1);
ISSUE <= 1;
end
else
if (WORKING)
ISSUE <= 0;
end
endmodule | 1 |
138,672 | data/full_repos/permissive/85002992/test/test_mvblck_todram.v | 85,002,992 | test_mvblck_todram.v | v | 487 | 73 | [] | [] | [] | null | line:25: before: "&" | null | 1: b'%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:3: Cannot find include file: test_inc.v\n`include "test_inc.v" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/test_inc.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/test_inc.v.v\n data/full_repos/permissive/85002992/test,data/full_repos/permissive/85002992/test_inc.v.sv\n test_inc.v\n test_inc.v.v\n test_inc.v.sv\n obj_dir/test_inc.v\n obj_dir/test_inc.v.v\n obj_dir/test_inc.v.sv\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:6: Cannot find include file: ../mcu/commands.v\n`include "../mcu/commands.v" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:7: Cannot find include file: ../mcu/state2.v\n`include "../mcu/state2.v" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:8: Cannot find include file: ../mcu/initializer.v\n`include "../mcu/initializer.v" \n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:9: Cannot find include file: ../mcu/integration2.v\n`include "../mcu/integration2.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:12: Cannot find include file: ../cache/cpu_mcu2.v\n`include "../cache/cpu_mcu2.v" \n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:15: Cannot find include file: ../hyperfabric/lsab.v\n`include "../hyperfabric/lsab.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:18: Cannot find include file: ../hyperfabric/transport.v\n`include "../hyperfabric/transport.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:19: Cannot find include file: ../hyperfabric/mvblck_todram.v\n`include "../hyperfabric/mvblck_todram.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:20: Cannot find include file: ../hyperfabric/mvblck_frdram.v\n`include "../hyperfabric/mvblck_frdram.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:246: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_n <= 0; CLK_p <= 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:247: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_dp <= 1; CLK_dn <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:248: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_n <= 1; CLK_p <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:249: Unsupported: Ignoring delay on this delayed statement.\n #1.5 CLK_dp <= 0; CLK_dn <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:254: Unsupported: Ignoring delay on this delayed statement.\n #1.5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:255: Unsupported: Ignoring delay on this delayed statement.\n #4.5 CPU_CLK <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:256: Unsupported: Ignoring delay on this delayed statement.\n #3 CPU_CLK <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:456: Unsupported: Ignoring delay on this delayed statement.\n #14.34 RST_ddr <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:457: Unsupported: Ignoring delay on this delayed statement.\n #400000 RST <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85002992/test/test_mvblck_todram.v:458: Unsupported: Ignoring delay on this delayed statement.\n #18432;\n ^\n%Error: Exiting due to 10 error(s), 10 warning(s)\n' | 302,645 | module | module GlaDOS;
reg CLK_p, CLK_n, CLK_dp, CLK_dn, RST, RST_ddr, CPU_CLK;
reg [31:0] counter, minicounter, readcount, readcount2, readcount_r;
initial
forever
begin
#1.5 CLK_n <= 0; CLK_p <= 1;
#1.5 CLK_dp <= 1; CLK_dn <= 0;
#1.5 CLK_n <= 1; CLK_p <= 0;
#1.5 CLK_dp <= 0; CLK_dn <= 1;
end
initial
forever
begin
#1.5;
#4.5 CPU_CLK <= 1;
#3 CPU_CLK <= 0;
end
wire [31:0] w_data0, w_data1, w_data2, w_data3;
wire w_write, w_read;
wire [1:0] w_write_fifo, w_read_fifo;
wire w_int0, w_int1, w_int2, w_int3;
wire [3:0] w_care;
wire [31:0] w_out;
wire w_s0, w_s1, w_s2, w_s3;
wire CKE, DQS, DM, CS;
wire [2:0] COMMAND;
wire [12:0] ADDRESS;
wire [1:0] BANK;
wire [15:0] DQ;
wire [31:0] mcu_data_into, mcu_data_outof;
wire [11:0] hf_coll_addr;
wire [3:0] hf_we_array;
wire hf_req_access;
wire mvblck_RST, w_issue, w_working;
wire [1:0] w_section;
wire [5:0] w_count_req, w_count_sent;
wire [11:0] w_start_address;
reg mcu_req_access;
ddr ddr_mem(.Clk(CLK_p),
.Clk_n(CLK_n),
.Cke(CKE),
.Cs_n(CS),
.Ras_n(COMMAND[2]),
.Cas_n(COMMAND[1]),
.We_n(COMMAND[0]),
.Ba(BANK),
.Addr(ADDRESS),
.Dm({DM,DM}),
.Dq(DQ),
.Dqs({DQS,DQS}));
ddr_memory_controler ddr_mc(.CLK_n(CLK_n),
.CLK_p(CLK_p),
.CLK_dp(CLK_dp),
.CLK_dn(CLK_dn),
.RST(RST_ddr),
.CKE(CKE),
.COMMAND(COMMAND),
.ADDRESS(ADDRESS),
.BANK(BANK),
.DQ(DQ),
.DQS(DQS),
.DM(DM),
.CS(CS),
.rand_req_address(0),
.rand_req_we(0),
.rand_req_we_array(0),
.rand_req(0),
.rand_req_ack(),
.bulk_req_address({14'd0,hf_coll_addr}),
.bulk_req_we(mcu_req_access),
.bulk_req_we_array(hf_we_array),
.bulk_req(mcu_req_access),
.bulk_req_ack(),
.bulk_req_algn(1'b1),
.bulk_req_algn_ack(),
.user_req_datain(mcu_data_into),
.user_req_dataout(mcu_data_outof));
test_fill_lsab lsab_write(.CLK(CLK_n),
.RST(RST),
.DATA0(w_data0), .DATA1(w_data1),
.DATA2(w_data2), .DATA3(w_data3),
.WRITE(w_write),
.WRITE_FIFO(w_write_fifo),
.INT0(w_int0), .INT1(w_int1),
.INT2(w_int2), .INT3(w_int3));
trans_core hyperfabric_switch(.CLK(CLK_n),
.RST(RST),
.out_0(), .out_1(),
.out_2(), .out_3(),
.out_4(), .out_5(mcu_data_into),
.out_6(), .out_7(),
.in_0(0), .in_1(w_out),
.in_2(0), .in_3(mcu_data_outof),
.in_4(0), .in_5(0),
.in_6(0), .in_7(0),
.isel(16'h0200),
.osel(16'h0020));
lsab_cr lsab(.CLK(CLK_n),
.RST(RST),
.READ(w_read),
.WRITE0(w_write),
.WRITE1(w_write),
.WRITE2(w_write),
.WRITE3(w_write),
.READ_FIFO(w_read_fifo),
.WRITE_FIFO(w_write_fifo),
.IN_0(w_data0), .IN_1(w_data1),
.IN_2(w_data2), .IN_3(w_data3),
.INT_IN_0(w_int0), .INT_IN_1(w_int1),
.INT_IN_2(w_int2), .INT_IN_3(w_int3),
.CAREOF_INT_0(1'b1), .CAREOF_INT_1(1'b1),
.CAREOF_INT_2(1'b1), .CAREOF_INT_3(1'b1),
.OUT(w_out),
.EMPTY_0(), .EMPTY_1(),
.EMPTY_2(), .EMPTY_3(),
.STOP_0(w_s0), .STOP_1(w_s1),
.STOP_2(w_s2), .STOP_3(w_s3));
hyper_mvblck_todram mut(.CLK(CLK_n),
.RST(mvblck_RST),
.LSAB_0_STOP(w_s0),
.LSAB_1_STOP(w_s1),
.LSAB_2_STOP(w_s2),
.LSAB_3_STOP(w_s3),
.LSAB_READ(w_read),
.LSAB_SECTION(w_read_fifo),
.START_ADDRESS(w_start_address),
.COUNT_REQ(w_count_req),
.SECTION(w_section),
.ISSUE(w_issue),
.COUNT_SENT(w_count_sent),
.WORKING(w_working),
.MCU_COLL_ADDRESS(hf_coll_addr),
.MCU_WE_ARRAY(hf_we_array),
.MCU_REQUEST_ACCESS(hf_req_access));
test_mvblck test_drv(.CLK(CLK_n),
.RST(RST),
.mvblck_RST(mvblck_RST),
.START_ADDRESS(w_start_address),
.COUNT_REQ(w_count_req),
.SECTION(w_section),
.ISSUE(w_issue),
.COUNT_SENT(w_count_sent),
.WORKING(w_working));
always @(posedge CLK_n)
if (!RST)
begin
mcu_req_access <= 0;
end
else
begin
counter <= counter +1;
mcu_req_access <= hf_req_access;
end
initial
begin
counter <= 0;
RST <= 0; RST_ddr <= 0;
#14.34 RST_ddr <= 1;
#400000 RST <= 1;
#18432;
$finish;
end
endmodule | module GlaDOS; |
reg CLK_p, CLK_n, CLK_dp, CLK_dn, RST, RST_ddr, CPU_CLK;
reg [31:0] counter, minicounter, readcount, readcount2, readcount_r;
initial
forever
begin
#1.5 CLK_n <= 0; CLK_p <= 1;
#1.5 CLK_dp <= 1; CLK_dn <= 0;
#1.5 CLK_n <= 1; CLK_p <= 0;
#1.5 CLK_dp <= 0; CLK_dn <= 1;
end
initial
forever
begin
#1.5;
#4.5 CPU_CLK <= 1;
#3 CPU_CLK <= 0;
end
wire [31:0] w_data0, w_data1, w_data2, w_data3;
wire w_write, w_read;
wire [1:0] w_write_fifo, w_read_fifo;
wire w_int0, w_int1, w_int2, w_int3;
wire [3:0] w_care;
wire [31:0] w_out;
wire w_s0, w_s1, w_s2, w_s3;
wire CKE, DQS, DM, CS;
wire [2:0] COMMAND;
wire [12:0] ADDRESS;
wire [1:0] BANK;
wire [15:0] DQ;
wire [31:0] mcu_data_into, mcu_data_outof;
wire [11:0] hf_coll_addr;
wire [3:0] hf_we_array;
wire hf_req_access;
wire mvblck_RST, w_issue, w_working;
wire [1:0] w_section;
wire [5:0] w_count_req, w_count_sent;
wire [11:0] w_start_address;
reg mcu_req_access;
ddr ddr_mem(.Clk(CLK_p),
.Clk_n(CLK_n),
.Cke(CKE),
.Cs_n(CS),
.Ras_n(COMMAND[2]),
.Cas_n(COMMAND[1]),
.We_n(COMMAND[0]),
.Ba(BANK),
.Addr(ADDRESS),
.Dm({DM,DM}),
.Dq(DQ),
.Dqs({DQS,DQS}));
ddr_memory_controler ddr_mc(.CLK_n(CLK_n),
.CLK_p(CLK_p),
.CLK_dp(CLK_dp),
.CLK_dn(CLK_dn),
.RST(RST_ddr),
.CKE(CKE),
.COMMAND(COMMAND),
.ADDRESS(ADDRESS),
.BANK(BANK),
.DQ(DQ),
.DQS(DQS),
.DM(DM),
.CS(CS),
.rand_req_address(0),
.rand_req_we(0),
.rand_req_we_array(0),
.rand_req(0),
.rand_req_ack(),
.bulk_req_address({14'd0,hf_coll_addr}),
.bulk_req_we(mcu_req_access),
.bulk_req_we_array(hf_we_array),
.bulk_req(mcu_req_access),
.bulk_req_ack(),
.bulk_req_algn(1'b1),
.bulk_req_algn_ack(),
.user_req_datain(mcu_data_into),
.user_req_dataout(mcu_data_outof));
test_fill_lsab lsab_write(.CLK(CLK_n),
.RST(RST),
.DATA0(w_data0), .DATA1(w_data1),
.DATA2(w_data2), .DATA3(w_data3),
.WRITE(w_write),
.WRITE_FIFO(w_write_fifo),
.INT0(w_int0), .INT1(w_int1),
.INT2(w_int2), .INT3(w_int3));
trans_core hyperfabric_switch(.CLK(CLK_n),
.RST(RST),
.out_0(), .out_1(),
.out_2(), .out_3(),
.out_4(), .out_5(mcu_data_into),
.out_6(), .out_7(),
.in_0(0), .in_1(w_out),
.in_2(0), .in_3(mcu_data_outof),
.in_4(0), .in_5(0),
.in_6(0), .in_7(0),
.isel(16'h0200),
.osel(16'h0020));
lsab_cr lsab(.CLK(CLK_n),
.RST(RST),
.READ(w_read),
.WRITE0(w_write),
.WRITE1(w_write),
.WRITE2(w_write),
.WRITE3(w_write),
.READ_FIFO(w_read_fifo),
.WRITE_FIFO(w_write_fifo),
.IN_0(w_data0), .IN_1(w_data1),
.IN_2(w_data2), .IN_3(w_data3),
.INT_IN_0(w_int0), .INT_IN_1(w_int1),
.INT_IN_2(w_int2), .INT_IN_3(w_int3),
.CAREOF_INT_0(1'b1), .CAREOF_INT_1(1'b1),
.CAREOF_INT_2(1'b1), .CAREOF_INT_3(1'b1),
.OUT(w_out),
.EMPTY_0(), .EMPTY_1(),
.EMPTY_2(), .EMPTY_3(),
.STOP_0(w_s0), .STOP_1(w_s1),
.STOP_2(w_s2), .STOP_3(w_s3));
hyper_mvblck_todram mut(.CLK(CLK_n),
.RST(mvblck_RST),
.LSAB_0_STOP(w_s0),
.LSAB_1_STOP(w_s1),
.LSAB_2_STOP(w_s2),
.LSAB_3_STOP(w_s3),
.LSAB_READ(w_read),
.LSAB_SECTION(w_read_fifo),
.START_ADDRESS(w_start_address),
.COUNT_REQ(w_count_req),
.SECTION(w_section),
.ISSUE(w_issue),
.COUNT_SENT(w_count_sent),
.WORKING(w_working),
.MCU_COLL_ADDRESS(hf_coll_addr),
.MCU_WE_ARRAY(hf_we_array),
.MCU_REQUEST_ACCESS(hf_req_access));
test_mvblck test_drv(.CLK(CLK_n),
.RST(RST),
.mvblck_RST(mvblck_RST),
.START_ADDRESS(w_start_address),
.COUNT_REQ(w_count_req),
.SECTION(w_section),
.ISSUE(w_issue),
.COUNT_SENT(w_count_sent),
.WORKING(w_working));
always @(posedge CLK_n)
if (!RST)
begin
mcu_req_access <= 0;
end
else
begin
counter <= counter +1;
mcu_req_access <= hf_req_access;
end
initial
begin
counter <= 0;
RST <= 0; RST_ddr <= 0;
#14.34 RST_ddr <= 1;
#400000 RST <= 1;
#18432;
$finish;
end
endmodule | 1 |
138,680 | data/full_repos/permissive/85134286/Example Design/example.v | 85,134,286 | example.v | v | 143 | 123 | [] | [] | [] | null | line:143 column:2: Illegal character '`' | null | 1: b'%Error: Cannot find file containing module: Design,data/full_repos/permissive/85134286\n ... Looked in:\n data/full_repos/permissive/85134286/Example/Design,data/full_repos/permissive/85134286\n data/full_repos/permissive/85134286/Example/Design,data/full_repos/permissive/85134286.v\n data/full_repos/permissive/85134286/Example/Design,data/full_repos/permissive/85134286.sv\n Design,data/full_repos/permissive/85134286\n Design,data/full_repos/permissive/85134286.v\n Design,data/full_repos/permissive/85134286.sv\n obj_dir/Design,data/full_repos/permissive/85134286\n obj_dir/Design,data/full_repos/permissive/85134286.v\n obj_dir/Design,data/full_repos/permissive/85134286.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/85134286/Example\n%Error: Cannot find file containing module: Design/example.v\n%Error: Exiting due to 3 error(s)\n' | 302,660 | module | module i2c_example (
input wire [7:0] hi_in,
output wire [1:0] hi_out,
inout wire [15:0] hi_inout,
inout wire hi_aa,
output wire hi_muxsel,
output wire gyro_cs,
output wire gyro_sa0,
inout wire gyro_scl,
inout wire gyro_sda
);
wire clk_ti;
wire [30:0] ok1;
wire [16:0] ok2;
wire [15:0] ep00wire, ep10wire;
wire [15:0] ti50_clkti;
wire [15:0] to70_clkti;
assign hi_muxsel = 1'b0;
assign gyro_cs = 1'b1;
assign gyro_sa0 = 1'b0;
wire reset_syspll;
wire reset_pixdcm;
wire reset_async;
wire reset_clkpix;
wire reset_clkti;
wire reset_clk0;
assign reset_async = ep00wire[0];
sync_reset sync_reset2 (.clk(clk_ti), .async_reset(reset_async), .sync_reset(reset_clkti));
wire [15:0] memdin;
wire [7:0] memdout;
i2cController # (
.CLOCK_STRETCH_SUPPORT (1),
.CLOCK_DIVIDER (480)
) i2c_ctrl0 (
.clk (clk_ti),
.reset (reset_clkti),
.start (ti50_clkti[0]),
.done (to70_clkti[0]),
.memclk (clk_ti),
.memstart (ti50_clkti[1]),
.memwrite (ti50_clkti[2]),
.memread (ti50_clkti[3]),
.memdin (memdin[7:0]),
.memdout (memdout[7:0]),
.i2c_sclk (gyro_scl),
.i2c_sdat (gyro_sda)
);
okHost host (
.hi_in (hi_in),
.hi_out (hi_out),
.hi_inout (hi_inout),
.hi_aa (hi_aa),
.ti_clk (clk_ti),
.ok1 (ok1),
.ok2 (ok2)
);
wire [17*2-1:0] ok2x;
okWireOR # (.N(2)) wireOR (.ok2(ok2), .ok2s(ok2x));
okWireIn wi00 (.ok1(ok1), .ep_addr(8'h00), .ep_dataout(ep00wire));
okWireIn wi10 (.ok1(ok1), .ep_addr(8'h10), .ep_dataout(memdin));
okTriggerIn ti50 (.ok1(ok1), .ep_addr(8'h50), .ep_clk(clk_ti), .ep_trigger(ti50_clkti));
okTriggerOut to70 (.ok1(ok1), .ok2(ok2x[ 0*17 +: 17 ]), .ep_addr(8'h70), .ep_clk(clk_ti), .ep_trigger(to70_clkti));
okWireOut wo30 (.ok1(ok1), .ok2(ok2x[ 1*17 +: 17 ]), .ep_addr(8'h30), .ep_datain({8'b0, memdout}));
endmodule | module i2c_example (
input wire [7:0] hi_in,
output wire [1:0] hi_out,
inout wire [15:0] hi_inout,
inout wire hi_aa,
output wire hi_muxsel,
output wire gyro_cs,
output wire gyro_sa0,
inout wire gyro_scl,
inout wire gyro_sda
); |
wire clk_ti;
wire [30:0] ok1;
wire [16:0] ok2;
wire [15:0] ep00wire, ep10wire;
wire [15:0] ti50_clkti;
wire [15:0] to70_clkti;
assign hi_muxsel = 1'b0;
assign gyro_cs = 1'b1;
assign gyro_sa0 = 1'b0;
wire reset_syspll;
wire reset_pixdcm;
wire reset_async;
wire reset_clkpix;
wire reset_clkti;
wire reset_clk0;
assign reset_async = ep00wire[0];
sync_reset sync_reset2 (.clk(clk_ti), .async_reset(reset_async), .sync_reset(reset_clkti));
wire [15:0] memdin;
wire [7:0] memdout;
i2cController # (
.CLOCK_STRETCH_SUPPORT (1),
.CLOCK_DIVIDER (480)
) i2c_ctrl0 (
.clk (clk_ti),
.reset (reset_clkti),
.start (ti50_clkti[0]),
.done (to70_clkti[0]),
.memclk (clk_ti),
.memstart (ti50_clkti[1]),
.memwrite (ti50_clkti[2]),
.memread (ti50_clkti[3]),
.memdin (memdin[7:0]),
.memdout (memdout[7:0]),
.i2c_sclk (gyro_scl),
.i2c_sdat (gyro_sda)
);
okHost host (
.hi_in (hi_in),
.hi_out (hi_out),
.hi_inout (hi_inout),
.hi_aa (hi_aa),
.ti_clk (clk_ti),
.ok1 (ok1),
.ok2 (ok2)
);
wire [17*2-1:0] ok2x;
okWireOR # (.N(2)) wireOR (.ok2(ok2), .ok2s(ok2x));
okWireIn wi00 (.ok1(ok1), .ep_addr(8'h00), .ep_dataout(ep00wire));
okWireIn wi10 (.ok1(ok1), .ep_addr(8'h10), .ep_dataout(memdin));
okTriggerIn ti50 (.ok1(ok1), .ep_addr(8'h50), .ep_clk(clk_ti), .ep_trigger(ti50_clkti));
okTriggerOut to70 (.ok1(ok1), .ok2(ok2x[ 0*17 +: 17 ]), .ep_addr(8'h70), .ep_clk(clk_ti), .ep_trigger(to70_clkti));
okWireOut wo30 (.ok1(ok1), .ok2(ok2x[ 1*17 +: 17 ]), .ep_addr(8'h30), .ep_datain({8'b0, memdout}));
endmodule | 5 |
138,682 | data/full_repos/permissive/85134286/src/i2cTokenizer.v | 85,134,286 | i2cTokenizer.v | v | 340 | 82 | [] | [] | [] | null | line:340 column:2: Illegal character '`' | data/verilator_xmls/d339a2c8-b5dd-407c-9152-fe26493df9fc.xml | null | 302,665 | module | module i2cTokenizer(
input wire clk,
input wire reset,
input wire tok_start,
input wire tok_stop,
input wire tok_write,
input wire tok_read,
output reg tok_done,
input wire [7:0] tok_datain,
output wire [7:0] tok_dataout,
input wire tok_rack,
output reg tok_wack,
inout wire i2c_sclk,
inout wire i2c_sdat
);
parameter CLOCK_STRETCH_SUPPORT = 1;
parameter CLOCK_DIVIDER = 16'd32;
reg [15:0] divcount;
reg divenable;
reg stretch_clk;
reg [3:0] i2c_shift_count;
reg [7:0] i2c_shift_reg;
reg i2c_dout;
reg i2c_sdat_oen;
reg i2c_sclk_oen;
reg i2c_sclk_oen_d;
reg tok_start_go;
reg tok_stop_go;
reg tok_write_go;
reg tok_read_go;
reg tok_rack_r;
assign i2c_sdat = (i2c_sdat_oen) ? (1'bz) : (i2c_dout);
assign i2c_sclk = (i2c_sclk_oen) ? (1'bz) : (1'b0);
assign tok_dataout = i2c_shift_reg;
integer state;
parameter s_idle = 0,
s_start0 = 10,
s_start1 = 11,
s_start2 = 12,
s_start3 = 13,
s_start4 = 14,
s_write0 = 20,
s_write1 = 21,
s_write2 = 22,
s_write3 = 23,
s_read0 = 30,
s_read1 = 31,
s_read2 = 32,
s_read3 = 33,
s_stop0 = 40,
s_stop1 = 41,
s_stop2 = 42,
s_stop3 = 43;
always @(posedge clk) begin
if (reset) begin
divcount <= 16'h0000;
divenable <= 1'b0;
state <= s_idle;
i2c_sclk_oen <= 1'b1;
i2c_dout <= 1'b1;
i2c_sdat_oen <= 1'b1;
i2c_shift_reg <= 8'b0;
i2c_shift_count <= 4'b0;
stretch_clk <= 1'b0;
tok_wack <= 1'b0;
tok_done <= 1'b0;
tok_start_go <= 1'b0;
tok_stop_go <= 1'b0;
tok_write_go <= 1'b0;
tok_read_go <= 1'b0;
tok_rack_r <= 1'b0;
end else begin
if (1 == CLOCK_STRETCH_SUPPORT) begin
i2c_sclk_oen_d <= i2c_sclk_oen;
stretch_clk <= (i2c_sclk_oen & ~i2c_sclk_oen_d & ~i2c_sclk) |
(stretch_clk & ~i2c_sclk);
end
divenable <= 1'b0;
if (divcount == 16'h0000) begin
divcount <= CLOCK_DIVIDER;
divenable <= 1'b1;
end else begin
if(1'b0 == stretch_clk) begin
divcount <= divcount - 1'b1;
end else begin
divcount <= CLOCK_DIVIDER;
end
end
end
tok_done <= 1'b0;
if (tok_done == 1'b1) begin
tok_start_go <= 1'b0;
tok_stop_go <= 1'b0;
tok_write_go <= 1'b0;
tok_read_go <= 1'b0;
end
if (tok_start == 1'b1) begin
tok_start_go <= 1'b1;
end
if (tok_stop == 1'b1) begin
tok_stop_go <= 1'b1;
end
if (tok_write == 1'b1) begin
tok_write_go <= 1'b1;
i2c_shift_count <= 8;
i2c_shift_reg <= tok_datain;
end
if (tok_read == 1'b1) begin
tok_read_go <= 1'b1;
i2c_shift_count <= 8;
i2c_shift_reg <= 8'h00;
tok_rack_r <= tok_rack;
end
if (divenable) begin
case (state)
s_idle: begin
if (tok_start_go == 1'b1) begin
i2c_dout <= 1'b0;
state <= s_start0;
end else if (tok_stop_go == 1'b1) begin
i2c_dout <= 1'b0;
state <= s_stop0;
end else if (tok_write_go == 1'b1) begin
state <= s_write0;
end else if (tok_read_go == 1'b1) begin
state <= s_read0;
end
end
s_start0: begin
i2c_sdat_oen <= 1'b1;
state <= s_start1;
end
s_start1: begin
i2c_sdat_oen <= 1'b1;
i2c_sclk_oen <= 1'b1;
state <= s_start2;
end
s_start2: begin
i2c_sdat_oen <= 1'b0;
i2c_sclk_oen <= 1'b1;
state <= s_start3;
end
s_start3: begin
state <= s_start4;
end
s_start4: begin
i2c_sclk_oen <= 1'b0;
tok_done <= 1'b1;
state <= s_idle;
end
s_write0: begin
i2c_sclk_oen <= 1'b0;
i2c_dout <= i2c_shift_reg[7];
i2c_shift_reg <= {i2c_shift_reg[6:0], 1'b0};
if (0 == i2c_shift_count) begin
i2c_sdat_oen <= 1'b1;
end else begin
i2c_sdat_oen <= 1'b0;
end
state <= s_write1;
end
s_write1: begin
i2c_sclk_oen <= 1'b1;
if (0 == i2c_shift_count) begin
tok_wack <= i2c_sdat;
end
state <= s_write2;
end
s_write2: begin
state <= s_write3;
end
s_write3: begin
i2c_sclk_oen <= 1'b0;
i2c_sdat_oen <= 1'b0;
if (i2c_shift_count > 0) begin
i2c_shift_count <= i2c_shift_count - 1'b1;
state <= s_write0;
end else begin
tok_done <= 1'b1;
state <= s_idle;
end
end
s_read0: begin
i2c_sclk_oen <= 1'b0;
if (0 == i2c_shift_count) begin
i2c_sdat_oen <= 1'b0;
i2c_dout <= tok_rack_r;
end else begin
i2c_sdat_oen <= 1'b1;
end
state <= s_read1;
end
s_read1: begin
i2c_sclk_oen <= 1'b1;
state <= s_read2;
end
s_read2: begin
if (i2c_shift_count > 0) begin
i2c_shift_reg <= {i2c_shift_reg[6:0], i2c_sdat};
end
state <= s_read3;
end
s_read3: begin
i2c_sclk_oen <= 1'b0;
if (i2c_shift_count > 0) begin
i2c_shift_count <= i2c_shift_count - 1'b1;
state <= s_read0;
end else begin
tok_done <= 1'b1;
state <= s_idle;
end
end
s_stop0: begin
i2c_sdat_oen <= 1'b0;
i2c_sclk_oen <= 1'b0;
state <= s_stop1;
end
s_stop1: begin
i2c_sclk_oen <= 1'b1;
state <= s_stop2;
end
s_stop2: begin
state <= s_stop3;
end
s_stop3: begin
i2c_sdat_oen <= 1'b1;
tok_done <= 1'b1;
state <= s_idle;
end
endcase
end
end
endmodule | module i2cTokenizer(
input wire clk,
input wire reset,
input wire tok_start,
input wire tok_stop,
input wire tok_write,
input wire tok_read,
output reg tok_done,
input wire [7:0] tok_datain,
output wire [7:0] tok_dataout,
input wire tok_rack,
output reg tok_wack,
inout wire i2c_sclk,
inout wire i2c_sdat
); |
parameter CLOCK_STRETCH_SUPPORT = 1;
parameter CLOCK_DIVIDER = 16'd32;
reg [15:0] divcount;
reg divenable;
reg stretch_clk;
reg [3:0] i2c_shift_count;
reg [7:0] i2c_shift_reg;
reg i2c_dout;
reg i2c_sdat_oen;
reg i2c_sclk_oen;
reg i2c_sclk_oen_d;
reg tok_start_go;
reg tok_stop_go;
reg tok_write_go;
reg tok_read_go;
reg tok_rack_r;
assign i2c_sdat = (i2c_sdat_oen) ? (1'bz) : (i2c_dout);
assign i2c_sclk = (i2c_sclk_oen) ? (1'bz) : (1'b0);
assign tok_dataout = i2c_shift_reg;
integer state;
parameter s_idle = 0,
s_start0 = 10,
s_start1 = 11,
s_start2 = 12,
s_start3 = 13,
s_start4 = 14,
s_write0 = 20,
s_write1 = 21,
s_write2 = 22,
s_write3 = 23,
s_read0 = 30,
s_read1 = 31,
s_read2 = 32,
s_read3 = 33,
s_stop0 = 40,
s_stop1 = 41,
s_stop2 = 42,
s_stop3 = 43;
always @(posedge clk) begin
if (reset) begin
divcount <= 16'h0000;
divenable <= 1'b0;
state <= s_idle;
i2c_sclk_oen <= 1'b1;
i2c_dout <= 1'b1;
i2c_sdat_oen <= 1'b1;
i2c_shift_reg <= 8'b0;
i2c_shift_count <= 4'b0;
stretch_clk <= 1'b0;
tok_wack <= 1'b0;
tok_done <= 1'b0;
tok_start_go <= 1'b0;
tok_stop_go <= 1'b0;
tok_write_go <= 1'b0;
tok_read_go <= 1'b0;
tok_rack_r <= 1'b0;
end else begin
if (1 == CLOCK_STRETCH_SUPPORT) begin
i2c_sclk_oen_d <= i2c_sclk_oen;
stretch_clk <= (i2c_sclk_oen & ~i2c_sclk_oen_d & ~i2c_sclk) |
(stretch_clk & ~i2c_sclk);
end
divenable <= 1'b0;
if (divcount == 16'h0000) begin
divcount <= CLOCK_DIVIDER;
divenable <= 1'b1;
end else begin
if(1'b0 == stretch_clk) begin
divcount <= divcount - 1'b1;
end else begin
divcount <= CLOCK_DIVIDER;
end
end
end
tok_done <= 1'b0;
if (tok_done == 1'b1) begin
tok_start_go <= 1'b0;
tok_stop_go <= 1'b0;
tok_write_go <= 1'b0;
tok_read_go <= 1'b0;
end
if (tok_start == 1'b1) begin
tok_start_go <= 1'b1;
end
if (tok_stop == 1'b1) begin
tok_stop_go <= 1'b1;
end
if (tok_write == 1'b1) begin
tok_write_go <= 1'b1;
i2c_shift_count <= 8;
i2c_shift_reg <= tok_datain;
end
if (tok_read == 1'b1) begin
tok_read_go <= 1'b1;
i2c_shift_count <= 8;
i2c_shift_reg <= 8'h00;
tok_rack_r <= tok_rack;
end
if (divenable) begin
case (state)
s_idle: begin
if (tok_start_go == 1'b1) begin
i2c_dout <= 1'b0;
state <= s_start0;
end else if (tok_stop_go == 1'b1) begin
i2c_dout <= 1'b0;
state <= s_stop0;
end else if (tok_write_go == 1'b1) begin
state <= s_write0;
end else if (tok_read_go == 1'b1) begin
state <= s_read0;
end
end
s_start0: begin
i2c_sdat_oen <= 1'b1;
state <= s_start1;
end
s_start1: begin
i2c_sdat_oen <= 1'b1;
i2c_sclk_oen <= 1'b1;
state <= s_start2;
end
s_start2: begin
i2c_sdat_oen <= 1'b0;
i2c_sclk_oen <= 1'b1;
state <= s_start3;
end
s_start3: begin
state <= s_start4;
end
s_start4: begin
i2c_sclk_oen <= 1'b0;
tok_done <= 1'b1;
state <= s_idle;
end
s_write0: begin
i2c_sclk_oen <= 1'b0;
i2c_dout <= i2c_shift_reg[7];
i2c_shift_reg <= {i2c_shift_reg[6:0], 1'b0};
if (0 == i2c_shift_count) begin
i2c_sdat_oen <= 1'b1;
end else begin
i2c_sdat_oen <= 1'b0;
end
state <= s_write1;
end
s_write1: begin
i2c_sclk_oen <= 1'b1;
if (0 == i2c_shift_count) begin
tok_wack <= i2c_sdat;
end
state <= s_write2;
end
s_write2: begin
state <= s_write3;
end
s_write3: begin
i2c_sclk_oen <= 1'b0;
i2c_sdat_oen <= 1'b0;
if (i2c_shift_count > 0) begin
i2c_shift_count <= i2c_shift_count - 1'b1;
state <= s_write0;
end else begin
tok_done <= 1'b1;
state <= s_idle;
end
end
s_read0: begin
i2c_sclk_oen <= 1'b0;
if (0 == i2c_shift_count) begin
i2c_sdat_oen <= 1'b0;
i2c_dout <= tok_rack_r;
end else begin
i2c_sdat_oen <= 1'b1;
end
state <= s_read1;
end
s_read1: begin
i2c_sclk_oen <= 1'b1;
state <= s_read2;
end
s_read2: begin
if (i2c_shift_count > 0) begin
i2c_shift_reg <= {i2c_shift_reg[6:0], i2c_sdat};
end
state <= s_read3;
end
s_read3: begin
i2c_sclk_oen <= 1'b0;
if (i2c_shift_count > 0) begin
i2c_shift_count <= i2c_shift_count - 1'b1;
state <= s_read0;
end else begin
tok_done <= 1'b1;
state <= s_idle;
end
end
s_stop0: begin
i2c_sdat_oen <= 1'b0;
i2c_sclk_oen <= 1'b0;
state <= s_stop1;
end
s_stop1: begin
i2c_sclk_oen <= 1'b1;
state <= s_stop2;
end
s_stop2: begin
state <= s_stop3;
end
s_stop3: begin
i2c_sdat_oen <= 1'b1;
tok_done <= 1'b1;
state <= s_idle;
end
endcase
end
end
endmodule | 5 |
138,683 | data/full_repos/permissive/85134286/src/okDRAM64X8D.v | 85,134,286 | okDRAM64X8D.v | v | 42 | 82 | [] | [] | [] | [(21, 41)] | null | data/verilator_xmls/154c1e36-21d9-44c0-89ca-ec2582167c6c.xml | null | 302,667 | module | module okDRAM64X8D(
input wire wclk,
input wire we,
input wire [5:0] addrA,
input wire [5:0] addrB,
input wire [7:0] din,
output wire [7:0] doutA,
output wire [7:0] doutB
);
reg [7:0] mem [63:0];
always @(posedge wclk) begin
if (we) begin
mem[addrA] <= din;
end
end
assign doutA = mem[addrA];
assign doutB = mem[addrB];
endmodule | module okDRAM64X8D(
input wire wclk,
input wire we,
input wire [5:0] addrA,
input wire [5:0] addrB,
input wire [7:0] din,
output wire [7:0] doutA,
output wire [7:0] doutB
); |
reg [7:0] mem [63:0];
always @(posedge wclk) begin
if (we) begin
mem[addrA] <= din;
end
end
assign doutA = mem[addrA];
assign doutB = mem[addrB];
endmodule | 5 |
138,686 | data/full_repos/permissive/85146369/verilog/src/d_flip.v | 85,146,369 | d_flip.v | v | 57 | 83 | [] | [] | [] | null | line:57: before: "/" | data/verilator_xmls/439b115d-362f-4793-8019-4c6c24cda553.xml | null | 302,670 | module | module dff_async_reset (
data ,
clk ,
reset ,
q
);
input data, clk, reset ;
output q;
reg q;
initial
begin
q <= 0;
end
always @ (posedge clk or posedge reset)
if (reset) begin
q <= 1'b0;
end else begin
q <= data;
end
endmodule | module dff_async_reset (
data ,
clk ,
reset ,
q
); |
input data, clk, reset ;
output q;
reg q;
initial
begin
q <= 0;
end
always @ (posedge clk or posedge reset)
if (reset) begin
q <= 1'b0;
end else begin
q <= data;
end
endmodule | 3 |
138,687 | data/full_repos/permissive/85146369/verilog/src/EXMEM.v | 85,146,369 | EXMEM.v | v | 44 | 92 | [] | [] | [] | [(23, 43)] | null | null | 1: b"%Error: data/full_repos/permissive/85146369/verilog/src/EXMEM.v:34: Cannot find file containing module: 'register'\n register #(32) reg1(.din(PC), .we(1'b1), .rst(rst), .clk(clk), .dout(PC_out));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85146369/verilog/src,data/full_repos/permissive/85146369/register\n data/full_repos/permissive/85146369/verilog/src,data/full_repos/permissive/85146369/register.v\n data/full_repos/permissive/85146369/verilog/src,data/full_repos/permissive/85146369/register.sv\n register\n register.v\n register.sv\n obj_dir/register\n obj_dir/register.v\n obj_dir/register.sv\n%Error: data/full_repos/permissive/85146369/verilog/src/EXMEM.v:35: Cannot find file containing module: 'register'\n register #(32) reg2(.din(result), .we(1'b1), .rst(rst), .clk(clk), .dout(result_out));\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/EXMEM.v:36: Cannot find file containing module: 'register'\n register #(32) reg3(.din(write_value), .we(1'b1), .rst(rst), .clk(clk), .dout(ram_write));\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/EXMEM.v:37: Cannot find file containing module: 'register'\n register #(5) reg4(.din(Rw), .we(1'b1), .rst(rst), .clk(clk), .dout(Rw_out));\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/EXMEM.v:38: Cannot find file containing module: 'register'\n register #(1) reg5(.din(we), .we(1'b1), .rst(rst), .clk(clk), .dout(we_out));\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/EXMEM.v:39: Cannot find file containing module: 'register'\n register #(2) reg6(.din(mem_label), .we(1'b1), .rst(rst), .clk(clk), .dout(mem_out));\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/EXMEM.v:40: Cannot find file containing module: 'register'\n register #(1) reg7(.din(syscall), .we(1'b1), .rst(rst), .clk(clk), .dout(syscall_out));\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/EXMEM.v:41: Cannot find file containing module: 'register'\n register #(1) reg8(.din(lbu), .we(1'b1), .rst(rst), .clk(clk), .dout(lbu_out));\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/EXMEM.v:42: Cannot find file containing module: 'register'\n register #(1) reg9(.din(jal), .we(1'b1), .rst(rst), .clk(clk), .dout(jal_out));\n ^~~~~~~~\n%Error: Exiting due to 9 error(s)\n" | 302,671 | module | module EXMEM(
input [31:0] PC, result, write_value,
input we, syscall, lbu, jal, rst, clk,
input [4:0] Rw,
input [1:0] mem_label,
output [31:0] PC_out, result_out, ram_write,
output [4:0] Rw_out,
output we_out, syscall_out, lbu_out, jal_out,
output [1:0] mem_out
);
register #(32) reg1(.din(PC), .we(1'b1), .rst(rst), .clk(clk), .dout(PC_out));
register #(32) reg2(.din(result), .we(1'b1), .rst(rst), .clk(clk), .dout(result_out));
register #(32) reg3(.din(write_value), .we(1'b1), .rst(rst), .clk(clk), .dout(ram_write));
register #(5) reg4(.din(Rw), .we(1'b1), .rst(rst), .clk(clk), .dout(Rw_out));
register #(1) reg5(.din(we), .we(1'b1), .rst(rst), .clk(clk), .dout(we_out));
register #(2) reg6(.din(mem_label), .we(1'b1), .rst(rst), .clk(clk), .dout(mem_out));
register #(1) reg7(.din(syscall), .we(1'b1), .rst(rst), .clk(clk), .dout(syscall_out));
register #(1) reg8(.din(lbu), .we(1'b1), .rst(rst), .clk(clk), .dout(lbu_out));
register #(1) reg9(.din(jal), .we(1'b1), .rst(rst), .clk(clk), .dout(jal_out));
endmodule | module EXMEM(
input [31:0] PC, result, write_value,
input we, syscall, lbu, jal, rst, clk,
input [4:0] Rw,
input [1:0] mem_label,
output [31:0] PC_out, result_out, ram_write,
output [4:0] Rw_out,
output we_out, syscall_out, lbu_out, jal_out,
output [1:0] mem_out
); |
register #(32) reg1(.din(PC), .we(1'b1), .rst(rst), .clk(clk), .dout(PC_out));
register #(32) reg2(.din(result), .we(1'b1), .rst(rst), .clk(clk), .dout(result_out));
register #(32) reg3(.din(write_value), .we(1'b1), .rst(rst), .clk(clk), .dout(ram_write));
register #(5) reg4(.din(Rw), .we(1'b1), .rst(rst), .clk(clk), .dout(Rw_out));
register #(1) reg5(.din(we), .we(1'b1), .rst(rst), .clk(clk), .dout(we_out));
register #(2) reg6(.din(mem_label), .we(1'b1), .rst(rst), .clk(clk), .dout(mem_out));
register #(1) reg7(.din(syscall), .we(1'b1), .rst(rst), .clk(clk), .dout(syscall_out));
register #(1) reg8(.din(lbu), .we(1'b1), .rst(rst), .clk(clk), .dout(lbu_out));
register #(1) reg9(.din(jal), .we(1'b1), .rst(rst), .clk(clk), .dout(jal_out));
endmodule | 3 |
138,689 | data/full_repos/permissive/85146369/verilog/src/IFID.v | 85,146,369 | IFID.v | v | 39 | 92 | [] | [] | [] | [(23, 38)] | null | null | 1: b"%Error: data/full_repos/permissive/85146369/verilog/src/IFID.v:31: Cannot find file containing module: 'register'\n register #(32) reg1(.din(PC_plus), .we(~lock), .rst(rst), .clk(clk), .dout(PC_out));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85146369/verilog/src,data/full_repos/permissive/85146369/register\n data/full_repos/permissive/85146369/verilog/src,data/full_repos/permissive/85146369/register.v\n data/full_repos/permissive/85146369/verilog/src,data/full_repos/permissive/85146369/register.sv\n register\n register.v\n register.sv\n obj_dir/register\n obj_dir/register.v\n obj_dir/register.sv\n%Error: data/full_repos/permissive/85146369/verilog/src/IFID.v:32: Cannot find file containing module: 'register'\n register #(32) reg2(.din(instrction), .we(~lock), .rst(rst), .clk(clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/IFID.v:34: Cannot find file containing module: 'register'\n register #(1) reg3(.din(int_trigger), .we(~lock), .rst(rst), .clk(clk), .dout(int_sig));\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/IFID.v:35: Cannot find file containing module: 'register'\n register #(2) reg4(.din(which_int), .we(~lock), .rst(rst), .clk(clk), .dout(int_num_out));\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/IFID.v:36: Cannot find file containing module: 'register'\n register #(32) reg5(.din(EPC), .we(~lock), .rst(rst), .clk(clk), .dout(EPC_out));\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/IFID.v:37: Cannot find file containing module: 'register'\n register #(32) reg6(.din(IE), .we(~lock), .rst(rst), .clk(clk), .dout(IE_out));\n ^~~~~~~~\n%Error: Exiting due to 6 error(s)\n" | 302,673 | module | module IFID(
input lock, int_trigger, rst, clk,
input [31:0] PC_plus, instrction, EPC, IE,
input [1:0] which_int,
output [31:0] PC_out, instrction_out, EPC_out, IE_out,
output int_sig,
output [1:0] int_num_out
);
register #(32) reg1(.din(PC_plus), .we(~lock), .rst(rst), .clk(clk), .dout(PC_out));
register #(32) reg2(.din(instrction), .we(~lock), .rst(rst), .clk(clk),
.dout(instrction_out));
register #(1) reg3(.din(int_trigger), .we(~lock), .rst(rst), .clk(clk), .dout(int_sig));
register #(2) reg4(.din(which_int), .we(~lock), .rst(rst), .clk(clk), .dout(int_num_out));
register #(32) reg5(.din(EPC), .we(~lock), .rst(rst), .clk(clk), .dout(EPC_out));
register #(32) reg6(.din(IE), .we(~lock), .rst(rst), .clk(clk), .dout(IE_out));
endmodule | module IFID(
input lock, int_trigger, rst, clk,
input [31:0] PC_plus, instrction, EPC, IE,
input [1:0] which_int,
output [31:0] PC_out, instrction_out, EPC_out, IE_out,
output int_sig,
output [1:0] int_num_out
); |
register #(32) reg1(.din(PC_plus), .we(~lock), .rst(rst), .clk(clk), .dout(PC_out));
register #(32) reg2(.din(instrction), .we(~lock), .rst(rst), .clk(clk),
.dout(instrction_out));
register #(1) reg3(.din(int_trigger), .we(~lock), .rst(rst), .clk(clk), .dout(int_sig));
register #(2) reg4(.din(which_int), .we(~lock), .rst(rst), .clk(clk), .dout(int_num_out));
register #(32) reg5(.din(EPC), .we(~lock), .rst(rst), .clk(clk), .dout(EPC_out));
register #(32) reg6(.din(IE), .we(~lock), .rst(rst), .clk(clk), .dout(IE_out));
endmodule | 3 |
138,690 | data/full_repos/permissive/85146369/verilog/src/interrupt.v | 85,146,369 | interrupt.v | v | 69 | 91 | [] | [] | [] | [(23, 68)] | null | null | 1: b'%Error: data/full_repos/permissive/85146369/verilog/src/interrupt.v:45: Cannot find file containing module: \'dff_async_reset\'\n dff_async_reset dff_a1(1\'b1, IR1_in, one, q_a1);\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85146369/verilog/src,data/full_repos/permissive/85146369/dff_async_reset\n data/full_repos/permissive/85146369/verilog/src,data/full_repos/permissive/85146369/dff_async_reset.v\n data/full_repos/permissive/85146369/verilog/src,data/full_repos/permissive/85146369/dff_async_reset.sv\n dff_async_reset\n dff_async_reset.v\n dff_async_reset.sv\n obj_dir/dff_async_reset\n obj_dir/dff_async_reset.v\n obj_dir/dff_async_reset.sv\n%Error: data/full_repos/permissive/85146369/verilog/src/interrupt.v:46: Cannot find file containing module: \'dff_async_reset\'\n dff_async_reset dff_a2(d_a2, clk, 1\'b0, one);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/interrupt.v:47: Cannot find file containing module: \'dff_async_reset\'\n dff_async_reset dff_b1(1\'b1, IR2_in, two, q_b1);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/interrupt.v:48: Cannot find file containing module: \'dff_async_reset\'\n dff_async_reset dff_b2(d_b2, clk, 1\'b0, two);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/interrupt.v:49: Cannot find file containing module: \'dff_async_reset\'\n dff_async_reset dff_c1(1\'b1, IR3_in, three, q_c1);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/interrupt.v:50: Cannot find file containing module: \'dff_async_reset\'\n dff_async_reset dff_c2(d_c2, clk, 1\'b0, three);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/interrupt.v:51: Cannot find file containing module: \'pri_encoder\'\n pri_encoder pri(.binary_out(which_int), .enable(1\'b1), .encoder_in(pri_in));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/interrupt.v:52: Cannot find file containing module: \'register\'\n register #(1) reg1((lock_value[0]|lock_value[1]), 1\'b1, rst, clk, reg_one);\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/interrupt.v:53: Cannot find file containing module: \'register\'\n register #(1) reg2(lock_value[1], 1\'b1, rst, clk, reg_two);\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/interrupt.v:54: Cannot find file containing module: \'register\'\n register #(1) reg3((lock_value[0]&lock_value[1]), 1\'b1, rst, clk, reg_three);\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/interrupt.v:55: Cannot find file containing module: \'register\'\n register #(2) cur_int(which_int, (int_sig|ex_eret), rst, clk, lock_value);\n ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/85146369/verilog/src/interrupt.v:60: Operator OR expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance interrupt\n assign int_sig = (which_int[0]|which_int[1]) & (~IE_value & int_ins);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/85146369/verilog/src/interrupt.v:60: Operator OR expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance interrupt\n assign int_sig = (which_int[0]|which_int[1]) & (~IE_value & int_ins);\n ^\n%Warning-WIDTH: data/full_repos/permissive/85146369/verilog/src/interrupt.v:60: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'int_ins\' generates 1 bits.\n : ... In instance interrupt\n assign int_sig = (which_int[0]|which_int[1]) & (~IE_value & int_ins);\n ^\n%Warning-WIDTH: data/full_repos/permissive/85146369/verilog/src/interrupt.v:60: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n : ... In instance interrupt\n assign int_sig = (which_int[0]|which_int[1]) & (~IE_value & int_ins);\n ^\n%Error: data/full_repos/permissive/85146369/verilog/src/interrupt.v:65: Cannot find file containing module: \'register\'\n register #(32) EPC_Cache(EPC_in, (ex_int_tri|(reg_jud&ex_mtc0)), rst, clk, EPC_value);\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/interrupt.v:66: Cannot find file containing module: \'register\'\n register #(1) IE_reg(EX_rt[0], (ex_int_tri|(~reg_jud&ex_mtc0)), rst, clk, IE_out);\n ^~~~~~~~\n%Error: Exiting due to 13 error(s), 4 warning(s)\n' | 302,674 | module | module interrupt(
input clk, rst, IR1_in, IR2_in, IR3_in, ex_eret, ex_mtc0, ex_int_tri, reg_jud,
input [31:0] EX_PC_next, EX_rt,
output [31:0] EPC_value, IE_value,
output int_sig,
output [1:0] which_int
);
wire one, two, three, rst1, rst2, rst3;
wire q_a1, q_b1, q_c1, d_a2, d_b2, d_c2;
wire reg_one, reg_two, reg_three, int_ins;
wire [3:0] pri_in;
wire [1:0] lock_value;
assign pri_in = {(~reg_three&three),(~reg_two&two),(~reg_one&one),1'b1};
assign d_a2 = ~rst1 & (one | q_a1);
assign d_b2 = ~rst2 & (two | q_b1);
assign d_c2 = ~rst3 & (three | q_c1);
dff_async_reset dff_a1(1'b1, IR1_in, one, q_a1);
dff_async_reset dff_a2(d_a2, clk, 1'b0, one);
dff_async_reset dff_b1(1'b1, IR2_in, two, q_b1);
dff_async_reset dff_b2(d_b2, clk, 1'b0, two);
dff_async_reset dff_c1(1'b1, IR3_in, three, q_c1);
dff_async_reset dff_c2(d_c2, clk, 1'b0, three);
pri_encoder pri(.binary_out(which_int), .enable(1'b1), .encoder_in(pri_in));
register #(1) reg1((lock_value[0]|lock_value[1]), 1'b1, rst, clk, reg_one);
register #(1) reg2(lock_value[1], 1'b1, rst, clk, reg_two);
register #(1) reg3((lock_value[0]&lock_value[1]), 1'b1, rst, clk, reg_three);
register #(2) cur_int(which_int, (int_sig|ex_eret), rst, clk, lock_value);
assign rst1 = lock_value[0]&~lock_value[1]&int_sig;
assign rst2 = ~lock_value[0]&lock_value[1]&int_sig;
assign rst3 = lock_value[0]&lock_value[1]&int_sig;
assign int_ins = (~reg_three&three)|(~reg_two&two)|(~reg_one&one);
assign int_sig = (which_int[0]|which_int[1]) & (~IE_value & int_ins);
wire epc_jud, IE_out;
wire [31:0] EPC_in;
assign epc_jud = ex_mtc0 & reg_jud;
assign EPC_in = epc_jud?EX_rt:EX_PC_next-1;
register #(32) EPC_Cache(EPC_in, (ex_int_tri|(reg_jud&ex_mtc0)), rst, clk, EPC_value);
register #(1) IE_reg(EX_rt[0], (ex_int_tri|(~reg_jud&ex_mtc0)), rst, clk, IE_out);
assign IE_value = {31'b0, IE_out};
endmodule | module interrupt(
input clk, rst, IR1_in, IR2_in, IR3_in, ex_eret, ex_mtc0, ex_int_tri, reg_jud,
input [31:0] EX_PC_next, EX_rt,
output [31:0] EPC_value, IE_value,
output int_sig,
output [1:0] which_int
); |
wire one, two, three, rst1, rst2, rst3;
wire q_a1, q_b1, q_c1, d_a2, d_b2, d_c2;
wire reg_one, reg_two, reg_three, int_ins;
wire [3:0] pri_in;
wire [1:0] lock_value;
assign pri_in = {(~reg_three&three),(~reg_two&two),(~reg_one&one),1'b1};
assign d_a2 = ~rst1 & (one | q_a1);
assign d_b2 = ~rst2 & (two | q_b1);
assign d_c2 = ~rst3 & (three | q_c1);
dff_async_reset dff_a1(1'b1, IR1_in, one, q_a1);
dff_async_reset dff_a2(d_a2, clk, 1'b0, one);
dff_async_reset dff_b1(1'b1, IR2_in, two, q_b1);
dff_async_reset dff_b2(d_b2, clk, 1'b0, two);
dff_async_reset dff_c1(1'b1, IR3_in, three, q_c1);
dff_async_reset dff_c2(d_c2, clk, 1'b0, three);
pri_encoder pri(.binary_out(which_int), .enable(1'b1), .encoder_in(pri_in));
register #(1) reg1((lock_value[0]|lock_value[1]), 1'b1, rst, clk, reg_one);
register #(1) reg2(lock_value[1], 1'b1, rst, clk, reg_two);
register #(1) reg3((lock_value[0]&lock_value[1]), 1'b1, rst, clk, reg_three);
register #(2) cur_int(which_int, (int_sig|ex_eret), rst, clk, lock_value);
assign rst1 = lock_value[0]&~lock_value[1]&int_sig;
assign rst2 = ~lock_value[0]&lock_value[1]&int_sig;
assign rst3 = lock_value[0]&lock_value[1]&int_sig;
assign int_ins = (~reg_three&three)|(~reg_two&two)|(~reg_one&one);
assign int_sig = (which_int[0]|which_int[1]) & (~IE_value & int_ins);
wire epc_jud, IE_out;
wire [31:0] EPC_in;
assign epc_jud = ex_mtc0 & reg_jud;
assign EPC_in = epc_jud?EX_rt:EX_PC_next-1;
register #(32) EPC_Cache(EPC_in, (ex_int_tri|(reg_jud&ex_mtc0)), rst, clk, EPC_value);
register #(1) IE_reg(EX_rt[0], (ex_int_tri|(~reg_jud&ex_mtc0)), rst, clk, IE_out);
assign IE_value = {31'b0, IE_out};
endmodule | 3 |
138,693 | data/full_repos/permissive/85146369/verilog/src/istWithOp.v | 85,146,369 | istWithOp.v | v | 52 | 83 | [] | [] | [] | [(23, 51)] | null | data/verilator_xmls/5fdfea38-e4f5-4749-9357-d9da8d006ac8.xml | null | 302,677 | module | module istWithOp(
input i31, i30, i29, i28, i27, i26,
output j, j2, op3, op2, op1, op0, rw, rw2, eq, eq2, regwrite, LBU
);
assign j = ~i31 & ~i30 & ~i29 & ~i28 & i27;
assign j2 = ~i26;
assign op3 = (~i31 & ~i30 & ~i29 & ~i28 & ~i27 & i26) |
(i28 & i27 & i26) | (~i31 & ~i30 & i29 & ~i28 & i27) |
(i29 & i28 & i26) | (i30 & i28 & i26) | (i31 & i28 & i26);
assign op2 = (~i27 & ~i26) | (~i31 & ~i30 & ~i29 & i28 & ~i27) |
(~i30 & i29 & ~i28 & i26) | (i30 & ~i28 & ~i27) | (i31 & ~i30 & ~i28 & i26);
assign op1 = (~i31 & ~i30 & ~i29 & ~i27 & i26) |
(~i31 & i28 & ~i26) | (i28 & i27 & ~i26) |
(~i31 & ~i30 & i29 & i27 & ~i26) |
(i29 & i28 & ~i26) | (i30 & i28 & ~i26);
assign op0 = (~i28 & ~i27) | (~i31 & ~i30 & i29 & ~i28 & ~i26) |
(i29 & ~i27 & ~i26) | (i30 & ~i27 & ~i26) | (i31 & ~i27 & ~i26) |
(i31 & ~i30 & ~i28 & i26);
assign rw = (i31 & ~i30 & ~i28 & i27 & i26) |
(i31 & ~i30 & ~i29 & i28 & ~i27 & ~i26);
assign rw2 = i29;
assign eq = (~i31 & ~i30 & ~i29 & ~i27 & i26) |
(~i31 & ~i30 & ~i29 & i28 & ~i27);
assign eq2 = ~i26;
assign regwrite = (~i31 & ~i30 & i29 & ~i28) |
(~i31 & ~i30 & i29 & ~i27) | (i31 & ~i30 & ~i29 & ~i28 & i27 & i26) |
(i31 & ~i30 & ~i29 & i28 & ~i27 & ~i26);
assign LBU = (i31 & ~i30 & ~i29 & i28 & ~i27 & ~i26);
endmodule | module istWithOp(
input i31, i30, i29, i28, i27, i26,
output j, j2, op3, op2, op1, op0, rw, rw2, eq, eq2, regwrite, LBU
); |
assign j = ~i31 & ~i30 & ~i29 & ~i28 & i27;
assign j2 = ~i26;
assign op3 = (~i31 & ~i30 & ~i29 & ~i28 & ~i27 & i26) |
(i28 & i27 & i26) | (~i31 & ~i30 & i29 & ~i28 & i27) |
(i29 & i28 & i26) | (i30 & i28 & i26) | (i31 & i28 & i26);
assign op2 = (~i27 & ~i26) | (~i31 & ~i30 & ~i29 & i28 & ~i27) |
(~i30 & i29 & ~i28 & i26) | (i30 & ~i28 & ~i27) | (i31 & ~i30 & ~i28 & i26);
assign op1 = (~i31 & ~i30 & ~i29 & ~i27 & i26) |
(~i31 & i28 & ~i26) | (i28 & i27 & ~i26) |
(~i31 & ~i30 & i29 & i27 & ~i26) |
(i29 & i28 & ~i26) | (i30 & i28 & ~i26);
assign op0 = (~i28 & ~i27) | (~i31 & ~i30 & i29 & ~i28 & ~i26) |
(i29 & ~i27 & ~i26) | (i30 & ~i27 & ~i26) | (i31 & ~i27 & ~i26) |
(i31 & ~i30 & ~i28 & i26);
assign rw = (i31 & ~i30 & ~i28 & i27 & i26) |
(i31 & ~i30 & ~i29 & i28 & ~i27 & ~i26);
assign rw2 = i29;
assign eq = (~i31 & ~i30 & ~i29 & ~i27 & i26) |
(~i31 & ~i30 & ~i29 & i28 & ~i27);
assign eq2 = ~i26;
assign regwrite = (~i31 & ~i30 & i29 & ~i28) |
(~i31 & ~i30 & i29 & ~i27) | (i31 & ~i30 & ~i29 & ~i28 & i27 & i26) |
(i31 & ~i30 & ~i29 & i28 & ~i27 & ~i26);
assign LBU = (i31 & ~i30 & ~i29 & i28 & ~i27 & ~i26);
endmodule | 3 |
138,694 | data/full_repos/permissive/85146369/verilog/src/main.v | 85,146,369 | main.v | v | 278 | 92 | [] | [] | [] | [(23, 259), (261, 278)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/85146369/verilog/src/main.v:265: Little bit endian vector: MSB < LSB of bit range: 0:31\n reg [0:31] cnt = 0;\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/85146369/verilog/src/main.v:275: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance main.d1\n cnt <= 1\'b0;\n ^~\n%Warning-LITENDIAN: data/full_repos/permissive/85146369/verilog/src/main.v:28: Little bit endian vector: MSB < LSB of bit range: 0:6\n output [0:6] led_display\n ^\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:76: Cannot find file containing module: \'register\'\n register #(10) PC(.din(PC_in), .we(~lock), .rst(rst), .clk(clock), .dout(PC_out));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85146369/verilog/src,data/full_repos/permissive/85146369/register\n data/full_repos/permissive/85146369/verilog/src,data/full_repos/permissive/85146369/register.v\n data/full_repos/permissive/85146369/verilog/src,data/full_repos/permissive/85146369/register.sv\n register\n register.v\n register.sv\n obj_dir/register\n obj_dir/register.v\n obj_dir/register.sv\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:77: Cannot find file containing module: \'rom\'\n rom rom_ist(.address(PC_out), .sel(1\'b1), .data(rom_out));\n ^~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:78: Cannot find file containing module: \'alu\'\n alu pc_c1(.x(32\'b1), .y({22\'b0, PC_out}), .op(4\'b0101), .result(pc1_result));\n ^~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:79: Cannot find file containing module: \'IFID\'\n IFID ifid(.lock(lock), .int_trigger(int_sig), .rst(jORrst), .clk(clock),\n ^~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:84: Cannot find file containing module: \'Controller\'\n Controller con(ID_ist, ID_IE, ID_EPC, \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:92: Cannot find file containing module: \'interrupt\'\n interrupt intrpt(clock, rst, INT_1, INT_2, INT_3, EX_eret, EX_mtc0, EX_int_tri, EX_CPR0,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:102: Cannot find file containing module: \'regfile\'\n regfile rgf(.read_reg1(ID_R1_sel), .read_reg2(ID_R2_sel), .write_reg(WB_RW),\n ^~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:123: Cannot find file containing module: \'redirect\'\n redirect red(ID_mtc0, EX_load, ID_OporFun, ID_shift, EX_We, MEM_We,\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:126: Cannot find file containing module: \'IDEX\'\n IDEX idex(ID_PC_out, ID_jal_address, ID_imm16_ext, ID_R1_af_red, \n ^~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:139: Cannot find file containing module: \'alu\'\n alu pc_c2(.x(EX_PC_out), .y(EX_imm16_out), .op(4\'b0101), .result(pc2_result));\n ^~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:141: Cannot find file containing module: \'alu\'\n alu main_cal(.x(EX_X), .y(EX_Y), .op(EX_aluop_out), .result(ex_redir),\n ^~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:151: Cannot find file containing module: \'EXMEM\'\n EXMEM exmem(EX_PC_out, EX_result, EX_ram_write,\n ^~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:160: Cannot find file containing module: \'ram\'\n ram main_ram(.address(MEM_result[11:2]), .Input(MEM_ram_write), .str(MEM_mem_label[0]), \n ^~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:168: Cannot find file containing module: \'MEMWB\'\n MEMWB memwb(MEM_result, ld_redir, MEM_PC,\n ^~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/85146369/verilog/src/main.v:198: Little bit endian vector: MSB < LSB of bit range: 0:6\n reg [0:6] what=0; \n ^\n%Error: Exiting due to 14 error(s), 4 warning(s)\n' | 302,678 | module | module main(
input clk, rst, asy_rst, INT_1, INT_2, INT_3, sel,
output ck_j,
output [7:0] which_led,
output [0:6] led_display
);
reg [31:0] circle;
wire lock, clock, jump, jORrst, isnop, ck_judge, clk_slow;
wire [31:0] rom_out, pc1_result, pc2_result, ram_data, ld_redir, lbu_data;
wire [9:0] PC_in, PC_out, PC_jump;
wire [7:0] lbu_data8;
dclk d1(clk, clk_slow);
wire [1:0] ID_b_ins_label, ID_memlabel, ID_j_label, ID_int_num;
wire [3:0] ID_aluop;
wire ID_OporFun, ID_We, ID_syscall, ID_shift, ID_shift_op_jud,
ID_lbu, ID_bgez, ID_jd1, ID_int_sig, ID_mfc0, ID_mtc0, ID_CPR0, ID_eret;
wire [4:0] ID_R1_sel, ID_R2_sel, ID_RW;
wire [31:0] ID_PC_out, ID_instr_index, ID_imm16_ext, ID_shamt_ext, ID_ist,
ID_R1_af_red, ID_R2_af_red, ID_jal_address, ID_CPR0_value,
ID_tmp1, ID_tmp2, ID_Y_op, PC_jump32, PC_jump32_pre, ID_EPC, ID_IE;
wire [4:0] WB_RW;
wire [31:0] WB_Din, WB_sel1, WB_sel2, WB_PC;
wire WB_we, WB_ld, WB_syscall, WB_jal;
wire EX_load, EX_We, EX_syscall_out, EX_lbu_out, EX_bgez_out, EX_equal,
EX_b, EX_eret, EX_mtc0, EX_int_tri, EX_CPR0, EX_mfc0;
wire [4:0] EX_RW;
wire [31:0] ex_redir, EX_jal_addr_out, EX_PC_out, EX_int_num_32,
EX_imm16_out, EX_X, EX_Y, EX_ram_write, EX_CPR0_value, EX_result;
wire [1:0] EX_b_ins_out, EX_mem_out, EX_jump_out, EX_int_num;
wire [3:0] EX_aluop_out;
wire MEM_We, MEM_syscall, MEM_jal, MEM_lbu;
wire [4:0] MEM_RW;
wire [1:0] MEM_mem_label;
wire [31:0] mem_redir, MEM_PC, MEM_result, MEM_ram_write;
wire [31:0] EPC_value, IE_value;
wire int_sig;
wire [1:0] which_int;
assign jORrst = jump|rst;
register #(10) PC(.din(PC_in), .we(~lock), .rst(rst), .clk(clock), .dout(PC_out));
rom rom_ist(.address(PC_out), .sel(1'b1), .data(rom_out));
alu pc_c1(.x(32'b1), .y({22'b0, PC_out}), .op(4'b0101), .result(pc1_result));
IFID ifid(.lock(lock), .int_trigger(int_sig), .rst(jORrst), .clk(clock),
.PC_plus(pc1_result), .instrction(rom_out), .EPC(EPC_value),
.IE(IE_value), .which_int(which_int), .PC_out(ID_PC_out),
.instrction_out(ID_ist), .EPC_out(ID_EPC), .IE_out(ID_IE),
.int_sig(ID_int_sig), .int_num_out(ID_int_num) );
Controller con(ID_ist, ID_IE, ID_EPC,
ID_instr_index, ID_imm16_ext, ID_shamt_ext, ID_CPR0_value,
ID_b_ins_label, ID_memlabel, ID_j_label,
ID_aluop,
ID_OporFun, ID_We, ID_syscall, ID_shift, ID_shift_op_jud, ID_lbu, ID_bgez,
ID_mfc0, ID_mtc0, ID_CPR0, ID_eret,
ID_R1_sel, ID_R2_sel, ID_RW);
interrupt intrpt(clock, rst, INT_1, INT_2, INT_3, EX_eret, EX_mtc0, EX_int_tri, EX_CPR0,
EX_PC_out, EX_ram_write,
EPC_value, IE_value,
int_sig,
which_int);
wire [31:0] rgf_reg1, rgf_reg2, rgf_a0, rgf_v0, rgf_s0, rgf_s1;
regfile rgf(.read_reg1(ID_R1_sel), .read_reg2(ID_R2_sel), .write_reg(WB_RW),
.write_data(WB_Din), .we(WB_we), .clk(~clock),.asy_rst(asy_rst), .reg1(rgf_reg1),
.reg2(rgf_reg2), .a0(rgf_a0), .v0(rgf_v0), .s0(rgf_s0), .s1(rgf_s1));
wire [1:0] Red_R1, Red_R2;
assign ID_R1_af_red = Red_R1[1]?(Red_R1[0]?ex_redir:mem_redir):
(Red_R1[0]?ex_redir:rgf_reg1);
assign ID_R2_af_red = Red_R2[1]?(Red_R2[0]?ex_redir:mem_redir):
(Red_R2[0]?ex_redir:rgf_reg2);
assign ID_jd1 = ID_shift & ID_shift_op_jud;
assign ID_tmp1 = ID_OporFun?ID_imm16_ext:ID_R2_af_red;
assign ID_tmp2 = ID_jd1?(ID_R2_af_red&32'h0000001f):ID_shamt_ext;
assign ID_Y_op = ID_shift?ID_tmp2:ID_tmp1;
assign ID_jal_address = ID_OporFun?ID_instr_index:ID_R1_af_red;
redirect red(ID_mtc0, EX_load, ID_OporFun, ID_shift, EX_We, MEM_We,
ID_R2_sel, ID_R1_sel, EX_RW, MEM_RW, ID_memlabel, lock, Red_R1, Red_R2);
assign isnop = lock?1'b1:1'b0;
IDEX idex(ID_PC_out, ID_jal_address, ID_imm16_ext, ID_R1_af_red,
ID_Y_op, ID_R2_af_red, ID_CPR0_value,
ID_b_ins_label, ID_memlabel, ID_j_label, ID_int_num,
ID_We, ID_syscall, ID_lbu, ID_bgez, isnop, clock, jORrst,
ID_CPR0, ID_mfc0, ID_mtc0, ID_eret, ID_int_sig,
ID_RW, ID_aluop,
EX_PC_out, EX_jal_addr_out, EX_imm16_out, EX_X, EX_Y, EX_ram_write, EX_CPR0_value,
EX_b_ins_out, EX_mem_out, EX_jump_out, EX_int_num,
EX_We, EX_syscall_out, EX_lbu_out, EX_bgez_out,
EX_CPR0, EX_mfc0, EX_mtc0, EX_eret, EX_int_tri,
EX_RW,
EX_aluop_out);
alu pc_c2(.x(EX_PC_out), .y(EX_imm16_out), .op(4'b0101), .result(pc2_result));
assign EX_load = EX_mem_out[1];
alu main_cal(.x(EX_X), .y(EX_Y), .op(EX_aluop_out), .result(ex_redir),
.equal(EX_equal));
assign EX_b = EX_b_ins_out[1]&((~EX_b_ins_out[0])^(EX_bgez_out?ex_redir[0]:EX_equal));
assign jump = EX_b|EX_jump_out[0]|EX_int_tri|EX_eret;
assign PC_jump32_pre = EX_jump_out[0]?EX_jal_addr_out:(EX_b?pc2_result:EX_PC_out);
assign EX_int_num_32 = {30'b0, EX_int_num};
assign PC_jump32 = EX_eret?EPC_value:(EX_int_tri?EX_int_num_32:PC_jump32_pre);
assign PC_jump = PC_jump32[9:0];
assign EX_result = EX_mfc0?EX_CPR0_value:ex_redir;
EXMEM exmem(EX_PC_out, EX_result, EX_ram_write,
EX_We, EX_syscall_out, EX_lbu_out, EX_jump_out[1], rst, clock,
EX_RW,
EX_mem_out,
MEM_PC, MEM_result, MEM_ram_write,
MEM_RW,
MEM_We, MEM_syscall, MEM_lbu, MEM_jal,
MEM_mem_label);
ram main_ram(.address(MEM_result[11:2]), .Input(MEM_ram_write), .str(MEM_mem_label[0]),
.sel(1'b1), .clk(clock), .ld(MEM_mem_label[1]), .clr(1'b0), .Data(ram_data));
assign ld_redir = MEM_lbu?(lbu_data):ram_data;
assign lbu_data8 = MEM_result[0]?(MEM_result[1]?ram_data[31:24]:ram_data[15:8]):
(MEM_result[1]?ram_data[23:16]:ram_data[7:0]);
assign lbu_data = {24'b0, lbu_data8};
assign mem_redir = MEM_mem_label[1]?ld_redir:MEM_result;
MEMWB memwb(MEM_result, ld_redir, MEM_PC,
MEM_mem_label[1], MEM_We, MEM_syscall, MEM_jal, clock, rst,
MEM_RW,
WB_sel1, WB_sel2, WB_PC,
WB_ld, WB_we, WB_syscall, WB_jal,
WB_RW);
assign WB_Din = WB_jal?WB_PC:(WB_ld?WB_sel2:WB_sel1);
assign PC_in = jump?PC_jump:pc1_result[9:0];
assign clock = ck_judge?clk_slow:1'b0;
assign ck_judge = ~(WB_syscall & (rgf_v0==32'ha));
parameter zero=7'b1000000,
one=7'b1111001,
two=7'b0100100,
three=7'b0110000,
four=7'b0011001,
five=7'b0010010,
six=7'b0000010,
seven=7'b1111000,
eight=7'b0000000,
nine=7'b0010000,
ten=7'b0001000,
eleven=7'b0000011,
twelve=7'b1000110,
thirteen=7'b0100001,
fourteen=7'b0000110,
fifteen=7'b0001110;
reg [7:0] which;
reg [0:6] what=0;
reg [3:0] value=0;
reg [20:0] cnt_scan=0;
always @(posedge clock) begin
if (rst) begin
circle = 0;
end
circle = circle+1;
end
always @(posedge clk)
begin
cnt_scan = cnt_scan + 1;
case(cnt_scan[18:16])
3'b000:which <= 8'b11111110;
3'b001:which <= 8'b11111101;
3'b010:which <= 8'b11111011;
3'b011:which <= 8'b11110111;
3'b100:which <= 8'b11101111;
3'b101:which <= 8'b11011111;
3'b110:which <= 8'b10111111;
3'b111:which <= 8'b01111111;
default:which <= 8'b01111111;
endcase
case(which)
8'b11111110:value<=sel?circle[3:0]:rgf_a0[3:0];
8'b11111101:value<=sel?circle[7:4]:rgf_a0[7:4];
8'b11111011:value<=sel?circle[11:8]:rgf_a0[11:8];
8'b11110111:value<=sel?circle[15:12]:rgf_a0[15:12];
8'b11101111:value<=rgf_a0[19:16];
8'b11011111:value<=rgf_a0[23:20];
8'b10111111:value<=rgf_a0[27:24];
8'b1111111:value<=rgf_a0[31:28];
endcase
case(value)
4'b0000: what <= zero;
4'b0001: what <= one;
4'b0010: what <= two;
4'b0011: what <= three;
4'b0100: what <= four;
4'b0101: what <= five;
4'b0110: what <= six;
4'b0111: what <= seven;
4'b1000: what <= eight;
4'b1001: what <= nine;
4'b1010: what <= ten;
4'b1011: what <= eleven;
4'b1100: what <= twelve;
4'b1101: what <= thirteen;
4'b1110: what <= fourteen;
4'b1111: what <= fifteen;
default: what <= zero;
endcase
end
assign which_led = which;
assign led_display = what;
assign ck_j = ck_judge;
endmodule | module main(
input clk, rst, asy_rst, INT_1, INT_2, INT_3, sel,
output ck_j,
output [7:0] which_led,
output [0:6] led_display
); |
reg [31:0] circle;
wire lock, clock, jump, jORrst, isnop, ck_judge, clk_slow;
wire [31:0] rom_out, pc1_result, pc2_result, ram_data, ld_redir, lbu_data;
wire [9:0] PC_in, PC_out, PC_jump;
wire [7:0] lbu_data8;
dclk d1(clk, clk_slow);
wire [1:0] ID_b_ins_label, ID_memlabel, ID_j_label, ID_int_num;
wire [3:0] ID_aluop;
wire ID_OporFun, ID_We, ID_syscall, ID_shift, ID_shift_op_jud,
ID_lbu, ID_bgez, ID_jd1, ID_int_sig, ID_mfc0, ID_mtc0, ID_CPR0, ID_eret;
wire [4:0] ID_R1_sel, ID_R2_sel, ID_RW;
wire [31:0] ID_PC_out, ID_instr_index, ID_imm16_ext, ID_shamt_ext, ID_ist,
ID_R1_af_red, ID_R2_af_red, ID_jal_address, ID_CPR0_value,
ID_tmp1, ID_tmp2, ID_Y_op, PC_jump32, PC_jump32_pre, ID_EPC, ID_IE;
wire [4:0] WB_RW;
wire [31:0] WB_Din, WB_sel1, WB_sel2, WB_PC;
wire WB_we, WB_ld, WB_syscall, WB_jal;
wire EX_load, EX_We, EX_syscall_out, EX_lbu_out, EX_bgez_out, EX_equal,
EX_b, EX_eret, EX_mtc0, EX_int_tri, EX_CPR0, EX_mfc0;
wire [4:0] EX_RW;
wire [31:0] ex_redir, EX_jal_addr_out, EX_PC_out, EX_int_num_32,
EX_imm16_out, EX_X, EX_Y, EX_ram_write, EX_CPR0_value, EX_result;
wire [1:0] EX_b_ins_out, EX_mem_out, EX_jump_out, EX_int_num;
wire [3:0] EX_aluop_out;
wire MEM_We, MEM_syscall, MEM_jal, MEM_lbu;
wire [4:0] MEM_RW;
wire [1:0] MEM_mem_label;
wire [31:0] mem_redir, MEM_PC, MEM_result, MEM_ram_write;
wire [31:0] EPC_value, IE_value;
wire int_sig;
wire [1:0] which_int;
assign jORrst = jump|rst;
register #(10) PC(.din(PC_in), .we(~lock), .rst(rst), .clk(clock), .dout(PC_out));
rom rom_ist(.address(PC_out), .sel(1'b1), .data(rom_out));
alu pc_c1(.x(32'b1), .y({22'b0, PC_out}), .op(4'b0101), .result(pc1_result));
IFID ifid(.lock(lock), .int_trigger(int_sig), .rst(jORrst), .clk(clock),
.PC_plus(pc1_result), .instrction(rom_out), .EPC(EPC_value),
.IE(IE_value), .which_int(which_int), .PC_out(ID_PC_out),
.instrction_out(ID_ist), .EPC_out(ID_EPC), .IE_out(ID_IE),
.int_sig(ID_int_sig), .int_num_out(ID_int_num) );
Controller con(ID_ist, ID_IE, ID_EPC,
ID_instr_index, ID_imm16_ext, ID_shamt_ext, ID_CPR0_value,
ID_b_ins_label, ID_memlabel, ID_j_label,
ID_aluop,
ID_OporFun, ID_We, ID_syscall, ID_shift, ID_shift_op_jud, ID_lbu, ID_bgez,
ID_mfc0, ID_mtc0, ID_CPR0, ID_eret,
ID_R1_sel, ID_R2_sel, ID_RW);
interrupt intrpt(clock, rst, INT_1, INT_2, INT_3, EX_eret, EX_mtc0, EX_int_tri, EX_CPR0,
EX_PC_out, EX_ram_write,
EPC_value, IE_value,
int_sig,
which_int);
wire [31:0] rgf_reg1, rgf_reg2, rgf_a0, rgf_v0, rgf_s0, rgf_s1;
regfile rgf(.read_reg1(ID_R1_sel), .read_reg2(ID_R2_sel), .write_reg(WB_RW),
.write_data(WB_Din), .we(WB_we), .clk(~clock),.asy_rst(asy_rst), .reg1(rgf_reg1),
.reg2(rgf_reg2), .a0(rgf_a0), .v0(rgf_v0), .s0(rgf_s0), .s1(rgf_s1));
wire [1:0] Red_R1, Red_R2;
assign ID_R1_af_red = Red_R1[1]?(Red_R1[0]?ex_redir:mem_redir):
(Red_R1[0]?ex_redir:rgf_reg1);
assign ID_R2_af_red = Red_R2[1]?(Red_R2[0]?ex_redir:mem_redir):
(Red_R2[0]?ex_redir:rgf_reg2);
assign ID_jd1 = ID_shift & ID_shift_op_jud;
assign ID_tmp1 = ID_OporFun?ID_imm16_ext:ID_R2_af_red;
assign ID_tmp2 = ID_jd1?(ID_R2_af_red&32'h0000001f):ID_shamt_ext;
assign ID_Y_op = ID_shift?ID_tmp2:ID_tmp1;
assign ID_jal_address = ID_OporFun?ID_instr_index:ID_R1_af_red;
redirect red(ID_mtc0, EX_load, ID_OporFun, ID_shift, EX_We, MEM_We,
ID_R2_sel, ID_R1_sel, EX_RW, MEM_RW, ID_memlabel, lock, Red_R1, Red_R2);
assign isnop = lock?1'b1:1'b0;
IDEX idex(ID_PC_out, ID_jal_address, ID_imm16_ext, ID_R1_af_red,
ID_Y_op, ID_R2_af_red, ID_CPR0_value,
ID_b_ins_label, ID_memlabel, ID_j_label, ID_int_num,
ID_We, ID_syscall, ID_lbu, ID_bgez, isnop, clock, jORrst,
ID_CPR0, ID_mfc0, ID_mtc0, ID_eret, ID_int_sig,
ID_RW, ID_aluop,
EX_PC_out, EX_jal_addr_out, EX_imm16_out, EX_X, EX_Y, EX_ram_write, EX_CPR0_value,
EX_b_ins_out, EX_mem_out, EX_jump_out, EX_int_num,
EX_We, EX_syscall_out, EX_lbu_out, EX_bgez_out,
EX_CPR0, EX_mfc0, EX_mtc0, EX_eret, EX_int_tri,
EX_RW,
EX_aluop_out);
alu pc_c2(.x(EX_PC_out), .y(EX_imm16_out), .op(4'b0101), .result(pc2_result));
assign EX_load = EX_mem_out[1];
alu main_cal(.x(EX_X), .y(EX_Y), .op(EX_aluop_out), .result(ex_redir),
.equal(EX_equal));
assign EX_b = EX_b_ins_out[1]&((~EX_b_ins_out[0])^(EX_bgez_out?ex_redir[0]:EX_equal));
assign jump = EX_b|EX_jump_out[0]|EX_int_tri|EX_eret;
assign PC_jump32_pre = EX_jump_out[0]?EX_jal_addr_out:(EX_b?pc2_result:EX_PC_out);
assign EX_int_num_32 = {30'b0, EX_int_num};
assign PC_jump32 = EX_eret?EPC_value:(EX_int_tri?EX_int_num_32:PC_jump32_pre);
assign PC_jump = PC_jump32[9:0];
assign EX_result = EX_mfc0?EX_CPR0_value:ex_redir;
EXMEM exmem(EX_PC_out, EX_result, EX_ram_write,
EX_We, EX_syscall_out, EX_lbu_out, EX_jump_out[1], rst, clock,
EX_RW,
EX_mem_out,
MEM_PC, MEM_result, MEM_ram_write,
MEM_RW,
MEM_We, MEM_syscall, MEM_lbu, MEM_jal,
MEM_mem_label);
ram main_ram(.address(MEM_result[11:2]), .Input(MEM_ram_write), .str(MEM_mem_label[0]),
.sel(1'b1), .clk(clock), .ld(MEM_mem_label[1]), .clr(1'b0), .Data(ram_data));
assign ld_redir = MEM_lbu?(lbu_data):ram_data;
assign lbu_data8 = MEM_result[0]?(MEM_result[1]?ram_data[31:24]:ram_data[15:8]):
(MEM_result[1]?ram_data[23:16]:ram_data[7:0]);
assign lbu_data = {24'b0, lbu_data8};
assign mem_redir = MEM_mem_label[1]?ld_redir:MEM_result;
MEMWB memwb(MEM_result, ld_redir, MEM_PC,
MEM_mem_label[1], MEM_We, MEM_syscall, MEM_jal, clock, rst,
MEM_RW,
WB_sel1, WB_sel2, WB_PC,
WB_ld, WB_we, WB_syscall, WB_jal,
WB_RW);
assign WB_Din = WB_jal?WB_PC:(WB_ld?WB_sel2:WB_sel1);
assign PC_in = jump?PC_jump:pc1_result[9:0];
assign clock = ck_judge?clk_slow:1'b0;
assign ck_judge = ~(WB_syscall & (rgf_v0==32'ha));
parameter zero=7'b1000000,
one=7'b1111001,
two=7'b0100100,
three=7'b0110000,
four=7'b0011001,
five=7'b0010010,
six=7'b0000010,
seven=7'b1111000,
eight=7'b0000000,
nine=7'b0010000,
ten=7'b0001000,
eleven=7'b0000011,
twelve=7'b1000110,
thirteen=7'b0100001,
fourteen=7'b0000110,
fifteen=7'b0001110;
reg [7:0] which;
reg [0:6] what=0;
reg [3:0] value=0;
reg [20:0] cnt_scan=0;
always @(posedge clock) begin
if (rst) begin
circle = 0;
end
circle = circle+1;
end
always @(posedge clk)
begin
cnt_scan = cnt_scan + 1;
case(cnt_scan[18:16])
3'b000:which <= 8'b11111110;
3'b001:which <= 8'b11111101;
3'b010:which <= 8'b11111011;
3'b011:which <= 8'b11110111;
3'b100:which <= 8'b11101111;
3'b101:which <= 8'b11011111;
3'b110:which <= 8'b10111111;
3'b111:which <= 8'b01111111;
default:which <= 8'b01111111;
endcase
case(which)
8'b11111110:value<=sel?circle[3:0]:rgf_a0[3:0];
8'b11111101:value<=sel?circle[7:4]:rgf_a0[7:4];
8'b11111011:value<=sel?circle[11:8]:rgf_a0[11:8];
8'b11110111:value<=sel?circle[15:12]:rgf_a0[15:12];
8'b11101111:value<=rgf_a0[19:16];
8'b11011111:value<=rgf_a0[23:20];
8'b10111111:value<=rgf_a0[27:24];
8'b1111111:value<=rgf_a0[31:28];
endcase
case(value)
4'b0000: what <= zero;
4'b0001: what <= one;
4'b0010: what <= two;
4'b0011: what <= three;
4'b0100: what <= four;
4'b0101: what <= five;
4'b0110: what <= six;
4'b0111: what <= seven;
4'b1000: what <= eight;
4'b1001: what <= nine;
4'b1010: what <= ten;
4'b1011: what <= eleven;
4'b1100: what <= twelve;
4'b1101: what <= thirteen;
4'b1110: what <= fourteen;
4'b1111: what <= fifteen;
default: what <= zero;
endcase
end
assign which_led = which;
assign led_display = what;
assign ck_j = ck_judge;
endmodule | 3 |
138,695 | data/full_repos/permissive/85146369/verilog/src/main.v | 85,146,369 | main.v | v | 278 | 92 | [] | [] | [] | [(23, 259), (261, 278)] | null | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/85146369/verilog/src/main.v:265: Little bit endian vector: MSB < LSB of bit range: 0:31\n reg [0:31] cnt = 0;\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/85146369/verilog/src/main.v:275: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance main.d1\n cnt <= 1\'b0;\n ^~\n%Warning-LITENDIAN: data/full_repos/permissive/85146369/verilog/src/main.v:28: Little bit endian vector: MSB < LSB of bit range: 0:6\n output [0:6] led_display\n ^\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:76: Cannot find file containing module: \'register\'\n register #(10) PC(.din(PC_in), .we(~lock), .rst(rst), .clk(clock), .dout(PC_out));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85146369/verilog/src,data/full_repos/permissive/85146369/register\n data/full_repos/permissive/85146369/verilog/src,data/full_repos/permissive/85146369/register.v\n data/full_repos/permissive/85146369/verilog/src,data/full_repos/permissive/85146369/register.sv\n register\n register.v\n register.sv\n obj_dir/register\n obj_dir/register.v\n obj_dir/register.sv\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:77: Cannot find file containing module: \'rom\'\n rom rom_ist(.address(PC_out), .sel(1\'b1), .data(rom_out));\n ^~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:78: Cannot find file containing module: \'alu\'\n alu pc_c1(.x(32\'b1), .y({22\'b0, PC_out}), .op(4\'b0101), .result(pc1_result));\n ^~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:79: Cannot find file containing module: \'IFID\'\n IFID ifid(.lock(lock), .int_trigger(int_sig), .rst(jORrst), .clk(clock),\n ^~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:84: Cannot find file containing module: \'Controller\'\n Controller con(ID_ist, ID_IE, ID_EPC, \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:92: Cannot find file containing module: \'interrupt\'\n interrupt intrpt(clock, rst, INT_1, INT_2, INT_3, EX_eret, EX_mtc0, EX_int_tri, EX_CPR0,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:102: Cannot find file containing module: \'regfile\'\n regfile rgf(.read_reg1(ID_R1_sel), .read_reg2(ID_R2_sel), .write_reg(WB_RW),\n ^~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:123: Cannot find file containing module: \'redirect\'\n redirect red(ID_mtc0, EX_load, ID_OporFun, ID_shift, EX_We, MEM_We,\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:126: Cannot find file containing module: \'IDEX\'\n IDEX idex(ID_PC_out, ID_jal_address, ID_imm16_ext, ID_R1_af_red, \n ^~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:139: Cannot find file containing module: \'alu\'\n alu pc_c2(.x(EX_PC_out), .y(EX_imm16_out), .op(4\'b0101), .result(pc2_result));\n ^~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:141: Cannot find file containing module: \'alu\'\n alu main_cal(.x(EX_X), .y(EX_Y), .op(EX_aluop_out), .result(ex_redir),\n ^~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:151: Cannot find file containing module: \'EXMEM\'\n EXMEM exmem(EX_PC_out, EX_result, EX_ram_write,\n ^~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:160: Cannot find file containing module: \'ram\'\n ram main_ram(.address(MEM_result[11:2]), .Input(MEM_ram_write), .str(MEM_mem_label[0]), \n ^~~\n%Error: data/full_repos/permissive/85146369/verilog/src/main.v:168: Cannot find file containing module: \'MEMWB\'\n MEMWB memwb(MEM_result, ld_redir, MEM_PC,\n ^~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/85146369/verilog/src/main.v:198: Little bit endian vector: MSB < LSB of bit range: 0:6\n reg [0:6] what=0; \n ^\n%Error: Exiting due to 14 error(s), 4 warning(s)\n' | 302,678 | module | module dclk(
input cp,
output cpo
);
reg [0:31] cnt = 0;
reg cpd=1;
assign cpo = cpd;
always @(posedge cp)
begin
cnt <= cnt+1'b1;
if (cnt >= 499999)
begin
cpd <= ~cpd;
cnt <= 1'b0;
end
end
endmodule | module dclk(
input cp,
output cpo
); |
reg [0:31] cnt = 0;
reg cpd=1;
assign cpo = cpd;
always @(posedge cp)
begin
cnt <= cnt+1'b1;
if (cnt >= 499999)
begin
cpd <= ~cpd;
cnt <= 1'b0;
end
end
endmodule | 3 |
138,696 | data/full_repos/permissive/85146369/verilog/src/MEMWB.v | 85,146,369 | MEMWB.v | v | 40 | 90 | [] | [] | [] | [(23, 39)] | null | null | 1: b"%Error: data/full_repos/permissive/85146369/verilog/src/MEMWB.v:31: Cannot find file containing module: 'register'\n register #(32) reg1(.din(sel1), .we(1'b1), .rst(rst), .clk(clk), .dout(sel1_out));\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85146369/verilog/src,data/full_repos/permissive/85146369/register\n data/full_repos/permissive/85146369/verilog/src,data/full_repos/permissive/85146369/register.v\n data/full_repos/permissive/85146369/verilog/src,data/full_repos/permissive/85146369/register.sv\n register\n register.v\n register.sv\n obj_dir/register\n obj_dir/register.v\n obj_dir/register.sv\n%Error: data/full_repos/permissive/85146369/verilog/src/MEMWB.v:32: Cannot find file containing module: 'register'\n register #(32) reg2(.din(sel2), .we(1'b1), .rst(rst), .clk(clk), .dout(sel2_out));\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/MEMWB.v:33: Cannot find file containing module: 'register'\n register #(1) reg3(.din(ld), .we(1'b1), .rst(rst), .clk(clk), .dout(ld_out));\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/MEMWB.v:34: Cannot find file containing module: 'register'\n register #(1) reg4(.din(we), .we(1'b1), .rst(rst), .clk(clk), .dout(we_out));\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/MEMWB.v:35: Cannot find file containing module: 'register'\n register #(1) reg5(.din(syscall), .we(1'b1), .rst(rst), .clk(clk), .dout(syscall_out));\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/MEMWB.v:36: Cannot find file containing module: 'register'\n register #(1) reg6(.din(jal), .we(1'b1), .rst(rst), .clk(clk), .dout(jal_out));\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/MEMWB.v:37: Cannot find file containing module: 'register'\n register #(5) reg7(.din(Rw), .we(1'b1), .rst(rst), .clk(clk), .dout(Rw_out));\n ^~~~~~~~\n%Error: data/full_repos/permissive/85146369/verilog/src/MEMWB.v:38: Cannot find file containing module: 'register'\n register #(32) reg8(.din(PC_jal), .we(1'b1), .rst(rst), .clk(clk), .dout(PC_jal_out));\n ^~~~~~~~\n%Error: Exiting due to 8 error(s)\n" | 302,679 | module | module MEMWB(
input [31:0] sel1, sel2, PC_jal,
input ld, we, syscall, jal, clk, rst,
input [4:0] Rw,
output [31:0] sel1_out, sel2_out, PC_jal_out,
output ld_out, we_out, syscall_out, jal_out,
output [4:0] Rw_out
);
register #(32) reg1(.din(sel1), .we(1'b1), .rst(rst), .clk(clk), .dout(sel1_out));
register #(32) reg2(.din(sel2), .we(1'b1), .rst(rst), .clk(clk), .dout(sel2_out));
register #(1) reg3(.din(ld), .we(1'b1), .rst(rst), .clk(clk), .dout(ld_out));
register #(1) reg4(.din(we), .we(1'b1), .rst(rst), .clk(clk), .dout(we_out));
register #(1) reg5(.din(syscall), .we(1'b1), .rst(rst), .clk(clk), .dout(syscall_out));
register #(1) reg6(.din(jal), .we(1'b1), .rst(rst), .clk(clk), .dout(jal_out));
register #(5) reg7(.din(Rw), .we(1'b1), .rst(rst), .clk(clk), .dout(Rw_out));
register #(32) reg8(.din(PC_jal), .we(1'b1), .rst(rst), .clk(clk), .dout(PC_jal_out));
endmodule | module MEMWB(
input [31:0] sel1, sel2, PC_jal,
input ld, we, syscall, jal, clk, rst,
input [4:0] Rw,
output [31:0] sel1_out, sel2_out, PC_jal_out,
output ld_out, we_out, syscall_out, jal_out,
output [4:0] Rw_out
); |
register #(32) reg1(.din(sel1), .we(1'b1), .rst(rst), .clk(clk), .dout(sel1_out));
register #(32) reg2(.din(sel2), .we(1'b1), .rst(rst), .clk(clk), .dout(sel2_out));
register #(1) reg3(.din(ld), .we(1'b1), .rst(rst), .clk(clk), .dout(ld_out));
register #(1) reg4(.din(we), .we(1'b1), .rst(rst), .clk(clk), .dout(we_out));
register #(1) reg5(.din(syscall), .we(1'b1), .rst(rst), .clk(clk), .dout(syscall_out));
register #(1) reg6(.din(jal), .we(1'b1), .rst(rst), .clk(clk), .dout(jal_out));
register #(5) reg7(.din(Rw), .we(1'b1), .rst(rst), .clk(clk), .dout(Rw_out));
register #(32) reg8(.din(PC_jal), .we(1'b1), .rst(rst), .clk(clk), .dout(PC_jal_out));
endmodule | 3 |
138,697 | data/full_repos/permissive/85146369/verilog/src/parser.v | 85,146,369 | parser.v | v | 44 | 83 | [] | [] | [] | [(23, 43)] | null | data/verilator_xmls/9b155e07-6c23-4ece-b330-8d31b79d2100.xml | null | 302,680 | module | module parser(
input [31:0] ins,
output [5:0] op,
output [4:0] rs,
output [4:0] rt,
output [4:0] rd,
output [4:0] shamt,
output [5:0] funct,
output [15:0] immediate16,
output [25:0] immediate26
);
assign op = ins[31:26];
assign rs = ins[25:21];
assign rt = ins[20:16];
assign rd = ins[15:11];
assign shamt = ins[10:6];
assign funct = ins[5:0];
assign immediate16 = ins[15:0];
assign immediate26 = ins[25:0];
endmodule | module parser(
input [31:0] ins,
output [5:0] op,
output [4:0] rs,
output [4:0] rt,
output [4:0] rd,
output [4:0] shamt,
output [5:0] funct,
output [15:0] immediate16,
output [25:0] immediate26
); |
assign op = ins[31:26];
assign rs = ins[25:21];
assign rt = ins[20:16];
assign rd = ins[15:11];
assign shamt = ins[10:6];
assign funct = ins[5:0];
assign immediate16 = ins[15:0];
assign immediate26 = ins[25:0];
endmodule | 3 |
138,698 | data/full_repos/permissive/85146369/verilog/src/pri_encoder.v | 85,146,369 | pri_encoder.v | v | 40 | 83 | [] | [] | [] | [(23, 40)] | null | data/verilator_xmls/e66d1227-ac1c-4e9f-b032-0a5150906a91.xml | null | 302,681 | module | module pri_encoder (
binary_out ,
encoder_in ,
enable
);
output [1:0] binary_out ;
input enable ;
input [3:0] encoder_in ;
wire [1:0] binary_out ;
assign binary_out = (!enable) ? 0 : (
(encoder_in[3]) ? 3 :
(encoder_in[2]) ? 2 :
(encoder_in[1]) ? 1 : 0);
endmodule | module pri_encoder (
binary_out ,
encoder_in ,
enable
); |
output [1:0] binary_out ;
input enable ;
input [3:0] encoder_in ;
wire [1:0] binary_out ;
assign binary_out = (!enable) ? 0 : (
(encoder_in[3]) ? 3 :
(encoder_in[2]) ? 2 :
(encoder_in[1]) ? 1 : 0);
endmodule | 3 |
138,700 | data/full_repos/permissive/85146369/verilog/src/redirect.v | 85,146,369 | redirect.v | v | 45 | 83 | [] | [] | [] | [(23, 44)] | null | data/verilator_xmls/2a4cabac-0661-44f3-b3bf-4b3f7a2504b4.xml | null | 302,683 | module | module redirect(
input ID_mtc0, EX_load, ID_OporFun, ID_shift, EX_We, MEM_We,
input [4:0] ID_R2, ID_R1, EX_RW, MEM_RW,
input [1:0] ID_mem,
output lock,
output [1:0] Red_R1, Red_R2
);
wire EX_R1_Red, EX_R2_Red, MEM_R1_Red, MEM_R2_Red;
wire tmp1, sw, tmp2;
assign EX_R1_Red = ~EX_load & (ID_R1==EX_RW) & EX_We;
assign tmp1 = ((ID_R2==EX_RW)&tmp2)|ID_mtc0;
assign tmp2 = ~(ID_shift|ID_OporFun);
assign EX_R2_Red = ~EX_load & tmp1 & EX_We;
assign lock = EX_load & ((tmp1|(ID_R1==EX_RW))&EX_We);
assign MEM_R1_Red = (MEM_RW==ID_R1)&MEM_We;
assign sw = ID_mem[0];
assign MEM_R2_Red = ((tmp2|sw)&(MEM_RW==ID_R2))&MEM_We;
assign Red_R1[0] = EX_R1_Red;
assign Red_R1[1] = MEM_R1_Red;
assign Red_R2[0] = EX_R2_Red;
assign Red_R2[1] = MEM_R2_Red;
endmodule | module redirect(
input ID_mtc0, EX_load, ID_OporFun, ID_shift, EX_We, MEM_We,
input [4:0] ID_R2, ID_R1, EX_RW, MEM_RW,
input [1:0] ID_mem,
output lock,
output [1:0] Red_R1, Red_R2
); |
wire EX_R1_Red, EX_R2_Red, MEM_R1_Red, MEM_R2_Red;
wire tmp1, sw, tmp2;
assign EX_R1_Red = ~EX_load & (ID_R1==EX_RW) & EX_We;
assign tmp1 = ((ID_R2==EX_RW)&tmp2)|ID_mtc0;
assign tmp2 = ~(ID_shift|ID_OporFun);
assign EX_R2_Red = ~EX_load & tmp1 & EX_We;
assign lock = EX_load & ((tmp1|(ID_R1==EX_RW))&EX_We);
assign MEM_R1_Red = (MEM_RW==ID_R1)&MEM_We;
assign sw = ID_mem[0];
assign MEM_R2_Red = ((tmp2|sw)&(MEM_RW==ID_R2))&MEM_We;
assign Red_R1[0] = EX_R1_Red;
assign Red_R1[1] = MEM_R1_Red;
assign Red_R2[0] = EX_R2_Red;
assign Red_R2[1] = MEM_R2_Red;
endmodule | 3 |
138,703 | data/full_repos/permissive/85146369/verilog/src/rom.v | 85,146,369 | rom.v | v | 35 | 83 | [] | [] | [] | [(23, 34)] | null | data/verilator_xmls/0a1d179a-b1e1-40ee-a384-7f90f8dc6c3b.xml | null | 302,686 | module | module rom(
input [9:0] address,
input sel,
output [31:0] data
);
reg [31:0] mem [0:1023];
assign data = sel?mem[address]:32'b0;
initial begin
$readmemh("/home/david/tmp/pipeline_int.hex",mem);
end
endmodule | module rom(
input [9:0] address,
input sel,
output [31:0] data
); |
reg [31:0] mem [0:1023];
assign data = sel?mem[address]:32'b0;
initial begin
$readmemh("/home/david/tmp/pipeline_int.hex",mem);
end
endmodule | 3 |
138,704 | data/full_repos/permissive/85174211/ALU.v | 85,174,211 | ALU.v | v | 46 | 38 | [] | [] | [] | [(2, 45)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/85174211/ALU.v:25: Signal definition not found, creating implicitly: \'zero\'\nassign zero = alu_a > 0;\n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 302,687 | module | module ALU(
input signed [31:0] alu_a,
input signed [31:0] alu_b,
input [4:0] shamt,
input [3:0] alu_op,
output reg [31:0] alu_out
);
parameter A_ADD = 4'b000;
parameter A_ADDU = 4'b001;
parameter A_SUB = 4'b010;
parameter A_SUBU = 4'b011;
parameter A_AND = 4'b100;
parameter A_OR = 4'b101;
parameter A_XOR = 4'b110;
parameter A_NOR = 4'b111;
parameter A_SLL = 4'b1000;
parameter A_SLLV = 4'b1001;
parameter A_SRL = 4'b1010;
parameter A_SRLV = 4'b1011;
initial
alu_out = 0;
assign zero = alu_a > 0;
always@(*)
case(alu_op)
A_ADD: alu_out = alu_a + alu_b;
A_ADDU: alu_out = alu_a + alu_b;
A_SUB: alu_out = alu_a - alu_b;
A_SUBU: alu_out = alu_a - alu_b;
A_AND: alu_out = alu_a & alu_b;
A_OR: alu_out = alu_a | alu_b;
A_XOR: alu_out = alu_a ^ alu_b;
A_NOR: alu_out = ~(alu_a | alu_b);
A_SLL: alu_out = alu_b << shamt;
A_SLLV: alu_out = alu_b << alu_a;
A_SRL: alu_out = alu_b >> shamt;
A_SRLV: alu_out = alu_b >> alu_a;
endcase
endmodule | module ALU(
input signed [31:0] alu_a,
input signed [31:0] alu_b,
input [4:0] shamt,
input [3:0] alu_op,
output reg [31:0] alu_out
); |
parameter A_ADD = 4'b000;
parameter A_ADDU = 4'b001;
parameter A_SUB = 4'b010;
parameter A_SUBU = 4'b011;
parameter A_AND = 4'b100;
parameter A_OR = 4'b101;
parameter A_XOR = 4'b110;
parameter A_NOR = 4'b111;
parameter A_SLL = 4'b1000;
parameter A_SLLV = 4'b1001;
parameter A_SRL = 4'b1010;
parameter A_SRLV = 4'b1011;
initial
alu_out = 0;
assign zero = alu_a > 0;
always@(*)
case(alu_op)
A_ADD: alu_out = alu_a + alu_b;
A_ADDU: alu_out = alu_a + alu_b;
A_SUB: alu_out = alu_a - alu_b;
A_SUBU: alu_out = alu_a - alu_b;
A_AND: alu_out = alu_a & alu_b;
A_OR: alu_out = alu_a | alu_b;
A_XOR: alu_out = alu_a ^ alu_b;
A_NOR: alu_out = ~(alu_a | alu_b);
A_SLL: alu_out = alu_b << shamt;
A_SLLV: alu_out = alu_b << alu_a;
A_SRL: alu_out = alu_b >> shamt;
A_SRLV: alu_out = alu_b >> alu_a;
endcase
endmodule | 0 |
138,705 | data/full_repos/permissive/85174211/BranchUnit.v | 85,174,211 | BranchUnit.v | v | 152 | 31 | [] | [] | [] | [(2, 151)] | null | data/verilator_xmls/c0be8236-9342-4d34-847c-e97f7e0287ca.xml | null | 302,688 | module | module BranchUnit(
input [5:0] Op,
input [4:0] Rt,
input [5:0] Funct,
input [31:0] l,
input [31:0] r,
output reg Jump,
output reg JumpR,
output reg Branch
);
initial
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
always@(*)
case(Op)
6'h0:
case(Funct)
6'h0:
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
6'h8:
begin
Branch = 1;
JumpR = 1;
Jump = 0;
end
default:
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
endcase
6'h1:
case(Rt)
5'h0:
if($signed(l) < 0)
begin
Branch = 1;
JumpR = 0;
Jump = 0;
end
else
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
5'h1:
if($signed(l) >= 0)
begin
Branch = 1;
JumpR = 0;
Jump = 0;
end
else
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
default:
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
endcase
6'h2:
begin
Branch = 1;
JumpR = 0;
Jump = 1;
end
6'h4:
if($signed(l) == $signed(r))
begin
Branch = 1;
JumpR = 0;
Jump = 0;
end
else
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
6'h5:
if($signed(l) != $signed(r))
begin
Branch = 1;
JumpR = 0;
Jump = 0;
end
else
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
6'h6:
if($signed(l) <= 0)
begin
Branch = 1;
JumpR = 0;
Jump = 0;
end
else
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
6'h7:
if($signed(l) > 0)
begin
Branch = 1;
JumpR = 0;
Jump = 0;
end
else
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
default:
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
endcase
endmodule | module BranchUnit(
input [5:0] Op,
input [4:0] Rt,
input [5:0] Funct,
input [31:0] l,
input [31:0] r,
output reg Jump,
output reg JumpR,
output reg Branch
); |
initial
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
always@(*)
case(Op)
6'h0:
case(Funct)
6'h0:
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
6'h8:
begin
Branch = 1;
JumpR = 1;
Jump = 0;
end
default:
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
endcase
6'h1:
case(Rt)
5'h0:
if($signed(l) < 0)
begin
Branch = 1;
JumpR = 0;
Jump = 0;
end
else
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
5'h1:
if($signed(l) >= 0)
begin
Branch = 1;
JumpR = 0;
Jump = 0;
end
else
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
default:
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
endcase
6'h2:
begin
Branch = 1;
JumpR = 0;
Jump = 1;
end
6'h4:
if($signed(l) == $signed(r))
begin
Branch = 1;
JumpR = 0;
Jump = 0;
end
else
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
6'h5:
if($signed(l) != $signed(r))
begin
Branch = 1;
JumpR = 0;
Jump = 0;
end
else
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
6'h6:
if($signed(l) <= 0)
begin
Branch = 1;
JumpR = 0;
Jump = 0;
end
else
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
6'h7:
if($signed(l) > 0)
begin
Branch = 1;
JumpR = 0;
Jump = 0;
end
else
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
default:
begin
Branch = 0;
JumpR = 0;
Jump = 0;
end
endcase
endmodule | 0 |
138,706 | data/full_repos/permissive/85174211/ControlUnit.v | 85,174,211 | ControlUnit.v | v | 224 | 40 | [] | [] | [] | [(2, 223)] | null | data/verilator_xmls/e5fb06fe-eed2-4607-a122-2398107245d9.xml | null | 302,689 | module | module ControlUnit(
input [5:0]Op,
input [5:0]Fun,
input [4:0]RtD,
output reg MemtoReg,
output reg MemWrite,
output reg Branch,
output reg ALUSrc,
output reg RegDst,
output reg RegWrite,
output reg [3:0]ALUControl,
output reg Jump,
output reg [2:0]BranchOp,
output reg JumpR,
output reg [2:0]LoadType,
output reg [1:0]SaveType,
output reg ALUASrc
);
always@(*)begin
MemtoReg=0;
MemWrite=0;
Branch=0;
ALUSrc=0;
RegDst=0;
RegWrite=0;
Jump=0;
ALUControl=0;
BranchOp=0;
JumpR=0;
LoadType=0;
SaveType=0;
ALUASrc=0;
case(Op)
6'h8:
begin
ALUSrc=1;
RegWrite=1;
ALUControl=1;
end
6'h9:
begin
ALUSrc=1;
RegWrite=1;
ALUControl=1;
end
6'hC:
begin
ALUSrc=1;
RegWrite=1;
ALUControl=3;
end
6'hD:
begin
ALUSrc=1;
RegWrite=1;
ALUControl=4;
end
6'hE:
begin
ALUSrc=1;
RegWrite=1;
ALUControl=5;
end
6'hA:
begin
ALUSrc=1;
RegWrite=1;
ALUControl=7;
end
6'hB:
begin
ALUSrc=1;
RegWrite=1;
ALUControl=0;
end
6'hF:
begin
ALUSrc=1;
RegWrite=1;
ALUControl=8;
end
6'h23:
begin
MemtoReg=1;
ALUSrc=1;
RegWrite=1;
ALUControl=1;
end
6'h20:
begin
MemtoReg=1;
ALUSrc=1;
RegWrite=1;
ALUControl=1;
LoadType=3;
end
6'h24:
begin
MemtoReg=1;
ALUSrc=1;
RegWrite=1;
ALUControl=1;
LoadType=4;
end
6'h21:
begin
MemtoReg=1;
ALUSrc=1;
RegWrite=1;
ALUControl=1;
LoadType=1;
end
6'h25:
begin
MemtoReg=1;
ALUSrc=1;
RegWrite=1;
ALUControl=1;
LoadType=2;
end
6'h2b:
begin
MemWrite=1;
ALUSrc=1;
ALUControl=1;
end
6'h29:
begin
MemWrite=1;
ALUSrc=1;
ALUControl=1;
SaveType=1;
end
6'h28:
begin
MemWrite=1;
ALUSrc=1;
ALUControl=1;
SaveType=2;
end
6'h0:
begin
RegDst=1;
RegWrite=1;
case(Fun)
6'h20: ALUControl=1;
6'h21: ALUControl=1;
6'h22: ALUControl=2;
6'h23: ALUControl=2;
6'h2A: ALUControl=7;
6'h2B: ALUControl=0;
6'h24: ALUControl=3;
6'h25: ALUControl=4;
6'h26: ALUControl=5;
6'h27: ALUControl=6;
6'h08:
begin
Jump=1;
JumpR=1;
Branch=1;
end
6'h4:ALUControl=9;
6'h7:ALUControl=10;
6'h6:ALUControl=11;
6'h0:
begin
ALUASrc=1;
ALUControl=9;
end
6'h2:
begin
ALUASrc=1;
ALUControl=11;
end
6'h3:
begin
ALUASrc=1;
ALUControl=10;
end
endcase
end
6'h4:
begin
Branch=1;
BranchOp=0;
end
6'h5:
begin
Branch=1;
BranchOp=5;
end
6'h6:
begin
Branch=1;
BranchOp=4;
end
6'h7:
begin
Branch=1;
BranchOp=1;
end
6'h1:
begin
if(RtD==0)begin
Branch=1;
BranchOp=3;
end
else if(RtD==1)begin
Branch=1;
BranchOp=2;
end
end
6'h2:
begin
Jump=1;
end
endcase
end
endmodule | module ControlUnit(
input [5:0]Op,
input [5:0]Fun,
input [4:0]RtD,
output reg MemtoReg,
output reg MemWrite,
output reg Branch,
output reg ALUSrc,
output reg RegDst,
output reg RegWrite,
output reg [3:0]ALUControl,
output reg Jump,
output reg [2:0]BranchOp,
output reg JumpR,
output reg [2:0]LoadType,
output reg [1:0]SaveType,
output reg ALUASrc
); |
always@(*)begin
MemtoReg=0;
MemWrite=0;
Branch=0;
ALUSrc=0;
RegDst=0;
RegWrite=0;
Jump=0;
ALUControl=0;
BranchOp=0;
JumpR=0;
LoadType=0;
SaveType=0;
ALUASrc=0;
case(Op)
6'h8:
begin
ALUSrc=1;
RegWrite=1;
ALUControl=1;
end
6'h9:
begin
ALUSrc=1;
RegWrite=1;
ALUControl=1;
end
6'hC:
begin
ALUSrc=1;
RegWrite=1;
ALUControl=3;
end
6'hD:
begin
ALUSrc=1;
RegWrite=1;
ALUControl=4;
end
6'hE:
begin
ALUSrc=1;
RegWrite=1;
ALUControl=5;
end
6'hA:
begin
ALUSrc=1;
RegWrite=1;
ALUControl=7;
end
6'hB:
begin
ALUSrc=1;
RegWrite=1;
ALUControl=0;
end
6'hF:
begin
ALUSrc=1;
RegWrite=1;
ALUControl=8;
end
6'h23:
begin
MemtoReg=1;
ALUSrc=1;
RegWrite=1;
ALUControl=1;
end
6'h20:
begin
MemtoReg=1;
ALUSrc=1;
RegWrite=1;
ALUControl=1;
LoadType=3;
end
6'h24:
begin
MemtoReg=1;
ALUSrc=1;
RegWrite=1;
ALUControl=1;
LoadType=4;
end
6'h21:
begin
MemtoReg=1;
ALUSrc=1;
RegWrite=1;
ALUControl=1;
LoadType=1;
end
6'h25:
begin
MemtoReg=1;
ALUSrc=1;
RegWrite=1;
ALUControl=1;
LoadType=2;
end
6'h2b:
begin
MemWrite=1;
ALUSrc=1;
ALUControl=1;
end
6'h29:
begin
MemWrite=1;
ALUSrc=1;
ALUControl=1;
SaveType=1;
end
6'h28:
begin
MemWrite=1;
ALUSrc=1;
ALUControl=1;
SaveType=2;
end
6'h0:
begin
RegDst=1;
RegWrite=1;
case(Fun)
6'h20: ALUControl=1;
6'h21: ALUControl=1;
6'h22: ALUControl=2;
6'h23: ALUControl=2;
6'h2A: ALUControl=7;
6'h2B: ALUControl=0;
6'h24: ALUControl=3;
6'h25: ALUControl=4;
6'h26: ALUControl=5;
6'h27: ALUControl=6;
6'h08:
begin
Jump=1;
JumpR=1;
Branch=1;
end
6'h4:ALUControl=9;
6'h7:ALUControl=10;
6'h6:ALUControl=11;
6'h0:
begin
ALUASrc=1;
ALUControl=9;
end
6'h2:
begin
ALUASrc=1;
ALUControl=11;
end
6'h3:
begin
ALUASrc=1;
ALUControl=10;
end
endcase
end
6'h4:
begin
Branch=1;
BranchOp=0;
end
6'h5:
begin
Branch=1;
BranchOp=5;
end
6'h6:
begin
Branch=1;
BranchOp=4;
end
6'h7:
begin
Branch=1;
BranchOp=1;
end
6'h1:
begin
if(RtD==0)begin
Branch=1;
BranchOp=3;
end
else if(RtD==1)begin
Branch=1;
BranchOp=2;
end
end
6'h2:
begin
Jump=1;
end
endcase
end
endmodule | 0 |
138,707 | data/full_repos/permissive/85174211/CPU.v | 85,174,211 | CPU.v | v | 296 | 31 | [] | [] | [] | [(2, 295)] | null | null | 1: b"%Error: data/full_repos/permissive/85174211/CPU.v:84: Cannot find file containing module: 'IF'\n IF inst_IF(\n ^~\n ... Looked in:\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/IF\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/IF.v\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/IF.sv\n IF\n IF.v\n IF.sv\n obj_dir/IF\n obj_dir/IF.v\n obj_dir/IF.sv\n%Error: data/full_repos/permissive/85174211/CPU.v:94: Cannot find file containing module: 'IF_ID'\n IF_ID inst_IF_ID\n ^~~~~\n%Error: data/full_repos/permissive/85174211/CPU.v:106: Cannot find file containing module: 'ID'\n ID inst_ID\n ^~\n%Error: data/full_repos/permissive/85174211/CPU.v:140: Cannot find file containing module: 'ID_EX'\n ID_EX inst_ID_EX\n ^~~~~\n%Error: data/full_repos/permissive/85174211/CPU.v:179: Cannot find file containing module: 'EX'\n EX inst_EX\n ^~\n%Error: data/full_repos/permissive/85174211/CPU.v:202: Cannot find file containing module: 'EX_MEM'\n EX_MEM inst_EX_MEM\n ^~~~~~\n%Error: data/full_repos/permissive/85174211/CPU.v:224: Cannot find file containing module: 'MEM'\n MEM inst_MEM\n ^~~\n%Error: data/full_repos/permissive/85174211/CPU.v:239: Cannot find file containing module: 'MEM_WB'\n MEM_WB inst_MEM_WB\n ^~~~~~\n%Error: data/full_repos/permissive/85174211/CPU.v:257: Cannot find file containing module: 'WB'\n WB inst_WB\n ^~\n%Error: data/full_repos/permissive/85174211/CPU.v:268: Cannot find file containing module: 'Hazard'\n Hazard inst_Hazard\n ^~~~~~\n%Error: Exiting due to 10 error(s)\n" | 302,690 | module | module CPU(
input clk,
input rst_n,
input [7:0]sw,
input [3:0]btn,
output [15:0]seg,
output [7:0]led
);
wire [1:0]ForwardAE;
wire [1:0]ForwardBE;
wire [3:0]ALUControlD;
wire [3:0]ALUControlE;
wire [31:0]ALUOutE;
wire [31:0]ALUOutM;
wire [31:0]ALUOutW;
wire [31:0]InstrD;
wire [31:0]InstrF;
wire [31:0]PCBranchD;
wire [31:0]PCPlus4D;
wire [31:0]PCPlus4F;
wire [31:0]RD1D;
wire [31:0]RD1E;
wire [31:0]RD2D;
wire [31:0]RD2E;
wire [31:0]ReadDataM;
wire [31:0]ReadDataW;
wire [31:0]ResultW;
wire [31:0]SignImmD;
wire [31:0]SignImmE;
wire [31:0]WriteDataE;
wire [31:0]WriteDataM;
wire [4:0]RdD;
wire [4:0]RdE;
wire [4:0]RsD;
wire [4:0]RsE;
wire [4:0]RtD;
wire [4:0]RtE;
wire [4:0]WriteRegE;
wire [4:0]WriteRegM;
wire [4:0]WriteRegW;
wire ALUSrcD;
wire ALUSrcE;
wire BranchD;
wire ForwardAD;
wire ForwardBD;
wire JumpD;
wire MemtoRegD;
wire MemtoRegE;
wire MemtoRegM;
wire MemtoRegW;
wire MemWriteD;
wire MemWriteE;
wire MemWriteM;
wire PCSrcD;
wire RegDstD;
wire RegDstE;
wire RegWriteD;
wire RegWriteE;
wire RegWriteM;
wire RegWriteW;
wire StallD;
wire StallF;
wire [2:0]LoadTypeD;
wire [1:0]SaveTypeD;
wire [2:0]LoadTypeE;
wire [1:0]SaveTypeE;
wire [2:0]LoadTypeM;
wire [1:0]SaveTypeM;
wire [2:0]LoadTypeW;
wire ALUASrcD;
wire ALUASrcE;
wire [4:0]shamtD;
wire [4:0]shamtE;
IF inst_IF(
.clk (clk),
.rst_n (rst_n),
.PCSrcD (PCSrcD),
.PCBranchD (PCBranchD),
.StallF (StallF),
.InstrF (InstrF),
.PCPlus4F (PCPlus4F)
);
IF_ID inst_IF_ID
(
.clk (clk),
.rst_n (rst_n),
.en (~StallD),
.clr (PCSrcD),
.InstrF (InstrF),
.InstrD (InstrD),
.PCPlus4F (PCPlus4F),
.PCPlus4D (PCPlus4D)
);
ID inst_ID
(
.clk (clk),
.rst_n (rst_n),
.InstrD (InstrD),
.PCPlus4D (PCPlus4D),
.RegWriteW (RegWriteW),
.ResultW (ResultW),
.WriteRegW (WriteRegW),
.ALUOutM (ALUOutM),
.ForwardAD (ForwardAD),
.ForwardBD (ForwardBD),
.PCBranchD (PCBranchD),
.PCSrcD (PCSrcD),
.MemtoRegD (MemtoRegD),
.MemWriteD (MemWriteD),
.BranchD (BranchD),
.ALUSrcD (ALUSrcD),
.RegDstD (RegDstD),
.RegWriteD (RegWriteD),
.ALUControlD (ALUControlD),
.JumpD (JumpD),
.RD1D (RD1D),
.RD2D (RD2D),
.RsD (RsD),
.RtD (RtD),
.RdD (RdD),
.SignImmD (SignImmD),
.LoadTypeD (LoadTypeD),
.SaveTypeD (SaveTypeD),
.ALUASrcD (ALUASrcD),
.shamtD (shamtD)
);
ID_EX inst_ID_EX
(
.clk (clk),
.rst_n (rst_n),
.clr (FlushE),
.RegWriteD (RegWriteD),
.RegWriteE (RegWriteE),
.MemtoRegD (MemtoRegD),
.MemtoRegE (MemtoRegE),
.MemWriteD (MemWriteD),
.MemWriteE (MemWriteE),
.ALUControlD (ALUControlD),
.ALUControlE (ALUControlE),
.ALUSrcD (ALUSrcD),
.ALUSrcE (ALUSrcE),
.RegDstD (RegDstD),
.RegDstE (RegDstE),
.RD1D (RD1D),
.RD1E (RD1E),
.RD2D (RD2D),
.RD2E (RD2E),
.RsD (RsD),
.RsE (RsE),
.RtD (RtD),
.RtE (RtE),
.RdD (RdD),
.RdE (RdE),
.SignImmD (SignImmD),
.SignImmE (SignImmE),
.LoadTypeD (LoadTypeD),
.LoadTypeE (LoadTypeE),
.SaveTypeD (SaveTypeD),
.SaveTypeE (SaveTypeE),
.ALUASrcD (ALUASrcD),
.ALUASrcE (ALUASrcE),
.shamtD (shamtD),
.shamtE (shamtE)
);
EX inst_EX
(
.clk (clk),
.rst_n (rst_n),
.ALUControlE (ALUControlE),
.ALUSrcE (ALUSrcE),
.RegDstE (RegDstE),
.RD1E (RD1E),
.RD2E (RD2E),
.RtE (RtE),
.RdE (RdE),
.SignImmE (SignImmE),
.ALUASrcE (ALUASrcE),
.shamtE (shamtE),
.ALUOutM (ALUOutM),
.ResultW (ResultW),
.ForwardAE (ForwardAE),
.ForwardBE (ForwardBE),
.ALUOutE (ALUOutE),
.WriteDataE (WriteDataE),
.WriteRegE (WriteRegE)
);
EX_MEM inst_EX_MEM
(
.clk (clk),
.rst_n (rst_n),
.RegWriteE (RegWriteE),
.RegWriteM (RegWriteM),
.MemtoRegE (MemtoRegE),
.MemtoRegM (MemtoRegM),
.MemWriteE (MemWriteE),
.MemWriteM (MemWriteM),
.ALUOutE (ALUOutE),
.ALUOutM (ALUOutM),
.WriteDataE (WriteDataE),
.WriteDataM (WriteDataM),
.WriteRegE (WriteRegE),
.WriteRegM (WriteRegM),
.LoadTypeE (LoadTypeE),
.LoadTypeM (LoadTypeM),
.SaveTypeE (SaveTypeE),
.SaveTypeM (SaveTypeM)
);
MEM inst_MEM
(
.clk (clk),
.rst_n (rst_n),
.MemWriteM (MemWriteM),
.ALUOutM (ALUOutM),
.WriteDataM (WriteDataM),
.SaveTypeM (SaveTypeM),
.ReadDataM (ReadDataM),
.sw (sw),
.btn (btn),
.seg (seg),
.led (led)
);
MEM_WB inst_MEM_WB
(
.clk (clk),
.rst_n (rst_n),
.RegWriteM (RegWriteM),
.RegWriteW (RegWriteW),
.MemtoRegM (MemtoRegM),
.MemtoRegW (MemtoRegW),
.ReadDataM (ReadDataM),
.ReadDataW (ReadDataW),
.ALUOutM (ALUOutM),
.ALUOutW (ALUOutW),
.WriteRegM (WriteRegM),
.WriteRegW (WriteRegW),
.LoadTypeM (LoadTypeM),
.LoadTypeW (LoadTypeW)
);
WB inst_WB
(
.clk (clk),
.rst_n (rst_n),
.MemtoRegW (MemtoRegW),
.ReadDataW (ReadDataW),
.ALUOutW (ALUOutW),
.LoadTypeW (LoadTypeW),
.ResultW (ResultW)
);
Hazard inst_Hazard
(
.BranchD (BranchD),
.RsD (RsD),
.RtD (RtD),
.RsE (RsE),
.RtE (RtE),
.WriteRegE (WriteRegE),
.MemtoRegE (MemtoRegE),
.RegWriteE (RegWriteE),
.WriteRegM (WriteRegM),
.MemtoRegM (MemtoRegM),
.RegWriteM (RegWriteM),
.WriteRegW (WriteRegW),
.MemtoRegW (MemtoRegW),
.RegWriteW (RegWriteW),
.RegDstD (RegDstD),
.RegWriteD (RegWriteD),
.StallF (StallF),
.StallD (StallD),
.ForwardAD (ForwardAD),
.ForwardBD (ForwardBD),
.FlushE (FlushE),
.ForwardAE (ForwardAE),
.ForwardBE (ForwardBE)
);
endmodule | module CPU(
input clk,
input rst_n,
input [7:0]sw,
input [3:0]btn,
output [15:0]seg,
output [7:0]led
); |
wire [1:0]ForwardAE;
wire [1:0]ForwardBE;
wire [3:0]ALUControlD;
wire [3:0]ALUControlE;
wire [31:0]ALUOutE;
wire [31:0]ALUOutM;
wire [31:0]ALUOutW;
wire [31:0]InstrD;
wire [31:0]InstrF;
wire [31:0]PCBranchD;
wire [31:0]PCPlus4D;
wire [31:0]PCPlus4F;
wire [31:0]RD1D;
wire [31:0]RD1E;
wire [31:0]RD2D;
wire [31:0]RD2E;
wire [31:0]ReadDataM;
wire [31:0]ReadDataW;
wire [31:0]ResultW;
wire [31:0]SignImmD;
wire [31:0]SignImmE;
wire [31:0]WriteDataE;
wire [31:0]WriteDataM;
wire [4:0]RdD;
wire [4:0]RdE;
wire [4:0]RsD;
wire [4:0]RsE;
wire [4:0]RtD;
wire [4:0]RtE;
wire [4:0]WriteRegE;
wire [4:0]WriteRegM;
wire [4:0]WriteRegW;
wire ALUSrcD;
wire ALUSrcE;
wire BranchD;
wire ForwardAD;
wire ForwardBD;
wire JumpD;
wire MemtoRegD;
wire MemtoRegE;
wire MemtoRegM;
wire MemtoRegW;
wire MemWriteD;
wire MemWriteE;
wire MemWriteM;
wire PCSrcD;
wire RegDstD;
wire RegDstE;
wire RegWriteD;
wire RegWriteE;
wire RegWriteM;
wire RegWriteW;
wire StallD;
wire StallF;
wire [2:0]LoadTypeD;
wire [1:0]SaveTypeD;
wire [2:0]LoadTypeE;
wire [1:0]SaveTypeE;
wire [2:0]LoadTypeM;
wire [1:0]SaveTypeM;
wire [2:0]LoadTypeW;
wire ALUASrcD;
wire ALUASrcE;
wire [4:0]shamtD;
wire [4:0]shamtE;
IF inst_IF(
.clk (clk),
.rst_n (rst_n),
.PCSrcD (PCSrcD),
.PCBranchD (PCBranchD),
.StallF (StallF),
.InstrF (InstrF),
.PCPlus4F (PCPlus4F)
);
IF_ID inst_IF_ID
(
.clk (clk),
.rst_n (rst_n),
.en (~StallD),
.clr (PCSrcD),
.InstrF (InstrF),
.InstrD (InstrD),
.PCPlus4F (PCPlus4F),
.PCPlus4D (PCPlus4D)
);
ID inst_ID
(
.clk (clk),
.rst_n (rst_n),
.InstrD (InstrD),
.PCPlus4D (PCPlus4D),
.RegWriteW (RegWriteW),
.ResultW (ResultW),
.WriteRegW (WriteRegW),
.ALUOutM (ALUOutM),
.ForwardAD (ForwardAD),
.ForwardBD (ForwardBD),
.PCBranchD (PCBranchD),
.PCSrcD (PCSrcD),
.MemtoRegD (MemtoRegD),
.MemWriteD (MemWriteD),
.BranchD (BranchD),
.ALUSrcD (ALUSrcD),
.RegDstD (RegDstD),
.RegWriteD (RegWriteD),
.ALUControlD (ALUControlD),
.JumpD (JumpD),
.RD1D (RD1D),
.RD2D (RD2D),
.RsD (RsD),
.RtD (RtD),
.RdD (RdD),
.SignImmD (SignImmD),
.LoadTypeD (LoadTypeD),
.SaveTypeD (SaveTypeD),
.ALUASrcD (ALUASrcD),
.shamtD (shamtD)
);
ID_EX inst_ID_EX
(
.clk (clk),
.rst_n (rst_n),
.clr (FlushE),
.RegWriteD (RegWriteD),
.RegWriteE (RegWriteE),
.MemtoRegD (MemtoRegD),
.MemtoRegE (MemtoRegE),
.MemWriteD (MemWriteD),
.MemWriteE (MemWriteE),
.ALUControlD (ALUControlD),
.ALUControlE (ALUControlE),
.ALUSrcD (ALUSrcD),
.ALUSrcE (ALUSrcE),
.RegDstD (RegDstD),
.RegDstE (RegDstE),
.RD1D (RD1D),
.RD1E (RD1E),
.RD2D (RD2D),
.RD2E (RD2E),
.RsD (RsD),
.RsE (RsE),
.RtD (RtD),
.RtE (RtE),
.RdD (RdD),
.RdE (RdE),
.SignImmD (SignImmD),
.SignImmE (SignImmE),
.LoadTypeD (LoadTypeD),
.LoadTypeE (LoadTypeE),
.SaveTypeD (SaveTypeD),
.SaveTypeE (SaveTypeE),
.ALUASrcD (ALUASrcD),
.ALUASrcE (ALUASrcE),
.shamtD (shamtD),
.shamtE (shamtE)
);
EX inst_EX
(
.clk (clk),
.rst_n (rst_n),
.ALUControlE (ALUControlE),
.ALUSrcE (ALUSrcE),
.RegDstE (RegDstE),
.RD1E (RD1E),
.RD2E (RD2E),
.RtE (RtE),
.RdE (RdE),
.SignImmE (SignImmE),
.ALUASrcE (ALUASrcE),
.shamtE (shamtE),
.ALUOutM (ALUOutM),
.ResultW (ResultW),
.ForwardAE (ForwardAE),
.ForwardBE (ForwardBE),
.ALUOutE (ALUOutE),
.WriteDataE (WriteDataE),
.WriteRegE (WriteRegE)
);
EX_MEM inst_EX_MEM
(
.clk (clk),
.rst_n (rst_n),
.RegWriteE (RegWriteE),
.RegWriteM (RegWriteM),
.MemtoRegE (MemtoRegE),
.MemtoRegM (MemtoRegM),
.MemWriteE (MemWriteE),
.MemWriteM (MemWriteM),
.ALUOutE (ALUOutE),
.ALUOutM (ALUOutM),
.WriteDataE (WriteDataE),
.WriteDataM (WriteDataM),
.WriteRegE (WriteRegE),
.WriteRegM (WriteRegM),
.LoadTypeE (LoadTypeE),
.LoadTypeM (LoadTypeM),
.SaveTypeE (SaveTypeE),
.SaveTypeM (SaveTypeM)
);
MEM inst_MEM
(
.clk (clk),
.rst_n (rst_n),
.MemWriteM (MemWriteM),
.ALUOutM (ALUOutM),
.WriteDataM (WriteDataM),
.SaveTypeM (SaveTypeM),
.ReadDataM (ReadDataM),
.sw (sw),
.btn (btn),
.seg (seg),
.led (led)
);
MEM_WB inst_MEM_WB
(
.clk (clk),
.rst_n (rst_n),
.RegWriteM (RegWriteM),
.RegWriteW (RegWriteW),
.MemtoRegM (MemtoRegM),
.MemtoRegW (MemtoRegW),
.ReadDataM (ReadDataM),
.ReadDataW (ReadDataW),
.ALUOutM (ALUOutM),
.ALUOutW (ALUOutW),
.WriteRegM (WriteRegM),
.WriteRegW (WriteRegW),
.LoadTypeM (LoadTypeM),
.LoadTypeW (LoadTypeW)
);
WB inst_WB
(
.clk (clk),
.rst_n (rst_n),
.MemtoRegW (MemtoRegW),
.ReadDataW (ReadDataW),
.ALUOutW (ALUOutW),
.LoadTypeW (LoadTypeW),
.ResultW (ResultW)
);
Hazard inst_Hazard
(
.BranchD (BranchD),
.RsD (RsD),
.RtD (RtD),
.RsE (RsE),
.RtE (RtE),
.WriteRegE (WriteRegE),
.MemtoRegE (MemtoRegE),
.RegWriteE (RegWriteE),
.WriteRegM (WriteRegM),
.MemtoRegM (MemtoRegM),
.RegWriteM (RegWriteM),
.WriteRegW (WriteRegW),
.MemtoRegW (MemtoRegW),
.RegWriteW (RegWriteW),
.RegDstD (RegDstD),
.RegWriteD (RegWriteD),
.StallF (StallF),
.StallD (StallD),
.ForwardAD (ForwardAD),
.ForwardBD (ForwardBD),
.FlushE (FlushE),
.ForwardAE (ForwardAE),
.ForwardBE (ForwardBE)
);
endmodule | 0 |
138,708 | data/full_repos/permissive/85174211/EX.v | 85,174,211 | EX.v | v | 41 | 81 | [] | [] | [] | [(2, 40)] | null | null | 1: b'%Error: data/full_repos/permissive/85174211/EX.v:32: Cannot find file containing module: \'ALU\'\n ALU alu(SrcAE,SrcBE,ALUControlE,ALUOutE);\n ^~~\n ... Looked in:\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/ALU\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/ALU.v\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/ALU.sv\n ALU\n ALU.v\n ALU.sv\n obj_dir/ALU\n obj_dir/ALU.v\n obj_dir/ALU.sv\n%Warning-WIDTH: data/full_repos/permissive/85174211/EX.v:38: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'shamtE\' generates 5 bits.\n : ... In instance EX\n assign SrcAE=ALUASrcE?shamtE:SrcAE_;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 302,691 | module | module EX(
input clk,
input rst_n,
input [3:0]ALUControlE,
input ALUSrcE,
input RegDstE,
input [31:0]RD1E,
input [31:0]RD2E,
input [4:0]RtE,
input [4:0]RdE,
input [31:0]SignImmE,
input ALUASrcE,
input [4:0]shamtE,
input [31:0]ALUOutM,
input [31:0]ResultW,
input [1:0]ForwardAE,
input [1:0]ForwardBE,
output [31:0]ALUOutE,
output [31:0]WriteDataE,
output [4:0]WriteRegE
);
wire [31:0]SrcAE;
wire [31:0]SrcAE_;
wire [31:0]SrcBE;
ALU alu(SrcAE,SrcBE,ALUControlE,ALUOutE);
assign SrcAE_ = (ForwardAE == 0) ? RD1E : ((ForwardAE==1) ? ResultW : ALUOutM);
assign WriteDataE = ForwardBE == 0 ? RD2E : ForwardBE == 1 ? ResultW : ALUOutM;
assign SrcBE = ALUSrcE ? SignImmE : WriteDataE;
assign WriteRegE = RegDstE ? RdE : RtE;
assign SrcAE=ALUASrcE?shamtE:SrcAE_;
endmodule | module EX(
input clk,
input rst_n,
input [3:0]ALUControlE,
input ALUSrcE,
input RegDstE,
input [31:0]RD1E,
input [31:0]RD2E,
input [4:0]RtE,
input [4:0]RdE,
input [31:0]SignImmE,
input ALUASrcE,
input [4:0]shamtE,
input [31:0]ALUOutM,
input [31:0]ResultW,
input [1:0]ForwardAE,
input [1:0]ForwardBE,
output [31:0]ALUOutE,
output [31:0]WriteDataE,
output [4:0]WriteRegE
); |
wire [31:0]SrcAE;
wire [31:0]SrcAE_;
wire [31:0]SrcBE;
ALU alu(SrcAE,SrcBE,ALUControlE,ALUOutE);
assign SrcAE_ = (ForwardAE == 0) ? RD1E : ((ForwardAE==1) ? ResultW : ALUOutM);
assign WriteDataE = ForwardBE == 0 ? RD2E : ForwardBE == 1 ? ResultW : ALUOutM;
assign SrcBE = ALUSrcE ? SignImmE : WriteDataE;
assign WriteRegE = RegDstE ? RdE : RtE;
assign SrcAE=ALUASrcE?shamtE:SrcAE_;
endmodule | 0 |
138,709 | data/full_repos/permissive/85174211/EX_MEM.v | 85,174,211 | EX_MEM.v | v | 68 | 83 | [] | [] | [] | [(21, 67)] | null | data/verilator_xmls/f78ebbbc-aed6-4929-8e71-360bacbf997a.xml | null | 302,692 | module | module EX_MEM(
input clk,
input rst_n,
input RegWriteE,
output reg RegWriteM,
input MemtoRegE,
output reg MemtoRegM,
input MemWriteE,
output reg MemWriteM,
input [31:0]ALUOutE,
output reg [31:0]ALUOutM,
input [31:0]WriteDataE,
output reg [31:0]WriteDataM,
input [4:0]WriteRegE,
output reg [4:0]WriteRegM,
input [2:0]LoadTypeE,
output reg [2:0]LoadTypeM,
input [1:0]SaveTypeE,
output reg [1:0]SaveTypeM
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
RegWriteM<=0;
MemtoRegM<=0;
MemWriteM<=0;
ALUOutM<=0;
WriteDataM<=0;
WriteRegM<=0;
LoadTypeM<=0;
SaveTypeM<=0;
end
else begin
RegWriteM<=RegWriteE;
MemtoRegM<=MemtoRegE;
MemWriteM<=MemWriteE;
ALUOutM<=ALUOutE;
WriteDataM<=WriteDataE;
WriteRegM<=WriteRegE;
LoadTypeM<=LoadTypeE;
SaveTypeM<=SaveTypeE;
end
end
endmodule | module EX_MEM(
input clk,
input rst_n,
input RegWriteE,
output reg RegWriteM,
input MemtoRegE,
output reg MemtoRegM,
input MemWriteE,
output reg MemWriteM,
input [31:0]ALUOutE,
output reg [31:0]ALUOutM,
input [31:0]WriteDataE,
output reg [31:0]WriteDataM,
input [4:0]WriteRegE,
output reg [4:0]WriteRegM,
input [2:0]LoadTypeE,
output reg [2:0]LoadTypeM,
input [1:0]SaveTypeE,
output reg [1:0]SaveTypeM
); |
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
RegWriteM<=0;
MemtoRegM<=0;
MemWriteM<=0;
ALUOutM<=0;
WriteDataM<=0;
WriteRegM<=0;
LoadTypeM<=0;
SaveTypeM<=0;
end
else begin
RegWriteM<=RegWriteE;
MemtoRegM<=MemtoRegE;
MemWriteM<=MemWriteE;
ALUOutM<=ALUOutE;
WriteDataM<=WriteDataE;
WriteRegM<=WriteRegE;
LoadTypeM<=LoadTypeE;
SaveTypeM<=SaveTypeE;
end
end
endmodule | 0 |
138,710 | data/full_repos/permissive/85174211/Hazard.v | 85,174,211 | Hazard.v | v | 84 | 119 | [] | [] | [] | [(2, 83)] | null | data/verilator_xmls/5f74a384-7489-4ef4-9574-105532506af4.xml | null | 302,693 | module | module Hazard(
input [4:0] RsD,
input [4:0] RtD,
input [4:0] RsE,
input [4:0] RtE,
input [4:0] WriteRegE,
input [4:0] WriteRegM,
input [4:0] WriteRegW,
input BranchD,
input JumpR,
input MemtoRegE,
input RegWriteE,
input RegWriteM,
input RegWriteW,
output reg StallF,
output reg StallD,
output reg ForwardAD,
output reg ForwardBD,
output reg FlushE,
output reg [1:0] ForwardAE,
output reg [1:0] ForwardBE
);
initial
begin
StallF = 0;
StallD = 0;
ForwardAD = 0;
ForwardBD = 0;
FlushE = 0;
ForwardAE = 2'b0;
ForwardBE = 2'b0;
end
always@(*)
begin
if(BranchD || JumpR)
begin
FlushE = 1;
if(RegWriteM && WriteRegM == RsD)
ForwardAD = 1;
else
ForwardAD = 0;
if(RegWriteM && WriteRegM == RtD)
ForwardBD = 1;
else
ForwardBD = 0;
end
else
begin
FlushE = 0;
ForwardAD = 0;
ForwardBD = 0;
end
if(RegWriteM && WriteRegM !=0 && WriteRegM == RsE)
ForwardAE = 2'b10;
else if(RegWriteW && WriteRegW !=0 && WriteRegM != 0 && WriteRegM != RsE && (WriteRegW == RsE))
ForwardAE = 2'b01;
else
ForwardAE = 0;
if(RegWriteM && WriteRegM !=0 && WriteRegM == RtE)
ForwardBE = 2'b10;
else if(RegWriteW && WriteRegW !=0 && WriteRegM != 0 && WriteRegM != RtE && (WriteRegW == RtE))
ForwardBE = 2'b01;
else
ForwardBE = 0;
if((MemtoRegE && (RtE == RsD || RtE == RtD)) || (RegWriteE && ((WriteRegE == RsD) || (WriteRegE == RtD)) && BranchD))
begin
StallF = 1;
StallD = 1;
end
else
begin
StallF = 0;
StallD = 0;
end
end
endmodule | module Hazard(
input [4:0] RsD,
input [4:0] RtD,
input [4:0] RsE,
input [4:0] RtE,
input [4:0] WriteRegE,
input [4:0] WriteRegM,
input [4:0] WriteRegW,
input BranchD,
input JumpR,
input MemtoRegE,
input RegWriteE,
input RegWriteM,
input RegWriteW,
output reg StallF,
output reg StallD,
output reg ForwardAD,
output reg ForwardBD,
output reg FlushE,
output reg [1:0] ForwardAE,
output reg [1:0] ForwardBE
); |
initial
begin
StallF = 0;
StallD = 0;
ForwardAD = 0;
ForwardBD = 0;
FlushE = 0;
ForwardAE = 2'b0;
ForwardBE = 2'b0;
end
always@(*)
begin
if(BranchD || JumpR)
begin
FlushE = 1;
if(RegWriteM && WriteRegM == RsD)
ForwardAD = 1;
else
ForwardAD = 0;
if(RegWriteM && WriteRegM == RtD)
ForwardBD = 1;
else
ForwardBD = 0;
end
else
begin
FlushE = 0;
ForwardAD = 0;
ForwardBD = 0;
end
if(RegWriteM && WriteRegM !=0 && WriteRegM == RsE)
ForwardAE = 2'b10;
else if(RegWriteW && WriteRegW !=0 && WriteRegM != 0 && WriteRegM != RsE && (WriteRegW == RsE))
ForwardAE = 2'b01;
else
ForwardAE = 0;
if(RegWriteM && WriteRegM !=0 && WriteRegM == RtE)
ForwardBE = 2'b10;
else if(RegWriteW && WriteRegW !=0 && WriteRegM != 0 && WriteRegM != RtE && (WriteRegW == RtE))
ForwardBE = 2'b01;
else
ForwardBE = 0;
if((MemtoRegE && (RtE == RsD || RtE == RtD)) || (RegWriteE && ((WriteRegE == RsD) || (WriteRegE == RtD)) && BranchD))
begin
StallF = 1;
StallD = 1;
end
else
begin
StallF = 0;
StallD = 0;
end
end
endmodule | 0 |
138,711 | data/full_repos/permissive/85174211/ID.v | 85,174,211 | ID.v | v | 78 | 77 | [] | [] | [] | [(2, 77)] | null | null | 1: b"%Error: data/full_repos/permissive/85174211/ID.v:54: Cannot find file containing module: 'ControlUnit'\n ControlUnit CU(Op,Fun,RtD,MemtoRegD,MemWriteD,BranchD,ALUSrcD,RegDstD,\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/ControlUnit\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/ControlUnit.v\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/ControlUnit.sv\n ControlUnit\n ControlUnit.v\n ControlUnit.sv\n obj_dir/ControlUnit\n obj_dir/ControlUnit.v\n obj_dir/ControlUnit.sv\n%Error: data/full_repos/permissive/85174211/ID.v:56: Cannot find file containing module: 'REG_FILE'\n REG_FILE REG(~clk,rst_n,A1,A2,A3,WD3,WE3,RD1,RD2);\n ^~~~~~~~\n%Error: data/full_repos/permissive/85174211/ID.v:57: Cannot find file containing module: 'SignExtend'\n SignExtend IMM(InstrD[15:0],SignImmD);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/85174211/ID.v:58: Cannot find file containing module: 'BranchUnit'\n BranchUnit BR(RD1D,RD2D,BranchOp,ConditionD);\n ^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 302,694 | module | module ID(
input clk,
input rst_n,
input [31:0]InstrD,
input [31:0]PCPlus4D,
input RegWriteW,
input [31:0]ResultW,
input [4:0]WriteRegW,
input [31:0]ALUOutM,
input ForwardAD,
input ForwardBD,
output [31:0]PCBranchD,
output PCSrcD,
output MemtoRegD,
output MemWriteD,
output BranchD,
output ALUSrcD,
output RegDstD,
output RegWriteD,
output [3:0]ALUControlD,
output JumpD,
output [31:0]RD1D,
output [31:0]RD2D,
output [4:0]RsD,
output [4:0]RtD,
output [4:0]RdD,
output [31:0]SignImmD,
output [2:0]LoadTypeD,
output [1:0]SaveTypeD,
output ALUASrcD,
output [4:0]shamtD
);
wire [5:0]Op;
wire [5:0]Fun;
wire [4:0]A1;
wire [4:0]A2;
wire [4:0]A3;
wire [31:0]WD3;
wire WE3;
wire [31:0]RD1;
wire [31:0]RD2;
wire [31:0]PCJumpD;
wire [2:0]BranchOp;
wire ConditionD;
wire JumpRD;
ControlUnit CU(Op,Fun,RtD,MemtoRegD,MemWriteD,BranchD,ALUSrcD,RegDstD,
RegWriteD,ALUControlD,JumpD,BranchOp,JumpRD,LoadTypeD,SaveTypeD,ALUASrcD);
REG_FILE REG(~clk,rst_n,A1,A2,A3,WD3,WE3,RD1,RD2);
SignExtend IMM(InstrD[15:0],SignImmD);
BranchUnit BR(RD1D,RD2D,BranchOp,ConditionD);
assign Op=InstrD[31:26];
assign Fun=InstrD[5:0];
assign A1=InstrD[25:21];
assign A2=InstrD[20:16];
assign A3=WriteRegW;
assign WD3=ResultW;
assign WE3=RegWriteW;
assign RsD=InstrD[25:21];
assign RtD=InstrD[20:16];
assign RdD=InstrD[15:11];
assign shamtD=InstrD[10:6];
assign PCJumpD=JumpRD?RD1D:{PCPlus4D[31:28],InstrD[25:0],2'b0};
assign PCBranchD=JumpD?PCJumpD:PCPlus4D+(SignImmD<<2);
assign PCSrcD=BranchD&ConditionD|JumpD;
assign RD1D=ForwardAD?ALUOutM:RD1;
assign RD2D=ForwardBD?ALUOutM:RD2;
endmodule | module ID(
input clk,
input rst_n,
input [31:0]InstrD,
input [31:0]PCPlus4D,
input RegWriteW,
input [31:0]ResultW,
input [4:0]WriteRegW,
input [31:0]ALUOutM,
input ForwardAD,
input ForwardBD,
output [31:0]PCBranchD,
output PCSrcD,
output MemtoRegD,
output MemWriteD,
output BranchD,
output ALUSrcD,
output RegDstD,
output RegWriteD,
output [3:0]ALUControlD,
output JumpD,
output [31:0]RD1D,
output [31:0]RD2D,
output [4:0]RsD,
output [4:0]RtD,
output [4:0]RdD,
output [31:0]SignImmD,
output [2:0]LoadTypeD,
output [1:0]SaveTypeD,
output ALUASrcD,
output [4:0]shamtD
); |
wire [5:0]Op;
wire [5:0]Fun;
wire [4:0]A1;
wire [4:0]A2;
wire [4:0]A3;
wire [31:0]WD3;
wire WE3;
wire [31:0]RD1;
wire [31:0]RD2;
wire [31:0]PCJumpD;
wire [2:0]BranchOp;
wire ConditionD;
wire JumpRD;
ControlUnit CU(Op,Fun,RtD,MemtoRegD,MemWriteD,BranchD,ALUSrcD,RegDstD,
RegWriteD,ALUControlD,JumpD,BranchOp,JumpRD,LoadTypeD,SaveTypeD,ALUASrcD);
REG_FILE REG(~clk,rst_n,A1,A2,A3,WD3,WE3,RD1,RD2);
SignExtend IMM(InstrD[15:0],SignImmD);
BranchUnit BR(RD1D,RD2D,BranchOp,ConditionD);
assign Op=InstrD[31:26];
assign Fun=InstrD[5:0];
assign A1=InstrD[25:21];
assign A2=InstrD[20:16];
assign A3=WriteRegW;
assign WD3=ResultW;
assign WE3=RegWriteW;
assign RsD=InstrD[25:21];
assign RtD=InstrD[20:16];
assign RdD=InstrD[15:11];
assign shamtD=InstrD[10:6];
assign PCJumpD=JumpRD?RD1D:{PCPlus4D[31:28],InstrD[25:0],2'b0};
assign PCBranchD=JumpD?PCJumpD:PCPlus4D+(SignImmD<<2);
assign PCSrcD=BranchD&ConditionD|JumpD;
assign RD1D=ForwardAD?ALUOutM:RD1;
assign RD2D=ForwardBD?ALUOutM:RD2;
endmodule | 0 |
138,712 | data/full_repos/permissive/85174211/ID_EX.v | 85,174,211 | ID_EX.v | v | 103 | 41 | [] | [] | [] | [(2, 102)] | null | data/verilator_xmls/82268506-8d7b-4a0d-a81b-204a78588d03.xml | null | 302,695 | module | module ID_EX(
input clk,
input rst_n,
input clr,
input RegWriteD,
output reg RegWriteE,
input MemtoRegD,
output reg MemtoRegE,
input MemWriteD,
output reg MemWriteE,
input [3:0]ALUControlD,
output reg [3:0]ALUControlE,
input ALUSrcD,
output reg ALUSrcE,
input RegDstD,
output reg RegDstE,
input [31:0]RD1D,
output reg [31:0]RD1E,
input [31:0]RD2D,
output reg [31:0]RD2E,
input [4:0]RsD,
output reg [4:0]RsE,
input [4:0]RtD,
output reg [4:0]RtE,
input [4:0]RdD,
output reg [4:0]RdE,
input [31:0]SignImmD,
output reg [31:0]SignImmE,
input [2:0]LoadTypeD,
output reg [2:0]LoadTypeE,
input [1:0]SaveTypeD,
output reg [1:0]SaveTypeE,
input ALUASrcD,
output reg ALUASrcE,
input [4:0]shamtD,
output reg [4:0]shamtE
);
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
RegWriteE<=0;
MemtoRegE<=0;
MemWriteE<=0;
ALUControlE<=0;
ALUSrcE<=0;
RegDstE<=0;
RD1E<=0;
RD2E<=0;
RsE<=0;
RtE<=0;
RdE<=0;
SignImmE<=0;
LoadTypeE<=0;
SaveTypeE<=0;
ALUASrcE<=0;
shamtE<=0;
end
else if(clr)
begin
RegWriteE<=0;
MemtoRegE<=0;
MemWriteE<=0;
ALUControlE<=0;
ALUSrcE<=0;
RegDstE<=0;
RD1E<=0;
RD2E<=0;
RsE<=0;
RtE<=0;
RdE<=0;
SignImmE<=0;
LoadTypeE<=0;
SaveTypeE<=0;
ALUASrcE<=0;
shamtE<=0;
end
else
begin
RegWriteE<=RegWriteD;
MemtoRegE<=MemtoRegD;
MemWriteE<=MemWriteD;
ALUControlE<=ALUControlD;
ALUSrcE<=ALUSrcD;
RegDstE<=RegDstD;
RD1E<=RD1D;
RD2E<=RD2D;
RsE<=RsD;
RtE<=RtD;
RdE<=RdD;
SignImmE<=SignImmD;
LoadTypeE<=LoadTypeD;
SaveTypeE<=SaveTypeD;
ALUASrcE<=ALUASrcD;
shamtE<=shamtD;
end
end
endmodule | module ID_EX(
input clk,
input rst_n,
input clr,
input RegWriteD,
output reg RegWriteE,
input MemtoRegD,
output reg MemtoRegE,
input MemWriteD,
output reg MemWriteE,
input [3:0]ALUControlD,
output reg [3:0]ALUControlE,
input ALUSrcD,
output reg ALUSrcE,
input RegDstD,
output reg RegDstE,
input [31:0]RD1D,
output reg [31:0]RD1E,
input [31:0]RD2D,
output reg [31:0]RD2E,
input [4:0]RsD,
output reg [4:0]RsE,
input [4:0]RtD,
output reg [4:0]RtE,
input [4:0]RdD,
output reg [4:0]RdE,
input [31:0]SignImmD,
output reg [31:0]SignImmE,
input [2:0]LoadTypeD,
output reg [2:0]LoadTypeE,
input [1:0]SaveTypeD,
output reg [1:0]SaveTypeE,
input ALUASrcD,
output reg ALUASrcE,
input [4:0]shamtD,
output reg [4:0]shamtE
); |
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
RegWriteE<=0;
MemtoRegE<=0;
MemWriteE<=0;
ALUControlE<=0;
ALUSrcE<=0;
RegDstE<=0;
RD1E<=0;
RD2E<=0;
RsE<=0;
RtE<=0;
RdE<=0;
SignImmE<=0;
LoadTypeE<=0;
SaveTypeE<=0;
ALUASrcE<=0;
shamtE<=0;
end
else if(clr)
begin
RegWriteE<=0;
MemtoRegE<=0;
MemWriteE<=0;
ALUControlE<=0;
ALUSrcE<=0;
RegDstE<=0;
RD1E<=0;
RD2E<=0;
RsE<=0;
RtE<=0;
RdE<=0;
SignImmE<=0;
LoadTypeE<=0;
SaveTypeE<=0;
ALUASrcE<=0;
shamtE<=0;
end
else
begin
RegWriteE<=RegWriteD;
MemtoRegE<=MemtoRegD;
MemWriteE<=MemWriteD;
ALUControlE<=ALUControlD;
ALUSrcE<=ALUSrcD;
RegDstE<=RegDstD;
RD1E<=RD1D;
RD2E<=RD2D;
RsE<=RsD;
RtE<=RtD;
RdE<=RdD;
SignImmE<=SignImmD;
LoadTypeE<=LoadTypeD;
SaveTypeE<=SaveTypeD;
ALUASrcE<=ALUASrcD;
shamtE<=shamtD;
end
end
endmodule | 0 |
138,713 | data/full_repos/permissive/85174211/IF.v | 85,174,211 | IF.v | v | 33 | 46 | [] | [] | [] | [(2, 32)] | null | null | 1: b"%Error: data/full_repos/permissive/85174211/IF.v:16: Cannot find file containing module: 'IMEM'\n IMEM imem(PCF[9:2],InstrF); \n ^~~~\n ... Looked in:\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/IMEM\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/IMEM.v\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/IMEM.sv\n IMEM\n IMEM.v\n IMEM.sv\n obj_dir/IMEM\n obj_dir/IMEM.v\n obj_dir/IMEM.sv\n%Error: Exiting due to 1 error(s)\n" | 302,696 | module | module IF(
input clk,
input rst_n,
input PCSrcD,
input [31:0] PCBranchD,
input StallF,
output [31:0] InstrF,
output [31:0] PCPlus4F
);
wire [31:0] iPC;
reg [31:0] PCF;
IMEM imem(PCF[9:2],InstrF);
assign iPC = PCSrcD ? PCBranchD : PCPlus4F;
assign PCPlus4F = PCF + 4;
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
begin
PCF<=0;
end
else if(~StallF)
begin
PCF<=iPC;
end
end
endmodule | module IF(
input clk,
input rst_n,
input PCSrcD,
input [31:0] PCBranchD,
input StallF,
output [31:0] InstrF,
output [31:0] PCPlus4F
); |
wire [31:0] iPC;
reg [31:0] PCF;
IMEM imem(PCF[9:2],InstrF);
assign iPC = PCSrcD ? PCBranchD : PCPlus4F;
assign PCPlus4F = PCF + 4;
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
begin
PCF<=0;
end
else if(~StallF)
begin
PCF<=iPC;
end
end
endmodule | 0 |
138,714 | data/full_repos/permissive/85174211/IF_ID.v | 85,174,211 | IF_ID.v | v | 29 | 46 | [] | [] | [] | [(2, 28)] | null | data/verilator_xmls/9dde7866-d6a3-46bc-9c52-b70804fd0609.xml | null | 302,697 | module | module IF_ID(
input clk,
input rst_n,
input en,
input clr,
input [31:0]InstrF,
output reg [31:0]InstrD,
input [31:0]PCPlus4F,
output reg [31:0]PCPlus4D
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
InstrD<=0;
PCPlus4D<=0;
end
else if (en) begin
InstrD<=InstrF;
PCPlus4D<=PCPlus4F;
if(clr) begin
InstrD<=0;
PCPlus4D<=0;
end
end
end
endmodule | module IF_ID(
input clk,
input rst_n,
input en,
input clr,
input [31:0]InstrF,
output reg [31:0]InstrD,
input [31:0]PCPlus4F,
output reg [31:0]PCPlus4D
); |
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
InstrD<=0;
PCPlus4D<=0;
end
else if (en) begin
InstrD<=InstrF;
PCPlus4D<=PCPlus4F;
if(clr) begin
InstrD<=0;
PCPlus4D<=0;
end
end
end
endmodule | 0 |
138,715 | data/full_repos/permissive/85174211/MEM.v | 85,174,211 | MEM.v | v | 93 | 65 | [] | [] | [] | [(2, 92)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/85174211/MEM.v:31: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'sw_r\' generates 8 bits.\n : ... In instance MEM\n 124:ReadDataM=sw_r;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/85174211/MEM.v:32: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'btn_r\' generates 4 bits.\n : ... In instance MEM\n 125:ReadDataM=btn_r;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85174211/MEM.v:33: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'seg\' generates 16 bits.\n : ... In instance MEM\n 126:ReadDataM=seg;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85174211/MEM.v:34: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'led\' generates 8 bits.\n : ... In instance MEM\n 127:ReadDataM=led;\n ^\n%Error: data/full_repos/permissive/85174211/MEM.v:90: Cannot find file containing module: \'DRAM\'\n DRAM dram(Addr,WriteData,clk,MemWriteM,ReadData);\n ^~~~\n ... Looked in:\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/DRAM\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/DRAM.v\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/DRAM.sv\n DRAM\n DRAM.v\n DRAM.sv\n obj_dir/DRAM\n obj_dir/DRAM.v\n obj_dir/DRAM.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n' | 302,698 | module | module MEM(
input clk,
input rst_n,
input MemWriteM,
input [31:0]ALUOutM,
input [31:0]WriteDataM,
input [1:0]SaveTypeM,
output reg [31:0]ReadDataM,
input [7:0]sw,
input [3:0]btn,
output reg [15:0]seg,
output reg [7:0]led
);
wire [7:0]Addr;
wire [1:0]TwoBit;
wire [31:0]ReadData;
reg [31:0]WriteData;
reg [7:0]sw_r;
reg [3:0]btn_r;
assign Addr=ALUOutM[9:2];
assign TwoBit=ALUOutM[1:0];
always@(*)begin
case(Addr)
124:ReadDataM=sw_r;
125:ReadDataM=btn_r;
126:ReadDataM=seg;
127:ReadDataM=led;
default:ReadDataM=ReadData;
endcase
end
always@(posedge clk or negedge rst_n)begin
if(~rst_n)begin
seg<=0;
led<=0;
end
else if(MemWriteM) begin
case(Addr)
126:seg<=WriteData[15:0];
127:led<=WriteData[7:0];
endcase
end
end
always@(posedge clk or negedge rst_n)begin
if(~rst_n)begin
sw_r<=0;
btn_r<=0;
end
else begin
sw_r<=sw;
btn_r<=btn;
end
end
always@(*)begin
case(SaveTypeM)
0:WriteData=WriteDataM;
1:
begin
if(TwoBit==0)
WriteData={ReadData[31:16],WriteDataM[15:0]};
else if(TwoBit==2)
WriteData={WriteDataM[15:0],ReadData[15:0]};
else
WriteData=0;
end
2:
begin
if(TwoBit==0)
WriteData={ReadData[31:8],WriteDataM[7:0]};
else if(TwoBit==1)
WriteData={ReadData[31:16],WriteDataM[7:0],ReadData[7:0]};
else if(TwoBit==2)
WriteData={ReadData[31:24],WriteDataM[7:0],ReadData[15:0]};
else
WriteData={WriteDataM[7:0],ReadData[23:0]};
end
default:WriteData=0;
endcase
end
DRAM dram(Addr,WriteData,clk,MemWriteM,ReadData);
endmodule | module MEM(
input clk,
input rst_n,
input MemWriteM,
input [31:0]ALUOutM,
input [31:0]WriteDataM,
input [1:0]SaveTypeM,
output reg [31:0]ReadDataM,
input [7:0]sw,
input [3:0]btn,
output reg [15:0]seg,
output reg [7:0]led
); |
wire [7:0]Addr;
wire [1:0]TwoBit;
wire [31:0]ReadData;
reg [31:0]WriteData;
reg [7:0]sw_r;
reg [3:0]btn_r;
assign Addr=ALUOutM[9:2];
assign TwoBit=ALUOutM[1:0];
always@(*)begin
case(Addr)
124:ReadDataM=sw_r;
125:ReadDataM=btn_r;
126:ReadDataM=seg;
127:ReadDataM=led;
default:ReadDataM=ReadData;
endcase
end
always@(posedge clk or negedge rst_n)begin
if(~rst_n)begin
seg<=0;
led<=0;
end
else if(MemWriteM) begin
case(Addr)
126:seg<=WriteData[15:0];
127:led<=WriteData[7:0];
endcase
end
end
always@(posedge clk or negedge rst_n)begin
if(~rst_n)begin
sw_r<=0;
btn_r<=0;
end
else begin
sw_r<=sw;
btn_r<=btn;
end
end
always@(*)begin
case(SaveTypeM)
0:WriteData=WriteDataM;
1:
begin
if(TwoBit==0)
WriteData={ReadData[31:16],WriteDataM[15:0]};
else if(TwoBit==2)
WriteData={WriteDataM[15:0],ReadData[15:0]};
else
WriteData=0;
end
2:
begin
if(TwoBit==0)
WriteData={ReadData[31:8],WriteDataM[7:0]};
else if(TwoBit==1)
WriteData={ReadData[31:16],WriteDataM[7:0],ReadData[7:0]};
else if(TwoBit==2)
WriteData={ReadData[31:24],WriteDataM[7:0],ReadData[15:0]};
else
WriteData={WriteDataM[7:0],ReadData[23:0]};
end
default:WriteData=0;
endcase
end
DRAM dram(Addr,WriteData,clk,MemWriteM,ReadData);
endmodule | 0 |
138,716 | data/full_repos/permissive/85174211/MEM_WB.v | 85,174,211 | MEM_WB.v | v | 59 | 83 | [] | [] | [] | [(21, 58)] | null | data/verilator_xmls/6a75f45f-a527-4daa-8e0c-be2d0ff45a69.xml | null | 302,699 | module | module MEM_WB(
input clk,
input rst_n,
input RegWriteM,
output reg RegWriteW,
input MemtoRegM,
output reg MemtoRegW,
input [31:0]ReadDataM,
output reg [31:0]ReadDataW,
input [31:0]ALUOutM,
output reg [31:0]ALUOutW,
input [4:0]WriteRegM,
output reg [4:0]WriteRegW,
input [2:0]LoadTypeM,
output reg [2:0]LoadTypeW
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
RegWriteW<=0;
MemtoRegW<=0;
ReadDataW<=0;
ALUOutW<=0;
WriteRegW<=0;
LoadTypeW<=0;
end
else begin
RegWriteW<=RegWriteM;
MemtoRegW<=MemtoRegM;
ReadDataW<=ReadDataM;
ALUOutW<=ALUOutM;
WriteRegW<=WriteRegM;
LoadTypeW<=LoadTypeM;
end
end
endmodule | module MEM_WB(
input clk,
input rst_n,
input RegWriteM,
output reg RegWriteW,
input MemtoRegM,
output reg MemtoRegW,
input [31:0]ReadDataM,
output reg [31:0]ReadDataW,
input [31:0]ALUOutM,
output reg [31:0]ALUOutW,
input [4:0]WriteRegM,
output reg [4:0]WriteRegW,
input [2:0]LoadTypeM,
output reg [2:0]LoadTypeW
); |
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
RegWriteW<=0;
MemtoRegW<=0;
ReadDataW<=0;
ALUOutW<=0;
WriteRegW<=0;
LoadTypeW<=0;
end
else begin
RegWriteW<=RegWriteM;
MemtoRegW<=MemtoRegM;
ReadDataW<=ReadDataM;
ALUOutW<=ALUOutM;
WriteRegW<=WriteRegM;
LoadTypeW<=LoadTypeM;
end
end
endmodule | 0 |
138,717 | data/full_repos/permissive/85174211/REG_FILE.v | 85,174,211 | REG_FILE.v | v | 28 | 37 | [] | [] | [] | [(2, 27)] | null | data/verilator_xmls/1cdfc66b-3a48-47a4-aae8-c70ddc90602f.xml | null | 302,700 | module | module REG_FILE(
input clk,
input [4:0] r1_addr,
input [4:0] r2_addr,
input [4:0] r3_addr,
input [31:0] r3_din,
input r3_wr,
output [31:0] r1_dout,
output [31:0] r2_dout
);
reg [31:0] data[0:31];
integer i;
initial
begin
for(i=0;i<32;i=i+1) data[i] = 32'h0;
end
assign r1_dout = data[r1_addr];
assign r2_dout = data[r2_addr];
always@(*)
begin
if(r3_wr)
data[r3_addr] = r3_din;
end
endmodule | module REG_FILE(
input clk,
input [4:0] r1_addr,
input [4:0] r2_addr,
input [4:0] r3_addr,
input [31:0] r3_din,
input r3_wr,
output [31:0] r1_dout,
output [31:0] r2_dout
); |
reg [31:0] data[0:31];
integer i;
initial
begin
for(i=0;i<32;i=i+1) data[i] = 32'h0;
end
assign r1_dout = data[r1_addr];
assign r2_dout = data[r2_addr];
always@(*)
begin
if(r3_wr)
data[r3_addr] = r3_din;
end
endmodule | 0 |
138,718 | data/full_repos/permissive/85174211/SignExtend.v | 85,174,211 | SignExtend.v | v | 11 | 56 | [] | [] | [] | [(2, 10)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/85174211/SignExtend.v:9: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'imm\' generates 16 bits.\n : ... In instance SignExtend\n assign signedimm = (imm[15] == 1)?(imm + N):(imm + P);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/85174211/SignExtend.v:9: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'imm\' generates 16 bits.\n : ... In instance SignExtend\n assign signedimm = (imm[15] == 1)?(imm + N):(imm + P);\n ^\n%Error: Exiting due to 2 warning(s)\n' | 302,701 | module | module SignExtend(
input signed [15:0]imm,
output [31:0]signedimm
);
parameter [31:0] N = 32'hffffffff;
parameter [31:0] P = 32'h0;
assign signedimm = (imm[15] == 1)?(imm + N):(imm + P);
endmodule | module SignExtend(
input signed [15:0]imm,
output [31:0]signedimm
); |
parameter [31:0] N = 32'hffffffff;
parameter [31:0] P = 32'h0;
assign signedimm = (imm[15] == 1)?(imm + N):(imm + P);
endmodule | 0 |
138,719 | data/full_repos/permissive/85174211/SplitWord.v | 85,174,211 | SplitWord.v | v | 53 | 43 | [] | [] | [] | [(2, 52)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/85174211/SplitWord.v:16: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 16 bits.\n : ... In instance SplitWord\n SplitDataW=$signed(ReadDataW[15:0]);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/85174211/SplitWord.v:18: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 16 bits.\n : ... In instance SplitWord\n SplitDataW=$signed(ReadDataW[31:16]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/85174211/SplitWord.v:23: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n : ... In instance SplitWord\n SplitDataW=ReadDataW[15:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/85174211/SplitWord.v:25: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n : ... In instance SplitWord\n SplitDataW=ReadDataW[31:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/85174211/SplitWord.v:30: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 8 bits.\n : ... In instance SplitWord\n SplitDataW=$signed(ReadDataW[7:0]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/85174211/SplitWord.v:32: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 8 bits.\n : ... In instance SplitWord\n SplitDataW=$signed(ReadDataW[15:8]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/85174211/SplitWord.v:34: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 8 bits.\n : ... In instance SplitWord\n SplitDataW=$signed(ReadDataW[23:16]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/85174211/SplitWord.v:36: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 8 bits.\n : ... In instance SplitWord\n SplitDataW=$signed(ReadDataW[31:24]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/85174211/SplitWord.v:41: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n : ... In instance SplitWord\n SplitDataW=ReadDataW[7:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/85174211/SplitWord.v:43: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n : ... In instance SplitWord\n SplitDataW=ReadDataW[15:8];\n ^\n%Warning-WIDTH: data/full_repos/permissive/85174211/SplitWord.v:45: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n : ... In instance SplitWord\n SplitDataW=ReadDataW[23:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/85174211/SplitWord.v:47: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n : ... In instance SplitWord\n SplitDataW=ReadDataW[31:24];\n ^\n%Error: Exiting due to 12 warning(s)\n' | 302,702 | module | module SplitWord(
input [31:0]ReadDataW,
input [2:0]LoadTypeW,
input [1:0]TwoBit,
output reg [31:0]SplitDataW
);
always@(*)begin
SplitDataW=0;
case(LoadTypeW)
0:SplitDataW=ReadDataW;
1:
begin
if(TwoBit==0)
SplitDataW=$signed(ReadDataW[15:0]);
else if(TwoBit==2)
SplitDataW=$signed(ReadDataW[31:16]);
end
2:
begin
if(TwoBit==0)
SplitDataW=ReadDataW[15:0];
else if(TwoBit==2)
SplitDataW=ReadDataW[31:16];
end
3:
begin
if(TwoBit==0)
SplitDataW=$signed(ReadDataW[7:0]);
else if(TwoBit==1)
SplitDataW=$signed(ReadDataW[15:8]);
else if(TwoBit==2)
SplitDataW=$signed(ReadDataW[23:16]);
else
SplitDataW=$signed(ReadDataW[31:24]);
end
4:
begin
if(TwoBit==0)
SplitDataW=ReadDataW[7:0];
else if(TwoBit==1)
SplitDataW=ReadDataW[15:8];
else if(TwoBit==2)
SplitDataW=ReadDataW[23:16];
else
SplitDataW=ReadDataW[31:24];
end
endcase
end
endmodule | module SplitWord(
input [31:0]ReadDataW,
input [2:0]LoadTypeW,
input [1:0]TwoBit,
output reg [31:0]SplitDataW
); |
always@(*)begin
SplitDataW=0;
case(LoadTypeW)
0:SplitDataW=ReadDataW;
1:
begin
if(TwoBit==0)
SplitDataW=$signed(ReadDataW[15:0]);
else if(TwoBit==2)
SplitDataW=$signed(ReadDataW[31:16]);
end
2:
begin
if(TwoBit==0)
SplitDataW=ReadDataW[15:0];
else if(TwoBit==2)
SplitDataW=ReadDataW[31:16];
end
3:
begin
if(TwoBit==0)
SplitDataW=$signed(ReadDataW[7:0]);
else if(TwoBit==1)
SplitDataW=$signed(ReadDataW[15:8]);
else if(TwoBit==2)
SplitDataW=$signed(ReadDataW[23:16]);
else
SplitDataW=$signed(ReadDataW[31:24]);
end
4:
begin
if(TwoBit==0)
SplitDataW=ReadDataW[7:0];
else if(TwoBit==1)
SplitDataW=ReadDataW[15:8];
else if(TwoBit==2)
SplitDataW=ReadDataW[23:16];
else
SplitDataW=ReadDataW[31:24];
end
endcase
end
endmodule | 0 |
138,720 | data/full_repos/permissive/85174211/test.v | 85,174,211 | test.v | v | 55 | 81 | [] | [] | [] | [(25, 53)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/85174211/test.v:46: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/85174211/test.v:50: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk=~clk;\n ^\n%Error: data/full_repos/permissive/85174211/test.v:36: Cannot find file containing module: \'CPU\'\n CPU uut (.clk(clk), .rst_n(rst_n), .sw(sw), .btn(btn), .seg(seg), .led(led));\n ^~~\n ... Looked in:\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/CPU\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/CPU.v\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/CPU.sv\n CPU\n CPU.v\n CPU.sv\n obj_dir/CPU\n obj_dir/CPU.v\n obj_dir/CPU.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,703 | module | module test;
reg clk;
reg rst_n;
reg [7:0]sw;
reg [3:0]btn;
wire [15:0]seg;
wire [7:0]led;
CPU uut (.clk(clk), .rst_n(rst_n), .sw(sw), .btn(btn), .seg(seg), .led(led));
initial begin
clk = 0;
rst_n = 0;
sw=0;
btn=0;
#100;
rst_n=1;
forever #10 clk=~clk;
end
endmodule | module test; |
reg clk;
reg rst_n;
reg [7:0]sw;
reg [3:0]btn;
wire [15:0]seg;
wire [7:0]led;
CPU uut (.clk(clk), .rst_n(rst_n), .sw(sw), .btn(btn), .seg(seg), .led(led));
initial begin
clk = 0;
rst_n = 0;
sw=0;
btn=0;
#100;
rst_n=1;
forever #10 clk=~clk;
end
endmodule | 0 |
138,721 | data/full_repos/permissive/85174211/TOP.v | 85,174,211 | TOP.v | v | 82 | 244 | [] | [] | [] | [(2, 81)] | null | null | 1: b"%Error: data/full_repos/permissive/85174211/TOP.v:35: Cannot find file containing module: 'converter'\nconverter con(c, 1, clk);\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/converter\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/converter.v\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/converter.sv\n converter\n converter.v\n converter.sv\n obj_dir/converter\n obj_dir/converter.v\n obj_dir/converter.sv\n%Error: data/full_repos/permissive/85174211/TOP.v:37: Cannot find file containing module: 'Plus'\nPlus PC_Inc(PCF, 32'h4, PCPlus4F); \n^~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:38: Cannot find file containing module: 'Update'\nUpdate PC_Update(clk, ~StallF, PCN, PCF);\n^~~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:39: Cannot find file containing module: 'SignExtend32'\nSignExtend32 extend2(InstF[15:0], SignImmD2);\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:41: Cannot find file containing module: 'BranchPredictor'\nBranchPredictor bp(PredictorStateD, Success, Wrong, InstF[31:26], PredictF, PredictedF, PredictorStateF);\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:42: Cannot find file containing module: 'Mux32'\nMux32 PC_Mux(PCSrcD & (~PredictD), PCBranchD, PCPlus4F, PC_N);\n^~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:43: Cannot find file containing module: 'Mux32'\nMux32 predict_mux(PredictedF & PredictF, SignImmD2, PC_N, PC);\n^~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:44: Cannot find file containing module: 'Mux32'\nMux32 predict_mux2(PredictedF & PredictD & (~PCSrcD), PCPlus4D, PC, PC2);\n^~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:45: Cannot find file containing module: 'Mux32'\nMux32 Jr_Mux(JumpR, RD1D, PC2, PC3);\n^~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:46: Cannot find file containing module: 'Mux32'\nMux32 J_Mux(Jump, {{4{address[25]}}, address, 2'b0} ,PC3, PCN);\n^~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:48: Cannot find file containing module: 'IROM'\nIROM Insts(PCF >> 2, InstF);\n^~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:49: Cannot find file containing module: 'IFID_R'\nIFID_R if_id(clk, (PredictedD & (PredictD ^ PCSrcD)) | (~PredictedD & PCSrcD), ~StallD, InstF, PCPlus4F, PredictF, PredictedF, PredictorStateF, InstD, PCPlus4D, PredictD, PredictedD, PredictorStateD); \n^~~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:50: Cannot find file containing module: 'REG_FILE'\nREG_FILE regfile(clk, A1, A2, WriteRegW, ResultW, RegWriteW, RD1Out, RD2Out);\n^~~~~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:52: Cannot find file containing module: 'Mux32'\nMux32 rd1mux(ForwardAD, ALUOutM, RD1Out, RD1D);\n^~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:53: Cannot find file containing module: 'Mux32'\nMux32 rd2mux(ForwardBD, ALUOutM, RD2Out, RD2D);\n^~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:54: Cannot find file containing module: 'BranchUnit'\nBranchUnit branch(opcode, RtD, funct, RD1D, RD2D, Jump, JumpR, PCSrcD);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:58: Cannot find file containing module: 'SignExtend32'\nSignExtend32 extend(immediate, SignImmD);\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:59: Cannot find file containing module: 'Plus'\nPlus pcbranchd(SignImmD << 2, PCPlus4D, PCBranchD);\n^~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:60: Cannot find file containing module: 'Control'\nControl ctrl_unit(c, opcode, shamt,funct, RegWriteD, MemtoRegD, MemWriteD, ALUControlD, ALUSrcD, RegDstD,BranchD);\n^~~~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:61: Cannot find file containing module: 'Hazard'\nHazard hzd_unit(RsD, RtD, RsE, RtE, WriteRegE, WriteRegM, WriteRegW, BranchD, JumpR, MemtoRegE, RegWriteE, RegWriteM, RegWriteW, StallF, StallD, ForwardAD, ForwardBD, FlushE, ForwardAE, ForwardBE);\n^~~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:63: Cannot find file containing module: 'IDEX_R'\nIDEX_R id_ex(clk, FlushE, RsD, RtD, RdD, SignImmD, RD1D, RD2D, shamt, RegWriteD, MemtoRegD, MemWriteD, ALUControlD, ALUSrcD, RegDstD, RsE, RtE, RdE, SignImmE, RD1E, RD2E, shamtE, RegWriteE, MemtoRegE, MemWriteE, ALUControlE, ALUSrcE, RegDstE);\n^~~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:65: Cannot find file containing module: 'Mux5'\nMux5 writerege(RegDstE, RdE, RtE, WriteRegE);\n^~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:66: Cannot find file containing module: 'Mux32_4'\nMux32_4 srcae(ForwardAE, RD1E, ResultW, ALUOutM, 0, SrcAE);\n^~~~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:67: Cannot find file containing module: 'Mux32_4'\nMux32_4 writedatae(ForwardBE, RD2E, ResultW, ALUOutM, 0, WriteDataE);\n^~~~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:68: Cannot find file containing module: 'Mux32'\nMux32 srcbe(ALUSrcE, SignImmE, WriteDataE, SrcBE);\n^~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:69: Cannot find file containing module: 'ALU'\nALU alu(SrcAE, SrcBE, shamtE, ALUControlE, ALUOutE);\n^~~\n%Error: data/full_repos/permissive/85174211/TOP.v:71: Cannot find file containing module: 'EXMEM_R'\nEXMEM_R em_mem(clk, RegWriteE, MemtoRegE, MemWriteE, ALUOutE, WriteDataE, WriteRegE, RegWriteM, MemtoRegM, MemWriteM, ALUOutM, WriteDataM, WriteRegM);\n^~~~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:73: Cannot find file containing module: 'DATARAM'\nDATARAM dataram(ALUOutM >> 2, WriteDataM, switch[6:0], clk, MemWriteM, ReadDataM, MEMREAD);\n^~~~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:74: Cannot find file containing module: 'Mux32'\nMux32 read_mux(switch[7], MEMREAD[31:16], MEMREAD[15:0], READOUT);\n^~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:75: Cannot find file containing module: 'display'\ndisplay dis(c, READOUT, sel, digits);\n^~~~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:77: Cannot find file containing module: 'MEMWB_R'\nMEMWB_R mem_wb(clk, RegWriteM, MemtoRegM, ReadDataM, ALUOutM, WriteRegM, RegWriteW, MemtoRegW, ReadDataW, ALUOutW, WriteRegW);\n^~~~~~~\n%Error: data/full_repos/permissive/85174211/TOP.v:79: Cannot find file containing module: 'Mux32'\nMux32 resultw(MemtoRegW, ReadDataW, ALUOutW, ResultW);\n^~~~~\n%Error: Exiting due to 32 error(s)\n" | 302,704 | module | module top(
input c,
input [7:0] switch,
output [6:0] digits,
output [3:0] sel
);
wire [31:0] PC3, PC2, PC, PC_N, PCN, PCF, PCPlus4F, InstF, PCPlus4D, InstD, WriteDataE, WriteDataM, ALUOutE, ALUOutM, ALUOutW, SrcAE, SrcBE, ResultW;
wire [31:0] RD1E, RD2E, RD1D, RD2D, RD1Out, RD2Out, SignImmD, SignImmE, PCBranchD, ReadDataW, ReadDataM, SignImmD2, MEMREAD;
wire [25:0] address;
wire [15:0] immediate, READOUT;
wire [5:0] opcode, funct;
wire [4:0] RsD, RtD, RdD, RsE, RtE, RdE, shamt, A1, A2, WriteRegE, WriteRegM, WriteRegW, shamtE;
wire [3:0] ALUControlD, ALUControlE;
wire [1:0] ForwardAE, ForwardBE,PredictorStateF, PredictorStateD;
wire PCSrcD, StallF, StallD, BranchD, EqualD, RegWriteD, MemtoRegD, MemWriteD, ALUSrcD, RegDstD, Wrong;
wire RegWriteE, MemtoRegE, MemWriteE, ALUSrcE, RegDstE, RegWriteM, MemtoRegM, MemWriteM, RegWriteW, MemtoRegW;
wire ForwardAD, ForwardBD, FlushE, Jump, JumpR, PredictF, PredictD, PredictedF, PredictedD, Success;
wire clk;
assign opcode = InstD[31:26];
assign RsD = InstD[25:21];
assign RtD = InstD[20:16];
assign RdD = InstD[15:11];
assign shamt = InstD[10:6];
assign funct = InstD[5:0];
assign immediate = InstD[15:0];
assign address = InstD[25:0];
assign A1 = RsD;
assign A2 = RtD;
assign Wrong = PCSrcD ^ PredictD;
assign Success = PredictedD & (~Wrong);
converter con(c, 1, clk);
Plus PC_Inc(PCF, 32'h4, PCPlus4F);
Update PC_Update(clk, ~StallF, PCN, PCF);
SignExtend32 extend2(InstF[15:0], SignImmD2);
BranchPredictor bp(PredictorStateD, Success, Wrong, InstF[31:26], PredictF, PredictedF, PredictorStateF);
Mux32 PC_Mux(PCSrcD & (~PredictD), PCBranchD, PCPlus4F, PC_N);
Mux32 predict_mux(PredictedF & PredictF, SignImmD2, PC_N, PC);
Mux32 predict_mux2(PredictedF & PredictD & (~PCSrcD), PCPlus4D, PC, PC2);
Mux32 Jr_Mux(JumpR, RD1D, PC2, PC3);
Mux32 J_Mux(Jump, {{4{address[25]}}, address, 2'b0} ,PC3, PCN);
IROM Insts(PCF >> 2, InstF);
IFID_R if_id(clk, (PredictedD & (PredictD ^ PCSrcD)) | (~PredictedD & PCSrcD), ~StallD, InstF, PCPlus4F, PredictF, PredictedF, PredictorStateF, InstD, PCPlus4D, PredictD, PredictedD, PredictorStateD);
REG_FILE regfile(clk, A1, A2, WriteRegW, ResultW, RegWriteW, RD1Out, RD2Out);
Mux32 rd1mux(ForwardAD, ALUOutM, RD1Out, RD1D);
Mux32 rd2mux(ForwardBD, ALUOutM, RD2Out, RD2D);
BranchUnit branch(opcode, RtD, funct, RD1D, RD2D, Jump, JumpR, PCSrcD);
SignExtend32 extend(immediate, SignImmD);
Plus pcbranchd(SignImmD << 2, PCPlus4D, PCBranchD);
Control ctrl_unit(c, opcode, shamt,funct, RegWriteD, MemtoRegD, MemWriteD, ALUControlD, ALUSrcD, RegDstD,BranchD);
Hazard hzd_unit(RsD, RtD, RsE, RtE, WriteRegE, WriteRegM, WriteRegW, BranchD, JumpR, MemtoRegE, RegWriteE, RegWriteM, RegWriteW, StallF, StallD, ForwardAD, ForwardBD, FlushE, ForwardAE, ForwardBE);
IDEX_R id_ex(clk, FlushE, RsD, RtD, RdD, SignImmD, RD1D, RD2D, shamt, RegWriteD, MemtoRegD, MemWriteD, ALUControlD, ALUSrcD, RegDstD, RsE, RtE, RdE, SignImmE, RD1E, RD2E, shamtE, RegWriteE, MemtoRegE, MemWriteE, ALUControlE, ALUSrcE, RegDstE);
Mux5 writerege(RegDstE, RdE, RtE, WriteRegE);
Mux32_4 srcae(ForwardAE, RD1E, ResultW, ALUOutM, 0, SrcAE);
Mux32_4 writedatae(ForwardBE, RD2E, ResultW, ALUOutM, 0, WriteDataE);
Mux32 srcbe(ALUSrcE, SignImmE, WriteDataE, SrcBE);
ALU alu(SrcAE, SrcBE, shamtE, ALUControlE, ALUOutE);
EXMEM_R em_mem(clk, RegWriteE, MemtoRegE, MemWriteE, ALUOutE, WriteDataE, WriteRegE, RegWriteM, MemtoRegM, MemWriteM, ALUOutM, WriteDataM, WriteRegM);
DATARAM dataram(ALUOutM >> 2, WriteDataM, switch[6:0], clk, MemWriteM, ReadDataM, MEMREAD);
Mux32 read_mux(switch[7], MEMREAD[31:16], MEMREAD[15:0], READOUT);
display dis(c, READOUT, sel, digits);
MEMWB_R mem_wb(clk, RegWriteM, MemtoRegM, ReadDataM, ALUOutM, WriteRegM, RegWriteW, MemtoRegW, ReadDataW, ALUOutW, WriteRegW);
Mux32 resultw(MemtoRegW, ReadDataW, ALUOutW, ResultW);
endmodule | module top(
input c,
input [7:0] switch,
output [6:0] digits,
output [3:0] sel
); |
wire [31:0] PC3, PC2, PC, PC_N, PCN, PCF, PCPlus4F, InstF, PCPlus4D, InstD, WriteDataE, WriteDataM, ALUOutE, ALUOutM, ALUOutW, SrcAE, SrcBE, ResultW;
wire [31:0] RD1E, RD2E, RD1D, RD2D, RD1Out, RD2Out, SignImmD, SignImmE, PCBranchD, ReadDataW, ReadDataM, SignImmD2, MEMREAD;
wire [25:0] address;
wire [15:0] immediate, READOUT;
wire [5:0] opcode, funct;
wire [4:0] RsD, RtD, RdD, RsE, RtE, RdE, shamt, A1, A2, WriteRegE, WriteRegM, WriteRegW, shamtE;
wire [3:0] ALUControlD, ALUControlE;
wire [1:0] ForwardAE, ForwardBE,PredictorStateF, PredictorStateD;
wire PCSrcD, StallF, StallD, BranchD, EqualD, RegWriteD, MemtoRegD, MemWriteD, ALUSrcD, RegDstD, Wrong;
wire RegWriteE, MemtoRegE, MemWriteE, ALUSrcE, RegDstE, RegWriteM, MemtoRegM, MemWriteM, RegWriteW, MemtoRegW;
wire ForwardAD, ForwardBD, FlushE, Jump, JumpR, PredictF, PredictD, PredictedF, PredictedD, Success;
wire clk;
assign opcode = InstD[31:26];
assign RsD = InstD[25:21];
assign RtD = InstD[20:16];
assign RdD = InstD[15:11];
assign shamt = InstD[10:6];
assign funct = InstD[5:0];
assign immediate = InstD[15:0];
assign address = InstD[25:0];
assign A1 = RsD;
assign A2 = RtD;
assign Wrong = PCSrcD ^ PredictD;
assign Success = PredictedD & (~Wrong);
converter con(c, 1, clk);
Plus PC_Inc(PCF, 32'h4, PCPlus4F);
Update PC_Update(clk, ~StallF, PCN, PCF);
SignExtend32 extend2(InstF[15:0], SignImmD2);
BranchPredictor bp(PredictorStateD, Success, Wrong, InstF[31:26], PredictF, PredictedF, PredictorStateF);
Mux32 PC_Mux(PCSrcD & (~PredictD), PCBranchD, PCPlus4F, PC_N);
Mux32 predict_mux(PredictedF & PredictF, SignImmD2, PC_N, PC);
Mux32 predict_mux2(PredictedF & PredictD & (~PCSrcD), PCPlus4D, PC, PC2);
Mux32 Jr_Mux(JumpR, RD1D, PC2, PC3);
Mux32 J_Mux(Jump, {{4{address[25]}}, address, 2'b0} ,PC3, PCN);
IROM Insts(PCF >> 2, InstF);
IFID_R if_id(clk, (PredictedD & (PredictD ^ PCSrcD)) | (~PredictedD & PCSrcD), ~StallD, InstF, PCPlus4F, PredictF, PredictedF, PredictorStateF, InstD, PCPlus4D, PredictD, PredictedD, PredictorStateD);
REG_FILE regfile(clk, A1, A2, WriteRegW, ResultW, RegWriteW, RD1Out, RD2Out);
Mux32 rd1mux(ForwardAD, ALUOutM, RD1Out, RD1D);
Mux32 rd2mux(ForwardBD, ALUOutM, RD2Out, RD2D);
BranchUnit branch(opcode, RtD, funct, RD1D, RD2D, Jump, JumpR, PCSrcD);
SignExtend32 extend(immediate, SignImmD);
Plus pcbranchd(SignImmD << 2, PCPlus4D, PCBranchD);
Control ctrl_unit(c, opcode, shamt,funct, RegWriteD, MemtoRegD, MemWriteD, ALUControlD, ALUSrcD, RegDstD,BranchD);
Hazard hzd_unit(RsD, RtD, RsE, RtE, WriteRegE, WriteRegM, WriteRegW, BranchD, JumpR, MemtoRegE, RegWriteE, RegWriteM, RegWriteW, StallF, StallD, ForwardAD, ForwardBD, FlushE, ForwardAE, ForwardBE);
IDEX_R id_ex(clk, FlushE, RsD, RtD, RdD, SignImmD, RD1D, RD2D, shamt, RegWriteD, MemtoRegD, MemWriteD, ALUControlD, ALUSrcD, RegDstD, RsE, RtE, RdE, SignImmE, RD1E, RD2E, shamtE, RegWriteE, MemtoRegE, MemWriteE, ALUControlE, ALUSrcE, RegDstE);
Mux5 writerege(RegDstE, RdE, RtE, WriteRegE);
Mux32_4 srcae(ForwardAE, RD1E, ResultW, ALUOutM, 0, SrcAE);
Mux32_4 writedatae(ForwardBE, RD2E, ResultW, ALUOutM, 0, WriteDataE);
Mux32 srcbe(ALUSrcE, SignImmE, WriteDataE, SrcBE);
ALU alu(SrcAE, SrcBE, shamtE, ALUControlE, ALUOutE);
EXMEM_R em_mem(clk, RegWriteE, MemtoRegE, MemWriteE, ALUOutE, WriteDataE, WriteRegE, RegWriteM, MemtoRegM, MemWriteM, ALUOutM, WriteDataM, WriteRegM);
DATARAM dataram(ALUOutM >> 2, WriteDataM, switch[6:0], clk, MemWriteM, ReadDataM, MEMREAD);
Mux32 read_mux(switch[7], MEMREAD[31:16], MEMREAD[15:0], READOUT);
display dis(c, READOUT, sel, digits);
MEMWB_R mem_wb(clk, RegWriteM, MemtoRegM, ReadDataM, ALUOutM, WriteRegM, RegWriteW, MemtoRegW, ReadDataW, ALUOutW, WriteRegW);
Mux32 resultw(MemtoRegW, ReadDataW, ALUOutW, ResultW);
endmodule | 0 |
138,722 | data/full_repos/permissive/85174211/WB.v | 85,174,211 | WB.v | v | 40 | 83 | [] | [] | [] | [(21, 39)] | null | null | 1: b"%Error: data/full_repos/permissive/85174211/WB.v:37: Cannot find file containing module: 'SplitWord'\n SplitWord spw(ReadDataW,LoadTypeW,ALUOutW[1:0],SplitDataW);\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/SplitWord\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/SplitWord.v\n data/full_repos/permissive/85174211,data/full_repos/permissive/85174211/SplitWord.sv\n SplitWord\n SplitWord.v\n SplitWord.sv\n obj_dir/SplitWord\n obj_dir/SplitWord.v\n obj_dir/SplitWord.sv\n%Error: Exiting due to 1 error(s)\n" | 302,705 | module | module WB(
input clk,
input rst_n,
input MemtoRegW,
input [31:0]ReadDataW,
input [31:0]ALUOutW,
input [2:0]LoadTypeW,
output [31:0]ResultW
);
wire [31:0]SplitDataW;
assign ResultW=MemtoRegW?SplitDataW:ALUOutW;
SplitWord spw(ReadDataW,LoadTypeW,ALUOutW[1:0],SplitDataW);
endmodule | module WB(
input clk,
input rst_n,
input MemtoRegW,
input [31:0]ReadDataW,
input [31:0]ALUOutW,
input [2:0]LoadTypeW,
output [31:0]ResultW
); |
wire [31:0]SplitDataW;
assign ResultW=MemtoRegW?SplitDataW:ALUOutW;
SplitWord spw(ReadDataW,LoadTypeW,ALUOutW[1:0],SplitDataW);
endmodule | 0 |
138,723 | data/full_repos/permissive/8521375/Clk.v | 8,521,375 | Clk.v | v | 130 | 101 | [] | ['general public license', 'free software foundation'] | [] | null | line:39: before: "real" | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/8521375/Clk.v:83: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'ClkGen\'\nmodule ClkGen (clk_i, clk_o, clk180_o);\n ^~~~~~\n : ... Top module \'ClkToPin\'\nmodule ClkToPin (clk_i, clk180_i, clk_o);\n ^~~~~~~~\n : ... Top module \'SyncToClock\'\nmodule SyncToClock (clk_i, unsynced_i, synced_o);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/8521375/Clk.v:89: Cannot find file containing module: \'ODDR2\'\n ODDR2 \n ^~~~~\n ... Looked in:\n data/full_repos/permissive/8521375,data/full_repos/permissive/8521375/ODDR2\n data/full_repos/permissive/8521375,data/full_repos/permissive/8521375/ODDR2.v\n data/full_repos/permissive/8521375,data/full_repos/permissive/8521375/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: data/full_repos/permissive/8521375/Clk.v:48: Cannot find file containing module: \'DCM_SP\'\n DCM_SP \n ^~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 302,706 | module | module ClkGen (clk_i, clk_o, clk180_o);
parameter MUL = 25;
parameter DIV = 3;
parameter real IN_FREQ = 12.0;
input clk_i;
output clk_o;
output clk180_o;
localparam real CLK_PERIOD = 1000.0/IN_FREQ;
DCM_SP
#(
.CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(DIV),
.CLKFX_MULTIPLY(MUL),
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(CLK_PERIOD),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DLL_FREQUENCY_MODE("LOW"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE")
)
DCM_SP_inst
(
.CLKFX(clk_o),
.CLKFX180(clk180_o),
.CLKIN(clk_i),
.RST(1'b0)
);
endmodule | module ClkGen (clk_i, clk_o, clk180_o); |
parameter MUL = 25;
parameter DIV = 3;
parameter real IN_FREQ = 12.0;
input clk_i;
output clk_o;
output clk180_o;
localparam real CLK_PERIOD = 1000.0/IN_FREQ;
DCM_SP
#(
.CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(DIV),
.CLKFX_MULTIPLY(MUL),
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(CLK_PERIOD),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DLL_FREQUENCY_MODE("LOW"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE")
)
DCM_SP_inst
(
.CLKFX(clk_o),
.CLKFX180(clk180_o),
.CLKIN(clk_i),
.RST(1'b0)
);
endmodule | 9 |
138,724 | data/full_repos/permissive/8521375/Clk.v | 8,521,375 | Clk.v | v | 130 | 101 | [] | ['general public license', 'free software foundation'] | [] | null | line:39: before: "real" | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/8521375/Clk.v:83: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'ClkGen\'\nmodule ClkGen (clk_i, clk_o, clk180_o);\n ^~~~~~\n : ... Top module \'ClkToPin\'\nmodule ClkToPin (clk_i, clk180_i, clk_o);\n ^~~~~~~~\n : ... Top module \'SyncToClock\'\nmodule SyncToClock (clk_i, unsynced_i, synced_o);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/8521375/Clk.v:89: Cannot find file containing module: \'ODDR2\'\n ODDR2 \n ^~~~~\n ... Looked in:\n data/full_repos/permissive/8521375,data/full_repos/permissive/8521375/ODDR2\n data/full_repos/permissive/8521375,data/full_repos/permissive/8521375/ODDR2.v\n data/full_repos/permissive/8521375,data/full_repos/permissive/8521375/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: data/full_repos/permissive/8521375/Clk.v:48: Cannot find file containing module: \'DCM_SP\'\n DCM_SP \n ^~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 302,706 | module | module ClkToPin (clk_i, clk180_i, clk_o);
input clk_i;
input clk180_i;
output clk_o;
ODDR2
#(
.DDR_ALIGNMENT("NONE"),
.INIT(1'b0),
.SRTYPE("SYNC")
)
ODDR2_inst
(
.Q(clk_o),
.C0(clk_i),
.C1(clk180_i),
.CE(1'b1),
.D0(1'b1),
.D1(1'b0),
.R(1'b0),
.S(1'b0)
);
endmodule | module ClkToPin (clk_i, clk180_i, clk_o); |
input clk_i;
input clk180_i;
output clk_o;
ODDR2
#(
.DDR_ALIGNMENT("NONE"),
.INIT(1'b0),
.SRTYPE("SYNC")
)
ODDR2_inst
(
.Q(clk_o),
.C0(clk_i),
.C1(clk180_i),
.CE(1'b1),
.D0(1'b1),
.D1(1'b0),
.R(1'b0),
.S(1'b0)
);
endmodule | 9 |
138,725 | data/full_repos/permissive/8521375/Clk.v | 8,521,375 | Clk.v | v | 130 | 101 | [] | ['general public license', 'free software foundation'] | [] | null | line:39: before: "real" | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/8521375/Clk.v:83: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'ClkGen\'\nmodule ClkGen (clk_i, clk_o, clk180_o);\n ^~~~~~\n : ... Top module \'ClkToPin\'\nmodule ClkToPin (clk_i, clk180_i, clk_o);\n ^~~~~~~~\n : ... Top module \'SyncToClock\'\nmodule SyncToClock (clk_i, unsynced_i, synced_o);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/8521375/Clk.v:89: Cannot find file containing module: \'ODDR2\'\n ODDR2 \n ^~~~~\n ... Looked in:\n data/full_repos/permissive/8521375,data/full_repos/permissive/8521375/ODDR2\n data/full_repos/permissive/8521375,data/full_repos/permissive/8521375/ODDR2.v\n data/full_repos/permissive/8521375,data/full_repos/permissive/8521375/ODDR2.sv\n ODDR2\n ODDR2.v\n ODDR2.sv\n obj_dir/ODDR2\n obj_dir/ODDR2.v\n obj_dir/ODDR2.sv\n%Error: data/full_repos/permissive/8521375/Clk.v:48: Cannot find file containing module: \'DCM_SP\'\n DCM_SP \n ^~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 302,706 | module | module SyncToClock (clk_i, unsynced_i, synced_o);
parameter syncStages = 2;
input clk_i;
input unsynced_i;
output synced_o;
reg [syncStages:1] sync_r;
always @(posedge clk_i)
sync_r <= {sync_r[syncStages-1:1], unsynced_i};
assign synced_o = sync_r[syncStages];
endmodule | module SyncToClock (clk_i, unsynced_i, synced_o); |
parameter syncStages = 2;
input clk_i;
input unsynced_i;
output synced_o;
reg [syncStages:1] sync_r;
always @(posedge clk_i)
sync_r <= {sync_r[syncStages-1:1], unsynced_i};
assign synced_o = sync_r[syncStages];
endmodule | 9 |
138,740 | data/full_repos/permissive/85218763/AutoBusSync/sync_bus.v | 85,218,763 | sync_bus.v | v | 100 | 82 | [] | [] | [] | [(36, 99)] | null | data/verilator_xmls/441ea09e-e5f5-4e7e-bdfd-81e4db169c99.xml | null | 302,715 | module | module sync_bus # (
parameter N = 1
) (
input wire clk_src,
input wire [N-1:0] bus_src,
input wire reset,
input wire clk_dst,
output reg [N-1:0] bus_dst
);
reg [N-1:0] bus_src_hold;
reg req_src;
reg req_dst1, req_dst;
reg ack_src1, ack_src;
reg ack_dst;
always @(posedge reset or posedge clk_src) begin
if (reset == 1'b1) begin
req_src <= 1'b0;
ack_src <= 1'b0;
bus_src_hold <= 0;
end else begin
if (req_src == 1'b1) begin
if (ack_src == 1'b1) begin
req_src <= 1'b0;
end
end else begin
if (ack_src == 1'b0) begin
if (bus_src_hold != bus_src) begin
bus_src_hold <= bus_src;
req_src <= 1'b1;
end
end
end
ack_src1 <= ack_dst;
ack_src <= ack_src1;
end
end
always @(posedge clk_dst) begin
req_dst1 <= req_src;
req_dst <= req_dst1;
if (req_dst == 1'b1) begin
bus_dst <= bus_src_hold;
ack_dst <= 1'b1;
end
if (req_dst == 1'b0) begin
ack_dst <= 1'b0;
end
end
endmodule | module sync_bus # (
parameter N = 1
) (
input wire clk_src,
input wire [N-1:0] bus_src,
input wire reset,
input wire clk_dst,
output reg [N-1:0] bus_dst
); |
reg [N-1:0] bus_src_hold;
reg req_src;
reg req_dst1, req_dst;
reg ack_src1, ack_src;
reg ack_dst;
always @(posedge reset or posedge clk_src) begin
if (reset == 1'b1) begin
req_src <= 1'b0;
ack_src <= 1'b0;
bus_src_hold <= 0;
end else begin
if (req_src == 1'b1) begin
if (ack_src == 1'b1) begin
req_src <= 1'b0;
end
end else begin
if (ack_src == 1'b0) begin
if (bus_src_hold != bus_src) begin
bus_src_hold <= bus_src;
req_src <= 1'b1;
end
end
end
ack_src1 <= ack_dst;
ack_src <= ack_src1;
end
end
always @(posedge clk_dst) begin
req_dst1 <= req_src;
req_dst <= req_dst1;
if (req_dst == 1'b1) begin
bus_dst <= bus_src_hold;
ack_dst <= 1'b1;
end
if (req_dst == 1'b0) begin
ack_dst <= 1'b0;
end
end
endmodule | 0 |
138,741 | data/full_repos/permissive/85218763/AutoBusSync/test_tf.v | 85,218,763 | test_tf.v | v | 86 | 82 | [] | [] | [] | [(32, 85)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/85218763/AutoBusSync/test_tf.v:60: Unsupported: Ignoring delay on this delayed statement.\nalways #(tCLK_SRC/2.0) clk_src = ~clk_src;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/85218763/AutoBusSync/test_tf.v:61: Unsupported: Ignoring delay on this delayed statement.\nalways #(tCLK_DST/2.0) clk_dst = ~clk_dst;\n ^\n%Error: data/full_repos/permissive/85218763/AutoBusSync/test_tf.v:66: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("dump.vcd"); $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/85218763/AutoBusSync/test_tf.v:66: Unsupported or unknown PLI call: $dumpvars\n $dumpfile("dump.vcd"); $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/85218763/AutoBusSync/test_tf.v:69: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85218763/AutoBusSync/test_tf.v:71: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85218763/AutoBusSync/test_tf.v:74: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85218763/AutoBusSync/test_tf.v:76: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85218763/AutoBusSync/test_tf.v:78: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85218763/AutoBusSync/test_tf.v:80: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,716 | module | module tf;
reg clk_src;
reg clk_dst;
reg reset;
reg [7:0] bus_src;
wire [7:0] bus_dst;
sync_bus # (
.N (8)
) dut (
.clk_src (clk_src),
.clk_dst (clk_dst),
.reset (reset),
.bus_src (bus_src),
.bus_dst (bus_dst)
);
parameter tCLK_SRC = 10;
parameter tCLK_DST = 23;
initial clk_src = 0;
initial clk_dst = 0;
always #(tCLK_SRC/2.0) clk_src = ~clk_src;
always #(tCLK_DST/2.0) clk_dst = ~clk_dst;
initial begin
$dumpfile("dump.vcd"); $dumpvars;
reset = 1'b1;
bus_src = 8'h00;
#100;
reset = 1'b0;
#100;
bus_src = 8'h3A;
#100;
bus_src = 8'h57;
#100;
bus_src = 8'h95;
#100;
bus_src = 8'hb3;
#100;
$finish;
end
endmodule | module tf; |
reg clk_src;
reg clk_dst;
reg reset;
reg [7:0] bus_src;
wire [7:0] bus_dst;
sync_bus # (
.N (8)
) dut (
.clk_src (clk_src),
.clk_dst (clk_dst),
.reset (reset),
.bus_src (bus_src),
.bus_dst (bus_dst)
);
parameter tCLK_SRC = 10;
parameter tCLK_DST = 23;
initial clk_src = 0;
initial clk_dst = 0;
always #(tCLK_SRC/2.0) clk_src = ~clk_src;
always #(tCLK_DST/2.0) clk_dst = ~clk_dst;
initial begin
$dumpfile("dump.vcd"); $dumpvars;
reset = 1'b1;
bus_src = 8'h00;
#100;
reset = 1'b0;
#100;
bus_src = 8'h3A;
#100;
bus_src = 8'h57;
#100;
bus_src = 8'h95;
#100;
bus_src = 8'hb3;
#100;
$finish;
end
endmodule | 0 |
138,742 | data/full_repos/permissive/85218763/SyncReset/test_tf.v | 85,218,763 | test_tf.v | v | 73 | 82 | [] | [] | [] | [(33, 72)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/85218763/SyncReset/test_tf.v:53: Unsupported: Ignoring delay on this delayed statement.\nalways #(tCLK/2.0) clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/85218763/SyncReset/test_tf.v:58: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("dump.vcd"); $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/85218763/SyncReset/test_tf.v:58: Unsupported or unknown PLI call: $dumpvars\n $dumpfile("dump.vcd"); $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/85218763/SyncReset/test_tf.v:60: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85218763/SyncReset/test_tf.v:62: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85218763/SyncReset/test_tf.v:65: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85218763/SyncReset/test_tf.v:67: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,718 | module | module tf;
reg clk;
reg reset_async;
wire reset_sync;
sync_reset dut (
.clk (clk),
.async_reset (reset_async),
.sync_reset (reset_sync)
);
parameter tCLK = 15;
initial clk = 0;
always #(tCLK/2.0) clk = ~clk;
initial begin
$dumpfile("dump.vcd"); $dumpvars;
reset_async = 1'b1;
#100;
reset_async = 1'b0;
#100;
reset_async = 1'b1;
#100;
reset_async = 1'b0;
#100;
$finish;
end
endmodule | module tf; |
reg clk;
reg reset_async;
wire reset_sync;
sync_reset dut (
.clk (clk),
.async_reset (reset_async),
.sync_reset (reset_sync)
);
parameter tCLK = 15;
initial clk = 0;
always #(tCLK/2.0) clk = ~clk;
initial begin
$dumpfile("dump.vcd"); $dumpvars;
reset_async = 1'b1;
#100;
reset_async = 1'b0;
#100;
reset_async = 1'b1;
#100;
reset_async = 1'b0;
#100;
$finish;
end
endmodule | 0 |
138,743 | data/full_repos/permissive/85218763/SyncTrig/sync_trig.v | 85,218,763 | sync_trig.v | v | 79 | 82 | [] | [] | [] | [(36, 78)] | null | data/verilator_xmls/f40ea812-187c-4769-9fc2-c1f05f093a8b.xml | null | 302,719 | module | module sync_trig(
input wire clk_i,
input wire clk_o,
input wire rst_i,
input wire rst_o,
input wire trig_i,
output reg trig_o
);
reg cross_reg_i;
reg [1:0] cross_reg_o;
reg [6:0] state;
localparam state_a = 0,
state_b = 1,
state_c = 2;
always @(posedge clk_o) begin
if(rst_o == 1'b1) begin
cross_reg_o <= 2'b00;
end else begin
cross_reg_o[0] <= cross_reg_i;
cross_reg_o[1] <= cross_reg_o[0];
trig_o <= 1'b0;
if(^cross_reg_o) begin
trig_o <= 1'b1;
end
end
end
always @(posedge clk_i) begin
if(rst_i == 1'b1) begin
cross_reg_i <= 1'b0;
end else begin
if(trig_i == 1'b1) begin
cross_reg_i <= ~cross_reg_i;
end
end
end
endmodule | module sync_trig(
input wire clk_i,
input wire clk_o,
input wire rst_i,
input wire rst_o,
input wire trig_i,
output reg trig_o
); |
reg cross_reg_i;
reg [1:0] cross_reg_o;
reg [6:0] state;
localparam state_a = 0,
state_b = 1,
state_c = 2;
always @(posedge clk_o) begin
if(rst_o == 1'b1) begin
cross_reg_o <= 2'b00;
end else begin
cross_reg_o[0] <= cross_reg_i;
cross_reg_o[1] <= cross_reg_o[0];
trig_o <= 1'b0;
if(^cross_reg_o) begin
trig_o <= 1'b1;
end
end
end
always @(posedge clk_i) begin
if(rst_i == 1'b1) begin
cross_reg_i <= 1'b0;
end else begin
if(trig_i == 1'b1) begin
cross_reg_i <= ~cross_reg_i;
end
end
end
endmodule | 0 |
138,744 | data/full_repos/permissive/85218763/SyncTrig/test_tf.v | 85,218,763 | test_tf.v | v | 84 | 82 | [] | [] | [] | null | line:79: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/85218763/SyncTrig/test_tf.v:60: Unsupported: Ignoring delay on this delayed statement.\nalways #(tCLK_src/2.0) clk_src = ~clk_src;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/85218763/SyncTrig/test_tf.v:61: Unsupported: Ignoring delay on this delayed statement.\nalways #(tCLK_dst/2.0) clk_dst = ~clk_dst;\n ^\n%Error: data/full_repos/permissive/85218763/SyncTrig/test_tf.v:66: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("dump.vcd"); $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/85218763/SyncTrig/test_tf.v:66: Unsupported or unknown PLI call: $dumpvars\n $dumpfile("dump.vcd"); $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/85218763/SyncTrig/test_tf.v:70: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85218763/SyncTrig/test_tf.v:72: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/85218763/SyncTrig/test_tf.v:74: syntax error, unexpected \'@\'\n @(posedge clk_src);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85218763/SyncTrig/test_tf.v:76: Unsupported: Ignoring delay on this delayed statement.\n #tCLK_src;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85218763/SyncTrig/test_tf.v:78: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,720 | module | module tf;
reg clk_src;
reg clk_dst;
reg reset_src;
reg reset_dst;
reg trig_src;
wire trig_dst;
sync_trig dut (
.clk_i (clk_src),
.clk_o (clk_dst),
.rst_i (reset_src),
.rst_o (reset_dst),
.trig_i (trig_src),
.trig_o (trig_dst)
);
parameter tCLK_src = 10;
parameter tCLK_dst = 7;
initial clk_src = 0;
initial clk_dst = 0;
always #(tCLK_src/2.0) clk_src = ~clk_src;
always #(tCLK_dst/2.0) clk_dst = ~clk_dst;
initial begin
$dumpfile("dump.vcd"); $dumpvars;
reset_src = 1'b1;
reset_dst = 1'b0;
trig_src = 1'b0;
#100;
reset_src = 1'b0;
#100;
@(posedge clk_src);
trig_src = 1'b1;
#tCLK_src;
trig_src = 1'b0;
#100
$finish;
end
endmodule | module tf; |
reg clk_src;
reg clk_dst;
reg reset_src;
reg reset_dst;
reg trig_src;
wire trig_dst;
sync_trig dut (
.clk_i (clk_src),
.clk_o (clk_dst),
.rst_i (reset_src),
.rst_o (reset_dst),
.trig_i (trig_src),
.trig_o (trig_dst)
);
parameter tCLK_src = 10;
parameter tCLK_dst = 7;
initial clk_src = 0;
initial clk_dst = 0;
always #(tCLK_src/2.0) clk_src = ~clk_src;
always #(tCLK_dst/2.0) clk_dst = ~clk_dst;
initial begin
$dumpfile("dump.vcd"); $dumpvars;
reset_src = 1'b1;
reset_dst = 1'b0;
trig_src = 1'b0;
#100;
reset_src = 1'b0;
#100;
@(posedge clk_src);
trig_src = 1'b1;
#tCLK_src;
trig_src = 1'b0;
#100
$finish;
end
endmodule | 0 |
138,747 | data/full_repos/permissive/85241035/src/test_tf.v | 85,241,035 | test_tf.v | v | 159 | 82 | [] | [] | [] | [(33, 158)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/85241035/src/test_tf.v:95: Unsupported: Ignoring delay on this delayed statement.\nalways #(tCLK/2.0) clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/85241035/src/test_tf.v:107: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85241035/src/test_tf.v:109: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/85241035/src/test_tf.v:112: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/85241035/src/test_tf.v:117: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85241035/src/test_tf.v:122: Unsupported: Ignoring delay on this delayed statement.\n #tCLK;\n ^\n%Error: data/full_repos/permissive/85241035/src/test_tf.v:126: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/85241035/src/test_tf.v:132: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85241035/src/test_tf.v:137: Unsupported: Ignoring delay on this delayed statement.\n #tCLK;\n ^\n%Error: data/full_repos/permissive/85241035/src/test_tf.v:141: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/85241035/src/test_tf.v:146: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85241035/src/test_tf.v:151: Unsupported: Ignoring delay on this delayed statement.\n #tCLK;\n ^\n%Error: Exiting due to 6 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,723 | module | module tf;
reg clk;
reg rst;
reg cmd_erase;
reg cmd_read;
reg cmd_write;
reg [15:0] cmd_addr;
reg [15:0] cmd_length;
reg [7:0] fifo_din;
wire [7:0] fifo_dout;
wire fifo_read;
wire fifo_write;
wire done;
wire [15:0] status;
wire flash_q, flash_c, flash_s_n, flash_d;
flash_b dut (
.clk (clk),
.reset (rst),
.cmd_erasesectors (cmd_erase),
.cmd_write (cmd_write),
.cmd_read (cmd_read),
.addr (cmd_addr),
.length (cmd_length),
.din (fifo_din),
.dout (fifo_dout),
.read (fifo_read),
.write (fifo_write),
.done (done),
.status (status),
.flash_q (flash_q),
.flash_c (flash_c),
.flash_s_n (flash_s_n),
.flash_d (flash_d)
);
M25P64 flash0 (
.c (flash_c),
.data_in (flash_d),
.data_out (flash_q),
.s (flash_s_n),
.w (1'b1),
.hold (1'b1)
);
parameter tCLK = 10;
initial clk = 0;
always #(tCLK/2.0) clk = ~clk;
initial cmd_erase = 1'b0;
initial cmd_read = 1'b0;
initial cmd_write = 1'b0;
initial cmd_addr = 16'h00;
initial cmd_length = 16'h00;
initial begin
rst = 1'b1;
#100;
rst = 1'b0;
#100;
@(posedge clk);
cmd_erase = 1'b1;
cmd_addr = 16'h00;
cmd_length = 16'h8;
@(posedge clk);
cmd_erase = 1'b0;
while(done == 1'b0) begin
#tCLK;
end
@(posedge clk);
cmd_write = 1'b1;
cmd_addr = 16'h10;
cmd_length = 1;
fifo_din = 8'hBE;
@(posedge clk);
cmd_write = 1'b0;
while(done == 1'b0) begin
#tCLK;
end
@(posedge clk);
cmd_read = 1'b1;
cmd_addr = 16'h0F;
cmd_length = 8'h03;
@(posedge clk);
cmd_read = 1'b0;
while(done == 1'b0) begin
#tCLK;
end
$finish;
end
endmodule | module tf; |
reg clk;
reg rst;
reg cmd_erase;
reg cmd_read;
reg cmd_write;
reg [15:0] cmd_addr;
reg [15:0] cmd_length;
reg [7:0] fifo_din;
wire [7:0] fifo_dout;
wire fifo_read;
wire fifo_write;
wire done;
wire [15:0] status;
wire flash_q, flash_c, flash_s_n, flash_d;
flash_b dut (
.clk (clk),
.reset (rst),
.cmd_erasesectors (cmd_erase),
.cmd_write (cmd_write),
.cmd_read (cmd_read),
.addr (cmd_addr),
.length (cmd_length),
.din (fifo_din),
.dout (fifo_dout),
.read (fifo_read),
.write (fifo_write),
.done (done),
.status (status),
.flash_q (flash_q),
.flash_c (flash_c),
.flash_s_n (flash_s_n),
.flash_d (flash_d)
);
M25P64 flash0 (
.c (flash_c),
.data_in (flash_d),
.data_out (flash_q),
.s (flash_s_n),
.w (1'b1),
.hold (1'b1)
);
parameter tCLK = 10;
initial clk = 0;
always #(tCLK/2.0) clk = ~clk;
initial cmd_erase = 1'b0;
initial cmd_read = 1'b0;
initial cmd_write = 1'b0;
initial cmd_addr = 16'h00;
initial cmd_length = 16'h00;
initial begin
rst = 1'b1;
#100;
rst = 1'b0;
#100;
@(posedge clk);
cmd_erase = 1'b1;
cmd_addr = 16'h00;
cmd_length = 16'h8;
@(posedge clk);
cmd_erase = 1'b0;
while(done == 1'b0) begin
#tCLK;
end
@(posedge clk);
cmd_write = 1'b1;
cmd_addr = 16'h10;
cmd_length = 1;
fifo_din = 8'hBE;
@(posedge clk);
cmd_write = 1'b0;
while(done == 1'b0) begin
#tCLK;
end
@(posedge clk);
cmd_read = 1'b1;
cmd_addr = 16'h0F;
cmd_length = 8'h03;
@(posedge clk);
cmd_read = 1'b0;
while(done == 1'b0) begin
#tCLK;
end
$finish;
end
endmodule | 13 |
138,749 | data/full_repos/permissive/85291251/ISEprj/DecInterp/src/data_fir.v | 85,291,251 | data_fir.v | v | 41 | 78 | [] | [] | [] | [(4, 41)] | null | null | 1: b'%Error: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/data_fir.v:22: Cannot find file containing module: \'wave_add\'\nwave_add \n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85291251/ISEprj/DecInterp/src,data/full_repos/permissive/85291251/wave_add\n data/full_repos/permissive/85291251/ISEprj/DecInterp/src,data/full_repos/permissive/85291251/wave_add.v\n data/full_repos/permissive/85291251/ISEprj/DecInterp/src,data/full_repos/permissive/85291251/wave_add.sv\n wave_add\n wave_add.v\n wave_add.sv\n obj_dir/wave_add\n obj_dir/wave_add.v\n obj_dir/wave_add.sv\n%Error: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/data_fir.v:33: Cannot find file containing module: \'radix_fir_65\'\nradix_fir_65 fir1(\n^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/data_fir.v:39: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 23 bits.\n : ... In instance data_fir\nassign fir_out = fir_out_reg>>(23 - 8 - 3); \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 302,726 | module | module data_fir(clk,rst_n,data_out,clk_data,fir_out,clk_fir);
`define OUT_WIDTH 8
`define FIR_OUT_SIZE 23
input clk;
input rst_n;
output [`OUT_WIDTH-1:0] data_out;
output [`OUT_WIDTH-1:0] fir_out;
output clk_data;
output clk_fir;
assign clk_data = clk;
assign clk_fir = clk;
wire data_change;
wire data_change1,data_change2;
wire [`OUT_WIDTH-1:0] data_reg;
wave_add
#( .fword1(10'd8), .fword2(10'd41))
iadd1 (
.clk(clk),
.rst_n(rst_n),
.data_change(data_change),
.data_out(data_reg)
);
assign data_out = data_reg - `OUT_WIDTH'd128;
wire [`FIR_OUT_SIZE-1:0] fir_out_reg;
radix_fir_65 fir1(
.clk(clk),
.reset(rst_n),
.X(data_out),
.Y(fir_out_reg)
);
assign fir_out = fir_out_reg>>(`FIR_OUT_SIZE - `OUT_WIDTH - 3);
endmodule | module data_fir(clk,rst_n,data_out,clk_data,fir_out,clk_fir); |
`define OUT_WIDTH 8
`define FIR_OUT_SIZE 23
input clk;
input rst_n;
output [`OUT_WIDTH-1:0] data_out;
output [`OUT_WIDTH-1:0] fir_out;
output clk_data;
output clk_fir;
assign clk_data = clk;
assign clk_fir = clk;
wire data_change;
wire data_change1,data_change2;
wire [`OUT_WIDTH-1:0] data_reg;
wave_add
#( .fword1(10'd8), .fword2(10'd41))
iadd1 (
.clk(clk),
.rst_n(rst_n),
.data_change(data_change),
.data_out(data_reg)
);
assign data_out = data_reg - `OUT_WIDTH'd128;
wire [`FIR_OUT_SIZE-1:0] fir_out_reg;
radix_fir_65 fir1(
.clk(clk),
.reset(rst_n),
.X(data_out),
.Y(fir_out_reg)
);
assign fir_out = fir_out_reg>>(`FIR_OUT_SIZE - `OUT_WIDTH - 3);
endmodule | 29 |
138,750 | data/full_repos/permissive/85291251/ISEprj/DecInterp/src/interpolation.v | 85,291,251 | interpolation.v | v | 129 | 121 | [] | [] | [] | [(3, 129)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/interpolation.v:32: Operator EQ expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'cnt\' generates 3 bits.\n : ... In instance interpolation\n if (cnt == (8 -1)>>1 || cnt == (8 -1))\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/interpolation.v:32: Operator EQ expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'cnt\' generates 3 bits.\n : ... In instance interpolation\n if (cnt == (8 -1)>>1 || cnt == (8 -1))\n ^~\n%Error: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/interpolation.v:39: Cannot find file containing module: \'wave_add\'\nwave_add \n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85291251/ISEprj/DecInterp/src,data/full_repos/permissive/85291251/wave_add\n data/full_repos/permissive/85291251/ISEprj/DecInterp/src,data/full_repos/permissive/85291251/wave_add.v\n data/full_repos/permissive/85291251/ISEprj/DecInterp/src,data/full_repos/permissive/85291251/wave_add.sv\n wave_add\n wave_add.v\n wave_add.sv\n obj_dir/wave_add\n obj_dir/wave_add.v\n obj_dir/wave_add.sv\n%Error: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/interpolation.v:51: Cannot find file containing module: \'hdec_1_Verilog\'\nhdec_1_Verilog hn1(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/interpolation.v:58: Cannot find file containing module: \'hdec_2_Verilog\'\nhdec_2_Verilog hn2(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/interpolation.v:65: Cannot find file containing module: \'hdec_3_Verilog\'\nhdec_3_Verilog hn3(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/interpolation.v:72: Cannot find file containing module: \'hdec_4_Verilog\'\nhdec_4_Verilog hn4(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/interpolation.v:79: Cannot find file containing module: \'hdec_5_Verilog\'\nhdec_5_Verilog hn5(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/interpolation.v:86: Cannot find file containing module: \'hdec_6_Verilog\'\nhdec_6_Verilog hn6(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/interpolation.v:93: Cannot find file containing module: \'hdec_7_Verilog\'\nhdec_7_Verilog hn7(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/interpolation.v:100: Cannot find file containing module: \'hdec_8_Verilog\'\nhdec_8_Verilog hn8(\n^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/interpolation.v:127: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 23 bits.\n : ... In instance interpolation\nassign fir_out = (fir_out_reg>>(23 - 8 - 3 -2)); \n ^\n%Error: Exiting due to 9 error(s), 3 warning(s)\n' | 302,728 | module | module interpolation(clk,rst_n,data_out,clk_data,fir_out,clk_fir);
`define OUT_WIDTH 8
`define FIR_OUTS_SIZE 20
`define FIR_OUT_SIZE 23
`define PHASE_NUM 8
`define PHASE_BIT 3
input clk;
input rst_n;
output [`OUT_WIDTH-1:0] data_out;
output [`OUT_WIDTH-1:0] fir_out;
output clk_data;
output clk_fir;
assign clk_fir = clk;
wire data_change;
wire [`OUT_WIDTH-1:0] data_reg;
reg clk_org;
assign clk_data = clk_org;
reg [`PHASE_BIT-1:0] cnt;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
cnt <= `PHASE_BIT'd0;
clk_org <= 0;
end
else begin
cnt <= cnt + 1'b1;
if (cnt == (`PHASE_NUM -1)>>1 || cnt == (`PHASE_NUM -1))
clk_org <= ~clk_org;
end
end
wave_add
#( .fword1(10'd8), .fword2(10'd41))
iadd2 (
.clk(clk_org),
.rst_n(rst_n),
.data_change(data_change),
.data_out(data_reg)
);
assign data_out = data_reg - `OUT_WIDTH'd128;
wire [`FIR_OUTS_SIZE-1:0] fir_outs[0:`PHASE_NUM-1];
hdec_1_Verilog hn1(
.clk(clk),
.reset(rst_n),
.X(data_out),
.Y(fir_outs[0])
);
hdec_2_Verilog hn2(
.clk(clk),
.reset(rst_n),
.X(data_out),
.Y(fir_outs[1])
);
hdec_3_Verilog hn3(
.clk(clk),
.reset(rst_n),
.X(data_out),
.Y(fir_outs[2])
);
hdec_4_Verilog hn4(
.clk(clk),
.reset(rst_n),
.X(data_out),
.Y(fir_outs[3])
);
hdec_5_Verilog hn5(
.clk(clk),
.reset(rst_n),
.X(data_out),
.Y(fir_outs[4])
);
hdec_6_Verilog hn6(
.clk(clk),
.reset(rst_n),
.X(data_out),
.Y(fir_outs[5])
);
hdec_7_Verilog hn7(
.clk(clk),
.reset(rst_n),
.X(data_out),
.Y(fir_outs[6])
);
hdec_8_Verilog hn8(
.clk(clk),
.reset(rst_n),
.X(data_out),
.Y(fir_outs[7])
);
reg [`FIR_OUT_SIZE-1:0] fir_out_reg;
wire [`FIR_OUT_SIZE-1:0] fir_outs_reg[0:`PHASE_NUM-1];
assign fir_outs_reg[0] = fir_outs[0][`FIR_OUTS_SIZE-1]==0?{`PHASE_BIT'b000, fir_outs[0]}:{`PHASE_BIT'b111, fir_outs[0]};
assign fir_outs_reg[1] = fir_outs[1][`FIR_OUTS_SIZE-1]==0?{`PHASE_BIT'b000, fir_outs[1]}:{`PHASE_BIT'b111, fir_outs[1]};
assign fir_outs_reg[2] = fir_outs[2][`FIR_OUTS_SIZE-1]==0?{`PHASE_BIT'b000, fir_outs[2]}:{`PHASE_BIT'b111, fir_outs[2]};
assign fir_outs_reg[3] = fir_outs[3][`FIR_OUTS_SIZE-1]==0?{`PHASE_BIT'b000, fir_outs[3]}:{`PHASE_BIT'b111, fir_outs[3]};
assign fir_outs_reg[4] = fir_outs[4][`FIR_OUTS_SIZE-1]==0?{`PHASE_BIT'b000, fir_outs[4]}:{`PHASE_BIT'b111, fir_outs[4]};
assign fir_outs_reg[5] = fir_outs[5][`FIR_OUTS_SIZE-1]==0?{`PHASE_BIT'b000, fir_outs[5]}:{`PHASE_BIT'b111, fir_outs[5]};
assign fir_outs_reg[6] = fir_outs[6][`FIR_OUTS_SIZE-1]==0?{`PHASE_BIT'b000, fir_outs[6]}:{`PHASE_BIT'b111, fir_outs[6]};
assign fir_outs_reg[7] = fir_outs[7][`FIR_OUTS_SIZE-1]==0?{`PHASE_BIT'b000, fir_outs[7]}:{`PHASE_BIT'b111, fir_outs[7]};
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
fir_out_reg <= `FIR_OUT_SIZE'd0;
else
fir_out_reg <= fir_outs_reg[cnt];
end
assign fir_out = (fir_out_reg>>(`FIR_OUT_SIZE - `OUT_WIDTH - `PHASE_BIT -2));
endmodule | module interpolation(clk,rst_n,data_out,clk_data,fir_out,clk_fir); |
`define OUT_WIDTH 8
`define FIR_OUTS_SIZE 20
`define FIR_OUT_SIZE 23
`define PHASE_NUM 8
`define PHASE_BIT 3
input clk;
input rst_n;
output [`OUT_WIDTH-1:0] data_out;
output [`OUT_WIDTH-1:0] fir_out;
output clk_data;
output clk_fir;
assign clk_fir = clk;
wire data_change;
wire [`OUT_WIDTH-1:0] data_reg;
reg clk_org;
assign clk_data = clk_org;
reg [`PHASE_BIT-1:0] cnt;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
cnt <= `PHASE_BIT'd0;
clk_org <= 0;
end
else begin
cnt <= cnt + 1'b1;
if (cnt == (`PHASE_NUM -1)>>1 || cnt == (`PHASE_NUM -1))
clk_org <= ~clk_org;
end
end
wave_add
#( .fword1(10'd8), .fword2(10'd41))
iadd2 (
.clk(clk_org),
.rst_n(rst_n),
.data_change(data_change),
.data_out(data_reg)
);
assign data_out = data_reg - `OUT_WIDTH'd128;
wire [`FIR_OUTS_SIZE-1:0] fir_outs[0:`PHASE_NUM-1];
hdec_1_Verilog hn1(
.clk(clk),
.reset(rst_n),
.X(data_out),
.Y(fir_outs[0])
);
hdec_2_Verilog hn2(
.clk(clk),
.reset(rst_n),
.X(data_out),
.Y(fir_outs[1])
);
hdec_3_Verilog hn3(
.clk(clk),
.reset(rst_n),
.X(data_out),
.Y(fir_outs[2])
);
hdec_4_Verilog hn4(
.clk(clk),
.reset(rst_n),
.X(data_out),
.Y(fir_outs[3])
);
hdec_5_Verilog hn5(
.clk(clk),
.reset(rst_n),
.X(data_out),
.Y(fir_outs[4])
);
hdec_6_Verilog hn6(
.clk(clk),
.reset(rst_n),
.X(data_out),
.Y(fir_outs[5])
);
hdec_7_Verilog hn7(
.clk(clk),
.reset(rst_n),
.X(data_out),
.Y(fir_outs[6])
);
hdec_8_Verilog hn8(
.clk(clk),
.reset(rst_n),
.X(data_out),
.Y(fir_outs[7])
);
reg [`FIR_OUT_SIZE-1:0] fir_out_reg;
wire [`FIR_OUT_SIZE-1:0] fir_outs_reg[0:`PHASE_NUM-1];
assign fir_outs_reg[0] = fir_outs[0][`FIR_OUTS_SIZE-1]==0?{`PHASE_BIT'b000, fir_outs[0]}:{`PHASE_BIT'b111, fir_outs[0]};
assign fir_outs_reg[1] = fir_outs[1][`FIR_OUTS_SIZE-1]==0?{`PHASE_BIT'b000, fir_outs[1]}:{`PHASE_BIT'b111, fir_outs[1]};
assign fir_outs_reg[2] = fir_outs[2][`FIR_OUTS_SIZE-1]==0?{`PHASE_BIT'b000, fir_outs[2]}:{`PHASE_BIT'b111, fir_outs[2]};
assign fir_outs_reg[3] = fir_outs[3][`FIR_OUTS_SIZE-1]==0?{`PHASE_BIT'b000, fir_outs[3]}:{`PHASE_BIT'b111, fir_outs[3]};
assign fir_outs_reg[4] = fir_outs[4][`FIR_OUTS_SIZE-1]==0?{`PHASE_BIT'b000, fir_outs[4]}:{`PHASE_BIT'b111, fir_outs[4]};
assign fir_outs_reg[5] = fir_outs[5][`FIR_OUTS_SIZE-1]==0?{`PHASE_BIT'b000, fir_outs[5]}:{`PHASE_BIT'b111, fir_outs[5]};
assign fir_outs_reg[6] = fir_outs[6][`FIR_OUTS_SIZE-1]==0?{`PHASE_BIT'b000, fir_outs[6]}:{`PHASE_BIT'b111, fir_outs[6]};
assign fir_outs_reg[7] = fir_outs[7][`FIR_OUTS_SIZE-1]==0?{`PHASE_BIT'b000, fir_outs[7]}:{`PHASE_BIT'b111, fir_outs[7]};
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
fir_out_reg <= `FIR_OUT_SIZE'd0;
else
fir_out_reg <= fir_outs_reg[cnt];
end
assign fir_out = (fir_out_reg>>(`FIR_OUT_SIZE - `OUT_WIDTH - `PHASE_BIT -2));
endmodule | 29 |
138,751 | data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v | 85,291,251 | radix_fir_65.v | v | 533 | 94 | [] | [] | [] | null | line:313: before: ";" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:36: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'X\' generates 8 bits.\n : ... In instance radix_fir_65\nassign x1 = X;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:37: Operator SHIFTL expects 11 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x3 = +(x1<<1)+(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:37: Operator SHIFTL expects 11 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x3 = +(x1<<1)+(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:38: Operator SHIFTL expects 12 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x5 = +(x1<<2)+(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:38: Operator SHIFTL expects 12 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x5 = +(x1<<2)+(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:39: Operator SHIFTL expects 12 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x7 = +(x1<<3)-(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:39: Operator SHIFTL expects 12 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x7 = +(x1<<3)-(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:76: Operator SHIFTL expects 15 bits on the LHS, but LHS\'s VARREF \'x3\' generates 11 bits.\n : ... In instance radix_fir_65\nassign x_58 = +(x3<<1)-(x1<<6);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:76: Operator SHIFTL expects 15 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x_58 = +(x3<<1)-(x1<<6);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:77: Operator SHIFTL expects 18 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x256 = +(x1<<8);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:78: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x95 = -(x1<<0)+(x3<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:78: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x3\' generates 11 bits.\n : ... In instance radix_fir_65\nassign x95 = -(x1<<0)+(x3<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:79: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x66 = +(x1<<1)+(x1<<6);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:79: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x66 = +(x1<<1)+(x1<<6);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:80: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x64 = +(x1<<6);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:81: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x3\' generates 11 bits.\n : ... In instance radix_fir_65\nassign x67 = +(x3<<0)+(x1<<6);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:81: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x67 = +(x3<<0)+(x1<<6);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:82: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x73 = -(x7<<0)+(x5<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:82: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x73 = -(x7<<0)+(x5<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:83: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x78 = +(x7<<1)+(x1<<6);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:83: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x78 = +(x7<<1)+(x1<<6);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:84: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x3\' generates 11 bits.\n : ... In instance radix_fir_65\nassign x83 = +(x3<<0)+(x5<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:84: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x83 = +(x3<<0)+(x5<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:85: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x89 = -(x7<<0)+(x3<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:85: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x3\' generates 11 bits.\n : ... In instance radix_fir_65\nassign x89 = -(x7<<0)+(x3<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:86: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x94 = -(x1<<1)+(x3<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:86: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x3\' generates 11 bits.\n : ... In instance radix_fir_65\nassign x94 = -(x1<<1)+(x3<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:87: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x3\' generates 11 bits.\n : ... In instance radix_fir_65\nassign x99 = +(x3<<0)+(x3<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:87: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x3\' generates 11 bits.\n : ... In instance radix_fir_65\nassign x99 = +(x3<<0)+(x3<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:88: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x105 = -(x7<<0)+(x7<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:88: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x105 = -(x7<<0)+(x7<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:89: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x110 = +(x7<<1)+(x3<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:89: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x3\' generates 11 bits.\n : ... In instance radix_fir_65\nassign x110 = +(x7<<1)+(x3<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:90: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x3\' generates 11 bits.\n : ... In instance radix_fir_65\nassign x116 = -(x3<<2)+(x1<<7);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:90: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x116 = -(x3<<2)+(x1<<7);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:91: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x121 = -(x7<<0)+(x1<<7);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:91: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x121 = -(x7<<0)+(x1<<7);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:92: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x126 = -(x1<<1)+(x1<<7);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:92: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x126 = -(x1<<1)+(x1<<7);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:93: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x130 = +(x1<<1)+(x1<<7);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:93: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x130 = +(x1<<1)+(x1<<7);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:94: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x135 = +(x7<<0)+(x1<<7);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:94: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x135 = +(x7<<0)+(x1<<7);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:95: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x139 = -(x5<<0)-(x7<<4)+(x1<<8);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:95: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x139 = -(x5<<0)-(x7<<4)+(x1<<8);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:95: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x139 = -(x5<<0)-(x7<<4)+(x1<<8);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:96: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x144 = -(x7<<4)+(x1<<8);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:96: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x144 = -(x7<<4)+(x1<<8);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:97: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x148 = +(x5<<2)+(x1<<7);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:97: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x148 = +(x5<<2)+(x1<<7);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:98: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x151 = +(x7<<0)-(x7<<4)+(x1<<8);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:98: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x151 = +(x7<<0)-(x7<<4)+(x1<<8);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:98: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x151 = +(x7<<0)-(x7<<4)+(x1<<8);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:99: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x155 = -(x5<<0)+(x5<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:99: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x155 = -(x5<<0)+(x5<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:100: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x158 = -(x1<<1)+(x5<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:100: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x158 = -(x1<<1)+(x5<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:101: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x161 = +(x1<<0)+(x5<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:101: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x161 = +(x1<<0)+(x5<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:102: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x3\' generates 11 bits.\n : ... In instance radix_fir_65\nassign x163 = +(x3<<0)+(x5<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:102: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x163 = +(x3<<0)+(x5<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:103: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x165 = +(x5<<0)+(x5<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:103: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x165 = +(x5<<0)+(x5<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:104: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x167 = +(x7<<0)+(x5<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:104: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x167 = +(x7<<0)+(x5<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:105: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x168 = +(x5<<3)+(x1<<7);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:105: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x168 = +(x5<<3)+(x1<<7);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:106: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x169 = -(x7<<0)-(x5<<4)+(x1<<8);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:106: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x169 = -(x7<<0)-(x5<<4)+(x1<<8);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:106: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_65\nassign x169 = -(x7<<0)-(x5<<4)+(x1<<8);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:107: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x170 = +(x5<<1)+(x5<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:107: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance radix_fir_65\nassign x170 = +(x5<<1)+(x5<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:318: Operator ADD expects 23 bits on the RHS, but RHS\'s VARREF \'SCM_0\' generates 15 bits.\n : ... In instance radix_fir_65\n MAC_0 <= MAC_1 + SCM_0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:319: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_1\' generates 18 bits.\n : ... In instance radix_fir_65\n MAC_1 <= MAC_2 + SCM_1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:320: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_2\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_2 <= MAC_3 + SCM_2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:321: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_3\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_3 <= MAC_4 + SCM_3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:322: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_4\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_4 <= MAC_5 + SCM_4;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:323: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_5\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_5 <= MAC_6 + SCM_5;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:324: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_6\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_6 <= MAC_7 + SCM_6;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:325: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_7\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_7 <= MAC_8 + SCM_7;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:326: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_8\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_8 <= MAC_9 + SCM_8;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:327: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_9\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_9 <= MAC_10 + SCM_9;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:328: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_10\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_10 <= MAC_11 + SCM_10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:329: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_11\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_11 <= MAC_12 + SCM_11;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:330: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_12\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_12 <= MAC_13 + SCM_12;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:331: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_13\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_13 <= MAC_14 + SCM_13;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:332: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_14\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_14 <= MAC_15 + SCM_14;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:333: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_15\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_15 <= MAC_16 + SCM_15;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:334: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_16\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_16 <= MAC_17 + SCM_16;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:335: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_17\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_17 <= MAC_18 + SCM_17;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:336: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_18\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_18 <= MAC_19 + SCM_18;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:337: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_19\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_19 <= MAC_20 + SCM_19;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:338: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_20\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_20 <= MAC_21 + SCM_20;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:339: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_21\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_21 <= MAC_22 + SCM_21;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:340: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_22\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_22 <= MAC_23 + SCM_22;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:341: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_23\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_23 <= MAC_24 + SCM_23;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:342: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_24\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_24 <= MAC_25 + SCM_24;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:343: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_25\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_25 <= MAC_26 + SCM_25;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:344: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_26\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_26 <= MAC_27 + SCM_26;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:345: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_27\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_27 <= MAC_28 + SCM_27;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:346: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_28\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_28 <= MAC_29 + SCM_28;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:347: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_29\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_29 <= MAC_30 + SCM_29;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:348: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_30\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_30 <= MAC_31 + SCM_30;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:349: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_31\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_31 <= MAC_32 + SCM_31;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:350: Operator ADD expects 22 bits on the RHS, but RHS\'s VARREF \'SCM_32\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_32 <= MAC_33 + SCM_32;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:351: Operator ADD expects 21 bits on the RHS, but RHS\'s VARREF \'SCM_33\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_33 <= MAC_34 + SCM_33;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:352: Operator ADD expects 21 bits on the RHS, but RHS\'s VARREF \'SCM_34\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_34 <= MAC_35 + SCM_34;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:353: Operator ADD expects 21 bits on the RHS, but RHS\'s VARREF \'SCM_35\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_35 <= MAC_36 + SCM_35;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:354: Operator ADD expects 21 bits on the RHS, but RHS\'s VARREF \'SCM_36\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_36 <= MAC_37 + SCM_36;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:355: Operator ADD expects 21 bits on the RHS, but RHS\'s VARREF \'SCM_37\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_37 <= MAC_38 + SCM_37;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:356: Operator ADD expects 21 bits on the RHS, but RHS\'s VARREF \'SCM_38\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_38 <= MAC_39 + SCM_38;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:357: Operator ADD expects 21 bits on the RHS, but RHS\'s VARREF \'SCM_39\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_39 <= MAC_40 + SCM_39;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:358: Operator ADD expects 21 bits on the RHS, but RHS\'s VARREF \'SCM_40\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_40 <= MAC_41 + SCM_40;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:359: Operator ADD expects 21 bits on the RHS, but RHS\'s VARREF \'SCM_41\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_41 <= MAC_42 + SCM_41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:360: Operator ADD expects 21 bits on the RHS, but RHS\'s VARREF \'SCM_42\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_42 <= MAC_43 + SCM_42;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:361: Operator ADD expects 21 bits on the RHS, but RHS\'s VARREF \'SCM_43\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_43 <= MAC_44 + SCM_43;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:362: Operator ADD expects 21 bits on the RHS, but RHS\'s VARREF \'SCM_44\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_44 <= MAC_45 + SCM_44;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:363: Operator ADD expects 21 bits on the RHS, but RHS\'s VARREF \'SCM_45\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_45 <= MAC_46 + SCM_45;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:364: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_46\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_46 <= MAC_47 + SCM_46;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:365: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_47\' generates 17 bits.\n : ... In instance radix_fir_65\n MAC_47 <= MAC_48 + SCM_47;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:366: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_48\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_48 <= MAC_49 + SCM_48;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:367: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_49\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_49 <= MAC_50 + SCM_49;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:368: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_50\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_50 <= MAC_51 + SCM_50;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:369: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_51\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_51 <= MAC_52 + SCM_51;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:370: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_52\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_52 <= MAC_53 + SCM_52;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:371: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_53\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_53 <= MAC_54 + SCM_53;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:372: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'SCM_54\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_54 <= MAC_55 + SCM_54;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:373: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'SCM_55\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_55 <= MAC_56 + SCM_55;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:374: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'SCM_56\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_56 <= MAC_57 + SCM_56;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:375: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'SCM_57\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_57 <= MAC_58 + SCM_57;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:376: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'SCM_58\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_58 <= MAC_59 + SCM_58;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:377: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'SCM_59\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_59 <= MAC_60 + SCM_59;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:378: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'SCM_60\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_60 <= MAC_61 + SCM_60;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:379: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'SCM_61\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_61 <= MAC_62 + SCM_61;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:380: Operator ADD expects 18 bits on the RHS, but RHS\'s VARREF \'SCM_62\' generates 16 bits.\n : ... In instance radix_fir_65\n MAC_62 <= MAC_63 + SCM_62;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/radix_fir_65.v:381: Operator ADD expects 18 bits on the LHS, but LHS\'s VARREF \'MAC_64\' generates 15 bits.\n : ... In instance radix_fir_65\n MAC_63 <= MAC_64 + SCM_63;\n ^\n%Error: Exiting due to 136 warning(s)\n' | 302,731 | module | module radix_fir_65 (clk, reset, X, Y);
parameter word_size_in = 8;
parameter word_size_out = 23;
input clk, reset;
input signed [word_size_in-1:0] X;
output signed [word_size_out-1:0] Y;
reg [word_size_out-1:0] Y;
wire signed [word_size_in:0] x1;
wire signed [10:0] x3;
wire signed [11:0] x5;
wire signed [11:0] x7;
assign x1 = X;
assign x3 = +(x1<<1)+(x1<<0);
assign x5 = +(x1<<2)+(x1<<0);
assign x7 = +(x1<<3)-(x1<<0);
wire signed [14:0] x_58;
wire signed [17:0] x256;
wire signed [15:0] x95;
wire signed [15:0] x66;
wire signed [15:0] x64;
wire signed [15:0] x67;
wire signed [15:0] x73;
wire signed [15:0] x78;
wire signed [15:0] x83;
wire signed [15:0] x89;
wire signed [15:0] x94;
wire signed [15:0] x99;
wire signed [15:0] x105;
wire signed [15:0] x110;
wire signed [15:0] x116;
wire signed [15:0] x121;
wire signed [15:0] x126;
wire signed [16:0] x130;
wire signed [16:0] x135;
wire signed [16:0] x139;
wire signed [16:0] x144;
wire signed [16:0] x148;
wire signed [16:0] x151;
wire signed [16:0] x155;
wire signed [16:0] x158;
wire signed [16:0] x161;
wire signed [16:0] x163;
wire signed [16:0] x165;
wire signed [16:0] x167;
wire signed [16:0] x168;
wire signed [16:0] x169;
wire signed [16:0] x170;
assign x_58 = +(x3<<1)-(x1<<6);
assign x256 = +(x1<<8);
assign x95 = -(x1<<0)+(x3<<5);
assign x66 = +(x1<<1)+(x1<<6);
assign x64 = +(x1<<6);
assign x67 = +(x3<<0)+(x1<<6);
assign x73 = -(x7<<0)+(x5<<4);
assign x78 = +(x7<<1)+(x1<<6);
assign x83 = +(x3<<0)+(x5<<4);
assign x89 = -(x7<<0)+(x3<<5);
assign x94 = -(x1<<1)+(x3<<5);
assign x99 = +(x3<<0)+(x3<<5);
assign x105 = -(x7<<0)+(x7<<4);
assign x110 = +(x7<<1)+(x3<<5);
assign x116 = -(x3<<2)+(x1<<7);
assign x121 = -(x7<<0)+(x1<<7);
assign x126 = -(x1<<1)+(x1<<7);
assign x130 = +(x1<<1)+(x1<<7);
assign x135 = +(x7<<0)+(x1<<7);
assign x139 = -(x5<<0)-(x7<<4)+(x1<<8);
assign x144 = -(x7<<4)+(x1<<8);
assign x148 = +(x5<<2)+(x1<<7);
assign x151 = +(x7<<0)-(x7<<4)+(x1<<8);
assign x155 = -(x5<<0)+(x5<<5);
assign x158 = -(x1<<1)+(x5<<5);
assign x161 = +(x1<<0)+(x5<<5);
assign x163 = +(x3<<0)+(x5<<5);
assign x165 = +(x5<<0)+(x5<<5);
assign x167 = +(x7<<0)+(x5<<5);
assign x168 = +(x5<<3)+(x1<<7);
assign x169 = -(x7<<0)-(x5<<4)+(x1<<8);
assign x170 = +(x5<<1)+(x5<<5);
wire signed [14:0] SCM_0;
wire signed [17:0] SCM_1;
wire signed [15:0] SCM_2;
wire signed [15:0] SCM_3;
wire signed [15:0] SCM_4;
wire signed [15:0] SCM_5;
wire signed [15:0] SCM_6;
wire signed [15:0] SCM_7;
wire signed [15:0] SCM_8;
wire signed [15:0] SCM_9;
wire signed [15:0] SCM_10;
wire signed [15:0] SCM_11;
wire signed [15:0] SCM_12;
wire signed [15:0] SCM_13;
wire signed [15:0] SCM_14;
wire signed [15:0] SCM_15;
wire signed [15:0] SCM_16;
wire signed [16:0] SCM_17;
wire signed [16:0] SCM_18;
wire signed [16:0] SCM_19;
wire signed [16:0] SCM_20;
wire signed [16:0] SCM_21;
wire signed [16:0] SCM_22;
wire signed [16:0] SCM_23;
wire signed [16:0] SCM_24;
wire signed [16:0] SCM_25;
wire signed [16:0] SCM_26;
wire signed [16:0] SCM_27;
wire signed [16:0] SCM_28;
wire signed [16:0] SCM_29;
wire signed [16:0] SCM_30;
wire signed [16:0] SCM_31;
wire signed [16:0] SCM_32;
wire signed [16:0] SCM_33;
wire signed [16:0] SCM_34;
wire signed [16:0] SCM_35;
wire signed [16:0] SCM_36;
wire signed [16:0] SCM_37;
wire signed [16:0] SCM_38;
wire signed [16:0] SCM_39;
wire signed [16:0] SCM_40;
wire signed [16:0] SCM_41;
wire signed [16:0] SCM_42;
wire signed [16:0] SCM_43;
wire signed [16:0] SCM_44;
wire signed [16:0] SCM_45;
wire signed [16:0] SCM_46;
wire signed [16:0] SCM_47;
wire signed [15:0] SCM_48;
wire signed [15:0] SCM_49;
wire signed [15:0] SCM_50;
wire signed [15:0] SCM_51;
wire signed [15:0] SCM_52;
wire signed [15:0] SCM_53;
wire signed [15:0] SCM_54;
wire signed [15:0] SCM_55;
wire signed [15:0] SCM_56;
wire signed [15:0] SCM_57;
wire signed [15:0] SCM_58;
wire signed [15:0] SCM_59;
wire signed [15:0] SCM_60;
wire signed [15:0] SCM_61;
wire signed [15:0] SCM_62;
wire signed [17:0] SCM_63;
wire signed [14:0] SCM_64;
assign SCM_0 = x_58;
assign SCM_1 = x256;
assign SCM_2 = x95;
assign SCM_3 = x66;
assign SCM_4 = x64;
assign SCM_5 = x67;
assign SCM_6 = x73;
assign SCM_7 = x78;
assign SCM_8 = x83;
assign SCM_9 = x89;
assign SCM_10 = x94;
assign SCM_11 = x99;
assign SCM_12 = x105;
assign SCM_13 = x110;
assign SCM_14 = x116;
assign SCM_15 = x121;
assign SCM_16 = x126;
assign SCM_17 = x130;
assign SCM_18 = x135;
assign SCM_19 = x139;
assign SCM_20 = x144;
assign SCM_21 = x148;
assign SCM_22 = x151;
assign SCM_23 = x155;
assign SCM_24 = x158;
assign SCM_25 = x161;
assign SCM_26 = x163;
assign SCM_27 = x165;
assign SCM_28 = x167;
assign SCM_29 = x168;
assign SCM_30 = x169;
assign SCM_31 = x170;
assign SCM_32 = x170;
assign SCM_33 = x170;
assign SCM_34 = x169;
assign SCM_35 = x168;
assign SCM_36 = x167;
assign SCM_37 = x165;
assign SCM_38 = x163;
assign SCM_39 = x161;
assign SCM_40 = x158;
assign SCM_41 = x155;
assign SCM_42 = x151;
assign SCM_43 = x148;
assign SCM_44 = x144;
assign SCM_45 = x139;
assign SCM_46 = x135;
assign SCM_47 = x130;
assign SCM_48 = x126;
assign SCM_49 = x121;
assign SCM_50 = x116;
assign SCM_51 = x110;
assign SCM_52 = x105;
assign SCM_53 = x99;
assign SCM_54 = x94;
assign SCM_55 = x89;
assign SCM_56 = x83;
assign SCM_57 = x78;
assign SCM_58 = x73;
assign SCM_59 = x67;
assign SCM_60 = x64;
assign SCM_61 = x66;
assign SCM_62 = x95;
assign SCM_63 = x256;
assign SCM_64 = x_58;
reg signed [22:0] MAC_0;
reg signed [21:0] MAC_1;
reg signed [21:0] MAC_2;
reg signed [21:0] MAC_3;
reg signed [21:0] MAC_4;
reg signed [21:0] MAC_5;
reg signed [21:0] MAC_6;
reg signed [21:0] MAC_7;
reg signed [21:0] MAC_8;
reg signed [21:0] MAC_9;
reg signed [21:0] MAC_10;
reg signed [21:0] MAC_11;
reg signed [21:0] MAC_12;
reg signed [21:0] MAC_13;
reg signed [21:0] MAC_14;
reg signed [21:0] MAC_15;
reg signed [21:0] MAC_16;
reg signed [21:0] MAC_17;
reg signed [21:0] MAC_18;
reg signed [21:0] MAC_19;
reg signed [21:0] MAC_20;
reg signed [21:0] MAC_21;
reg signed [21:0] MAC_22;
reg signed [21:0] MAC_23;
reg signed [21:0] MAC_24;
reg signed [21:0] MAC_25;
reg signed [21:0] MAC_26;
reg signed [21:0] MAC_27;
reg signed [21:0] MAC_28;
reg signed [21:0] MAC_29;
reg signed [21:0] MAC_30;
reg signed [21:0] MAC_31;
reg signed [21:0] MAC_32;
reg signed [20:0] MAC_33;
reg signed [20:0] MAC_34;
reg signed [20:0] MAC_35;
reg signed [20:0] MAC_36;
reg signed [20:0] MAC_37;
reg signed [20:0] MAC_38;
reg signed [20:0] MAC_39;
reg signed [20:0] MAC_40;
reg signed [20:0] MAC_41;
reg signed [20:0] MAC_42;
reg signed [20:0] MAC_43;
reg signed [20:0] MAC_44;
reg signed [20:0] MAC_45;
reg signed [19:0] MAC_46;
reg signed [19:0] MAC_47;
reg signed [19:0] MAC_48;
reg signed [19:0] MAC_49;
reg signed [19:0] MAC_50;
reg signed [19:0] MAC_51;
reg signed [19:0] MAC_52;
reg signed [19:0] MAC_53;
reg signed [18:0] MAC_54;
reg signed [18:0] MAC_55;
reg signed [18:0] MAC_56;
reg signed [18:0] MAC_57;
reg signed [18:0] MAC_58;
reg signed [18:0] MAC_59;
reg signed [18:0] MAC_60;
reg signed [17:0] MAC_61;
reg signed [17:0] MAC_62;
reg signed [17:0] MAC_63;
reg signed [14:0] MAC_64;
wire signed [22:0] Y_in;
always @(posedge clk or negedge reset) begin
if(~reset) begin
reset_reg;
end
else begin
init_reg;
Y <= Y_in;
MAC_0 <= MAC_1 + SCM_0;
MAC_1 <= MAC_2 + SCM_1;
MAC_2 <= MAC_3 + SCM_2;
MAC_3 <= MAC_4 + SCM_3;
MAC_4 <= MAC_5 + SCM_4;
MAC_5 <= MAC_6 + SCM_5;
MAC_6 <= MAC_7 + SCM_6;
MAC_7 <= MAC_8 + SCM_7;
MAC_8 <= MAC_9 + SCM_8;
MAC_9 <= MAC_10 + SCM_9;
MAC_10 <= MAC_11 + SCM_10;
MAC_11 <= MAC_12 + SCM_11;
MAC_12 <= MAC_13 + SCM_12;
MAC_13 <= MAC_14 + SCM_13;
MAC_14 <= MAC_15 + SCM_14;
MAC_15 <= MAC_16 + SCM_15;
MAC_16 <= MAC_17 + SCM_16;
MAC_17 <= MAC_18 + SCM_17;
MAC_18 <= MAC_19 + SCM_18;
MAC_19 <= MAC_20 + SCM_19;
MAC_20 <= MAC_21 + SCM_20;
MAC_21 <= MAC_22 + SCM_21;
MAC_22 <= MAC_23 + SCM_22;
MAC_23 <= MAC_24 + SCM_23;
MAC_24 <= MAC_25 + SCM_24;
MAC_25 <= MAC_26 + SCM_25;
MAC_26 <= MAC_27 + SCM_26;
MAC_27 <= MAC_28 + SCM_27;
MAC_28 <= MAC_29 + SCM_28;
MAC_29 <= MAC_30 + SCM_29;
MAC_30 <= MAC_31 + SCM_30;
MAC_31 <= MAC_32 + SCM_31;
MAC_32 <= MAC_33 + SCM_32;
MAC_33 <= MAC_34 + SCM_33;
MAC_34 <= MAC_35 + SCM_34;
MAC_35 <= MAC_36 + SCM_35;
MAC_36 <= MAC_37 + SCM_36;
MAC_37 <= MAC_38 + SCM_37;
MAC_38 <= MAC_39 + SCM_38;
MAC_39 <= MAC_40 + SCM_39;
MAC_40 <= MAC_41 + SCM_40;
MAC_41 <= MAC_42 + SCM_41;
MAC_42 <= MAC_43 + SCM_42;
MAC_43 <= MAC_44 + SCM_43;
MAC_44 <= MAC_45 + SCM_44;
MAC_45 <= MAC_46 + SCM_45;
MAC_46 <= MAC_47 + SCM_46;
MAC_47 <= MAC_48 + SCM_47;
MAC_48 <= MAC_49 + SCM_48;
MAC_49 <= MAC_50 + SCM_49;
MAC_50 <= MAC_51 + SCM_50;
MAC_51 <= MAC_52 + SCM_51;
MAC_52 <= MAC_53 + SCM_52;
MAC_53 <= MAC_54 + SCM_53;
MAC_54 <= MAC_55 + SCM_54;
MAC_55 <= MAC_56 + SCM_55;
MAC_56 <= MAC_57 + SCM_56;
MAC_57 <= MAC_58 + SCM_57;
MAC_58 <= MAC_59 + SCM_58;
MAC_59 <= MAC_60 + SCM_59;
MAC_60 <= MAC_61 + SCM_60;
MAC_61 <= MAC_62 + SCM_61;
MAC_62 <= MAC_63 + SCM_62;
MAC_63 <= MAC_64 + SCM_63;
MAC_64 <= SCM_64;
end
end
assign Y_in = MAC_0;
task reset_reg;
begin
MAC_0 <= 0;
MAC_1 <= 0;
MAC_2 <= 0;
MAC_3 <= 0;
MAC_4 <= 0;
MAC_5 <= 0;
MAC_6 <= 0;
MAC_7 <= 0;
MAC_8 <= 0;
MAC_9 <= 0;
MAC_10 <= 0;
MAC_11 <= 0;
MAC_12 <= 0;
MAC_13 <= 0;
MAC_14 <= 0;
MAC_15 <= 0;
MAC_16 <= 0;
MAC_17 <= 0;
MAC_18 <= 0;
MAC_19 <= 0;
MAC_20 <= 0;
MAC_21 <= 0;
MAC_22 <= 0;
MAC_23 <= 0;
MAC_24 <= 0;
MAC_25 <= 0;
MAC_26 <= 0;
MAC_27 <= 0;
MAC_28 <= 0;
MAC_29 <= 0;
MAC_30 <= 0;
MAC_31 <= 0;
MAC_32 <= 0;
MAC_33 <= 0;
MAC_34 <= 0;
MAC_35 <= 0;
MAC_36 <= 0;
MAC_37 <= 0;
MAC_38 <= 0;
MAC_39 <= 0;
MAC_40 <= 0;
MAC_41 <= 0;
MAC_42 <= 0;
MAC_43 <= 0;
MAC_44 <= 0;
MAC_45 <= 0;
MAC_46 <= 0;
MAC_47 <= 0;
MAC_48 <= 0;
MAC_49 <= 0;
MAC_50 <= 0;
MAC_51 <= 0;
MAC_52 <= 0;
MAC_53 <= 0;
MAC_54 <= 0;
MAC_55 <= 0;
MAC_56 <= 0;
MAC_57 <= 0;
MAC_58 <= 0;
MAC_59 <= 0;
MAC_60 <= 0;
MAC_61 <= 0;
MAC_62 <= 0;
MAC_63 <= 0;
MAC_64 <= 0;
Y <= 0;
end
endtask
task init_reg;
begin
Y <= Y;
MAC_0 <= MAC_0;
MAC_1 <= MAC_1;
MAC_2 <= MAC_2;
MAC_3 <= MAC_3;
MAC_4 <= MAC_4;
MAC_5 <= MAC_5;
MAC_6 <= MAC_6;
MAC_7 <= MAC_7;
MAC_8 <= MAC_8;
MAC_9 <= MAC_9;
MAC_10 <= MAC_10;
MAC_11 <= MAC_11;
MAC_12 <= MAC_12;
MAC_13 <= MAC_13;
MAC_14 <= MAC_14;
MAC_15 <= MAC_15;
MAC_16 <= MAC_16;
MAC_17 <= MAC_17;
MAC_18 <= MAC_18;
MAC_19 <= MAC_19;
MAC_20 <= MAC_20;
MAC_21 <= MAC_21;
MAC_22 <= MAC_22;
MAC_23 <= MAC_23;
MAC_24 <= MAC_24;
MAC_25 <= MAC_25;
MAC_26 <= MAC_26;
MAC_27 <= MAC_27;
MAC_28 <= MAC_28;
MAC_29 <= MAC_29;
MAC_30 <= MAC_30;
MAC_31 <= MAC_31;
MAC_32 <= MAC_32;
MAC_33 <= MAC_33;
MAC_34 <= MAC_34;
MAC_35 <= MAC_35;
MAC_36 <= MAC_36;
MAC_37 <= MAC_37;
MAC_38 <= MAC_38;
MAC_39 <= MAC_39;
MAC_40 <= MAC_40;
MAC_41 <= MAC_41;
MAC_42 <= MAC_42;
MAC_43 <= MAC_43;
MAC_44 <= MAC_44;
MAC_45 <= MAC_45;
MAC_46 <= MAC_46;
MAC_47 <= MAC_47;
MAC_48 <= MAC_48;
MAC_49 <= MAC_49;
MAC_50 <= MAC_50;
MAC_51 <= MAC_51;
MAC_52 <= MAC_52;
MAC_53 <= MAC_53;
MAC_54 <= MAC_54;
MAC_55 <= MAC_55;
MAC_56 <= MAC_56;
MAC_57 <= MAC_57;
MAC_58 <= MAC_58;
MAC_59 <= MAC_59;
MAC_60 <= MAC_60;
MAC_61 <= MAC_61;
MAC_62 <= MAC_62;
MAC_63 <= MAC_63;
MAC_64 <= MAC_64;
end
endtask
endmodule | module radix_fir_65 (clk, reset, X, Y); |
parameter word_size_in = 8;
parameter word_size_out = 23;
input clk, reset;
input signed [word_size_in-1:0] X;
output signed [word_size_out-1:0] Y;
reg [word_size_out-1:0] Y;
wire signed [word_size_in:0] x1;
wire signed [10:0] x3;
wire signed [11:0] x5;
wire signed [11:0] x7;
assign x1 = X;
assign x3 = +(x1<<1)+(x1<<0);
assign x5 = +(x1<<2)+(x1<<0);
assign x7 = +(x1<<3)-(x1<<0);
wire signed [14:0] x_58;
wire signed [17:0] x256;
wire signed [15:0] x95;
wire signed [15:0] x66;
wire signed [15:0] x64;
wire signed [15:0] x67;
wire signed [15:0] x73;
wire signed [15:0] x78;
wire signed [15:0] x83;
wire signed [15:0] x89;
wire signed [15:0] x94;
wire signed [15:0] x99;
wire signed [15:0] x105;
wire signed [15:0] x110;
wire signed [15:0] x116;
wire signed [15:0] x121;
wire signed [15:0] x126;
wire signed [16:0] x130;
wire signed [16:0] x135;
wire signed [16:0] x139;
wire signed [16:0] x144;
wire signed [16:0] x148;
wire signed [16:0] x151;
wire signed [16:0] x155;
wire signed [16:0] x158;
wire signed [16:0] x161;
wire signed [16:0] x163;
wire signed [16:0] x165;
wire signed [16:0] x167;
wire signed [16:0] x168;
wire signed [16:0] x169;
wire signed [16:0] x170;
assign x_58 = +(x3<<1)-(x1<<6);
assign x256 = +(x1<<8);
assign x95 = -(x1<<0)+(x3<<5);
assign x66 = +(x1<<1)+(x1<<6);
assign x64 = +(x1<<6);
assign x67 = +(x3<<0)+(x1<<6);
assign x73 = -(x7<<0)+(x5<<4);
assign x78 = +(x7<<1)+(x1<<6);
assign x83 = +(x3<<0)+(x5<<4);
assign x89 = -(x7<<0)+(x3<<5);
assign x94 = -(x1<<1)+(x3<<5);
assign x99 = +(x3<<0)+(x3<<5);
assign x105 = -(x7<<0)+(x7<<4);
assign x110 = +(x7<<1)+(x3<<5);
assign x116 = -(x3<<2)+(x1<<7);
assign x121 = -(x7<<0)+(x1<<7);
assign x126 = -(x1<<1)+(x1<<7);
assign x130 = +(x1<<1)+(x1<<7);
assign x135 = +(x7<<0)+(x1<<7);
assign x139 = -(x5<<0)-(x7<<4)+(x1<<8);
assign x144 = -(x7<<4)+(x1<<8);
assign x148 = +(x5<<2)+(x1<<7);
assign x151 = +(x7<<0)-(x7<<4)+(x1<<8);
assign x155 = -(x5<<0)+(x5<<5);
assign x158 = -(x1<<1)+(x5<<5);
assign x161 = +(x1<<0)+(x5<<5);
assign x163 = +(x3<<0)+(x5<<5);
assign x165 = +(x5<<0)+(x5<<5);
assign x167 = +(x7<<0)+(x5<<5);
assign x168 = +(x5<<3)+(x1<<7);
assign x169 = -(x7<<0)-(x5<<4)+(x1<<8);
assign x170 = +(x5<<1)+(x5<<5);
wire signed [14:0] SCM_0;
wire signed [17:0] SCM_1;
wire signed [15:0] SCM_2;
wire signed [15:0] SCM_3;
wire signed [15:0] SCM_4;
wire signed [15:0] SCM_5;
wire signed [15:0] SCM_6;
wire signed [15:0] SCM_7;
wire signed [15:0] SCM_8;
wire signed [15:0] SCM_9;
wire signed [15:0] SCM_10;
wire signed [15:0] SCM_11;
wire signed [15:0] SCM_12;
wire signed [15:0] SCM_13;
wire signed [15:0] SCM_14;
wire signed [15:0] SCM_15;
wire signed [15:0] SCM_16;
wire signed [16:0] SCM_17;
wire signed [16:0] SCM_18;
wire signed [16:0] SCM_19;
wire signed [16:0] SCM_20;
wire signed [16:0] SCM_21;
wire signed [16:0] SCM_22;
wire signed [16:0] SCM_23;
wire signed [16:0] SCM_24;
wire signed [16:0] SCM_25;
wire signed [16:0] SCM_26;
wire signed [16:0] SCM_27;
wire signed [16:0] SCM_28;
wire signed [16:0] SCM_29;
wire signed [16:0] SCM_30;
wire signed [16:0] SCM_31;
wire signed [16:0] SCM_32;
wire signed [16:0] SCM_33;
wire signed [16:0] SCM_34;
wire signed [16:0] SCM_35;
wire signed [16:0] SCM_36;
wire signed [16:0] SCM_37;
wire signed [16:0] SCM_38;
wire signed [16:0] SCM_39;
wire signed [16:0] SCM_40;
wire signed [16:0] SCM_41;
wire signed [16:0] SCM_42;
wire signed [16:0] SCM_43;
wire signed [16:0] SCM_44;
wire signed [16:0] SCM_45;
wire signed [16:0] SCM_46;
wire signed [16:0] SCM_47;
wire signed [15:0] SCM_48;
wire signed [15:0] SCM_49;
wire signed [15:0] SCM_50;
wire signed [15:0] SCM_51;
wire signed [15:0] SCM_52;
wire signed [15:0] SCM_53;
wire signed [15:0] SCM_54;
wire signed [15:0] SCM_55;
wire signed [15:0] SCM_56;
wire signed [15:0] SCM_57;
wire signed [15:0] SCM_58;
wire signed [15:0] SCM_59;
wire signed [15:0] SCM_60;
wire signed [15:0] SCM_61;
wire signed [15:0] SCM_62;
wire signed [17:0] SCM_63;
wire signed [14:0] SCM_64;
assign SCM_0 = x_58;
assign SCM_1 = x256;
assign SCM_2 = x95;
assign SCM_3 = x66;
assign SCM_4 = x64;
assign SCM_5 = x67;
assign SCM_6 = x73;
assign SCM_7 = x78;
assign SCM_8 = x83;
assign SCM_9 = x89;
assign SCM_10 = x94;
assign SCM_11 = x99;
assign SCM_12 = x105;
assign SCM_13 = x110;
assign SCM_14 = x116;
assign SCM_15 = x121;
assign SCM_16 = x126;
assign SCM_17 = x130;
assign SCM_18 = x135;
assign SCM_19 = x139;
assign SCM_20 = x144;
assign SCM_21 = x148;
assign SCM_22 = x151;
assign SCM_23 = x155;
assign SCM_24 = x158;
assign SCM_25 = x161;
assign SCM_26 = x163;
assign SCM_27 = x165;
assign SCM_28 = x167;
assign SCM_29 = x168;
assign SCM_30 = x169;
assign SCM_31 = x170;
assign SCM_32 = x170;
assign SCM_33 = x170;
assign SCM_34 = x169;
assign SCM_35 = x168;
assign SCM_36 = x167;
assign SCM_37 = x165;
assign SCM_38 = x163;
assign SCM_39 = x161;
assign SCM_40 = x158;
assign SCM_41 = x155;
assign SCM_42 = x151;
assign SCM_43 = x148;
assign SCM_44 = x144;
assign SCM_45 = x139;
assign SCM_46 = x135;
assign SCM_47 = x130;
assign SCM_48 = x126;
assign SCM_49 = x121;
assign SCM_50 = x116;
assign SCM_51 = x110;
assign SCM_52 = x105;
assign SCM_53 = x99;
assign SCM_54 = x94;
assign SCM_55 = x89;
assign SCM_56 = x83;
assign SCM_57 = x78;
assign SCM_58 = x73;
assign SCM_59 = x67;
assign SCM_60 = x64;
assign SCM_61 = x66;
assign SCM_62 = x95;
assign SCM_63 = x256;
assign SCM_64 = x_58;
reg signed [22:0] MAC_0;
reg signed [21:0] MAC_1;
reg signed [21:0] MAC_2;
reg signed [21:0] MAC_3;
reg signed [21:0] MAC_4;
reg signed [21:0] MAC_5;
reg signed [21:0] MAC_6;
reg signed [21:0] MAC_7;
reg signed [21:0] MAC_8;
reg signed [21:0] MAC_9;
reg signed [21:0] MAC_10;
reg signed [21:0] MAC_11;
reg signed [21:0] MAC_12;
reg signed [21:0] MAC_13;
reg signed [21:0] MAC_14;
reg signed [21:0] MAC_15;
reg signed [21:0] MAC_16;
reg signed [21:0] MAC_17;
reg signed [21:0] MAC_18;
reg signed [21:0] MAC_19;
reg signed [21:0] MAC_20;
reg signed [21:0] MAC_21;
reg signed [21:0] MAC_22;
reg signed [21:0] MAC_23;
reg signed [21:0] MAC_24;
reg signed [21:0] MAC_25;
reg signed [21:0] MAC_26;
reg signed [21:0] MAC_27;
reg signed [21:0] MAC_28;
reg signed [21:0] MAC_29;
reg signed [21:0] MAC_30;
reg signed [21:0] MAC_31;
reg signed [21:0] MAC_32;
reg signed [20:0] MAC_33;
reg signed [20:0] MAC_34;
reg signed [20:0] MAC_35;
reg signed [20:0] MAC_36;
reg signed [20:0] MAC_37;
reg signed [20:0] MAC_38;
reg signed [20:0] MAC_39;
reg signed [20:0] MAC_40;
reg signed [20:0] MAC_41;
reg signed [20:0] MAC_42;
reg signed [20:0] MAC_43;
reg signed [20:0] MAC_44;
reg signed [20:0] MAC_45;
reg signed [19:0] MAC_46;
reg signed [19:0] MAC_47;
reg signed [19:0] MAC_48;
reg signed [19:0] MAC_49;
reg signed [19:0] MAC_50;
reg signed [19:0] MAC_51;
reg signed [19:0] MAC_52;
reg signed [19:0] MAC_53;
reg signed [18:0] MAC_54;
reg signed [18:0] MAC_55;
reg signed [18:0] MAC_56;
reg signed [18:0] MAC_57;
reg signed [18:0] MAC_58;
reg signed [18:0] MAC_59;
reg signed [18:0] MAC_60;
reg signed [17:0] MAC_61;
reg signed [17:0] MAC_62;
reg signed [17:0] MAC_63;
reg signed [14:0] MAC_64;
wire signed [22:0] Y_in;
always @(posedge clk or negedge reset) begin
if(~reset) begin
reset_reg;
end
else begin
init_reg;
Y <= Y_in;
MAC_0 <= MAC_1 + SCM_0;
MAC_1 <= MAC_2 + SCM_1;
MAC_2 <= MAC_3 + SCM_2;
MAC_3 <= MAC_4 + SCM_3;
MAC_4 <= MAC_5 + SCM_4;
MAC_5 <= MAC_6 + SCM_5;
MAC_6 <= MAC_7 + SCM_6;
MAC_7 <= MAC_8 + SCM_7;
MAC_8 <= MAC_9 + SCM_8;
MAC_9 <= MAC_10 + SCM_9;
MAC_10 <= MAC_11 + SCM_10;
MAC_11 <= MAC_12 + SCM_11;
MAC_12 <= MAC_13 + SCM_12;
MAC_13 <= MAC_14 + SCM_13;
MAC_14 <= MAC_15 + SCM_14;
MAC_15 <= MAC_16 + SCM_15;
MAC_16 <= MAC_17 + SCM_16;
MAC_17 <= MAC_18 + SCM_17;
MAC_18 <= MAC_19 + SCM_18;
MAC_19 <= MAC_20 + SCM_19;
MAC_20 <= MAC_21 + SCM_20;
MAC_21 <= MAC_22 + SCM_21;
MAC_22 <= MAC_23 + SCM_22;
MAC_23 <= MAC_24 + SCM_23;
MAC_24 <= MAC_25 + SCM_24;
MAC_25 <= MAC_26 + SCM_25;
MAC_26 <= MAC_27 + SCM_26;
MAC_27 <= MAC_28 + SCM_27;
MAC_28 <= MAC_29 + SCM_28;
MAC_29 <= MAC_30 + SCM_29;
MAC_30 <= MAC_31 + SCM_30;
MAC_31 <= MAC_32 + SCM_31;
MAC_32 <= MAC_33 + SCM_32;
MAC_33 <= MAC_34 + SCM_33;
MAC_34 <= MAC_35 + SCM_34;
MAC_35 <= MAC_36 + SCM_35;
MAC_36 <= MAC_37 + SCM_36;
MAC_37 <= MAC_38 + SCM_37;
MAC_38 <= MAC_39 + SCM_38;
MAC_39 <= MAC_40 + SCM_39;
MAC_40 <= MAC_41 + SCM_40;
MAC_41 <= MAC_42 + SCM_41;
MAC_42 <= MAC_43 + SCM_42;
MAC_43 <= MAC_44 + SCM_43;
MAC_44 <= MAC_45 + SCM_44;
MAC_45 <= MAC_46 + SCM_45;
MAC_46 <= MAC_47 + SCM_46;
MAC_47 <= MAC_48 + SCM_47;
MAC_48 <= MAC_49 + SCM_48;
MAC_49 <= MAC_50 + SCM_49;
MAC_50 <= MAC_51 + SCM_50;
MAC_51 <= MAC_52 + SCM_51;
MAC_52 <= MAC_53 + SCM_52;
MAC_53 <= MAC_54 + SCM_53;
MAC_54 <= MAC_55 + SCM_54;
MAC_55 <= MAC_56 + SCM_55;
MAC_56 <= MAC_57 + SCM_56;
MAC_57 <= MAC_58 + SCM_57;
MAC_58 <= MAC_59 + SCM_58;
MAC_59 <= MAC_60 + SCM_59;
MAC_60 <= MAC_61 + SCM_60;
MAC_61 <= MAC_62 + SCM_61;
MAC_62 <= MAC_63 + SCM_62;
MAC_63 <= MAC_64 + SCM_63;
MAC_64 <= SCM_64;
end
end
assign Y_in = MAC_0;
task reset_reg;
begin
MAC_0 <= 0;
MAC_1 <= 0;
MAC_2 <= 0;
MAC_3 <= 0;
MAC_4 <= 0;
MAC_5 <= 0;
MAC_6 <= 0;
MAC_7 <= 0;
MAC_8 <= 0;
MAC_9 <= 0;
MAC_10 <= 0;
MAC_11 <= 0;
MAC_12 <= 0;
MAC_13 <= 0;
MAC_14 <= 0;
MAC_15 <= 0;
MAC_16 <= 0;
MAC_17 <= 0;
MAC_18 <= 0;
MAC_19 <= 0;
MAC_20 <= 0;
MAC_21 <= 0;
MAC_22 <= 0;
MAC_23 <= 0;
MAC_24 <= 0;
MAC_25 <= 0;
MAC_26 <= 0;
MAC_27 <= 0;
MAC_28 <= 0;
MAC_29 <= 0;
MAC_30 <= 0;
MAC_31 <= 0;
MAC_32 <= 0;
MAC_33 <= 0;
MAC_34 <= 0;
MAC_35 <= 0;
MAC_36 <= 0;
MAC_37 <= 0;
MAC_38 <= 0;
MAC_39 <= 0;
MAC_40 <= 0;
MAC_41 <= 0;
MAC_42 <= 0;
MAC_43 <= 0;
MAC_44 <= 0;
MAC_45 <= 0;
MAC_46 <= 0;
MAC_47 <= 0;
MAC_48 <= 0;
MAC_49 <= 0;
MAC_50 <= 0;
MAC_51 <= 0;
MAC_52 <= 0;
MAC_53 <= 0;
MAC_54 <= 0;
MAC_55 <= 0;
MAC_56 <= 0;
MAC_57 <= 0;
MAC_58 <= 0;
MAC_59 <= 0;
MAC_60 <= 0;
MAC_61 <= 0;
MAC_62 <= 0;
MAC_63 <= 0;
MAC_64 <= 0;
Y <= 0;
end
endtask
task init_reg;
begin
Y <= Y;
MAC_0 <= MAC_0;
MAC_1 <= MAC_1;
MAC_2 <= MAC_2;
MAC_3 <= MAC_3;
MAC_4 <= MAC_4;
MAC_5 <= MAC_5;
MAC_6 <= MAC_6;
MAC_7 <= MAC_7;
MAC_8 <= MAC_8;
MAC_9 <= MAC_9;
MAC_10 <= MAC_10;
MAC_11 <= MAC_11;
MAC_12 <= MAC_12;
MAC_13 <= MAC_13;
MAC_14 <= MAC_14;
MAC_15 <= MAC_15;
MAC_16 <= MAC_16;
MAC_17 <= MAC_17;
MAC_18 <= MAC_18;
MAC_19 <= MAC_19;
MAC_20 <= MAC_20;
MAC_21 <= MAC_21;
MAC_22 <= MAC_22;
MAC_23 <= MAC_23;
MAC_24 <= MAC_24;
MAC_25 <= MAC_25;
MAC_26 <= MAC_26;
MAC_27 <= MAC_27;
MAC_28 <= MAC_28;
MAC_29 <= MAC_29;
MAC_30 <= MAC_30;
MAC_31 <= MAC_31;
MAC_32 <= MAC_32;
MAC_33 <= MAC_33;
MAC_34 <= MAC_34;
MAC_35 <= MAC_35;
MAC_36 <= MAC_36;
MAC_37 <= MAC_37;
MAC_38 <= MAC_38;
MAC_39 <= MAC_39;
MAC_40 <= MAC_40;
MAC_41 <= MAC_41;
MAC_42 <= MAC_42;
MAC_43 <= MAC_43;
MAC_44 <= MAC_44;
MAC_45 <= MAC_45;
MAC_46 <= MAC_46;
MAC_47 <= MAC_47;
MAC_48 <= MAC_48;
MAC_49 <= MAC_49;
MAC_50 <= MAC_50;
MAC_51 <= MAC_51;
MAC_52 <= MAC_52;
MAC_53 <= MAC_53;
MAC_54 <= MAC_54;
MAC_55 <= MAC_55;
MAC_56 <= MAC_56;
MAC_57 <= MAC_57;
MAC_58 <= MAC_58;
MAC_59 <= MAC_59;
MAC_60 <= MAC_60;
MAC_61 <= MAC_61;
MAC_62 <= MAC_62;
MAC_63 <= MAC_63;
MAC_64 <= MAC_64;
end
endtask
endmodule | 29 |
138,753 | data/full_repos/permissive/85291251/ISEprj/DecInterp/src/wave_add.v | 85,291,251 | wave_add.v | v | 51 | 71 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/wave_add.v:32: Cannot find file containing module: 'sin_dds'\nsin_dds i1 (\n^~~~~~~\n ... Looked in:\n data/full_repos/permissive/85291251/ISEprj/DecInterp/src,data/full_repos/permissive/85291251/sin_dds\n data/full_repos/permissive/85291251/ISEprj/DecInterp/src,data/full_repos/permissive/85291251/sin_dds.v\n data/full_repos/permissive/85291251/ISEprj/DecInterp/src,data/full_repos/permissive/85291251/sin_dds.sv\n sin_dds\n sin_dds.v\n sin_dds.sv\n obj_dir/sin_dds\n obj_dir/sin_dds.v\n obj_dir/sin_dds.sv\n%Error: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/wave_add.v:41: Cannot find file containing module: 'sin_dds'\nsin_dds i2 (\n^~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 302,733 | module | module wave_add(clk,rst_n,data_out,data_change);
`define OUT_WIDTH 8
`define ADDR_WIDTH 10
input clk;
input rst_n;
output data_change;
output [`OUT_WIDTH-1:0] data_out;
parameter fword1 = `ADDR_WIDTH'd4,
fword2 = `ADDR_WIDTH'd20,
pword1 = `ADDR_WIDTH'd0,
pword2 = `ADDR_WIDTH'd0,
aword1 = 3'd1,
aword2 = 3'd1;
wire [`OUT_WIDTH-1:0] data_out1;
wire [`OUT_WIDTH-1:0] data_out2;
assign data_out = (data_out1>>aword1) + (data_out2>>aword2);
wire data_change1,data_change2;
sin_dds i1 (
.clk(clk),
.data_change(data_change1),
.data_out(data_out1),
.fword(fword1),
.pword(pword1),
.rst_n(rst_n)
);
sin_dds i2 (
.clk(clk),
.data_change(data_change2),
.data_out(data_out2),
.fword(fword2),
.pword(pword2),
.rst_n(rst_n)
);
assign data_change = data_change1 || data_change2;
endmodule | module wave_add(clk,rst_n,data_out,data_change); |
`define OUT_WIDTH 8
`define ADDR_WIDTH 10
input clk;
input rst_n;
output data_change;
output [`OUT_WIDTH-1:0] data_out;
parameter fword1 = `ADDR_WIDTH'd4,
fword2 = `ADDR_WIDTH'd20,
pword1 = `ADDR_WIDTH'd0,
pword2 = `ADDR_WIDTH'd0,
aword1 = 3'd1,
aword2 = 3'd1;
wire [`OUT_WIDTH-1:0] data_out1;
wire [`OUT_WIDTH-1:0] data_out2;
assign data_out = (data_out1>>aword1) + (data_out2>>aword2);
wire data_change1,data_change2;
sin_dds i1 (
.clk(clk),
.data_change(data_change1),
.data_out(data_out1),
.fword(fword1),
.pword(pword1),
.rst_n(rst_n)
);
sin_dds i2 (
.clk(clk),
.data_change(data_change2),
.data_out(data_out2),
.fword(fword2),
.pword(pword2),
.rst_n(rst_n)
);
assign data_change = data_change1 || data_change2;
endmodule | 29 |
138,754 | data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v | 85,291,251 | hdec_4_Verilog.v | v | 241 | 94 | [] | [] | [] | null | line:153: before: ";" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:35: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'X\' generates 8 bits.\n : ... In instance hdec_4_Verilog\nassign x1 = X;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:36: Operator SHIFTL expects 11 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_4_Verilog\nassign x3 = +(x1<<1)+(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:36: Operator SHIFTL expects 11 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_4_Verilog\nassign x3 = +(x1<<1)+(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:37: Operator SHIFTL expects 12 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_4_Verilog\nassign x5 = +(x1<<2)+(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:37: Operator SHIFTL expects 12 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_4_Verilog\nassign x5 = +(x1<<2)+(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:61: Operator SHIFTL expects 10 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_4_Verilog\nassign x_1 = -(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:63: Operator SHIFTL expects 12 bits on the LHS, but LHS\'s VARREF \'x3\' generates 11 bits.\n : ... In instance hdec_4_Verilog\nassign x6 = +(x3<<1);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:64: Operator SHIFTL expects 13 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance hdec_4_Verilog\nassign x9 = -(x7<<0)+(x1<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:64: Operator SHIFTL expects 13 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_4_Verilog\nassign x9 = -(x7<<0)+(x1<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:65: Operator SHIFTL expects 14 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance hdec_4_Verilog\nassign x_25 = +(x7<<0)-(x1<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:65: Operator SHIFTL expects 14 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_4_Verilog\nassign x_25 = +(x7<<0)-(x1<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:66: Operator SHIFTL expects 15 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance hdec_4_Verilog\nassign x_37 = -(x5<<0)-(x1<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:66: Operator SHIFTL expects 15 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_4_Verilog\nassign x_37 = -(x5<<0)-(x1<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:67: Operator SHIFTL expects 11 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_4_Verilog\nassign x_2 = -(x1<<1);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:68: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance hdec_4_Verilog\nassign x91 = -(x5<<0)+(x3<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:68: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x3\' generates 11 bits.\n : ... In instance hdec_4_Verilog\nassign x91 = -(x5<<0)+(x3<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:69: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance hdec_4_Verilog\nassign x199 = +(x7<<0)+(x3<<6);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:69: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x3\' generates 11 bits.\n : ... In instance hdec_4_Verilog\nassign x199 = +(x7<<0)+(x3<<6);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:70: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_4_Verilog\nassign x255 = -(x1<<0)+(x1<<8);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:70: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_4_Verilog\nassign x255 = -(x1<<0)+(x1<<8);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:71: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance hdec_4_Verilog\nassign x220 = +(x7<<2)+(x3<<6);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:71: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x3\' generates 11 bits.\n : ... In instance hdec_4_Verilog\nassign x220 = +(x7<<2)+(x3<<6);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:72: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance hdec_4_Verilog\nassign x119 = +(x7<<0)+(x7<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:72: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance hdec_4_Verilog\nassign x119 = +(x7<<0)+(x7<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:73: Operator SHIFTL expects 14 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_4_Verilog\nassign x17 = +(x1<<0)+(x1<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:73: Operator SHIFTL expects 14 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_4_Verilog\nassign x17 = +(x1<<0)+(x1<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:74: Operator SHIFTL expects 15 bits on the LHS, but LHS\'s VARREF \'x17\' generates 14 bits.\n : ... In instance hdec_4_Verilog\nassign x_34 = -(x17<<1);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:75: Operator SHIFTL expects 14 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_4_Verilog\nassign x_30 = +(x1<<1)-(x1<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:75: Operator SHIFTL expects 14 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_4_Verilog\nassign x_30 = +(x1<<1)-(x1<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:76: Operator SHIFTL expects 12 bits on the LHS, but LHS\'s VARREF \'x3\' generates 11 bits.\n : ... In instance hdec_4_Verilog\nassign x_6 = -(x3<<1);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:77: Operator SHIFTL expects 13 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_4_Verilog\nassign x8 = +(x1<<3);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:78: Operator SHIFTL expects 12 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_4_Verilog\nassign x7 = +(x1<<3)-(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:78: Operator SHIFTL expects 12 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_4_Verilog\nassign x7 = +(x1<<3)-(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:79: Operator SHIFTL expects 11 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_4_Verilog\nassign x2 = (x1<<1);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:158: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_0\' generates 10 bits.\n : ... In instance hdec_4_Verilog\n MAC_0 <= MAC_1 + SCM_0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:159: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_1\' generates 10 bits.\n : ... In instance hdec_4_Verilog\n MAC_1 <= MAC_2 + SCM_1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:160: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_2\' generates 12 bits.\n : ... In instance hdec_4_Verilog\n MAC_2 <= MAC_3 + SCM_2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:161: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_3\' generates 13 bits.\n : ... In instance hdec_4_Verilog\n MAC_3 <= MAC_4 + SCM_3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:162: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_4\' generates 10 bits.\n : ... In instance hdec_4_Verilog\n MAC_4 <= MAC_5 + SCM_4;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:163: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_5\' generates 14 bits.\n : ... In instance hdec_4_Verilog\n MAC_5 <= MAC_6 + SCM_5;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:164: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_6\' generates 15 bits.\n : ... In instance hdec_4_Verilog\n MAC_6 <= MAC_7 + SCM_6;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:165: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'SCM_7\' generates 11 bits.\n : ... In instance hdec_4_Verilog\n MAC_7 <= MAC_8 + SCM_7;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:166: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'SCM_8\' generates 16 bits.\n : ... In instance hdec_4_Verilog\n MAC_8 <= MAC_9 + SCM_8;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:167: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'SCM_9\' generates 17 bits.\n : ... In instance hdec_4_Verilog\n MAC_9 <= MAC_10 + SCM_9;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:168: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'SCM_10\' generates 17 bits.\n : ... In instance hdec_4_Verilog\n MAC_10 <= MAC_11 + SCM_10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:171: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'SCM_13\' generates 14 bits.\n : ... In instance hdec_4_Verilog\n MAC_13 <= MAC_14 + SCM_13;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:174: Operator ADD expects 14 bits on the RHS, but RHS\'s VARREF \'SCM_16\' generates 12 bits.\n : ... In instance hdec_4_Verilog\n MAC_16 <= MAC_17 + SCM_16;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_4_Verilog.v:176: Operator ADD expects 13 bits on the LHS, but LHS\'s VARREF \'MAC_19\' generates 11 bits.\n : ... In instance hdec_4_Verilog\n MAC_18 <= MAC_19 + SCM_18;\n ^\n%Error: Exiting due to 48 warning(s)\n' | 302,737 | module | module hdec_4_Verilog (clk, reset, X, Y);
parameter word_size_in = 8;
parameter word_size_out = 20;
input clk, reset;
input signed [word_size_in-1:0] X;
output signed [word_size_out-1:0] Y;
reg [word_size_out-1:0] Y;
wire signed [word_size_in:0] x1;
wire signed [10:0] x3;
wire signed [11:0] x5;
assign x1 = X;
assign x3 = +(x1<<1)+(x1<<0);
assign x5 = +(x1<<2)+(x1<<0);
wire signed [9:0] x_1;
wire signed [9:0] x0;
wire signed [11:0] x6;
wire signed [12:0] x9;
wire signed [13:0] x_25;
wire signed [14:0] x_37;
wire signed [10:0] x_2;
wire signed [15:0] x91;
wire signed [16:0] x199;
wire signed [16:0] x255;
wire signed [16:0] x220;
wire signed [15:0] x119;
wire signed [13:0] x17;
wire signed [14:0] x_34;
wire signed [13:0] x_30;
wire signed [11:0] x_6;
wire signed [12:0] x8;
wire signed [11:0] x7;
wire signed [10:0] x2;
assign x_1 = -(x1<<0);
assign x0 = 0;
assign x6 = +(x3<<1);
assign x9 = -(x7<<0)+(x1<<4);
assign x_25 = +(x7<<0)-(x1<<5);
assign x_37 = -(x5<<0)-(x1<<5);
assign x_2 = -(x1<<1);
assign x91 = -(x5<<0)+(x3<<5);
assign x199 = +(x7<<0)+(x3<<6);
assign x255 = -(x1<<0)+(x1<<8);
assign x220 = +(x7<<2)+(x3<<6);
assign x119 = +(x7<<0)+(x7<<4);
assign x17 = +(x1<<0)+(x1<<4);
assign x_34 = -(x17<<1);
assign x_30 = +(x1<<1)-(x1<<5);
assign x_6 = -(x3<<1);
assign x8 = +(x1<<3);
assign x7 = +(x1<<3)-(x1<<0);
assign x2 = (x1<<1);
wire signed [9:0] SCM_0;
wire signed [9:0] SCM_1;
wire signed [11:0] SCM_2;
wire signed [12:0] SCM_3;
wire signed [9:0] SCM_4;
wire signed [13:0] SCM_5;
wire signed [14:0] SCM_6;
wire signed [10:0] SCM_7;
wire signed [15:0] SCM_8;
wire signed [16:0] SCM_9;
wire signed [16:0] SCM_10;
wire signed [16:0] SCM_11;
wire signed [15:0] SCM_12;
wire signed [13:0] SCM_13;
wire signed [14:0] SCM_14;
wire signed [13:0] SCM_15;
wire signed [11:0] SCM_16;
wire signed [12:0] SCM_17;
wire signed [11:0] SCM_18;
wire signed [10:0] SCM_19;
wire signed [9:0] SCM_20;
assign SCM_0 = x_1;
assign SCM_1 = x0;
assign SCM_2 = x6;
assign SCM_3 = x9;
assign SCM_4 = x_1;
assign SCM_5 = x_25;
assign SCM_6 = x_37;
assign SCM_7 = x_2;
assign SCM_8 = x91;
assign SCM_9 = x199;
assign SCM_10 = x255;
assign SCM_11 = x220;
assign SCM_12 = x119;
assign SCM_13 = x17;
assign SCM_14 = x_34;
assign SCM_15 = x_30;
assign SCM_16 = x_6;
assign SCM_17 = x8;
assign SCM_18 = x7;
assign SCM_19 = x2;
assign SCM_20 = x_1;
reg signed [19:0] MAC_0;
reg signed [19:0] MAC_1;
reg signed [19:0] MAC_2;
reg signed [19:0] MAC_3;
reg signed [19:0] MAC_4;
reg signed [19:0] MAC_5;
reg signed [19:0] MAC_6;
reg signed [18:0] MAC_7;
reg signed [18:0] MAC_8;
reg signed [18:0] MAC_9;
reg signed [18:0] MAC_10;
reg signed [17:0] MAC_11;
reg signed [16:0] MAC_12;
reg signed [15:0] MAC_13;
reg signed [15:0] MAC_14;
reg signed [14:0] MAC_15;
reg signed [13:0] MAC_16;
reg signed [13:0] MAC_17;
reg signed [12:0] MAC_18;
reg signed [10:0] MAC_19;
reg signed [9:0] MAC_20;
wire signed [19:0] Y_in;
always @(posedge clk or negedge reset) begin
if(~reset) begin
reset_reg;
end
else begin
init_reg;
Y <= Y_in;
MAC_0 <= MAC_1 + SCM_0;
MAC_1 <= MAC_2 + SCM_1;
MAC_2 <= MAC_3 + SCM_2;
MAC_3 <= MAC_4 + SCM_3;
MAC_4 <= MAC_5 + SCM_4;
MAC_5 <= MAC_6 + SCM_5;
MAC_6 <= MAC_7 + SCM_6;
MAC_7 <= MAC_8 + SCM_7;
MAC_8 <= MAC_9 + SCM_8;
MAC_9 <= MAC_10 + SCM_9;
MAC_10 <= MAC_11 + SCM_10;
MAC_11 <= MAC_12 + SCM_11;
MAC_12 <= MAC_13 + SCM_12;
MAC_13 <= MAC_14 + SCM_13;
MAC_14 <= MAC_15 + SCM_14;
MAC_15 <= MAC_16 + SCM_15;
MAC_16 <= MAC_17 + SCM_16;
MAC_17 <= MAC_18 + SCM_17;
MAC_18 <= MAC_19 + SCM_18;
MAC_19 <= MAC_20 + SCM_19;
MAC_20 <= SCM_20;
end
end
assign Y_in = MAC_0;
task reset_reg;
begin
MAC_0 <= 0;
MAC_1 <= 0;
MAC_2 <= 0;
MAC_3 <= 0;
MAC_4 <= 0;
MAC_5 <= 0;
MAC_6 <= 0;
MAC_7 <= 0;
MAC_8 <= 0;
MAC_9 <= 0;
MAC_10 <= 0;
MAC_11 <= 0;
MAC_12 <= 0;
MAC_13 <= 0;
MAC_14 <= 0;
MAC_15 <= 0;
MAC_16 <= 0;
MAC_17 <= 0;
MAC_18 <= 0;
MAC_19 <= 0;
MAC_20 <= 0;
Y <= 0;
end
endtask
task init_reg;
begin
Y <= Y;
MAC_0 <= MAC_0;
MAC_1 <= MAC_1;
MAC_2 <= MAC_2;
MAC_3 <= MAC_3;
MAC_4 <= MAC_4;
MAC_5 <= MAC_5;
MAC_6 <= MAC_6;
MAC_7 <= MAC_7;
MAC_8 <= MAC_8;
MAC_9 <= MAC_9;
MAC_10 <= MAC_10;
MAC_11 <= MAC_11;
MAC_12 <= MAC_12;
MAC_13 <= MAC_13;
MAC_14 <= MAC_14;
MAC_15 <= MAC_15;
MAC_16 <= MAC_16;
MAC_17 <= MAC_17;
MAC_18 <= MAC_18;
MAC_19 <= MAC_19;
MAC_20 <= MAC_20;
end
endtask
endmodule | module hdec_4_Verilog (clk, reset, X, Y); |
parameter word_size_in = 8;
parameter word_size_out = 20;
input clk, reset;
input signed [word_size_in-1:0] X;
output signed [word_size_out-1:0] Y;
reg [word_size_out-1:0] Y;
wire signed [word_size_in:0] x1;
wire signed [10:0] x3;
wire signed [11:0] x5;
assign x1 = X;
assign x3 = +(x1<<1)+(x1<<0);
assign x5 = +(x1<<2)+(x1<<0);
wire signed [9:0] x_1;
wire signed [9:0] x0;
wire signed [11:0] x6;
wire signed [12:0] x9;
wire signed [13:0] x_25;
wire signed [14:0] x_37;
wire signed [10:0] x_2;
wire signed [15:0] x91;
wire signed [16:0] x199;
wire signed [16:0] x255;
wire signed [16:0] x220;
wire signed [15:0] x119;
wire signed [13:0] x17;
wire signed [14:0] x_34;
wire signed [13:0] x_30;
wire signed [11:0] x_6;
wire signed [12:0] x8;
wire signed [11:0] x7;
wire signed [10:0] x2;
assign x_1 = -(x1<<0);
assign x0 = 0;
assign x6 = +(x3<<1);
assign x9 = -(x7<<0)+(x1<<4);
assign x_25 = +(x7<<0)-(x1<<5);
assign x_37 = -(x5<<0)-(x1<<5);
assign x_2 = -(x1<<1);
assign x91 = -(x5<<0)+(x3<<5);
assign x199 = +(x7<<0)+(x3<<6);
assign x255 = -(x1<<0)+(x1<<8);
assign x220 = +(x7<<2)+(x3<<6);
assign x119 = +(x7<<0)+(x7<<4);
assign x17 = +(x1<<0)+(x1<<4);
assign x_34 = -(x17<<1);
assign x_30 = +(x1<<1)-(x1<<5);
assign x_6 = -(x3<<1);
assign x8 = +(x1<<3);
assign x7 = +(x1<<3)-(x1<<0);
assign x2 = (x1<<1);
wire signed [9:0] SCM_0;
wire signed [9:0] SCM_1;
wire signed [11:0] SCM_2;
wire signed [12:0] SCM_3;
wire signed [9:0] SCM_4;
wire signed [13:0] SCM_5;
wire signed [14:0] SCM_6;
wire signed [10:0] SCM_7;
wire signed [15:0] SCM_8;
wire signed [16:0] SCM_9;
wire signed [16:0] SCM_10;
wire signed [16:0] SCM_11;
wire signed [15:0] SCM_12;
wire signed [13:0] SCM_13;
wire signed [14:0] SCM_14;
wire signed [13:0] SCM_15;
wire signed [11:0] SCM_16;
wire signed [12:0] SCM_17;
wire signed [11:0] SCM_18;
wire signed [10:0] SCM_19;
wire signed [9:0] SCM_20;
assign SCM_0 = x_1;
assign SCM_1 = x0;
assign SCM_2 = x6;
assign SCM_3 = x9;
assign SCM_4 = x_1;
assign SCM_5 = x_25;
assign SCM_6 = x_37;
assign SCM_7 = x_2;
assign SCM_8 = x91;
assign SCM_9 = x199;
assign SCM_10 = x255;
assign SCM_11 = x220;
assign SCM_12 = x119;
assign SCM_13 = x17;
assign SCM_14 = x_34;
assign SCM_15 = x_30;
assign SCM_16 = x_6;
assign SCM_17 = x8;
assign SCM_18 = x7;
assign SCM_19 = x2;
assign SCM_20 = x_1;
reg signed [19:0] MAC_0;
reg signed [19:0] MAC_1;
reg signed [19:0] MAC_2;
reg signed [19:0] MAC_3;
reg signed [19:0] MAC_4;
reg signed [19:0] MAC_5;
reg signed [19:0] MAC_6;
reg signed [18:0] MAC_7;
reg signed [18:0] MAC_8;
reg signed [18:0] MAC_9;
reg signed [18:0] MAC_10;
reg signed [17:0] MAC_11;
reg signed [16:0] MAC_12;
reg signed [15:0] MAC_13;
reg signed [15:0] MAC_14;
reg signed [14:0] MAC_15;
reg signed [13:0] MAC_16;
reg signed [13:0] MAC_17;
reg signed [12:0] MAC_18;
reg signed [10:0] MAC_19;
reg signed [9:0] MAC_20;
wire signed [19:0] Y_in;
always @(posedge clk or negedge reset) begin
if(~reset) begin
reset_reg;
end
else begin
init_reg;
Y <= Y_in;
MAC_0 <= MAC_1 + SCM_0;
MAC_1 <= MAC_2 + SCM_1;
MAC_2 <= MAC_3 + SCM_2;
MAC_3 <= MAC_4 + SCM_3;
MAC_4 <= MAC_5 + SCM_4;
MAC_5 <= MAC_6 + SCM_5;
MAC_6 <= MAC_7 + SCM_6;
MAC_7 <= MAC_8 + SCM_7;
MAC_8 <= MAC_9 + SCM_8;
MAC_9 <= MAC_10 + SCM_9;
MAC_10 <= MAC_11 + SCM_10;
MAC_11 <= MAC_12 + SCM_11;
MAC_12 <= MAC_13 + SCM_12;
MAC_13 <= MAC_14 + SCM_13;
MAC_14 <= MAC_15 + SCM_14;
MAC_15 <= MAC_16 + SCM_15;
MAC_16 <= MAC_17 + SCM_16;
MAC_17 <= MAC_18 + SCM_17;
MAC_18 <= MAC_19 + SCM_18;
MAC_19 <= MAC_20 + SCM_19;
MAC_20 <= SCM_20;
end
end
assign Y_in = MAC_0;
task reset_reg;
begin
MAC_0 <= 0;
MAC_1 <= 0;
MAC_2 <= 0;
MAC_3 <= 0;
MAC_4 <= 0;
MAC_5 <= 0;
MAC_6 <= 0;
MAC_7 <= 0;
MAC_8 <= 0;
MAC_9 <= 0;
MAC_10 <= 0;
MAC_11 <= 0;
MAC_12 <= 0;
MAC_13 <= 0;
MAC_14 <= 0;
MAC_15 <= 0;
MAC_16 <= 0;
MAC_17 <= 0;
MAC_18 <= 0;
MAC_19 <= 0;
MAC_20 <= 0;
Y <= 0;
end
endtask
task init_reg;
begin
Y <= Y;
MAC_0 <= MAC_0;
MAC_1 <= MAC_1;
MAC_2 <= MAC_2;
MAC_3 <= MAC_3;
MAC_4 <= MAC_4;
MAC_5 <= MAC_5;
MAC_6 <= MAC_6;
MAC_7 <= MAC_7;
MAC_8 <= MAC_8;
MAC_9 <= MAC_9;
MAC_10 <= MAC_10;
MAC_11 <= MAC_11;
MAC_12 <= MAC_12;
MAC_13 <= MAC_13;
MAC_14 <= MAC_14;
MAC_15 <= MAC_15;
MAC_16 <= MAC_16;
MAC_17 <= MAC_17;
MAC_18 <= MAC_18;
MAC_19 <= MAC_19;
MAC_20 <= MAC_20;
end
endtask
endmodule | 29 |
138,755 | data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v | 85,291,251 | hdec_7_Verilog.v | v | 239 | 94 | [] | [] | [] | null | line:151: before: ";" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:34: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'X\' generates 8 bits.\n : ... In instance hdec_7_Verilog\nassign x1 = X;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:35: Operator SHIFTL expects 11 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_7_Verilog\nassign x3 = +(x1<<1)+(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:35: Operator SHIFTL expects 11 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_7_Verilog\nassign x3 = +(x1<<1)+(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:59: Operator SHIFTL expects 10 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_7_Verilog\nassign x_1 = -(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:60: Operator SHIFTL expects 11 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_7_Verilog\nassign x2 = +(x1<<1);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:61: Operator SHIFTL expects 13 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_7_Verilog\nassign x8 = +(x1<<3);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:62: Operator SHIFTL expects 12 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_7_Verilog\nassign x7 = +(x1<<3)-(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:62: Operator SHIFTL expects 12 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_7_Verilog\nassign x7 = +(x1<<3)-(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:63: Operator SHIFTL expects 13 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance hdec_7_Verilog\nassign x_9 = +(x7<<0)-(x1<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:63: Operator SHIFTL expects 13 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_7_Verilog\nassign x_9 = +(x7<<0)-(x1<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:64: Operator SHIFTL expects 15 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_7_Verilog\nassign x_33 = -(x1<<0)-(x1<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:64: Operator SHIFTL expects 15 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_7_Verilog\nassign x_33 = -(x1<<0)-(x1<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:65: Operator SHIFTL expects 14 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_7_Verilog\nassign x_31 = +(x1<<0)-(x1<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:65: Operator SHIFTL expects 14 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_7_Verilog\nassign x_31 = +(x1<<0)-(x1<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:66: Operator SHIFTL expects 14 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance hdec_7_Verilog\nassign x27 = -(x5<<0)+(x1<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:66: Operator SHIFTL expects 14 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_7_Verilog\nassign x27 = -(x5<<0)+(x1<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:67: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance hdec_7_Verilog\nassign x133 = +(x5<<0)+(x1<<7);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:67: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_7_Verilog\nassign x133 = +(x5<<0)+(x1<<7);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:68: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance hdec_7_Verilog\nassign x229 = +(x5<<0)+(x7<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:68: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance hdec_7_Verilog\nassign x229 = +(x5<<0)+(x7<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:69: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x3\' generates 11 bits.\n : ... In instance hdec_7_Verilog\nassign x253 = -(x3<<0)+(x1<<8);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:69: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_7_Verilog\nassign x253 = -(x3<<0)+(x1<<8);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:70: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance hdec_7_Verilog\nassign x187 = -(x5<<0)+(x3<<6);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:70: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x3\' generates 11 bits.\n : ... In instance hdec_7_Verilog\nassign x187 = -(x5<<0)+(x3<<6);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:71: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x3\' generates 11 bits.\n : ... In instance hdec_7_Verilog\nassign x77 = -(x3<<0)+(x5<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:71: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance hdec_7_Verilog\nassign x77 = -(x3<<0)+(x5<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:72: Operator SHIFTL expects 15 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance hdec_7_Verilog\nassign x_37 = -(x5<<0)-(x1<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:72: Operator SHIFTL expects 15 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_7_Verilog\nassign x_37 = -(x5<<0)-(x1<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:73: Operator SHIFTL expects 14 bits on the LHS, but LHS\'s VARREF \'x5\' generates 12 bits.\n : ... In instance hdec_7_Verilog\nassign x_22 = +(x5<<1)-(x1<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:73: Operator SHIFTL expects 14 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_7_Verilog\nassign x_22 = +(x5<<1)-(x1<<5);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:74: Operator SHIFTL expects 10 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_7_Verilog\nassign x1t = +(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:75: Operator SHIFTL expects 13 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance hdec_7_Verilog\nassign x9 = -(x7<<0)+(x1<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:75: Operator SHIFTL expects 13 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_7_Verilog\nassign x9 = -(x7<<0)+(x1<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:76: Operator SHIFTL expects 12 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_7_Verilog\nassign x5 = +(x1<<2)+(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:76: Operator SHIFTL expects 12 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance hdec_7_Verilog\nassign x5 = +(x1<<2)+(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:156: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_0\' generates 10 bits.\n : ... In instance hdec_7_Verilog\n MAC_0 <= MAC_1 + SCM_0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:157: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_1\' generates 11 bits.\n : ... In instance hdec_7_Verilog\n MAC_1 <= MAC_2 + SCM_1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:158: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_2\' generates 13 bits.\n : ... In instance hdec_7_Verilog\n MAC_2 <= MAC_3 + SCM_2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:159: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_3\' generates 12 bits.\n : ... In instance hdec_7_Verilog\n MAC_3 <= MAC_4 + SCM_3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:160: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_4\' generates 13 bits.\n : ... In instance hdec_7_Verilog\n MAC_4 <= MAC_5 + SCM_4;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:161: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_5\' generates 15 bits.\n : ... In instance hdec_7_Verilog\n MAC_5 <= MAC_6 + SCM_5;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:162: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'SCM_6\' generates 14 bits.\n : ... In instance hdec_7_Verilog\n MAC_6 <= MAC_7 + SCM_6;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:163: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'SCM_7\' generates 14 bits.\n : ... In instance hdec_7_Verilog\n MAC_7 <= MAC_8 + SCM_7;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:164: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'SCM_8\' generates 17 bits.\n : ... In instance hdec_7_Verilog\n MAC_8 <= MAC_9 + SCM_8;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:165: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'SCM_9\' generates 17 bits.\n : ... In instance hdec_7_Verilog\n MAC_9 <= MAC_10 + SCM_9;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:166: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'SCM_10\' generates 17 bits.\n : ... In instance hdec_7_Verilog\n MAC_10 <= MAC_11 + SCM_10;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:169: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'SCM_13\' generates 13 bits.\n : ... In instance hdec_7_Verilog\n MAC_13 <= MAC_14 + SCM_13;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:172: Operator ADD expects 14 bits on the RHS, but RHS\'s VARREF \'SCM_16\' generates 10 bits.\n : ... In instance hdec_7_Verilog\n MAC_16 <= MAC_17 + SCM_16;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/ISEprj/DecInterp/src/fir/hdec_7_Verilog.v:174: Operator ADD expects 12 bits on the LHS, but LHS\'s VARREF \'MAC_19\' generates 10 bits.\n : ... In instance hdec_7_Verilog\n MAC_18 <= MAC_19 + SCM_18;\n ^\n%Error: Exiting due to 49 warning(s)\n' | 302,740 | module | module hdec_7_Verilog (clk, reset, X, Y);
parameter word_size_in = 8;
parameter word_size_out = 20;
input clk, reset;
input signed [word_size_in-1:0] X;
output signed [word_size_out-1:0] Y;
reg [word_size_out-1:0] Y;
wire signed [word_size_in:0] x1;
wire signed [10:0] x3;
assign x1 = X;
assign x3 = +(x1<<1)+(x1<<0);
wire signed [9:0] x_1;
wire signed [10:0] x2;
wire signed [12:0] x8;
wire signed [11:0] x7;
wire signed [12:0] x_9;
wire signed [14:0] x_33;
wire signed [13:0] x_31;
wire signed [13:0] x27;
wire signed [16:0] x133;
wire signed [16:0] x229;
wire signed [16:0] x253;
wire signed [16:0] x187;
wire signed [15:0] x77;
wire signed [14:0] x_37;
wire signed [13:0] x_22;
wire signed [9:0] x1t;
wire signed [12:0] x9;
wire signed [11:0] x5;
wire signed [9:0] x0;
assign x_1 = -(x1<<0);
assign x2 = +(x1<<1);
assign x8 = +(x1<<3);
assign x7 = +(x1<<3)-(x1<<0);
assign x_9 = +(x7<<0)-(x1<<4);
assign x_33 = -(x1<<0)-(x1<<5);
assign x_31 = +(x1<<0)-(x1<<5);
assign x27 = -(x5<<0)+(x1<<5);
assign x133 = +(x5<<0)+(x1<<7);
assign x229 = +(x5<<0)+(x7<<5);
assign x253 = -(x3<<0)+(x1<<8);
assign x187 = -(x5<<0)+(x3<<6);
assign x77 = -(x3<<0)+(x5<<4);
assign x_37 = -(x5<<0)-(x1<<5);
assign x_22 = +(x5<<1)-(x1<<5);
assign x1t = +(x1<<0);
assign x9 = -(x7<<0)+(x1<<4);
assign x5 = +(x1<<2)+(x1<<0);
assign x0 = 0;
wire signed [9:0] SCM_0;
wire signed [10:0] SCM_1;
wire signed [12:0] SCM_2;
wire signed [11:0] SCM_3;
wire signed [12:0] SCM_4;
wire signed [14:0] SCM_5;
wire signed [13:0] SCM_6;
wire signed [13:0] SCM_7;
wire signed [16:0] SCM_8;
wire signed [16:0] SCM_9;
wire signed [16:0] SCM_10;
wire signed [16:0] SCM_11;
wire signed [15:0] SCM_12;
wire signed [12:0] SCM_13;
wire signed [14:0] SCM_14;
wire signed [13:0] SCM_15;
wire signed [9:0] SCM_16;
wire signed [12:0] SCM_17;
wire signed [11:0] SCM_18;
wire signed [9:0] SCM_19;
wire signed [9:0] SCM_20;
assign SCM_0 = x_1;
assign SCM_1 = x2;
assign SCM_2 = x8;
assign SCM_3 = x7;
assign SCM_4 = x_9;
assign SCM_5 = x_33;
assign SCM_6 = x_31;
assign SCM_7 = x27;
assign SCM_8 = x133;
assign SCM_9 = x229;
assign SCM_10 = x253;
assign SCM_11 = x187;
assign SCM_12 = x77;
assign SCM_13 = x_9;
assign SCM_14 = x_37;
assign SCM_15 = x_22;
assign SCM_16 = x1t;
assign SCM_17 = x9;
assign SCM_18 = x5;
assign SCM_19 = x0;
assign SCM_20 = x_1;
reg signed [19:0] MAC_0;
reg signed [19:0] MAC_1;
reg signed [19:0] MAC_2;
reg signed [19:0] MAC_3;
reg signed [19:0] MAC_4;
reg signed [19:0] MAC_5;
reg signed [18:0] MAC_6;
reg signed [18:0] MAC_7;
reg signed [18:0] MAC_8;
reg signed [18:0] MAC_9;
reg signed [18:0] MAC_10;
reg signed [17:0] MAC_11;
reg signed [16:0] MAC_12;
reg signed [15:0] MAC_13;
reg signed [15:0] MAC_14;
reg signed [14:0] MAC_15;
reg signed [13:0] MAC_16;
reg signed [12:0] MAC_17;
reg signed [11:0] MAC_18;
reg signed [9:0] MAC_19;
reg signed [9:0] MAC_20;
wire signed [19:0] Y_in;
always @(posedge clk or negedge reset) begin
if(~reset) begin
reset_reg;
end
else begin
init_reg;
Y <= Y_in;
MAC_0 <= MAC_1 + SCM_0;
MAC_1 <= MAC_2 + SCM_1;
MAC_2 <= MAC_3 + SCM_2;
MAC_3 <= MAC_4 + SCM_3;
MAC_4 <= MAC_5 + SCM_4;
MAC_5 <= MAC_6 + SCM_5;
MAC_6 <= MAC_7 + SCM_6;
MAC_7 <= MAC_8 + SCM_7;
MAC_8 <= MAC_9 + SCM_8;
MAC_9 <= MAC_10 + SCM_9;
MAC_10 <= MAC_11 + SCM_10;
MAC_11 <= MAC_12 + SCM_11;
MAC_12 <= MAC_13 + SCM_12;
MAC_13 <= MAC_14 + SCM_13;
MAC_14 <= MAC_15 + SCM_14;
MAC_15 <= MAC_16 + SCM_15;
MAC_16 <= MAC_17 + SCM_16;
MAC_17 <= MAC_18 + SCM_17;
MAC_18 <= MAC_19 + SCM_18;
MAC_19 <= MAC_20 + SCM_19;
MAC_20 <= SCM_20;
end
end
assign Y_in = MAC_0;
task reset_reg;
begin
MAC_0 <= 0;
MAC_1 <= 0;
MAC_2 <= 0;
MAC_3 <= 0;
MAC_4 <= 0;
MAC_5 <= 0;
MAC_6 <= 0;
MAC_7 <= 0;
MAC_8 <= 0;
MAC_9 <= 0;
MAC_10 <= 0;
MAC_11 <= 0;
MAC_12 <= 0;
MAC_13 <= 0;
MAC_14 <= 0;
MAC_15 <= 0;
MAC_16 <= 0;
MAC_17 <= 0;
MAC_18 <= 0;
MAC_19 <= 0;
MAC_20 <= 0;
Y <= 0;
end
endtask
task init_reg;
begin
Y <= Y;
MAC_0 <= MAC_0;
MAC_1 <= MAC_1;
MAC_2 <= MAC_2;
MAC_3 <= MAC_3;
MAC_4 <= MAC_4;
MAC_5 <= MAC_5;
MAC_6 <= MAC_6;
MAC_7 <= MAC_7;
MAC_8 <= MAC_8;
MAC_9 <= MAC_9;
MAC_10 <= MAC_10;
MAC_11 <= MAC_11;
MAC_12 <= MAC_12;
MAC_13 <= MAC_13;
MAC_14 <= MAC_14;
MAC_15 <= MAC_15;
MAC_16 <= MAC_16;
MAC_17 <= MAC_17;
MAC_18 <= MAC_18;
MAC_19 <= MAC_19;
MAC_20 <= MAC_20;
end
endtask
endmodule | module hdec_7_Verilog (clk, reset, X, Y); |
parameter word_size_in = 8;
parameter word_size_out = 20;
input clk, reset;
input signed [word_size_in-1:0] X;
output signed [word_size_out-1:0] Y;
reg [word_size_out-1:0] Y;
wire signed [word_size_in:0] x1;
wire signed [10:0] x3;
assign x1 = X;
assign x3 = +(x1<<1)+(x1<<0);
wire signed [9:0] x_1;
wire signed [10:0] x2;
wire signed [12:0] x8;
wire signed [11:0] x7;
wire signed [12:0] x_9;
wire signed [14:0] x_33;
wire signed [13:0] x_31;
wire signed [13:0] x27;
wire signed [16:0] x133;
wire signed [16:0] x229;
wire signed [16:0] x253;
wire signed [16:0] x187;
wire signed [15:0] x77;
wire signed [14:0] x_37;
wire signed [13:0] x_22;
wire signed [9:0] x1t;
wire signed [12:0] x9;
wire signed [11:0] x5;
wire signed [9:0] x0;
assign x_1 = -(x1<<0);
assign x2 = +(x1<<1);
assign x8 = +(x1<<3);
assign x7 = +(x1<<3)-(x1<<0);
assign x_9 = +(x7<<0)-(x1<<4);
assign x_33 = -(x1<<0)-(x1<<5);
assign x_31 = +(x1<<0)-(x1<<5);
assign x27 = -(x5<<0)+(x1<<5);
assign x133 = +(x5<<0)+(x1<<7);
assign x229 = +(x5<<0)+(x7<<5);
assign x253 = -(x3<<0)+(x1<<8);
assign x187 = -(x5<<0)+(x3<<6);
assign x77 = -(x3<<0)+(x5<<4);
assign x_37 = -(x5<<0)-(x1<<5);
assign x_22 = +(x5<<1)-(x1<<5);
assign x1t = +(x1<<0);
assign x9 = -(x7<<0)+(x1<<4);
assign x5 = +(x1<<2)+(x1<<0);
assign x0 = 0;
wire signed [9:0] SCM_0;
wire signed [10:0] SCM_1;
wire signed [12:0] SCM_2;
wire signed [11:0] SCM_3;
wire signed [12:0] SCM_4;
wire signed [14:0] SCM_5;
wire signed [13:0] SCM_6;
wire signed [13:0] SCM_7;
wire signed [16:0] SCM_8;
wire signed [16:0] SCM_9;
wire signed [16:0] SCM_10;
wire signed [16:0] SCM_11;
wire signed [15:0] SCM_12;
wire signed [12:0] SCM_13;
wire signed [14:0] SCM_14;
wire signed [13:0] SCM_15;
wire signed [9:0] SCM_16;
wire signed [12:0] SCM_17;
wire signed [11:0] SCM_18;
wire signed [9:0] SCM_19;
wire signed [9:0] SCM_20;
assign SCM_0 = x_1;
assign SCM_1 = x2;
assign SCM_2 = x8;
assign SCM_3 = x7;
assign SCM_4 = x_9;
assign SCM_5 = x_33;
assign SCM_6 = x_31;
assign SCM_7 = x27;
assign SCM_8 = x133;
assign SCM_9 = x229;
assign SCM_10 = x253;
assign SCM_11 = x187;
assign SCM_12 = x77;
assign SCM_13 = x_9;
assign SCM_14 = x_37;
assign SCM_15 = x_22;
assign SCM_16 = x1t;
assign SCM_17 = x9;
assign SCM_18 = x5;
assign SCM_19 = x0;
assign SCM_20 = x_1;
reg signed [19:0] MAC_0;
reg signed [19:0] MAC_1;
reg signed [19:0] MAC_2;
reg signed [19:0] MAC_3;
reg signed [19:0] MAC_4;
reg signed [19:0] MAC_5;
reg signed [18:0] MAC_6;
reg signed [18:0] MAC_7;
reg signed [18:0] MAC_8;
reg signed [18:0] MAC_9;
reg signed [18:0] MAC_10;
reg signed [17:0] MAC_11;
reg signed [16:0] MAC_12;
reg signed [15:0] MAC_13;
reg signed [15:0] MAC_14;
reg signed [14:0] MAC_15;
reg signed [13:0] MAC_16;
reg signed [12:0] MAC_17;
reg signed [11:0] MAC_18;
reg signed [9:0] MAC_19;
reg signed [9:0] MAC_20;
wire signed [19:0] Y_in;
always @(posedge clk or negedge reset) begin
if(~reset) begin
reset_reg;
end
else begin
init_reg;
Y <= Y_in;
MAC_0 <= MAC_1 + SCM_0;
MAC_1 <= MAC_2 + SCM_1;
MAC_2 <= MAC_3 + SCM_2;
MAC_3 <= MAC_4 + SCM_3;
MAC_4 <= MAC_5 + SCM_4;
MAC_5 <= MAC_6 + SCM_5;
MAC_6 <= MAC_7 + SCM_6;
MAC_7 <= MAC_8 + SCM_7;
MAC_8 <= MAC_9 + SCM_8;
MAC_9 <= MAC_10 + SCM_9;
MAC_10 <= MAC_11 + SCM_10;
MAC_11 <= MAC_12 + SCM_11;
MAC_12 <= MAC_13 + SCM_12;
MAC_13 <= MAC_14 + SCM_13;
MAC_14 <= MAC_15 + SCM_14;
MAC_15 <= MAC_16 + SCM_15;
MAC_16 <= MAC_17 + SCM_16;
MAC_17 <= MAC_18 + SCM_17;
MAC_18 <= MAC_19 + SCM_18;
MAC_19 <= MAC_20 + SCM_19;
MAC_20 <= SCM_20;
end
end
assign Y_in = MAC_0;
task reset_reg;
begin
MAC_0 <= 0;
MAC_1 <= 0;
MAC_2 <= 0;
MAC_3 <= 0;
MAC_4 <= 0;
MAC_5 <= 0;
MAC_6 <= 0;
MAC_7 <= 0;
MAC_8 <= 0;
MAC_9 <= 0;
MAC_10 <= 0;
MAC_11 <= 0;
MAC_12 <= 0;
MAC_13 <= 0;
MAC_14 <= 0;
MAC_15 <= 0;
MAC_16 <= 0;
MAC_17 <= 0;
MAC_18 <= 0;
MAC_19 <= 0;
MAC_20 <= 0;
Y <= 0;
end
endtask
task init_reg;
begin
Y <= Y;
MAC_0 <= MAC_0;
MAC_1 <= MAC_1;
MAC_2 <= MAC_2;
MAC_3 <= MAC_3;
MAC_4 <= MAC_4;
MAC_5 <= MAC_5;
MAC_6 <= MAC_6;
MAC_7 <= MAC_7;
MAC_8 <= MAC_8;
MAC_9 <= MAC_9;
MAC_10 <= MAC_10;
MAC_11 <= MAC_11;
MAC_12 <= MAC_12;
MAC_13 <= MAC_13;
MAC_14 <= MAC_14;
MAC_15 <= MAC_15;
MAC_16 <= MAC_16;
MAC_17 <= MAC_17;
MAC_18 <= MAC_18;
MAC_19 <= MAC_19;
MAC_20 <= MAC_20;
end
endtask
endmodule | 29 |
138,757 | data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v | 85,291,251 | hdec_5_Verilog.v | v | 218 | 94 | [] | [] | [] | null | line:130: before: ";" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:32: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'X\' generates 8 bits.\n : ... In instance radix_fir_21\nassign x1 = X;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:47: Operator SHIFTL expects 10 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_21\nassign x_1 = -(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:49: Operator SHIFTL expects 12 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_21\nassign x7 = +(x1<<3)-(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:49: Operator SHIFTL expects 12 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_21\nassign x7 = +(x1<<3)-(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:50: Operator SHIFTL expects 13 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance radix_fir_21\nassign x9 = -(x7<<0)+(x1<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:50: Operator SHIFTL expects 13 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_21\nassign x9 = -(x7<<0)+(x1<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:51: Operator SHIFTL expects 12 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_21\nassign x_4 = -(x1<<2);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:52: Operator SHIFTL expects 14 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance radix_fir_21\nassign x_28 = -(x7<<2);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:53: Operator SHIFTL expects 15 bits on the LHS, but LHS\'s VARREF \'x9\' generates 13 bits.\n : ... In instance radix_fir_21\nassign x_36 = -(x9<<2);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:54: Operator SHIFTL expects 12 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_21\nassign x7 = +(x1<<3)-(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:54: Operator SHIFTL expects 12 bits on the LHS, but LHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_21\nassign x7 = +(x1<<3)-(x1<<0);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:55: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance radix_fir_21\nassign x105 = -(x7<<0)+(x7<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:55: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'x7\' generates 12 bits.\n : ... In instance radix_fir_21\nassign x105 = -(x7<<0)+(x7<<4);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:56: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'x105\' generates 16 bits.\n : ... In instance radix_fir_21\nassign x210 = +(x105<<1);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:82: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_21\nassign SCM_1 = x1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:100: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'x1\' generates 9 bits.\n : ... In instance radix_fir_21\nassign SCM_19 = x1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:135: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_0\' generates 10 bits.\n : ... In instance radix_fir_21\n MAC_0 <= MAC_1 + SCM_0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:136: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_1\' generates 10 bits.\n : ... In instance radix_fir_21\n MAC_1 <= MAC_2 + SCM_1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:137: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_2\' generates 12 bits.\n : ... In instance radix_fir_21\n MAC_2 <= MAC_3 + SCM_2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:138: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_3\' generates 13 bits.\n : ... In instance radix_fir_21\n MAC_3 <= MAC_4 + SCM_3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:139: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_4\' generates 12 bits.\n : ... In instance radix_fir_21\n MAC_4 <= MAC_5 + SCM_4;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:140: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'SCM_5\' generates 14 bits.\n : ... In instance radix_fir_21\n MAC_5 <= MAC_6 + SCM_5;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:141: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'SCM_6\' generates 15 bits.\n : ... In instance radix_fir_21\n MAC_6 <= MAC_7 + SCM_6;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:142: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'SCM_7\' generates 12 bits.\n : ... In instance radix_fir_21\n MAC_7 <= MAC_8 + SCM_7;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:143: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'SCM_8\' generates 16 bits.\n : ... In instance radix_fir_21\n MAC_8 <= MAC_9 + SCM_8;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:144: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'SCM_9\' generates 17 bits.\n : ... In instance radix_fir_21\n MAC_9 <= MAC_10 + SCM_9;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:148: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'SCM_13\' generates 12 bits.\n : ... In instance radix_fir_21\n MAC_13 <= MAC_14 + SCM_13;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:151: Operator ADD expects 14 bits on the RHS, but RHS\'s VARREF \'SCM_16\' generates 12 bits.\n : ... In instance radix_fir_21\n MAC_16 <= MAC_17 + SCM_16;\n ^\n%Warning-WIDTH: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:153: Operator ADD expects 13 bits on the LHS, but LHS\'s VARREF \'MAC_19\' generates 11 bits.\n : ... In instance radix_fir_21\n MAC_18 <= MAC_19 + SCM_18;\n ^\n%Error: data/full_repos/permissive/85291251/SimAssitant/FIR_dec/hdec_5_Verilog.v:48: Wire inputs its own output, creating circular logic (wire x=x)\n : ... In instance radix_fir_21\nassign x1 = +(x1<<0);\n ^\n%Error: Exiting due to 1 error(s), 29 warning(s)\n' | 302,747 | module | module radix_fir_21 (clk, reset, X, Y);
parameter word_size_in = 8;
parameter word_size_out = 20;
input clk, reset;
input signed [word_size_in-1:0] X;
output signed [word_size_out-1:0] Y;
reg [word_size_out-1:0] Y;
wire signed [word_size_in:0] x1;
assign x1 = X;
wire signed [9:0] x_1;
wire signed [9:0] x1;
wire signed [11:0] x7;
wire signed [12:0] x9;
wire signed [11:0] x_4;
wire signed [13:0] x_28;
wire signed [14:0] x_36;
wire signed [15:0] x105;
wire signed [16:0] x210;
wire signed [17:0] x256;
assign x_1 = -(x1<<0);
assign x1 = +(x1<<0);
assign x7 = +(x1<<3)-(x1<<0);
assign x9 = -(x7<<0)+(x1<<4);
assign x_4 = -(x1<<2);
assign x_28 = -(x7<<2);
assign x_36 = -(x9<<2);
assign x7 = +(x1<<3)-(x1<<0);
assign x105 = -(x7<<0)+(x7<<4);
assign x210 = +(x105<<1);
wire signed [9:0] SCM_0;
wire signed [9:0] SCM_1;
wire signed [11:0] SCM_2;
wire signed [12:0] SCM_3;
wire signed [11:0] SCM_4;
wire signed [13:0] SCM_5;
wire signed [14:0] SCM_6;
wire signed [11:0] SCM_7;
wire signed [15:0] SCM_8;
wire signed [16:0] SCM_9;
wire signed [17:0] SCM_10;
wire signed [16:0] SCM_11;
wire signed [15:0] SCM_12;
wire signed [11:0] SCM_13;
wire signed [14:0] SCM_14;
wire signed [13:0] SCM_15;
wire signed [11:0] SCM_16;
wire signed [12:0] SCM_17;
wire signed [11:0] SCM_18;
wire signed [9:0] SCM_19;
wire signed [9:0] SCM_20;
assign SCM_0 = x_1;
assign SCM_1 = x1;
assign SCM_2 = x7;
assign SCM_3 = x9;
assign SCM_4 = x_4;
assign SCM_5 = x_28;
assign SCM_6 = x_36;
assign SCM_7 = x7;
assign SCM_8 = x105;
assign SCM_9 = x210;
assign SCM_10 = x256;
assign SCM_11 = x210;
assign SCM_12 = x105;
assign SCM_13 = x7;
assign SCM_14 = x_36;
assign SCM_15 = x_28;
assign SCM_16 = x_4;
assign SCM_17 = x9;
assign SCM_18 = x7;
assign SCM_19 = x1;
assign SCM_20 = x_1;
reg signed [19:0] MAC_0;
reg signed [19:0] MAC_1;
reg signed [19:0] MAC_2;
reg signed [19:0] MAC_3;
reg signed [19:0] MAC_4;
reg signed [19:0] MAC_5;
reg signed [18:0] MAC_6;
reg signed [18:0] MAC_7;
reg signed [18:0] MAC_8;
reg signed [18:0] MAC_9;
reg signed [18:0] MAC_10;
reg signed [17:0] MAC_11;
reg signed [16:0] MAC_12;
reg signed [15:0] MAC_13;
reg signed [15:0] MAC_14;
reg signed [14:0] MAC_15;
reg signed [13:0] MAC_16;
reg signed [13:0] MAC_17;
reg signed [12:0] MAC_18;
reg signed [10:0] MAC_19;
reg signed [9:0] MAC_20;
wire signed [19:0] Y_in;
always @(posedge clk or negedge reset) begin
if(~reset) begin
reset_reg;
end
else begin
init_reg;
Y <= Y_in;
MAC_0 <= MAC_1 + SCM_0;
MAC_1 <= MAC_2 + SCM_1;
MAC_2 <= MAC_3 + SCM_2;
MAC_3 <= MAC_4 + SCM_3;
MAC_4 <= MAC_5 + SCM_4;
MAC_5 <= MAC_6 + SCM_5;
MAC_6 <= MAC_7 + SCM_6;
MAC_7 <= MAC_8 + SCM_7;
MAC_8 <= MAC_9 + SCM_8;
MAC_9 <= MAC_10 + SCM_9;
MAC_10 <= MAC_11 + SCM_10;
MAC_11 <= MAC_12 + SCM_11;
MAC_12 <= MAC_13 + SCM_12;
MAC_13 <= MAC_14 + SCM_13;
MAC_14 <= MAC_15 + SCM_14;
MAC_15 <= MAC_16 + SCM_15;
MAC_16 <= MAC_17 + SCM_16;
MAC_17 <= MAC_18 + SCM_17;
MAC_18 <= MAC_19 + SCM_18;
MAC_19 <= MAC_20 + SCM_19;
MAC_20 <= SCM_20;
end
end
assign Y_in = MAC_0;
task reset_reg;
begin
MAC_0 <= 0;
MAC_1 <= 0;
MAC_2 <= 0;
MAC_3 <= 0;
MAC_4 <= 0;
MAC_5 <= 0;
MAC_6 <= 0;
MAC_7 <= 0;
MAC_8 <= 0;
MAC_9 <= 0;
MAC_10 <= 0;
MAC_11 <= 0;
MAC_12 <= 0;
MAC_13 <= 0;
MAC_14 <= 0;
MAC_15 <= 0;
MAC_16 <= 0;
MAC_17 <= 0;
MAC_18 <= 0;
MAC_19 <= 0;
MAC_20 <= 0;
Y <= 0;
end
endtask
task init_reg;
begin
Y <= Y;
MAC_0 <= MAC_0;
MAC_1 <= MAC_1;
MAC_2 <= MAC_2;
MAC_3 <= MAC_3;
MAC_4 <= MAC_4;
MAC_5 <= MAC_5;
MAC_6 <= MAC_6;
MAC_7 <= MAC_7;
MAC_8 <= MAC_8;
MAC_9 <= MAC_9;
MAC_10 <= MAC_10;
MAC_11 <= MAC_11;
MAC_12 <= MAC_12;
MAC_13 <= MAC_13;
MAC_14 <= MAC_14;
MAC_15 <= MAC_15;
MAC_16 <= MAC_16;
MAC_17 <= MAC_17;
MAC_18 <= MAC_18;
MAC_19 <= MAC_19;
MAC_20 <= MAC_20;
end
endtask
endmodule | module radix_fir_21 (clk, reset, X, Y); |
parameter word_size_in = 8;
parameter word_size_out = 20;
input clk, reset;
input signed [word_size_in-1:0] X;
output signed [word_size_out-1:0] Y;
reg [word_size_out-1:0] Y;
wire signed [word_size_in:0] x1;
assign x1 = X;
wire signed [9:0] x_1;
wire signed [9:0] x1;
wire signed [11:0] x7;
wire signed [12:0] x9;
wire signed [11:0] x_4;
wire signed [13:0] x_28;
wire signed [14:0] x_36;
wire signed [15:0] x105;
wire signed [16:0] x210;
wire signed [17:0] x256;
assign x_1 = -(x1<<0);
assign x1 = +(x1<<0);
assign x7 = +(x1<<3)-(x1<<0);
assign x9 = -(x7<<0)+(x1<<4);
assign x_4 = -(x1<<2);
assign x_28 = -(x7<<2);
assign x_36 = -(x9<<2);
assign x7 = +(x1<<3)-(x1<<0);
assign x105 = -(x7<<0)+(x7<<4);
assign x210 = +(x105<<1);
wire signed [9:0] SCM_0;
wire signed [9:0] SCM_1;
wire signed [11:0] SCM_2;
wire signed [12:0] SCM_3;
wire signed [11:0] SCM_4;
wire signed [13:0] SCM_5;
wire signed [14:0] SCM_6;
wire signed [11:0] SCM_7;
wire signed [15:0] SCM_8;
wire signed [16:0] SCM_9;
wire signed [17:0] SCM_10;
wire signed [16:0] SCM_11;
wire signed [15:0] SCM_12;
wire signed [11:0] SCM_13;
wire signed [14:0] SCM_14;
wire signed [13:0] SCM_15;
wire signed [11:0] SCM_16;
wire signed [12:0] SCM_17;
wire signed [11:0] SCM_18;
wire signed [9:0] SCM_19;
wire signed [9:0] SCM_20;
assign SCM_0 = x_1;
assign SCM_1 = x1;
assign SCM_2 = x7;
assign SCM_3 = x9;
assign SCM_4 = x_4;
assign SCM_5 = x_28;
assign SCM_6 = x_36;
assign SCM_7 = x7;
assign SCM_8 = x105;
assign SCM_9 = x210;
assign SCM_10 = x256;
assign SCM_11 = x210;
assign SCM_12 = x105;
assign SCM_13 = x7;
assign SCM_14 = x_36;
assign SCM_15 = x_28;
assign SCM_16 = x_4;
assign SCM_17 = x9;
assign SCM_18 = x7;
assign SCM_19 = x1;
assign SCM_20 = x_1;
reg signed [19:0] MAC_0;
reg signed [19:0] MAC_1;
reg signed [19:0] MAC_2;
reg signed [19:0] MAC_3;
reg signed [19:0] MAC_4;
reg signed [19:0] MAC_5;
reg signed [18:0] MAC_6;
reg signed [18:0] MAC_7;
reg signed [18:0] MAC_8;
reg signed [18:0] MAC_9;
reg signed [18:0] MAC_10;
reg signed [17:0] MAC_11;
reg signed [16:0] MAC_12;
reg signed [15:0] MAC_13;
reg signed [15:0] MAC_14;
reg signed [14:0] MAC_15;
reg signed [13:0] MAC_16;
reg signed [13:0] MAC_17;
reg signed [12:0] MAC_18;
reg signed [10:0] MAC_19;
reg signed [9:0] MAC_20;
wire signed [19:0] Y_in;
always @(posedge clk or negedge reset) begin
if(~reset) begin
reset_reg;
end
else begin
init_reg;
Y <= Y_in;
MAC_0 <= MAC_1 + SCM_0;
MAC_1 <= MAC_2 + SCM_1;
MAC_2 <= MAC_3 + SCM_2;
MAC_3 <= MAC_4 + SCM_3;
MAC_4 <= MAC_5 + SCM_4;
MAC_5 <= MAC_6 + SCM_5;
MAC_6 <= MAC_7 + SCM_6;
MAC_7 <= MAC_8 + SCM_7;
MAC_8 <= MAC_9 + SCM_8;
MAC_9 <= MAC_10 + SCM_9;
MAC_10 <= MAC_11 + SCM_10;
MAC_11 <= MAC_12 + SCM_11;
MAC_12 <= MAC_13 + SCM_12;
MAC_13 <= MAC_14 + SCM_13;
MAC_14 <= MAC_15 + SCM_14;
MAC_15 <= MAC_16 + SCM_15;
MAC_16 <= MAC_17 + SCM_16;
MAC_17 <= MAC_18 + SCM_17;
MAC_18 <= MAC_19 + SCM_18;
MAC_19 <= MAC_20 + SCM_19;
MAC_20 <= SCM_20;
end
end
assign Y_in = MAC_0;
task reset_reg;
begin
MAC_0 <= 0;
MAC_1 <= 0;
MAC_2 <= 0;
MAC_3 <= 0;
MAC_4 <= 0;
MAC_5 <= 0;
MAC_6 <= 0;
MAC_7 <= 0;
MAC_8 <= 0;
MAC_9 <= 0;
MAC_10 <= 0;
MAC_11 <= 0;
MAC_12 <= 0;
MAC_13 <= 0;
MAC_14 <= 0;
MAC_15 <= 0;
MAC_16 <= 0;
MAC_17 <= 0;
MAC_18 <= 0;
MAC_19 <= 0;
MAC_20 <= 0;
Y <= 0;
end
endtask
task init_reg;
begin
Y <= Y;
MAC_0 <= MAC_0;
MAC_1 <= MAC_1;
MAC_2 <= MAC_2;
MAC_3 <= MAC_3;
MAC_4 <= MAC_4;
MAC_5 <= MAC_5;
MAC_6 <= MAC_6;
MAC_7 <= MAC_7;
MAC_8 <= MAC_8;
MAC_9 <= MAC_9;
MAC_10 <= MAC_10;
MAC_11 <= MAC_11;
MAC_12 <= MAC_12;
MAC_13 <= MAC_13;
MAC_14 <= MAC_14;
MAC_15 <= MAC_15;
MAC_16 <= MAC_16;
MAC_17 <= MAC_17;
MAC_18 <= MAC_18;
MAC_19 <= MAC_19;
MAC_20 <= MAC_20;
end
endtask
endmodule | 29 |
138,758 | data/full_repos/permissive/85417887/ALU16.v | 85,417,887 | ALU16.v | v | 97 | 132 | [] | [] | [] | null | line:21: before: "primitive" | null | 1: b"%Error: data/full_repos/permissive/85417887/ALU16.v:64: Cannot find file containing module: 'Full_Adder'\n Full_Adder f(A[0],in[0],Cin[0],S[0],Cout[0]); \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85417887,data/full_repos/permissive/85417887/Full_Adder\n data/full_repos/permissive/85417887,data/full_repos/permissive/85417887/Full_Adder.v\n data/full_repos/permissive/85417887,data/full_repos/permissive/85417887/Full_Adder.sv\n Full_Adder\n Full_Adder.v\n Full_Adder.sv\n obj_dir/Full_Adder\n obj_dir/Full_Adder.v\n obj_dir/Full_Adder.sv\n%Error: data/full_repos/permissive/85417887/ALU16.v:72: Cannot find file containing module: 'Full_Adder'\n Full_Adder f(A[i],in[i],Cin[i],S[i],Cout[i]); \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/85417887/ALU16.v:79: Cannot find file containing module: 'Full_Adder'\n Full_Adder f2(A[15],in[15],Cin[15],S[15],Cout[15]); \n ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 302,769 | module | module ALU16(
input [15:0] A,
input [15:0] B,
input [3:0] sel,
output [15:0] out,
output N,
output L,
output Z,
output C,
output F
);
wire [15:0] Cin,Cout , in , S;
MUX2 m21_1(in[0],~B[0],B[0],sel[0]);
MUX4 m4(Cin[0],B[0],sel[0],1'b1,1'b0,sel[2],sel[1]);
Full_Adder f(A[0],in[0],Cin[0],S[0],Cout[0]);
MUX2 m21_2(out[0],Cout[0],S[0],sel[3]);
generate
genvar i;
for (i=1; i < 15; i=i+1) begin: r
MUX2 m2_1(in[i],~B[i],B[i],sel[0]);
MUX4 m4(Cin[i],B[i],Cout[i-1],1'b1,1'b0,sel[2],sel[1]);
Full_Adder f(A[i],in[i],Cin[i],S[i],Cout[i]);
MUX2 m2_2(out[i],Cout[i],S[i],sel[3]);
end
endgenerate
MUX2 m22_1(in[15],~B[15],B[15],sel[0]);
MUX4 m24(Cin[15],B[15],Cout[14],1'b1,1'b0,sel[2],sel[1]);
Full_Adder f2(A[15],in[15],Cin[15],S[15],Cout[15]);
MUX2 m22_2(out[15],Cout[15],S[15],sel[3]);
assign Z = ~(S[0] | S[1] | S[2] | S[3] | S[4] | S[5] | S[6] | S[7] | S[8] | S[9] | S[10] | S[11] | S[12] | S[13] | S[14] | S[15]);
MUX2 m(C,~Cout[15],Cout[15],sel[0]);
assign F = Cin[15] ^ Cout[15];
assign L = ~Cout[15] ;
assign N = S[15] ^ Cout[15] ^Cin[15] ;
endmodule | module ALU16(
input [15:0] A,
input [15:0] B,
input [3:0] sel,
output [15:0] out,
output N,
output L,
output Z,
output C,
output F
); |
wire [15:0] Cin,Cout , in , S;
MUX2 m21_1(in[0],~B[0],B[0],sel[0]);
MUX4 m4(Cin[0],B[0],sel[0],1'b1,1'b0,sel[2],sel[1]);
Full_Adder f(A[0],in[0],Cin[0],S[0],Cout[0]);
MUX2 m21_2(out[0],Cout[0],S[0],sel[3]);
generate
genvar i;
for (i=1; i < 15; i=i+1) begin: r
MUX2 m2_1(in[i],~B[i],B[i],sel[0]);
MUX4 m4(Cin[i],B[i],Cout[i-1],1'b1,1'b0,sel[2],sel[1]);
Full_Adder f(A[i],in[i],Cin[i],S[i],Cout[i]);
MUX2 m2_2(out[i],Cout[i],S[i],sel[3]);
end
endgenerate
MUX2 m22_1(in[15],~B[15],B[15],sel[0]);
MUX4 m24(Cin[15],B[15],Cout[14],1'b1,1'b0,sel[2],sel[1]);
Full_Adder f2(A[15],in[15],Cin[15],S[15],Cout[15]);
MUX2 m22_2(out[15],Cout[15],S[15],sel[3]);
assign Z = ~(S[0] | S[1] | S[2] | S[3] | S[4] | S[5] | S[6] | S[7] | S[8] | S[9] | S[10] | S[11] | S[12] | S[13] | S[14] | S[15]);
MUX2 m(C,~Cout[15],Cout[15],sel[0]);
assign F = Cin[15] ^ Cout[15];
assign L = ~Cout[15] ;
assign N = S[15] ^ Cout[15] ^Cin[15] ;
endmodule | 0 |
138,759 | data/full_repos/permissive/85417887/Demux16.v | 85,417,887 | Demux16.v | v | 52 | 83 | [] | [] | [] | [(22, 51)] | null | data/verilator_xmls/58979cdc-0f17-4be9-8d89-ec817a366745.xml | null | 302,770 | module | module Demux16(
input in,
input [3:0] sel,
output [15:0] out
);
wire w0,w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15 ;
assign #8 out[0] = ~sel[3] & ~sel[2] & ~sel[1] & ~sel[0] & in ;
assign #8 out[1] = ~sel[3] & ~sel[2] & ~sel[1] & sel[0] & in ;
assign #8 out[2] = ~sel[3] & ~sel[2] & sel[1] & ~sel[0] & in ;
assign #8 out[3] = ~sel[3] & ~sel[2] & sel[1] & sel[0] & in ;
assign #8 out[4] = ~sel[3] & sel[2] & ~sel[1] & ~sel[0] & in ;
assign #8 out[5] = ~sel[3] & sel[2] & ~sel[1] & sel[0] & in ;
assign #8 out[6] = ~sel[3] & sel[2] & sel[1] & ~sel[0] & in ;
assign #8 out[7] = ~sel[3] & sel[2] & sel[1] & sel[0] & in ;
assign #8 out[8] = sel[3] & ~sel[2] & ~sel[1] & ~sel[0] & in ;
assign #8 out[9] = sel[3] & ~sel[2] & ~sel[1] & sel[0] & in ;
assign #8 out[10] = sel[3] & ~sel[2] & sel[1] & ~sel[0] & in ;
assign #8 out[11] = sel[3] & ~sel[2] & sel[1] & sel[0] & in ;
assign #8 out[12] = sel[3] & sel[2] & ~sel[1] & ~sel[0] & in ;
assign #8 out[13] = sel[3] & sel[2] & ~sel[1] & sel[0] & in ;
assign #8 out[14] = sel[3] & sel[2] & sel[1] & ~sel[0] & in ;
assign #8 out[15] = sel[3] & sel[2] & sel[1] & sel[0] & in ;
endmodule | module Demux16(
input in,
input [3:0] sel,
output [15:0] out
); |
wire w0,w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15 ;
assign #8 out[0] = ~sel[3] & ~sel[2] & ~sel[1] & ~sel[0] & in ;
assign #8 out[1] = ~sel[3] & ~sel[2] & ~sel[1] & sel[0] & in ;
assign #8 out[2] = ~sel[3] & ~sel[2] & sel[1] & ~sel[0] & in ;
assign #8 out[3] = ~sel[3] & ~sel[2] & sel[1] & sel[0] & in ;
assign #8 out[4] = ~sel[3] & sel[2] & ~sel[1] & ~sel[0] & in ;
assign #8 out[5] = ~sel[3] & sel[2] & ~sel[1] & sel[0] & in ;
assign #8 out[6] = ~sel[3] & sel[2] & sel[1] & ~sel[0] & in ;
assign #8 out[7] = ~sel[3] & sel[2] & sel[1] & sel[0] & in ;
assign #8 out[8] = sel[3] & ~sel[2] & ~sel[1] & ~sel[0] & in ;
assign #8 out[9] = sel[3] & ~sel[2] & ~sel[1] & sel[0] & in ;
assign #8 out[10] = sel[3] & ~sel[2] & sel[1] & ~sel[0] & in ;
assign #8 out[11] = sel[3] & ~sel[2] & sel[1] & sel[0] & in ;
assign #8 out[12] = sel[3] & sel[2] & ~sel[1] & ~sel[0] & in ;
assign #8 out[13] = sel[3] & sel[2] & ~sel[1] & sel[0] & in ;
assign #8 out[14] = sel[3] & sel[2] & sel[1] & ~sel[0] & in ;
assign #8 out[15] = sel[3] & sel[2] & sel[1] & sel[0] & in ;
endmodule | 0 |
138,760 | data/full_repos/permissive/85417887/DFF.v | 85,417,887 | DFF.v | v | 89 | 83 | [] | [] | [] | null | line:26: before: "(" | data/verilator_xmls/5b11ccc8-0bad-4bab-ae27-3f145d41e8ae.xml | null | 302,771 | module | module NAND(
input in1,
input in2,
output out
);
buf#(2) (out,~(in1 & in2));
endmodule | module NAND(
input in1,
input in2,
output out
); |
buf#(2) (out,~(in1 & in2));
endmodule | 0 |
138,761 | data/full_repos/permissive/85417887/DFF.v | 85,417,887 | DFF.v | v | 89 | 83 | [] | [] | [] | null | line:26: before: "(" | data/verilator_xmls/5b11ccc8-0bad-4bab-ae27-3f145d41e8ae.xml | null | 302,771 | module | module NOR(
input in1,
input in2,
output out
);
buf#(3,2) (out,~(in1 | in2));
endmodule | module NOR(
input in1,
input in2,
output out
); |
buf#(3,2) (out,~(in1 | in2));
endmodule | 0 |
138,762 | data/full_repos/permissive/85417887/DFF.v | 85,417,887 | DFF.v | v | 89 | 83 | [] | [] | [] | null | line:26: before: "(" | data/verilator_xmls/5b11ccc8-0bad-4bab-ae27-3f145d41e8ae.xml | null | 302,771 | module | module DNlatch_NOR(
input En,
input D,
output Q,
output not_Q
);
wire not_D,A,B ;
NOR n1(D,D,not_D);
NOR n2(D,En,A);
NOR n3(not_D,En,B);
NOR n4(A,not_Q,Q);
NOR n5(B,Q,not_Q);
endmodule | module DNlatch_NOR(
input En,
input D,
output Q,
output not_Q
); |
wire not_D,A,B ;
NOR n1(D,D,not_D);
NOR n2(D,En,A);
NOR n3(not_D,En,B);
NOR n4(A,not_Q,Q);
NOR n5(B,Q,not_Q);
endmodule | 0 |
138,763 | data/full_repos/permissive/85417887/DFF.v | 85,417,887 | DFF.v | v | 89 | 83 | [] | [] | [] | null | line:26: before: "(" | data/verilator_xmls/5b11ccc8-0bad-4bab-ae27-3f145d41e8ae.xml | null | 302,771 | module | module Dlatch_NAND(
input En,
input D,
output Q,
output not_Q
);
wire not_D,A,B ;
NAND n1(D,D,not_D);
NAND n2(D,En,A);
NAND n3(not_D,En,B);
NAND n4(A,not_Q,Q);
NAND n5(B,Q,not_Q);
endmodule | module Dlatch_NAND(
input En,
input D,
output Q,
output not_Q
); |
wire not_D,A,B ;
NAND n1(D,D,not_D);
NAND n2(D,En,A);
NAND n3(not_D,En,B);
NAND n4(A,not_Q,Q);
NAND n5(B,Q,not_Q);
endmodule | 0 |
138,764 | data/full_repos/permissive/85417887/DFF.v | 85,417,887 | DFF.v | v | 89 | 83 | [] | [] | [] | null | line:26: before: "(" | data/verilator_xmls/5b11ccc8-0bad-4bab-ae27-3f145d41e8ae.xml | null | 302,771 | module | module DFF(
input clk,
input En,
input D,
output Q
);
wire D2;
DNlatch_NOR dn1(clk,D,D2,);
Dlatch_NAND d1((clk & En),D2,Q,);
endmodule | module DFF(
input clk,
input En,
input D,
output Q
); |
wire D2;
DNlatch_NOR dn1(clk,D,D2,);
Dlatch_NAND d1((clk & En),D2,Q,);
endmodule | 0 |
138,765 | data/full_repos/permissive/85417887/Full_Adder.v | 85,417,887 | Full_Adder.v | v | 58 | 83 | [] | [] | [] | null | line:27: before: "(" | null | 1: b"%Error: data/full_repos/permissive/85417887/Full_Adder.v:51: Cannot find file containing module: 'NAND'\n NAND n1(A,B,G); \n ^~~~\n ... Looked in:\n data/full_repos/permissive/85417887,data/full_repos/permissive/85417887/NAND\n data/full_repos/permissive/85417887,data/full_repos/permissive/85417887/NAND.v\n data/full_repos/permissive/85417887,data/full_repos/permissive/85417887/NAND.sv\n NAND\n NAND.v\n NAND.sv\n obj_dir/NAND\n obj_dir/NAND.v\n obj_dir/NAND.sv\n%Error: data/full_repos/permissive/85417887/Full_Adder.v:54: Cannot find file containing module: 'NAND'\n NAND n2(P,Ci,i1);\n ^~~~\n%Error: data/full_repos/permissive/85417887/Full_Adder.v:56: Cannot find file containing module: 'NAND'\n NAND n3(G,i1,Co);\n ^~~~\n%Error: Exiting due to 3 error(s)\n" | 302,772 | module | module XOR(
input in1,
input in2,
output out
);
buf#(5) (out,in1 ^ in2);
endmodule | module XOR(
input in1,
input in2,
output out
); |
buf#(5) (out,in1 ^ in2);
endmodule | 0 |
138,766 | data/full_repos/permissive/85417887/Full_Adder.v | 85,417,887 | Full_Adder.v | v | 58 | 83 | [] | [] | [] | null | line:27: before: "(" | null | 1: b"%Error: data/full_repos/permissive/85417887/Full_Adder.v:51: Cannot find file containing module: 'NAND'\n NAND n1(A,B,G); \n ^~~~\n ... Looked in:\n data/full_repos/permissive/85417887,data/full_repos/permissive/85417887/NAND\n data/full_repos/permissive/85417887,data/full_repos/permissive/85417887/NAND.v\n data/full_repos/permissive/85417887,data/full_repos/permissive/85417887/NAND.sv\n NAND\n NAND.v\n NAND.sv\n obj_dir/NAND\n obj_dir/NAND.v\n obj_dir/NAND.sv\n%Error: data/full_repos/permissive/85417887/Full_Adder.v:54: Cannot find file containing module: 'NAND'\n NAND n2(P,Ci,i1);\n ^~~~\n%Error: data/full_repos/permissive/85417887/Full_Adder.v:56: Cannot find file containing module: 'NAND'\n NAND n3(G,i1,Co);\n ^~~~\n%Error: Exiting due to 3 error(s)\n" | 302,772 | module | module Full_Adder(
input A,
input B,
input Ci,
output S,
output Co
);
wire P , i1 , G ;
XOR x1(A,B,P);
NAND n1(A,B,G);
XOR x2(P,Ci,S);
NAND n2(P,Ci,i1);
NAND n3(G,i1,Co);
endmodule | module Full_Adder(
input A,
input B,
input Ci,
output S,
output Co
); |
wire P , i1 , G ;
XOR x1(A,B,P);
NAND n1(A,B,G);
XOR x2(P,Ci,S);
NAND n2(P,Ci,i1);
NAND n3(G,i1,Co);
endmodule | 0 |
138,767 | data/full_repos/permissive/85417887/RF.v | 85,417,887 | RF.v | v | 118 | 221 | [] | [] | [] | null | line:84: before: "(" | null | 1: b"%Error: data/full_repos/permissive/85417887/RF.v:102: Cannot find file containing module: 'Demux16'\n Demux16 dm(WrEn,Rw,d); \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/85417887,data/full_repos/permissive/85417887/Demux16\n data/full_repos/permissive/85417887,data/full_repos/permissive/85417887/Demux16.v\n data/full_repos/permissive/85417887,data/full_repos/permissive/85417887/Demux16.sv\n Demux16\n Demux16.v\n Demux16.sv\n obj_dir/Demux16\n obj_dir/Demux16.v\n obj_dir/Demux16.sv\n%Error: data/full_repos/permissive/85417887/RF.v:107: Cannot find file containing module: 'Reg_Cell'\n Reg_Cell e(w,clk,d[i],register[i]); \n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 302,774 | module | module MUX16(
input [15:0] register15,
input [15:0] register14,
input [15:0] register13,
input [15:0] register12,
input [15:0] register11,
input [15:0] register10,
input [15:0] register9,
input [15:0] register8,
input [15:0] register7,
input [15:0] register6,
input [15:0] register5,
input [15:0] register4,
input [15:0] register3,
input [15:0] register2,
input [15:0] register1,
input [15:0] register0,
input [3:0] sel,
output [15:0] out
);
wire [15:0] registers[15:0] ;
assign registers[0]= register0;
assign registers[1]= register1;
assign registers[2]= register2;
assign registers[3]= register3;
assign registers[4]= register4;
assign registers[5]= register5;
assign registers[6]= register6;
assign registers[7]= register7;
assign registers[8]= register8;
assign registers[9]= register9;
assign registers[10]= register10;
assign registers[11]= register11;
assign registers[12]= register12;
assign registers[13]= register13;
assign registers[14]= register14;
assign registers[15]= register15;
assign #5 out = registers[sel] ;
endmodule | module MUX16(
input [15:0] register15,
input [15:0] register14,
input [15:0] register13,
input [15:0] register12,
input [15:0] register11,
input [15:0] register10,
input [15:0] register9,
input [15:0] register8,
input [15:0] register7,
input [15:0] register6,
input [15:0] register5,
input [15:0] register4,
input [15:0] register3,
input [15:0] register2,
input [15:0] register1,
input [15:0] register0,
input [3:0] sel,
output [15:0] out
); |
wire [15:0] registers[15:0] ;
assign registers[0]= register0;
assign registers[1]= register1;
assign registers[2]= register2;
assign registers[3]= register3;
assign registers[4]= register4;
assign registers[5]= register5;
assign registers[6]= register6;
assign registers[7]= register7;
assign registers[8]= register8;
assign registers[9]= register9;
assign registers[10]= register10;
assign registers[11]= register11;
assign registers[12]= register12;
assign registers[13]= register13;
assign registers[14]= register14;
assign registers[15]= register15;
assign #5 out = registers[sel] ;
endmodule | 0 |
138,768 | data/full_repos/permissive/85417887/RF.v | 85,417,887 | RF.v | v | 118 | 221 | [] | [] | [] | null | line:84: before: "(" | null | 1: b"%Error: data/full_repos/permissive/85417887/RF.v:102: Cannot find file containing module: 'Demux16'\n Demux16 dm(WrEn,Rw,d); \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/85417887,data/full_repos/permissive/85417887/Demux16\n data/full_repos/permissive/85417887,data/full_repos/permissive/85417887/Demux16.v\n data/full_repos/permissive/85417887,data/full_repos/permissive/85417887/Demux16.sv\n Demux16\n Demux16.v\n Demux16.sv\n obj_dir/Demux16\n obj_dir/Demux16.v\n obj_dir/Demux16.sv\n%Error: data/full_repos/permissive/85417887/RF.v:107: Cannot find file containing module: 'Reg_Cell'\n Reg_Cell e(w,clk,d[i],register[i]); \n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 302,774 | module | module RF(
input [3:0] Ra,
input [3:0] Rb,
input [3:0] Rw,
input WrEn,
input clk,
input [15:0] Wdat,
output [15:0] Adat,
output [15:0] Bdat
);
wire [15:0] d ;
wire [15:0] w;
wire [15:0] register[15:0] ;
buf#(8)(w[0],Wdat[0]);
buf#(8)(w[1],Wdat[1]);
buf#(8)(w[2],Wdat[2]);
buf#(8)(w[3],Wdat[3]);
buf#(8)(w[4],Wdat[4]);
buf#(8)(w[5],Wdat[5]);
buf#(8)(w[6],Wdat[6]);
buf#(8)(w[7],Wdat[7]);
buf#(8)(w[8],Wdat[8]);
buf#(8)(w[9],Wdat[9]);
buf#(8)(w[10],Wdat[10]);
buf#(8)(w[11],Wdat[11]);
buf#(8)(w[12],Wdat[12]);
buf#(8)(w[13],Wdat[13]);
buf#(8)(w[14],Wdat[14]);
buf#(8)(w[15],Wdat[15]);
Demux16 dm(WrEn,Rw,d);
generate
genvar i;
for (i=0; i < 16; i=i+1) begin: r
Reg_Cell e(w,clk,d[i],register[i]);
end
endgenerate
MUX16 Mux_A(register[15],register[14],register[13],register[12],register[11],register[10],register[9],register[8],register[7],register[6],register[5],register[4],register[3],register[2],register[1],register[0],Ra,Adat);
MUX16 Mux_B(register[15],register[14],register[13],register[12],register[11],register[10],register[9],register[8],register[7],register[6],register[5],register[4],register[3],register[2],register[1],register[0],Rb,Bdat);
endmodule | module RF(
input [3:0] Ra,
input [3:0] Rb,
input [3:0] Rw,
input WrEn,
input clk,
input [15:0] Wdat,
output [15:0] Adat,
output [15:0] Bdat
); |
wire [15:0] d ;
wire [15:0] w;
wire [15:0] register[15:0] ;
buf#(8)(w[0],Wdat[0]);
buf#(8)(w[1],Wdat[1]);
buf#(8)(w[2],Wdat[2]);
buf#(8)(w[3],Wdat[3]);
buf#(8)(w[4],Wdat[4]);
buf#(8)(w[5],Wdat[5]);
buf#(8)(w[6],Wdat[6]);
buf#(8)(w[7],Wdat[7]);
buf#(8)(w[8],Wdat[8]);
buf#(8)(w[9],Wdat[9]);
buf#(8)(w[10],Wdat[10]);
buf#(8)(w[11],Wdat[11]);
buf#(8)(w[12],Wdat[12]);
buf#(8)(w[13],Wdat[13]);
buf#(8)(w[14],Wdat[14]);
buf#(8)(w[15],Wdat[15]);
Demux16 dm(WrEn,Rw,d);
generate
genvar i;
for (i=0; i < 16; i=i+1) begin: r
Reg_Cell e(w,clk,d[i],register[i]);
end
endgenerate
MUX16 Mux_A(register[15],register[14],register[13],register[12],register[11],register[10],register[9],register[8],register[7],register[6],register[5],register[4],register[3],register[2],register[1],register[0],Ra,Adat);
MUX16 Mux_B(register[15],register[14],register[13],register[12],register[11],register[10],register[9],register[8],register[7],register[6],register[5],register[4],register[3],register[2],register[1],register[0],Rb,Bdat);
endmodule | 0 |
138,769 | data/full_repos/permissive/85417887/testALU16.v | 85,417,887 | testALU16.v | v | 420 | 122 | [] | [] | [] | [(25, 418)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:60: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/85417887/testALU16.v:62: Unsupported or unknown PLI call: $monitor\n $monitor("OUT %g C= %b F= %b out= %b , %d N= %b Z= %b L= %b ", $time,C, F, $signed(out), $signed(out), N,Z,L);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:71: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:80: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:87: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:96: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:105: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:112: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:120: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:127: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:134: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:142: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:151: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:159: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/85417887/testALU16.v:161: Unsupported or unknown PLI call: $monitor\n $monitor("OUT %g C= %b F= %b out= %b , %d N= %b Z= %b L= %b ", $time,C, F, $unsigned(out), $unsigned(out), N,Z,L);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:169: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:177: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:185: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:194: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:202: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:210: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:218: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:227: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:235: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:243: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:251: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:261: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:269: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:277: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:285: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:295: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:303: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:311: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:319: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:326: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:335: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:343: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:352: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:359: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:367: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:375: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:383: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/85417887/testALU16.v:388: Unsupported or unknown PLI call: $monitor\n $monitor("OUT %g C= %b F= %b out= %b , %d N= %b Z= %b L= %b ", $time,C, F, $signed(out), $signed(out), N,Z,L);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:391: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/85417887/testALU16.v:396: Unsupported or unknown PLI call: $monitor\n $monitor("OUT %g C= %b F= %b out= %b , %d N= %b Z= %b L= %b ", $time,C, F, $signed(out), $signed(out), N,Z,L);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:399: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/85417887/testALU16.v:404: Unsupported or unknown PLI call: $monitor\n $monitor("OUT %g C= %b F= %b out= %b , %d N= %b Z= %b L= %b ", $time,C, F, $signed(out), $signed(out), N,Z,L);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testALU16.v:407: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/85417887/testALU16.v:412: Unsupported or unknown PLI call: $monitor\n $monitor("OUT %g C= %b F= %b out= %b , %d N= %b Z= %b L= %b ", $time,C, F, $signed(out), $signed(out), N,Z,L);\n ^~~~~~~~\n%Error: Exiting due to 6 error(s), 43 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,775 | module | module testALU16;
reg [15:0] A;
reg [15:0] B;
reg [3:0] sel;
wire [15:0] out;
wire N;
wire L;
wire Z;
wire C;
wire F;
ALU16 uut (
.A(A),
.B(B),
.sel(sel),
.out(out),
.N(N),
.L(L),
.Z(Z),
.C(C),
.F(F)
);
initial begin
A = 0;
B = 0;
sel = 0;
#100;
$display("First signed operations" );
$monitor("OUT %g C= %b F= %b out= %b , %d N= %b Z= %b L= %b ", $time,C, F, $signed(out), $signed(out), N,Z,L);
$display("SUM" );
A = $signed(16'd69);
B = $signed(16'd55);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUM ") ;
A = $signed(-16'd10);
B = $signed(16'd55);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUM" );
A = $signed(-16'd10);
B = $signed(-16'd55);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUM" );
A = $signed(+16'd55);
B = $signed(-16'd55);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUB" );
A = $signed(-16'd10);
B = $signed(16'd55);
sel = 4'b0101 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUB" );
A = $signed(+16'd10);
B = $signed(-16'd55);
sel = 4'b0101 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUM" );
A = $signed(-16'd16372);
B = $signed(-16'd16372);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUB" );
A = $signed(+16'd16372);
B = $signed(-16'd6880);
sel = 4'b0101 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUM" );
A = $signed(-16'd16372);
B = $signed(+16'd16372);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUM" );
A = $signed(+16'd16384);
B = $signed(+16'd16394);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUM" );
A = $signed(+16'd16372);
B = $signed(+16'd10880);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUM" );
A = $signed(+16'd16372);
B = $signed(+16'd20880);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("Now logic operations" );
$monitor("OUT %g C= %b F= %b out= %b , %d N= %b Z= %b L= %b ", $time,C, F, $unsigned(out), $unsigned(out), N,Z,L);
$display("AND" );
A = $unsigned(+16'd16372);
B = $unsigned(+16'd20880);
sel = 4'b1000 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("AND" );
A = $unsigned(+16'd15);
B = $unsigned(+16'd2);
sel = 4'b1000 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("AND" );
A = $unsigned(+16'd100);
B = $unsigned(+16'd185);
sel = 4'b1000 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("AND" );
A = $unsigned(+16'd0);
B = $unsigned(+16'd32767);
sel = 4'b1000 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("XOR" );
A = $unsigned(+16'd0);
B = $unsigned(+16'd32767);
sel = 4'b0000 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("XOR" );
A = $unsigned(+16'd16372);
B = $unsigned(+16'd20880);
sel = 4'b0000 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("XOR" );
A = $unsigned(+16'd15);
B = $unsigned(+16'd2);
sel = 4'b0000 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("XOR" );
A = $unsigned(+16'd100);
B = $unsigned(+16'd185);
sel = 4'b0000 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("XNOR" );
A = $unsigned(+16'd0);
B = $unsigned(+16'd32767);
sel = 4'b0010 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("XNOR" );
A = $unsigned(+16'd16372);
B = $unsigned(+16'd20880);
sel = 4'b0010 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("XNOR" );
A = $unsigned(+16'd15);
B = $unsigned(+16'd2);
sel = 4'b0010 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("XNOR" );
A = $unsigned(+16'd100);
B = $unsigned(+16'd185);
sel = 4'b0010 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("OR" );
A = $unsigned(+16'd0);
B = $unsigned(+16'd32767);
sel = 4'b1010 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("OR" );
A = $unsigned(+16'd16372);
B = $unsigned(+16'd20880);
sel = 4'b1010 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("OR" );
A = $unsigned(+16'd15);
B = $unsigned(+16'd2);
sel = 4'b1010 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("OR" );
A = $unsigned(+16'd100);
B = $unsigned(+16'd185);
sel = 4'b1010 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("NOT A" );
A = $unsigned(+16'd0);
B = $unsigned(+16'd32767);
sel = 4'b0111 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("NOT A" );
A = $unsigned(+16'd16372);
B = $unsigned(+16'd20880);
sel = 4'b0111 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("NOT A" );
A = $unsigned(+16'd15);
B = $unsigned(+16'd2);
sel = 4'b0111 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("NOT A" );
A = $unsigned(+16'd100);
B = $unsigned(+16'd185);
sel = 4'b0111 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("Lastly unsigned operations" );
$display("SUM" );
A = $unsigned(+16'd100);
B = $unsigned(+16'd185);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("SUM" );
A = $unsigned(+16'd35000);
B = $unsigned(+16'd30536);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("SUM" );
A = $unsigned(+16'd31);
B = $unsigned(+16'd10000);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("SUM" );
A = $unsigned(+16'd32000);
B = $unsigned(+16'd32000);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("SUB" );
A = $unsigned(+16'd10000);
B = $unsigned(+16'd31);
sel = 4'b0101 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("SUB" );
A = $unsigned(+16'd32000);
B = $unsigned(+16'd16000);
sel = 4'b0101 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("SUB" );
A = $unsigned(+16'd500);
B = $unsigned(+16'd500);
sel = 4'b0101 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("SUB" );
A = $unsigned(+16'd500);
B = $unsigned(+16'd600);
sel = 4'b0101 ;
$monitor("OUT %g C= %b F= %b out= %b , %d N= %b Z= %b L= %b ", $time,C, F, $signed(out), $signed(out), N,Z,L);
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("SUB" );
A = $unsigned(+16'd500);
B = $unsigned(+16'd1000);
sel = 4'b0101 ;
$monitor("OUT %g C= %b F= %b out= %b , %d N= %b Z= %b L= %b ", $time,C, F, $signed(out), $signed(out), N,Z,L);
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("SUB" );
A = $unsigned(+16'd2);
B = $unsigned(+16'd5);
sel = 4'b0101 ;
$monitor("OUT %g C= %b F= %b out= %b , %d N= %b Z= %b L= %b ", $time,C, F, $signed(out), $signed(out), N,Z,L);
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("SUB" );
A = $unsigned(+16'd2);
B = $unsigned(+16'd500);
sel = 4'b0101 ;
$monitor("OUT %g C= %b F= %b out= %b , %d N= %b Z= %b L= %b ", $time,C, F, $signed(out), $signed(out), N,Z,L);
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
end
endmodule | module testALU16; |
reg [15:0] A;
reg [15:0] B;
reg [3:0] sel;
wire [15:0] out;
wire N;
wire L;
wire Z;
wire C;
wire F;
ALU16 uut (
.A(A),
.B(B),
.sel(sel),
.out(out),
.N(N),
.L(L),
.Z(Z),
.C(C),
.F(F)
);
initial begin
A = 0;
B = 0;
sel = 0;
#100;
$display("First signed operations" );
$monitor("OUT %g C= %b F= %b out= %b , %d N= %b Z= %b L= %b ", $time,C, F, $signed(out), $signed(out), N,Z,L);
$display("SUM" );
A = $signed(16'd69);
B = $signed(16'd55);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUM ") ;
A = $signed(-16'd10);
B = $signed(16'd55);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUM" );
A = $signed(-16'd10);
B = $signed(-16'd55);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUM" );
A = $signed(+16'd55);
B = $signed(-16'd55);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUB" );
A = $signed(-16'd10);
B = $signed(16'd55);
sel = 4'b0101 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUB" );
A = $signed(+16'd10);
B = $signed(-16'd55);
sel = 4'b0101 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUM" );
A = $signed(-16'd16372);
B = $signed(-16'd16372);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUB" );
A = $signed(+16'd16372);
B = $signed(-16'd6880);
sel = 4'b0101 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUM" );
A = $signed(-16'd16372);
B = $signed(+16'd16372);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUM" );
A = $signed(+16'd16384);
B = $signed(+16'd16394);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUM" );
A = $signed(+16'd16372);
B = $signed(+16'd10880);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("SUM" );
A = $signed(+16'd16372);
B = $signed(+16'd20880);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $signed(A), $signed(A), $signed(B), $signed(B), sel );
#100;
$display("Now logic operations" );
$monitor("OUT %g C= %b F= %b out= %b , %d N= %b Z= %b L= %b ", $time,C, F, $unsigned(out), $unsigned(out), N,Z,L);
$display("AND" );
A = $unsigned(+16'd16372);
B = $unsigned(+16'd20880);
sel = 4'b1000 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("AND" );
A = $unsigned(+16'd15);
B = $unsigned(+16'd2);
sel = 4'b1000 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("AND" );
A = $unsigned(+16'd100);
B = $unsigned(+16'd185);
sel = 4'b1000 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("AND" );
A = $unsigned(+16'd0);
B = $unsigned(+16'd32767);
sel = 4'b1000 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("XOR" );
A = $unsigned(+16'd0);
B = $unsigned(+16'd32767);
sel = 4'b0000 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("XOR" );
A = $unsigned(+16'd16372);
B = $unsigned(+16'd20880);
sel = 4'b0000 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("XOR" );
A = $unsigned(+16'd15);
B = $unsigned(+16'd2);
sel = 4'b0000 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("XOR" );
A = $unsigned(+16'd100);
B = $unsigned(+16'd185);
sel = 4'b0000 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("XNOR" );
A = $unsigned(+16'd0);
B = $unsigned(+16'd32767);
sel = 4'b0010 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("XNOR" );
A = $unsigned(+16'd16372);
B = $unsigned(+16'd20880);
sel = 4'b0010 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("XNOR" );
A = $unsigned(+16'd15);
B = $unsigned(+16'd2);
sel = 4'b0010 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("XNOR" );
A = $unsigned(+16'd100);
B = $unsigned(+16'd185);
sel = 4'b0010 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("OR" );
A = $unsigned(+16'd0);
B = $unsigned(+16'd32767);
sel = 4'b1010 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("OR" );
A = $unsigned(+16'd16372);
B = $unsigned(+16'd20880);
sel = 4'b1010 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("OR" );
A = $unsigned(+16'd15);
B = $unsigned(+16'd2);
sel = 4'b1010 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("OR" );
A = $unsigned(+16'd100);
B = $unsigned(+16'd185);
sel = 4'b1010 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("NOT A" );
A = $unsigned(+16'd0);
B = $unsigned(+16'd32767);
sel = 4'b0111 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("NOT A" );
A = $unsigned(+16'd16372);
B = $unsigned(+16'd20880);
sel = 4'b0111 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("NOT A" );
A = $unsigned(+16'd15);
B = $unsigned(+16'd2);
sel = 4'b0111 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("NOT A" );
A = $unsigned(+16'd100);
B = $unsigned(+16'd185);
sel = 4'b0111 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("Lastly unsigned operations" );
$display("SUM" );
A = $unsigned(+16'd100);
B = $unsigned(+16'd185);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("SUM" );
A = $unsigned(+16'd35000);
B = $unsigned(+16'd30536);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("SUM" );
A = $unsigned(+16'd31);
B = $unsigned(+16'd10000);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("SUM" );
A = $unsigned(+16'd32000);
B = $unsigned(+16'd32000);
sel = 4'b0100 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("SUB" );
A = $unsigned(+16'd10000);
B = $unsigned(+16'd31);
sel = 4'b0101 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("SUB" );
A = $unsigned(+16'd32000);
B = $unsigned(+16'd16000);
sel = 4'b0101 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("SUB" );
A = $unsigned(+16'd500);
B = $unsigned(+16'd500);
sel = 4'b0101 ;
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("SUB" );
A = $unsigned(+16'd500);
B = $unsigned(+16'd600);
sel = 4'b0101 ;
$monitor("OUT %g C= %b F= %b out= %b , %d N= %b Z= %b L= %b ", $time,C, F, $signed(out), $signed(out), N,Z,L);
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("SUB" );
A = $unsigned(+16'd500);
B = $unsigned(+16'd1000);
sel = 4'b0101 ;
$monitor("OUT %g C= %b F= %b out= %b , %d N= %b Z= %b L= %b ", $time,C, F, $signed(out), $signed(out), N,Z,L);
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("SUB" );
A = $unsigned(+16'd2);
B = $unsigned(+16'd5);
sel = 4'b0101 ;
$monitor("OUT %g C= %b F= %b out= %b , %d N= %b Z= %b L= %b ", $time,C, F, $signed(out), $signed(out), N,Z,L);
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
#100;
$display("SUB" );
A = $unsigned(+16'd2);
B = $unsigned(+16'd500);
sel = 4'b0101 ;
$monitor("OUT %g C= %b F= %b out= %b , %d N= %b Z= %b L= %b ", $time,C, F, $signed(out), $signed(out), N,Z,L);
$display("IN %g A= %b,%d B= %b,%d sel= %b ", $time, $unsigned(A), $unsigned(A), $unsigned(B), $unsigned(B), sel );
end
endmodule | 0 |
138,770 | data/full_repos/permissive/85417887/testRF.v | 85,417,887 | testRF.v | v | 134 | 134 | [] | [] | [] | [(25, 132)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/85417887/testRF.v:53: Unsupported: Ignoring delay on this delayed statement.\n #100 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/85417887/testRF.v:67: Unsupported or unknown PLI call: $monitor\n $monitor( "%g clk=%b Ra=%d Rb =%d Rw=%d WrEn=%b Adat=%h Bdat=%h Wdat=%h", $time, clk, Ra, Rb, Rw , WrEn , Adat , Bdat , Wdat);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testRF.v:70: Unsupported: Ignoring delay on this delayed statement.\n #250;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testRF.v:76: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testRF.v:80: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testRF.v:84: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testRF.v:88: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testRF.v:93: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testRF.v:99: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testRF.v:105: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testRF.v:111: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/85417887/testRF.v:115: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Error: Exiting due to 1 error(s), 11 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,776 | module | module testRF;
reg [3:0] Ra;
reg [3:0] Rb;
reg [3:0] Rw;
reg WrEn;
reg clk;
reg [15:0] Wdat;
wire [15:0] Adat;
wire [15:0] Bdat;
RF dut (
.Ra(Ra),
.Rb(Rb),
.Rw(Rw),
.WrEn(WrEn),
.clk(clk),
.Wdat(Wdat),
.Adat(Adat),
.Bdat(Bdat)
);
always begin
#100 clk = ~clk;
end
initial begin
Ra = 0;
Rb = 0;
Rw = 0;
WrEn = 0;
clk = 0;
Wdat = 0;
$monitor( "%g clk=%b Ra=%d Rb =%d Rw=%d WrEn=%b Adat=%h Bdat=%h Wdat=%h", $time, clk, Ra, Rb, Rw , WrEn , Adat , Bdat , Wdat);
#250;
Wdat = 16'hABCD;
WrEn = 1;
Rw = 4'd5;
#100;
Ra = 4'd5;
WrEn =0 ;
#100;
Wdat = 16'hE050;
Rw = 4'd12;
#200;
WrEn =1;
Rb=4'd12;
#200;
Wdat = 16'h5290;
Rw = 4'd5;
#200;
Wdat = 16'h529E;
Rw = 4'd9;
#200;
Wdat = 16'h529E;
Rw = 4'd12;
Ra = 4'd9;
#200;
WrEn =0;
Wdat = 16'hEEEE;
Ra = 4'd12;
Rb = 4'd5;
#200;
WrEn =1;
Rw = 4'd9;
#200;
WrEn =0;
Wdat = 16'hAAAA;
Ra = 4'd9;
end
endmodule | module testRF; |
reg [3:0] Ra;
reg [3:0] Rb;
reg [3:0] Rw;
reg WrEn;
reg clk;
reg [15:0] Wdat;
wire [15:0] Adat;
wire [15:0] Bdat;
RF dut (
.Ra(Ra),
.Rb(Rb),
.Rw(Rw),
.WrEn(WrEn),
.clk(clk),
.Wdat(Wdat),
.Adat(Adat),
.Bdat(Bdat)
);
always begin
#100 clk = ~clk;
end
initial begin
Ra = 0;
Rb = 0;
Rw = 0;
WrEn = 0;
clk = 0;
Wdat = 0;
$monitor( "%g clk=%b Ra=%d Rb =%d Rw=%d WrEn=%b Adat=%h Bdat=%h Wdat=%h", $time, clk, Ra, Rb, Rw , WrEn , Adat , Bdat , Wdat);
#250;
Wdat = 16'hABCD;
WrEn = 1;
Rw = 4'd5;
#100;
Ra = 4'd5;
WrEn =0 ;
#100;
Wdat = 16'hE050;
Rw = 4'd12;
#200;
WrEn =1;
Rb=4'd12;
#200;
Wdat = 16'h5290;
Rw = 4'd5;
#200;
Wdat = 16'h529E;
Rw = 4'd9;
#200;
Wdat = 16'h529E;
Rw = 4'd12;
Ra = 4'd9;
#200;
WrEn =0;
Wdat = 16'hEEEE;
Ra = 4'd12;
Rb = 4'd5;
#200;
WrEn =1;
Rw = 4'd9;
#200;
WrEn =0;
Wdat = 16'hAAAA;
Ra = 4'd9;
end
endmodule | 0 |
138,771 | data/full_repos/permissive/85728940/cortex-m0/hdl/cortex-m0-nvic.v | 85,728,940 | cortex-m0-nvic.v | v | 29 | 74 | [] | [] | [] | null | line:28: before: ";" | null | 1: b"%Error: data/full_repos/permissive/85728940/cortex-m0/hdl/cortex-m0-nvic.v:16: Can't find definition of variable: 'N_EXT_INT'\n input [N_EXT_INT-1:0] ext_int,\n ^~~~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 302,778 | module | module cortex_m0_nvic (
input clk,
input reset,
input [N_EXT_INT-1:0] ext_int,
input nmi
);
reg [31:0] ISER;
reg [31:0] ICER;
reg [31:0] ISPR;
reg [31:0] ICPR;
reg [31:0] IPR[7:0];
endmodule | module cortex_m0_nvic (
input clk,
input reset,
input [N_EXT_INT-1:0] ext_int,
input nmi
); |
reg [31:0] ISER;
reg [31:0] ICER;
reg [31:0] ISPR;
reg [31:0] ICPR;
reg [31:0] IPR[7:0];
endmodule | 0 |
138,772 | data/full_repos/permissive/85728940/cortex-m0/hdl/cortex-m0-pipeline-decode.v | 85,728,940 | cortex-m0-pipeline-decode.v | v | 186 | 86 | [] | [] | [] | null | line:16: before: "output" | null | 1: b"%Error: data/full_repos/permissive/85728940/cortex-m0/hdl/cortex-m0-pipeline-decode.v:16: syntax error, unexpected output, expecting ')' or ','\n output reg [2:0] Rd;\n ^~~~~~\n%Error: data/full_repos/permissive/85728940/cortex-m0/hdl/cortex-m0-pipeline-decode.v:17: syntax error, unexpected output\n output reg [2:0] Rm;\n ^~~~~~\n%Error: data/full_repos/permissive/85728940/cortex-m0/hdl/cortex-m0-pipeline-decode.v:18: syntax error, unexpected output\n output reg [2:0] Rn;\n ^~~~~~\n%Error: data/full_repos/permissive/85728940/cortex-m0/hdl/cortex-m0-pipeline-decode.v:19: syntax error, unexpected output\n output reg [7:0] imm;\n ^~~~~~\n%Error: data/full_repos/permissive/85728940/cortex-m0/hdl/cortex-m0-pipeline-decode.v:20: syntax error, unexpected ')'\n);\n^\n%Error: data/full_repos/permissive/85728940/cortex-m0/hdl/cortex-m0-pipeline-decode.v:44: syntax error, unexpected wire, expecting ',' or ';'\nwire sasmc = main_opcode == 6'b00xxxx;\n^~~~\n%Error: data/full_repos/permissive/85728940/cortex-m0/hdl/cortex-m0-pipeline-decode.v:133: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n);\n^\n%Error: Exiting due to 7 error(s)\n" | 302,779 | module | module cortex_m0_decode (
input clk,
input reset,
input [15:0] inst
output reg [2:0] Rd;
output reg [2:0] Rm;
output reg [2:0] Rn;
output reg [7:0] imm;
);
wire main_opcode = inst[15:10]
wire sasmc = main_opcode == 6'b00xxxx;
wire data_processing = main_opcode == 6'b010000;
wire special = main_opcode == 6'b010001;
wire load_store_single = (main_opcode == 6'b0101xx) || (main_opcode == 6'b0110xx) ||
(main_opcode == 6'b0111xx) || (main_opcode == 6'b100xxx);
wire misc = (inst[15:12] == 4'b1011) && (
( inst[11:5] == 7'b0000xxx ) ||
( inst[11:5] == 7'b00100xx ) ||
);
endmodule | module cortex_m0_decode (
input clk,
input reset,
input [15:0] inst
output reg [2:0] Rd; |
output reg [2:0] Rm;
output reg [2:0] Rn;
output reg [7:0] imm;
);
wire main_opcode = inst[15:10]
wire sasmc = main_opcode == 6'b00xxxx;
wire data_processing = main_opcode == 6'b010000;
wire special = main_opcode == 6'b010001;
wire load_store_single = (main_opcode == 6'b0101xx) || (main_opcode == 6'b0110xx) ||
(main_opcode == 6'b0111xx) || (main_opcode == 6'b100xxx);
wire misc = (inst[15:12] == 4'b1011) && (
( inst[11:5] == 7'b0000xxx ) ||
( inst[11:5] == 7'b00100xx ) ||
);
endmodule | 0 |
138,773 | data/full_repos/permissive/85728940/cortex-m0/hdl/cortex-m0-systick.v | 85,728,940 | cortex-m0-systick.v | v | 34 | 71 | [] | [] | [] | null | line:15: before: ";" | null | 1: b"%Error: data/full_repos/permissive/85728940/cortex-m0/hdl/cortex-m0-systick.v:15: syntax error, unexpected ';', expecting ')' or ','\n output [23:0]syst_cvr;\n ^\n%Error: data/full_repos/permissive/85728940/cortex-m0/hdl/cortex-m0-systick.v:25: syntax error, unexpected always\nalways @ (posedge clk)\n^~~~~~\n%Error: Exiting due to 2 error(s)\n" | 302,782 | module | module cortex_m0_systick (
input clk,
input reset,
output [23:0]syst_cvr;
);
reg [23:0]ticks;
reg[31:0] syst_csr;
reg[31:0] syst_rvr;
reg[31:0] syst_cvr;
reg[31:0] syst_calib;
always @ (posedge clk)
begin
if (reset)
syst_cvr <= 24'b0;
else
syst_cvr <= ticks + 1;
end
endmodule | module cortex_m0_systick (
input clk,
input reset,
output [23:0]syst_cvr; |
);
reg [23:0]ticks;
reg[31:0] syst_csr;
reg[31:0] syst_rvr;
reg[31:0] syst_cvr;
reg[31:0] syst_calib;
always @ (posedge clk)
begin
if (reset)
syst_cvr <= 24'b0;
else
syst_cvr <= ticks + 1;
end
endmodule | 0 |
138,774 | data/full_repos/permissive/85728940/cortex-m0/hdl/cortex-m0.v | 85,728,940 | cortex-m0.v | v | 49 | 71 | [] | [] | [] | null | line:44: before: ")" | null | 1: b"%Error: data/full_repos/permissive/85728940/cortex-m0/hdl/cortex-m0.v:44: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: Exiting due to 1 error(s)\n" | 302,783 | module | module cortex_m0 (
input clk,
input reset,
);
endmodule | module cortex_m0 (
input clk,
input reset,
); |
endmodule | 0 |
138,775 | data/full_repos/permissive/85783852/32bitREGISTER/32bitREGISTER.v | 85,783,852 | 32bitREGISTER.v | v | 36 | 134 | [] | [] | [] | [(1, 36)] | null | null | 1: b"%Error: data/full_repos/permissive/85783852/32bitREGISTER/32bitREGISTER.v:25: Cannot find file containing module: 'DECODER_5BIT'\n DECODER_5BIT DecoderRead1(Read_Register1,readAddress1);\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85783852/32bitREGISTER,data/full_repos/permissive/85783852/DECODER_5BIT\n data/full_repos/permissive/85783852/32bitREGISTER,data/full_repos/permissive/85783852/DECODER_5BIT.v\n data/full_repos/permissive/85783852/32bitREGISTER,data/full_repos/permissive/85783852/DECODER_5BIT.sv\n DECODER_5BIT\n DECODER_5BIT.v\n DECODER_5BIT.sv\n obj_dir/DECODER_5BIT\n obj_dir/DECODER_5BIT.v\n obj_dir/DECODER_5BIT.sv\n%Error: data/full_repos/permissive/85783852/32bitREGISTER/32bitREGISTER.v:26: Cannot find file containing module: 'DECODER_5BIT'\n DECODER_5BIT DecoderRead2(Read_Register2,readAddress2);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/85783852/32bitREGISTER/32bitREGISTER.v:27: Cannot find file containing module: 'DECODER_5BIT'\n DECODER_5BIT DecoderWrite(Write_Register,writeAddress);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/85783852/32bitREGISTER/32bitREGISTER.v:33: Cannot find file containing module: 'REGISTER_32BIT'\n REGISTER_32BIT REGUNIT_32BIT(Read_Data1,Read_Data2,Write_Data,Reg_Write,readAddress1[i],readAddress2[i],writeAddress[i]);\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 302,784 | module | module REGISTER_32BITS(Read_Register1,Read_Data1,Read_Register2,Read_Data2,Write_Register,Write_Data,Reg_Write);
input [4:0] Read_Register1;
output [31:0] Read_Data1;
input [4:0] Read_Register2;
output [31:0] Read_Data2;
input [4:0] Write_Register;
input [31:0] Write_Data;
input Reg_Write;
wire [31:0] readAddress1;
wire [31:0] readAddress2;
wire [31:0] writeAddress;
DECODER_5BIT DecoderRead1(Read_Register1,readAddress1);
DECODER_5BIT DecoderRead2(Read_Register2,readAddress2);
DECODER_5BIT DecoderWrite(Write_Register,writeAddress);
generate
genvar i;
for (i=0; i<32; i=i+1) begin : regUnit0
REGISTER_32BIT REGUNIT_32BIT(Read_Data1,Read_Data2,Write_Data,Reg_Write,readAddress1[i],readAddress2[i],writeAddress[i]);
end
endgenerate
endmodule | module REGISTER_32BITS(Read_Register1,Read_Data1,Read_Register2,Read_Data2,Write_Register,Write_Data,Reg_Write); |
input [4:0] Read_Register1;
output [31:0] Read_Data1;
input [4:0] Read_Register2;
output [31:0] Read_Data2;
input [4:0] Write_Register;
input [31:0] Write_Data;
input Reg_Write;
wire [31:0] readAddress1;
wire [31:0] readAddress2;
wire [31:0] writeAddress;
DECODER_5BIT DecoderRead1(Read_Register1,readAddress1);
DECODER_5BIT DecoderRead2(Read_Register2,readAddress2);
DECODER_5BIT DecoderWrite(Write_Register,writeAddress);
generate
genvar i;
for (i=0; i<32; i=i+1) begin : regUnit0
REGISTER_32BIT REGUNIT_32BIT(Read_Data1,Read_Data2,Write_Data,Reg_Write,readAddress1[i],readAddress2[i],writeAddress[i]);
end
endgenerate
endmodule | 0 |
138,776 | data/full_repos/permissive/85783852/32bitREGISTER/registerUnit.v | 85,783,852 | registerUnit.v | v | 14 | 34 | [] | [] | [] | [(1, 14)] | null | data/verilator_xmls/668dc812-205e-4fdc-ab09-b6edc2400e70.xml | null | 302,785 | module | module REGISTER_UNIT(D,Q,R_W);
input D;
output reg Q;
input R_W;
always @(posedge R_W)
begin
if (R_W == 1)
Q <= D;
end
endmodule | module REGISTER_UNIT(D,Q,R_W); |
input D;
output reg Q;
input R_W;
always @(posedge R_W)
begin
if (R_W == 1)
Q <= D;
end
endmodule | 0 |
138,777 | data/full_repos/permissive/85783852/32bitREGISTER/REGISTER_32BIT.v | 85,783,852 | REGISTER_32BIT.v | v | 37 | 106 | [] | [] | [] | [(1, 37)] | null | null | 1: b"%Error: data/full_repos/permissive/85783852/32bitREGISTER/REGISTER_32BIT.v:30: Cannot find file containing module: 'REGISTER_UNIT'\n REGISTER_UNIT UNIT(D[j],Q[j],EN_out);\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85783852/32bitREGISTER,data/full_repos/permissive/85783852/REGISTER_UNIT\n data/full_repos/permissive/85783852/32bitREGISTER,data/full_repos/permissive/85783852/REGISTER_UNIT.v\n data/full_repos/permissive/85783852/32bitREGISTER,data/full_repos/permissive/85783852/REGISTER_UNIT.sv\n REGISTER_UNIT\n REGISTER_UNIT.v\n REGISTER_UNIT.sv\n obj_dir/REGISTER_UNIT\n obj_dir/REGISTER_UNIT.v\n obj_dir/REGISTER_UNIT.sv\n%Error: Exiting due to 1 error(s)\n" | 302,786 | module | module REGISTER_32BIT(Read_Data1,Read_Data2,Write_Data,Reg_Write,readAddress1,readAddress2,writeAddress);
output [31:0] Read_Data1;
output [31:0] Read_Data2;
input [31:0] Write_Data;
input Reg_Write;
input readAddress1;
input readAddress2;
input writeAddress;
wire EN_out;
wire [31:0] D;
wire [31:0] Q;
and andGate_EN(EN_out,Reg_Write,writeAddress);
generate
genvar j;
for (j=0; j<32; j=j+1) begin : regUnit1
REGISTER_UNIT UNIT(D[j],Q[j],EN_out);
bufif1 buffGate0(Read_Data1[j],Q[j],readAddress1);
bufif1 buffGate1(Read_Data2[j],Q[j],readAddress2);
bufif1 buffGate2(D[j],Write_Data[j],writeAddress);
end
endgenerate
endmodule | module REGISTER_32BIT(Read_Data1,Read_Data2,Write_Data,Reg_Write,readAddress1,readAddress2,writeAddress); |
output [31:0] Read_Data1;
output [31:0] Read_Data2;
input [31:0] Write_Data;
input Reg_Write;
input readAddress1;
input readAddress2;
input writeAddress;
wire EN_out;
wire [31:0] D;
wire [31:0] Q;
and andGate_EN(EN_out,Reg_Write,writeAddress);
generate
genvar j;
for (j=0; j<32; j=j+1) begin : regUnit1
REGISTER_UNIT UNIT(D[j],Q[j],EN_out);
bufif1 buffGate0(Read_Data1[j],Q[j],readAddress1);
bufif1 buffGate1(Read_Data2[j],Q[j],readAddress2);
bufif1 buffGate2(D[j],Write_Data[j],writeAddress);
end
endgenerate
endmodule | 0 |
138,778 | data/full_repos/permissive/85881028/Proc_32.v | 85,881,028 | Proc_32.v | v | 470 | 111 | [] | [] | [] | [(5, 469)] | null | null | 1: b'%Error: data/full_repos/permissive/85881028/Proc_32.v:31: Cannot find file containing module: \'DSP48E1\'\nDSP48E1 #(\n^~~~~~~\n ... Looked in:\n data/full_repos/permissive/85881028,data/full_repos/permissive/85881028/DSP48E1\n data/full_repos/permissive/85881028,data/full_repos/permissive/85881028/DSP48E1.v\n data/full_repos/permissive/85881028,data/full_repos/permissive/85881028/DSP48E1.sv\n DSP48E1\n DSP48E1.v\n DSP48E1.sv\n obj_dir/DSP48E1\n obj_dir/DSP48E1.v\n obj_dir/DSP48E1.sv\n%Error: data/full_repos/permissive/85881028/Proc_32.v:145: Cannot find file containing module: \'DSP48E1\'\nDSP48E1 #(\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/85881028/Proc_32.v:246: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'17\'h0\' generates 17 bits.\n : ... In instance mult35x35_parallel_pipe\n B_IN_3_REG1 <= 17\'b0; end\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/85881028/Proc_32.v:256: Cannot find file containing module: \'DSP48E1\'\n DSP48E1 #(\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/85881028/Proc_32.v:365: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'17\'h0\' generates 17 bits.\n : ... In instance mult35x35_parallel_pipe\n begin A_IN_4_REG1 <= 17\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/85881028/Proc_32.v:366: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'17\'h0\' generates 17 bits.\n : ... In instance mult35x35_parallel_pipe\n A_IN_4_REG2 <= 17\'b0; end\n ^~\n%Error: data/full_repos/permissive/85881028/Proc_32.v:376: Cannot find file containing module: \'DSP48E1\'\n DSP48E1 #(\n ^~~~~~~\n%Error: Exiting due to 4 error(s), 3 warning(s)\n' | 302,788 | module | module mult35x35_parallel_pipe (CLK, RST, A_IN, B_IN, PROD_OUT);
input CLK, RST;
input [34:0] A_IN, B_IN;
output [69:0] PROD_OUT;
wire [17:0] BCOUT_1, BCOUT_3;
wire [47:0] PCOUT_1, PCOUT_2, PCOUT_3;
wire [47:0] POUT_1, POUT_3, POUT_4;
reg [16:0] POUT_1_REG1, POUT_1_REG2, POUT_1_REG3, POUT_3_REG1;
reg [16:0] A_IN_3_REG1;
reg [17:0] A_IN_4_REG1, A_IN_4_REG2, B_IN_3_REG1;
wire [34:0] A_IN_WIRE, B_IN_WIRE;
assign A_IN_WIRE = A_IN;
assign B_IN_WIRE = B_IN;
DSP48E1 #(
.A_INPUT("DIRECT"),
.B_INPUT("DIRECT"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_SIMD("ONE48"),
.AUTORESET_PATDET("NO_RESET"),
.MASK(48'h3fffffffffff),
.PATTERN(48'h000000000000),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_PATTERN_DETECT("NO_PATDET"),
.ACASCREG(1),
.ADREG(1),
.ALUMODEREG(1),
.AREG(1),
.BCASCREG(1),
.BREG(1),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(0),
.INMODEREG(1),
.MREG(1),
.OPMODEREG(0),
.PREG(1)
)
DSP48E1_1 (
.ACOUT(),
.BCOUT(BCOUT_1),
.CARRYCASCOUT(),
.MULTSIGNOUT(),
.PCOUT(PCOUT_1),
.OVERFLOW(),
.PATTERNBDETECT(),
.PATTERNDETECT(),
.UNDERFLOW(),
.CARRYOUT(),
.P(POUT_1),
.ACIN(30'b0),
.BCIN(18'b0),
.CARRYCASCIN(1'b0),
.MULTSIGNIN(),
.PCIN(48'b0),
.ALUMODE(4'b0000),
.CARRYINSEL(3'b0),
.CLK(CLK),
.INMODE(5'b00000),
.OPMODE(7'b0000101),
.A({13'b0,A_IN_WIRE[16:0]}),
.B({1'b0,B_IN_WIRE[16:0]}),
.C(48'b0),
.CARRYIN(1'b0),
.D(25'b0),
.CEA1(1'b0),
.CEA2(1'b1),
.CEAD(1'b0),
.CEALUMODE(1'b1),
.CEB1(1'b1),
.CEB2(1'b1),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b1),
.CED(1'b0),
.CEINMODE(1'b1),
.CEM(1'b1),
.CEP(1'b1),
.RSTA(RST),
.RSTALLCARRYIN(RST),
.RSTALUMODE(RST),
.RSTB(RST),
.RSTC(RST),
.RSTCTRL(RST),
.RSTD(RST),
.RSTINMODE(RST),
.RSTM(RST),
.RSTP(RST)
);
always @ (posedge CLK or posedge RST)
begin
if (RST)
begin POUT_1_REG1 <= 17'b0;
POUT_1_REG2 <= 17'b0;
POUT_1_REG3 <= 17'b0; end
else
begin POUT_1_REG1 <= POUT_1[16:0];
POUT_1_REG2 <= POUT_1_REG1;
POUT_1_REG3 <= POUT_1_REG2; end
end
assign PROD_OUT[16:0] = POUT_1_REG3;
DSP48E1 #(
.A_INPUT("DIRECT"),
.B_INPUT("CASCADE"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_SIMD("ONE48"),
.AUTORESET_PATDET("NO_RESET"),
.MASK(48'h3fffffffffff),
.PATTERN(48'h000000000000),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_PATTERN_DETECT("NO_PATDET"),
.ACASCREG(1),
.ADREG(1),
.ALUMODEREG(1),
.AREG(2),
.BCASCREG(1),
.BREG(1),
.CARRYINREG(0),
.CARRYINSELREG(1),
.CREG(1),
.DREG(1),
.INMODEREG(1),
.MREG(1),
.OPMODEREG(0),
.PREG(1)
)
DSP48E1_2 (
.ACOUT(),
.BCOUT(),
.CARRYCASCOUT(),
.MULTSIGNOUT(),
.PCOUT(PCOUT_2),
.OVERFLOW(),
.PATTERNBDETECT(),
.PATTERNDETECT(),
.UNDERFLOW(),
.CARRYOUT(),
.P(),
.ACIN(30'b0),
.BCIN(BCOUT_1),
.CARRYCASCIN(1'b0),
.MULTSIGNIN(),
.PCIN(PCOUT_1),
.ALUMODE(4'b0000),
.CARRYINSEL(3'b0),
.CLK(CLK),
.INMODE(5'b00000),
.OPMODE(7'b1010101),
.A({12'b0,A_IN[34:17]}),
.B(18'b0),
.C(48'b0),
.CARRYIN(1'b0),
.D(25'b0),
.CEA1(1'b1),
.CEA2(1'b1),
.CEAD(1'b0),
.CEALUMODE(1'b1),
.CEB1(1'b0),
.CEB2(1'b1),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b1),
.CED(1'b0),
.CEINMODE(1'b1),
.CEM(1'b1),
.CEP(1'b1),
.RSTA(RST),
.RSTALLCARRYIN(RST),
.RSTALUMODE(RST),
.RSTB(RST),
.RSTC(RST),
.RSTCTRL(RST),
.RSTD(RST),
.RSTINMODE(RST),
.RSTM(RST),
.RSTP(RST)
);
always @ (posedge CLK or posedge RST)
begin
if (RST)
begin A_IN_3_REG1 <= 17'b0;
B_IN_3_REG1 <= 17'b0; end
else
begin A_IN_3_REG1 <= (A_IN_WIRE[16:0]);
B_IN_3_REG1 <= B_IN_WIRE[34:17]; end
end
DSP48E1 #(
.A_INPUT("DIRECT"),
.B_INPUT("DIRECT"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_SIMD("ONE48"),
.AUTORESET_PATDET("NO_RESET"),
.MASK(48'h3fffffffffff),
.PATTERN(48'h000000000000),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_PATTERN_DETECT("NO_PATDET"),
.ACASCREG(1),
.ADREG(1),
.ALUMODEREG(1),
.AREG(2),
.BCASCREG(1),
.BREG(2),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(0),
.INMODEREG(1),
.MREG(1),
.OPMODEREG(0),
.PREG(1)
)
DSP48E1_3 (
.ACOUT(),
.BCOUT(BCOUT_3),
.CARRYCASCOUT(),
.MULTSIGNOUT(),
.PCOUT(PCOUT_3),
.OVERFLOW(),
.PATTERNBDETECT(),
.PATTERNDETECT(),
.UNDERFLOW(),
.CARRYOUT(),
.P(POUT_3),
.ACIN(30'b0),
.BCIN(18'b0),
.CARRYCASCIN(),
.MULTSIGNIN(),
.PCIN(PCOUT_2),
.ALUMODE(4'b0000),
.CARRYINSEL(3'b0),
.CLK(CLK),
.INMODE(5'b00000),
.OPMODE(7'b0010101),
.A({13'b0,A_IN_3_REG1}),
.B(B_IN_3_REG1),
.C(48'b0),
.CARRYIN(1'b0),
.D(25'b0),
.CEA1(1'b1),
.CEA2(1'b1),
.CEAD(1'b0),
.CEALUMODE(1'b1),
.CEB1(1'b1),
.CEB2(1'b1),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b1),
.CED(1'b0),
.CEINMODE(1'b1),
.CEM(1'b1),
.CEP(1'b1),
.RSTA(RST),
.RSTALLCARRYIN(RST),
.RSTALUMODE(RST),
.RSTB(RST),
.RSTC(RST),
.RSTCTRL(RST),
.RSTD(RST),
.RSTINMODE(RST),
.RSTM(RST),
.RSTP(RST)
);
always @ (posedge CLK or posedge RST)
begin
if (RST)
begin POUT_3_REG1 <= 17'b0; end
else
begin POUT_3_REG1 <= POUT_3[16:0]; end
end
assign PROD_OUT[33:17] = POUT_3_REG1;
always @ (posedge CLK or posedge RST)
begin
if (RST)
begin A_IN_4_REG1 <= 17'b0;
A_IN_4_REG2 <= 17'b0; end
else
begin A_IN_4_REG1 <= A_IN[34:17];
A_IN_4_REG2 <= A_IN_4_REG1; end
end
DSP48E1 #(
.A_INPUT("DIRECT"),
.B_INPUT("CASCADE"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_SIMD("ONE48"),
.AUTORESET_PATDET("NO_RESET"),
.MASK(48'h3fffffffffff),
.PATTERN(48'h000000000000),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_PATTERN_DETECT("NO_PATDET"),
.ACASCREG(1),
.ADREG(1),
.ALUMODEREG(1),
.AREG(2),
.BCASCREG(1),
.BREG(2),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(0),
.INMODEREG(1),
.MREG(1),
.OPMODEREG(0),
.PREG(1)
)
DSP48E1_4 (
.ACOUT(),
.BCOUT(),
.CARRYCASCOUT(),
.MULTSIGNOUT(),
.PCOUT(),
.OVERFLOW(),
.PATTERNBDETECT(),
.PATTERNDETECT(),
.UNDERFLOW(),
.CARRYOUT(),
.P(POUT_4),
.ACIN(30'b0),
.BCIN(BCOUT_3),
.CARRYCASCIN(),
.MULTSIGNIN(),
.PCIN(PCOUT_3),
.ALUMODE(4'b0000),
.CARRYINSEL(3'b0),
.CLK(CLK),
.INMODE(5'b00000),
.OPMODE(7'b1010101),
.A({12'b0,A_IN_4_REG2}),
.B(18'b0),
.C(48'b0),
.CARRYIN(1'b0),
.D(25'b0),
.CEA1(1'b1),
.CEA2(1'b1),
.CEAD(1'b0),
.CEALUMODE(1'b1),
.CEB1(1'b1),
.CEB2(1'b1),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b1),
.CED(1'b0),
.CEINMODE(1'b1),
.CEM(1'b1),
.CEP(1'b1),
.RSTA(RST),
.RSTALLCARRYIN(RST),
.RSTALUMODE(RST),
.RSTB(RST),
.RSTC(RST),
.RSTCTRL(RST),
.RSTD(RST),
.RSTINMODE(RST),
.RSTM(RST),
.RSTP(RST)
);
assign PROD_OUT[69:34] = POUT_4[35:0];
endmodule | module mult35x35_parallel_pipe (CLK, RST, A_IN, B_IN, PROD_OUT); |
input CLK, RST;
input [34:0] A_IN, B_IN;
output [69:0] PROD_OUT;
wire [17:0] BCOUT_1, BCOUT_3;
wire [47:0] PCOUT_1, PCOUT_2, PCOUT_3;
wire [47:0] POUT_1, POUT_3, POUT_4;
reg [16:0] POUT_1_REG1, POUT_1_REG2, POUT_1_REG3, POUT_3_REG1;
reg [16:0] A_IN_3_REG1;
reg [17:0] A_IN_4_REG1, A_IN_4_REG2, B_IN_3_REG1;
wire [34:0] A_IN_WIRE, B_IN_WIRE;
assign A_IN_WIRE = A_IN;
assign B_IN_WIRE = B_IN;
DSP48E1 #(
.A_INPUT("DIRECT"),
.B_INPUT("DIRECT"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_SIMD("ONE48"),
.AUTORESET_PATDET("NO_RESET"),
.MASK(48'h3fffffffffff),
.PATTERN(48'h000000000000),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_PATTERN_DETECT("NO_PATDET"),
.ACASCREG(1),
.ADREG(1),
.ALUMODEREG(1),
.AREG(1),
.BCASCREG(1),
.BREG(1),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(0),
.INMODEREG(1),
.MREG(1),
.OPMODEREG(0),
.PREG(1)
)
DSP48E1_1 (
.ACOUT(),
.BCOUT(BCOUT_1),
.CARRYCASCOUT(),
.MULTSIGNOUT(),
.PCOUT(PCOUT_1),
.OVERFLOW(),
.PATTERNBDETECT(),
.PATTERNDETECT(),
.UNDERFLOW(),
.CARRYOUT(),
.P(POUT_1),
.ACIN(30'b0),
.BCIN(18'b0),
.CARRYCASCIN(1'b0),
.MULTSIGNIN(),
.PCIN(48'b0),
.ALUMODE(4'b0000),
.CARRYINSEL(3'b0),
.CLK(CLK),
.INMODE(5'b00000),
.OPMODE(7'b0000101),
.A({13'b0,A_IN_WIRE[16:0]}),
.B({1'b0,B_IN_WIRE[16:0]}),
.C(48'b0),
.CARRYIN(1'b0),
.D(25'b0),
.CEA1(1'b0),
.CEA2(1'b1),
.CEAD(1'b0),
.CEALUMODE(1'b1),
.CEB1(1'b1),
.CEB2(1'b1),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b1),
.CED(1'b0),
.CEINMODE(1'b1),
.CEM(1'b1),
.CEP(1'b1),
.RSTA(RST),
.RSTALLCARRYIN(RST),
.RSTALUMODE(RST),
.RSTB(RST),
.RSTC(RST),
.RSTCTRL(RST),
.RSTD(RST),
.RSTINMODE(RST),
.RSTM(RST),
.RSTP(RST)
);
always @ (posedge CLK or posedge RST)
begin
if (RST)
begin POUT_1_REG1 <= 17'b0;
POUT_1_REG2 <= 17'b0;
POUT_1_REG3 <= 17'b0; end
else
begin POUT_1_REG1 <= POUT_1[16:0];
POUT_1_REG2 <= POUT_1_REG1;
POUT_1_REG3 <= POUT_1_REG2; end
end
assign PROD_OUT[16:0] = POUT_1_REG3;
DSP48E1 #(
.A_INPUT("DIRECT"),
.B_INPUT("CASCADE"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_SIMD("ONE48"),
.AUTORESET_PATDET("NO_RESET"),
.MASK(48'h3fffffffffff),
.PATTERN(48'h000000000000),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_PATTERN_DETECT("NO_PATDET"),
.ACASCREG(1),
.ADREG(1),
.ALUMODEREG(1),
.AREG(2),
.BCASCREG(1),
.BREG(1),
.CARRYINREG(0),
.CARRYINSELREG(1),
.CREG(1),
.DREG(1),
.INMODEREG(1),
.MREG(1),
.OPMODEREG(0),
.PREG(1)
)
DSP48E1_2 (
.ACOUT(),
.BCOUT(),
.CARRYCASCOUT(),
.MULTSIGNOUT(),
.PCOUT(PCOUT_2),
.OVERFLOW(),
.PATTERNBDETECT(),
.PATTERNDETECT(),
.UNDERFLOW(),
.CARRYOUT(),
.P(),
.ACIN(30'b0),
.BCIN(BCOUT_1),
.CARRYCASCIN(1'b0),
.MULTSIGNIN(),
.PCIN(PCOUT_1),
.ALUMODE(4'b0000),
.CARRYINSEL(3'b0),
.CLK(CLK),
.INMODE(5'b00000),
.OPMODE(7'b1010101),
.A({12'b0,A_IN[34:17]}),
.B(18'b0),
.C(48'b0),
.CARRYIN(1'b0),
.D(25'b0),
.CEA1(1'b1),
.CEA2(1'b1),
.CEAD(1'b0),
.CEALUMODE(1'b1),
.CEB1(1'b0),
.CEB2(1'b1),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b1),
.CED(1'b0),
.CEINMODE(1'b1),
.CEM(1'b1),
.CEP(1'b1),
.RSTA(RST),
.RSTALLCARRYIN(RST),
.RSTALUMODE(RST),
.RSTB(RST),
.RSTC(RST),
.RSTCTRL(RST),
.RSTD(RST),
.RSTINMODE(RST),
.RSTM(RST),
.RSTP(RST)
);
always @ (posedge CLK or posedge RST)
begin
if (RST)
begin A_IN_3_REG1 <= 17'b0;
B_IN_3_REG1 <= 17'b0; end
else
begin A_IN_3_REG1 <= (A_IN_WIRE[16:0]);
B_IN_3_REG1 <= B_IN_WIRE[34:17]; end
end
DSP48E1 #(
.A_INPUT("DIRECT"),
.B_INPUT("DIRECT"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_SIMD("ONE48"),
.AUTORESET_PATDET("NO_RESET"),
.MASK(48'h3fffffffffff),
.PATTERN(48'h000000000000),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_PATTERN_DETECT("NO_PATDET"),
.ACASCREG(1),
.ADREG(1),
.ALUMODEREG(1),
.AREG(2),
.BCASCREG(1),
.BREG(2),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(0),
.INMODEREG(1),
.MREG(1),
.OPMODEREG(0),
.PREG(1)
)
DSP48E1_3 (
.ACOUT(),
.BCOUT(BCOUT_3),
.CARRYCASCOUT(),
.MULTSIGNOUT(),
.PCOUT(PCOUT_3),
.OVERFLOW(),
.PATTERNBDETECT(),
.PATTERNDETECT(),
.UNDERFLOW(),
.CARRYOUT(),
.P(POUT_3),
.ACIN(30'b0),
.BCIN(18'b0),
.CARRYCASCIN(),
.MULTSIGNIN(),
.PCIN(PCOUT_2),
.ALUMODE(4'b0000),
.CARRYINSEL(3'b0),
.CLK(CLK),
.INMODE(5'b00000),
.OPMODE(7'b0010101),
.A({13'b0,A_IN_3_REG1}),
.B(B_IN_3_REG1),
.C(48'b0),
.CARRYIN(1'b0),
.D(25'b0),
.CEA1(1'b1),
.CEA2(1'b1),
.CEAD(1'b0),
.CEALUMODE(1'b1),
.CEB1(1'b1),
.CEB2(1'b1),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b1),
.CED(1'b0),
.CEINMODE(1'b1),
.CEM(1'b1),
.CEP(1'b1),
.RSTA(RST),
.RSTALLCARRYIN(RST),
.RSTALUMODE(RST),
.RSTB(RST),
.RSTC(RST),
.RSTCTRL(RST),
.RSTD(RST),
.RSTINMODE(RST),
.RSTM(RST),
.RSTP(RST)
);
always @ (posedge CLK or posedge RST)
begin
if (RST)
begin POUT_3_REG1 <= 17'b0; end
else
begin POUT_3_REG1 <= POUT_3[16:0]; end
end
assign PROD_OUT[33:17] = POUT_3_REG1;
always @ (posedge CLK or posedge RST)
begin
if (RST)
begin A_IN_4_REG1 <= 17'b0;
A_IN_4_REG2 <= 17'b0; end
else
begin A_IN_4_REG1 <= A_IN[34:17];
A_IN_4_REG2 <= A_IN_4_REG1; end
end
DSP48E1 #(
.A_INPUT("DIRECT"),
.B_INPUT("CASCADE"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_SIMD("ONE48"),
.AUTORESET_PATDET("NO_RESET"),
.MASK(48'h3fffffffffff),
.PATTERN(48'h000000000000),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_PATTERN_DETECT("NO_PATDET"),
.ACASCREG(1),
.ADREG(1),
.ALUMODEREG(1),
.AREG(2),
.BCASCREG(1),
.BREG(2),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(0),
.INMODEREG(1),
.MREG(1),
.OPMODEREG(0),
.PREG(1)
)
DSP48E1_4 (
.ACOUT(),
.BCOUT(),
.CARRYCASCOUT(),
.MULTSIGNOUT(),
.PCOUT(),
.OVERFLOW(),
.PATTERNBDETECT(),
.PATTERNDETECT(),
.UNDERFLOW(),
.CARRYOUT(),
.P(POUT_4),
.ACIN(30'b0),
.BCIN(BCOUT_3),
.CARRYCASCIN(),
.MULTSIGNIN(),
.PCIN(PCOUT_3),
.ALUMODE(4'b0000),
.CARRYINSEL(3'b0),
.CLK(CLK),
.INMODE(5'b00000),
.OPMODE(7'b1010101),
.A({12'b0,A_IN_4_REG2}),
.B(18'b0),
.C(48'b0),
.CARRYIN(1'b0),
.D(25'b0),
.CEA1(1'b1),
.CEA2(1'b1),
.CEAD(1'b0),
.CEALUMODE(1'b1),
.CEB1(1'b1),
.CEB2(1'b1),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b1),
.CED(1'b0),
.CEINMODE(1'b1),
.CEM(1'b1),
.CEP(1'b1),
.RSTA(RST),
.RSTALLCARRYIN(RST),
.RSTALUMODE(RST),
.RSTB(RST),
.RSTC(RST),
.RSTCTRL(RST),
.RSTD(RST),
.RSTINMODE(RST),
.RSTM(RST),
.RSTP(RST)
);
assign PROD_OUT[69:34] = POUT_4[35:0];
endmodule | 2 |
138,779 | data/full_repos/permissive/85881028/test_bench.v | 85,881,028 | test_bench.v | v | 61 | 108 | [] | [] | [] | [(6, 470), (472, 528)] | null | null | 1: b'%Error: data/full_repos/permissive/85881028/test_bench.v:2: Cannot find include file: Proc_32.v\n`include "Proc_32.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85881028,data/full_repos/permissive/85881028/Proc_32.v\n data/full_repos/permissive/85881028,data/full_repos/permissive/85881028/Proc_32.v.v\n data/full_repos/permissive/85881028,data/full_repos/permissive/85881028/Proc_32.v.sv\n Proc_32.v\n Proc_32.v.v\n Proc_32.v.sv\n obj_dir/Proc_32.v\n obj_dir/Proc_32.v.v\n obj_dir/Proc_32.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/85881028/test_bench.v:20: Unsupported: Ignoring delay on this delayed statement.\n #5 clk_tb <= ~ clk_tb;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/85881028/test_bench.v:25: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("mul32.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/85881028/test_bench.v:26: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, testbench);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/85881028/test_bench.v:28: Unsupported: Ignoring delay on this delayed statement.\n#20 rst_tb=0;\n^\n%Error: data/full_repos/permissive/85881028/test_bench.v:38: Too many digits for 32 bit number: 34359738369\n ... As that number was unsized (\'d...) it is limited to 32 bits (IEEE 1800-2017 5.7.1)\n ... Suggest adding a size to it.\nfor (i=34359738369;i<34359738370;i=i+1)begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/85881028/test_bench.v:38: Too many digits for 32 bit number: 34359738370\nfor (i=34359738369;i<34359738370;i=i+1)begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/85881028/test_bench.v:39: Too many digits for 32 bit number: 34359738369\n for (j=34359738369;j<34359738370;j=j+1) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/85881028/test_bench.v:39: Too many digits for 32 bit number: 34359738370\n for (j=34359738369;j<34359738370;j=j+1) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/85881028/test_bench.v:42: Unsupported or unknown PLI call: $monitor\n $monitor($time,"ERROR 101");\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/85881028/test_bench.v:41: Unsupported: Ignoring delay on this delayed statement.\n #170 if(product_tb != k) begin\n ^\n%Error: Exiting due to 8 error(s), 3 warning(s)\n' | 302,789 | module | module testbench;
localparam W=35;
reg clk_tb,rst_tb;
integer i=0,j=0;
reg [W-1:0] a_tb,b_tb;
reg flag;
wire [2*W-1:0] product_tb;
reg [2*W-1:0] k;
mult35x35_parallel_pipe test (.A_IN(a_tb), .B_IN(b_tb), .CLK(clk_tb), .RST(rst_tb), .PROD_OUT(product_tb));
always @ (*) begin
#5 clk_tb <= ~ clk_tb;
end
initial
begin
$dumpfile("mul32.vcd");
$dumpvars(0, testbench);
clk_tb=1; rst_tb=1;i=0;j=0;flag=0;
#20 rst_tb=0;
for (i=34359738369;i<34359738370;i=i+1)begin
for (j=34359738369;j<34359738370;j=j+1) begin
a_tb=i;b_tb=j;k=a_tb*b_tb;
#170 if(product_tb != k) begin
$monitor($time,"ERROR 101");
flag=1;
end
end
end
if (flag==1)
$display($time,"Test failed??");
else
$display($time,"Test successfull!!");
$finish;
end
endmodule | module testbench; |
localparam W=35;
reg clk_tb,rst_tb;
integer i=0,j=0;
reg [W-1:0] a_tb,b_tb;
reg flag;
wire [2*W-1:0] product_tb;
reg [2*W-1:0] k;
mult35x35_parallel_pipe test (.A_IN(a_tb), .B_IN(b_tb), .CLK(clk_tb), .RST(rst_tb), .PROD_OUT(product_tb));
always @ (*) begin
#5 clk_tb <= ~ clk_tb;
end
initial
begin
$dumpfile("mul32.vcd");
$dumpvars(0, testbench);
clk_tb=1; rst_tb=1;i=0;j=0;flag=0;
#20 rst_tb=0;
for (i=34359738369;i<34359738370;i=i+1)begin
for (j=34359738369;j<34359738370;j=j+1) begin
a_tb=i;b_tb=j;k=a_tb*b_tb;
#170 if(product_tb != k) begin
$monitor($time,"ERROR 101");
flag=1;
end
end
end
if (flag==1)
$display($time,"Test failed??");
else
$display($time,"Test successfull!!");
$finish;
end
endmodule | 2 |
138,780 | data/full_repos/permissive/85994503/verilog/fir_srg.v | 85,994,503 | fir_srg.v | v | 37 | 61 | [] | [] | [] | [(5, 36)] | null | data/verilator_xmls/4726bcdd-4513-439d-a911-da41bdc808ed.xml | null | 302,790 | module | module fir_srg
(input clk,
input reset,
input signed [7:0] x,
output reg signed [7:0] y);
reg signed [7:0] tap [0:3];
integer I;
always @(posedge clk or posedge reset)
begin : P1
if (reset) begin
for (I=0; I<=3; I=I+1) tap[I] <= 0;
y <= 0;
end else begin
y <= (tap[1] <<< 1) + tap[1] + (tap[1] >>> 1)- tap[0]
+ ( tap[1] >>> 2) + (tap[2] <<< 1) + tap[2]
+ (tap[2] >>> 1) + (tap[2] >>> 2) - tap[3];
for (I=3; I>0; I=I-1) begin
tap[I] <= tap[I-1];
end
tap[0] <= x;
end
end
endmodule | module fir_srg
(input clk,
input reset,
input signed [7:0] x,
output reg signed [7:0] y); |
reg signed [7:0] tap [0:3];
integer I;
always @(posedge clk or posedge reset)
begin : P1
if (reset) begin
for (I=0; I<=3; I=I+1) tap[I] <= 0;
y <= 0;
end else begin
y <= (tap[1] <<< 1) + tap[1] + (tap[1] >>> 1)- tap[0]
+ ( tap[1] >>> 2) + (tap[2] <<< 1) + tap[2]
+ (tap[2] >>> 1) + (tap[2] >>> 2) - tap[3];
for (I=3; I>0; I=I-1) begin
tap[I] <= tap[I-1];
end
tap[0] <= x;
end
end
endmodule | 0 |
138,781 | data/full_repos/permissive/85994503/verilog/IIC.v | 85,994,503 | IIC.v | v | 117 | 77 | [] | [] | [] | [(2, 115)] | null | data/verilator_xmls/84b260a5-0967-42b6-9795-2f6723eb1a7d.xml | null | 302,791 | module | module IIC(MCLK, RESET, ENABLE, DATA, FINISHED, AUD_SCLK, AUD_SDAT);
input MCLK;
input RESET;
input ENABLE;
input [15:0]DATA;
output AUD_SCLK;
output reg FINISHED;
inout AUD_SDAT;
reg ERROR;
reg [6:0]SD_CONTROL;
reg SDA;
reg SCL;
reg [9:0]COUNT;
initial begin
COUNT = 0;
SD_CONTROL = 0;
SDA = 1;
SCL = 1;
end
assign AUD_SCLK = ((SD_CONTROL >= 4) & (SD_CONTROL < 31))? ~COUNT[9] : SCL;
assign AUD_SDAT = SDA;
always@(posedge MCLK) COUNT = COUNT + 1;
always @ (posedge COUNT[9] or negedge RESET) begin
if(!RESET) begin
SD_CONTROL <= 0;
FINISHED <= 0;
end
else begin
if(!ENABLE) SD_CONTROL <= 0;
else begin
if (SD_CONTROL < 40)SD_CONTROL <= SD_CONTROL + 1;
else SD_CONTROL <= 0;
if(SD_CONTROL == 32) FINISHED <= 1;
else FINISHED <= 0;
end
end
end
always@(posedge COUNT[9] or negedge RESET) begin
if (!RESET) begin
SCL <= 1;
SDA <= 1;
end
else
case (SD_CONTROL)
7'd0 : begin SDA <= 1; SCL <= 1; end
7'd1 : SDA <= 0;
7'd2 : SCL <= 0;
7'd3 : SDA <= 0;
7'd4 : SDA <= 0;
7'd5 : SDA <= 1;
7'd6 : SDA <= 1;
7'd7 : SDA <= 0;
7'd8 : SDA <= 1;
7'd9 : SDA <= 0;
7'd10 : SDA <= 0;
7'd11 : SDA <= 1'bz;
7'd12 : SDA <= DATA[15];
7'd13 : SDA <= DATA[14];
7'd14 : SDA <= DATA[13];
7'd15 : SDA <= DATA[12];
7'd16 : SDA <= DATA[11];
7'd17 : SDA <= DATA[10];
7'd18 : SDA <= DATA[9];
7'd19 : SDA <= DATA[8];
7'd20 : SDA <= 1'bz;
7'd21 : SDA <= DATA[7];
7'd22 : SDA <= DATA[6];
7'd23 : SDA <= DATA[5];
7'd24 : SDA <= DATA[4];
7'd25 : SDA <= DATA[3];
7'd26 : SDA <= DATA[2];
7'd27 : SDA <= DATA[1];
7'd28 : SDA <= DATA[0];
7'd29 : SDA <= 1'bz;
7'd30 : begin SDA <= 0; SCL <=1; end
7'd31 : begin SDA <= 1; end
endcase
end
endmodule | module IIC(MCLK, RESET, ENABLE, DATA, FINISHED, AUD_SCLK, AUD_SDAT); |
input MCLK;
input RESET;
input ENABLE;
input [15:0]DATA;
output AUD_SCLK;
output reg FINISHED;
inout AUD_SDAT;
reg ERROR;
reg [6:0]SD_CONTROL;
reg SDA;
reg SCL;
reg [9:0]COUNT;
initial begin
COUNT = 0;
SD_CONTROL = 0;
SDA = 1;
SCL = 1;
end
assign AUD_SCLK = ((SD_CONTROL >= 4) & (SD_CONTROL < 31))? ~COUNT[9] : SCL;
assign AUD_SDAT = SDA;
always@(posedge MCLK) COUNT = COUNT + 1;
always @ (posedge COUNT[9] or negedge RESET) begin
if(!RESET) begin
SD_CONTROL <= 0;
FINISHED <= 0;
end
else begin
if(!ENABLE) SD_CONTROL <= 0;
else begin
if (SD_CONTROL < 40)SD_CONTROL <= SD_CONTROL + 1;
else SD_CONTROL <= 0;
if(SD_CONTROL == 32) FINISHED <= 1;
else FINISHED <= 0;
end
end
end
always@(posedge COUNT[9] or negedge RESET) begin
if (!RESET) begin
SCL <= 1;
SDA <= 1;
end
else
case (SD_CONTROL)
7'd0 : begin SDA <= 1; SCL <= 1; end
7'd1 : SDA <= 0;
7'd2 : SCL <= 0;
7'd3 : SDA <= 0;
7'd4 : SDA <= 0;
7'd5 : SDA <= 1;
7'd6 : SDA <= 1;
7'd7 : SDA <= 0;
7'd8 : SDA <= 1;
7'd9 : SDA <= 0;
7'd10 : SDA <= 0;
7'd11 : SDA <= 1'bz;
7'd12 : SDA <= DATA[15];
7'd13 : SDA <= DATA[14];
7'd14 : SDA <= DATA[13];
7'd15 : SDA <= DATA[12];
7'd16 : SDA <= DATA[11];
7'd17 : SDA <= DATA[10];
7'd18 : SDA <= DATA[9];
7'd19 : SDA <= DATA[8];
7'd20 : SDA <= 1'bz;
7'd21 : SDA <= DATA[7];
7'd22 : SDA <= DATA[6];
7'd23 : SDA <= DATA[5];
7'd24 : SDA <= DATA[4];
7'd25 : SDA <= DATA[3];
7'd26 : SDA <= DATA[2];
7'd27 : SDA <= DATA[1];
7'd28 : SDA <= DATA[0];
7'd29 : SDA <= 1'bz;
7'd30 : begin SDA <= 0; SCL <=1; end
7'd31 : begin SDA <= 1; end
endcase
end
endmodule | 0 |
138,782 | data/full_repos/permissive/86135381/io_calibration.v | 86,135,381 | io_calibration.v | v | 73 | 85 | [] | [] | [] | [(16, 72)] | null | data/verilator_xmls/12a4acc9-af5f-45be-8a6e-0b72a8a25e21.xml | null | 302,792 | module | module io_calibration (
input wire rst,
input wire clk,
input wire start,
input wire [13:0] adc,
output wire ce,
output wire done);
localparam IDLE = 5'b00001,
INIT = 5'b00010,
CHECK = 5'b00100,
ERROR = 5'b01000,
DONE = 5'b10000;
wire mismatch;
reg [13:0] buffer;
reg [13:0] prev;
reg [13:0] count;
reg [4:0] state;
reg [4:0] next_state;
always @(posedge clk)
if (rst == 1) state <= IDLE;
else state <= next_state;
always @(*) begin
next_state = state;
case (state)
IDLE : if (start == 1) next_state = INIT;
INIT : if (count == 4) next_state = CHECK;
CHECK : if (mismatch == 1) next_state = ERROR;
else if (count == 2000) next_state = DONE;
ERROR : next_state = INIT;
DONE : next_state = DONE;
default : next_state = IDLE;
endcase
end
assign ce = state == ERROR;
assign done = state == DONE;
assign mismatch = buffer != prev + 1;
always @(posedge clk)
if (rst == 1) begin
prev <= 0;
count <= 0;
buffer <= 0;
end else begin
prev <= buffer;
count <= (state == INIT || state == CHECK) ? count + 1 : 0;
buffer <= adc;
end
endmodule | module io_calibration (
input wire rst,
input wire clk,
input wire start,
input wire [13:0] adc,
output wire ce,
output wire done); |
localparam IDLE = 5'b00001,
INIT = 5'b00010,
CHECK = 5'b00100,
ERROR = 5'b01000,
DONE = 5'b10000;
wire mismatch;
reg [13:0] buffer;
reg [13:0] prev;
reg [13:0] count;
reg [4:0] state;
reg [4:0] next_state;
always @(posedge clk)
if (rst == 1) state <= IDLE;
else state <= next_state;
always @(*) begin
next_state = state;
case (state)
IDLE : if (start == 1) next_state = INIT;
INIT : if (count == 4) next_state = CHECK;
CHECK : if (mismatch == 1) next_state = ERROR;
else if (count == 2000) next_state = DONE;
ERROR : next_state = INIT;
DONE : next_state = DONE;
default : next_state = IDLE;
endcase
end
assign ce = state == ERROR;
assign done = state == DONE;
assign mismatch = buffer != prev + 1;
always @(posedge clk)
if (rst == 1) begin
prev <= 0;
count <= 0;
buffer <= 0;
end else begin
prev <= buffer;
count <= (state == INIT || state == CHECK) ? count + 1 : 0;
buffer <= adc;
end
endmodule | 0 |
138,783 | data/full_repos/permissive/86135381/io_i2c.v | 86,135,381 | io_i2c.v | v | 167 | 81 | [] | [] | [] | [(1, 166)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/86135381/io_i2c.v:66: Operator EQ expects 32 or 28 bits on the LHS, but LHS\'s VARREF \'count_clk\' generates 8 bits.\n : ... In instance i2c_master\n end else if (count_clk == MAX_COUNT_CLK) begin\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/86135381/io_i2c.v:73: Operator EQ expects 32 or 28 bits on the LHS, but LHS\'s VARREF \'count_clk\' generates 8 bits.\n : ... In instance i2c_master\n if (count_clk == MAX_COUNT_CLK && count_quad == 0) data_ce <= 1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/86135381/io_i2c.v:86: Bit extraction of var[7:0] requires 3 bit index, not 8 bits.\n : ... In instance i2c_master\n assign sda_int = (state == COMMAND) ? addr_rw[bit_count] :\n ^\n%Warning-WIDTH: data/full_repos/permissive/86135381/io_i2c.v:87: Bit extraction of var[7:0] requires 3 bit index, not 8 bits.\n : ... In instance i2c_master\n (state == WR) ? data_tx[bit_count] :\n ^\n%Warning-WIDTH: data/full_repos/permissive/86135381/io_i2c.v:95: Operator EQ expects 32 or 28 bits on the LHS, but LHS\'s VARREF \'count_clk\' generates 8 bits.\n : ... In instance i2c_master\n if (count_clk == MAX_COUNT_CLK && count_quad == 1) scl_ce <= 1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/86135381/io_i2c.v:163: Bit extraction of var[7:0] requires 3 bit index, not 8 bits.\n : ... In instance i2c_master\n if (state == RD) data_rx[bit_count] <= sda;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 302,793 | module | module i2c_master #(
parameter input_clk = 200_000_000,
parameter bus_clk = 400_000
) (
input clk,
input rst,
input ena,
input [6:0] addr,
input rw,
input [7:0] data_wr,
output busy,
output load,
output reg [7:0] data_rd,
inout sda,
inout scl);
localparam MAX_COUNT_CLK = input_clk/bus_clk/4;
localparam READY = 9'b000000001;
localparam START = 9'b000000010;
localparam COMMAND = 9'b000000100;
localparam SLV_ACK1 = 9'b000001000;
localparam WR = 9'b000010000;
localparam RD = 9'b000100000;
localparam SLV_ACK2 = 9'b001000000;
localparam MSTR_ACK = 9'b010000000;
localparam STOP = 9'b100000000;
reg rst_lcl;
reg [8:0] state;
reg [8:0] next_state;
wire same_cmd;
reg [7:0] count_clk;
reg [1:0] count_quad;
reg data_ce;
wire stretching;
reg scl_ce;
reg scl_ena;
wire sda_int;
wire sda_ena_n;
reg [7:0] addr_rw;
reg [7:0] data_tx;
reg [7:0] data_rx;
reg [7:0] bit_count;
reg [7:0] data_rd_buf;
always @(posedge clk)
rst_lcl <= rst;
always @(posedge clk)
if (rst_lcl) begin
count_clk <= 0;
count_quad <= 0;
end else if (count_clk == MAX_COUNT_CLK) begin
count_clk <= 0;
count_quad <= count_quad + 1;
end else if (stretching == 0)
count_clk <= count_clk + 1;
always @(posedge clk) begin
if (count_clk == MAX_COUNT_CLK && count_quad == 0) data_ce <= 1;
else data_ce <= 0;
end
assign stretching = (count_quad == 2'b10) && (scl == 0);
assign sda = (sda_ena_n == 0) ? 0 : 1'bZ;
assign sda_ena_n = (state == START || state == STOP) ? 0 : sda_int;
assign sda_int = (state == COMMAND) ? addr_rw[bit_count] :
(state == WR) ? data_tx[bit_count] :
(state == MSTR_ACK && same_cmd) ? 0 : 1;
always @(posedge clk) begin
if (count_clk == MAX_COUNT_CLK && count_quad == 1) scl_ce <= 1;
else scl_ce <= 0;
end
always @(posedge clk)
if (rst_lcl) scl_ena <= 0;
else if (scl_ce) scl_ena <= (state & (READY | STOP)) == 0;
assign scl = (scl_ena == 1 && count_quad[1] == 0) ? 0 : 1'bZ;
always @(posedge clk)
if (rst_lcl) state <= READY;
else if (data_ce) state <= next_state;
always @(*) begin
next_state = state;
case (state)
READY: if (ena == 1) next_state = START;
START: next_state = COMMAND;
COMMAND: if (bit_count == 0) next_state = SLV_ACK1;
SLV_ACK1: if (addr_rw[0] == 0) next_state = WR;
else next_state = RD;
WR: if (bit_count == 0) next_state = SLV_ACK2;
RD: if (bit_count == 0) next_state = MSTR_ACK;
SLV_ACK2: if (ena == 1)
if (same_cmd == 1) next_state = WR;
else next_state = START;
else next_state = STOP;
MSTR_ACK: if (ena == 1)
if (same_cmd == 1) next_state = WR;
else next_state = START;
else next_state = STOP;
STOP: next_state = READY;
endcase
end
assign busy = state != READY;
assign load = state == SLV_ACK2;
assign same_cmd = addr_rw == {addr,rw};
always @(posedge clk)
if (data_ce)
if (state == COMMAND || state == RD || state == WR)
bit_count <= bit_count - 1;
else bit_count <= 7;
always @(posedge clk)
if (data_ce) begin
if (state == START) addr_rw <= {addr,rw};
if (state == SLV_ACK1 || state == SLV_ACK2) data_tx <= data_wr;
end
always @(posedge clk)
if (rst_lcl) data_rd <= 0;
else if (data_ce) begin
if (state == MSTR_ACK) data_rd <= data_rx;
if (state == RD) data_rx[bit_count] <= sda;
end
endmodule | module i2c_master #(
parameter input_clk = 200_000_000,
parameter bus_clk = 400_000
) (
input clk,
input rst,
input ena,
input [6:0] addr,
input rw,
input [7:0] data_wr,
output busy,
output load,
output reg [7:0] data_rd,
inout sda,
inout scl); |
localparam MAX_COUNT_CLK = input_clk/bus_clk/4;
localparam READY = 9'b000000001;
localparam START = 9'b000000010;
localparam COMMAND = 9'b000000100;
localparam SLV_ACK1 = 9'b000001000;
localparam WR = 9'b000010000;
localparam RD = 9'b000100000;
localparam SLV_ACK2 = 9'b001000000;
localparam MSTR_ACK = 9'b010000000;
localparam STOP = 9'b100000000;
reg rst_lcl;
reg [8:0] state;
reg [8:0] next_state;
wire same_cmd;
reg [7:0] count_clk;
reg [1:0] count_quad;
reg data_ce;
wire stretching;
reg scl_ce;
reg scl_ena;
wire sda_int;
wire sda_ena_n;
reg [7:0] addr_rw;
reg [7:0] data_tx;
reg [7:0] data_rx;
reg [7:0] bit_count;
reg [7:0] data_rd_buf;
always @(posedge clk)
rst_lcl <= rst;
always @(posedge clk)
if (rst_lcl) begin
count_clk <= 0;
count_quad <= 0;
end else if (count_clk == MAX_COUNT_CLK) begin
count_clk <= 0;
count_quad <= count_quad + 1;
end else if (stretching == 0)
count_clk <= count_clk + 1;
always @(posedge clk) begin
if (count_clk == MAX_COUNT_CLK && count_quad == 0) data_ce <= 1;
else data_ce <= 0;
end
assign stretching = (count_quad == 2'b10) && (scl == 0);
assign sda = (sda_ena_n == 0) ? 0 : 1'bZ;
assign sda_ena_n = (state == START || state == STOP) ? 0 : sda_int;
assign sda_int = (state == COMMAND) ? addr_rw[bit_count] :
(state == WR) ? data_tx[bit_count] :
(state == MSTR_ACK && same_cmd) ? 0 : 1;
always @(posedge clk) begin
if (count_clk == MAX_COUNT_CLK && count_quad == 1) scl_ce <= 1;
else scl_ce <= 0;
end
always @(posedge clk)
if (rst_lcl) scl_ena <= 0;
else if (scl_ce) scl_ena <= (state & (READY | STOP)) == 0;
assign scl = (scl_ena == 1 && count_quad[1] == 0) ? 0 : 1'bZ;
always @(posedge clk)
if (rst_lcl) state <= READY;
else if (data_ce) state <= next_state;
always @(*) begin
next_state = state;
case (state)
READY: if (ena == 1) next_state = START;
START: next_state = COMMAND;
COMMAND: if (bit_count == 0) next_state = SLV_ACK1;
SLV_ACK1: if (addr_rw[0] == 0) next_state = WR;
else next_state = RD;
WR: if (bit_count == 0) next_state = SLV_ACK2;
RD: if (bit_count == 0) next_state = MSTR_ACK;
SLV_ACK2: if (ena == 1)
if (same_cmd == 1) next_state = WR;
else next_state = START;
else next_state = STOP;
MSTR_ACK: if (ena == 1)
if (same_cmd == 1) next_state = WR;
else next_state = START;
else next_state = STOP;
STOP: next_state = READY;
endcase
end
assign busy = state != READY;
assign load = state == SLV_ACK2;
assign same_cmd = addr_rw == {addr,rw};
always @(posedge clk)
if (data_ce)
if (state == COMMAND || state == RD || state == WR)
bit_count <= bit_count - 1;
else bit_count <= 7;
always @(posedge clk)
if (data_ce) begin
if (state == START) addr_rw <= {addr,rw};
if (state == SLV_ACK1 || state == SLV_ACK2) data_tx <= data_wr;
end
always @(posedge clk)
if (rst_lcl) data_rd <= 0;
else if (data_ce) begin
if (state == MSTR_ACK) data_rd <= data_rx;
if (state == RD) data_rx[bit_count] <= sda;
end
endmodule | 0 |
138,784 | data/full_repos/permissive/86135381/io_init.v | 86,135,381 | io_init.v | v | 116 | 81 | [] | [] | [] | [(1, 115)] | null | null | 1: b"%Error: data/full_repos/permissive/86135381/io_init.v:73: Cannot find file containing module: 'io_init_clock'\n io_init_clock clock_init (rst, clk, init_cdce_ena, init_cdce_done, \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/io_init_clock\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/io_init_clock.v\n data/full_repos/permissive/86135381,data/full_repos/permissive/86135381/io_init_clock.sv\n io_init_clock\n io_init_clock.v\n io_init_clock.sv\n obj_dir/io_init_clock\n obj_dir/io_init_clock.v\n obj_dir/io_init_clock.sv\n%Error: data/full_repos/permissive/86135381/io_init.v:77: Cannot find file containing module: 'io_init_adc'\n io_init_adc adc_init (rst, clk, init_adc_ena, init_ads_done, \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86135381/io_init.v:80: Cannot find file containing module: 'io_init_dac'\n io_init_dac dac_init (rst, clk, init_dac_ena, init_dac_done, \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/86135381/io_init.v:83: Cannot find file containing module: 'io_init_monitor'\n io_init_monitor monitor_init (rst, clk, init_mon_ena, init_amc_done, \n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 302,794 | module | module io_init (
input wire rst,
input wire clk,
input wire init_ena,
output reg spi_sclk,
output reg spi_sdata,
output wire cdce_n_en,
input wire cdce_miso,
output wire cdce_n_reset,
output wire cdce_n_pd,
output wire ref_en,
output wire ads_n_en,
output wire adc_reset,
output wire dac_n_en,
output wire amc_n_en,
output wire mon_n_rst,
output wire init_done,
output wire start_calibration,
input wire adc_calibrated);
localparam IDLE = 8'b00000001;
localparam INIT_CDCE = 8'b00000010;
localparam INIT_ADC = 8'b00000100;
localparam INIT_DAC = 8'b00001000;
localparam INIT_MON = 8'b00010000;
localparam FINISHED = 8'b00100000;
localparam CALIBRATE = 8'b01000000;
localparam ADC_AGAIN = 8'b10000000;
reg [7:0] state, next_state;
wire cdce_spi_sclk, cdce_spi_sdata, init_cdce_done,
ads_spi_sclk, ads_spi_sdata, init_ads_done,
dac_spi_sclk, dac_spi_sdata, init_dac_done,
amc_spi_sdata, amc_spi_sclk, init_amc_done,
init_cdce_ena, init_adc_ena, init_dac_ena, init_mon_ena;
always @(*) begin
spi_sclk = 0;
spi_sdata = 0;
case (state)
INIT_CDCE : begin
spi_sclk = cdce_spi_sclk;
spi_sdata = cdce_spi_sdata;
end
INIT_ADC : begin
spi_sclk = ads_spi_sclk;
spi_sdata = ads_spi_sdata;
end
INIT_DAC : begin
spi_sclk = dac_spi_sclk;
spi_sdata = dac_spi_sdata;
end
INIT_MON : begin
spi_sclk = amc_spi_sclk;
spi_sdata = amc_spi_sdata;
end
ADC_AGAIN : begin
spi_sclk = ads_spi_sclk;
spi_sdata = ads_spi_sdata;
end
endcase
end
io_init_clock clock_init (rst, clk, init_cdce_ena, init_cdce_done,
cdce_spi_sclk, cdce_spi_sdata, cdce_n_en, cdce_miso, ref_en,
cdce_n_reset, cdce_n_pd);
io_init_adc adc_init (rst, clk, init_adc_ena, init_ads_done,
ads_spi_sclk, ads_spi_sdata, ads_n_en, adc_reset, adc_calibrated);
io_init_dac dac_init (rst, clk, init_dac_ena, init_dac_done,
dac_spi_sclk, dac_spi_sdata, dac_n_en);
io_init_monitor monitor_init (rst, clk, init_mon_ena, init_amc_done,
amc_spi_sclk, amc_spi_sdata, amc_n_en, mon_n_rst);
always @(posedge clk)
if (rst) state <= IDLE;
else state <= next_state;
always @(*) begin
next_state = state;
case (state)
IDLE : if (init_ena == 1) next_state = INIT_CDCE;
INIT_CDCE : if (init_cdce_done == 1) next_state = INIT_ADC;
INIT_ADC : if (init_ads_done == 1) next_state = INIT_DAC;
INIT_DAC : if (init_dac_done == 1) next_state = INIT_MON;
INIT_MON : if (init_amc_done == 1) next_state = CALIBRATE;
CALIBRATE : if (adc_calibrated == 1) next_state = ADC_AGAIN;
ADC_AGAIN : if (init_ads_done == 1) next_state = FINISHED;
FINISHED : if (init_ena == 0) next_state = IDLE;
default : next_state = IDLE;
endcase
end
assign init_cdce_ena = state == INIT_CDCE;
assign init_adc_ena = state == INIT_ADC || state == ADC_AGAIN;
assign init_dac_ena = state == INIT_DAC;
assign init_mon_ena = state == INIT_MON;
assign init_done = state == FINISHED;
assign start_calibration = state == CALIBRATE;
endmodule | module io_init (
input wire rst,
input wire clk,
input wire init_ena,
output reg spi_sclk,
output reg spi_sdata,
output wire cdce_n_en,
input wire cdce_miso,
output wire cdce_n_reset,
output wire cdce_n_pd,
output wire ref_en,
output wire ads_n_en,
output wire adc_reset,
output wire dac_n_en,
output wire amc_n_en,
output wire mon_n_rst,
output wire init_done,
output wire start_calibration,
input wire adc_calibrated); |
localparam IDLE = 8'b00000001;
localparam INIT_CDCE = 8'b00000010;
localparam INIT_ADC = 8'b00000100;
localparam INIT_DAC = 8'b00001000;
localparam INIT_MON = 8'b00010000;
localparam FINISHED = 8'b00100000;
localparam CALIBRATE = 8'b01000000;
localparam ADC_AGAIN = 8'b10000000;
reg [7:0] state, next_state;
wire cdce_spi_sclk, cdce_spi_sdata, init_cdce_done,
ads_spi_sclk, ads_spi_sdata, init_ads_done,
dac_spi_sclk, dac_spi_sdata, init_dac_done,
amc_spi_sdata, amc_spi_sclk, init_amc_done,
init_cdce_ena, init_adc_ena, init_dac_ena, init_mon_ena;
always @(*) begin
spi_sclk = 0;
spi_sdata = 0;
case (state)
INIT_CDCE : begin
spi_sclk = cdce_spi_sclk;
spi_sdata = cdce_spi_sdata;
end
INIT_ADC : begin
spi_sclk = ads_spi_sclk;
spi_sdata = ads_spi_sdata;
end
INIT_DAC : begin
spi_sclk = dac_spi_sclk;
spi_sdata = dac_spi_sdata;
end
INIT_MON : begin
spi_sclk = amc_spi_sclk;
spi_sdata = amc_spi_sdata;
end
ADC_AGAIN : begin
spi_sclk = ads_spi_sclk;
spi_sdata = ads_spi_sdata;
end
endcase
end
io_init_clock clock_init (rst, clk, init_cdce_ena, init_cdce_done,
cdce_spi_sclk, cdce_spi_sdata, cdce_n_en, cdce_miso, ref_en,
cdce_n_reset, cdce_n_pd);
io_init_adc adc_init (rst, clk, init_adc_ena, init_ads_done,
ads_spi_sclk, ads_spi_sdata, ads_n_en, adc_reset, adc_calibrated);
io_init_dac dac_init (rst, clk, init_dac_ena, init_dac_done,
dac_spi_sclk, dac_spi_sdata, dac_n_en);
io_init_monitor monitor_init (rst, clk, init_mon_ena, init_amc_done,
amc_spi_sclk, amc_spi_sdata, amc_n_en, mon_n_rst);
always @(posedge clk)
if (rst) state <= IDLE;
else state <= next_state;
always @(*) begin
next_state = state;
case (state)
IDLE : if (init_ena == 1) next_state = INIT_CDCE;
INIT_CDCE : if (init_cdce_done == 1) next_state = INIT_ADC;
INIT_ADC : if (init_ads_done == 1) next_state = INIT_DAC;
INIT_DAC : if (init_dac_done == 1) next_state = INIT_MON;
INIT_MON : if (init_amc_done == 1) next_state = CALIBRATE;
CALIBRATE : if (adc_calibrated == 1) next_state = ADC_AGAIN;
ADC_AGAIN : if (init_ads_done == 1) next_state = FINISHED;
FINISHED : if (init_ena == 0) next_state = IDLE;
default : next_state = IDLE;
endcase
end
assign init_cdce_ena = state == INIT_CDCE;
assign init_adc_ena = state == INIT_ADC || state == ADC_AGAIN;
assign init_dac_ena = state == INIT_DAC;
assign init_mon_ena = state == INIT_MON;
assign init_done = state == FINISHED;
assign start_calibration = state == CALIBRATE;
endmodule | 0 |
Subsets and Splits
No saved queries yet
Save your SQL queries to embed, download, and access them later. Queries will appear here once saved.