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138,493 | data/full_repos/permissive/84007307/MUX4.v | 84,007,307 | MUX4.v | v | 49 | 83 | [] | [] | [] | null | line:21: before: "primitive" | data/verilator_xmls/a7d9b5a9-46b5-46c7-a36f-ebc2d196de24.xml | null | 302,440 | module | module MUX4(
input [3:0] in,
input [1:0] sel,
output out
);
MUX4_UDP m(out,in[3],in[2],in[1],in[0], sel[1],sel[0]);
endmodule | module MUX4(
input [3:0] in,
input [1:0] sel,
output out
); |
MUX4_UDP m(out,in[3],in[2],in[1],in[0], sel[1],sel[0]);
endmodule | 0 |
138,494 | data/full_repos/permissive/84007307/NAND.v | 84,007,307 | NAND.v | v | 29 | 83 | [] | [] | [] | null | line:26: before: "(" | data/verilator_xmls/49ebf1ff-5a88-4322-9fd9-d66dc083cafb.xml | null | 302,441 | module | module NAND(
input in1,
input in2,
output out
);
buf#(2) (out,~(in1 & in2));
endmodule | module NAND(
input in1,
input in2,
output out
); |
buf#(2) (out,~(in1 & in2));
endmodule | 0 |
138,495 | data/full_repos/permissive/84007307/NOR.v | 84,007,307 | NOR.v | v | 30 | 83 | [] | [] | [] | null | line:27: before: "(" | data/verilator_xmls/5416af5a-782d-4cb2-8f8b-4affeed3ef26.xml | null | 302,442 | module | module NOR(
input in1,
input in2,
output out
);
buf#(3,2) (out,~(in1 | in2));
endmodule | module NOR(
input in1,
input in2,
output out
); |
buf#(3,2) (out,~(in1 | in2));
endmodule | 0 |
138,496 | data/full_repos/permissive/84007307/REG32.v | 84,007,307 | REG32.v | v | 39 | 83 | [] | [] | [] | null | line:33: before: ")" | null | 1: b"%Error: data/full_repos/permissive/84007307/REG32.v:33: Cannot find file containing module: 'DFF'\n DFF d(clk,in[i],R,out[i] , );\n ^~~\n ... Looked in:\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/DFF\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/DFF.v\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/DFF.sv\n DFF\n DFF.v\n DFF.sv\n obj_dir/DFF\n obj_dir/DFF.v\n obj_dir/DFF.sv\n%Error: Exiting due to 1 error(s)\n" | 302,443 | module | module REG32(
input [31:0] in,
input clk,
input R,
output [31:0] out
);
generate
genvar i;
for (i=0; i < 32; i=i+1) begin: d
DFF d(clk,in[i],R,out[i] , );
end
endgenerate
endmodule | module REG32(
input [31:0] in,
input clk,
input R,
output [31:0] out
); |
generate
genvar i;
for (i=0; i < 32; i=i+1) begin: d
DFF d(clk,in[i],R,out[i] , );
end
endgenerate
endmodule | 0 |
138,497 | data/full_repos/permissive/84007307/testDFF.v | 84,007,307 | testDFF.v | v | 86 | 81 | [] | [] | [] | [(25, 84)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/84007307/testDFF.v:48: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testDFF.v:50: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testDFF.v:58: Unsupported: Ignoring delay on this delayed statement.\n #249; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testDFF.v:62: Unsupported: Ignoring delay on this delayed statement.\n #300; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testDFF.v:66: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testDFF.v:70: Unsupported: Ignoring delay on this delayed statement.\n #400; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testDFF.v:74: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testDFF.v:78: Unsupported: Ignoring delay on this delayed statement.\n #200; \n ^\n%Error: data/full_repos/permissive/84007307/testDFF.v:37: Cannot find file containing module: \'DFF\'\n DFF dut (\n ^~~\n ... Looked in:\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/DFF\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/DFF.v\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/DFF.sv\n DFF\n DFF.v\n DFF.sv\n obj_dir/DFF\n obj_dir/DFF.v\n obj_dir/DFF.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,444 | module | module testDFF;
reg clk;
reg D;
reg R;
wire Q;
wire not_Q;
DFF dut (
.clk(clk),
.D(D),
.R(R),
.Q(Q),
.not_Q(not_Q)
);
always begin
clk = 0;
#100;
clk = 1;
#100;
end
initial begin
D = 0;
R = 1;
#249;
D = 1;
R = 0;
#300;
D = 0;
R = 0;
#200;
D = 1;
R = 0;
#400;
D = 0;
R = 1;
#200;
D = 0;
R = 0;
#200;
D = 1;
R = 0;
end
endmodule | module testDFF; |
reg clk;
reg D;
reg R;
wire Q;
wire not_Q;
DFF dut (
.clk(clk),
.D(D),
.R(R),
.Q(Q),
.not_Q(not_Q)
);
always begin
clk = 0;
#100;
clk = 1;
#100;
end
initial begin
D = 0;
R = 1;
#249;
D = 1;
R = 0;
#300;
D = 0;
R = 0;
#200;
D = 1;
R = 0;
#400;
D = 0;
R = 1;
#200;
D = 0;
R = 0;
#200;
D = 1;
R = 0;
end
endmodule | 0 |
138,498 | data/full_repos/permissive/84007307/testDNlatch_NAND.v | 84,007,307 | testDNlatch_NAND.v | v | 92 | 81 | [] | [] | [] | [(25, 90)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/84007307/testDNlatch_NAND.v:49: Unsupported: Ignoring delay on this delayed statement.\n #50; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testDNlatch_NAND.v:54: Unsupported: Ignoring delay on this delayed statement.\n #50; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testDNlatch_NAND.v:59: Unsupported: Ignoring delay on this delayed statement.\n #50; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testDNlatch_NAND.v:64: Unsupported: Ignoring delay on this delayed statement.\n #50; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testDNlatch_NAND.v:69: Unsupported: Ignoring delay on this delayed statement.\n #50; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testDNlatch_NAND.v:73: Unsupported: Ignoring delay on this delayed statement.\n #50; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testDNlatch_NAND.v:77: Unsupported: Ignoring delay on this delayed statement.\n #50; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testDNlatch_NAND.v:81: Unsupported: Ignoring delay on this delayed statement.\n #50; \n ^\n%Error: data/full_repos/permissive/84007307/testDNlatch_NAND.v:36: Cannot find file containing module: \'DNlatch_NAND\'\n DNlatch_NAND dut (\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/DNlatch_NAND\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/DNlatch_NAND.v\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/DNlatch_NAND.sv\n DNlatch_NAND\n DNlatch_NAND.v\n DNlatch_NAND.sv\n obj_dir/DNlatch_NAND\n obj_dir/DNlatch_NAND.v\n obj_dir/DNlatch_NAND.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,447 | module | module testDNlatch_NAND;
reg En;
reg D;
wire Q;
wire not_Q;
DNlatch_NAND dut (
.En(En),
.D(D),
.Q(Q),
.not_Q(not_Q)
);
initial begin
En = 1;
D = 0;
#50;
En = 0;
D = 0;
#50;
En = 0;
D = 1;
#50;
En = 0;
D = 0;
#50;
En = 1;
D = 0;
#50;
En = 1;
D = 1;
#50;
En = 0;
D = 1;
#50;
En = 1;
D = 0;
#50;
En = 1;
D = 1;
end
endmodule | module testDNlatch_NAND; |
reg En;
reg D;
wire Q;
wire not_Q;
DNlatch_NAND dut (
.En(En),
.D(D),
.Q(Q),
.not_Q(not_Q)
);
initial begin
En = 1;
D = 0;
#50;
En = 0;
D = 0;
#50;
En = 0;
D = 1;
#50;
En = 0;
D = 0;
#50;
En = 1;
D = 0;
#50;
En = 1;
D = 1;
#50;
En = 0;
D = 1;
#50;
En = 1;
D = 0;
#50;
En = 1;
D = 1;
end
endmodule | 0 |
138,499 | data/full_repos/permissive/84007307/testFULL_ADDER.v | 84,007,307 | testFULL_ADDER.v | v | 92 | 81 | [] | [] | [] | [(25, 90)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/84007307/testFULL_ADDER.v:51: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testFULL_ADDER.v:56: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testFULL_ADDER.v:61: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testFULL_ADDER.v:66: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testFULL_ADDER.v:71: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testFULL_ADDER.v:76: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testFULL_ADDER.v:81: Unsupported: Ignoring delay on this delayed statement.\n #30;\n ^\n%Error: data/full_repos/permissive/84007307/testFULL_ADDER.v:37: Cannot find file containing module: \'FULL_ADDER\'\n FULL_ADDER dut (\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/FULL_ADDER\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/FULL_ADDER.v\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/FULL_ADDER.sv\n FULL_ADDER\n FULL_ADDER.v\n FULL_ADDER.sv\n obj_dir/FULL_ADDER\n obj_dir/FULL_ADDER.v\n obj_dir/FULL_ADDER.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,449 | module | module testFULL_ADDER;
reg A;
reg B;
reg Ci;
wire S;
wire Co;
FULL_ADDER dut (
.A(A),
.B(B),
.Ci(Ci),
.S(S),
.Co(Co)
);
initial begin
A = 0;
B = 0;
Ci = 0;
#30;
A = 0;
B = 0;
Ci = 1;
#30;
A = 0;
B = 1;
Ci = 0;
#30;
A = 0;
B = 1;
Ci = 1;
#30;
A = 1;
B = 0;
Ci = 0;
#30;
A = 1;
B = 0;
Ci = 1;
#30;
A = 1;
B =1;
Ci = 0;
#30;
A = 1;
B = 1;
Ci = 1;
end
endmodule | module testFULL_ADDER; |
reg A;
reg B;
reg Ci;
wire S;
wire Co;
FULL_ADDER dut (
.A(A),
.B(B),
.Ci(Ci),
.S(S),
.Co(Co)
);
initial begin
A = 0;
B = 0;
Ci = 0;
#30;
A = 0;
B = 0;
Ci = 1;
#30;
A = 0;
B = 1;
Ci = 0;
#30;
A = 0;
B = 1;
Ci = 1;
#30;
A = 1;
B = 0;
Ci = 0;
#30;
A = 1;
B = 0;
Ci = 1;
#30;
A = 1;
B =1;
Ci = 0;
#30;
A = 1;
B = 1;
Ci = 1;
end
endmodule | 0 |
138,500 | data/full_repos/permissive/84007307/testINVERTER.v | 84,007,307 | testINVERTER.v | v | 53 | 81 | [] | [] | [] | [(25, 51)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/84007307/testINVERTER.v:44: Unsupported: Ignoring delay on this delayed statement.\n #10 in = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testINVERTER.v:45: Unsupported: Ignoring delay on this delayed statement.\n #10 ; \n ^\n%Error: data/full_repos/permissive/84007307/testINVERTER.v:34: Cannot find file containing module: \'INVERTER\'\n INVERTER dut (\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/INVERTER\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/INVERTER.v\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/INVERTER.sv\n INVERTER\n INVERTER.v\n INVERTER.sv\n obj_dir/INVERTER\n obj_dir/INVERTER.v\n obj_dir/INVERTER.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,450 | module | module testINVERTER;
reg in;
wire out;
INVERTER dut (
.in(in),
.out(out)
);
always begin
in = 0;
#10 in = 1;
#10 ;
end
endmodule | module testINVERTER; |
reg in;
wire out;
INVERTER dut (
.in(in),
.out(out)
);
always begin
in = 0;
#10 in = 1;
#10 ;
end
endmodule | 0 |
138,501 | data/full_repos/permissive/84007307/testMUX2.v | 84,007,307 | testMUX2.v | v | 80 | 81 | [] | [] | [] | [(25, 78)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX2.v:46: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX2.v:50: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX2.v:54: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX2.v:58: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX2.v:62: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX2.v:66: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX2.v:70: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Error: data/full_repos/permissive/84007307/testMUX2.v:35: Cannot find file containing module: \'MUX2\'\n MUX2 dut (\n ^~~~\n ... Looked in:\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/MUX2\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/MUX2.v\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/MUX2.sv\n MUX2\n MUX2.v\n MUX2.sv\n obj_dir/MUX2\n obj_dir/MUX2.v\n obj_dir/MUX2.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,451 | module | module testMUX2;
reg [1:0] in;
reg sel;
wire out;
MUX2 dut (
.in(in),
.sel(sel),
.out(out)
);
initial begin
in = 0;
sel = 0;
#20;
in = 2'b01;
sel=1;
#20;
in = 2'b10;
sel=0;
#20;
in = 2'b11;
sel=1;
#20;
in = 2'b00;
sel=1;
#20;
in = 2'b01;
sel=0;
#20;
in = 2'b10;
sel=1;
#20;
in = 2'b11;
sel=0 ;
end
endmodule | module testMUX2; |
reg [1:0] in;
reg sel;
wire out;
MUX2 dut (
.in(in),
.sel(sel),
.out(out)
);
initial begin
in = 0;
sel = 0;
#20;
in = 2'b01;
sel=1;
#20;
in = 2'b10;
sel=0;
#20;
in = 2'b11;
sel=1;
#20;
in = 2'b00;
sel=1;
#20;
in = 2'b01;
sel=0;
#20;
in = 2'b10;
sel=1;
#20;
in = 2'b11;
sel=0 ;
end
endmodule | 0 |
138,502 | data/full_repos/permissive/84007307/testMUX32.v | 84,007,307 | testMUX32.v | v | 139 | 81 | [] | [] | [] | [(25, 137)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX32.v:71: Unsupported: Ignoring delay on this delayed statement.\n #30; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX32.v:75: Unsupported: Ignoring delay on this delayed statement.\n #30; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX32.v:79: Unsupported: Ignoring delay on this delayed statement.\n #30; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX32.v:84: Unsupported: Ignoring delay on this delayed statement.\n #30; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX32.v:88: Unsupported: Ignoring delay on this delayed statement.\n #30; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX32.v:93: Unsupported: Ignoring delay on this delayed statement.\n #30; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX32.v:97: Unsupported: Ignoring delay on this delayed statement.\n #30; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX32.v:101: Unsupported: Ignoring delay on this delayed statement.\n #30; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX32.v:107: Unsupported: Ignoring delay on this delayed statement.\n #30; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX32.v:113: Unsupported: Ignoring delay on this delayed statement.\n #30; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX32.v:117: Unsupported: Ignoring delay on this delayed statement.\n #30; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX32.v:121: Unsupported: Ignoring delay on this delayed statement.\n #30; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX32.v:126: Unsupported: Ignoring delay on this delayed statement.\n #30; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX32.v:131: Unsupported: Ignoring delay on this delayed statement.\n #30; \n ^\n%Error: data/full_repos/permissive/84007307/testMUX32.v:35: Cannot find file containing module: \'MUX32\'\n MUX32 dut (\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/MUX32\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/MUX32.v\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/MUX32.sv\n MUX32\n MUX32.v\n MUX32.sv\n obj_dir/MUX32\n obj_dir/MUX32.v\n obj_dir/MUX32.sv\n%Warning-WIDTH: data/full_repos/permissive/84007307/testMUX32.v:73: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hf\' generates 4 bits.\n : ... In instance testMUX32\n sel=4\'b1111 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84007307/testMUX32.v:77: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h2\' generates 4 bits.\n : ... In instance testMUX32\n sel=4\'b0010 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84007307/testMUX32.v:81: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hb\' generates 4 bits.\n : ... In instance testMUX32\n sel=4\'b1011 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84007307/testMUX32.v:86: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance testMUX32\n sel=4\'b1000 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84007307/testMUX32.v:90: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hb\' generates 4 bits.\n : ... In instance testMUX32\n sel=4\'b1011 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84007307/testMUX32.v:95: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hb\' generates 4 bits.\n : ... In instance testMUX32\n sel=4\'b1011 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84007307/testMUX32.v:99: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h9\' generates 4 bits.\n : ... In instance testMUX32\n sel=4\'b1001 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84007307/testMUX32.v:103: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h3\' generates 4 bits.\n : ... In instance testMUX32\n sel=4\'b0011 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84007307/testMUX32.v:109: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h3\' generates 4 bits.\n : ... In instance testMUX32\n sel=4\'b0011 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84007307/testMUX32.v:115: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hf\' generates 4 bits.\n : ... In instance testMUX32\n sel=4\'b1111 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84007307/testMUX32.v:119: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h6\' generates 4 bits.\n : ... In instance testMUX32\n sel=4\'b0110 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84007307/testMUX32.v:123: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h9\' generates 4 bits.\n : ... In instance testMUX32\n sel=4\'b1001 ; \n ^\n%Warning-WIDTH: data/full_repos/permissive/84007307/testMUX32.v:128: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n : ... In instance testMUX32\n sel=4\'b0001 ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84007307/testMUX32.v:133: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h8\' generates 4 bits.\n : ... In instance testMUX32\n sel=4\'b1000 ;\n ^\n%Error: Exiting due to 1 error(s), 28 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,452 | module | module testMUX32;
reg [31:0] in;
reg [4:0] sel;
wire out;
MUX32 dut (
.in(in),
.sel(sel),
.out(out)
);
initial begin
in = 0;
sel = 0;
#30;
in=32'hEEEEEEEE ;
sel=4'b1111 ;
#30;
in=32'hEE0E5EA0 ;
sel=4'b0010 ;
#30;
in=32'hEEEE5EEE ;
sel=4'b1011 ;
#30;
in=32'h000050A0 ;
sel=4'b1000 ;
#30;
in=32'hEE3EEEEE ;
sel=4'b1011 ;
#30;
in=32'h0AB000A0 ;
sel=4'b1011 ;
#30;
in=32'hEE0E5EEE ;
sel=4'b1001 ;
#30;
in=32'h0AB000B0 ;
sel=4'b0011 ;
#30;
in=32'hEE0E5EAE ;
sel=4'b0011 ;
#30;
in=32'hEA003070 ;
sel=4'b1111 ;
#30;
in=32'h100200E5 ;
sel=4'b0110 ;
#30;
in=32'hD0D020E0 ;
sel=4'b1001 ;
#30;
in=32'h0607A061 ;
sel=4'b0001 ;
#30;
in=32'h09005E00 ;
sel=4'b1000 ;
end
endmodule | module testMUX32; |
reg [31:0] in;
reg [4:0] sel;
wire out;
MUX32 dut (
.in(in),
.sel(sel),
.out(out)
);
initial begin
in = 0;
sel = 0;
#30;
in=32'hEEEEEEEE ;
sel=4'b1111 ;
#30;
in=32'hEE0E5EA0 ;
sel=4'b0010 ;
#30;
in=32'hEEEE5EEE ;
sel=4'b1011 ;
#30;
in=32'h000050A0 ;
sel=4'b1000 ;
#30;
in=32'hEE3EEEEE ;
sel=4'b1011 ;
#30;
in=32'h0AB000A0 ;
sel=4'b1011 ;
#30;
in=32'hEE0E5EEE ;
sel=4'b1001 ;
#30;
in=32'h0AB000B0 ;
sel=4'b0011 ;
#30;
in=32'hEE0E5EAE ;
sel=4'b0011 ;
#30;
in=32'hEA003070 ;
sel=4'b1111 ;
#30;
in=32'h100200E5 ;
sel=4'b0110 ;
#30;
in=32'hD0D020E0 ;
sel=4'b1001 ;
#30;
in=32'h0607A061 ;
sel=4'b0001 ;
#30;
in=32'h09005E00 ;
sel=4'b1000 ;
end
endmodule | 0 |
138,503 | data/full_repos/permissive/84007307/testMUX4_UDP.v | 84,007,307 | testMUX4_UDP.v | v | 62 | 81 | [] | [] | [] | null | line:56: before: "$" | null | 1: b'%Error: data/full_repos/permissive/84007307/testMUX4_UDP.v:42: Unsupported or unknown PLI call: $monitor\n $monitor(" in = %b sel = %b out = %b",in,sel,out);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX4_UDP.v:47: Unsupported: Ignoring delay on this delayed statement.\n #5 in = 4\'b0000; sel = 2\'b00;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX4_UDP.v:48: Unsupported: Ignoring delay on this delayed statement.\n #5 in = 4\'b0001; sel = 2\'b00;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX4_UDP.v:49: Unsupported: Ignoring delay on this delayed statement.\n #5 in = 4\'b0010; sel = 2\'b01;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX4_UDP.v:50: Unsupported: Ignoring delay on this delayed statement.\n #5 in = 4\'b0100; sel = 2\'b01;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX4_UDP.v:51: Unsupported: Ignoring delay on this delayed statement.\n #5 in = 4\'bXXX0; sel = 2\'b00; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX4_UDP.v:52: Unsupported: Ignoring delay on this delayed statement.\n #5 in = 4\'b1X10; sel = 2\'b11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX4_UDP.v:53: Unsupported: Ignoring delay on this delayed statement.\n #5 in = 4\'b1101; sel = 2\'b10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX4_UDP.v:54: Unsupported: Ignoring delay on this delayed statement.\n #5 in = 4\'b1001; sel = 2\'b10; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testMUX4_UDP.v:56: Unsupported: Ignoring delay on this delayed statement.\n #1 $finish;\n ^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,453 | module | module testMUX4_UDP();
reg [3:0] in;
reg [1:0] sel;
wire out;
MUX4 dut (
.in(in),
.sel(sel),
.out(out)
);
initial begin
$monitor(" in = %b sel = %b out = %b",in,sel,out);
in = 4'b0000;
sel = 2'b00;
#5 in = 4'b0000; sel = 2'b00;
#5 in = 4'b0001; sel = 2'b00;
#5 in = 4'b0010; sel = 2'b01;
#5 in = 4'b0100; sel = 2'b01;
#5 in = 4'bXXX0; sel = 2'b00;
#5 in = 4'b1X10; sel = 2'b11;
#5 in = 4'b1101; sel = 2'b10;
#5 in = 4'b1001; sel = 2'b10;
#1 $finish;
end
endmodule | module testMUX4_UDP(); |
reg [3:0] in;
reg [1:0] sel;
wire out;
MUX4 dut (
.in(in),
.sel(sel),
.out(out)
);
initial begin
$monitor(" in = %b sel = %b out = %b",in,sel,out);
in = 4'b0000;
sel = 2'b00;
#5 in = 4'b0000; sel = 2'b00;
#5 in = 4'b0001; sel = 2'b00;
#5 in = 4'b0010; sel = 2'b01;
#5 in = 4'b0100; sel = 2'b01;
#5 in = 4'bXXX0; sel = 2'b00;
#5 in = 4'b1X10; sel = 2'b11;
#5 in = 4'b1101; sel = 2'b10;
#5 in = 4'b1001; sel = 2'b10;
#1 $finish;
end
endmodule | 0 |
138,504 | data/full_repos/permissive/84007307/testNAND.v | 84,007,307 | testNAND.v | v | 76 | 81 | [] | [] | [] | [(25, 74)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/84007307/testNAND.v:46: Unsupported: Ignoring delay on this delayed statement.\n #10 ; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testNAND.v:50: Unsupported: Ignoring delay on this delayed statement.\n #10 ; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testNAND.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10 ; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testNAND.v:58: Unsupported: Ignoring delay on this delayed statement.\n #10 ; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testNAND.v:62: Unsupported: Ignoring delay on this delayed statement.\n #10 ; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testNAND.v:66: Unsupported: Ignoring delay on this delayed statement.\n #10 ; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testNAND.v:70: Unsupported: Ignoring delay on this delayed statement.\n #10 ;\n ^\n%Error: data/full_repos/permissive/84007307/testNAND.v:35: Cannot find file containing module: \'NAND\'\n NAND dut (\n ^~~~\n ... Looked in:\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/NAND\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/NAND.v\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/NAND.sv\n NAND\n NAND.v\n NAND.sv\n obj_dir/NAND\n obj_dir/NAND.v\n obj_dir/NAND.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,454 | module | module testNAND;
reg in1;
reg in2;
wire out;
NAND dut (
.in1(in1),
.in2(in2),
.out(out)
);
initial begin
in1 = 1;
in2 = 1;
#10 ;
in1 = 0;
in2 = 0;
#10 ;
in1 = 1;
in2 = 1;
#10 ;
in1 = 1;
in2 = 0;
#10 ;
in1 = 1;
in2 = 1;
#10 ;
in1 = 0;
in2 = 1;
#10 ;
in1 = 1;
in2 = 0;
#10 ;
end
endmodule | module testNAND; |
reg in1;
reg in2;
wire out;
NAND dut (
.in1(in1),
.in2(in2),
.out(out)
);
initial begin
in1 = 1;
in2 = 1;
#10 ;
in1 = 0;
in2 = 0;
#10 ;
in1 = 1;
in2 = 1;
#10 ;
in1 = 1;
in2 = 0;
#10 ;
in1 = 1;
in2 = 1;
#10 ;
in1 = 0;
in2 = 1;
#10 ;
in1 = 1;
in2 = 0;
#10 ;
end
endmodule | 0 |
138,505 | data/full_repos/permissive/84007307/testREG32.v | 84,007,307 | testREG32.v | v | 120 | 81 | [] | [] | [] | null | line:58: before: "#" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/84007307/testREG32.v:46: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testREG32.v:48: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testREG32.v:58: Unsupported: Ignoring delay on this delayed statement.\n #300; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testREG32.v:57: Unsupported: Ignoring delay on this delayed statement.\n #50\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testREG32.v:62: Unsupported: Ignoring delay on this delayed statement.\n #300; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testREG32.v:65: Unsupported: Ignoring delay on this delayed statement.\n #300; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testREG32.v:69: Unsupported: Ignoring delay on this delayed statement.\n #300; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testREG32.v:73: Unsupported: Ignoring delay on this delayed statement.\n #300; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testREG32.v:77: Unsupported: Ignoring delay on this delayed statement.\n #300; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testREG32.v:81: Unsupported: Ignoring delay on this delayed statement.\n #300; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testREG32.v:84: Unsupported: Ignoring delay on this delayed statement.\n #300; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testREG32.v:89: Unsupported: Ignoring delay on this delayed statement.\n #300; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testREG32.v:95: Unsupported: Ignoring delay on this delayed statement.\n #300; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testREG32.v:99: Unsupported: Ignoring delay on this delayed statement.\n #300; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testREG32.v:102: Unsupported: Ignoring delay on this delayed statement.\n #300; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testREG32.v:106: Unsupported: Ignoring delay on this delayed statement.\n #300; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/84007307/testREG32.v:110: Unsupported: Ignoring delay on this delayed statement.\n #300; \n ^\n%Error: data/full_repos/permissive/84007307/testREG32.v:36: Cannot find file containing module: \'REG32\'\n REG32 dut (\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/REG32\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/REG32.v\n data/full_repos/permissive/84007307,data/full_repos/permissive/84007307/REG32.sv\n REG32\n REG32.v\n REG32.sv\n obj_dir/REG32\n obj_dir/REG32.v\n obj_dir/REG32.sv\n%Error: Exiting due to 1 error(s), 17 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,456 | module | module testREG32;
reg [31:0] in;
reg clk;
reg R;
wire [31:0] out;
REG32 dut (
.in(in),
.clk(clk),
.R(R),
.out(out)
);
always begin
clk = 0;
#100;
clk = 1;
#100;
end
initial begin
in = 0;
R = 1;
#50
#300;
R = 0;
in=32'hEEEEEEEE ;
#300;
in=32'hEE0E5EA0 ;
#300;
in=32'hEEEE5EEE ;
#300;
R = 1;
in=32'h000050A0 ;
#300;
in=32'hEE3EEEEE ;
#300;
R = 0;
in=32'h0AB000A0 ;
#300;
in=32'hEE0E5EEE ;
#300;
in=32'h0AB000B0 ;
#300;
R=1;
in=32'hEE0E5EAE ;
#300;
R=0;
in=32'hEA003070 ;
#300;
in=32'h100200E5 ;
#300;
in=32'hD0D020E0 ;
#300;
in=32'h0607A061 ;
#300;
in=32'h09005E00 ;
end
endmodule | module testREG32; |
reg [31:0] in;
reg clk;
reg R;
wire [31:0] out;
REG32 dut (
.in(in),
.clk(clk),
.R(R),
.out(out)
);
always begin
clk = 0;
#100;
clk = 1;
#100;
end
initial begin
in = 0;
R = 1;
#50
#300;
R = 0;
in=32'hEEEEEEEE ;
#300;
in=32'hEE0E5EA0 ;
#300;
in=32'hEEEE5EEE ;
#300;
R = 1;
in=32'h000050A0 ;
#300;
in=32'hEE3EEEEE ;
#300;
R = 0;
in=32'h0AB000A0 ;
#300;
in=32'hEE0E5EEE ;
#300;
in=32'h0AB000B0 ;
#300;
R=1;
in=32'hEE0E5EAE ;
#300;
R=0;
in=32'hEA003070 ;
#300;
in=32'h100200E5 ;
#300;
in=32'hD0D020E0 ;
#300;
in=32'h0607A061 ;
#300;
in=32'h09005E00 ;
end
endmodule | 0 |
138,506 | data/full_repos/permissive/84007307/XOR.v | 84,007,307 | XOR.v | v | 30 | 83 | [] | [] | [] | null | line:27: before: "(" | data/verilator_xmls/757941f0-474e-4576-8aed-8c6ba5a7015a.xml | null | 302,458 | module | module XOR(
input in1,
input in2,
output out
);
buf#(5) (out,in1 ^ in2);
endmodule | module XOR(
input in1,
input in2,
output out
); |
buf#(5) (out,in1 ^ in2);
endmodule | 0 |
138,507 | data/full_repos/permissive/84121480/bcd_ctr.v | 84,121,480 | bcd_ctr.v | v | 67 | 87 | [] | [] | [] | [(13, 67)] | null | data/verilator_xmls/0a3e378d-3b1c-4613-8f47-01609594cef8.xml | null | 302,459 | module | module bcd_ctr(clk, en, ar, dig1, dig2, dig3);
input clk, ar, en;
output reg [3:0] dig1, dig2, dig3;
wire dig1_carry, dig2_carry, dig3_carry;
assign dig1_carry = (dig1 == 4'd9);
assign dig2_carry = dig1_carry&(dig2 == 4'd9);
assign dig3_carry = dig2_carry&(dig3 == 4'd9);
always @ (posedge clk or negedge ar)
begin
if(~ar)
begin
dig1 <= 4'd0;
dig2 <= 4'd0;
dig3 <= 4'd0;
end else if(~dig3_carry&en)
begin
if(dig2_carry)
begin
dig3 <= dig3 + 1;
dig2 <= 0;
dig1 <= 0;
end else if(dig1_carry)
begin
dig2 <= dig2 + 1;
dig1 <= 0;
end else
begin
dig1 <= dig1 + 1;
end
end
end
endmodule | module bcd_ctr(clk, en, ar, dig1, dig2, dig3); |
input clk, ar, en;
output reg [3:0] dig1, dig2, dig3;
wire dig1_carry, dig2_carry, dig3_carry;
assign dig1_carry = (dig1 == 4'd9);
assign dig2_carry = dig1_carry&(dig2 == 4'd9);
assign dig3_carry = dig2_carry&(dig3 == 4'd9);
always @ (posedge clk or negedge ar)
begin
if(~ar)
begin
dig1 <= 4'd0;
dig2 <= 4'd0;
dig3 <= 4'd0;
end else if(~dig3_carry&en)
begin
if(dig2_carry)
begin
dig3 <= dig3 + 1;
dig2 <= 0;
dig1 <= 0;
end else if(dig1_carry)
begin
dig2 <= dig2 + 1;
dig1 <= 0;
end else
begin
dig1 <= dig1 + 1;
end
end
end
endmodule | 0 |
138,508 | data/full_repos/permissive/84121480/clock_divider.v | 84,121,480 | clock_divider.v | v | 68 | 63 | [] | [] | [] | [(12, 68)] | null | data/verilator_xmls/9d492964-b4a3-4f56-bdd8-7c916b8f72fa.xml | null | 302,460 | module | module clock_divider(clk, ar, x, y);
parameter width_x = 26;
parameter halfperiod_x = 26'd50000000;
parameter width_y = 15;
parameter halfperiod_y = 15'd25000;
input clk, ar;
output reg x, y;
reg [width_x-1:0] ctr_x;
reg [width_y-1:0] ctr_y;
always @ (posedge clk or negedge ar)
begin
if(~ar)
begin
ctr_x <= 0;
ctr_y <= 0;
x <= 0;
y <= 0;
end
else
begin
if(ctr_x>=halfperiod_x-1)
begin
x <= ~x;
ctr_x <= 0;
end
else begin
ctr_x <= ctr_x + 1;
end
if(ctr_y>=halfperiod_y-1)
begin
y <= ~y;
ctr_y <= 0;
end
else begin
ctr_y <= ctr_y + 1;
end
end
end
endmodule | module clock_divider(clk, ar, x, y); |
parameter width_x = 26;
parameter halfperiod_x = 26'd50000000;
parameter width_y = 15;
parameter halfperiod_y = 15'd25000;
input clk, ar;
output reg x, y;
reg [width_x-1:0] ctr_x;
reg [width_y-1:0] ctr_y;
always @ (posedge clk or negedge ar)
begin
if(~ar)
begin
ctr_x <= 0;
ctr_y <= 0;
x <= 0;
y <= 0;
end
else
begin
if(ctr_x>=halfperiod_x-1)
begin
x <= ~x;
ctr_x <= 0;
end
else begin
ctr_x <= ctr_x + 1;
end
if(ctr_y>=halfperiod_y-1)
begin
y <= ~y;
ctr_y <= 0;
end
else begin
ctr_y <= ctr_y + 1;
end
end
end
endmodule | 0 |
138,509 | data/full_repos/permissive/84121480/ctr_fsm.v | 84,121,480 | ctr_fsm.v | v | 92 | 96 | [] | [] | [] | [(12, 92)] | null | data/verilator_xmls/c975a6d6-dbaa-44db-a9d6-3e6e49291672.xml | null | 302,461 | module | module ctr_fsm(clk, ar, start, stop, ctr_en, ctr_ar);
parameter [1:0] IDLE=2'b00, PRERUN=2'b01, RUN=2'b10, STOPPED=2'b11;
parameter start_assert = 1'b1;
parameter stop_assert = 1'b0;
input clk, ar, start, stop;
output ctr_en, ctr_ar;
reg [1:0] state;
assign ctr_en = (state==RUN);
assign ctr_ar = ~(state==PRERUN|state==IDLE);
always @ (posedge clk or negedge ar)
begin
if(~ar)
begin
state <= IDLE;
end else
begin
case(state)
IDLE:begin
if(start==start_assert)
begin
state<=PRERUN;
end else
begin
state<=IDLE;
end
end
PRERUN:begin
if(stop==stop_assert)
begin
state<=STOPPED;
end else
begin
state<=RUN;
end
end
RUN:begin
if(stop==stop_assert)
begin
state<=STOPPED;
end
else begin
state<=RUN;
end
end
default:begin
if(start==~start_assert)
begin
state<=IDLE;
end else
begin
state<=STOPPED;
end
end
endcase
end
end
endmodule | module ctr_fsm(clk, ar, start, stop, ctr_en, ctr_ar); |
parameter [1:0] IDLE=2'b00, PRERUN=2'b01, RUN=2'b10, STOPPED=2'b11;
parameter start_assert = 1'b1;
parameter stop_assert = 1'b0;
input clk, ar, start, stop;
output ctr_en, ctr_ar;
reg [1:0] state;
assign ctr_en = (state==RUN);
assign ctr_ar = ~(state==PRERUN|state==IDLE);
always @ (posedge clk or negedge ar)
begin
if(~ar)
begin
state <= IDLE;
end else
begin
case(state)
IDLE:begin
if(start==start_assert)
begin
state<=PRERUN;
end else
begin
state<=IDLE;
end
end
PRERUN:begin
if(stop==stop_assert)
begin
state<=STOPPED;
end else
begin
state<=RUN;
end
end
RUN:begin
if(stop==stop_assert)
begin
state<=STOPPED;
end
else begin
state<=RUN;
end
end
default:begin
if(start==~start_assert)
begin
state<=IDLE;
end else
begin
state<=STOPPED;
end
end
endcase
end
end
endmodule | 0 |
138,510 | data/full_repos/permissive/84121480/lfsr.v | 84,121,480 | lfsr.v | v | 47 | 61 | [] | [] | [] | [(13, 47)] | null | data/verilator_xmls/c4b88791-fbfd-4bb1-9224-41ed0852c90c.xml | null | 302,462 | module | module lfsr(clk, ar, sr, q);
input clk, ar;
output q;
output reg [7:0] sr;
wire polynomial;
assign polynomial = sr[7]^sr[5]^sr[4]^sr[3];
assign q = sr[7];
always @ (posedge clk or negedge ar)
begin
if(~ar)
begin
sr <= 8'b00000001;
end
else
begin
sr <= { sr[6:0], polynomial };
end
end
endmodule | module lfsr(clk, ar, sr, q); |
input clk, ar;
output q;
output reg [7:0] sr;
wire polynomial;
assign polynomial = sr[7]^sr[5]^sr[4]^sr[3];
assign q = sr[7];
always @ (posedge clk or negedge ar)
begin
if(~ar)
begin
sr <= 8'b00000001;
end
else
begin
sr <= { sr[6:0], polynomial };
end
end
endmodule | 0 |
138,511 | data/full_repos/permissive/84121480/tld.v | 84,121,480 | tld.v | v | 34 | 120 | [] | [] | [] | [(12, 33)] | null | null | 1: b"%Error: data/full_repos/permissive/84121480/tld.v:20: Cannot find file containing module: 'clock_divider'\n clock_divider clkdiv ( .clk(clock), .ar(ar), .x(slow_clock), .y(fast_clock));\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/84121480,data/full_repos/permissive/84121480/clock_divider\n data/full_repos/permissive/84121480,data/full_repos/permissive/84121480/clock_divider.v\n data/full_repos/permissive/84121480,data/full_repos/permissive/84121480/clock_divider.sv\n clock_divider\n clock_divider.v\n clock_divider.sv\n obj_dir/clock_divider\n obj_dir/clock_divider.v\n obj_dir/clock_divider.sv\n%Error: data/full_repos/permissive/84121480/tld.v:22: Cannot find file containing module: 'lfsr'\n lfsr shiftreg ( .clk(slow_clock), .ar(ar), .sr( ), .q(random_bit));\n ^~~~\n%Error: data/full_repos/permissive/84121480/tld.v:24: Cannot find file containing module: 'ctr_fsm'\n ctr_fsm fsm (.clk(fast_clock), .ar(ar), .start(random_bit), .stop(button), .ctr_en(ctr_en), .ctr_ar(ctr_ar));\n ^~~~~~~\n%Error: data/full_repos/permissive/84121480/tld.v:26: Cannot find file containing module: 'bcd_ctr'\n bcd_ctr bcd (.clk(fast_clock), .en(ctr_en), .ar(ctr_ar), .dig1(dig1), .dig2(dig2), .dig3(dig3));\n ^~~~~~~\n%Error: data/full_repos/permissive/84121480/tld.v:28: Cannot find file containing module: 'sevseg_decoder'\n sevseg_decoder decoder1 (.val(dig1), .a(a1), .b(b1), .c(c1), .d(d1), .e(e1), .f(f1), .g(g1));\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84121480/tld.v:29: Cannot find file containing module: 'sevseg_decoder'\n sevseg_decoder decoder2 (.val(dig2), .a(a2), .b(b2), .c(c2), .d(d2), .e(e2), .f(f2), .g(g2));\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84121480/tld.v:30: Cannot find file containing module: 'sevseg_decoder'\n sevseg_decoder decoder3 (.val(dig3), .a(a3), .b(b3), .c(c3), .d(d3), .e(e3), .f(f3), .g(g3));\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n" | 302,464 | module | module tld(clock, ar, button, a1, b1, c1, d1, e1, f1, g1, a2, b2, c2, d2, e2, f2, g2, a3, b3, c3, d3, e3, f3, g3, led);
input wire clock, ar, button;
output wire a1, b1, c1, d1, e1, f1, g1, a2, b2, c2, d2, e2, f2, g2, a3, b3, c3, d3, e3, f3, g3, led;
wire fast_clock, slow_clock, random_bit, ctr_en, ctr_ar;
wire [3:0] dig1, dig2, dig3;
clock_divider clkdiv ( .clk(clock), .ar(ar), .x(slow_clock), .y(fast_clock));
lfsr shiftreg ( .clk(slow_clock), .ar(ar), .sr( ), .q(random_bit));
ctr_fsm fsm (.clk(fast_clock), .ar(ar), .start(random_bit), .stop(button), .ctr_en(ctr_en), .ctr_ar(ctr_ar));
bcd_ctr bcd (.clk(fast_clock), .en(ctr_en), .ar(ctr_ar), .dig1(dig1), .dig2(dig2), .dig3(dig3));
sevseg_decoder decoder1 (.val(dig1), .a(a1), .b(b1), .c(c1), .d(d1), .e(e1), .f(f1), .g(g1));
sevseg_decoder decoder2 (.val(dig2), .a(a2), .b(b2), .c(c2), .d(d2), .e(e2), .f(f2), .g(g2));
sevseg_decoder decoder3 (.val(dig3), .a(a3), .b(b3), .c(c3), .d(d3), .e(e3), .f(f3), .g(g3));
assign led = ctr_en;
endmodule | module tld(clock, ar, button, a1, b1, c1, d1, e1, f1, g1, a2, b2, c2, d2, e2, f2, g2, a3, b3, c3, d3, e3, f3, g3, led); |
input wire clock, ar, button;
output wire a1, b1, c1, d1, e1, f1, g1, a2, b2, c2, d2, e2, f2, g2, a3, b3, c3, d3, e3, f3, g3, led;
wire fast_clock, slow_clock, random_bit, ctr_en, ctr_ar;
wire [3:0] dig1, dig2, dig3;
clock_divider clkdiv ( .clk(clock), .ar(ar), .x(slow_clock), .y(fast_clock));
lfsr shiftreg ( .clk(slow_clock), .ar(ar), .sr( ), .q(random_bit));
ctr_fsm fsm (.clk(fast_clock), .ar(ar), .start(random_bit), .stop(button), .ctr_en(ctr_en), .ctr_ar(ctr_ar));
bcd_ctr bcd (.clk(fast_clock), .en(ctr_en), .ar(ctr_ar), .dig1(dig1), .dig2(dig2), .dig3(dig3));
sevseg_decoder decoder1 (.val(dig1), .a(a1), .b(b1), .c(c1), .d(d1), .e(e1), .f(f1), .g(g1));
sevseg_decoder decoder2 (.val(dig2), .a(a2), .b(b2), .c(c2), .d(d2), .e(e2), .f(f2), .g(g2));
sevseg_decoder decoder3 (.val(dig3), .a(a3), .b(b3), .c(c3), .d(d3), .e(e3), .f(f3), .g(g3));
assign led = ctr_en;
endmodule | 0 |
138,512 | data/full_repos/permissive/84314966/src/DM.v | 84,314,966 | DM.v | v | 255 | 70 | [] | [] | [] | null | line:72: before: ";" | null | 1: b'%Error: data/full_repos/permissive/84314966/src/DM.v:1: Cannot find include file: DM_parameters.vh\n`include "DM_parameters.vh" \n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/84314966/src,data/full_repos/permissive/84314966/DM_parameters.vh\n data/full_repos/permissive/84314966/src,data/full_repos/permissive/84314966/DM_parameters.vh.v\n data/full_repos/permissive/84314966/src,data/full_repos/permissive/84314966/DM_parameters.vh.sv\n DM_parameters.vh\n DM_parameters.vh.v\n DM_parameters.vh.sv\n obj_dir/DM_parameters.vh\n obj_dir/DM_parameters.vh.v\n obj_dir/DM_parameters.vh.sv\n%Error: data/full_repos/permissive/84314966/src/DM.v:2: Cannot find include file: dmi_addr_map.vh\n`include "dmi_addr_map.vh" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:6: syntax error, unexpected \';\', expecting \')\' or \',\'\n input reset;\n ^\n%Error: data/full_repos/permissive/84314966/src/DM.v:10: Define or directive not defined: \'`ADDRESS_SIZE\'\n input [`ADDRESS_SIZE-1:0] DMI_raddr;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:11: Define or directive not defined: \'`ADDRESS_SIZE\'\n input [`ADDRESS_SIZE-1:0] DMI_waddr;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:28: Define or directive not defined: \'`XPR_LEN\'\n output [`XPR_LEN-1:0] debug_wdata,\n ^~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:29: Define or directive not defined: \'`XPR_LEN\'\n input [`XPR_LEN-1:0] debug_rdata,\n ^~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:74: syntax error, unexpected always\n always@(*)\n ^~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:96: syntax error, unexpected always\n always@(posedge reset or posedge clk)\n ^~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:115: Define or directive not defined: \'`DM_STATE_WIDTH\'\n reg [`DM_STATE_WIDTH-1] dm_state;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:115: syntax error, unexpected \']\', expecting \':\'\n reg [`DM_STATE_WIDTH-1] dm_state;\n ^\n%Error: data/full_repos/permissive/84314966/src/DM.v:116: Define or directive not defined: \'`DM_STATE_WIDTH\'\n wire [`DM_STATE_WIDTH-1] dm_state_next;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:116: syntax error, unexpected \']\', expecting \':\'\n wire [`DM_STATE_WIDTH-1] dm_state_next;\n ^\n%Error: data/full_repos/permissive/84314966/src/DM.v:119: syntax error, unexpected always\nalways@(posedge reset or posedge clk)\n^~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:122: Define or directive not defined: \'`DM_STATE_WIDTH\'\n dm_state<=`DM_STATE_WIDTH\'d0;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:141: Define or directive not defined: \'`XPR_LEN\'\n debug_wdata=`XPR_LEN\'d0;\n ^~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:148: Define or directive not defined: \'`DM_MUSH_MODE\'\n `DM_MUSH_MODE:\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:152: Define or directive not defined: \'`DM_HALTING\'\n dm_state_next=`DM_HALTING;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:158: Define or directive not defined: \'`DM_HALTING\'\n `DM_HALTING:\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:163: Define or directive not defined: \'`DM_HALTED\'\n dm_state_next=`DM_HALTED;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:169: Define or directive not defined: \'`DM_HALTED\'\n `DM_HALTED:\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:173: Define or directive not defined: \'`DM_COMMAND_CHECKED\'\n dm_state_next=`DM_COMMAND_CHECKED;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:178: Define or directive not defined: \'`DM_COMMAND_CHECKED\'\n `DM_COMMAND_CHECKED:\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:185: Define or directive not defined: \'`DM_ERROR_DETECTED\'\n dm_state_next=`DM_ERROR_DETECTED;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:190: Define or directive not defined: \'`DM_ERROR_DETECTED\'\n dm_state_next=`DM_ERROR_DETECTED;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:197: Define or directive not defined: \'`DM_ERROR_DETECTED\'\n dm_state_next=`DM_ERROR_DETECTED;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:202: Define or directive not defined: \'`DM_ERROR_DETECTED\'\n dm_state_next=`DM_ERROR_DETECTED;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:208: Define or directive not defined: \'`DM_ACCESS_COMMAND_EXECUTING_1\'\n dm_state_next=`DM_ACCESS_COMMAND_EXECUTING_1;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:213: Define or directive not defined: \'`DM_ACCESS_COMMAND_EXECUTING_1\'\n `DM_ACCESS_COMMAND_EXECUTING_1:\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:223: Define or directive not defined: \'`DM_HALTED\'\n dm_state_next=`DM_HALTED;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:228: Define or directive not defined: \'`DM_ACCESS_COMMAND_EXECUTING_1\'\n dm_state_next=`DM_ACCESS_COMMAND_EXECUTING_1;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:239: Define or directive not defined: \'`DM_HALTED\'\n dm_state_next=`DM_HALTED;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:243: Define or directive not defined: \'`DM_ACCESS_COMMAND_EXECUTING_1\'\n dm_state_next=`DM_ACCESS_COMMAND_EXECUTING_1;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84314966/src/DM.v:247: Define or directive not defined: \'`DM_HALTED\'\n dm_state_next=`DM_HALTED;\n ^~~~~~~~~~\n%Error: Exiting due to 34 error(s)\n' | 302,468 | module | module DM(
input reset;
input clk;
input [`ADDRESS_SIZE-1:0] DMI_raddr;
input [`ADDRESS_SIZE-1:0] DMI_waddr;
input [31:0] DMI_wdata;
input write_en;
input read_en;
output [31:0] rdata;
output dm_busy;
output haltreq;
input core_haltack;
output resumereq;
output [12:0] register_index;
output debug_write;
output debug_read;
output [`XPR_LEN-1:0] debug_wdata,
input [`XPR_LEN-1:0] debug_rdata,
input reg_rack;
input reg_wack;
);
reg [31:0] abstract_data_0;
reg [31:0] dmcontrol;
reg [31:0] dmstatus;
reg [31:0] hart_info;
reg [31:0] hart_summary;
reg [31:0] hart_array_window_select;
reg [31:0] hart_array_window;
reg [31:0] abstractcs;
reg [31:0] command;
reg [31:0] abstract_command_autoexec;
reg [31:0] config_string_addr_0;
reg [31:0] config_string_addr_1;
reg [31:0] config_string_addr_2;
reg [31:0] config_string_addr_3;
reg [31:0] program_buffer_0;
reg [31:0] program_buffer_1;
reg [31:0] authentication_data;
reg [31:0] serial_control_and_status;
reg [31:0] serial_tx;
reg [31:0] serial_rx;
reg [31:0] system_bus_access_control_and_status;
reg [31:0] system_bus_address_0;
reg [31:0] system_bus_address_1;
reg [31:0] system_bus_address_2;
reg [31:0] system_bus_data_0;
reg [31:0] system_bus_data_1;
reg [31:0] system_bus_data_2;
reg [31:0] system_bus_data_3;
wire target_register;
always@(*)
begin
case(address)
0x04:
begin
target_register=abstract_data_0;
end
0x0f:
begin
end
endcase
end
haltreq = dmcontrol[31]? 1'b1: 1'b0;
resumereq = dmcontrol[30]? 1'b1:1'b0;
wire [31:0] abstractcs_next;
always@(posedge reset or posedge clk)
begin
if(reset)
abstractcs[12] <=1'b0;
else
abstractcs[12] <= ( write_en? 1'b1: abstractcs[12]);
end
assign register_index=command[15:0];
always@(*)
begin
case(command[31:24])
8'd0:
end
reg [`DM_STATE_WIDTH-1] dm_state;
wire [`DM_STATE_WIDTH-1] dm_state_next;
reg command_written;
always@(posedge reset or posedge clk)
begin
if(reset)
dm_state<=`DM_STATE_WIDTH'd0;
else
dm_state<=dm_state_next;
end
always@(*)
begin
dmstatus_next=dmstatus;
haltreq=1'b0;
resumereq=1'b0;
debug_write=1'b0;
debug_read=1'b0;
register_index=12'd0;
debug_wdata=`XPR_LEN'd0;
abstract_data_0_next=abstract_data_0;
dm_busy=1'b0;
case(dm_state)
`DM_MUSH_MODE:
begin
if(dmcontrol[31])
begin
dm_state_next=`DM_HALTING;
dmstatus_next[10]=1'b0;
dmstatus_next[11]=1'b0;
end
end
`DM_HALTING:
begin
haltreq=1'b1;
if(core_haltack)
begin
dm_state_next=`DM_HALTED;
dmstatus_next[9]=1'b1;
dmstatus_next[8]=1'b1;
end
end
`DM_HALTED:
begin
if(command_written==1'b1 && command[31:24]==8'd1)
begin
dm_state_next=`DM_COMMAND_CHECKED;
abstractcs_next[12]=1'b1;
end
end
`DM_COMMAND_CHECKED:
begin
dm_busy=1'b1;
if(write_en==1'b1)
begin
dm_state_next=`DM_ERROR_DETECTED;
abstractcs_next[10:8]=3'd1;
end
else if(command[31:24]!=8'd1)
begin
dm_state_next=`DM_ERROR_DETECTED;
abstractcs_next[10:8]=3'd2;
end
else if(command[22:20]!=3'd2)
begin
dm_state_next=`DM_ERROR_DETECTED;
abstractcs_next[10:8]=3'd3;
end
else if(dmstatus[9]==1'b0)
begin
dm_state_next=`DM_ERROR_DETECTED;
abstractcs_next[10:8]=3'd4;
end
else
begin
dm_state_next=`DM_ACCESS_COMMAND_EXECUTING_1;
abstractcs_next[10:8]=3'd0;
end
end
`DM_ACCESS_COMMAND_EXECUTING_1:
begin
dm_busy=1'b1;
if(command[16]==1'b0 && command[17]==1'b1)
begin
debug_read=1'b1;
register_index=command[11:0];
if(reg_rack==1'b1)
begin
dm_state_next=`DM_HALTED;
abstract_data_0_next=debug_rdata;
end
else
begin
dm_state_next=`DM_ACCESS_COMMAND_EXECUTING_1;
end
end
else if(command[16]==1'b1 && command[17]==1'b1)
begin
debug_write=1'b1;
register_index=command[11:0];
debug_wdata=abstract_data_0;
if(reg_wack==1'b1)
begin
dm_state_next=`DM_HALTED;
end
else
begin
dm_state_next=`DM_ACCESS_COMMAND_EXECUTING_1;
end
end
else
dm_state_next=`DM_HALTED;
end
endcase
end
endmodule | module DM(
input reset; |
input clk;
input [`ADDRESS_SIZE-1:0] DMI_raddr;
input [`ADDRESS_SIZE-1:0] DMI_waddr;
input [31:0] DMI_wdata;
input write_en;
input read_en;
output [31:0] rdata;
output dm_busy;
output haltreq;
input core_haltack;
output resumereq;
output [12:0] register_index;
output debug_write;
output debug_read;
output [`XPR_LEN-1:0] debug_wdata,
input [`XPR_LEN-1:0] debug_rdata,
input reg_rack;
input reg_wack;
);
reg [31:0] abstract_data_0;
reg [31:0] dmcontrol;
reg [31:0] dmstatus;
reg [31:0] hart_info;
reg [31:0] hart_summary;
reg [31:0] hart_array_window_select;
reg [31:0] hart_array_window;
reg [31:0] abstractcs;
reg [31:0] command;
reg [31:0] abstract_command_autoexec;
reg [31:0] config_string_addr_0;
reg [31:0] config_string_addr_1;
reg [31:0] config_string_addr_2;
reg [31:0] config_string_addr_3;
reg [31:0] program_buffer_0;
reg [31:0] program_buffer_1;
reg [31:0] authentication_data;
reg [31:0] serial_control_and_status;
reg [31:0] serial_tx;
reg [31:0] serial_rx;
reg [31:0] system_bus_access_control_and_status;
reg [31:0] system_bus_address_0;
reg [31:0] system_bus_address_1;
reg [31:0] system_bus_address_2;
reg [31:0] system_bus_data_0;
reg [31:0] system_bus_data_1;
reg [31:0] system_bus_data_2;
reg [31:0] system_bus_data_3;
wire target_register;
always@(*)
begin
case(address)
0x04:
begin
target_register=abstract_data_0;
end
0x0f:
begin
end
endcase
end
haltreq = dmcontrol[31]? 1'b1: 1'b0;
resumereq = dmcontrol[30]? 1'b1:1'b0;
wire [31:0] abstractcs_next;
always@(posedge reset or posedge clk)
begin
if(reset)
abstractcs[12] <=1'b0;
else
abstractcs[12] <= ( write_en? 1'b1: abstractcs[12]);
end
assign register_index=command[15:0];
always@(*)
begin
case(command[31:24])
8'd0:
end
reg [`DM_STATE_WIDTH-1] dm_state;
wire [`DM_STATE_WIDTH-1] dm_state_next;
reg command_written;
always@(posedge reset or posedge clk)
begin
if(reset)
dm_state<=`DM_STATE_WIDTH'd0;
else
dm_state<=dm_state_next;
end
always@(*)
begin
dmstatus_next=dmstatus;
haltreq=1'b0;
resumereq=1'b0;
debug_write=1'b0;
debug_read=1'b0;
register_index=12'd0;
debug_wdata=`XPR_LEN'd0;
abstract_data_0_next=abstract_data_0;
dm_busy=1'b0;
case(dm_state)
`DM_MUSH_MODE:
begin
if(dmcontrol[31])
begin
dm_state_next=`DM_HALTING;
dmstatus_next[10]=1'b0;
dmstatus_next[11]=1'b0;
end
end
`DM_HALTING:
begin
haltreq=1'b1;
if(core_haltack)
begin
dm_state_next=`DM_HALTED;
dmstatus_next[9]=1'b1;
dmstatus_next[8]=1'b1;
end
end
`DM_HALTED:
begin
if(command_written==1'b1 && command[31:24]==8'd1)
begin
dm_state_next=`DM_COMMAND_CHECKED;
abstractcs_next[12]=1'b1;
end
end
`DM_COMMAND_CHECKED:
begin
dm_busy=1'b1;
if(write_en==1'b1)
begin
dm_state_next=`DM_ERROR_DETECTED;
abstractcs_next[10:8]=3'd1;
end
else if(command[31:24]!=8'd1)
begin
dm_state_next=`DM_ERROR_DETECTED;
abstractcs_next[10:8]=3'd2;
end
else if(command[22:20]!=3'd2)
begin
dm_state_next=`DM_ERROR_DETECTED;
abstractcs_next[10:8]=3'd3;
end
else if(dmstatus[9]==1'b0)
begin
dm_state_next=`DM_ERROR_DETECTED;
abstractcs_next[10:8]=3'd4;
end
else
begin
dm_state_next=`DM_ACCESS_COMMAND_EXECUTING_1;
abstractcs_next[10:8]=3'd0;
end
end
`DM_ACCESS_COMMAND_EXECUTING_1:
begin
dm_busy=1'b1;
if(command[16]==1'b0 && command[17]==1'b1)
begin
debug_read=1'b1;
register_index=command[11:0];
if(reg_rack==1'b1)
begin
dm_state_next=`DM_HALTED;
abstract_data_0_next=debug_rdata;
end
else
begin
dm_state_next=`DM_ACCESS_COMMAND_EXECUTING_1;
end
end
else if(command[16]==1'b1 && command[17]==1'b1)
begin
debug_write=1'b1;
register_index=command[11:0];
debug_wdata=abstract_data_0;
if(reg_wack==1'b1)
begin
dm_state_next=`DM_HALTED;
end
else
begin
dm_state_next=`DM_ACCESS_COMMAND_EXECUTING_1;
end
end
else
dm_state_next=`DM_HALTED;
end
endcase
end
endmodule | 0 |
138,513 | data/full_repos/permissive/84399449/acciones_to_bcd.v | 84,399,449 | acciones_to_bcd.v | v | 99 | 91 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xe1 in position 626: invalid continuation byte | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/84399449/acciones_to_bcd.v:45: Unsupported: Ignoring delay on this delayed statement.\n #10 BCD4 = 4\'b0001;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/84399449/acciones_to_bcd.v:47: Unsupported: Ignoring delay on this delayed statement.\n #10 BCD3 = 4\'b1001;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84399449/acciones_to_bcd.v:67: Unsupported: Ignoring delay on this delayed statement.\n #10 BCD1 = 4\'b0000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84399449/acciones_to_bcd.v:87: Unsupported: Ignoring delay on this delayed statement.\n #10 BCD2 = 4\'b0110;\n ^\n%Error: Exiting due to 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,505 | module | module acciones_to_bcd(
input clk,
input rst,
input [1:0] piso,
input [1:0] accion,
input puertas,
output reg [3:0] BCD1,
output reg [3:0] BCD2,
output reg [3:0] BCD3,
output reg [3:0] BCD4
);
initial begin
BCD4 = 1;
BCD3 = 9;
BCD2 = 6;
BCD1 = 0;
end
always @ (posedge clk)
begin
if (rst == 1)
begin
BCD4 = 4'b1110;
#10 BCD4 = 4'b0001;
BCD3 = 4'b0110;
#10 BCD3 = 4'b1001;
end
else
begin
if (piso == 2'b00)
BCD4 = 4'b0001;
else if (piso == 2'b01)
BCD4 = 4'b0010;
else if (piso == 2'b10)
BCD4 = 4'b0011;
else
BCD4 = 4'b0100;
end
end
always @ (posedge clk)
begin
if (rst == 1)
begin
BCD1 = 4'b1111;
#10 BCD1 = 4'b0000;
end
else
begin
if (accion == 2'b00)
BCD1 = 4'b0000;
else if (accion == 2'b01)
BCD1 = 4'b0101;
else if (accion == 2'b10)
BCD1 = 4'b1000;
else
BCD1 = 0;
end
end
always @ (posedge clk)
begin
if (rst == 1)
begin
BCD2 = 4'b1001;
#10 BCD2 = 4'b0110;
end
else
begin
if (puertas == 1'b0)
BCD2 = 4'b0111;
else
BCD2 = 4'b0110;
end
end
endmodule | module acciones_to_bcd(
input clk,
input rst,
input [1:0] piso,
input [1:0] accion,
input puertas,
output reg [3:0] BCD1,
output reg [3:0] BCD2,
output reg [3:0] BCD3,
output reg [3:0] BCD4
); |
initial begin
BCD4 = 1;
BCD3 = 9;
BCD2 = 6;
BCD1 = 0;
end
always @ (posedge clk)
begin
if (rst == 1)
begin
BCD4 = 4'b1110;
#10 BCD4 = 4'b0001;
BCD3 = 4'b0110;
#10 BCD3 = 4'b1001;
end
else
begin
if (piso == 2'b00)
BCD4 = 4'b0001;
else if (piso == 2'b01)
BCD4 = 4'b0010;
else if (piso == 2'b10)
BCD4 = 4'b0011;
else
BCD4 = 4'b0100;
end
end
always @ (posedge clk)
begin
if (rst == 1)
begin
BCD1 = 4'b1111;
#10 BCD1 = 4'b0000;
end
else
begin
if (accion == 2'b00)
BCD1 = 4'b0000;
else if (accion == 2'b01)
BCD1 = 4'b0101;
else if (accion == 2'b10)
BCD1 = 4'b1000;
else
BCD1 = 0;
end
end
always @ (posedge clk)
begin
if (rst == 1)
begin
BCD2 = 4'b1001;
#10 BCD2 = 4'b0110;
end
else
begin
if (puertas == 1'b0)
BCD2 = 4'b0111;
else
BCD2 = 4'b0110;
end
end
endmodule | 0 |
138,514 | data/full_repos/permissive/84399449/bcd_to_display.v | 84,399,449 | bcd_to_display.v | v | 44 | 82 | [] | [] | [] | [(6, 43)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/84399449/bcd_to_display.v:15: Unsupported: Ignoring delay on this delayed statement.\n #10 DISPLAY = 8\'b00000000;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/84399449/bcd_to_display.v:23: Unsupported: Ignoring delay on this delayed statement.\n #10 DISPLAY = 8\'b00000000;\n ^\n%Error: Exiting due to 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,506 | module | module bcd_to_display(
input clk,
input rst,
input [3:0] BCD,
output reg[7:0] DISPLAY
);
initial begin
DISPLAY = 8'b11111111;
#10 DISPLAY = 8'b00000000;
end
always @ (posedge clk)
begin
if (rst)
begin
DISPLAY = 8'b11111111;
#10 DISPLAY = 8'b00000000;
end
else
begin
case (BCD)
4'b0000: DISPLAY = 8'b11111110;
4'b0001: DISPLAY = 8'b11001111;
4'b0010: DISPLAY = 8'b10010010;
4'b0011: DISPLAY = 8'b10000110;
4'b0100: DISPLAY = 8'b11001100;
4'b0101: DISPLAY = 8'b10100100;
4'b0110: DISPLAY = 8'b10001000;
4'b0111: DISPLAY = 8'b10110001;
4'b1000: DISPLAY = 8'b10000000;
4'b1001: DISPLAY = 8'b10011000;
default: DISPLAY = 8'b0;
endcase
end
end
endmodule | module bcd_to_display(
input clk,
input rst,
input [3:0] BCD,
output reg[7:0] DISPLAY
); |
initial begin
DISPLAY = 8'b11111111;
#10 DISPLAY = 8'b00000000;
end
always @ (posedge clk)
begin
if (rst)
begin
DISPLAY = 8'b11111111;
#10 DISPLAY = 8'b00000000;
end
else
begin
case (BCD)
4'b0000: DISPLAY = 8'b11111110;
4'b0001: DISPLAY = 8'b11001111;
4'b0010: DISPLAY = 8'b10010010;
4'b0011: DISPLAY = 8'b10000110;
4'b0100: DISPLAY = 8'b11001100;
4'b0101: DISPLAY = 8'b10100100;
4'b0110: DISPLAY = 8'b10001000;
4'b0111: DISPLAY = 8'b10110001;
4'b1000: DISPLAY = 8'b10000000;
4'b1001: DISPLAY = 8'b10011000;
default: DISPLAY = 8'b0;
endcase
end
end
endmodule | 0 |
138,515 | data/full_repos/permissive/84399449/fpgadisplay_controller.v | 84,399,449 | fpgadisplay_controller.v | v | 80 | 106 | [] | [] | [] | null | line:43: before: "play" | null | 1: b'%Error: data/full_repos/permissive/84399449/fpgadisplay_controller.v:28: Cannot find file containing module: \'frequency_divider\'\n frequency_divider divisor (CLK_1Hz, CLK_2Hz, CLK_1KHz, clk);\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/84399449,data/full_repos/permissive/84399449/frequency_divider\n data/full_repos/permissive/84399449,data/full_repos/permissive/84399449/frequency_divider.v\n data/full_repos/permissive/84399449,data/full_repos/permissive/84399449/frequency_divider.sv\n frequency_divider\n frequency_divider.v\n frequency_divider.sv\n obj_dir/frequency_divider\n obj_dir/frequency_divider.v\n obj_dir/frequency_divider.sv\n%Warning-WIDTH: data/full_repos/permissive/84399449/fpgadisplay_controller.v:37: Operator EQ expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'contador_seg\' generates 1 bits.\n : ... In instance display_refresher\n if (contador_seg == 10)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/84399449/fpgadisplay_controller.v:55: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'DISPLAY1\' generates 1 bits.\n : ... In instance display_refresher\n DISPLAY = DISPLAY1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84399449/fpgadisplay_controller.v:60: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'DISPLAY2\' generates 1 bits.\n : ... In instance display_refresher\n DISPLAY = DISPLAY2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84399449/fpgadisplay_controller.v:65: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'DISPLAY3\' generates 1 bits.\n : ... In instance display_refresher\n DISPLAY = DISPLAY3;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84399449/fpgadisplay_controller.v:70: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'DISPLAY4\' generates 1 bits.\n : ... In instance display_refresher\n DISPLAY = DISPLAY4;\n ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n' | 302,507 | module | module display_refresher(
input clk,
input DISPLAY1,
input DISPLAY2,
input DISPLAY3,
input DISPLAY4,
output reg [6:0] DISPLAY,
output reg [3:0] ANODES,
output reg contador_seg
);
reg [1:0] Prstate, Nxtstate;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
initial begin Prstate = S0; end
(* keep="soft" *)
wire CLK_1Hz;
(* keep="soft" *)
wire CLK_2Hz;
wire CLK_1KHz;
frequency_divider divisor (CLK_1Hz, CLK_2Hz, CLK_1KHz, clk);
always @ (posedge CLK_1KHz) begin
Prstate = Nxtstate;
end
always @ (posedge CLK_1Hz)
begin
contador_seg = contador_seg + 1;
if (contador_seg == 10)
contador_seg = 0;
end
always @ (Prstate)
case (Prstate)
S0: Nxtstate = S1;
S1: Nxtstate = S2;
S2: Nxtstate = S3;
S3: Nxtstate = S0;
default: Nxtstate = S0;
endcase
always @ (*)
case (Prstate)
S0:
begin
ANODES = 4'b1110;
DISPLAY = DISPLAY1;
end
S1:
begin
ANODES = 4'b1101;
DISPLAY = DISPLAY2;
end
S2:
begin
ANODES = 4'b1011;
DISPLAY = DISPLAY3;
end
S3:
begin
ANODES = 4'b0111;
DISPLAY = DISPLAY4;
end
default:
begin
ANODES = 4'b0000;
DISPLAY = 7'b1111110;
end
endcase
endmodule | module display_refresher(
input clk,
input DISPLAY1,
input DISPLAY2,
input DISPLAY3,
input DISPLAY4,
output reg [6:0] DISPLAY,
output reg [3:0] ANODES,
output reg contador_seg
); |
reg [1:0] Prstate, Nxtstate;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
initial begin Prstate = S0; end
(* keep="soft" *)
wire CLK_1Hz;
(* keep="soft" *)
wire CLK_2Hz;
wire CLK_1KHz;
frequency_divider divisor (CLK_1Hz, CLK_2Hz, CLK_1KHz, clk);
always @ (posedge CLK_1KHz) begin
Prstate = Nxtstate;
end
always @ (posedge CLK_1Hz)
begin
contador_seg = contador_seg + 1;
if (contador_seg == 10)
contador_seg = 0;
end
always @ (Prstate)
case (Prstate)
S0: Nxtstate = S1;
S1: Nxtstate = S2;
S2: Nxtstate = S3;
S3: Nxtstate = S0;
default: Nxtstate = S0;
endcase
always @ (*)
case (Prstate)
S0:
begin
ANODES = 4'b1110;
DISPLAY = DISPLAY1;
end
S1:
begin
ANODES = 4'b1101;
DISPLAY = DISPLAY2;
end
S2:
begin
ANODES = 4'b1011;
DISPLAY = DISPLAY3;
end
S3:
begin
ANODES = 4'b0111;
DISPLAY = DISPLAY4;
end
default:
begin
ANODES = 4'b0000;
DISPLAY = 7'b1111110;
end
endcase
endmodule | 0 |
138,516 | data/full_repos/permissive/84399449/frequency_divider.v | 84,399,449 | frequency_divider.v | v | 40 | 86 | [] | [] | [] | [(3, 33)] | null | data/verilator_xmls/90e0df12-ee8a-4dad-82ab-f1dc86cf6477.xml | null | 302,508 | module | module frequency_divider(output CLK_1Hz, output CLK_2Hz, output CLK_1KHz, input CLK);
reg [26:0] count_1Hz;
reg [25:0] count_2Hz;
reg [16:0] count_1KHz;
initial begin count_1Hz=0; count_2Hz=0; count_1KHz=0; end
always @ (posedge CLK)
begin
count_1Hz = count_1Hz+27'b000000000000000000000000001;
count_2Hz = count_2Hz+26'b00000000000000000000000001;
count_1KHz = count_1KHz+17'b00000000000000001;
end
assign CLK_1Hz = count_1Hz[26];
assign CLK_2Hz = count_2Hz[25];
assign CLK_1KHz = count_1KHz[16];
endmodule | module frequency_divider(output CLK_1Hz, output CLK_2Hz, output CLK_1KHz, input CLK); |
reg [26:0] count_1Hz;
reg [25:0] count_2Hz;
reg [16:0] count_1KHz;
initial begin count_1Hz=0; count_2Hz=0; count_1KHz=0; end
always @ (posedge CLK)
begin
count_1Hz = count_1Hz+27'b000000000000000000000000001;
count_2Hz = count_2Hz+26'b00000000000000000000000001;
count_1KHz = count_1KHz+17'b00000000000000001;
end
assign CLK_1Hz = count_1Hz[26];
assign CLK_2Hz = count_2Hz[25];
assign CLK_1KHz = count_1KHz[16];
endmodule | 0 |
138,517 | data/full_repos/permissive/84399449/manejo_entradas.v | 84,399,449 | manejo_entradas.v | v | 68 | 174 | [] | [] | [] | [(22, 67)] | null | data/verilator_xmls/2d95b95f-cc0c-46ac-abd9-a2f5ff8943ec.xml | null | 302,509 | module | module manejo_entradas(
input clk,
input piso1,
input piso2,
input piso3,
input piso4,
input S1,
input B2,
input S2,
input B3,
input S3,
input B4,
output reg [3:0] boton_pres
);
initial begin
boton_pres = 0;
end
always @ (posedge clk)
begin
if (piso1)
boton_pres = 1;
else if (piso2)
boton_pres = 2;
else if (piso3)
boton_pres = 3;
else if (piso4)
boton_pres = 4;
else if (S1)
boton_pres = 5;
else if (B2)
boton_pres = 6;
else if (S2)
boton_pres = 7;
else if (B3)
boton_pres = 8;
else if (S3)
boton_pres = 9;
else if (B4)
boton_pres = 10;
else
boton_pres = 0;
end
endmodule | module manejo_entradas(
input clk,
input piso1,
input piso2,
input piso3,
input piso4,
input S1,
input B2,
input S2,
input B3,
input S3,
input B4,
output reg [3:0] boton_pres
); |
initial begin
boton_pres = 0;
end
always @ (posedge clk)
begin
if (piso1)
boton_pres = 1;
else if (piso2)
boton_pres = 2;
else if (piso3)
boton_pres = 3;
else if (piso4)
boton_pres = 4;
else if (S1)
boton_pres = 5;
else if (B2)
boton_pres = 6;
else if (S2)
boton_pres = 7;
else if (B3)
boton_pres = 8;
else if (S3)
boton_pres = 9;
else if (B4)
boton_pres = 10;
else
boton_pres = 0;
end
endmodule | 0 |
138,518 | data/full_repos/permissive/84399449/manejo_memoria.v | 84,399,449 | manejo_memoria.v | v | 337 | 193 | [] | [] | [] | [(21, 336)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/84399449/manejo_memoria.v:86: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'contador\' generates 32 bits.\n : ... In instance manejo_memoria\n indice_encontrado = contador;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/84399449/manejo_memoria.v:116: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'contador\' generates 32 bits.\n : ... In instance manejo_memoria\n indice_encontrado = contador;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84399449/manejo_memoria.v:127: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'contador\' generates 32 bits.\n : ... In instance manejo_memoria\n indice_encontrado = contador;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84399449/manejo_memoria.v:139: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'contador\' generates 32 bits.\n : ... In instance manejo_memoria\n indice_encontrado = contador;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84399449/manejo_memoria.v:149: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'contador\' generates 32 bits.\n : ... In instance manejo_memoria\n indice_encontrado = contador;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84399449/manejo_memoria.v:167: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'contador\' generates 32 bits.\n : ... In instance manejo_memoria\n indice_encontrado = contador;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84399449/manejo_memoria.v:177: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'contador\' generates 32 bits.\n : ... In instance manejo_memoria\n indice_encontrado = contador;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84399449/manejo_memoria.v:189: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'contador\' generates 32 bits.\n : ... In instance manejo_memoria\n indice_encontrado = contador;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84399449/manejo_memoria.v:199: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'contador\' generates 32 bits.\n : ... In instance manejo_memoria\n indice_encontrado = contador;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84399449/manejo_memoria.v:211: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'contador\' generates 32 bits.\n : ... In instance manejo_memoria\n indice_encontrado = contador;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84399449/manejo_memoria.v:230: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'contador\' generates 32 bits.\n : ... In instance manejo_memoria\n indice_encontrado = contador;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84399449/manejo_memoria.v:240: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'contador\' generates 32 bits.\n : ... In instance manejo_memoria\n indice_encontrado = contador;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84399449/manejo_memoria.v:252: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'contador\' generates 32 bits.\n : ... In instance manejo_memoria\n indice_encontrado = contador;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84399449/manejo_memoria.v:265: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'contador\' generates 32 bits.\n : ... In instance manejo_memoria\n indice_encontrado = contador;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84399449/manejo_memoria.v:275: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'contador\' generates 32 bits.\n : ... In instance manejo_memoria\n indice_encontrado = contador;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84399449/manejo_memoria.v:293: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'contador\' generates 32 bits.\n : ... In instance manejo_memoria\n indice_encontrado = contador;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84399449/manejo_memoria.v:303: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'contador\' generates 32 bits.\n : ... In instance manejo_memoria\n indice_encontrado = contador;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84399449/manejo_memoria.v:315: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'contador\' generates 32 bits.\n : ... In instance manejo_memoria\n indice_encontrado = contador;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84399449/manejo_memoria.v:325: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'contador\' generates 32 bits.\n : ... In instance manejo_memoria\n indice_encontrado = contador;\n ^\n%Error: Exiting due to 19 warning(s)\n' | 302,510 | module | module manejo_memoria(
input clk,
input rst,
input LE,
input puertas_m,
input [1:0] accion_m,
input [1:0] piso_m,
input [3:0] boton_pres,
output reg [3:0] memoria
);
reg [3:0] RAM [0:11];
reg [4:0] indice_encontrado = 11;
integer contador = 0;
reg insertado = 0;
reg obteniendo = 0;
initial begin
RAM[0] = 0;
RAM[1] = 0;
RAM[2] = 0;
RAM[3] = 0;
RAM[4] = 0;
RAM[5] = 0;
RAM[6] = 0;
RAM[7] = 0;
RAM[8] = 0;
RAM[9] = 0;
RAM[10] = 0;
RAM[11] = 0;
memoria = 0;
end
always @ (posedge clk)
begin
if (rst)
begin
memoria = 0;
RAM[0] = 0;
RAM[1] = 0;
RAM[2] = 0;
RAM[3] = 0;
RAM[4] = 0;
RAM[5] = 0;
RAM[6] = 0;
RAM[7] = 0;
RAM[8] = 0;
RAM[9] = 0;
RAM[10] = 0;
RAM[11] = 0;
end
else
if (LE == 1)
begin
obteniendo = 1;
insertado = 0;
indice_encontrado = 11;
if (boton_pres == 0)
RAM[11] = 0;
else
for (contador = 0; contador <= 10; contador = contador + 1)
begin
if (RAM[contador] == boton_pres)
begin
indice_encontrado = contador;
end
end
if (indice_encontrado == 11)
begin
for (contador = 10; contador >= 0; contador = contador - 1)
if ((RAM[contador] == 0) && (insertado == 0))
begin
insertado = 1;
RAM[contador] = boton_pres;
end
end
end
else
begin
if (obteniendo == 1)
begin
obteniendo = 0;
if (piso_m == 0)
begin
if (accion_m == 0)
begin
indice_encontrado = 11;
for (contador = 0; contador <= 10; contador = contador + 1)
begin
if (RAM[contador] == 1 || RAM[contador] == 5)
begin
RAM[contador] = 0;
if (puertas_m == 0)
begin
indice_encontrado = contador;
memoria = 1;
end
end
end
if (indice_encontrado == 11)
begin
for (contador = 10; contador >= 0; contador = contador - 1)
if (RAM[contador] == 2 || RAM[contador] == 3 || RAM[contador] == 4 || RAM[contador] == 6 || RAM[contador] == 7 || RAM[contador] == 8 || RAM[contador] == 9 || RAM[contador] == 10)
begin
memoria = RAM[contador];
indice_encontrado = contador;
end
if (indice_encontrado == 11)
memoria = 0;
end
end
else if (accion_m == 1)
begin
indice_encontrado = 11;
for (contador = 0; contador <= 10; contador = contador + 1)
if (RAM[contador] == 2 || RAM[contador] == 7)
begin
indice_encontrado = contador;
memoria = RAM[contador];
RAM[contador] = 0;
end
if (indice_encontrado == 11)
begin
for (contador = 10; contador >= 0; contador = contador - 1)
if (RAM[contador] == 3 || RAM[contador] == 4 || RAM[contador] == 6 || RAM[contador] == 8 || RAM[contador] == 9 || RAM[contador] == 10)
begin
memoria = RAM[contador];
indice_encontrado = contador;
end
if (indice_encontrado == 11)
memoria = 0;
end
end
end
else if (piso_m == 1)
begin
if (accion_m == 0)
begin
indice_encontrado = 11;
for (contador = 0; contador <= 10; contador = contador + 1)
if (RAM[contador] == 2 || RAM[contador] == 6 || RAM[contador] == 7)
begin
RAM[contador] = 0;
if (puertas_m == 0)
begin
indice_encontrado = contador;
memoria = 2;
end
end
if (indice_encontrado == 11)
begin
for (contador = 10; contador >= 0; contador = contador - 1)
if (RAM[contador] == 1 || RAM[contador] == 3 || RAM[contador] == 4 || RAM[contador] == 5 || RAM[contador] == 8 || RAM[contador] == 9 || RAM[contador] == 10)
begin
memoria = RAM[contador];
indice_encontrado = contador;
end
if (indice_encontrado == 11)
memoria = 0;
end
end
else if (accion_m == 1)
begin
indice_encontrado = 11;
for (contador = 0; contador <= 10; contador = contador + 1)
if (RAM[contador] == 3 || RAM[contador] == 9)
begin
indice_encontrado = contador;
memoria = RAM[contador];
RAM[contador] = 0;
end
if (indice_encontrado == 11)
begin
for (contador = 10; contador >= 0; contador = contador - 1)
if (RAM[contador] == 4 || RAM[contador] == 10 || RAM[contador] == 8)
begin
memoria = RAM[contador];
indice_encontrado = contador;
end
if (indice_encontrado == 11)
memoria = 0;
end
end
else if (accion_m == 2)
begin
indice_encontrado = 11;
for (contador = 0; contador <= 10; contador = contador + 1)
if (RAM[contador] == 1 || RAM[contador] == 5)
begin
indice_encontrado = contador;
memoria = RAM[contador];
RAM[contador] = 0;
end
if (indice_encontrado == 11)
memoria = 0;
end
end
else if (piso_m==2)
begin
if (accion_m == 0)
begin
indice_encontrado = 11;
for (contador = 0; contador <= 10; contador = contador + 1)
if (RAM[contador] == 3 || RAM[contador] == 8 || RAM[contador] == 9)
begin
RAM[contador] = 0;
if (puertas_m == 0)
begin
indice_encontrado = contador;
memoria = 3;
end
end
if (indice_encontrado == 11)
begin
for (contador = 10; contador >= 0; contador = contador - 1)
if (RAM[contador] == 2 || RAM[contador] == 1 || RAM[contador] == 4 || RAM[contador] == 6 || RAM[contador] == 7 || RAM[contador] == 5 || RAM[contador] == 10)
begin
memoria = RAM[contador];
indice_encontrado = contador;
end
if (indice_encontrado == 11)
memoria = 0;
end
end
else if (accion_m == 1)
begin
indice_encontrado = 11;
for (contador = 0; contador <= 10; contador = contador + 1)
if (RAM[contador] == 4 || RAM[contador] == 10)
begin
indice_encontrado = contador;
memoria = RAM[contador];
RAM[contador] = 0;
end
if (indice_encontrado == 11)
memoria = 0;
end
else if (accion_m == 2)
begin
indice_encontrado = 11;
for (contador = 0; contador <= 10; contador = contador + 1)
if (RAM[contador] == 2 || RAM[contador] == 6)
begin
indice_encontrado = contador;
memoria = RAM[contador];
RAM[contador] = 0;
end
if (indice_encontrado == 11)
begin
for (contador = 10; contador >= 0; contador = contador - 1)
if (RAM[contador] == 1 || RAM[contador] == 5 || RAM[contador] == 7)
begin
memoria = RAM[contador];
indice_encontrado = contador;
end
if (indice_encontrado == 11)
memoria = 0;
end
end
end
else
begin
if (accion_m == 0)
begin
indice_encontrado = 11;
for (contador = 0; contador <= 10; contador = contador + 1)
if (RAM[contador] == 4 || RAM[contador] == 10)
begin
RAM[contador] = 0;
if (puertas_m == 0)
begin
indice_encontrado = contador;
memoria = 4;
end
end
if (indice_encontrado == 11)
begin
for (contador = 10; contador >= 0; contador = contador - 1)
if (RAM[contador] == 2 || RAM[contador] == 3 || RAM[contador] == 1 || RAM[contador] == 6 || RAM[contador] == 7 || RAM[contador] == 8 || RAM[contador] == 9 || RAM[contador] == 5)
begin
memoria = RAM[contador];
indice_encontrado = contador;
end
if (indice_encontrado == 11)
memoria = 0;
end
end
else if (accion_m == 2)
begin
indice_encontrado = 11;
for (contador = 0; contador <= 10; contador = contador + 1)
if (RAM[contador] == 3 || RAM[contador] == 8)
begin
indice_encontrado = contador;
memoria = RAM[contador];
RAM[contador] = 0;
end
if (indice_encontrado == 11)
begin
for (contador = 10; contador >= 0; contador = contador - 1)
if (RAM[contador] == 1 || RAM[contador] == 2 || RAM[contador] == 5 || RAM[contador] == 6 || RAM[contador] == 7 || RAM[contador] == 9)
begin
memoria = RAM[contador];
indice_encontrado = contador;
end
if (indice_encontrado == 11)
memoria = 0;
end
end
end
end
end
end
endmodule | module manejo_memoria(
input clk,
input rst,
input LE,
input puertas_m,
input [1:0] accion_m,
input [1:0] piso_m,
input [3:0] boton_pres,
output reg [3:0] memoria
); |
reg [3:0] RAM [0:11];
reg [4:0] indice_encontrado = 11;
integer contador = 0;
reg insertado = 0;
reg obteniendo = 0;
initial begin
RAM[0] = 0;
RAM[1] = 0;
RAM[2] = 0;
RAM[3] = 0;
RAM[4] = 0;
RAM[5] = 0;
RAM[6] = 0;
RAM[7] = 0;
RAM[8] = 0;
RAM[9] = 0;
RAM[10] = 0;
RAM[11] = 0;
memoria = 0;
end
always @ (posedge clk)
begin
if (rst)
begin
memoria = 0;
RAM[0] = 0;
RAM[1] = 0;
RAM[2] = 0;
RAM[3] = 0;
RAM[4] = 0;
RAM[5] = 0;
RAM[6] = 0;
RAM[7] = 0;
RAM[8] = 0;
RAM[9] = 0;
RAM[10] = 0;
RAM[11] = 0;
end
else
if (LE == 1)
begin
obteniendo = 1;
insertado = 0;
indice_encontrado = 11;
if (boton_pres == 0)
RAM[11] = 0;
else
for (contador = 0; contador <= 10; contador = contador + 1)
begin
if (RAM[contador] == boton_pres)
begin
indice_encontrado = contador;
end
end
if (indice_encontrado == 11)
begin
for (contador = 10; contador >= 0; contador = contador - 1)
if ((RAM[contador] == 0) && (insertado == 0))
begin
insertado = 1;
RAM[contador] = boton_pres;
end
end
end
else
begin
if (obteniendo == 1)
begin
obteniendo = 0;
if (piso_m == 0)
begin
if (accion_m == 0)
begin
indice_encontrado = 11;
for (contador = 0; contador <= 10; contador = contador + 1)
begin
if (RAM[contador] == 1 || RAM[contador] == 5)
begin
RAM[contador] = 0;
if (puertas_m == 0)
begin
indice_encontrado = contador;
memoria = 1;
end
end
end
if (indice_encontrado == 11)
begin
for (contador = 10; contador >= 0; contador = contador - 1)
if (RAM[contador] == 2 || RAM[contador] == 3 || RAM[contador] == 4 || RAM[contador] == 6 || RAM[contador] == 7 || RAM[contador] == 8 || RAM[contador] == 9 || RAM[contador] == 10)
begin
memoria = RAM[contador];
indice_encontrado = contador;
end
if (indice_encontrado == 11)
memoria = 0;
end
end
else if (accion_m == 1)
begin
indice_encontrado = 11;
for (contador = 0; contador <= 10; contador = contador + 1)
if (RAM[contador] == 2 || RAM[contador] == 7)
begin
indice_encontrado = contador;
memoria = RAM[contador];
RAM[contador] = 0;
end
if (indice_encontrado == 11)
begin
for (contador = 10; contador >= 0; contador = contador - 1)
if (RAM[contador] == 3 || RAM[contador] == 4 || RAM[contador] == 6 || RAM[contador] == 8 || RAM[contador] == 9 || RAM[contador] == 10)
begin
memoria = RAM[contador];
indice_encontrado = contador;
end
if (indice_encontrado == 11)
memoria = 0;
end
end
end
else if (piso_m == 1)
begin
if (accion_m == 0)
begin
indice_encontrado = 11;
for (contador = 0; contador <= 10; contador = contador + 1)
if (RAM[contador] == 2 || RAM[contador] == 6 || RAM[contador] == 7)
begin
RAM[contador] = 0;
if (puertas_m == 0)
begin
indice_encontrado = contador;
memoria = 2;
end
end
if (indice_encontrado == 11)
begin
for (contador = 10; contador >= 0; contador = contador - 1)
if (RAM[contador] == 1 || RAM[contador] == 3 || RAM[contador] == 4 || RAM[contador] == 5 || RAM[contador] == 8 || RAM[contador] == 9 || RAM[contador] == 10)
begin
memoria = RAM[contador];
indice_encontrado = contador;
end
if (indice_encontrado == 11)
memoria = 0;
end
end
else if (accion_m == 1)
begin
indice_encontrado = 11;
for (contador = 0; contador <= 10; contador = contador + 1)
if (RAM[contador] == 3 || RAM[contador] == 9)
begin
indice_encontrado = contador;
memoria = RAM[contador];
RAM[contador] = 0;
end
if (indice_encontrado == 11)
begin
for (contador = 10; contador >= 0; contador = contador - 1)
if (RAM[contador] == 4 || RAM[contador] == 10 || RAM[contador] == 8)
begin
memoria = RAM[contador];
indice_encontrado = contador;
end
if (indice_encontrado == 11)
memoria = 0;
end
end
else if (accion_m == 2)
begin
indice_encontrado = 11;
for (contador = 0; contador <= 10; contador = contador + 1)
if (RAM[contador] == 1 || RAM[contador] == 5)
begin
indice_encontrado = contador;
memoria = RAM[contador];
RAM[contador] = 0;
end
if (indice_encontrado == 11)
memoria = 0;
end
end
else if (piso_m==2)
begin
if (accion_m == 0)
begin
indice_encontrado = 11;
for (contador = 0; contador <= 10; contador = contador + 1)
if (RAM[contador] == 3 || RAM[contador] == 8 || RAM[contador] == 9)
begin
RAM[contador] = 0;
if (puertas_m == 0)
begin
indice_encontrado = contador;
memoria = 3;
end
end
if (indice_encontrado == 11)
begin
for (contador = 10; contador >= 0; contador = contador - 1)
if (RAM[contador] == 2 || RAM[contador] == 1 || RAM[contador] == 4 || RAM[contador] == 6 || RAM[contador] == 7 || RAM[contador] == 5 || RAM[contador] == 10)
begin
memoria = RAM[contador];
indice_encontrado = contador;
end
if (indice_encontrado == 11)
memoria = 0;
end
end
else if (accion_m == 1)
begin
indice_encontrado = 11;
for (contador = 0; contador <= 10; contador = contador + 1)
if (RAM[contador] == 4 || RAM[contador] == 10)
begin
indice_encontrado = contador;
memoria = RAM[contador];
RAM[contador] = 0;
end
if (indice_encontrado == 11)
memoria = 0;
end
else if (accion_m == 2)
begin
indice_encontrado = 11;
for (contador = 0; contador <= 10; contador = contador + 1)
if (RAM[contador] == 2 || RAM[contador] == 6)
begin
indice_encontrado = contador;
memoria = RAM[contador];
RAM[contador] = 0;
end
if (indice_encontrado == 11)
begin
for (contador = 10; contador >= 0; contador = contador - 1)
if (RAM[contador] == 1 || RAM[contador] == 5 || RAM[contador] == 7)
begin
memoria = RAM[contador];
indice_encontrado = contador;
end
if (indice_encontrado == 11)
memoria = 0;
end
end
end
else
begin
if (accion_m == 0)
begin
indice_encontrado = 11;
for (contador = 0; contador <= 10; contador = contador + 1)
if (RAM[contador] == 4 || RAM[contador] == 10)
begin
RAM[contador] = 0;
if (puertas_m == 0)
begin
indice_encontrado = contador;
memoria = 4;
end
end
if (indice_encontrado == 11)
begin
for (contador = 10; contador >= 0; contador = contador - 1)
if (RAM[contador] == 2 || RAM[contador] == 3 || RAM[contador] == 1 || RAM[contador] == 6 || RAM[contador] == 7 || RAM[contador] == 8 || RAM[contador] == 9 || RAM[contador] == 5)
begin
memoria = RAM[contador];
indice_encontrado = contador;
end
if (indice_encontrado == 11)
memoria = 0;
end
end
else if (accion_m == 2)
begin
indice_encontrado = 11;
for (contador = 0; contador <= 10; contador = contador + 1)
if (RAM[contador] == 3 || RAM[contador] == 8)
begin
indice_encontrado = contador;
memoria = RAM[contador];
RAM[contador] = 0;
end
if (indice_encontrado == 11)
begin
for (contador = 10; contador >= 0; contador = contador - 1)
if (RAM[contador] == 1 || RAM[contador] == 2 || RAM[contador] == 5 || RAM[contador] == 6 || RAM[contador] == 7 || RAM[contador] == 9)
begin
memoria = RAM[contador];
indice_encontrado = contador;
end
if (indice_encontrado == 11)
memoria = 0;
end
end
end
end
end
end
endmodule | 0 |
138,519 | data/full_repos/permissive/84399449/maquina_estados.v | 84,399,449 | maquina_estados.v | v | 371 | 107 | [] | [] | [] | null | line:122: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/84399449/maquina_estados.v:181: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/84399449/maquina_estados.v:86: Cannot find file containing module: \'frequency_divider\'\n frequency_divider divisor (CLK_1Hz, CLK_2Hz, CLK_1KHz, clk);\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/84399449,data/full_repos/permissive/84399449/frequency_divider\n data/full_repos/permissive/84399449,data/full_repos/permissive/84399449/frequency_divider.v\n data/full_repos/permissive/84399449,data/full_repos/permissive/84399449/frequency_divider.sv\n frequency_divider\n frequency_divider.v\n frequency_divider.sv\n obj_dir/frequency_divider\n obj_dir/frequency_divider.v\n obj_dir/frequency_divider.sv\n%Error: data/full_repos/permissive/84399449/maquina_estados.v:88: Cannot find file containing module: \'manejo_entradas\'\n manejo_entradas entradas(\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84399449/maquina_estados.v:103: Cannot find file containing module: \'manejo_memoria\'\n manejo_memoria memory(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84399449/maquina_estados.v:114: Cannot find file containing module: \'acciones_to_bcd\'\n acciones_to_bcd obtenerbcd(\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84399449/maquina_estados.v:126: Cannot find file containing module: \'bcd_to_display\'\n bcd_to_display deco1(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84399449/maquina_estados.v:133: Cannot find file containing module: \'bcd_to_display\'\n bcd_to_display deco2(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84399449/maquina_estados.v:140: Cannot find file containing module: \'bcd_to_display\'\n bcd_to_display deco3(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84399449/maquina_estados.v:147: Cannot find file containing module: \'bcd_to_display\'\n bcd_to_display deco4(\n ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/84399449/maquina_estados.v:319: Operator ADD expects 27 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n : ... In instance maquina_estados\n contador_ciclos = contador_ciclos + 4\'b000000000000000000000000001;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84399449/maquina_estados.v:365: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h7e\' generates 7 bits.\n : ... In instance maquina_estados\n DISPLAY = 7\'b1111110;\n ^\n%Error: Exiting due to 8 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,511 | module | module maquina_estados(
input clk,
input rst,
input piso1,
input piso2,
input piso3,
input piso4,
input S1,
input B2,
input S2,
input B3,
input S3,
input B4,
output reg[7:0] DISPLAY,
output reg[3:0] ANODES
);
parameter P1=0, P2=1, P3=2, P4=3;
reg [1:0] e_actual = P1;
reg [1:0] e_siguiente = P1;
reg agregar = 0;
reg obtener = 0;
wire [3:0] memoria;
reg [26:0] contador_ciclos = 0;
wire [3:0] boton_pres;
wire [3:0] BCD4, BCD3, BCD2, BCD1;
wire [7:0] DISPLAY4, DISPLAY3, DISPLAY2, DISPLAY1;
reg [1:0] piso = 0;
reg [1:0] accion = 0;
reg puertas = 0;
reg [3:0] contador_seg = 0;
reg LE = 1;
reg [1:0] Prstate, Nxtstate;
parameter State0 = 2'b00, State1 = 2'b01, State2 = 2'b10, State3 = 2'b11;
initial
begin
Prstate = State0;
piso = 0;
accion = 0;
puertas = 0;
contador_seg = 0;
end
(* keep="soft" *)
wire CLK_1Hz;
(* keep="soft" *)
wire CLK_2Hz;
wire CLK_1KHz;
frequency_divider divisor (CLK_1Hz, CLK_2Hz, CLK_1KHz, clk);
manejo_entradas entradas(
clk,
piso1,
piso2,
piso3,
piso4,
S1,
B2,
S2,
B3,
S3,
B4,
boton_pres
);
manejo_memoria memory(
clk,
rst,
LE,
puertas,
accion,
piso,
boton_pres,
memoria
);
acciones_to_bcd obtenerbcd(
clk,
rst,
piso,
accion,
puertas,
BCD1,
BCD2,
BCD3,
BCD4
);
bcd_to_display deco1(
clk,
rst,
BCD1,
DISPLAY4
);
bcd_to_display deco2(
clk,
rst,
BCD2,
DISPLAY3
);
bcd_to_display deco3(
clk,
rst,
BCD3,
DISPLAY2
);
bcd_to_display deco4(
clk,
rst,
BCD4,
DISPLAY1
);
always @ (posedge clk)
begin
if(rst)
begin
accion = 0;
piso = 0;
puertas = 0;
e_actual = P1;
LE = 1;
contador_seg = 4'b0;
end
else
begin
LE = 1;
if (contador_ciclos == 100000000)
begin
contador_seg = contador_seg + 4'b0001;
end
else if (contador_seg == 2)
begin
contador_seg = 4'b0;
LE = 0;
#200;
case(e_actual)
P1:begin
case(memoria)
0:
begin
piso = 0;
accion = 0;
puertas = 0;
e_siguiente=P1;
end
1,5:
begin
piso = 0;
accion = 0;
puertas = 1;
e_siguiente=P1;
end
2,3,4,6,7,8,9,10:
begin
piso = 0;
accion = 1;
puertas = 0;
e_siguiente=P2;
end
default:e_siguiente=P1;
endcase
end
P2:begin
case(memoria)
0:begin
piso = 1;
accion = 0;
puertas = 0;
e_siguiente=P2;
end
1,5:
begin
piso = 1;
accion = 2;
puertas = 0;
e_siguiente=P1;
end
2,6,7:begin
piso = 1;
accion = 0;
puertas = 1;
e_siguiente=P2;
end
3,4,8,9,10:begin
piso = 1;
accion = 1;
puertas = 0;
e_siguiente=P3;
end
default:e_siguiente=P1;
endcase
end
P3:begin
case(memoria)
0:begin
piso = 2;
accion = 0;
puertas = 0;
e_siguiente=P3;
end
1,2,5,6,7:
begin
piso = 2;
accion = 2;
puertas = 0;
e_siguiente=P2;
end
3,8,9:begin
piso = 2;
accion = 0;
puertas = 1;
e_siguiente=P3;
end
4,10:begin
piso = 2;
accion = 1;
puertas = 0;
e_siguiente=P4;
end
default:e_siguiente=P1;
endcase
end
P4:begin
case(memoria)
0:begin
piso = 3;
accion = 0;
puertas = 0;
e_siguiente=P4;
end
1,2,3,5,6,7,8,9:
begin
piso = 3;
accion = 2;
puertas = 0;
e_siguiente=P3;
end
4,10:begin
piso = 3;
accion = 0;
puertas = 1;
e_siguiente=P4;
end
default:e_siguiente=P1;
endcase
end
default: e_siguiente=P1;
endcase
e_actual = e_siguiente;
end
end
end
always @ (posedge clk)
begin
if (rst)
begin
contador_ciclos = 27'b0;
end
else
begin
contador_ciclos = contador_ciclos + 4'b000000000000000000000000001;
if (contador_ciclos == 100000100)
begin
contador_ciclos = 27'b0;
end
end
end
always @ (posedge CLK_1KHz) begin
Prstate = Nxtstate;
case (Prstate)
State0: Nxtstate = State1;
State1: Nxtstate = State2;
State2: Nxtstate = State3;
State3: Nxtstate = State0;
default: Nxtstate = State0;
endcase
end
always @ (posedge clk)
case (Prstate)
State0:
begin
ANODES = 4'b1110;
DISPLAY = DISPLAY1;
end
State1:
begin
ANODES = 4'b1101;
DISPLAY = DISPLAY2;
end
State2:
begin
ANODES = 4'b1011;
DISPLAY = DISPLAY3;
end
State3:
begin
ANODES = 4'b0111;
DISPLAY = DISPLAY4;
end
default:
begin
ANODES = 4'b0000;
DISPLAY = 7'b1111110;
end
endcase
endmodule | module maquina_estados(
input clk,
input rst,
input piso1,
input piso2,
input piso3,
input piso4,
input S1,
input B2,
input S2,
input B3,
input S3,
input B4,
output reg[7:0] DISPLAY,
output reg[3:0] ANODES
); |
parameter P1=0, P2=1, P3=2, P4=3;
reg [1:0] e_actual = P1;
reg [1:0] e_siguiente = P1;
reg agregar = 0;
reg obtener = 0;
wire [3:0] memoria;
reg [26:0] contador_ciclos = 0;
wire [3:0] boton_pres;
wire [3:0] BCD4, BCD3, BCD2, BCD1;
wire [7:0] DISPLAY4, DISPLAY3, DISPLAY2, DISPLAY1;
reg [1:0] piso = 0;
reg [1:0] accion = 0;
reg puertas = 0;
reg [3:0] contador_seg = 0;
reg LE = 1;
reg [1:0] Prstate, Nxtstate;
parameter State0 = 2'b00, State1 = 2'b01, State2 = 2'b10, State3 = 2'b11;
initial
begin
Prstate = State0;
piso = 0;
accion = 0;
puertas = 0;
contador_seg = 0;
end
(* keep="soft" *)
wire CLK_1Hz;
(* keep="soft" *)
wire CLK_2Hz;
wire CLK_1KHz;
frequency_divider divisor (CLK_1Hz, CLK_2Hz, CLK_1KHz, clk);
manejo_entradas entradas(
clk,
piso1,
piso2,
piso3,
piso4,
S1,
B2,
S2,
B3,
S3,
B4,
boton_pres
);
manejo_memoria memory(
clk,
rst,
LE,
puertas,
accion,
piso,
boton_pres,
memoria
);
acciones_to_bcd obtenerbcd(
clk,
rst,
piso,
accion,
puertas,
BCD1,
BCD2,
BCD3,
BCD4
);
bcd_to_display deco1(
clk,
rst,
BCD1,
DISPLAY4
);
bcd_to_display deco2(
clk,
rst,
BCD2,
DISPLAY3
);
bcd_to_display deco3(
clk,
rst,
BCD3,
DISPLAY2
);
bcd_to_display deco4(
clk,
rst,
BCD4,
DISPLAY1
);
always @ (posedge clk)
begin
if(rst)
begin
accion = 0;
piso = 0;
puertas = 0;
e_actual = P1;
LE = 1;
contador_seg = 4'b0;
end
else
begin
LE = 1;
if (contador_ciclos == 100000000)
begin
contador_seg = contador_seg + 4'b0001;
end
else if (contador_seg == 2)
begin
contador_seg = 4'b0;
LE = 0;
#200;
case(e_actual)
P1:begin
case(memoria)
0:
begin
piso = 0;
accion = 0;
puertas = 0;
e_siguiente=P1;
end
1,5:
begin
piso = 0;
accion = 0;
puertas = 1;
e_siguiente=P1;
end
2,3,4,6,7,8,9,10:
begin
piso = 0;
accion = 1;
puertas = 0;
e_siguiente=P2;
end
default:e_siguiente=P1;
endcase
end
P2:begin
case(memoria)
0:begin
piso = 1;
accion = 0;
puertas = 0;
e_siguiente=P2;
end
1,5:
begin
piso = 1;
accion = 2;
puertas = 0;
e_siguiente=P1;
end
2,6,7:begin
piso = 1;
accion = 0;
puertas = 1;
e_siguiente=P2;
end
3,4,8,9,10:begin
piso = 1;
accion = 1;
puertas = 0;
e_siguiente=P3;
end
default:e_siguiente=P1;
endcase
end
P3:begin
case(memoria)
0:begin
piso = 2;
accion = 0;
puertas = 0;
e_siguiente=P3;
end
1,2,5,6,7:
begin
piso = 2;
accion = 2;
puertas = 0;
e_siguiente=P2;
end
3,8,9:begin
piso = 2;
accion = 0;
puertas = 1;
e_siguiente=P3;
end
4,10:begin
piso = 2;
accion = 1;
puertas = 0;
e_siguiente=P4;
end
default:e_siguiente=P1;
endcase
end
P4:begin
case(memoria)
0:begin
piso = 3;
accion = 0;
puertas = 0;
e_siguiente=P4;
end
1,2,3,5,6,7,8,9:
begin
piso = 3;
accion = 2;
puertas = 0;
e_siguiente=P3;
end
4,10:begin
piso = 3;
accion = 0;
puertas = 1;
e_siguiente=P4;
end
default:e_siguiente=P1;
endcase
end
default: e_siguiente=P1;
endcase
e_actual = e_siguiente;
end
end
end
always @ (posedge clk)
begin
if (rst)
begin
contador_ciclos = 27'b0;
end
else
begin
contador_ciclos = contador_ciclos + 4'b000000000000000000000000001;
if (contador_ciclos == 100000100)
begin
contador_ciclos = 27'b0;
end
end
end
always @ (posedge CLK_1KHz) begin
Prstate = Nxtstate;
case (Prstate)
State0: Nxtstate = State1;
State1: Nxtstate = State2;
State2: Nxtstate = State3;
State3: Nxtstate = State0;
default: Nxtstate = State0;
endcase
end
always @ (posedge clk)
case (Prstate)
State0:
begin
ANODES = 4'b1110;
DISPLAY = DISPLAY1;
end
State1:
begin
ANODES = 4'b1101;
DISPLAY = DISPLAY2;
end
State2:
begin
ANODES = 4'b1011;
DISPLAY = DISPLAY3;
end
State3:
begin
ANODES = 4'b0111;
DISPLAY = DISPLAY4;
end
default:
begin
ANODES = 4'b0000;
DISPLAY = 7'b1111110;
end
endcase
endmodule | 0 |
138,520 | data/full_repos/permissive/84399449/memory_finder.v | 84,399,449 | memory_finder.v | v | 46 | 83 | [] | [] | [] | [(21, 45)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/84399449/memory_finder.v:40: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'contador\' generates 1 bits.\n : ... In instance memory_finder\n indice_encontrado = contador;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/84399449/memory_finder.v:37: Bit extraction of array[10:0] requires 4 bit index, not 1 bits.\n : ... In instance memory_finder\n if (RAM[contador] == boton)\n ^\n%Error: Exiting due to 2 warning(s)\n' | 302,512 | module | module memory_finder(
input [3:0] RAM [0:10],
input [3:0] boton,
input encontrar,
input pila,
output reg encontrado,
output reg [3:0] indice_encontrado);
reg contador = 0;
always @ (posedge encontrar)
begin
encontrado = 0;
indice_encontrado = 11;
begin
for (contador = 0; contador <= pila; contador = contador + 1)
if (RAM[contador] == boton)
begin
encontrado = 1;
indice_encontrado = contador;
end
end
end
endmodule | module memory_finder(
input [3:0] RAM [0:10],
input [3:0] boton,
input encontrar,
input pila,
output reg encontrado,
output reg [3:0] indice_encontrado); |
reg contador = 0;
always @ (posedge encontrar)
begin
encontrado = 0;
indice_encontrado = 11;
begin
for (contador = 0; contador <= pila; contador = contador + 1)
if (RAM[contador] == boton)
begin
encontrado = 1;
indice_encontrado = contador;
end
end
end
endmodule | 0 |
138,521 | data/full_repos/permissive/84399449/test.v | 84,399,449 | test.v | v | 59 | 81 | [] | [] | [] | null | None: at end of input | data/verilator_xmls/2ea4924e-b917-4eb5-b552-bd187195c53b.xml | null | 302,513 | module | module test;
endmodule | module test; |
endmodule | 0 |
138,522 | data/full_repos/permissive/84399449/testbench.v | 84,399,449 | testbench.v | v | 110 | 81 | [] | [] | [] | null | line:71: before: ")" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/84399449/testbench.v:89: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/84399449/testbench.v:90: Unsupported: Ignoring delay on this delayed statement.\n #10 rst = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84399449/testbench.v:91: Unsupported: Ignoring delay on this delayed statement.\n #10 rst = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84399449/testbench.v:92: Unsupported: Ignoring delay on this delayed statement.\n #10 piso2 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84399449/testbench.v:93: Unsupported: Ignoring delay on this delayed statement.\n #10 piso2 = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84399449/testbench.v:101: Unsupported: Ignoring delay on this delayed statement.\n #1 clk <= ~clk;\n ^\n%Error: data/full_repos/permissive/84399449/testbench.v:51: Cannot find file containing module: \'maquina_estados\'\n maquina_estados uut (\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/84399449,data/full_repos/permissive/84399449/maquina_estados\n data/full_repos/permissive/84399449,data/full_repos/permissive/84399449/maquina_estados.v\n data/full_repos/permissive/84399449,data/full_repos/permissive/84399449/maquina_estados.sv\n maquina_estados\n maquina_estados.v\n maquina_estados.sv\n obj_dir/maquina_estados\n obj_dir/maquina_estados.v\n obj_dir/maquina_estados.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,514 | module | module testbench;
reg clk;
reg rst;
reg piso1;
reg piso2;
reg piso3;
reg piso4;
reg S1;
reg B2;
reg S2;
reg B3;
reg S3;
reg B4;
wire [7:0] DISPLAY;
wire [3:0] ANODES;
maquina_estados uut (
.clk(clk),
.rst(rst),
.piso1(piso1),
.piso2(piso2),
.piso3(piso3),
.piso4(piso4),
.S1(S1),
.B2(B2),
.S2(S2),
.B3(B3),
.S3(S3),
.B4(B4),
.DISPLAY(DISPLAY),
.ANODES(ANODES),
);
initial begin
clk = 0;
rst = 0;
piso1 = 0;
piso2 = 0;
piso3 = 0;
piso4 = 0;
S1 = 0;
B2 = 0;
S2 = 0;
B3 = 0;
S3 = 0;
B4 = 0;
#100;
#10 rst = 1;
#10 rst = 0;
#10 piso2 = 1;
#10 piso2 = 0;
end
always
begin
#1 clk <= ~clk;
end
endmodule | module testbench; |
reg clk;
reg rst;
reg piso1;
reg piso2;
reg piso3;
reg piso4;
reg S1;
reg B2;
reg S2;
reg B3;
reg S3;
reg B4;
wire [7:0] DISPLAY;
wire [3:0] ANODES;
maquina_estados uut (
.clk(clk),
.rst(rst),
.piso1(piso1),
.piso2(piso2),
.piso3(piso3),
.piso4(piso4),
.S1(S1),
.B2(B2),
.S2(S2),
.B3(B3),
.S3(S3),
.B4(B4),
.DISPLAY(DISPLAY),
.ANODES(ANODES),
);
initial begin
clk = 0;
rst = 0;
piso1 = 0;
piso2 = 0;
piso3 = 0;
piso4 = 0;
S1 = 0;
B2 = 0;
S2 = 0;
B3 = 0;
S3 = 0;
B4 = 0;
#100;
#10 rst = 1;
#10 rst = 0;
#10 piso2 = 1;
#10 piso2 = 0;
end
always
begin
#1 clk <= ~clk;
end
endmodule | 0 |
138,524 | data/full_repos/permissive/84416386/lib/bambu_io_hw/bambu_putchar.v | 84,416,386 | bambu_putchar.v | v | 98 | 168 | [] | ['general public license', 'free software foundation'] | [] | [(13, 97)] | null | null | 1: b"%Error: data/full_repos/permissive/84416386/lib/bambu_io_hw/bambu_putchar.v:22: Cannot find file containing module: 'sync_fifo'\n sync_fifo #(.width(8))\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/84416386/lib/bambu_io_hw,data/full_repos/permissive/84416386/sync_fifo\n data/full_repos/permissive/84416386/lib/bambu_io_hw,data/full_repos/permissive/84416386/sync_fifo.v\n data/full_repos/permissive/84416386/lib/bambu_io_hw,data/full_repos/permissive/84416386/sync_fifo.sv\n sync_fifo\n sync_fifo.v\n sync_fifo.sv\n obj_dir/sync_fifo\n obj_dir/sync_fifo.v\n obj_dir/sync_fifo.sv\n%Error: Exiting due to 1 error(s)\n" | 302,516 | module | module bambu_putchar (input clock, input reset, input start_port, output reg done_port, input [7:0] c, output reg [7:0] TX_DATA, output reg TX_ENABLE, input TX_READY);
reg fifo_read;
wire [7:0] fifo_out;
wire fifo_empty;
reg [7:0] fifo_in;
reg fifo_write;
wire fifo_full;
sync_fifo #(.width(8))
the_fifo (.clk(clock), .reset(reset), .wr_enable(fifo_write), .rd_enable(fifo_read),
.empty(fifo_empty), .full(fifo_full), .rd_data(fifo_out), .wr_data(fifo_in),
.count());
reg [1:0] fifo_state;
reg [2:0] tx_state;
reg TX_READY_reg;
wire TX_READY_posedge;
localparam FIFO_STATE_IDLE = 2'b01,
FIFO_STATE_WRITE = 2'b10;
localparam TX_STATE_IDLE = 3'b001,
TX_STATE_TX_BYTE = 3'b010,
TX_STATE_WAIT_TX_READY = 3'b100;
always @(posedge clock or posedge reset)
begin
if (reset) begin
fifo_write <= 1'b0;
done_port <= 1'b0;
fifo_state <= FIFO_STATE_IDLE;
end else begin
done_port <= 1'b0;
fifo_write <= 1'b0;
if (fifo_state == FIFO_STATE_IDLE) begin
if (start_port) begin
fifo_in <= c;
fifo_state <= FIFO_STATE_WRITE;
end
end else begin
if (fifo_full == 1'b0) begin
fifo_write <= 1'b1;
fifo_state <= FIFO_STATE_IDLE;
done_port <= 1'b1;
end
end
end
end
assign TX_READY_posedge = TX_READY & ~TX_READY_reg;
always @(posedge clock or posedge reset)
begin
if (reset) begin
tx_state <= TX_STATE_IDLE;
TX_DATA <= 8'b0;
TX_ENABLE <= 1'b0;
fifo_read <= 1'b0;
TX_READY_reg <= 1'b0;
end else begin
fifo_read <= 1'b0;
TX_ENABLE <= 1'b0;
TX_READY_reg <= TX_READY;
case(tx_state)
TX_STATE_IDLE : begin
if (fifo_empty == 1'b0 && TX_READY == 1'b1) begin
fifo_read <= 1'b1;
tx_state <= TX_STATE_TX_BYTE;
end
end
TX_STATE_TX_BYTE : begin
TX_DATA <= fifo_out;
TX_ENABLE <= 1'b1;
tx_state <= TX_STATE_WAIT_TX_READY;
end
TX_STATE_WAIT_TX_READY : begin
if (TX_READY_posedge == 1'b1)
tx_state <= TX_STATE_IDLE;
end
endcase
end
end
endmodule | module bambu_putchar (input clock, input reset, input start_port, output reg done_port, input [7:0] c, output reg [7:0] TX_DATA, output reg TX_ENABLE, input TX_READY); |
reg fifo_read;
wire [7:0] fifo_out;
wire fifo_empty;
reg [7:0] fifo_in;
reg fifo_write;
wire fifo_full;
sync_fifo #(.width(8))
the_fifo (.clk(clock), .reset(reset), .wr_enable(fifo_write), .rd_enable(fifo_read),
.empty(fifo_empty), .full(fifo_full), .rd_data(fifo_out), .wr_data(fifo_in),
.count());
reg [1:0] fifo_state;
reg [2:0] tx_state;
reg TX_READY_reg;
wire TX_READY_posedge;
localparam FIFO_STATE_IDLE = 2'b01,
FIFO_STATE_WRITE = 2'b10;
localparam TX_STATE_IDLE = 3'b001,
TX_STATE_TX_BYTE = 3'b010,
TX_STATE_WAIT_TX_READY = 3'b100;
always @(posedge clock or posedge reset)
begin
if (reset) begin
fifo_write <= 1'b0;
done_port <= 1'b0;
fifo_state <= FIFO_STATE_IDLE;
end else begin
done_port <= 1'b0;
fifo_write <= 1'b0;
if (fifo_state == FIFO_STATE_IDLE) begin
if (start_port) begin
fifo_in <= c;
fifo_state <= FIFO_STATE_WRITE;
end
end else begin
if (fifo_full == 1'b0) begin
fifo_write <= 1'b1;
fifo_state <= FIFO_STATE_IDLE;
done_port <= 1'b1;
end
end
end
end
assign TX_READY_posedge = TX_READY & ~TX_READY_reg;
always @(posedge clock or posedge reset)
begin
if (reset) begin
tx_state <= TX_STATE_IDLE;
TX_DATA <= 8'b0;
TX_ENABLE <= 1'b0;
fifo_read <= 1'b0;
TX_READY_reg <= 1'b0;
end else begin
fifo_read <= 1'b0;
TX_ENABLE <= 1'b0;
TX_READY_reg <= TX_READY;
case(tx_state)
TX_STATE_IDLE : begin
if (fifo_empty == 1'b0 && TX_READY == 1'b1) begin
fifo_read <= 1'b1;
tx_state <= TX_STATE_TX_BYTE;
end
end
TX_STATE_TX_BYTE : begin
TX_DATA <= fifo_out;
TX_ENABLE <= 1'b1;
tx_state <= TX_STATE_WAIT_TX_READY;
end
TX_STATE_WAIT_TX_READY : begin
if (TX_READY_posedge == 1'b1)
tx_state <= TX_STATE_IDLE;
end
endcase
end
end
endmodule | 5 |
138,525 | data/full_repos/permissive/84416386/lib/toplevel/sync_fifo.v | 84,416,386 | sync_fifo.v | v | 162 | 87 | [] | ['redistribution and use in source and binary forms, with or without modification, are permitted'] | ['all rights reserved'] | [(35, 161)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/84416386/lib/toplevel/sync_fifo.v:69: Operator EQ expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'value\' generates 5 bits.\n : ... In instance sync_fifo\n if (value == depth-1)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 302,519 | module | module sync_fifo
#(
parameter depth = 32,
parameter width = 32,
parameter log2_depth = log2(depth),
parameter log2_depthp1 = log2(depth+1)
)
(
input clk,
input reset,
input wr_enable,
input rd_enable,
output reg empty,
output reg full,
output [width-1:0] rd_data,
input [width-1:0] wr_data,
output reg [log2_depthp1-1:0] count
);
function integer log2;
input [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
function [log2_depth-1:0] increment;
input [log2_depth-1:0] value;
begin
if (value == depth-1)
increment = 0;
else
increment = value+1;
end
endfunction
wire writing = wr_enable && (rd_enable || !full);
wire reading = rd_enable && !empty;
reg [log2_depth-1:0] rd_ptr;
reg [log2_depth-1:0] next_rd_ptr;
always @(*)
if (reset)
next_rd_ptr = 0;
else if (reading)
next_rd_ptr = increment(rd_ptr);
else
next_rd_ptr = rd_ptr;
always @(posedge clk)
rd_ptr <= next_rd_ptr;
reg [log2_depth-1:0] wr_ptr;
reg [log2_depth-1:0] next_wr_ptr;
always @(*)
if (reset)
next_wr_ptr = 0;
else if (writing)
next_wr_ptr = increment(wr_ptr);
else
next_wr_ptr = wr_ptr;
always @(posedge clk)
wr_ptr <= next_wr_ptr;
always @(posedge clk)
if (reset)
count <= 0;
else if (writing && !reading)
count <= count+1;
else if (reading && !writing)
count <= count-1;
always @(posedge clk)
if (reset)
empty <= 1;
else if (reading && next_wr_ptr == next_rd_ptr && !full)
empty <= 1;
else
if (writing && !reading)
empty <= 0;
always @(posedge clk)
if (reset)
full <= 0;
else if (writing && next_wr_ptr == next_rd_ptr)
full <= 1;
else if (reading && !writing)
full <= 0;
reg [width-1:0] mem [depth-1:0];
always @(posedge clk)
begin
if (writing)
mem[wr_ptr] <= wr_data;
rd_ptr <= next_rd_ptr;
end
assign rd_data = mem[rd_ptr];
endmodule | module sync_fifo
#(
parameter depth = 32,
parameter width = 32,
parameter log2_depth = log2(depth),
parameter log2_depthp1 = log2(depth+1)
)
(
input clk,
input reset,
input wr_enable,
input rd_enable,
output reg empty,
output reg full,
output [width-1:0] rd_data,
input [width-1:0] wr_data,
output reg [log2_depthp1-1:0] count
); |
function integer log2;
input [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
function [log2_depth-1:0] increment;
input [log2_depth-1:0] value;
begin
if (value == depth-1)
increment = 0;
else
increment = value+1;
end
endfunction
wire writing = wr_enable && (rd_enable || !full);
wire reading = rd_enable && !empty;
reg [log2_depth-1:0] rd_ptr;
reg [log2_depth-1:0] next_rd_ptr;
always @(*)
if (reset)
next_rd_ptr = 0;
else if (reading)
next_rd_ptr = increment(rd_ptr);
else
next_rd_ptr = rd_ptr;
always @(posedge clk)
rd_ptr <= next_rd_ptr;
reg [log2_depth-1:0] wr_ptr;
reg [log2_depth-1:0] next_wr_ptr;
always @(*)
if (reset)
next_wr_ptr = 0;
else if (writing)
next_wr_ptr = increment(wr_ptr);
else
next_wr_ptr = wr_ptr;
always @(posedge clk)
wr_ptr <= next_wr_ptr;
always @(posedge clk)
if (reset)
count <= 0;
else if (writing && !reading)
count <= count+1;
else if (reading && !writing)
count <= count-1;
always @(posedge clk)
if (reset)
empty <= 1;
else if (reading && next_wr_ptr == next_rd_ptr && !full)
empty <= 1;
else
if (writing && !reading)
empty <= 0;
always @(posedge clk)
if (reset)
full <= 0;
else if (writing && next_wr_ptr == next_rd_ptr)
full <= 1;
else if (reading && !writing)
full <= 0;
reg [width-1:0] mem [depth-1:0];
always @(posedge clk)
begin
if (writing)
mem[wr_ptr] <= wr_data;
rd_ptr <= next_rd_ptr;
end
assign rd_data = mem[rd_ptr];
endmodule | 5 |
138,526 | data/full_repos/permissive/84416386/lib/toplevel/sync_fifo.v | 84,416,386 | sync_fifo.v | v | 162 | 87 | [] | ['redistribution and use in source and binary forms, with or without modification, are permitted'] | ['all rights reserved'] | [(35, 161)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/84416386/lib/toplevel/sync_fifo.v:69: Operator EQ expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'value\' generates 5 bits.\n : ... In instance sync_fifo\n if (value == depth-1)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 302,519 | function | function integer log2;
input [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction | function integer log2; |
input [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction | 5 |
138,527 | data/full_repos/permissive/84416386/lib/toplevel/sync_fifo.v | 84,416,386 | sync_fifo.v | v | 162 | 87 | [] | ['redistribution and use in source and binary forms, with or without modification, are permitted'] | ['all rights reserved'] | [(35, 161)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/84416386/lib/toplevel/sync_fifo.v:69: Operator EQ expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'value\' generates 5 bits.\n : ... In instance sync_fifo\n if (value == depth-1)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 302,519 | function | function [log2_depth-1:0] increment;
input [log2_depth-1:0] value;
begin
if (value == depth-1)
increment = 0;
else
increment = value+1;
end
endfunction | function [log2_depth-1:0] increment; |
input [log2_depth-1:0] value;
begin
if (value == depth-1)
increment = 0;
else
increment = value+1;
end
endfunction | 5 |
138,529 | data/full_repos/permissive/84416386/tb/pll.v | 84,416,386 | pll.v | v | 18 | 33 | [] | [] | [] | [(1, 17)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/84416386/tb/pll.v:11: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,525 | module | module pll(
input clock_in,
output clock_out,
output reg locked
);
assign clock_out = clock_in;
initial begin
locked <= 1'b0;
#5;
locked <= 1'b1;
end
endmodule | module pll(
input clock_in,
output clock_out,
output reg locked
); |
assign clock_out = clock_in;
initial begin
locked <= 1'b0;
#5;
locked <= 1'b1;
end
endmodule | 5 |
138,530 | data/full_repos/permissive/84500285/I2c slave/simple_slave.v | 84,500,285 | simple_slave.v | v | 84 | 172 | [] | [] | [] | null | line:57: before: "CrcError" | null | 1: b'%Error: Cannot find file containing module: slave,data/full_repos/permissive/84500285\n ... Looked in:\n data/full_repos/permissive/84500285/I2c/slave,data/full_repos/permissive/84500285\n data/full_repos/permissive/84500285/I2c/slave,data/full_repos/permissive/84500285.v\n data/full_repos/permissive/84500285/I2c/slave,data/full_repos/permissive/84500285.sv\n slave,data/full_repos/permissive/84500285\n slave,data/full_repos/permissive/84500285.v\n slave,data/full_repos/permissive/84500285.sv\n obj_dir/slave,data/full_repos/permissive/84500285\n obj_dir/slave,data/full_repos/permissive/84500285.v\n obj_dir/slave,data/full_repos/permissive/84500285.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/84500285/I2c\n%Error: Cannot find file containing module: slave/simple_slave.v\n%Error: Exiting due to 3 error(s)\n' | 302,526 | module | module simple_slave (
input SCK,
output SDA,
output reg [7:0] PWM_INTERFACE
);
parameter [7:0] moduleAddress=8'b10101011;
parameter [4:0] initialState=0, getAddr=1, isItMe=8, ackSent=9,
dataRecv=17, postSend=18, notMe=19;
reg [4:0] eventCounter =0;
reg sda_ack =0;
assign SDA = (sda_ack)? 0:1'bz;
wire busIsBusy;
reg [7:0] addrDataBuff;
reg started =0, stopped =0;
assign busIsBusy= started ^ stopped;
reg startId;
always @ (negedge SDA) begin
if(SCK==1 & !busIsBusy)
started<=~started;
end
always @ (posedge SDA) begin
if(SCK==1 & busIsBusy) begin
stopped<=~stopped;
end
end
always @ (negedge SCK) begin
if(busIsBusy) begin
case(eventCounter)
initialState:
eventCounter<=getAddr;
isItMe:
if(addrDataBuff==moduleAddress) begin
sda_ack<=1;
eventCounter<=ackSent;
end
else begin
eventCounter<=notMe;
startId<=started;
end
dataRecv: begin
sda_ack<=1;
PWM_INTERFACE<=addrDataBuff;
eventCounter<=postSend;
end
notMe:
if(startId!=started)
eventCounter<=getAddr;
default: begin
sda_ack<=0;
if(eventCounter==postSend)
eventCounter<=initialState;
else if(eventCounter!=notMe)
eventCounter<=eventCounter+1;
end
endcase
end
end
always @ (posedge SCK) begin
if(busIsBusy) begin
if((eventCounter>initialState &eventCounter<ackSent) | (eventCounter>ackSent &eventCounter<postSend))
addrDataBuff<={addrDataBuff[6:0],SDA};
end
end
endmodule | module simple_slave (
input SCK,
output SDA,
output reg [7:0] PWM_INTERFACE
); |
parameter [7:0] moduleAddress=8'b10101011;
parameter [4:0] initialState=0, getAddr=1, isItMe=8, ackSent=9,
dataRecv=17, postSend=18, notMe=19;
reg [4:0] eventCounter =0;
reg sda_ack =0;
assign SDA = (sda_ack)? 0:1'bz;
wire busIsBusy;
reg [7:0] addrDataBuff;
reg started =0, stopped =0;
assign busIsBusy= started ^ stopped;
reg startId;
always @ (negedge SDA) begin
if(SCK==1 & !busIsBusy)
started<=~started;
end
always @ (posedge SDA) begin
if(SCK==1 & busIsBusy) begin
stopped<=~stopped;
end
end
always @ (negedge SCK) begin
if(busIsBusy) begin
case(eventCounter)
initialState:
eventCounter<=getAddr;
isItMe:
if(addrDataBuff==moduleAddress) begin
sda_ack<=1;
eventCounter<=ackSent;
end
else begin
eventCounter<=notMe;
startId<=started;
end
dataRecv: begin
sda_ack<=1;
PWM_INTERFACE<=addrDataBuff;
eventCounter<=postSend;
end
notMe:
if(startId!=started)
eventCounter<=getAddr;
default: begin
sda_ack<=0;
if(eventCounter==postSend)
eventCounter<=initialState;
else if(eventCounter!=notMe)
eventCounter<=eventCounter+1;
end
endcase
end
end
always @ (posedge SCK) begin
if(busIsBusy) begin
if((eventCounter>initialState &eventCounter<ackSent) | (eventCounter>ackSent &eventCounter<postSend))
addrDataBuff<={addrDataBuff[6:0],SDA};
end
end
endmodule | 0 |
138,531 | data/full_repos/permissive/84500285/Top module/rtl/i2c_pwm_interface.v | 84,500,285 | i2c_pwm_interface.v | v | 34 | 146 | [] | [] | [] | [(11, 33)] | null | null | 1: b'%Error: Cannot find file containing module: module/rtl,data/full_repos/permissive/84500285\n ... Looked in:\n data/full_repos/permissive/84500285/Top/module/rtl,data/full_repos/permissive/84500285\n data/full_repos/permissive/84500285/Top/module/rtl,data/full_repos/permissive/84500285.v\n data/full_repos/permissive/84500285/Top/module/rtl,data/full_repos/permissive/84500285.sv\n module/rtl,data/full_repos/permissive/84500285\n module/rtl,data/full_repos/permissive/84500285.v\n module/rtl,data/full_repos/permissive/84500285.sv\n obj_dir/module/rtl,data/full_repos/permissive/84500285\n obj_dir/module/rtl,data/full_repos/permissive/84500285.v\n obj_dir/module/rtl,data/full_repos/permissive/84500285.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/84500285/Top\n%Error: Cannot find file containing module: module/rtl/i2c_pwm_interface.v\n%Error: Exiting due to 3 error(s)\n' | 302,528 | module | module I2C_PWM_INTERFACE (
input SCK,
input CLK_IN,
output SDA,
output PWM_OUT
);
parameter moduleAddress=8'b10101011,N = 31, K=1;
wire [7:0] PWM_INTERFACE;
simple_slave #(moduleAddress) i2c_slave(
.SDA(SDA),
.SCK(SCK),
.PWM_INTERFACE(PWM_INTERFACE));
PWM_INTERFACE #(N,K) pwm(
.CLK_IN(CLK_IN),
.PWM_DCycle(PWM_INTERFACE),
.PWM_OUT(PWM_OUT)
);
endmodule | module I2C_PWM_INTERFACE (
input SCK,
input CLK_IN,
output SDA,
output PWM_OUT
); |
parameter moduleAddress=8'b10101011,N = 31, K=1;
wire [7:0] PWM_INTERFACE;
simple_slave #(moduleAddress) i2c_slave(
.SDA(SDA),
.SCK(SCK),
.PWM_INTERFACE(PWM_INTERFACE));
PWM_INTERFACE #(N,K) pwm(
.CLK_IN(CLK_IN),
.PWM_DCycle(PWM_INTERFACE),
.PWM_OUT(PWM_OUT)
);
endmodule | 0 |
138,532 | data/full_repos/permissive/84500285/Top module/rtl/pwm.v | 84,500,285 | pwm.v | v | 35 | 111 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: Cannot find file containing module: module/rtl,data/full_repos/permissive/84500285\n ... Looked in:\n data/full_repos/permissive/84500285/Top/module/rtl,data/full_repos/permissive/84500285\n data/full_repos/permissive/84500285/Top/module/rtl,data/full_repos/permissive/84500285.v\n data/full_repos/permissive/84500285/Top/module/rtl,data/full_repos/permissive/84500285.sv\n module/rtl,data/full_repos/permissive/84500285\n module/rtl,data/full_repos/permissive/84500285.v\n module/rtl,data/full_repos/permissive/84500285.sv\n obj_dir/module/rtl,data/full_repos/permissive/84500285\n obj_dir/module/rtl,data/full_repos/permissive/84500285.v\n obj_dir/module/rtl,data/full_repos/permissive/84500285.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/84500285/Top\n%Error: Cannot find file containing module: module/rtl/pwm.v\n%Error: Exiting due to 3 error(s)\n' | 302,529 | module | module PWM_INTERFACE (
input CLK_IN,
input [7:0] PWM_DCycle,
output reg PWM_OUT
);
parameter [4:0] N = 31, K=1;
reg [31:0] clk_div =0;
reg [7:0] pwm_clk =0;
always @ ( posedge CLK_IN ) begin
clk_div<=clk_div+K;
end
always @ (posedge clk_div[N]) begin
pwm_clk<=pwm_clk+1;
end
always @ ( * ) begin
if(pwm_clk<=PWM_DCycle & PWM_DCycle!=0)
PWM_OUT<=1;
else
PWM_OUT<=0;
end
endmodule | module PWM_INTERFACE (
input CLK_IN,
input [7:0] PWM_DCycle,
output reg PWM_OUT
); |
parameter [4:0] N = 31, K=1;
reg [31:0] clk_div =0;
reg [7:0] pwm_clk =0;
always @ ( posedge CLK_IN ) begin
clk_div<=clk_div+K;
end
always @ (posedge clk_div[N]) begin
pwm_clk<=pwm_clk+1;
end
always @ ( * ) begin
if(pwm_clk<=PWM_DCycle & PWM_DCycle!=0)
PWM_OUT<=1;
else
PWM_OUT<=0;
end
endmodule | 0 |
138,533 | data/full_repos/permissive/84500285/Top module/testbench/testbench.v | 84,500,285 | testbench.v | v | 95 | 108 | [] | [] | [] | null | line:9: before: "=" | null | 1: b'%Error: Cannot find file containing module: module/testbench,data/full_repos/permissive/84500285\n ... Looked in:\n data/full_repos/permissive/84500285/Top/module/testbench,data/full_repos/permissive/84500285\n data/full_repos/permissive/84500285/Top/module/testbench,data/full_repos/permissive/84500285.v\n data/full_repos/permissive/84500285/Top/module/testbench,data/full_repos/permissive/84500285.sv\n module/testbench,data/full_repos/permissive/84500285\n module/testbench,data/full_repos/permissive/84500285.v\n module/testbench,data/full_repos/permissive/84500285.sv\n obj_dir/module/testbench,data/full_repos/permissive/84500285\n obj_dir/module/testbench,data/full_repos/permissive/84500285.v\n obj_dir/module/testbench,data/full_repos/permissive/84500285.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/84500285/Top\n%Error: Cannot find file containing module: module/testbench/testbench.v\n%Error: Exiting due to 3 error(s)\n' | 302,530 | module | module virtual_master(
output reg SDA,
output reg SCL,
output reg dbg=0
);
reg [7:0] dataSent = 8'bz0zzz0zz, addressSent=8'bzzz0000z;
integer i=0;
task sendData;
input [7:0] addressSent,dataSent;
begin
#5;
SDA=1;SCL=1;
#1;
SDA=0;
#1;
SCL=0;
for(i=7;i>=0;i--) begin
SCL=0;SDA=addressSent[i];#1;SCL=1;#1;
end
SDA=1'bz;
SCL=0;
#1;
SCL=1;#1;
for(i=7;i>=0;i--) begin
SCL=0;SDA=dataSent[i];#1;SCL=1;#1;
end
SCL=0;#1;SCL=1;#1;SCL=0;#1;
SDA=0;#1;SCL=1;#2;SDA=1'bz;
#10;
end
endtask
endmodule | module virtual_master(
output reg SDA,
output reg SCL,
output reg dbg=0
); |
reg [7:0] dataSent = 8'bz0zzz0zz, addressSent=8'bzzz0000z;
integer i=0;
task sendData;
input [7:0] addressSent,dataSent;
begin
#5;
SDA=1;SCL=1;
#1;
SDA=0;
#1;
SCL=0;
for(i=7;i>=0;i--) begin
SCL=0;SDA=addressSent[i];#1;SCL=1;#1;
end
SDA=1'bz;
SCL=0;
#1;
SCL=1;#1;
for(i=7;i>=0;i--) begin
SCL=0;SDA=dataSent[i];#1;SCL=1;#1;
end
SCL=0;#1;SCL=1;#1;SCL=0;#1;
SDA=0;#1;SCL=1;#2;SDA=1'bz;
#10;
end
endtask
endmodule | 0 |
138,534 | data/full_repos/permissive/84500285/Top module/testbench/testbench.v | 84,500,285 | testbench.v | v | 95 | 108 | [] | [] | [] | null | line:9: before: "=" | null | 1: b'%Error: Cannot find file containing module: module/testbench,data/full_repos/permissive/84500285\n ... Looked in:\n data/full_repos/permissive/84500285/Top/module/testbench,data/full_repos/permissive/84500285\n data/full_repos/permissive/84500285/Top/module/testbench,data/full_repos/permissive/84500285.v\n data/full_repos/permissive/84500285/Top/module/testbench,data/full_repos/permissive/84500285.sv\n module/testbench,data/full_repos/permissive/84500285\n module/testbench,data/full_repos/permissive/84500285.v\n module/testbench,data/full_repos/permissive/84500285.sv\n obj_dir/module/testbench,data/full_repos/permissive/84500285\n obj_dir/module/testbench,data/full_repos/permissive/84500285.v\n obj_dir/module/testbench,data/full_repos/permissive/84500285.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/84500285/Top\n%Error: Cannot find file containing module: module/testbench/testbench.v\n%Error: Exiting due to 3 error(s)\n' | 302,530 | module | module TB ();
pullup(SDA);
pullup(SCK);
reg CLK_IN=0;
wire PWM_OUT_1,PWM_OUT_2,PWM_OUT_3;
parameter [7:0] dev1 = 8'bzzz0000z,dev2 = 8'bzzzz000z, dev3 = 8'bz0z0000z;
I2C_PWM_INTERFACE #(8'hE1,6,1) uut_1(
.SDA(SDA),
.SCK(SCK),
.CLK_IN(CLK_IN),
.PWM_OUT(PWM_OUT_1)
);
I2C_PWM_INTERFACE #(8'hF1,6,1) uut_2(
.SDA(SDA),
.SCK(SCK),
.CLK_IN(CLK_IN),
.PWM_OUT(PWM_OUT_2)
);
I2C_PWM_INTERFACE #(8'hA1,6,1) uut_3(
.SDA(SDA),
.SCK(SCK),
.CLK_IN(CLK_IN),
.PWM_OUT(PWM_OUT_3)
);
virtual_master master(.SDA(SDA),.SCL(SCK));
initial begin
$dumpfile("testing.dump");
$dumpvars;
master.sendData(dev1,8'b0zzzzzzz);
master.sendData(dev2,8'b00zz00z0);
master.sendData(dev3,8'bzz00z000);
end
always begin
CLK_IN=~CLK_IN;
#1;
if($time==500us)$finish();
end
endmodule | module TB (); |
pullup(SDA);
pullup(SCK);
reg CLK_IN=0;
wire PWM_OUT_1,PWM_OUT_2,PWM_OUT_3;
parameter [7:0] dev1 = 8'bzzz0000z,dev2 = 8'bzzzz000z, dev3 = 8'bz0z0000z;
I2C_PWM_INTERFACE #(8'hE1,6,1) uut_1(
.SDA(SDA),
.SCK(SCK),
.CLK_IN(CLK_IN),
.PWM_OUT(PWM_OUT_1)
);
I2C_PWM_INTERFACE #(8'hF1,6,1) uut_2(
.SDA(SDA),
.SCK(SCK),
.CLK_IN(CLK_IN),
.PWM_OUT(PWM_OUT_2)
);
I2C_PWM_INTERFACE #(8'hA1,6,1) uut_3(
.SDA(SDA),
.SCK(SCK),
.CLK_IN(CLK_IN),
.PWM_OUT(PWM_OUT_3)
);
virtual_master master(.SDA(SDA),.SCL(SCK));
initial begin
$dumpfile("testing.dump");
$dumpvars;
master.sendData(dev1,8'b0zzzzzzz);
master.sendData(dev2,8'b00zz00z0);
master.sendData(dev3,8'bzz00z000);
end
always begin
CLK_IN=~CLK_IN;
#1;
if($time==500us)$finish();
end
endmodule | 0 |
138,535 | data/full_repos/permissive/84554637/src/gm_tables.v | 84,554,637 | gm_tables.v | v | 35 | 73 | [] | [] | [] | null | line:3: before: "(" | data/verilator_xmls/8440bbb0-c07e-4c9b-b58e-2377f2898863.xml | null | 302,531 | module | module gm_tables();
function [7 : 0] gm2(input [7 : 0] op);
begin
gm2 = {op[6 : 0], 1'b0} ^ (8'h1b & {8{op[7]}});
end
endfunction
function [7 : 0] gm3(input [7 : 0] op);
begin
gm3 = gm2(op) ^ op;
end
endfunction
initial
begin : generator
reg [8 : 0] ctr;
$display("Generating gm2 and gm3 tables");
$display("-----------------------------");
$display("GM2:");
for (ctr = 0 ; ctr < 256 ; ctr = ctr + 1)
begin
$display("gm2(0x%02x) = 0x%02x", ctr[7 : 0], gm2(ctr[7 : 0]));
end
$display("");
$display("GM3:");
for (ctr = 0 ; ctr < 256 ; ctr = ctr + 1)
begin
$display("gm3(0x%02x) = 0x%02x", ctr[7 : 0], gm3(ctr[7 : 0]));
end
end
endmodule | module gm_tables(); |
function [7 : 0] gm2(input [7 : 0] op);
begin
gm2 = {op[6 : 0], 1'b0} ^ (8'h1b & {8{op[7]}});
end
endfunction
function [7 : 0] gm3(input [7 : 0] op);
begin
gm3 = gm2(op) ^ op;
end
endfunction
initial
begin : generator
reg [8 : 0] ctr;
$display("Generating gm2 and gm3 tables");
$display("-----------------------------");
$display("GM2:");
for (ctr = 0 ; ctr < 256 ; ctr = ctr + 1)
begin
$display("gm2(0x%02x) = 0x%02x", ctr[7 : 0], gm2(ctr[7 : 0]));
end
$display("");
$display("GM3:");
for (ctr = 0 ; ctr < 256 ; ctr = ctr + 1)
begin
$display("gm3(0x%02x) = 0x%02x", ctr[7 : 0], gm3(ctr[7 : 0]));
end
end
endmodule | 5 |
138,536 | data/full_repos/permissive/84554637/src/gm_tables.v | 84,554,637 | gm_tables.v | v | 35 | 73 | [] | [] | [] | null | line:3: before: "(" | data/verilator_xmls/8440bbb0-c07e-4c9b-b58e-2377f2898863.xml | null | 302,531 | function | function [7 : 0] gm2(input [7 : 0] op);
begin
gm2 = {op[6 : 0], 1'b0} ^ (8'h1b & {8{op[7]}});
end
endfunction | function [7 : 0] gm2(input [7 : 0] op); |
begin
gm2 = {op[6 : 0], 1'b0} ^ (8'h1b & {8{op[7]}});
end
endfunction | 5 |
138,537 | data/full_repos/permissive/84554637/src/gm_tables.v | 84,554,637 | gm_tables.v | v | 35 | 73 | [] | [] | [] | null | line:3: before: "(" | data/verilator_xmls/8440bbb0-c07e-4c9b-b58e-2377f2898863.xml | null | 302,531 | function | function [7 : 0] gm3(input [7 : 0] op);
begin
gm3 = gm2(op) ^ op;
end
endfunction | function [7 : 0] gm3(input [7 : 0] op); |
begin
gm3 = gm2(op) ^ op;
end
endfunction | 5 |
138,543 | data/full_repos/permissive/84653396/src/mfp_eic_handler.v | 84,653,396 | mfp_eic_handler.v | v | 73 | 107 | [] | [] | [] | [(56, 97), (102, 119)] | null | null | 1: b'%Error: data/full_repos/permissive/84653396/src/mfp_eic_handler.v:6: Cannot find include file: mfp_eic_core.vh\n`include "mfp_eic_core.vh" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/84653396/src,data/full_repos/permissive/84653396/mfp_eic_core.vh\n data/full_repos/permissive/84653396/src,data/full_repos/permissive/84653396/mfp_eic_core.vh.v\n data/full_repos/permissive/84653396/src,data/full_repos/permissive/84653396/mfp_eic_core.vh.sv\n mfp_eic_core.vh\n mfp_eic_core.vh.v\n mfp_eic_core.vh.sv\n obj_dir/mfp_eic_core.vh\n obj_dir/mfp_eic_core.vh.v\n obj_dir/mfp_eic_core.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 302,535 | module | module handler_params_encoder
(
input [ 7 : 0 ] irqNumber,
input irqDetected,
output [ 17 : 1 ] EIC_Offset,
output [ 3 : 0 ] EIC_ShadowSet,
output [ 7 : 0 ] EIC_Interrupt,
output [ 5 : 0 ] EIC_Vector
);
assign EIC_ShadowSet = 4'b0;
assign EIC_Interrupt = irqDetected ? irqNumber + 1 : 8'b0;
`ifdef EIC_USE_EXPLICIT_VECTOR_OFFSET
parameter HANDLER_BASE = 17'h100;
parameter HANDLER_SHIFT = 4;
assign EIC_Offset = HANDLER_BASE + (irqNumber << HANDLER_SHIFT);
assign EIC_Vector = 6'b0;
`else
assign EIC_Offset = 17'h0;
assign EIC_Vector = irqNumber[5:0];
`endif
endmodule | module handler_params_encoder
(
input [ 7 : 0 ] irqNumber,
input irqDetected,
output [ 17 : 1 ] EIC_Offset,
output [ 3 : 0 ] EIC_ShadowSet,
output [ 7 : 0 ] EIC_Interrupt,
output [ 5 : 0 ] EIC_Vector
); |
assign EIC_ShadowSet = 4'b0;
assign EIC_Interrupt = irqDetected ? irqNumber + 1 : 8'b0;
`ifdef EIC_USE_EXPLICIT_VECTOR_OFFSET
parameter HANDLER_BASE = 17'h100;
parameter HANDLER_SHIFT = 4;
assign EIC_Offset = HANDLER_BASE + (irqNumber << HANDLER_SHIFT);
assign EIC_Vector = 6'b0;
`else
assign EIC_Offset = 17'h0;
assign EIC_Vector = irqNumber[5:0];
`endif
endmodule | 1 |
138,544 | data/full_repos/permissive/84653396/src/mfp_eic_handler.v | 84,653,396 | mfp_eic_handler.v | v | 73 | 107 | [] | [] | [] | [(56, 97), (102, 119)] | null | null | 1: b'%Error: data/full_repos/permissive/84653396/src/mfp_eic_handler.v:6: Cannot find include file: mfp_eic_core.vh\n`include "mfp_eic_core.vh" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/84653396/src,data/full_repos/permissive/84653396/mfp_eic_core.vh\n data/full_repos/permissive/84653396/src,data/full_repos/permissive/84653396/mfp_eic_core.vh.v\n data/full_repos/permissive/84653396/src,data/full_repos/permissive/84653396/mfp_eic_core.vh.sv\n mfp_eic_core.vh\n mfp_eic_core.vh.v\n mfp_eic_core.vh.sv\n obj_dir/mfp_eic_core.vh\n obj_dir/mfp_eic_core.vh.v\n obj_dir/mfp_eic_core.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 302,535 | module | module handler_params_decoder
(
input [ 5 : 0 ] irqVector,
input [ 17 : 1 ] irqOffset,
output [ 7 : 0 ] irqNumber
);
`ifdef EIC_USE_EXPLICIT_VECTOR_OFFSET
parameter HANDLER_BASE = 17'h100;
parameter HANDLER_SHIFT = 4;
assign irqNumber = ((irqOffset - HANDLER_BASE) >> HANDLER_SHIFT);
`else
assign irqNumber = {2'b0, irqVector };
`endif
endmodule | module handler_params_decoder
(
input [ 5 : 0 ] irqVector,
input [ 17 : 1 ] irqOffset,
output [ 7 : 0 ] irqNumber
); |
`ifdef EIC_USE_EXPLICIT_VECTOR_OFFSET
parameter HANDLER_BASE = 17'h100;
parameter HANDLER_SHIFT = 4;
assign irqNumber = ((irqOffset - HANDLER_BASE) >> HANDLER_SHIFT);
`else
assign irqNumber = {2'b0, irqVector };
`endif
endmodule | 1 |
138,545 | data/full_repos/permissive/84653396/src/mfp_eic_priority_encoder.v | 84,653,396 | mfp_eic_priority_encoder.v | v | 77 | 69 | [] | [] | [] | [(7, 31), (33, 57), (59, 77)] | null | data/verilator_xmls/65ee4024-23a5-4ee1-9222-21a2d2513e99.xml | null | 302,536 | module | module priority_encoder255
(
input [ 255 : 0 ] in,
output reg detect,
output reg [ 7 : 0 ] out
);
wire [3:0] detectL;
wire [5:0] preoutL [3:0];
wire [1:0] preoutM;
priority_encoder64 e10( in[ 63:0 ], detectL[0], preoutL[0] );
priority_encoder64 e11( in[ 127:64 ], detectL[1], preoutL[1] );
priority_encoder64 e12( in[ 191:128 ], detectL[2], preoutL[2] );
priority_encoder64 e13( in[ 255:192 ], detectL[3], preoutL[3] );
always @ (*)
casez(detectL)
default : {detect, out} = 9'b0;
4'b0001 : {detect, out} = { 3'b100, preoutL[0] };
4'b001? : {detect, out} = { 3'b101, preoutL[1] };
4'b01?? : {detect, out} = { 3'b110, preoutL[2] };
4'b1??? : {detect, out} = { 3'b111, preoutL[3] };
endcase
endmodule | module priority_encoder255
(
input [ 255 : 0 ] in,
output reg detect,
output reg [ 7 : 0 ] out
); |
wire [3:0] detectL;
wire [5:0] preoutL [3:0];
wire [1:0] preoutM;
priority_encoder64 e10( in[ 63:0 ], detectL[0], preoutL[0] );
priority_encoder64 e11( in[ 127:64 ], detectL[1], preoutL[1] );
priority_encoder64 e12( in[ 191:128 ], detectL[2], preoutL[2] );
priority_encoder64 e13( in[ 255:192 ], detectL[3], preoutL[3] );
always @ (*)
casez(detectL)
default : {detect, out} = 9'b0;
4'b0001 : {detect, out} = { 3'b100, preoutL[0] };
4'b001? : {detect, out} = { 3'b101, preoutL[1] };
4'b01?? : {detect, out} = { 3'b110, preoutL[2] };
4'b1??? : {detect, out} = { 3'b111, preoutL[3] };
endcase
endmodule | 1 |
138,546 | data/full_repos/permissive/84653396/src/mfp_eic_priority_encoder.v | 84,653,396 | mfp_eic_priority_encoder.v | v | 77 | 69 | [] | [] | [] | [(7, 31), (33, 57), (59, 77)] | null | data/verilator_xmls/65ee4024-23a5-4ee1-9222-21a2d2513e99.xml | null | 302,536 | module | module priority_encoder64
(
input [ 63 : 0 ] in,
output detect,
output [ 5 : 0 ] out
);
wire [7:0] detectL;
wire [2:0] preoutL [7:0];
wire [2:0] preoutM;
priority_encoder8 e30( in[ 7:0 ], detectL[0], preoutL[0] );
priority_encoder8 e31( in[ 15:8 ], detectL[1], preoutL[1] );
priority_encoder8 e32( in[ 23:16 ], detectL[2], preoutL[2] );
priority_encoder8 e33( in[ 31:24 ], detectL[3], preoutL[3] );
priority_encoder8 e34( in[ 39:32 ], detectL[4], preoutL[4] );
priority_encoder8 e35( in[ 47:40 ], detectL[5], preoutL[5] );
priority_encoder8 e36( in[ 55:48 ], detectL[6], preoutL[6] );
priority_encoder8 e37( in[ 63:56 ], detectL[7], preoutL[7] );
priority_encoder8 e20(detectL, detect, preoutM);
assign out = detect ? { preoutM, preoutL[preoutM] } : 6'b0;
endmodule | module priority_encoder64
(
input [ 63 : 0 ] in,
output detect,
output [ 5 : 0 ] out
); |
wire [7:0] detectL;
wire [2:0] preoutL [7:0];
wire [2:0] preoutM;
priority_encoder8 e30( in[ 7:0 ], detectL[0], preoutL[0] );
priority_encoder8 e31( in[ 15:8 ], detectL[1], preoutL[1] );
priority_encoder8 e32( in[ 23:16 ], detectL[2], preoutL[2] );
priority_encoder8 e33( in[ 31:24 ], detectL[3], preoutL[3] );
priority_encoder8 e34( in[ 39:32 ], detectL[4], preoutL[4] );
priority_encoder8 e35( in[ 47:40 ], detectL[5], preoutL[5] );
priority_encoder8 e36( in[ 55:48 ], detectL[6], preoutL[6] );
priority_encoder8 e37( in[ 63:56 ], detectL[7], preoutL[7] );
priority_encoder8 e20(detectL, detect, preoutM);
assign out = detect ? { preoutM, preoutL[preoutM] } : 6'b0;
endmodule | 1 |
138,547 | data/full_repos/permissive/84653396/src/mfp_eic_priority_encoder.v | 84,653,396 | mfp_eic_priority_encoder.v | v | 77 | 69 | [] | [] | [] | [(7, 31), (33, 57), (59, 77)] | null | data/verilator_xmls/65ee4024-23a5-4ee1-9222-21a2d2513e99.xml | null | 302,536 | module | module priority_encoder8
(
input [ 7 : 0 ] in,
output reg detect,
output reg [ 2 : 0 ] out
);
always @ (*)
casez(in)
default : {detect, out} = 4'b0000;
8'b00000001 : {detect, out} = 4'b1000;
8'b0000001? : {detect, out} = 4'b1001;
8'b000001?? : {detect, out} = 4'b1010;
8'b00001??? : {detect, out} = 4'b1011;
8'b0001???? : {detect, out} = 4'b1100;
8'b001????? : {detect, out} = 4'b1101;
8'b01?????? : {detect, out} = 4'b1110;
8'b1??????? : {detect, out} = 4'b1111;
endcase
endmodule | module priority_encoder8
(
input [ 7 : 0 ] in,
output reg detect,
output reg [ 2 : 0 ] out
); |
always @ (*)
casez(in)
default : {detect, out} = 4'b0000;
8'b00000001 : {detect, out} = 4'b1000;
8'b0000001? : {detect, out} = 4'b1001;
8'b000001?? : {detect, out} = 4'b1010;
8'b00001??? : {detect, out} = 4'b1011;
8'b0001???? : {detect, out} = 4'b1100;
8'b001????? : {detect, out} = 4'b1101;
8'b01?????? : {detect, out} = 4'b1110;
8'b1??????? : {detect, out} = 4'b1111;
endcase
endmodule | 1 |
138,548 | data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v | 84,653,396 | eicAhbTest.v | v | 145 | 126 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:7: Cannot find include file: mfp_eic_core.vh\n`include "mfp_eic_core.vh" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/84653396/src/testbench,data/full_repos/permissive/84653396/mfp_eic_core.vh\n data/full_repos/permissive/84653396/src/testbench,data/full_repos/permissive/84653396/mfp_eic_core.vh.v\n data/full_repos/permissive/84653396/src/testbench,data/full_repos/permissive/84653396/mfp_eic_core.vh.sv\n mfp_eic_core.vh\n mfp_eic_core.vh.v\n mfp_eic_core.vh.sv\n obj_dir/mfp_eic_core.vh\n obj_dir/mfp_eic_core.vh.v\n obj_dir/mfp_eic_core.vh.sv\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:11: Cannot find include file: ahb_lite.vh\n `include "ahb_lite.vh" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:13: Define or directive not defined: \'`EIC_CHANNELS\'\n : ... Suggested alternative: \'`EIC_SENSE_CHANNELS\'\n reg [ `EIC_CHANNELS -1 : 0 ] signal;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:19: Define or directive not defined: \'`EIC_ADDR_WIDTH\'\n reg [ `EIC_ADDR_WIDTH - 1 : 0 ] read_addr;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:21: Define or directive not defined: \'`EIC_ADDR_WIDTH\'\n reg [ `EIC_ADDR_WIDTH - 1 : 0 ] write_addr;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:27: syntax error, unexpected \'@\'\n @(posedge HCLK);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:93: Unsupported: Ignoring delay on this delayed statement.\n always #(Tclk/2) HCLK = ~HCLK;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:101: syntax error, unexpected \'@\'\n @(posedge HCLK);\n ^\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:105: syntax error, unexpected \'@\'\n @(posedge HCLK);\n ^\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:108: Define or directive not defined: \'`EIC_REG_EICR\'\n ahbPhaseFst(`EIC_REG_EICR << 2, WRITE, HSIZE_X32, St_x); \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:108: syntax error, unexpected <<, expecting \')\'\n ahbPhaseFst(`EIC_REG_EICR << 2, WRITE, HSIZE_X32, St_x); \n ^~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:109: Define or directive not defined: \'`EIC_REG_EISMSK_0\'\n ahbPhase (`EIC_REG_EISMSK_0 << 2, WRITE, HSIZE_X32, 32\'h01); \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:109: syntax error, unexpected <<, expecting \')\'\n ahbPhase (`EIC_REG_EISMSK_0 << 2, WRITE, HSIZE_X32, 32\'h01); \n ^~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:110: Define or directive not defined: \'`EIC_REG_EIMSK_0\'\n ahbPhase (`EIC_REG_EIMSK_0 << 2, WRITE, HSIZE_X32, 32\'h05); \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:110: syntax error, unexpected <<, expecting \')\'\n ahbPhase (`EIC_REG_EIMSK_0 << 2, WRITE, HSIZE_X32, 32\'h05); \n ^~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:111: Define or directive not defined: \'`EIC_REG_EIMSK_1\'\n ahbPhase (`EIC_REG_EIMSK_1 << 2, WRITE, HSIZE_X32, 32\'h03); \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:111: syntax error, unexpected <<, expecting \')\'\n ahbPhase (`EIC_REG_EIMSK_1 << 2, WRITE, HSIZE_X32, 32\'h03); \n ^~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:112: Define or directive not defined: \'`EIC_REG_EICR\'\n ahbPhase (`EIC_REG_EICR << 2, READ, HSIZE_X32, 32\'h01); \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:112: syntax error, unexpected <<, expecting \')\'\n ahbPhase (`EIC_REG_EICR << 2, READ, HSIZE_X32, 32\'h01); \n ^~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:113: Define or directive not defined: \'`EIC_REG_EISMSK_0\'\n ahbPhase (`EIC_REG_EISMSK_0 << 2, READ, HSIZE_X32, St_x);\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:113: syntax error, unexpected <<, expecting \')\'\n ahbPhase (`EIC_REG_EISMSK_0 << 2, READ, HSIZE_X32, St_x);\n ^~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:114: Define or directive not defined: \'`EIC_REG_EIMSK_0\'\n ahbPhase (`EIC_REG_EIMSK_0 << 2, READ, HSIZE_X32, St_x);\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:114: syntax error, unexpected <<, expecting \')\'\n ahbPhase (`EIC_REG_EIMSK_0 << 2, READ, HSIZE_X32, St_x);\n ^~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:115: Define or directive not defined: \'`EIC_REG_EIMSK_1\'\n ahbPhase (`EIC_REG_EIMSK_1 << 2, READ, HSIZE_X32, St_x);\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:115: syntax error, unexpected <<, expecting \')\'\n ahbPhase (`EIC_REG_EIMSK_1 << 2, READ, HSIZE_X32, St_x);\n ^~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:118: syntax error, unexpected \'@\'\n @(posedge HCLK); signal[1] = 1\'b1;\n ^\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:121: syntax error, unexpected \'@\'\n @(posedge HCLK); signal[32] = 1\'b1;\n ^\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:122: syntax error, unexpected \'@\'\n @(posedge HCLK); signal[32] = 1\'b0;\n ^\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:125: Define or directive not defined: \'`EIC_REG_EIFR_1\'\n ahbPhase (`EIC_REG_EIFR_1 << 2, READ, HSIZE_X32, St_x);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:125: syntax error, unexpected <<, expecting \')\'\n ahbPhase (`EIC_REG_EIFR_1 << 2, READ, HSIZE_X32, St_x);\n ^~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:126: Define or directive not defined: \'`EIC_REG_EIFRC_1\'\n ahbPhase (`EIC_REG_EIFRC_1 << 2, WRITE, HSIZE_X32, St_x); \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:126: syntax error, unexpected <<, expecting \')\'\n ahbPhase (`EIC_REG_EIFRC_1 << 2, WRITE, HSIZE_X32, St_x); \n ^~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:127: Define or directive not defined: \'`EIC_REG_EIFR_0\'\n ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32\'h01);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:127: syntax error, unexpected <<, expecting \')\'\n ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32\'h01);\n ^~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:130: Define or directive not defined: \'`EIC_REG_EIFR_0\'\n ahbPhase (`EIC_REG_EIFR_0 << 2, WRITE, HSIZE_X32, St_x);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:130: syntax error, unexpected <<, expecting \')\'\n ahbPhase (`EIC_REG_EIFR_0 << 2, WRITE, HSIZE_X32, St_x);\n ^~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:131: Define or directive not defined: \'`EIC_REG_EIFR_0\'\n ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32\'h01); \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:131: syntax error, unexpected <<, expecting \')\'\n ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32\'h01); \n ^~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:134: Define or directive not defined: \'`EIC_REG_EIFRS_0\'\n ahbPhase (`EIC_REG_EIFRS_0 << 2, WRITE, HSIZE_X32, St_x);\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:134: syntax error, unexpected <<, expecting \')\'\n ahbPhase (`EIC_REG_EIFRS_0 << 2, WRITE, HSIZE_X32, St_x);\n ^~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:135: Define or directive not defined: \'`EIC_REG_EIFR_0\'\n ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32\'h04); \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:135: syntax error, unexpected <<, expecting \')\'\n ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32\'h04); \n ^~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:136: Define or directive not defined: \'`EIC_REG_EIFR_0\'\n ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, St_x);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:136: syntax error, unexpected <<, expecting \')\'\n ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, St_x);\n ^~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:137: Define or directive not defined: \'`EIC_REG_EIFR_0\'\n ahbPhaseLst(`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, St_x);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicAhbTest.v:137: syntax error, unexpected <<, expecting \')\'\n ahbPhaseLst(`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, St_x);\n ^~\n%Error: Exiting due to 45 error(s), 1 warning(s)\n' | 302,538 | module | module test_eicAhb;
`include "ahb_lite.vh"
reg [ `EIC_CHANNELS -1 : 0 ] signal;
wire [ 17 : 1 ] EIC_Offset;
wire [ 3 : 0 ] EIC_ShadowSet;
wire [ 7 : 0 ] EIC_Interrupt;
wire [ 5 : 0 ] EIC_Vector;
wire EIC_Present;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] read_addr;
wire [ 31 : 0 ] read_data;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] write_addr;
reg [ 31 : 0 ] write_data;
reg write_enable;
task delay;
begin
@(posedge HCLK);
@(posedge HCLK);
@(posedge HCLK);
end
endtask
mfp_ahb_lite_eic eic
(
.HCLK ( HCLK ),
.HRESETn ( HRESETn ),
.HADDR ( HADDR ),
.HBURST ( HBURST ),
.HSEL ( HSEL ),
.HSIZE ( HSIZE ),
.HTRANS ( HTRANS ),
.HWDATA ( HWDATA ),
.HWRITE ( HWRITE ),
.HRDATA ( HRDATA ),
.HREADY ( HREADY ),
.HRESP ( HRESP ),
.signal ( signal ),
.EIC_Offset ( EIC_Offset ),
.EIC_ShadowSet ( EIC_ShadowSet ),
.EIC_Interrupt ( EIC_Interrupt ),
.EIC_Vector ( EIC_Vector ),
.EIC_Present ( EIC_Present )
);
parameter Tclk = 20;
always #(Tclk/2) HCLK = ~HCLK;
initial begin
begin
signal = 16'b0;
HRESETn = 0;
@(posedge HCLK);
@(posedge HCLK);
HRESETn = 1;
@(posedge HCLK);
@(posedge HCLK);
ahbPhaseFst(`EIC_REG_EICR << 2, WRITE, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EISMSK_0 << 2, WRITE, HSIZE_X32, 32'h01);
ahbPhase (`EIC_REG_EIMSK_0 << 2, WRITE, HSIZE_X32, 32'h05);
ahbPhase (`EIC_REG_EIMSK_1 << 2, WRITE, HSIZE_X32, 32'h03);
ahbPhase (`EIC_REG_EICR << 2, READ, HSIZE_X32, 32'h01);
ahbPhase (`EIC_REG_EISMSK_0 << 2, READ, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIMSK_0 << 2, READ, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIMSK_1 << 2, READ, HSIZE_X32, St_x);
@(posedge HCLK); signal[0] = 1'b1;
@(posedge HCLK); signal[1] = 1'b1;
delay();
@(posedge HCLK); signal[32] = 1'b1;
@(posedge HCLK); signal[32] = 1'b0;
delay();
ahbPhase (`EIC_REG_EIFR_1 << 2, READ, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIFRC_1 << 2, WRITE, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32'h01);
delay();
ahbPhase (`EIC_REG_EIFR_0 << 2, WRITE, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32'h01);
delay();
ahbPhase (`EIC_REG_EIFRS_0 << 2, WRITE, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32'h04);
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, St_x);
ahbPhaseLst(`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, St_x);
delay();
end
$stop;
$finish;
end
endmodule | module test_eicAhb; |
`include "ahb_lite.vh"
reg [ `EIC_CHANNELS -1 : 0 ] signal;
wire [ 17 : 1 ] EIC_Offset;
wire [ 3 : 0 ] EIC_ShadowSet;
wire [ 7 : 0 ] EIC_Interrupt;
wire [ 5 : 0 ] EIC_Vector;
wire EIC_Present;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] read_addr;
wire [ 31 : 0 ] read_data;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] write_addr;
reg [ 31 : 0 ] write_data;
reg write_enable;
task delay;
begin
@(posedge HCLK);
@(posedge HCLK);
@(posedge HCLK);
end
endtask
mfp_ahb_lite_eic eic
(
.HCLK ( HCLK ),
.HRESETn ( HRESETn ),
.HADDR ( HADDR ),
.HBURST ( HBURST ),
.HSEL ( HSEL ),
.HSIZE ( HSIZE ),
.HTRANS ( HTRANS ),
.HWDATA ( HWDATA ),
.HWRITE ( HWRITE ),
.HRDATA ( HRDATA ),
.HREADY ( HREADY ),
.HRESP ( HRESP ),
.signal ( signal ),
.EIC_Offset ( EIC_Offset ),
.EIC_ShadowSet ( EIC_ShadowSet ),
.EIC_Interrupt ( EIC_Interrupt ),
.EIC_Vector ( EIC_Vector ),
.EIC_Present ( EIC_Present )
);
parameter Tclk = 20;
always #(Tclk/2) HCLK = ~HCLK;
initial begin
begin
signal = 16'b0;
HRESETn = 0;
@(posedge HCLK);
@(posedge HCLK);
HRESETn = 1;
@(posedge HCLK);
@(posedge HCLK);
ahbPhaseFst(`EIC_REG_EICR << 2, WRITE, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EISMSK_0 << 2, WRITE, HSIZE_X32, 32'h01);
ahbPhase (`EIC_REG_EIMSK_0 << 2, WRITE, HSIZE_X32, 32'h05);
ahbPhase (`EIC_REG_EIMSK_1 << 2, WRITE, HSIZE_X32, 32'h03);
ahbPhase (`EIC_REG_EICR << 2, READ, HSIZE_X32, 32'h01);
ahbPhase (`EIC_REG_EISMSK_0 << 2, READ, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIMSK_0 << 2, READ, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIMSK_1 << 2, READ, HSIZE_X32, St_x);
@(posedge HCLK); signal[0] = 1'b1;
@(posedge HCLK); signal[1] = 1'b1;
delay();
@(posedge HCLK); signal[32] = 1'b1;
@(posedge HCLK); signal[32] = 1'b0;
delay();
ahbPhase (`EIC_REG_EIFR_1 << 2, READ, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIFRC_1 << 2, WRITE, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32'h01);
delay();
ahbPhase (`EIC_REG_EIFR_0 << 2, WRITE, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32'h01);
delay();
ahbPhase (`EIC_REG_EIFRS_0 << 2, WRITE, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32'h04);
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, St_x);
ahbPhaseLst(`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, St_x);
delay();
end
$stop;
$finish;
end
endmodule | 1 |
138,549 | data/full_repos/permissive/84653396/src/testbench/eicTest.v | 84,653,396 | eicTest.v | v | 148 | 95 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:7: Cannot find include file: mfp_eic_core.vh\n`include "mfp_eic_core.vh" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/84653396/src/testbench,data/full_repos/permissive/84653396/mfp_eic_core.vh\n data/full_repos/permissive/84653396/src/testbench,data/full_repos/permissive/84653396/mfp_eic_core.vh.v\n data/full_repos/permissive/84653396/src/testbench,data/full_repos/permissive/84653396/mfp_eic_core.vh.sv\n mfp_eic_core.vh\n mfp_eic_core.vh.v\n mfp_eic_core.vh.sv\n obj_dir/mfp_eic_core.vh\n obj_dir/mfp_eic_core.vh.v\n obj_dir/mfp_eic_core.vh.sv\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:11: Cannot find include file: ahb_lite.vh\n `include "ahb_lite.vh" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:13: Define or directive not defined: \'`EIC_CHANNELS\'\n : ... Suggested alternative: \'`EIC_SENSE_CHANNELS\'\n reg [ `EIC_CHANNELS -1 : 0 ] signal;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:19: Define or directive not defined: \'`EIC_ADDR_WIDTH\'\n reg [ `EIC_ADDR_WIDTH - 1 : 0 ] read_addr;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:21: Define or directive not defined: \'`EIC_ADDR_WIDTH\'\n reg [ `EIC_ADDR_WIDTH - 1 : 0 ] write_addr;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:26: Define or directive not defined: \'`EIC_ADDR_WIDTH\'\n input [ `EIC_ADDR_WIDTH - 1 : 0 ] _read_addr;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:30: syntax error, unexpected \'@\'\n @(posedge HCLK);\n ^\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:38: Define or directive not defined: \'`EIC_ADDR_WIDTH\'\n input [ `EIC_ADDR_WIDTH - 1 : 0 ] _write_addr;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:46: syntax error, unexpected \'@\'\n @(posedge HCLK);\n ^\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:57: syntax error, unexpected \'@\'\n @(posedge HCLK);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/84653396/src/testbench/eicTest.v:81: Unsupported: Ignoring delay on this delayed statement.\n always #(Tclk/2) HCLK = ~HCLK;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:105: syntax error, unexpected \'@\'\n @(posedge HCLK);\n ^\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:109: syntax error, unexpected \'@\'\n @(posedge HCLK);\n ^\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:112: Define or directive not defined: \'`EIC_REG_EICR\'\n eicWrite(`EIC_REG_EICR, 32\'h01); \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:113: Define or directive not defined: \'`EIC_REG_EISMSK_0\'\n eicWrite(`EIC_REG_EISMSK_0, 32\'h05); \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:115: Define or directive not defined: \'`EIC_REG_EIMSK_0\'\n eicWrite(`EIC_REG_EIMSK_0, 32\'h03); \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:116: Define or directive not defined: \'`EIC_REG_EIMSK_1\'\n eicWrite(`EIC_REG_EIMSK_1, 32\'h01); \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:118: Define or directive not defined: \'`EIC_REG_EIMSK_0\'\n eicRead(`EIC_REG_EIMSK_0);\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:119: Define or directive not defined: \'`EIC_REG_EIMSK_1\'\n eicRead(`EIC_REG_EIMSK_1);\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:121: syntax error, unexpected \'@\'\n @(posedge HCLK); signal[0] = 1\'b1;\n ^\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:122: syntax error, unexpected \'@\'\n @(posedge HCLK); signal[1] = 1\'b1;\n ^\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:125: syntax error, unexpected \'@\'\n @(posedge HCLK); signal[32] = 1\'b1;\n ^\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:126: syntax error, unexpected \'@\'\n @(posedge HCLK); signal[32] = 1\'b0;\n ^\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:129: Define or directive not defined: \'`EIC_REG_EIFR_1\'\n eicRead(`EIC_REG_EIFR_1);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:131: Define or directive not defined: \'`EIC_REG_EIFRC_1\'\n eicWrite(`EIC_REG_EIFRC_1, 32\'h01); \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:133: Define or directive not defined: \'`EIC_REG_EIFR_0\'\n eicRead(`EIC_REG_EIFR_0);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:136: Define or directive not defined: \'`EIC_REG_EIFR_0\'\n eicWrite(`EIC_REG_EIFR_0, 32\'h01); \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:137: Define or directive not defined: \'`EIC_REG_EIFR_0\'\n eicRead(`EIC_REG_EIFR_0);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:140: Define or directive not defined: \'`EIC_REG_EIFRS_0\'\n eicWrite(`EIC_REG_EIFRS_0, 32\'h04); \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/84653396/src/testbench/eicTest.v:141: Define or directive not defined: \'`EIC_REG_EIFR_0\'\n eicRead(`EIC_REG_EIFR_0);\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 29 error(s), 1 warning(s)\n' | 302,539 | module | module test_eic;
`include "ahb_lite.vh"
reg [ `EIC_CHANNELS -1 : 0 ] signal;
wire [ 17 : 1 ] EIC_Offset;
wire [ 3 : 0 ] EIC_ShadowSet;
wire [ 7 : 0 ] EIC_Interrupt;
wire [ 5 : 0 ] EIC_Vector;
wire EIC_Present;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] read_addr;
wire [ 31 : 0 ] read_data;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] write_addr;
reg [ 31 : 0 ] write_data;
reg write_enable;
task eicRead;
input [ `EIC_ADDR_WIDTH - 1 : 0 ] _read_addr;
begin
read_addr = _read_addr;
@(posedge HCLK);
$display("%t READEN ADDR=%h DATA=%h",
$time, _read_addr, read_data);
end
endtask
task eicWrite;
input [ `EIC_ADDR_WIDTH - 1 : 0 ] _write_addr;
input [ 31 : 0 ] _write_data;
begin
write_addr = _write_addr;
write_data = _write_data;
write_enable = 1'b1;
@(posedge HCLK);
write_enable = 1'b0;
$display("%t WRITEN ADDR=%h DATA=%h",
$time, _write_addr, _write_data);
end
endtask
task delay;
begin
@(posedge HCLK);
@(posedge HCLK);
@(posedge HCLK);
end
endtask
mfp_eic_core eic
(
.CLK ( HCLK ),
.RESETn ( HRESETn ),
.signal ( signal ),
.read_addr ( read_addr ),
.read_data ( read_data ),
.write_addr ( write_addr ),
.write_data ( write_data ),
.write_enable ( write_enable ),
.EIC_Offset ( EIC_Offset ),
.EIC_ShadowSet ( EIC_ShadowSet ),
.EIC_Interrupt ( EIC_Interrupt ),
.EIC_Vector ( EIC_Vector ),
.EIC_Present ( EIC_Present )
);
parameter Tclk = 20;
always #(Tclk/2) HCLK = ~HCLK;
initial begin
begin
signal = 16'b0;
HRESETn = 0;
@(posedge HCLK);
@(posedge HCLK);
HRESETn = 1;
@(posedge HCLK);
@(posedge HCLK);
eicWrite(`EIC_REG_EICR, 32'h01);
eicWrite(`EIC_REG_EISMSK_0, 32'h05);
eicWrite(`EIC_REG_EIMSK_0, 32'h03);
eicWrite(`EIC_REG_EIMSK_1, 32'h01);
eicRead(`EIC_REG_EIMSK_0);
eicRead(`EIC_REG_EIMSK_1);
@(posedge HCLK); signal[0] = 1'b1;
@(posedge HCLK); signal[1] = 1'b1;
delay();
@(posedge HCLK); signal[32] = 1'b1;
@(posedge HCLK); signal[32] = 1'b0;
delay();
eicRead(`EIC_REG_EIFR_1);
eicWrite(`EIC_REG_EIFRC_1, 32'h01);
eicRead(`EIC_REG_EIFR_0);
delay();
eicWrite(`EIC_REG_EIFR_0, 32'h01);
eicRead(`EIC_REG_EIFR_0);
delay();
eicWrite(`EIC_REG_EIFRS_0, 32'h04);
eicRead(`EIC_REG_EIFR_0);
delay();
end
$stop;
$finish;
end
endmodule | module test_eic; |
`include "ahb_lite.vh"
reg [ `EIC_CHANNELS -1 : 0 ] signal;
wire [ 17 : 1 ] EIC_Offset;
wire [ 3 : 0 ] EIC_ShadowSet;
wire [ 7 : 0 ] EIC_Interrupt;
wire [ 5 : 0 ] EIC_Vector;
wire EIC_Present;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] read_addr;
wire [ 31 : 0 ] read_data;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] write_addr;
reg [ 31 : 0 ] write_data;
reg write_enable;
task eicRead;
input [ `EIC_ADDR_WIDTH - 1 : 0 ] _read_addr;
begin
read_addr = _read_addr;
@(posedge HCLK);
$display("%t READEN ADDR=%h DATA=%h",
$time, _read_addr, read_data);
end
endtask
task eicWrite;
input [ `EIC_ADDR_WIDTH - 1 : 0 ] _write_addr;
input [ 31 : 0 ] _write_data;
begin
write_addr = _write_addr;
write_data = _write_data;
write_enable = 1'b1;
@(posedge HCLK);
write_enable = 1'b0;
$display("%t WRITEN ADDR=%h DATA=%h",
$time, _write_addr, _write_data);
end
endtask
task delay;
begin
@(posedge HCLK);
@(posedge HCLK);
@(posedge HCLK);
end
endtask
mfp_eic_core eic
(
.CLK ( HCLK ),
.RESETn ( HRESETn ),
.signal ( signal ),
.read_addr ( read_addr ),
.read_data ( read_data ),
.write_addr ( write_addr ),
.write_data ( write_data ),
.write_enable ( write_enable ),
.EIC_Offset ( EIC_Offset ),
.EIC_ShadowSet ( EIC_ShadowSet ),
.EIC_Interrupt ( EIC_Interrupt ),
.EIC_Vector ( EIC_Vector ),
.EIC_Present ( EIC_Present )
);
parameter Tclk = 20;
always #(Tclk/2) HCLK = ~HCLK;
initial begin
begin
signal = 16'b0;
HRESETn = 0;
@(posedge HCLK);
@(posedge HCLK);
HRESETn = 1;
@(posedge HCLK);
@(posedge HCLK);
eicWrite(`EIC_REG_EICR, 32'h01);
eicWrite(`EIC_REG_EISMSK_0, 32'h05);
eicWrite(`EIC_REG_EIMSK_0, 32'h03);
eicWrite(`EIC_REG_EIMSK_1, 32'h01);
eicRead(`EIC_REG_EIMSK_0);
eicRead(`EIC_REG_EIMSK_1);
@(posedge HCLK); signal[0] = 1'b1;
@(posedge HCLK); signal[1] = 1'b1;
delay();
@(posedge HCLK); signal[32] = 1'b1;
@(posedge HCLK); signal[32] = 1'b0;
delay();
eicRead(`EIC_REG_EIFR_1);
eicWrite(`EIC_REG_EIFRC_1, 32'h01);
eicRead(`EIC_REG_EIFR_0);
delay();
eicWrite(`EIC_REG_EIFR_0, 32'h01);
eicRead(`EIC_REG_EIFR_0);
delay();
eicWrite(`EIC_REG_EIFRS_0, 32'h04);
eicRead(`EIC_REG_EIFR_0);
delay();
end
$stop;
$finish;
end
endmodule | 1 |
138,550 | data/full_repos/permissive/84681598/adder.v | 84,681,598 | adder.v | v | 103 | 153 | [] | [] | [] | null | line:6: before: "|" | null | 1: b"%Error: data/full_repos/permissive/84681598/adder.v:6: syntax error, unexpected '|', expecting ')' or ',' or or\n always @(x | y) fork \n ^\n%Error: data/full_repos/permissive/84681598/adder.v:29: Unsupported: fork statements\n always @(*) fork\n ^~~~\n%Error: data/full_repos/permissive/84681598/adder.v:53: Unsupported: fork statements\n always @(*) fork\n ^~~~\n%Error: Exiting due to 3 error(s)\n" | 302,540 | module | module B_cell(x,y,carry_in,sum, propagate_out, generate_out);
input x,y,carry_in;
output sum, propagate_out, generate_out;
reg sum, propagate_out, generate_out;
always @(x | y) fork
generate_out <= x & y;
propagate_out <= x ^ y;
join
always @(carry_in) begin
sum <= propagate_out^carry_in;
end
endmodule | module B_cell(x,y,carry_in,sum, propagate_out, generate_out); |
input x,y,carry_in;
output sum, propagate_out, generate_out;
reg sum, propagate_out, generate_out;
always @(x | y) fork
generate_out <= x & y;
propagate_out <= x ^ y;
join
always @(carry_in) begin
sum <= propagate_out^carry_in;
end
endmodule | 0 |
138,551 | data/full_repos/permissive/84681598/adder.v | 84,681,598 | adder.v | v | 103 | 153 | [] | [] | [] | null | line:6: before: "|" | null | 1: b"%Error: data/full_repos/permissive/84681598/adder.v:6: syntax error, unexpected '|', expecting ')' or ',' or or\n always @(x | y) fork \n ^\n%Error: data/full_repos/permissive/84681598/adder.v:29: Unsupported: fork statements\n always @(*) fork\n ^~~~\n%Error: data/full_repos/permissive/84681598/adder.v:53: Unsupported: fork statements\n always @(*) fork\n ^~~~\n%Error: Exiting due to 3 error(s)\n" | 302,540 | module | module CLA4(x, y, carry_in, sum, p_out, g_out);
input[3:0] x , y;
input carry_in;
output[3:0] sum;
output p_out, g_out;
wire[3:0] carry, p_in, g_in;
reg p_out, g_out;
B_cell b0(x[0], y[0], carry[0], sum[0], p_in[0], g_in[0]);
B_cell b1(x[1], y[1], carry[1], sum[1], p_in[1], g_in[1]);
B_cell b2(x[2], y[2], carry[2], sum[2], p_in[2], g_in[2]);
B_cell b3(x[3], y[3], carry[3], sum[3], p_in[3], g_in[3]);
always @(*) fork
carry[0] <= carry_in;
carry[1] <= g_in[0] | (p_in[0]&carry_in);
carry[2] <= g_in[1] | (p_in[1]&g_in[0]) | (p_in[1]&p_in[0]&carry_in);
carry[3] <= g_in[2] | (p_in[2]&g_in[1]) | (p_in[2]&p_in[1]&g_in[0]) | (p_in[2]&p_in[1]&p_in[0]&carry_in);
p_out <= p_in[0]&p_in[1]&p_in[2]&p_in[3];
g_out <= g_in[3] | (p_in[3]&g_in[2]) | (p_in[3]&p_in[2]&g_in[1]) | (p_in[3]&p_in[2]&p_in[1]&g_in[0]);
join
endmodule | module CLA4(x, y, carry_in, sum, p_out, g_out); |
input[3:0] x , y;
input carry_in;
output[3:0] sum;
output p_out, g_out;
wire[3:0] carry, p_in, g_in;
reg p_out, g_out;
B_cell b0(x[0], y[0], carry[0], sum[0], p_in[0], g_in[0]);
B_cell b1(x[1], y[1], carry[1], sum[1], p_in[1], g_in[1]);
B_cell b2(x[2], y[2], carry[2], sum[2], p_in[2], g_in[2]);
B_cell b3(x[3], y[3], carry[3], sum[3], p_in[3], g_in[3]);
always @(*) fork
carry[0] <= carry_in;
carry[1] <= g_in[0] | (p_in[0]&carry_in);
carry[2] <= g_in[1] | (p_in[1]&g_in[0]) | (p_in[1]&p_in[0]&carry_in);
carry[3] <= g_in[2] | (p_in[2]&g_in[1]) | (p_in[2]&p_in[1]&g_in[0]) | (p_in[2]&p_in[1]&p_in[0]&carry_in);
p_out <= p_in[0]&p_in[1]&p_in[2]&p_in[3];
g_out <= g_in[3] | (p_in[3]&g_in[2]) | (p_in[3]&p_in[2]&g_in[1]) | (p_in[3]&p_in[2]&p_in[1]&g_in[0]);
join
endmodule | 0 |
138,552 | data/full_repos/permissive/84681598/adder.v | 84,681,598 | adder.v | v | 103 | 153 | [] | [] | [] | null | line:6: before: "|" | null | 1: b"%Error: data/full_repos/permissive/84681598/adder.v:6: syntax error, unexpected '|', expecting ')' or ',' or or\n always @(x | y) fork \n ^\n%Error: data/full_repos/permissive/84681598/adder.v:29: Unsupported: fork statements\n always @(*) fork\n ^~~~\n%Error: data/full_repos/permissive/84681598/adder.v:53: Unsupported: fork statements\n always @(*) fork\n ^~~~\n%Error: Exiting due to 3 error(s)\n" | 302,540 | module | module adder(x, y, carry_in, sum, carry_out);
input[15:0] x , y;
input carry_in;
output[15:0] sum;
output carry_out;
wire[3:0] carry, p_in, g_in;
CLA4 cla4_0(x[3:0], y[3:0], carry[0], sum[3:0], p_in[0], g_in[0]);
CLA4 cla4_1(x[7:4], y[7:4], carry[1], sum[7:4], p_in[1], g_in[1]);
CLA4 cla4_2(x[11:8], y[11:8], carry[2], sum[11:8], p_in[2], g_in[2]);
CLA4 cla4_3(x[15:12], y[15:12], carry[3], sum[15:12], p_in[3], g_in[3]);
always @(*) fork
carry[0] <= carry_in;
carry[1] <= g_in[0] | (p_in[0]&carry_in);
carry[2] <= g_in[1] | (p_in[1]&g_in[0]) | (p_in[1]&p_in[0]&carry_in);
carry[3] <= g_in[2] | (p_in[2]&g_in[1]) | (p_in[2]&p_in[1]&g_in[0]) | (p_in[2]&p_in[1]&p_in[0]&carry_in);
carry_out <= g_in[3] | (p_in[3]&g_in[2]) | (p_in[3]&p_in[2]&g_in[1]) | (p_in[3]&p_in[2]&p_in[1]&g_in[0]) | (p_in[3]&p_in[2]&p_in[1]&p_in[0]&carry_in);
join
endmodule | module adder(x, y, carry_in, sum, carry_out); |
input[15:0] x , y;
input carry_in;
output[15:0] sum;
output carry_out;
wire[3:0] carry, p_in, g_in;
CLA4 cla4_0(x[3:0], y[3:0], carry[0], sum[3:0], p_in[0], g_in[0]);
CLA4 cla4_1(x[7:4], y[7:4], carry[1], sum[7:4], p_in[1], g_in[1]);
CLA4 cla4_2(x[11:8], y[11:8], carry[2], sum[11:8], p_in[2], g_in[2]);
CLA4 cla4_3(x[15:12], y[15:12], carry[3], sum[15:12], p_in[3], g_in[3]);
always @(*) fork
carry[0] <= carry_in;
carry[1] <= g_in[0] | (p_in[0]&carry_in);
carry[2] <= g_in[1] | (p_in[1]&g_in[0]) | (p_in[1]&p_in[0]&carry_in);
carry[3] <= g_in[2] | (p_in[2]&g_in[1]) | (p_in[2]&p_in[1]&g_in[0]) | (p_in[2]&p_in[1]&p_in[0]&carry_in);
carry_out <= g_in[3] | (p_in[3]&g_in[2]) | (p_in[3]&p_in[2]&g_in[1]) | (p_in[3]&p_in[2]&p_in[1]&g_in[0]) | (p_in[3]&p_in[2]&p_in[1]&p_in[0]&carry_in);
join
endmodule | 0 |
138,553 | data/full_repos/permissive/84681598/array8x8.v | 84,681,598 | array8x8.v | v | 89 | 47 | [] | [] | [] | [(1, 23), (25, 88)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/84681598/array8x8.v:54: Signal definition not found, creating implicitly: \'pp2\'\n .pp_out(pp2)\n ^~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/84681598/array8x8.v:72: Signal definition not found, creating implicitly: \'pp5\'\n : ... Suggested alternative: \'pp2\'\n .pp_out(pp5)\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/84681598/array8x8.v:12: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n : ... In instance array8x8.Array7\n P_partial = 16\'b0000000000000000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84681598/array8x8.v:17: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s VARREF \'M_in\' generates 16 bits.\n : ... In instance array8x8.Array7\n P_partial = M_in;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84681598/array8x8.v:54: Output port connection \'pp_out\' expects 17 bits on the pin connection, but pin connection\'s VARREF \'pp2\' generates 1 bits.\n : ... In instance array8x8\n .pp_out(pp2)\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/84681598/array8x8.v:72: Output port connection \'pp_out\' expects 17 bits on the pin connection, but pin connection\'s VARREF \'pp5\' generates 1 bits.\n : ... In instance array8x8\n .pp_out(pp5)\n ^~~~~~\n%Error: Exiting due to 6 warning(s)\n' | 302,541 | module | module array (pp_out, M_in, Q);
input [15:0] M_in;
input [7:0] Q;
output[16:0] pp_out;
reg[16:0] P_partial;
always@(M_in, Q, pp_out, P_partial)
begin
case(Q[0])
1'b0:
begin
P_partial = 16'b0000000000000000;
end
1'b1:
begin
P_partial = M_in;
end
endcase
end
assign pp_out = P_partial;
endmodule | module array (pp_out, M_in, Q); |
input [15:0] M_in;
input [7:0] Q;
output[16:0] pp_out;
reg[16:0] P_partial;
always@(M_in, Q, pp_out, P_partial)
begin
case(Q[0])
1'b0:
begin
P_partial = 16'b0000000000000000;
end
1'b1:
begin
P_partial = M_in;
end
endcase
end
assign pp_out = P_partial;
endmodule | 0 |
138,554 | data/full_repos/permissive/84681598/array8x8.v | 84,681,598 | array8x8.v | v | 89 | 47 | [] | [] | [] | [(1, 23), (25, 88)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/84681598/array8x8.v:54: Signal definition not found, creating implicitly: \'pp2\'\n .pp_out(pp2)\n ^~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/84681598/array8x8.v:72: Signal definition not found, creating implicitly: \'pp5\'\n : ... Suggested alternative: \'pp2\'\n .pp_out(pp5)\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/84681598/array8x8.v:12: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n : ... In instance array8x8.Array7\n P_partial = 16\'b0000000000000000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84681598/array8x8.v:17: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s VARREF \'M_in\' generates 16 bits.\n : ... In instance array8x8.Array7\n P_partial = M_in;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84681598/array8x8.v:54: Output port connection \'pp_out\' expects 17 bits on the pin connection, but pin connection\'s VARREF \'pp2\' generates 1 bits.\n : ... In instance array8x8\n .pp_out(pp2)\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/84681598/array8x8.v:72: Output port connection \'pp_out\' expects 17 bits on the pin connection, but pin connection\'s VARREF \'pp5\' generates 1 bits.\n : ... In instance array8x8\n .pp_out(pp5)\n ^~~~~~\n%Error: Exiting due to 6 warning(s)\n' | 302,541 | module | module array8x8(P, M, Q);
input [7:0] M, Q;
output [16:0] P;
wire [16:0] PP0;
wire [16:0] PP1;
wire [16:0] PP2;
wire [16:0] PP3;
wire [16:0] PP4;
wire [16:0] PP5;
wire [16:0] PP6;
wire [16:0] PP7;
array Array0(
.M_in({8'b00000000,M}),
.Q(Q),
.pp_out(PP0)
);
array Array1(
.M_in({8'b00000000,M} << 1),
.Q(Q >> 1),
.pp_out(PP1)
);
array Array2(
.M_in({8'b00000000,M} << 2),
.Q(Q >> 2),
.pp_out(pp2)
);
array Array3(
.M_in({8'b00000000,M} << 3),
.Q(Q >> 3),
.pp_out(PP3)
);
array Array4(
.M_in({8'b00000000,M} << 4),
.Q(Q >> 4),
.pp_out(PP4)
);
array Array5(
.M_in({8'b00000000,M} << 5),
.Q(Q >> 5),
.pp_out(pp5)
);
array Array6(
.M_in({8'b00000000,M} << 6),
.Q(Q >> 6),
.pp_out(PP6)
);
array Array7(
.M_in({8'b00000000,M} << 7),
.Q(Q >> 7),
.pp_out(PP7)
);
assign P = (PP0+PP1+PP2+PP3+PP4+PP5+PP6+PP7);
endmodule | module array8x8(P, M, Q); |
input [7:0] M, Q;
output [16:0] P;
wire [16:0] PP0;
wire [16:0] PP1;
wire [16:0] PP2;
wire [16:0] PP3;
wire [16:0] PP4;
wire [16:0] PP5;
wire [16:0] PP6;
wire [16:0] PP7;
array Array0(
.M_in({8'b00000000,M}),
.Q(Q),
.pp_out(PP0)
);
array Array1(
.M_in({8'b00000000,M} << 1),
.Q(Q >> 1),
.pp_out(PP1)
);
array Array2(
.M_in({8'b00000000,M} << 2),
.Q(Q >> 2),
.pp_out(pp2)
);
array Array3(
.M_in({8'b00000000,M} << 3),
.Q(Q >> 3),
.pp_out(PP3)
);
array Array4(
.M_in({8'b00000000,M} << 4),
.Q(Q >> 4),
.pp_out(PP4)
);
array Array5(
.M_in({8'b00000000,M} << 5),
.Q(Q >> 5),
.pp_out(pp5)
);
array Array6(
.M_in({8'b00000000,M} << 6),
.Q(Q >> 6),
.pp_out(PP6)
);
array Array7(
.M_in({8'b00000000,M} << 7),
.Q(Q >> 7),
.pp_out(PP7)
);
assign P = (PP0+PP1+PP2+PP3+PP4+PP5+PP6+PP7);
endmodule | 0 |
138,555 | data/full_repos/permissive/84681598/datapath.v | 84,681,598 | datapath.v | v | 518 | 205 | [] | [] | [] | null | line:103: before: "wire" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapath.v:103: syntax error, unexpected wire, expecting \',\' or \';\'\n wire eq_in, ne_in, gte_in, lt_in, or_out;\n ^~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:114: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:120: syntax error, unexpected assign\n assign out[2] = in[1] & !(in[0])\n ^~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:129: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:143: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:164: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:170: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg[63:0] C;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:177: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A - B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:180: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A * B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:183: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A / B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:186: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A >> B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:189: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A << B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:193: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:197: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = {C[0] , C[31:1]};\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:204: syntax error, unexpected \'=\', expecting IDENTIFIER\n rotateCount = 0;\n ^\n%Error: Exiting due to 15 error(s)\n' | 302,542 | module | module Datapath(clk, reset, mem_write_enable, mem_read_enable, G_ra, G_rb, G_rc, R_in, R_out, BA_out,CON_en, write_signals, read_signals, ALU_signals);
input[9:0] write_signals, read_signals;
input[4:0] ALU_signals;
input reset, mem_write_enable, mem_read_enable, G_ra, G_rb, G_rc, R_in, R_out, BA_out, CON_en;
input clk;
wire HI_write_enable, LO_write_enable, Zhi_write_enable, Zlo_write_enable, PC_write_enable, MDR_write_enable, MAR_write_enable, InPort_write_enable, OutPort_write_enable, Y_write_enable, IR_write_enable;
wire[15:0] GPR_write_enable, GPR_read_signals;
wire[31:0] R0_output, R1_output, R2_output, R3_output, R4_output, R5_output, R6_output, R7_output, R8_output, R9_output, R10_output,
R11_output, R12_output, R13_output, R14_output, R15_output, HI_output, LO_output, Zhi_output, Zlo_output, PC_output, MDR_output, InPort_output, C_sign_extended;
wire clk, Mem_read_enable, Mem_write_enable, Mem_RW, CON_out;
wire[31:0] Bus, MDMux_out, MDR_data, ALU_Y_input, Bus_enable, CLU_in, Data_to_RAM, Data_from_RAM;
wire[63:0] ALU_output;
wire[8:0] Mem_address;
CON_FF CON(CON_out, CLU_in, Bus, CON_en);
CLU control_unit(G_ra, G_rb, G_rc, R_in, R_out, BA_out, CLU_in, GPR_read_signals, GPR_write_enable, C_sign_extended);
ALU logic_unit(ALU_output, Bus, ALU_Y_input, C_sign_extended, ALU_signals);
RAM_1_PORT RAM(Mem_address, clk, Data_to_RAM, Mem_RW, Data_from_RAM);
Bus_Write_Mux Bus_Mux(Bus, Bus_enable, R0_output, R1_output, R2_output, R3_output, R4_output, R5_output, R6_output, R7_output, R8_output, R9_output, R10_output,
R11_output, R12_output, R13_output, R14_output, R15_output, HI_output, LO_output, Zhi_output, Zlo_output, PC_output, MDR_output, InPort_output, C_sign_extended);
reg32_R0 R0(R0_output, reset, clk, BA_out, GPR_write_enable[0], Bus);
reg32 R1(R1_output, reset, clk, GPR_write_enable[1], Bus);
reg32 R2(R2_output, reset, clk, GPR_write_enable[2], Bus);
reg32 R3(R3_output, reset, clk, GPR_write_enable[3], Bus);
reg32 R4(R4_output, reset, clk, GPR_write_enable[4], Bus);
reg32 R5(R5_output, reset, clk, GPR_write_enable[5], Bus);
reg32 R6(R6_output, reset, clk, GPR_write_enable[6], Bus);
reg32 R7(R7_output, reset, clk, GPR_write_enable[7], Bus);
reg32 R8(R8_output, reset, clk, GPR_write_enable[8], Bus);
reg32 R9(R9_output, reset, clk, GPR_write_enable[9], Bus);
reg32 R10(R10_output, reset, clk, GPR_write_enable[10], Bus);
reg32 R11(R11_output, reset, clk, GPR_write_enable[11], Bus);
reg32 R12(R12_output, reset, clk, GPR_write_enable[12], Bus);
reg32 R13(R13_output, reset, clk, GPR_write_enable[13], Bus);
reg32 R14(R14_output, reset, clk, GPR_write_enable[14], Bus);
reg32 R15(R15_output, reset, clk, GPR_write_enable[15], Bus);
reg32 HI(HI_output, reset, clk, HI_write_enable, Bus);
reg32 LO(LO_output, reset, clk, LO_write_enable, Bus);
reg32 PC(PC_output, reset, clk, PC_write_enable, Bus);
reg32_MDR MDR(Data_to_RAM, MDR_output, Mem_RW, reset, clk, MDR_write_enable, Mem_write_enable, Mem_read_enable, Bus, Data_from_RAM);
reg32_MAR MAR(Mem_address, reset, clk, MAR_write_enable, Bus);
reg32 InPort(InPort_output, reset, clk, InPort_write_enable, IOdata_in);
reg32 OutPort(IOdata_out, reset, clk, OutPort_write_enable, Bus);
reg32 IR(CLU_in, reset, clk, IR_write_enable, Bus);
reg32 Y(ALU_Y_input, reset, clk, Y_write_enable, Bus);
reg64 Z(Zhi_output, Zlo_output, reset, clk, ALU_output);
assign HI_write_enable = write_signals[0];
assign LO_write_enable = write_signals[1];
assign Zhi_write_enable = write_signals[2];
assign Zlo_write_enable = write_signals[3];
assign PC_write_enable = write_signals[4];
assign MDR_write_enable = write_signals[5];
assign OutPort_write_enable = write_signals[6];
assign InPort_write_enable = 1;
assign MAR_write_enable = write_signals[7];
assign Y_write_enable = write_signals[8];
assign IR_write_enable = write_signals[9];
assign Bus_enable[15:0] = GPR_read_signals[15:0];
assign Bus_enable[23:16] = read_signals[7:0];
endmodule | module Datapath(clk, reset, mem_write_enable, mem_read_enable, G_ra, G_rb, G_rc, R_in, R_out, BA_out,CON_en, write_signals, read_signals, ALU_signals); |
input[9:0] write_signals, read_signals;
input[4:0] ALU_signals;
input reset, mem_write_enable, mem_read_enable, G_ra, G_rb, G_rc, R_in, R_out, BA_out, CON_en;
input clk;
wire HI_write_enable, LO_write_enable, Zhi_write_enable, Zlo_write_enable, PC_write_enable, MDR_write_enable, MAR_write_enable, InPort_write_enable, OutPort_write_enable, Y_write_enable, IR_write_enable;
wire[15:0] GPR_write_enable, GPR_read_signals;
wire[31:0] R0_output, R1_output, R2_output, R3_output, R4_output, R5_output, R6_output, R7_output, R8_output, R9_output, R10_output,
R11_output, R12_output, R13_output, R14_output, R15_output, HI_output, LO_output, Zhi_output, Zlo_output, PC_output, MDR_output, InPort_output, C_sign_extended;
wire clk, Mem_read_enable, Mem_write_enable, Mem_RW, CON_out;
wire[31:0] Bus, MDMux_out, MDR_data, ALU_Y_input, Bus_enable, CLU_in, Data_to_RAM, Data_from_RAM;
wire[63:0] ALU_output;
wire[8:0] Mem_address;
CON_FF CON(CON_out, CLU_in, Bus, CON_en);
CLU control_unit(G_ra, G_rb, G_rc, R_in, R_out, BA_out, CLU_in, GPR_read_signals, GPR_write_enable, C_sign_extended);
ALU logic_unit(ALU_output, Bus, ALU_Y_input, C_sign_extended, ALU_signals);
RAM_1_PORT RAM(Mem_address, clk, Data_to_RAM, Mem_RW, Data_from_RAM);
Bus_Write_Mux Bus_Mux(Bus, Bus_enable, R0_output, R1_output, R2_output, R3_output, R4_output, R5_output, R6_output, R7_output, R8_output, R9_output, R10_output,
R11_output, R12_output, R13_output, R14_output, R15_output, HI_output, LO_output, Zhi_output, Zlo_output, PC_output, MDR_output, InPort_output, C_sign_extended);
reg32_R0 R0(R0_output, reset, clk, BA_out, GPR_write_enable[0], Bus);
reg32 R1(R1_output, reset, clk, GPR_write_enable[1], Bus);
reg32 R2(R2_output, reset, clk, GPR_write_enable[2], Bus);
reg32 R3(R3_output, reset, clk, GPR_write_enable[3], Bus);
reg32 R4(R4_output, reset, clk, GPR_write_enable[4], Bus);
reg32 R5(R5_output, reset, clk, GPR_write_enable[5], Bus);
reg32 R6(R6_output, reset, clk, GPR_write_enable[6], Bus);
reg32 R7(R7_output, reset, clk, GPR_write_enable[7], Bus);
reg32 R8(R8_output, reset, clk, GPR_write_enable[8], Bus);
reg32 R9(R9_output, reset, clk, GPR_write_enable[9], Bus);
reg32 R10(R10_output, reset, clk, GPR_write_enable[10], Bus);
reg32 R11(R11_output, reset, clk, GPR_write_enable[11], Bus);
reg32 R12(R12_output, reset, clk, GPR_write_enable[12], Bus);
reg32 R13(R13_output, reset, clk, GPR_write_enable[13], Bus);
reg32 R14(R14_output, reset, clk, GPR_write_enable[14], Bus);
reg32 R15(R15_output, reset, clk, GPR_write_enable[15], Bus);
reg32 HI(HI_output, reset, clk, HI_write_enable, Bus);
reg32 LO(LO_output, reset, clk, LO_write_enable, Bus);
reg32 PC(PC_output, reset, clk, PC_write_enable, Bus);
reg32_MDR MDR(Data_to_RAM, MDR_output, Mem_RW, reset, clk, MDR_write_enable, Mem_write_enable, Mem_read_enable, Bus, Data_from_RAM);
reg32_MAR MAR(Mem_address, reset, clk, MAR_write_enable, Bus);
reg32 InPort(InPort_output, reset, clk, InPort_write_enable, IOdata_in);
reg32 OutPort(IOdata_out, reset, clk, OutPort_write_enable, Bus);
reg32 IR(CLU_in, reset, clk, IR_write_enable, Bus);
reg32 Y(ALU_Y_input, reset, clk, Y_write_enable, Bus);
reg64 Z(Zhi_output, Zlo_output, reset, clk, ALU_output);
assign HI_write_enable = write_signals[0];
assign LO_write_enable = write_signals[1];
assign Zhi_write_enable = write_signals[2];
assign Zlo_write_enable = write_signals[3];
assign PC_write_enable = write_signals[4];
assign MDR_write_enable = write_signals[5];
assign OutPort_write_enable = write_signals[6];
assign InPort_write_enable = 1;
assign MAR_write_enable = write_signals[7];
assign Y_write_enable = write_signals[8];
assign IR_write_enable = write_signals[9];
assign Bus_enable[15:0] = GPR_read_signals[15:0];
assign Bus_enable[23:16] = read_signals[7:0];
endmodule | 0 |
138,556 | data/full_repos/permissive/84681598/datapath.v | 84,681,598 | datapath.v | v | 518 | 205 | [] | [] | [] | null | line:103: before: "wire" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapath.v:103: syntax error, unexpected wire, expecting \',\' or \';\'\n wire eq_in, ne_in, gte_in, lt_in, or_out;\n ^~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:114: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:120: syntax error, unexpected assign\n assign out[2] = in[1] & !(in[0])\n ^~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:129: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:143: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:164: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:170: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg[63:0] C;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:177: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A - B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:180: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A * B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:183: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A / B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:186: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A >> B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:189: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A << B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:193: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:197: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = {C[0] , C[31:1]};\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:204: syntax error, unexpected \'=\', expecting IDENTIFIER\n rotateCount = 0;\n ^\n%Error: Exiting due to 15 error(s)\n' | 302,542 | module | module CLU(G_ra, G_rb, G_rc, R_in, R_out, BA_out, IR, read_signals, write_signals, C_sign_extended);
input G_ra, G_rb, G_rc, R_in, R_out, BA_out;
input[31:0] IR;
output[15:0] read_signals, write_signals;
output[31:0] C_sign_extended;
Select_Decode SD(G_ra, G_rb, G_rc, R_in, R_out, BA_out, IR[26:23], IR[22:19], IR[18:15], read_signals, write_signals);
sign_extend SE(C_sign_extended, IR[18:0]);
endmodule | module CLU(G_ra, G_rb, G_rc, R_in, R_out, BA_out, IR, read_signals, write_signals, C_sign_extended); |
input G_ra, G_rb, G_rc, R_in, R_out, BA_out;
input[31:0] IR;
output[15:0] read_signals, write_signals;
output[31:0] C_sign_extended;
Select_Decode SD(G_ra, G_rb, G_rc, R_in, R_out, BA_out, IR[26:23], IR[22:19], IR[18:15], read_signals, write_signals);
sign_extend SE(C_sign_extended, IR[18:0]);
endmodule | 0 |
138,557 | data/full_repos/permissive/84681598/datapath.v | 84,681,598 | datapath.v | v | 518 | 205 | [] | [] | [] | null | line:103: before: "wire" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapath.v:103: syntax error, unexpected wire, expecting \',\' or \';\'\n wire eq_in, ne_in, gte_in, lt_in, or_out;\n ^~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:114: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:120: syntax error, unexpected assign\n assign out[2] = in[1] & !(in[0])\n ^~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:129: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:143: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:164: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:170: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg[63:0] C;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:177: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A - B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:180: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A * B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:183: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A / B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:186: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A >> B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:189: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A << B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:193: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:197: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = {C[0] , C[31:1]};\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:204: syntax error, unexpected \'=\', expecting IDENTIFIER\n rotateCount = 0;\n ^\n%Error: Exiting due to 15 error(s)\n' | 302,542 | module | module CON_FF(out, IR, Bus_data, CON_en);
input[31:0] IR, Bus_data;
input CON_en;
output out;
reg out
wire eq_in, ne_in, gte_in, lt_in, or_out;
wire[3:0] decoder_output;
decoder2_4 IR_decoder(decoder_output, IR[1:0]);
assign eq_in = ~| Bus_data;
assign ne_in = !eq_in;
assign gte_in = Bus_data[31];
assign lt_in = !gte_in;
assign or_out = (decoder_output[0] & eq_in) | (decoder_output[1] & ne_in) | (decoder_output[2] & gte_in) | (decoder_output[3] & lt_in) ;
always begin
out = or_out & CON_en;
endmodule | module CON_FF(out, IR, Bus_data, CON_en); |
input[31:0] IR, Bus_data;
input CON_en;
output out;
reg out
wire eq_in, ne_in, gte_in, lt_in, or_out;
wire[3:0] decoder_output;
decoder2_4 IR_decoder(decoder_output, IR[1:0]);
assign eq_in = ~| Bus_data;
assign ne_in = !eq_in;
assign gte_in = Bus_data[31];
assign lt_in = !gte_in;
assign or_out = (decoder_output[0] & eq_in) | (decoder_output[1] & ne_in) | (decoder_output[2] & gte_in) | (decoder_output[3] & lt_in) ;
always begin
out = or_out & CON_en;
endmodule | 0 |
138,558 | data/full_repos/permissive/84681598/datapath.v | 84,681,598 | datapath.v | v | 518 | 205 | [] | [] | [] | null | line:103: before: "wire" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapath.v:103: syntax error, unexpected wire, expecting \',\' or \';\'\n wire eq_in, ne_in, gte_in, lt_in, or_out;\n ^~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:114: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:120: syntax error, unexpected assign\n assign out[2] = in[1] & !(in[0])\n ^~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:129: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:143: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:164: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:170: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg[63:0] C;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:177: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A - B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:180: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A * B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:183: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A / B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:186: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A >> B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:189: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A << B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:193: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:197: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = {C[0] , C[31:1]};\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:204: syntax error, unexpected \'=\', expecting IDENTIFIER\n rotateCount = 0;\n ^\n%Error: Exiting due to 15 error(s)\n' | 302,542 | module | module decoder2_4(out, in);
input[1:0] in;
output[3:0] out;
assign out[3] = in[1] & in[0]
assign out[2] = in[1] & !(in[0])
assign out[1] = !(in[1]) & in[0]
assign out[0] = !(in[1]) & !(in[0])
endmodule | module decoder2_4(out, in); |
input[1:0] in;
output[3:0] out;
assign out[3] = in[1] & in[0]
assign out[2] = in[1] & !(in[0])
assign out[1] = !(in[1]) & in[0]
assign out[0] = !(in[1]) & !(in[0])
endmodule | 0 |
138,559 | data/full_repos/permissive/84681598/datapath.v | 84,681,598 | datapath.v | v | 518 | 205 | [] | [] | [] | null | line:103: before: "wire" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapath.v:103: syntax error, unexpected wire, expecting \',\' or \';\'\n wire eq_in, ne_in, gte_in, lt_in, or_out;\n ^~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:114: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:120: syntax error, unexpected assign\n assign out[2] = in[1] & !(in[0])\n ^~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:129: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:143: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:164: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:170: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg[63:0] C;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:177: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A - B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:180: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A * B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:183: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A / B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:186: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A >> B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:189: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A << B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:193: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:197: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = {C[0] , C[31:1]};\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:204: syntax error, unexpected \'=\', expecting IDENTIFIER\n rotateCount = 0;\n ^\n%Error: Exiting due to 15 error(s)\n' | 302,542 | module | module sign_extend(value_sign_extend, value);
input[18:0] value;
output[31:0] value_sign_extend;
assign value_sign_extend = {value[18],value[18],value[18],value[18],value[18],value[18],value[18],value[18],value[18],value[18],value[18],value[18],value[18],value[18], value[17:0]}
endmodule | module sign_extend(value_sign_extend, value); |
input[18:0] value;
output[31:0] value_sign_extend;
assign value_sign_extend = {value[18],value[18],value[18],value[18],value[18],value[18],value[18],value[18],value[18],value[18],value[18],value[18],value[18],value[18], value[17:0]}
endmodule | 0 |
138,560 | data/full_repos/permissive/84681598/datapath.v | 84,681,598 | datapath.v | v | 518 | 205 | [] | [] | [] | null | line:103: before: "wire" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapath.v:103: syntax error, unexpected wire, expecting \',\' or \';\'\n wire eq_in, ne_in, gte_in, lt_in, or_out;\n ^~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:114: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:120: syntax error, unexpected assign\n assign out[2] = in[1] & !(in[0])\n ^~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:129: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:143: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:164: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:170: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg[63:0] C;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:177: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A - B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:180: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A * B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:183: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A / B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:186: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A >> B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:189: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A << B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:193: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:197: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = {C[0] , C[31:1]};\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:204: syntax error, unexpected \'=\', expecting IDENTIFIER\n rotateCount = 0;\n ^\n%Error: Exiting due to 15 error(s)\n' | 302,542 | module | module Select_Decode(G_ra, G_rb, G_rc, R_in, R_out, BA_out, Ra, Rb, Rc, read_signals, write_signals);
input G_ra, G_rb, G_rc, R_in, R_out, BA_out;
input[3:0] Ra, Rb, Rc;
output[15:0] read_signals, write_signals;
wire[3:0] decoder_input;
wire[15:0] decoder_output;
decoder_4_16 decoder(decoder_input, decoder_output);
assign decoder_input = (Ra & G_ra) & (Rb & G_rb) & (Rc & G_rb);
assign read_signals = R_in & decoder_output;
assign write_signals = (BA_out & R_out) & decoder_output;
endmodule | module Select_Decode(G_ra, G_rb, G_rc, R_in, R_out, BA_out, Ra, Rb, Rc, read_signals, write_signals); |
input G_ra, G_rb, G_rc, R_in, R_out, BA_out;
input[3:0] Ra, Rb, Rc;
output[15:0] read_signals, write_signals;
wire[3:0] decoder_input;
wire[15:0] decoder_output;
decoder_4_16 decoder(decoder_input, decoder_output);
assign decoder_input = (Ra & G_ra) & (Rb & G_rb) & (Rc & G_rb);
assign read_signals = R_in & decoder_output;
assign write_signals = (BA_out & R_out) & decoder_output;
endmodule | 0 |
138,561 | data/full_repos/permissive/84681598/datapath.v | 84,681,598 | datapath.v | v | 518 | 205 | [] | [] | [] | null | line:103: before: "wire" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapath.v:103: syntax error, unexpected wire, expecting \',\' or \';\'\n wire eq_in, ne_in, gte_in, lt_in, or_out;\n ^~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:114: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:120: syntax error, unexpected assign\n assign out[2] = in[1] & !(in[0])\n ^~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:129: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:143: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:164: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:170: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg[63:0] C;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:177: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A - B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:180: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A * B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:183: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A / B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:186: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A >> B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:189: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A << B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:193: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:197: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = {C[0] , C[31:1]};\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:204: syntax error, unexpected \'=\', expecting IDENTIFIER\n rotateCount = 0;\n ^\n%Error: Exiting due to 15 error(s)\n' | 302,542 | module | module decoder_4_16 (in, out);
input[3:0] in;
output [15:0] out;
assign out[0] = (!in[3]) & (!in[2]) & (!in[1]) & (!in[0]);
assign out[1] = (!in[3]) & (!in[2]) & (!in[1]) & (in[0]);
assign out[2] = (!in[3]) & (!in[2]) & (in[1]) & (!in[0]);
assign out[3] = (!in[3]) & (!in[2]) & (in[1]) & (in[0]);
assign out[4] = (!in[3]) & (in[2]) & (!in[1]) & (!in[0]);
assign out[5] = (!in[3]) & (in[2]) & (!in[1]) & (in[0]);
assign out[6] = (!in[3]) & (in[2]) & (in[1]) & (!in[0]);
assign out[7] = (!in[3]) & (in[2]) & (in[1]) & (in[0]);
assign out[8] = (in[3]) & (!in[2]) & (!in[1]) & (!in[0]);
assign out[9] = (in[3]) & (!in[2]) & (!in[1]) & (in[0]);
assign out[10] = (in[3]) & (!in[2]) & (in[1]) & (!in[0]);
assign out[11] = (in[3]) & (!in[2]) & (in[1]) & (in[0]);
assign out[12] = (in[3]) & (in[2]) & (!in[1]) & (!in[0]);
assign out[13] = (in[3]) & (in[2]) & (!in[1]) & (in[0]);
assign out[14] = (in[3]) & (in[2]) & (in[1]) & (!in[0]);
assign out[15] = (in[3]) & (in[2]) & (in[1]) & (in[0]);
endmodule | module decoder_4_16 (in, out); |
input[3:0] in;
output [15:0] out;
assign out[0] = (!in[3]) & (!in[2]) & (!in[1]) & (!in[0]);
assign out[1] = (!in[3]) & (!in[2]) & (!in[1]) & (in[0]);
assign out[2] = (!in[3]) & (!in[2]) & (in[1]) & (!in[0]);
assign out[3] = (!in[3]) & (!in[2]) & (in[1]) & (in[0]);
assign out[4] = (!in[3]) & (in[2]) & (!in[1]) & (!in[0]);
assign out[5] = (!in[3]) & (in[2]) & (!in[1]) & (in[0]);
assign out[6] = (!in[3]) & (in[2]) & (in[1]) & (!in[0]);
assign out[7] = (!in[3]) & (in[2]) & (in[1]) & (in[0]);
assign out[8] = (in[3]) & (!in[2]) & (!in[1]) & (!in[0]);
assign out[9] = (in[3]) & (!in[2]) & (!in[1]) & (in[0]);
assign out[10] = (in[3]) & (!in[2]) & (in[1]) & (!in[0]);
assign out[11] = (in[3]) & (!in[2]) & (in[1]) & (in[0]);
assign out[12] = (in[3]) & (in[2]) & (!in[1]) & (!in[0]);
assign out[13] = (in[3]) & (in[2]) & (!in[1]) & (in[0]);
assign out[14] = (in[3]) & (in[2]) & (in[1]) & (!in[0]);
assign out[15] = (in[3]) & (in[2]) & (in[1]) & (in[0]);
endmodule | 0 |
138,562 | data/full_repos/permissive/84681598/datapath.v | 84,681,598 | datapath.v | v | 518 | 205 | [] | [] | [] | null | line:103: before: "wire" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapath.v:103: syntax error, unexpected wire, expecting \',\' or \';\'\n wire eq_in, ne_in, gte_in, lt_in, or_out;\n ^~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:114: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:120: syntax error, unexpected assign\n assign out[2] = in[1] & !(in[0])\n ^~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:129: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:143: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:164: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:170: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg[63:0] C;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:177: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A - B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:180: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A * B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:183: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A / B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:186: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A >> B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:189: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A << B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:193: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:197: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = {C[0] , C[31:1]};\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:204: syntax error, unexpected \'=\', expecting IDENTIFIER\n rotateCount = 0;\n ^\n%Error: Exiting due to 15 error(s)\n' | 302,542 | module | module ALU(C, A, B, immediate, opperation_signal);
input[31:0] A, B, immediate;
input[4:0] opperation_signal;
output[63:0] C;
reg[63:0] C;
integer i, rotateCount;
always @(*) begin
if (opperation_signal == 5'b00101) begin
C[31:0] = A + B;
end
if (opperation_signal == 5'b00110) begin
C[31:0] = A - B;
end
if (opperation_signal == 5'b10000) begin
C = A * B;
end
if (opperation_signal == 5'b10001) begin
C = A / B;
end
if (opperation_signal == 5'b01001) begin
C[31:0] = A >> B;
end
if (opperation_signal == 5'b01010) begin
C[31:0] = A << B;
end
if (opperation_signal == 5'b01011) begin
C[31:0] = A;
for(i = 0; i<32; i=i+1) begin
if(i<B) begin
C = {C[0] , C[31:1]};
end
end
end
if (opperation_signal == 5'b01100) begin
rotateCount = 0;
C[31:0] = A;
while((B > rotateCount) && (rotateCount < 32)) begin
C = {C[30:0] , C[31]};
rotateCount = rotateCount + 1;
end
end
if (opperation_signal == 5'b00111) begin
C[31:0] = A & B;
end
if (opperation_signal == 5'b01000) begin
C[31:0] = A | B;
end
if (opperation_signal == 5'b10010) begin
C[31:0] = !A + 1;
end
if (opperation_signal == 5'b10011) begin
C[31:0] = !A;
end
if (opperation_signal == 5'b01110) begin
C[31:0] = A & immediate;
end
if (opperation_signal == 5'b01111) begin
C[31:0] = A | immediate;
end
if (opperation_signal == 5'b01101) begin
C[31:0] = A + immediate;
end
if (opperation_signal == 5'b11111) begin
C[31:0] = A + 1;
end
end
endmodule | module ALU(C, A, B, immediate, opperation_signal); |
input[31:0] A, B, immediate;
input[4:0] opperation_signal;
output[63:0] C;
reg[63:0] C;
integer i, rotateCount;
always @(*) begin
if (opperation_signal == 5'b00101) begin
C[31:0] = A + B;
end
if (opperation_signal == 5'b00110) begin
C[31:0] = A - B;
end
if (opperation_signal == 5'b10000) begin
C = A * B;
end
if (opperation_signal == 5'b10001) begin
C = A / B;
end
if (opperation_signal == 5'b01001) begin
C[31:0] = A >> B;
end
if (opperation_signal == 5'b01010) begin
C[31:0] = A << B;
end
if (opperation_signal == 5'b01011) begin
C[31:0] = A;
for(i = 0; i<32; i=i+1) begin
if(i<B) begin
C = {C[0] , C[31:1]};
end
end
end
if (opperation_signal == 5'b01100) begin
rotateCount = 0;
C[31:0] = A;
while((B > rotateCount) && (rotateCount < 32)) begin
C = {C[30:0] , C[31]};
rotateCount = rotateCount + 1;
end
end
if (opperation_signal == 5'b00111) begin
C[31:0] = A & B;
end
if (opperation_signal == 5'b01000) begin
C[31:0] = A | B;
end
if (opperation_signal == 5'b10010) begin
C[31:0] = !A + 1;
end
if (opperation_signal == 5'b10011) begin
C[31:0] = !A;
end
if (opperation_signal == 5'b01110) begin
C[31:0] = A & immediate;
end
if (opperation_signal == 5'b01111) begin
C[31:0] = A | immediate;
end
if (opperation_signal == 5'b01101) begin
C[31:0] = A + immediate;
end
if (opperation_signal == 5'b11111) begin
C[31:0] = A + 1;
end
end
endmodule | 0 |
138,563 | data/full_repos/permissive/84681598/datapath.v | 84,681,598 | datapath.v | v | 518 | 205 | [] | [] | [] | null | line:103: before: "wire" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapath.v:103: syntax error, unexpected wire, expecting \',\' or \';\'\n wire eq_in, ne_in, gte_in, lt_in, or_out;\n ^~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:114: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:120: syntax error, unexpected assign\n assign out[2] = in[1] & !(in[0])\n ^~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:129: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:143: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:164: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:170: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg[63:0] C;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:177: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A - B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:180: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A * B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:183: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A / B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:186: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A >> B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:189: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A << B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:193: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:197: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = {C[0] , C[31:1]};\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:204: syntax error, unexpected \'=\', expecting IDENTIFIER\n rotateCount = 0;\n ^\n%Error: Exiting due to 15 error(s)\n' | 302,542 | module | module Bus_Write_Mux(busMuxOut, Bus_enable, in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8,
in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16, in_17, in_18, in_19, in_20, in_21, in_22, in_23);
input[31:0] Bus_enable, in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8,
in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16, in_17, in_18, in_19, in_20, in_21, in_22, in_23;
output[31:0] busMuxOut;
wire[4:0] Encoded_Signals;
Encoder32_5 bus_encoder(Bus_enable, Encoded_Signals);
mux24 select_input(busMuxOut, Encoded_Signals, in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8,
in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16, in_17, in_18, in_19, in_20, in_21, in_22, in_23);
endmodule | module Bus_Write_Mux(busMuxOut, Bus_enable, in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8,
in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16, in_17, in_18, in_19, in_20, in_21, in_22, in_23); |
input[31:0] Bus_enable, in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8,
in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16, in_17, in_18, in_19, in_20, in_21, in_22, in_23;
output[31:0] busMuxOut;
wire[4:0] Encoded_Signals;
Encoder32_5 bus_encoder(Bus_enable, Encoded_Signals);
mux24 select_input(busMuxOut, Encoded_Signals, in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8,
in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16, in_17, in_18, in_19, in_20, in_21, in_22, in_23);
endmodule | 0 |
138,564 | data/full_repos/permissive/84681598/datapath.v | 84,681,598 | datapath.v | v | 518 | 205 | [] | [] | [] | null | line:103: before: "wire" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapath.v:103: syntax error, unexpected wire, expecting \',\' or \';\'\n wire eq_in, ne_in, gte_in, lt_in, or_out;\n ^~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:114: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:120: syntax error, unexpected assign\n assign out[2] = in[1] & !(in[0])\n ^~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:129: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:143: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:164: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:170: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg[63:0] C;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:177: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A - B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:180: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A * B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:183: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A / B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:186: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A >> B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:189: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A << B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:193: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:197: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = {C[0] , C[31:1]};\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:204: syntax error, unexpected \'=\', expecting IDENTIFIER\n rotateCount = 0;\n ^\n%Error: Exiting due to 15 error(s)\n' | 302,542 | module | module Encoder32_5(out, in);
input[31:0] in;
output[4:0] out;
reg[4:0] out;
always @ (*)begin
if (in == 32'h00000002) begin
out = 5'b00001;
end
if (in == 32'h00000004) begin
out = 5'b00010;
end
if (in == 32'h00000008) begin
out = 5'b00011;
end
if (in == 32'h00000010) begin
out = 5'b00100;
end
if (in == 32'h00000020) begin
out = 5'b00101;
end
if (in == 32'h00000040) begin
out = 5'b00110;
end
if (in == 32'h00000080) begin
out = 5'b00111;
end
if (in == 32'h00000100) begin
out = 5'b01000;
end
if (in == 32'h00000200) begin
out = 5'b01001;
end
if (in == 32'h00000400) begin
out = 5'b01010;
end
if (in == 32'h00000800) begin
out = 5'b01011;
end
if (in == 32'h00001000) begin
out = 5'b01100;
end
if (in == 32'h00002000) begin
out = 5'b01101;
end
if (in == 32'h00004000) begin
out = 5'b01110;
end
if (in == 32'h00008000) begin
out = 5'b01111;
end
if (in == 32'h00010000) begin
out = 5'b10000;
end
if (in == 32'h00020000) begin
out = 5'b10001;
end
if (in == 32'h00040000) begin
out = 5'b10010;
end
if (in == 32'h00080000) begin
out = 5'b10011;
end
if (in == 32'h00100000) begin
out = 5'b10100;
end
if (in == 32'h00200000) begin
out = 5'b10101;
end
if (in == 32'h00400000) begin
out = 5'b10110;
end
if (in == 32'h00800000) begin
out = 5'b10111;
end
if (in == 32'h01000000) begin
out = 5'b11000;
end
end
endmodule | module Encoder32_5(out, in); |
input[31:0] in;
output[4:0] out;
reg[4:0] out;
always @ (*)begin
if (in == 32'h00000002) begin
out = 5'b00001;
end
if (in == 32'h00000004) begin
out = 5'b00010;
end
if (in == 32'h00000008) begin
out = 5'b00011;
end
if (in == 32'h00000010) begin
out = 5'b00100;
end
if (in == 32'h00000020) begin
out = 5'b00101;
end
if (in == 32'h00000040) begin
out = 5'b00110;
end
if (in == 32'h00000080) begin
out = 5'b00111;
end
if (in == 32'h00000100) begin
out = 5'b01000;
end
if (in == 32'h00000200) begin
out = 5'b01001;
end
if (in == 32'h00000400) begin
out = 5'b01010;
end
if (in == 32'h00000800) begin
out = 5'b01011;
end
if (in == 32'h00001000) begin
out = 5'b01100;
end
if (in == 32'h00002000) begin
out = 5'b01101;
end
if (in == 32'h00004000) begin
out = 5'b01110;
end
if (in == 32'h00008000) begin
out = 5'b01111;
end
if (in == 32'h00010000) begin
out = 5'b10000;
end
if (in == 32'h00020000) begin
out = 5'b10001;
end
if (in == 32'h00040000) begin
out = 5'b10010;
end
if (in == 32'h00080000) begin
out = 5'b10011;
end
if (in == 32'h00100000) begin
out = 5'b10100;
end
if (in == 32'h00200000) begin
out = 5'b10101;
end
if (in == 32'h00400000) begin
out = 5'b10110;
end
if (in == 32'h00800000) begin
out = 5'b10111;
end
if (in == 32'h01000000) begin
out = 5'b11000;
end
end
endmodule | 0 |
138,565 | data/full_repos/permissive/84681598/datapath.v | 84,681,598 | datapath.v | v | 518 | 205 | [] | [] | [] | null | line:103: before: "wire" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapath.v:103: syntax error, unexpected wire, expecting \',\' or \';\'\n wire eq_in, ne_in, gte_in, lt_in, or_out;\n ^~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:114: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:120: syntax error, unexpected assign\n assign out[2] = in[1] & !(in[0])\n ^~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:129: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:143: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:164: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:170: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg[63:0] C;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:177: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A - B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:180: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A * B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:183: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A / B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:186: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A >> B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:189: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A << B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:193: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:197: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = {C[0] , C[31:1]};\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:204: syntax error, unexpected \'=\', expecting IDENTIFIER\n rotateCount = 0;\n ^\n%Error: Exiting due to 15 error(s)\n' | 302,542 | module | module mux24(out, select, in_0, in_1, in_2 ,in_3, in_4,in_5, in_6, in_7, in_8, in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16,
in_17, in_18, in_19, in_20, in_21, in_22, in_23);
input[31:0] in_0, in_1, in_2 ,in_3, in_4,in_5, in_6, in_7, in_8, in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16,
in_17, in_18, in_19, in_20, in_21, in_22, in_23;
input[5:0] select;
output[31:0] out;
reg[31:0] out;
always begin
if (select == 5'b00000) begin
out = in_0;
end
if (select == 5'b00001) begin
out = in_1;
end
if (select == 5'b00010) begin
out = in_2;
end
if (select == 5'b00011) begin
out = in_3;
end
if (select == 5'b00100) begin
out = in_4;
end
if (select == 5'b00101) begin
out = in_5;
end
if (select == 5'b00110) begin
out = in_6;
end
if (select == 5'b00111) begin
out = in_7;
end
if (select == 5'b01000) begin
out = in_8;
end
if (select == 5'b01001) begin
out = in_9;
end
if (select == 5'b01010) begin
out = in_10;
end
if (select == 5'b01011) begin
out = in_11;
end
if (select == 5'b01100) begin
out = in_12;
end
if (select == 5'b01101) begin
out = in_13;
end
if (select == 5'b01110) begin
out = in_14;
end
if (select == 5'b01111) begin
out = in_15;
end
if (select == 5'b10000) begin
out = in_16;
end
if (select == 5'b10001) begin
out = in_17;
end
if (select == 5'b10010) begin
out = in_17;
end
if (select == 5'b10011) begin
out = in_19;
end
if (select == 5'b10100) begin
out = in_20;
end
if (select == 5'b10101) begin
out = in_21;
end
if (select == 5'b10110) begin
out = in_22;
end
if (select == 5'b10111) begin
out = in_23;
end
end
endmodule | module mux24(out, select, in_0, in_1, in_2 ,in_3, in_4,in_5, in_6, in_7, in_8, in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16,
in_17, in_18, in_19, in_20, in_21, in_22, in_23); |
input[31:0] in_0, in_1, in_2 ,in_3, in_4,in_5, in_6, in_7, in_8, in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16,
in_17, in_18, in_19, in_20, in_21, in_22, in_23;
input[5:0] select;
output[31:0] out;
reg[31:0] out;
always begin
if (select == 5'b00000) begin
out = in_0;
end
if (select == 5'b00001) begin
out = in_1;
end
if (select == 5'b00010) begin
out = in_2;
end
if (select == 5'b00011) begin
out = in_3;
end
if (select == 5'b00100) begin
out = in_4;
end
if (select == 5'b00101) begin
out = in_5;
end
if (select == 5'b00110) begin
out = in_6;
end
if (select == 5'b00111) begin
out = in_7;
end
if (select == 5'b01000) begin
out = in_8;
end
if (select == 5'b01001) begin
out = in_9;
end
if (select == 5'b01010) begin
out = in_10;
end
if (select == 5'b01011) begin
out = in_11;
end
if (select == 5'b01100) begin
out = in_12;
end
if (select == 5'b01101) begin
out = in_13;
end
if (select == 5'b01110) begin
out = in_14;
end
if (select == 5'b01111) begin
out = in_15;
end
if (select == 5'b10000) begin
out = in_16;
end
if (select == 5'b10001) begin
out = in_17;
end
if (select == 5'b10010) begin
out = in_17;
end
if (select == 5'b10011) begin
out = in_19;
end
if (select == 5'b10100) begin
out = in_20;
end
if (select == 5'b10101) begin
out = in_21;
end
if (select == 5'b10110) begin
out = in_22;
end
if (select == 5'b10111) begin
out = in_23;
end
end
endmodule | 0 |
138,566 | data/full_repos/permissive/84681598/datapath.v | 84,681,598 | datapath.v | v | 518 | 205 | [] | [] | [] | null | line:103: before: "wire" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapath.v:103: syntax error, unexpected wire, expecting \',\' or \';\'\n wire eq_in, ne_in, gte_in, lt_in, or_out;\n ^~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:114: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:120: syntax error, unexpected assign\n assign out[2] = in[1] & !(in[0])\n ^~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:129: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:143: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:164: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:170: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg[63:0] C;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:177: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A - B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:180: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A * B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:183: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A / B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:186: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A >> B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:189: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A << B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:193: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:197: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = {C[0] , C[31:1]};\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:204: syntax error, unexpected \'=\', expecting IDENTIFIER\n rotateCount = 0;\n ^\n%Error: Exiting due to 15 error(s)\n' | 302,542 | module | module reg32(Rout, clr, clk, write_enable, write_value);
input clr,clk, write_enable;
input [31:0] write_value;
output [31:0]Rout;
reg[31:0] Rout;
always @ (posedge clk)begin
if(clr) begin
Rout = 32'h00000000;
end
if(write_enable) begin
Rout = write_value;
end
end
endmodule | module reg32(Rout, clr, clk, write_enable, write_value); |
input clr,clk, write_enable;
input [31:0] write_value;
output [31:0]Rout;
reg[31:0] Rout;
always @ (posedge clk)begin
if(clr) begin
Rout = 32'h00000000;
end
if(write_enable) begin
Rout = write_value;
end
end
endmodule | 0 |
138,567 | data/full_repos/permissive/84681598/datapath.v | 84,681,598 | datapath.v | v | 518 | 205 | [] | [] | [] | null | line:103: before: "wire" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapath.v:103: syntax error, unexpected wire, expecting \',\' or \';\'\n wire eq_in, ne_in, gte_in, lt_in, or_out;\n ^~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:114: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:120: syntax error, unexpected assign\n assign out[2] = in[1] & !(in[0])\n ^~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:129: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:143: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:164: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:170: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg[63:0] C;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:177: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A - B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:180: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A * B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:183: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A / B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:186: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A >> B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:189: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A << B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:193: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:197: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = {C[0] , C[31:1]};\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:204: syntax error, unexpected \'=\', expecting IDENTIFIER\n rotateCount = 0;\n ^\n%Error: Exiting due to 15 error(s)\n' | 302,542 | module | module reg32_R0(Rout, clr, clk, BA_out, write_enable, write_value);
input clr,clk, write_enable, BA_out;
input [31:0] write_value;
output [31:0]Rout;
reg[31:0] Rout;
always @ (posedge clk)begin
if(clr) begin
Rout = 32'h00000000;
end
if(write_enable) begin
Rout = write_value & (!BA_out);
end
end
endmodule | module reg32_R0(Rout, clr, clk, BA_out, write_enable, write_value); |
input clr,clk, write_enable, BA_out;
input [31:0] write_value;
output [31:0]Rout;
reg[31:0] Rout;
always @ (posedge clk)begin
if(clr) begin
Rout = 32'h00000000;
end
if(write_enable) begin
Rout = write_value & (!BA_out);
end
end
endmodule | 0 |
138,568 | data/full_repos/permissive/84681598/datapath.v | 84,681,598 | datapath.v | v | 518 | 205 | [] | [] | [] | null | line:103: before: "wire" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapath.v:103: syntax error, unexpected wire, expecting \',\' or \';\'\n wire eq_in, ne_in, gte_in, lt_in, or_out;\n ^~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:114: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:120: syntax error, unexpected assign\n assign out[2] = in[1] & !(in[0])\n ^~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:129: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:143: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:164: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:170: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg[63:0] C;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:177: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A - B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:180: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A * B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:183: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A / B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:186: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A >> B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:189: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A << B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:193: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:197: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = {C[0] , C[31:1]};\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:204: syntax error, unexpected \'=\', expecting IDENTIFIER\n rotateCount = 0;\n ^\n%Error: Exiting due to 15 error(s)\n' | 302,542 | module | module reg32_MDR(Memory_output, Bus_output, Mem_RW, clr, clk, MDR_write_enable, Memory_write_enable, Memory_read_enable, Bus_input, Memory_input);
input clr,clk, Memory_write_enable, Memory_read_enable, MDR_write_enable;
input [31:0] Bus_input, Memory_input;
output [31:0]Memory_output, Bus_output;
output Mem_RW;
reg Mem_RW;
reg[31:0] Rout;
wire[31:0] register;
MDMux_in input_select(Bus_input, Memory_input, Memory_read_enable, register);
MDMux_out output_select(Rout, Memory_write_enable, Bus_output, Memory_output);
always @ (posedge clk)begin
Mem_RW = MDR_write_enable & (!Memory_read_enable);
if(clr) begin
Rout = 32'h00000000;
end
if(MDR_write_enable) begin
Rout = register;
end
end
endmodule | module reg32_MDR(Memory_output, Bus_output, Mem_RW, clr, clk, MDR_write_enable, Memory_write_enable, Memory_read_enable, Bus_input, Memory_input); |
input clr,clk, Memory_write_enable, Memory_read_enable, MDR_write_enable;
input [31:0] Bus_input, Memory_input;
output [31:0]Memory_output, Bus_output;
output Mem_RW;
reg Mem_RW;
reg[31:0] Rout;
wire[31:0] register;
MDMux_in input_select(Bus_input, Memory_input, Memory_read_enable, register);
MDMux_out output_select(Rout, Memory_write_enable, Bus_output, Memory_output);
always @ (posedge clk)begin
Mem_RW = MDR_write_enable & (!Memory_read_enable);
if(clr) begin
Rout = 32'h00000000;
end
if(MDR_write_enable) begin
Rout = register;
end
end
endmodule | 0 |
138,569 | data/full_repos/permissive/84681598/datapath.v | 84,681,598 | datapath.v | v | 518 | 205 | [] | [] | [] | null | line:103: before: "wire" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapath.v:103: syntax error, unexpected wire, expecting \',\' or \';\'\n wire eq_in, ne_in, gte_in, lt_in, or_out;\n ^~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:114: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:120: syntax error, unexpected assign\n assign out[2] = in[1] & !(in[0])\n ^~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:129: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:143: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:164: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:170: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg[63:0] C;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:177: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A - B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:180: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A * B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:183: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A / B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:186: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A >> B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:189: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A << B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:193: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:197: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = {C[0] , C[31:1]};\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:204: syntax error, unexpected \'=\', expecting IDENTIFIER\n rotateCount = 0;\n ^\n%Error: Exiting due to 15 error(s)\n' | 302,542 | module | module reg32_MAR(Rout, clr, clk, write_enable, write_value);
input clr,clk, write_enable;
input [31:0] write_value;
output [8:0] Rout;
reg[31:0] value;
assign Rout = value[8:0];
always @ (posedge clk)begin
if(clr) begin
value = 32'h00000000;
end
if(write_enable) begin
value = write_value;
end
end
endmodule | module reg32_MAR(Rout, clr, clk, write_enable, write_value); |
input clr,clk, write_enable;
input [31:0] write_value;
output [8:0] Rout;
reg[31:0] value;
assign Rout = value[8:0];
always @ (posedge clk)begin
if(clr) begin
value = 32'h00000000;
end
if(write_enable) begin
value = write_value;
end
end
endmodule | 0 |
138,570 | data/full_repos/permissive/84681598/datapath.v | 84,681,598 | datapath.v | v | 518 | 205 | [] | [] | [] | null | line:103: before: "wire" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapath.v:103: syntax error, unexpected wire, expecting \',\' or \';\'\n wire eq_in, ne_in, gte_in, lt_in, or_out;\n ^~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:114: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:120: syntax error, unexpected assign\n assign out[2] = in[1] & !(in[0])\n ^~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:129: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:143: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:164: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:170: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg[63:0] C;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:177: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A - B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:180: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A * B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:183: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A / B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:186: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A >> B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:189: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A << B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:193: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:197: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = {C[0] , C[31:1]};\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:204: syntax error, unexpected \'=\', expecting IDENTIFIER\n rotateCount = 0;\n ^\n%Error: Exiting due to 15 error(s)\n' | 302,542 | module | module MDMux_in(Bus_data, Mdata_in, Mem_read_enable, MDMux_out);
input Mem_read_enable;
input[31:0] Bus_data, Mdata_in;
output[31:0] MDMux_out;
assign MDMux_out = (Mem_read_enable & Mdata_in) | (!Mem_read_enable & Bus_data);
endmodule | module MDMux_in(Bus_data, Mdata_in, Mem_read_enable, MDMux_out); |
input Mem_read_enable;
input[31:0] Bus_data, Mdata_in;
output[31:0] MDMux_out;
assign MDMux_out = (Mem_read_enable & Mdata_in) | (!Mem_read_enable & Bus_data);
endmodule | 0 |
138,571 | data/full_repos/permissive/84681598/datapath.v | 84,681,598 | datapath.v | v | 518 | 205 | [] | [] | [] | null | line:103: before: "wire" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapath.v:103: syntax error, unexpected wire, expecting \',\' or \';\'\n wire eq_in, ne_in, gte_in, lt_in, or_out;\n ^~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:114: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:120: syntax error, unexpected assign\n assign out[2] = in[1] & !(in[0])\n ^~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:129: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:143: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:164: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:170: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg[63:0] C;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:177: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A - B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:180: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A * B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:183: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A / B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:186: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A >> B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:189: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A << B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:193: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:197: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = {C[0] , C[31:1]};\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:204: syntax error, unexpected \'=\', expecting IDENTIFIER\n rotateCount = 0;\n ^\n%Error: Exiting due to 15 error(s)\n' | 302,542 | module | module MDMux_out(MDR_data, Mem_write_enable, BusData_out, Mdata_out);
input Mem_write_enable;
input[31:0] MDR_data;
output[31:0] BusData_out, Mdata_out;
assign Mdata_out = MDR_data & Mem_write_enable;
assign BusData_out = MDR_data & (!Mem_write_enable);
endmodule | module MDMux_out(MDR_data, Mem_write_enable, BusData_out, Mdata_out); |
input Mem_write_enable;
input[31:0] MDR_data;
output[31:0] BusData_out, Mdata_out;
assign Mdata_out = MDR_data & Mem_write_enable;
assign BusData_out = MDR_data & (!Mem_write_enable);
endmodule | 0 |
138,572 | data/full_repos/permissive/84681598/datapath.v | 84,681,598 | datapath.v | v | 518 | 205 | [] | [] | [] | null | line:103: before: "wire" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapath.v:103: syntax error, unexpected wire, expecting \',\' or \';\'\n wire eq_in, ne_in, gte_in, lt_in, or_out;\n ^~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:114: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:120: syntax error, unexpected assign\n assign out[2] = in[1] & !(in[0])\n ^~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:129: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:143: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:164: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/84681598/datapath.v:170: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg[63:0] C;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:177: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A - B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:180: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A * B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:183: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = A / B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:186: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A >> B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:189: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A << B;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:193: syntax error, unexpected \'[\', expecting IDENTIFIER\n C[31:0] = A;\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:197: syntax error, unexpected \'=\', expecting IDENTIFIER\n C = {C[0] , C[31:1]};\n ^\n%Error: data/full_repos/permissive/84681598/datapath.v:204: syntax error, unexpected \'=\', expecting IDENTIFIER\n rotateCount = 0;\n ^\n%Error: Exiting due to 15 error(s)\n' | 302,542 | module | module reg64(Rout_hi, Rout_low, clr, clk, write_value);
input clr,clk;
input [63:0] write_value;
output [31:0]Rout_hi, Rout_low;
reg[31:0] Rout_hi, Rout_low;
always @ (posedge clk) begin
Rout_hi = write_value[63:32];
Rout_low = write_value[31:0];
if(clr) begin
Rout_hi = 0;
Rout_low = 0;
end
end
endmodule | module reg64(Rout_hi, Rout_low, clr, clk, write_value); |
input clr,clk;
input [63:0] write_value;
output [31:0]Rout_hi, Rout_low;
reg[31:0] Rout_hi, Rout_low;
always @ (posedge clk) begin
Rout_hi = write_value[63:32];
Rout_low = write_value[31:0];
if(clr) begin
Rout_hi = 0;
Rout_low = 0;
end
end
endmodule | 0 |
138,573 | data/full_repos/permissive/84681598/datapathP1.v | 84,681,598 | datapathP1.v | v | 409 | 191 | [] | [] | [] | null | line:151: before: "end" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapathP1.v:151: syntax error, unexpected end\n end\n ^~~\n%Error: Exiting due to 1 error(s)\n' | 302,543 | module | module datapathP1(ALU_signals, Mdata_in, Mdata_out, Maddress_out, reset, clk, Bus,
Mem_read, Mem_write,
R0_write_enable, R1_write_enable, R2_write_enable, R3_write_enable, R4_write_enable, R5_write_enable,
R6_write_enable, R7_write_enable, R8_write_enable, R9_write_enable, R10_write_enable, R11_write_enable,
R12_write_enable, R13_write_enable, R14_write_enable, R15_write_enable, Z_write_enable,
HI_write_enable, LO_write_enable, Zhi_write_enable, Zlo_write_enable, PC_write_enable,
MDR_write_enable, MAR_write_enable, InPort_write_enable, OutPort_write_enable, Y_write_enable, IR_write_enable,
Bus_select_R0, Bus_select_R1, Bus_select_R2, Bus_select_R3, Bus_select_R4, Bus_select_R5, Bus_select_R6, Bus_select_R7, Bus_select_R8, Bus_select_R9,
Bus_select_R10, Bus_select_R11, Bus_select_R12, Bus_select_R13, Bus_select_R14, Bus_select_R15, Bus_select_HI, Bus_select_LO, Bus_select_Zhi, Bus_select_Zlo, Bus_select_PC, Bus_select_MDR,
Bus_select_INPort, Bus_select_C);
input[31:0] Mdata_in;
input[3:0] ALU_signals;
input reset;
output[31:0] Maddress_out, Mdata_out;
input clk;
input Mem_read, Mem_write,
R0_write_enable, R1_write_enable, R2_write_enable, R3_write_enable, R4_write_enable, R5_write_enable,
R6_write_enable, R7_write_enable, R8_write_enable, R9_write_enable, R10_write_enable, R11_write_enable,
R12_write_enable, R13_write_enable, R14_write_enable, R15_write_enable, Z_write_enable,
HI_write_enable, LO_write_enable, Zhi_write_enable, Zlo_write_enable, PC_write_enable,
MDR_write_enable, MAR_write_enable, InPort_write_enable, OutPort_write_enable, Y_write_enable, IR_write_enable,
Bus_select_R0, Bus_select_R1, Bus_select_R2, Bus_select_R3, Bus_select_R4, Bus_select_R5, Bus_select_R6, Bus_select_R7, Bus_select_R8, Bus_select_R9,
Bus_select_R10, Bus_select_R11, Bus_select_R12, Bus_select_R13, Bus_select_R14, Bus_select_R15, Bus_select_HI, Bus_select_LO, Bus_select_Zhi, Bus_select_Zlo, Bus_select_PC, Bus_select_MDR,
Bus_select_INPort, Bus_select_C;
output [31:0] Bus;
wire[31:0] R0_output, R1_output, R2_output, R3_output, R4_output, R5_output, R6_output, R7_output, R8_output, R9_output, R10_output,
R11_output, R12_output, R13_output, R14_output, R15_output, HI_output, LO_output, Zhi_output, Zlo_output, PC_output, MDR_output, InPort_output, C_sign_extended;
wire clk, Mem_read, Mem_write;
wire[31:0] Bus, MDMux_out, MDR_data, ALU_Y_input, Bus_enable, BusMuxIn[31:0];
wire[63:0] ALU_output;
wire[31:0] CLU_in;
wire[31:0] IOdata_out, IOdata_in;
ALU Alu(Bus, ALU_Y_input, ALU_output, ALU_signals);
Bus_Write_Mux Bus_Mux(Bus, Bus_enable, R0_output, R1_output, R2_output, R3_output, R4_output, R5_output, R6_output, R7_output, R8_output, R9_output, R10_output,
R11_output, R12_output, R13_output, R14_output, R15_output, HI_output, LO_output, Zhi_output, Zlo_output, PC_output, MDR_output, InPort_output, C_sign_extended);
reg32 R0(R0_output, reset, clk, R0_write_enable, Bus);
reg32 R1(R1_output, reset, clk, R1_write_enable, Bus);
reg32 R2(R2_output, reset, clk, R2_write_enable, Bus);
reg32 R3(R3_output, reset, clk, R3_write_enable, Bus);
reg32 R4(R4_output, reset, clk, R4_write_enable, Bus);
reg32 R5(R5_output, reset, clk, R5_write_enable, Bus);
reg32 R6(R6_output, reset, clk, R6_write_enable, Bus);
reg32 R7(R7_output, reset, clk, R7_write_enable, Bus);
reg32 R8(R8_output, reset, clk, R8_write_enable, Bus);
reg32 R9(R9_output, reset, clk, R9_write_enable, Bus);
reg32 R10(R10_output, reset, clk, R10_write_enable, Bus);
reg32 R11(R11_output, reset, clk, R11_write_enable, Bus);
reg32 R12(R12_output, reset, clk, R12_write_enable, Bus);
reg32 R13(R13_output, reset, clk, R13_write_enable, Bus);
reg32 R14(R14_output, reset, clk, R14_write_enable, Bus);
reg32 R15(R15_output, reset, clk, R15_write_enable, Bus);
reg32 HI(HI_output, reset, clk, HI_write_enable, Bus);
reg32 LO(LO_output, reset, clk, LO_write_enable, Bus);
reg32 PC(PC_output, reset, clk, PC_write_enable, Bus);
reg32_MDR MDR(Mdata_out, MDR_output, reset, clk, MDR_write_enable, Mem_write, Mem_read, Bus, Mdata_in);
reg32 MAR(Maddress_out, reset, clk, MAR_write_enable, Bus);
reg32 InPort(InPort_output, reset, clk, InPort_write_enable, IOdata_in);
reg32 OutPort(IOdata_out, reset, clk, OutPort_write_enable, Bus);
reg32 IR(CLU_in, reset, clk, IR_write_enable, Bus);
reg32 Y(ALU_Y_input, reset, clk, Y_write_enable, Bus);
reg64 Z(Zhi_output, Zlo_output, reset, clk, Z_write_enable, ALU_output);
assign Bus_enable[23:0] = {Bus_select_R0, Bus_select_R1, Bus_select_R2, Bus_select_R3, Bus_select_R4, Bus_select_R5, Bus_select_R6, Bus_select_R7, Bus_select_R8, Bus_select_R9,
Bus_select_R10, Bus_select_R11, Bus_select_R12, Bus_select_R13, Bus_select_R14, Bus_select_R15, Bus_select_HI, Bus_select_LO, Bus_select_Zhi, Bus_select_Zlo, Bus_select_PC, Bus_select_MDR,
Bus_select_INPort, Bus_select_C};
endmodule | module datapathP1(ALU_signals, Mdata_in, Mdata_out, Maddress_out, reset, clk, Bus,
Mem_read, Mem_write,
R0_write_enable, R1_write_enable, R2_write_enable, R3_write_enable, R4_write_enable, R5_write_enable,
R6_write_enable, R7_write_enable, R8_write_enable, R9_write_enable, R10_write_enable, R11_write_enable,
R12_write_enable, R13_write_enable, R14_write_enable, R15_write_enable, Z_write_enable,
HI_write_enable, LO_write_enable, Zhi_write_enable, Zlo_write_enable, PC_write_enable,
MDR_write_enable, MAR_write_enable, InPort_write_enable, OutPort_write_enable, Y_write_enable, IR_write_enable,
Bus_select_R0, Bus_select_R1, Bus_select_R2, Bus_select_R3, Bus_select_R4, Bus_select_R5, Bus_select_R6, Bus_select_R7, Bus_select_R8, Bus_select_R9,
Bus_select_R10, Bus_select_R11, Bus_select_R12, Bus_select_R13, Bus_select_R14, Bus_select_R15, Bus_select_HI, Bus_select_LO, Bus_select_Zhi, Bus_select_Zlo, Bus_select_PC, Bus_select_MDR,
Bus_select_INPort, Bus_select_C); |
input[31:0] Mdata_in;
input[3:0] ALU_signals;
input reset;
output[31:0] Maddress_out, Mdata_out;
input clk;
input Mem_read, Mem_write,
R0_write_enable, R1_write_enable, R2_write_enable, R3_write_enable, R4_write_enable, R5_write_enable,
R6_write_enable, R7_write_enable, R8_write_enable, R9_write_enable, R10_write_enable, R11_write_enable,
R12_write_enable, R13_write_enable, R14_write_enable, R15_write_enable, Z_write_enable,
HI_write_enable, LO_write_enable, Zhi_write_enable, Zlo_write_enable, PC_write_enable,
MDR_write_enable, MAR_write_enable, InPort_write_enable, OutPort_write_enable, Y_write_enable, IR_write_enable,
Bus_select_R0, Bus_select_R1, Bus_select_R2, Bus_select_R3, Bus_select_R4, Bus_select_R5, Bus_select_R6, Bus_select_R7, Bus_select_R8, Bus_select_R9,
Bus_select_R10, Bus_select_R11, Bus_select_R12, Bus_select_R13, Bus_select_R14, Bus_select_R15, Bus_select_HI, Bus_select_LO, Bus_select_Zhi, Bus_select_Zlo, Bus_select_PC, Bus_select_MDR,
Bus_select_INPort, Bus_select_C;
output [31:0] Bus;
wire[31:0] R0_output, R1_output, R2_output, R3_output, R4_output, R5_output, R6_output, R7_output, R8_output, R9_output, R10_output,
R11_output, R12_output, R13_output, R14_output, R15_output, HI_output, LO_output, Zhi_output, Zlo_output, PC_output, MDR_output, InPort_output, C_sign_extended;
wire clk, Mem_read, Mem_write;
wire[31:0] Bus, MDMux_out, MDR_data, ALU_Y_input, Bus_enable, BusMuxIn[31:0];
wire[63:0] ALU_output;
wire[31:0] CLU_in;
wire[31:0] IOdata_out, IOdata_in;
ALU Alu(Bus, ALU_Y_input, ALU_output, ALU_signals);
Bus_Write_Mux Bus_Mux(Bus, Bus_enable, R0_output, R1_output, R2_output, R3_output, R4_output, R5_output, R6_output, R7_output, R8_output, R9_output, R10_output,
R11_output, R12_output, R13_output, R14_output, R15_output, HI_output, LO_output, Zhi_output, Zlo_output, PC_output, MDR_output, InPort_output, C_sign_extended);
reg32 R0(R0_output, reset, clk, R0_write_enable, Bus);
reg32 R1(R1_output, reset, clk, R1_write_enable, Bus);
reg32 R2(R2_output, reset, clk, R2_write_enable, Bus);
reg32 R3(R3_output, reset, clk, R3_write_enable, Bus);
reg32 R4(R4_output, reset, clk, R4_write_enable, Bus);
reg32 R5(R5_output, reset, clk, R5_write_enable, Bus);
reg32 R6(R6_output, reset, clk, R6_write_enable, Bus);
reg32 R7(R7_output, reset, clk, R7_write_enable, Bus);
reg32 R8(R8_output, reset, clk, R8_write_enable, Bus);
reg32 R9(R9_output, reset, clk, R9_write_enable, Bus);
reg32 R10(R10_output, reset, clk, R10_write_enable, Bus);
reg32 R11(R11_output, reset, clk, R11_write_enable, Bus);
reg32 R12(R12_output, reset, clk, R12_write_enable, Bus);
reg32 R13(R13_output, reset, clk, R13_write_enable, Bus);
reg32 R14(R14_output, reset, clk, R14_write_enable, Bus);
reg32 R15(R15_output, reset, clk, R15_write_enable, Bus);
reg32 HI(HI_output, reset, clk, HI_write_enable, Bus);
reg32 LO(LO_output, reset, clk, LO_write_enable, Bus);
reg32 PC(PC_output, reset, clk, PC_write_enable, Bus);
reg32_MDR MDR(Mdata_out, MDR_output, reset, clk, MDR_write_enable, Mem_write, Mem_read, Bus, Mdata_in);
reg32 MAR(Maddress_out, reset, clk, MAR_write_enable, Bus);
reg32 InPort(InPort_output, reset, clk, InPort_write_enable, IOdata_in);
reg32 OutPort(IOdata_out, reset, clk, OutPort_write_enable, Bus);
reg32 IR(CLU_in, reset, clk, IR_write_enable, Bus);
reg32 Y(ALU_Y_input, reset, clk, Y_write_enable, Bus);
reg64 Z(Zhi_output, Zlo_output, reset, clk, Z_write_enable, ALU_output);
assign Bus_enable[23:0] = {Bus_select_R0, Bus_select_R1, Bus_select_R2, Bus_select_R3, Bus_select_R4, Bus_select_R5, Bus_select_R6, Bus_select_R7, Bus_select_R8, Bus_select_R9,
Bus_select_R10, Bus_select_R11, Bus_select_R12, Bus_select_R13, Bus_select_R14, Bus_select_R15, Bus_select_HI, Bus_select_LO, Bus_select_Zhi, Bus_select_Zlo, Bus_select_PC, Bus_select_MDR,
Bus_select_INPort, Bus_select_C};
endmodule | 0 |
138,574 | data/full_repos/permissive/84681598/datapathP1.v | 84,681,598 | datapathP1.v | v | 409 | 191 | [] | [] | [] | null | line:151: before: "end" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapathP1.v:151: syntax error, unexpected end\n end\n ^~~\n%Error: Exiting due to 1 error(s)\n' | 302,543 | module | module ALU(A, B, C, opperation_signal);
input[31:0] A, B;
input[3:0] opperation_signal;
output[63:0] C;
reg[63:0] C;
integer rotateCount;
always @ (*) begin
case (opperation_signal)
0: C[31:0] = A + B;
1: C[31:0] = A - B;
2: C = A * B;
3: C = A / B;
4: C[31:0] = A >> B;
5: C[31:0] = A << B;
6: begin
rotateCount = 0;
C[31:0] = A;
while((B > rotateCount) && (rotateCount < 32)) begin
C = {C[0] , C[31:1]};
rotateCount = rotateCount + 1;
end
end
7:begin
rotateCount = 0;
C[31:0] = A;
while((B > rotateCount) && (rotateCount < 32)) begin
C = {C[30:0] , C[31]};
rotateCount = rotateCount + 1;
end
end
8: C[31:0] = A & B;
9: C[31:0] = A | B;
10: C[31:0] = ~A + 1;
11: C[31:0] = ~A;
12: C[31:0] = A + 1;
default: C = 0;
endcase
end
endmodule | module ALU(A, B, C, opperation_signal); |
input[31:0] A, B;
input[3:0] opperation_signal;
output[63:0] C;
reg[63:0] C;
integer rotateCount;
always @ (*) begin
case (opperation_signal)
0: C[31:0] = A + B;
1: C[31:0] = A - B;
2: C = A * B;
3: C = A / B;
4: C[31:0] = A >> B;
5: C[31:0] = A << B;
6: begin
rotateCount = 0;
C[31:0] = A;
while((B > rotateCount) && (rotateCount < 32)) begin
C = {C[0] , C[31:1]};
rotateCount = rotateCount + 1;
end
end
7:begin
rotateCount = 0;
C[31:0] = A;
while((B > rotateCount) && (rotateCount < 32)) begin
C = {C[30:0] , C[31]};
rotateCount = rotateCount + 1;
end
end
8: C[31:0] = A & B;
9: C[31:0] = A | B;
10: C[31:0] = ~A + 1;
11: C[31:0] = ~A;
12: C[31:0] = A + 1;
default: C = 0;
endcase
end
endmodule | 0 |
138,575 | data/full_repos/permissive/84681598/datapathP1.v | 84,681,598 | datapathP1.v | v | 409 | 191 | [] | [] | [] | null | line:151: before: "end" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapathP1.v:151: syntax error, unexpected end\n end\n ^~~\n%Error: Exiting due to 1 error(s)\n' | 302,543 | module | module Bus_Write_Mux(busMuxOut, Bus_enable, in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8,
in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16, in_17, in_18, in_19, in_20, in_21, in_22, in_23);
input[31:0] Bus_enable, in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8,
in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16, in_17, in_18, in_19, in_20, in_21, in_22, in_23;
output[31:0] busMuxOut;
wire[4:0] Encoded_Signals;
Encoder32_5 bus_encoder(Encoded_Signals, Bus_enable);
mux24 select_input(busMuxOut, Encoded_Signals, in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8,
in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16, in_17, in_18, in_19, in_20, in_21, in_22, in_23);
endmodule | module Bus_Write_Mux(busMuxOut, Bus_enable, in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8,
in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16, in_17, in_18, in_19, in_20, in_21, in_22, in_23); |
input[31:0] Bus_enable, in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8,
in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16, in_17, in_18, in_19, in_20, in_21, in_22, in_23;
output[31:0] busMuxOut;
wire[4:0] Encoded_Signals;
Encoder32_5 bus_encoder(Encoded_Signals, Bus_enable);
mux24 select_input(busMuxOut, Encoded_Signals, in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8,
in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16, in_17, in_18, in_19, in_20, in_21, in_22, in_23);
endmodule | 0 |
138,576 | data/full_repos/permissive/84681598/datapathP1.v | 84,681,598 | datapathP1.v | v | 409 | 191 | [] | [] | [] | null | line:151: before: "end" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapathP1.v:151: syntax error, unexpected end\n end\n ^~~\n%Error: Exiting due to 1 error(s)\n' | 302,543 | module | module Encoder32_5(out, in);
input[31:0] in;
output[4:0] out;
reg[4:0] out;
always @ (*) begin
if (in == 32'h00000002) begin
out = 5'b00001;
end
else if (in == 32'h00000004) begin
out = 5'b00010;
end
else if (in == 32'h00000008) begin
out = 5'b00011;
end
else if (in == 32'h00000010) begin
out = 5'b00100;
end
else if (in == 32'h00000020) begin
out = 5'b00101;
end
else if (in == 32'h00000040) begin
out = 5'b00110;
end
else if (in == 32'h00000080) begin
out = 5'b00111;
end
else if (in == 32'h00000100) begin
out = 5'b01000;
end
else if (in == 32'h00000200) begin
out = 5'b01001;
end
else if (in == 32'h00000400) begin
out = 5'b01010;
end
else if (in == 32'h00000800) begin
out = 5'b01011;
end
else if (in == 32'h00001000) begin
out = 5'b01100;
end
else if (in == 32'h00002000) begin
out = 5'b01101;
end
else if (in == 32'h00004000) begin
out = 5'b01110;
end
else if (in == 32'h00008000) begin
out = 5'b01111;
end
else if (in == 32'h00010000) begin
out = 5'b10000;
end
else if (in == 32'h00020000) begin
out = 5'b10001;
end
else if (in == 32'h00040000) begin
out = 5'b10010;
end
else if (in == 32'h00080000) begin
out = 5'b10011;
end
else if (in == 32'h00100000) begin
out = 5'b10100;
end
else if (in == 32'h00200000) begin
out = 5'b10101;
end
else if (in == 32'h00400000) begin
out = 5'b10110;
end
else if (in == 32'h00800000) begin
out = 5'b10111;
end
else if (in == 32'h01000000) begin
out = 5'b11000;
end
end
endmodule | module Encoder32_5(out, in); |
input[31:0] in;
output[4:0] out;
reg[4:0] out;
always @ (*) begin
if (in == 32'h00000002) begin
out = 5'b00001;
end
else if (in == 32'h00000004) begin
out = 5'b00010;
end
else if (in == 32'h00000008) begin
out = 5'b00011;
end
else if (in == 32'h00000010) begin
out = 5'b00100;
end
else if (in == 32'h00000020) begin
out = 5'b00101;
end
else if (in == 32'h00000040) begin
out = 5'b00110;
end
else if (in == 32'h00000080) begin
out = 5'b00111;
end
else if (in == 32'h00000100) begin
out = 5'b01000;
end
else if (in == 32'h00000200) begin
out = 5'b01001;
end
else if (in == 32'h00000400) begin
out = 5'b01010;
end
else if (in == 32'h00000800) begin
out = 5'b01011;
end
else if (in == 32'h00001000) begin
out = 5'b01100;
end
else if (in == 32'h00002000) begin
out = 5'b01101;
end
else if (in == 32'h00004000) begin
out = 5'b01110;
end
else if (in == 32'h00008000) begin
out = 5'b01111;
end
else if (in == 32'h00010000) begin
out = 5'b10000;
end
else if (in == 32'h00020000) begin
out = 5'b10001;
end
else if (in == 32'h00040000) begin
out = 5'b10010;
end
else if (in == 32'h00080000) begin
out = 5'b10011;
end
else if (in == 32'h00100000) begin
out = 5'b10100;
end
else if (in == 32'h00200000) begin
out = 5'b10101;
end
else if (in == 32'h00400000) begin
out = 5'b10110;
end
else if (in == 32'h00800000) begin
out = 5'b10111;
end
else if (in == 32'h01000000) begin
out = 5'b11000;
end
end
endmodule | 0 |
138,577 | data/full_repos/permissive/84681598/datapathP1.v | 84,681,598 | datapathP1.v | v | 409 | 191 | [] | [] | [] | null | line:151: before: "end" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapathP1.v:151: syntax error, unexpected end\n end\n ^~~\n%Error: Exiting due to 1 error(s)\n' | 302,543 | module | module mux24(out, select, in_0, in_1, in_2 ,in_3, in_4,in_5, in_6, in_7, in_8, in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16,
in_17, in_18, in_19, in_20, in_21, in_22, in_23);
input[31:0] in_0, in_1, in_2 ,in_3, in_4,in_5, in_6, in_7, in_8, in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16,
in_17, in_18, in_19, in_20, in_21, in_22, in_23;
input[4:0] select;
output[31:0] out;
reg[31:0] out;
always @ (*) begin
if (select == 5'b00000) begin
out = in_0;
end
else if (select == 5'b00001) begin
out = in_1;
end
else if (select == 5'b00010) begin
out = in_2;
end
else if (select == 5'b00011) begin
out = in_3;
end
else if (select == 5'b00100) begin
out = in_4;
end
else if (select == 5'b00101) begin
out = in_5;
end
else if (select == 5'b00110) begin
out = in_6;
end
else if (select == 5'b00111) begin
out = in_7;
end
else if (select == 5'b01000) begin
out = in_8;
end
else if (select == 5'b01001) begin
out = in_9;
end
else if (select == 5'b01010) begin
out = in_10;
end
else if (select == 5'b01011) begin
out = in_11;
end
else if (select == 5'b01100) begin
out = in_12;
end
else if (select == 5'b01101) begin
out = in_13;
end
else if (select == 5'b01110) begin
out = in_14;
end
else if (select == 5'b01111) begin
out = in_15;
end
else if (select == 5'b10000) begin
out = in_16;
end
else if (select == 5'b10001) begin
out = in_17;
end
else if (select == 5'b10010) begin
out = in_17;
end
else if (select == 5'b10011) begin
out = in_19;
end
else if (select == 5'b10100) begin
out = in_20;
end
else if (select == 5'b10101) begin
out = in_21;
end
else if (select == 5'b10110) begin
out = in_22;
end
else if (select == 5'b10111) begin
out = in_23;
end
else begin
out = 32'h00000000;
end
end
endmodule | module mux24(out, select, in_0, in_1, in_2 ,in_3, in_4,in_5, in_6, in_7, in_8, in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16,
in_17, in_18, in_19, in_20, in_21, in_22, in_23); |
input[31:0] in_0, in_1, in_2 ,in_3, in_4,in_5, in_6, in_7, in_8, in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16,
in_17, in_18, in_19, in_20, in_21, in_22, in_23;
input[4:0] select;
output[31:0] out;
reg[31:0] out;
always @ (*) begin
if (select == 5'b00000) begin
out = in_0;
end
else if (select == 5'b00001) begin
out = in_1;
end
else if (select == 5'b00010) begin
out = in_2;
end
else if (select == 5'b00011) begin
out = in_3;
end
else if (select == 5'b00100) begin
out = in_4;
end
else if (select == 5'b00101) begin
out = in_5;
end
else if (select == 5'b00110) begin
out = in_6;
end
else if (select == 5'b00111) begin
out = in_7;
end
else if (select == 5'b01000) begin
out = in_8;
end
else if (select == 5'b01001) begin
out = in_9;
end
else if (select == 5'b01010) begin
out = in_10;
end
else if (select == 5'b01011) begin
out = in_11;
end
else if (select == 5'b01100) begin
out = in_12;
end
else if (select == 5'b01101) begin
out = in_13;
end
else if (select == 5'b01110) begin
out = in_14;
end
else if (select == 5'b01111) begin
out = in_15;
end
else if (select == 5'b10000) begin
out = in_16;
end
else if (select == 5'b10001) begin
out = in_17;
end
else if (select == 5'b10010) begin
out = in_17;
end
else if (select == 5'b10011) begin
out = in_19;
end
else if (select == 5'b10100) begin
out = in_20;
end
else if (select == 5'b10101) begin
out = in_21;
end
else if (select == 5'b10110) begin
out = in_22;
end
else if (select == 5'b10111) begin
out = in_23;
end
else begin
out = 32'h00000000;
end
end
endmodule | 0 |
138,578 | data/full_repos/permissive/84681598/datapathP1.v | 84,681,598 | datapathP1.v | v | 409 | 191 | [] | [] | [] | null | line:151: before: "end" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapathP1.v:151: syntax error, unexpected end\n end\n ^~~\n%Error: Exiting due to 1 error(s)\n' | 302,543 | module | module reg32_MDR(Memory_output, Bus_output, clr, clk, MDR_write_enable, Memory_write_enable, Memory_read_enable, Bus_input, Memory_input);
input clr,clk, Memory_write_enable, Memory_read_enable, MDR_write_enable;
input [31:0] Bus_input, Memory_input;
output [31:0]Memory_output, Bus_output;
reg[31:0] Rout;
wire[31:0] register;
MDMux_in input_select(Bus_input, Memory_input, Memory_read_enable, register);
MDMux_out output_select(Rout, Memory_write_enable, Bus_output, Memory_output);
always @ (posedge clk)begin
if(clr) begin
Rout = 32'h00000000;
end
if(MDR_write_enable) begin
Rout = register;
end
end
endmodule | module reg32_MDR(Memory_output, Bus_output, clr, clk, MDR_write_enable, Memory_write_enable, Memory_read_enable, Bus_input, Memory_input); |
input clr,clk, Memory_write_enable, Memory_read_enable, MDR_write_enable;
input [31:0] Bus_input, Memory_input;
output [31:0]Memory_output, Bus_output;
reg[31:0] Rout;
wire[31:0] register;
MDMux_in input_select(Bus_input, Memory_input, Memory_read_enable, register);
MDMux_out output_select(Rout, Memory_write_enable, Bus_output, Memory_output);
always @ (posedge clk)begin
if(clr) begin
Rout = 32'h00000000;
end
if(MDR_write_enable) begin
Rout = register;
end
end
endmodule | 0 |
138,579 | data/full_repos/permissive/84681598/datapathP1.v | 84,681,598 | datapathP1.v | v | 409 | 191 | [] | [] | [] | null | line:151: before: "end" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapathP1.v:151: syntax error, unexpected end\n end\n ^~~\n%Error: Exiting due to 1 error(s)\n' | 302,543 | module | module MDMux_in(Bus_data, Mdata_in, Mem_read_enable, MDMux_out);
input Mem_read_enable;
input[31:0] Bus_data, Mdata_in;
output[31:0] MDMux_out;
assign MDMux_out = (Mem_read_enable & Mdata_in) | (!Mem_read_enable & Bus_data);
endmodule | module MDMux_in(Bus_data, Mdata_in, Mem_read_enable, MDMux_out); |
input Mem_read_enable;
input[31:0] Bus_data, Mdata_in;
output[31:0] MDMux_out;
assign MDMux_out = (Mem_read_enable & Mdata_in) | (!Mem_read_enable & Bus_data);
endmodule | 0 |
138,580 | data/full_repos/permissive/84681598/datapathP1.v | 84,681,598 | datapathP1.v | v | 409 | 191 | [] | [] | [] | null | line:151: before: "end" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapathP1.v:151: syntax error, unexpected end\n end\n ^~~\n%Error: Exiting due to 1 error(s)\n' | 302,543 | module | module MDMux_out(MDR_data, Mem_write_enable, BusData_out, Mdata_out);
input Mem_write_enable;
input[31:0] MDR_data;
output[31:0] BusData_out, Mdata_out;
assign Mdata_out = MDR_data & Mem_write_enable;
assign BusData_out = MDR_data & (!Mem_write_enable);
endmodule | module MDMux_out(MDR_data, Mem_write_enable, BusData_out, Mdata_out); |
input Mem_write_enable;
input[31:0] MDR_data;
output[31:0] BusData_out, Mdata_out;
assign Mdata_out = MDR_data & Mem_write_enable;
assign BusData_out = MDR_data & (!Mem_write_enable);
endmodule | 0 |
138,581 | data/full_repos/permissive/84681598/datapathP1.v | 84,681,598 | datapathP1.v | v | 409 | 191 | [] | [] | [] | null | line:151: before: "end" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapathP1.v:151: syntax error, unexpected end\n end\n ^~~\n%Error: Exiting due to 1 error(s)\n' | 302,543 | module | module reg32(Rout, clr, clk, write_enable, BusMuxOut);
input clr,clk, write_enable;
input [31:0] BusMuxOut;
output [31:0]Rout;
reg[31:0] Rout;
initial begin
Rout <= 0;
end
always @ (posedge clk)begin
if(clr == 1) begin
Rout <= 0;
end
else if(write_enable == 1) begin
Rout <= BusMuxOut;
end
end
endmodule | module reg32(Rout, clr, clk, write_enable, BusMuxOut); |
input clr,clk, write_enable;
input [31:0] BusMuxOut;
output [31:0]Rout;
reg[31:0] Rout;
initial begin
Rout <= 0;
end
always @ (posedge clk)begin
if(clr == 1) begin
Rout <= 0;
end
else if(write_enable == 1) begin
Rout <= BusMuxOut;
end
end
endmodule | 0 |
138,582 | data/full_repos/permissive/84681598/datapathP1.v | 84,681,598 | datapathP1.v | v | 409 | 191 | [] | [] | [] | null | line:151: before: "end" | null | 1: b'%Error: data/full_repos/permissive/84681598/datapathP1.v:151: syntax error, unexpected end\n end\n ^~~\n%Error: Exiting due to 1 error(s)\n' | 302,543 | module | module reg64(Rout_hi, Rout_low, clr, clk, write_enable, input_value);
input clr,clk, write_enable;
input [63:0] input_value;
output [31:0]Rout_hi, Rout_low;
reg[31:0] Rout_hi, Rout_low;
always @ (posedge clk)begin
if(write_enable == 1) begin
Rout_hi = input_value[63:32];
Rout_low = input_value[31:0];
end
else if(clr) begin
Rout_hi = 0;
Rout_low = 0;
end
end
endmodule | module reg64(Rout_hi, Rout_low, clr, clk, write_enable, input_value); |
input clr,clk, write_enable;
input [63:0] input_value;
output [31:0]Rout_hi, Rout_low;
reg[31:0] Rout_hi, Rout_low;
always @ (posedge clk)begin
if(write_enable == 1) begin
Rout_hi = input_value[63:32];
Rout_low = input_value[31:0];
end
else if(clr) begin
Rout_hi = 0;
Rout_low = 0;
end
end
endmodule | 0 |
138,583 | data/full_repos/permissive/84683344/clock.v | 84,683,344 | clock.v | v | 26 | 83 | [] | [] | [] | null | line:15: before: "(" | data/verilator_xmls/e65c8647-d44f-487e-9145-8326db715906.xml | null | 302,545 | module | module clock(clksrc, clk, clklk);
input clksrc;
output reg clk;
output clklk;
localparam threshold = 50000;
reg [31:0] count;
assign clklk = 1;
always @ (posedge(clksrc)) begin
if (count == threshold - 1) begin
count <= 32'b0;
clk <= ~clk;
end else begin
count <= count + 1;
clk <= clk;
end
end
endmodule | module clock(clksrc, clk, clklk); |
input clksrc;
output reg clk;
output clklk;
localparam threshold = 50000;
reg [31:0] count;
assign clklk = 1;
always @ (posedge(clksrc)) begin
if (count == threshold - 1) begin
count <= 32'b0;
clk <= ~clk;
end else begin
count <= count + 1;
clk <= clk;
end
end
endmodule | 0 |
138,584 | data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v | 84,760,667 | sorter_top.v | v | 422 | 81 | [] | [] | [] | [(2, 357), (360, 420)] | null | null | 1: b"%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:40: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Areg_reg_3_ ( .D(A_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/84760667/Synopsis/Synthesized,data/full_repos/permissive/84760667/SDFFSRX1\n data/full_repos/permissive/84760667/Synopsis/Synthesized,data/full_repos/permissive/84760667/SDFFSRX1.v\n data/full_repos/permissive/84760667/Synopsis/Synthesized,data/full_repos/permissive/84760667/SDFFSRX1.sv\n SDFFSRX1\n SDFFSRX1.v\n SDFFSRX1.sv\n obj_dir/SDFFSRX1\n obj_dir/SDFFSRX1.v\n obj_dir/SDFFSRX1.sv\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:42: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Areg_reg_2_ ( .D(A_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:44: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Areg_reg_1_ ( .D(A_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:46: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Areg_reg_0_ ( .D(A_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:48: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Breg_reg_3_ ( .D(B_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:50: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Breg_reg_2_ ( .D(B_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:52: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Breg_reg_1_ ( .D(B_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:54: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Breg_reg_0_ ( .D(B_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:56: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Creg_reg_3_ ( .D(C_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:58: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Creg_reg_2_ ( .D(C_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:60: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Creg_reg_1_ ( .D(C_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:62: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Creg_reg_0_ ( .D(C_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:64: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Dreg_reg_3_ ( .D(D_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:66: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Dreg_reg_2_ ( .D(D_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:68: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Dreg_reg_1_ ( .D(D_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:70: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Dreg_reg_0_ ( .D(D_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:72: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_A_reg_3_ ( .D(O1_A_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:74: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_A_reg_2_ ( .D(O1_A_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:76: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_A_reg_1_ ( .D(O1_A_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:78: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_A_reg_0_ ( .D(O1_A_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:80: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_B_reg_3_ ( .D(O1_B_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:82: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_B_reg_2_ ( .D(O1_B_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:84: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_B_reg_1_ ( .D(O1_B_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:86: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_B_reg_0_ ( .D(O1_B_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:88: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_C_reg_3_ ( .D(O1_C_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:90: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_C_reg_2_ ( .D(O1_C_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:92: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_C_reg_1_ ( .D(O1_C_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:94: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_C_reg_0_ ( .D(O1_C_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:96: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_D_reg_3_ ( .D(O1_D_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:98: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_D_reg_2_ ( .D(O1_D_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:100: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_D_reg_1_ ( .D(O1_D_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:102: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_D_reg_0_ ( .D(O1_D_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:104: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_A_reg_3_ ( .D(O2_A_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:106: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_A_reg_2_ ( .D(O2_A_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:108: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_A_reg_1_ ( .D(O2_A_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:110: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_A_reg_0_ ( .D(O2_A_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:112: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_B_reg_3_ ( .D(O2_B_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:114: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_B_reg_2_ ( .D(O2_B_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:116: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_B_reg_1_ ( .D(O2_B_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:118: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_B_reg_0_ ( .D(O2_B_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:120: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_C_reg_3_ ( .D(O2_C_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:122: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_C_reg_2_ ( .D(O2_C_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:124: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_C_reg_1_ ( .D(O2_C_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:126: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_C_reg_0_ ( .D(O2_C_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:128: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_D_reg_3_ ( .D(O2_D_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:130: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_D_reg_2_ ( .D(O2_D_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:132: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_D_reg_1_ ( .D(O2_D_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:134: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_D_reg_0_ ( .D(O2_D_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:136: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 S1reg_reg_3_ ( .D(S1_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:138: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 S1reg_reg_2_ ( .D(S1_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n" | 302,560 | module | module sorter ( Clk, A_3_, A_2_, A_1_, A_0_, B_3_, B_2_, B_1_, B_0_, C_3_,
C_2_, C_1_, C_0_, D_3_, D_2_, D_1_, D_0_, S1reg_3_, S1reg_2_, S1reg_1_,
S1reg_0_, S2reg_3_, S2reg_2_, S2reg_1_, S2reg_0_, S3reg_3_, S3reg_2_,
S3reg_1_, S3reg_0_, S4reg_3_, S4reg_2_, S4reg_1_, S4reg_0_ );
input Clk, A_3_, A_2_, A_1_, A_0_, B_3_, B_2_, B_1_, B_0_, C_3_, C_2_, C_1_,
C_0_, D_3_, D_2_, D_1_, D_0_;
output S1reg_3_, S1reg_2_, S1reg_1_, S1reg_0_, S2reg_3_, S2reg_2_, S2reg_1_,
S2reg_0_, S3reg_3_, S3reg_2_, S3reg_1_, S3reg_0_, S4reg_3_, S4reg_2_,
S4reg_1_, S4reg_0_;
wire Areg_3_, Areg_2_, Areg_1_, Areg_0_, Breg_3_, Breg_2_, Breg_1_,
Breg_0_, Creg_3_, Creg_2_, Creg_1_, Creg_0_, Dreg_3_, Dreg_1_,
R1_A_3_, R1_A_2_, R1_A_1_, R1_A_0_, O1_A_3_, O1_A_2_, O1_A_1_,
O1_A_0_, R1_B_3_, R1_B_2_, R1_B_1_, R1_B_0_, O1_B_3_, O1_B_2_,
O1_B_1_, O1_B_0_, R1_C_3_, R1_C_2_, R1_C_1_, R1_C_0_, O1_C_3_,
O1_C_2_, O1_C_1_, O1_C_0_, R1_D_3_, R1_D_1_, O1_D_3_, O1_D_2_,
O1_D_1_, O1_D_0_, R2_A_3_, R2_A_2_, R2_A_1_, R2_A_0_, O2_A_3_,
O2_A_2_, O2_A_1_, O2_A_0_, R2_B_3_, R2_B_2_, R2_B_1_, R2_B_0_,
O2_B_3_, O2_B_2_, O2_B_1_, O2_B_0_, R2_C_3_, R2_C_2_, R2_C_1_,
R2_C_0_, O2_C_3_, O2_C_2_, O2_C_1_, O2_C_0_, R2_D_3_, R2_D_1_,
O2_D_3_, O2_D_2_, O2_D_1_, O2_D_0_, S1_3_, S1_2_, S1_1_, S1_0_, S2_3_,
S2_2_, S2_1_, S2_0_, S3_3_, S3_2_, S3_1_, S3_0_, S4_3_, S4_2_, S4_1_,
S4_0_, N18, T1_1_3_, T1_1_2_, T1_1_1_, T1_1_0_, N22, T1_2_3_, T1_2_2_,
T1_2_0_, N26, N30, T2_1_3_, T2_1_2_, T2_1_1_, T2_1_0_, N34, T2_2_3_,
T2_2_2_, T2_2_0_, N38, N42, T3_1_3_, T3_1_2_, T3_1_1_, T3_1_0_, N46,
T3_2_3_, T3_2_2_, T3_2_0_, N50, n209, n210, n211, n212, n213, n214,
n215, n216, n217, n218, n219, n220, n222, n224, n227, n228, n230,
n231, n232, n233, n234, n235, n236, n237, n238, n239, n241, n243,
n246, n247, n249, n250, n251, n252, n253, n254, n255, n256, n257,
n258, n260, n262, n265, n266, n268, n269, n270, n271, n272, n273,
n274, n275, n276, n277, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11,
n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25,
n26, n27, n28, n87, n93, n96, n99, n105, n108, n114, n120, n131, n137,
n140, n143, n149, n152, n158, n164, n175, n181, n184, n187, n193,
n196, n202, n208, n221, n223, n225, n226, n229, n240, n242, n244,
n245, n248, n259, n261, n263, n264, n267, n278, n279, n280, n281,
n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, n292,
n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303;
SDFFSRX1 Areg_reg_3_ ( .D(A_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Areg_3_), .QN(n3) );
SDFFSRX1 Areg_reg_2_ ( .D(A_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Areg_2_) );
SDFFSRX1 Areg_reg_1_ ( .D(A_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Areg_1_), .QN(n9) );
SDFFSRX1 Areg_reg_0_ ( .D(A_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Areg_0_) );
SDFFSRX1 Breg_reg_3_ ( .D(B_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Breg_3_), .QN(n13) );
SDFFSRX1 Breg_reg_2_ ( .D(B_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Breg_2_), .QN(n4) );
SDFFSRX1 Breg_reg_1_ ( .D(B_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Breg_1_) );
SDFFSRX1 Breg_reg_0_ ( .D(B_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Breg_0_), .QN(n10) );
SDFFSRX1 Creg_reg_3_ ( .D(C_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Creg_3_), .QN(n14) );
SDFFSRX1 Creg_reg_2_ ( .D(C_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Creg_2_), .QN(n19) );
SDFFSRX1 Creg_reg_1_ ( .D(C_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Creg_1_) );
SDFFSRX1 Creg_reg_0_ ( .D(C_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Creg_0_), .QN(n22) );
SDFFSRX1 Dreg_reg_3_ ( .D(D_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Dreg_3_), .QN(n202) );
SDFFSRX1 Dreg_reg_2_ ( .D(D_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .QN(n181) );
SDFFSRX1 Dreg_reg_1_ ( .D(D_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Dreg_1_), .QN(n262) );
SDFFSRX1 Dreg_reg_0_ ( .D(D_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .QN(n158) );
SDFFSRX1 R1_A_reg_3_ ( .D(O1_A_3_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_A_3_), .QN(n1) );
SDFFSRX1 R1_A_reg_2_ ( .D(O1_A_2_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_A_2_) );
SDFFSRX1 R1_A_reg_1_ ( .D(O1_A_1_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_A_1_), .QN(n5) );
SDFFSRX1 R1_A_reg_0_ ( .D(O1_A_0_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_A_0_) );
SDFFSRX1 R1_B_reg_3_ ( .D(O1_B_3_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_B_3_), .QN(n17) );
SDFFSRX1 R1_B_reg_2_ ( .D(O1_B_2_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_B_2_), .QN(n7) );
SDFFSRX1 R1_B_reg_1_ ( .D(O1_B_1_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_B_1_) );
SDFFSRX1 R1_B_reg_0_ ( .D(O1_B_0_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_B_0_), .QN(n11) );
SDFFSRX1 R1_C_reg_3_ ( .D(O1_C_3_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_C_3_), .QN(n15) );
SDFFSRX1 R1_C_reg_2_ ( .D(O1_C_2_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_C_2_), .QN(n20) );
SDFFSRX1 R1_C_reg_1_ ( .D(O1_C_1_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_C_1_) );
SDFFSRX1 R1_C_reg_0_ ( .D(O1_C_0_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_C_0_), .QN(n23) );
SDFFSRX1 R1_D_reg_3_ ( .D(O1_D_3_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_D_3_), .QN(n282) );
SDFFSRX1 R1_D_reg_2_ ( .D(O1_D_2_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .QN(n267) );
SDFFSRX1 R1_D_reg_1_ ( .D(O1_D_1_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_D_1_), .QN(n243) );
SDFFSRX1 R1_D_reg_0_ ( .D(O1_D_0_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .QN(n261) );
SDFFSRX1 R2_A_reg_3_ ( .D(O2_A_3_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_A_3_), .QN(n2) );
SDFFSRX1 R2_A_reg_2_ ( .D(O2_A_2_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_A_2_) );
SDFFSRX1 R2_A_reg_1_ ( .D(O2_A_1_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_A_1_), .QN(n6) );
SDFFSRX1 R2_A_reg_0_ ( .D(O2_A_0_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_A_0_) );
SDFFSRX1 R2_B_reg_3_ ( .D(O2_B_3_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_B_3_), .QN(n18) );
SDFFSRX1 R2_B_reg_2_ ( .D(O2_B_2_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_B_2_), .QN(n8) );
SDFFSRX1 R2_B_reg_1_ ( .D(O2_B_1_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_B_1_) );
SDFFSRX1 R2_B_reg_0_ ( .D(O2_B_0_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_B_0_), .QN(n12) );
SDFFSRX1 R2_C_reg_3_ ( .D(O2_C_3_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_C_3_), .QN(n16) );
SDFFSRX1 R2_C_reg_2_ ( .D(O2_C_2_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_C_2_), .QN(n21) );
SDFFSRX1 R2_C_reg_1_ ( .D(O2_C_1_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_C_1_) );
SDFFSRX1 R2_C_reg_0_ ( .D(O2_C_0_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_C_0_), .QN(n24) );
SDFFSRX1 R2_D_reg_3_ ( .D(O2_D_3_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_D_3_), .QN(n303) );
SDFFSRX1 R2_D_reg_2_ ( .D(O2_D_2_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .QN(n298) );
SDFFSRX1 R2_D_reg_1_ ( .D(O2_D_1_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_D_1_), .QN(n224) );
SDFFSRX1 R2_D_reg_0_ ( .D(O2_D_0_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .QN(n295) );
SDFFSRX1 S1reg_reg_3_ ( .D(S1_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S1reg_3_) );
SDFFSRX1 S1reg_reg_2_ ( .D(S1_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S1reg_2_) );
SDFFSRX1 S1reg_reg_1_ ( .D(S1_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S1reg_1_) );
SDFFSRX1 S1reg_reg_0_ ( .D(S1_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S1reg_0_) );
SDFFSRX1 S2reg_reg_3_ ( .D(S2_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S2reg_3_) );
SDFFSRX1 S2reg_reg_2_ ( .D(S2_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S2reg_2_) );
SDFFSRX1 S2reg_reg_1_ ( .D(S2_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S2reg_1_) );
SDFFSRX1 S2reg_reg_0_ ( .D(S2_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S2reg_0_) );
SDFFSRX1 S3reg_reg_3_ ( .D(S3_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S3reg_3_) );
SDFFSRX1 S3reg_reg_2_ ( .D(S3_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S3reg_2_) );
SDFFSRX1 S3reg_reg_1_ ( .D(S3_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S3reg_1_) );
SDFFSRX1 S3reg_reg_0_ ( .D(S3_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S3reg_0_) );
SDFFSRX1 S4reg_reg_3_ ( .D(S4_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S4reg_3_) );
SDFFSRX1 S4reg_reg_2_ ( .D(S4_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S4reg_2_) );
SDFFSRX1 S4reg_reg_1_ ( .D(S4_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S4reg_1_) );
SDFFSRX1 S4reg_reg_0_ ( .D(S4_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S4reg_0_) );
INVX8 U140 ( .A(n209), .Y(T3_2_3_) );
INVX8 U141 ( .A(n210), .Y(T3_2_2_) );
INVX8 U143 ( .A(n212), .Y(T3_2_0_) );
INVX8 U144 ( .A(n213), .Y(T2_2_3_) );
INVX8 U145 ( .A(n214), .Y(T2_2_2_) );
INVX8 U147 ( .A(n216), .Y(T2_2_0_) );
INVX8 U148 ( .A(n217), .Y(T1_2_3_) );
INVX8 U149 ( .A(n218), .Y(T1_2_2_) );
INVX8 U151 ( .A(n220), .Y(T1_2_0_) );
INVX8 U152 ( .A(N50), .Y(n222) );
INVX8 U153 ( .A(n227), .Y(S2_3_) );
INVX8 U154 ( .A(n228), .Y(T3_1_3_) );
INVX8 U155 ( .A(n230), .Y(S2_2_) );
INVX8 U156 ( .A(n231), .Y(T3_1_2_) );
INVX8 U157 ( .A(n232), .Y(S2_1_) );
INVX8 U158 ( .A(n233), .Y(T3_1_1_) );
INVX8 U159 ( .A(n234), .Y(S2_0_) );
INVX8 U160 ( .A(n235), .Y(T3_1_0_) );
INVX8 U162 ( .A(n236), .Y(S1_3_) );
INVX8 U163 ( .A(n237), .Y(S1_2_) );
INVX8 U164 ( .A(n238), .Y(S1_1_) );
INVX8 U165 ( .A(n239), .Y(S1_0_) );
INVX8 U167 ( .A(N38), .Y(n241) );
INVX8 U168 ( .A(n246), .Y(O2_B_3_) );
INVX8 U169 ( .A(n247), .Y(T2_1_3_) );
INVX8 U170 ( .A(n249), .Y(O2_B_2_) );
INVX8 U171 ( .A(n250), .Y(T2_1_2_) );
INVX8 U172 ( .A(n251), .Y(O2_B_1_) );
INVX8 U173 ( .A(n252), .Y(T2_1_1_) );
INVX8 U174 ( .A(n253), .Y(O2_B_0_) );
INVX8 U175 ( .A(n254), .Y(T2_1_0_) );
INVX8 U177 ( .A(n255), .Y(O2_A_3_) );
INVX8 U178 ( .A(n256), .Y(O2_A_2_) );
INVX8 U179 ( .A(n257), .Y(O2_A_1_) );
INVX8 U180 ( .A(n258), .Y(O2_A_0_) );
INVX8 U182 ( .A(N26), .Y(n260) );
INVX8 U183 ( .A(n265), .Y(O1_B_3_) );
INVX8 U184 ( .A(n266), .Y(T1_1_3_) );
INVX8 U185 ( .A(n268), .Y(O1_B_2_) );
INVX8 U186 ( .A(n269), .Y(T1_1_2_) );
INVX8 U187 ( .A(n270), .Y(O1_B_1_) );
INVX8 U188 ( .A(n271), .Y(T1_1_1_) );
INVX8 U189 ( .A(n272), .Y(O1_B_0_) );
INVX8 U190 ( .A(n273), .Y(T1_1_0_) );
INVX8 U192 ( .A(n274), .Y(O1_A_3_) );
INVX8 U193 ( .A(n275), .Y(O1_A_2_) );
INVX8 U194 ( .A(n276), .Y(O1_A_1_) );
INVX8 U195 ( .A(n277), .Y(O1_A_0_) );
OAI22X1 U197 ( .A0(N50), .A1(n303), .B0(n209), .B1(n222), .Y(S4_3_) );
OAI22X1 U198 ( .A0(N50), .A1(n298), .B0(n210), .B1(n222), .Y(S4_2_) );
OAI22X1 U199 ( .A0(N50), .A1(n224), .B0(n211), .B1(n222), .Y(S4_1_) );
OAI22X1 U200 ( .A0(N50), .A1(n295), .B0(n212), .B1(n222), .Y(S4_0_) );
OAI22X1 U201 ( .A0(n222), .A1(n303), .B0(N50), .B1(n209), .Y(S3_3_) );
AOI22X1 U202 ( .A0(n93), .A1(R2_C_3_), .B0(T3_1_3_), .B1(N46), .Y(n209) );
OAI22X1 U203 ( .A0(n222), .A1(n298), .B0(N50), .B1(n210), .Y(S3_2_) );
AOI22X1 U204 ( .A0(n93), .A1(R2_C_2_), .B0(T3_1_2_), .B1(N46), .Y(n210) );
OAI22X1 U205 ( .A0(n222), .A1(n224), .B0(N50), .B1(n211), .Y(S3_1_) );
AOI22X1 U206 ( .A0(n93), .A1(R2_C_1_), .B0(T3_1_1_), .B1(N46), .Y(n211) );
OAI22X1 U207 ( .A0(n222), .A1(n295), .B0(N50), .B1(n212), .Y(S3_0_) );
AOI22X1 U208 ( .A0(n93), .A1(R2_C_0_), .B0(T3_1_0_), .B1(N46), .Y(n212) );
AOI22X1 U209 ( .A0(N46), .A1(R2_C_3_), .B0(n93), .B1(T3_1_3_), .Y(n227) );
AOI22X1 U210 ( .A0(N42), .A1(R2_A_3_), .B0(n87), .B1(R2_B_3_), .Y(n228) );
AOI22X1 U211 ( .A0(N46), .A1(R2_C_2_), .B0(n93), .B1(T3_1_2_), .Y(n230) );
AOI22X1 U212 ( .A0(N42), .A1(R2_A_2_), .B0(n87), .B1(R2_B_2_), .Y(n231) );
AOI22X1 U213 ( .A0(N46), .A1(R2_C_1_), .B0(n93), .B1(T3_1_1_), .Y(n232) );
AOI22X1 U214 ( .A0(N42), .A1(R2_A_1_), .B0(n87), .B1(R2_B_1_), .Y(n233) );
AOI22X1 U215 ( .A0(N46), .A1(R2_C_0_), .B0(n93), .B1(T3_1_0_), .Y(n234) );
AOI22X1 U216 ( .A0(N42), .A1(R2_A_0_), .B0(n87), .B1(R2_B_0_), .Y(n235) );
AOI22X1 U217 ( .A0(R2_B_3_), .A1(N42), .B0(n87), .B1(R2_A_3_), .Y(n236) );
AOI22X1 U218 ( .A0(N42), .A1(R2_B_2_), .B0(n87), .B1(R2_A_2_), .Y(n237) );
AOI22X1 U219 ( .A0(N42), .A1(R2_B_1_), .B0(n87), .B1(R2_A_1_), .Y(n238) );
AOI22X1 U220 ( .A0(N42), .A1(R2_B_0_), .B0(n87), .B1(R2_A_0_), .Y(n239) );
OAI22X1 U221 ( .A0(N38), .A1(n282), .B0(n213), .B1(n241), .Y(O2_D_3_) );
OAI22X1 U222 ( .A0(N38), .A1(n267), .B0(n214), .B1(n241), .Y(O2_D_2_) );
OAI22X1 U223 ( .A0(N38), .A1(n243), .B0(n215), .B1(n241), .Y(O2_D_1_) );
OAI22X1 U224 ( .A0(N38), .A1(n261), .B0(n216), .B1(n241), .Y(O2_D_0_) );
OAI22X1 U225 ( .A0(n241), .A1(n282), .B0(N38), .B1(n213), .Y(O2_C_3_) );
AOI22X1 U226 ( .A0(n28), .A1(R1_C_3_), .B0(T2_1_3_), .B1(N34), .Y(n213) );
OAI22X1 U227 ( .A0(n241), .A1(n267), .B0(N38), .B1(n214), .Y(O2_C_2_) );
AOI22X1 U228 ( .A0(n28), .A1(R1_C_2_), .B0(T2_1_2_), .B1(N34), .Y(n214) );
OAI22X1 U229 ( .A0(n241), .A1(n243), .B0(N38), .B1(n215), .Y(O2_C_1_) );
AOI22X1 U230 ( .A0(n28), .A1(R1_C_1_), .B0(T2_1_1_), .B1(N34), .Y(n215) );
OAI22X1 U231 ( .A0(n241), .A1(n261), .B0(N38), .B1(n216), .Y(O2_C_0_) );
AOI22X1 U232 ( .A0(n28), .A1(R1_C_0_), .B0(T2_1_0_), .B1(N34), .Y(n216) );
AOI22X1 U233 ( .A0(N34), .A1(R1_C_3_), .B0(n28), .B1(T2_1_3_), .Y(n246) );
AOI22X1 U234 ( .A0(N30), .A1(R1_A_3_), .B0(n27), .B1(R1_B_3_), .Y(n247) );
AOI22X1 U235 ( .A0(N34), .A1(R1_C_2_), .B0(n28), .B1(T2_1_2_), .Y(n249) );
AOI22X1 U236 ( .A0(N30), .A1(R1_A_2_), .B0(n27), .B1(R1_B_2_), .Y(n250) );
AOI22X1 U237 ( .A0(N34), .A1(R1_C_1_), .B0(n28), .B1(T2_1_1_), .Y(n251) );
AOI22X1 U238 ( .A0(N30), .A1(R1_A_1_), .B0(n27), .B1(R1_B_1_), .Y(n252) );
AOI22X1 U239 ( .A0(N34), .A1(R1_C_0_), .B0(n28), .B1(T2_1_0_), .Y(n253) );
AOI22X1 U240 ( .A0(N30), .A1(R1_A_0_), .B0(n27), .B1(R1_B_0_), .Y(n254) );
AOI22X1 U241 ( .A0(R1_B_3_), .A1(N30), .B0(n27), .B1(R1_A_3_), .Y(n255) );
AOI22X1 U242 ( .A0(N30), .A1(R1_B_2_), .B0(n27), .B1(R1_A_2_), .Y(n256) );
AOI22X1 U243 ( .A0(N30), .A1(R1_B_1_), .B0(n27), .B1(R1_A_1_), .Y(n257) );
AOI22X1 U244 ( .A0(N30), .A1(R1_B_0_), .B0(n27), .B1(R1_A_0_), .Y(n258) );
OAI22X1 U245 ( .A0(N26), .A1(n202), .B0(n217), .B1(n260), .Y(O1_D_3_) );
OAI22X1 U246 ( .A0(N26), .A1(n181), .B0(n218), .B1(n260), .Y(O1_D_2_) );
OAI22X1 U247 ( .A0(N26), .A1(n262), .B0(n219), .B1(n260), .Y(O1_D_1_) );
OAI22X1 U248 ( .A0(N26), .A1(n158), .B0(n220), .B1(n260), .Y(O1_D_0_) );
OAI22X1 U249 ( .A0(n260), .A1(n202), .B0(N26), .B1(n217), .Y(O1_C_3_) );
AOI22X1 U250 ( .A0(n26), .A1(Creg_3_), .B0(T1_1_3_), .B1(N22), .Y(n217) );
OAI22X1 U251 ( .A0(n260), .A1(n181), .B0(N26), .B1(n218), .Y(O1_C_2_) );
AOI22X1 U252 ( .A0(n26), .A1(Creg_2_), .B0(T1_1_2_), .B1(N22), .Y(n218) );
OAI22X1 U253 ( .A0(n260), .A1(n262), .B0(N26), .B1(n219), .Y(O1_C_1_) );
AOI22X1 U254 ( .A0(n26), .A1(Creg_1_), .B0(T1_1_1_), .B1(N22), .Y(n219) );
OAI22X1 U255 ( .A0(n260), .A1(n158), .B0(N26), .B1(n220), .Y(O1_C_0_) );
AOI22X1 U256 ( .A0(n26), .A1(Creg_0_), .B0(T1_1_0_), .B1(N22), .Y(n220) );
AOI22X1 U257 ( .A0(N22), .A1(Creg_3_), .B0(n26), .B1(T1_1_3_), .Y(n265) );
AOI22X1 U258 ( .A0(n25), .A1(Breg_3_), .B0(Areg_3_), .B1(N18), .Y(n266) );
AOI22X1 U259 ( .A0(N22), .A1(Creg_2_), .B0(n26), .B1(T1_1_2_), .Y(n268) );
AOI22X1 U260 ( .A0(n25), .A1(Breg_2_), .B0(N18), .B1(Areg_2_), .Y(n269) );
AOI22X1 U261 ( .A0(N22), .A1(Creg_1_), .B0(n26), .B1(T1_1_1_), .Y(n270) );
AOI22X1 U262 ( .A0(n25), .A1(Breg_1_), .B0(N18), .B1(Areg_1_), .Y(n271) );
AOI22X1 U263 ( .A0(N22), .A1(Creg_0_), .B0(n26), .B1(T1_1_0_), .Y(n272) );
AOI22X1 U264 ( .A0(n25), .A1(Breg_0_), .B0(N18), .B1(Areg_0_), .Y(n273) );
AOI22X1 U265 ( .A0(N18), .A1(Breg_3_), .B0(n25), .B1(Areg_3_), .Y(n274) );
AOI22X1 U266 ( .A0(N18), .A1(Breg_2_), .B0(n25), .B1(Areg_2_), .Y(n275) );
AOI22X1 U267 ( .A0(N18), .A1(Breg_1_), .B0(n25), .B1(Areg_1_), .Y(n276) );
AOI22X1 U268 ( .A0(N18), .A1(Breg_0_), .B0(n25), .B1(Areg_0_), .Y(n277) );
INVX8 U4 ( .A(N18), .Y(n25) );
INVX8 U5 ( .A(N22), .Y(n26) );
INVX8 U6 ( .A(N30), .Y(n27) );
INVX8 U7 ( .A(N34), .Y(n28) );
INVX8 U8 ( .A(N42), .Y(n87) );
INVX8 U9 ( .A(N46), .Y(n93) );
AND2X1 U10 ( .A(Areg_2_), .B(n4), .Y(n108) );
NOR2X1 U11 ( .A(n10), .B(Areg_0_), .Y(n99) );
AND2X1 U12 ( .A(n99), .B(n9), .Y(n96) );
OAI22X1 U142 ( .A0(n99), .A1(n9), .B0(Breg_1_), .B1(n96), .Y(n105) );
OAI22X1 U146 ( .A0(n108), .A1(n105), .B0(Areg_2_), .B1(n4), .Y(n114) );
OAI21X1 U150 ( .A0(Breg_3_), .A1(n3), .B0(n114), .Y(n120) );
OAI21X1 U161 ( .A0(Areg_3_), .A1(n13), .B0(n120), .Y(N18) );
AND2X1 U166 ( .A(T1_1_2_), .B(n19), .Y(n143) );
NOR2X1 U176 ( .A(n22), .B(T1_1_0_), .Y(n137) );
AND2X1 U181 ( .A(n137), .B(n271), .Y(n131) );
OAI22X1 U191 ( .A0(n137), .A1(n271), .B0(Creg_1_), .B1(n131), .Y(n140) );
OAI22X1 U196 ( .A0(n143), .A1(n140), .B0(T1_1_2_), .B1(n19), .Y(n149) );
OAI21X1 U269 ( .A0(Creg_3_), .A1(n266), .B0(n149), .Y(n152) );
OAI21X1 U270 ( .A0(T1_1_3_), .A1(n14), .B0(n152), .Y(N22) );
AND2X1 U271 ( .A(T1_2_2_), .B(n181), .Y(n187) );
NOR2X1 U272 ( .A(n158), .B(T1_2_0_), .Y(n175) );
AND2X1 U273 ( .A(n175), .B(n219), .Y(n164) );
OAI22X1 U274 ( .A0(n175), .A1(n219), .B0(Dreg_1_), .B1(n164), .Y(n184) );
OAI22X1 U275 ( .A0(n187), .A1(n184), .B0(T1_2_2_), .B1(n181), .Y(n193) );
OAI21X1 U276 ( .A0(Dreg_3_), .A1(n217), .B0(n193), .Y(n196) );
OAI21X1 U277 ( .A0(T1_2_3_), .A1(n202), .B0(n196), .Y(N26) );
AND2X1 U278 ( .A(R1_A_2_), .B(n7), .Y(n225) );
NOR2X1 U279 ( .A(n11), .B(R1_A_0_), .Y(n221) );
AND2X1 U280 ( .A(n221), .B(n5), .Y(n208) );
OAI22X1 U281 ( .A0(n221), .A1(n5), .B0(R1_B_1_), .B1(n208), .Y(n223) );
OAI22X1 U282 ( .A0(n225), .A1(n223), .B0(R1_A_2_), .B1(n7), .Y(n226) );
OAI21X1 U283 ( .A0(R1_B_3_), .A1(n1), .B0(n226), .Y(n229) );
OAI21X1 U284 ( .A0(R1_A_3_), .A1(n17), .B0(n229), .Y(N30) );
AND2X1 U285 ( .A(T2_1_2_), .B(n20), .Y(n245) );
NOR2X1 U286 ( .A(n23), .B(T2_1_0_), .Y(n242) );
AND2X1 U287 ( .A(n242), .B(n252), .Y(n240) );
OAI22X1 U288 ( .A0(n242), .A1(n252), .B0(R1_C_1_), .B1(n240), .Y(n244) );
OAI22X1 U289 ( .A0(n245), .A1(n244), .B0(T2_1_2_), .B1(n20), .Y(n248) );
OAI21X1 U290 ( .A0(R1_C_3_), .A1(n247), .B0(n248), .Y(n259) );
OAI21X1 U291 ( .A0(T2_1_3_), .A1(n15), .B0(n259), .Y(N34) );
AND2X1 U292 ( .A(T2_2_2_), .B(n267), .Y(n279) );
NOR2X1 U293 ( .A(n261), .B(T2_2_0_), .Y(n264) );
AND2X1 U294 ( .A(n264), .B(n215), .Y(n263) );
OAI22X1 U295 ( .A0(n264), .A1(n215), .B0(R1_D_1_), .B1(n263), .Y(n278) );
OAI22X1 U296 ( .A0(n279), .A1(n278), .B0(T2_2_2_), .B1(n267), .Y(n280) );
OAI21X1 U297 ( .A0(R1_D_3_), .A1(n213), .B0(n280), .Y(n281) );
OAI21X1 U298 ( .A0(T2_2_3_), .A1(n282), .B0(n281), .Y(N38) );
AND2X1 U299 ( .A(R2_A_2_), .B(n8), .Y(n286) );
NOR2X1 U300 ( .A(n12), .B(R2_A_0_), .Y(n284) );
AND2X1 U301 ( .A(n284), .B(n6), .Y(n283) );
OAI22X1 U302 ( .A0(n284), .A1(n6), .B0(R2_B_1_), .B1(n283), .Y(n285) );
OAI22X1 U303 ( .A0(n286), .A1(n285), .B0(R2_A_2_), .B1(n8), .Y(n287) );
OAI21X1 U304 ( .A0(R2_B_3_), .A1(n2), .B0(n287), .Y(n288) );
OAI21X1 U305 ( .A0(R2_A_3_), .A1(n18), .B0(n288), .Y(N42) );
AND2X1 U306 ( .A(T3_1_2_), .B(n21), .Y(n292) );
NOR2X1 U307 ( .A(n24), .B(T3_1_0_), .Y(n290) );
AND2X1 U308 ( .A(n290), .B(n233), .Y(n289) );
OAI22X1 U309 ( .A0(n290), .A1(n233), .B0(R2_C_1_), .B1(n289), .Y(n291) );
OAI22X1 U310 ( .A0(n292), .A1(n291), .B0(T3_1_2_), .B1(n21), .Y(n293) );
OAI21X1 U311 ( .A0(R2_C_3_), .A1(n228), .B0(n293), .Y(n294) );
OAI21X1 U312 ( .A0(T3_1_3_), .A1(n16), .B0(n294), .Y(N46) );
AND2X1 U313 ( .A(T3_2_2_), .B(n298), .Y(n300) );
NOR2X1 U314 ( .A(n295), .B(T3_2_0_), .Y(n297) );
AND2X1 U315 ( .A(n297), .B(n211), .Y(n296) );
OAI22X1 U316 ( .A0(n297), .A1(n211), .B0(R2_D_1_), .B1(n296), .Y(n299) );
OAI22X1 U317 ( .A0(n300), .A1(n299), .B0(T3_2_2_), .B1(n298), .Y(n301) );
OAI21X1 U318 ( .A0(R2_D_3_), .A1(n209), .B0(n301), .Y(n302) );
OAI21X1 U319 ( .A0(T3_2_3_), .A1(n303), .B0(n302), .Y(N50) );
endmodule | module sorter ( Clk, A_3_, A_2_, A_1_, A_0_, B_3_, B_2_, B_1_, B_0_, C_3_,
C_2_, C_1_, C_0_, D_3_, D_2_, D_1_, D_0_, S1reg_3_, S1reg_2_, S1reg_1_,
S1reg_0_, S2reg_3_, S2reg_2_, S2reg_1_, S2reg_0_, S3reg_3_, S3reg_2_,
S3reg_1_, S3reg_0_, S4reg_3_, S4reg_2_, S4reg_1_, S4reg_0_ ); |
input Clk, A_3_, A_2_, A_1_, A_0_, B_3_, B_2_, B_1_, B_0_, C_3_, C_2_, C_1_,
C_0_, D_3_, D_2_, D_1_, D_0_;
output S1reg_3_, S1reg_2_, S1reg_1_, S1reg_0_, S2reg_3_, S2reg_2_, S2reg_1_,
S2reg_0_, S3reg_3_, S3reg_2_, S3reg_1_, S3reg_0_, S4reg_3_, S4reg_2_,
S4reg_1_, S4reg_0_;
wire Areg_3_, Areg_2_, Areg_1_, Areg_0_, Breg_3_, Breg_2_, Breg_1_,
Breg_0_, Creg_3_, Creg_2_, Creg_1_, Creg_0_, Dreg_3_, Dreg_1_,
R1_A_3_, R1_A_2_, R1_A_1_, R1_A_0_, O1_A_3_, O1_A_2_, O1_A_1_,
O1_A_0_, R1_B_3_, R1_B_2_, R1_B_1_, R1_B_0_, O1_B_3_, O1_B_2_,
O1_B_1_, O1_B_0_, R1_C_3_, R1_C_2_, R1_C_1_, R1_C_0_, O1_C_3_,
O1_C_2_, O1_C_1_, O1_C_0_, R1_D_3_, R1_D_1_, O1_D_3_, O1_D_2_,
O1_D_1_, O1_D_0_, R2_A_3_, R2_A_2_, R2_A_1_, R2_A_0_, O2_A_3_,
O2_A_2_, O2_A_1_, O2_A_0_, R2_B_3_, R2_B_2_, R2_B_1_, R2_B_0_,
O2_B_3_, O2_B_2_, O2_B_1_, O2_B_0_, R2_C_3_, R2_C_2_, R2_C_1_,
R2_C_0_, O2_C_3_, O2_C_2_, O2_C_1_, O2_C_0_, R2_D_3_, R2_D_1_,
O2_D_3_, O2_D_2_, O2_D_1_, O2_D_0_, S1_3_, S1_2_, S1_1_, S1_0_, S2_3_,
S2_2_, S2_1_, S2_0_, S3_3_, S3_2_, S3_1_, S3_0_, S4_3_, S4_2_, S4_1_,
S4_0_, N18, T1_1_3_, T1_1_2_, T1_1_1_, T1_1_0_, N22, T1_2_3_, T1_2_2_,
T1_2_0_, N26, N30, T2_1_3_, T2_1_2_, T2_1_1_, T2_1_0_, N34, T2_2_3_,
T2_2_2_, T2_2_0_, N38, N42, T3_1_3_, T3_1_2_, T3_1_1_, T3_1_0_, N46,
T3_2_3_, T3_2_2_, T3_2_0_, N50, n209, n210, n211, n212, n213, n214,
n215, n216, n217, n218, n219, n220, n222, n224, n227, n228, n230,
n231, n232, n233, n234, n235, n236, n237, n238, n239, n241, n243,
n246, n247, n249, n250, n251, n252, n253, n254, n255, n256, n257,
n258, n260, n262, n265, n266, n268, n269, n270, n271, n272, n273,
n274, n275, n276, n277, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11,
n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25,
n26, n27, n28, n87, n93, n96, n99, n105, n108, n114, n120, n131, n137,
n140, n143, n149, n152, n158, n164, n175, n181, n184, n187, n193,
n196, n202, n208, n221, n223, n225, n226, n229, n240, n242, n244,
n245, n248, n259, n261, n263, n264, n267, n278, n279, n280, n281,
n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, n292,
n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303;
SDFFSRX1 Areg_reg_3_ ( .D(A_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Areg_3_), .QN(n3) );
SDFFSRX1 Areg_reg_2_ ( .D(A_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Areg_2_) );
SDFFSRX1 Areg_reg_1_ ( .D(A_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Areg_1_), .QN(n9) );
SDFFSRX1 Areg_reg_0_ ( .D(A_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Areg_0_) );
SDFFSRX1 Breg_reg_3_ ( .D(B_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Breg_3_), .QN(n13) );
SDFFSRX1 Breg_reg_2_ ( .D(B_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Breg_2_), .QN(n4) );
SDFFSRX1 Breg_reg_1_ ( .D(B_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Breg_1_) );
SDFFSRX1 Breg_reg_0_ ( .D(B_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Breg_0_), .QN(n10) );
SDFFSRX1 Creg_reg_3_ ( .D(C_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Creg_3_), .QN(n14) );
SDFFSRX1 Creg_reg_2_ ( .D(C_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Creg_2_), .QN(n19) );
SDFFSRX1 Creg_reg_1_ ( .D(C_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Creg_1_) );
SDFFSRX1 Creg_reg_0_ ( .D(C_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Creg_0_), .QN(n22) );
SDFFSRX1 Dreg_reg_3_ ( .D(D_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Dreg_3_), .QN(n202) );
SDFFSRX1 Dreg_reg_2_ ( .D(D_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .QN(n181) );
SDFFSRX1 Dreg_reg_1_ ( .D(D_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(Dreg_1_), .QN(n262) );
SDFFSRX1 Dreg_reg_0_ ( .D(D_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .QN(n158) );
SDFFSRX1 R1_A_reg_3_ ( .D(O1_A_3_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_A_3_), .QN(n1) );
SDFFSRX1 R1_A_reg_2_ ( .D(O1_A_2_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_A_2_) );
SDFFSRX1 R1_A_reg_1_ ( .D(O1_A_1_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_A_1_), .QN(n5) );
SDFFSRX1 R1_A_reg_0_ ( .D(O1_A_0_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_A_0_) );
SDFFSRX1 R1_B_reg_3_ ( .D(O1_B_3_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_B_3_), .QN(n17) );
SDFFSRX1 R1_B_reg_2_ ( .D(O1_B_2_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_B_2_), .QN(n7) );
SDFFSRX1 R1_B_reg_1_ ( .D(O1_B_1_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_B_1_) );
SDFFSRX1 R1_B_reg_0_ ( .D(O1_B_0_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_B_0_), .QN(n11) );
SDFFSRX1 R1_C_reg_3_ ( .D(O1_C_3_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_C_3_), .QN(n15) );
SDFFSRX1 R1_C_reg_2_ ( .D(O1_C_2_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_C_2_), .QN(n20) );
SDFFSRX1 R1_C_reg_1_ ( .D(O1_C_1_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_C_1_) );
SDFFSRX1 R1_C_reg_0_ ( .D(O1_C_0_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_C_0_), .QN(n23) );
SDFFSRX1 R1_D_reg_3_ ( .D(O1_D_3_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_D_3_), .QN(n282) );
SDFFSRX1 R1_D_reg_2_ ( .D(O1_D_2_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .QN(n267) );
SDFFSRX1 R1_D_reg_1_ ( .D(O1_D_1_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R1_D_1_), .QN(n243) );
SDFFSRX1 R1_D_reg_0_ ( .D(O1_D_0_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .QN(n261) );
SDFFSRX1 R2_A_reg_3_ ( .D(O2_A_3_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_A_3_), .QN(n2) );
SDFFSRX1 R2_A_reg_2_ ( .D(O2_A_2_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_A_2_) );
SDFFSRX1 R2_A_reg_1_ ( .D(O2_A_1_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_A_1_), .QN(n6) );
SDFFSRX1 R2_A_reg_0_ ( .D(O2_A_0_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_A_0_) );
SDFFSRX1 R2_B_reg_3_ ( .D(O2_B_3_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_B_3_), .QN(n18) );
SDFFSRX1 R2_B_reg_2_ ( .D(O2_B_2_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_B_2_), .QN(n8) );
SDFFSRX1 R2_B_reg_1_ ( .D(O2_B_1_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_B_1_) );
SDFFSRX1 R2_B_reg_0_ ( .D(O2_B_0_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_B_0_), .QN(n12) );
SDFFSRX1 R2_C_reg_3_ ( .D(O2_C_3_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_C_3_), .QN(n16) );
SDFFSRX1 R2_C_reg_2_ ( .D(O2_C_2_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_C_2_), .QN(n21) );
SDFFSRX1 R2_C_reg_1_ ( .D(O2_C_1_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_C_1_) );
SDFFSRX1 R2_C_reg_0_ ( .D(O2_C_0_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_C_0_), .QN(n24) );
SDFFSRX1 R2_D_reg_3_ ( .D(O2_D_3_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_D_3_), .QN(n303) );
SDFFSRX1 R2_D_reg_2_ ( .D(O2_D_2_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .QN(n298) );
SDFFSRX1 R2_D_reg_1_ ( .D(O2_D_1_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .Q(R2_D_1_), .QN(n224) );
SDFFSRX1 R2_D_reg_0_ ( .D(O2_D_0_), .SI(1'b0), .SE(1'b0), .CK(Clk),
.SN(1'b1), .RN(1'b1), .QN(n295) );
SDFFSRX1 S1reg_reg_3_ ( .D(S1_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S1reg_3_) );
SDFFSRX1 S1reg_reg_2_ ( .D(S1_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S1reg_2_) );
SDFFSRX1 S1reg_reg_1_ ( .D(S1_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S1reg_1_) );
SDFFSRX1 S1reg_reg_0_ ( .D(S1_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S1reg_0_) );
SDFFSRX1 S2reg_reg_3_ ( .D(S2_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S2reg_3_) );
SDFFSRX1 S2reg_reg_2_ ( .D(S2_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S2reg_2_) );
SDFFSRX1 S2reg_reg_1_ ( .D(S2_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S2reg_1_) );
SDFFSRX1 S2reg_reg_0_ ( .D(S2_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S2reg_0_) );
SDFFSRX1 S3reg_reg_3_ ( .D(S3_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S3reg_3_) );
SDFFSRX1 S3reg_reg_2_ ( .D(S3_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S3reg_2_) );
SDFFSRX1 S3reg_reg_1_ ( .D(S3_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S3reg_1_) );
SDFFSRX1 S3reg_reg_0_ ( .D(S3_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S3reg_0_) );
SDFFSRX1 S4reg_reg_3_ ( .D(S4_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S4reg_3_) );
SDFFSRX1 S4reg_reg_2_ ( .D(S4_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S4reg_2_) );
SDFFSRX1 S4reg_reg_1_ ( .D(S4_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S4reg_1_) );
SDFFSRX1 S4reg_reg_0_ ( .D(S4_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1),
.RN(1'b1), .Q(S4reg_0_) );
INVX8 U140 ( .A(n209), .Y(T3_2_3_) );
INVX8 U141 ( .A(n210), .Y(T3_2_2_) );
INVX8 U143 ( .A(n212), .Y(T3_2_0_) );
INVX8 U144 ( .A(n213), .Y(T2_2_3_) );
INVX8 U145 ( .A(n214), .Y(T2_2_2_) );
INVX8 U147 ( .A(n216), .Y(T2_2_0_) );
INVX8 U148 ( .A(n217), .Y(T1_2_3_) );
INVX8 U149 ( .A(n218), .Y(T1_2_2_) );
INVX8 U151 ( .A(n220), .Y(T1_2_0_) );
INVX8 U152 ( .A(N50), .Y(n222) );
INVX8 U153 ( .A(n227), .Y(S2_3_) );
INVX8 U154 ( .A(n228), .Y(T3_1_3_) );
INVX8 U155 ( .A(n230), .Y(S2_2_) );
INVX8 U156 ( .A(n231), .Y(T3_1_2_) );
INVX8 U157 ( .A(n232), .Y(S2_1_) );
INVX8 U158 ( .A(n233), .Y(T3_1_1_) );
INVX8 U159 ( .A(n234), .Y(S2_0_) );
INVX8 U160 ( .A(n235), .Y(T3_1_0_) );
INVX8 U162 ( .A(n236), .Y(S1_3_) );
INVX8 U163 ( .A(n237), .Y(S1_2_) );
INVX8 U164 ( .A(n238), .Y(S1_1_) );
INVX8 U165 ( .A(n239), .Y(S1_0_) );
INVX8 U167 ( .A(N38), .Y(n241) );
INVX8 U168 ( .A(n246), .Y(O2_B_3_) );
INVX8 U169 ( .A(n247), .Y(T2_1_3_) );
INVX8 U170 ( .A(n249), .Y(O2_B_2_) );
INVX8 U171 ( .A(n250), .Y(T2_1_2_) );
INVX8 U172 ( .A(n251), .Y(O2_B_1_) );
INVX8 U173 ( .A(n252), .Y(T2_1_1_) );
INVX8 U174 ( .A(n253), .Y(O2_B_0_) );
INVX8 U175 ( .A(n254), .Y(T2_1_0_) );
INVX8 U177 ( .A(n255), .Y(O2_A_3_) );
INVX8 U178 ( .A(n256), .Y(O2_A_2_) );
INVX8 U179 ( .A(n257), .Y(O2_A_1_) );
INVX8 U180 ( .A(n258), .Y(O2_A_0_) );
INVX8 U182 ( .A(N26), .Y(n260) );
INVX8 U183 ( .A(n265), .Y(O1_B_3_) );
INVX8 U184 ( .A(n266), .Y(T1_1_3_) );
INVX8 U185 ( .A(n268), .Y(O1_B_2_) );
INVX8 U186 ( .A(n269), .Y(T1_1_2_) );
INVX8 U187 ( .A(n270), .Y(O1_B_1_) );
INVX8 U188 ( .A(n271), .Y(T1_1_1_) );
INVX8 U189 ( .A(n272), .Y(O1_B_0_) );
INVX8 U190 ( .A(n273), .Y(T1_1_0_) );
INVX8 U192 ( .A(n274), .Y(O1_A_3_) );
INVX8 U193 ( .A(n275), .Y(O1_A_2_) );
INVX8 U194 ( .A(n276), .Y(O1_A_1_) );
INVX8 U195 ( .A(n277), .Y(O1_A_0_) );
OAI22X1 U197 ( .A0(N50), .A1(n303), .B0(n209), .B1(n222), .Y(S4_3_) );
OAI22X1 U198 ( .A0(N50), .A1(n298), .B0(n210), .B1(n222), .Y(S4_2_) );
OAI22X1 U199 ( .A0(N50), .A1(n224), .B0(n211), .B1(n222), .Y(S4_1_) );
OAI22X1 U200 ( .A0(N50), .A1(n295), .B0(n212), .B1(n222), .Y(S4_0_) );
OAI22X1 U201 ( .A0(n222), .A1(n303), .B0(N50), .B1(n209), .Y(S3_3_) );
AOI22X1 U202 ( .A0(n93), .A1(R2_C_3_), .B0(T3_1_3_), .B1(N46), .Y(n209) );
OAI22X1 U203 ( .A0(n222), .A1(n298), .B0(N50), .B1(n210), .Y(S3_2_) );
AOI22X1 U204 ( .A0(n93), .A1(R2_C_2_), .B0(T3_1_2_), .B1(N46), .Y(n210) );
OAI22X1 U205 ( .A0(n222), .A1(n224), .B0(N50), .B1(n211), .Y(S3_1_) );
AOI22X1 U206 ( .A0(n93), .A1(R2_C_1_), .B0(T3_1_1_), .B1(N46), .Y(n211) );
OAI22X1 U207 ( .A0(n222), .A1(n295), .B0(N50), .B1(n212), .Y(S3_0_) );
AOI22X1 U208 ( .A0(n93), .A1(R2_C_0_), .B0(T3_1_0_), .B1(N46), .Y(n212) );
AOI22X1 U209 ( .A0(N46), .A1(R2_C_3_), .B0(n93), .B1(T3_1_3_), .Y(n227) );
AOI22X1 U210 ( .A0(N42), .A1(R2_A_3_), .B0(n87), .B1(R2_B_3_), .Y(n228) );
AOI22X1 U211 ( .A0(N46), .A1(R2_C_2_), .B0(n93), .B1(T3_1_2_), .Y(n230) );
AOI22X1 U212 ( .A0(N42), .A1(R2_A_2_), .B0(n87), .B1(R2_B_2_), .Y(n231) );
AOI22X1 U213 ( .A0(N46), .A1(R2_C_1_), .B0(n93), .B1(T3_1_1_), .Y(n232) );
AOI22X1 U214 ( .A0(N42), .A1(R2_A_1_), .B0(n87), .B1(R2_B_1_), .Y(n233) );
AOI22X1 U215 ( .A0(N46), .A1(R2_C_0_), .B0(n93), .B1(T3_1_0_), .Y(n234) );
AOI22X1 U216 ( .A0(N42), .A1(R2_A_0_), .B0(n87), .B1(R2_B_0_), .Y(n235) );
AOI22X1 U217 ( .A0(R2_B_3_), .A1(N42), .B0(n87), .B1(R2_A_3_), .Y(n236) );
AOI22X1 U218 ( .A0(N42), .A1(R2_B_2_), .B0(n87), .B1(R2_A_2_), .Y(n237) );
AOI22X1 U219 ( .A0(N42), .A1(R2_B_1_), .B0(n87), .B1(R2_A_1_), .Y(n238) );
AOI22X1 U220 ( .A0(N42), .A1(R2_B_0_), .B0(n87), .B1(R2_A_0_), .Y(n239) );
OAI22X1 U221 ( .A0(N38), .A1(n282), .B0(n213), .B1(n241), .Y(O2_D_3_) );
OAI22X1 U222 ( .A0(N38), .A1(n267), .B0(n214), .B1(n241), .Y(O2_D_2_) );
OAI22X1 U223 ( .A0(N38), .A1(n243), .B0(n215), .B1(n241), .Y(O2_D_1_) );
OAI22X1 U224 ( .A0(N38), .A1(n261), .B0(n216), .B1(n241), .Y(O2_D_0_) );
OAI22X1 U225 ( .A0(n241), .A1(n282), .B0(N38), .B1(n213), .Y(O2_C_3_) );
AOI22X1 U226 ( .A0(n28), .A1(R1_C_3_), .B0(T2_1_3_), .B1(N34), .Y(n213) );
OAI22X1 U227 ( .A0(n241), .A1(n267), .B0(N38), .B1(n214), .Y(O2_C_2_) );
AOI22X1 U228 ( .A0(n28), .A1(R1_C_2_), .B0(T2_1_2_), .B1(N34), .Y(n214) );
OAI22X1 U229 ( .A0(n241), .A1(n243), .B0(N38), .B1(n215), .Y(O2_C_1_) );
AOI22X1 U230 ( .A0(n28), .A1(R1_C_1_), .B0(T2_1_1_), .B1(N34), .Y(n215) );
OAI22X1 U231 ( .A0(n241), .A1(n261), .B0(N38), .B1(n216), .Y(O2_C_0_) );
AOI22X1 U232 ( .A0(n28), .A1(R1_C_0_), .B0(T2_1_0_), .B1(N34), .Y(n216) );
AOI22X1 U233 ( .A0(N34), .A1(R1_C_3_), .B0(n28), .B1(T2_1_3_), .Y(n246) );
AOI22X1 U234 ( .A0(N30), .A1(R1_A_3_), .B0(n27), .B1(R1_B_3_), .Y(n247) );
AOI22X1 U235 ( .A0(N34), .A1(R1_C_2_), .B0(n28), .B1(T2_1_2_), .Y(n249) );
AOI22X1 U236 ( .A0(N30), .A1(R1_A_2_), .B0(n27), .B1(R1_B_2_), .Y(n250) );
AOI22X1 U237 ( .A0(N34), .A1(R1_C_1_), .B0(n28), .B1(T2_1_1_), .Y(n251) );
AOI22X1 U238 ( .A0(N30), .A1(R1_A_1_), .B0(n27), .B1(R1_B_1_), .Y(n252) );
AOI22X1 U239 ( .A0(N34), .A1(R1_C_0_), .B0(n28), .B1(T2_1_0_), .Y(n253) );
AOI22X1 U240 ( .A0(N30), .A1(R1_A_0_), .B0(n27), .B1(R1_B_0_), .Y(n254) );
AOI22X1 U241 ( .A0(R1_B_3_), .A1(N30), .B0(n27), .B1(R1_A_3_), .Y(n255) );
AOI22X1 U242 ( .A0(N30), .A1(R1_B_2_), .B0(n27), .B1(R1_A_2_), .Y(n256) );
AOI22X1 U243 ( .A0(N30), .A1(R1_B_1_), .B0(n27), .B1(R1_A_1_), .Y(n257) );
AOI22X1 U244 ( .A0(N30), .A1(R1_B_0_), .B0(n27), .B1(R1_A_0_), .Y(n258) );
OAI22X1 U245 ( .A0(N26), .A1(n202), .B0(n217), .B1(n260), .Y(O1_D_3_) );
OAI22X1 U246 ( .A0(N26), .A1(n181), .B0(n218), .B1(n260), .Y(O1_D_2_) );
OAI22X1 U247 ( .A0(N26), .A1(n262), .B0(n219), .B1(n260), .Y(O1_D_1_) );
OAI22X1 U248 ( .A0(N26), .A1(n158), .B0(n220), .B1(n260), .Y(O1_D_0_) );
OAI22X1 U249 ( .A0(n260), .A1(n202), .B0(N26), .B1(n217), .Y(O1_C_3_) );
AOI22X1 U250 ( .A0(n26), .A1(Creg_3_), .B0(T1_1_3_), .B1(N22), .Y(n217) );
OAI22X1 U251 ( .A0(n260), .A1(n181), .B0(N26), .B1(n218), .Y(O1_C_2_) );
AOI22X1 U252 ( .A0(n26), .A1(Creg_2_), .B0(T1_1_2_), .B1(N22), .Y(n218) );
OAI22X1 U253 ( .A0(n260), .A1(n262), .B0(N26), .B1(n219), .Y(O1_C_1_) );
AOI22X1 U254 ( .A0(n26), .A1(Creg_1_), .B0(T1_1_1_), .B1(N22), .Y(n219) );
OAI22X1 U255 ( .A0(n260), .A1(n158), .B0(N26), .B1(n220), .Y(O1_C_0_) );
AOI22X1 U256 ( .A0(n26), .A1(Creg_0_), .B0(T1_1_0_), .B1(N22), .Y(n220) );
AOI22X1 U257 ( .A0(N22), .A1(Creg_3_), .B0(n26), .B1(T1_1_3_), .Y(n265) );
AOI22X1 U258 ( .A0(n25), .A1(Breg_3_), .B0(Areg_3_), .B1(N18), .Y(n266) );
AOI22X1 U259 ( .A0(N22), .A1(Creg_2_), .B0(n26), .B1(T1_1_2_), .Y(n268) );
AOI22X1 U260 ( .A0(n25), .A1(Breg_2_), .B0(N18), .B1(Areg_2_), .Y(n269) );
AOI22X1 U261 ( .A0(N22), .A1(Creg_1_), .B0(n26), .B1(T1_1_1_), .Y(n270) );
AOI22X1 U262 ( .A0(n25), .A1(Breg_1_), .B0(N18), .B1(Areg_1_), .Y(n271) );
AOI22X1 U263 ( .A0(N22), .A1(Creg_0_), .B0(n26), .B1(T1_1_0_), .Y(n272) );
AOI22X1 U264 ( .A0(n25), .A1(Breg_0_), .B0(N18), .B1(Areg_0_), .Y(n273) );
AOI22X1 U265 ( .A0(N18), .A1(Breg_3_), .B0(n25), .B1(Areg_3_), .Y(n274) );
AOI22X1 U266 ( .A0(N18), .A1(Breg_2_), .B0(n25), .B1(Areg_2_), .Y(n275) );
AOI22X1 U267 ( .A0(N18), .A1(Breg_1_), .B0(n25), .B1(Areg_1_), .Y(n276) );
AOI22X1 U268 ( .A0(N18), .A1(Breg_0_), .B0(n25), .B1(Areg_0_), .Y(n277) );
INVX8 U4 ( .A(N18), .Y(n25) );
INVX8 U5 ( .A(N22), .Y(n26) );
INVX8 U6 ( .A(N30), .Y(n27) );
INVX8 U7 ( .A(N34), .Y(n28) );
INVX8 U8 ( .A(N42), .Y(n87) );
INVX8 U9 ( .A(N46), .Y(n93) );
AND2X1 U10 ( .A(Areg_2_), .B(n4), .Y(n108) );
NOR2X1 U11 ( .A(n10), .B(Areg_0_), .Y(n99) );
AND2X1 U12 ( .A(n99), .B(n9), .Y(n96) );
OAI22X1 U142 ( .A0(n99), .A1(n9), .B0(Breg_1_), .B1(n96), .Y(n105) );
OAI22X1 U146 ( .A0(n108), .A1(n105), .B0(Areg_2_), .B1(n4), .Y(n114) );
OAI21X1 U150 ( .A0(Breg_3_), .A1(n3), .B0(n114), .Y(n120) );
OAI21X1 U161 ( .A0(Areg_3_), .A1(n13), .B0(n120), .Y(N18) );
AND2X1 U166 ( .A(T1_1_2_), .B(n19), .Y(n143) );
NOR2X1 U176 ( .A(n22), .B(T1_1_0_), .Y(n137) );
AND2X1 U181 ( .A(n137), .B(n271), .Y(n131) );
OAI22X1 U191 ( .A0(n137), .A1(n271), .B0(Creg_1_), .B1(n131), .Y(n140) );
OAI22X1 U196 ( .A0(n143), .A1(n140), .B0(T1_1_2_), .B1(n19), .Y(n149) );
OAI21X1 U269 ( .A0(Creg_3_), .A1(n266), .B0(n149), .Y(n152) );
OAI21X1 U270 ( .A0(T1_1_3_), .A1(n14), .B0(n152), .Y(N22) );
AND2X1 U271 ( .A(T1_2_2_), .B(n181), .Y(n187) );
NOR2X1 U272 ( .A(n158), .B(T1_2_0_), .Y(n175) );
AND2X1 U273 ( .A(n175), .B(n219), .Y(n164) );
OAI22X1 U274 ( .A0(n175), .A1(n219), .B0(Dreg_1_), .B1(n164), .Y(n184) );
OAI22X1 U275 ( .A0(n187), .A1(n184), .B0(T1_2_2_), .B1(n181), .Y(n193) );
OAI21X1 U276 ( .A0(Dreg_3_), .A1(n217), .B0(n193), .Y(n196) );
OAI21X1 U277 ( .A0(T1_2_3_), .A1(n202), .B0(n196), .Y(N26) );
AND2X1 U278 ( .A(R1_A_2_), .B(n7), .Y(n225) );
NOR2X1 U279 ( .A(n11), .B(R1_A_0_), .Y(n221) );
AND2X1 U280 ( .A(n221), .B(n5), .Y(n208) );
OAI22X1 U281 ( .A0(n221), .A1(n5), .B0(R1_B_1_), .B1(n208), .Y(n223) );
OAI22X1 U282 ( .A0(n225), .A1(n223), .B0(R1_A_2_), .B1(n7), .Y(n226) );
OAI21X1 U283 ( .A0(R1_B_3_), .A1(n1), .B0(n226), .Y(n229) );
OAI21X1 U284 ( .A0(R1_A_3_), .A1(n17), .B0(n229), .Y(N30) );
AND2X1 U285 ( .A(T2_1_2_), .B(n20), .Y(n245) );
NOR2X1 U286 ( .A(n23), .B(T2_1_0_), .Y(n242) );
AND2X1 U287 ( .A(n242), .B(n252), .Y(n240) );
OAI22X1 U288 ( .A0(n242), .A1(n252), .B0(R1_C_1_), .B1(n240), .Y(n244) );
OAI22X1 U289 ( .A0(n245), .A1(n244), .B0(T2_1_2_), .B1(n20), .Y(n248) );
OAI21X1 U290 ( .A0(R1_C_3_), .A1(n247), .B0(n248), .Y(n259) );
OAI21X1 U291 ( .A0(T2_1_3_), .A1(n15), .B0(n259), .Y(N34) );
AND2X1 U292 ( .A(T2_2_2_), .B(n267), .Y(n279) );
NOR2X1 U293 ( .A(n261), .B(T2_2_0_), .Y(n264) );
AND2X1 U294 ( .A(n264), .B(n215), .Y(n263) );
OAI22X1 U295 ( .A0(n264), .A1(n215), .B0(R1_D_1_), .B1(n263), .Y(n278) );
OAI22X1 U296 ( .A0(n279), .A1(n278), .B0(T2_2_2_), .B1(n267), .Y(n280) );
OAI21X1 U297 ( .A0(R1_D_3_), .A1(n213), .B0(n280), .Y(n281) );
OAI21X1 U298 ( .A0(T2_2_3_), .A1(n282), .B0(n281), .Y(N38) );
AND2X1 U299 ( .A(R2_A_2_), .B(n8), .Y(n286) );
NOR2X1 U300 ( .A(n12), .B(R2_A_0_), .Y(n284) );
AND2X1 U301 ( .A(n284), .B(n6), .Y(n283) );
OAI22X1 U302 ( .A0(n284), .A1(n6), .B0(R2_B_1_), .B1(n283), .Y(n285) );
OAI22X1 U303 ( .A0(n286), .A1(n285), .B0(R2_A_2_), .B1(n8), .Y(n287) );
OAI21X1 U304 ( .A0(R2_B_3_), .A1(n2), .B0(n287), .Y(n288) );
OAI21X1 U305 ( .A0(R2_A_3_), .A1(n18), .B0(n288), .Y(N42) );
AND2X1 U306 ( .A(T3_1_2_), .B(n21), .Y(n292) );
NOR2X1 U307 ( .A(n24), .B(T3_1_0_), .Y(n290) );
AND2X1 U308 ( .A(n290), .B(n233), .Y(n289) );
OAI22X1 U309 ( .A0(n290), .A1(n233), .B0(R2_C_1_), .B1(n289), .Y(n291) );
OAI22X1 U310 ( .A0(n292), .A1(n291), .B0(T3_1_2_), .B1(n21), .Y(n293) );
OAI21X1 U311 ( .A0(R2_C_3_), .A1(n228), .B0(n293), .Y(n294) );
OAI21X1 U312 ( .A0(T3_1_3_), .A1(n16), .B0(n294), .Y(N46) );
AND2X1 U313 ( .A(T3_2_2_), .B(n298), .Y(n300) );
NOR2X1 U314 ( .A(n295), .B(T3_2_0_), .Y(n297) );
AND2X1 U315 ( .A(n297), .B(n211), .Y(n296) );
OAI22X1 U316 ( .A0(n297), .A1(n211), .B0(R2_D_1_), .B1(n296), .Y(n299) );
OAI22X1 U317 ( .A0(n300), .A1(n299), .B0(T3_2_2_), .B1(n298), .Y(n301) );
OAI21X1 U318 ( .A0(R2_D_3_), .A1(n209), .B0(n301), .Y(n302) );
OAI21X1 U319 ( .A0(T3_2_3_), .A1(n303), .B0(n302), .Y(N50) );
endmodule | 0 |
138,585 | data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v | 84,760,667 | sorter_top.v | v | 422 | 81 | [] | [] | [] | [(2, 357), (360, 420)] | null | null | 1: b"%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:40: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Areg_reg_3_ ( .D(A_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/84760667/Synopsis/Synthesized,data/full_repos/permissive/84760667/SDFFSRX1\n data/full_repos/permissive/84760667/Synopsis/Synthesized,data/full_repos/permissive/84760667/SDFFSRX1.v\n data/full_repos/permissive/84760667/Synopsis/Synthesized,data/full_repos/permissive/84760667/SDFFSRX1.sv\n SDFFSRX1\n SDFFSRX1.v\n SDFFSRX1.sv\n obj_dir/SDFFSRX1\n obj_dir/SDFFSRX1.v\n obj_dir/SDFFSRX1.sv\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:42: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Areg_reg_2_ ( .D(A_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:44: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Areg_reg_1_ ( .D(A_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:46: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Areg_reg_0_ ( .D(A_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:48: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Breg_reg_3_ ( .D(B_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:50: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Breg_reg_2_ ( .D(B_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:52: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Breg_reg_1_ ( .D(B_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:54: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Breg_reg_0_ ( .D(B_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:56: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Creg_reg_3_ ( .D(C_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:58: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Creg_reg_2_ ( .D(C_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:60: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Creg_reg_1_ ( .D(C_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:62: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Creg_reg_0_ ( .D(C_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:64: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Dreg_reg_3_ ( .D(D_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:66: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Dreg_reg_2_ ( .D(D_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:68: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Dreg_reg_1_ ( .D(D_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:70: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 Dreg_reg_0_ ( .D(D_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:72: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_A_reg_3_ ( .D(O1_A_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:74: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_A_reg_2_ ( .D(O1_A_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:76: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_A_reg_1_ ( .D(O1_A_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:78: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_A_reg_0_ ( .D(O1_A_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:80: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_B_reg_3_ ( .D(O1_B_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:82: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_B_reg_2_ ( .D(O1_B_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:84: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_B_reg_1_ ( .D(O1_B_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:86: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_B_reg_0_ ( .D(O1_B_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:88: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_C_reg_3_ ( .D(O1_C_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:90: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_C_reg_2_ ( .D(O1_C_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:92: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_C_reg_1_ ( .D(O1_C_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:94: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_C_reg_0_ ( .D(O1_C_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:96: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_D_reg_3_ ( .D(O1_D_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:98: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_D_reg_2_ ( .D(O1_D_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:100: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_D_reg_1_ ( .D(O1_D_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:102: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R1_D_reg_0_ ( .D(O1_D_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:104: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_A_reg_3_ ( .D(O2_A_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:106: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_A_reg_2_ ( .D(O2_A_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:108: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_A_reg_1_ ( .D(O2_A_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:110: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_A_reg_0_ ( .D(O2_A_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:112: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_B_reg_3_ ( .D(O2_B_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:114: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_B_reg_2_ ( .D(O2_B_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:116: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_B_reg_1_ ( .D(O2_B_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:118: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_B_reg_0_ ( .D(O2_B_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:120: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_C_reg_3_ ( .D(O2_C_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:122: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_C_reg_2_ ( .D(O2_C_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:124: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_C_reg_1_ ( .D(O2_C_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:126: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_C_reg_0_ ( .D(O2_C_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:128: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_D_reg_3_ ( .D(O2_D_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:130: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_D_reg_2_ ( .D(O2_D_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:132: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_D_reg_1_ ( .D(O2_D_1_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:134: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 R2_D_reg_0_ ( .D(O2_D_0_), .SI(1'b0), .SE(1'b0), .CK(Clk), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:136: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 S1reg_reg_3_ ( .D(S1_3_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: data/full_repos/permissive/84760667/Synopsis/Synthesized/sorter_top.v:138: Cannot find file containing module: 'SDFFSRX1'\n SDFFSRX1 S1reg_reg_2_ ( .D(S1_2_), .SI(1'b0), .SE(1'b0), .CK(Clk), .SN(1'b1), \n ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n" | 302,560 | module | module sorter_top ( padA_3_, padA_2_, padA_1_, padA_0_, padB_3_, padB_2_,
padB_1_, padB_0_, padC_3_, padC_2_, padC_1_, padC_0_, padD_3_, padD_2_,
padD_1_, padD_0_, padClk, padS1reg_3_, padS1reg_2_, padS1reg_1_,
padS1reg_0_, padS2reg_3_, padS2reg_2_, padS2reg_1_, padS2reg_0_,
padS3reg_3_, padS3reg_2_, padS3reg_1_, padS3reg_0_, padS4reg_3_,
padS4reg_2_, padS4reg_1_, padS4reg_0_ );
input padA_3_, padA_2_, padA_1_, padA_0_, padB_3_, padB_2_, padB_1_, padB_0_,
padC_3_, padC_2_, padC_1_, padC_0_, padD_3_, padD_2_, padD_1_,
padD_0_, padClk;
output padS1reg_3_, padS1reg_2_, padS1reg_1_, padS1reg_0_, padS2reg_3_,
padS2reg_2_, padS2reg_1_, padS2reg_0_, padS3reg_3_, padS3reg_2_,
padS3reg_1_, padS3reg_0_, padS4reg_3_, padS4reg_2_, padS4reg_1_,
padS4reg_0_;
wire A_3_, A_2_, A_1_, A_0_, B_3_, B_2_, B_1_, B_0_, C_3_, C_2_, C_1_,
C_0_, D_3_, D_2_, D_1_, D_0_, S1reg_3_, S1reg_2_, S1reg_1_, S1reg_0_,
S2reg_3_, S2reg_2_, S2reg_1_, S2reg_0_, S3reg_3_, S3reg_2_, S3reg_1_,
S3reg_0_, S4reg_3_, S4reg_2_, S4reg_1_, S4reg_0_, clk;
PDUDGZ inpA_3 ( .PAD(padA_3_), .Y(A_3_) );
PDUDGZ inpA_2 ( .PAD(padA_2_), .Y(A_2_) );
PDUDGZ inpA_1 ( .PAD(padA_1_), .Y(A_1_) );
PDUDGZ inpA_0 ( .PAD(padA_0_), .Y(A_0_) );
PDUDGZ inpB_3 ( .PAD(padB_3_), .Y(B_3_) );
PDUDGZ inpB_2 ( .PAD(padB_2_), .Y(B_2_) );
PDUDGZ inpB_1 ( .PAD(padB_1_), .Y(B_1_) );
PDUDGZ inpB_0 ( .PAD(padB_0_), .Y(B_0_) );
PDUDGZ inpC_3 ( .PAD(padC_3_), .Y(C_3_) );
PDUDGZ inpC_2 ( .PAD(padC_2_), .Y(C_2_) );
PDUDGZ inpC_1 ( .PAD(padC_1_), .Y(C_1_) );
PDUDGZ inpC_0 ( .PAD(padC_0_), .Y(C_0_) );
PDUDGZ inpD_3 ( .PAD(padD_3_), .Y(D_3_) );
PDUDGZ inpD_2 ( .PAD(padD_2_), .Y(D_2_) );
PDUDGZ inpD_1 ( .PAD(padD_1_), .Y(D_1_) );
PDUDGZ inpD_0 ( .PAD(padD_0_), .Y(D_0_) );
PDO12CDG opResS1_3 ( .A(S1reg_3_), .PAD(padS1reg_3_) );
PDO12CDG opResS1_2 ( .A(S1reg_2_), .PAD(padS1reg_2_) );
PDO12CDG opResS1_1 ( .A(S1reg_1_), .PAD(padS1reg_1_) );
PDO12CDG opResS1_0 ( .A(S1reg_0_), .PAD(padS1reg_0_) );
PDO12CDG opResS2_3 ( .A(S2reg_3_), .PAD(padS2reg_3_) );
PDO12CDG opResS2_2 ( .A(S2reg_2_), .PAD(padS2reg_2_) );
PDO12CDG opResS2_1 ( .A(S2reg_1_), .PAD(padS2reg_1_) );
PDO12CDG opResS2_0 ( .A(S2reg_0_), .PAD(padS2reg_0_) );
PDO12CDG opResS3_3 ( .A(S3reg_3_), .PAD(padS3reg_3_) );
PDO12CDG opResS3_2 ( .A(S3reg_2_), .PAD(padS3reg_2_) );
PDO12CDG opResS3_1 ( .A(S3reg_1_), .PAD(padS3reg_1_) );
PDO12CDG opResS3_0 ( .A(S3reg_0_), .PAD(padS3reg_0_) );
PDO12CDG opResS4_3 ( .A(S4reg_3_), .PAD(padS4reg_3_) );
PDO12CDG opResS4_2 ( .A(S4reg_2_), .PAD(padS4reg_2_) );
PDO12CDG opResS4_1 ( .A(S4reg_1_), .PAD(padS4reg_1_) );
PDO12CDG opResS4_0 ( .A(S4reg_0_), .PAD(padS4reg_0_) );
PDUDGZ padClkG ( .PAD(padClk), .Y(clk) );
sorter coreG ( .Clk(clk), .A_3_(A_3_), .A_2_(A_2_), .A_1_(A_1_), .A_0_(A_0_),
.B_3_(B_3_), .B_2_(B_2_), .B_1_(B_1_), .B_0_(B_0_), .C_3_(C_3_),
.C_2_(C_2_), .C_1_(C_1_), .C_0_(C_0_), .D_3_(D_3_), .D_2_(D_2_),
.D_1_(D_1_), .D_0_(D_0_), .S1reg_3_(S1reg_3_), .S1reg_2_(S1reg_2_),
.S1reg_1_(S1reg_1_), .S1reg_0_(S1reg_0_), .S2reg_3_(S2reg_3_),
.S2reg_2_(S2reg_2_), .S2reg_1_(S2reg_1_), .S2reg_0_(S2reg_0_),
.S3reg_3_(S3reg_3_), .S3reg_2_(S3reg_2_), .S3reg_1_(S3reg_1_),
.S3reg_0_(S3reg_0_), .S4reg_3_(S4reg_3_), .S4reg_2_(S4reg_2_),
.S4reg_1_(S4reg_1_), .S4reg_0_(S4reg_0_) );
endmodule | module sorter_top ( padA_3_, padA_2_, padA_1_, padA_0_, padB_3_, padB_2_,
padB_1_, padB_0_, padC_3_, padC_2_, padC_1_, padC_0_, padD_3_, padD_2_,
padD_1_, padD_0_, padClk, padS1reg_3_, padS1reg_2_, padS1reg_1_,
padS1reg_0_, padS2reg_3_, padS2reg_2_, padS2reg_1_, padS2reg_0_,
padS3reg_3_, padS3reg_2_, padS3reg_1_, padS3reg_0_, padS4reg_3_,
padS4reg_2_, padS4reg_1_, padS4reg_0_ ); |
input padA_3_, padA_2_, padA_1_, padA_0_, padB_3_, padB_2_, padB_1_, padB_0_,
padC_3_, padC_2_, padC_1_, padC_0_, padD_3_, padD_2_, padD_1_,
padD_0_, padClk;
output padS1reg_3_, padS1reg_2_, padS1reg_1_, padS1reg_0_, padS2reg_3_,
padS2reg_2_, padS2reg_1_, padS2reg_0_, padS3reg_3_, padS3reg_2_,
padS3reg_1_, padS3reg_0_, padS4reg_3_, padS4reg_2_, padS4reg_1_,
padS4reg_0_;
wire A_3_, A_2_, A_1_, A_0_, B_3_, B_2_, B_1_, B_0_, C_3_, C_2_, C_1_,
C_0_, D_3_, D_2_, D_1_, D_0_, S1reg_3_, S1reg_2_, S1reg_1_, S1reg_0_,
S2reg_3_, S2reg_2_, S2reg_1_, S2reg_0_, S3reg_3_, S3reg_2_, S3reg_1_,
S3reg_0_, S4reg_3_, S4reg_2_, S4reg_1_, S4reg_0_, clk;
PDUDGZ inpA_3 ( .PAD(padA_3_), .Y(A_3_) );
PDUDGZ inpA_2 ( .PAD(padA_2_), .Y(A_2_) );
PDUDGZ inpA_1 ( .PAD(padA_1_), .Y(A_1_) );
PDUDGZ inpA_0 ( .PAD(padA_0_), .Y(A_0_) );
PDUDGZ inpB_3 ( .PAD(padB_3_), .Y(B_3_) );
PDUDGZ inpB_2 ( .PAD(padB_2_), .Y(B_2_) );
PDUDGZ inpB_1 ( .PAD(padB_1_), .Y(B_1_) );
PDUDGZ inpB_0 ( .PAD(padB_0_), .Y(B_0_) );
PDUDGZ inpC_3 ( .PAD(padC_3_), .Y(C_3_) );
PDUDGZ inpC_2 ( .PAD(padC_2_), .Y(C_2_) );
PDUDGZ inpC_1 ( .PAD(padC_1_), .Y(C_1_) );
PDUDGZ inpC_0 ( .PAD(padC_0_), .Y(C_0_) );
PDUDGZ inpD_3 ( .PAD(padD_3_), .Y(D_3_) );
PDUDGZ inpD_2 ( .PAD(padD_2_), .Y(D_2_) );
PDUDGZ inpD_1 ( .PAD(padD_1_), .Y(D_1_) );
PDUDGZ inpD_0 ( .PAD(padD_0_), .Y(D_0_) );
PDO12CDG opResS1_3 ( .A(S1reg_3_), .PAD(padS1reg_3_) );
PDO12CDG opResS1_2 ( .A(S1reg_2_), .PAD(padS1reg_2_) );
PDO12CDG opResS1_1 ( .A(S1reg_1_), .PAD(padS1reg_1_) );
PDO12CDG opResS1_0 ( .A(S1reg_0_), .PAD(padS1reg_0_) );
PDO12CDG opResS2_3 ( .A(S2reg_3_), .PAD(padS2reg_3_) );
PDO12CDG opResS2_2 ( .A(S2reg_2_), .PAD(padS2reg_2_) );
PDO12CDG opResS2_1 ( .A(S2reg_1_), .PAD(padS2reg_1_) );
PDO12CDG opResS2_0 ( .A(S2reg_0_), .PAD(padS2reg_0_) );
PDO12CDG opResS3_3 ( .A(S3reg_3_), .PAD(padS3reg_3_) );
PDO12CDG opResS3_2 ( .A(S3reg_2_), .PAD(padS3reg_2_) );
PDO12CDG opResS3_1 ( .A(S3reg_1_), .PAD(padS3reg_1_) );
PDO12CDG opResS3_0 ( .A(S3reg_0_), .PAD(padS3reg_0_) );
PDO12CDG opResS4_3 ( .A(S4reg_3_), .PAD(padS4reg_3_) );
PDO12CDG opResS4_2 ( .A(S4reg_2_), .PAD(padS4reg_2_) );
PDO12CDG opResS4_1 ( .A(S4reg_1_), .PAD(padS4reg_1_) );
PDO12CDG opResS4_0 ( .A(S4reg_0_), .PAD(padS4reg_0_) );
PDUDGZ padClkG ( .PAD(padClk), .Y(clk) );
sorter coreG ( .Clk(clk), .A_3_(A_3_), .A_2_(A_2_), .A_1_(A_1_), .A_0_(A_0_),
.B_3_(B_3_), .B_2_(B_2_), .B_1_(B_1_), .B_0_(B_0_), .C_3_(C_3_),
.C_2_(C_2_), .C_1_(C_1_), .C_0_(C_0_), .D_3_(D_3_), .D_2_(D_2_),
.D_1_(D_1_), .D_0_(D_0_), .S1reg_3_(S1reg_3_), .S1reg_2_(S1reg_2_),
.S1reg_1_(S1reg_1_), .S1reg_0_(S1reg_0_), .S2reg_3_(S2reg_3_),
.S2reg_2_(S2reg_2_), .S2reg_1_(S2reg_1_), .S2reg_0_(S2reg_0_),
.S3reg_3_(S3reg_3_), .S3reg_2_(S3reg_2_), .S3reg_1_(S3reg_1_),
.S3reg_0_(S3reg_0_), .S4reg_3_(S4reg_3_), .S4reg_2_(S4reg_2_),
.S4reg_1_(S4reg_1_), .S4reg_0_(S4reg_0_) );
endmodule | 0 |
138,586 | data/full_repos/permissive/84784314/mojo_io_shield/work/planAhead/Elevator/Elevator.srcs/sources_1/imports/verilog/mojo_top_0.v | 84,784,314 | mojo_top_0.v | v | 75 | 58 | [] | [] | [] | [(1, 75)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/84784314/mojo_io_shield/work/planAhead/Elevator/Elevator.srcs/sources_1/imports/verilog/mojo_top_0.v:42: Operator ADD expects 26 bits on the RHS, but RHS\'s CONST \'8\'hfa\' generates 8 bits.\n : ... In instance mojo_top_0\n slow_clk_d = slow_clk_q + 8\'hFA;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/84784314/mojo_io_shield/work/planAhead/Elevator/Elevator.srcs/sources_1/imports/verilog/mojo_top_0.v:44: Operator ADD expects 26 bits on the RHS, but RHS\'s CONST \'11\'h4e2\' generates 11 bits.\n : ... In instance mojo_top_0\n slow_clk_d = slow_clk_q + 11\'h4E2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84784314/mojo_io_shield/work/planAhead/Elevator/Elevator.srcs/sources_1/imports/verilog/mojo_top_0.v:46: Operator ADD expects 26 bits on the RHS, but RHS\'s CONST \'13\'h186a\' generates 13 bits.\n : ... In instance mojo_top_0\n slow_clk_d = slow_clk_q + 13\'h186A;\n ^\n%Warning-WIDTH: data/full_repos/permissive/84784314/mojo_io_shield/work/planAhead/Elevator/Elevator.srcs/sources_1/imports/verilog/mojo_top_0.v:45: Operator MODDIV expects 26 bits on the RHS, but RHS\'s CONST \'13\'h186a\' generates 13 bits.\n : ... In instance mojo_top_0\n end else if (pb[2] && ~(slow_clk_q % 13\'h186A)) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/84784314/mojo_io_shield/work/planAhead/Elevator/Elevator.srcs/sources_1/imports/verilog/mojo_top_0.v:45: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s NOT generates 26 bits.\n : ... In instance mojo_top_0\n end else if (pb[2] && ~(slow_clk_q % 13\'h186A)) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/84784314/mojo_io_shield/work/planAhead/Elevator/Elevator.srcs/sources_1/imports/verilog/mojo_top_0.v:43: Operator MODDIV expects 26 bits on the RHS, but RHS\'s CONST \'11\'h4e2\' generates 11 bits.\n : ... In instance mojo_top_0\n end else if (pb[1] && ~(slow_clk_q % 11\'h4E2)) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/84784314/mojo_io_shield/work/planAhead/Elevator/Elevator.srcs/sources_1/imports/verilog/mojo_top_0.v:43: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s NOT generates 26 bits.\n : ... In instance mojo_top_0\n end else if (pb[1] && ~(slow_clk_q % 11\'h4E2)) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/84784314/mojo_io_shield/work/planAhead/Elevator/Elevator.srcs/sources_1/imports/verilog/mojo_top_0.v:41: Operator MODDIV expects 26 bits on the RHS, but RHS\'s CONST \'8\'hfa\' generates 8 bits.\n : ... In instance mojo_top_0\n if (pb[0] && ~(slow_clk_q % 8\'hFA)) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/84784314/mojo_io_shield/work/planAhead/Elevator/Elevator.srcs/sources_1/imports/verilog/mojo_top_0.v:41: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s NOT generates 26 bits.\n : ... In instance mojo_top_0\n if (pb[0] && ~(slow_clk_q % 8\'hFA)) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/84784314/mojo_io_shield/work/planAhead/Elevator/Elevator.srcs/sources_1/imports/verilog/mojo_top_0.v:54: Operator ASSIGNDLY expects 26 bits on the Assign RHS, but Assign RHS\'s CONST \'25\'h0\' generates 25 bits.\n : ... In instance mojo_top_0\n slow_clk_q <= 25\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/84784314/mojo_io_shield/work/planAhead/Elevator/Elevator.srcs/sources_1/imports/verilog/mojo_top_0.v:57: Operator ASSIGNDLY expects 26 bits on the Assign RHS, but Assign RHS\'s CONST \'25\'h0\' generates 25 bits.\n : ... In instance mojo_top_0\n slow_clk_q <= 25\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/84784314/mojo_io_shield/work/planAhead/Elevator/Elevator.srcs/sources_1/imports/verilog/mojo_top_0.v:56: Operator EQ expects 26 bits on the RHS, but RHS\'s CONST \'25\'h17d7840\' generates 25 bits.\n : ... In instance mojo_top_0\n end else if (slow_clk_q == 25\'h17D7840) begin\n ^~\n%Error: data/full_repos/permissive/84784314/mojo_io_shield/work/planAhead/Elevator/Elevator.srcs/sources_1/imports/verilog/mojo_top_0.v:64: Cannot find file containing module: \'clock_1\'\nclock_1 real_deal (\n^~~~~~~\n ... Looked in:\n data/full_repos/permissive/84784314/mojo_io_shield/work/planAhead/Elevator/Elevator.srcs/sources_1/imports/verilog,data/full_repos/permissive/84784314/clock_1\n data/full_repos/permissive/84784314/mojo_io_shield/work/planAhead/Elevator/Elevator.srcs/sources_1/imports/verilog,data/full_repos/permissive/84784314/clock_1.v\n data/full_repos/permissive/84784314/mojo_io_shield/work/planAhead/Elevator/Elevator.srcs/sources_1/imports/verilog,data/full_repos/permissive/84784314/clock_1.sv\n clock_1\n clock_1.v\n clock_1.sv\n obj_dir/clock_1\n obj_dir/clock_1.v\n obj_dir/clock_1.sv\n%Error: Exiting due to 1 error(s), 12 warning(s)\n' | 302,564 | module | module mojo_top_0(
input clk,
input rst_n,
input cclk,
output[7:0]led,
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
output [3:0] spi_channel,
input avr_tx,
output avr_rx,
input avr_rx_busy,
output [23:0] io_led,
output [7:0] io_seg,
output [3:0] io_sel,
input [3:0] pb,
input en,
output pm
);
wire rst = ~rst_n;
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
assign led[7:0] = {8{slow_clk}};
reg [25:0] slow_clk_d, slow_clk_q;
reg slow_clk;
always @(slow_clk_q) begin
if (pb[0] && ~(slow_clk_q % 8'hFA)) begin
slow_clk_d = slow_clk_q + 8'hFA;
end else if (pb[1] && ~(slow_clk_q % 11'h4E2)) begin
slow_clk_d = slow_clk_q + 11'h4E2;
end else if (pb[2] && ~(slow_clk_q % 13'h186A)) begin
slow_clk_d = slow_clk_q + 13'h186A;
end else begin
slow_clk_d = slow_clk_q + 1'b1;
end
end
always @(posedge clk, posedge rst) begin
if (rst == 1) begin
slow_clk_q <= 25'b0;
slow_clk <= 1'b0;
end else if (slow_clk_q == 25'h17D7840) begin
slow_clk_q <= 25'b0;
slow_clk <= ~slow_clk;
end else begin
slow_clk_q <= slow_clk_d;
end
end
clock_1 real_deal (
.clk(slow_clk),
.fast_clk(slow_clk_q[16]),
.rst(rst),
.en(~en),
.sec(io_led[7:0]),
.pm(io_led[23:8]),
.io_seg(io_seg),
.io_sel(io_sel)
);
endmodule | module mojo_top_0(
input clk,
input rst_n,
input cclk,
output[7:0]led,
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
output [3:0] spi_channel,
input avr_tx,
output avr_rx,
input avr_rx_busy,
output [23:0] io_led,
output [7:0] io_seg,
output [3:0] io_sel,
input [3:0] pb,
input en,
output pm
); |
wire rst = ~rst_n;
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
assign led[7:0] = {8{slow_clk}};
reg [25:0] slow_clk_d, slow_clk_q;
reg slow_clk;
always @(slow_clk_q) begin
if (pb[0] && ~(slow_clk_q % 8'hFA)) begin
slow_clk_d = slow_clk_q + 8'hFA;
end else if (pb[1] && ~(slow_clk_q % 11'h4E2)) begin
slow_clk_d = slow_clk_q + 11'h4E2;
end else if (pb[2] && ~(slow_clk_q % 13'h186A)) begin
slow_clk_d = slow_clk_q + 13'h186A;
end else begin
slow_clk_d = slow_clk_q + 1'b1;
end
end
always @(posedge clk, posedge rst) begin
if (rst == 1) begin
slow_clk_q <= 25'b0;
slow_clk <= 1'b0;
end else if (slow_clk_q == 25'h17D7840) begin
slow_clk_q <= 25'b0;
slow_clk <= ~slow_clk;
end else begin
slow_clk_q <= slow_clk_d;
end
end
clock_1 real_deal (
.clk(slow_clk),
.fast_clk(slow_clk_q[16]),
.rst(rst),
.en(~en),
.sec(io_led[7:0]),
.pm(io_led[23:8]),
.io_seg(io_seg),
.io_sel(io_sel)
);
endmodule | 0 |
138,587 | data/full_repos/permissive/84784314/myhdl/tb_clock.v | 84,784,314 | tb_clock.v | v | 33 | 22 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/84784314/myhdl/tb_clock.v:11: Unsupported or unknown PLI call: $from_myhdl\n $from_myhdl(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/84784314/myhdl/tb_clock.v:18: Unsupported or unknown PLI call: $to_myhdl\n $to_myhdl(\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,568 | module | module tb_clock;
reg clk;
reg reset;
reg en;
reg [23:0] count_vec;
wire pm;
reg [41:0] LED_vec;
initial begin
$from_myhdl(
clk,
reset,
en,
count_vec,
LED_vec
);
$to_myhdl(
pm
);
end
clock dut(
clk,
reset,
en,
count_vec,
pm,
LED_vec
);
endmodule | module tb_clock; |
reg clk;
reg reset;
reg en;
reg [23:0] count_vec;
wire pm;
reg [41:0] LED_vec;
initial begin
$from_myhdl(
clk,
reset,
en,
count_vec,
LED_vec
);
$to_myhdl(
pm
);
end
clock dut(
clk,
reset,
en,
count_vec,
pm,
LED_vec
);
endmodule | 0 |
138,588 | data/full_repos/permissive/85002992/aexm/aexm_bpcu.v | 85,002,992 | aexm_bpcu.v | v | 224 | 75 | [] | [] | [] | null | line:54: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/85002992/aexm/aexm_bpcu.v:186: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'xIPC\' generates 30 bits.\n : ... In instance aexm_bpcu\n assign aexm_icache_precycle_addr = xIPC;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 302,569 | module | module aexm_bpcu (
aexm_icache_precycle_addr, rIPC, rPC,
dSKIP, xSKIP, rBRA,
dMXALT, xRESULT, c_io_rg, xREGA,
cpu_mode_memop, dINST, gclk, x_en, d_en
);
parameter IW = 24;
output [31:0] aexm_icache_precycle_addr;
output [31:2] rIPC, rPC;
output dSKIP;
output xSKIP;
output rBRA;
input [1:0] dMXALT;
input [31:0] xRESULT;
input [31:0] c_io_rg;
input [31:0] xREGA;
input [31:0] dINST;
input cpu_mode_memop;
input gclk, x_en, d_en;
wire [5:0] dOPC;
wire [4:0] dRD, dRA, dRB;
wire [10:0] dALT;
assign {dOPC, dRD, dRA, dRB, dALT} = dINST;
reg [31:0] wREGA = 32'd0;
always @(posedge gclk)
if (d_en)
case (dMXALT)
2'o2: wREGA <= c_io_rg;
2'o1: wREGA <= xRESULT;
default: wREGA <= xREGA;
endcase
reg chain_endpoint = 1'b1, careof_equal_n = 1'b1,
careof_ltgt = 1'b0, expect_equal = 1'b0,
expect_ltgt = 1'b0, invert_answer = 1'b1,
rSKIP_n = 1'b1, fSKIP, dSKIP, xSKIP = 1'b0,
xBRA, rBRA = 1'b0;
wire reg_equal_null_n, ltgt_true, expect_reg_equal,
dBCC, dBRU;
always @(posedge gclk)
if (fSKIP) begin
chain_endpoint <= 1;
careof_equal_n <= 1;
careof_ltgt <= 0;
expect_equal <= 0;
expect_ltgt <= 0;
invert_answer <= 1;
rSKIP_n <= 1;
end else if (d_en) begin
if (dSKIP) begin
rSKIP_n <= 0;
end else begin
chain_endpoint <= !(dBRU ||
(dBCC &&
((dRD[2:0] == 3'h0) ||
(dRD[2:0] == 3'h1) ||
(dRD[2:0] == 3'h3) ||
(dRD[2:0] == 3'h4) ||
(dRD[2:0] == 3'h5))));
careof_equal_n <= !(dBCC &&
((dRD[2:0] == 3'h0) ||
(dRD[2:0] == 3'h1) ||
(dRD[2:0] == 3'h3) ||
(dRD[2:0] == 3'h4) ||
(dRD[2:0] == 3'h5)));
careof_ltgt <= dBCC &&
((dRD[2:0] == 3'h2) ||
(dRD[2:0] == 3'h3) ||
(dRD[2:0] == 3'h4) ||
(dRD[2:0] == 3'h5));
expect_equal <= !dBRU;
expect_ltgt <= ((dRD[2:0] == 3'h2) ||
(dRD[2:0] == 3'h3) ||
(dRD[2:0] == 3'h4)) ? 1 : 0;
invert_answer <= dBCC &&
((dRD[2:0] == 3'h1) ||
(dRD[2:0] == 3'h4));
rSKIP_n <= ((dBRU && dRA[4]) || (dBCC && dRD[4]));
end
end
assign reg_equal_null_n = expect_equal ?
(((wREGA ^ 32'd0) == 0) ? chain_endpoint : 1) :
0;
assign ltgt_true = careof_ltgt && (expect_ltgt == wREGA[31]);
assign expect_reg_equal = careof_equal_n ?
(careof_ltgt ?
!ltgt_true :
expect_equal) :
(careof_ltgt ?
(ltgt_true ?
0 :
expect_equal) :
expect_equal);
always @(expect_reg_equal or reg_equal_null_n or invert_answer or
rSKIP_n)
case ({expect_reg_equal,reg_equal_null_n,invert_answer})
3'b000: begin
xBRA <= 1;
dSKIP <= !rSKIP_n; fSKIP <= 1;
end
3'b001: begin
xBRA <= 0;
dSKIP <= rSKIP_n; fSKIP <= 0;
end
3'b010: begin
xBRA <= 1;
dSKIP <= !rSKIP_n; fSKIP <= 1;
end
3'b011: begin
xBRA <= 0;
dSKIP <= 0; fSKIP <= 0;
end
3'b100: begin
xBRA <= 1;
dSKIP <= !rSKIP_n; fSKIP <= 1;
end
3'b101: begin
xBRA <= 0;
dSKIP <= 0; fSKIP <= 0;
end
3'b110: begin
xBRA <= 0;
dSKIP <= 0; fSKIP <= 0;
end
3'b111: begin
xBRA <= 1;
dSKIP <= !rSKIP_n; fSKIP <= 1;
end
endcase
assign dBCC = ((dOPC == 6'o47) | (dOPC == 6'o57));
assign dBRU = ((dOPC == 6'o46) | (dOPC == 6'o56));
reg [31:2] pre_rIPC = 30'h0, rIPC = 30'h0, xIPC;
reg [31:2] rPC = 30'h0, xPC;
wire [31:2] pc_inc;
assign aexm_icache_precycle_addr = xIPC;
assign pc_inc = {{(29){1'b0}},cpu_mode_memop};
always @(xBRA or rIPC or rPC or xRESULT or pre_rIPC or pc_inc)
begin
xPC <= rIPC;
xIPC <= (xBRA) ? xRESULT[31:2] : (pre_rIPC + pc_inc);
end
always @(posedge gclk)
if (x_en) begin
pre_rIPC <= xIPC;
rIPC <= pre_rIPC;
rPC <= xPC;
xSKIP <= dSKIP;
rBRA <= xBRA;
end
endmodule | module aexm_bpcu (
aexm_icache_precycle_addr, rIPC, rPC,
dSKIP, xSKIP, rBRA,
dMXALT, xRESULT, c_io_rg, xREGA,
cpu_mode_memop, dINST, gclk, x_en, d_en
); |
parameter IW = 24;
output [31:0] aexm_icache_precycle_addr;
output [31:2] rIPC, rPC;
output dSKIP;
output xSKIP;
output rBRA;
input [1:0] dMXALT;
input [31:0] xRESULT;
input [31:0] c_io_rg;
input [31:0] xREGA;
input [31:0] dINST;
input cpu_mode_memop;
input gclk, x_en, d_en;
wire [5:0] dOPC;
wire [4:0] dRD, dRA, dRB;
wire [10:0] dALT;
assign {dOPC, dRD, dRA, dRB, dALT} = dINST;
reg [31:0] wREGA = 32'd0;
always @(posedge gclk)
if (d_en)
case (dMXALT)
2'o2: wREGA <= c_io_rg;
2'o1: wREGA <= xRESULT;
default: wREGA <= xREGA;
endcase
reg chain_endpoint = 1'b1, careof_equal_n = 1'b1,
careof_ltgt = 1'b0, expect_equal = 1'b0,
expect_ltgt = 1'b0, invert_answer = 1'b1,
rSKIP_n = 1'b1, fSKIP, dSKIP, xSKIP = 1'b0,
xBRA, rBRA = 1'b0;
wire reg_equal_null_n, ltgt_true, expect_reg_equal,
dBCC, dBRU;
always @(posedge gclk)
if (fSKIP) begin
chain_endpoint <= 1;
careof_equal_n <= 1;
careof_ltgt <= 0;
expect_equal <= 0;
expect_ltgt <= 0;
invert_answer <= 1;
rSKIP_n <= 1;
end else if (d_en) begin
if (dSKIP) begin
rSKIP_n <= 0;
end else begin
chain_endpoint <= !(dBRU ||
(dBCC &&
((dRD[2:0] == 3'h0) ||
(dRD[2:0] == 3'h1) ||
(dRD[2:0] == 3'h3) ||
(dRD[2:0] == 3'h4) ||
(dRD[2:0] == 3'h5))));
careof_equal_n <= !(dBCC &&
((dRD[2:0] == 3'h0) ||
(dRD[2:0] == 3'h1) ||
(dRD[2:0] == 3'h3) ||
(dRD[2:0] == 3'h4) ||
(dRD[2:0] == 3'h5)));
careof_ltgt <= dBCC &&
((dRD[2:0] == 3'h2) ||
(dRD[2:0] == 3'h3) ||
(dRD[2:0] == 3'h4) ||
(dRD[2:0] == 3'h5));
expect_equal <= !dBRU;
expect_ltgt <= ((dRD[2:0] == 3'h2) ||
(dRD[2:0] == 3'h3) ||
(dRD[2:0] == 3'h4)) ? 1 : 0;
invert_answer <= dBCC &&
((dRD[2:0] == 3'h1) ||
(dRD[2:0] == 3'h4));
rSKIP_n <= ((dBRU && dRA[4]) || (dBCC && dRD[4]));
end
end
assign reg_equal_null_n = expect_equal ?
(((wREGA ^ 32'd0) == 0) ? chain_endpoint : 1) :
0;
assign ltgt_true = careof_ltgt && (expect_ltgt == wREGA[31]);
assign expect_reg_equal = careof_equal_n ?
(careof_ltgt ?
!ltgt_true :
expect_equal) :
(careof_ltgt ?
(ltgt_true ?
0 :
expect_equal) :
expect_equal);
always @(expect_reg_equal or reg_equal_null_n or invert_answer or
rSKIP_n)
case ({expect_reg_equal,reg_equal_null_n,invert_answer})
3'b000: begin
xBRA <= 1;
dSKIP <= !rSKIP_n; fSKIP <= 1;
end
3'b001: begin
xBRA <= 0;
dSKIP <= rSKIP_n; fSKIP <= 0;
end
3'b010: begin
xBRA <= 1;
dSKIP <= !rSKIP_n; fSKIP <= 1;
end
3'b011: begin
xBRA <= 0;
dSKIP <= 0; fSKIP <= 0;
end
3'b100: begin
xBRA <= 1;
dSKIP <= !rSKIP_n; fSKIP <= 1;
end
3'b101: begin
xBRA <= 0;
dSKIP <= 0; fSKIP <= 0;
end
3'b110: begin
xBRA <= 0;
dSKIP <= 0; fSKIP <= 0;
end
3'b111: begin
xBRA <= 1;
dSKIP <= !rSKIP_n; fSKIP <= 1;
end
endcase
assign dBCC = ((dOPC == 6'o47) | (dOPC == 6'o57));
assign dBRU = ((dOPC == 6'o46) | (dOPC == 6'o56));
reg [31:2] pre_rIPC = 30'h0, rIPC = 30'h0, xIPC;
reg [31:2] rPC = 30'h0, xPC;
wire [31:2] pc_inc;
assign aexm_icache_precycle_addr = xIPC;
assign pc_inc = {{(29){1'b0}},cpu_mode_memop};
always @(xBRA or rIPC or rPC or xRESULT or pre_rIPC or pc_inc)
begin
xPC <= rIPC;
xIPC <= (xBRA) ? xRESULT[31:2] : (pre_rIPC + pc_inc);
end
always @(posedge gclk)
if (x_en) begin
pre_rIPC <= xIPC;
rIPC <= pre_rIPC;
rPC <= xPC;
xSKIP <= dSKIP;
rBRA <= xBRA;
end
endmodule | 1 |
138,590 | data/full_repos/permissive/85002992/aexm/aexm_edk32.v | 85,002,992 | aexm_edk32.v | v | 230 | 63 | [] | [] | [] | [(1, 229)] | null | null | 1: b"%Error: data/full_repos/permissive/85002992/aexm/aexm_edk32.v:94: Cannot find file containing module: 'aexm_enable'\n aexm_enable enable(.CLK(gclk),\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85002992/aexm,data/full_repos/permissive/85002992/aexm_enable\n data/full_repos/permissive/85002992/aexm,data/full_repos/permissive/85002992/aexm_enable.v\n data/full_repos/permissive/85002992/aexm,data/full_repos/permissive/85002992/aexm_enable.sv\n aexm_enable\n aexm_enable.v\n aexm_enable.sv\n obj_dir/aexm_enable\n obj_dir/aexm_enable.v\n obj_dir/aexm_enable.sv\n%Error: data/full_repos/permissive/85002992/aexm/aexm_edk32.v:107: Cannot find file containing module: 'aexm_ibuf'\n aexm_ibuf\n ^~~~~~~~~\n%Error: data/full_repos/permissive/85002992/aexm/aexm_edk32.v:129: Cannot find file containing module: 'aexm_ctrl'\n aexm_ctrl\n ^~~~~~~~~\n%Error: data/full_repos/permissive/85002992/aexm/aexm_edk32.v:155: Cannot find file containing module: 'aexm_bpcu'\n aexm_bpcu #(IW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/85002992/aexm/aexm_edk32.v:174: Cannot find file containing module: 'aexm_regf'\n aexm_regf\n ^~~~~~~~~\n%Error: data/full_repos/permissive/85002992/aexm/aexm_edk32.v:200: Cannot find file containing module: 'aexm_xecu'\n aexm_xecu #(DW, BSF)\n ^~~~~~~~~\n%Error: Exiting due to 6 error(s)\n" | 302,571 | module | module aexm_edk32 (
aexm_icache_precycle_addr,
aexm_dcache_precycle_addr,
aexm_dcache_datao, aexm_dcache_precycle_we,
aexm_dcache_precycle_enable, aexm_icache_precycle_enable,
aexm_dcache_we_tlb, aexm_icache_we_tlb,
aexm_dcache_force_miss,
aexm_icache_datai, aexm_dcache_datai,
aexm_icache_cache_busy, aexm_dcache_cache_busy,
sys_int_i, sys_clk_i, sys_rst_i
);
parameter IW = 32;
parameter DW = 32;
parameter BSF = 1;
output [31:0] aexm_icache_precycle_addr;
input [31:0] aexm_icache_datai;
output aexm_icache_precycle_enable;
output [31:0] aexm_dcache_precycle_addr;
input [31:0] aexm_dcache_datai;
output [31:0] aexm_dcache_datao;
output aexm_dcache_precycle_we;
output aexm_dcache_precycle_enable;
output aexm_dcache_we_tlb;
output aexm_icache_we_tlb;
output aexm_dcache_force_miss;
input aexm_icache_cache_busy;
input aexm_dcache_cache_busy;
input sys_int_i;
wire [10:0] xALT;
wire dSKIP;
wire xSKIP;
wire rBRA;
wire [31:0] c_io_rg;
wire [3:0] rDWBSEL;
wire [15:0] xIMM;
wire rMSR_IE;
wire [1:0] dMXALT;
wire [2:0] xMXALU;
wire [1:0] rMXDST;
wire rMXDST_use_combined;
wire [1:0] dMXSRC;
wire [1:0] dMXTGT;
wire [5:0] xOPC;
wire [5:0] dOPC;
wire [31:2] rIPC;
wire [31:2] rPC;
wire MEMOP_MXDST;
wire [4:0] xRA;
wire [4:0] xRB;
wire [4:0] xRD;
wire [4:0] dRA;
wire [4:0] dRB;
wire [4:0] dRD;
wire [31:0] xREGA;
wire [31:0] xREGB;
wire [31:0] xRESULT;
wire [31:0] rRESULT;
wire [4:0] rRW;
wire rRDWE;
wire [31:0] dIMMVAL;
wire fSTALL;
wire [31:0] dINST;
wire late_forward_D;
wire dSTRLOD;
wire dLOD;
wire cpu_enable;
wire cpu_mode_memop;
input sys_clk_i;
input sys_rst_i;
assign aexm_dcache_we_tlb = 1'b0;
assign aexm_icache_we_tlb = 1'b0;
wire grst = sys_rst_i;
wire gclk = sys_clk_i;
aexm_enable enable(.CLK(gclk),
.grst(grst),
.icache_busy(aexm_icache_cache_busy),
.dcache_busy(aexm_dcache_cache_busy),
.dSTRLOD(dSTRLOD),
.dLOD(dLOD),
.dSKIP(dSKIP),
.fSTALL(fSTALL),
.cpu_mode_memop(cpu_mode_memop),
.cpu_enable(cpu_enable),
.icache_enable(aexm_icache_precycle_enable),
.dcache_enable(aexm_dcache_precycle_enable));
aexm_ibuf
ibuf (
.xIMM (xIMM[15:0]),
.xRA (xRA[4:0]),
.xRD (xRD[4:0]),
.xRB (xRB[4:0]),
.xALT (xALT[10:0]),
.xOPC (xOPC[5:0]),
.dOPC (dOPC[5:0]),
.dIMMVAL (dIMMVAL[31:0]),
.dINST (dINST[31:0]),
.dRA (dRA),
.dRB (dRB),
.dRD (dRD),
.rMSR_IE (rMSR_IE),
.rBRA (rBRA),
.aexm_icache_datai (aexm_icache_datai),
.sys_int_i (sys_int_i),
.gclk (gclk),
.d_en (cpu_enable));
aexm_ctrl
ctrl (
.rMXDST (rMXDST[1:0]),
.rMXDST_use_combined (rMXDST_use_combined),
.MEMOP_MXDST (MEMOP_MXDST),
.dMXSRC (dMXSRC[1:0]),
.dMXTGT (dMXTGT[1:0]),
.dMXALT (dMXALT[1:0]),
.xMXALU (xMXALU[2:0]),
.rRW (rRW[4:0]),
.rRDWE (rRDWE),
.dSTRLOD (dSTRLOD),
.dLOD (dLOD),
.fSTALL (fSTALL),
.late_forward_D (late_forward_D),
.aexm_dcache_precycle_we (aexm_dcache_precycle_we),
.aexm_dcache_force_miss (aexm_dcache_force_miss),
.xSKIP (xSKIP),
.xALT (xALT[10:0]),
.xRD (xRD[4:0]),
.dINST (dINST[31:0]),
.gclk (gclk),
.d_en (cpu_enable),
.x_en (cpu_enable));
aexm_bpcu #(IW)
bpcu (
.aexm_icache_precycle_addr (aexm_icache_precycle_addr),
.rIPC (rIPC[31:2]),
.rPC (rPC[31:2]),
.dSKIP (dSKIP),
.xSKIP (xSKIP),
.rBRA (rBRA),
.cpu_mode_memop (cpu_mode_memop),
.dMXALT (dMXALT[1:0]),
.dINST (dINST[31:0]),
.xRESULT (xRESULT[31:0]),
.c_io_rg (c_io_rg[31:0]),
.xREGA (xREGA[31:0]),
.gclk (gclk),
.d_en (cpu_enable),
.x_en (cpu_enable));
aexm_regf
regf (
.xREGA (xREGA[31:0]),
.xREGB (xREGB[31:0]),
.c_io_rg (c_io_rg[31:0]),
.aexm_dcache_datao (aexm_dcache_datao),
.xOPC (xOPC[5:0]),
.dRA (dRA),
.dRB (dRB),
.dRD (dRD),
.rRW (rRW[4:0]),
.rRDWE (rRDWE),
.xRD (xRD[4:0]),
.rMXDST (rMXDST[1:0]),
.rMXDST_use_combined (rMXDST_use_combined),
.MEMOP_MXDST (MEMOP_MXDST),
.late_forward_D (late_forward_D),
.rPC (rPC[31:2]),
.rRESULT (rRESULT[31:0]),
.rDWBSEL (rDWBSEL[3:0]),
.aexm_dcache_datai (aexm_dcache_datai),
.gclk (gclk),
.d_en (cpu_enable),
.x_en (cpu_enable));
aexm_xecu #(DW, BSF)
xecu (
.aexm_dcache_precycle_addr (aexm_dcache_precycle_addr),
.xRESULT (xRESULT[31:0]),
.rRESULT (rRESULT[31:0]),
.rDWBSEL (rDWBSEL[3:0]),
.rMSR_IE (rMSR_IE),
.xREGA (xREGA[31:0]),
.xREGB (xREGB[31:0]),
.dMXSRC (dMXSRC[1:0]),
.dMXTGT (dMXTGT[1:0]),
.xRA (xRA[4:0]),
.xMXALU (xMXALU[2:0]),
.xSKIP (xSKIP),
.xALT (xALT[10:0]),
.dIMMVAL (dIMMVAL[31:0]),
.xIMM (xIMM[15:0]),
.xOPC (xOPC[5:0]),
.dOPC (dOPC[5:0]),
.xRD (xRD[4:0]),
.c_io_rg (c_io_rg[31:0]),
.rIPC (rIPC[31:2]),
.rPC (rPC[31:2]),
.gclk (gclk),
.d_en (cpu_enable),
.x_en (cpu_enable));
endmodule | module aexm_edk32 (
aexm_icache_precycle_addr,
aexm_dcache_precycle_addr,
aexm_dcache_datao, aexm_dcache_precycle_we,
aexm_dcache_precycle_enable, aexm_icache_precycle_enable,
aexm_dcache_we_tlb, aexm_icache_we_tlb,
aexm_dcache_force_miss,
aexm_icache_datai, aexm_dcache_datai,
aexm_icache_cache_busy, aexm_dcache_cache_busy,
sys_int_i, sys_clk_i, sys_rst_i
); |
parameter IW = 32;
parameter DW = 32;
parameter BSF = 1;
output [31:0] aexm_icache_precycle_addr;
input [31:0] aexm_icache_datai;
output aexm_icache_precycle_enable;
output [31:0] aexm_dcache_precycle_addr;
input [31:0] aexm_dcache_datai;
output [31:0] aexm_dcache_datao;
output aexm_dcache_precycle_we;
output aexm_dcache_precycle_enable;
output aexm_dcache_we_tlb;
output aexm_icache_we_tlb;
output aexm_dcache_force_miss;
input aexm_icache_cache_busy;
input aexm_dcache_cache_busy;
input sys_int_i;
wire [10:0] xALT;
wire dSKIP;
wire xSKIP;
wire rBRA;
wire [31:0] c_io_rg;
wire [3:0] rDWBSEL;
wire [15:0] xIMM;
wire rMSR_IE;
wire [1:0] dMXALT;
wire [2:0] xMXALU;
wire [1:0] rMXDST;
wire rMXDST_use_combined;
wire [1:0] dMXSRC;
wire [1:0] dMXTGT;
wire [5:0] xOPC;
wire [5:0] dOPC;
wire [31:2] rIPC;
wire [31:2] rPC;
wire MEMOP_MXDST;
wire [4:0] xRA;
wire [4:0] xRB;
wire [4:0] xRD;
wire [4:0] dRA;
wire [4:0] dRB;
wire [4:0] dRD;
wire [31:0] xREGA;
wire [31:0] xREGB;
wire [31:0] xRESULT;
wire [31:0] rRESULT;
wire [4:0] rRW;
wire rRDWE;
wire [31:0] dIMMVAL;
wire fSTALL;
wire [31:0] dINST;
wire late_forward_D;
wire dSTRLOD;
wire dLOD;
wire cpu_enable;
wire cpu_mode_memop;
input sys_clk_i;
input sys_rst_i;
assign aexm_dcache_we_tlb = 1'b0;
assign aexm_icache_we_tlb = 1'b0;
wire grst = sys_rst_i;
wire gclk = sys_clk_i;
aexm_enable enable(.CLK(gclk),
.grst(grst),
.icache_busy(aexm_icache_cache_busy),
.dcache_busy(aexm_dcache_cache_busy),
.dSTRLOD(dSTRLOD),
.dLOD(dLOD),
.dSKIP(dSKIP),
.fSTALL(fSTALL),
.cpu_mode_memop(cpu_mode_memop),
.cpu_enable(cpu_enable),
.icache_enable(aexm_icache_precycle_enable),
.dcache_enable(aexm_dcache_precycle_enable));
aexm_ibuf
ibuf (
.xIMM (xIMM[15:0]),
.xRA (xRA[4:0]),
.xRD (xRD[4:0]),
.xRB (xRB[4:0]),
.xALT (xALT[10:0]),
.xOPC (xOPC[5:0]),
.dOPC (dOPC[5:0]),
.dIMMVAL (dIMMVAL[31:0]),
.dINST (dINST[31:0]),
.dRA (dRA),
.dRB (dRB),
.dRD (dRD),
.rMSR_IE (rMSR_IE),
.rBRA (rBRA),
.aexm_icache_datai (aexm_icache_datai),
.sys_int_i (sys_int_i),
.gclk (gclk),
.d_en (cpu_enable));
aexm_ctrl
ctrl (
.rMXDST (rMXDST[1:0]),
.rMXDST_use_combined (rMXDST_use_combined),
.MEMOP_MXDST (MEMOP_MXDST),
.dMXSRC (dMXSRC[1:0]),
.dMXTGT (dMXTGT[1:0]),
.dMXALT (dMXALT[1:0]),
.xMXALU (xMXALU[2:0]),
.rRW (rRW[4:0]),
.rRDWE (rRDWE),
.dSTRLOD (dSTRLOD),
.dLOD (dLOD),
.fSTALL (fSTALL),
.late_forward_D (late_forward_D),
.aexm_dcache_precycle_we (aexm_dcache_precycle_we),
.aexm_dcache_force_miss (aexm_dcache_force_miss),
.xSKIP (xSKIP),
.xALT (xALT[10:0]),
.xRD (xRD[4:0]),
.dINST (dINST[31:0]),
.gclk (gclk),
.d_en (cpu_enable),
.x_en (cpu_enable));
aexm_bpcu #(IW)
bpcu (
.aexm_icache_precycle_addr (aexm_icache_precycle_addr),
.rIPC (rIPC[31:2]),
.rPC (rPC[31:2]),
.dSKIP (dSKIP),
.xSKIP (xSKIP),
.rBRA (rBRA),
.cpu_mode_memop (cpu_mode_memop),
.dMXALT (dMXALT[1:0]),
.dINST (dINST[31:0]),
.xRESULT (xRESULT[31:0]),
.c_io_rg (c_io_rg[31:0]),
.xREGA (xREGA[31:0]),
.gclk (gclk),
.d_en (cpu_enable),
.x_en (cpu_enable));
aexm_regf
regf (
.xREGA (xREGA[31:0]),
.xREGB (xREGB[31:0]),
.c_io_rg (c_io_rg[31:0]),
.aexm_dcache_datao (aexm_dcache_datao),
.xOPC (xOPC[5:0]),
.dRA (dRA),
.dRB (dRB),
.dRD (dRD),
.rRW (rRW[4:0]),
.rRDWE (rRDWE),
.xRD (xRD[4:0]),
.rMXDST (rMXDST[1:0]),
.rMXDST_use_combined (rMXDST_use_combined),
.MEMOP_MXDST (MEMOP_MXDST),
.late_forward_D (late_forward_D),
.rPC (rPC[31:2]),
.rRESULT (rRESULT[31:0]),
.rDWBSEL (rDWBSEL[3:0]),
.aexm_dcache_datai (aexm_dcache_datai),
.gclk (gclk),
.d_en (cpu_enable),
.x_en (cpu_enable));
aexm_xecu #(DW, BSF)
xecu (
.aexm_dcache_precycle_addr (aexm_dcache_precycle_addr),
.xRESULT (xRESULT[31:0]),
.rRESULT (rRESULT[31:0]),
.rDWBSEL (rDWBSEL[3:0]),
.rMSR_IE (rMSR_IE),
.xREGA (xREGA[31:0]),
.xREGB (xREGB[31:0]),
.dMXSRC (dMXSRC[1:0]),
.dMXTGT (dMXTGT[1:0]),
.xRA (xRA[4:0]),
.xMXALU (xMXALU[2:0]),
.xSKIP (xSKIP),
.xALT (xALT[10:0]),
.dIMMVAL (dIMMVAL[31:0]),
.xIMM (xIMM[15:0]),
.xOPC (xOPC[5:0]),
.dOPC (dOPC[5:0]),
.xRD (xRD[4:0]),
.c_io_rg (c_io_rg[31:0]),
.rIPC (rIPC[31:2]),
.rPC (rPC[31:2]),
.gclk (gclk),
.d_en (cpu_enable),
.x_en (cpu_enable));
endmodule | 1 |
138,591 | data/full_repos/permissive/85002992/aexm/aexm_enable.v | 85,002,992 | aexm_enable.v | v | 106 | 68 | [] | [] | [] | null | line:15: before: "," | null | 1: b"%Error: data/full_repos/permissive/85002992/aexm/aexm_enable.v:13: Duplicate declaration of signal: 'cpu_mode_memop'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg cpu_mode_memop = 1'b0;\n ^~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/aexm/aexm_enable.v:9: ... Location of original declaration\n output cpu_mode_memop, \n ^~~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 302,572 | module | module aexm_enable(input CLK,
input grst,
input icache_busy,
input dcache_busy,
input dSTRLOD,
input dLOD,
input dSKIP,
input fSTALL,
output cpu_mode_memop,
output cpu_enable,
output icache_enable,
output dcache_enable);
reg cpu_mode_memop = 1'b0;
reg starter = 1'b0, grst_delay = 1'b0;
reg just_issued_dcache_command = 1'b0;
reg dcache_LOD_enable_reg = 1'b0,
dcache_LOD_enable_dly = 1'b0,
xLOD = 1'b0, xSTRLOD = 1'b0;
wire enter_memop_criterion,
exit_memop_criterion,
dcache_LOD_enable;
assign cpu_enable = (cpu_mode_memop && (! icache_busy)) ||
(starter);
assign enter_memop_criterion = cpu_mode_memop &&
(dSTRLOD || fSTALL) &&
(! dSKIP) &&
cpu_enable;
assign exit_memop_criterion = (!cpu_mode_memop) &&
(xLOD ?
((!icache_busy) &&
(!dcache_busy) &&
(dcache_LOD_enable_dly)) :
((!icache_busy) &&
(!dcache_busy) &&
(!just_issued_dcache_command)));
assign icache_enable = starter ||
(cpu_mode_memop ?
(cpu_enable && (! enter_memop_criterion)) :
(exit_memop_criterion));
assign dcache_enable = xLOD ?
dcache_LOD_enable :
(exit_memop_criterion && xSTRLOD);
assign dcache_LOD_enable = (!cpu_mode_memop) &&
(!dcache_LOD_enable_reg) &&
(!dcache_busy) &&
(!just_issued_dcache_command);
always @(posedge CLK)
if (!grst)
begin
grst_delay <= 0; starter <= 0;
cpu_mode_memop <= 0;
just_issued_dcache_command <= 0;
dcache_LOD_enable_reg <= 0; dcache_LOD_enable_dly <= 0; xLOD <= 0;
xSTRLOD <= 0;
end
else
begin
begin
grst_delay <= 1;
if (grst && !grst_delay)
starter <= 1;
else
starter <= 0;
end
just_issued_dcache_command <= dcache_enable;
if (cpu_enable)
begin
xSTRLOD <= dSTRLOD;
xLOD <= dLOD;
end
if (cpu_mode_memop)
begin
if (enter_memop_criterion)
cpu_mode_memop <= 0;
end
else
begin
if (exit_memop_criterion)
begin
cpu_mode_memop <= 1;
dcache_LOD_enable_reg <= 0;
dcache_LOD_enable_dly <= 0;
end
else
begin
if (dcache_LOD_enable)
dcache_LOD_enable_reg <= 1;
dcache_LOD_enable_dly <= dcache_LOD_enable_reg;
end
end
end
endmodule | module aexm_enable(input CLK,
input grst,
input icache_busy,
input dcache_busy,
input dSTRLOD,
input dLOD,
input dSKIP,
input fSTALL,
output cpu_mode_memop,
output cpu_enable,
output icache_enable,
output dcache_enable); |
reg cpu_mode_memop = 1'b0;
reg starter = 1'b0, grst_delay = 1'b0;
reg just_issued_dcache_command = 1'b0;
reg dcache_LOD_enable_reg = 1'b0,
dcache_LOD_enable_dly = 1'b0,
xLOD = 1'b0, xSTRLOD = 1'b0;
wire enter_memop_criterion,
exit_memop_criterion,
dcache_LOD_enable;
assign cpu_enable = (cpu_mode_memop && (! icache_busy)) ||
(starter);
assign enter_memop_criterion = cpu_mode_memop &&
(dSTRLOD || fSTALL) &&
(! dSKIP) &&
cpu_enable;
assign exit_memop_criterion = (!cpu_mode_memop) &&
(xLOD ?
((!icache_busy) &&
(!dcache_busy) &&
(dcache_LOD_enable_dly)) :
((!icache_busy) &&
(!dcache_busy) &&
(!just_issued_dcache_command)));
assign icache_enable = starter ||
(cpu_mode_memop ?
(cpu_enable && (! enter_memop_criterion)) :
(exit_memop_criterion));
assign dcache_enable = xLOD ?
dcache_LOD_enable :
(exit_memop_criterion && xSTRLOD);
assign dcache_LOD_enable = (!cpu_mode_memop) &&
(!dcache_LOD_enable_reg) &&
(!dcache_busy) &&
(!just_issued_dcache_command);
always @(posedge CLK)
if (!grst)
begin
grst_delay <= 0; starter <= 0;
cpu_mode_memop <= 0;
just_issued_dcache_command <= 0;
dcache_LOD_enable_reg <= 0; dcache_LOD_enable_dly <= 0; xLOD <= 0;
xSTRLOD <= 0;
end
else
begin
begin
grst_delay <= 1;
if (grst && !grst_delay)
starter <= 1;
else
starter <= 0;
end
just_issued_dcache_command <= dcache_enable;
if (cpu_enable)
begin
xSTRLOD <= dSTRLOD;
xLOD <= dLOD;
end
if (cpu_mode_memop)
begin
if (enter_memop_criterion)
cpu_mode_memop <= 0;
end
else
begin
if (exit_memop_criterion)
begin
cpu_mode_memop <= 1;
dcache_LOD_enable_reg <= 0;
dcache_LOD_enable_dly <= 0;
end
else
begin
if (dcache_LOD_enable)
dcache_LOD_enable_reg <= 1;
dcache_LOD_enable_dly <= dcache_LOD_enable_reg;
end
end
end
endmodule | 1 |
138,593 | data/full_repos/permissive/85002992/aexm/aexm_regf.v | 85,002,992 | aexm_regf.v | v | 185 | 75 | [] | [] | [] | [(1, 184)] | null | null | 1: b"%Error: data/full_repos/permissive/85002992/aexm/aexm_regf.v:168: Can't find definition of 'ram' in dotted scope/variable: 'RAM_A.ram'\n RAM_A.ram.r_data[i] <= $random;\n ^~~\n ... Known scopes under 'RAM_A': <no cells found>\n%Error: data/full_repos/permissive/85002992/aexm/aexm_regf.v:169: Can't find definition of 'ram' in dotted scope/variable: 'RAM_B.ram'\n RAM_B.ram.r_data[i] <= $random;\n ^~~\n ... Known scopes under 'RAM_B': <no cells found>\n%Error: data/full_repos/permissive/85002992/aexm/aexm_regf.v:170: Can't find definition of 'ram' in dotted scope/variable: 'RAM_D.ram'\n RAM_D.ram.r_data[i] <= $random;\n ^~~\n ... Known scopes under 'RAM_D': <no cells found>\n%Error: data/full_repos/permissive/85002992/aexm/aexm_regf.v:173: Can't find definition of 'ram' in dotted scope/variable: 'RAM_A.ram'\n RAM_A.ram.r_data[0] <= 32'd0;\n ^~~\n ... Known scopes under 'RAM_A': <no cells found>\n%Error: data/full_repos/permissive/85002992/aexm/aexm_regf.v:174: Can't find definition of 'ram' in dotted scope/variable: 'RAM_B.ram'\n RAM_B.ram.r_data[0] <= 32'd0;\n ^~~\n ... Known scopes under 'RAM_B': <no cells found>\n%Error: data/full_repos/permissive/85002992/aexm/aexm_regf.v:175: Can't find definition of 'ram' in dotted scope/variable: 'RAM_D.ram'\n RAM_D.ram.r_data[0] <= 32'd0;\n ^~~\n ... Known scopes under 'RAM_D': <no cells found>\n%Error: data/full_repos/permissive/85002992/aexm/aexm_regf.v:176: Can't find definition of 'ram' in dotted scope/variable: 'RAM_A.ram'\n RAM_A.ram.r_data[31] <= 32'd1;\n ^~~\n ... Known scopes under 'RAM_A': <no cells found>\n%Error: data/full_repos/permissive/85002992/aexm/aexm_regf.v:177: Can't find definition of 'ram' in dotted scope/variable: 'RAM_B.ram'\n RAM_B.ram.r_data[31] <= 32'd1;\n ^~~\n ... Known scopes under 'RAM_B': <no cells found>\n%Error: data/full_repos/permissive/85002992/aexm/aexm_regf.v:178: Can't find definition of 'ram' in dotted scope/variable: 'RAM_D.ram'\n RAM_D.ram.r_data[31] <= 32'd1;\n ^~~\n ... Known scopes under 'RAM_D': <no cells found>\n%Error: Exiting due to 9 error(s)\n" | 302,574 | module | module aexm_regf (
xREGA, xREGB, c_io_rg, aexm_dcache_datao,
xOPC, rRW, rRDWE, xRD, rMXDST, rMXDST_use_combined, MEMOP_MXDST, rPC,
rRESULT, rDWBSEL, aexm_dcache_datai, late_forward_D,
gclk, x_en, d_en,
dRA, dRB, dRD
);
output [31:0] xREGA, xREGB;
output [31:0] c_io_rg;
input [5:0] xOPC;
input [4:0] rRW, xRD;
input [1:0] rMXDST;
input MEMOP_MXDST;
input [31:2] rPC;
input [31:0] rRESULT;
input [3:0] rDWBSEL;
input [4:0] dRA, dRB, dRD;
input rMXDST_use_combined;
input rRDWE;
input late_forward_D;
output [31:0] aexm_dcache_datao;
input [31:0] aexm_dcache_datai;
input gclk, x_en, d_en;
wire [31:0] wDWBDI = aexm_dcache_datai;
reg [31:0] rDWBDI, xDWBDI;
always @(rDWBSEL or wDWBDI) begin
case (rDWBSEL)
4'h8: xDWBDI <= {24'd0, wDWBDI[31:24]};
4'h4: xDWBDI <= {24'd0, wDWBDI[23:16]};
4'h2: xDWBDI <= {24'd0, wDWBDI[15:8]};
4'h1: xDWBDI <= {24'd0, wDWBDI[7:0]};
4'hC: xDWBDI <= {16'd0, wDWBDI[31:16]};
4'h3: xDWBDI <= {16'd0, wDWBDI[15:0]};
4'hF: xDWBDI <= wDWBDI;
default: xDWBDI <= 32'hX;
endcase
end
wire [31:0] c_io_rg, c_io_rg_d;
reg [31:0] combined_input;
reg w_en;
wire [31:0] xREGA, xREGB, xREGD;
reg [31:0] rREGD;
wire [31:0] xWDAT;
wire do_write;
assign do_write = (rRDWE && w_en && (rMXDST != 2'o3));
assign xWDAT = rMXDST_use_combined ? combined_input : rRESULT;
iceram32 RAM_A(.RDATA(xREGA),
.RADDR({3'h0,dRA}),
.RE(d_en),
.RCLKE(1'b1),
.RCLK(!gclk),
.WDATA(xWDAT),
.MASK(0),
.WADDR({3'h0,rRW}),
.WE(do_write),
.WCLKE(1'b1),
.WCLK(!gclk));
iceram32 RAM_B(.RDATA(xREGB),
.RADDR({3'h0,dRB}),
.RE(d_en),
.RCLKE(1'b1),
.RCLK(!gclk),
.WDATA(xWDAT),
.MASK(0),
.WADDR({3'h0,rRW}),
.WE(do_write),
.WCLKE(1'b1),
.WCLK(!gclk));
iceram32 RAM_D(.RDATA(xREGD),
.RADDR({3'h0,dRD}),
.RE(d_en),
.RCLKE(1'b1),
.RCLK(!gclk),
.WDATA(xWDAT),
.MASK(0),
.WADDR({3'h0,rRW}),
.WE(do_write),
.WCLKE(1'b1),
.WCLK(!gclk));
always @(posedge gclk)
begin
rDWBDI <= xDWBDI;
w_en <= x_en;
if (MEMOP_MXDST)
combined_input <= rDWBDI;
else
combined_input <= {rPC,2'h0};
if (late_forward_D)
rREGD <= c_io_rg_d;
else
rREGD <= xREGD;
end
assign c_io_rg_d = ((rRW == dRD) && (rMXDST != 2'h2)) ?
rRESULT : rDWBDI;
assign c_io_rg = (((rRW == dRA) ||
(rRW == dRB)) &&
(rMXDST != 2'h2)) ?
rRESULT : rDWBDI;
reg [31:0] xDWBDO;
wire [31:0] xDST;
wire fDFWD_M = (rRW == xRD) & (rMXDST == 2'o2) & rRDWE;
wire fDFWD_R = (rRW == xRD) & (rMXDST == 2'o0) & rRDWE;
assign aexm_dcache_datao = xDWBDO;
assign xDST = (fDFWD_M) ? rDWBDI :
(fDFWD_R) ? rRESULT :
rREGD;
always @(xOPC or xDST)
case (xOPC[1:0])
2'h0: xDWBDO <= {(4){xDST[7:0]}};
2'h1: xDWBDO <= {(2){xDST[15:0]}};
2'h2: xDWBDO <= xDST;
default: xDWBDO <= 32'hX;
endcase
integer i;
initial begin
for (i=0; i<32; i=i+1) begin
RAM_A.ram.r_data[i] <= $random;
RAM_B.ram.r_data[i] <= $random;
RAM_D.ram.r_data[i] <= $random;
end
RAM_A.ram.r_data[0] <= 32'd0;
RAM_B.ram.r_data[0] <= 32'd0;
RAM_D.ram.r_data[0] <= 32'd0;
RAM_A.ram.r_data[31] <= 32'd1;
RAM_B.ram.r_data[31] <= 32'd1;
RAM_D.ram.r_data[31] <= 32'd1;
end
endmodule | module aexm_regf (
xREGA, xREGB, c_io_rg, aexm_dcache_datao,
xOPC, rRW, rRDWE, xRD, rMXDST, rMXDST_use_combined, MEMOP_MXDST, rPC,
rRESULT, rDWBSEL, aexm_dcache_datai, late_forward_D,
gclk, x_en, d_en,
dRA, dRB, dRD
); |
output [31:0] xREGA, xREGB;
output [31:0] c_io_rg;
input [5:0] xOPC;
input [4:0] rRW, xRD;
input [1:0] rMXDST;
input MEMOP_MXDST;
input [31:2] rPC;
input [31:0] rRESULT;
input [3:0] rDWBSEL;
input [4:0] dRA, dRB, dRD;
input rMXDST_use_combined;
input rRDWE;
input late_forward_D;
output [31:0] aexm_dcache_datao;
input [31:0] aexm_dcache_datai;
input gclk, x_en, d_en;
wire [31:0] wDWBDI = aexm_dcache_datai;
reg [31:0] rDWBDI, xDWBDI;
always @(rDWBSEL or wDWBDI) begin
case (rDWBSEL)
4'h8: xDWBDI <= {24'd0, wDWBDI[31:24]};
4'h4: xDWBDI <= {24'd0, wDWBDI[23:16]};
4'h2: xDWBDI <= {24'd0, wDWBDI[15:8]};
4'h1: xDWBDI <= {24'd0, wDWBDI[7:0]};
4'hC: xDWBDI <= {16'd0, wDWBDI[31:16]};
4'h3: xDWBDI <= {16'd0, wDWBDI[15:0]};
4'hF: xDWBDI <= wDWBDI;
default: xDWBDI <= 32'hX;
endcase
end
wire [31:0] c_io_rg, c_io_rg_d;
reg [31:0] combined_input;
reg w_en;
wire [31:0] xREGA, xREGB, xREGD;
reg [31:0] rREGD;
wire [31:0] xWDAT;
wire do_write;
assign do_write = (rRDWE && w_en && (rMXDST != 2'o3));
assign xWDAT = rMXDST_use_combined ? combined_input : rRESULT;
iceram32 RAM_A(.RDATA(xREGA),
.RADDR({3'h0,dRA}),
.RE(d_en),
.RCLKE(1'b1),
.RCLK(!gclk),
.WDATA(xWDAT),
.MASK(0),
.WADDR({3'h0,rRW}),
.WE(do_write),
.WCLKE(1'b1),
.WCLK(!gclk));
iceram32 RAM_B(.RDATA(xREGB),
.RADDR({3'h0,dRB}),
.RE(d_en),
.RCLKE(1'b1),
.RCLK(!gclk),
.WDATA(xWDAT),
.MASK(0),
.WADDR({3'h0,rRW}),
.WE(do_write),
.WCLKE(1'b1),
.WCLK(!gclk));
iceram32 RAM_D(.RDATA(xREGD),
.RADDR({3'h0,dRD}),
.RE(d_en),
.RCLKE(1'b1),
.RCLK(!gclk),
.WDATA(xWDAT),
.MASK(0),
.WADDR({3'h0,rRW}),
.WE(do_write),
.WCLKE(1'b1),
.WCLK(!gclk));
always @(posedge gclk)
begin
rDWBDI <= xDWBDI;
w_en <= x_en;
if (MEMOP_MXDST)
combined_input <= rDWBDI;
else
combined_input <= {rPC,2'h0};
if (late_forward_D)
rREGD <= c_io_rg_d;
else
rREGD <= xREGD;
end
assign c_io_rg_d = ((rRW == dRD) && (rMXDST != 2'h2)) ?
rRESULT : rDWBDI;
assign c_io_rg = (((rRW == dRA) ||
(rRW == dRB)) &&
(rMXDST != 2'h2)) ?
rRESULT : rDWBDI;
reg [31:0] xDWBDO;
wire [31:0] xDST;
wire fDFWD_M = (rRW == xRD) & (rMXDST == 2'o2) & rRDWE;
wire fDFWD_R = (rRW == xRD) & (rMXDST == 2'o0) & rRDWE;
assign aexm_dcache_datao = xDWBDO;
assign xDST = (fDFWD_M) ? rDWBDI :
(fDFWD_R) ? rRESULT :
rREGD;
always @(xOPC or xDST)
case (xOPC[1:0])
2'h0: xDWBDO <= {(4){xDST[7:0]}};
2'h1: xDWBDO <= {(2){xDST[15:0]}};
2'h2: xDWBDO <= xDST;
default: xDWBDO <= 32'hX;
endcase
integer i;
initial begin
for (i=0; i<32; i=i+1) begin
RAM_A.ram.r_data[i] <= $random;
RAM_B.ram.r_data[i] <= $random;
RAM_D.ram.r_data[i] <= $random;
end
RAM_A.ram.r_data[0] <= 32'd0;
RAM_B.ram.r_data[0] <= 32'd0;
RAM_D.ram.r_data[0] <= 32'd0;
RAM_A.ram.r_data[31] <= 32'd1;
RAM_B.ram.r_data[31] <= 32'd1;
RAM_D.ram.r_data[31] <= 32'd1;
end
endmodule | 1 |
138,595 | data/full_repos/permissive/85002992/cache/cpu_mcu2.v | 85,002,992 | cpu_mcu2.v | v | 378 | 76 | [] | [] | [] | null | line:32: before: "," | null | 1: b"%Error: data/full_repos/permissive/85002992/cache/cpu_mcu2.v:32: Duplicate declaration of signal: 'MMU_FAULT'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg MMU_FAULT = 1'b0, cache_busy = 1'b0,\n ^~~~~~~~~\n data/full_repos/permissive/85002992/cache/cpu_mcu2.v:30: ... Location of original declaration\n output MMU_FAULT,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/85002992/cache/cpu_mcu2.v:32: Duplicate declaration of signal: 'cache_busy'\n reg MMU_FAULT = 1'b0, cache_busy = 1'b0,\n ^~~~~~~~~~\n data/full_repos/permissive/85002992/cache/cpu_mcu2.v:7: ... Location of original declaration\n output cache_busy,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/cache/cpu_mcu2.v:33: Duplicate declaration of signal: 'mem_do_act'\n mem_do_act = 1'b0, mem_we = 1'b0,\n ^~~~~~~~~~\n data/full_repos/permissive/85002992/cache/cpu_mcu2.v:15: ... Location of original declaration\n output mem_do_act,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/cache/cpu_mcu2.v:33: Duplicate declaration of signal: 'mem_we'\n mem_do_act = 1'b0, mem_we = 1'b0,\n ^~~~~~\n data/full_repos/permissive/85002992/cache/cpu_mcu2.v:13: ... Location of original declaration\n output mem_we,\n ^~~~~~\n%Error: data/full_repos/permissive/85002992/cache/cpu_mcu2.v:34: Duplicate declaration of signal: 'dma_wrte'\n dma_wrte = 1'b0, dma_read = 1'b0;\n ^~~~~~~~\n data/full_repos/permissive/85002992/cache/cpu_mcu2.v:20: ... Location of original declaration\n output dma_wrte,\n ^~~~~~~~\n%Error: data/full_repos/permissive/85002992/cache/cpu_mcu2.v:34: Duplicate declaration of signal: 'dma_read'\n dma_wrte = 1'b0, dma_read = 1'b0;\n ^~~~~~~~\n data/full_repos/permissive/85002992/cache/cpu_mcu2.v:21: ... Location of original declaration\n output dma_read,\n ^~~~~~~~\n%Error: data/full_repos/permissive/85002992/cache/cpu_mcu2.v:35: Duplicate declaration of signal: 'cache_datai'\n reg [31:0] cache_datai = 32'd0,\n ^~~~~~~~~~~\n data/full_repos/permissive/85002992/cache/cpu_mcu2.v:5: ... Location of original declaration\n output [31:0] cache_datai, \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/cache/cpu_mcu2.v:36: Duplicate declaration of signal: 'mem_addr'\n mem_addr = 32'd0,\n ^~~~~~~~\n data/full_repos/permissive/85002992/cache/cpu_mcu2.v:12: ... Location of original declaration\n output [31:0] mem_addr,\n ^~~~~~~~\n%Error: data/full_repos/permissive/85002992/cache/cpu_mcu2.v:37: Duplicate declaration of signal: 'mem_dataintomem'\n mem_dataintomem = 32'd0;\n ^~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/cache/cpu_mcu2.v:16: ... Location of original declaration\n output [31:0] mem_dataintomem,\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n" | 302,576 | module | module snowball_cache(input CPU_CLK,
input MCU_CLK,
input [31:0] cache_precycle_addr,
input [31:0] cache_datao,
output [31:0] cache_datai,
input cache_precycle_we,
output cache_busy,
input cache_precycle_enable,
input cache_precycle_force_miss,
output [31:0] mem_addr,
output mem_we,
output [3:0] mem_we_array,
output mem_do_act,
output [31:0] mem_dataintomem,
input mem_ack,
input [31:0] mem_datafrommem,
output dma_wrte,
output dma_read,
input dma_wrte_ack,
input dma_read_ack,
input [31:0] dma_data_read,
input VMEM_ACT,
input cache_inhibit,
input fake_miss,
output MMU_FAULT,
input WE_TLB);
reg MMU_FAULT = 1'b0, cache_busy = 1'b0,
mem_do_act = 1'b0, mem_we = 1'b0,
dma_wrte = 1'b0, dma_read = 1'b0;
reg [31:0] cache_datai = 32'd0,
mem_addr = 32'd0,
mem_dataintomem = 32'd0;
reg vmem = 1'b0;
reg mcu_responded_trans = 1'b0,
mcu_active_trans = 1'b0;
reg cache_vld = 1'b0, cache_tlb = 1'b0,
tlb_en_sticky = 1'b0,
cache_en_sticky = 1'b0, cache_busy_real = 1'b0;
reg mcu_responded = 1'b0, mcu_responded_reg = 1'b0;
reg [31:0] cache_cycle_addr, data_tomem_trans;
reg cache_cycle_we, tlb_cycle_we;
reg mcu_we = 1'b0, tlb_we = 1'b0,
mem_do_act_reg = 1'b0, mcu_active_delay = 1'b0,
w_we_trans, w_tlb_trans, w_we_recv, w_tlb_recv,
mandatory_lookup_sig = 1'b0,
mandatory_lookup_pre_sig = 1'b0,
mandatory_lookup_sig_recv = 1'b0,
mandatory_lookup_exp = 1'b0,
mandatory_lookup_capture, datain_mux_dma,
cache_prev_we = 1'b0, mcu_active = 1'b0,
mcu_active_reg = 1'b0, write_other = 1'b1,
cache_cycle_force_miss_n;
reg [2:0] read_counter = 3'h0;
reg [31:0] data_mcu_trans = 0, data_mcu_trans_other = 0,
w_addr_trans, w_data_trans,
w_addr_recv, w_data_recv, dma_data_read_reg = 0;
reg [7:0] w_addr, cache_prev_idx;
wire [31:0] data_cache, wdata_data, wctag_data,
mem_dataintocpu;
wire cache_hit, w_MMU_FAULT;
wire [15:0] tlb_in_tag, tlb_in_mmu;
wire [15:0] vmem_rsp_tag, rsp_tag, mmu_req, mmu_vtag;
wire [23:0] req_tag;
wire [7:0] idx_pre, tlb_idx_pre, tlb_idx;
wire cache_work, wdata_we,
activate_tlb, activate_cache,
tlb_reinit, cache_reinit, mandatory_lookup,
mandatory_lookup_act, mem_lookup;
reg mcu_valid_data, capture_data;
assign mem_we_array = 4'b1100;
assign idx_pre = cache_precycle_addr[7:0];
assign tlb_idx_pre = cache_precycle_addr[15:8];
assign tlb_idx = cache_cycle_addr[15:8];
assign mmu_req = cache_cycle_addr[31:16];
assign cache_work = cache_precycle_enable && (! cache_inhibit);
assign vmem_rsp_tag = vmem ? rsp_tag : mmu_req;
assign tlb_in_tag = mem_dataintomem[31:16];
assign tlb_in_mmu = mem_dataintomem[15:0];
assign cache_hit = ((req_tag ^ {vmem_rsp_tag,tlb_idx}) ==
{(24){1'b0}}) ? cache_cycle_force_miss_n : 0;
assign w_MMU_FAULT = (mmu_vtag ^ mmu_req) != {(16){1'b0}} ? vmem : 0;
iceram32 cachedat(.RDATA(data_cache),
.RADDR(idx_pre),
.RE(cache_work),
.RCLKE(1'b1),
.RCLK(CPU_CLK),
.WDATA(wdata_data),
.MASK(0),
.WADDR(w_addr),
.WE(wdata_we),
.WCLKE(1'b1),
.WCLK(MCU_CLK));
wire [7:0] ignore_cachetag;
iceram32 cachetag(.RDATA({ignore_cachetag,req_tag}),
.RADDR(idx_pre),
.RE(cache_work),
.RCLKE(1'b1),
.RCLK(CPU_CLK),
.WDATA(wctag_data),
.MASK(0),
.WADDR(w_addr),
.WE(wdata_we),
.WCLKE(1'b1),
.WCLK(MCU_CLK));
iceram16 tlb(.RDATA(rsp_tag),
.RADDR(tlb_idx_pre),
.RE(cache_work),
.RCLKE(1'b1),
.RCLK(CPU_CLK),
.WDATA(tlb_in_tag),
.MASK({(16){1'b0}}),
.WADDR(mem_addr[7:0]),
.WE(tlb_we),
.WCLKE(1'b1),
.WCLK(MCU_CLK));
iceram16 tlbtag(.RDATA(mmu_vtag),
.RADDR(tlb_idx_pre),
.RE(cache_work),
.RCLKE(1'b1),
.RCLK(CPU_CLK),
.WDATA(tlb_in_mmu),
.MASK({(16){1'b0}}),
.WADDR(mem_addr[7:0]),
.WE(tlb_we),
.WCLKE(1'b1),
.WCLK(MCU_CLK));
assign cache_reinit = cache_en_sticky && (mcu_responded ||
((! cache_busy_real) &&
(! fake_miss)));
assign tlb_reinit = tlb_en_sticky && (mcu_responded ||
((! cache_busy_real) &&
(! fake_miss)));
assign mandatory_lookup = ((mandatory_lookup_sig_recv ^
mandatory_lookup_exp) &&
cache_prev_we) ||
(cache_vld && cache_cycle_we);
assign mandatory_lookup_act = mandatory_lookup_capture &&
(cache_prev_idx == cache_cycle_addr[7:0]);
assign activate_cache = (cache_work && (! (cache_busy || mem_lookup))) ||
cache_reinit;
assign activate_tlb = (WE_TLB && (! (cache_busy || mem_lookup))) ||
tlb_reinit;
assign mem_lookup = (cache_vld && (!w_MMU_FAULT) &&
((! cache_hit) ||
cache_cycle_we ||
mandatory_lookup_act)) ||
cache_tlb;
always @(posedge CPU_CLK)
begin
vmem <= VMEM_ACT;
MMU_FAULT <= w_MMU_FAULT;
if (cache_work || WE_TLB)
begin
cache_cycle_force_miss_n <= ! cache_precycle_force_miss;
cache_cycle_addr <= cache_precycle_addr;
cache_cycle_we <= cache_precycle_we;
data_tomem_trans <= cache_datao;
tlb_cycle_we <= WE_TLB;
mandatory_lookup_capture <= mandatory_lookup;
end
if (cache_vld && (! cache_cycle_we))
begin
if (cache_hit)
cache_datai <= data_cache;
else
cache_datai <= data_mcu_trans_other;
end
else if (mcu_responded)
cache_datai <= data_mcu_trans;
begin
w_addr_trans <= {vmem_rsp_tag,cache_cycle_addr[15:0]};
w_data_trans <= data_tomem_trans;
w_we_trans <= cache_cycle_we;
w_tlb_trans <= tlb_cycle_we;
end
if (mem_lookup)
begin
mcu_active_trans <= !mcu_active_trans;
cache_busy_real <= 1;
cache_prev_we <= cache_cycle_we;
cache_prev_idx <= cache_cycle_addr[7:0];
if (cache_cycle_we)
begin
mandatory_lookup_exp <= !mandatory_lookup_exp;
end
end
else
begin
if (mcu_responded)
cache_busy_real <= 0;
end
if (mem_lookup || fake_miss)
cache_busy <= 1;
else
if ((cache_busy_real && mcu_responded) ||
(! cache_busy_real))
cache_busy <= 0;
if (activate_cache || activate_tlb)
begin
if (activate_cache)
begin
cache_vld <= 1;
cache_en_sticky <= 0;
end
else if (activate_tlb)
begin
cache_tlb <= 1;
tlb_en_sticky <= 0;
end
end
else
begin
cache_vld <= 0;
cache_tlb <= 0;
if (cache_work && (! tlb_en_sticky))
cache_en_sticky <= 1;
if (WE_TLB && (! cache_en_sticky))
tlb_en_sticky <= 1;
end
mcu_responded <= (mcu_responded_trans ^ mcu_responded_reg) &&
!mcu_responded;
if (mcu_responded)
mcu_responded_reg <= !mcu_responded_reg;
mandatory_lookup_sig_recv <= mandatory_lookup_sig;
end
assign mem_dataintocpu = datain_mux_dma ?
dma_data_read_reg : mem_datafrommem;
assign wdata_data = mem_dataintomem | (write_other ?
data_mcu_trans_other :
data_mcu_trans);
assign wdata_we = mcu_active_delay || mcu_valid_data;
assign wctag_data = mem_addr[31:8];
always @(read_counter)
case (read_counter)
3'd5: begin mcu_valid_data <= 0; capture_data <= 1; end
3'd6: begin mcu_valid_data <= 1; capture_data <= 0; end
3'd7: begin mcu_valid_data <= 1; capture_data <= 0; end
default: begin mcu_valid_data <= 0; capture_data <= 0; end
endcase
always @(posedge MCU_CLK)
begin
mcu_active <= (mcu_active_trans ^ mcu_active_reg) && !mcu_active;
if (mcu_active)
mcu_active_reg <= !mcu_active_reg;
mcu_active_delay <= mcu_active;
if (mcu_active_delay && mcu_we)
mandatory_lookup_pre_sig <= !mandatory_lookup_pre_sig;
mandatory_lookup_sig <= mandatory_lookup_pre_sig;
begin
w_data_recv <= w_data_trans;
w_addr_recv <= w_addr_trans;
w_we_recv <= w_we_trans;
w_tlb_recv <= w_tlb_trans;
end
if (mcu_active)
begin
mem_do_act <= (w_addr_recv[31:30] == 2'b00);
dma_wrte <= (w_addr_recv[31:30] == 2'b11) && ( w_we_recv);
dma_read <= (w_addr_recv[31:30] == 2'b11) && (!w_we_recv);
datain_mux_dma <= (w_addr_recv[31:30] == 2'b11) || w_we_recv;
if (w_we_recv | w_tlb_recv)
mem_dataintomem <= w_data_recv;
mem_addr <= w_addr_recv;
mcu_we <= w_we_recv;
tlb_we <= w_tlb_recv;
mem_we <= w_we_recv || w_tlb_recv;
end
else
begin
tlb_we <= 0;
if (mem_ack)
begin
mem_do_act <= 0;
mem_dataintomem <= 0;
mem_we <= 0;
end
if (dma_wrte_ack)
dma_wrte <= 0;
if (dma_read_ack)
dma_read <= 0;
end
mem_do_act_reg <= mem_do_act;
if ((mem_ack || dma_read_ack) &&
(! mem_we))
read_counter <= 3'd2;
else
if (read_counter != 3'd0)
read_counter <= read_counter +1;
if (mcu_active)
begin
data_mcu_trans_other <= 0;
dma_data_read_reg <= 0;
w_addr <= w_addr_recv[7:0];
end
else
begin
if (!write_other)
begin
data_mcu_trans_other <= mem_dataintocpu;
w_addr <= {w_addr[7:1],(~w_addr[0])};
end
if (dma_read_ack)
dma_data_read_reg <= dma_data_read;
end
if (capture_data)
begin
data_mcu_trans <= mem_dataintocpu;
write_other <= 0;
end
else
begin
write_other <= 1;
end
if (((mem_ack || dma_wrte_ack) && mem_we) ||
(capture_data))
mcu_responded_trans <= !mcu_responded_trans;
end
endmodule | module snowball_cache(input CPU_CLK,
input MCU_CLK,
input [31:0] cache_precycle_addr,
input [31:0] cache_datao,
output [31:0] cache_datai,
input cache_precycle_we,
output cache_busy,
input cache_precycle_enable,
input cache_precycle_force_miss,
output [31:0] mem_addr,
output mem_we,
output [3:0] mem_we_array,
output mem_do_act,
output [31:0] mem_dataintomem,
input mem_ack,
input [31:0] mem_datafrommem,
output dma_wrte,
output dma_read,
input dma_wrte_ack,
input dma_read_ack,
input [31:0] dma_data_read,
input VMEM_ACT,
input cache_inhibit,
input fake_miss,
output MMU_FAULT,
input WE_TLB); |
reg MMU_FAULT = 1'b0, cache_busy = 1'b0,
mem_do_act = 1'b0, mem_we = 1'b0,
dma_wrte = 1'b0, dma_read = 1'b0;
reg [31:0] cache_datai = 32'd0,
mem_addr = 32'd0,
mem_dataintomem = 32'd0;
reg vmem = 1'b0;
reg mcu_responded_trans = 1'b0,
mcu_active_trans = 1'b0;
reg cache_vld = 1'b0, cache_tlb = 1'b0,
tlb_en_sticky = 1'b0,
cache_en_sticky = 1'b0, cache_busy_real = 1'b0;
reg mcu_responded = 1'b0, mcu_responded_reg = 1'b0;
reg [31:0] cache_cycle_addr, data_tomem_trans;
reg cache_cycle_we, tlb_cycle_we;
reg mcu_we = 1'b0, tlb_we = 1'b0,
mem_do_act_reg = 1'b0, mcu_active_delay = 1'b0,
w_we_trans, w_tlb_trans, w_we_recv, w_tlb_recv,
mandatory_lookup_sig = 1'b0,
mandatory_lookup_pre_sig = 1'b0,
mandatory_lookup_sig_recv = 1'b0,
mandatory_lookup_exp = 1'b0,
mandatory_lookup_capture, datain_mux_dma,
cache_prev_we = 1'b0, mcu_active = 1'b0,
mcu_active_reg = 1'b0, write_other = 1'b1,
cache_cycle_force_miss_n;
reg [2:0] read_counter = 3'h0;
reg [31:0] data_mcu_trans = 0, data_mcu_trans_other = 0,
w_addr_trans, w_data_trans,
w_addr_recv, w_data_recv, dma_data_read_reg = 0;
reg [7:0] w_addr, cache_prev_idx;
wire [31:0] data_cache, wdata_data, wctag_data,
mem_dataintocpu;
wire cache_hit, w_MMU_FAULT;
wire [15:0] tlb_in_tag, tlb_in_mmu;
wire [15:0] vmem_rsp_tag, rsp_tag, mmu_req, mmu_vtag;
wire [23:0] req_tag;
wire [7:0] idx_pre, tlb_idx_pre, tlb_idx;
wire cache_work, wdata_we,
activate_tlb, activate_cache,
tlb_reinit, cache_reinit, mandatory_lookup,
mandatory_lookup_act, mem_lookup;
reg mcu_valid_data, capture_data;
assign mem_we_array = 4'b1100;
assign idx_pre = cache_precycle_addr[7:0];
assign tlb_idx_pre = cache_precycle_addr[15:8];
assign tlb_idx = cache_cycle_addr[15:8];
assign mmu_req = cache_cycle_addr[31:16];
assign cache_work = cache_precycle_enable && (! cache_inhibit);
assign vmem_rsp_tag = vmem ? rsp_tag : mmu_req;
assign tlb_in_tag = mem_dataintomem[31:16];
assign tlb_in_mmu = mem_dataintomem[15:0];
assign cache_hit = ((req_tag ^ {vmem_rsp_tag,tlb_idx}) ==
{(24){1'b0}}) ? cache_cycle_force_miss_n : 0;
assign w_MMU_FAULT = (mmu_vtag ^ mmu_req) != {(16){1'b0}} ? vmem : 0;
iceram32 cachedat(.RDATA(data_cache),
.RADDR(idx_pre),
.RE(cache_work),
.RCLKE(1'b1),
.RCLK(CPU_CLK),
.WDATA(wdata_data),
.MASK(0),
.WADDR(w_addr),
.WE(wdata_we),
.WCLKE(1'b1),
.WCLK(MCU_CLK));
wire [7:0] ignore_cachetag;
iceram32 cachetag(.RDATA({ignore_cachetag,req_tag}),
.RADDR(idx_pre),
.RE(cache_work),
.RCLKE(1'b1),
.RCLK(CPU_CLK),
.WDATA(wctag_data),
.MASK(0),
.WADDR(w_addr),
.WE(wdata_we),
.WCLKE(1'b1),
.WCLK(MCU_CLK));
iceram16 tlb(.RDATA(rsp_tag),
.RADDR(tlb_idx_pre),
.RE(cache_work),
.RCLKE(1'b1),
.RCLK(CPU_CLK),
.WDATA(tlb_in_tag),
.MASK({(16){1'b0}}),
.WADDR(mem_addr[7:0]),
.WE(tlb_we),
.WCLKE(1'b1),
.WCLK(MCU_CLK));
iceram16 tlbtag(.RDATA(mmu_vtag),
.RADDR(tlb_idx_pre),
.RE(cache_work),
.RCLKE(1'b1),
.RCLK(CPU_CLK),
.WDATA(tlb_in_mmu),
.MASK({(16){1'b0}}),
.WADDR(mem_addr[7:0]),
.WE(tlb_we),
.WCLKE(1'b1),
.WCLK(MCU_CLK));
assign cache_reinit = cache_en_sticky && (mcu_responded ||
((! cache_busy_real) &&
(! fake_miss)));
assign tlb_reinit = tlb_en_sticky && (mcu_responded ||
((! cache_busy_real) &&
(! fake_miss)));
assign mandatory_lookup = ((mandatory_lookup_sig_recv ^
mandatory_lookup_exp) &&
cache_prev_we) ||
(cache_vld && cache_cycle_we);
assign mandatory_lookup_act = mandatory_lookup_capture &&
(cache_prev_idx == cache_cycle_addr[7:0]);
assign activate_cache = (cache_work && (! (cache_busy || mem_lookup))) ||
cache_reinit;
assign activate_tlb = (WE_TLB && (! (cache_busy || mem_lookup))) ||
tlb_reinit;
assign mem_lookup = (cache_vld && (!w_MMU_FAULT) &&
((! cache_hit) ||
cache_cycle_we ||
mandatory_lookup_act)) ||
cache_tlb;
always @(posedge CPU_CLK)
begin
vmem <= VMEM_ACT;
MMU_FAULT <= w_MMU_FAULT;
if (cache_work || WE_TLB)
begin
cache_cycle_force_miss_n <= ! cache_precycle_force_miss;
cache_cycle_addr <= cache_precycle_addr;
cache_cycle_we <= cache_precycle_we;
data_tomem_trans <= cache_datao;
tlb_cycle_we <= WE_TLB;
mandatory_lookup_capture <= mandatory_lookup;
end
if (cache_vld && (! cache_cycle_we))
begin
if (cache_hit)
cache_datai <= data_cache;
else
cache_datai <= data_mcu_trans_other;
end
else if (mcu_responded)
cache_datai <= data_mcu_trans;
begin
w_addr_trans <= {vmem_rsp_tag,cache_cycle_addr[15:0]};
w_data_trans <= data_tomem_trans;
w_we_trans <= cache_cycle_we;
w_tlb_trans <= tlb_cycle_we;
end
if (mem_lookup)
begin
mcu_active_trans <= !mcu_active_trans;
cache_busy_real <= 1;
cache_prev_we <= cache_cycle_we;
cache_prev_idx <= cache_cycle_addr[7:0];
if (cache_cycle_we)
begin
mandatory_lookup_exp <= !mandatory_lookup_exp;
end
end
else
begin
if (mcu_responded)
cache_busy_real <= 0;
end
if (mem_lookup || fake_miss)
cache_busy <= 1;
else
if ((cache_busy_real && mcu_responded) ||
(! cache_busy_real))
cache_busy <= 0;
if (activate_cache || activate_tlb)
begin
if (activate_cache)
begin
cache_vld <= 1;
cache_en_sticky <= 0;
end
else if (activate_tlb)
begin
cache_tlb <= 1;
tlb_en_sticky <= 0;
end
end
else
begin
cache_vld <= 0;
cache_tlb <= 0;
if (cache_work && (! tlb_en_sticky))
cache_en_sticky <= 1;
if (WE_TLB && (! cache_en_sticky))
tlb_en_sticky <= 1;
end
mcu_responded <= (mcu_responded_trans ^ mcu_responded_reg) &&
!mcu_responded;
if (mcu_responded)
mcu_responded_reg <= !mcu_responded_reg;
mandatory_lookup_sig_recv <= mandatory_lookup_sig;
end
assign mem_dataintocpu = datain_mux_dma ?
dma_data_read_reg : mem_datafrommem;
assign wdata_data = mem_dataintomem | (write_other ?
data_mcu_trans_other :
data_mcu_trans);
assign wdata_we = mcu_active_delay || mcu_valid_data;
assign wctag_data = mem_addr[31:8];
always @(read_counter)
case (read_counter)
3'd5: begin mcu_valid_data <= 0; capture_data <= 1; end
3'd6: begin mcu_valid_data <= 1; capture_data <= 0; end
3'd7: begin mcu_valid_data <= 1; capture_data <= 0; end
default: begin mcu_valid_data <= 0; capture_data <= 0; end
endcase
always @(posedge MCU_CLK)
begin
mcu_active <= (mcu_active_trans ^ mcu_active_reg) && !mcu_active;
if (mcu_active)
mcu_active_reg <= !mcu_active_reg;
mcu_active_delay <= mcu_active;
if (mcu_active_delay && mcu_we)
mandatory_lookup_pre_sig <= !mandatory_lookup_pre_sig;
mandatory_lookup_sig <= mandatory_lookup_pre_sig;
begin
w_data_recv <= w_data_trans;
w_addr_recv <= w_addr_trans;
w_we_recv <= w_we_trans;
w_tlb_recv <= w_tlb_trans;
end
if (mcu_active)
begin
mem_do_act <= (w_addr_recv[31:30] == 2'b00);
dma_wrte <= (w_addr_recv[31:30] == 2'b11) && ( w_we_recv);
dma_read <= (w_addr_recv[31:30] == 2'b11) && (!w_we_recv);
datain_mux_dma <= (w_addr_recv[31:30] == 2'b11) || w_we_recv;
if (w_we_recv | w_tlb_recv)
mem_dataintomem <= w_data_recv;
mem_addr <= w_addr_recv;
mcu_we <= w_we_recv;
tlb_we <= w_tlb_recv;
mem_we <= w_we_recv || w_tlb_recv;
end
else
begin
tlb_we <= 0;
if (mem_ack)
begin
mem_do_act <= 0;
mem_dataintomem <= 0;
mem_we <= 0;
end
if (dma_wrte_ack)
dma_wrte <= 0;
if (dma_read_ack)
dma_read <= 0;
end
mem_do_act_reg <= mem_do_act;
if ((mem_ack || dma_read_ack) &&
(! mem_we))
read_counter <= 3'd2;
else
if (read_counter != 3'd0)
read_counter <= read_counter +1;
if (mcu_active)
begin
data_mcu_trans_other <= 0;
dma_data_read_reg <= 0;
w_addr <= w_addr_recv[7:0];
end
else
begin
if (!write_other)
begin
data_mcu_trans_other <= mem_dataintocpu;
w_addr <= {w_addr[7:1],(~w_addr[0])};
end
if (dma_read_ack)
dma_data_read_reg <= dma_data_read;
end
if (capture_data)
begin
data_mcu_trans <= mem_dataintocpu;
write_other <= 0;
end
else
begin
write_other <= 1;
end
if (((mem_ack || dma_wrte_ack) && mem_we) ||
(capture_data))
mcu_responded_trans <= !mcu_responded_trans;
end
endmodule | 1 |
138,597 | data/full_repos/permissive/85002992/hyperfabric/lsab.v | 85,002,992 | lsab.v | v | 737 | 77 | [] | [] | [] | null | line:43: before: "," | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/85002992/hyperfabric/lsab.v:382: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'lsab_cr\'\nmodule lsab_cr(input CLK,\n ^~~~~~~\n : ... Top module \'lsab_cw\'\nmodule lsab_cw(input CLK,\n ^~~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:43: Duplicate declaration of signal: \'EMPTY_0\'\n reg EMPTY_0 = 1\'b1, EMPTY_1 = 1\'b1,\n ^~~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:27: ... Location of original declaration\n output EMPTY_0,\n ^~~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:43: Duplicate declaration of signal: \'EMPTY_1\'\n reg EMPTY_0 = 1\'b1, EMPTY_1 = 1\'b1,\n ^~~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:28: ... Location of original declaration\n output EMPTY_1,\n ^~~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:44: Duplicate declaration of signal: \'EMPTY_2\'\n EMPTY_2 = 1\'b1, EMPTY_3 = 1\'b1,\n ^~~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:29: ... Location of original declaration\n output EMPTY_2,\n ^~~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:44: Duplicate declaration of signal: \'EMPTY_3\'\n EMPTY_2 = 1\'b1, EMPTY_3 = 1\'b1,\n ^~~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:30: ... Location of original declaration\n output EMPTY_3,\n ^~~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:45: Duplicate declaration of signal: \'STOP_0\'\n STOP_0 = 1\'b1, STOP_1 = 1\'b1,\n ^~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:31: ... Location of original declaration\n output STOP_0,\n ^~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:45: Duplicate declaration of signal: \'STOP_1\'\n STOP_0 = 1\'b1, STOP_1 = 1\'b1,\n ^~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:32: ... Location of original declaration\n output STOP_1,\n ^~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:46: Duplicate declaration of signal: \'STOP_2\'\n STOP_2 = 1\'b1, STOP_3 = 1\'b1;\n ^~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:33: ... Location of original declaration\n output STOP_2,\n ^~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:46: Duplicate declaration of signal: \'STOP_3\'\n STOP_2 = 1\'b1, STOP_3 = 1\'b1;\n ^~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:34: ... Location of original declaration\n output STOP_3,\n ^~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:408: Duplicate declaration of signal: \'OUT_0\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg [31:0] OUT_0 = 32\'d0, OUT_1 = 32\'d0,\n ^~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:392: ... Location of original declaration\n output [31:0] OUT_0,\n ^~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:408: Duplicate declaration of signal: \'OUT_1\'\n reg [31:0] OUT_0 = 32\'d0, OUT_1 = 32\'d0,\n ^~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:393: ... Location of original declaration\n output [31:0] OUT_1,\n ^~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:409: Duplicate declaration of signal: \'OUT_2\'\n OUT_2 = 32\'d0, OUT_3 = 32\'d0;\n ^~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:394: ... Location of original declaration\n output [31:0] OUT_2,\n ^~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:409: Duplicate declaration of signal: \'OUT_3\'\n OUT_2 = 32\'d0, OUT_3 = 32\'d0;\n ^~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:395: ... Location of original declaration\n output [31:0] OUT_3,\n ^~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:410: Duplicate declaration of signal: \'BFULL\'\n reg BFULL = 1\'b0;\n ^~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:396: ... Location of original declaration\n output BFULL,\n ^~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:411: Duplicate declaration of signal: \'DEV_0_ERR_ACK\'\n reg DEV_0_ERR_ACK = 1\'b0,\n ^~~~~~~~~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:402: ... Location of original declaration\n output DEV_0_ERR_ACK,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:412: Duplicate declaration of signal: \'DEV_1_ERR_ACK\'\n DEV_1_ERR_ACK = 1\'b0,\n ^~~~~~~~~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:403: ... Location of original declaration\n output DEV_1_ERR_ACK,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:413: Duplicate declaration of signal: \'DEV_2_ERR_ACK\'\n DEV_2_ERR_ACK = 1\'b0,\n ^~~~~~~~~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:404: ... Location of original declaration\n output DEV_2_ERR_ACK,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:414: Duplicate declaration of signal: \'DEV_3_ERR_ACK\'\n DEV_3_ERR_ACK = 1\'b0;\n ^~~~~~~~~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:405: ... Location of original declaration\n output DEV_3_ERR_ACK,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:415: Duplicate declaration of signal: \'DEVERR\'\n reg DEVERR = 1\'b0;\n ^~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:406: ... Location of original declaration\n output DEVERR,\n ^~~~~~\n%Error: Exiting due to 18 error(s), 1 warning(s)\n' | 302,578 | module | module lsab_cr(input CLK,
input RST,
input READ,
input WRITE0,
input WRITE1,
input WRITE2,
input WRITE3,
input [1:0] READ_FIFO,
input [1:0] WRITE_FIFO,
input [31:0] IN_0,
input [31:0] IN_1,
input [31:0] IN_2,
input [31:0] IN_3,
input INT_IN_0,
input INT_IN_1,
input INT_IN_2,
input INT_IN_3,
input CAREOF_INT_0,
input CAREOF_INT_1,
input CAREOF_INT_2,
input CAREOF_INT_3,
input [24:0] ANCILL_IN_0,
input [24:0] ANCILL_IN_1,
input [24:0] ANCILL_IN_2,
input [24:0] ANCILL_IN_3,
output reg [31:0] OUT,
output EMPTY_0,
output EMPTY_1,
output EMPTY_2,
output EMPTY_3,
output STOP_0,
output STOP_1,
output STOP_2,
output STOP_3,
output reg INT_OUT_0,
output reg INT_OUT_1,
output reg INT_OUT_2,
output reg INT_OUT_3,
output reg [24:0] ANCILL_OUT_0,
output reg [24:0] ANCILL_OUT_1,
output reg [24:0] ANCILL_OUT_2,
output reg [24:0] ANCILL_OUT_3);
reg EMPTY_0 = 1'b1, EMPTY_1 = 1'b1,
EMPTY_2 = 1'b1, EMPTY_3 = 1'b1,
STOP_0 = 1'b1, STOP_1 = 1'b1,
STOP_2 = 1'b1, STOP_3 = 1'b1;
reg full_0 = 1'b0, full_1 = 1'b0,
full_2 = 1'b0, full_3 = 1'b0;
reg [5:0] len_0 = 6'h0, len_1 = 6'h0,
len_2 = 6'h0, len_3 = 6'h0;
reg [5:0] write_addr_0 = 6'h0, write_addr_1 = 6'h0,
write_addr_2 = 6'h0, write_addr_3 = 6'h0;
reg [5:0] read_addr_0 = 6'h0, read_addr_1 = 6'h0,
read_addr_2 = 6'h0, read_addr_3 = 6'h0;
reg re_prev;
wire read_0, read_1, read_2, read_3;
wire write_0, write_1, write_2, write_3;
wire do_read_0, do_read_1, do_read_2, do_read_3;
wire do_write_0, do_write_1, do_write_2, do_write_3;
reg become_empty_0, become_empty_1,
become_empty_2, become_empty_3;
reg become_full_0, become_full_1,
become_full_2, become_full_3;
reg [5:0] become_len_0, become_len_1,
become_len_2, become_len_3;
reg [1:0] intbuff_raddr_0 = 2'h1, intbuff_raddr_trail_0 = 2'h0,
intbuff_waddr_0 = 2'h1,
intbuff_raddr_1 = 2'h1, intbuff_raddr_trail_1 = 2'h0,
intbuff_waddr_1 = 2'h1,
intbuff_raddr_2 = 2'h1, intbuff_raddr_trail_2 = 2'h0,
intbuff_waddr_2 = 2'h1,
intbuff_raddr_3 = 2'h1, intbuff_raddr_trail_3 = 2'h0,
intbuff_waddr_3 = 2'h1;
wire intbuff_int_det_0, intbuff_int_0,
intbuff_empty_0, intbuff_full_0,
intbuff_int_det_1, intbuff_int_1,
intbuff_empty_1, intbuff_full_1,
intbuff_int_det_2, intbuff_int_2,
intbuff_empty_2, intbuff_full_2,
intbuff_int_det_3, intbuff_int_3,
intbuff_empty_3, intbuff_full_3;
reg [5:0] intbuff_0[3:0], intbuff_1[3:0], intbuff_2[3:0],
intbuff_3[3:0];
reg [24:0] ancbuff_0[3:0], ancbuff_1[3:0], ancbuff_2[3:0],
ancbuff_3[3:0];
wire [31:0] out_mem;
reg [31:0] in_mem;
reg [7:0] write_addr, read_addr;
reg we, re;
assign read_0 = READ && (READ_FIFO == 2'h0);
assign read_1 = READ && (READ_FIFO == 2'h1);
assign read_2 = READ && (READ_FIFO == 2'h2);
assign read_3 = READ && (READ_FIFO == 2'h3);
assign write_0 = WRITE0 && (WRITE_FIFO == 2'h0);
assign write_1 = WRITE1 && (WRITE_FIFO == 2'h1);
assign write_2 = WRITE2 && (WRITE_FIFO == 2'h2);
assign write_3 = WRITE3 && (WRITE_FIFO == 2'h3);
assign do_write_0 = full_0 ? 0 : write_0;
assign do_write_1 = full_1 ? 0 : write_1;
assign do_write_2 = full_2 ? 0 : write_2;
assign do_write_3 = full_3 ? 0 : write_3;
assign do_read_0 = STOP_0 ? 0 : read_0;
assign do_read_1 = STOP_1 ? 0 : read_1;
assign do_read_2 = STOP_2 ? 0 : read_2;
assign do_read_3 = STOP_3 ? 0 : read_3;
always @(len_0 or do_read_0 or do_write_0 or full_0 or EMPTY_0)
case ({len_0,do_read_0,do_write_0})
{6'h3f,2'b10}: begin become_full_0 <= 0; become_empty_0 <= 0; end
{6'h3e,2'b01}: begin become_full_0 <= 1; become_empty_0 <= 0; end
{6'h01,2'b10}: begin become_full_0 <= 0; become_empty_0 <= 1; end
{6'h00,2'b01}: begin become_full_0 <= 0; become_empty_0 <= 0; end
default: begin become_full_0 <= full_0; become_empty_0 <= EMPTY_0; end
endcase
always @(len_1 or do_read_1 or do_write_1 or full_1 or EMPTY_1)
case ({len_1,do_read_1,do_write_1})
{6'h3f,2'b10}: begin become_full_1 <= 0; become_empty_1 <= 0; end
{6'h3e,2'b01}: begin become_full_1 <= 1; become_empty_1 <= 0; end
{6'h01,2'b10}: begin become_full_1 <= 0; become_empty_1 <= 1; end
{6'h00,2'b01}: begin become_full_1 <= 0; become_empty_1 <= 0; end
default: begin become_full_1 <= full_1; become_empty_1 <= EMPTY_1; end
endcase
always @(len_2 or do_read_2 or do_write_2 or full_2 or EMPTY_2)
case ({len_2,do_read_2,do_write_2})
{6'h3f,2'b10}: begin become_full_2 <= 0; become_empty_2 <= 0; end
{6'h3e,2'b01}: begin become_full_2 <= 1; become_empty_2 <= 0; end
{6'h01,2'b10}: begin become_full_2 <= 0; become_empty_2 <= 1; end
{6'h00,2'b01}: begin become_full_2 <= 0; become_empty_2 <= 0; end
default: begin become_full_2 <= full_2; become_empty_2 <= EMPTY_2; end
endcase
always @(len_3 or do_read_3 or do_write_3 or full_3 or EMPTY_3)
case ({len_3,do_read_3,do_write_3})
{6'h3f,2'b10}: begin become_full_3 <= 0; become_empty_3 <= 0; end
{6'h3e,2'b01}: begin become_full_3 <= 1; become_empty_3 <= 0; end
{6'h01,2'b10}: begin become_full_3 <= 0; become_empty_3 <= 1; end
{6'h00,2'b01}: begin become_full_3 <= 0; become_empty_3 <= 0; end
default: begin become_full_3 <= full_3; become_empty_3 <= EMPTY_3; end
endcase
always @(do_read_0 or do_write_0 or len_0)
case ({do_read_0,do_write_0})
2'b10: become_len_0 <= len_0 -1;
2'b01: become_len_0 <= len_0 +1;
default: become_len_0 <= len_0;
endcase
always @(do_read_1 or do_write_1 or len_1)
case ({do_read_1,do_write_1})
2'b10: become_len_1 <= len_1 -1;
2'b01: become_len_1 <= len_1 +1;
default: become_len_1 <= len_1;
endcase
always @(do_read_2 or do_write_2 or len_2)
case ({do_read_2,do_write_2})
2'b10: become_len_2 <= len_2 -1;
2'b01: become_len_2 <= len_2 +1;
default: become_len_2 <= len_2;
endcase
always @(do_read_3 or do_write_3 or len_3)
case ({do_read_3,do_write_3})
2'b10: become_len_3 <= len_3 -1;
2'b01: become_len_3 <= len_3 +1;
default: become_len_3 <= len_3;
endcase
always @(WRITE_FIFO or
IN_0 or IN_1 or IN_2 or IN_3 or
write_addr_0 or write_addr_1 or write_addr_2 or write_addr_3 or
do_write_0 or do_write_1 or do_write_2 or do_write_3)
case (WRITE_FIFO)
2'b00: begin
in_mem <= IN_0;
write_addr <= {2'b00,write_addr_0};
we <= do_write_0;
end
2'b01: begin
in_mem <= IN_1;
write_addr <= {2'b01,write_addr_1};
we <= do_write_1;
end
2'b10: begin
in_mem <= IN_2;
write_addr <= {2'b10,write_addr_2};
we <= do_write_2;
end
2'b11: begin
in_mem <= IN_3;
write_addr <= {2'b11,write_addr_3};
we <= do_write_3;
end
endcase
always @(READ_FIFO or
read_addr_0 or read_addr_1 or read_addr_2 or read_addr_3 or
do_read_0 or do_read_1 or do_read_2 or do_read_3)
case (READ_FIFO)
2'b00: begin
read_addr <= {2'b00,read_addr_0};
re <= do_read_0;
end
2'b01: begin
read_addr <= {2'b01,read_addr_1};
re <= do_read_1;
end
2'b10: begin
read_addr <= {2'b10,read_addr_2};
re <= do_read_2;
end
2'b11: begin
read_addr <= {2'b11,read_addr_3};
re <= do_read_3;
end
endcase
iceram32 lsab_sram(.RDATA(out_mem),
.RADDR(read_addr),
.RE(re),
.RCLKE(1'b1),
.RCLK(CLK),
.WDATA(in_mem),
.MASK(0),
.WADDR(write_addr),
.WE(we),
.WCLKE(1'b1),
.WCLK(CLK));
assign intbuff_int_det_0 = ((intbuff_0[intbuff_raddr_0] ^
read_addr_0) == 0) &&
do_read_0 &&
!intbuff_empty_0;
assign intbuff_int_0 = intbuff_int_det_0 && CAREOF_INT_0;
assign intbuff_empty_0 = intbuff_raddr_0 == intbuff_waddr_0;
assign intbuff_full_0 = intbuff_raddr_trail_0 == intbuff_waddr_0;
assign intbuff_int_det_1 = ((intbuff_1[intbuff_raddr_1] ^
read_addr_1) == 0) &&
do_read_1 &&
!intbuff_empty_1;
assign intbuff_int_1 = intbuff_int_det_1 && CAREOF_INT_1;
assign intbuff_empty_1 = intbuff_raddr_1 == intbuff_waddr_1;
assign intbuff_full_1 = intbuff_raddr_trail_1 == intbuff_waddr_1;
assign intbuff_int_det_2 = ((intbuff_2[intbuff_raddr_2] ^
read_addr_2) == 0) &&
do_read_2 &&
!intbuff_empty_2;
assign intbuff_int_2 = intbuff_int_det_2 && CAREOF_INT_2;
assign intbuff_empty_2 = intbuff_raddr_2 == intbuff_waddr_2;
assign intbuff_full_2 = intbuff_raddr_trail_2 == intbuff_waddr_2;
assign intbuff_int_det_3 = ((intbuff_3[intbuff_raddr_3] ^
read_addr_3) == 0) &&
do_read_3 &&
!intbuff_empty_3;
assign intbuff_int_3 = intbuff_int_det_3 && CAREOF_INT_3;
assign intbuff_empty_3 = intbuff_raddr_3 == intbuff_waddr_3;
assign intbuff_full_3 = intbuff_raddr_trail_3 == intbuff_waddr_3;
always @(posedge CLK)
if (RST)
begin
STOP_0 <= become_empty_0 || intbuff_int_0;
INT_OUT_0 <= intbuff_int_0;
EMPTY_0 <= become_empty_0;
ANCILL_OUT_0 <= ancbuff_0[intbuff_raddr_0];
full_0 <= become_full_0;
STOP_1 <= become_empty_1 || intbuff_int_1;
INT_OUT_1 <= intbuff_int_1;
EMPTY_1 <= become_empty_1;
ANCILL_OUT_1 <= ancbuff_1[intbuff_raddr_1];
full_1 <= become_full_1;
STOP_2 <= become_empty_2 || intbuff_int_2;
INT_OUT_2 <= intbuff_int_2;
EMPTY_2 <= become_empty_2;
ANCILL_OUT_2 <= ancbuff_2[intbuff_raddr_2];
full_2 <= become_full_2;
STOP_3 <= become_empty_3 || intbuff_int_3;
INT_OUT_3 <= intbuff_int_3;
EMPTY_3 <= become_empty_3;
ANCILL_OUT_3 <= ancbuff_3[intbuff_raddr_3];
full_3 <= become_full_3;
len_0 <= become_len_0;
len_1 <= become_len_1;
len_2 <= become_len_2;
len_3 <= become_len_3;
if (do_write_0)
write_addr_0 <= write_addr_0 + 1;
if (do_read_0)
read_addr_0 <= read_addr_0 + 1;
if (do_write_1)
write_addr_1 <= write_addr_1 + 1;
if (do_read_1)
read_addr_1 <= read_addr_1 + 1;
if (do_write_2)
write_addr_2 <= write_addr_2 + 1;
if (do_read_2)
read_addr_2 <= read_addr_2 + 1;
if (do_write_3)
write_addr_3 <= write_addr_3 + 1;
if (do_read_3)
read_addr_3 <= read_addr_3 + 1;
re_prev <= re;
if (re_prev)
OUT <= out_mem;
if (intbuff_int_det_0)
begin
intbuff_raddr_0 <= intbuff_raddr_0 +1;
intbuff_raddr_trail_0 <= intbuff_raddr_trail_0 +1;
end
if (INT_IN_0 && do_write_0 && (!intbuff_full_0))
begin
intbuff_0[intbuff_waddr_0] <= write_addr_0;
ancbuff_0[intbuff_waddr_0] <= ANCILL_IN_0;
intbuff_waddr_0 <= intbuff_waddr_0 +1;
end
if (intbuff_int_det_1)
begin
intbuff_raddr_1 <= intbuff_raddr_1 +1;
intbuff_raddr_trail_1 <= intbuff_raddr_trail_1 +1;
end
if (INT_IN_1 && do_write_1 && (!intbuff_full_1))
begin
intbuff_1[intbuff_waddr_1] <= write_addr_1;
ancbuff_1[intbuff_waddr_1] <= ANCILL_IN_1;
intbuff_waddr_1 <= intbuff_waddr_1 +1;
end
if (intbuff_int_det_2)
begin
intbuff_raddr_2 <= intbuff_raddr_2 +1;
intbuff_raddr_trail_2 <= intbuff_raddr_trail_2 +1;
end
if (INT_IN_2 && do_write_2 && (!intbuff_full_2))
begin
intbuff_2[intbuff_waddr_2] <= write_addr_2;
ancbuff_2[intbuff_waddr_2] <= ANCILL_IN_2;
intbuff_waddr_2 <= intbuff_waddr_2 +1;
end
if (intbuff_int_det_3)
begin
intbuff_raddr_3 <= intbuff_raddr_3 +1;
intbuff_raddr_trail_3 <= intbuff_raddr_trail_3 +1;
end
if (INT_IN_3 && do_write_3 && (!intbuff_full_3))
begin
intbuff_3[intbuff_waddr_3] <= write_addr_3;
ancbuff_3[intbuff_waddr_3] <= ANCILL_IN_3;
intbuff_waddr_3 <= intbuff_waddr_3 +1;
end
end
endmodule | module lsab_cr(input CLK,
input RST,
input READ,
input WRITE0,
input WRITE1,
input WRITE2,
input WRITE3,
input [1:0] READ_FIFO,
input [1:0] WRITE_FIFO,
input [31:0] IN_0,
input [31:0] IN_1,
input [31:0] IN_2,
input [31:0] IN_3,
input INT_IN_0,
input INT_IN_1,
input INT_IN_2,
input INT_IN_3,
input CAREOF_INT_0,
input CAREOF_INT_1,
input CAREOF_INT_2,
input CAREOF_INT_3,
input [24:0] ANCILL_IN_0,
input [24:0] ANCILL_IN_1,
input [24:0] ANCILL_IN_2,
input [24:0] ANCILL_IN_3,
output reg [31:0] OUT,
output EMPTY_0,
output EMPTY_1,
output EMPTY_2,
output EMPTY_3,
output STOP_0,
output STOP_1,
output STOP_2,
output STOP_3,
output reg INT_OUT_0,
output reg INT_OUT_1,
output reg INT_OUT_2,
output reg INT_OUT_3,
output reg [24:0] ANCILL_OUT_0,
output reg [24:0] ANCILL_OUT_1,
output reg [24:0] ANCILL_OUT_2,
output reg [24:0] ANCILL_OUT_3); |
reg EMPTY_0 = 1'b1, EMPTY_1 = 1'b1,
EMPTY_2 = 1'b1, EMPTY_3 = 1'b1,
STOP_0 = 1'b1, STOP_1 = 1'b1,
STOP_2 = 1'b1, STOP_3 = 1'b1;
reg full_0 = 1'b0, full_1 = 1'b0,
full_2 = 1'b0, full_3 = 1'b0;
reg [5:0] len_0 = 6'h0, len_1 = 6'h0,
len_2 = 6'h0, len_3 = 6'h0;
reg [5:0] write_addr_0 = 6'h0, write_addr_1 = 6'h0,
write_addr_2 = 6'h0, write_addr_3 = 6'h0;
reg [5:0] read_addr_0 = 6'h0, read_addr_1 = 6'h0,
read_addr_2 = 6'h0, read_addr_3 = 6'h0;
reg re_prev;
wire read_0, read_1, read_2, read_3;
wire write_0, write_1, write_2, write_3;
wire do_read_0, do_read_1, do_read_2, do_read_3;
wire do_write_0, do_write_1, do_write_2, do_write_3;
reg become_empty_0, become_empty_1,
become_empty_2, become_empty_3;
reg become_full_0, become_full_1,
become_full_2, become_full_3;
reg [5:0] become_len_0, become_len_1,
become_len_2, become_len_3;
reg [1:0] intbuff_raddr_0 = 2'h1, intbuff_raddr_trail_0 = 2'h0,
intbuff_waddr_0 = 2'h1,
intbuff_raddr_1 = 2'h1, intbuff_raddr_trail_1 = 2'h0,
intbuff_waddr_1 = 2'h1,
intbuff_raddr_2 = 2'h1, intbuff_raddr_trail_2 = 2'h0,
intbuff_waddr_2 = 2'h1,
intbuff_raddr_3 = 2'h1, intbuff_raddr_trail_3 = 2'h0,
intbuff_waddr_3 = 2'h1;
wire intbuff_int_det_0, intbuff_int_0,
intbuff_empty_0, intbuff_full_0,
intbuff_int_det_1, intbuff_int_1,
intbuff_empty_1, intbuff_full_1,
intbuff_int_det_2, intbuff_int_2,
intbuff_empty_2, intbuff_full_2,
intbuff_int_det_3, intbuff_int_3,
intbuff_empty_3, intbuff_full_3;
reg [5:0] intbuff_0[3:0], intbuff_1[3:0], intbuff_2[3:0],
intbuff_3[3:0];
reg [24:0] ancbuff_0[3:0], ancbuff_1[3:0], ancbuff_2[3:0],
ancbuff_3[3:0];
wire [31:0] out_mem;
reg [31:0] in_mem;
reg [7:0] write_addr, read_addr;
reg we, re;
assign read_0 = READ && (READ_FIFO == 2'h0);
assign read_1 = READ && (READ_FIFO == 2'h1);
assign read_2 = READ && (READ_FIFO == 2'h2);
assign read_3 = READ && (READ_FIFO == 2'h3);
assign write_0 = WRITE0 && (WRITE_FIFO == 2'h0);
assign write_1 = WRITE1 && (WRITE_FIFO == 2'h1);
assign write_2 = WRITE2 && (WRITE_FIFO == 2'h2);
assign write_3 = WRITE3 && (WRITE_FIFO == 2'h3);
assign do_write_0 = full_0 ? 0 : write_0;
assign do_write_1 = full_1 ? 0 : write_1;
assign do_write_2 = full_2 ? 0 : write_2;
assign do_write_3 = full_3 ? 0 : write_3;
assign do_read_0 = STOP_0 ? 0 : read_0;
assign do_read_1 = STOP_1 ? 0 : read_1;
assign do_read_2 = STOP_2 ? 0 : read_2;
assign do_read_3 = STOP_3 ? 0 : read_3;
always @(len_0 or do_read_0 or do_write_0 or full_0 or EMPTY_0)
case ({len_0,do_read_0,do_write_0})
{6'h3f,2'b10}: begin become_full_0 <= 0; become_empty_0 <= 0; end
{6'h3e,2'b01}: begin become_full_0 <= 1; become_empty_0 <= 0; end
{6'h01,2'b10}: begin become_full_0 <= 0; become_empty_0 <= 1; end
{6'h00,2'b01}: begin become_full_0 <= 0; become_empty_0 <= 0; end
default: begin become_full_0 <= full_0; become_empty_0 <= EMPTY_0; end
endcase
always @(len_1 or do_read_1 or do_write_1 or full_1 or EMPTY_1)
case ({len_1,do_read_1,do_write_1})
{6'h3f,2'b10}: begin become_full_1 <= 0; become_empty_1 <= 0; end
{6'h3e,2'b01}: begin become_full_1 <= 1; become_empty_1 <= 0; end
{6'h01,2'b10}: begin become_full_1 <= 0; become_empty_1 <= 1; end
{6'h00,2'b01}: begin become_full_1 <= 0; become_empty_1 <= 0; end
default: begin become_full_1 <= full_1; become_empty_1 <= EMPTY_1; end
endcase
always @(len_2 or do_read_2 or do_write_2 or full_2 or EMPTY_2)
case ({len_2,do_read_2,do_write_2})
{6'h3f,2'b10}: begin become_full_2 <= 0; become_empty_2 <= 0; end
{6'h3e,2'b01}: begin become_full_2 <= 1; become_empty_2 <= 0; end
{6'h01,2'b10}: begin become_full_2 <= 0; become_empty_2 <= 1; end
{6'h00,2'b01}: begin become_full_2 <= 0; become_empty_2 <= 0; end
default: begin become_full_2 <= full_2; become_empty_2 <= EMPTY_2; end
endcase
always @(len_3 or do_read_3 or do_write_3 or full_3 or EMPTY_3)
case ({len_3,do_read_3,do_write_3})
{6'h3f,2'b10}: begin become_full_3 <= 0; become_empty_3 <= 0; end
{6'h3e,2'b01}: begin become_full_3 <= 1; become_empty_3 <= 0; end
{6'h01,2'b10}: begin become_full_3 <= 0; become_empty_3 <= 1; end
{6'h00,2'b01}: begin become_full_3 <= 0; become_empty_3 <= 0; end
default: begin become_full_3 <= full_3; become_empty_3 <= EMPTY_3; end
endcase
always @(do_read_0 or do_write_0 or len_0)
case ({do_read_0,do_write_0})
2'b10: become_len_0 <= len_0 -1;
2'b01: become_len_0 <= len_0 +1;
default: become_len_0 <= len_0;
endcase
always @(do_read_1 or do_write_1 or len_1)
case ({do_read_1,do_write_1})
2'b10: become_len_1 <= len_1 -1;
2'b01: become_len_1 <= len_1 +1;
default: become_len_1 <= len_1;
endcase
always @(do_read_2 or do_write_2 or len_2)
case ({do_read_2,do_write_2})
2'b10: become_len_2 <= len_2 -1;
2'b01: become_len_2 <= len_2 +1;
default: become_len_2 <= len_2;
endcase
always @(do_read_3 or do_write_3 or len_3)
case ({do_read_3,do_write_3})
2'b10: become_len_3 <= len_3 -1;
2'b01: become_len_3 <= len_3 +1;
default: become_len_3 <= len_3;
endcase
always @(WRITE_FIFO or
IN_0 or IN_1 or IN_2 or IN_3 or
write_addr_0 or write_addr_1 or write_addr_2 or write_addr_3 or
do_write_0 or do_write_1 or do_write_2 or do_write_3)
case (WRITE_FIFO)
2'b00: begin
in_mem <= IN_0;
write_addr <= {2'b00,write_addr_0};
we <= do_write_0;
end
2'b01: begin
in_mem <= IN_1;
write_addr <= {2'b01,write_addr_1};
we <= do_write_1;
end
2'b10: begin
in_mem <= IN_2;
write_addr <= {2'b10,write_addr_2};
we <= do_write_2;
end
2'b11: begin
in_mem <= IN_3;
write_addr <= {2'b11,write_addr_3};
we <= do_write_3;
end
endcase
always @(READ_FIFO or
read_addr_0 or read_addr_1 or read_addr_2 or read_addr_3 or
do_read_0 or do_read_1 or do_read_2 or do_read_3)
case (READ_FIFO)
2'b00: begin
read_addr <= {2'b00,read_addr_0};
re <= do_read_0;
end
2'b01: begin
read_addr <= {2'b01,read_addr_1};
re <= do_read_1;
end
2'b10: begin
read_addr <= {2'b10,read_addr_2};
re <= do_read_2;
end
2'b11: begin
read_addr <= {2'b11,read_addr_3};
re <= do_read_3;
end
endcase
iceram32 lsab_sram(.RDATA(out_mem),
.RADDR(read_addr),
.RE(re),
.RCLKE(1'b1),
.RCLK(CLK),
.WDATA(in_mem),
.MASK(0),
.WADDR(write_addr),
.WE(we),
.WCLKE(1'b1),
.WCLK(CLK));
assign intbuff_int_det_0 = ((intbuff_0[intbuff_raddr_0] ^
read_addr_0) == 0) &&
do_read_0 &&
!intbuff_empty_0;
assign intbuff_int_0 = intbuff_int_det_0 && CAREOF_INT_0;
assign intbuff_empty_0 = intbuff_raddr_0 == intbuff_waddr_0;
assign intbuff_full_0 = intbuff_raddr_trail_0 == intbuff_waddr_0;
assign intbuff_int_det_1 = ((intbuff_1[intbuff_raddr_1] ^
read_addr_1) == 0) &&
do_read_1 &&
!intbuff_empty_1;
assign intbuff_int_1 = intbuff_int_det_1 && CAREOF_INT_1;
assign intbuff_empty_1 = intbuff_raddr_1 == intbuff_waddr_1;
assign intbuff_full_1 = intbuff_raddr_trail_1 == intbuff_waddr_1;
assign intbuff_int_det_2 = ((intbuff_2[intbuff_raddr_2] ^
read_addr_2) == 0) &&
do_read_2 &&
!intbuff_empty_2;
assign intbuff_int_2 = intbuff_int_det_2 && CAREOF_INT_2;
assign intbuff_empty_2 = intbuff_raddr_2 == intbuff_waddr_2;
assign intbuff_full_2 = intbuff_raddr_trail_2 == intbuff_waddr_2;
assign intbuff_int_det_3 = ((intbuff_3[intbuff_raddr_3] ^
read_addr_3) == 0) &&
do_read_3 &&
!intbuff_empty_3;
assign intbuff_int_3 = intbuff_int_det_3 && CAREOF_INT_3;
assign intbuff_empty_3 = intbuff_raddr_3 == intbuff_waddr_3;
assign intbuff_full_3 = intbuff_raddr_trail_3 == intbuff_waddr_3;
always @(posedge CLK)
if (RST)
begin
STOP_0 <= become_empty_0 || intbuff_int_0;
INT_OUT_0 <= intbuff_int_0;
EMPTY_0 <= become_empty_0;
ANCILL_OUT_0 <= ancbuff_0[intbuff_raddr_0];
full_0 <= become_full_0;
STOP_1 <= become_empty_1 || intbuff_int_1;
INT_OUT_1 <= intbuff_int_1;
EMPTY_1 <= become_empty_1;
ANCILL_OUT_1 <= ancbuff_1[intbuff_raddr_1];
full_1 <= become_full_1;
STOP_2 <= become_empty_2 || intbuff_int_2;
INT_OUT_2 <= intbuff_int_2;
EMPTY_2 <= become_empty_2;
ANCILL_OUT_2 <= ancbuff_2[intbuff_raddr_2];
full_2 <= become_full_2;
STOP_3 <= become_empty_3 || intbuff_int_3;
INT_OUT_3 <= intbuff_int_3;
EMPTY_3 <= become_empty_3;
ANCILL_OUT_3 <= ancbuff_3[intbuff_raddr_3];
full_3 <= become_full_3;
len_0 <= become_len_0;
len_1 <= become_len_1;
len_2 <= become_len_2;
len_3 <= become_len_3;
if (do_write_0)
write_addr_0 <= write_addr_0 + 1;
if (do_read_0)
read_addr_0 <= read_addr_0 + 1;
if (do_write_1)
write_addr_1 <= write_addr_1 + 1;
if (do_read_1)
read_addr_1 <= read_addr_1 + 1;
if (do_write_2)
write_addr_2 <= write_addr_2 + 1;
if (do_read_2)
read_addr_2 <= read_addr_2 + 1;
if (do_write_3)
write_addr_3 <= write_addr_3 + 1;
if (do_read_3)
read_addr_3 <= read_addr_3 + 1;
re_prev <= re;
if (re_prev)
OUT <= out_mem;
if (intbuff_int_det_0)
begin
intbuff_raddr_0 <= intbuff_raddr_0 +1;
intbuff_raddr_trail_0 <= intbuff_raddr_trail_0 +1;
end
if (INT_IN_0 && do_write_0 && (!intbuff_full_0))
begin
intbuff_0[intbuff_waddr_0] <= write_addr_0;
ancbuff_0[intbuff_waddr_0] <= ANCILL_IN_0;
intbuff_waddr_0 <= intbuff_waddr_0 +1;
end
if (intbuff_int_det_1)
begin
intbuff_raddr_1 <= intbuff_raddr_1 +1;
intbuff_raddr_trail_1 <= intbuff_raddr_trail_1 +1;
end
if (INT_IN_1 && do_write_1 && (!intbuff_full_1))
begin
intbuff_1[intbuff_waddr_1] <= write_addr_1;
ancbuff_1[intbuff_waddr_1] <= ANCILL_IN_1;
intbuff_waddr_1 <= intbuff_waddr_1 +1;
end
if (intbuff_int_det_2)
begin
intbuff_raddr_2 <= intbuff_raddr_2 +1;
intbuff_raddr_trail_2 <= intbuff_raddr_trail_2 +1;
end
if (INT_IN_2 && do_write_2 && (!intbuff_full_2))
begin
intbuff_2[intbuff_waddr_2] <= write_addr_2;
ancbuff_2[intbuff_waddr_2] <= ANCILL_IN_2;
intbuff_waddr_2 <= intbuff_waddr_2 +1;
end
if (intbuff_int_det_3)
begin
intbuff_raddr_3 <= intbuff_raddr_3 +1;
intbuff_raddr_trail_3 <= intbuff_raddr_trail_3 +1;
end
if (INT_IN_3 && do_write_3 && (!intbuff_full_3))
begin
intbuff_3[intbuff_waddr_3] <= write_addr_3;
ancbuff_3[intbuff_waddr_3] <= ANCILL_IN_3;
intbuff_waddr_3 <= intbuff_waddr_3 +1;
end
end
endmodule | 1 |
138,598 | data/full_repos/permissive/85002992/hyperfabric/lsab.v | 85,002,992 | lsab.v | v | 737 | 77 | [] | [] | [] | null | line:43: before: "," | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/85002992/hyperfabric/lsab.v:382: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'lsab_cr\'\nmodule lsab_cr(input CLK,\n ^~~~~~~\n : ... Top module \'lsab_cw\'\nmodule lsab_cw(input CLK,\n ^~~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:43: Duplicate declaration of signal: \'EMPTY_0\'\n reg EMPTY_0 = 1\'b1, EMPTY_1 = 1\'b1,\n ^~~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:27: ... Location of original declaration\n output EMPTY_0,\n ^~~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:43: Duplicate declaration of signal: \'EMPTY_1\'\n reg EMPTY_0 = 1\'b1, EMPTY_1 = 1\'b1,\n ^~~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:28: ... Location of original declaration\n output EMPTY_1,\n ^~~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:44: Duplicate declaration of signal: \'EMPTY_2\'\n EMPTY_2 = 1\'b1, EMPTY_3 = 1\'b1,\n ^~~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:29: ... Location of original declaration\n output EMPTY_2,\n ^~~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:44: Duplicate declaration of signal: \'EMPTY_3\'\n EMPTY_2 = 1\'b1, EMPTY_3 = 1\'b1,\n ^~~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:30: ... Location of original declaration\n output EMPTY_3,\n ^~~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:45: Duplicate declaration of signal: \'STOP_0\'\n STOP_0 = 1\'b1, STOP_1 = 1\'b1,\n ^~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:31: ... Location of original declaration\n output STOP_0,\n ^~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:45: Duplicate declaration of signal: \'STOP_1\'\n STOP_0 = 1\'b1, STOP_1 = 1\'b1,\n ^~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:32: ... Location of original declaration\n output STOP_1,\n ^~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:46: Duplicate declaration of signal: \'STOP_2\'\n STOP_2 = 1\'b1, STOP_3 = 1\'b1;\n ^~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:33: ... Location of original declaration\n output STOP_2,\n ^~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:46: Duplicate declaration of signal: \'STOP_3\'\n STOP_2 = 1\'b1, STOP_3 = 1\'b1;\n ^~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:34: ... Location of original declaration\n output STOP_3,\n ^~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:408: Duplicate declaration of signal: \'OUT_0\'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg [31:0] OUT_0 = 32\'d0, OUT_1 = 32\'d0,\n ^~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:392: ... Location of original declaration\n output [31:0] OUT_0,\n ^~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:408: Duplicate declaration of signal: \'OUT_1\'\n reg [31:0] OUT_0 = 32\'d0, OUT_1 = 32\'d0,\n ^~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:393: ... Location of original declaration\n output [31:0] OUT_1,\n ^~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:409: Duplicate declaration of signal: \'OUT_2\'\n OUT_2 = 32\'d0, OUT_3 = 32\'d0;\n ^~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:394: ... Location of original declaration\n output [31:0] OUT_2,\n ^~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:409: Duplicate declaration of signal: \'OUT_3\'\n OUT_2 = 32\'d0, OUT_3 = 32\'d0;\n ^~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:395: ... Location of original declaration\n output [31:0] OUT_3,\n ^~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:410: Duplicate declaration of signal: \'BFULL\'\n reg BFULL = 1\'b0;\n ^~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:396: ... Location of original declaration\n output BFULL,\n ^~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:411: Duplicate declaration of signal: \'DEV_0_ERR_ACK\'\n reg DEV_0_ERR_ACK = 1\'b0,\n ^~~~~~~~~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:402: ... Location of original declaration\n output DEV_0_ERR_ACK,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:412: Duplicate declaration of signal: \'DEV_1_ERR_ACK\'\n DEV_1_ERR_ACK = 1\'b0,\n ^~~~~~~~~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:403: ... Location of original declaration\n output DEV_1_ERR_ACK,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:413: Duplicate declaration of signal: \'DEV_2_ERR_ACK\'\n DEV_2_ERR_ACK = 1\'b0,\n ^~~~~~~~~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:404: ... Location of original declaration\n output DEV_2_ERR_ACK,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:414: Duplicate declaration of signal: \'DEV_3_ERR_ACK\'\n DEV_3_ERR_ACK = 1\'b0;\n ^~~~~~~~~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:405: ... Location of original declaration\n output DEV_3_ERR_ACK,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/lsab.v:415: Duplicate declaration of signal: \'DEVERR\'\n reg DEVERR = 1\'b0;\n ^~~~~~\n data/full_repos/permissive/85002992/hyperfabric/lsab.v:406: ... Location of original declaration\n output DEVERR,\n ^~~~~~\n%Error: Exiting due to 18 error(s), 1 warning(s)\n' | 302,578 | module | module lsab_cw(input CLK,
input RST,
input READ0,
input READ1,
input READ2,
input READ3,
input WRITE,
input [1:0] READ_FIFO,
input [1:0] WRITE_FIFO,
input [31:0] IN,
output [31:0] OUT_0,
output [31:0] OUT_1,
output [31:0] OUT_2,
output [31:0] OUT_3,
output BFULL,
input DEV_0_ERR,
input DEV_1_ERR,
input DEV_2_ERR,
input DEV_3_ERR,
output DEV_0_ERR_ACK,
output DEV_1_ERR_ACK,
output DEV_2_ERR_ACK,
output DEV_3_ERR_ACK,
output DEVERR,
input DEVERRACK);
reg [31:0] OUT_0 = 32'd0, OUT_1 = 32'd0,
OUT_2 = 32'd0, OUT_3 = 32'd0;
reg BFULL = 1'b0;
reg DEV_0_ERR_ACK = 1'b0,
DEV_1_ERR_ACK = 1'b0,
DEV_2_ERR_ACK = 1'b0,
DEV_3_ERR_ACK = 1'b0;
reg DEVERR = 1'b0;
reg empty_0 = 1'b1, empty_1 = 1'b1,
empty_2 = 1'b1, empty_3 = 1'b1;
reg full_0 = 1'b0, full_1 = 1'b0,
full_2 = 1'b0, full_3 = 1'b0;
reg bfull_0 = 1'b0, bfull_1 = 1'b0,
bfull_2 = 1'b0, bfull_3 = 1'b0;
reg [5:0] len_0 = 6'd0, len_1 = 6'd0, len_2 = 6'd0, len_3 = 6'd0;
reg [5:0] write_addr_0 = 6'd0, write_addr_1 = 6'd0,
write_addr_2 = 6'd0, write_addr_3 = 6'd0;
reg [5:0] read_addr_0 = 6'd0, read_addr_1 = 6'd0,
read_addr_2 = 6'd0, read_addr_3 = 6'd0;
reg re_prev;
reg [1:0] re_fifo_prev;
wire read_0, read_1, read_2, read_3;
wire write_0, write_1, write_2, write_3;
wire do_read_0, do_read_1, do_read_2, do_read_3;
wire do_write_0, do_write_1, do_write_2, do_write_3;
reg become_empty_0, become_empty_1,
become_empty_2, become_empty_3;
reg become_full_0, become_full_1,
become_full_2, become_full_3;
reg become_bfull_0, become_bfull_1,
become_bfull_2, become_bfull_3;
reg [5:0] become_len_0, become_len_1,
become_len_2, become_len_3;
wire [31:0] out_mem;
reg [7:0] write_addr, read_addr;
reg we, re;
assign read_0 = READ0 && (READ_FIFO == 2'h0);
assign read_1 = READ1 && (READ_FIFO == 2'h1);
assign read_2 = READ2 && (READ_FIFO == 2'h2);
assign read_3 = READ3 && (READ_FIFO == 2'h3);
assign write_0 = WRITE && (WRITE_FIFO == 2'h0);
assign write_1 = WRITE && (WRITE_FIFO == 2'h1);
assign write_2 = WRITE && (WRITE_FIFO == 2'h2);
assign write_3 = WRITE && (WRITE_FIFO == 2'h3);
assign do_write_0 = full_0 ? 0 : write_0;
assign do_write_1 = full_1 ? 0 : write_1;
assign do_write_2 = full_2 ? 0 : write_2;
assign do_write_3 = full_3 ? 0 : write_3;
assign do_read_0 = empty_0 ? 0 : read_0;
assign do_read_1 = empty_1 ? 0 : read_1;
assign do_read_2 = empty_2 ? 0 : read_2;
assign do_read_3 = empty_3 ? 0 : read_3;
always @(len_0 or do_read_0 or do_write_0 or full_0 or empty_0 or bfull_0)
case ({len_0,do_read_0,do_write_0})
{6'h3f,2'b10}: begin
become_full_0 <= 0; become_empty_0 <= 0; become_bfull_0 <= 1;
end
{6'h3e,2'b01}: begin
become_full_0 <= 1; become_empty_0 <= 0; become_bfull_0 <= 1;
end
{6'h37,2'b10}: begin
become_full_0 <= 0; become_empty_0 <= 0; become_bfull_0 <= 0;
end
{6'h36,2'b01}: begin
become_full_0 <= 0; become_empty_0 <= 0; become_bfull_0 <= 1;
end
{6'h01,2'b10}: begin
become_full_0 <= 0; become_empty_0 <= 1; become_bfull_0 <= 0;
end
{6'h00,2'b01}: begin
become_full_0 <= 0; become_empty_0 <= 0; become_bfull_0 <= 0;
end
default: begin
become_full_0 <= full_0; become_empty_0 <= empty_0;
become_bfull_0 <= bfull_0;
end
endcase
always @(len_1 or do_read_1 or do_write_1 or full_1 or empty_1 or bfull_1)
case ({len_1,do_read_1,do_write_1})
{6'h3f,2'b10}: begin
become_full_1 <= 0; become_empty_1 <= 0; become_bfull_1 <= 1;
end
{6'h3e,2'b01}: begin
become_full_1 <= 1; become_empty_1 <= 0; become_bfull_1 <= 1;
end
{6'h37,2'b10}: begin
become_full_1 <= 0; become_empty_1 <= 0; become_bfull_1 <= 0;
end
{6'h36,2'b01}: begin
become_full_1 <= 0; become_empty_1 <= 0; become_bfull_1 <= 1;
end
{6'h01,2'b10}: begin
become_full_1 <= 0; become_empty_1 <= 1; become_bfull_1 <= 0;
end
{6'h00,2'b01}: begin
become_full_1 <= 0; become_empty_1 <= 0; become_bfull_1 <= 0;
end
default: begin
become_full_1 <= full_1; become_empty_1 <= empty_1;
become_bfull_1 <= bfull_1;
end
endcase
always @(len_2 or do_read_2 or do_write_2 or full_2 or empty_2 or bfull_2)
case ({len_2,do_read_2,do_write_2})
{6'h3f,2'b10}: begin
become_full_2 <= 0; become_empty_2 <= 0; become_bfull_2 <= 1;
end
{6'h3e,2'b01}: begin
become_full_2 <= 1; become_empty_2 <= 0; become_bfull_2 <= 1;
end
{6'h37,2'b10}: begin
become_full_2 <= 0; become_empty_2 <= 0; become_bfull_2 <= 0;
end
{6'h36,2'b01}: begin
become_full_2 <= 0; become_empty_2 <= 0; become_bfull_2 <= 1;
end
{6'h01,2'b10}: begin
become_full_2 <= 0; become_empty_2 <= 1; become_bfull_2 <= 0;
end
{6'h00,2'b01}: begin
become_full_2 <= 0; become_empty_2 <= 0; become_bfull_2 <= 0;
end
default: begin
become_full_2 <= full_2; become_empty_2 <= empty_2;
become_bfull_2 <= bfull_2;
end
endcase
always @(len_3 or do_read_3 or do_write_3 or full_3 or empty_3 or bfull_3)
case ({len_3,do_read_3,do_write_3})
{6'h3f,2'b10}: begin
become_full_3 <= 0; become_empty_3 <= 0; become_bfull_3 <= 1;
end
{6'h3e,2'b01}: begin
become_full_3 <= 1; become_empty_3 <= 0; become_bfull_3 <= 1;
end
{6'h37,2'b10}: begin
become_full_3 <= 0; become_empty_3 <= 0; become_bfull_3 <= 0;
end
{6'h36,2'b01}: begin
become_full_3 <= 0; become_empty_3 <= 0; become_bfull_3 <= 1;
end
{6'h01,2'b10}: begin
become_full_3 <= 0; become_empty_3 <= 1; become_bfull_3 <= 0;
end
{6'h00,2'b01}: begin
become_full_3 <= 0; become_empty_3 <= 0; become_bfull_3 <= 0;
end
default: begin
become_full_3 <= full_3; become_empty_3 <= empty_3;
become_bfull_3 <= bfull_3;
end
endcase
always @(do_read_0 or do_write_0 or len_0)
case ({do_read_0,do_write_0})
2'b10: become_len_0 <= len_0 -1;
2'b01: become_len_0 <= len_0 +1;
default: become_len_0 <= len_0;
endcase
always @(do_read_1 or do_write_1 or len_1)
case ({do_read_1,do_write_1})
2'b10: become_len_1 <= len_1 -1;
2'b01: become_len_1 <= len_1 +1;
default: become_len_1 <= len_1;
endcase
always @(do_read_2 or do_write_2 or len_2)
case ({do_read_2,do_write_2})
2'b10: become_len_2 <= len_2 -1;
2'b01: become_len_2 <= len_2 +1;
default: become_len_2 <= len_2;
endcase
always @(do_read_3 or do_write_3 or len_3)
case ({do_read_3,do_write_3})
2'b10: become_len_3 <= len_3 -1;
2'b01: become_len_3 <= len_3 +1;
default: become_len_3 <= len_3;
endcase
always @(WRITE_FIFO or
write_addr_0 or write_addr_1 or write_addr_2 or write_addr_3 or
do_write_0 or do_write_1 or do_write_2 or do_write_3)
case (WRITE_FIFO)
2'b00: begin
write_addr <= {2'b00,write_addr_0};
we <= do_write_0;
end
2'b01: begin
write_addr <= {2'b01,write_addr_1};
we <= do_write_1;
end
2'b10: begin
write_addr <= {2'b10,write_addr_2};
we <= do_write_2;
end
2'b11: begin
write_addr <= {2'b11,write_addr_3};
we <= do_write_3;
end
endcase
always @(READ_FIFO or
read_addr_0 or read_addr_1 or read_addr_2 or read_addr_3 or
do_read_0 or do_read_1 or do_read_2 or do_read_3)
case (READ_FIFO)
2'b00: begin
read_addr <= {2'b00,read_addr_0};
re <= do_read_0;
end
2'b01: begin
read_addr <= {2'b01,read_addr_1};
re <= do_read_1;
end
2'b10: begin
read_addr <= {2'b10,read_addr_2};
re <= do_read_2;
end
2'b11: begin
read_addr <= {2'b11,read_addr_3};
re <= do_read_3;
end
endcase
iceram32 lsab_sram(.RDATA(out_mem),
.RADDR(read_addr),
.RE(re),
.RCLKE(1'b1),
.RCLK(CLK),
.WDATA(IN),
.MASK(0),
.WADDR(write_addr),
.WE(we),
.WCLKE(1'b1),
.WCLK(CLK));
always @(posedge CLK)
if (RST)
begin
case (WRITE_FIFO)
2'h0: begin
BFULL <= become_bfull_0;
DEVERR <= DEV_0_ERR;
DEV_0_ERR_ACK <= DEVERRACK;
DEV_1_ERR_ACK <= 0;
DEV_2_ERR_ACK <= 0;
DEV_3_ERR_ACK <= 0;
end
2'h1: begin
BFULL <= become_bfull_1;
DEVERR <= DEV_1_ERR;
DEV_0_ERR_ACK <= 0;
DEV_1_ERR_ACK <= DEVERRACK;
DEV_2_ERR_ACK <= 0;
DEV_3_ERR_ACK <= 0;
end
2'h2: begin
BFULL <= become_bfull_2;
DEVERR <= DEV_2_ERR;
DEV_0_ERR_ACK <= 0;
DEV_1_ERR_ACK <= 0;
DEV_2_ERR_ACK <= DEVERRACK;
DEV_3_ERR_ACK <= 0;
end
2'h3: begin
BFULL <= become_bfull_3;
DEVERR <= DEV_3_ERR;
DEV_0_ERR_ACK <= 0;
DEV_1_ERR_ACK <= 0;
DEV_2_ERR_ACK <= 0;
DEV_3_ERR_ACK <= DEVERRACK;
end
endcase
empty_0 <= become_empty_0;
full_0 <= become_full_0;
empty_1 <= become_empty_1;
full_1 <= become_full_1;
empty_2 <= become_empty_2;
full_2 <= become_full_2;
empty_3 <= become_empty_3;
full_3 <= become_full_3;
len_0 <= become_len_0;
len_1 <= become_len_1;
len_2 <= become_len_2;
len_3 <= become_len_3;
if (do_write_0)
write_addr_0 <= write_addr_0 + 1;
if (do_read_0)
read_addr_0 <= read_addr_0 + 1;
if (do_write_1)
write_addr_1 <= write_addr_1 + 1;
if (do_read_1)
read_addr_1 <= read_addr_1 + 1;
if (do_write_2)
write_addr_2 <= write_addr_2 + 1;
if (do_read_2)
read_addr_2 <= read_addr_2 + 1;
if (do_write_3)
write_addr_3 <= write_addr_3 + 1;
if (do_read_3)
read_addr_3 <= read_addr_3 + 1;
re_prev <= re;
re_fifo_prev <= READ_FIFO;
if (re_prev)
case (re_fifo_prev)
2'b00: OUT_0 <= out_mem;
2'b01: OUT_1 <= out_mem;
2'b10: OUT_2 <= out_mem;
2'b11: OUT_3 <= out_mem;
endcase
end
endmodule | module lsab_cw(input CLK,
input RST,
input READ0,
input READ1,
input READ2,
input READ3,
input WRITE,
input [1:0] READ_FIFO,
input [1:0] WRITE_FIFO,
input [31:0] IN,
output [31:0] OUT_0,
output [31:0] OUT_1,
output [31:0] OUT_2,
output [31:0] OUT_3,
output BFULL,
input DEV_0_ERR,
input DEV_1_ERR,
input DEV_2_ERR,
input DEV_3_ERR,
output DEV_0_ERR_ACK,
output DEV_1_ERR_ACK,
output DEV_2_ERR_ACK,
output DEV_3_ERR_ACK,
output DEVERR,
input DEVERRACK); |
reg [31:0] OUT_0 = 32'd0, OUT_1 = 32'd0,
OUT_2 = 32'd0, OUT_3 = 32'd0;
reg BFULL = 1'b0;
reg DEV_0_ERR_ACK = 1'b0,
DEV_1_ERR_ACK = 1'b0,
DEV_2_ERR_ACK = 1'b0,
DEV_3_ERR_ACK = 1'b0;
reg DEVERR = 1'b0;
reg empty_0 = 1'b1, empty_1 = 1'b1,
empty_2 = 1'b1, empty_3 = 1'b1;
reg full_0 = 1'b0, full_1 = 1'b0,
full_2 = 1'b0, full_3 = 1'b0;
reg bfull_0 = 1'b0, bfull_1 = 1'b0,
bfull_2 = 1'b0, bfull_3 = 1'b0;
reg [5:0] len_0 = 6'd0, len_1 = 6'd0, len_2 = 6'd0, len_3 = 6'd0;
reg [5:0] write_addr_0 = 6'd0, write_addr_1 = 6'd0,
write_addr_2 = 6'd0, write_addr_3 = 6'd0;
reg [5:0] read_addr_0 = 6'd0, read_addr_1 = 6'd0,
read_addr_2 = 6'd0, read_addr_3 = 6'd0;
reg re_prev;
reg [1:0] re_fifo_prev;
wire read_0, read_1, read_2, read_3;
wire write_0, write_1, write_2, write_3;
wire do_read_0, do_read_1, do_read_2, do_read_3;
wire do_write_0, do_write_1, do_write_2, do_write_3;
reg become_empty_0, become_empty_1,
become_empty_2, become_empty_3;
reg become_full_0, become_full_1,
become_full_2, become_full_3;
reg become_bfull_0, become_bfull_1,
become_bfull_2, become_bfull_3;
reg [5:0] become_len_0, become_len_1,
become_len_2, become_len_3;
wire [31:0] out_mem;
reg [7:0] write_addr, read_addr;
reg we, re;
assign read_0 = READ0 && (READ_FIFO == 2'h0);
assign read_1 = READ1 && (READ_FIFO == 2'h1);
assign read_2 = READ2 && (READ_FIFO == 2'h2);
assign read_3 = READ3 && (READ_FIFO == 2'h3);
assign write_0 = WRITE && (WRITE_FIFO == 2'h0);
assign write_1 = WRITE && (WRITE_FIFO == 2'h1);
assign write_2 = WRITE && (WRITE_FIFO == 2'h2);
assign write_3 = WRITE && (WRITE_FIFO == 2'h3);
assign do_write_0 = full_0 ? 0 : write_0;
assign do_write_1 = full_1 ? 0 : write_1;
assign do_write_2 = full_2 ? 0 : write_2;
assign do_write_3 = full_3 ? 0 : write_3;
assign do_read_0 = empty_0 ? 0 : read_0;
assign do_read_1 = empty_1 ? 0 : read_1;
assign do_read_2 = empty_2 ? 0 : read_2;
assign do_read_3 = empty_3 ? 0 : read_3;
always @(len_0 or do_read_0 or do_write_0 or full_0 or empty_0 or bfull_0)
case ({len_0,do_read_0,do_write_0})
{6'h3f,2'b10}: begin
become_full_0 <= 0; become_empty_0 <= 0; become_bfull_0 <= 1;
end
{6'h3e,2'b01}: begin
become_full_0 <= 1; become_empty_0 <= 0; become_bfull_0 <= 1;
end
{6'h37,2'b10}: begin
become_full_0 <= 0; become_empty_0 <= 0; become_bfull_0 <= 0;
end
{6'h36,2'b01}: begin
become_full_0 <= 0; become_empty_0 <= 0; become_bfull_0 <= 1;
end
{6'h01,2'b10}: begin
become_full_0 <= 0; become_empty_0 <= 1; become_bfull_0 <= 0;
end
{6'h00,2'b01}: begin
become_full_0 <= 0; become_empty_0 <= 0; become_bfull_0 <= 0;
end
default: begin
become_full_0 <= full_0; become_empty_0 <= empty_0;
become_bfull_0 <= bfull_0;
end
endcase
always @(len_1 or do_read_1 or do_write_1 or full_1 or empty_1 or bfull_1)
case ({len_1,do_read_1,do_write_1})
{6'h3f,2'b10}: begin
become_full_1 <= 0; become_empty_1 <= 0; become_bfull_1 <= 1;
end
{6'h3e,2'b01}: begin
become_full_1 <= 1; become_empty_1 <= 0; become_bfull_1 <= 1;
end
{6'h37,2'b10}: begin
become_full_1 <= 0; become_empty_1 <= 0; become_bfull_1 <= 0;
end
{6'h36,2'b01}: begin
become_full_1 <= 0; become_empty_1 <= 0; become_bfull_1 <= 1;
end
{6'h01,2'b10}: begin
become_full_1 <= 0; become_empty_1 <= 1; become_bfull_1 <= 0;
end
{6'h00,2'b01}: begin
become_full_1 <= 0; become_empty_1 <= 0; become_bfull_1 <= 0;
end
default: begin
become_full_1 <= full_1; become_empty_1 <= empty_1;
become_bfull_1 <= bfull_1;
end
endcase
always @(len_2 or do_read_2 or do_write_2 or full_2 or empty_2 or bfull_2)
case ({len_2,do_read_2,do_write_2})
{6'h3f,2'b10}: begin
become_full_2 <= 0; become_empty_2 <= 0; become_bfull_2 <= 1;
end
{6'h3e,2'b01}: begin
become_full_2 <= 1; become_empty_2 <= 0; become_bfull_2 <= 1;
end
{6'h37,2'b10}: begin
become_full_2 <= 0; become_empty_2 <= 0; become_bfull_2 <= 0;
end
{6'h36,2'b01}: begin
become_full_2 <= 0; become_empty_2 <= 0; become_bfull_2 <= 1;
end
{6'h01,2'b10}: begin
become_full_2 <= 0; become_empty_2 <= 1; become_bfull_2 <= 0;
end
{6'h00,2'b01}: begin
become_full_2 <= 0; become_empty_2 <= 0; become_bfull_2 <= 0;
end
default: begin
become_full_2 <= full_2; become_empty_2 <= empty_2;
become_bfull_2 <= bfull_2;
end
endcase
always @(len_3 or do_read_3 or do_write_3 or full_3 or empty_3 or bfull_3)
case ({len_3,do_read_3,do_write_3})
{6'h3f,2'b10}: begin
become_full_3 <= 0; become_empty_3 <= 0; become_bfull_3 <= 1;
end
{6'h3e,2'b01}: begin
become_full_3 <= 1; become_empty_3 <= 0; become_bfull_3 <= 1;
end
{6'h37,2'b10}: begin
become_full_3 <= 0; become_empty_3 <= 0; become_bfull_3 <= 0;
end
{6'h36,2'b01}: begin
become_full_3 <= 0; become_empty_3 <= 0; become_bfull_3 <= 1;
end
{6'h01,2'b10}: begin
become_full_3 <= 0; become_empty_3 <= 1; become_bfull_3 <= 0;
end
{6'h00,2'b01}: begin
become_full_3 <= 0; become_empty_3 <= 0; become_bfull_3 <= 0;
end
default: begin
become_full_3 <= full_3; become_empty_3 <= empty_3;
become_bfull_3 <= bfull_3;
end
endcase
always @(do_read_0 or do_write_0 or len_0)
case ({do_read_0,do_write_0})
2'b10: become_len_0 <= len_0 -1;
2'b01: become_len_0 <= len_0 +1;
default: become_len_0 <= len_0;
endcase
always @(do_read_1 or do_write_1 or len_1)
case ({do_read_1,do_write_1})
2'b10: become_len_1 <= len_1 -1;
2'b01: become_len_1 <= len_1 +1;
default: become_len_1 <= len_1;
endcase
always @(do_read_2 or do_write_2 or len_2)
case ({do_read_2,do_write_2})
2'b10: become_len_2 <= len_2 -1;
2'b01: become_len_2 <= len_2 +1;
default: become_len_2 <= len_2;
endcase
always @(do_read_3 or do_write_3 or len_3)
case ({do_read_3,do_write_3})
2'b10: become_len_3 <= len_3 -1;
2'b01: become_len_3 <= len_3 +1;
default: become_len_3 <= len_3;
endcase
always @(WRITE_FIFO or
write_addr_0 or write_addr_1 or write_addr_2 or write_addr_3 or
do_write_0 or do_write_1 or do_write_2 or do_write_3)
case (WRITE_FIFO)
2'b00: begin
write_addr <= {2'b00,write_addr_0};
we <= do_write_0;
end
2'b01: begin
write_addr <= {2'b01,write_addr_1};
we <= do_write_1;
end
2'b10: begin
write_addr <= {2'b10,write_addr_2};
we <= do_write_2;
end
2'b11: begin
write_addr <= {2'b11,write_addr_3};
we <= do_write_3;
end
endcase
always @(READ_FIFO or
read_addr_0 or read_addr_1 or read_addr_2 or read_addr_3 or
do_read_0 or do_read_1 or do_read_2 or do_read_3)
case (READ_FIFO)
2'b00: begin
read_addr <= {2'b00,read_addr_0};
re <= do_read_0;
end
2'b01: begin
read_addr <= {2'b01,read_addr_1};
re <= do_read_1;
end
2'b10: begin
read_addr <= {2'b10,read_addr_2};
re <= do_read_2;
end
2'b11: begin
read_addr <= {2'b11,read_addr_3};
re <= do_read_3;
end
endcase
iceram32 lsab_sram(.RDATA(out_mem),
.RADDR(read_addr),
.RE(re),
.RCLKE(1'b1),
.RCLK(CLK),
.WDATA(IN),
.MASK(0),
.WADDR(write_addr),
.WE(we),
.WCLKE(1'b1),
.WCLK(CLK));
always @(posedge CLK)
if (RST)
begin
case (WRITE_FIFO)
2'h0: begin
BFULL <= become_bfull_0;
DEVERR <= DEV_0_ERR;
DEV_0_ERR_ACK <= DEVERRACK;
DEV_1_ERR_ACK <= 0;
DEV_2_ERR_ACK <= 0;
DEV_3_ERR_ACK <= 0;
end
2'h1: begin
BFULL <= become_bfull_1;
DEVERR <= DEV_1_ERR;
DEV_0_ERR_ACK <= 0;
DEV_1_ERR_ACK <= DEVERRACK;
DEV_2_ERR_ACK <= 0;
DEV_3_ERR_ACK <= 0;
end
2'h2: begin
BFULL <= become_bfull_2;
DEVERR <= DEV_2_ERR;
DEV_0_ERR_ACK <= 0;
DEV_1_ERR_ACK <= 0;
DEV_2_ERR_ACK <= DEVERRACK;
DEV_3_ERR_ACK <= 0;
end
2'h3: begin
BFULL <= become_bfull_3;
DEVERR <= DEV_3_ERR;
DEV_0_ERR_ACK <= 0;
DEV_1_ERR_ACK <= 0;
DEV_2_ERR_ACK <= 0;
DEV_3_ERR_ACK <= DEVERRACK;
end
endcase
empty_0 <= become_empty_0;
full_0 <= become_full_0;
empty_1 <= become_empty_1;
full_1 <= become_full_1;
empty_2 <= become_empty_2;
full_2 <= become_full_2;
empty_3 <= become_empty_3;
full_3 <= become_full_3;
len_0 <= become_len_0;
len_1 <= become_len_1;
len_2 <= become_len_2;
len_3 <= become_len_3;
if (do_write_0)
write_addr_0 <= write_addr_0 + 1;
if (do_read_0)
read_addr_0 <= read_addr_0 + 1;
if (do_write_1)
write_addr_1 <= write_addr_1 + 1;
if (do_read_1)
read_addr_1 <= read_addr_1 + 1;
if (do_write_2)
write_addr_2 <= write_addr_2 + 1;
if (do_read_2)
read_addr_2 <= read_addr_2 + 1;
if (do_write_3)
write_addr_3 <= write_addr_3 + 1;
if (do_read_3)
read_addr_3 <= read_addr_3 + 1;
re_prev <= re;
re_fifo_prev <= READ_FIFO;
if (re_prev)
case (re_fifo_prev)
2'b00: OUT_0 <= out_mem;
2'b01: OUT_1 <= out_mem;
2'b10: OUT_2 <= out_mem;
2'b11: OUT_3 <= out_mem;
endcase
end
endmodule | 1 |
138,600 | data/full_repos/permissive/85002992/hyperfabric/mvblck_todram.v | 85,002,992 | mvblck_todram.v | v | 150 | 68 | [] | [] | [] | null | line:36: before: "," | null | 1: b"%Error: data/full_repos/permissive/85002992/hyperfabric/mvblck_todram.v:36: Duplicate declaration of signal: 'WORKING'\n reg WORKING = 1'b0,\n ^~~~~~~\n data/full_repos/permissive/85002992/hyperfabric/mvblck_todram.v:28: ... Location of original declaration\n output WORKING,\n ^~~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/mvblck_todram.v:37: Duplicate declaration of signal: 'LSAB_READ'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n LSAB_READ = 1'b0;\n ^~~~~~~~~\n data/full_repos/permissive/85002992/hyperfabric/mvblck_todram.v:18: ... Location of original declaration\n output LSAB_READ,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/mvblck_todram.v:38: Duplicate declaration of signal: 'MCU_REQUEST_ACCESS'\n reg [1:0] MCU_REQUEST_ACCESS = 2'd0;\n ^~~~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/hyperfabric/mvblck_todram.v:35: ... Location of original declaration\n output [1:0] MCU_REQUEST_ACCESS);\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/hyperfabric/mvblck_todram.v:39: Duplicate declaration of signal: 'MCU_COLL_ADDRESS'\n reg [8:0] MCU_COLL_ADDRESS = 9'd0;\n ^~~~~~~~~~~~~~~~\n data/full_repos/permissive/85002992/hyperfabric/mvblck_todram.v:33: ... Location of original declaration\n output [8:0] MCU_COLL_ADDRESS,\n ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 302,580 | module | module hyper_mvblck_todram(input CLK,
input RST,
input LSAB_0_INT,
input LSAB_1_INT,
input LSAB_2_INT,
input LSAB_3_INT,
input LSAB_0_STOP,
input LSAB_1_STOP,
input LSAB_2_STOP,
input LSAB_3_STOP,
input [24:0] LSAB_0_ANCILL,
input [24:0] LSAB_1_ANCILL,
input [24:0] LSAB_2_ANCILL,
input [24:0] LSAB_3_ANCILL,
output LSAB_READ,
output reg [1:0] LSAB_SECTION,
input [8:0] START_ADDRESS,
input [5:0] COUNT_REQ,
input [1:0] SECTION,
input [1:0] DRAM_SEL,
input ISSUE,
output reg [5:0] COUNT_SENT,
output WORKING,
output reg IRQ_OUT,
output reg ABRUPT_STOP,
output reg [24:0] ANCILL_OUT,
output [8:0] MCU_COLL_ADDRESS,
output reg [3:0] MCU_WE_ARRAY,
output [1:0] MCU_REQUEST_ACCESS);
reg WORKING = 1'b0,
LSAB_READ = 1'b0;
reg [1:0] MCU_REQUEST_ACCESS = 2'd0;
reg [8:0] MCU_COLL_ADDRESS = 9'd0;
reg stop_prev_n, stop_n,
am_working = 1'b0,
working_pre = 1'b0,
irq;
reg [24:0] ancill;
reg [5:0] len_left;
reg [8:0] track_addr;
wire trigger;
assign trigger = track_addr[0];
always @(LSAB_0_STOP or LSAB_1_STOP or
LSAB_2_STOP or LSAB_3_STOP or
LSAB_0_INT or LSAB_1_INT or
LSAB_2_INT or LSAB_3_INT or
LSAB_0_ANCILL or LSAB_1_ANCILL or
LSAB_2_ANCILL or LSAB_3_ANCILL or
LSAB_SECTION or LSAB_READ)
case (LSAB_SECTION)
2'b00: begin
stop_n <= (LSAB_READ && !LSAB_0_STOP);
irq <= LSAB_0_INT;
ancill <= LSAB_0_ANCILL;
end
2'b01: begin
stop_n <= (LSAB_READ && !LSAB_1_STOP);
irq <= LSAB_1_INT;
ancill <= LSAB_1_ANCILL;
end
2'b10: begin
stop_n <= (LSAB_READ && !LSAB_2_STOP);
irq <= LSAB_2_INT;
ancill <= LSAB_2_ANCILL;
end
2'b11: begin
stop_n <= (LSAB_READ && !LSAB_3_STOP);
irq <= LSAB_3_INT;
ancill <= LSAB_3_ANCILL;
end
default: begin
stop_n <= 1'bx;
irq <= 1'bx;
ancill <= {(25){1'bx}};
end
endcase
always @(posedge CLK)
if (!RST)
begin
am_working <= 0; working_pre <= 0; WORKING <= 0; LSAB_READ <= 0;
MCU_REQUEST_ACCESS <= 0; MCU_COLL_ADDRESS <= 0; COUNT_SENT <= 0;
IRQ_OUT <= 0; ABRUPT_STOP <= 0;
end
else
begin
if (! am_working)
begin
LSAB_SECTION <= SECTION;
len_left <= COUNT_REQ;
track_addr <= START_ADDRESS;
stop_prev_n <= 0;
am_working <= ISSUE;
MCU_REQUEST_ACCESS <= 0;
if (ISSUE)
LSAB_READ <= 1;
end
else
begin
if (stop_n)
begin
len_left <= len_left -1;
LSAB_READ <= (len_left > 1);
end
else
begin
LSAB_READ <= 0;
am_working <= 0;
COUNT_SENT <= COUNT_REQ - len_left;
IRQ_OUT <= irq;
ABRUPT_STOP <= LSAB_READ;
ANCILL_OUT <= ancill;
end
track_addr <= track_addr +1;
stop_prev_n <= stop_n;
if (trigger)
begin
MCU_WE_ARRAY <= {stop_prev_n,stop_prev_n,stop_n,stop_n};
MCU_COLL_ADDRESS <= {track_addr[8:1],1'b0};
MCU_REQUEST_ACCESS <= DRAM_SEL;
end
else
begin
MCU_REQUEST_ACCESS <= 0;
end
end
working_pre <= am_working;
WORKING <= working_pre;
end
endmodule | module hyper_mvblck_todram(input CLK,
input RST,
input LSAB_0_INT,
input LSAB_1_INT,
input LSAB_2_INT,
input LSAB_3_INT,
input LSAB_0_STOP,
input LSAB_1_STOP,
input LSAB_2_STOP,
input LSAB_3_STOP,
input [24:0] LSAB_0_ANCILL,
input [24:0] LSAB_1_ANCILL,
input [24:0] LSAB_2_ANCILL,
input [24:0] LSAB_3_ANCILL,
output LSAB_READ,
output reg [1:0] LSAB_SECTION,
input [8:0] START_ADDRESS,
input [5:0] COUNT_REQ,
input [1:0] SECTION,
input [1:0] DRAM_SEL,
input ISSUE,
output reg [5:0] COUNT_SENT,
output WORKING,
output reg IRQ_OUT,
output reg ABRUPT_STOP,
output reg [24:0] ANCILL_OUT,
output [8:0] MCU_COLL_ADDRESS,
output reg [3:0] MCU_WE_ARRAY,
output [1:0] MCU_REQUEST_ACCESS); |
reg WORKING = 1'b0,
LSAB_READ = 1'b0;
reg [1:0] MCU_REQUEST_ACCESS = 2'd0;
reg [8:0] MCU_COLL_ADDRESS = 9'd0;
reg stop_prev_n, stop_n,
am_working = 1'b0,
working_pre = 1'b0,
irq;
reg [24:0] ancill;
reg [5:0] len_left;
reg [8:0] track_addr;
wire trigger;
assign trigger = track_addr[0];
always @(LSAB_0_STOP or LSAB_1_STOP or
LSAB_2_STOP or LSAB_3_STOP or
LSAB_0_INT or LSAB_1_INT or
LSAB_2_INT or LSAB_3_INT or
LSAB_0_ANCILL or LSAB_1_ANCILL or
LSAB_2_ANCILL or LSAB_3_ANCILL or
LSAB_SECTION or LSAB_READ)
case (LSAB_SECTION)
2'b00: begin
stop_n <= (LSAB_READ && !LSAB_0_STOP);
irq <= LSAB_0_INT;
ancill <= LSAB_0_ANCILL;
end
2'b01: begin
stop_n <= (LSAB_READ && !LSAB_1_STOP);
irq <= LSAB_1_INT;
ancill <= LSAB_1_ANCILL;
end
2'b10: begin
stop_n <= (LSAB_READ && !LSAB_2_STOP);
irq <= LSAB_2_INT;
ancill <= LSAB_2_ANCILL;
end
2'b11: begin
stop_n <= (LSAB_READ && !LSAB_3_STOP);
irq <= LSAB_3_INT;
ancill <= LSAB_3_ANCILL;
end
default: begin
stop_n <= 1'bx;
irq <= 1'bx;
ancill <= {(25){1'bx}};
end
endcase
always @(posedge CLK)
if (!RST)
begin
am_working <= 0; working_pre <= 0; WORKING <= 0; LSAB_READ <= 0;
MCU_REQUEST_ACCESS <= 0; MCU_COLL_ADDRESS <= 0; COUNT_SENT <= 0;
IRQ_OUT <= 0; ABRUPT_STOP <= 0;
end
else
begin
if (! am_working)
begin
LSAB_SECTION <= SECTION;
len_left <= COUNT_REQ;
track_addr <= START_ADDRESS;
stop_prev_n <= 0;
am_working <= ISSUE;
MCU_REQUEST_ACCESS <= 0;
if (ISSUE)
LSAB_READ <= 1;
end
else
begin
if (stop_n)
begin
len_left <= len_left -1;
LSAB_READ <= (len_left > 1);
end
else
begin
LSAB_READ <= 0;
am_working <= 0;
COUNT_SENT <= COUNT_REQ - len_left;
IRQ_OUT <= irq;
ABRUPT_STOP <= LSAB_READ;
ANCILL_OUT <= ancill;
end
track_addr <= track_addr +1;
stop_prev_n <= stop_n;
if (trigger)
begin
MCU_WE_ARRAY <= {stop_prev_n,stop_prev_n,stop_n,stop_n};
MCU_COLL_ADDRESS <= {track_addr[8:1],1'b0};
MCU_REQUEST_ACCESS <= DRAM_SEL;
end
else
begin
MCU_REQUEST_ACCESS <= 0;
end
end
working_pre <= am_working;
WORKING <= working_pre;
end
endmodule | 1 |
138,602 | data/full_repos/permissive/85002992/hyperfabric/transport.v | 85,002,992 | transport.v | v | 311 | 76 | [] | [] | [] | [(1, 101), (103, 195), (197, 310)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/85002992/hyperfabric/transport.v:103: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'trans_core\'\nmodule trans_core(input CLK,\n ^~~~~~~~~~\n : ... Top module \'trans_lsab\'\nmodule trans_lsab(input CLK,\n ^~~~~~~~~~\n : ... Top module \'trans_fast\'\nmodule trans_fast(input CLK,\n ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 302,582 | module | module trans_core(input CLK,
output reg [31:0] out_0,
output reg [31:0] out_1,
output reg [31:0] out_2,
output reg [31:0] out_3,
output reg [31:0] out_4,
output reg [31:0] out_5,
output reg [31:0] out_6,
output reg [31:0] out_7,
input [31:0] in_0,
input [31:0] in_1,
input [31:0] in_2,
input [31:0] in_3,
input [31:0] in_4,
input [31:0] in_5,
input [31:0] in_6,
input [31:0] in_7,
input [15:0] isel,
input [15:0] osel);
reg [31:0] fan_block_0, fan_block_1;
wire isel_0_0, isel_0_1, isel_0_2, isel_0_3,
isel_0_4, isel_0_5, isel_0_6, isel_0_7;
wire isel_1_0, isel_1_1, isel_1_2, isel_1_3,
isel_1_4, isel_1_5, isel_1_6, isel_1_7;
wire osel_0, osel_1, osel_2, osel_3,
osel_4, osel_5, osel_6, osel_7;
wire omux_0, omux_1, omux_2, omux_3,
omux_4, omux_5, omux_6, omux_7;
wire [31:0] in_block_0,
in_block_0_0, in_block_0_1,
in_block_0_2, in_block_0_3;
wire [31:0] in_block_1,
in_block_1_0, in_block_1_1,
in_block_1_2, in_block_1_3;
wire [31:0] out_block_0, out_block_1, out_block_2, out_block_3,
out_block_4, out_block_5, out_block_6, out_block_7;
assign isel_0_0 = isel[0]; assign isel_1_0 = isel[8];
assign isel_0_1 = isel[1]; assign isel_1_1 = isel[9];
assign isel_0_2 = isel[2]; assign isel_1_2 = isel[10];
assign isel_0_3 = isel[3]; assign isel_1_3 = isel[11];
assign isel_0_4 = isel[4]; assign isel_1_4 = isel[12];
assign isel_0_5 = isel[5]; assign isel_1_5 = isel[13];
assign isel_0_6 = isel[6]; assign isel_1_6 = isel[14];
assign isel_0_7 = isel[7]; assign isel_1_7 = isel[15];
assign osel_0 = osel[0]; assign omux_0 = osel[8];
assign osel_1 = osel[1]; assign omux_1 = osel[9];
assign osel_2 = osel[2]; assign omux_2 = osel[10];
assign osel_3 = osel[3]; assign omux_3 = osel[11];
assign osel_4 = osel[4]; assign omux_4 = osel[12];
assign osel_5 = osel[5]; assign omux_5 = osel[13];
assign osel_6 = osel[6]; assign omux_6 = osel[14];
assign osel_7 = osel[7]; assign omux_7 = osel[15];
assign in_block_0_0 = ({32{isel_0_0}} & in_0) | ({32{isel_0_1}} & in_1);
assign in_block_0_1 = ({32{isel_0_2}} & in_2) | ({32{isel_0_3}} & in_3);
assign in_block_0_2 = ({32{isel_0_4}} & in_4) | ({32{isel_0_5}} & in_5);
assign in_block_0_3 = ({32{isel_0_6}} & in_6) | ({32{isel_0_7}} & in_7);
assign in_block_0 = in_block_0_0 | in_block_0_1 |
in_block_0_2 | in_block_0_3;
assign in_block_1_0 = ({32{isel_1_0}} & in_0) | ({32{isel_1_1}} & in_1);
assign in_block_1_1 = ({32{isel_1_2}} & in_2) | ({32{isel_1_3}} & in_3);
assign in_block_1_2 = ({32{isel_1_4}} & in_4) | ({32{isel_1_5}} & in_5);
assign in_block_1_3 = ({32{isel_1_6}} & in_6) | ({32{isel_1_7}} & in_7);
assign in_block_1 = in_block_1_0 | in_block_1_1 |
in_block_1_2 | in_block_1_3;
assign out_block_0 = omux_0 ? fan_block_0 : fan_block_1;
assign out_block_1 = omux_1 ? fan_block_0 : fan_block_1;
assign out_block_2 = omux_2 ? fan_block_0 : fan_block_1;
assign out_block_3 = omux_3 ? fan_block_0 : fan_block_1;
assign out_block_4 = omux_4 ? fan_block_0 : fan_block_1;
assign out_block_5 = omux_5 ? fan_block_0 : fan_block_1;
assign out_block_6 = omux_6 ? fan_block_0 : fan_block_1;
assign out_block_7 = omux_7 ? fan_block_0 : fan_block_1;
always @(posedge CLK)
begin
fan_block_0 <= in_block_0;
fan_block_1 <= in_block_1;
if (osel_0)
out_0 <= out_block_0;
if (osel_1)
out_1 <= out_block_1;
if (osel_2)
out_2 <= out_block_2;
if (osel_3)
out_3 <= out_block_3;
if (osel_4)
out_4 <= out_block_4;
if (osel_5)
out_5 <= out_block_5;
if (osel_6)
out_6 <= out_block_6;
if (osel_7)
out_7 <= out_block_7;
end
endmodule | module trans_core(input CLK,
output reg [31:0] out_0,
output reg [31:0] out_1,
output reg [31:0] out_2,
output reg [31:0] out_3,
output reg [31:0] out_4,
output reg [31:0] out_5,
output reg [31:0] out_6,
output reg [31:0] out_7,
input [31:0] in_0,
input [31:0] in_1,
input [31:0] in_2,
input [31:0] in_3,
input [31:0] in_4,
input [31:0] in_5,
input [31:0] in_6,
input [31:0] in_7,
input [15:0] isel,
input [15:0] osel); |
reg [31:0] fan_block_0, fan_block_1;
wire isel_0_0, isel_0_1, isel_0_2, isel_0_3,
isel_0_4, isel_0_5, isel_0_6, isel_0_7;
wire isel_1_0, isel_1_1, isel_1_2, isel_1_3,
isel_1_4, isel_1_5, isel_1_6, isel_1_7;
wire osel_0, osel_1, osel_2, osel_3,
osel_4, osel_5, osel_6, osel_7;
wire omux_0, omux_1, omux_2, omux_3,
omux_4, omux_5, omux_6, omux_7;
wire [31:0] in_block_0,
in_block_0_0, in_block_0_1,
in_block_0_2, in_block_0_3;
wire [31:0] in_block_1,
in_block_1_0, in_block_1_1,
in_block_1_2, in_block_1_3;
wire [31:0] out_block_0, out_block_1, out_block_2, out_block_3,
out_block_4, out_block_5, out_block_6, out_block_7;
assign isel_0_0 = isel[0]; assign isel_1_0 = isel[8];
assign isel_0_1 = isel[1]; assign isel_1_1 = isel[9];
assign isel_0_2 = isel[2]; assign isel_1_2 = isel[10];
assign isel_0_3 = isel[3]; assign isel_1_3 = isel[11];
assign isel_0_4 = isel[4]; assign isel_1_4 = isel[12];
assign isel_0_5 = isel[5]; assign isel_1_5 = isel[13];
assign isel_0_6 = isel[6]; assign isel_1_6 = isel[14];
assign isel_0_7 = isel[7]; assign isel_1_7 = isel[15];
assign osel_0 = osel[0]; assign omux_0 = osel[8];
assign osel_1 = osel[1]; assign omux_1 = osel[9];
assign osel_2 = osel[2]; assign omux_2 = osel[10];
assign osel_3 = osel[3]; assign omux_3 = osel[11];
assign osel_4 = osel[4]; assign omux_4 = osel[12];
assign osel_5 = osel[5]; assign omux_5 = osel[13];
assign osel_6 = osel[6]; assign omux_6 = osel[14];
assign osel_7 = osel[7]; assign omux_7 = osel[15];
assign in_block_0_0 = ({32{isel_0_0}} & in_0) | ({32{isel_0_1}} & in_1);
assign in_block_0_1 = ({32{isel_0_2}} & in_2) | ({32{isel_0_3}} & in_3);
assign in_block_0_2 = ({32{isel_0_4}} & in_4) | ({32{isel_0_5}} & in_5);
assign in_block_0_3 = ({32{isel_0_6}} & in_6) | ({32{isel_0_7}} & in_7);
assign in_block_0 = in_block_0_0 | in_block_0_1 |
in_block_0_2 | in_block_0_3;
assign in_block_1_0 = ({32{isel_1_0}} & in_0) | ({32{isel_1_1}} & in_1);
assign in_block_1_1 = ({32{isel_1_2}} & in_2) | ({32{isel_1_3}} & in_3);
assign in_block_1_2 = ({32{isel_1_4}} & in_4) | ({32{isel_1_5}} & in_5);
assign in_block_1_3 = ({32{isel_1_6}} & in_6) | ({32{isel_1_7}} & in_7);
assign in_block_1 = in_block_1_0 | in_block_1_1 |
in_block_1_2 | in_block_1_3;
assign out_block_0 = omux_0 ? fan_block_0 : fan_block_1;
assign out_block_1 = omux_1 ? fan_block_0 : fan_block_1;
assign out_block_2 = omux_2 ? fan_block_0 : fan_block_1;
assign out_block_3 = omux_3 ? fan_block_0 : fan_block_1;
assign out_block_4 = omux_4 ? fan_block_0 : fan_block_1;
assign out_block_5 = omux_5 ? fan_block_0 : fan_block_1;
assign out_block_6 = omux_6 ? fan_block_0 : fan_block_1;
assign out_block_7 = omux_7 ? fan_block_0 : fan_block_1;
always @(posedge CLK)
begin
fan_block_0 <= in_block_0;
fan_block_1 <= in_block_1;
if (osel_0)
out_0 <= out_block_0;
if (osel_1)
out_1 <= out_block_1;
if (osel_2)
out_2 <= out_block_2;
if (osel_3)
out_3 <= out_block_3;
if (osel_4)
out_4 <= out_block_4;
if (osel_5)
out_5 <= out_block_5;
if (osel_6)
out_6 <= out_block_6;
if (osel_7)
out_7 <= out_block_7;
end
endmodule | 1 |
138,603 | data/full_repos/permissive/85002992/hyperfabric/transport.v | 85,002,992 | transport.v | v | 311 | 76 | [] | [] | [] | [(1, 101), (103, 195), (197, 310)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/85002992/hyperfabric/transport.v:103: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'trans_core\'\nmodule trans_core(input CLK,\n ^~~~~~~~~~\n : ... Top module \'trans_lsab\'\nmodule trans_lsab(input CLK,\n ^~~~~~~~~~\n : ... Top module \'trans_fast\'\nmodule trans_fast(input CLK,\n ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 302,582 | module | module trans_lsab(input CLK,
output reg [31:0] out_0,
output reg [31:0] out_1,
output reg [31:0] out_2,
output reg [31:0] out_3,
output reg [31:0] out_4,
output reg [31:0] out_5,
output reg [31:0] out_6,
output reg [31:0] out_7,
input [31:0] in_0,
input [31:0] in_1,
input [31:0] in_2,
input [31:0] in_3,
input [31:0] in_4,
input [31:0] in_5,
input [31:0] in_6,
input [31:0] in_7,
input [31:0] lsab,
input [7:0] isel,
input [15:0] osel);
reg [31:0] fan_block_0;
wire isel_0_0, isel_0_1, isel_0_2, isel_0_3,
isel_0_4, isel_0_5, isel_0_6, isel_0_7;
wire osel_0, osel_1, osel_2, osel_3,
osel_4, osel_5, osel_6, osel_7;
wire omux_0, omux_1, omux_2, omux_3,
omux_4, omux_5, omux_6, omux_7;
wire [31:0] fan_block_1;
wire [31:0] in_block_0,
in_block_0_0, in_block_0_1,
in_block_0_2, in_block_0_3;
wire [31:0] out_block_0, out_block_1, out_block_2, out_block_3,
out_block_4, out_block_5, out_block_6, out_block_7;
assign isel_0_0 = isel[0];
assign isel_0_1 = isel[1];
assign isel_0_2 = isel[2];
assign isel_0_3 = isel[3];
assign isel_0_4 = isel[4];
assign isel_0_5 = isel[5];
assign isel_0_6 = isel[6];
assign isel_0_7 = isel[7];
assign osel_0 = osel[0]; assign omux_0 = osel[8];
assign osel_1 = osel[1]; assign omux_1 = osel[9];
assign osel_2 = osel[2]; assign omux_2 = osel[10];
assign osel_3 = osel[3]; assign omux_3 = osel[11];
assign osel_4 = osel[4]; assign omux_4 = osel[12];
assign osel_5 = osel[5]; assign omux_5 = osel[13];
assign osel_6 = osel[6]; assign omux_6 = osel[14];
assign osel_7 = osel[7]; assign omux_7 = osel[15];
assign in_block_0_0 = ({32{isel_0_0}} & in_0) | ({32{isel_0_1}} & in_1);
assign in_block_0_1 = ({32{isel_0_2}} & in_2) | ({32{isel_0_3}} & in_3);
assign in_block_0_2 = ({32{isel_0_4}} & in_4) | ({32{isel_0_5}} & in_5);
assign in_block_0_3 = ({32{isel_0_6}} & in_6) | ({32{isel_0_7}} & in_7);
assign in_block_0 = in_block_0_0 | in_block_0_1 |
in_block_0_2 | in_block_0_3;
assign out_block_0 = omux_0 ? fan_block_0 : fan_block_1;
assign out_block_1 = omux_1 ? fan_block_0 : fan_block_1;
assign out_block_2 = omux_2 ? fan_block_0 : fan_block_1;
assign out_block_3 = omux_3 ? fan_block_0 : fan_block_1;
assign out_block_4 = omux_4 ? fan_block_0 : fan_block_1;
assign out_block_5 = omux_5 ? fan_block_0 : fan_block_1;
assign out_block_6 = omux_6 ? fan_block_0 : fan_block_1;
assign out_block_7 = omux_7 ? fan_block_0 : fan_block_1;
assign fan_block_1 = lsab;
always @(posedge CLK)
begin
fan_block_0 <= in_block_0;
if (osel_0)
out_0 <= out_block_0;
if (osel_1)
out_1 <= out_block_1;
if (osel_2)
out_2 <= out_block_2;
if (osel_3)
out_3 <= out_block_3;
if (osel_4)
out_4 <= out_block_4;
if (osel_5)
out_5 <= out_block_5;
if (osel_6)
out_6 <= out_block_6;
if (osel_7)
out_7 <= out_block_7;
end
endmodule | module trans_lsab(input CLK,
output reg [31:0] out_0,
output reg [31:0] out_1,
output reg [31:0] out_2,
output reg [31:0] out_3,
output reg [31:0] out_4,
output reg [31:0] out_5,
output reg [31:0] out_6,
output reg [31:0] out_7,
input [31:0] in_0,
input [31:0] in_1,
input [31:0] in_2,
input [31:0] in_3,
input [31:0] in_4,
input [31:0] in_5,
input [31:0] in_6,
input [31:0] in_7,
input [31:0] lsab,
input [7:0] isel,
input [15:0] osel); |
reg [31:0] fan_block_0;
wire isel_0_0, isel_0_1, isel_0_2, isel_0_3,
isel_0_4, isel_0_5, isel_0_6, isel_0_7;
wire osel_0, osel_1, osel_2, osel_3,
osel_4, osel_5, osel_6, osel_7;
wire omux_0, omux_1, omux_2, omux_3,
omux_4, omux_5, omux_6, omux_7;
wire [31:0] fan_block_1;
wire [31:0] in_block_0,
in_block_0_0, in_block_0_1,
in_block_0_2, in_block_0_3;
wire [31:0] out_block_0, out_block_1, out_block_2, out_block_3,
out_block_4, out_block_5, out_block_6, out_block_7;
assign isel_0_0 = isel[0];
assign isel_0_1 = isel[1];
assign isel_0_2 = isel[2];
assign isel_0_3 = isel[3];
assign isel_0_4 = isel[4];
assign isel_0_5 = isel[5];
assign isel_0_6 = isel[6];
assign isel_0_7 = isel[7];
assign osel_0 = osel[0]; assign omux_0 = osel[8];
assign osel_1 = osel[1]; assign omux_1 = osel[9];
assign osel_2 = osel[2]; assign omux_2 = osel[10];
assign osel_3 = osel[3]; assign omux_3 = osel[11];
assign osel_4 = osel[4]; assign omux_4 = osel[12];
assign osel_5 = osel[5]; assign omux_5 = osel[13];
assign osel_6 = osel[6]; assign omux_6 = osel[14];
assign osel_7 = osel[7]; assign omux_7 = osel[15];
assign in_block_0_0 = ({32{isel_0_0}} & in_0) | ({32{isel_0_1}} & in_1);
assign in_block_0_1 = ({32{isel_0_2}} & in_2) | ({32{isel_0_3}} & in_3);
assign in_block_0_2 = ({32{isel_0_4}} & in_4) | ({32{isel_0_5}} & in_5);
assign in_block_0_3 = ({32{isel_0_6}} & in_6) | ({32{isel_0_7}} & in_7);
assign in_block_0 = in_block_0_0 | in_block_0_1 |
in_block_0_2 | in_block_0_3;
assign out_block_0 = omux_0 ? fan_block_0 : fan_block_1;
assign out_block_1 = omux_1 ? fan_block_0 : fan_block_1;
assign out_block_2 = omux_2 ? fan_block_0 : fan_block_1;
assign out_block_3 = omux_3 ? fan_block_0 : fan_block_1;
assign out_block_4 = omux_4 ? fan_block_0 : fan_block_1;
assign out_block_5 = omux_5 ? fan_block_0 : fan_block_1;
assign out_block_6 = omux_6 ? fan_block_0 : fan_block_1;
assign out_block_7 = omux_7 ? fan_block_0 : fan_block_1;
assign fan_block_1 = lsab;
always @(posedge CLK)
begin
fan_block_0 <= in_block_0;
if (osel_0)
out_0 <= out_block_0;
if (osel_1)
out_1 <= out_block_1;
if (osel_2)
out_2 <= out_block_2;
if (osel_3)
out_3 <= out_block_3;
if (osel_4)
out_4 <= out_block_4;
if (osel_5)
out_5 <= out_block_5;
if (osel_6)
out_6 <= out_block_6;
if (osel_7)
out_7 <= out_block_7;
end
endmodule | 1 |
138,604 | data/full_repos/permissive/85002992/hyperfabric/transport.v | 85,002,992 | transport.v | v | 311 | 76 | [] | [] | [] | [(1, 101), (103, 195), (197, 310)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/85002992/hyperfabric/transport.v:103: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'trans_core\'\nmodule trans_core(input CLK,\n ^~~~~~~~~~\n : ... Top module \'trans_lsab\'\nmodule trans_lsab(input CLK,\n ^~~~~~~~~~\n : ... Top module \'trans_fast\'\nmodule trans_fast(input CLK,\n ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 302,582 | module | module trans_fast(input CLK,
output reg [31:0] out_0,
output reg [31:0] out_1,
output reg [31:0] out_2,
output reg [31:0] out_3,
output reg [31:0] out_4,
output reg [31:0] out_5,
output reg [31:0] out_6,
output reg [31:0] out_7,
input [31:0] in_0,
input [31:0] in_1,
input [31:0] in_2,
input [31:0] in_3,
input [7:0] isel,
input [15:0] osel);
reg [31:0] fan_block_0;
wire osel_0, osel_1, osel_2, osel_3,
osel_4, osel_5, osel_6, osel_7;
wire omux_0, omux_1, omux_2, omux_3,
omux_4, omux_5, omux_6, omux_7;
wire [31:0] out_block_0, out_block_1, out_block_2, out_block_3,
out_block_4, out_block_5, out_block_6, out_block_7;
wire [31:0] s_gate;
wire [31:0] f_gate;
wire sel_high, sel_low;
assign osel_0 = osel[0]; assign omux_0 = osel[8];
assign osel_1 = osel[1]; assign omux_1 = osel[9];
assign osel_2 = osel[2]; assign omux_2 = osel[10];
assign osel_3 = osel[3]; assign omux_3 = osel[11];
assign osel_4 = osel[4]; assign omux_4 = osel[12];
assign osel_5 = osel[5]; assign omux_5 = osel[13];
assign osel_6 = osel[6]; assign omux_6 = osel[14];
assign osel_7 = osel[7]; assign omux_7 = osel[15];
assign out_block_0 = fan_block_0;
assign out_block_1 = fan_block_0;
assign out_block_2 = fan_block_0;
assign out_block_3 = fan_block_0;
assign out_block_4 = fan_block_0;
assign out_block_5 = fan_block_0;
assign out_block_6 = fan_block_0;
assign out_block_7 = fan_block_0;
assign sel_low = isel[0];
assign sel_high = isel[1];
assign s_gate = sel_high ? ({32{sel_low}}) : (sel_low ? in_2 : in_3);
assign f_gate[0] = sel_high ?(s_gate[0] ?in_0[0] :in_1[0] ):s_gate[0];
assign f_gate[1] = sel_high ?(s_gate[1] ?in_0[1] :in_1[1] ):s_gate[1];
assign f_gate[2] = sel_high ?(s_gate[2] ?in_0[2] :in_1[2] ):s_gate[2];
assign f_gate[3] = sel_high ?(s_gate[3] ?in_0[3] :in_1[3] ):s_gate[3];
assign f_gate[4] = sel_high ?(s_gate[4] ?in_0[4] :in_1[4] ):s_gate[4];
assign f_gate[5] = sel_high ?(s_gate[5] ?in_0[5] :in_1[5] ):s_gate[5];
assign f_gate[6] = sel_high ?(s_gate[6] ?in_0[6] :in_1[6] ):s_gate[6];
assign f_gate[7] = sel_high ?(s_gate[7] ?in_0[7] :in_1[7] ):s_gate[7];
assign f_gate[8] = sel_high ?(s_gate[8] ?in_0[8] :in_1[8] ):s_gate[8];
assign f_gate[9] = sel_high ?(s_gate[9] ?in_0[9] :in_1[9] ):s_gate[9];
assign f_gate[10]= sel_high ?(s_gate[10]?in_0[10]:in_1[10]):s_gate[10];
assign f_gate[11]= sel_high ?(s_gate[11]?in_0[11]:in_1[11]):s_gate[11];
assign f_gate[12]= sel_high ?(s_gate[12]?in_0[12]:in_1[12]):s_gate[12];
assign f_gate[13]= sel_high ?(s_gate[13]?in_0[13]:in_1[13]):s_gate[13];
assign f_gate[14]= sel_high ?(s_gate[14]?in_0[14]:in_1[14]):s_gate[14];
assign f_gate[15]= sel_high ?(s_gate[15]?in_0[15]:in_1[15]):s_gate[15];
assign f_gate[16]= sel_high ?(s_gate[16]?in_0[16]:in_1[16]):s_gate[16];
assign f_gate[17]= sel_high ?(s_gate[17]?in_0[17]:in_1[17]):s_gate[17];
assign f_gate[18]= sel_high ?(s_gate[18]?in_0[18]:in_1[18]):s_gate[18];
assign f_gate[19]= sel_high ?(s_gate[19]?in_0[19]:in_1[19]):s_gate[19];
assign f_gate[20]= sel_high ?(s_gate[20]?in_0[20]:in_1[20]):s_gate[20];
assign f_gate[21]= sel_high ?(s_gate[21]?in_0[21]:in_1[21]):s_gate[21];
assign f_gate[22]= sel_high ?(s_gate[22]?in_0[22]:in_1[22]):s_gate[22];
assign f_gate[23]= sel_high ?(s_gate[23]?in_0[23]:in_1[23]):s_gate[23];
assign f_gate[24]= sel_high ?(s_gate[24]?in_0[24]:in_1[24]):s_gate[24];
assign f_gate[25]= sel_high ?(s_gate[25]?in_0[25]:in_1[25]):s_gate[25];
assign f_gate[26]= sel_high ?(s_gate[26]?in_0[26]:in_1[26]):s_gate[26];
assign f_gate[27]= sel_high ?(s_gate[27]?in_0[27]:in_1[27]):s_gate[27];
assign f_gate[28]= sel_high ?(s_gate[28]?in_0[28]:in_1[28]):s_gate[28];
assign f_gate[29]= sel_high ?(s_gate[29]?in_0[29]:in_1[29]):s_gate[29];
assign f_gate[30]= sel_high ?(s_gate[30]?in_0[30]:in_1[30]):s_gate[30];
assign f_gate[31]= sel_high ?(s_gate[31]?in_0[31]:in_1[31]):s_gate[31];
always @(posedge CLK)
begin
fan_block_0 <= f_gate;
if (osel_0)
out_0 <= out_block_0;
if (osel_1)
out_1 <= out_block_1;
if (osel_2)
out_2 <= out_block_2;
if (osel_3)
out_3 <= out_block_3;
if (osel_4)
out_4 <= out_block_4;
if (osel_5)
out_5 <= out_block_5;
if (osel_6)
out_6 <= out_block_6;
if (osel_7)
out_7 <= out_block_7;
end
endmodule | module trans_fast(input CLK,
output reg [31:0] out_0,
output reg [31:0] out_1,
output reg [31:0] out_2,
output reg [31:0] out_3,
output reg [31:0] out_4,
output reg [31:0] out_5,
output reg [31:0] out_6,
output reg [31:0] out_7,
input [31:0] in_0,
input [31:0] in_1,
input [31:0] in_2,
input [31:0] in_3,
input [7:0] isel,
input [15:0] osel); |
reg [31:0] fan_block_0;
wire osel_0, osel_1, osel_2, osel_3,
osel_4, osel_5, osel_6, osel_7;
wire omux_0, omux_1, omux_2, omux_3,
omux_4, omux_5, omux_6, omux_7;
wire [31:0] out_block_0, out_block_1, out_block_2, out_block_3,
out_block_4, out_block_5, out_block_6, out_block_7;
wire [31:0] s_gate;
wire [31:0] f_gate;
wire sel_high, sel_low;
assign osel_0 = osel[0]; assign omux_0 = osel[8];
assign osel_1 = osel[1]; assign omux_1 = osel[9];
assign osel_2 = osel[2]; assign omux_2 = osel[10];
assign osel_3 = osel[3]; assign omux_3 = osel[11];
assign osel_4 = osel[4]; assign omux_4 = osel[12];
assign osel_5 = osel[5]; assign omux_5 = osel[13];
assign osel_6 = osel[6]; assign omux_6 = osel[14];
assign osel_7 = osel[7]; assign omux_7 = osel[15];
assign out_block_0 = fan_block_0;
assign out_block_1 = fan_block_0;
assign out_block_2 = fan_block_0;
assign out_block_3 = fan_block_0;
assign out_block_4 = fan_block_0;
assign out_block_5 = fan_block_0;
assign out_block_6 = fan_block_0;
assign out_block_7 = fan_block_0;
assign sel_low = isel[0];
assign sel_high = isel[1];
assign s_gate = sel_high ? ({32{sel_low}}) : (sel_low ? in_2 : in_3);
assign f_gate[0] = sel_high ?(s_gate[0] ?in_0[0] :in_1[0] ):s_gate[0];
assign f_gate[1] = sel_high ?(s_gate[1] ?in_0[1] :in_1[1] ):s_gate[1];
assign f_gate[2] = sel_high ?(s_gate[2] ?in_0[2] :in_1[2] ):s_gate[2];
assign f_gate[3] = sel_high ?(s_gate[3] ?in_0[3] :in_1[3] ):s_gate[3];
assign f_gate[4] = sel_high ?(s_gate[4] ?in_0[4] :in_1[4] ):s_gate[4];
assign f_gate[5] = sel_high ?(s_gate[5] ?in_0[5] :in_1[5] ):s_gate[5];
assign f_gate[6] = sel_high ?(s_gate[6] ?in_0[6] :in_1[6] ):s_gate[6];
assign f_gate[7] = sel_high ?(s_gate[7] ?in_0[7] :in_1[7] ):s_gate[7];
assign f_gate[8] = sel_high ?(s_gate[8] ?in_0[8] :in_1[8] ):s_gate[8];
assign f_gate[9] = sel_high ?(s_gate[9] ?in_0[9] :in_1[9] ):s_gate[9];
assign f_gate[10]= sel_high ?(s_gate[10]?in_0[10]:in_1[10]):s_gate[10];
assign f_gate[11]= sel_high ?(s_gate[11]?in_0[11]:in_1[11]):s_gate[11];
assign f_gate[12]= sel_high ?(s_gate[12]?in_0[12]:in_1[12]):s_gate[12];
assign f_gate[13]= sel_high ?(s_gate[13]?in_0[13]:in_1[13]):s_gate[13];
assign f_gate[14]= sel_high ?(s_gate[14]?in_0[14]:in_1[14]):s_gate[14];
assign f_gate[15]= sel_high ?(s_gate[15]?in_0[15]:in_1[15]):s_gate[15];
assign f_gate[16]= sel_high ?(s_gate[16]?in_0[16]:in_1[16]):s_gate[16];
assign f_gate[17]= sel_high ?(s_gate[17]?in_0[17]:in_1[17]):s_gate[17];
assign f_gate[18]= sel_high ?(s_gate[18]?in_0[18]:in_1[18]):s_gate[18];
assign f_gate[19]= sel_high ?(s_gate[19]?in_0[19]:in_1[19]):s_gate[19];
assign f_gate[20]= sel_high ?(s_gate[20]?in_0[20]:in_1[20]):s_gate[20];
assign f_gate[21]= sel_high ?(s_gate[21]?in_0[21]:in_1[21]):s_gate[21];
assign f_gate[22]= sel_high ?(s_gate[22]?in_0[22]:in_1[22]):s_gate[22];
assign f_gate[23]= sel_high ?(s_gate[23]?in_0[23]:in_1[23]):s_gate[23];
assign f_gate[24]= sel_high ?(s_gate[24]?in_0[24]:in_1[24]):s_gate[24];
assign f_gate[25]= sel_high ?(s_gate[25]?in_0[25]:in_1[25]):s_gate[25];
assign f_gate[26]= sel_high ?(s_gate[26]?in_0[26]:in_1[26]):s_gate[26];
assign f_gate[27]= sel_high ?(s_gate[27]?in_0[27]:in_1[27]):s_gate[27];
assign f_gate[28]= sel_high ?(s_gate[28]?in_0[28]:in_1[28]):s_gate[28];
assign f_gate[29]= sel_high ?(s_gate[29]?in_0[29]:in_1[29]):s_gate[29];
assign f_gate[30]= sel_high ?(s_gate[30]?in_0[30]:in_1[30]):s_gate[30];
assign f_gate[31]= sel_high ?(s_gate[31]?in_0[31]:in_1[31]):s_gate[31];
always @(posedge CLK)
begin
fan_block_0 <= f_gate;
if (osel_0)
out_0 <= out_block_0;
if (osel_1)
out_1 <= out_block_1;
if (osel_2)
out_2 <= out_block_2;
if (osel_3)
out_3 <= out_block_3;
if (osel_4)
out_4 <= out_block_4;
if (osel_5)
out_5 <= out_block_5;
if (osel_6)
out_6 <= out_block_6;
if (osel_7)
out_7 <= out_block_7;
end
endmodule | 1 |
138,611 | data/full_repos/permissive/85002992/mcu/integration3.v | 85,002,992 | integration3.v | v | 102 | 61 | [] | [] | [] | [(1, 101)] | null | null | 1: b"%Error: data/full_repos/permissive/85002992/mcu/integration3.v:49: Cannot find file containing module: 'clock_driver'\n clock_driver clock(.CLK_n(CLK_n),\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/85002992/mcu,data/full_repos/permissive/85002992/clock_driver\n data/full_repos/permissive/85002992/mcu,data/full_repos/permissive/85002992/clock_driver.v\n data/full_repos/permissive/85002992/mcu,data/full_repos/permissive/85002992/clock_driver.sv\n clock_driver\n clock_driver.v\n clock_driver.sv\n obj_dir/clock_driver\n obj_dir/clock_driver.v\n obj_dir/clock_driver.sv\n%Error: data/full_repos/permissive/85002992/mcu/integration3.v:54: Cannot find file containing module: 'initializer'\n initializer initializer_m(.CLK_n(CLK_n),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/integration3.v:64: Cannot find file containing module: 'state2'\n state2 interdictor_tracker(.CLK(CLK_n),\n ^~~~~~\n%Error: data/full_repos/permissive/85002992/mcu/integration3.v:89: Cannot find file containing module: 'outputs'\n outputs data_driver(.CLK_n(CLK_n),\n ^~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 302,587 | module | module ddr_memory_controler(input CLK_n,
input CLK_dn,
input RST_MASTER,
output MEM_CLK_P,
output MEM_CLK_N,
output CKE,
output [2:0] COMMAND,
output [13:0] ADDRESS,
output [2:0] BANK,
inout [15:0] DQ,
inout UDQS,
inout LDQS,
output UDM,
output LDM,
output CS,
input refresh_strobe,
input [25:0] rand_req_address,
input rand_req_we,
input [3:0] rand_req_we_array,
input rand_req,
output rand_req_ack,
input [31:0] rand_req_datain,
input [25:0] bulk_req_address,
input bulk_req_we,
input [3:0] bulk_req_we_array,
input bulk_req,
output bulk_req_ack,
input bulk_req_algn,
output bulk_req_algn_ack,
input [31:0] bulk_req_datain,
output [31:0] user_req_dataout);
wire [31:0] user_req_datain;
wire [2:0] command_user;
wire [13:0] address_user;
wire [2:0] bank_user;
wire [3:0] internal_com_lat,
internal_we_array;
wire internal_data_mux,
internal_data_mux_invert;
assign CS = 1'b0;
assign user_req_datain = (internal_data_mux_invert ?
!internal_data_mux : internal_data_mux) ?
bulk_req_datain : rand_req_datain;
clock_driver clock(.CLK_n(CLK_n),
.RST(RST_MASTER),
.CLK_P(MEM_CLK_P),
.CLK_N(MEM_CLK_N));
initializer initializer_m(.CLK_n(CLK_n),
.RST(RST_MASTER),
.CKE(CKE),
.COMMAND_PIN(COMMAND),
.ADDRESS_PIN(ADDRESS),
.BANK_PIN(BANK),
.COMMAND_USER(command_user),
.ADDRESS_USER(address_user),
.BANK_USER(bank_user));
state2 interdictor_tracker(.CLK(CLK_n),
.REFRESH_STROBE(refresh_strobe),
.ADDRESS_RAND(rand_req_address),
.port_WE_RAND(rand_req_we),
.port_REQUEST_ACCESS_RAND(rand_req),
.GRANT_ACCESS_RAND(rand_req_ack),
.WE_ARRAY_RAND(rand_req_we_array),
.port_ADDRESS_BULK(bulk_req_address),
.port_WE_BULK(bulk_req_we),
.port_REQUEST_ACCESS_BULK(bulk_req),
.GRANT_ACCESS_BULK(bulk_req_ack),
.port_REQUEST_ALIGN_BULK(bulk_req_algn),
.GRANT_ALIGN_BULK(bulk_req_algn_ack),
.port_WE_ARRAY_BULK(bulk_req_we_array),
.ADDRESS_REG(address_user),
.BANK_REG(bank_user),
.COMMAND_REG(command_user),
.INTERNAL_DATA_MUX(internal_data_mux),
.INTERNAL_DATA_MUX_INVERT(internal_data_mux_invert),
.INTERNAL_COMMAND_LATCHED(internal_com_lat),
.INTERNAL_WE_ARRAY(internal_we_array));
outputs data_driver(.CLK_n(CLK_n),
.CLK_dn(CLK_dn),
.COMMAND_LATCHED(internal_com_lat),
.WE_ARRAY(internal_we_array),
.port_DATA_W(user_req_datain),
.DQ(DQ),
.UDQS(UDQS),
.LDQS(LDQS),
.DATA_R(user_req_dataout),
.UDM(UDM),
.LDM(LDM));
endmodule | module ddr_memory_controler(input CLK_n,
input CLK_dn,
input RST_MASTER,
output MEM_CLK_P,
output MEM_CLK_N,
output CKE,
output [2:0] COMMAND,
output [13:0] ADDRESS,
output [2:0] BANK,
inout [15:0] DQ,
inout UDQS,
inout LDQS,
output UDM,
output LDM,
output CS,
input refresh_strobe,
input [25:0] rand_req_address,
input rand_req_we,
input [3:0] rand_req_we_array,
input rand_req,
output rand_req_ack,
input [31:0] rand_req_datain,
input [25:0] bulk_req_address,
input bulk_req_we,
input [3:0] bulk_req_we_array,
input bulk_req,
output bulk_req_ack,
input bulk_req_algn,
output bulk_req_algn_ack,
input [31:0] bulk_req_datain,
output [31:0] user_req_dataout); |
wire [31:0] user_req_datain;
wire [2:0] command_user;
wire [13:0] address_user;
wire [2:0] bank_user;
wire [3:0] internal_com_lat,
internal_we_array;
wire internal_data_mux,
internal_data_mux_invert;
assign CS = 1'b0;
assign user_req_datain = (internal_data_mux_invert ?
!internal_data_mux : internal_data_mux) ?
bulk_req_datain : rand_req_datain;
clock_driver clock(.CLK_n(CLK_n),
.RST(RST_MASTER),
.CLK_P(MEM_CLK_P),
.CLK_N(MEM_CLK_N));
initializer initializer_m(.CLK_n(CLK_n),
.RST(RST_MASTER),
.CKE(CKE),
.COMMAND_PIN(COMMAND),
.ADDRESS_PIN(ADDRESS),
.BANK_PIN(BANK),
.COMMAND_USER(command_user),
.ADDRESS_USER(address_user),
.BANK_USER(bank_user));
state2 interdictor_tracker(.CLK(CLK_n),
.REFRESH_STROBE(refresh_strobe),
.ADDRESS_RAND(rand_req_address),
.port_WE_RAND(rand_req_we),
.port_REQUEST_ACCESS_RAND(rand_req),
.GRANT_ACCESS_RAND(rand_req_ack),
.WE_ARRAY_RAND(rand_req_we_array),
.port_ADDRESS_BULK(bulk_req_address),
.port_WE_BULK(bulk_req_we),
.port_REQUEST_ACCESS_BULK(bulk_req),
.GRANT_ACCESS_BULK(bulk_req_ack),
.port_REQUEST_ALIGN_BULK(bulk_req_algn),
.GRANT_ALIGN_BULK(bulk_req_algn_ack),
.port_WE_ARRAY_BULK(bulk_req_we_array),
.ADDRESS_REG(address_user),
.BANK_REG(bank_user),
.COMMAND_REG(command_user),
.INTERNAL_DATA_MUX(internal_data_mux),
.INTERNAL_DATA_MUX_INVERT(internal_data_mux_invert),
.INTERNAL_COMMAND_LATCHED(internal_com_lat),
.INTERNAL_WE_ARRAY(internal_we_array));
outputs data_driver(.CLK_n(CLK_n),
.CLK_dn(CLK_dn),
.COMMAND_LATCHED(internal_com_lat),
.WE_ARRAY(internal_we_array),
.port_DATA_W(user_req_datain),
.DQ(DQ),
.UDQS(UDQS),
.LDQS(LDQS),
.DATA_R(user_req_dataout),
.UDM(UDM),
.LDM(LDM));
endmodule | 1 |
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