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138,217 | data/full_repos/permissive/82757492/AI/AI.v | 82,757,492 | AI.v | v | 109 | 125 | [] | [] | [] | [(2, 17), (21, 31), (36, 62), (65, 71), (73, 79), (83, 95), (97, 108)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/82757492/AI/AI.v:97: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SimpleAI\'\nmodule SimpleAI (\n ^~~~~~~~\n : ... Top module \'Select2\'\nmodule Select2(\n ^~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 301,936 | module | module TwoInGrid(
input [8:0] X_state,
input [8:0] Y_state,
output wire [8:0] cout
);
wire [8:0] rows, cols;
wire [2:0] diag1, diag2;
TwoInRow row1 (X_state[2:0], Y_state[2:0], rows[2:0]);
TwoInRow row2 (X_state[5:3], Y_state[5:3], rows[5:3]);
TwoInRow row3 (X_state[8:6], Y_state[8:6], rows[8:6]);
TwoInRow col1 ({X_state[2], X_state[5], X_state[8]}, {Y_state[2], Y_state[5], Y_state[8]}, {cols[2], cols[5], cols[8]});
TwoInRow col2 ({X_state[1], X_state[4], X_state[7]}, {Y_state[1], Y_state[4], Y_state[7]}, {cols[1], cols[4], cols[7]});
TwoInRow col3 ({X_state[0], X_state[3], X_state[6]}, {Y_state[0], Y_state[3], Y_state[6]}, {cols[0], cols[3], cols[6]});
TwoInRow diagCheck1 ({X_state[8], X_state[4], X_state[0]}, {Y_state[8], Y_state[4], Y_state[0]}, diag1);
TwoInRow diagCheck2 ({X_state[6], X_state[4], X_state[2]}, {Y_state[6], Y_state[4], Y_state[2]}, diag2);
assign cout = rows | cols |
{diag1[2], 1'b0, 1'b0, 1'b0, diag1[1], 1'b0, 1'b0, 1'b0, diag1[0]} |
{1'b0, 1'b0, diag2[2], 1'b0, diag2[1], 1'b0, diag2[0], 1'b0, 1'b0};
endmodule | module TwoInGrid(
input [8:0] X_state,
input [8:0] Y_state,
output wire [8:0] cout
); |
wire [8:0] rows, cols;
wire [2:0] diag1, diag2;
TwoInRow row1 (X_state[2:0], Y_state[2:0], rows[2:0]);
TwoInRow row2 (X_state[5:3], Y_state[5:3], rows[5:3]);
TwoInRow row3 (X_state[8:6], Y_state[8:6], rows[8:6]);
TwoInRow col1 ({X_state[2], X_state[5], X_state[8]}, {Y_state[2], Y_state[5], Y_state[8]}, {cols[2], cols[5], cols[8]});
TwoInRow col2 ({X_state[1], X_state[4], X_state[7]}, {Y_state[1], Y_state[4], Y_state[7]}, {cols[1], cols[4], cols[7]});
TwoInRow col3 ({X_state[0], X_state[3], X_state[6]}, {Y_state[0], Y_state[3], Y_state[6]}, {cols[0], cols[3], cols[6]});
TwoInRow diagCheck1 ({X_state[8], X_state[4], X_state[0]}, {Y_state[8], Y_state[4], Y_state[0]}, diag1);
TwoInRow diagCheck2 ({X_state[6], X_state[4], X_state[2]}, {Y_state[6], Y_state[4], Y_state[2]}, diag2);
assign cout = rows | cols |
{diag1[2], 1'b0, 1'b0, 1'b0, diag1[1], 1'b0, 1'b0, 1'b0, diag1[0]} |
{1'b0, 1'b0, diag2[2], 1'b0, diag2[1], 1'b0, diag2[0], 1'b0, 1'b0};
endmodule | 0 |
138,218 | data/full_repos/permissive/82757492/AI/AI.v | 82,757,492 | AI.v | v | 109 | 125 | [] | [] | [] | [(2, 17), (21, 31), (36, 62), (65, 71), (73, 79), (83, 95), (97, 108)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/82757492/AI/AI.v:97: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SimpleAI\'\nmodule SimpleAI (\n ^~~~~~~~\n : ... Top module \'Select2\'\nmodule Select2(\n ^~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 301,936 | module | module RARb #(parameter n = 8)
(r, g);
input [n - 1 : 0] r;
output [n - 1 : 0] g;
wire [ n - 1 : 0 ] c = {1'b1, (~r[n-1:1] & c[n-1:1])};
assign g = r & c;
endmodule | module RARb #(parameter n = 8)
(r, g); |
input [n - 1 : 0] r;
output [n - 1 : 0] g;
wire [ n - 1 : 0 ] c = {1'b1, (~r[n-1:1] & c[n-1:1])};
assign g = r & c;
endmodule | 0 |
138,219 | data/full_repos/permissive/82757492/AI/AI.v | 82,757,492 | AI.v | v | 109 | 125 | [] | [] | [] | [(2, 17), (21, 31), (36, 62), (65, 71), (73, 79), (83, 95), (97, 108)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/82757492/AI/AI.v:97: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SimpleAI\'\nmodule SimpleAI (\n ^~~~~~~~\n : ... Top module \'Select2\'\nmodule Select2(\n ^~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 301,936 | module | module Empty(
input [8:0] in,
output [8:0] out);
RARb #(9) ra({in[4],in[0],in[2],in[6],in[8],in[1],in[3],in[5],in[7]},
{out[4],out[0],out[2],out[6],out[8],out[1],out[3],out[5],out[7]}) ;
endmodule | module Empty(
input [8:0] in,
output [8:0] out); |
RARb #(9) ra({in[4],in[0],in[2],in[6],in[8],in[1],in[3],in[5],in[7]},
{out[4],out[0],out[2],out[6],out[8],out[1],out[3],out[5],out[7]}) ;
endmodule | 0 |
138,220 | data/full_repos/permissive/82757492/AI/AI.v | 82,757,492 | AI.v | v | 109 | 125 | [] | [] | [] | [(2, 17), (21, 31), (36, 62), (65, 71), (73, 79), (83, 95), (97, 108)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/82757492/AI/AI.v:97: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SimpleAI\'\nmodule SimpleAI (\n ^~~~~~~~\n : ... Top module \'Select2\'\nmodule Select2(\n ^~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 301,936 | module | module Select3(
input [8:0] a,
input [8:0] b,
input [8:0] c,
output wire [8:0] out);
wire [26:0] x;
RARb #(27) ra({a, b, c}, x);
assign out = x[26:18] | x[17:9] | x[8:0];
endmodule | module Select3(
input [8:0] a,
input [8:0] b,
input [8:0] c,
output wire [8:0] out); |
wire [26:0] x;
RARb #(27) ra({a, b, c}, x);
assign out = x[26:18] | x[17:9] | x[8:0];
endmodule | 0 |
138,221 | data/full_repos/permissive/82757492/AI/AI.v | 82,757,492 | AI.v | v | 109 | 125 | [] | [] | [] | [(2, 17), (21, 31), (36, 62), (65, 71), (73, 79), (83, 95), (97, 108)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/82757492/AI/AI.v:97: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'SimpleAI\'\nmodule SimpleAI (\n ^~~~~~~~\n : ... Top module \'Select2\'\nmodule Select2(\n ^~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 301,936 | module | module Select2(
input [8:0] a,
input [8:0] b,
output wire [8:0] out);
wire [17:0] x;
RARb #(18) ra({a, b}, x);
assign out = x[17:9] | x[8:0];
endmodule | module Select2(
input [8:0] a,
input [8:0] b,
output wire [8:0] out); |
wire [17:0] x;
RARb #(18) ra({a, b}, x);
assign out = x[17:9] | x[8:0];
endmodule | 0 |
138,222 | data/full_repos/permissive/82757492/AI/Lookup.v | 82,757,492 | Lookup.v | v | 193 | 151 | [] | [] | [] | [(2, 23), (26, 177), (179, 193)] | null | null | 1: b"%Error: data/full_repos/permissive/82757492/AI/Lookup.v:189: Cannot find file containing module: 'RARb'\n RARb #(45) ra({a, b, c, d, e}, x);\n ^~~~\n ... Looked in:\n data/full_repos/permissive/82757492/AI,data/full_repos/permissive/82757492/RARb\n data/full_repos/permissive/82757492/AI,data/full_repos/permissive/82757492/RARb.v\n data/full_repos/permissive/82757492/AI,data/full_repos/permissive/82757492/RARb.sv\n RARb\n RARb.v\n RARb.sv\n obj_dir/RARb\n obj_dir/RARb.v\n obj_dir/RARb.sv\n%Error: data/full_repos/permissive/82757492/AI/Lookup.v:20: Cannot find file containing module: 'Empty'\n Empty emptyx (~(X_state | O_state), empty); \n ^~~~~\n%Error: Exiting due to 2 error(s)\n" | 301,937 | module | module LookupTableAI (
input [8:0] X_state,
input [8:0] O_state,
output wire [8:0] AIMove
);
wire [8:0] rotation1, rotation2, rotation3, rotation4, empty;
LookupTable rot1 (X_state, O_state, rotation1);
LookupTable rot2 ({X_state[6], X_state[3], X_state[0], X_state[7], X_state[4], X_state[1], X_state[8], X_state[5], X_state[2]},
{O_state[6], O_state[3], O_state[0], O_state[7], O_state[4], O_state[1], O_state[8], O_state[5], O_state[2]},
{rotation2[6], rotation2[3], rotation2[0], rotation2[7], rotation2[4], rotation2[1], rotation2[8], rotation2[5], rotation2[2]});
LookupTable rot3 ({X_state[2], X_state[5], X_state[8], X_state[1], X_state[4], X_state[7], X_state[0], X_state[3], X_state[6]},
{O_state[2], O_state[5], O_state[8], O_state[1], O_state[4], O_state[7], O_state[0], O_state[3], O_state[6]},
{rotation3[2], rotation3[5], rotation3[8], rotation3[1], rotation3[4], rotation3[7], rotation3[0], rotation3[3], rotation3[6]});
LookupTable rot4 ({X_state[0], X_state[1], X_state[2], X_state[3], X_state[4], X_state[5], X_state[6], X_state[7], X_state[8]},
{O_state[0], O_state[1], O_state[2], O_state[3], O_state[4], O_state[5], O_state[6], O_state[7], O_state[8]},
{rotation4[0], rotation4[1], rotation4[2], rotation4[3], rotation4[4], rotation4[5], rotation4[6], rotation4[7], rotation4[8]});
Empty emptyx (~(X_state | O_state), empty);
Select5 pick(rotation1, rotation2, rotation3, rotation4, empty, AIMove);
endmodule | module LookupTableAI (
input [8:0] X_state,
input [8:0] O_state,
output wire [8:0] AIMove
); |
wire [8:0] rotation1, rotation2, rotation3, rotation4, empty;
LookupTable rot1 (X_state, O_state, rotation1);
LookupTable rot2 ({X_state[6], X_state[3], X_state[0], X_state[7], X_state[4], X_state[1], X_state[8], X_state[5], X_state[2]},
{O_state[6], O_state[3], O_state[0], O_state[7], O_state[4], O_state[1], O_state[8], O_state[5], O_state[2]},
{rotation2[6], rotation2[3], rotation2[0], rotation2[7], rotation2[4], rotation2[1], rotation2[8], rotation2[5], rotation2[2]});
LookupTable rot3 ({X_state[2], X_state[5], X_state[8], X_state[1], X_state[4], X_state[7], X_state[0], X_state[3], X_state[6]},
{O_state[2], O_state[5], O_state[8], O_state[1], O_state[4], O_state[7], O_state[0], O_state[3], O_state[6]},
{rotation3[2], rotation3[5], rotation3[8], rotation3[1], rotation3[4], rotation3[7], rotation3[0], rotation3[3], rotation3[6]});
LookupTable rot4 ({X_state[0], X_state[1], X_state[2], X_state[3], X_state[4], X_state[5], X_state[6], X_state[7], X_state[8]},
{O_state[0], O_state[1], O_state[2], O_state[3], O_state[4], O_state[5], O_state[6], O_state[7], O_state[8]},
{rotation4[0], rotation4[1], rotation4[2], rotation4[3], rotation4[4], rotation4[5], rotation4[6], rotation4[7], rotation4[8]});
Empty emptyx (~(X_state | O_state), empty);
Select5 pick(rotation1, rotation2, rotation3, rotation4, empty, AIMove);
endmodule | 0 |
138,223 | data/full_repos/permissive/82757492/AI/Lookup.v | 82,757,492 | Lookup.v | v | 193 | 151 | [] | [] | [] | [(2, 23), (26, 177), (179, 193)] | null | null | 1: b"%Error: data/full_repos/permissive/82757492/AI/Lookup.v:189: Cannot find file containing module: 'RARb'\n RARb #(45) ra({a, b, c, d, e}, x);\n ^~~~\n ... Looked in:\n data/full_repos/permissive/82757492/AI,data/full_repos/permissive/82757492/RARb\n data/full_repos/permissive/82757492/AI,data/full_repos/permissive/82757492/RARb.v\n data/full_repos/permissive/82757492/AI,data/full_repos/permissive/82757492/RARb.sv\n RARb\n RARb.v\n RARb.sv\n obj_dir/RARb\n obj_dir/RARb.v\n obj_dir/RARb.sv\n%Error: data/full_repos/permissive/82757492/AI/Lookup.v:20: Cannot find file containing module: 'Empty'\n Empty emptyx (~(X_state | O_state), empty); \n ^~~~~\n%Error: Exiting due to 2 error(s)\n" | 301,937 | module | module LookupTable (
input [8:0] X_state,
input [8:0] O_state,
output wire [8:0] AIMove
);
reg [8:0] move;
wire [8:0] empty;
always @(*)
begin
case(X_state)
9'b000000000: move = 9'b100000000;
9'b100000000:
case(O_state)
9'b000000001: move = 9'b001000000;
9'b000000010: move = 9'b001000000;
9'b000000100: move = 9'b010000000;
9'b000001000: move = 9'b000010000;
9'b000010000: move = 9'b010000000;
9'b000100000: move = 9'b010000000;
9'b001000000: move = 9'b000100000;
9'b010000000: move = 9'b000100000;
default:
move = 9'b000000000;
endcase
9'b101000000:
case (O_state)
9'b000000011: move = 9'b010000000;
9'b000000101: move = 9'b010000000;
9'b000001001: move = 9'b010000000;
9'b000010001: move = 9'b010000000;
9'b000100001: move = 9'b010000000;
9'b010000001: move = 9'b000000100;
9'b000000110: move = 9'b010000000;
9'b000001010: move = 9'b010000000;
9'b000010010: move = 9'b010000000;
9'b000100010: move = 9'b010000000;
9'b010000010: move = 9'b000010000;
default: move = 9'b000000000;
endcase
9'b110000000:
case (O_state)
9'b000000011: move = 9'b001000000;
9'b000000110: move = 9'b001000000;
9'b000001010: move = 9'b001000000;
9'b000010010: move = 9'b001000000;
9'b000100010: move = 9'b001000000;
9'b001000010: move = 9'b000010000;
9'b000010001: move = 9'b001000000;
9'b000010100: move = 9'b001000000;
9'b000011000: move = 9'b001000000;
9'b000110000: move = 9'b001000000;
9'b001010000: move = 9'b000000100;
9'b000100001: move = 9'b001000000;
9'b000100100: move = 9'b001000000;
9'b000101000: move = 9'b001000000;
9'b001100000: move = 9'b000010000;
default: move = 9'b000000000;
endcase
9'b100010000:
case (O_state)
9'b000001001: move = 9'b001000000;
9'b000001010: move = 9'b000000001;
9'b000001100: move = 9'b000000001;
9'b000101000: move = 9'b000000001;
9'b001001000: move = 9'b000000001;
9'b010001000: move = 9'b000000001;
default: move = 9'b000000000;
endcase
9'b100100000:
case (O_state)
9'b001000001: move = 9'b000000100;
9'b001000010: move = 9'b000000100;
9'b001000100: move = 9'b000010000;
9'b001001000: move = 9'b000000100;
9'b001010000: move = 9'b000000100;
9'b011000000: move = 9'b000000100;
9'b010000001: move = 9'b000000100;
9'b010000010: move = 9'b000000100;
9'b010000100: move = 9'b000010000;
9'b010001000: move = 9'b000000100;
9'b010010000: move = 9'b000000100;
default: move = 9'b000000000;
endcase
9'b100110000:
case (O_state)
9'b011000100: move = 9'b000001000;
9'b010001100: move = 9'b000000001;
9'b010000110: move = 9'b000001000;
9'b010000101: move = 9'b000001000;
9'b001001100: move = 9'b000000001;
9'b001000110: move = 9'b000001000;
9'b001000101: move = 9'b000001000;
default: move = 9'b000000000;
endcase
9'b110010000:
case (O_state)
9'b001101000: move = 9'b000000010;
9'b001100100: move = 9'b000000010;
9'b001100010: move = 9'b000000001;
9'b001100001: move = 9'b000000010;
9'b001001100: move = 9'b000000010;
9'b001000110: move = 9'b000000001;
9'b001000101: move = 9'b000000010;
default: move = 9'b000000000;
endcase
9'b110000100:
case (O_state)
9'b001110000: move = 9'b000001000;
9'b001011000: move = 9'b000100000;
9'b001010010: move = 9'b000100000;
9'b001010001: move = 9'b000100000;
default: move = 9'b000000000;
endcase
9'b101010000:
case (O_state)
9'b010001001: move = 9'b000000100;
9'b000101001: move = 9'b010000000;
9'b000001101: move = 9'b010000000;
9'b000001011: move = 9'b010000000;
9'b010100010: move = 9'b000000100;
9'b010001010: move = 9'b000000100;
9'b010000110: move = 9'b000000001;
9'b010000011: move = 9'b000000100;
default: move = 9'b000000000;
endcase
9'b101000100:
case (O_state)
9'b010100001: move = 9'b000010000;
9'b010010001: move = 9'b000100000;
9'b010001001: move = 9'b000100000;
9'b010000011: move = 9'b000100000;
default: move = 9'b000000000;
endcase
9'b110001100:
case (O_state)
9'b001110010: move = 9'b000000001;
9'b001110001: move = 9'b000000010;
endcase
default: move = 9'b000000000;
endcase
end
assign AIMove = move;
endmodule | module LookupTable (
input [8:0] X_state,
input [8:0] O_state,
output wire [8:0] AIMove
); |
reg [8:0] move;
wire [8:0] empty;
always @(*)
begin
case(X_state)
9'b000000000: move = 9'b100000000;
9'b100000000:
case(O_state)
9'b000000001: move = 9'b001000000;
9'b000000010: move = 9'b001000000;
9'b000000100: move = 9'b010000000;
9'b000001000: move = 9'b000010000;
9'b000010000: move = 9'b010000000;
9'b000100000: move = 9'b010000000;
9'b001000000: move = 9'b000100000;
9'b010000000: move = 9'b000100000;
default:
move = 9'b000000000;
endcase
9'b101000000:
case (O_state)
9'b000000011: move = 9'b010000000;
9'b000000101: move = 9'b010000000;
9'b000001001: move = 9'b010000000;
9'b000010001: move = 9'b010000000;
9'b000100001: move = 9'b010000000;
9'b010000001: move = 9'b000000100;
9'b000000110: move = 9'b010000000;
9'b000001010: move = 9'b010000000;
9'b000010010: move = 9'b010000000;
9'b000100010: move = 9'b010000000;
9'b010000010: move = 9'b000010000;
default: move = 9'b000000000;
endcase
9'b110000000:
case (O_state)
9'b000000011: move = 9'b001000000;
9'b000000110: move = 9'b001000000;
9'b000001010: move = 9'b001000000;
9'b000010010: move = 9'b001000000;
9'b000100010: move = 9'b001000000;
9'b001000010: move = 9'b000010000;
9'b000010001: move = 9'b001000000;
9'b000010100: move = 9'b001000000;
9'b000011000: move = 9'b001000000;
9'b000110000: move = 9'b001000000;
9'b001010000: move = 9'b000000100;
9'b000100001: move = 9'b001000000;
9'b000100100: move = 9'b001000000;
9'b000101000: move = 9'b001000000;
9'b001100000: move = 9'b000010000;
default: move = 9'b000000000;
endcase
9'b100010000:
case (O_state)
9'b000001001: move = 9'b001000000;
9'b000001010: move = 9'b000000001;
9'b000001100: move = 9'b000000001;
9'b000101000: move = 9'b000000001;
9'b001001000: move = 9'b000000001;
9'b010001000: move = 9'b000000001;
default: move = 9'b000000000;
endcase
9'b100100000:
case (O_state)
9'b001000001: move = 9'b000000100;
9'b001000010: move = 9'b000000100;
9'b001000100: move = 9'b000010000;
9'b001001000: move = 9'b000000100;
9'b001010000: move = 9'b000000100;
9'b011000000: move = 9'b000000100;
9'b010000001: move = 9'b000000100;
9'b010000010: move = 9'b000000100;
9'b010000100: move = 9'b000010000;
9'b010001000: move = 9'b000000100;
9'b010010000: move = 9'b000000100;
default: move = 9'b000000000;
endcase
9'b100110000:
case (O_state)
9'b011000100: move = 9'b000001000;
9'b010001100: move = 9'b000000001;
9'b010000110: move = 9'b000001000;
9'b010000101: move = 9'b000001000;
9'b001001100: move = 9'b000000001;
9'b001000110: move = 9'b000001000;
9'b001000101: move = 9'b000001000;
default: move = 9'b000000000;
endcase
9'b110010000:
case (O_state)
9'b001101000: move = 9'b000000010;
9'b001100100: move = 9'b000000010;
9'b001100010: move = 9'b000000001;
9'b001100001: move = 9'b000000010;
9'b001001100: move = 9'b000000010;
9'b001000110: move = 9'b000000001;
9'b001000101: move = 9'b000000010;
default: move = 9'b000000000;
endcase
9'b110000100:
case (O_state)
9'b001110000: move = 9'b000001000;
9'b001011000: move = 9'b000100000;
9'b001010010: move = 9'b000100000;
9'b001010001: move = 9'b000100000;
default: move = 9'b000000000;
endcase
9'b101010000:
case (O_state)
9'b010001001: move = 9'b000000100;
9'b000101001: move = 9'b010000000;
9'b000001101: move = 9'b010000000;
9'b000001011: move = 9'b010000000;
9'b010100010: move = 9'b000000100;
9'b010001010: move = 9'b000000100;
9'b010000110: move = 9'b000000001;
9'b010000011: move = 9'b000000100;
default: move = 9'b000000000;
endcase
9'b101000100:
case (O_state)
9'b010100001: move = 9'b000010000;
9'b010010001: move = 9'b000100000;
9'b010001001: move = 9'b000100000;
9'b010000011: move = 9'b000100000;
default: move = 9'b000000000;
endcase
9'b110001100:
case (O_state)
9'b001110010: move = 9'b000000001;
9'b001110001: move = 9'b000000010;
endcase
default: move = 9'b000000000;
endcase
end
assign AIMove = move;
endmodule | 0 |
138,224 | data/full_repos/permissive/82757492/AI/Lookup.v | 82,757,492 | Lookup.v | v | 193 | 151 | [] | [] | [] | [(2, 23), (26, 177), (179, 193)] | null | null | 1: b"%Error: data/full_repos/permissive/82757492/AI/Lookup.v:189: Cannot find file containing module: 'RARb'\n RARb #(45) ra({a, b, c, d, e}, x);\n ^~~~\n ... Looked in:\n data/full_repos/permissive/82757492/AI,data/full_repos/permissive/82757492/RARb\n data/full_repos/permissive/82757492/AI,data/full_repos/permissive/82757492/RARb.v\n data/full_repos/permissive/82757492/AI,data/full_repos/permissive/82757492/RARb.sv\n RARb\n RARb.v\n RARb.sv\n obj_dir/RARb\n obj_dir/RARb.v\n obj_dir/RARb.sv\n%Error: data/full_repos/permissive/82757492/AI/Lookup.v:20: Cannot find file containing module: 'Empty'\n Empty emptyx (~(X_state | O_state), empty); \n ^~~~~\n%Error: Exiting due to 2 error(s)\n" | 301,937 | module | module Select5(
input [8:0] a,
input [8:0] b,
input [8:0] c,
input [8:0] d,
input [8:0] e,
output wire [8:0] out);
wire [44:0] x;
RARb #(45) ra({a, b, c, d, e}, x);
assign out = x[44:36] | x[35:27] | x[26:18] | x[17:9] | x[8:0];
endmodule | module Select5(
input [8:0] a,
input [8:0] b,
input [8:0] c,
input [8:0] d,
input [8:0] e,
output wire [8:0] out); |
wire [44:0] x;
RARb #(45) ra({a, b, c, d, e}, x);
assign out = x[44:36] | x[35:27] | x[26:18] | x[17:9] | x[8:0];
endmodule | 0 |
138,225 | data/full_repos/permissive/82757492/AI/Lookup_TB.v | 82,757,492 | Lookup_TB.v | v | 70 | 85 | [] | [] | [] | null | line:47 column:15: Illegal character "'" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82757492/AI/Lookup_TB.v:29: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/82757492/AI/Lookup_TB.v:33: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82757492/AI/Lookup_TB.v:36: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82757492/AI/Lookup_TB.v:40: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82757492/AI/Lookup_TB.v:44: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/82757492/AI/Lookup_TB.v:47: Illegal base character: 0\n O_state = 9\'0001000001;\n ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82757492/AI/Lookup_TB.v:48: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82757492/AI/Lookup_TB.v:51: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/82757492/AI/Lookup_TB.v:54: Illegal base character: 0\n O_state = 9\'0000000000;\n ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82757492/AI/Lookup_TB.v:55: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82757492/AI/Lookup_TB.v:59: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,938 | module | module LookupAI_TB;
reg [8:0] X_state;
reg [8:0] O_state;
wire [8:0] AI_move;
integer i, j;
initial begin
#10;
X_state = 9'b000000000;
O_state = 9'b000000000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
X_state = 9'b100000000;
O_state = 9'b000100000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
X_state = 9'b101000000;
O_state = 9'0001000001;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
X_state = 9'b111000000;
O_state = 9'0000000000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#200;
$finish;
end
LookupTableAI lai (
X_state,
O_state,
AI_move
);
endmodule | module LookupAI_TB; |
reg [8:0] X_state;
reg [8:0] O_state;
wire [8:0] AI_move;
integer i, j;
initial begin
#10;
X_state = 9'b000000000;
O_state = 9'b000000000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
X_state = 9'b100000000;
O_state = 9'b000100000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
X_state = 9'b101000000;
O_state = 9'0001000001;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
X_state = 9'b111000000;
O_state = 9'0000000000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#200;
$finish;
end
LookupTableAI lai (
X_state,
O_state,
AI_move
);
endmodule | 0 |
138,226 | data/full_repos/permissive/82757492/AI/SimpleAI_TB.v | 82,757,492 | SimpleAI_TB.v | v | 96 | 85 | [] | [] | [] | [(21, 95)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82757492/AI/SimpleAI_TB.v:29: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/82757492/AI/SimpleAI_TB.v:60: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82757492/AI/SimpleAI_TB.v:63: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82757492/AI/SimpleAI_TB.v:66: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82757492/AI/SimpleAI_TB.v:69: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82757492/AI/SimpleAI_TB.v:72: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82757492/AI/SimpleAI_TB.v:75: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82757492/AI/SimpleAI_TB.v:78: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82757492/AI/SimpleAI_TB.v:83: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Error: data/full_repos/permissive/82757492/AI/SimpleAI_TB.v:89: Cannot find file containing module: \'SimpleAI\'\n SimpleAI sa (\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82757492/AI,data/full_repos/permissive/82757492/SimpleAI\n data/full_repos/permissive/82757492/AI,data/full_repos/permissive/82757492/SimpleAI.v\n data/full_repos/permissive/82757492/AI,data/full_repos/permissive/82757492/SimpleAI.sv\n SimpleAI\n SimpleAI.v\n SimpleAI.sv\n obj_dir/SimpleAI\n obj_dir/SimpleAI.v\n obj_dir/SimpleAI.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,939 | module | module SimpleAI_TB;
reg [8:0] X_state;
reg [8:0] O_state;
wire [8:0] AI_move;
integer i, j;
initial begin
#10;
X_state = 9'b00010000;
O_state = 9'b01000000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
X_state = 9'b100000000;
O_state = 9'b000010000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
X_state = 9'b110000000;
O_state = 9'b000110000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
X_state = 9'b10001001;
O_state = 9'b001101000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#200;
$finish;
end
SimpleAI sa (
X_state,
O_state,
AI_move
);
endmodule | module SimpleAI_TB; |
reg [8:0] X_state;
reg [8:0] O_state;
wire [8:0] AI_move;
integer i, j;
initial begin
#10;
X_state = 9'b00010000;
O_state = 9'b01000000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
X_state = 9'b100000000;
O_state = 9'b000010000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
X_state = 9'b110000000;
O_state = 9'b000110000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
X_state = 9'b10001001;
O_state = 9'b001101000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#200;
$finish;
end
SimpleAI sa (
X_state,
O_state,
AI_move
);
endmodule | 0 |
138,227 | data/full_repos/permissive/82757492/Game/Game.v | 82,757,492 | Game.v | v | 213 | 90 | [] | [] | [] | [(21, 212)] | null | null | 1: b"%Error: data/full_repos/permissive/82757492/Game/Game.v:58: Cannot find file containing module: 'clockdiv'\nclockdiv U1(\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82757492/Game,data/full_repos/permissive/82757492/clockdiv\n data/full_repos/permissive/82757492/Game,data/full_repos/permissive/82757492/clockdiv.v\n data/full_repos/permissive/82757492/Game,data/full_repos/permissive/82757492/clockdiv.sv\n clockdiv\n clockdiv.v\n clockdiv.sv\n obj_dir/clockdiv\n obj_dir/clockdiv.v\n obj_dir/clockdiv.sv\n%Error: data/full_repos/permissive/82757492/Game/Game.v:76: Cannot find file containing module: 'Synchronizer'\n Synchronizer rst_sync(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82757492/Game/Game.v:83: Cannot find file containing module: 'Synchronizer'\n Synchronizer input_move_sync(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82757492/Game/Game.v:90: Cannot find file containing module: 'Synchronizer'\n Synchronizer AI_sw_sync(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82757492/Game/Game.v:97: Cannot find file containing module: 'Synchronizer'\n Synchronizer input1_sw_sync(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82757492/Game/Game.v:104: Cannot find file containing module: 'Synchronizer'\n Synchronizer input2_sw_sync(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82757492/Game/Game.v:111: Cannot find file containing module: 'Synchronizer'\n Synchronizer input3_sw_sync(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82757492/Game/Game.v:118: Cannot find file containing module: 'Synchronizer'\n Synchronizer input4_sw_sync(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82757492/Game/Game.v:129: Cannot find file containing module: 'Debouncer'\n Debouncer deb_S(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82757492/Game/Game.v:155: Cannot find file containing module: 'SimpleAI'\nSimpleAI sa(\n^~~~~~~~\n%Error: data/full_repos/permissive/82757492/Game/Game.v:161: Cannot find file containing module: 'LookupTableAI'\nLookupTableAI hard_ai(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82757492/Game/Game.v:169: Cannot find file containing module: 'GameState'\nGameState state(\n^~~~~~~~~\n%Error: data/full_repos/permissive/82757492/Game/Game.v:189: Cannot find file containing module: 'vga640x480'\nvga640x480 U3(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/82757492/Game/Game.v:203: Cannot find file containing module: 'Display'\n Display d(\n ^~~~~~~\n%Error: Exiting due to 14 error(s)\n" | 301,940 | module | module Game(
input wire clk,
input wire clr,
input wire [4:0] sw,
input wire btnInput,
input wire btnReset,
output wire [2:0] red,
output wire [2:0] green,
output wire [1:0] blue,
output wire hsync,
output wire vsync,
output wire [7:0] seg,
output wire [3:0] an
);
wire pix_en;
wire logic_en;
wire logic_en_delay;
wire display_en;
reg rst_vga;
reg rst_ff;
always @(posedge clk or posedge clr) begin
if (clr) begin
{rst_vga,rst_ff} <= 2'b11;
end
else begin
{rst_vga,rst_ff} <= {rst_ff,1'b0};
end
end
clockdiv U1(
.clk(clk),
.rst(rst_vga),
.logic_en(logic_en),
.logic_en_1(logic_en_delay),
.pix_en(pix_en),
.display_en(display_en)
);
wire btnMove_sync;
wire rst;
wire AI_switch;
wire switch1, switch2, switch3, switch4;
Synchronizer rst_sync(
.clk(clk),
.async_in(btnReset),
.reset(1'b0),
.synch_out(rst)
);
Synchronizer input_move_sync(
.clk(clk),
.async_in(btnInput),
.reset(rst),
.synch_out(btnMove_sync)
);
Synchronizer AI_sw_sync(
.clk(clk),
.async_in(sw[0]),
.reset(rst),
.synch_out(AI_switch)
);
Synchronizer input1_sw_sync(
.clk(clk),
.async_in(sw[1]),
.reset(rst),
.synch_out(switch1)
);
Synchronizer input2_sw_sync(
.clk(clk),
.async_in(sw[2]),
.reset(rst),
.synch_out(switch2)
);
Synchronizer input3_sw_sync(
.clk(clk),
.async_in(sw[3]),
.reset(rst),
.synch_out(switch3)
);
Synchronizer input4_sw_sync(
.clk(clk),
.async_in(sw[4]),
.reset(rst),
.synch_out(switch4)
);
wire move;
Debouncer deb_S(
.clk(clk),
.clk2(logic_en),
.real_btn_input(btnMove_sync),
.debounced_btn_input(move)
);
reg [3:0] nextMove;
always @(*)
begin nextMove = {switch4, switch3, switch2, switch1};
end
wire [8:0] X_state;
wire [8:0] O_state;
wire [2:0] GameStatus;
wire [8:0] AIMove;
wire [8:0] AIMove_hard;
SimpleAI sa(
.X_state(X_state),
.O_state(O_state),
.AIMove(AIMove)
);
LookupTableAI hard_ai(
.X_state(X_state),
.O_state(O_state),
.AIMove(AIMove_hard)
);
wire [7:0] numWins;
GameState state(
.rst(rst),
.move(move),
.clk(logic_en_delay),
.nextMove(nextMove),
.AISwitch(AI_switch),
.AIMove(AIMove),
.AIMove_Hard(AIMove_hard),
.X_state(X_state),
.O_state(O_state),
.GameStatus(GameStatus),
.numWins(numWins)
);
vga640x480 U3(
.pix_en(pix_en),
.clk(clk),
.rst(rst_vga),
.o_vec(O_state),
.x_vec(X_state),
.game_status(GameStatus),
.hsync(hsync),
.vsync(vsync),
.red(red),
.green(green),
.blue(blue)
);
Display d(
.Value(numWins),
.clk(display_en),
.seg(seg),
.an(an)
);
endmodule | module Game(
input wire clk,
input wire clr,
input wire [4:0] sw,
input wire btnInput,
input wire btnReset,
output wire [2:0] red,
output wire [2:0] green,
output wire [1:0] blue,
output wire hsync,
output wire vsync,
output wire [7:0] seg,
output wire [3:0] an
); |
wire pix_en;
wire logic_en;
wire logic_en_delay;
wire display_en;
reg rst_vga;
reg rst_ff;
always @(posedge clk or posedge clr) begin
if (clr) begin
{rst_vga,rst_ff} <= 2'b11;
end
else begin
{rst_vga,rst_ff} <= {rst_ff,1'b0};
end
end
clockdiv U1(
.clk(clk),
.rst(rst_vga),
.logic_en(logic_en),
.logic_en_1(logic_en_delay),
.pix_en(pix_en),
.display_en(display_en)
);
wire btnMove_sync;
wire rst;
wire AI_switch;
wire switch1, switch2, switch3, switch4;
Synchronizer rst_sync(
.clk(clk),
.async_in(btnReset),
.reset(1'b0),
.synch_out(rst)
);
Synchronizer input_move_sync(
.clk(clk),
.async_in(btnInput),
.reset(rst),
.synch_out(btnMove_sync)
);
Synchronizer AI_sw_sync(
.clk(clk),
.async_in(sw[0]),
.reset(rst),
.synch_out(AI_switch)
);
Synchronizer input1_sw_sync(
.clk(clk),
.async_in(sw[1]),
.reset(rst),
.synch_out(switch1)
);
Synchronizer input2_sw_sync(
.clk(clk),
.async_in(sw[2]),
.reset(rst),
.synch_out(switch2)
);
Synchronizer input3_sw_sync(
.clk(clk),
.async_in(sw[3]),
.reset(rst),
.synch_out(switch3)
);
Synchronizer input4_sw_sync(
.clk(clk),
.async_in(sw[4]),
.reset(rst),
.synch_out(switch4)
);
wire move;
Debouncer deb_S(
.clk(clk),
.clk2(logic_en),
.real_btn_input(btnMove_sync),
.debounced_btn_input(move)
);
reg [3:0] nextMove;
always @(*)
begin nextMove = {switch4, switch3, switch2, switch1};
end
wire [8:0] X_state;
wire [8:0] O_state;
wire [2:0] GameStatus;
wire [8:0] AIMove;
wire [8:0] AIMove_hard;
SimpleAI sa(
.X_state(X_state),
.O_state(O_state),
.AIMove(AIMove)
);
LookupTableAI hard_ai(
.X_state(X_state),
.O_state(O_state),
.AIMove(AIMove_hard)
);
wire [7:0] numWins;
GameState state(
.rst(rst),
.move(move),
.clk(logic_en_delay),
.nextMove(nextMove),
.AISwitch(AI_switch),
.AIMove(AIMove),
.AIMove_Hard(AIMove_hard),
.X_state(X_state),
.O_state(O_state),
.GameStatus(GameStatus),
.numWins(numWins)
);
vga640x480 U3(
.pix_en(pix_en),
.clk(clk),
.rst(rst_vga),
.o_vec(O_state),
.x_vec(X_state),
.game_status(GameStatus),
.hsync(hsync),
.vsync(vsync),
.red(red),
.green(green),
.blue(blue)
);
Display d(
.Value(numWins),
.clk(display_en),
.seg(seg),
.an(an)
);
endmodule | 0 |
138,228 | data/full_repos/permissive/82757492/Game/GameState.v | 82,757,492 | GameState.v | v | 195 | 121 | [] | [] | [] | [(2, 194)] | null | data/verilator_xmls/ab0782c6-fabf-4616-8df5-d119e56dfd98.xml | null | 301,941 | module | module GameState (
input rst,
input move ,
input clk,
input [3:0] nextMove,
input AISwitch,
input [8:0] AIMove,
input [8:0] AIMove_Hard,
output wire [8:0] X_state,
output wire [8:0] O_state,
output wire [2:0] GameStatus,
output wire [7:0] numWins
);
reg [8:0] X_pos;
reg [8:0] tmp_X_pos;
reg [8:0] O_pos;
reg [8:0] tmp_O_pos = 9'b000000000;
reg [2:0] game_stats = 0;
reg [7:0] tmp_Score = 0;
reg player;
reg tmp_player;
always @(*)
begin
if(move)
begin
if(player == 0)
begin
case(nextMove)
0:
if(((X_pos[8] | O_pos[8]) != 1) && tmp_X_pos[8] != 1)
begin
tmp_O_pos = O_pos | 9'b100000000;
tmp_player = ~player;
end
1:
if(((X_pos[7] | O_pos[7]) != 1) && (tmp_X_pos[7] != 1))
begin
tmp_O_pos = O_pos | 9'b010000000;
tmp_player = ~player;
end
2:
if(((X_pos[6] | O_pos[6]) != 1) && (tmp_X_pos[6] != 1))
begin
tmp_O_pos = O_pos | 9'b001000000;
tmp_player = ~player;
end
3:
if(((X_pos[5] | O_pos[5]) != 1) && (tmp_X_pos[5] != 1))
begin
tmp_O_pos = O_pos | 9'b000100000;
tmp_player = ~player;
end
4:
if(((X_pos[4] | O_pos[4]) != 1) && (tmp_X_pos[4] != 1))
begin
tmp_O_pos = O_pos | 9'b000010000;
tmp_player = ~player;
end
5:
if(((X_pos[3] | O_pos[3]) != 1) && (tmp_X_pos[3] != 1))
begin
tmp_O_pos = O_pos | 9'b000001000;
tmp_player = ~player;
end
6:
if(((X_pos[2] | O_pos[2]) != 1) && (tmp_X_pos[2] != 1))
begin
tmp_O_pos = O_pos | 9'b000000100;
tmp_player = ~player;
end
7:
if(((X_pos[1] | O_pos[1]) != 1) && (tmp_X_pos[1] != 1))
begin
tmp_O_pos = O_pos | 9'b000000010;
tmp_player = ~player;
end
8:
if(((X_pos[0] | O_pos[0]) != 1) && (tmp_X_pos[0] != 1))
begin
tmp_O_pos = O_pos | 9'b000000001;
tmp_player = ~player;
end
default:
;
endcase
end
end
else if(player == 1 && move == 0 && tmp_player == 1)
begin
if(AISwitch == 1'b0) begin
tmp_X_pos = X_pos | AIMove;
tmp_player = ~player;
end
else begin
tmp_X_pos = X_pos | AIMove_Hard;
tmp_player = ~player;
end
end
end
always @ (posedge clk or posedge rst)
begin
if (rst) begin
game_stats <= 0;
player <= 1;
X_pos <= 9'b000000000;
O_pos <= 9'b000000000;
end
else begin
player <= tmp_player;
X_pos <= tmp_X_pos;
O_pos <= tmp_O_pos;
if (move) begin
case(nextMove)
0,1,2,3,4,5,6,7,8:
begin
game_stats <= 0;
end
default:
game_stats <= 4;
endcase
if(game_stats == 0 && (O_pos == 9'b000_000_111 || O_pos == 9'b000_111_000 || O_pos == 9'b111_000_000 ||
O_pos == 9'b100_100_100 || O_pos == 9'b010_010_010 || O_pos == 9'b001_001_001 ||
O_pos == 9'b100_010_001 || O_pos == 9'b001_010_100))
begin
tmp_Score <= tmp_Score + 1;
game_stats <= 2;
end
else if((O_pos | X_pos) == 9'b111_111_111)
game_stats <= 3;
end
else begin
if(game_stats == 0 && (X_pos == 9'b000_000_111 || X_pos == 9'b000_111_000 || X_pos == 9'b111_000_000 ||
X_pos == 9'b100_100_100 || X_pos == 9'b010_010_010 || X_pos == 9'b001_001_001 ||
X_pos == 9'b100_010_001 || X_pos == 9'b001_010_100))
begin
tmp_Score <= tmp_Score + 1;
game_stats <= 1;
end
else if((O_pos | X_pos) == 9'b111_111_111)
game_stats <= 3;
end
end
end
assign GameStatus = game_stats;
assign X_state = X_pos;
assign O_state = O_pos;
assign numWins = tmp_Score;
endmodule | module GameState (
input rst,
input move ,
input clk,
input [3:0] nextMove,
input AISwitch,
input [8:0] AIMove,
input [8:0] AIMove_Hard,
output wire [8:0] X_state,
output wire [8:0] O_state,
output wire [2:0] GameStatus,
output wire [7:0] numWins
); |
reg [8:0] X_pos;
reg [8:0] tmp_X_pos;
reg [8:0] O_pos;
reg [8:0] tmp_O_pos = 9'b000000000;
reg [2:0] game_stats = 0;
reg [7:0] tmp_Score = 0;
reg player;
reg tmp_player;
always @(*)
begin
if(move)
begin
if(player == 0)
begin
case(nextMove)
0:
if(((X_pos[8] | O_pos[8]) != 1) && tmp_X_pos[8] != 1)
begin
tmp_O_pos = O_pos | 9'b100000000;
tmp_player = ~player;
end
1:
if(((X_pos[7] | O_pos[7]) != 1) && (tmp_X_pos[7] != 1))
begin
tmp_O_pos = O_pos | 9'b010000000;
tmp_player = ~player;
end
2:
if(((X_pos[6] | O_pos[6]) != 1) && (tmp_X_pos[6] != 1))
begin
tmp_O_pos = O_pos | 9'b001000000;
tmp_player = ~player;
end
3:
if(((X_pos[5] | O_pos[5]) != 1) && (tmp_X_pos[5] != 1))
begin
tmp_O_pos = O_pos | 9'b000100000;
tmp_player = ~player;
end
4:
if(((X_pos[4] | O_pos[4]) != 1) && (tmp_X_pos[4] != 1))
begin
tmp_O_pos = O_pos | 9'b000010000;
tmp_player = ~player;
end
5:
if(((X_pos[3] | O_pos[3]) != 1) && (tmp_X_pos[3] != 1))
begin
tmp_O_pos = O_pos | 9'b000001000;
tmp_player = ~player;
end
6:
if(((X_pos[2] | O_pos[2]) != 1) && (tmp_X_pos[2] != 1))
begin
tmp_O_pos = O_pos | 9'b000000100;
tmp_player = ~player;
end
7:
if(((X_pos[1] | O_pos[1]) != 1) && (tmp_X_pos[1] != 1))
begin
tmp_O_pos = O_pos | 9'b000000010;
tmp_player = ~player;
end
8:
if(((X_pos[0] | O_pos[0]) != 1) && (tmp_X_pos[0] != 1))
begin
tmp_O_pos = O_pos | 9'b000000001;
tmp_player = ~player;
end
default:
;
endcase
end
end
else if(player == 1 && move == 0 && tmp_player == 1)
begin
if(AISwitch == 1'b0) begin
tmp_X_pos = X_pos | AIMove;
tmp_player = ~player;
end
else begin
tmp_X_pos = X_pos | AIMove_Hard;
tmp_player = ~player;
end
end
end
always @ (posedge clk or posedge rst)
begin
if (rst) begin
game_stats <= 0;
player <= 1;
X_pos <= 9'b000000000;
O_pos <= 9'b000000000;
end
else begin
player <= tmp_player;
X_pos <= tmp_X_pos;
O_pos <= tmp_O_pos;
if (move) begin
case(nextMove)
0,1,2,3,4,5,6,7,8:
begin
game_stats <= 0;
end
default:
game_stats <= 4;
endcase
if(game_stats == 0 && (O_pos == 9'b000_000_111 || O_pos == 9'b000_111_000 || O_pos == 9'b111_000_000 ||
O_pos == 9'b100_100_100 || O_pos == 9'b010_010_010 || O_pos == 9'b001_001_001 ||
O_pos == 9'b100_010_001 || O_pos == 9'b001_010_100))
begin
tmp_Score <= tmp_Score + 1;
game_stats <= 2;
end
else if((O_pos | X_pos) == 9'b111_111_111)
game_stats <= 3;
end
else begin
if(game_stats == 0 && (X_pos == 9'b000_000_111 || X_pos == 9'b000_111_000 || X_pos == 9'b111_000_000 ||
X_pos == 9'b100_100_100 || X_pos == 9'b010_010_010 || X_pos == 9'b001_001_001 ||
X_pos == 9'b100_010_001 || X_pos == 9'b001_010_100))
begin
tmp_Score <= tmp_Score + 1;
game_stats <= 1;
end
else if((O_pos | X_pos) == 9'b111_111_111)
game_stats <= 3;
end
end
end
assign GameStatus = game_stats;
assign X_state = X_pos;
assign O_state = O_pos;
assign numWins = tmp_Score;
endmodule | 0 |
138,229 | data/full_repos/permissive/82757492/Game/GameState_tb.v | 82,757,492 | GameState_tb.v | v | 182 | 99 | [] | [] | [] | [(4, 182)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82757492/Game/GameState_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #1 rst = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/82757492/Game/GameState_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82757492/Game/GameState_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82757492/Game/GameState_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82757492/Game/GameState_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82757492/Game/GameState_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82757492/Game/GameState_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82757492/Game/GameState_tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/82757492/Game/GameState_tb.v:148: Cannot find file containing module: \'SimpleAI\'\nSimpleAI sa(\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82757492/Game,data/full_repos/permissive/82757492/SimpleAI\n data/full_repos/permissive/82757492/Game,data/full_repos/permissive/82757492/SimpleAI.v\n data/full_repos/permissive/82757492/Game,data/full_repos/permissive/82757492/SimpleAI.sv\n SimpleAI\n SimpleAI.v\n SimpleAI.sv\n obj_dir/SimpleAI\n obj_dir/SimpleAI.v\n obj_dir/SimpleAI.sv\n%Error: data/full_repos/permissive/82757492/Game/GameState_tb.v:154: Cannot find file containing module: \'LookupTableAI\'\nLookupTableAI hard_ai(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82757492/Game/GameState_tb.v:159: Cannot find file containing module: \'GameState\'\nGameState state(\n^~~~~~~~~\n%Error: Exiting due to 3 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 301,942 | module | module GameState_TB;
reg rst;
reg move;
reg clk;
reg [3:0] nextMove;
wire [8:0] X_state;
wire [8:0] O_state;
wire [8:0] AIMove;
wire [8:0] AIMove_hard;
wire [7:0] numWins;
wire [2:0] status;
reg AISwitch;
integer i, j;
initial begin
clk = 0;
rst = 1;
AISwitch =0 ;
move = 0;
#1 rst = 0;
i = 0; j = 0;
while(i < 9 && j < 9)
begin
if(X_state[i] == 1)
$write("X");
else if(O_state[i] == 1)
$write("O");
else
$write("B");
if((i +1) %3 == 0 && i != 0) $write("\n");
i = i+1; j=j+1;
end
$write("\n\n\n");
move =1;
nextMove = 1;
#20
i = 0; j = 0; while(i < 9 && j < 9)
begin
if(X_state[i] == 1)
$write("X");
else if(O_state[i] == 1)
$write("O");
else
$write("B");
if((i +1) %3 == 0 && i != 0) $write("\n");
i = i+1; j=j+1;
end
$write("\n\n\n");
move = 0;
#20
move = 1;
nextMove = 2;
#5
i = 0; j = 0;
while(i < 9 && j < 9)
begin
if(X_state[i] == 1)
$write("X");
else if(O_state[i] == 1)
$write("O");
else
$write("B");
if((i +1) %3 == 0 && i != 0) $write("\n");
i = i+1; j=j+1;
end
$write("\n\n\n");
move = 0;
#20
move = 1;
nextMove = 3;
i = 0; j = 0;
while(i < 9 && j < 9)
begin
if(X_state[i] == 1)
$write("X");
else if(O_state[i] == 1)
$write("O");
else
$write("B");
if((i +1) %3 == 0 && i != 0) $write("\n");
i = i+1; j=j+1;
end
$write("\n\n\n");
#5
i = 0; j = 0;
while(i < 9 && j < 9)
begin
if(X_state[i] == 1)
$write("X");
else if(O_state[i] == 1)
$write("O");
else
$write("B");
if((i +1) %3 == 0 && i != 0) $write("\n");
i = i+1; j=j+1;
end
$write("\n\n\n");
move = 0;
#20
i = 0; j = 0;
while(i < 9 && j < 9)
begin
if(X_state[i] == 1)
$write("X");
else if(O_state[i] == 1)
$write("O");
else
$write("B");
if((i +1) %3 == 0 && i != 0) $write("\n");
i = i+1; j=j+1;
end
$write("\n");
$display("X_pos | AIMove %b", AIMove);
$display("X: %b", X_state);
$display("O: %b", O_state);
$display("Game Status: %b", status);
$display(O_state == 9'b000_000_111 || O_state == 9'b000_111_000 || O_state == 9'b111_000_000 ||
O_state == 9'b100_100_100 || O_state == 9'b010_010_010 || O_state == 9'b001_001_001 ||
O_state == 9'b100_010_001 || O_state == 9'b001_010_100);
$finish;
end
always #5 clk = ~clk;
SimpleAI sa(
.X_state(X_state),
.O_state(O_state),
.AIMove(AIMove)
);
LookupTableAI hard_ai(
.X_state(X_state),
.O_state(O_state),
.AIMove(AIMove_hard)
);
GameState state(
.rst(rst),
.move(move),
.clk(clk),
.nextMove(nextMove),
.AISwitch(AISwitch),
.AIMove(AIMove),
.AIMove_Hard(AIMove_hard),
.numWins(numWins),
.X_state(X_state),
.O_state(O_state),
.GameStatus(status)
);
endmodule | module GameState_TB; |
reg rst;
reg move;
reg clk;
reg [3:0] nextMove;
wire [8:0] X_state;
wire [8:0] O_state;
wire [8:0] AIMove;
wire [8:0] AIMove_hard;
wire [7:0] numWins;
wire [2:0] status;
reg AISwitch;
integer i, j;
initial begin
clk = 0;
rst = 1;
AISwitch =0 ;
move = 0;
#1 rst = 0;
i = 0; j = 0;
while(i < 9 && j < 9)
begin
if(X_state[i] == 1)
$write("X");
else if(O_state[i] == 1)
$write("O");
else
$write("B");
if((i +1) %3 == 0 && i != 0) $write("\n");
i = i+1; j=j+1;
end
$write("\n\n\n");
move =1;
nextMove = 1;
#20
i = 0; j = 0; while(i < 9 && j < 9)
begin
if(X_state[i] == 1)
$write("X");
else if(O_state[i] == 1)
$write("O");
else
$write("B");
if((i +1) %3 == 0 && i != 0) $write("\n");
i = i+1; j=j+1;
end
$write("\n\n\n");
move = 0;
#20
move = 1;
nextMove = 2;
#5
i = 0; j = 0;
while(i < 9 && j < 9)
begin
if(X_state[i] == 1)
$write("X");
else if(O_state[i] == 1)
$write("O");
else
$write("B");
if((i +1) %3 == 0 && i != 0) $write("\n");
i = i+1; j=j+1;
end
$write("\n\n\n");
move = 0;
#20
move = 1;
nextMove = 3;
i = 0; j = 0;
while(i < 9 && j < 9)
begin
if(X_state[i] == 1)
$write("X");
else if(O_state[i] == 1)
$write("O");
else
$write("B");
if((i +1) %3 == 0 && i != 0) $write("\n");
i = i+1; j=j+1;
end
$write("\n\n\n");
#5
i = 0; j = 0;
while(i < 9 && j < 9)
begin
if(X_state[i] == 1)
$write("X");
else if(O_state[i] == 1)
$write("O");
else
$write("B");
if((i +1) %3 == 0 && i != 0) $write("\n");
i = i+1; j=j+1;
end
$write("\n\n\n");
move = 0;
#20
i = 0; j = 0;
while(i < 9 && j < 9)
begin
if(X_state[i] == 1)
$write("X");
else if(O_state[i] == 1)
$write("O");
else
$write("B");
if((i +1) %3 == 0 && i != 0) $write("\n");
i = i+1; j=j+1;
end
$write("\n");
$display("X_pos | AIMove %b", AIMove);
$display("X: %b", X_state);
$display("O: %b", O_state);
$display("Game Status: %b", status);
$display(O_state == 9'b000_000_111 || O_state == 9'b000_111_000 || O_state == 9'b111_000_000 ||
O_state == 9'b100_100_100 || O_state == 9'b010_010_010 || O_state == 9'b001_001_001 ||
O_state == 9'b100_010_001 || O_state == 9'b001_010_100);
$finish;
end
always #5 clk = ~clk;
SimpleAI sa(
.X_state(X_state),
.O_state(O_state),
.AIMove(AIMove)
);
LookupTableAI hard_ai(
.X_state(X_state),
.O_state(O_state),
.AIMove(AIMove_hard)
);
GameState state(
.rst(rst),
.move(move),
.clk(clk),
.nextMove(nextMove),
.AISwitch(AISwitch),
.AIMove(AIMove),
.AIMove_Hard(AIMove_hard),
.numWins(numWins),
.X_state(X_state),
.O_state(O_state),
.GameStatus(status)
);
endmodule | 0 |
138,230 | data/full_repos/permissive/82757492/HandlingInput/Debouncer.v | 82,757,492 | Debouncer.v | v | 41 | 83 | [] | [] | [] | [(22, 41)] | null | data/verilator_xmls/b43e6e62-606a-453e-986f-36ccf1309db2.xml | null | 301,943 | module | module Debouncer(
input clk,
input clk2,
input real_btn_input,
output debounced_btn_input
);
reg [1:0] btn_delay_counter;
assign debounced_btn_input = (~btn_delay_counter[0] && btn_delay_counter[1]);
always @(posedge clk ) begin
if( clk2 == 1 ) begin
btn_delay_counter <= {real_btn_input, btn_delay_counter[1]};
end
else begin
btn_delay_counter <= btn_delay_counter;
end
end
endmodule | module Debouncer(
input clk,
input clk2,
input real_btn_input,
output debounced_btn_input
); |
reg [1:0] btn_delay_counter;
assign debounced_btn_input = (~btn_delay_counter[0] && btn_delay_counter[1]);
always @(posedge clk ) begin
if( clk2 == 1 ) begin
btn_delay_counter <= {real_btn_input, btn_delay_counter[1]};
end
else begin
btn_delay_counter <= btn_delay_counter;
end
end
endmodule | 0 |
138,231 | data/full_repos/permissive/82757492/Score/Display.v | 82,757,492 | Display.v | v | 130 | 83 | [] | [] | [] | [(22, 100), (104, 130)] | null | null | 1: b"%Error: data/full_repos/permissive/82757492/Score/Display.v:47: Cannot find file containing module: 'binary_to_BCD'\n binary_to_BCD converter(\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82757492/Score,data/full_repos/permissive/82757492/binary_to_BCD\n data/full_repos/permissive/82757492/Score,data/full_repos/permissive/82757492/binary_to_BCD.v\n data/full_repos/permissive/82757492/Score,data/full_repos/permissive/82757492/binary_to_BCD.sv\n binary_to_BCD\n binary_to_BCD.v\n binary_to_BCD.sv\n obj_dir/binary_to_BCD\n obj_dir/binary_to_BCD.v\n obj_dir/binary_to_BCD.sv\n%Error: Exiting due to 1 error(s)\n" | 301,946 | module | module Display(
Value, clk,
seg, an
);
input clk;
input [7:0] Value;
output reg [7:0] seg;
output reg [3:0] an;
wire [7:0] Minute0;
wire [7:0] Minute1;
wire [7:0] Second0;
wire [7:0] Second1;
reg [1:0] state;
reg [1:0] nextState;
wire [3:0] Digit1Input;
wire [3:0] Digit3Input;
wire [3:0] Digit4Input;
binary_to_BCD converter(
.A(Value),
.ONES(Digit3Input),
.TENS(Digit4Input),
.HUNDREDS(Digit1Input)
);
DisplayDigit min0 (
.clk(clk),
.Digit(Digit1Input),
.Display(Minute0)
);
DisplayDigit sec0 (
.clk(clk),
.Digit(Digit3Input),
.Display(Second0)
);
DisplayDigit sec1 (
.clk(clk),
.Digit(Digit4Input),
.Display(Second1)
);
always @(posedge clk) begin
case(state)
2'b00: begin
an = 4'b1110;
seg = Second0;
nextState = 2'b01;
end
2'b01: begin
an = 4'b1101;
seg = Second1;
nextState = 2'b10;
end
2'b10: begin
an = 4'b1011;
seg = Minute0;
nextState = 2'b11;
end
default: begin
an = 4'b0111;
seg = 8'b11111111;
nextState = 2'b00;
end
endcase
end
always @ (posedge clk) begin
state <= nextState;
end
endmodule | module Display(
Value, clk,
seg, an
); |
input clk;
input [7:0] Value;
output reg [7:0] seg;
output reg [3:0] an;
wire [7:0] Minute0;
wire [7:0] Minute1;
wire [7:0] Second0;
wire [7:0] Second1;
reg [1:0] state;
reg [1:0] nextState;
wire [3:0] Digit1Input;
wire [3:0] Digit3Input;
wire [3:0] Digit4Input;
binary_to_BCD converter(
.A(Value),
.ONES(Digit3Input),
.TENS(Digit4Input),
.HUNDREDS(Digit1Input)
);
DisplayDigit min0 (
.clk(clk),
.Digit(Digit1Input),
.Display(Minute0)
);
DisplayDigit sec0 (
.clk(clk),
.Digit(Digit3Input),
.Display(Second0)
);
DisplayDigit sec1 (
.clk(clk),
.Digit(Digit4Input),
.Display(Second1)
);
always @(posedge clk) begin
case(state)
2'b00: begin
an = 4'b1110;
seg = Second0;
nextState = 2'b01;
end
2'b01: begin
an = 4'b1101;
seg = Second1;
nextState = 2'b10;
end
2'b10: begin
an = 4'b1011;
seg = Minute0;
nextState = 2'b11;
end
default: begin
an = 4'b0111;
seg = 8'b11111111;
nextState = 2'b00;
end
endcase
end
always @ (posedge clk) begin
state <= nextState;
end
endmodule | 0 |
138,232 | data/full_repos/permissive/82757492/Score/Display.v | 82,757,492 | Display.v | v | 130 | 83 | [] | [] | [] | [(22, 100), (104, 130)] | null | null | 1: b"%Error: data/full_repos/permissive/82757492/Score/Display.v:47: Cannot find file containing module: 'binary_to_BCD'\n binary_to_BCD converter(\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82757492/Score,data/full_repos/permissive/82757492/binary_to_BCD\n data/full_repos/permissive/82757492/Score,data/full_repos/permissive/82757492/binary_to_BCD.v\n data/full_repos/permissive/82757492/Score,data/full_repos/permissive/82757492/binary_to_BCD.sv\n binary_to_BCD\n binary_to_BCD.v\n binary_to_BCD.sv\n obj_dir/binary_to_BCD\n obj_dir/binary_to_BCD.v\n obj_dir/binary_to_BCD.sv\n%Error: Exiting due to 1 error(s)\n" | 301,946 | module | module DisplayDigit (
clk, Digit,
Display
);
input clk;
input [3:0] Digit;
output reg [7:0] Display;
always @ (posedge clk) begin
case (Digit)
4'h0: Display = 8'b11000000;
4'h1: Display = 8'b11111001;
4'h2: Display = 8'b10100100;
4'h3: Display = 8'b10110000;
4'h4: Display = 8'b10011001;
4'h5: Display = 8'b10010010;
4'h6: Display = 8'b10000010;
4'h7: Display = 8'b11111000;
4'h8: Display = 8'b10000000;
4'h9: Display = 8'b10010000;
default: Display = 8'b11111111;
endcase
end
endmodule | module DisplayDigit (
clk, Digit,
Display
); |
input clk;
input [3:0] Digit;
output reg [7:0] Display;
always @ (posedge clk) begin
case (Digit)
4'h0: Display = 8'b11000000;
4'h1: Display = 8'b11111001;
4'h2: Display = 8'b10100100;
4'h3: Display = 8'b10110000;
4'h4: Display = 8'b10011001;
4'h5: Display = 8'b10010010;
4'h6: Display = 8'b10000010;
4'h7: Display = 8'b11111000;
4'h8: Display = 8'b10000000;
4'h9: Display = 8'b10010000;
default: Display = 8'b11111111;
endcase
end
endmodule | 0 |
138,233 | data/full_repos/permissive/82757492/VGA/clockdiv.v | 82,757,492 | clockdiv.v | v | 61 | 148 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xf7 in position 1126: invalid start byte | data/verilator_xmls/e2b930ad-aa0d-48bb-ad7e-b5d5b4ea94e8.xml | null | 301,947 | module | module clockdiv(
input wire clk,
input wire rst,
output wire logic_en,
output wire logic_en_1,
output wire pix_en,
output wire display_en
);
reg [17:0] q;
always @(posedge clk)
begin
if (rst == 1)
q <= 0;
else
q <= q+1;
end
assign logic_en = q[15] & ~q[14] & ~q[13] & ~q[12] & ~q[11] & ~q[10] & ~q[9] & ~q[8] & ~q[7] & ~q[6] & ~q[5] & ~q[4] & ~q[3]& ~q[2] & ~q[1]& ~q[0];
assign logic_en_1 = q[15] & ~q[14] & ~q[13] & ~q[12] & ~q[11] & ~q[10] & ~q[9] & ~q[8] & ~q[7] & ~q[6] & ~q[5] & ~q[4] & ~q[3]& ~q[2] & ~q[1]& q[0];
assign display_en = q[14] & ~q[13] & ~q[12] & ~q[11] & ~q[10] & ~q[9] & ~q[8] & ~q[7] & ~q[6] & ~q[5] & ~q[4] & ~q[3]& ~q[2] & ~q[1]& ~q[0];
assign pix_en = ~q[1] & ~q[0];
endmodule | module clockdiv(
input wire clk,
input wire rst,
output wire logic_en,
output wire logic_en_1,
output wire pix_en,
output wire display_en
); |
reg [17:0] q;
always @(posedge clk)
begin
if (rst == 1)
q <= 0;
else
q <= q+1;
end
assign logic_en = q[15] & ~q[14] & ~q[13] & ~q[12] & ~q[11] & ~q[10] & ~q[9] & ~q[8] & ~q[7] & ~q[6] & ~q[5] & ~q[4] & ~q[3]& ~q[2] & ~q[1]& ~q[0];
assign logic_en_1 = q[15] & ~q[14] & ~q[13] & ~q[12] & ~q[11] & ~q[10] & ~q[9] & ~q[8] & ~q[7] & ~q[6] & ~q[5] & ~q[4] & ~q[3]& ~q[2] & ~q[1]& q[0];
assign display_en = q[14] & ~q[13] & ~q[12] & ~q[11] & ~q[10] & ~q[9] & ~q[8] & ~q[7] & ~q[6] & ~q[5] & ~q[4] & ~q[3]& ~q[2] & ~q[1]& ~q[0];
assign pix_en = ~q[1] & ~q[0];
endmodule | 0 |
138,234 | data/full_repos/permissive/82757492/VGA/vga640x480.v | 82,757,492 | vga640x480.v | v | 632 | 149 | [] | [] | [] | [(21, 631)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/82757492/VGA/vga640x480.v:103: Operator VAR \'o_pic\' expects 2501 bits on the Initial value, but Initial value\'s REPLICATE generates 2500 bits.\n : ... In instance vga640x480\nparameter [2500:0] o_pic = {\n ^~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/82757492/VGA/vga640x480.v:156: Operator VAR \'x_pic\' expects 2501 bits on the Initial value, but Initial value\'s REPLICATE generates 2500 bits.\n : ... In instance vga640x480\nparameter [2500:0] x_pic = {\n ^~~~~\n%Error: Exiting due to 2 warning(s)\n' | 301,948 | module | module vga640x480(
input wire pix_en,
input wire clk,
input wire rst,
input wire [8:0] o_vec,
input wire [8:0] x_vec,
input wire [2:0] game_status,
output wire hsync,
output wire vsync,
output reg [2:0] red,
output reg [2:0] green,
output reg [1:0] blue
);
parameter [9:0] hpixels = 800;
parameter [9:0] vlines = 521;
parameter [9:0] hpulse = 96;
parameter [9:0] vpulse = 2;
parameter [9:0] hbp = 144;
parameter [9:0] hfp = 784;
parameter [9:0] vbp = 31;
parameter [9:0] vfp = 511;
reg [9:0] hc;
reg [9:0] vc;
always @(posedge clk)
begin
if (rst == 1)
begin
hc <= 0;
vc <= 0;
end
else if (pix_en == 1)
begin
if (hc < hpixels - 1)
hc <= hc + 1;
else
begin
hc <= 0;
if (vc < vlines - 1)
vc <= vc + 1;
else
vc <= 0;
end
end
end
assign hsync = (hc < hpulse) ? 0:1;
assign vsync = (vc < vpulse) ? 0:1;
parameter [9:0] line_thickness = 2;
parameter [9:0] tile_offset = 10;
parameter [9:0] tile_width = 50;
parameter [9:0] radius = 15;
parameter [9:0] circle_thickness = 2;
reg [50:0] x_arr [50:0];
reg [50:0] y_arr [50:0];
parameter [2500:0] o_pic = {
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000001111111111100000000000000000000},
{50'b00000000000000001111111111111111100000000000000000},
{50'b00000000000000011111111111111111110000000000000000},
{50'b00000000000001111110000000000011111100000000000000},
{50'b00000000000011111000000000000000111110000000000000},
{50'b00000000000111100000000000000000001111000000000000},
{50'b00000000001111000000000000000000000111100000000000},
{50'b00000000001110000000000000000000000011100000000000},
{50'b00000000011100000000000000000000000001110000000000},
{50'b00000000111100000000000000000000000001111000000000},
{50'b00000000111000000000000000000000000000111000000000},
{50'b00000000111000000000000000000000000000111000000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000000111000000000000000000000000000111000000000},
{50'b00000000111000000000000000000000000000111000000000},
{50'b00000000111100000000000000000000000001111000000000},
{50'b00000000011100000000000000000000000001110000000000},
{50'b00000000001110000000000000000000000011100000000000},
{50'b00000000001111000000000000000000000111100000000000},
{50'b00000000000111100000000000000000001111000000000000},
{50'b00000000000011111000000000000000111110000000000000},
{50'b00000000000001111110000000000011111100000000000000},
{50'b00000000000000011111111111111111110000000000000000},
{50'b00000000000000001111111111111111100000000000000000},
{50'b00000000000000000001111111111100000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000}
};
parameter [2500:0] x_pic = {
{50'b00000000000000000000000000000000000000000000000000},
{50'b01110000000000000000000000000000000000000000000111},
{50'b00111000000000000000000000000000000000000000001110},
{50'b00011100000000000000000000000000000000000000011100},
{50'b00001110000000000000000000000000000000000000111000},
{50'b00000111000000000000000000000000000000000001110000},
{50'b00000011100000000000000000000000000000000011100000},
{50'b00000001110000000000000000000000000000000111000000},
{50'b00000000111000000000000000000000000000001110000000},
{50'b00000000011100000000000000000000000000011100000000},
{50'b00000000001110000000000000000000000000111000000000},
{50'b00000000000111000000000000000000000001110000000000},
{50'b00000000000011100000000000000000000011100000000000},
{50'b00000000000001110000000000000000000111000000000000},
{50'b00000000000000111000000000000000001110000000000000},
{50'b00000000000000011100000000000000011100000000000000},
{50'b00000000000000001110000000000000111000000000000000},
{50'b00000000000000000111000000000001110000000000000000},
{50'b00000000000000000011100000000011100000000000000000},
{50'b00000000000000000001110000000111000000000000000000},
{50'b00000000000000000000111000001110000000000000000000},
{50'b00000000000000000000011100011100000000000000000000},
{50'b00000000000000000000001110111000000000000000000000},
{50'b00000000000000000000000111110000000000000000000000},
{50'b00000000000000000000000011100000000000000000000000},
{50'b00000000000000000000000111110000000000000000000000},
{50'b00000000000000000000001110111000000000000000000000},
{50'b00000000000000000000011100011100000000000000000000},
{50'b00000000000000000000111000001110000000000000000000},
{50'b00000000000000000001110000000111000000000000000000},
{50'b00000000000000000011100000000011100000000000000000},
{50'b00000000000000000111000000000001110000000000000000},
{50'b00000000000000001110000000000000111000000000000000},
{50'b00000000000000011100000000000000011100000000000000},
{50'b00000000000000111000000000000000001110000000000000},
{50'b00000000000001110000000000000000000111000000000000},
{50'b00000000000011100000000000000000000011100000000000},
{50'b00000000000111000000000000000000000001110000000000},
{50'b00000000001110000000000000000000000000111000000000},
{50'b00000000011100000000000000000000000000011100000000},
{50'b00000000111000000000000000000000000000001110000000},
{50'b00000001110000000000000000000000000000000111000000},
{50'b00000011100000000000000000000000000000000011100000},
{50'b00000111000000000000000000000000000000000001110000},
{50'b00001110000000000000000000000000000000000000111000},
{50'b00011100000000000000000000000000000000000000011100},
{50'b00111000000000000000000000000000000000000000001110},
{50'b01110000000000000000000000000000000000000000000111},
{50'b01100000000000000000000000000000000000000000000011},
{50'b01000000000000000000000000000000000000000000000001}
};
always @(*)
begin
if (vc >= vbp && vc < vfp)
begin
if ( (hc >= (hbp + tile_offset + tile_width) && hc < (hbp + tile_offset + tile_width + line_thickness)
&& vc >= (vbp + tile_offset) && vc < (vbp + tile_offset + 3*tile_width + 2*line_thickness))
|| (hc >= (hbp + tile_offset + tile_width*2 + line_thickness) && hc < (hbp + tile_offset + tile_width*2 + line_thickness*2)
&& vc >= (vbp + tile_offset) && vc < (vbp + tile_offset + 3*tile_width + 2*line_thickness))
|| (vc >= (vbp + tile_offset + tile_width*2 + line_thickness) && vc < (vbp + tile_offset + tile_width*2 + line_thickness*2)
&& hc >= (hbp + tile_offset) && hc < (hbp + tile_offset + 3*tile_width + 2*line_thickness))
|| (vc >= (vbp + tile_offset + tile_width) && vc < (vbp + tile_offset + tile_width + line_thickness)
&& hc >= (hbp + tile_offset) && hc < (hbp + tile_offset + 3*tile_width + 2*line_thickness)))
begin
red = 3'b010;
green = 3'b100;
blue = 2'b11;
end
else if ( (hc >= (hbp + tile_offset) && hc < (hbp + tile_offset + tile_width))
&& (vc >= (vbp + tile_offset) && vc < (vbp + tile_offset + tile_width)))
begin
if (o_vec[0])
begin
if (o_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b00;
end
end
else if (x_vec[0])
begin
if (x_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b00;
end
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b00;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness + tile_width) && hc < (hbp + tile_offset + tile_width*2 + line_thickness))
&& (vc >= (vbp + tile_offset) && vc < (vbp + tile_offset + tile_width)))
begin
if (o_vec[1])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b00;
end
end
else if (x_vec[1])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b00;
end
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b00;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness*2 + tile_width*2) && hc < (hbp + tile_offset + tile_width*3 + line_thickness*2))
&& (vc >= (vbp + tile_offset) && vc < (vbp + tile_offset + tile_width)))
begin
if (o_vec[2])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness*2) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b000;
blue = 2'b11;
end
end
else if (x_vec[2])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness*2) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b000;
blue = 2'b11;
end
end
else
begin
red = 3'b000;
green = 3'b000;
blue = 2'b11;
end
end
else if ( (hc >= (hbp + tile_offset) && hc < (hbp + tile_offset + tile_width))
&& (vc >= (vbp + tile_offset + line_thickness + tile_width) && vc < (vbp + tile_offset + tile_width*2 + line_thickness)))
begin
if (o_vec[3])
begin
if (o_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b111;
blue = 2'b00;
end
end
else if (x_vec[3])
begin
if (x_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b111;
blue = 2'b00;
end
end
else
begin
red = 3'b111;
green = 3'b111;
blue = 2'b00;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness + tile_width) && hc < (hbp + tile_offset + tile_width*2 + line_thickness))
&& (vc >= (vbp + tile_offset + line_thickness + tile_width) && vc < (vbp + tile_offset + tile_width*2 + line_thickness)))
begin
if (o_vec[4])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b11;
end
end
else if (x_vec[4])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b11;
end
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b11;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness*2 + tile_width*2) && hc < (hbp + tile_offset + tile_width*3 + line_thickness*2))
&& (vc >= (vbp + tile_offset + line_thickness + tile_width) && vc < (vbp + tile_offset + tile_width*2 + line_thickness)))
begin
if (o_vec[5])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness*2) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b11;
end
end
else if (x_vec[5])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness*2) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b11;
end
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b11;
end
end
else if ( (hc >= (hbp + tile_offset) && hc < (hbp + tile_offset + tile_width))
&& (vc >= (vbp + tile_offset + line_thickness*2 + tile_width*2) && vc < (vbp + tile_offset + tile_width*3 + line_thickness*2)))
begin
if (o_vec[6])
begin
if (o_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness * 2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b010;
green = 3'b000;
blue = 2'b00;
end
end
else if (x_vec[6])
begin
if (x_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness * 2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b010;
green = 3'b000;
blue = 2'b00;
end
end
else
begin
red = 3'b010;
green = 3'b000;
blue = 2'b00;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness + tile_width) && hc < (hbp + tile_offset + tile_width*2 + line_thickness))
&& (vc >= (vbp + tile_offset + line_thickness*2 + tile_width*2) && vc < (vbp + tile_offset + tile_width*3 + line_thickness*2)))
begin
if (o_vec[7])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness*2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b010;
blue = 2'b00;
end
end
else if (x_vec[7])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness*2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b010;
blue = 2'b00;
end
end
else
begin
red = 3'b000;
green = 3'b010;
blue = 2'b00;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness*2 + tile_width*2) && hc < (hbp + tile_offset + tile_width*3 + line_thickness*2))
&& (vc >= (vbp + tile_offset + line_thickness*2 + tile_width*2) && vc < (vbp + tile_offset + tile_width*3 + line_thickness*2)))
begin
if (o_vec[8])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness * 2) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness * 2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b010;
green = 3'b010;
blue = 2'b00;
end
end
else if (x_vec[8])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness * 2) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness * 2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b010;
green = 3'b010;
blue = 2'b00;
end
end
else
begin
red = 3'b010;
green = 3'b010;
blue = 2'b00;
end
end
else if (hc >= (hbp) && hc < (hfp))
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 0;
green = 0;
blue = 0;
end
end
else
begin
red = 0;
green = 0;
blue = 0;
end
end
endmodule | module vga640x480(
input wire pix_en,
input wire clk,
input wire rst,
input wire [8:0] o_vec,
input wire [8:0] x_vec,
input wire [2:0] game_status,
output wire hsync,
output wire vsync,
output reg [2:0] red,
output reg [2:0] green,
output reg [1:0] blue
); |
parameter [9:0] hpixels = 800;
parameter [9:0] vlines = 521;
parameter [9:0] hpulse = 96;
parameter [9:0] vpulse = 2;
parameter [9:0] hbp = 144;
parameter [9:0] hfp = 784;
parameter [9:0] vbp = 31;
parameter [9:0] vfp = 511;
reg [9:0] hc;
reg [9:0] vc;
always @(posedge clk)
begin
if (rst == 1)
begin
hc <= 0;
vc <= 0;
end
else if (pix_en == 1)
begin
if (hc < hpixels - 1)
hc <= hc + 1;
else
begin
hc <= 0;
if (vc < vlines - 1)
vc <= vc + 1;
else
vc <= 0;
end
end
end
assign hsync = (hc < hpulse) ? 0:1;
assign vsync = (vc < vpulse) ? 0:1;
parameter [9:0] line_thickness = 2;
parameter [9:0] tile_offset = 10;
parameter [9:0] tile_width = 50;
parameter [9:0] radius = 15;
parameter [9:0] circle_thickness = 2;
reg [50:0] x_arr [50:0];
reg [50:0] y_arr [50:0];
parameter [2500:0] o_pic = {
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000001111111111100000000000000000000},
{50'b00000000000000001111111111111111100000000000000000},
{50'b00000000000000011111111111111111110000000000000000},
{50'b00000000000001111110000000000011111100000000000000},
{50'b00000000000011111000000000000000111110000000000000},
{50'b00000000000111100000000000000000001111000000000000},
{50'b00000000001111000000000000000000000111100000000000},
{50'b00000000001110000000000000000000000011100000000000},
{50'b00000000011100000000000000000000000001110000000000},
{50'b00000000111100000000000000000000000001111000000000},
{50'b00000000111000000000000000000000000000111000000000},
{50'b00000000111000000000000000000000000000111000000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000000111000000000000000000000000000111000000000},
{50'b00000000111000000000000000000000000000111000000000},
{50'b00000000111100000000000000000000000001111000000000},
{50'b00000000011100000000000000000000000001110000000000},
{50'b00000000001110000000000000000000000011100000000000},
{50'b00000000001111000000000000000000000111100000000000},
{50'b00000000000111100000000000000000001111000000000000},
{50'b00000000000011111000000000000000111110000000000000},
{50'b00000000000001111110000000000011111100000000000000},
{50'b00000000000000011111111111111111110000000000000000},
{50'b00000000000000001111111111111111100000000000000000},
{50'b00000000000000000001111111111100000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000}
};
parameter [2500:0] x_pic = {
{50'b00000000000000000000000000000000000000000000000000},
{50'b01110000000000000000000000000000000000000000000111},
{50'b00111000000000000000000000000000000000000000001110},
{50'b00011100000000000000000000000000000000000000011100},
{50'b00001110000000000000000000000000000000000000111000},
{50'b00000111000000000000000000000000000000000001110000},
{50'b00000011100000000000000000000000000000000011100000},
{50'b00000001110000000000000000000000000000000111000000},
{50'b00000000111000000000000000000000000000001110000000},
{50'b00000000011100000000000000000000000000011100000000},
{50'b00000000001110000000000000000000000000111000000000},
{50'b00000000000111000000000000000000000001110000000000},
{50'b00000000000011100000000000000000000011100000000000},
{50'b00000000000001110000000000000000000111000000000000},
{50'b00000000000000111000000000000000001110000000000000},
{50'b00000000000000011100000000000000011100000000000000},
{50'b00000000000000001110000000000000111000000000000000},
{50'b00000000000000000111000000000001110000000000000000},
{50'b00000000000000000011100000000011100000000000000000},
{50'b00000000000000000001110000000111000000000000000000},
{50'b00000000000000000000111000001110000000000000000000},
{50'b00000000000000000000011100011100000000000000000000},
{50'b00000000000000000000001110111000000000000000000000},
{50'b00000000000000000000000111110000000000000000000000},
{50'b00000000000000000000000011100000000000000000000000},
{50'b00000000000000000000000111110000000000000000000000},
{50'b00000000000000000000001110111000000000000000000000},
{50'b00000000000000000000011100011100000000000000000000},
{50'b00000000000000000000111000001110000000000000000000},
{50'b00000000000000000001110000000111000000000000000000},
{50'b00000000000000000011100000000011100000000000000000},
{50'b00000000000000000111000000000001110000000000000000},
{50'b00000000000000001110000000000000111000000000000000},
{50'b00000000000000011100000000000000011100000000000000},
{50'b00000000000000111000000000000000001110000000000000},
{50'b00000000000001110000000000000000000111000000000000},
{50'b00000000000011100000000000000000000011100000000000},
{50'b00000000000111000000000000000000000001110000000000},
{50'b00000000001110000000000000000000000000111000000000},
{50'b00000000011100000000000000000000000000011100000000},
{50'b00000000111000000000000000000000000000001110000000},
{50'b00000001110000000000000000000000000000000111000000},
{50'b00000011100000000000000000000000000000000011100000},
{50'b00000111000000000000000000000000000000000001110000},
{50'b00001110000000000000000000000000000000000000111000},
{50'b00011100000000000000000000000000000000000000011100},
{50'b00111000000000000000000000000000000000000000001110},
{50'b01110000000000000000000000000000000000000000000111},
{50'b01100000000000000000000000000000000000000000000011},
{50'b01000000000000000000000000000000000000000000000001}
};
always @(*)
begin
if (vc >= vbp && vc < vfp)
begin
if ( (hc >= (hbp + tile_offset + tile_width) && hc < (hbp + tile_offset + tile_width + line_thickness)
&& vc >= (vbp + tile_offset) && vc < (vbp + tile_offset + 3*tile_width + 2*line_thickness))
|| (hc >= (hbp + tile_offset + tile_width*2 + line_thickness) && hc < (hbp + tile_offset + tile_width*2 + line_thickness*2)
&& vc >= (vbp + tile_offset) && vc < (vbp + tile_offset + 3*tile_width + 2*line_thickness))
|| (vc >= (vbp + tile_offset + tile_width*2 + line_thickness) && vc < (vbp + tile_offset + tile_width*2 + line_thickness*2)
&& hc >= (hbp + tile_offset) && hc < (hbp + tile_offset + 3*tile_width + 2*line_thickness))
|| (vc >= (vbp + tile_offset + tile_width) && vc < (vbp + tile_offset + tile_width + line_thickness)
&& hc >= (hbp + tile_offset) && hc < (hbp + tile_offset + 3*tile_width + 2*line_thickness)))
begin
red = 3'b010;
green = 3'b100;
blue = 2'b11;
end
else if ( (hc >= (hbp + tile_offset) && hc < (hbp + tile_offset + tile_width))
&& (vc >= (vbp + tile_offset) && vc < (vbp + tile_offset + tile_width)))
begin
if (o_vec[0])
begin
if (o_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b00;
end
end
else if (x_vec[0])
begin
if (x_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b00;
end
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b00;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness + tile_width) && hc < (hbp + tile_offset + tile_width*2 + line_thickness))
&& (vc >= (vbp + tile_offset) && vc < (vbp + tile_offset + tile_width)))
begin
if (o_vec[1])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b00;
end
end
else if (x_vec[1])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b00;
end
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b00;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness*2 + tile_width*2) && hc < (hbp + tile_offset + tile_width*3 + line_thickness*2))
&& (vc >= (vbp + tile_offset) && vc < (vbp + tile_offset + tile_width)))
begin
if (o_vec[2])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness*2) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b000;
blue = 2'b11;
end
end
else if (x_vec[2])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness*2) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b000;
blue = 2'b11;
end
end
else
begin
red = 3'b000;
green = 3'b000;
blue = 2'b11;
end
end
else if ( (hc >= (hbp + tile_offset) && hc < (hbp + tile_offset + tile_width))
&& (vc >= (vbp + tile_offset + line_thickness + tile_width) && vc < (vbp + tile_offset + tile_width*2 + line_thickness)))
begin
if (o_vec[3])
begin
if (o_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b111;
blue = 2'b00;
end
end
else if (x_vec[3])
begin
if (x_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b111;
blue = 2'b00;
end
end
else
begin
red = 3'b111;
green = 3'b111;
blue = 2'b00;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness + tile_width) && hc < (hbp + tile_offset + tile_width*2 + line_thickness))
&& (vc >= (vbp + tile_offset + line_thickness + tile_width) && vc < (vbp + tile_offset + tile_width*2 + line_thickness)))
begin
if (o_vec[4])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b11;
end
end
else if (x_vec[4])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b11;
end
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b11;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness*2 + tile_width*2) && hc < (hbp + tile_offset + tile_width*3 + line_thickness*2))
&& (vc >= (vbp + tile_offset + line_thickness + tile_width) && vc < (vbp + tile_offset + tile_width*2 + line_thickness)))
begin
if (o_vec[5])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness*2) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b11;
end
end
else if (x_vec[5])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness*2) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b11;
end
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b11;
end
end
else if ( (hc >= (hbp + tile_offset) && hc < (hbp + tile_offset + tile_width))
&& (vc >= (vbp + tile_offset + line_thickness*2 + tile_width*2) && vc < (vbp + tile_offset + tile_width*3 + line_thickness*2)))
begin
if (o_vec[6])
begin
if (o_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness * 2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b010;
green = 3'b000;
blue = 2'b00;
end
end
else if (x_vec[6])
begin
if (x_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness * 2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b010;
green = 3'b000;
blue = 2'b00;
end
end
else
begin
red = 3'b010;
green = 3'b000;
blue = 2'b00;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness + tile_width) && hc < (hbp + tile_offset + tile_width*2 + line_thickness))
&& (vc >= (vbp + tile_offset + line_thickness*2 + tile_width*2) && vc < (vbp + tile_offset + tile_width*3 + line_thickness*2)))
begin
if (o_vec[7])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness*2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b010;
blue = 2'b00;
end
end
else if (x_vec[7])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness*2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b010;
blue = 2'b00;
end
end
else
begin
red = 3'b000;
green = 3'b010;
blue = 2'b00;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness*2 + tile_width*2) && hc < (hbp + tile_offset + tile_width*3 + line_thickness*2))
&& (vc >= (vbp + tile_offset + line_thickness*2 + tile_width*2) && vc < (vbp + tile_offset + tile_width*3 + line_thickness*2)))
begin
if (o_vec[8])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness * 2) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness * 2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b010;
green = 3'b010;
blue = 2'b00;
end
end
else if (x_vec[8])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness * 2) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness * 2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b010;
green = 3'b010;
blue = 2'b00;
end
end
else
begin
red = 3'b010;
green = 3'b010;
blue = 2'b00;
end
end
else if (hc >= (hbp) && hc < (hfp))
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 0;
green = 0;
blue = 0;
end
end
else
begin
red = 0;
green = 0;
blue = 0;
end
end
endmodule | 0 |
138,235 | data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv | 82,812,436 | mcenoc-rv-system.sv | sv | 477 | 109 | [] | [] | [] | null | line:36: before: "*" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:48: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk_in_p = ~clk_in_p;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:55: Unsupported: Ignoring delay on this delayed statement.\n #300000 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:56: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:57: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:58: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:59: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:60: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:61: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:62: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:63: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:64: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:69: Unsupported: Ignoring delay on this delayed statement.\n #1000000 $finish();\n ^\n%Warning-MULTITOP: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:39: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mcenoc_rv_system_top\'\nmodule mcenoc_rv_system_top (\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_rv_system_tb\'\nmodule mcenoc_rv_system_tb (\n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_ni_open_test\'\nmodule mcenoc_ni_open_test #(\n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_ni_loopback_test\'\nmodule mcenoc_ni_loopback_test #(\n ^~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_network_test\'\nmodule mcenoc_network_test #(\n ^~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:34: Signal definition not found, creating implicitly: \'pll_ic2_in4\'\n : ... Suggested alternative: \'pll_i2c_in4\'\n assign pll_ic2_in4 = 1\'b0;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:319: Cannot find file containing module: \'mcenoc_clk\'\n mcenoc_clk clkblk(.clk_in1_p(clk_in_p), .clk_in1_n(clk_in_n), .clk_out1(clk), .clk_out2(usbclk), .*);\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/mcenoc_clk\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/mcenoc_clk.v\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/mcenoc_clk.sv\n mcenoc_clk\n mcenoc_clk.v\n mcenoc_clk.sv\n obj_dir/mcenoc_clk\n obj_dir/mcenoc_clk.v\n obj_dir/mcenoc_clk.sv\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:355: Cannot find file containing module: \'uob_network\'\n uob_network #(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:391: Cannot find file containing module: \'pcpi_uart\'\n pcpi_uart uart(.rx(uart_rx), .tx(uart_tx), .irq(irq[3]), .eoi(eoi[3]), .*);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:394: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:428: Cannot find file containing module: \'picorv32_mem\'\n picorv32_mem mem (\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:436: Cannot find file containing module: \'picorv32\'\n picorv32 #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:255: Cannot find file containing module: \'uob_network\'\n uob_network #(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:268: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance mcenoc_network_test\n assign dat_in[port] = 1\'b0;\n ^\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:276: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:143: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:103: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s), 15 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,062 | module | module mcenoc_rv_system_top (
input clk_in_p,
input clk_in_n,
input uart_rx,
output uart_tx,
output led,
output usbclk,
output pll_clk_en,
output pll_i2c_in4
);
assign pll_clk_en = 1'b1;
assign pll_ic2_in4 = 1'b0;
mcenoc_rv_system #(.num_cores(16), .mcenoc_data_width(8), .mcenoc_bits_per_switch(1)) sys(.*);
endmodule | module mcenoc_rv_system_top (
input clk_in_p,
input clk_in_n,
input uart_rx,
output uart_tx,
output led,
output usbclk,
output pll_clk_en,
output pll_i2c_in4
); |
assign pll_clk_en = 1'b1;
assign pll_ic2_in4 = 1'b0;
mcenoc_rv_system #(.num_cores(16), .mcenoc_data_width(8), .mcenoc_bits_per_switch(1)) sys(.*);
endmodule | 0 |
138,236 | data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv | 82,812,436 | mcenoc-rv-system.sv | sv | 477 | 109 | [] | [] | [] | null | line:36: before: "*" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:48: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk_in_p = ~clk_in_p;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:55: Unsupported: Ignoring delay on this delayed statement.\n #300000 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:56: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:57: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:58: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:59: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:60: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:61: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:62: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:63: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:64: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:69: Unsupported: Ignoring delay on this delayed statement.\n #1000000 $finish();\n ^\n%Warning-MULTITOP: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:39: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mcenoc_rv_system_top\'\nmodule mcenoc_rv_system_top (\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_rv_system_tb\'\nmodule mcenoc_rv_system_tb (\n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_ni_open_test\'\nmodule mcenoc_ni_open_test #(\n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_ni_loopback_test\'\nmodule mcenoc_ni_loopback_test #(\n ^~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_network_test\'\nmodule mcenoc_network_test #(\n ^~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:34: Signal definition not found, creating implicitly: \'pll_ic2_in4\'\n : ... Suggested alternative: \'pll_i2c_in4\'\n assign pll_ic2_in4 = 1\'b0;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:319: Cannot find file containing module: \'mcenoc_clk\'\n mcenoc_clk clkblk(.clk_in1_p(clk_in_p), .clk_in1_n(clk_in_n), .clk_out1(clk), .clk_out2(usbclk), .*);\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/mcenoc_clk\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/mcenoc_clk.v\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/mcenoc_clk.sv\n mcenoc_clk\n mcenoc_clk.v\n mcenoc_clk.sv\n obj_dir/mcenoc_clk\n obj_dir/mcenoc_clk.v\n obj_dir/mcenoc_clk.sv\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:355: Cannot find file containing module: \'uob_network\'\n uob_network #(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:391: Cannot find file containing module: \'pcpi_uart\'\n pcpi_uart uart(.rx(uart_rx), .tx(uart_tx), .irq(irq[3]), .eoi(eoi[3]), .*);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:394: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:428: Cannot find file containing module: \'picorv32_mem\'\n picorv32_mem mem (\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:436: Cannot find file containing module: \'picorv32\'\n picorv32 #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:255: Cannot find file containing module: \'uob_network\'\n uob_network #(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:268: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance mcenoc_network_test\n assign dat_in[port] = 1\'b0;\n ^\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:276: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:143: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:103: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s), 15 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,062 | module | module mcenoc_rv_system_tb (
output uart_tx
);
reg clk_in_p = 0, uart_rx = 1;
wire clk_in_n, led;
wire usbclk;
assign clk_in_n = ~clk_in_p;
always #5 clk_in_p = ~clk_in_p;
mcenoc_rv_system #(.num_cores(8), .mcenoc_data_width(8), .mcenoc_bits_per_switch(1)) dut(.*);
initial begin
#300000 uart_rx <= 0;
#80 uart_rx <= 1;
#80 uart_rx <= 1;
#80 uart_rx <= 0;
#80 uart_rx <= 1;
#80 uart_rx <= 0;
#80 uart_rx <= 0;
#80 uart_rx <= 1;
#80 uart_rx <= 0;
#80 uart_rx <= 1;
end
initial begin
#1000000 $finish();
end
endmodule | module mcenoc_rv_system_tb (
output uart_tx
); |
reg clk_in_p = 0, uart_rx = 1;
wire clk_in_n, led;
wire usbclk;
assign clk_in_n = ~clk_in_p;
always #5 clk_in_p = ~clk_in_p;
mcenoc_rv_system #(.num_cores(8), .mcenoc_data_width(8), .mcenoc_bits_per_switch(1)) dut(.*);
initial begin
#300000 uart_rx <= 0;
#80 uart_rx <= 1;
#80 uart_rx <= 1;
#80 uart_rx <= 0;
#80 uart_rx <= 1;
#80 uart_rx <= 0;
#80 uart_rx <= 0;
#80 uart_rx <= 1;
#80 uart_rx <= 0;
#80 uart_rx <= 1;
end
initial begin
#1000000 $finish();
end
endmodule | 0 |
138,237 | data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv | 82,812,436 | mcenoc-rv-system.sv | sv | 477 | 109 | [] | [] | [] | null | line:36: before: "*" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:48: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk_in_p = ~clk_in_p;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:55: Unsupported: Ignoring delay on this delayed statement.\n #300000 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:56: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:57: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:58: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:59: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:60: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:61: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:62: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:63: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:64: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:69: Unsupported: Ignoring delay on this delayed statement.\n #1000000 $finish();\n ^\n%Warning-MULTITOP: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:39: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mcenoc_rv_system_top\'\nmodule mcenoc_rv_system_top (\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_rv_system_tb\'\nmodule mcenoc_rv_system_tb (\n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_ni_open_test\'\nmodule mcenoc_ni_open_test #(\n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_ni_loopback_test\'\nmodule mcenoc_ni_loopback_test #(\n ^~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_network_test\'\nmodule mcenoc_network_test #(\n ^~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:34: Signal definition not found, creating implicitly: \'pll_ic2_in4\'\n : ... Suggested alternative: \'pll_i2c_in4\'\n assign pll_ic2_in4 = 1\'b0;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:319: Cannot find file containing module: \'mcenoc_clk\'\n mcenoc_clk clkblk(.clk_in1_p(clk_in_p), .clk_in1_n(clk_in_n), .clk_out1(clk), .clk_out2(usbclk), .*);\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/mcenoc_clk\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/mcenoc_clk.v\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/mcenoc_clk.sv\n mcenoc_clk\n mcenoc_clk.v\n mcenoc_clk.sv\n obj_dir/mcenoc_clk\n obj_dir/mcenoc_clk.v\n obj_dir/mcenoc_clk.sv\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:355: Cannot find file containing module: \'uob_network\'\n uob_network #(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:391: Cannot find file containing module: \'pcpi_uart\'\n pcpi_uart uart(.rx(uart_rx), .tx(uart_tx), .irq(irq[3]), .eoi(eoi[3]), .*);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:394: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:428: Cannot find file containing module: \'picorv32_mem\'\n picorv32_mem mem (\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:436: Cannot find file containing module: \'picorv32\'\n picorv32 #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:255: Cannot find file containing module: \'uob_network\'\n uob_network #(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:268: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance mcenoc_network_test\n assign dat_in[port] = 1\'b0;\n ^\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:276: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:143: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:103: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s), 15 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,062 | module | module mcenoc_ni_open_test #(
parameter MCENOC_DATA_WIDTH=1,
parameter MCENOC_BITS_PER_SWITCH=1
) (
input clk,
input resetn,
input reset,
input pcpi_valid,
input [31:0] pcpi_insn,
input [31:0] pcpi_rs1,
input [31:0] eoi,
output [31:0] pcpi_rd,
output pcpi_wr,
output pcpi_wait,
output pcpi_ready,
output [31:0] irq,
input [MCENOC_DATA_WIDTH-1:0] data_in,
input act_in,
input err_in,
input cts_in,
input clm_in
);
wire [MCENOC_DATA_WIDTH-1:0] data_out;
wire act_out;
wire clm_out;
wire err_out;
wire cts_out;
pcpi_mcenoc_ni #(
.NETWORK_BITS_PER_SWITCH(MCENOC_BITS_PER_SWITCH),
.NETWORK_DWIDTH(MCENOC_DATA_WIDTH),
.OPEN_SVA(1)
) mcenoc_ni (
.irq(irq[4]),
.eoi(eoi[4]),
.*
);
endmodule | module mcenoc_ni_open_test #(
parameter MCENOC_DATA_WIDTH=1,
parameter MCENOC_BITS_PER_SWITCH=1
) (
input clk,
input resetn,
input reset,
input pcpi_valid,
input [31:0] pcpi_insn,
input [31:0] pcpi_rs1,
input [31:0] eoi,
output [31:0] pcpi_rd,
output pcpi_wr,
output pcpi_wait,
output pcpi_ready,
output [31:0] irq,
input [MCENOC_DATA_WIDTH-1:0] data_in,
input act_in,
input err_in,
input cts_in,
input clm_in
); |
wire [MCENOC_DATA_WIDTH-1:0] data_out;
wire act_out;
wire clm_out;
wire err_out;
wire cts_out;
pcpi_mcenoc_ni #(
.NETWORK_BITS_PER_SWITCH(MCENOC_BITS_PER_SWITCH),
.NETWORK_DWIDTH(MCENOC_DATA_WIDTH),
.OPEN_SVA(1)
) mcenoc_ni (
.irq(irq[4]),
.eoi(eoi[4]),
.*
);
endmodule | 0 |
138,238 | data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv | 82,812,436 | mcenoc-rv-system.sv | sv | 477 | 109 | [] | [] | [] | null | line:36: before: "*" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:48: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk_in_p = ~clk_in_p;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:55: Unsupported: Ignoring delay on this delayed statement.\n #300000 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:56: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:57: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:58: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:59: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:60: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:61: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:62: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:63: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:64: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:69: Unsupported: Ignoring delay on this delayed statement.\n #1000000 $finish();\n ^\n%Warning-MULTITOP: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:39: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mcenoc_rv_system_top\'\nmodule mcenoc_rv_system_top (\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_rv_system_tb\'\nmodule mcenoc_rv_system_tb (\n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_ni_open_test\'\nmodule mcenoc_ni_open_test #(\n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_ni_loopback_test\'\nmodule mcenoc_ni_loopback_test #(\n ^~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_network_test\'\nmodule mcenoc_network_test #(\n ^~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:34: Signal definition not found, creating implicitly: \'pll_ic2_in4\'\n : ... Suggested alternative: \'pll_i2c_in4\'\n assign pll_ic2_in4 = 1\'b0;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:319: Cannot find file containing module: \'mcenoc_clk\'\n mcenoc_clk clkblk(.clk_in1_p(clk_in_p), .clk_in1_n(clk_in_n), .clk_out1(clk), .clk_out2(usbclk), .*);\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/mcenoc_clk\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/mcenoc_clk.v\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/mcenoc_clk.sv\n mcenoc_clk\n mcenoc_clk.v\n mcenoc_clk.sv\n obj_dir/mcenoc_clk\n obj_dir/mcenoc_clk.v\n obj_dir/mcenoc_clk.sv\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:355: Cannot find file containing module: \'uob_network\'\n uob_network #(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:391: Cannot find file containing module: \'pcpi_uart\'\n pcpi_uart uart(.rx(uart_rx), .tx(uart_tx), .irq(irq[3]), .eoi(eoi[3]), .*);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:394: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:428: Cannot find file containing module: \'picorv32_mem\'\n picorv32_mem mem (\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:436: Cannot find file containing module: \'picorv32\'\n picorv32 #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:255: Cannot find file containing module: \'uob_network\'\n uob_network #(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:268: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance mcenoc_network_test\n assign dat_in[port] = 1\'b0;\n ^\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:276: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:143: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:103: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s), 15 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,062 | module | module mcenoc_ni_loopback_test #(
parameter MCENOC_DATA_WIDTH=1,
parameter MCENOC_BITS_PER_SWITCH=1
) (
input clk,
input resetn,
input pcpi_valid,
input [31:0] pcpi_insn,
input [31:0] pcpi_rs1,
input [31:0] eoi,
output [31:0] pcpi_rd,
output pcpi_wr,
output pcpi_wait,
output pcpi_ready,
output [31:0] irq
);
wire [MCENOC_DATA_WIDTH-1:0]dat_in;
wire act;
wire clm;
wire err;
wire cts;
wire [MCENOC_DATA_WIDTH-1:0]dat;
wire reset;
assign reset = !resetn;
pcpi_mcenoc_ni #(
.NETWORK_BITS_PER_SWITCH(MCENOC_BITS_PER_SWITCH),
.NETWORK_DWIDTH(MCENOC_DATA_WIDTH),
.NETWORK_NPORTS(1)
) mcenoc_ni (
.data_in(dat),
.clm_in(clm),
.act_in(act),
.cts_out(cts),
.err_out(err),
.data_out(dat),
.clm_out(clm),
.act_out(act),
.cts_in(cts),
.err_in(err),
.irq(irq[4]),
.eoi(eoi[4]),
.*
);
`ifdef SVA_ENABLE_0
default clocking svaclk @(posedge clk);
endclocking
default disable iff (!resetn);
assume property (!err && !eoi && !irq);
sequence initclaim();
($rose(resetn) && !err && !clm && !pcpi_valid) ##1
pcpi_valid && pcpi_insn[6:0] == 7'b0001011 && pcpi_insn[31:25] == 26 &&
pcpi_insn[23:20] == 4'b0 && pcpi_insn[24] == 1 && pcpi_rs1 == 1 ##1
!pcpi_valid;
endsequence
initclaimv: assert property (
initclaim() |-> $past(pcpi_ready) && clm
);
sequence txword();
pcpi_valid && pcpi_insn[6:0] == 7'b0001011 && pcpi_insn[31:25] == 25 &&
pcpi_insn[21:20] == 2'h3 && $stable(pcpi_rs1);
endsequence
txwordstart: assert property(
initclaim() ##1 txword() [*1:3] |-> pcpi_wait && !pcpi_ready
);
txwordend: assert property(
initclaim() ##1 txword() [*4] |-> $fell(pcpi_wait) && $rose(pcpi_ready) && pcpi_valid ##1 pcpi_valid
);
sequence rxword();
pcpi_valid && pcpi_insn[6:0] == 7'b0001011 && pcpi_insn[31:25] == 24 &&
pcpi_insn[21:20] == 2'h3;
endsequence
rxwordstart: assert property(
initclaim() ##1 txword() [*4] ##0 pcpi_ready ##1 $fell(pcpi_valid) |=> 1'b0
);
property endtoend();
bit [31:0] txdata;
initclaim() ##1 (txword(), txdata = pcpi_rs1) ##1 txword() [*4] ##1
!pcpi_valid ##1
pcpi_valid && pcpi_insn[6:0] == 7'b0001011 && pcpi_insn[31:25] == 24 &&
pcpi_insn[21:20] == 2'h3 [*4]
|-> pcpi_ready && pcpi_wr && pcpi_rd == txdata;
endproperty
txrx: assert property (endtoend());
`endif
endmodule | module mcenoc_ni_loopback_test #(
parameter MCENOC_DATA_WIDTH=1,
parameter MCENOC_BITS_PER_SWITCH=1
) (
input clk,
input resetn,
input pcpi_valid,
input [31:0] pcpi_insn,
input [31:0] pcpi_rs1,
input [31:0] eoi,
output [31:0] pcpi_rd,
output pcpi_wr,
output pcpi_wait,
output pcpi_ready,
output [31:0] irq
); |
wire [MCENOC_DATA_WIDTH-1:0]dat_in;
wire act;
wire clm;
wire err;
wire cts;
wire [MCENOC_DATA_WIDTH-1:0]dat;
wire reset;
assign reset = !resetn;
pcpi_mcenoc_ni #(
.NETWORK_BITS_PER_SWITCH(MCENOC_BITS_PER_SWITCH),
.NETWORK_DWIDTH(MCENOC_DATA_WIDTH),
.NETWORK_NPORTS(1)
) mcenoc_ni (
.data_in(dat),
.clm_in(clm),
.act_in(act),
.cts_out(cts),
.err_out(err),
.data_out(dat),
.clm_out(clm),
.act_out(act),
.cts_in(cts),
.err_in(err),
.irq(irq[4]),
.eoi(eoi[4]),
.*
);
`ifdef SVA_ENABLE_0
default clocking svaclk @(posedge clk);
endclocking
default disable iff (!resetn);
assume property (!err && !eoi && !irq);
sequence initclaim();
($rose(resetn) && !err && !clm && !pcpi_valid) ##1
pcpi_valid && pcpi_insn[6:0] == 7'b0001011 && pcpi_insn[31:25] == 26 &&
pcpi_insn[23:20] == 4'b0 && pcpi_insn[24] == 1 && pcpi_rs1 == 1 ##1
!pcpi_valid;
endsequence
initclaimv: assert property (
initclaim() |-> $past(pcpi_ready) && clm
);
sequence txword();
pcpi_valid && pcpi_insn[6:0] == 7'b0001011 && pcpi_insn[31:25] == 25 &&
pcpi_insn[21:20] == 2'h3 && $stable(pcpi_rs1);
endsequence
txwordstart: assert property(
initclaim() ##1 txword() [*1:3] |-> pcpi_wait && !pcpi_ready
);
txwordend: assert property(
initclaim() ##1 txword() [*4] |-> $fell(pcpi_wait) && $rose(pcpi_ready) && pcpi_valid ##1 pcpi_valid
);
sequence rxword();
pcpi_valid && pcpi_insn[6:0] == 7'b0001011 && pcpi_insn[31:25] == 24 &&
pcpi_insn[21:20] == 2'h3;
endsequence
rxwordstart: assert property(
initclaim() ##1 txword() [*4] ##0 pcpi_ready ##1 $fell(pcpi_valid) |=> 1'b0
);
property endtoend();
bit [31:0] txdata;
initclaim() ##1 (txword(), txdata = pcpi_rs1) ##1 txword() [*4] ##1
!pcpi_valid ##1
pcpi_valid && pcpi_insn[6:0] == 7'b0001011 && pcpi_insn[31:25] == 24 &&
pcpi_insn[21:20] == 2'h3 [*4]
|-> pcpi_ready && pcpi_wr && pcpi_rd == txdata;
endproperty
txrx: assert property (endtoend());
`endif
endmodule | 0 |
138,239 | data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv | 82,812,436 | mcenoc-rv-system.sv | sv | 477 | 109 | [] | [] | [] | null | line:36: before: "*" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:48: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk_in_p = ~clk_in_p;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:55: Unsupported: Ignoring delay on this delayed statement.\n #300000 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:56: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:57: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:58: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:59: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:60: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:61: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:62: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:63: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:64: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:69: Unsupported: Ignoring delay on this delayed statement.\n #1000000 $finish();\n ^\n%Warning-MULTITOP: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:39: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mcenoc_rv_system_top\'\nmodule mcenoc_rv_system_top (\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_rv_system_tb\'\nmodule mcenoc_rv_system_tb (\n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_ni_open_test\'\nmodule mcenoc_ni_open_test #(\n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_ni_loopback_test\'\nmodule mcenoc_ni_loopback_test #(\n ^~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_network_test\'\nmodule mcenoc_network_test #(\n ^~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:34: Signal definition not found, creating implicitly: \'pll_ic2_in4\'\n : ... Suggested alternative: \'pll_i2c_in4\'\n assign pll_ic2_in4 = 1\'b0;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:319: Cannot find file containing module: \'mcenoc_clk\'\n mcenoc_clk clkblk(.clk_in1_p(clk_in_p), .clk_in1_n(clk_in_n), .clk_out1(clk), .clk_out2(usbclk), .*);\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/mcenoc_clk\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/mcenoc_clk.v\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/mcenoc_clk.sv\n mcenoc_clk\n mcenoc_clk.v\n mcenoc_clk.sv\n obj_dir/mcenoc_clk\n obj_dir/mcenoc_clk.v\n obj_dir/mcenoc_clk.sv\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:355: Cannot find file containing module: \'uob_network\'\n uob_network #(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:391: Cannot find file containing module: \'pcpi_uart\'\n pcpi_uart uart(.rx(uart_rx), .tx(uart_tx), .irq(irq[3]), .eoi(eoi[3]), .*);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:394: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:428: Cannot find file containing module: \'picorv32_mem\'\n picorv32_mem mem (\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:436: Cannot find file containing module: \'picorv32\'\n picorv32 #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:255: Cannot find file containing module: \'uob_network\'\n uob_network #(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:268: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance mcenoc_network_test\n assign dat_in[port] = 1\'b0;\n ^\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:276: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:143: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:103: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s), 15 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,062 | module | module mcenoc_network_test #(
parameter num_cores = 16,
parameter mcenoc_data_width=8,
parameter bits_per_switch=1
) (
input clk,
input resetn,
input pcpi_valid,
input [31:0] pcpi_insn,
input [31:0] pcpi_rs1,
input [31:0] eoi,
output [31:0] pcpi_rd,
output pcpi_wr,
output pcpi_wait,
output pcpi_ready,
output [31:0] irq
);
wire reset = !resetn;
wire [mcenoc_data_width-1:0]dat_in[num_cores-1:0];
wire act_in[num_cores-1:0];
wire clm_in[num_cores-1:0];
wire err_in[num_cores-1:0];
wire cts_in[num_cores-1:0];
wire [mcenoc_data_width-1:0]dat_out[num_cores-1:0];
wire cts_out[num_cores-1:0];
wire err_out[num_cores-1:0];
wire act_out[num_cores-1:0];
wire clm_out[num_cores-1:0];
uob_network #(
.n_ports(num_cores),
.data_width(mcenoc_data_width),
.bits_per_switch(bits_per_switch),
.asrt_on(0)
) nw (
.rst(reset),
.*
);
genvar port;
generate
for (port = 1; port < num_cores; port = port + 1) begin:uobnpull
assign dat_in[port] = 1'b0;
assign act_in[port] = 1'b0;
assign clm_in[port] = 1'b0;
assign err_in[port] = 1'b0;
assign cts_in[port] = 1'b0;
end
endgenerate
pcpi_mcenoc_ni #(
.NETWORK_NPORTS(num_cores),
.NETWORK_BITS_PER_SWITCH(1),
.NETWORK_DWIDTH(mcenoc_data_width)
) mcenoc_ni (
.data_in(dat_out[0]),
.clm_in(clm_out[0]),
.act_in(act_out[0]),
.cts_out(cts_in[0]),
.err_out(err_in[0]),
.data_out(dat_in[0]),
.clm_out(clm_in[0]),
.act_out(act_in[0]),
.cts_in(cts_out[0]),
.err_in(err_out[0]),
.irq(irq[4]),
.eoi(eoi[4]),
.*
);
endmodule | module mcenoc_network_test #(
parameter num_cores = 16,
parameter mcenoc_data_width=8,
parameter bits_per_switch=1
) (
input clk,
input resetn,
input pcpi_valid,
input [31:0] pcpi_insn,
input [31:0] pcpi_rs1,
input [31:0] eoi,
output [31:0] pcpi_rd,
output pcpi_wr,
output pcpi_wait,
output pcpi_ready,
output [31:0] irq
); |
wire reset = !resetn;
wire [mcenoc_data_width-1:0]dat_in[num_cores-1:0];
wire act_in[num_cores-1:0];
wire clm_in[num_cores-1:0];
wire err_in[num_cores-1:0];
wire cts_in[num_cores-1:0];
wire [mcenoc_data_width-1:0]dat_out[num_cores-1:0];
wire cts_out[num_cores-1:0];
wire err_out[num_cores-1:0];
wire act_out[num_cores-1:0];
wire clm_out[num_cores-1:0];
uob_network #(
.n_ports(num_cores),
.data_width(mcenoc_data_width),
.bits_per_switch(bits_per_switch),
.asrt_on(0)
) nw (
.rst(reset),
.*
);
genvar port;
generate
for (port = 1; port < num_cores; port = port + 1) begin:uobnpull
assign dat_in[port] = 1'b0;
assign act_in[port] = 1'b0;
assign clm_in[port] = 1'b0;
assign err_in[port] = 1'b0;
assign cts_in[port] = 1'b0;
end
endgenerate
pcpi_mcenoc_ni #(
.NETWORK_NPORTS(num_cores),
.NETWORK_BITS_PER_SWITCH(1),
.NETWORK_DWIDTH(mcenoc_data_width)
) mcenoc_ni (
.data_in(dat_out[0]),
.clm_in(clm_out[0]),
.act_in(act_out[0]),
.cts_out(cts_in[0]),
.err_out(err_in[0]),
.data_out(dat_in[0]),
.clm_out(clm_in[0]),
.act_out(act_in[0]),
.cts_in(cts_out[0]),
.err_in(err_out[0]),
.irq(irq[4]),
.eoi(eoi[4]),
.*
);
endmodule | 0 |
138,240 | data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv | 82,812,436 | mcenoc-rv-system.sv | sv | 477 | 109 | [] | [] | [] | null | line:36: before: "*" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:48: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk_in_p = ~clk_in_p;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:55: Unsupported: Ignoring delay on this delayed statement.\n #300000 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:56: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:57: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:58: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:59: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:60: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:61: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:62: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:63: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:64: Unsupported: Ignoring delay on this delayed statement.\n #80 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:69: Unsupported: Ignoring delay on this delayed statement.\n #1000000 $finish();\n ^\n%Warning-MULTITOP: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:39: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'mcenoc_rv_system_top\'\nmodule mcenoc_rv_system_top (\n ^~~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_rv_system_tb\'\nmodule mcenoc_rv_system_tb (\n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_ni_open_test\'\nmodule mcenoc_ni_open_test #(\n ^~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_ni_loopback_test\'\nmodule mcenoc_ni_loopback_test #(\n ^~~~~~~~~~~~~~~~~~~~~~~\n : ... Top module \'mcenoc_network_test\'\nmodule mcenoc_network_test #(\n ^~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:34: Signal definition not found, creating implicitly: \'pll_ic2_in4\'\n : ... Suggested alternative: \'pll_i2c_in4\'\n assign pll_ic2_in4 = 1\'b0;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:319: Cannot find file containing module: \'mcenoc_clk\'\n mcenoc_clk clkblk(.clk_in1_p(clk_in_p), .clk_in1_n(clk_in_n), .clk_out1(clk), .clk_out2(usbclk), .*);\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/mcenoc_clk\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/mcenoc_clk.v\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/mcenoc_clk.sv\n mcenoc_clk\n mcenoc_clk.v\n mcenoc_clk.sv\n obj_dir/mcenoc_clk\n obj_dir/mcenoc_clk.v\n obj_dir/mcenoc_clk.sv\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:355: Cannot find file containing module: \'uob_network\'\n uob_network #(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:391: Cannot find file containing module: \'pcpi_uart\'\n pcpi_uart uart(.rx(uart_rx), .tx(uart_tx), .irq(irq[3]), .eoi(eoi[3]), .*);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:394: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:428: Cannot find file containing module: \'picorv32_mem\'\n picorv32_mem mem (\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:436: Cannot find file containing module: \'picorv32\'\n picorv32 #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:255: Cannot find file containing module: \'uob_network\'\n uob_network #(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:268: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance mcenoc_network_test\n assign dat_in[port] = 1\'b0;\n ^\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:276: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:143: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mcenoc-rv-system.sv:103: Cannot find file containing module: \'pcpi_mcenoc_ni\'\n pcpi_mcenoc_ni #(\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s), 15 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,062 | module | module mcenoc_rv_system #(
parameter num_cores = 1,
parameter mcenoc_data_width=1,
parameter reset_time = 64,
parameter mcenoc_bits_per_switch=1
) (
input clk_in_p,
input clk_in_n,
input uart_rx,
output uart_tx,
output led,
output usbclk
);
wire clk, locked;
reg resetn = 0;
integer rstcnt = 0;
wire reset;
assign reset = !resetn;
mcenoc_clk clkblk(.clk_in1_p(clk_in_p), .clk_in1_n(clk_in_n), .clk_out1(clk), .clk_out2(usbclk), .*);
reg [22:0] clkdiv = 0;
reg ledval = 0;
assign led = ledval;
always_ff @(posedge clk) begin
if (locked) begin
if (clkdiv == 0) ledval = ~ledval;
clkdiv = clkdiv + 1;
if (rstcnt == reset_time) begin
resetn = 1;
end else begin
rstcnt = rstcnt + 1;
resetn = 0;
end
end else rstcnt = 0;
end
wire [mcenoc_data_width-1:0]dat_in[num_cores-1:0];
wire act_in[num_cores-1:0];
wire clm_in[num_cores-1:0];
wire err_in[num_cores-1:0];
wire cts_in[num_cores-1:0];
wire [mcenoc_data_width-1:0]dat_out[num_cores-1:0];
wire cts_out[num_cores-1:0];
wire err_out[num_cores-1:0];
wire act_out[num_cores-1:0];
wire clm_out[num_cores-1:0];
generate
if (num_cores > 1) begin
uob_network #(
.n_ports(num_cores),
.data_width(mcenoc_data_width),
.bits_per_switch(mcenoc_bits_per_switch)
) nw (
.rst(reset),
.*
);
end else begin
assign dat_out[0] = dat_in[0];
assign clm_out[0] = clm_in[0];
assign act_out[0] = act_in[0];
assign cts_out[0] = cts_in[0];
assign err_out[0] = err_in[0];
end
endgenerate
wire [31:0] paddr;
wire [num_cores-1:0] psel;
wire penable;
wire pready;
wire [31:0] prdata;
wire pslverr;
genvar gi;
generate for (gi = 0; gi < num_cores; gi = gi + 1) begin:coregen
wire pcpi_valid, pcpi_wr, pcpi_wait, pcpi_ready;
wire [31:0] pcpi_insn, pcpi_rs1, pcpi_rd, irq, eoi;
assign irq[31:5] = 0;
assign irq[2:0] = 0;
if (gi == 0) begin
pcpi_uart uart(.rx(uart_rx), .tx(uart_tx), .irq(irq[3]), .eoi(eoi[3]), .*);
end
pcpi_mcenoc_ni #(
.NETWORK_NPORTS(num_cores),
.NETWORK_BITS_PER_SWITCH(1),
.NETWORK_DWIDTH(mcenoc_data_width)
) mcenoc_ni (
.data_in(dat_out[gi]),
.clm_in(clm_out[gi]),
.act_in(act_out[gi]),
.cts_out(cts_in[gi]),
.err_out(err_in[gi]),
.data_out(dat_in[gi]),
.clm_out(clm_in[gi]),
.act_out(act_in[gi]),
.cts_in(cts_out[gi]),
.err_in(err_out[gi]),
.irq(irq[4]),
.eoi(eoi[4]),
.pclk(),
.presetn(),
.pwdata(),
.pstrb(),
.pprot(),
.psel(psel[gi]),
.pwrite(),
.*
);
wire mem_ready = 1;
wire mem_valid, mem_write;
wire [3:0] mem_wstrb, mem_la_wstrb;
wire [31:0] mem_addr, mem_rdata, mem_wdata;
assign mem_wstrb = mem_la_wstrb & {4{mem_write}};
picorv32_mem mem (
.clk(clk),
.mem_wstrb(mem_wstrb),
.mem_addr(mem_addr),
.mem_wdata(mem_wdata),
.mem_rdata(mem_rdata)
);
picorv32 #(
.COMPRESSED_ISA(1),
.TWO_CYCLE_COMPARE(0),
.BARREL_SHIFTER(1),
.ENABLE_PCPI(1),
.ENABLE_MUL(1),
.ENABLE_IRQ(1),
.ENABLE_DIV(1),
`ifdef XILINX_SIMULATOR
.PROGADDR_RESET(32'h0000_0004),
`else
.PROGADDR_RESET(32'h0000_0004),
`endif
.PROGADDR_IRQ(32'h0000_0020),
.MASKED_IRQ(32'h0000_0000)
) cpu(
.clk(clk),
.resetn(resetn),
.mem_ready(mem_ready),
.mem_valid(mem_valid),
.mem_rdata(mem_rdata),
.mem_la_write(mem_write),
.mem_la_addr(mem_addr),
.mem_la_wstrb(mem_la_wstrb),
.mem_la_wdata(mem_wdata),
.pcpi_valid(pcpi_valid),
.pcpi_insn(pcpi_insn),
.pcpi_rs1(pcpi_rs1),
.pcpi_wr(pcpi_wr),
.pcpi_rd(pcpi_rd),
.pcpi_wait(pcpi_wait),
.pcpi_ready(pcpi_ready),
.irq(irq),
.eoi(eoi)
);
end
endgenerate
endmodule | module mcenoc_rv_system #(
parameter num_cores = 1,
parameter mcenoc_data_width=1,
parameter reset_time = 64,
parameter mcenoc_bits_per_switch=1
) (
input clk_in_p,
input clk_in_n,
input uart_rx,
output uart_tx,
output led,
output usbclk
); |
wire clk, locked;
reg resetn = 0;
integer rstcnt = 0;
wire reset;
assign reset = !resetn;
mcenoc_clk clkblk(.clk_in1_p(clk_in_p), .clk_in1_n(clk_in_n), .clk_out1(clk), .clk_out2(usbclk), .*);
reg [22:0] clkdiv = 0;
reg ledval = 0;
assign led = ledval;
always_ff @(posedge clk) begin
if (locked) begin
if (clkdiv == 0) ledval = ~ledval;
clkdiv = clkdiv + 1;
if (rstcnt == reset_time) begin
resetn = 1;
end else begin
rstcnt = rstcnt + 1;
resetn = 0;
end
end else rstcnt = 0;
end
wire [mcenoc_data_width-1:0]dat_in[num_cores-1:0];
wire act_in[num_cores-1:0];
wire clm_in[num_cores-1:0];
wire err_in[num_cores-1:0];
wire cts_in[num_cores-1:0];
wire [mcenoc_data_width-1:0]dat_out[num_cores-1:0];
wire cts_out[num_cores-1:0];
wire err_out[num_cores-1:0];
wire act_out[num_cores-1:0];
wire clm_out[num_cores-1:0];
generate
if (num_cores > 1) begin
uob_network #(
.n_ports(num_cores),
.data_width(mcenoc_data_width),
.bits_per_switch(mcenoc_bits_per_switch)
) nw (
.rst(reset),
.*
);
end else begin
assign dat_out[0] = dat_in[0];
assign clm_out[0] = clm_in[0];
assign act_out[0] = act_in[0];
assign cts_out[0] = cts_in[0];
assign err_out[0] = err_in[0];
end
endgenerate
wire [31:0] paddr;
wire [num_cores-1:0] psel;
wire penable;
wire pready;
wire [31:0] prdata;
wire pslverr;
genvar gi;
generate for (gi = 0; gi < num_cores; gi = gi + 1) begin:coregen
wire pcpi_valid, pcpi_wr, pcpi_wait, pcpi_ready;
wire [31:0] pcpi_insn, pcpi_rs1, pcpi_rd, irq, eoi;
assign irq[31:5] = 0;
assign irq[2:0] = 0;
if (gi == 0) begin
pcpi_uart uart(.rx(uart_rx), .tx(uart_tx), .irq(irq[3]), .eoi(eoi[3]), .*);
end
pcpi_mcenoc_ni #(
.NETWORK_NPORTS(num_cores),
.NETWORK_BITS_PER_SWITCH(1),
.NETWORK_DWIDTH(mcenoc_data_width)
) mcenoc_ni (
.data_in(dat_out[gi]),
.clm_in(clm_out[gi]),
.act_in(act_out[gi]),
.cts_out(cts_in[gi]),
.err_out(err_in[gi]),
.data_out(dat_in[gi]),
.clm_out(clm_in[gi]),
.act_out(act_in[gi]),
.cts_in(cts_out[gi]),
.err_in(err_out[gi]),
.irq(irq[4]),
.eoi(eoi[4]),
.pclk(),
.presetn(),
.pwdata(),
.pstrb(),
.pprot(),
.psel(psel[gi]),
.pwrite(),
.*
);
wire mem_ready = 1;
wire mem_valid, mem_write;
wire [3:0] mem_wstrb, mem_la_wstrb;
wire [31:0] mem_addr, mem_rdata, mem_wdata;
assign mem_wstrb = mem_la_wstrb & {4{mem_write}};
picorv32_mem mem (
.clk(clk),
.mem_wstrb(mem_wstrb),
.mem_addr(mem_addr),
.mem_wdata(mem_wdata),
.mem_rdata(mem_rdata)
);
picorv32 #(
.COMPRESSED_ISA(1),
.TWO_CYCLE_COMPARE(0),
.BARREL_SHIFTER(1),
.ENABLE_PCPI(1),
.ENABLE_MUL(1),
.ENABLE_IRQ(1),
.ENABLE_DIV(1),
`ifdef XILINX_SIMULATOR
.PROGADDR_RESET(32'h0000_0004),
`else
.PROGADDR_RESET(32'h0000_0004),
`endif
.PROGADDR_IRQ(32'h0000_0020),
.MASKED_IRQ(32'h0000_0000)
) cpu(
.clk(clk),
.resetn(resetn),
.mem_ready(mem_ready),
.mem_valid(mem_valid),
.mem_rdata(mem_rdata),
.mem_la_write(mem_write),
.mem_la_addr(mem_addr),
.mem_la_wstrb(mem_la_wstrb),
.mem_la_wdata(mem_wdata),
.pcpi_valid(pcpi_valid),
.pcpi_insn(pcpi_insn),
.pcpi_rs1(pcpi_rs1),
.pcpi_wr(pcpi_wr),
.pcpi_rd(pcpi_rd),
.pcpi_wait(pcpi_wait),
.pcpi_ready(pcpi_ready),
.irq(irq),
.eoi(eoi)
);
end
endgenerate
endmodule | 0 |
138,241 | data/full_repos/permissive/82812436/src/system/mem-decoder.sv | 82,812,436 | mem-decoder.sv | sv | 53 | 96 | [] | [] | [] | null | line:22: before: "interface" | null | 1: b"%Error: data/full_repos/permissive/82812436/src/system/mem-decoder.sv:43: Unsupported: Interfaced port on top level module\n mem_iface decif\n ^~~~~\n%Error: data/full_repos/permissive/82812436/src/system/mem-decoder.sv:43: Parent cell's interface is not found: 'mem_iface'\n mem_iface decif\n ^~~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/82812436/src/system/mem-decoder.sv:22: ../V3LinkDot.cpp:397: Module/etc never assigned a symbol entry?\ninterface mem_iface ();\n ^~~~~~~~~\n ... See the manual and https://verilator.org for more assistance.\n" | 302,063 | module | module mem_decoder #(parameter rom_base = 0, parameter rom_size = 1024,
parameter ram_base = 1024, parameter ram_size = 6144) (
mem_iface decif
);
assign decif.en_rom = (decif.addr >= rom_base && decif.addr < rom_base + rom_size);
assign decif.en_ram = (decif.addr >= ram_base && decif.addr < ram_base + ram_size);
assign decif.ready = decif.en_rom | decif.en_ram;
assign decif.cpu_rdata = decif.en_rom ? decif.rom_rdata : decif.ram_rdata;
assign decif.rom_addr = decif.addr[31:2];
endmodule | module mem_decoder #(parameter rom_base = 0, parameter rom_size = 1024,
parameter ram_base = 1024, parameter ram_size = 6144) (
mem_iface decif
); |
assign decif.en_rom = (decif.addr >= rom_base && decif.addr < rom_base + rom_size);
assign decif.en_ram = (decif.addr >= ram_base && decif.addr < ram_base + ram_size);
assign decif.ready = decif.en_rom | decif.en_ram;
assign decif.cpu_rdata = decif.en_rom ? decif.rom_rdata : decif.ram_rdata;
assign decif.rom_addr = decif.addr[31:2];
endmodule | 0 |
138,242 | data/full_repos/permissive/82812436/src/system/pcpi-uart.sv | 82,812,436 | pcpi-uart.sv | sv | 180 | 86 | [] | [] | [] | null | Syntax Error | null | 1: b"%Error: data/full_repos/permissive/82812436/src/system/pcpi-uart.sv:90: Cannot find file containing module: 'uart'\n uart #(.CLOCK_DIVIDE(CLOCK_DIVIDE)) uart (.rx(rx_2), .*);\n ^~~~\n ... Looked in:\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/uart\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/uart.v\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/uart.sv\n uart\n uart.v\n uart.sv\n obj_dir/uart\n obj_dir/uart.v\n obj_dir/uart.sv\n%Error: Exiting due to 1 error(s)\n" | 302,065 | module | module pcpi_uart(
input clk,
input resetn,
input pcpi_valid,
input [31:0] pcpi_insn,
input [31:0] pcpi_rs1,
output tri pcpi_wr,
output tri [31:0] pcpi_rd,
output pcpi_wait,
output tri pcpi_ready,
output irq,
input eoi,
input rx,
output tx
);
`ifdef XILINX_SIMULATOR
parameter CLOCK_DIVIDE = 4;
`else
parameter CLOCK_DIVIDE = 217;
`endif
typedef enum { IRQ_IDLE, IRQ_RAISED, IRQ_HANDLE } irq_state_t;
irq_state_t irq_state = IRQ_IDLE;
wire rst = ~resetn;
wire is_receiving, recv_error;
wire [7:0] rx_byte, tx_byte;
wire received, is_transmitting;
bit transmit = 0, write = 0, ready = 0, wt = 0, rx_latched, rx_unlatch = 0;
bit rx_irq_en = 0, tx_irq_en = 0, tx_wait = 1;
byte rx_data = 0;
logic [31:0] rdata = 0;
bit irq_r = 0;
wire [31:0] status = {28'b0, rx_irq_en, tx_irq_en, rx_latched, is_transmitting};
wire instr_trigger = (
pcpi_valid &&
pcpi_insn[6:0] == `PCPI_UART_CUSTOM0_OPCODE &&
pcpi_insn[31:25] >= `PCPI_UART_CUSTOM0_F7_START &&
pcpi_insn[31:25] <= `PCPI_UART_CUSTOM0_F7_END
);
assign pcpi_wr = (instr_trigger) ? write : 1'bZ;
assign pcpi_ready = (instr_trigger) ? ready : 1'bZ;
assign pcpi_rd = (instr_trigger) ? rdata : 32'bZ;
assign pcpi_wait = (instr_trigger) ? wt : 1'bZ;
assign tx_byte = pcpi_rs1[7:0];
assign irq = irq_r & !eoi;
reg rx_1, rx_2;
always_ff @(posedge clk) begin
rx_1 <= rx;
rx_2 <= rx_1;
end
uart #(.CLOCK_DIVIDE(CLOCK_DIVIDE)) uart (.rx(rx_2), .*);
always_ff @(posedge clk) begin
write <= 0;
ready <= 0;
rdata <= 0;
wt <= 0;
transmit <= 0;
rx_unlatch <= 0;
rx_irq_en <= rx_irq_en;
tx_irq_en <= tx_irq_en;
tx_wait <= tx_wait;
if (instr_trigger) begin
wt <= 1;
case (pcpi_insn[31:25])
default: begin
end
`PCPI_UART_CUSTOM0_F7_URC: begin
rdata <= status;
write <= 1;
ready <= 1;
wt <= 0;
end
`PCPI_UART_CUSTOM0_F7_UWC: begin
ready <= 1;
wt <= 0;
rx_irq_en <= pcpi_rs1[3];
tx_irq_en <= pcpi_rs1[2];
end
`PCPI_UART_CUSTOM0_F7_URX: begin
if (!received && rx_latched) begin
rdata <= {24'b0, rx_byte};
write <= 1;
ready <= 1;
wt <= 0;
rx_unlatch <= 1;
end
end
`PCPI_UART_CUSTOM0_F7_UTX: begin
if (!is_transmitting) begin
ready <= 1;
wt <= 0;
transmit <= 1;
end
end
endcase
end
end
always_ff @(posedge clk) begin
irq_r <= irq_r;
case (irq_state)
IRQ_IDLE: begin
if ((received && rx_irq_en) || (!is_transmitting && tx_irq_en)) begin
irq_r <= 1;
irq_state <= IRQ_RAISED;
end
end
IRQ_RAISED: begin
if (eoi) begin
irq_r <= 0;
irq_state <= IRQ_HANDLE;
end
end
IRQ_HANDLE: begin
if (!eoi) begin
irq_state <= IRQ_IDLE;
end
end
endcase
end
always_ff @(posedge clk) begin
rx_latched <= rx_latched;
if (received) begin
rx_data <= rx_byte;
rx_latched <= 1;
end else if (rx_unlatch) begin
rx_latched <= 0;
end
end
endmodule | module pcpi_uart(
input clk,
input resetn,
input pcpi_valid,
input [31:0] pcpi_insn,
input [31:0] pcpi_rs1,
output tri pcpi_wr,
output tri [31:0] pcpi_rd,
output pcpi_wait,
output tri pcpi_ready,
output irq,
input eoi,
input rx,
output tx
); |
`ifdef XILINX_SIMULATOR
parameter CLOCK_DIVIDE = 4;
`else
parameter CLOCK_DIVIDE = 217;
`endif
typedef enum { IRQ_IDLE, IRQ_RAISED, IRQ_HANDLE } irq_state_t;
irq_state_t irq_state = IRQ_IDLE;
wire rst = ~resetn;
wire is_receiving, recv_error;
wire [7:0] rx_byte, tx_byte;
wire received, is_transmitting;
bit transmit = 0, write = 0, ready = 0, wt = 0, rx_latched, rx_unlatch = 0;
bit rx_irq_en = 0, tx_irq_en = 0, tx_wait = 1;
byte rx_data = 0;
logic [31:0] rdata = 0;
bit irq_r = 0;
wire [31:0] status = {28'b0, rx_irq_en, tx_irq_en, rx_latched, is_transmitting};
wire instr_trigger = (
pcpi_valid &&
pcpi_insn[6:0] == `PCPI_UART_CUSTOM0_OPCODE &&
pcpi_insn[31:25] >= `PCPI_UART_CUSTOM0_F7_START &&
pcpi_insn[31:25] <= `PCPI_UART_CUSTOM0_F7_END
);
assign pcpi_wr = (instr_trigger) ? write : 1'bZ;
assign pcpi_ready = (instr_trigger) ? ready : 1'bZ;
assign pcpi_rd = (instr_trigger) ? rdata : 32'bZ;
assign pcpi_wait = (instr_trigger) ? wt : 1'bZ;
assign tx_byte = pcpi_rs1[7:0];
assign irq = irq_r & !eoi;
reg rx_1, rx_2;
always_ff @(posedge clk) begin
rx_1 <= rx;
rx_2 <= rx_1;
end
uart #(.CLOCK_DIVIDE(CLOCK_DIVIDE)) uart (.rx(rx_2), .*);
always_ff @(posedge clk) begin
write <= 0;
ready <= 0;
rdata <= 0;
wt <= 0;
transmit <= 0;
rx_unlatch <= 0;
rx_irq_en <= rx_irq_en;
tx_irq_en <= tx_irq_en;
tx_wait <= tx_wait;
if (instr_trigger) begin
wt <= 1;
case (pcpi_insn[31:25])
default: begin
end
`PCPI_UART_CUSTOM0_F7_URC: begin
rdata <= status;
write <= 1;
ready <= 1;
wt <= 0;
end
`PCPI_UART_CUSTOM0_F7_UWC: begin
ready <= 1;
wt <= 0;
rx_irq_en <= pcpi_rs1[3];
tx_irq_en <= pcpi_rs1[2];
end
`PCPI_UART_CUSTOM0_F7_URX: begin
if (!received && rx_latched) begin
rdata <= {24'b0, rx_byte};
write <= 1;
ready <= 1;
wt <= 0;
rx_unlatch <= 1;
end
end
`PCPI_UART_CUSTOM0_F7_UTX: begin
if (!is_transmitting) begin
ready <= 1;
wt <= 0;
transmit <= 1;
end
end
endcase
end
end
always_ff @(posedge clk) begin
irq_r <= irq_r;
case (irq_state)
IRQ_IDLE: begin
if ((received && rx_irq_en) || (!is_transmitting && tx_irq_en)) begin
irq_r <= 1;
irq_state <= IRQ_RAISED;
end
end
IRQ_RAISED: begin
if (eoi) begin
irq_r <= 0;
irq_state <= IRQ_HANDLE;
end
end
IRQ_HANDLE: begin
if (!eoi) begin
irq_state <= IRQ_IDLE;
end
end
endcase
end
always_ff @(posedge clk) begin
rx_latched <= rx_latched;
if (received) begin
rx_data <= rx_byte;
rx_latched <= 1;
end else if (rx_unlatch) begin
rx_latched <= 0;
end
end
endmodule | 0 |
138,243 | data/full_repos/permissive/82812436/src/system/picorv32_mem.sv | 82,812,436 | picorv32_mem.sv | sv | 69 | 83 | [] | [] | [] | [(22, 69)] | null | null | 1: b"%Error: data/full_repos/permissive/82812436/src/system/picorv32_mem.sv:55: Cannot find file containing module: 'picorv32_bram'\n picorv32_bram ram (\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/picorv32_bram\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/picorv32_bram.v\n data/full_repos/permissive/82812436/src/system,data/full_repos/permissive/82812436/picorv32_bram.sv\n picorv32_bram\n picorv32_bram.v\n picorv32_bram.sv\n obj_dir/picorv32_bram\n obj_dir/picorv32_bram.v\n obj_dir/picorv32_bram.sv\n%Error: data/full_repos/permissive/82812436/src/system/picorv32_mem.sv:63: Cannot find file containing module: 'picorv32_brom'\n picorv32_brom rom (\n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 302,066 | module | module picorv32_mem #(
parameter ROM_BASE=0,
parameter ROM_SIZE=2048,
parameter RAM_BASE=32'h0000_8000,
parameter RAM_SIZE=32'h0000_8000
)(
input clk,
input [3:0] mem_wstrb,
input [31:0] mem_addr,
input [31:0] mem_wdata,
output [31:0] mem_rdata
);
wire sel_ram, sel_rom;
wire [3:0] ram_wstrb;
wire [31:0] ram_addr, ram_rdata, ram_wdata,
rom_addr, rom_rdata;
assign sel_rom = mem_addr >= ROM_BASE && mem_addr < ROM_BASE + ROM_SIZE;
assign sel_ram = mem_addr >= RAM_BASE && mem_addr < RAM_BASE + RAM_SIZE;
assign ram_wstrb = sel_ram ? mem_wstrb : 0;
assign ram_addr = sel_ram ? ((mem_addr - RAM_BASE) >> 2) : 0;
assign ram_wdata = sel_ram ? mem_wdata : 0;
assign rom_addr = sel_rom ? ((mem_addr - ROM_BASE) >> 2) : 0;
assign mem_rdata = sel_ram ? ram_rdata : sel_rom ? rom_rdata : 0;
picorv32_bram ram (
.clka(clk),
.wea(ram_wstrb),
.addra(ram_addr),
.dina(ram_wdata),
.douta(ram_rdata)
);
picorv32_brom rom (
.clka(clk),
.addra(rom_addr),
.douta(rom_rdata)
);
endmodule | module picorv32_mem #(
parameter ROM_BASE=0,
parameter ROM_SIZE=2048,
parameter RAM_BASE=32'h0000_8000,
parameter RAM_SIZE=32'h0000_8000
)(
input clk,
input [3:0] mem_wstrb,
input [31:0] mem_addr,
input [31:0] mem_wdata,
output [31:0] mem_rdata
); |
wire sel_ram, sel_rom;
wire [3:0] ram_wstrb;
wire [31:0] ram_addr, ram_rdata, ram_wdata,
rom_addr, rom_rdata;
assign sel_rom = mem_addr >= ROM_BASE && mem_addr < ROM_BASE + ROM_SIZE;
assign sel_ram = mem_addr >= RAM_BASE && mem_addr < RAM_BASE + RAM_SIZE;
assign ram_wstrb = sel_ram ? mem_wstrb : 0;
assign ram_addr = sel_ram ? ((mem_addr - RAM_BASE) >> 2) : 0;
assign ram_wdata = sel_ram ? mem_wdata : 0;
assign rom_addr = sel_rom ? ((mem_addr - ROM_BASE) >> 2) : 0;
assign mem_rdata = sel_ram ? ram_rdata : sel_rom ? rom_rdata : 0;
picorv32_bram ram (
.clka(clk),
.wea(ram_wstrb),
.addra(ram_addr),
.dina(ram_wdata),
.douta(ram_rdata)
);
picorv32_brom rom (
.clka(clk),
.addra(rom_addr),
.douta(rom_rdata)
);
endmodule | 0 |
138,244 | data/full_repos/permissive/82849654/src/baudgen_tx.v | 82,849,654 | baudgen_tx.v | v | 67 | 91 | [] | ['gpl license'] | [] | null | line:54: before: "integer" | null | 1: b'%Error: data/full_repos/permissive/82849654/src/baudgen_tx.v:13: Cannot find include file: src/baudgen.vh\n`include "src/baudgen.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82849654/src,data/full_repos/permissive/82849654/src/baudgen.vh\n data/full_repos/permissive/82849654/src,data/full_repos/permissive/82849654/src/baudgen.vh.v\n data/full_repos/permissive/82849654/src,data/full_repos/permissive/82849654/src/baudgen.vh.sv\n src/baudgen.vh\n src/baudgen.vh.v\n src/baudgen.vh.sv\n obj_dir/src/baudgen.vh\n obj_dir/src/baudgen.vh.v\n obj_dir/src/baudgen.vh.sv\n%Error: data/full_repos/permissive/82849654/src/baudgen_tx.v:41: Cannot find include file: src/functions.vh\n`include "src/functions.vh" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82849654/src/baudgen_tx.v:32: Define or directive not defined: \'`B9600\'\n parameter BAUDRATE = `B9600 \n ^~~~~~\n%Error: data/full_repos/permissive/82849654/src/baudgen_tx.v:33: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n)(\n^\n%Error: data/full_repos/permissive/82849654/src/baudgen_tx.v:35: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire clk, \n ^~~~~\n%Error: data/full_repos/permissive/82849654/src/baudgen_tx.v:36: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire clk_ena, \n ^~~~~\n%Error: data/full_repos/permissive/82849654/src/baudgen_tx.v:37: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire clk_out \n ^~~~~~\n%Error: data/full_repos/permissive/82849654/src/baudgen_tx.v:48: syntax error, unexpected always\nalways @(posedge clk)\n^~~~~~\n%Error: Exiting due to 8 error(s)\n' | 302,072 | module | module baudgen_tx #(
parameter BAUDRATE = `B9600
)(
input wire rstn,
input wire clk,
input wire clk_ena,
output wire clk_out
);
`include "src/functions.vh"
localparam N = clog2(BAUDRATE);
reg [N-1:0] divcounter = 0;
always @(posedge clk)
if (!rstn)
divcounter <= 0;
else if (clk_ena)
divcounter <= (divcounter == BAUDRATE - 1) ? 0 : divcounter + 1;
else
divcounter <= BAUDRATE - 1;
assign clk_out = (divcounter == 0) ? clk_ena : 0;
endmodule | module baudgen_tx #(
parameter BAUDRATE = `B9600
)(
input wire rstn,
input wire clk,
input wire clk_ena,
output wire clk_out
); |
`include "src/functions.vh"
localparam N = clog2(BAUDRATE);
reg [N-1:0] divcounter = 0;
always @(posedge clk)
if (!rstn)
divcounter <= 0;
else if (clk_ena)
divcounter <= (divcounter == BAUDRATE - 1) ? 0 : divcounter + 1;
else
divcounter <= BAUDRATE - 1;
assign clk_out = (divcounter == 0) ? clk_ena : 0;
endmodule | 0 |
138,245 | data/full_repos/permissive/82849654/src/cmd_parser.v | 82,849,654 | cmd_parser.v | v | 642 | 97 | [] | [] | [] | null | line:36: before: "integer" | null | 1: b'%Error: data/full_repos/permissive/82849654/src/cmd_parser.v:34: Cannot find include file: src/functions.vh\n`include "src/functions.vh" \n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82849654/src,data/full_repos/permissive/82849654/src/functions.vh\n data/full_repos/permissive/82849654/src,data/full_repos/permissive/82849654/src/functions.vh.v\n data/full_repos/permissive/82849654/src,data/full_repos/permissive/82849654/src/functions.vh.sv\n src/functions.vh\n src/functions.vh.v\n src/functions.vh.sv\n obj_dir/src/functions.vh\n obj_dir/src/functions.vh.v\n obj_dir/src/functions.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 302,073 | module | module cmd_parser #(
parameter SHOW_INIT_MSG = 1,
parameter NPIS = 14,
parameter NPOS = 11
)(
input wire clk,
input wire rstn,
output wire tx_start_o,
output wire [7:0] tx_data_o,
input wire tx_ready_i,
input wire [7:0] rx_data,
input wire new_rx_data,
output reg [7:0] leds,
output wire [7:0] sseg,
output wire [3:0] an,
output reg [1:NPIS] part_pis_o,
input wire [1:NPOS] part_pos_i
);
wire clk_i;
reg scan_i, scan_i_nxt;
reg reset_i;
reg test_se_i;
reg test_tm_i;
reg scan_o;
`include "src/functions.vh"
localparam NPIS_WIDTH = clog2(NPIS);
localparam NPOS_WIDTH = clog2(NPOS);
reg [NPIS_WIDTH:0] cont_pis, cont_pis_nxt;
reg [NPOS_WIDTH:0] cont_pos, cont_pos_nxt;
reg [1:NPOS] part_pos;
reg [1:NPIS] part_pis;
reg csoc_clk;
reg clk_en, clk_en_nxt;
reg csoc_rstn, csoc_rstn_nxt;
reg csoc_test_se, csoc_test_se_nxt;
reg csoc_test_tm, csoc_test_tm_nxt;
reg csoc_uart_read, csoc_uart_read_nxt;
reg [7:0] csoc_data_o_reg, csoc_data_o_nxt;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
part_pis_o <= 0;
part_pos <= 0;
scan_i <= 0;
reset_i <= 0;
test_se_i <= 0;
test_tm_i <= 0;
scan_o <= 0;
end
else begin
part_pis_o[01] <= csoc_clk;
part_pis_o[09] <= scan_i;
part_pis_o[10] <= csoc_rstn;
part_pis_o[11] <= csoc_test_se;
part_pis_o[12] <= csoc_test_tm;
part_pos <= part_pos_i;
scan_o <= part_pos_i[9];
scan_i <= scan_i_nxt;
end
end
localparam VERSION_SIZE = 4;
reg [7:0] version [0:VERSION_SIZE-1];
initial begin
$readmemh("version.txt", version);
end
sevenseg ss0 (
.clk(clk),
.rstn(rstn),
.display_0(version[0]),
.display_1(version[1]),
.display_2(version[2]),
.display_3(version[3]),
.decplace(2'b10),
.seg(sseg),
.an(an)
);
always @(posedge clk or negedge rstn) begin
if (!rstn)
leds <= 0;
else
leds <= part_pos_i[2:9];
end
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
csoc_clk <= 0;
end
else
if (clk_en)
csoc_clk <= ~csoc_clk;
end
assign clk_i = csoc_clk;
reg [4:0] state, state_nxt;
reg tx_start, tx_start_nxt;
reg run_done, run_done_nxt;
localparam
RESET = 0,
AVOID_MSG = 18,
INITIAL_MESSAGE = 1,
S1 = 2,
S2 = 3,
S3 = 4,
WAITING_COMMAND = 5,
SET_DUT_STATE = 6,
SA1 = 26,
GET_DUT_STATE = 7,
SB5 = 27,
SB51 = 30,
SB6 = 28,
SXX = 31,
EXECUTE_DUT = 8,
SET_INPUTS_STATE = 9,
GET_OUTPUTS_STATE = 10,
S4 = 11,
FREE_RUN_DUT = 12,
S5 = 13,
S11 = 14,
S21 = 15,
S31 = 16,
S111 = 17,
S1111 = 19,
SX5 = 20,
SX11 = 21,
SX21 = 22,
SX31 = 23,
SX111 = 24,
SX1111 = 25,
PAUSE_DUT = 29;
localparam
RESET_CMD = "r",
SET_STATE_CMD = "s",
GET_STATE_CMD = "g",
SET_INPUTS_CMD = "i",
GET_OUTPUTS_CMD = "o",
EXECUTE_CMD = "e",
FREE_RUN_CMD = "f",
PAUSE_CMD = "p";
assign tx_start_o = tx_start;
localparam MSG_SIZE = 20;
reg [7:0] mgs_mem [0:MSG_SIZE-1];
reg [7:0] msg_data, msg_data_nxt;
reg [5:0] msg_addr, msg_addr_nxt;
initial begin
$readmemh("initial_message.txt", mgs_mem);
end
reg [7:0] tx_data, tx_data_nxt;
reg [15:0] clk_count, clk_count_nxt;
reg [6:0] col_break, col_break_nxt;
reg [15:0] nclks, nclks_nxt;
reg low_byte, low_byte_nxt;
assign tx_data_o = tx_data;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
state <= RESET;
tx_start <= 0;
tx_data <= 0;
clk_count <= 0;
col_break <= 0;
msg_data <= 0;
msg_addr <= 0;
run_done <= 0;
clk_en <= 0;
nclks <= 0;
low_byte <= 0;
csoc_rstn <= 0;
csoc_test_se <= 1;
csoc_test_tm <= 1;
csoc_uart_read <= 0;
csoc_data_o_reg <= 0;
cont_pos <= 0;
cont_pis <= 0;
end
else begin
state <= state_nxt;
tx_start <= tx_start_nxt;
clk_count <= clk_count_nxt;
col_break <= col_break_nxt;
msg_data <= mgs_mem[msg_addr];
msg_addr <= msg_addr_nxt;
tx_data <= tx_data_nxt;
run_done <= run_done_nxt;
clk_en <= clk_en_nxt;
nclks <= nclks_nxt;
low_byte <= low_byte_nxt;
csoc_rstn <= csoc_rstn_nxt;
csoc_test_se <= csoc_test_se_nxt;
csoc_test_tm <= csoc_test_tm_nxt;
csoc_uart_read <= csoc_uart_read_nxt;
csoc_data_o_reg <= csoc_data_o_nxt;
cont_pos <= cont_pos_nxt;
cont_pis <= cont_pis_nxt;
end
end
always @(*) begin
state_nxt = state;
tx_start_nxt = tx_start;
tx_data_nxt = tx_data;
clk_count_nxt = clk_count;
col_break_nxt = col_break;
msg_addr_nxt = msg_addr;
run_done_nxt = run_done;
clk_en_nxt = clk_en;
nclks_nxt = nclks;
low_byte_nxt = low_byte;
csoc_rstn_nxt = csoc_rstn;
csoc_test_se_nxt = csoc_test_se;
csoc_test_tm_nxt = csoc_test_tm;
csoc_uart_read_nxt = csoc_uart_read;
csoc_data_o_nxt = csoc_data_o_reg;
cont_pos_nxt = cont_pos;
cont_pis_nxt = cont_pis;
scan_i_nxt = scan_i;
case (state)
RESET: begin
csoc_rstn_nxt = 1;
csoc_test_se_nxt = 1;
csoc_test_tm_nxt = 1;
csoc_uart_read_nxt = 0;
csoc_data_o_nxt = 0;
msg_addr_nxt = 0;
if (SHOW_INIT_MSG)
state_nxt = INITIAL_MESSAGE;
else
state_nxt = AVOID_MSG;
end
AVOID_MSG: begin
state_nxt = WAITING_COMMAND;
end
INITIAL_MESSAGE: begin
if (tx_ready_i) begin
tx_start_nxt = 1;
state_nxt = S1;
end
end
S1: begin
if (!tx_ready_i) begin
tx_start_nxt = 0;
state_nxt = S2;
end
end
S2: begin
if (tx_ready_i) begin
msg_addr_nxt = msg_addr + 1;
if (msg_addr <= MSG_SIZE) begin
state_nxt = S3;
end
else begin
msg_addr_nxt = 0;
state_nxt = WAITING_COMMAND;
end
end
end
S3: begin
if (msg_addr <= MSG_SIZE) begin
tx_data_nxt = msg_data;
end
else begin
tx_data_nxt = "\n";
end
state_nxt = INITIAL_MESSAGE;
end
WAITING_COMMAND: begin
csoc_test_se_nxt = 0;
csoc_test_tm_nxt = 0;
csoc_rstn_nxt = 1;
nclks_nxt = 0;
clk_en_nxt = 0;
clk_count_nxt = 0;
if(new_rx_data) begin
case (rx_data)
RESET_CMD: state_nxt = RESET;
EXECUTE_CMD: state_nxt = EXECUTE_DUT;
FREE_RUN_CMD: state_nxt = FREE_RUN_DUT;
PAUSE_CMD: state_nxt = PAUSE_DUT;
SET_STATE_CMD: state_nxt = SET_DUT_STATE;
GET_STATE_CMD: state_nxt = GET_DUT_STATE;
SET_INPUTS_CMD: state_nxt = SET_INPUTS_STATE;
GET_OUTPUTS_CMD: state_nxt = GET_OUTPUTS_STATE;
endcase
end
end
SET_DUT_STATE: begin
csoc_test_se_nxt = 1;
csoc_test_tm_nxt = 1;
if(new_rx_data) begin
if (low_byte) begin
nclks_nxt[7:0] = rx_data;
low_byte_nxt = 0;
state_nxt = SB5;
clk_count_nxt = 0;
clk_en_nxt = 0;
end
else begin
nclks_nxt[15:8] = rx_data;
low_byte_nxt = 1;
end
end
end
SB5: begin
if (clk_count >= nclks) begin
scan_i_nxt = 0;
state_nxt = WAITING_COMMAND;
end
else
if(new_rx_data) begin
clk_count_nxt = clk_count + 1;
case (rx_data)
"0": scan_i_nxt = 0;
"1": scan_i_nxt = 1;
endcase
state_nxt = SB51;
end
end
SB51: begin
clk_en_nxt = 1;
if (csoc_clk) begin
clk_en_nxt = 0;
state_nxt = SB6;
end
end
SB6: begin
state_nxt = SXX;
end
SXX: begin
state_nxt = SB5;
end
GET_DUT_STATE: begin
csoc_test_se_nxt = 1;
csoc_test_tm_nxt = 1;
clk_en_nxt = 0;
clk_count_nxt = 0;
if(new_rx_data) begin
if (low_byte) begin
nclks_nxt[7:0] = rx_data;
low_byte_nxt = 0;
state_nxt = S31;
end
else begin
nclks_nxt[15:8] = rx_data;
low_byte_nxt = 1;
end
end
end
S31: begin
clk_en_nxt = 1;
if (csoc_clk) begin
clk_en_nxt = 0;
state_nxt = S5;
end
end
S5: begin
if (tx_ready_i) begin
clk_en_nxt = 1;
if (csoc_clk) begin
clk_en_nxt = 0;
clk_count_nxt = clk_count + 1;
state_nxt = S21;
end
end
end
S21: begin
case (scan_o)
0: tx_data_nxt = "0";
1: tx_data_nxt = "1";
endcase
state_nxt = S1111;
end
S1111: begin
tx_start_nxt = 1;
if (!tx_ready_i) begin
tx_start_nxt = 0;
state_nxt = S11;
end
end
S11: begin
if (clk_count > nclks) begin
clk_count_nxt = 0;
state_nxt = WAITING_COMMAND;
end
else begin
state_nxt = S5;
end
end
EXECUTE_DUT: begin
csoc_test_se_nxt = 0;
csoc_test_tm_nxt = 0;
if(new_rx_data) begin
if (low_byte) begin
nclks_nxt[7:0] = rx_data;
low_byte_nxt = 0;
state_nxt = S4;
end
else begin
nclks_nxt[15:8] = rx_data;
low_byte_nxt = 1;
end
end
end
S4: begin
clk_en_nxt = 1;
if (csoc_clk)
if (clk_count == nclks-1) begin
clk_en_nxt = 0;
state_nxt = WAITING_COMMAND;
end
else
clk_count_nxt = clk_count + 1;
end
FREE_RUN_DUT: begin
clk_en_nxt = 1;
if (csoc_clk)
clk_count_nxt = clk_count + 1;
if(new_rx_data)
if (rx_data == PAUSE_CMD)
state_nxt = WAITING_COMMAND;
end
PAUSE_DUT: begin
clk_en_nxt = 0;
state_nxt = WAITING_COMMAND;
end
GET_OUTPUTS_STATE: begin
clk_en_nxt = 0;
csoc_test_se_nxt = 1;
csoc_test_tm_nxt = 1;
if(new_rx_data) begin
if (low_byte) begin
nclks_nxt[7:0] = rx_data;
low_byte_nxt = 0;
state_nxt = SX5;
end
else begin
nclks_nxt[15:8] = rx_data;
low_byte_nxt = 1;
end
end
cont_pos_nxt = 1;
end
SX5: begin
if (tx_ready_i) begin
if (part_pos[cont_pos])
tx_data_nxt = "1";
else
tx_data_nxt = "0";
cont_pos_nxt = cont_pos + 1;
state_nxt = SX1111;
end
end
SX1111: begin
tx_start_nxt = 1;
state_nxt = SX111;
end
SX111: begin
tx_start_nxt = 0;
state_nxt = SX11;
end
SX11: begin
if (!tx_ready_i) begin
tx_start_nxt = 0;
state_nxt = SX21;
end
end
SX21: begin
if (tx_ready_i)
if (cont_pos > nclks) begin
state_nxt = WAITING_COMMAND;
end
else
state_nxt = SX31;
end
SX31: begin
if (part_pos[cont_pos])
tx_data_nxt = "1";
else
tx_data_nxt = "0";
state_nxt = SX5;
end
SET_INPUTS_STATE: begin
csoc_test_se_nxt = 1;
csoc_test_tm_nxt = 1;
if(new_rx_data) begin
if (low_byte) begin
nclks_nxt[7:0] = rx_data;
low_byte_nxt = 0;
state_nxt = SA1;
end
else begin
nclks_nxt[15:8] = rx_data;
low_byte_nxt = 1;
end
end
cont_pis_nxt = 1;
end
SA1: begin
clk_en_nxt = 1;
if(new_rx_data) begin
case (rx_data)
"0" : part_pis[cont_pis] = rx_data;
"1" : part_pis[cont_pis] = rx_data;
endcase
clk_en_nxt = 1;
cont_pis_nxt = cont_pis + 1;
if (cont_pis >= nclks) begin
clk_en_nxt = 0;
state_nxt = WAITING_COMMAND;
if (!csoc_clk)
clk_en_nxt = 1;
end
end
end
endcase
end
endmodule | module cmd_parser #(
parameter SHOW_INIT_MSG = 1,
parameter NPIS = 14,
parameter NPOS = 11
)(
input wire clk,
input wire rstn,
output wire tx_start_o,
output wire [7:0] tx_data_o,
input wire tx_ready_i,
input wire [7:0] rx_data,
input wire new_rx_data,
output reg [7:0] leds,
output wire [7:0] sseg,
output wire [3:0] an,
output reg [1:NPIS] part_pis_o,
input wire [1:NPOS] part_pos_i
); |
wire clk_i;
reg scan_i, scan_i_nxt;
reg reset_i;
reg test_se_i;
reg test_tm_i;
reg scan_o;
`include "src/functions.vh"
localparam NPIS_WIDTH = clog2(NPIS);
localparam NPOS_WIDTH = clog2(NPOS);
reg [NPIS_WIDTH:0] cont_pis, cont_pis_nxt;
reg [NPOS_WIDTH:0] cont_pos, cont_pos_nxt;
reg [1:NPOS] part_pos;
reg [1:NPIS] part_pis;
reg csoc_clk;
reg clk_en, clk_en_nxt;
reg csoc_rstn, csoc_rstn_nxt;
reg csoc_test_se, csoc_test_se_nxt;
reg csoc_test_tm, csoc_test_tm_nxt;
reg csoc_uart_read, csoc_uart_read_nxt;
reg [7:0] csoc_data_o_reg, csoc_data_o_nxt;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
part_pis_o <= 0;
part_pos <= 0;
scan_i <= 0;
reset_i <= 0;
test_se_i <= 0;
test_tm_i <= 0;
scan_o <= 0;
end
else begin
part_pis_o[01] <= csoc_clk;
part_pis_o[09] <= scan_i;
part_pis_o[10] <= csoc_rstn;
part_pis_o[11] <= csoc_test_se;
part_pis_o[12] <= csoc_test_tm;
part_pos <= part_pos_i;
scan_o <= part_pos_i[9];
scan_i <= scan_i_nxt;
end
end
localparam VERSION_SIZE = 4;
reg [7:0] version [0:VERSION_SIZE-1];
initial begin
$readmemh("version.txt", version);
end
sevenseg ss0 (
.clk(clk),
.rstn(rstn),
.display_0(version[0]),
.display_1(version[1]),
.display_2(version[2]),
.display_3(version[3]),
.decplace(2'b10),
.seg(sseg),
.an(an)
);
always @(posedge clk or negedge rstn) begin
if (!rstn)
leds <= 0;
else
leds <= part_pos_i[2:9];
end
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
csoc_clk <= 0;
end
else
if (clk_en)
csoc_clk <= ~csoc_clk;
end
assign clk_i = csoc_clk;
reg [4:0] state, state_nxt;
reg tx_start, tx_start_nxt;
reg run_done, run_done_nxt;
localparam
RESET = 0,
AVOID_MSG = 18,
INITIAL_MESSAGE = 1,
S1 = 2,
S2 = 3,
S3 = 4,
WAITING_COMMAND = 5,
SET_DUT_STATE = 6,
SA1 = 26,
GET_DUT_STATE = 7,
SB5 = 27,
SB51 = 30,
SB6 = 28,
SXX = 31,
EXECUTE_DUT = 8,
SET_INPUTS_STATE = 9,
GET_OUTPUTS_STATE = 10,
S4 = 11,
FREE_RUN_DUT = 12,
S5 = 13,
S11 = 14,
S21 = 15,
S31 = 16,
S111 = 17,
S1111 = 19,
SX5 = 20,
SX11 = 21,
SX21 = 22,
SX31 = 23,
SX111 = 24,
SX1111 = 25,
PAUSE_DUT = 29;
localparam
RESET_CMD = "r",
SET_STATE_CMD = "s",
GET_STATE_CMD = "g",
SET_INPUTS_CMD = "i",
GET_OUTPUTS_CMD = "o",
EXECUTE_CMD = "e",
FREE_RUN_CMD = "f",
PAUSE_CMD = "p";
assign tx_start_o = tx_start;
localparam MSG_SIZE = 20;
reg [7:0] mgs_mem [0:MSG_SIZE-1];
reg [7:0] msg_data, msg_data_nxt;
reg [5:0] msg_addr, msg_addr_nxt;
initial begin
$readmemh("initial_message.txt", mgs_mem);
end
reg [7:0] tx_data, tx_data_nxt;
reg [15:0] clk_count, clk_count_nxt;
reg [6:0] col_break, col_break_nxt;
reg [15:0] nclks, nclks_nxt;
reg low_byte, low_byte_nxt;
assign tx_data_o = tx_data;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
state <= RESET;
tx_start <= 0;
tx_data <= 0;
clk_count <= 0;
col_break <= 0;
msg_data <= 0;
msg_addr <= 0;
run_done <= 0;
clk_en <= 0;
nclks <= 0;
low_byte <= 0;
csoc_rstn <= 0;
csoc_test_se <= 1;
csoc_test_tm <= 1;
csoc_uart_read <= 0;
csoc_data_o_reg <= 0;
cont_pos <= 0;
cont_pis <= 0;
end
else begin
state <= state_nxt;
tx_start <= tx_start_nxt;
clk_count <= clk_count_nxt;
col_break <= col_break_nxt;
msg_data <= mgs_mem[msg_addr];
msg_addr <= msg_addr_nxt;
tx_data <= tx_data_nxt;
run_done <= run_done_nxt;
clk_en <= clk_en_nxt;
nclks <= nclks_nxt;
low_byte <= low_byte_nxt;
csoc_rstn <= csoc_rstn_nxt;
csoc_test_se <= csoc_test_se_nxt;
csoc_test_tm <= csoc_test_tm_nxt;
csoc_uart_read <= csoc_uart_read_nxt;
csoc_data_o_reg <= csoc_data_o_nxt;
cont_pos <= cont_pos_nxt;
cont_pis <= cont_pis_nxt;
end
end
always @(*) begin
state_nxt = state;
tx_start_nxt = tx_start;
tx_data_nxt = tx_data;
clk_count_nxt = clk_count;
col_break_nxt = col_break;
msg_addr_nxt = msg_addr;
run_done_nxt = run_done;
clk_en_nxt = clk_en;
nclks_nxt = nclks;
low_byte_nxt = low_byte;
csoc_rstn_nxt = csoc_rstn;
csoc_test_se_nxt = csoc_test_se;
csoc_test_tm_nxt = csoc_test_tm;
csoc_uart_read_nxt = csoc_uart_read;
csoc_data_o_nxt = csoc_data_o_reg;
cont_pos_nxt = cont_pos;
cont_pis_nxt = cont_pis;
scan_i_nxt = scan_i;
case (state)
RESET: begin
csoc_rstn_nxt = 1;
csoc_test_se_nxt = 1;
csoc_test_tm_nxt = 1;
csoc_uart_read_nxt = 0;
csoc_data_o_nxt = 0;
msg_addr_nxt = 0;
if (SHOW_INIT_MSG)
state_nxt = INITIAL_MESSAGE;
else
state_nxt = AVOID_MSG;
end
AVOID_MSG: begin
state_nxt = WAITING_COMMAND;
end
INITIAL_MESSAGE: begin
if (tx_ready_i) begin
tx_start_nxt = 1;
state_nxt = S1;
end
end
S1: begin
if (!tx_ready_i) begin
tx_start_nxt = 0;
state_nxt = S2;
end
end
S2: begin
if (tx_ready_i) begin
msg_addr_nxt = msg_addr + 1;
if (msg_addr <= MSG_SIZE) begin
state_nxt = S3;
end
else begin
msg_addr_nxt = 0;
state_nxt = WAITING_COMMAND;
end
end
end
S3: begin
if (msg_addr <= MSG_SIZE) begin
tx_data_nxt = msg_data;
end
else begin
tx_data_nxt = "\n";
end
state_nxt = INITIAL_MESSAGE;
end
WAITING_COMMAND: begin
csoc_test_se_nxt = 0;
csoc_test_tm_nxt = 0;
csoc_rstn_nxt = 1;
nclks_nxt = 0;
clk_en_nxt = 0;
clk_count_nxt = 0;
if(new_rx_data) begin
case (rx_data)
RESET_CMD: state_nxt = RESET;
EXECUTE_CMD: state_nxt = EXECUTE_DUT;
FREE_RUN_CMD: state_nxt = FREE_RUN_DUT;
PAUSE_CMD: state_nxt = PAUSE_DUT;
SET_STATE_CMD: state_nxt = SET_DUT_STATE;
GET_STATE_CMD: state_nxt = GET_DUT_STATE;
SET_INPUTS_CMD: state_nxt = SET_INPUTS_STATE;
GET_OUTPUTS_CMD: state_nxt = GET_OUTPUTS_STATE;
endcase
end
end
SET_DUT_STATE: begin
csoc_test_se_nxt = 1;
csoc_test_tm_nxt = 1;
if(new_rx_data) begin
if (low_byte) begin
nclks_nxt[7:0] = rx_data;
low_byte_nxt = 0;
state_nxt = SB5;
clk_count_nxt = 0;
clk_en_nxt = 0;
end
else begin
nclks_nxt[15:8] = rx_data;
low_byte_nxt = 1;
end
end
end
SB5: begin
if (clk_count >= nclks) begin
scan_i_nxt = 0;
state_nxt = WAITING_COMMAND;
end
else
if(new_rx_data) begin
clk_count_nxt = clk_count + 1;
case (rx_data)
"0": scan_i_nxt = 0;
"1": scan_i_nxt = 1;
endcase
state_nxt = SB51;
end
end
SB51: begin
clk_en_nxt = 1;
if (csoc_clk) begin
clk_en_nxt = 0;
state_nxt = SB6;
end
end
SB6: begin
state_nxt = SXX;
end
SXX: begin
state_nxt = SB5;
end
GET_DUT_STATE: begin
csoc_test_se_nxt = 1;
csoc_test_tm_nxt = 1;
clk_en_nxt = 0;
clk_count_nxt = 0;
if(new_rx_data) begin
if (low_byte) begin
nclks_nxt[7:0] = rx_data;
low_byte_nxt = 0;
state_nxt = S31;
end
else begin
nclks_nxt[15:8] = rx_data;
low_byte_nxt = 1;
end
end
end
S31: begin
clk_en_nxt = 1;
if (csoc_clk) begin
clk_en_nxt = 0;
state_nxt = S5;
end
end
S5: begin
if (tx_ready_i) begin
clk_en_nxt = 1;
if (csoc_clk) begin
clk_en_nxt = 0;
clk_count_nxt = clk_count + 1;
state_nxt = S21;
end
end
end
S21: begin
case (scan_o)
0: tx_data_nxt = "0";
1: tx_data_nxt = "1";
endcase
state_nxt = S1111;
end
S1111: begin
tx_start_nxt = 1;
if (!tx_ready_i) begin
tx_start_nxt = 0;
state_nxt = S11;
end
end
S11: begin
if (clk_count > nclks) begin
clk_count_nxt = 0;
state_nxt = WAITING_COMMAND;
end
else begin
state_nxt = S5;
end
end
EXECUTE_DUT: begin
csoc_test_se_nxt = 0;
csoc_test_tm_nxt = 0;
if(new_rx_data) begin
if (low_byte) begin
nclks_nxt[7:0] = rx_data;
low_byte_nxt = 0;
state_nxt = S4;
end
else begin
nclks_nxt[15:8] = rx_data;
low_byte_nxt = 1;
end
end
end
S4: begin
clk_en_nxt = 1;
if (csoc_clk)
if (clk_count == nclks-1) begin
clk_en_nxt = 0;
state_nxt = WAITING_COMMAND;
end
else
clk_count_nxt = clk_count + 1;
end
FREE_RUN_DUT: begin
clk_en_nxt = 1;
if (csoc_clk)
clk_count_nxt = clk_count + 1;
if(new_rx_data)
if (rx_data == PAUSE_CMD)
state_nxt = WAITING_COMMAND;
end
PAUSE_DUT: begin
clk_en_nxt = 0;
state_nxt = WAITING_COMMAND;
end
GET_OUTPUTS_STATE: begin
clk_en_nxt = 0;
csoc_test_se_nxt = 1;
csoc_test_tm_nxt = 1;
if(new_rx_data) begin
if (low_byte) begin
nclks_nxt[7:0] = rx_data;
low_byte_nxt = 0;
state_nxt = SX5;
end
else begin
nclks_nxt[15:8] = rx_data;
low_byte_nxt = 1;
end
end
cont_pos_nxt = 1;
end
SX5: begin
if (tx_ready_i) begin
if (part_pos[cont_pos])
tx_data_nxt = "1";
else
tx_data_nxt = "0";
cont_pos_nxt = cont_pos + 1;
state_nxt = SX1111;
end
end
SX1111: begin
tx_start_nxt = 1;
state_nxt = SX111;
end
SX111: begin
tx_start_nxt = 0;
state_nxt = SX11;
end
SX11: begin
if (!tx_ready_i) begin
tx_start_nxt = 0;
state_nxt = SX21;
end
end
SX21: begin
if (tx_ready_i)
if (cont_pos > nclks) begin
state_nxt = WAITING_COMMAND;
end
else
state_nxt = SX31;
end
SX31: begin
if (part_pos[cont_pos])
tx_data_nxt = "1";
else
tx_data_nxt = "0";
state_nxt = SX5;
end
SET_INPUTS_STATE: begin
csoc_test_se_nxt = 1;
csoc_test_tm_nxt = 1;
if(new_rx_data) begin
if (low_byte) begin
nclks_nxt[7:0] = rx_data;
low_byte_nxt = 0;
state_nxt = SA1;
end
else begin
nclks_nxt[15:8] = rx_data;
low_byte_nxt = 1;
end
end
cont_pis_nxt = 1;
end
SA1: begin
clk_en_nxt = 1;
if(new_rx_data) begin
case (rx_data)
"0" : part_pis[cont_pis] = rx_data;
"1" : part_pis[cont_pis] = rx_data;
endcase
clk_en_nxt = 1;
cont_pis_nxt = cont_pis + 1;
if (cont_pis >= nclks) begin
clk_en_nxt = 0;
state_nxt = WAITING_COMMAND;
if (!csoc_clk)
clk_en_nxt = 1;
end
end
end
endcase
end
endmodule | 0 |
138,246 | data/full_repos/permissive/82849654/src/csoc.v | 82,849,654 | csoc.v | v | 64 | 53 | [] | [] | [] | [(4, 63)] | null | data/verilator_xmls/a8b7f9b5-66ae-4baf-9347-add21739e63e.xml | null | 302,074 | module | module csoc #(
parameter NREGS = 1918
)(
input clk_i,
input rstn_i,
input uart_read_i,
output uart_write_o,
input [7:0] data_i,
output [7:0] data_o,
input xtal_a_i,
output xtal_b_o,
output clk_o,
input test_tm_i,
input test_se_i
);
reg [NREGS-1:0] ffs_chain, ffs_chain_nxt;
reg uart_write, uart_write_nxt;
reg [7:0] data_or, data_or_nxt;
reg xtal_b, xtal_b_nxt;
reg clk_or, clk_or_nxt;
always @(posedge clk_i or negedge rstn_i) begin
if (!rstn_i) begin
uart_write <= 0;
data_or <= 0;
ffs_chain <= 0;
xtal_b <= 0;
clk_or <= 0;
end
else begin
data_or <= data_or_nxt;
uart_write <= uart_write_nxt;
clk_or <= clk_or_nxt;
xtal_b <= xtal_b_nxt;
ffs_chain <= ffs_chain_nxt;
end
end
always @(*) begin
uart_write_nxt = uart_write;
clk_or_nxt = clk_or;
xtal_b_nxt = xtal_b;
if (test_se_i) begin
ffs_chain_nxt = {data_i[0], ffs_chain[NREGS-1:1]};
data_or_nxt = {7'h0, ffs_chain[0]};
end
else begin
ffs_chain_nxt = ffs_chain;
data_or_nxt = data_or;
end
end
assign uart_write_o = uart_write;
assign data_o = data_or;
assign clk_o = xtal_a_i;
assign xtal_b_o = ~ xtal_a_i;
endmodule | module csoc #(
parameter NREGS = 1918
)(
input clk_i,
input rstn_i,
input uart_read_i,
output uart_write_o,
input [7:0] data_i,
output [7:0] data_o,
input xtal_a_i,
output xtal_b_o,
output clk_o,
input test_tm_i,
input test_se_i
); |
reg [NREGS-1:0] ffs_chain, ffs_chain_nxt;
reg uart_write, uart_write_nxt;
reg [7:0] data_or, data_or_nxt;
reg xtal_b, xtal_b_nxt;
reg clk_or, clk_or_nxt;
always @(posedge clk_i or negedge rstn_i) begin
if (!rstn_i) begin
uart_write <= 0;
data_or <= 0;
ffs_chain <= 0;
xtal_b <= 0;
clk_or <= 0;
end
else begin
data_or <= data_or_nxt;
uart_write <= uart_write_nxt;
clk_or <= clk_or_nxt;
xtal_b <= xtal_b_nxt;
ffs_chain <= ffs_chain_nxt;
end
end
always @(*) begin
uart_write_nxt = uart_write;
clk_or_nxt = clk_or;
xtal_b_nxt = xtal_b;
if (test_se_i) begin
ffs_chain_nxt = {data_i[0], ffs_chain[NREGS-1:1]};
data_or_nxt = {7'h0, ffs_chain[0]};
end
else begin
ffs_chain_nxt = ffs_chain;
data_or_nxt = data_or;
end
end
assign uart_write_o = uart_write;
assign data_o = data_or;
assign clk_o = xtal_a_i;
assign xtal_b_o = ~ xtal_a_i;
endmodule | 0 |
138,247 | data/full_repos/permissive/82849654/src/part_tester.v | 82,849,654 | part_tester.v | v | 96 | 90 | [] | ['gpl license'] | [] | null | line:13: before: "," | null | 1: b"%Error: data/full_repos/permissive/82849654/src/part_tester.v:13: Define or directive not defined: '`B9600'\n parameter BAUDRATE = `B9600,\n ^~~~~~\n%Error: data/full_repos/permissive/82849654/src/part_tester.v:13: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n parameter BAUDRATE = `B9600,\n ^\n%Error: data/full_repos/permissive/82849654/src/part_tester.v:15: syntax error, unexpected parameter, expecting IDENTIFIER\n parameter NPOS = 11\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82849654/src/part_tester.v:16: syntax error, unexpected ')', expecting ';'\n)(\n^\n%Error: data/full_repos/permissive/82849654/src/part_tester.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire rst, \n ^~~~~\n%Error: data/full_repos/permissive/82849654/src/part_tester.v:21: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire rx, \n ^~~~~\n%Error: data/full_repos/permissive/82849654/src/part_tester.v:22: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire tx, \n ^~~~~~\n%Error: data/full_repos/permissive/82849654/src/part_tester.v:25: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire [7:0] leds, \n ^~~~~~\n%Error: data/full_repos/permissive/82849654/src/part_tester.v:26: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire [7:0] sseg, \n ^~~~~~\n%Error: data/full_repos/permissive/82849654/src/part_tester.v:27: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire [3:0] an, \n ^~~~~~\n%Error: data/full_repos/permissive/82849654/src/part_tester.v:30: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire [1:14] part_pis_o, \n ^~~~~~\n%Error: data/full_repos/permissive/82849654/src/part_tester.v:31: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [1:11] part_pos_i \n ^~~~~\n%Error: data/full_repos/permissive/82849654/src/part_tester.v:32: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/82849654/src/part_tester.v:44: syntax error, unexpected always\nalways @(posedge clk or posedge rst) begin\n^~~~~~\n%Error: Exiting due to 14 error(s)\n" | 302,076 | module | module part_tester #(
parameter SHOW_INIT_MSG = 1,
parameter BAUDRATE = `B9600,
parameter NPIS = 14,
parameter NPOS = 11
)(
input wire clk,
input wire rst,
input wire rx,
output wire tx,
output wire [7:0] leds,
output wire [7:0] sseg,
output wire [3:0] an,
output wire [1:14] part_pis_o,
input wire [1:11] part_pos_i
);
reg [1:0] master_rst_n;
wire rx_rcv;
wire [7:0] rx_data;
wire [7:0] tx_data;
wire tx_start;
wire tx_ready;
always @(posedge clk or posedge rst) begin
if (rst) begin
master_rst_n <= 0;
end
else begin
master_rst_n[1] <= 1;
master_rst_n[0] <= master_rst_n[1];
end
end
uart_tx #(.BAUDRATE(BAUDRATE)) tx0 (
.clk(clk),
.rstn(master_rst_n[0]),
.start(tx_start),
.data(tx_data),
.ready(tx_ready),
.tx(tx)
);
uart_rx #(.BAUDRATE(BAUDRATE)) rx0 (
.clk(clk),
.rstn(master_rst_n[0]),
.rx(rx),
.rcv(rx_rcv),
.data(rx_data)
);
cmd_parser #(
.SHOW_INIT_MSG(SHOW_INIT_MSG),
.NPIS(NPIS),
.NPOS(NPOS)
)
cp0 (
.clk(clk),
.rstn(master_rst_n[0]),
.tx_start_o(tx_start),
.tx_data_o(tx_data),
.tx_ready_i(tx_ready),
.rx_data(rx_data),
.new_rx_data(rx_rcv),
.leds(leds),
.sseg(sseg),
.an(an),
.part_pis_o(part_pis_o),
.part_pos_i(part_pos_i)
);
endmodule | module part_tester #(
parameter SHOW_INIT_MSG = 1,
parameter BAUDRATE = `B9600,
parameter NPIS = 14,
parameter NPOS = 11
)(
input wire clk,
input wire rst,
input wire rx,
output wire tx,
output wire [7:0] leds,
output wire [7:0] sseg,
output wire [3:0] an,
output wire [1:14] part_pis_o,
input wire [1:11] part_pos_i
); |
reg [1:0] master_rst_n;
wire rx_rcv;
wire [7:0] rx_data;
wire [7:0] tx_data;
wire tx_start;
wire tx_ready;
always @(posedge clk or posedge rst) begin
if (rst) begin
master_rst_n <= 0;
end
else begin
master_rst_n[1] <= 1;
master_rst_n[0] <= master_rst_n[1];
end
end
uart_tx #(.BAUDRATE(BAUDRATE)) tx0 (
.clk(clk),
.rstn(master_rst_n[0]),
.start(tx_start),
.data(tx_data),
.ready(tx_ready),
.tx(tx)
);
uart_rx #(.BAUDRATE(BAUDRATE)) rx0 (
.clk(clk),
.rstn(master_rst_n[0]),
.rx(rx),
.rcv(rx_rcv),
.data(rx_data)
);
cmd_parser #(
.SHOW_INIT_MSG(SHOW_INIT_MSG),
.NPIS(NPIS),
.NPOS(NPOS)
)
cp0 (
.clk(clk),
.rstn(master_rst_n[0]),
.tx_start_o(tx_start),
.tx_data_o(tx_data),
.tx_ready_i(tx_ready),
.rx_data(rx_data),
.new_rx_data(rx_rcv),
.leds(leds),
.sseg(sseg),
.an(an),
.part_pis_o(part_pis_o),
.part_pos_i(part_pos_i)
);
endmodule | 0 |
138,248 | data/full_repos/permissive/82849654/src/sevenseg.v | 82,849,654 | sevenseg.v | v | 110 | 79 | [] | [] | [] | [(2, 109)] | null | data/verilator_xmls/7fe4b768-b40e-4825-b723-92ede3f1e799.xml | null | 302,077 | module | module sevenseg
(
input wire clk,
input wire rstn,
input wire [7:0] display_0,
input wire [7:0] display_1,
input wire [7:0] display_2,
input wire [7:0] display_3,
input wire [1:0] decplace,
output reg [7:0] seg,
output reg [3:0] an
);
localparam NUM_0 = 8'b11000000;
localparam NUM_1 = 8'b11111001;
localparam NUM_2 = 8'b10100100;
localparam NUM_3 = 8'b10110000;
localparam NUM_4 = 8'b10011001;
localparam NUM_5 = 8'b10010010;
localparam NUM_6 = 8'b10000010;
localparam NUM_7 = 8'b11111000;
localparam NUM_8 = 8'b10000000;
localparam NUM_9 = 8'b10010000;
localparam CHAR_A = 8'b10001000;
localparam CHAR_B = 8'b10000011;
localparam CHAR_C = 8'b11000110;
localparam CHAR_D = 8'b10100001;
localparam CHAR_E = 8'b10000110;
localparam CHAR_F = 8'b10001110;
localparam CHAR_G = 8'b10000010;
localparam CHAR_H = 8'b10001001;
localparam CHAR_K = 8'b10001111;
localparam CHAR_L = 8'b11000111;
localparam CHAR_o = 8'b10100011;
localparam CHAR_S = 8'b10010010;
localparam CHAR_T = 8'b11111000;
localparam CHAR_P = 8'b10001100;
localparam SPACE = 8'b11111111;
localparam HYPHEN = 8'b10111111;
localparam UNDERLINE = 8'b11110111;
localparam OVERRLINE = 8'b11111110;
reg [16:0] cnt;
reg [7:0] digit;
always @(cnt[16:15]) begin
case (cnt[16:15])
2'b11: an <= 4'b1110;
2'b10: an <= 4'b1101;
2'b01: an <= 4'b1011;
default: an <= 4'b0111;
endcase
end
always @(cnt[16:15] or display_0 or display_1 or display_2 or display_3) begin
case (cnt[16:15])
2'b00: digit <= display_0;
2'b01: digit <= display_1;
2'b10: digit <= display_2;
default: digit <= display_3;
endcase
case (digit)
8'h20: seg <= SPACE;
8'h2d: seg <= HYPHEN;
8'h30: seg <= NUM_0;
8'h31: seg <= NUM_1;
8'h32: seg <= NUM_2;
8'h33: seg <= NUM_3;
8'h34: seg <= NUM_4;
8'h35: seg <= NUM_5;
8'h36: seg <= NUM_6;
8'h37: seg <= NUM_7;
8'h38: seg <= NUM_8;
8'h39: seg <= NUM_9;
8'h41: seg <= CHAR_A;
8'h43: seg <= CHAR_C;
8'h45: seg <= CHAR_E;
8'h47: seg <= CHAR_G;
8'h48: seg <= CHAR_H;
8'h4b: seg <= CHAR_K;
8'h4c: seg <= CHAR_L;
8'h50: seg <= CHAR_P;
8'h53: seg <= CHAR_S;
8'h5f: seg <= UNDERLINE;
8'h6f: seg <= CHAR_o;
default: seg <= OVERRLINE;
endcase
end
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
cnt <= 0;
end
else
cnt <= cnt + 1;
end
endmodule | module sevenseg
(
input wire clk,
input wire rstn,
input wire [7:0] display_0,
input wire [7:0] display_1,
input wire [7:0] display_2,
input wire [7:0] display_3,
input wire [1:0] decplace,
output reg [7:0] seg,
output reg [3:0] an
); |
localparam NUM_0 = 8'b11000000;
localparam NUM_1 = 8'b11111001;
localparam NUM_2 = 8'b10100100;
localparam NUM_3 = 8'b10110000;
localparam NUM_4 = 8'b10011001;
localparam NUM_5 = 8'b10010010;
localparam NUM_6 = 8'b10000010;
localparam NUM_7 = 8'b11111000;
localparam NUM_8 = 8'b10000000;
localparam NUM_9 = 8'b10010000;
localparam CHAR_A = 8'b10001000;
localparam CHAR_B = 8'b10000011;
localparam CHAR_C = 8'b11000110;
localparam CHAR_D = 8'b10100001;
localparam CHAR_E = 8'b10000110;
localparam CHAR_F = 8'b10001110;
localparam CHAR_G = 8'b10000010;
localparam CHAR_H = 8'b10001001;
localparam CHAR_K = 8'b10001111;
localparam CHAR_L = 8'b11000111;
localparam CHAR_o = 8'b10100011;
localparam CHAR_S = 8'b10010010;
localparam CHAR_T = 8'b11111000;
localparam CHAR_P = 8'b10001100;
localparam SPACE = 8'b11111111;
localparam HYPHEN = 8'b10111111;
localparam UNDERLINE = 8'b11110111;
localparam OVERRLINE = 8'b11111110;
reg [16:0] cnt;
reg [7:0] digit;
always @(cnt[16:15]) begin
case (cnt[16:15])
2'b11: an <= 4'b1110;
2'b10: an <= 4'b1101;
2'b01: an <= 4'b1011;
default: an <= 4'b0111;
endcase
end
always @(cnt[16:15] or display_0 or display_1 or display_2 or display_3) begin
case (cnt[16:15])
2'b00: digit <= display_0;
2'b01: digit <= display_1;
2'b10: digit <= display_2;
default: digit <= display_3;
endcase
case (digit)
8'h20: seg <= SPACE;
8'h2d: seg <= HYPHEN;
8'h30: seg <= NUM_0;
8'h31: seg <= NUM_1;
8'h32: seg <= NUM_2;
8'h33: seg <= NUM_3;
8'h34: seg <= NUM_4;
8'h35: seg <= NUM_5;
8'h36: seg <= NUM_6;
8'h37: seg <= NUM_7;
8'h38: seg <= NUM_8;
8'h39: seg <= NUM_9;
8'h41: seg <= CHAR_A;
8'h43: seg <= CHAR_C;
8'h45: seg <= CHAR_E;
8'h47: seg <= CHAR_G;
8'h48: seg <= CHAR_H;
8'h4b: seg <= CHAR_K;
8'h4c: seg <= CHAR_L;
8'h50: seg <= CHAR_P;
8'h53: seg <= CHAR_S;
8'h5f: seg <= UNDERLINE;
8'h6f: seg <= CHAR_o;
default: seg <= OVERRLINE;
endcase
end
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
cnt <= 0;
end
else
cnt <= cnt + 1;
end
endmodule | 0 |
138,249 | data/full_repos/permissive/82849654/src/tb.v | 82,849,654 | tb.v | v | 434 | 95 | [] | [] | [] | null | line:189: before: ";" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/82849654/src/tb.v:174: Unsupported: Ignoring delay on this delayed statement.\nalways #20 clk = !clk; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/82849654/src/tb.v:202: Unsupported: Ignoring delay on this delayed statement.\n while(part0.cp0.state != 5) #1;\n ^\n%Error: data/full_repos/permissive/82849654/src/tb.v:210: syntax error, unexpected \'@\'\n @ (posedge rcv)\n ^\n%Error: data/full_repos/permissive/82849654/src/tb.v:230: syntax error, unexpected \'@\'\n @ (negedge ready)\n ^\n%Error: data/full_repos/permissive/82849654/src/tb.v:234: syntax error, unexpected \'@\'\n @ (posedge ready);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/82849654/src/tb.v:272: Unsupported: Ignoring delay on this delayed statement.\n #cycles\n ^\n%Error: data/full_repos/permissive/82849654/src/tb.v:371: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("part_tester.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/82849654/src/tb.v:372: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82849654/src/tb.v:382: Unsupported: Ignoring delay on this delayed statement.\n #70 rst = 0;\n ^\n%Error: data/full_repos/permissive/82849654/src/tb.v:413: Unsupported or unknown PLI call: $urandom\n cmd = $urandom%7;\n ^~~~~~~~\n%Error: data/full_repos/permissive/82849654/src/tb.v:414: Unsupported or unknown PLI call: $urandom\n cycles = $urandom%100;\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/82849654/src/tb.v:427: Unsupported: Ignoring delay on this delayed statement.\n #1000 $finish;\n ^\n%Error: Exiting due to 7 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,078 | module | module tb ();
parameter BAUDRATE = 9600;
reg clk;
reg rst;
reg xtal;
wire rstn;
reg send;
reg [7:0] send_data;
wire dut_rx;
wire ready;
wire dut_tx;
wire rcv;
wire [7:0] data_rcv;
wire [7:0] leds;
wire [7:0] sseg;
wire [3:0] an;
localparam NREGS = 6;
localparam NPIS = 14;
localparam NPOS = 11;
wire [1:NPIS] part_pis;
wire [1:NPOS] part_pos;
wire csoc_clk;
wire csoc_rstn;
wire csoc_test_se;
wire csoc_test_tm;
wire csoc_uart_read;
wire [7:0] csoc_data_i;
wire csoc_uart_write;
wire [7:0] csoc_data_o;
wire csoc_xtal_i;
wire csoc_xtal_o;
wire csoc_clk_o;
assign csoc_clk = part_pis[1];
assign csoc_data_i = part_pis[2:9];
assign csoc_rstn = part_pis[10];
assign csoc_test_se = part_pis[11];
assign csoc_test_tm = part_pis[12];
assign csoc_uart_read = part_pis[13];
assign csoc_xtal_i = part_pos[14];
assign part_pos[1] = csoc_xtal_o;
assign part_pos[2:9] = csoc_data_o;
assign part_pos[10] = csoc_uart_write;
assign part_pos[11] = csoc_clk_o;
reg [8*14:1] part_pos_names [1:NPOS];
reg [8*14:1] part_pis_names [1:NPIS];
initial begin
part_pis_names[1] = "clk";
part_pis_names[2] = "data_i_0";
part_pis_names[3] = "data_i_1";
part_pis_names[4] = "data_i_2";
part_pis_names[5] = "data_i_3";
part_pis_names[6] = "data_i_4";
part_pis_names[7] = "data_i_5";
part_pis_names[8] = "data_i_6";
part_pis_names[9] = "data_i_7";
part_pis_names[10] = "rstn";
part_pis_names[11] = "test_se";
part_pis_names[12] = "test_tm";
part_pis_names[13] = "uart_read";
part_pis_names[14] = "xtal_i";
part_pos_names[1] = "clk_o";
part_pos_names[2] = "data_o_0";
part_pos_names[3] = "data_o_1";
part_pos_names[4] = "data_o_2";
part_pos_names[5] = "data_o_3";
part_pos_names[6] = "data_o_4";
part_pos_names[7] = "data_o_5";
part_pos_names[8] = "data_o_6";
part_pos_names[9] = "data_o_7";
part_pos_names[10] = "uart_write";
part_pos_names[11] = "xtal_o";
end
localparam
RESET_CMD = "r",
SET_STATE_CMD = "s",
GET_STATE_CMD = "g",
SET_INPUTS_CMD = "i",
GET_OUTPUTS_CMD = "o",
EXECUTE_CMD = "e",
FREE_RUN_CMD = "f",
PAUSE_CMD = "p";
uart_rx #(.BAUDRATE(BAUDRATE)) rx0 (
.clk(clk),
.rstn(rstn),
.rx(dut_tx),
.rcv(rcv),
.data(data_rcv)
);
uart_tx #(.BAUDRATE(BAUDRATE)) tx0 (
.clk(clk),
.rstn(rstn),
.start(send),
.data(send_data),
.ready(ready),
.tx(dut_rx)
);
localparam SHOW_INIT_MSG = 1;
part_tester #(.SHOW_INIT_MSG(SHOW_INIT_MSG), .BAUDRATE(BAUDRATE)) part0 (
.clk(clk),
.rst(rst),
.rx(dut_rx),
.tx(dut_tx),
.leds(leds),
.sseg(sseg),
.an(an),
.part_pis_o(part_pis),
.part_pos_i(part_pos)
);
csoc #(.NREGS(NREGS)) csoc0 (
.clk_i(csoc_clk),
.rstn_i(csoc_rstn),
.uart_read_i(csoc_uart_read),
.uart_write_o(csoc_uart_write),
.data_i(csoc_data_i),
.data_o(csoc_data_o),
.xtal_a_i(xtal),
.xtal_b_o(csoc_xtal_o),
.clk_o(csoc_clk_o),
.test_tm_i(csoc_test_tm),
.test_se_i(csoc_test_se)
);
always #20 clk = !clk;
assign rstn = ~rst;
task initial_message;
begin
$display("\nTASK: Receiving initial message");
if(data_rcv == "\n") begin
recv_task;
$write("\n");
end
while(data_rcv != "\n")
begin
recv_task;
$write("\n");
end
end
endtask
task wait_for_idle_state;
begin
while(part0.cp0.state != 5) #1;
end
endtask
task recv_task;
integer data_ascii;
begin
@ (posedge rcv)
if ((data_rcv < 32) || (data_rcv > 126))
data_ascii = "_";
else
data_ascii = data_rcv;
$write("- Data received: ------- %3d|%0c|0x%h|%b", data_rcv, data_ascii, data_rcv, data_rcv);
end
endtask
task send_task;
input [7:0] data;
integer data_ascii;
begin
if ((data < 32) || (data > 126))
data_ascii = "_";
else
data_ascii = data;
$write("- Sending data: -------- %3d|%0c|0x%h|%b", data, data_ascii, data, data);
send_data = data;
send = 1;
@ (negedge ready)
@ (posedge clk)
send = 0;
send_data = 0;
@ (posedge ready);
end
endtask
task reset_part_test;
begin
$display("\nTASK: Reseting the DUT");
send_task(RESET_CMD);
$write("\n");
initial_message;
wait_for_idle_state;
end
endtask
task execute_dut;
input [15:0] cycles;
begin
$display("\nTASK: Executing DUT for %0d cycles", cycles);
send_task(EXECUTE_CMD);
$write("\n");
send_task(cycles[15:8]);
$write("\n");
send_task(cycles[7:0]);
$write("\n");
wait_for_idle_state;
end
endtask
task free_run_dut;
input [15:0] cycles;
begin
$display("\nTASK: DUT running free");
send_task(FREE_RUN_CMD);
$write("\n");
#cycles
send_task(PAUSE_CMD);
$write("\n");
$display("- Stopped by user after %0d cycles", cycles);
wait_for_idle_state;
end
endtask
task get_dut;
input [7:0] cmd;
input [15:0] data_width;
integer i;
begin
case (cmd)
GET_STATE_CMD: $write("\nTASK: Getting DUT internal state for %0d cycles\n", data_width);
GET_OUTPUTS_CMD: $write("\nTASK: Getting DUT outputs state for %0d cycles\n", data_width);
default: begin
$display("\nTASK: ERROR, missing command to get DUT state");
$finish;
end
endcase
send_task(cmd);
$write("\n");
send_task(data_width[15:8]);
$write("\n");
send_task(data_width[7:0]);
$write("\n");
for (i=0; i<data_width; i=i+1) begin
recv_task;
if (cmd == GET_OUTPUTS_CMD)
$write(" %4d %0s \n", i+1, part_pos_names[i+1]);
else
$write(" %4d cycles\n", i+1);
end
wait_for_idle_state;
end
endtask
task set_dut;
input [15:0] cmd;
input [15:0] data_width;
input integer data;
integer i;
begin
case (cmd)
SET_STATE_CMD: $write("\nTASK: Setting DUT internal state for %0d cycles\n", data_width);
SET_INPUTS_CMD: $write("\nTASK: Setting DUT inputs state for %0d cycles\n", data_width);
default: begin
$display("ERROR, missing command to set DUT state");
$finish;
end
endcase
send_task(cmd);
$write("\n");
send_task(data_width[15:8]);
$write("\n");
send_task(data_width[7:0]);
$write("\n");
for (i=0; i<data_width; i=i+1) begin
case (i)
0: send_task("1");
1: send_task("0");
2: send_task("1");
3: send_task("0");
4: send_task("0");
5: send_task("1");
default: send_task("0");
endcase
$write(" %4d ", i+1);
if (cmd == SET_INPUTS_CMD)
$write(" %0s \n", part_pis_names[i+1]);
else
$write("cycles \n");
end
wait_for_idle_state;
end
endtask
integer seed;
integer cmd;
integer cont;
integer cycles;
initial begin
$dumpfile("part_tester.vcd");
$dumpvars(0);
$write("\nCSoC Test Running...\n");
clk = 0;
rst = 1;
xtal = 0;
send = 0;
send_data = 0;
#70 rst = 0;
if (SHOW_INIT_MSG)
initial_message;
for (cont=0; cont<30; cont=cont+1)
begin
cmd = $urandom%7;
cycles = $urandom%100;
$write("\n#> Command %0d\n", cmd);
case (cmd)
1: execute_dut(cycles);
2: free_run_dut(cycles);
3: set_dut(SET_STATE_CMD, cycles, "1011");
4: set_dut(SET_INPUTS_CMD, NPIS, "10001010111111");
5: get_dut(GET_STATE_CMD, cycles);
6: get_dut(GET_OUTPUTS_CMD, NPOS);
default: reset_part_test;
endcase
end
#1000 $finish;
end
endmodule | module tb (); |
parameter BAUDRATE = 9600;
reg clk;
reg rst;
reg xtal;
wire rstn;
reg send;
reg [7:0] send_data;
wire dut_rx;
wire ready;
wire dut_tx;
wire rcv;
wire [7:0] data_rcv;
wire [7:0] leds;
wire [7:0] sseg;
wire [3:0] an;
localparam NREGS = 6;
localparam NPIS = 14;
localparam NPOS = 11;
wire [1:NPIS] part_pis;
wire [1:NPOS] part_pos;
wire csoc_clk;
wire csoc_rstn;
wire csoc_test_se;
wire csoc_test_tm;
wire csoc_uart_read;
wire [7:0] csoc_data_i;
wire csoc_uart_write;
wire [7:0] csoc_data_o;
wire csoc_xtal_i;
wire csoc_xtal_o;
wire csoc_clk_o;
assign csoc_clk = part_pis[1];
assign csoc_data_i = part_pis[2:9];
assign csoc_rstn = part_pis[10];
assign csoc_test_se = part_pis[11];
assign csoc_test_tm = part_pis[12];
assign csoc_uart_read = part_pis[13];
assign csoc_xtal_i = part_pos[14];
assign part_pos[1] = csoc_xtal_o;
assign part_pos[2:9] = csoc_data_o;
assign part_pos[10] = csoc_uart_write;
assign part_pos[11] = csoc_clk_o;
reg [8*14:1] part_pos_names [1:NPOS];
reg [8*14:1] part_pis_names [1:NPIS];
initial begin
part_pis_names[1] = "clk";
part_pis_names[2] = "data_i_0";
part_pis_names[3] = "data_i_1";
part_pis_names[4] = "data_i_2";
part_pis_names[5] = "data_i_3";
part_pis_names[6] = "data_i_4";
part_pis_names[7] = "data_i_5";
part_pis_names[8] = "data_i_6";
part_pis_names[9] = "data_i_7";
part_pis_names[10] = "rstn";
part_pis_names[11] = "test_se";
part_pis_names[12] = "test_tm";
part_pis_names[13] = "uart_read";
part_pis_names[14] = "xtal_i";
part_pos_names[1] = "clk_o";
part_pos_names[2] = "data_o_0";
part_pos_names[3] = "data_o_1";
part_pos_names[4] = "data_o_2";
part_pos_names[5] = "data_o_3";
part_pos_names[6] = "data_o_4";
part_pos_names[7] = "data_o_5";
part_pos_names[8] = "data_o_6";
part_pos_names[9] = "data_o_7";
part_pos_names[10] = "uart_write";
part_pos_names[11] = "xtal_o";
end
localparam
RESET_CMD = "r",
SET_STATE_CMD = "s",
GET_STATE_CMD = "g",
SET_INPUTS_CMD = "i",
GET_OUTPUTS_CMD = "o",
EXECUTE_CMD = "e",
FREE_RUN_CMD = "f",
PAUSE_CMD = "p";
uart_rx #(.BAUDRATE(BAUDRATE)) rx0 (
.clk(clk),
.rstn(rstn),
.rx(dut_tx),
.rcv(rcv),
.data(data_rcv)
);
uart_tx #(.BAUDRATE(BAUDRATE)) tx0 (
.clk(clk),
.rstn(rstn),
.start(send),
.data(send_data),
.ready(ready),
.tx(dut_rx)
);
localparam SHOW_INIT_MSG = 1;
part_tester #(.SHOW_INIT_MSG(SHOW_INIT_MSG), .BAUDRATE(BAUDRATE)) part0 (
.clk(clk),
.rst(rst),
.rx(dut_rx),
.tx(dut_tx),
.leds(leds),
.sseg(sseg),
.an(an),
.part_pis_o(part_pis),
.part_pos_i(part_pos)
);
csoc #(.NREGS(NREGS)) csoc0 (
.clk_i(csoc_clk),
.rstn_i(csoc_rstn),
.uart_read_i(csoc_uart_read),
.uart_write_o(csoc_uart_write),
.data_i(csoc_data_i),
.data_o(csoc_data_o),
.xtal_a_i(xtal),
.xtal_b_o(csoc_xtal_o),
.clk_o(csoc_clk_o),
.test_tm_i(csoc_test_tm),
.test_se_i(csoc_test_se)
);
always #20 clk = !clk;
assign rstn = ~rst;
task initial_message;
begin
$display("\nTASK: Receiving initial message");
if(data_rcv == "\n") begin
recv_task;
$write("\n");
end
while(data_rcv != "\n")
begin
recv_task;
$write("\n");
end
end
endtask
task wait_for_idle_state;
begin
while(part0.cp0.state != 5) #1;
end
endtask
task recv_task;
integer data_ascii;
begin
@ (posedge rcv)
if ((data_rcv < 32) || (data_rcv > 126))
data_ascii = "_";
else
data_ascii = data_rcv;
$write("- Data received: ------- %3d|%0c|0x%h|%b", data_rcv, data_ascii, data_rcv, data_rcv);
end
endtask
task send_task;
input [7:0] data;
integer data_ascii;
begin
if ((data < 32) || (data > 126))
data_ascii = "_";
else
data_ascii = data;
$write("- Sending data: -------- %3d|%0c|0x%h|%b", data, data_ascii, data, data);
send_data = data;
send = 1;
@ (negedge ready)
@ (posedge clk)
send = 0;
send_data = 0;
@ (posedge ready);
end
endtask
task reset_part_test;
begin
$display("\nTASK: Reseting the DUT");
send_task(RESET_CMD);
$write("\n");
initial_message;
wait_for_idle_state;
end
endtask
task execute_dut;
input [15:0] cycles;
begin
$display("\nTASK: Executing DUT for %0d cycles", cycles);
send_task(EXECUTE_CMD);
$write("\n");
send_task(cycles[15:8]);
$write("\n");
send_task(cycles[7:0]);
$write("\n");
wait_for_idle_state;
end
endtask
task free_run_dut;
input [15:0] cycles;
begin
$display("\nTASK: DUT running free");
send_task(FREE_RUN_CMD);
$write("\n");
#cycles
send_task(PAUSE_CMD);
$write("\n");
$display("- Stopped by user after %0d cycles", cycles);
wait_for_idle_state;
end
endtask
task get_dut;
input [7:0] cmd;
input [15:0] data_width;
integer i;
begin
case (cmd)
GET_STATE_CMD: $write("\nTASK: Getting DUT internal state for %0d cycles\n", data_width);
GET_OUTPUTS_CMD: $write("\nTASK: Getting DUT outputs state for %0d cycles\n", data_width);
default: begin
$display("\nTASK: ERROR, missing command to get DUT state");
$finish;
end
endcase
send_task(cmd);
$write("\n");
send_task(data_width[15:8]);
$write("\n");
send_task(data_width[7:0]);
$write("\n");
for (i=0; i<data_width; i=i+1) begin
recv_task;
if (cmd == GET_OUTPUTS_CMD)
$write(" %4d %0s \n", i+1, part_pos_names[i+1]);
else
$write(" %4d cycles\n", i+1);
end
wait_for_idle_state;
end
endtask
task set_dut;
input [15:0] cmd;
input [15:0] data_width;
input integer data;
integer i;
begin
case (cmd)
SET_STATE_CMD: $write("\nTASK: Setting DUT internal state for %0d cycles\n", data_width);
SET_INPUTS_CMD: $write("\nTASK: Setting DUT inputs state for %0d cycles\n", data_width);
default: begin
$display("ERROR, missing command to set DUT state");
$finish;
end
endcase
send_task(cmd);
$write("\n");
send_task(data_width[15:8]);
$write("\n");
send_task(data_width[7:0]);
$write("\n");
for (i=0; i<data_width; i=i+1) begin
case (i)
0: send_task("1");
1: send_task("0");
2: send_task("1");
3: send_task("0");
4: send_task("0");
5: send_task("1");
default: send_task("0");
endcase
$write(" %4d ", i+1);
if (cmd == SET_INPUTS_CMD)
$write(" %0s \n", part_pis_names[i+1]);
else
$write("cycles \n");
end
wait_for_idle_state;
end
endtask
integer seed;
integer cmd;
integer cont;
integer cycles;
initial begin
$dumpfile("part_tester.vcd");
$dumpvars(0);
$write("\nCSoC Test Running...\n");
clk = 0;
rst = 1;
xtal = 0;
send = 0;
send_data = 0;
#70 rst = 0;
if (SHOW_INIT_MSG)
initial_message;
for (cont=0; cont<30; cont=cont+1)
begin
cmd = $urandom%7;
cycles = $urandom%100;
$write("\n#> Command %0d\n", cmd);
case (cmd)
1: execute_dut(cycles);
2: free_run_dut(cycles);
3: set_dut(SET_STATE_CMD, cycles, "1011");
4: set_dut(SET_INPUTS_CMD, NPIS, "10001010111111");
5: get_dut(GET_STATE_CMD, cycles);
6: get_dut(GET_OUTPUTS_CMD, NPOS);
default: reset_part_test;
endcase
end
#1000 $finish;
end
endmodule | 0 |
138,250 | data/full_repos/permissive/82891137/alu.v | 82,891,137 | alu.v | v | 60 | 66 | [] | [] | [] | null | line:60: before: "/" | null | 1: b"%Error: data/full_repos/permissive/82891137/alu.v:49: Cannot find file containing module: 'alu_flags'\n alu_flags #(\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82891137,data/full_repos/permissive/82891137/alu_flags\n data/full_repos/permissive/82891137,data/full_repos/permissive/82891137/alu_flags.v\n data/full_repos/permissive/82891137,data/full_repos/permissive/82891137/alu_flags.sv\n alu_flags\n alu_flags.v\n alu_flags.sv\n obj_dir/alu_flags\n obj_dir/alu_flags.v\n obj_dir/alu_flags.sv\n%Error: Exiting due to 1 error(s)\n" | 302,081 | module | module alu
#(parameter DATA_WIDTH = 32)
(
input [DATA_WIDTH-1:0] srcA,
input [DATA_WIDTH-1:0] srcB,
input [3:0] aluop,
output reg [DATA_WIDTH-1:0] aluout,
output zero,
output of,
output uof
);
wire signed [DATA_WIDTH-1:0] signed_srcA;
wire signed [DATA_WIDTH-1:0] signed_srcB;
assign signed_srcA = $signed(srcA);
assign signed_srcB = $signed(srcB);
always @ ( * ) begin
case (aluop)
4'd0: aluout <= srcA << srcB;
4'd1: aluout <= srcA >>> srcB;
4'd2: aluout <= srcA >> srcB;
4'd3: aluout <= srcA * srcB;
4'd4: aluout <= srcA / srcB;
4'd5: aluout <= srcA + srcB;
4'd6: aluout <= srcA - srcB;
4'd7: aluout <= srcA & srcB;
4'd8: aluout <= srcA | srcB;
4'd9: aluout <= srcA ^ srcB;
4'd10: aluout <= ~(srcA | srcB);
4'd11: aluout <= (signed_srcA < signed_srcB) ? 1 : 0;
4'd12: aluout <= (srcA < srcB) ? 1 : 0;
default: aluout <= 0;
endcase
end
alu_flags #(
.DATA_WIDTH(DATA_WIDTH)
) FLAGS (
.srcA(srcA),
.srcB(srcB),
.aluop(aluop),
.zero(zero),
.of(of),
.uof(uof)
);
endmodule | module alu
#(parameter DATA_WIDTH = 32)
(
input [DATA_WIDTH-1:0] srcA,
input [DATA_WIDTH-1:0] srcB,
input [3:0] aluop,
output reg [DATA_WIDTH-1:0] aluout,
output zero,
output of,
output uof
); |
wire signed [DATA_WIDTH-1:0] signed_srcA;
wire signed [DATA_WIDTH-1:0] signed_srcB;
assign signed_srcA = $signed(srcA);
assign signed_srcB = $signed(srcB);
always @ ( * ) begin
case (aluop)
4'd0: aluout <= srcA << srcB;
4'd1: aluout <= srcA >>> srcB;
4'd2: aluout <= srcA >> srcB;
4'd3: aluout <= srcA * srcB;
4'd4: aluout <= srcA / srcB;
4'd5: aluout <= srcA + srcB;
4'd6: aluout <= srcA - srcB;
4'd7: aluout <= srcA & srcB;
4'd8: aluout <= srcA | srcB;
4'd9: aluout <= srcA ^ srcB;
4'd10: aluout <= ~(srcA | srcB);
4'd11: aluout <= (signed_srcA < signed_srcB) ? 1 : 0;
4'd12: aluout <= (srcA < srcB) ? 1 : 0;
default: aluout <= 0;
endcase
end
alu_flags #(
.DATA_WIDTH(DATA_WIDTH)
) FLAGS (
.srcA(srcA),
.srcB(srcB),
.aluop(aluop),
.zero(zero),
.of(of),
.uof(uof)
);
endmodule | 0 |
138,251 | data/full_repos/permissive/82891137/alu_flags.v | 82,891,137 | alu_flags.v | v | 37 | 169 | [] | [] | [] | null | line:37: before: "/" | data/verilator_xmls/ba17cb57-f30f-4fa1-8c1f-e5a710b894db.xml | null | 302,082 | module | module alu_flags
#(parameter DATA_WIDTH = 32)
(
input [DATA_WIDTH-1:0] srcA,
input [DATA_WIDTH-1:0] srcB,
input [3:0] aluop,
output zero,
output of,
output uof
);
wire [DATA_WIDTH-1:0] sum, diff;
wire carry1, carry2;
assign {carry1, sum} = srcA + srcB;
assign {carry2, diff} = srcA - srcB;
assign zero = (srcA == srcB);
assign of = (aluop == 4'd5) ? ((srcA[DATA_WIDTH-1] & srcB[DATA_WIDTH-1] & ~sum[DATA_WIDTH-1]) | (~srcA[DATA_WIDTH-1] & ~srcB[DATA_WIDTH-1] & sum[DATA_WIDTH-1]))
: (aluop == 4'd6) ? ((srcA[DATA_WIDTH-1] & ~srcB[DATA_WIDTH-1] & ~diff[DATA_WIDTH-1]) | (~srcA[DATA_WIDTH-1] & srcB[DATA_WIDTH-1] & diff[DATA_WIDTH-1]))
: 0;
assign uof = (aluop == 4'd5) ? (carry1)
: (aluop == 4'd6) ? (carry2)
: 0;
endmodule | module alu_flags
#(parameter DATA_WIDTH = 32)
(
input [DATA_WIDTH-1:0] srcA,
input [DATA_WIDTH-1:0] srcB,
input [3:0] aluop,
output zero,
output of,
output uof
); |
wire [DATA_WIDTH-1:0] sum, diff;
wire carry1, carry2;
assign {carry1, sum} = srcA + srcB;
assign {carry2, diff} = srcA - srcB;
assign zero = (srcA == srcB);
assign of = (aluop == 4'd5) ? ((srcA[DATA_WIDTH-1] & srcB[DATA_WIDTH-1] & ~sum[DATA_WIDTH-1]) | (~srcA[DATA_WIDTH-1] & ~srcB[DATA_WIDTH-1] & sum[DATA_WIDTH-1]))
: (aluop == 4'd6) ? ((srcA[DATA_WIDTH-1] & ~srcB[DATA_WIDTH-1] & ~diff[DATA_WIDTH-1]) | (~srcA[DATA_WIDTH-1] & srcB[DATA_WIDTH-1] & diff[DATA_WIDTH-1]))
: 0;
assign uof = (aluop == 4'd5) ? (carry1)
: (aluop == 4'd6) ? (carry2)
: 0;
endmodule | 0 |
138,252 | data/full_repos/permissive/82891137/counter.v | 82,891,137 | counter.v | v | 31 | 40 | [] | [] | [] | [(11, 30)] | null | data/verilator_xmls/6b1a1057-6073-4be3-9e1c-e0249799773e.xml | null | 302,083 | module | module counter
#(parameter DATA_WIDTH = 1, STEP = 1)
(
input clk,
input rst,
input en,
output reg [(DATA_WIDTH-1):0] count
);
always @(posedge clk) begin
if (rst) begin
count <= 0 ;
end else if (en) begin
count <= count + 1;
end else begin
count <= count;
end
end
endmodule | module counter
#(parameter DATA_WIDTH = 1, STEP = 1)
(
input clk,
input rst,
input en,
output reg [(DATA_WIDTH-1):0] count
); |
always @(posedge clk) begin
if (rst) begin
count <= 0 ;
end else if (en) begin
count <= count + 1;
end else begin
count <= count;
end
end
endmodule | 0 |
138,253 | data/full_repos/permissive/82891137/data_to_segment.v | 82,891,137 | data_to_segment.v | v | 48 | 41 | [] | [] | [] | [(1, 48)] | null | null | 1: b"%Error: data/full_repos/permissive/82891137/data_to_segment.v:8: Cannot find file containing module: 'integer_to_segment'\n integer_to_segment trans1 (\n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82891137,data/full_repos/permissive/82891137/integer_to_segment\n data/full_repos/permissive/82891137,data/full_repos/permissive/82891137/integer_to_segment.v\n data/full_repos/permissive/82891137,data/full_repos/permissive/82891137/integer_to_segment.sv\n integer_to_segment\n integer_to_segment.v\n integer_to_segment.sv\n obj_dir/integer_to_segment\n obj_dir/integer_to_segment.v\n obj_dir/integer_to_segment.sv\n%Error: data/full_repos/permissive/82891137/data_to_segment.v:13: Cannot find file containing module: 'integer_to_segment'\n integer_to_segment trans2 (\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82891137/data_to_segment.v:18: Cannot find file containing module: 'integer_to_segment'\n integer_to_segment trans3 (\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82891137/data_to_segment.v:23: Cannot find file containing module: 'integer_to_segment'\n integer_to_segment trans4 (\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82891137/data_to_segment.v:28: Cannot find file containing module: 'integer_to_segment'\n integer_to_segment trans5 (\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82891137/data_to_segment.v:33: Cannot find file containing module: 'integer_to_segment'\n integer_to_segment trans6 (\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82891137/data_to_segment.v:38: Cannot find file containing module: 'integer_to_segment'\n integer_to_segment trans7 (\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/82891137/data_to_segment.v:43: Cannot find file containing module: 'integer_to_segment'\n integer_to_segment trans8 (\n ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n" | 302,084 | module | module data_to_segment
#(parameter DATA_WIDTH = 32)
(
input [(DATA_WIDTH-1):0] data,
output [(DATA_WIDTH*2)-1:0] seg_data
);
integer_to_segment trans1 (
.int_data(data[3:0]),
.seg_data(seg_data[7:0])
);
integer_to_segment trans2 (
.int_data(data[7:4]),
.seg_data(seg_data[15:8])
);
integer_to_segment trans3 (
.int_data(data[11:8]),
.seg_data(seg_data[23:16])
);
integer_to_segment trans4 (
.int_data(data[15:12]),
.seg_data(seg_data[31:24])
);
integer_to_segment trans5 (
.int_data(data[19:16]),
.seg_data(seg_data[39:32])
);
integer_to_segment trans6 (
.int_data(data[23:20]),
.seg_data(seg_data[47:40])
);
integer_to_segment trans7 (
.int_data(data[27:24]),
.seg_data(seg_data[55:48])
);
integer_to_segment trans8 (
.int_data(data[31:28]),
.seg_data(seg_data[63:56])
);
endmodule | module data_to_segment
#(parameter DATA_WIDTH = 32)
(
input [(DATA_WIDTH-1):0] data,
output [(DATA_WIDTH*2)-1:0] seg_data
); |
integer_to_segment trans1 (
.int_data(data[3:0]),
.seg_data(seg_data[7:0])
);
integer_to_segment trans2 (
.int_data(data[7:4]),
.seg_data(seg_data[15:8])
);
integer_to_segment trans3 (
.int_data(data[11:8]),
.seg_data(seg_data[23:16])
);
integer_to_segment trans4 (
.int_data(data[15:12]),
.seg_data(seg_data[31:24])
);
integer_to_segment trans5 (
.int_data(data[19:16]),
.seg_data(seg_data[39:32])
);
integer_to_segment trans6 (
.int_data(data[23:20]),
.seg_data(seg_data[47:40])
);
integer_to_segment trans7 (
.int_data(data[27:24]),
.seg_data(seg_data[55:48])
);
integer_to_segment trans8 (
.int_data(data[31:28]),
.seg_data(seg_data[63:56])
);
endmodule | 0 |
138,254 | data/full_repos/permissive/82891137/dmem.v | 82,891,137 | dmem.v | v | 38 | 60 | [] | [] | [] | [(13, 37)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/82891137/dmem.v:34: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s REPLICATE generates 31 bits.\n : ... In instance dmem\n assign rdata = re ? RAM[addr] : {(DATA_WIDTH-1){1\'bx}};\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/82891137/dmem.v:35: Bit extraction of array[1023:0] requires 10 bit index, not 5 bits.\n : ... In instance dmem\n assign led_data = RAM[switch_addr];\n ^\n%Error: Exiting due to 2 warning(s)\n' | 302,085 | module | module dmem
#(parameter DATA_WIDTH = 32, BUS_WIDTH = 10)
(
input clk,
input re,
input we,
input [BUS_WIDTH-1:0] addr,
input [DATA_WIDTH-1:0] wdata,
input [4:0] switch_addr,
output [DATA_WIDTH-1:0] rdata,
output [DATA_WIDTH-1:0] led_data
);
reg [DATA_WIDTH-1:0] RAM [0:(2**BUS_WIDTH)-1];
always @ (posedge clk) begin
if (we) begin
RAM[addr] <= wdata;
end
end
assign rdata = re ? RAM[addr] : {(DATA_WIDTH-1){1'bx}};
assign led_data = RAM[switch_addr];
endmodule | module dmem
#(parameter DATA_WIDTH = 32, BUS_WIDTH = 10)
(
input clk,
input re,
input we,
input [BUS_WIDTH-1:0] addr,
input [DATA_WIDTH-1:0] wdata,
input [4:0] switch_addr,
output [DATA_WIDTH-1:0] rdata,
output [DATA_WIDTH-1:0] led_data
); |
reg [DATA_WIDTH-1:0] RAM [0:(2**BUS_WIDTH)-1];
always @ (posedge clk) begin
if (we) begin
RAM[addr] <= wdata;
end
end
assign rdata = re ? RAM[addr] : {(DATA_WIDTH-1){1'bx}};
assign led_data = RAM[switch_addr];
endmodule | 0 |
138,255 | data/full_repos/permissive/82891137/imem.v | 82,891,137 | imem.v | v | 26 | 78 | [] | [] | [] | null | None: at end of input | data/verilator_xmls/30004063-996f-45db-981d-19f79440d476.xml | null | 302,086 | module | module imem
#(parameter DATA_WIDTH = 32, BUS_WIDTH = 10, CODE_FILE= "mips/benchmark.hex")
(
input [BUS_WIDTH-1:0] addr,
output [DATA_WIDTH-1:0] rdata
);
reg [DATA_WIDTH-1:0] ROM [0:(2**BUS_WIDTH)-1];
initial begin
$readmemh(CODE_FILE, ROM, 0, (2**BUS_WIDTH)-1);
end
assign rdata = ROM[addr];
endmodule | module imem
#(parameter DATA_WIDTH = 32, BUS_WIDTH = 10, CODE_FILE= "mips/benchmark.hex")
(
input [BUS_WIDTH-1:0] addr,
output [DATA_WIDTH-1:0] rdata
); |
reg [DATA_WIDTH-1:0] ROM [0:(2**BUS_WIDTH)-1];
initial begin
$readmemh(CODE_FILE, ROM, 0, (2**BUS_WIDTH)-1);
end
assign rdata = ROM[addr];
endmodule | 0 |
138,256 | data/full_repos/permissive/82891137/integer_to_segment.v | 82,891,137 | integer_to_segment.v | v | 28 | 59 | [] | [] | [] | [(1, 28)] | null | data/verilator_xmls/b1a7be21-7466-4617-87b0-29da4138fbf9.xml | null | 302,087 | module | module integer_to_segment
(
input [3:0] int_data,
output reg [7:0] seg_data
);
always @(int_data) begin
case (int_data)
4'b0000: seg_data <= 8'b11000000;
4'b0001: seg_data <= 8'b11111001;
4'b0010: seg_data <= 8'b10100100;
4'b0011: seg_data <= 8'b10110000;
4'b0100: seg_data <= 8'b10011001;
4'b0101: seg_data <= 8'b10010010;
4'b0110: seg_data <= 8'b10000010;
4'b0111: seg_data <= 8'b11111000;
4'b1000: seg_data <= 8'b10000000;
4'b1001: seg_data <= 8'b10010000;
4'b1010: seg_data <= 8'b10001000;
4'b1011: seg_data <= 8'b10000011;
4'b1100: seg_data <= 8'b11000110;
4'b1101: seg_data <= 8'b10100001;
4'b1110: seg_data <= 8'b10000110;
4'b1111: seg_data <= 8'b10001110;
default: seg_data <= 8'b11111111;
endcase
end
endmodule | module integer_to_segment
(
input [3:0] int_data,
output reg [7:0] seg_data
); |
always @(int_data) begin
case (int_data)
4'b0000: seg_data <= 8'b11000000;
4'b0001: seg_data <= 8'b11111001;
4'b0010: seg_data <= 8'b10100100;
4'b0011: seg_data <= 8'b10110000;
4'b0100: seg_data <= 8'b10011001;
4'b0101: seg_data <= 8'b10010010;
4'b0110: seg_data <= 8'b10000010;
4'b0111: seg_data <= 8'b11111000;
4'b1000: seg_data <= 8'b10000000;
4'b1001: seg_data <= 8'b10010000;
4'b1010: seg_data <= 8'b10001000;
4'b1011: seg_data <= 8'b10000011;
4'b1100: seg_data <= 8'b11000110;
4'b1101: seg_data <= 8'b10100001;
4'b1110: seg_data <= 8'b10000110;
4'b1111: seg_data <= 8'b10001110;
default: seg_data <= 8'b11111111;
endcase
end
endmodule | 0 |
138,257 | data/full_repos/permissive/82891137/latch_counter.v | 82,891,137 | latch_counter.v | v | 36 | 59 | [] | [] | [] | [(9, 35)] | null | data/verilator_xmls/a392dd6c-6940-4713-b61c-f717e9d2cfa6.xml | null | 302,088 | module | module latch_counter
(
input clk,
input rst,
input en,
output reg count
);
initial begin
count <= 0;
end
always @(posedge clk) begin
if (rst) begin
count <= 0 ;
end else if (en) begin
if (count != 1) begin
count <= count + 1;
end else begin
count <= count;
end
end else begin
count <= count;
end
end
endmodule | module latch_counter
(
input clk,
input rst,
input en,
output reg count
); |
initial begin
count <= 0;
end
always @(posedge clk) begin
if (rst) begin
count <= 0 ;
end else if (en) begin
if (count != 1) begin
count <= count + 1;
end else begin
count <= count;
end
end else begin
count <= count;
end
end
endmodule | 0 |
138,258 | data/full_repos/permissive/82891137/led_unit.v | 82,891,137 | led_unit.v | v | 71 | 40 | [] | [] | [] | [(1, 71)] | null | null | 1: b"%Error: data/full_repos/permissive/82891137/led_unit.v:19: Cannot find file containing module: 'data_to_segment'\n data_to_segment #(\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82891137,data/full_repos/permissive/82891137/data_to_segment\n data/full_repos/permissive/82891137,data/full_repos/permissive/82891137/data_to_segment.v\n data/full_repos/permissive/82891137,data/full_repos/permissive/82891137/data_to_segment.sv\n data_to_segment\n data_to_segment.v\n data_to_segment.sv\n obj_dir/data_to_segment\n obj_dir/data_to_segment.v\n obj_dir/data_to_segment.sv\n%Error: Exiting due to 1 error(s)\n" | 302,089 | module | module led_unit
#(parameter DATA_WIDTH = 32)
(
input clk_src,
input [(DATA_WIDTH-1):0] led_data,
output reg [7:0] anodes,
output reg [7:0] cnodes
);
reg [2:0] count;
wire [(DATA_WIDTH*2)-1:0] seg_data;
initial begin
count <= 0;
anodes <= 0;
cnodes <= 0;
end
data_to_segment #(
.DATA_WIDTH(DATA_WIDTH)
) data_to_segment (
.data(led_data),
.seg_data(seg_data)
);
always @(posedge clk_src) begin
count = count + 1;
end
always @(count) begin
case (count)
3'b000: begin
anodes = 8'b11111110;
cnodes = seg_data[7:0];
end
3'b001: begin
anodes = 8'b11111101;
cnodes = seg_data[15:8];
end
3'b010: begin
anodes = 8'b11111011;
cnodes = seg_data[23:16];
end
3'b011: begin
anodes = 8'b11110111;
cnodes = seg_data[31:24];
end
3'b100: begin
anodes = 8'b11101111;
cnodes = seg_data[39:32];
end
3'b101: begin
anodes = 8'b11011111;
cnodes = seg_data[47:40];
end
3'b110: begin
anodes = 8'b10111111;
cnodes = seg_data[55:48];
end
3'b111: begin
anodes = 8'b01111111;
cnodes = seg_data[63:56];
end
default: begin
anodes = 8'b11111110;
cnodes = 8'b11111111;
end
endcase
end
endmodule | module led_unit
#(parameter DATA_WIDTH = 32)
(
input clk_src,
input [(DATA_WIDTH-1):0] led_data,
output reg [7:0] anodes,
output reg [7:0] cnodes
); |
reg [2:0] count;
wire [(DATA_WIDTH*2)-1:0] seg_data;
initial begin
count <= 0;
anodes <= 0;
cnodes <= 0;
end
data_to_segment #(
.DATA_WIDTH(DATA_WIDTH)
) data_to_segment (
.data(led_data),
.seg_data(seg_data)
);
always @(posedge clk_src) begin
count = count + 1;
end
always @(count) begin
case (count)
3'b000: begin
anodes = 8'b11111110;
cnodes = seg_data[7:0];
end
3'b001: begin
anodes = 8'b11111101;
cnodes = seg_data[15:8];
end
3'b010: begin
anodes = 8'b11111011;
cnodes = seg_data[23:16];
end
3'b011: begin
anodes = 8'b11110111;
cnodes = seg_data[31:24];
end
3'b100: begin
anodes = 8'b11101111;
cnodes = seg_data[39:32];
end
3'b101: begin
anodes = 8'b11011111;
cnodes = seg_data[47:40];
end
3'b110: begin
anodes = 8'b10111111;
cnodes = seg_data[55:48];
end
3'b111: begin
anodes = 8'b01111111;
cnodes = seg_data[63:56];
end
default: begin
anodes = 8'b11111110;
cnodes = 8'b11111111;
end
endcase
end
endmodule | 0 |
138,259 | data/full_repos/permissive/82891137/regfile.v | 82,891,137 | regfile.v | v | 52 | 92 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/82891137/regfile.v:30: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/82891137,data/full_repos/permissive/82891137/defines.vh\n data/full_repos/permissive/82891137,data/full_repos/permissive/82891137/defines.vh.v\n data/full_repos/permissive/82891137,data/full_repos/permissive/82891137/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/82891137/regfile.v:48: Define or directive not defined: \'`V0\'\n assign v0_data = regfile[`V0];\n ^~~\n%Error: data/full_repos/permissive/82891137/regfile.v:48: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign v0_data = regfile[`V0];\n ^\n%Error: data/full_repos/permissive/82891137/regfile.v:49: Define or directive not defined: \'`A0\'\n assign a0_data = regfile[`A0];\n ^~~\n%Error: data/full_repos/permissive/82891137/regfile.v:49: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign a0_data = regfile[`A0];\n ^\n%Error: Exiting due to 5 error(s)\n' | 302,090 | module | module regfile
#(parameter DATA_WIDTH = 32)
(
input clk,
input rst,
input we,
input [4:0] raddrA,
input [4:0] raddrB,
input [4:0] waddr,
input [DATA_WIDTH-1:0] wdata,
output [DATA_WIDTH-1:0] regA,
output [DATA_WIDTH-1:0] regB,
output [DATA_WIDTH-1:0] v0_data,
output [DATA_WIDTH-1:0] a0_data
);
`include "defines.vh"
reg [4:0] i;
reg [DATA_WIDTH-1:0] regfile [0:31];
always @ (posedge clk) begin
if (rst) begin
for (i = 0; i < 31; i = i + 1)
begin
regfile[i] <= 0;
end
end else if (we && waddr != 0) begin
regfile[waddr] <= wdata;
end
end
assign regA = (raddrA != 0) ? regfile[raddrA] : 0;
assign regB = (raddrB != 0) ? regfile[raddrB] : 0;
assign v0_data = regfile[`V0];
assign a0_data = regfile[`A0];
endmodule | module regfile
#(parameter DATA_WIDTH = 32)
(
input clk,
input rst,
input we,
input [4:0] raddrA,
input [4:0] raddrB,
input [4:0] waddr,
input [DATA_WIDTH-1:0] wdata,
output [DATA_WIDTH-1:0] regA,
output [DATA_WIDTH-1:0] regB,
output [DATA_WIDTH-1:0] v0_data,
output [DATA_WIDTH-1:0] a0_data
); |
`include "defines.vh"
reg [4:0] i;
reg [DATA_WIDTH-1:0] regfile [0:31];
always @ (posedge clk) begin
if (rst) begin
for (i = 0; i < 31; i = i + 1)
begin
regfile[i] <= 0;
end
end else if (we && waddr != 0) begin
regfile[waddr] <= wdata;
end
end
assign regA = (raddrA != 0) ? regfile[raddrA] : 0;
assign regB = (raddrB != 0) ? regfile[raddrB] : 0;
assign v0_data = regfile[`V0];
assign a0_data = regfile[`A0];
endmodule | 0 |
138,260 | data/full_repos/permissive/82891137/register.v | 82,891,137 | register.v | v | 32 | 38 | [] | [] | [] | [(11, 31)] | null | data/verilator_xmls/0625c5c4-282f-47e8-96d8-abb3227caf86.xml | null | 302,091 | module | module register
#(parameter DATA_WIDTH = 32)
(
input clk,
input rst,
input en,
input [DATA_WIDTH-1:0] din,
output reg [DATA_WIDTH-1:0] dout
);
always @ (posedge clk) begin
if (rst) begin
dout <= 0;
end else if (en) begin
dout <= din;
end else begin
dout <= dout;
end
end
endmodule | module register
#(parameter DATA_WIDTH = 32)
(
input clk,
input rst,
input en,
input [DATA_WIDTH-1:0] din,
output reg [DATA_WIDTH-1:0] dout
); |
always @ (posedge clk) begin
if (rst) begin
dout <= 0;
end else if (en) begin
dout <= din;
end else begin
dout <= dout;
end
end
endmodule | 0 |
138,261 | data/full_repos/permissive/82891137/tick_divider.v | 82,891,137 | tick_divider.v | v | 15 | 45 | [] | [] | [] | [(1, 15)] | null | data/verilator_xmls/a5800a99-daf7-4138-afa2-3ba44cdcdaec.xml | null | 302,092 | module | module tick_divider
#(parameter DATA_WIDTH = 32)
(
input clk_src,
output reg [(DATA_WIDTH-1): 0] clk_group
);
initial begin
clk_group <= {(DATA_WIDTH){1'b0}};
end
always @(posedge clk_src) begin
clk_group <= clk_group + 1;
end
endmodule | module tick_divider
#(parameter DATA_WIDTH = 32)
(
input clk_src,
output reg [(DATA_WIDTH-1): 0] clk_group
); |
initial begin
clk_group <= {(DATA_WIDTH){1'b0}};
end
always @(posedge clk_src) begin
clk_group <= clk_group + 1;
end
endmodule | 0 |
138,262 | data/full_repos/permissive/83113169/cordic1/verilog/cordic.v | 83,113,169 | cordic.v | v | 458 | 61 | [] | [] | [] | null | None: at end of input | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/83113169/cordic1/verilog/cordic.v:98: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 14 bits.\n : ... In instance cordic\n z0<=deg[16-3:0];\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 302,096 | module | module cordic(deg,clk,rst_n,sin,cos);
`define WIDTH 16
input [`WIDTH-1:0] deg;
input clk;
input rst_n;
output reg [`WIDTH-1:0] sin;
output reg [`WIDTH-1:0] cos;
reg [1:0] quadrant [`WIDTH-1:0];
reg [`WIDTH-1:0] x0;
reg [`WIDTH-1:0] y0;
reg [`WIDTH-1:0] z0;
reg [`WIDTH-1:0] x1;
reg [`WIDTH-1:0] y1;
reg [`WIDTH-1:0] z1;
reg [`WIDTH-1:0] x2;
reg [`WIDTH-1:0] y2;
reg [`WIDTH-1:0] z2;
reg [`WIDTH-1:0] x3;
reg [`WIDTH-1:0] y3;
reg [`WIDTH-1:0] z3;
reg [`WIDTH-1:0] x4;
reg [`WIDTH-1:0] y4;
reg [`WIDTH-1:0] z4;
reg [`WIDTH-1:0] x5;
reg [`WIDTH-1:0] y5;
reg [`WIDTH-1:0] z5;
reg [`WIDTH-1:0] x6;
reg [`WIDTH-1:0] y6;
reg [`WIDTH-1:0] z6;
reg [`WIDTH-1:0] x7;
reg [`WIDTH-1:0] y7;
reg [`WIDTH-1:0] z7;
reg [`WIDTH-1:0] x8;
reg [`WIDTH-1:0] y8;
reg [`WIDTH-1:0] z8;
reg [`WIDTH-1:0] x9;
reg [`WIDTH-1:0] y9;
reg [`WIDTH-1:0] z9;
reg [`WIDTH-1:0] x10;
reg [`WIDTH-1:0] y10;
reg [`WIDTH-1:0] z10;
reg [`WIDTH-1:0] x11;
reg [`WIDTH-1:0] y11;
reg [`WIDTH-1:0] z11;
reg [`WIDTH-1:0] x12;
reg [`WIDTH-1:0] y12;
reg [`WIDTH-1:0] z12;
reg [`WIDTH-1:0] x13;
reg [`WIDTH-1:0] y13;
reg [`WIDTH-1:0] z13;
reg [`WIDTH-1:0] x14;
reg [`WIDTH-1:0] y14;
reg [`WIDTH-1:0] z14;
reg [`WIDTH-1:0] x15;
reg [`WIDTH-1:0] y15;
reg [`WIDTH-1:0] z15;
`define rot0 16'h2000
`define rot1 16'h12e4
`define rot2 16'h09fb
`define rot3 16'h0511
`define rot4 16'h028b
`define rot5 16'h0146
`define rot6 16'h00a3
`define rot7 16'h0051
`define rot8 16'h0029
`define rot9 16'h0014
`define rot10 16'h000a
`define rot11 16'h0005
`define rot12 16'h0003
`define rot13 16'h0001
`define rot14 16'h0001
`define rot15 16'h0000
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x0<=0;
y0<=0;
z0=0;
end
else begin
x0<=16'h4dba;
y0<=0;
z0<=deg[`WIDTH-3:0];
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x1<=0;
y1<=0;
z1=0;
end
else
if(z0[`WIDTH-1]==1'b0)begin
x1<=x0-(y0>>0);
y1<=y0+(x0>>0);
z1<=z0-`rot0;
end
else begin
x1<=x0+(y0>>0);
y1<=y0-(x0>>0);
z1<=z0+`rot0;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x2<=0;
y2<=0;
z2=0;
end
else
if(z1[`WIDTH-1]==1'b0)begin
x2<=x1-(y1>>1);
y2<=y1+(x1>>1);
z2<=z1-`rot1;
end
else begin
x2<=x1+(y1>>1);
y2<=y1-(x1>>1);
z2<=z1+`rot1;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x3<=0;
y3<=0;
z3=0;
end
else
if(z2[`WIDTH-1]==1'b0)begin
x3<=x2-(y2>>2);
y3<=y2+(x2>>2);
z3<=z2-`rot2;
end
else begin
x3<=x2+(y2>>2);
y3<=y2-(x2>>2);
z3<=z2+`rot2;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x4<=0;
y4<=0;
z4=0;
end
else
if(z3[`WIDTH-1]==1'b0)begin
x4<=x3-(y3>>3);
y4<=y3+(x3>>3);
z4<=z3-`rot3;
end
else begin
x4<=x3+(y3>>3);
y4<=y3-(x3>>3);
z4<=z3+`rot3;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x5<=0;
y5<=0;
z5=0;
end
else
if(z4[`WIDTH-1]==1'b0)begin
x5<=x4-(y4>>4);
y5<=y4+(x4>>4);
z5<=z4-`rot4;
end
else begin
x5<=x4+(y4>>4);
y5<=y4-(x4>>4);
z5<=z4+`rot4;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x6<=0;
y6<=0;
z6=0;
end
else
if(z5[`WIDTH-1]==1'b0)begin
x6<=x5-(y5>>5);
y6<=y5+(x5>>5);
z6<=z5-`rot5;
end
else begin
x6<=x5+(y5>>5);
y6<=y5-(x5>>5);
z6<=z5+`rot5;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x7<=0;
y7<=0;
z7=0;
end
else
if(z6[`WIDTH-1]==1'b0)begin
x7<=x6-(y6>>6);
y7<=y6+(x6>>6);
z7<=z6-`rot6;
end
else begin
x7<=x6+(y6>>6);
y7<=y6-(x6>>6);
z7<=z6+`rot6;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x8<=0;
y8<=0;
z8=0;
end
else
if(z7[`WIDTH-1]==1'b0)begin
x8<=x7-(y7>>7);
y8<=y7+(x7>>7);
z8<=z7-`rot7;
end
else begin
x8<=x7+(y7>>7);
y8<=y7-(x7>>7);
z8<=z7+`rot7;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x9<=0;
y9<=0;
z9=0;
end
else
if(z8[`WIDTH-1]==1'b0)begin
x9<=x8-(y8>>8);
y9<=y8+(x8>>8);
z9<=z8-`rot8;
end
else begin
x9<=x8+(y8>>8);
y9<=y8-(x8>>8);
z9<=z8+`rot8;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x10<=0;
y10<=0;
z10=0;
end
else
if(z9[`WIDTH-1]==1'b0)begin
x10<=x9-(y9>>9);
y10<=y9+(x9>>9);
z10<=z9-`rot9;
end
else begin
x10<=x9+(y9>>9);
y10<=y9-(x9>>9);
z10<=z9+`rot9;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x11<=0;
y11<=0;
z11=0;
end
else
if(z10[`WIDTH-1]==1'b0)begin
x11<=x10-(y10>>10);
y11<=y10+(x10>>10);
z11<=z10-`rot10;
end
else begin
x11<=x10+(y10>>10);
y11<=y10-(x10>>10);
z11<=z10+`rot10;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x12<=0;
y12<=0;
z12=0;
end
else
if(z11[`WIDTH-1]==1'b0)begin
x12<=x11-(y11>>11);
y12<=y11+(x11>>11);
z12<=z11-`rot11;
end
else begin
x12<=x11+(y11>>11);
y12<=y11-(x11>>11);
z12<=z11+`rot11;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x13<=0;
y13<=0;
z13=0;
end
else
if(z12[`WIDTH-1]==1'b0)begin
x13<=x12-(y12>>12);
y13<=y12+(x12>>12);
z13<=z12-`rot12;
end
else begin
x13<=x12+(y12>>12);
y13<=y12-(x12>>12);
z13<=z12+`rot12;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x14<=0;
y14<=0;
z14=0;
end
else
if(z13[`WIDTH-1]==1'b0)begin
x14<=x13-(y13>>13);
y14<=y13+(x13>>13);
z14<=z13-`rot13;
end
else begin
x14<=x13+(y13>>13);
y14<=y13-(x13>>13);
z14<=z13+`rot13;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x15<=0;
y15<=0;
z15=0;
end
else
if(z14[`WIDTH-1]==1'b0)begin
x15<=x14-(y14>>14);
y15<=y14+(x14>>14);
z15<=z14-`rot14;
end
else begin
x15<=x14+(y14>>14);
y15<=y14-(x14>>14);
z15<=z14+`rot14;
end
end
always @(*)begin
if(x15>=16'b0111111111111111)
x15<=16'b0111111111111111;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
quadrant[0]<=2'b0;
quadrant[1]<=2'b0;
quadrant[2]<=2'b0;
quadrant[3]<=2'b0;
quadrant[4]<=2'b0;
quadrant[5]<=2'b0;
quadrant[6]<=2'b0;
quadrant[7]<=2'b0;
quadrant[8]<=2'b0;
quadrant[9]<=2'b0;
quadrant[10]<=2'b0;
quadrant[11]<=2'b0;
quadrant[12]<=2'b0;
quadrant[13]<=2'b0;
quadrant[14]<=2'b0;
quadrant[15]<=2'b0;
end
else begin
quadrant[0]<=deg[`WIDTH-1:`WIDTH-2];
quadrant[1]<=quadrant[0];
quadrant[2]<=quadrant[1];
quadrant[3]<=quadrant[2];
quadrant[4]<=quadrant[3];
quadrant[5]<=quadrant[4];
quadrant[6]<=quadrant[5];
quadrant[7]<=quadrant[6];
quadrant[8]<=quadrant[7];
quadrant[9]<=quadrant[8];
quadrant[10]<=quadrant[9];
quadrant[11]<=quadrant[10];
quadrant[12]<=quadrant[11];
quadrant[13]<=quadrant[12];
quadrant[14]<=quadrant[13];
quadrant[15]<=quadrant[14];
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
end
else
case(quadrant[15])
2'b00:begin
cos <= x15;
sin <= y15;
end
2'b01:begin
cos <= ~(y15) + 1'b1;
sin <= x15;
end
2'b10:begin
cos <= ~(x15) + 1'b1;
sin <= ~(y15) + 1'b1;
end
2'b11:begin
cos <= y15;
sin <= ~(x15) + 1'b1;
end
endcase
end
endmodule | module cordic(deg,clk,rst_n,sin,cos); |
`define WIDTH 16
input [`WIDTH-1:0] deg;
input clk;
input rst_n;
output reg [`WIDTH-1:0] sin;
output reg [`WIDTH-1:0] cos;
reg [1:0] quadrant [`WIDTH-1:0];
reg [`WIDTH-1:0] x0;
reg [`WIDTH-1:0] y0;
reg [`WIDTH-1:0] z0;
reg [`WIDTH-1:0] x1;
reg [`WIDTH-1:0] y1;
reg [`WIDTH-1:0] z1;
reg [`WIDTH-1:0] x2;
reg [`WIDTH-1:0] y2;
reg [`WIDTH-1:0] z2;
reg [`WIDTH-1:0] x3;
reg [`WIDTH-1:0] y3;
reg [`WIDTH-1:0] z3;
reg [`WIDTH-1:0] x4;
reg [`WIDTH-1:0] y4;
reg [`WIDTH-1:0] z4;
reg [`WIDTH-1:0] x5;
reg [`WIDTH-1:0] y5;
reg [`WIDTH-1:0] z5;
reg [`WIDTH-1:0] x6;
reg [`WIDTH-1:0] y6;
reg [`WIDTH-1:0] z6;
reg [`WIDTH-1:0] x7;
reg [`WIDTH-1:0] y7;
reg [`WIDTH-1:0] z7;
reg [`WIDTH-1:0] x8;
reg [`WIDTH-1:0] y8;
reg [`WIDTH-1:0] z8;
reg [`WIDTH-1:0] x9;
reg [`WIDTH-1:0] y9;
reg [`WIDTH-1:0] z9;
reg [`WIDTH-1:0] x10;
reg [`WIDTH-1:0] y10;
reg [`WIDTH-1:0] z10;
reg [`WIDTH-1:0] x11;
reg [`WIDTH-1:0] y11;
reg [`WIDTH-1:0] z11;
reg [`WIDTH-1:0] x12;
reg [`WIDTH-1:0] y12;
reg [`WIDTH-1:0] z12;
reg [`WIDTH-1:0] x13;
reg [`WIDTH-1:0] y13;
reg [`WIDTH-1:0] z13;
reg [`WIDTH-1:0] x14;
reg [`WIDTH-1:0] y14;
reg [`WIDTH-1:0] z14;
reg [`WIDTH-1:0] x15;
reg [`WIDTH-1:0] y15;
reg [`WIDTH-1:0] z15;
`define rot0 16'h2000
`define rot1 16'h12e4
`define rot2 16'h09fb
`define rot3 16'h0511
`define rot4 16'h028b
`define rot5 16'h0146
`define rot6 16'h00a3
`define rot7 16'h0051
`define rot8 16'h0029
`define rot9 16'h0014
`define rot10 16'h000a
`define rot11 16'h0005
`define rot12 16'h0003
`define rot13 16'h0001
`define rot14 16'h0001
`define rot15 16'h0000
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x0<=0;
y0<=0;
z0=0;
end
else begin
x0<=16'h4dba;
y0<=0;
z0<=deg[`WIDTH-3:0];
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x1<=0;
y1<=0;
z1=0;
end
else
if(z0[`WIDTH-1]==1'b0)begin
x1<=x0-(y0>>0);
y1<=y0+(x0>>0);
z1<=z0-`rot0;
end
else begin
x1<=x0+(y0>>0);
y1<=y0-(x0>>0);
z1<=z0+`rot0;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x2<=0;
y2<=0;
z2=0;
end
else
if(z1[`WIDTH-1]==1'b0)begin
x2<=x1-(y1>>1);
y2<=y1+(x1>>1);
z2<=z1-`rot1;
end
else begin
x2<=x1+(y1>>1);
y2<=y1-(x1>>1);
z2<=z1+`rot1;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x3<=0;
y3<=0;
z3=0;
end
else
if(z2[`WIDTH-1]==1'b0)begin
x3<=x2-(y2>>2);
y3<=y2+(x2>>2);
z3<=z2-`rot2;
end
else begin
x3<=x2+(y2>>2);
y3<=y2-(x2>>2);
z3<=z2+`rot2;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x4<=0;
y4<=0;
z4=0;
end
else
if(z3[`WIDTH-1]==1'b0)begin
x4<=x3-(y3>>3);
y4<=y3+(x3>>3);
z4<=z3-`rot3;
end
else begin
x4<=x3+(y3>>3);
y4<=y3-(x3>>3);
z4<=z3+`rot3;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x5<=0;
y5<=0;
z5=0;
end
else
if(z4[`WIDTH-1]==1'b0)begin
x5<=x4-(y4>>4);
y5<=y4+(x4>>4);
z5<=z4-`rot4;
end
else begin
x5<=x4+(y4>>4);
y5<=y4-(x4>>4);
z5<=z4+`rot4;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x6<=0;
y6<=0;
z6=0;
end
else
if(z5[`WIDTH-1]==1'b0)begin
x6<=x5-(y5>>5);
y6<=y5+(x5>>5);
z6<=z5-`rot5;
end
else begin
x6<=x5+(y5>>5);
y6<=y5-(x5>>5);
z6<=z5+`rot5;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x7<=0;
y7<=0;
z7=0;
end
else
if(z6[`WIDTH-1]==1'b0)begin
x7<=x6-(y6>>6);
y7<=y6+(x6>>6);
z7<=z6-`rot6;
end
else begin
x7<=x6+(y6>>6);
y7<=y6-(x6>>6);
z7<=z6+`rot6;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x8<=0;
y8<=0;
z8=0;
end
else
if(z7[`WIDTH-1]==1'b0)begin
x8<=x7-(y7>>7);
y8<=y7+(x7>>7);
z8<=z7-`rot7;
end
else begin
x8<=x7+(y7>>7);
y8<=y7-(x7>>7);
z8<=z7+`rot7;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x9<=0;
y9<=0;
z9=0;
end
else
if(z8[`WIDTH-1]==1'b0)begin
x9<=x8-(y8>>8);
y9<=y8+(x8>>8);
z9<=z8-`rot8;
end
else begin
x9<=x8+(y8>>8);
y9<=y8-(x8>>8);
z9<=z8+`rot8;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x10<=0;
y10<=0;
z10=0;
end
else
if(z9[`WIDTH-1]==1'b0)begin
x10<=x9-(y9>>9);
y10<=y9+(x9>>9);
z10<=z9-`rot9;
end
else begin
x10<=x9+(y9>>9);
y10<=y9-(x9>>9);
z10<=z9+`rot9;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x11<=0;
y11<=0;
z11=0;
end
else
if(z10[`WIDTH-1]==1'b0)begin
x11<=x10-(y10>>10);
y11<=y10+(x10>>10);
z11<=z10-`rot10;
end
else begin
x11<=x10+(y10>>10);
y11<=y10-(x10>>10);
z11<=z10+`rot10;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x12<=0;
y12<=0;
z12=0;
end
else
if(z11[`WIDTH-1]==1'b0)begin
x12<=x11-(y11>>11);
y12<=y11+(x11>>11);
z12<=z11-`rot11;
end
else begin
x12<=x11+(y11>>11);
y12<=y11-(x11>>11);
z12<=z11+`rot11;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x13<=0;
y13<=0;
z13=0;
end
else
if(z12[`WIDTH-1]==1'b0)begin
x13<=x12-(y12>>12);
y13<=y12+(x12>>12);
z13<=z12-`rot12;
end
else begin
x13<=x12+(y12>>12);
y13<=y12-(x12>>12);
z13<=z12+`rot12;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x14<=0;
y14<=0;
z14=0;
end
else
if(z13[`WIDTH-1]==1'b0)begin
x14<=x13-(y13>>13);
y14<=y13+(x13>>13);
z14<=z13-`rot13;
end
else begin
x14<=x13+(y13>>13);
y14<=y13-(x13>>13);
z14<=z13+`rot13;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
x15<=0;
y15<=0;
z15=0;
end
else
if(z14[`WIDTH-1]==1'b0)begin
x15<=x14-(y14>>14);
y15<=y14+(x14>>14);
z15<=z14-`rot14;
end
else begin
x15<=x14+(y14>>14);
y15<=y14-(x14>>14);
z15<=z14+`rot14;
end
end
always @(*)begin
if(x15>=16'b0111111111111111)
x15<=16'b0111111111111111;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
quadrant[0]<=2'b0;
quadrant[1]<=2'b0;
quadrant[2]<=2'b0;
quadrant[3]<=2'b0;
quadrant[4]<=2'b0;
quadrant[5]<=2'b0;
quadrant[6]<=2'b0;
quadrant[7]<=2'b0;
quadrant[8]<=2'b0;
quadrant[9]<=2'b0;
quadrant[10]<=2'b0;
quadrant[11]<=2'b0;
quadrant[12]<=2'b0;
quadrant[13]<=2'b0;
quadrant[14]<=2'b0;
quadrant[15]<=2'b0;
end
else begin
quadrant[0]<=deg[`WIDTH-1:`WIDTH-2];
quadrant[1]<=quadrant[0];
quadrant[2]<=quadrant[1];
quadrant[3]<=quadrant[2];
quadrant[4]<=quadrant[3];
quadrant[5]<=quadrant[4];
quadrant[6]<=quadrant[5];
quadrant[7]<=quadrant[6];
quadrant[8]<=quadrant[7];
quadrant[9]<=quadrant[8];
quadrant[10]<=quadrant[9];
quadrant[11]<=quadrant[10];
quadrant[12]<=quadrant[11];
quadrant[13]<=quadrant[12];
quadrant[14]<=quadrant[13];
quadrant[15]<=quadrant[14];
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
end
else
case(quadrant[15])
2'b00:begin
cos <= x15;
sin <= y15;
end
2'b01:begin
cos <= ~(y15) + 1'b1;
sin <= x15;
end
2'b10:begin
cos <= ~(x15) + 1'b1;
sin <= ~(y15) + 1'b1;
end
2'b11:begin
cos <= y15;
sin <= ~(x15) + 1'b1;
end
endcase
end
endmodule | 0 |
138,263 | data/full_repos/permissive/83113169/cordic1/verilog/cordic_tb.v | 83,113,169 | cordic_tb.v | v | 37 | 67 | [] | [] | [] | [(3, 37)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/83113169/cordic1/verilog/cordic_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n #30 rst_n=1\'b0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/83113169/cordic1/verilog/cordic_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n #30 rst_n=1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83113169/cordic1/verilog/cordic_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #5 clk=!clk;\n ^\n%Error: data/full_repos/permissive/83113169/cordic1/verilog/cordic_tb.v:9: Cannot find file containing module: \'cordic\'\n cordic U1(.deg(deg),.clk(clk),.rst_n(rst_n),.sin(sin),.cos(cos));\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/83113169/cordic1/verilog,data/full_repos/permissive/83113169/cordic\n data/full_repos/permissive/83113169/cordic1/verilog,data/full_repos/permissive/83113169/cordic.v\n data/full_repos/permissive/83113169/cordic1/verilog,data/full_repos/permissive/83113169/cordic.sv\n cordic\n cordic.v\n cordic.sv\n obj_dir/cordic\n obj_dir/cordic.v\n obj_dir/cordic.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,097 | module | module cordic_tb;
wire [15:0] sin;
wire [15:0] cos;
reg [15:0] deg;
reg clk;
reg rst_n;
cordic U1(.deg(deg),.clk(clk),.rst_n(rst_n),.sin(sin),.cos(cos));
initial begin
deg=0;
clk=0;
rst_n=1'b1;
#30 rst_n=1'b0;
#30 rst_n=1'b1;
end
always
#5 clk=!clk;
endmodule | module cordic_tb; |
wire [15:0] sin;
wire [15:0] cos;
reg [15:0] deg;
reg clk;
reg rst_n;
cordic U1(.deg(deg),.clk(clk),.rst_n(rst_n),.sin(sin),.cos(cos));
initial begin
deg=0;
clk=0;
rst_n=1'b1;
#30 rst_n=1'b0;
#30 rst_n=1'b1;
end
always
#5 clk=!clk;
endmodule | 0 |
138,264 | data/full_repos/permissive/83113169/cordic2/butterfly/butterfly_loc.v | 83,113,169 | butterfly_loc.v | v | 38 | 63 | [] | [] | [] | [(1, 37)] | null | data/verilator_xmls/37f32460-9f07-45a3-9688-5bbf5d746873.xml | null | 302,098 | module | module butterfly_loc
#(parameter shift_num=8)
(X_in,Y_in,b,clk,rst_n,X_out,Y_out);
`define WIDTH 22
input [`WIDTH-1:0] X_in;
input [`WIDTH-1:0] Y_in;
input b;
input clk;
input rst_n;
output reg [`WIDTH-1:0] X_out;
output reg [`WIDTH-1:0] Y_out;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
X_out<=0;
Y_out<=0;
end
else begin
if(b==1'b1) begin
X_out<=X_in-(Y_in>>shift_num);
Y_out<=Y_in+(X_in>>shift_num);
end
else begin
X_out<=X_in+(Y_in>>shift_num);
Y_out<=Y_in-(X_in>>shift_num);
end
end
end
endmodule | module butterfly_loc
#(parameter shift_num=8)
(X_in,Y_in,b,clk,rst_n,X_out,Y_out); |
`define WIDTH 22
input [`WIDTH-1:0] X_in;
input [`WIDTH-1:0] Y_in;
input b;
input clk;
input rst_n;
output reg [`WIDTH-1:0] X_out;
output reg [`WIDTH-1:0] Y_out;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
X_out<=0;
Y_out<=0;
end
else begin
if(b==1'b1) begin
X_out<=X_in-(Y_in>>shift_num);
Y_out<=Y_in+(X_in>>shift_num);
end
else begin
X_out<=X_in+(Y_in>>shift_num);
Y_out<=Y_in-(X_in>>shift_num);
end
end
end
endmodule | 0 |
138,265 | data/full_repos/permissive/83113169/cordic2/butterfly/butterfly_step.v | 83,113,169 | butterfly_step.v | v | 44 | 78 | [] | [] | [] | [(1, 44)] | null | null | 1: b"%Error: data/full_repos/permissive/83113169/cordic2/butterfly/butterfly_step.v:19: Cannot find file containing module: 'butterfly_loc'\nbutterfly_loc\n^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83113169/cordic2/butterfly,data/full_repos/permissive/83113169/butterfly_loc\n data/full_repos/permissive/83113169/cordic2/butterfly,data/full_repos/permissive/83113169/butterfly_loc.v\n data/full_repos/permissive/83113169/cordic2/butterfly,data/full_repos/permissive/83113169/butterfly_loc.sv\n butterfly_loc\n butterfly_loc.v\n butterfly_loc.sv\n obj_dir/butterfly_loc\n obj_dir/butterfly_loc.v\n obj_dir/butterfly_loc.sv\n%Error: data/full_repos/permissive/83113169/cordic2/butterfly/butterfly_step.v:25: Cannot find file containing module: 'butterfly_loc'\nbutterfly_loc\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83113169/cordic2/butterfly/butterfly_step.v:30: Cannot find file containing module: 'butterfly_loc'\nbutterfly_loc\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83113169/cordic2/butterfly/butterfly_step.v:36: Cannot find file containing module: 'butterfly_loc'\nbutterfly_loc\n^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 302,099 | module | module butterfly_step(X5,Y5,clk,b,rst_n,X9,Y9);
`define WIDTH 22
input [`WIDTH-1:0] X5;
input [`WIDTH-1:0] Y5;
input [3:0] b;
input clk,rst_n;
output [`WIDTH-1:0] X9;
output [`WIDTH-1:0] Y9;
wire [`WIDTH-1:0] X6;
wire [`WIDTH-1:0] Y6;
wire [`WIDTH-1:0] X7;
wire [`WIDTH-1:0] Y7;
wire [`WIDTH-1:0] X8;
wire [`WIDTH-1:0] Y8;
butterfly_loc
#(.shift_num(5))
U1
(.X_in(X5),.Y_in(Y5),.b(b[3]),.clk(clk),.rst_n(rst_n),.X_out(X6),.Y_out(Y6));
butterfly_loc
#(.shift_num(6))
U2
(.X_in(X6),.Y_in(Y6),.b(b[2]),.clk(clk),.rst_n(rst_n),.X_out(X7),.Y_out(Y7));
butterfly_loc
#(.shift_num(7))
U3
(.X_in(X7),.Y_in(Y7),.b(b[1]),.clk(clk),.rst_n(rst_n),.X_out(X8),.Y_out(Y8));
butterfly_loc
#(.shift_num(8))
U4
(.X_in(X8),.Y_in(Y8),.b(b[0]),.clk(clk),.rst_n(rst_n),.X_out(X9),.Y_out(Y9));
endmodule | module butterfly_step(X5,Y5,clk,b,rst_n,X9,Y9); |
`define WIDTH 22
input [`WIDTH-1:0] X5;
input [`WIDTH-1:0] Y5;
input [3:0] b;
input clk,rst_n;
output [`WIDTH-1:0] X9;
output [`WIDTH-1:0] Y9;
wire [`WIDTH-1:0] X6;
wire [`WIDTH-1:0] Y6;
wire [`WIDTH-1:0] X7;
wire [`WIDTH-1:0] Y7;
wire [`WIDTH-1:0] X8;
wire [`WIDTH-1:0] Y8;
butterfly_loc
#(.shift_num(5))
U1
(.X_in(X5),.Y_in(Y5),.b(b[3]),.clk(clk),.rst_n(rst_n),.X_out(X6),.Y_out(Y6));
butterfly_loc
#(.shift_num(6))
U2
(.X_in(X6),.Y_in(Y6),.b(b[2]),.clk(clk),.rst_n(rst_n),.X_out(X7),.Y_out(Y7));
butterfly_loc
#(.shift_num(7))
U3
(.X_in(X7),.Y_in(Y7),.b(b[1]),.clk(clk),.rst_n(rst_n),.X_out(X8),.Y_out(Y8));
butterfly_loc
#(.shift_num(8))
U4
(.X_in(X8),.Y_in(Y8),.b(b[0]),.clk(clk),.rst_n(rst_n),.X_out(X9),.Y_out(Y9));
endmodule | 0 |
138,266 | data/full_repos/permissive/83113169/cordic2/cordic/adder.v | 83,113,169 | adder.v | v | 20 | 45 | [] | [] | [] | [(1, 20)] | null | data/verilator_xmls/d1663fbb-aeab-4335-bad8-d8726fbc10a2.xml | null | 302,100 | module | module adder(Fcw,clk,rst_n,out);
input [35:0] Fcw;
input clk;
input rst_n;
output reg [35:0] out;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
out<=0;
end
else begin
out=out+Fcw;
end
end
endmodule | module adder(Fcw,clk,rst_n,out); |
input [35:0] Fcw;
input clk;
input rst_n;
output reg [35:0] out;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
out<=0;
end
else begin
out=out+Fcw;
end
end
endmodule | 0 |
138,267 | data/full_repos/permissive/83113169/cordic2/cordic/cordic_improving.v | 83,113,169 | cordic_improving.v | v | 77 | 88 | [] | [] | [] | [(1, 73)] | null | null | 1: b"%Error: data/full_repos/permissive/83113169/cordic2/cordic/cordic_improving.v:17: Cannot find file containing module: 'adder'\nadder U1 (.Fcw(Fcw),.clk(clk),.rst_n(rst_n),.out(phi));\n^~~~~\n ... Looked in:\n data/full_repos/permissive/83113169/cordic2/cordic,data/full_repos/permissive/83113169/adder\n data/full_repos/permissive/83113169/cordic2/cordic,data/full_repos/permissive/83113169/adder.v\n data/full_repos/permissive/83113169/cordic2/cordic,data/full_repos/permissive/83113169/adder.sv\n adder\n adder.v\n adder.sv\n obj_dir/adder\n obj_dir/adder.v\n obj_dir/adder.sv\n%Error: data/full_repos/permissive/83113169/cordic2/cordic/cordic_improving.v:22: Cannot find file containing module: 'quarant_mirror'\nquarant_mirror U2(.in(phi1[18:0]),.MSB3(phi1[19]),.out(phi2),.clk(clk));\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83113169/cordic2/cordic/cordic_improving.v:27: Cannot find file containing module: 'multiplier'\nmultiplier U3(.in(phi2),.out(b),.clk(clk));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/83113169/cordic2/cordic/cordic_improving.v:31: Cannot find file containing module: 'cordic_rom'\n cordic_rom U4(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/83113169/cordic2/cordic/cordic_improving.v:38: Cannot find file containing module: 'butterfly_step'\nbutterfly_step U6(.X5(X5),.Y5(Y5),.clk(clk),.b(b[11:8]),.rst_n(rst_n),.X9(X9),.Y9(Y9));\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83113169/cordic2/cordic/cordic_improving.v:45: Cannot find file containing module: 'merge_step'\nmerge_step U7(.X9(X9),.Y9(Y9),.b(b[7:0]),.X17(X17),.Y17(Y17),.clk(clk));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/83113169/cordic2/cordic/cordic_improving.v:48: Cannot find file containing module: 'out_put'\nout_put U8(.X17(X17),.Y17(Y17),.MSB(phi1_4[21:19]),.cos(cos),.sin(sin),.clk(clk));\n^~~~~~~\n%Error: Exiting due to 7 error(s)\n" | 302,101 | module | module cordic_improving(Fcw,clk,rst_n,sin,cos);
input clk;
input rst_n;
input [35:0] Fcw;
wire [35:0] phi;
wire [21:0] phi1;
reg [21:0] phi1_1,phi1_2,phi1_3,phi1_4;
wire [18:0] phi2;
wire [15:0] b;
wire [21:0] X5,Y5,X9,Y9,X17,Y17;
output [15:0] sin,cos;
adder U1 (.Fcw(Fcw),.clk(clk),.rst_n(rst_n),.out(phi));
assign phi1 =phi[35:14] ;
quarant_mirror U2(.in(phi1[18:0]),.MSB3(phi1[19]),.out(phi2),.clk(clk));
multiplier U3(.in(phi2),.out(b),.clk(clk));
cordic_rom U4(
.address(b[15:12]),
.X5(X5),
.Y5(Y5),.clk(clk));
butterfly_step U6(.X5(X5),.Y5(Y5),.clk(clk),.b(b[11:8]),.rst_n(rst_n),.X9(X9),.Y9(Y9));
merge_step U7(.X9(X9),.Y9(Y9),.b(b[7:0]),.X17(X17),.Y17(Y17),.clk(clk));
out_put U8(.X17(X17),.Y17(Y17),.MSB(phi1_4[21:19]),.cos(cos),.sin(sin),.clk(clk));
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
phi1_1<=0;
phi1_2<=0;
phi1_3<=0;
phi1_4<=0;
end
else begin
phi1_1<=phi1;
phi1_2<=phi1_1;
phi1_3<=phi1_2;
phi1_4<=phi1_3;
end
end
endmodule | module cordic_improving(Fcw,clk,rst_n,sin,cos); |
input clk;
input rst_n;
input [35:0] Fcw;
wire [35:0] phi;
wire [21:0] phi1;
reg [21:0] phi1_1,phi1_2,phi1_3,phi1_4;
wire [18:0] phi2;
wire [15:0] b;
wire [21:0] X5,Y5,X9,Y9,X17,Y17;
output [15:0] sin,cos;
adder U1 (.Fcw(Fcw),.clk(clk),.rst_n(rst_n),.out(phi));
assign phi1 =phi[35:14] ;
quarant_mirror U2(.in(phi1[18:0]),.MSB3(phi1[19]),.out(phi2),.clk(clk));
multiplier U3(.in(phi2),.out(b),.clk(clk));
cordic_rom U4(
.address(b[15:12]),
.X5(X5),
.Y5(Y5),.clk(clk));
butterfly_step U6(.X5(X5),.Y5(Y5),.clk(clk),.b(b[11:8]),.rst_n(rst_n),.X9(X9),.Y9(Y9));
merge_step U7(.X9(X9),.Y9(Y9),.b(b[7:0]),.X17(X17),.Y17(Y17),.clk(clk));
out_put U8(.X17(X17),.Y17(Y17),.MSB(phi1_4[21:19]),.cos(cos),.sin(sin),.clk(clk));
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
phi1_1<=0;
phi1_2<=0;
phi1_3<=0;
phi1_4<=0;
end
else begin
phi1_1<=phi1;
phi1_2<=phi1_1;
phi1_3<=phi1_2;
phi1_4<=phi1_3;
end
end
endmodule | 0 |
138,268 | data/full_repos/permissive/83113169/cordic2/cordic/multiplier.v | 83,113,169 | multiplier.v | v | 20 | 34 | [] | [] | [] | null | line:11: before: "posedge" | data/verilator_xmls/b5297192-4985-4cfe-a22d-5c5ee2620025.xml | null | 302,102 | module | module multiplier(in,out,clk);
input [18:0] in;
input clk;
output reg [15:0] out;
reg [21:0] tmp;
reg [21:0] tmp1;
reg [21:0] tmp2;
reg [21:0] tmp3;
reg [21:0] tmp4;
reg [21:0] tmp5;
always @(in or posedge clk) begin
tmp1<={in[18:0],3'b000}>>1;
tmp2<={in[18:0],3'b000}>>2;
tmp3<={in[18:0],3'b000}>>5;
tmp4<={in[18:0],3'b000}>>8;
tmp5<={in[18:0],3'b000}>>12;
tmp<=tmp1+tmp2+tmp3+tmp4+tmp5;
out<=tmp[21:6];
end
endmodule | module multiplier(in,out,clk); |
input [18:0] in;
input clk;
output reg [15:0] out;
reg [21:0] tmp;
reg [21:0] tmp1;
reg [21:0] tmp2;
reg [21:0] tmp3;
reg [21:0] tmp4;
reg [21:0] tmp5;
always @(in or posedge clk) begin
tmp1<={in[18:0],3'b000}>>1;
tmp2<={in[18:0],3'b000}>>2;
tmp3<={in[18:0],3'b000}>>5;
tmp4<={in[18:0],3'b000}>>8;
tmp5<={in[18:0],3'b000}>>12;
tmp<=tmp1+tmp2+tmp3+tmp4+tmp5;
out<=tmp[21:6];
end
endmodule | 0 |
138,269 | data/full_repos/permissive/83113169/cordic2/cordic/output.v | 83,113,169 | output.v | v | 49 | 41 | [] | [] | [] | [(1, 49)] | null | data/verilator_xmls/bce7d1a2-dd0c-4809-a5b5-0b501c9d80f1.xml | null | 302,103 | module | module out_put(X17,Y17,MSB,cos,sin,clk);
`define WIDTH 22
input [`WIDTH-1:0] X17;
input [`WIDTH-1:0] Y17;
input clk;
input [2:0] MSB;
output reg[15:0] cos;
output reg [15:0] sin;
always @(posedge clk) begin
case(MSB)
3'b000:begin
cos<=X17[21:6];
sin<=Y17[21:6];
end
3'b001:begin
cos<=Y17[21:6];
sin<=X17[21:6];
end
3'b010:begin
cos<=-Y17[21:6];
sin<=X17[21:6];
end
3'b011:begin
cos<=-X17[21:6];
sin<=Y17[21:6];
end
3'b100:begin
cos<=-X17[21:6];
sin<=-Y17[21:6];
end
3'b101:begin
cos<=-Y17[21:6];
sin<=-X17[21:6];
end
3'b110:begin
cos<=Y17[21:6];
sin<=-X17[21:6];
end
3'b111:begin
cos<=X17[21:6];
sin<=-Y17[21:6];
end
endcase
end
endmodule | module out_put(X17,Y17,MSB,cos,sin,clk); |
`define WIDTH 22
input [`WIDTH-1:0] X17;
input [`WIDTH-1:0] Y17;
input clk;
input [2:0] MSB;
output reg[15:0] cos;
output reg [15:0] sin;
always @(posedge clk) begin
case(MSB)
3'b000:begin
cos<=X17[21:6];
sin<=Y17[21:6];
end
3'b001:begin
cos<=Y17[21:6];
sin<=X17[21:6];
end
3'b010:begin
cos<=-Y17[21:6];
sin<=X17[21:6];
end
3'b011:begin
cos<=-X17[21:6];
sin<=Y17[21:6];
end
3'b100:begin
cos<=-X17[21:6];
sin<=-Y17[21:6];
end
3'b101:begin
cos<=-Y17[21:6];
sin<=-X17[21:6];
end
3'b110:begin
cos<=Y17[21:6];
sin<=-X17[21:6];
end
3'b111:begin
cos<=X17[21:6];
sin<=-Y17[21:6];
end
endcase
end
endmodule | 0 |
138,270 | data/full_repos/permissive/83113169/cordic2/cordic/quadrant_mirror.v | 83,113,169 | quadrant_mirror.v | v | 20 | 40 | [] | [] | [] | [(1, 19)] | null | data/verilator_xmls/27daec28-4b04-45bb-afca-4b02a637ff40.xml | null | 302,104 | module | module quarant_mirror(in,MSB3,out,clk);
input [18:0] in;
input clk;
input MSB3;
output reg [18:0] out;
always @(posedge clk)begin
if(MSB3==1'b0)begin
out<=in;
end
else begin
out<=(~in)+1'b1;
end
end
endmodule | module quarant_mirror(in,MSB3,out,clk); |
input [18:0] in;
input clk;
input MSB3;
output reg [18:0] out;
always @(posedge clk)begin
if(MSB3==1'b0)begin
out<=in;
end
else begin
out<=(~in)+1'b1;
end
end
endmodule | 0 |
138,271 | data/full_repos/permissive/83113169/cordic2/merge/merge_loc.v | 83,113,169 | merge_loc.v | v | 31 | 45 | [] | [] | [] | [(1, 30)] | null | data/verilator_xmls/0ab13d2e-ea75-455e-9419-27ccf42d245e.xml | null | 302,105 | module | module merge_loc
#(parameter shift_num=9)
(A_in,b,A_out,clk);
`define WIDTH 22
input [`WIDTH-1:0] A_in;
input clk;
input b;
output reg [`WIDTH-1:0] A_out;
always @(posedge clk)
begin
if (b==1'b1) begin
A_out=A_in>>shift_num;
end
else begin
A_out=~(A_in>>shift_num)+1;
end
end
endmodule | module merge_loc
#(parameter shift_num=9)
(A_in,b,A_out,clk); |
`define WIDTH 22
input [`WIDTH-1:0] A_in;
input clk;
input b;
output reg [`WIDTH-1:0] A_out;
always @(posedge clk)
begin
if (b==1'b1) begin
A_out=A_in>>shift_num;
end
else begin
A_out=~(A_in>>shift_num)+1;
end
end
endmodule | 0 |
138,272 | data/full_repos/permissive/83113169/cordic2/merge/merge_step.v | 83,113,169 | merge_step.v | v | 84 | 67 | [] | [] | [] | [(1, 83)] | null | null | 1: b"%Error: data/full_repos/permissive/83113169/cordic2/merge/merge_step.v:33: Cannot find file containing module: 'merge_loc'\nmerge_loc #(.shift_num(9))\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83113169/cordic2/merge,data/full_repos/permissive/83113169/merge_loc\n data/full_repos/permissive/83113169/cordic2/merge,data/full_repos/permissive/83113169/merge_loc.v\n data/full_repos/permissive/83113169/cordic2/merge,data/full_repos/permissive/83113169/merge_loc.sv\n merge_loc\n merge_loc.v\n merge_loc.sv\n obj_dir/merge_loc\n obj_dir/merge_loc.v\n obj_dir/merge_loc.sv\n%Error: data/full_repos/permissive/83113169/cordic2/merge/merge_step.v:35: Cannot find file containing module: 'merge_loc'\nmerge_loc #(.shift_num(10))\n^~~~~~~~~\n%Error: data/full_repos/permissive/83113169/cordic2/merge/merge_step.v:37: Cannot find file containing module: 'merge_loc'\nmerge_loc #(.shift_num(11))\n^~~~~~~~~\n%Error: data/full_repos/permissive/83113169/cordic2/merge/merge_step.v:39: Cannot find file containing module: 'merge_loc'\nmerge_loc #(.shift_num(12))\n^~~~~~~~~\n%Error: data/full_repos/permissive/83113169/cordic2/merge/merge_step.v:41: Cannot find file containing module: 'merge_loc'\nmerge_loc #(.shift_num(13))\n^~~~~~~~~\n%Error: data/full_repos/permissive/83113169/cordic2/merge/merge_step.v:43: Cannot find file containing module: 'merge_loc'\nmerge_loc #(.shift_num(14))\n^~~~~~~~~\n%Error: data/full_repos/permissive/83113169/cordic2/merge/merge_step.v:45: Cannot find file containing module: 'merge_loc'\nmerge_loc #(.shift_num(15))\n^~~~~~~~~\n%Error: data/full_repos/permissive/83113169/cordic2/merge/merge_step.v:47: Cannot find file containing module: 'merge_loc'\nmerge_loc #(.shift_num(16))\n^~~~~~~~~\n%Error: data/full_repos/permissive/83113169/cordic2/merge/merge_step.v:51: Cannot find file containing module: 'merge_loc'\nmerge_loc #(.shift_num(9))\n^~~~~~~~~\n%Error: data/full_repos/permissive/83113169/cordic2/merge/merge_step.v:53: Cannot find file containing module: 'merge_loc'\nmerge_loc #(.shift_num(10))\n^~~~~~~~~\n%Error: data/full_repos/permissive/83113169/cordic2/merge/merge_step.v:55: Cannot find file containing module: 'merge_loc'\nmerge_loc #(.shift_num(11))\n^~~~~~~~~\n%Error: data/full_repos/permissive/83113169/cordic2/merge/merge_step.v:57: Cannot find file containing module: 'merge_loc'\nmerge_loc #(.shift_num(12))\n^~~~~~~~~\n%Error: data/full_repos/permissive/83113169/cordic2/merge/merge_step.v:59: Cannot find file containing module: 'merge_loc'\nmerge_loc #(.shift_num(13))\n^~~~~~~~~\n%Error: data/full_repos/permissive/83113169/cordic2/merge/merge_step.v:61: Cannot find file containing module: 'merge_loc'\nmerge_loc #(.shift_num(14))\n^~~~~~~~~\n%Error: data/full_repos/permissive/83113169/cordic2/merge/merge_step.v:63: Cannot find file containing module: 'merge_loc'\nmerge_loc #(.shift_num(15))\n^~~~~~~~~\n%Error: data/full_repos/permissive/83113169/cordic2/merge/merge_step.v:65: Cannot find file containing module: 'merge_loc'\nmerge_loc #(.shift_num(16))\n^~~~~~~~~\n%Error: Exiting due to 16 error(s)\n" | 302,106 | module | module merge_step(X9,Y9,b,X17,Y17,clk);
`define WIDTH 22
input clk;
input [`WIDTH-1:0] X9;
input [`WIDTH-1:0] Y9;
input [7:0] b;
output reg [`WIDTH-1:0] X17;
output reg [`WIDTH-1:0] Y17;
wire [`WIDTH-1:0] tmpX10;
wire [`WIDTH-1:0] tmpX11;
wire [`WIDTH-1:0] tmpX12;
wire [`WIDTH-1:0] tmpX13;
wire [`WIDTH-1:0] tmpX14;
wire [`WIDTH-1:0] tmpX15;
wire [`WIDTH-1:0] tmpX16;
wire [`WIDTH-1:0] tmpX17;
wire [`WIDTH-1:0] tmpY10;
wire [`WIDTH-1:0] tmpY11;
wire [`WIDTH-1:0] tmpY12;
wire [`WIDTH-1:0] tmpY13;
wire [`WIDTH-1:0] tmpY14;
wire [`WIDTH-1:0] tmpY15;
wire [`WIDTH-1:0] tmpY16;
wire [`WIDTH-1:0] tmpY17;
merge_loc #(.shift_num(9))
M1 (.A_in(Y9),.b(b[7]),.A_out(tmpY10),.clk(clk));
merge_loc #(.shift_num(10))
M2 (.A_in(Y9),.b(b[6]),.A_out(tmpY11),.clk(clk));
merge_loc #(.shift_num(11))
M3 (.A_in(Y9),.b(b[5]),.A_out(tmpY12),.clk(clk));
merge_loc #(.shift_num(12))
M4 (.A_in(Y9),.b(b[4]),.A_out(tmpY13),.clk(clk));
merge_loc #(.shift_num(13))
M5 (.A_in(Y9),.b(b[3]),.A_out(tmpY14),.clk(clk));
merge_loc #(.shift_num(14))
M6 (.A_in(Y9),.b(b[2]),.A_out(tmpY15),.clk(clk));
merge_loc #(.shift_num(15))
M7 (.A_in(Y9),.b(b[1]),.A_out(tmpY16),.clk(clk));
merge_loc #(.shift_num(16))
M8 (.A_in(Y9),.b(b[0]),.A_out(tmpY17),.clk(clk));
merge_loc #(.shift_num(9))
M9 (.A_in(X9),.b(b[7]),.A_out(tmpX10),.clk(clk));
merge_loc #(.shift_num(10))
M10 (.A_in(X9),.b(b[6]),.A_out(tmpX11),.clk(clk));
merge_loc #(.shift_num(11))
M11 (.A_in(X9),.b(b[5]),.A_out(tmpX12),.clk(clk));
merge_loc #(.shift_num(12))
M12 (.A_in(X9),.b(b[4]),.A_out(tmpX13),.clk(clk));
merge_loc #(.shift_num(13))
M13 (.A_in(X9),.b(b[3]),.A_out(tmpX14),.clk(clk));
merge_loc #(.shift_num(14))
M14 (.A_in(X9),.b(b[2]),.A_out(tmpX15),.clk(clk));
merge_loc #(.shift_num(15))
M15 (.A_in(X9),.b(b[1]),.A_out(tmpX16),.clk(clk));
merge_loc #(.shift_num(16))
M16 (.A_in(X9),.b(b[0]),.A_out(tmpX17),.clk(clk));
always @(*)begin
if(X17>=22'b0111111111111111111111)
X17<=22'b0111111111111111111111;
end
always @(X9 or Y9) begin
X17<=X9-tmpY10-tmpY11-tmpY12-tmpY13-tmpY14-tmpY15-tmpY16-tmpY17;
Y17<=Y9+tmpX10+tmpX11+tmpX12+tmpX13+tmpX14+tmpX15+tmpX16+tmpX17;
end
endmodule | module merge_step(X9,Y9,b,X17,Y17,clk); |
`define WIDTH 22
input clk;
input [`WIDTH-1:0] X9;
input [`WIDTH-1:0] Y9;
input [7:0] b;
output reg [`WIDTH-1:0] X17;
output reg [`WIDTH-1:0] Y17;
wire [`WIDTH-1:0] tmpX10;
wire [`WIDTH-1:0] tmpX11;
wire [`WIDTH-1:0] tmpX12;
wire [`WIDTH-1:0] tmpX13;
wire [`WIDTH-1:0] tmpX14;
wire [`WIDTH-1:0] tmpX15;
wire [`WIDTH-1:0] tmpX16;
wire [`WIDTH-1:0] tmpX17;
wire [`WIDTH-1:0] tmpY10;
wire [`WIDTH-1:0] tmpY11;
wire [`WIDTH-1:0] tmpY12;
wire [`WIDTH-1:0] tmpY13;
wire [`WIDTH-1:0] tmpY14;
wire [`WIDTH-1:0] tmpY15;
wire [`WIDTH-1:0] tmpY16;
wire [`WIDTH-1:0] tmpY17;
merge_loc #(.shift_num(9))
M1 (.A_in(Y9),.b(b[7]),.A_out(tmpY10),.clk(clk));
merge_loc #(.shift_num(10))
M2 (.A_in(Y9),.b(b[6]),.A_out(tmpY11),.clk(clk));
merge_loc #(.shift_num(11))
M3 (.A_in(Y9),.b(b[5]),.A_out(tmpY12),.clk(clk));
merge_loc #(.shift_num(12))
M4 (.A_in(Y9),.b(b[4]),.A_out(tmpY13),.clk(clk));
merge_loc #(.shift_num(13))
M5 (.A_in(Y9),.b(b[3]),.A_out(tmpY14),.clk(clk));
merge_loc #(.shift_num(14))
M6 (.A_in(Y9),.b(b[2]),.A_out(tmpY15),.clk(clk));
merge_loc #(.shift_num(15))
M7 (.A_in(Y9),.b(b[1]),.A_out(tmpY16),.clk(clk));
merge_loc #(.shift_num(16))
M8 (.A_in(Y9),.b(b[0]),.A_out(tmpY17),.clk(clk));
merge_loc #(.shift_num(9))
M9 (.A_in(X9),.b(b[7]),.A_out(tmpX10),.clk(clk));
merge_loc #(.shift_num(10))
M10 (.A_in(X9),.b(b[6]),.A_out(tmpX11),.clk(clk));
merge_loc #(.shift_num(11))
M11 (.A_in(X9),.b(b[5]),.A_out(tmpX12),.clk(clk));
merge_loc #(.shift_num(12))
M12 (.A_in(X9),.b(b[4]),.A_out(tmpX13),.clk(clk));
merge_loc #(.shift_num(13))
M13 (.A_in(X9),.b(b[3]),.A_out(tmpX14),.clk(clk));
merge_loc #(.shift_num(14))
M14 (.A_in(X9),.b(b[2]),.A_out(tmpX15),.clk(clk));
merge_loc #(.shift_num(15))
M15 (.A_in(X9),.b(b[1]),.A_out(tmpX16),.clk(clk));
merge_loc #(.shift_num(16))
M16 (.A_in(X9),.b(b[0]),.A_out(tmpX17),.clk(clk));
always @(*)begin
if(X17>=22'b0111111111111111111111)
X17<=22'b0111111111111111111111;
end
always @(X9 or Y9) begin
X17<=X9-tmpY10-tmpY11-tmpY12-tmpY13-tmpY14-tmpY15-tmpY16-tmpY17;
Y17<=Y9+tmpX10+tmpX11+tmpX12+tmpX13+tmpX14+tmpX15+tmpX16+tmpX17;
end
endmodule | 0 |
138,273 | data/full_repos/permissive/83113169/cordic2/rom/cordic_rom.v | 83,113,169 | cordic_rom.v | v | 184 | 62 | [] | [] | [] | [(1, 184)] | null | data/verilator_xmls/a14148d4-5d09-4ca7-a3b7-1d8d1a0785c5.xml | null | 302,107 | module | module cordic_rom (
address,
X5,
Y5,clk);
input [3:0] address;
input clk;
output reg [21:0] X5;
output reg [21:0] Y5;
parameter[21:0] c0=22'b0111111111101010101010;
parameter[21:0] c1=22'b0111111101101010110010;
parameter[21:0] c2=22'b0111111001101011100010;
parameter[21:0] c3=22'b0111110011101101111010;
parameter[21:0] c4=22'b0111101011110011011001;
parameter[21:0] c5=22'b0111100001111101111101;
parameter[21:0] c6=22'b0111010110010000000101;
parameter[21:0] c7=22'b0111001000101100101011;
parameter[21:0] c8=22'b0110111001010111001000;
parameter[21:0] c9=22'b0110101000010011010010;
parameter[21:0] c10=22'b0110010101100101011001;
parameter[21:0] c11=22'b0110000001010010001001;
parameter[21:0] c12=22'b0101101011011110100110;
parameter[21:0] s0=22'b0000001111111111101010;
parameter[21:0] s1=22'b0000101111111011000000;
parameter[21:0] s2=22'b0001001111101010010111;
parameter[21:0] s3=22'b0001101111000101110100;
parameter[21:0] s4=22'b0010001110000101011111;
parameter[21:0] s5=22'b0010101100100001101011;
parameter[21:0] s6=22'b0011001010010010101111;
parameter[21:0] s7=22'b0011100111010001001111;
parameter[21:0] s8=22'b0100000011010101111100;
parameter[21:0] s9=22'b0100011110011001110101;
parameter[21:0] s10=22'b0100111000010110001001;
parameter[21:0] s11=22'b0101010001000100011001;
parameter[21:0] s12=22'b0101101000011110011001;
always@(posedge clk)
begin
case(address)
4'b0000:
begin
X5<=c0;
Y5<=s0;
end
4'b0001:
begin
X5<=c1;
Y5<=s1;
end
4'b0010:
begin
X5<=c2;
Y5<=s2;
end
4'b0011:
begin
X5<=c3;
Y5<=s3;
end
4'b0100:
begin
X5<=c4;
Y5<=s4;
end
4'b0101:
begin
X5<=c5;
Y5<=s5;
end
4'b0110:
begin
X5<=c6;
Y5<=s6;
end
4'b0111:
begin
X5<=c7;
Y5<=s7;
end
4'b1000:
begin
X5<=c8;
Y5<=s8;
end
4'b1001:
begin
X5<=c9;
Y5<=s9;
end
4'b1010:
begin
X5<=c10;
Y5<=s10;
end
4'b1011:
begin
X5<=c11;
Y5<=s11;
end
4'b1100:
begin
X5<=c12;
Y5<=s12;
end
default:
begin
X5<=0;
Y5<=0;
end
endcase
end
endmodule | module cordic_rom (
address,
X5,
Y5,clk); |
input [3:0] address;
input clk;
output reg [21:0] X5;
output reg [21:0] Y5;
parameter[21:0] c0=22'b0111111111101010101010;
parameter[21:0] c1=22'b0111111101101010110010;
parameter[21:0] c2=22'b0111111001101011100010;
parameter[21:0] c3=22'b0111110011101101111010;
parameter[21:0] c4=22'b0111101011110011011001;
parameter[21:0] c5=22'b0111100001111101111101;
parameter[21:0] c6=22'b0111010110010000000101;
parameter[21:0] c7=22'b0111001000101100101011;
parameter[21:0] c8=22'b0110111001010111001000;
parameter[21:0] c9=22'b0110101000010011010010;
parameter[21:0] c10=22'b0110010101100101011001;
parameter[21:0] c11=22'b0110000001010010001001;
parameter[21:0] c12=22'b0101101011011110100110;
parameter[21:0] s0=22'b0000001111111111101010;
parameter[21:0] s1=22'b0000101111111011000000;
parameter[21:0] s2=22'b0001001111101010010111;
parameter[21:0] s3=22'b0001101111000101110100;
parameter[21:0] s4=22'b0010001110000101011111;
parameter[21:0] s5=22'b0010101100100001101011;
parameter[21:0] s6=22'b0011001010010010101111;
parameter[21:0] s7=22'b0011100111010001001111;
parameter[21:0] s8=22'b0100000011010101111100;
parameter[21:0] s9=22'b0100011110011001110101;
parameter[21:0] s10=22'b0100111000010110001001;
parameter[21:0] s11=22'b0101010001000100011001;
parameter[21:0] s12=22'b0101101000011110011001;
always@(posedge clk)
begin
case(address)
4'b0000:
begin
X5<=c0;
Y5<=s0;
end
4'b0001:
begin
X5<=c1;
Y5<=s1;
end
4'b0010:
begin
X5<=c2;
Y5<=s2;
end
4'b0011:
begin
X5<=c3;
Y5<=s3;
end
4'b0100:
begin
X5<=c4;
Y5<=s4;
end
4'b0101:
begin
X5<=c5;
Y5<=s5;
end
4'b0110:
begin
X5<=c6;
Y5<=s6;
end
4'b0111:
begin
X5<=c7;
Y5<=s7;
end
4'b1000:
begin
X5<=c8;
Y5<=s8;
end
4'b1001:
begin
X5<=c9;
Y5<=s9;
end
4'b1010:
begin
X5<=c10;
Y5<=s10;
end
4'b1011:
begin
X5<=c11;
Y5<=s11;
end
4'b1100:
begin
X5<=c12;
Y5<=s12;
end
default:
begin
X5<=0;
Y5<=0;
end
endcase
end
endmodule | 0 |
138,274 | data/full_repos/permissive/83198026/actionRAM.v | 83,198,026 | actionRAM.v | v | 160 | 112 | [] | [] | [] | null | line:153: before: "." | null | 1: b"%Error: data/full_repos/permissive/83198026/actionRAM.v:138: Cannot find file containing module: 'ram'\nram ram_112_64(\n^~~\n ... Looked in:\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/ram\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/ram.v\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/ram.sv\n ram\n ram.v\n ram.sv\n obj_dir/ram\n obj_dir/ram.v\n obj_dir/ram.sv\n%Error: Exiting due to 1 error(s)\n" | 302,108 | module | module actionRAM(
clk,
reset,
index_valid,
index,
action_valid,
action,
ruleSet_valid,
ruleSet,
result_valid,
result
);
parameter depthRAM = 6;
input clk;
input reset;
input index_valid;
input [depthRAM+4:0] index;
output reg action_valid;
output reg [124:0] action;
input ruleSet_valid;
input [129:0] ruleSet;
output reg result_valid;
output reg [119:0] result;
reg [119:0] data_b;
reg rden_b,wren_b;
wire [119:0] q_a,q_b;
reg [5:0] addr_b;
reg index_valid_temp[1:0];
reg [4:0] bid_temp[1:0];
reg [5:0] index_temp[1:0];
always @ (posedge clk or negedge reset) begin
if(!reset) begin
index_valid_temp[0] <= 1'b0;
index_valid_temp[1] <= 1'b0;
bid_temp[0] <= 5'b0;
index_temp[0] <= 6'b0;
end
else begin
index_valid_temp[0] <= index_valid;
index_valid_temp[1] <= index_valid_temp[0];
bid_temp[0] <= index[10:6];
bid_temp[1] <= bid_temp[0];
index_temp[0] <= index[5:0];
index_temp[1] <= index_temp[0];
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
action_valid <= 1'b0;
action <= 125'b0;
end
else begin
if(index_valid_temp[1]==1'b1) begin
action_valid <= 1'b1;
if(index_temp[1]==6'h3f) action <= {bid_temp[1],24'b0,1'b1,1'b0,1'b1,93'b0};
else action <= {bid_temp[1],q_a};
end
else action_valid <= 1'b0;
end
end
reg [3:0] state;
parameter idle = 4'd0,
wait_1 = 4'd1,
wait_2 = 4'd2,
read_ram= 4'd3;
always @(posedge clk or negedge reset) begin
if(!reset) begin
state <= idle;
wren_b <= 1'b0;
rden_b <= 1'b0;
data_b <= 120'b0;
addr_b <= 6'b0;
result_valid <= 1'b0;
result <= 120'b0;
end
else begin
case(state)
idle: begin
result_valid <= 1'b0;
if(ruleSet_valid==1'b1) begin
if(ruleSet[128]==1'b1) begin
wren_b <= 1'b1;
addr_b <= ruleSet[5:0];
data_b <= ruleSet[127:8];
state <= idle;
end
else begin
rden_b <= 1'b1;
addr_b <= ruleSet[5:0];
state <= wait_1;
end
end
else begin
wren_b <= 1'b0;
rden_b <= 1'b0;
end
end
wait_1: begin
rden_b <= 1'b0;
state <= wait_2;
end
wait_2: state <= read_ram;
read_ram: begin
result_valid <= 1'b1;
result <= q_b;
state <= idle;
end
default: state <= idle;
endcase
end
end
ram ram_112_64(
.address_a(index[5:0]),
.address_b(addr_b),
.clock(clk),
.data_a(120'b0),
.data_b(data_b),
.rden_a(index_valid),
.rden_b(rden_b),
.wren_a(1'b0),
.wren_b(wren_b),
.q_a(q_a),
.q_b(q_b)
);
defparam
ram_112_64.width = 120,
ram_112_64.depth = 6,
ram_112_64.words = 64;
endmodule | module actionRAM(
clk,
reset,
index_valid,
index,
action_valid,
action,
ruleSet_valid,
ruleSet,
result_valid,
result
); |
parameter depthRAM = 6;
input clk;
input reset;
input index_valid;
input [depthRAM+4:0] index;
output reg action_valid;
output reg [124:0] action;
input ruleSet_valid;
input [129:0] ruleSet;
output reg result_valid;
output reg [119:0] result;
reg [119:0] data_b;
reg rden_b,wren_b;
wire [119:0] q_a,q_b;
reg [5:0] addr_b;
reg index_valid_temp[1:0];
reg [4:0] bid_temp[1:0];
reg [5:0] index_temp[1:0];
always @ (posedge clk or negedge reset) begin
if(!reset) begin
index_valid_temp[0] <= 1'b0;
index_valid_temp[1] <= 1'b0;
bid_temp[0] <= 5'b0;
index_temp[0] <= 6'b0;
end
else begin
index_valid_temp[0] <= index_valid;
index_valid_temp[1] <= index_valid_temp[0];
bid_temp[0] <= index[10:6];
bid_temp[1] <= bid_temp[0];
index_temp[0] <= index[5:0];
index_temp[1] <= index_temp[0];
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
action_valid <= 1'b0;
action <= 125'b0;
end
else begin
if(index_valid_temp[1]==1'b1) begin
action_valid <= 1'b1;
if(index_temp[1]==6'h3f) action <= {bid_temp[1],24'b0,1'b1,1'b0,1'b1,93'b0};
else action <= {bid_temp[1],q_a};
end
else action_valid <= 1'b0;
end
end
reg [3:0] state;
parameter idle = 4'd0,
wait_1 = 4'd1,
wait_2 = 4'd2,
read_ram= 4'd3;
always @(posedge clk or negedge reset) begin
if(!reset) begin
state <= idle;
wren_b <= 1'b0;
rden_b <= 1'b0;
data_b <= 120'b0;
addr_b <= 6'b0;
result_valid <= 1'b0;
result <= 120'b0;
end
else begin
case(state)
idle: begin
result_valid <= 1'b0;
if(ruleSet_valid==1'b1) begin
if(ruleSet[128]==1'b1) begin
wren_b <= 1'b1;
addr_b <= ruleSet[5:0];
data_b <= ruleSet[127:8];
state <= idle;
end
else begin
rden_b <= 1'b1;
addr_b <= ruleSet[5:0];
state <= wait_1;
end
end
else begin
wren_b <= 1'b0;
rden_b <= 1'b0;
end
end
wait_1: begin
rden_b <= 1'b0;
state <= wait_2;
end
wait_2: state <= read_ram;
read_ram: begin
result_valid <= 1'b1;
result <= q_b;
state <= idle;
end
default: state <= idle;
endcase
end
end
ram ram_112_64(
.address_a(index[5:0]),
.address_b(addr_b),
.clock(clk),
.data_a(120'b0),
.data_b(data_b),
.rden_a(index_valid),
.rden_b(rden_b),
.wren_a(1'b0),
.wren_b(wren_b),
.q_a(q_a),
.q_b(q_b)
);
defparam
ram_112_64.width = 120,
ram_112_64.depth = 6,
ram_112_64.words = 64;
endmodule | 0 |
138,275 | data/full_repos/permissive/83198026/calculate_time.v | 83,198,026 | calculate_time.v | v | 177 | 51 | [] | [] | [] | null | line:170: before: "." | null | 1: b"%Error: data/full_repos/permissive/83198026/calculate_time.v:156: Cannot find file containing module: 'ram'\nram ram_count(\n^~~\n ... Looked in:\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/ram\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/ram.v\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/ram.sv\n ram\n ram.v\n ram.sv\n obj_dir/ram\n obj_dir/ram.v\n obj_dir/ram.sv\n%Error: Exiting due to 1 error(s)\n" | 302,111 | module | module calculate_time(
clk,
reset,
start_valid,
ramID_start,
count,
over_valid,
ramID_over,
pktDelay,
pktCount
);
parameter id=1;
parameter widthExtraction = 2;
parameter limitTime = 50000;
input clk;
input reset;
input start_valid;
input [4:0] ramID_start;
output reg [31:0] count;
input over_valid;
input [4:0] ramID_over;
output reg [31:0] pktDelay;
output reg [31:0] pktCount;
reg [5:0] addr_a,addr_b;
reg [31:0] data_b;
reg rden_a,wren_b;
wire [31:0] q_a;
reg [31:0] timeOver;
reg [3:0] countID;
integer i;
reg state;
reg [1:0] state_cal;
parameter idle = 2'd0,
wait1 = 2'd1,
calTime = 2'd2;
always @(posedge clk or negedge reset) begin
if(!reset) begin
countID <= 4'd0;
wren_b <= 1'b0;
addr_b <= 6'b0;
data_b <= 32'b0;
end
else begin
if(start_valid==1'b1) begin
countID <= countID +4'd1;
if(countID[widthExtraction-1:0]== id) begin
wren_b <= 1'b1;
addr_b <= addr_b + 6'd1;
data_b <= count;
end
else wren_b <= 1'b0;
end
else begin
countID <= countID;
wren_b <= 1'b0;
end
end
end
always @ (posedge clk or negedge reset) begin
if(!reset) begin
rden_a <= 1'b0;
addr_a <= 6'b0;
state <= 1'b0;
timeOver <= 32'b0;
end
else begin
case(state)
1'b0: begin
if(over_valid==1'b1) begin
rden_a <= 1'b1;
addr_a <= addr_a + 6'd1;
state <= 1'b1;
timeOver <= count;
end
else state <= 1'b0;
end
1'b1: begin
rden_a<= 1'b0;
if(over_valid==1'b0) begin
state <= 1'b0;
end
else state <= 1'b1;
end
endcase
end
end
always @ (posedge clk or negedge reset) begin
if(!reset) begin
pktDelay <= 32'b0;
state_cal <= idle;
pktCount <= 32'b0;
end
else begin
case(state_cal)
idle: begin
if(rden_a == 1'b1) state_cal <= wait1;
else state_cal <= idle;
if(count==limitTime) begin
pktDelay <= 32'b0;
pktCount <= 32'b0;
end
end
wait1: begin
state_cal <= calTime;
if(count==limitTime) begin
pktDelay <= 32'b0;
pktCount <= 32'b0;
end
end
calTime: begin
if((q_a > timeOver)||(count==limitTime)) begin
pktDelay <= 32'b0;
pktCount <= 32'b0;
end
else begin
pktDelay <= pktDelay + timeOver-q_a;
pktCount <= pktCount + 32'b1;
end
state_cal <= idle;
end
default: begin end
endcase
end
end
always @ (posedge clk or negedge reset) begin
if(!reset) count <= 32'b0;
else begin
if(count == limitTime) count <= 32'b0;
else count <= count+32'd1;
end
end
ram ram_count(
.address_a(addr_a),
.address_b(addr_b),
.clock(clk),
.data_a(32'd0),
.data_b(data_b),
.rden_a(rden_a),
.rden_b(1'b0),
.wren_a(1'b0),
.wren_b(wren_b),
.q_a(q_a),
.q_b()
);
defparam
ram_count.width = 32,
ram_count.depth = 6,
ram_count.words = 64;
endmodule | module calculate_time(
clk,
reset,
start_valid,
ramID_start,
count,
over_valid,
ramID_over,
pktDelay,
pktCount
); |
parameter id=1;
parameter widthExtraction = 2;
parameter limitTime = 50000;
input clk;
input reset;
input start_valid;
input [4:0] ramID_start;
output reg [31:0] count;
input over_valid;
input [4:0] ramID_over;
output reg [31:0] pktDelay;
output reg [31:0] pktCount;
reg [5:0] addr_a,addr_b;
reg [31:0] data_b;
reg rden_a,wren_b;
wire [31:0] q_a;
reg [31:0] timeOver;
reg [3:0] countID;
integer i;
reg state;
reg [1:0] state_cal;
parameter idle = 2'd0,
wait1 = 2'd1,
calTime = 2'd2;
always @(posedge clk or negedge reset) begin
if(!reset) begin
countID <= 4'd0;
wren_b <= 1'b0;
addr_b <= 6'b0;
data_b <= 32'b0;
end
else begin
if(start_valid==1'b1) begin
countID <= countID +4'd1;
if(countID[widthExtraction-1:0]== id) begin
wren_b <= 1'b1;
addr_b <= addr_b + 6'd1;
data_b <= count;
end
else wren_b <= 1'b0;
end
else begin
countID <= countID;
wren_b <= 1'b0;
end
end
end
always @ (posedge clk or negedge reset) begin
if(!reset) begin
rden_a <= 1'b0;
addr_a <= 6'b0;
state <= 1'b0;
timeOver <= 32'b0;
end
else begin
case(state)
1'b0: begin
if(over_valid==1'b1) begin
rden_a <= 1'b1;
addr_a <= addr_a + 6'd1;
state <= 1'b1;
timeOver <= count;
end
else state <= 1'b0;
end
1'b1: begin
rden_a<= 1'b0;
if(over_valid==1'b0) begin
state <= 1'b0;
end
else state <= 1'b1;
end
endcase
end
end
always @ (posedge clk or negedge reset) begin
if(!reset) begin
pktDelay <= 32'b0;
state_cal <= idle;
pktCount <= 32'b0;
end
else begin
case(state_cal)
idle: begin
if(rden_a == 1'b1) state_cal <= wait1;
else state_cal <= idle;
if(count==limitTime) begin
pktDelay <= 32'b0;
pktCount <= 32'b0;
end
end
wait1: begin
state_cal <= calTime;
if(count==limitTime) begin
pktDelay <= 32'b0;
pktCount <= 32'b0;
end
end
calTime: begin
if((q_a > timeOver)||(count==limitTime)) begin
pktDelay <= 32'b0;
pktCount <= 32'b0;
end
else begin
pktDelay <= pktDelay + timeOver-q_a;
pktCount <= pktCount + 32'b1;
end
state_cal <= idle;
end
default: begin end
endcase
end
end
always @ (posedge clk or negedge reset) begin
if(!reset) count <= 32'b0;
else begin
if(count == limitTime) count <= 32'b0;
else count <= count+32'd1;
end
end
ram ram_count(
.address_a(addr_a),
.address_b(addr_b),
.clock(clk),
.data_a(32'd0),
.data_b(data_b),
.rden_a(rden_a),
.rden_b(1'b0),
.wren_a(1'b0),
.wren_b(wren_b),
.q_a(q_a),
.q_b()
);
defparam
ram_count.width = 32,
ram_count.depth = 6,
ram_count.words = 64;
endmodule | 0 |
138,276 | data/full_repos/permissive/83198026/data_128to32.v | 83,198,026 | data_128to32.v | v | 99 | 85 | [] | [] | [] | [(7, 99)] | null | data/verilator_xmls/d416e2c8-a018-4291-ba96-de5756f49fb3.xml | null | 302,112 | module | module data_128to32(
clk,
reset,
headerOut_enable,
rdreq,
data_in,
headerData_out_valid,
headerData_out,
headerData_finish_valid,
pktID
);
parameter widthPkt = 138,
widthHeaderData = 32;
input clk;
input reset;
input headerOut_enable;
output reg rdreq;
input [widthPkt-1:0] data_in;
output reg headerData_out_valid;
output reg [widthHeaderData-1:0] headerData_out;
output reg headerData_finish_valid;
output reg [7:0] pktID;
reg [widthPkt-1:0] headerData_temp;
reg [2:0] state;
parameter idle = 3'd0,
read_fifo = 3'd1,
out_2 = 3'd2,
out_3 = 3'd3,
out_4 = 3'd4;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
headerData_out_valid <= 1'b0;
headerData_out <= {widthHeaderData{1'b0}};
rdreq <= 1'b0;
headerData_finish_valid <= 1'b0;
pktID <= 8'b0;
state <= idle;
end
else begin
case(state)
idle: begin
headerData_out_valid <= 1'b0;
headerData_finish_valid <= 1'b0;
if(headerOut_enable == 1'b1) begin
rdreq <= 1'b1;
state <= read_fifo;
end
else begin
rdreq <= 1'b0;
end
end
read_fifo: begin
rdreq <= 1'b0;
headerData_temp <= data_in;
headerData_out_valid <= 1'b1;
headerData_out <= data_in[127:96];
state <= out_2;
end
out_2: begin
headerData_out <= headerData_temp[95:64];
state <= out_3;
end
out_3: begin
headerData_out <= headerData_temp[63:32];
state <= out_4;
end
out_4: begin
headerData_out <= headerData_temp[31:0];
if(headerData_temp[129:128]==2'b1) begin
headerData_finish_valid <= 1'b1;
pktID <= headerData_temp[137:130];
state <= idle;
end
else headerData_finish_valid <= 1'b0;
if(headerOut_enable==1'b1) begin
state <= read_fifo;
rdreq <= 1'b1;
end
else state <= idle;
end
default: state <= idle;
endcase
end
end
endmodule | module data_128to32(
clk,
reset,
headerOut_enable,
rdreq,
data_in,
headerData_out_valid,
headerData_out,
headerData_finish_valid,
pktID
); |
parameter widthPkt = 138,
widthHeaderData = 32;
input clk;
input reset;
input headerOut_enable;
output reg rdreq;
input [widthPkt-1:0] data_in;
output reg headerData_out_valid;
output reg [widthHeaderData-1:0] headerData_out;
output reg headerData_finish_valid;
output reg [7:0] pktID;
reg [widthPkt-1:0] headerData_temp;
reg [2:0] state;
parameter idle = 3'd0,
read_fifo = 3'd1,
out_2 = 3'd2,
out_3 = 3'd3,
out_4 = 3'd4;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
headerData_out_valid <= 1'b0;
headerData_out <= {widthHeaderData{1'b0}};
rdreq <= 1'b0;
headerData_finish_valid <= 1'b0;
pktID <= 8'b0;
state <= idle;
end
else begin
case(state)
idle: begin
headerData_out_valid <= 1'b0;
headerData_finish_valid <= 1'b0;
if(headerOut_enable == 1'b1) begin
rdreq <= 1'b1;
state <= read_fifo;
end
else begin
rdreq <= 1'b0;
end
end
read_fifo: begin
rdreq <= 1'b0;
headerData_temp <= data_in;
headerData_out_valid <= 1'b1;
headerData_out <= data_in[127:96];
state <= out_2;
end
out_2: begin
headerData_out <= headerData_temp[95:64];
state <= out_3;
end
out_3: begin
headerData_out <= headerData_temp[63:32];
state <= out_4;
end
out_4: begin
headerData_out <= headerData_temp[31:0];
if(headerData_temp[129:128]==2'b1) begin
headerData_finish_valid <= 1'b1;
pktID <= headerData_temp[137:130];
state <= idle;
end
else headerData_finish_valid <= 1'b0;
if(headerOut_enable==1'b1) begin
state <= read_fifo;
rdreq <= 1'b1;
end
else state <= idle;
end
default: state <= idle;
endcase
end
end
endmodule | 0 |
138,277 | data/full_repos/permissive/83198026/ditributor.v | 83,198,026 | ditributor.v | v | 166 | 99 | [] | [] | [] | null | line:114: before: "." | null | 1: b"%Error: data/full_repos/permissive/83198026/ditributor.v:103: Cannot find file containing module: 'data_128to32'\n data_128to32 header_128to32(\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/data_128to32\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/data_128to32.v\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/data_128to32.sv\n data_128to32\n data_128to32.v\n data_128to32.sv\n obj_dir/data_128to32\n obj_dir/data_128to32.v\n obj_dir/data_128to32.sv\n%Error: data/full_repos/permissive/83198026/ditributor.v:144: Cannot find file containing module: 'fifo'\n fifo fifo_header(\n ^~~~\n%Error: Exiting due to 2 error(s)\n" | 302,113 | module | module distributor(
clk,
reset,
headerData_in_valid,
headerData_in,
headerEnd_valid,
bid_bitmap,
headerData_out_valid,
headerData_out,
pktID_out,
headerData_finish_valid,
headerIn_enable
);
parameter widthHeaderData = 32,
numExtraction = 8,
widthPkt = 138;
input clk;
input reset;
input headerData_in_valid;
input [widthPkt-1:0] headerData_in;
input headerEnd_valid;
input [numExtraction-1:0] bid_bitmap;
output wire [numExtraction-1:0] headerData_out_valid;
output wire [widthHeaderData*numExtraction-1:0] headerData_out;
output wire [numExtraction-1:0] headerData_finish_valid;
output wire [8*numExtraction-1:0] pktID_out;
output reg headerIn_enable;
integer i1,i2,i3,i4,i5;
reg [7:0] ramID;
reg [numExtraction-1:0] usedw_bitmap;
reg [1:0] bidStart_tag[numExtraction-1:0];
reg [1:0] bidEnd_tag[numExtraction-1:0];
reg empty_tag[numExtraction-1:0];
reg [widthPkt-1:0] data_header;
wire rdreq_header[numExtraction-1:0];
reg [numExtraction-1:0]wrreq_header;
wire empty_header[numExtraction-1:0];
wire [widthPkt-1:0] q_header[numExtraction-1:0];
wire [5:0] usedw_header[numExtraction-1:0];
reg state;
parameter idle = 1'd0,
wait_end = 1'd1;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
ramID <= 8'b1;
state <= idle;
wrreq_header <= {numExtraction{1'b0}};
end
else begin
case(state)
idle: begin
if(headerData_in_valid == 1'b1) begin
data_header <= headerData_in;
wrreq_header <= ramID;
state <= wait_end;
end
else wrreq_header <= {numExtraction{1'b0}};
end
wait_end: begin
if(headerData_in[129:128] == 2'b1) begin
if(ramID == 8'h80) ramID <= 8'd1;
else ramID <= ramID + ramID;
state <= idle;
end
else state <= wait_end;
data_header <= headerData_in;
end
endcase
end
end
generate
genvar j;
for(j=0;j<numExtraction;j=j+1) begin : data_128to32
data_128to32 header_128to32(
.clk(clk),
.reset(reset),
.headerOut_enable(bid_bitmap[j]&(~empty_header[j])),
.rdreq(rdreq_header[j]),
.data_in(q_header[j]),
.headerData_out_valid(headerData_out_valid[j]),
.headerData_out(headerData_out[(j+1)*widthHeaderData-1:j*widthHeaderData]),
.pktID(pktID_out[j*8+7:j*8]),
.headerData_finish_valid(headerData_finish_valid[j])
);
defparam header_128to32.widthPkt = widthPkt,
header_128to32.widthHeaderData = widthHeaderData;
end
endgenerate
always @ (posedge clk or negedge reset) begin
if(!reset) begin
headerIn_enable <= 1'b0;
usedw_bitmap <= {numExtraction{1'b0}};
end
else begin
for(i2=0;i2<numExtraction;i2=i2+1)begin
if(usedw_header[i2]>6'd50) usedw_bitmap[i2] <= 1'b1;
else usedw_bitmap[i2] <= 1'b0;
end
if(usedw_bitmap=={numExtraction{1'b0}}) headerIn_enable <= 1'b1;
else headerIn_enable <= 1'b0;
end
end
generate
genvar i;
for(i=0;i<numExtraction;i=i+1) begin : fifo
fifo fifo_header(
.aclr(!reset),
.clock(clk),
.data(data_header),
.rdreq(rdreq_header[i]),
.wrreq(wrreq_header[i]),
.empty(empty_header[i]),
.full(),
.q(q_header[i]),
.usedw(usedw_header[i])
);
defparam
fifo_header.width = 138,
fifo_header.depth = 6,
fifo_header.words = 64;
end
endgenerate
endmodule | module distributor(
clk,
reset,
headerData_in_valid,
headerData_in,
headerEnd_valid,
bid_bitmap,
headerData_out_valid,
headerData_out,
pktID_out,
headerData_finish_valid,
headerIn_enable
); |
parameter widthHeaderData = 32,
numExtraction = 8,
widthPkt = 138;
input clk;
input reset;
input headerData_in_valid;
input [widthPkt-1:0] headerData_in;
input headerEnd_valid;
input [numExtraction-1:0] bid_bitmap;
output wire [numExtraction-1:0] headerData_out_valid;
output wire [widthHeaderData*numExtraction-1:0] headerData_out;
output wire [numExtraction-1:0] headerData_finish_valid;
output wire [8*numExtraction-1:0] pktID_out;
output reg headerIn_enable;
integer i1,i2,i3,i4,i5;
reg [7:0] ramID;
reg [numExtraction-1:0] usedw_bitmap;
reg [1:0] bidStart_tag[numExtraction-1:0];
reg [1:0] bidEnd_tag[numExtraction-1:0];
reg empty_tag[numExtraction-1:0];
reg [widthPkt-1:0] data_header;
wire rdreq_header[numExtraction-1:0];
reg [numExtraction-1:0]wrreq_header;
wire empty_header[numExtraction-1:0];
wire [widthPkt-1:0] q_header[numExtraction-1:0];
wire [5:0] usedw_header[numExtraction-1:0];
reg state;
parameter idle = 1'd0,
wait_end = 1'd1;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
ramID <= 8'b1;
state <= idle;
wrreq_header <= {numExtraction{1'b0}};
end
else begin
case(state)
idle: begin
if(headerData_in_valid == 1'b1) begin
data_header <= headerData_in;
wrreq_header <= ramID;
state <= wait_end;
end
else wrreq_header <= {numExtraction{1'b0}};
end
wait_end: begin
if(headerData_in[129:128] == 2'b1) begin
if(ramID == 8'h80) ramID <= 8'd1;
else ramID <= ramID + ramID;
state <= idle;
end
else state <= wait_end;
data_header <= headerData_in;
end
endcase
end
end
generate
genvar j;
for(j=0;j<numExtraction;j=j+1) begin : data_128to32
data_128to32 header_128to32(
.clk(clk),
.reset(reset),
.headerOut_enable(bid_bitmap[j]&(~empty_header[j])),
.rdreq(rdreq_header[j]),
.data_in(q_header[j]),
.headerData_out_valid(headerData_out_valid[j]),
.headerData_out(headerData_out[(j+1)*widthHeaderData-1:j*widthHeaderData]),
.pktID(pktID_out[j*8+7:j*8]),
.headerData_finish_valid(headerData_finish_valid[j])
);
defparam header_128to32.widthPkt = widthPkt,
header_128to32.widthHeaderData = widthHeaderData;
end
endgenerate
always @ (posedge clk or negedge reset) begin
if(!reset) begin
headerIn_enable <= 1'b0;
usedw_bitmap <= {numExtraction{1'b0}};
end
else begin
for(i2=0;i2<numExtraction;i2=i2+1)begin
if(usedw_header[i2]>6'd50) usedw_bitmap[i2] <= 1'b1;
else usedw_bitmap[i2] <= 1'b0;
end
if(usedw_bitmap=={numExtraction{1'b0}}) headerIn_enable <= 1'b1;
else headerIn_enable <= 1'b0;
end
end
generate
genvar i;
for(i=0;i<numExtraction;i=i+1) begin : fifo
fifo fifo_header(
.aclr(!reset),
.clock(clk),
.data(data_header),
.rdreq(rdreq_header[i]),
.wrreq(wrreq_header[i]),
.empty(empty_header[i]),
.full(),
.q(q_header[i]),
.usedw(usedw_header[i])
);
defparam
fifo_header.width = 138,
fifo_header.depth = 6,
fifo_header.words = 64;
end
endgenerate
endmodule | 0 |
138,278 | data/full_repos/permissive/83198026/extractor.v | 83,198,026 | extractor.v | v | 733 | 121 | [] | [] | [] | null | line:638: before: "." | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/83198026/extractor.v:235: Operator CASE expects 3 bits on the Case expression, but Case expression\'s SEL generates 2 bits.\n : ... In instance extractor\n case(q_location_temp[3][9:8])\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/83198026/extractor.v:235: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'2\'h0\' generates 2 bits.\n : ... In instance extractor\n case(q_location_temp[3][9:8])\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/83198026/extractor.v:235: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'2\'h1\' generates 2 bits.\n : ... In instance extractor\n case(q_location_temp[3][9:8])\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/83198026/extractor.v:235: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance extractor\n case(q_location_temp[3][9:8])\n ^~~~\n%Warning-WIDTHCONCAT: data/full_repos/permissive/83198026/extractor.v:283: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance extractor\n if(q_location_temp[4][0]==1\'b0) offset <= {q_pktID_temp[4],q_location_temp[4][23:16] + fieldValue[31:28]*4};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/83198026/extractor.v:283: Unsized numbers/parameters not allowed in replications.\n : ... In instance extractor\n if(q_location_temp[4][0]==1\'b0) offset <= {q_pktID_temp[4],q_location_temp[4][23:16] + fieldValue[31:28]*4};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/83198026/extractor.v:284: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance extractor\n else offset <= {q_pktID_temp[4],q_location_temp[4][23:16] + fieldValue[27:24]*4};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/83198026/extractor.v:284: Unsized numbers/parameters not allowed in replications.\n : ... In instance extractor\n else offset <= {q_pktID_temp[4],q_location_temp[4][23:16] + fieldValue[27:24]*4};\n ^\n%Warning-WIDTH: data/full_repos/permissive/83198026/extractor.v:370: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance extractor\n else state_locationIn <= 1\'b0;\n ^~\n%Error: data/full_repos/permissive/83198026/extractor.v:624: Cannot find file containing module: \'ram\'\nram ram_32_256(\n^~~\n ... Looked in:\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/ram\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/ram.v\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/ram.sv\n ram\n ram.v\n ram.sv\n obj_dir/ram\n obj_dir/ram.v\n obj_dir/ram.sv\n%Error: data/full_repos/permissive/83198026/extractor.v:646: Cannot find file containing module: \'fifo\'\nfifo fifo_action( \n^~~~\n%Error: data/full_repos/permissive/83198026/extractor.v:662: Cannot find file containing module: \'fifo\'\nfifo fifo_newHeader(\n^~~~\n%Error: data/full_repos/permissive/83198026/extractor.v:678: Cannot find file containing module: \'fifo\'\nfifo fifo_location( \n^~~~\n%Error: data/full_repos/permissive/83198026/extractor.v:696: Cannot find file containing module: \'fifo\'\nfifo fifo_offset(\n^~~~\n%Error: data/full_repos/permissive/83198026/extractor.v:714: Cannot find file containing module: \'fifo\'\nfifo fifo_bid(\n^~~~\n%Error: Exiting due to 6 error(s), 9 warning(s)\n' | 302,114 | module | module extractor(
clk,
reset,
headerData_valid,
headerData,
headerData_finish_valid,
pktID,
action_valid,
action,
field_valid,
field,
hvOffset,
field_finish_valid,
field_finish_bid,
bid_enable,
stateType_valid,
stateType
);
parameter extractionID = 1,
widthExtraction = 3,
widthHeaderData = 32;
integer i;
input clk;
input reset;
input headerData_valid;
input [widthHeaderData-1:0] headerData;
input headerData_finish_valid;
input [7:0] pktID;
input action_valid;
input [124:0] action;
output reg field_valid;
output reg [widthHeaderData-1:0] field;
output reg [11:0] hvOffset;
output reg field_finish_valid;
output reg [23:0] field_finish_bid;
output reg bid_enable;
output reg stateType_valid;
output reg [44:0] stateType;
reg [2:0] bid_count;
reg bid_count_add;
reg state_headIn;
reg [1:0] ramID;
reg [5:0] addr_temp;
reg [7:0] pktID_temp;
reg [4:0] bid_temp;
reg [7:0] state_temp;
reg [7:0] typeOffset_temp;
reg [7:0] typeMask_temp;
reg end_temp;
reg extraction_temp;
reg flowMod_temp;
reg [4:0] reserved;
reg [7:0] hvOffset_temp,hvOffset_temp_reserved;
reg [15:0] length_temp;
reg [15:0] location_temp[3:0];
reg [7:0] headerOffset_temp;
reg [7:0] headerLocation;
reg [7:0] headerLocation_count,headerLocation_limit;
reg [117:0] action_temp;
reg [3:0] state_locationIn;
parameter idle_locationIn = 4'd0,
read_fifo_action = 4'd1,
read_fifo_newHeader = 4'd2,
write_typeOffset = 4'd3,
write_headerOffset = 4'd4,
write_fieldLocation_0=4'd5,
write_fieldLocation_1=4'd6,
write_fieldLocation_2=4'd7,
write_fieldLocation_3=4'd8,
write_end = 4'd9;
reg [7:0] addr_a,addr_b;
reg [widthHeaderData-1:0] data_b;
reg wren_b,rden_a;
wire [widthHeaderData-1:0] q_a;
reg [124:0] data_action;
reg wrreq_action,rdreq_action;
wire empty_action;
wire [124:0] q_action;
reg [132:0] data_newHeader;
reg wrreq_newHeader,rdreq_newHeader;
wire empty_newHeader;
wire [132:0] q_newHeader;
reg [39:0] data_location;
reg wrreq_location,rdreq_location;
wire empty_location;
wire [39:0] q_location;
reg [15:0] offset;
reg offset_valid;
reg rdreq_offset;
wire empty_offset;
wire [15:0] q_offset;
reg [4:0] data_bid;
reg rdreq_bid,wrreq_bid;
wire empty_bid;
wire [4:0] q_bid;
reg stage_enable[4:0];
reg [31:0] q_location_temp[4:0];
reg [7:0] q_pktID_temp[4:0];
reg offset_valid_temp[4:0];
reg [7:0] offset_temp[4:0];
reg [31:0] field_temp,fieldValue,maskBit_temp;
reg state_stage_0,state_stage_1,state_stage_2,state_stage_3;
parameter clock_0 = 1'd0,
clock_1 = 1'd1;
always @(posedge clk or negedge reset) begin
if(!reset) begin
state_stage_0 <= clock_0;
rdreq_location <= 1'b0;
end
else begin
case(state_stage_0)
clock_0: begin
if(empty_location==1'b0) begin
rdreq_location <= 1'b1;
state_stage_0 <= clock_1;
end
else state_stage_0 <= clock_0;
end
clock_1: begin
rdreq_location <= 1'b0;
state_stage_0 <= clock_0;
end
endcase
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
addr_a <= 8'b0;
rden_a <= 1'b0;
stage_enable[0] <= 1'b0;
state_stage_1 <= clock_0;
field_finish_valid <= 1'b0;
field_finish_bid <= 24'b0;
offset_valid_temp[0] <= 1'b0;
offset_temp[0] <= 8'b0;
end
else begin
case(state_stage_1)
clock_0: begin
if(rdreq_location==1'b1) begin
state_stage_1 <= clock_1;
if(q_location[31]==1'b1) begin
rden_a <= 1'b0;
field_finish_valid <= 1'b1;
field_finish_bid <= {q_location[23:16],3'b0,q_location[28:24],q_location[39:32]};
stage_enable[0] <= 1'b0;
end
else if((q_location[29]==1'b1) && (q_location[15]==1'b0)) begin
rden_a <= 1'b0;
offset_valid_temp[0] <= 1'b1;
offset_temp[0] <= q_location[23:16] + q_location[7:0];
stage_enable[0] <= 1'b0;
end
else begin
rden_a <= 1'b1;
addr_a <= {q_location[25:24],{1'b0,q_location[14:10]}};
stage_enable[0] <= 1'b1;
end
end
else begin
state_stage_1 <= clock_0;
rden_a <= 1'b0;
stage_enable[0] <= 1'b0;
end
end
clock_1: begin
if(rden_a==1'b1) addr_a <= addr_a + 8'd1;
field_finish_valid <= 1'b0;
offset_valid_temp[0] <= 1'b0;
state_stage_1 <= clock_0;
end
endcase
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
state_stage_2 <= clock_0;
fieldValue <= 32'b0;
field_temp <= 32'b0;
maskBit_temp <= 32'b0;
end
else begin
case(state_stage_2)
clock_0: begin
if(stage_enable[2]==1'b1) begin
field_temp <= q_a;
state_stage_2 <= clock_1;
end
else state_stage_2 <= clock_0;
end
clock_1: begin
if(stage_enable[3]==1'b1) begin
case(q_location_temp[3][9:8])
2'd0: fieldValue <= field_temp;
2'd1: fieldValue <= {field_temp[23:0],q_a[31:24]};
2'd2: fieldValue <= {field_temp[15:0],q_a[31:16]};
3'd3: fieldValue <= {field_temp[7:0],q_a[31:8]};
endcase
case(q_location_temp[3][23:16])
8'd0: maskBit_temp <= 32'hffff_ffff;
8'd8: maskBit_temp <= 32'hffff_ff00;
8'd16: maskBit_temp <= 32'hffff_0000;
8'd24: maskBit_temp <= 32'hff00_0000;
default: maskBit_temp <= 32'hffff_ffff;
endcase
end
state_stage_2 <= clock_0;
end
endcase
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
state_stage_3 <= clock_0;
offset_valid <= 1'b0;
offset <= 16'b0;
stateType_valid <= 1'b0;
stateType <= 45'b0;
field_valid <= 1'b0;
field <= 32'b0;
hvOffset <= 12'b0;
end
else begin
case(state_stage_3)
clock_0: begin
if(stage_enable[4]==1'b1) begin
case(q_location_temp[4][31:29])
3'b000: begin
hvOffset <= {q_location_temp[4][28:24],q_location_temp[4][22:16]};
field_valid <= 1'b1;
field <= fieldValue;
end
3'b010: begin
stateType_valid <= 1'b1;
stateType <= {q_location_temp[4][28:24],fieldValue&maskBit_temp,q_location_temp[4][7:0]};
end
3'b001: begin
offset_valid <= 1'b1;
if(q_location_temp[4][0]==1'b0) offset <= {q_pktID_temp[4],q_location_temp[4][23:16] + fieldValue[31:28]*4};
else offset <= {q_pktID_temp[4],q_location_temp[4][23:16] + fieldValue[27:24]*4};
end
default: begin
end
endcase
state_stage_3 <= clock_1;
end
else if(offset_valid_temp[4]==1'b1) begin
offset_valid <= 1'b1;
offset <= {q_pktID_temp[4],offset_temp[4]};
state_stage_3 <= clock_1;
end
else state_stage_3 <= clock_0;
end
clock_1: begin
offset_valid <= 1'b0;
stateType_valid <= 1'b0;
field_valid <= 1'b0;
state_stage_3 <= clock_0;
end
endcase
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
stage_enable[1] <= 1'b0;stage_enable[2] <= 1'b0;
stage_enable[3] <= 1'b0;stage_enable[4] <= 1'b0;
offset_valid_temp[1] <= 1'b0;offset_valid_temp[2] <= 1'b0;
end
else begin
stage_enable[1] <= stage_enable[0];
stage_enable[2] <= stage_enable[1];
stage_enable[3] <= stage_enable[2];
stage_enable[4] <= stage_enable[3];
q_location_temp[0] <= q_location[31:0];
q_location_temp[1] <= q_location_temp[0];
q_location_temp[2] <= q_location_temp[1];
q_location_temp[3] <= q_location_temp[2];
q_location_temp[4] <= q_location_temp[3];
q_pktID_temp[0] <= q_location[39:32];
q_pktID_temp[1] <= q_pktID_temp[0];
q_pktID_temp[2] <= q_pktID_temp[1];
q_pktID_temp[3] <= q_pktID_temp[2];
q_pktID_temp[4] <= q_pktID_temp[3];
offset_valid_temp[1] <= offset_valid_temp[0];
offset_valid_temp[2] <= offset_valid_temp[1];
offset_valid_temp[3] <= offset_valid_temp[2];
offset_valid_temp[4] <= offset_valid_temp[3];
offset_temp[1] <= offset_temp[0];
offset_temp[2] <= offset_temp[1];
offset_temp[3] <= offset_temp[2];
offset_temp[4] <= offset_temp[3];
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
wrreq_location <= 1'b0;
data_location <= 40'b0;
state_locationIn <= idle_locationIn;
rdreq_action <= 1'b0;
rdreq_newHeader <= 1'b0;
rdreq_offset <= 1'b0;
pktID_temp <= 8'd0;
typeMask_temp <= 8'd0;
end
else begin
case(state_locationIn)
idle_locationIn: begin
wrreq_location <= 1'b0;
if(empty_action == 1'b0) begin
state_locationIn <= read_fifo_action;
rdreq_action <= 1'b1;
rdreq_offset <= 1'b1;
end
else if(empty_newHeader == 1'b0) begin
state_locationIn <= read_fifo_newHeader;
rdreq_newHeader <= 1'b1;
end
else state_locationIn <= 1'b0;
end
read_fifo_action: begin
rdreq_action <= 1'b0;
rdreq_offset <= 1'b0;
{pktID_temp,headerOffset_temp} <= q_offset;
{bid_temp,state_temp,typeOffset_temp,typeMask_temp,end_temp,extraction_temp,flowMod_temp,
reserved,hvOffset_temp,length_temp,location_temp[0],
location_temp[1],location_temp[2],location_temp[3]} <= q_action;
case(q_action[95:94])
2'b00: state_locationIn <= write_typeOffset;
2'b01: state_locationIn <= write_typeOffset;
2'b10: state_locationIn <= write_end;
2'b11: state_locationIn <= write_fieldLocation_0;
endcase
headerLocation <= q_action[63:56] + q_offset[7:0];
headerLocation_limit <= q_action[55:48];
headerLocation_count <= 8'd0;
end
read_fifo_newHeader: begin
rdreq_newHeader <= 1'b0;
headerOffset_temp <= 8'b0;
{pktID_temp,bid_temp,state_temp,typeOffset_temp,typeMask_temp,end_temp,extraction_temp,flowMod_temp,
reserved,hvOffset_temp,length_temp,location_temp[0],
location_temp[1],location_temp[2],location_temp[3]} <= q_newHeader;
case(q_newHeader[95:94])
2'b00: state_locationIn <= write_typeOffset;
2'b01: state_locationIn <= write_typeOffset;
2'b10: state_locationIn <= write_end;
2'b11: state_locationIn <= write_fieldLocation_0;
endcase
{headerLocation,headerLocation_limit}<= q_newHeader[63:48];
headerLocation_count <= 8'd0;
end
write_typeOffset: begin
wrreq_location <= 1'b1;
data_location <= {pktID_temp,1'b0,1'b1,1'b0,bid_temp,typeMask_temp,typeOffset_temp+headerOffset_temp,state_temp};
state_locationIn <= write_headerOffset;
end
write_headerOffset: begin
wrreq_location <= 1'b1;
data_location <= {pktID_temp,1'b0,1'b0,1'b1,bid_temp,headerOffset_temp,length_temp};
if(extraction_temp==1'b1) state_locationIn <= write_fieldLocation_0;
else state_locationIn <= idle_locationIn;
end
write_fieldLocation_0: begin
wrreq_location <= 1'b1;
data_location <= {pktID_temp,1'b0,1'b0,1'b0,bid_temp,hvOffset_temp,headerLocation,8'b0};
hvOffset_temp <= hvOffset_temp + 8'd1;
if(headerLocation_count < headerLocation_limit) begin
headerLocation_count <= headerLocation_count + 8'd1;
headerLocation <= headerLocation + 8'd4;
state_locationIn <= write_fieldLocation_0;
end
else begin
case({end_temp,location_temp[1][15]})
2'b00: state_locationIn <= idle_locationIn;
2'b10: state_locationIn <= write_end;
default: begin
headerLocation <= location_temp[1][15:8] + headerOffset_temp;
headerLocation_limit <= location_temp[1][7:0];
headerLocation_count <= 8'd0;
state_locationIn <= write_fieldLocation_1;
end
endcase
end
end
write_fieldLocation_1: begin
wrreq_location <= 1'b1;
data_location <= {pktID_temp,1'b0,1'b0,1'b0,bid_temp,hvOffset_temp,headerLocation,8'b0};
hvOffset_temp <= hvOffset_temp + 8'd1;
if(headerLocation_count < headerLocation_limit) begin
headerLocation_count <= headerLocation_count + 8'd1;
headerLocation <= headerLocation + 8'd4;
state_locationIn <= write_fieldLocation_1;
end
else begin
case({end_temp,location_temp[2][15]})
2'b00: state_locationIn <= idle_locationIn;
2'b10: state_locationIn <= write_end;
default: begin
headerLocation <= location_temp[2][15:8] + headerOffset_temp;
headerLocation_limit <= location_temp[2][7:0];
headerLocation_count <= 8'd0;
state_locationIn <= write_fieldLocation_2;
end
endcase
end
end
write_fieldLocation_2: begin
wrreq_location <= 1'b1;
data_location <= {pktID_temp,1'b0,1'b0,1'b0,bid_temp,hvOffset_temp,headerLocation,8'b0};
hvOffset_temp <= hvOffset_temp + 8'd1;
if(headerLocation_count < headerLocation_limit) begin
headerLocation_count <= headerLocation_count + 8'd1;
headerLocation <= headerLocation + 8'd4;
state_locationIn <= write_fieldLocation_2;
end
else begin
case({end_temp,location_temp[3][15]})
2'b00: state_locationIn <= idle_locationIn;
2'b10: state_locationIn <= write_end;
default: begin
headerLocation <= location_temp[3][15:8] + headerOffset_temp;
headerLocation_limit <= location_temp[3][7:0];
headerLocation_count <= 8'd0;
state_locationIn <= write_fieldLocation_3;
end
endcase
end
end
write_fieldLocation_3: begin
wrreq_location <= 1'b1;
data_location <= {pktID_temp,1'b0,1'b0,1'b0,bid_temp,hvOffset_temp,headerLocation,8'b0};
hvOffset_temp <= hvOffset_temp + 8'd1;
if(headerLocation_count < headerLocation_limit) begin
headerLocation_count <= headerLocation_count + 8'd1;
headerLocation <= headerLocation + 8'd4;
state_locationIn <= write_fieldLocation_3;
end
else begin
if(end_temp==1'b1) state_locationIn <= write_end;
else state_locationIn <= idle_locationIn;
end
end
write_end: begin
wrreq_location <= 1'b1;
if(flowMod_temp == 1'b1) data_location <= {pktID_temp,1'b1,2'b0,bid_temp,1'b1,23'b0};
else data_location <= {pktID_temp,1'b1,2'b0,bid_temp,24'b0};
state_locationIn <= idle_locationIn;
end
default: state_locationIn <= idle_locationIn;
endcase
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
wren_b <= 1'b0;
addr_b <= 8'd0;
data_b <= 32'b0;
state_headIn <= 1'b0;
bid_count_add <= 1'b0;
wrreq_newHeader <= 1'b0;
data_newHeader <= 133'b0;
end
else begin
case(state_headIn)
1'b0: begin
if(headerData_valid==1'b1) begin
wren_b <= 1'b1;
addr_b <= {ramID,6'b0};
data_b <= headerData;
state_headIn <= 1'b1;
bid_count_add <= 1'b1;
end
else wren_b <= 1'b0;
wrreq_newHeader <= 1'b0;
end
1'b1: begin
if(headerData_finish_valid == 1'b1) begin
state_headIn <= 1'b0;
data_newHeader <= {pktID,extractionID[2:0],ramID,8'h0,8'd12,8'd16,2'b01,6'b0,8'b0,8'b0,8'd14,1'b1,7'b0,8'd3,48'b0};
wrreq_newHeader <= 1'b1;
end
else state_headIn <= 1'b1;
wren_b <= 1'b1;
addr_b <= addr_b + 8'd1;
data_b <= headerData;
bid_count_add <= 1'b0;
end
endcase
end
end
reg [1:0] state_bid;
parameter idle_bid = 2'd0,
write_fifo_bid = 2'd1,
ready_bid = 2'd2;
always @(posedge clk or negedge reset) begin
if(!reset) begin
bid_enable <= 1'b0;
bid_count <= 3'd0;
state_bid <= idle_bid;
data_bid <= 5'b0;
wrreq_bid <= 1'b0;
end
else begin
case(state_bid)
idle_bid: begin
data_bid <= {extractionID[2:0],2'b0};
wrreq_bid <= 1'b1;
state_bid <= write_fifo_bid;
end
write_fifo_bid: begin
if(data_bid[1:0]==2'd2) state_bid <= ready_bid;
else state_bid <= write_fifo_bid;
data_bid <= data_bid + 5'd1;
end
ready_bid: begin
if(field_finish_valid==1'b1) begin
wrreq_bid <= 1'b1;
data_bid <= field_finish_bid[12:8];
end
else wrreq_bid <= 1'b0;
state_bid <= ready_bid;
end
default: state_bid <= idle_bid;
endcase
if(bid_count > 3'd0) bid_enable <= 1'b1;
else bid_enable <= 1'b0;
case({bid_count_add,wrreq_bid})
2'b00: bid_count <= bid_count;
2'b01: bid_count <= bid_count + 3'd1;
2'b10: bid_count <= bid_count - 3'd1;
2'b11: bid_count <= bid_count;
default: bid_count <= bid_count;
endcase
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
rdreq_bid <= 1'b0;
ramID <= 2'b0;
end
else begin
ramID <= q_bid[1:0];
if(headerData_finish_valid==1'b1) rdreq_bid <= 1'b1;
else rdreq_bid <= 1'b0;
end
end
always @ (posedge clk or negedge reset) begin
if(!reset) begin
wrreq_action <= 1'b0;
data_action <= 125'b0;
end
else begin
if((action_valid == 1'b1) && action[124:122]==extractionID[2:0]) begin
wrreq_action <= 1'b1;
data_action <= action;
end
else wrreq_action <= 1'b0;
end
end
ram ram_32_256(
.address_a(addr_a),
.address_b(addr_b),
.clock(clk),
.data_a({widthHeaderData{1'b0}}),
.data_b(data_b),
.rden_a(rden_a),
.rden_b(1'b0),
.wren_a(1'b0),
.wren_b(wren_b),
.q_a(q_a),
.q_b()
);
defparam
ram_32_256.width = widthHeaderData,
ram_32_256.depth = 8,
ram_32_256.words = 256;
fifo fifo_action(
.aclr(!reset),
.clock(clk),
.data(data_action),
.rdreq(rdreq_action),
.wrreq(wrreq_action),
.empty(empty_action),
.full(),
.q(q_action),
.usedw()
);
defparam
fifo_action.width = 125,
fifo_action.depth = 3,
fifo_action.words = 8;
fifo fifo_newHeader(
.aclr(!reset),
.clock(clk),
.data(data_newHeader),
.rdreq(rdreq_newHeader),
.wrreq(wrreq_newHeader),
.empty(empty_newHeader),
.full(),
.q(q_newHeader),
.usedw()
);
defparam
fifo_newHeader.width = 133,
fifo_newHeader.depth = 3,
fifo_newHeader.words = 8;
fifo fifo_location(
.aclr(!reset),
.clock(clk),
.data(data_location),
.rdreq(rdreq_location),
.wrreq(wrreq_location),
.empty(empty_location),
.full(),
.q(q_location),
.usedw()
);
defparam
fifo_location.width = 40,
fifo_location.depth = 3,
fifo_location.words = 8;
fifo fifo_offset(
.aclr(!reset),
.clock(clk),
.data(offset),
.rdreq(rdreq_offset),
.wrreq(offset_valid),
.empty(empty_offset),
.full(),
.q(q_offset),
.usedw()
);
defparam
fifo_offset.width = 16,
fifo_offset.depth = 4,
fifo_offset.words = 16;
fifo fifo_bid(
.aclr(!reset),
.clock(clk),
.data(data_bid),
.rdreq(headerData_finish_valid),
.wrreq(wrreq_bid),
.empty(empty_bid),
.full(),
.q(q_bid),
.usedw()
);
defparam
fifo_bid.width = 5,
fifo_bid.depth = 4,
fifo_bid.words = 16;
endmodule | module extractor(
clk,
reset,
headerData_valid,
headerData,
headerData_finish_valid,
pktID,
action_valid,
action,
field_valid,
field,
hvOffset,
field_finish_valid,
field_finish_bid,
bid_enable,
stateType_valid,
stateType
); |
parameter extractionID = 1,
widthExtraction = 3,
widthHeaderData = 32;
integer i;
input clk;
input reset;
input headerData_valid;
input [widthHeaderData-1:0] headerData;
input headerData_finish_valid;
input [7:0] pktID;
input action_valid;
input [124:0] action;
output reg field_valid;
output reg [widthHeaderData-1:0] field;
output reg [11:0] hvOffset;
output reg field_finish_valid;
output reg [23:0] field_finish_bid;
output reg bid_enable;
output reg stateType_valid;
output reg [44:0] stateType;
reg [2:0] bid_count;
reg bid_count_add;
reg state_headIn;
reg [1:0] ramID;
reg [5:0] addr_temp;
reg [7:0] pktID_temp;
reg [4:0] bid_temp;
reg [7:0] state_temp;
reg [7:0] typeOffset_temp;
reg [7:0] typeMask_temp;
reg end_temp;
reg extraction_temp;
reg flowMod_temp;
reg [4:0] reserved;
reg [7:0] hvOffset_temp,hvOffset_temp_reserved;
reg [15:0] length_temp;
reg [15:0] location_temp[3:0];
reg [7:0] headerOffset_temp;
reg [7:0] headerLocation;
reg [7:0] headerLocation_count,headerLocation_limit;
reg [117:0] action_temp;
reg [3:0] state_locationIn;
parameter idle_locationIn = 4'd0,
read_fifo_action = 4'd1,
read_fifo_newHeader = 4'd2,
write_typeOffset = 4'd3,
write_headerOffset = 4'd4,
write_fieldLocation_0=4'd5,
write_fieldLocation_1=4'd6,
write_fieldLocation_2=4'd7,
write_fieldLocation_3=4'd8,
write_end = 4'd9;
reg [7:0] addr_a,addr_b;
reg [widthHeaderData-1:0] data_b;
reg wren_b,rden_a;
wire [widthHeaderData-1:0] q_a;
reg [124:0] data_action;
reg wrreq_action,rdreq_action;
wire empty_action;
wire [124:0] q_action;
reg [132:0] data_newHeader;
reg wrreq_newHeader,rdreq_newHeader;
wire empty_newHeader;
wire [132:0] q_newHeader;
reg [39:0] data_location;
reg wrreq_location,rdreq_location;
wire empty_location;
wire [39:0] q_location;
reg [15:0] offset;
reg offset_valid;
reg rdreq_offset;
wire empty_offset;
wire [15:0] q_offset;
reg [4:0] data_bid;
reg rdreq_bid,wrreq_bid;
wire empty_bid;
wire [4:0] q_bid;
reg stage_enable[4:0];
reg [31:0] q_location_temp[4:0];
reg [7:0] q_pktID_temp[4:0];
reg offset_valid_temp[4:0];
reg [7:0] offset_temp[4:0];
reg [31:0] field_temp,fieldValue,maskBit_temp;
reg state_stage_0,state_stage_1,state_stage_2,state_stage_3;
parameter clock_0 = 1'd0,
clock_1 = 1'd1;
always @(posedge clk or negedge reset) begin
if(!reset) begin
state_stage_0 <= clock_0;
rdreq_location <= 1'b0;
end
else begin
case(state_stage_0)
clock_0: begin
if(empty_location==1'b0) begin
rdreq_location <= 1'b1;
state_stage_0 <= clock_1;
end
else state_stage_0 <= clock_0;
end
clock_1: begin
rdreq_location <= 1'b0;
state_stage_0 <= clock_0;
end
endcase
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
addr_a <= 8'b0;
rden_a <= 1'b0;
stage_enable[0] <= 1'b0;
state_stage_1 <= clock_0;
field_finish_valid <= 1'b0;
field_finish_bid <= 24'b0;
offset_valid_temp[0] <= 1'b0;
offset_temp[0] <= 8'b0;
end
else begin
case(state_stage_1)
clock_0: begin
if(rdreq_location==1'b1) begin
state_stage_1 <= clock_1;
if(q_location[31]==1'b1) begin
rden_a <= 1'b0;
field_finish_valid <= 1'b1;
field_finish_bid <= {q_location[23:16],3'b0,q_location[28:24],q_location[39:32]};
stage_enable[0] <= 1'b0;
end
else if((q_location[29]==1'b1) && (q_location[15]==1'b0)) begin
rden_a <= 1'b0;
offset_valid_temp[0] <= 1'b1;
offset_temp[0] <= q_location[23:16] + q_location[7:0];
stage_enable[0] <= 1'b0;
end
else begin
rden_a <= 1'b1;
addr_a <= {q_location[25:24],{1'b0,q_location[14:10]}};
stage_enable[0] <= 1'b1;
end
end
else begin
state_stage_1 <= clock_0;
rden_a <= 1'b0;
stage_enable[0] <= 1'b0;
end
end
clock_1: begin
if(rden_a==1'b1) addr_a <= addr_a + 8'd1;
field_finish_valid <= 1'b0;
offset_valid_temp[0] <= 1'b0;
state_stage_1 <= clock_0;
end
endcase
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
state_stage_2 <= clock_0;
fieldValue <= 32'b0;
field_temp <= 32'b0;
maskBit_temp <= 32'b0;
end
else begin
case(state_stage_2)
clock_0: begin
if(stage_enable[2]==1'b1) begin
field_temp <= q_a;
state_stage_2 <= clock_1;
end
else state_stage_2 <= clock_0;
end
clock_1: begin
if(stage_enable[3]==1'b1) begin
case(q_location_temp[3][9:8])
2'd0: fieldValue <= field_temp;
2'd1: fieldValue <= {field_temp[23:0],q_a[31:24]};
2'd2: fieldValue <= {field_temp[15:0],q_a[31:16]};
3'd3: fieldValue <= {field_temp[7:0],q_a[31:8]};
endcase
case(q_location_temp[3][23:16])
8'd0: maskBit_temp <= 32'hffff_ffff;
8'd8: maskBit_temp <= 32'hffff_ff00;
8'd16: maskBit_temp <= 32'hffff_0000;
8'd24: maskBit_temp <= 32'hff00_0000;
default: maskBit_temp <= 32'hffff_ffff;
endcase
end
state_stage_2 <= clock_0;
end
endcase
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
state_stage_3 <= clock_0;
offset_valid <= 1'b0;
offset <= 16'b0;
stateType_valid <= 1'b0;
stateType <= 45'b0;
field_valid <= 1'b0;
field <= 32'b0;
hvOffset <= 12'b0;
end
else begin
case(state_stage_3)
clock_0: begin
if(stage_enable[4]==1'b1) begin
case(q_location_temp[4][31:29])
3'b000: begin
hvOffset <= {q_location_temp[4][28:24],q_location_temp[4][22:16]};
field_valid <= 1'b1;
field <= fieldValue;
end
3'b010: begin
stateType_valid <= 1'b1;
stateType <= {q_location_temp[4][28:24],fieldValue&maskBit_temp,q_location_temp[4][7:0]};
end
3'b001: begin
offset_valid <= 1'b1;
if(q_location_temp[4][0]==1'b0) offset <= {q_pktID_temp[4],q_location_temp[4][23:16] + fieldValue[31:28]*4};
else offset <= {q_pktID_temp[4],q_location_temp[4][23:16] + fieldValue[27:24]*4};
end
default: begin
end
endcase
state_stage_3 <= clock_1;
end
else if(offset_valid_temp[4]==1'b1) begin
offset_valid <= 1'b1;
offset <= {q_pktID_temp[4],offset_temp[4]};
state_stage_3 <= clock_1;
end
else state_stage_3 <= clock_0;
end
clock_1: begin
offset_valid <= 1'b0;
stateType_valid <= 1'b0;
field_valid <= 1'b0;
state_stage_3 <= clock_0;
end
endcase
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
stage_enable[1] <= 1'b0;stage_enable[2] <= 1'b0;
stage_enable[3] <= 1'b0;stage_enable[4] <= 1'b0;
offset_valid_temp[1] <= 1'b0;offset_valid_temp[2] <= 1'b0;
end
else begin
stage_enable[1] <= stage_enable[0];
stage_enable[2] <= stage_enable[1];
stage_enable[3] <= stage_enable[2];
stage_enable[4] <= stage_enable[3];
q_location_temp[0] <= q_location[31:0];
q_location_temp[1] <= q_location_temp[0];
q_location_temp[2] <= q_location_temp[1];
q_location_temp[3] <= q_location_temp[2];
q_location_temp[4] <= q_location_temp[3];
q_pktID_temp[0] <= q_location[39:32];
q_pktID_temp[1] <= q_pktID_temp[0];
q_pktID_temp[2] <= q_pktID_temp[1];
q_pktID_temp[3] <= q_pktID_temp[2];
q_pktID_temp[4] <= q_pktID_temp[3];
offset_valid_temp[1] <= offset_valid_temp[0];
offset_valid_temp[2] <= offset_valid_temp[1];
offset_valid_temp[3] <= offset_valid_temp[2];
offset_valid_temp[4] <= offset_valid_temp[3];
offset_temp[1] <= offset_temp[0];
offset_temp[2] <= offset_temp[1];
offset_temp[3] <= offset_temp[2];
offset_temp[4] <= offset_temp[3];
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
wrreq_location <= 1'b0;
data_location <= 40'b0;
state_locationIn <= idle_locationIn;
rdreq_action <= 1'b0;
rdreq_newHeader <= 1'b0;
rdreq_offset <= 1'b0;
pktID_temp <= 8'd0;
typeMask_temp <= 8'd0;
end
else begin
case(state_locationIn)
idle_locationIn: begin
wrreq_location <= 1'b0;
if(empty_action == 1'b0) begin
state_locationIn <= read_fifo_action;
rdreq_action <= 1'b1;
rdreq_offset <= 1'b1;
end
else if(empty_newHeader == 1'b0) begin
state_locationIn <= read_fifo_newHeader;
rdreq_newHeader <= 1'b1;
end
else state_locationIn <= 1'b0;
end
read_fifo_action: begin
rdreq_action <= 1'b0;
rdreq_offset <= 1'b0;
{pktID_temp,headerOffset_temp} <= q_offset;
{bid_temp,state_temp,typeOffset_temp,typeMask_temp,end_temp,extraction_temp,flowMod_temp,
reserved,hvOffset_temp,length_temp,location_temp[0],
location_temp[1],location_temp[2],location_temp[3]} <= q_action;
case(q_action[95:94])
2'b00: state_locationIn <= write_typeOffset;
2'b01: state_locationIn <= write_typeOffset;
2'b10: state_locationIn <= write_end;
2'b11: state_locationIn <= write_fieldLocation_0;
endcase
headerLocation <= q_action[63:56] + q_offset[7:0];
headerLocation_limit <= q_action[55:48];
headerLocation_count <= 8'd0;
end
read_fifo_newHeader: begin
rdreq_newHeader <= 1'b0;
headerOffset_temp <= 8'b0;
{pktID_temp,bid_temp,state_temp,typeOffset_temp,typeMask_temp,end_temp,extraction_temp,flowMod_temp,
reserved,hvOffset_temp,length_temp,location_temp[0],
location_temp[1],location_temp[2],location_temp[3]} <= q_newHeader;
case(q_newHeader[95:94])
2'b00: state_locationIn <= write_typeOffset;
2'b01: state_locationIn <= write_typeOffset;
2'b10: state_locationIn <= write_end;
2'b11: state_locationIn <= write_fieldLocation_0;
endcase
{headerLocation,headerLocation_limit}<= q_newHeader[63:48];
headerLocation_count <= 8'd0;
end
write_typeOffset: begin
wrreq_location <= 1'b1;
data_location <= {pktID_temp,1'b0,1'b1,1'b0,bid_temp,typeMask_temp,typeOffset_temp+headerOffset_temp,state_temp};
state_locationIn <= write_headerOffset;
end
write_headerOffset: begin
wrreq_location <= 1'b1;
data_location <= {pktID_temp,1'b0,1'b0,1'b1,bid_temp,headerOffset_temp,length_temp};
if(extraction_temp==1'b1) state_locationIn <= write_fieldLocation_0;
else state_locationIn <= idle_locationIn;
end
write_fieldLocation_0: begin
wrreq_location <= 1'b1;
data_location <= {pktID_temp,1'b0,1'b0,1'b0,bid_temp,hvOffset_temp,headerLocation,8'b0};
hvOffset_temp <= hvOffset_temp + 8'd1;
if(headerLocation_count < headerLocation_limit) begin
headerLocation_count <= headerLocation_count + 8'd1;
headerLocation <= headerLocation + 8'd4;
state_locationIn <= write_fieldLocation_0;
end
else begin
case({end_temp,location_temp[1][15]})
2'b00: state_locationIn <= idle_locationIn;
2'b10: state_locationIn <= write_end;
default: begin
headerLocation <= location_temp[1][15:8] + headerOffset_temp;
headerLocation_limit <= location_temp[1][7:0];
headerLocation_count <= 8'd0;
state_locationIn <= write_fieldLocation_1;
end
endcase
end
end
write_fieldLocation_1: begin
wrreq_location <= 1'b1;
data_location <= {pktID_temp,1'b0,1'b0,1'b0,bid_temp,hvOffset_temp,headerLocation,8'b0};
hvOffset_temp <= hvOffset_temp + 8'd1;
if(headerLocation_count < headerLocation_limit) begin
headerLocation_count <= headerLocation_count + 8'd1;
headerLocation <= headerLocation + 8'd4;
state_locationIn <= write_fieldLocation_1;
end
else begin
case({end_temp,location_temp[2][15]})
2'b00: state_locationIn <= idle_locationIn;
2'b10: state_locationIn <= write_end;
default: begin
headerLocation <= location_temp[2][15:8] + headerOffset_temp;
headerLocation_limit <= location_temp[2][7:0];
headerLocation_count <= 8'd0;
state_locationIn <= write_fieldLocation_2;
end
endcase
end
end
write_fieldLocation_2: begin
wrreq_location <= 1'b1;
data_location <= {pktID_temp,1'b0,1'b0,1'b0,bid_temp,hvOffset_temp,headerLocation,8'b0};
hvOffset_temp <= hvOffset_temp + 8'd1;
if(headerLocation_count < headerLocation_limit) begin
headerLocation_count <= headerLocation_count + 8'd1;
headerLocation <= headerLocation + 8'd4;
state_locationIn <= write_fieldLocation_2;
end
else begin
case({end_temp,location_temp[3][15]})
2'b00: state_locationIn <= idle_locationIn;
2'b10: state_locationIn <= write_end;
default: begin
headerLocation <= location_temp[3][15:8] + headerOffset_temp;
headerLocation_limit <= location_temp[3][7:0];
headerLocation_count <= 8'd0;
state_locationIn <= write_fieldLocation_3;
end
endcase
end
end
write_fieldLocation_3: begin
wrreq_location <= 1'b1;
data_location <= {pktID_temp,1'b0,1'b0,1'b0,bid_temp,hvOffset_temp,headerLocation,8'b0};
hvOffset_temp <= hvOffset_temp + 8'd1;
if(headerLocation_count < headerLocation_limit) begin
headerLocation_count <= headerLocation_count + 8'd1;
headerLocation <= headerLocation + 8'd4;
state_locationIn <= write_fieldLocation_3;
end
else begin
if(end_temp==1'b1) state_locationIn <= write_end;
else state_locationIn <= idle_locationIn;
end
end
write_end: begin
wrreq_location <= 1'b1;
if(flowMod_temp == 1'b1) data_location <= {pktID_temp,1'b1,2'b0,bid_temp,1'b1,23'b0};
else data_location <= {pktID_temp,1'b1,2'b0,bid_temp,24'b0};
state_locationIn <= idle_locationIn;
end
default: state_locationIn <= idle_locationIn;
endcase
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
wren_b <= 1'b0;
addr_b <= 8'd0;
data_b <= 32'b0;
state_headIn <= 1'b0;
bid_count_add <= 1'b0;
wrreq_newHeader <= 1'b0;
data_newHeader <= 133'b0;
end
else begin
case(state_headIn)
1'b0: begin
if(headerData_valid==1'b1) begin
wren_b <= 1'b1;
addr_b <= {ramID,6'b0};
data_b <= headerData;
state_headIn <= 1'b1;
bid_count_add <= 1'b1;
end
else wren_b <= 1'b0;
wrreq_newHeader <= 1'b0;
end
1'b1: begin
if(headerData_finish_valid == 1'b1) begin
state_headIn <= 1'b0;
data_newHeader <= {pktID,extractionID[2:0],ramID,8'h0,8'd12,8'd16,2'b01,6'b0,8'b0,8'b0,8'd14,1'b1,7'b0,8'd3,48'b0};
wrreq_newHeader <= 1'b1;
end
else state_headIn <= 1'b1;
wren_b <= 1'b1;
addr_b <= addr_b + 8'd1;
data_b <= headerData;
bid_count_add <= 1'b0;
end
endcase
end
end
reg [1:0] state_bid;
parameter idle_bid = 2'd0,
write_fifo_bid = 2'd1,
ready_bid = 2'd2;
always @(posedge clk or negedge reset) begin
if(!reset) begin
bid_enable <= 1'b0;
bid_count <= 3'd0;
state_bid <= idle_bid;
data_bid <= 5'b0;
wrreq_bid <= 1'b0;
end
else begin
case(state_bid)
idle_bid: begin
data_bid <= {extractionID[2:0],2'b0};
wrreq_bid <= 1'b1;
state_bid <= write_fifo_bid;
end
write_fifo_bid: begin
if(data_bid[1:0]==2'd2) state_bid <= ready_bid;
else state_bid <= write_fifo_bid;
data_bid <= data_bid + 5'd1;
end
ready_bid: begin
if(field_finish_valid==1'b1) begin
wrreq_bid <= 1'b1;
data_bid <= field_finish_bid[12:8];
end
else wrreq_bid <= 1'b0;
state_bid <= ready_bid;
end
default: state_bid <= idle_bid;
endcase
if(bid_count > 3'd0) bid_enable <= 1'b1;
else bid_enable <= 1'b0;
case({bid_count_add,wrreq_bid})
2'b00: bid_count <= bid_count;
2'b01: bid_count <= bid_count + 3'd1;
2'b10: bid_count <= bid_count - 3'd1;
2'b11: bid_count <= bid_count;
default: bid_count <= bid_count;
endcase
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
rdreq_bid <= 1'b0;
ramID <= 2'b0;
end
else begin
ramID <= q_bid[1:0];
if(headerData_finish_valid==1'b1) rdreq_bid <= 1'b1;
else rdreq_bid <= 1'b0;
end
end
always @ (posedge clk or negedge reset) begin
if(!reset) begin
wrreq_action <= 1'b0;
data_action <= 125'b0;
end
else begin
if((action_valid == 1'b1) && action[124:122]==extractionID[2:0]) begin
wrreq_action <= 1'b1;
data_action <= action;
end
else wrreq_action <= 1'b0;
end
end
ram ram_32_256(
.address_a(addr_a),
.address_b(addr_b),
.clock(clk),
.data_a({widthHeaderData{1'b0}}),
.data_b(data_b),
.rden_a(rden_a),
.rden_b(1'b0),
.wren_a(1'b0),
.wren_b(wren_b),
.q_a(q_a),
.q_b()
);
defparam
ram_32_256.width = widthHeaderData,
ram_32_256.depth = 8,
ram_32_256.words = 256;
fifo fifo_action(
.aclr(!reset),
.clock(clk),
.data(data_action),
.rdreq(rdreq_action),
.wrreq(wrreq_action),
.empty(empty_action),
.full(),
.q(q_action),
.usedw()
);
defparam
fifo_action.width = 125,
fifo_action.depth = 3,
fifo_action.words = 8;
fifo fifo_newHeader(
.aclr(!reset),
.clock(clk),
.data(data_newHeader),
.rdreq(rdreq_newHeader),
.wrreq(wrreq_newHeader),
.empty(empty_newHeader),
.full(),
.q(q_newHeader),
.usedw()
);
defparam
fifo_newHeader.width = 133,
fifo_newHeader.depth = 3,
fifo_newHeader.words = 8;
fifo fifo_location(
.aclr(!reset),
.clock(clk),
.data(data_location),
.rdreq(rdreq_location),
.wrreq(wrreq_location),
.empty(empty_location),
.full(),
.q(q_location),
.usedw()
);
defparam
fifo_location.width = 40,
fifo_location.depth = 3,
fifo_location.words = 8;
fifo fifo_offset(
.aclr(!reset),
.clock(clk),
.data(offset),
.rdreq(rdreq_offset),
.wrreq(offset_valid),
.empty(empty_offset),
.full(),
.q(q_offset),
.usedw()
);
defparam
fifo_offset.width = 16,
fifo_offset.depth = 4,
fifo_offset.words = 16;
fifo fifo_bid(
.aclr(!reset),
.clock(clk),
.data(data_bid),
.rdreq(headerData_finish_valid),
.wrreq(wrreq_bid),
.empty(empty_bid),
.full(),
.q(q_bid),
.usedw()
);
defparam
fifo_bid.width = 5,
fifo_bid.depth = 4,
fifo_bid.words = 16;
endmodule | 0 |
138,279 | data/full_repos/permissive/83198026/hash_function.v | 83,198,026 | hash_function.v | v | 56 | 46 | [] | [] | [] | [(1, 55)] | null | data/verilator_xmls/11af6da2-c44f-470c-b078-b6ee96302b57.xml | null | 302,117 | module | module hash_function(
clk,
reset,
key_valid,
key,
hash_value_valid,
hash_1,
hash_2,
hash_3
);
input clk;
input reset;
input key_valid;
input [39:0] key;
output reg hash_value_valid;
output reg [8:0] hash_1;
output reg [8:0] hash_2;
output reg [8:0] hash_3;
reg state;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
hash_value_valid <= 1'b0;
hash_1 <= 9'd0;
hash_2 <= 9'd0;
hash_3 <= 9'd0;
state <= 1'b0;
end
else begin
case(state)
1'b0: begin
if(key_valid == 1'b1) begin
hash_value_valid <= 1'b1;
hash_1 <= {1'b0,key[39:35],key[2:0]};
hash_2 <= {1'b0,key[39:35],key[2:0]};
hash_3 <= {1'b0,key[39:35],key[2:0]};
state <= 1'b1;
end
else hash_value_valid <= 1'b0;
end
1'b1: begin
hash_value_valid <= 1'b1;
hash_1 <= {1'b1,key[39:35],key[2:0]};
hash_2 <= {1'b1,key[34:30],key[2:0]};
hash_3 <= {1'b1,key[34:30],key[2:0]};
state <= 1'b0;
end
endcase
end
end
endmodule | module hash_function(
clk,
reset,
key_valid,
key,
hash_value_valid,
hash_1,
hash_2,
hash_3
); |
input clk;
input reset;
input key_valid;
input [39:0] key;
output reg hash_value_valid;
output reg [8:0] hash_1;
output reg [8:0] hash_2;
output reg [8:0] hash_3;
reg state;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
hash_value_valid <= 1'b0;
hash_1 <= 9'd0;
hash_2 <= 9'd0;
hash_3 <= 9'd0;
state <= 1'b0;
end
else begin
case(state)
1'b0: begin
if(key_valid == 1'b1) begin
hash_value_valid <= 1'b1;
hash_1 <= {1'b0,key[39:35],key[2:0]};
hash_2 <= {1'b0,key[39:35],key[2:0]};
hash_3 <= {1'b0,key[39:35],key[2:0]};
state <= 1'b1;
end
else hash_value_valid <= 1'b0;
end
1'b1: begin
hash_value_valid <= 1'b1;
hash_1 <= {1'b1,key[39:35],key[2:0]};
hash_2 <= {1'b1,key[34:30],key[2:0]};
hash_3 <= {1'b1,key[34:30],key[2:0]};
state <= 1'b0;
end
endcase
end
end
endmodule | 0 |
138,280 | data/full_repos/permissive/83198026/head_buffer.v | 83,198,026 | head_buffer.v | v | 201 | 84 | [] | [] | [] | null | line:193: before: "." | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/83198026/head_buffer.v:96: Operator ASSIGNDLY expects 45 bits on the Assign RHS, but Assign RHS\'s CONST \'37\'h0\' generates 37 bits.\n : ... In instance head_buffer\n type_out <= 37\'b0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/83198026/head_buffer.v:179: Cannot find file containing module: \'ram\'\nram ram_32_1024(\n^~~\n ... Looked in:\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/ram\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/ram.v\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/ram.sv\n ram\n ram.v\n ram.sv\n obj_dir/ram\n obj_dir/ram.v\n obj_dir/ram.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 302,118 | module | module head_buffer(
clk,
reset,
head_in,
head_in_valid,
ramID,
addr_in,
addr_in_valid,
type_out,
type_out_valid
);
input clk;
input reset;
input [31:0] head_in;
input head_in_valid;
input [4:0] ramID;
input [19:0] addr_in;
input addr_in_valid;
output reg [44:0] type_out;
output reg type_out_valid;
reg [4:0] ramIDtemp[3:0];
reg addr_in_validTemp[3:0];
reg [7:0] stateTemp[3:0];
reg [9:0] addr_a,addr_b;
reg rden_a,wren_b;
reg [31:0] data_b;
wire [31:0] q_a;
reg [1:0] addr_temp[3:0];
reg [31:0] type_temp;
parameter idle = 3'd0,
wait_1 = 3'd1,
wait_2 = 3'd2,
read_1 = 3'd3,
read_2 = 3'd4;
reg state_headIn;
always @(posedge clk or negedge reset) begin
if(!reset) begin
rden_a <= 1'b0;
addr_a <= 10'b0;
end
else begin
if(addr_in_valid == 1'b1) begin
rden_a <= 1'b1;
addr_a <= {5'b0,addr_in[6:2]};
end
else if (addr_in_validTemp[0]==1'b1) begin
rden_a <= 1'b1;
addr_a <= addr_a+10'd1;
end
else rden_a <= 1'b0;
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
type_temp <= 32'b0;
end
else begin
type_temp <= q_a;
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
type_out_valid <= 1'b0;
type_out <= 37'b0;
end
else begin
if(addr_in_validTemp[3] == 1'b1) begin
type_out_valid <= 1'b1;
case(addr_temp[3])
2'd0: type_out <= {ramIDtemp[3],type_temp,stateTemp[3]};
2'd1: type_out <= {ramIDtemp[3],type_temp[23:0],q_a[31:24],stateTemp[3]};
2'd2: type_out <= {ramIDtemp[3],type_temp[15:0],q_a[31:16],stateTemp[3]};
2'd3: type_out <= {ramIDtemp[3],type_temp[7:0],q_a[31:8],stateTemp[3]};
endcase
end
else type_out_valid <= 1'b0;
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
ramIDtemp[0] <= 5'd0;ramIDtemp[1] <= 5'd0;
ramIDtemp[2] <= 5'd0;ramIDtemp[3] <= 5'd0;
addr_temp[0] <= 2'b0;
addr_in_validTemp[0] <= 1'b0;
stateTemp[0] <= 8'd0;
end
else begin
ramIDtemp[0] <= addr_in[11:7];
ramIDtemp[1] <= ramIDtemp[0];
ramIDtemp[2] <= ramIDtemp[1];
ramIDtemp[3] <= ramIDtemp[2];
addr_temp[0] <= addr_in[1:0];
addr_temp[1] <= addr_temp[0];
addr_temp[2] <= addr_temp[1];
addr_temp[3] <= addr_temp[2];
addr_in_validTemp[0] <= addr_in_valid;
addr_in_validTemp[1] <= addr_in_validTemp[0];
addr_in_validTemp[2] <= addr_in_validTemp[1];
addr_in_validTemp[3] <= addr_in_validTemp[2];
stateTemp[0] <= addr_in[19:12];
stateTemp[1] <= stateTemp[0];
stateTemp[2] <= stateTemp[1];
stateTemp[3] <= stateTemp[2];
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
wren_b <= 1'b0;
addr_b <= 10'b0;
state_headIn <= 1'b0;
end
else begin
case(state_headIn)
1'b0: begin
if(head_in_valid==1'b1) begin
wren_b <= 1'b1;
addr_b <= {ramID,5'b0};
data_b <= head_in;
state_headIn <= 1'b1;
end
else wren_b <= 1'b0;
end
1'b1: begin
if(head_in_valid == 1'b1) begin
wren_b <= 1'b1;
addr_b <= addr_b + 10'd1;
data_b <= head_in;
state_headIn <= 1'b1;
end
else begin
wren_b <= 1'b0;
state_headIn <= 1'b0;
end
end
endcase
end
end
ram ram_32_1024(
.address_a(addr_a),
.address_b(addr_b),
.clock(clk),
.data_a(32'b0),
.data_b(data_b),
.rden_a(rden_a),
.rden_b(1'b0),
.wren_a(1'b0),
.wren_b(wren_b),
.q_a(q_a),
.q_b()
);
defparam
ram_32_1024.width = 32,
ram_32_1024.depth = 10,
ram_32_1024.words = 1024;
endmodule | module head_buffer(
clk,
reset,
head_in,
head_in_valid,
ramID,
addr_in,
addr_in_valid,
type_out,
type_out_valid
); |
input clk;
input reset;
input [31:0] head_in;
input head_in_valid;
input [4:0] ramID;
input [19:0] addr_in;
input addr_in_valid;
output reg [44:0] type_out;
output reg type_out_valid;
reg [4:0] ramIDtemp[3:0];
reg addr_in_validTemp[3:0];
reg [7:0] stateTemp[3:0];
reg [9:0] addr_a,addr_b;
reg rden_a,wren_b;
reg [31:0] data_b;
wire [31:0] q_a;
reg [1:0] addr_temp[3:0];
reg [31:0] type_temp;
parameter idle = 3'd0,
wait_1 = 3'd1,
wait_2 = 3'd2,
read_1 = 3'd3,
read_2 = 3'd4;
reg state_headIn;
always @(posedge clk or negedge reset) begin
if(!reset) begin
rden_a <= 1'b0;
addr_a <= 10'b0;
end
else begin
if(addr_in_valid == 1'b1) begin
rden_a <= 1'b1;
addr_a <= {5'b0,addr_in[6:2]};
end
else if (addr_in_validTemp[0]==1'b1) begin
rden_a <= 1'b1;
addr_a <= addr_a+10'd1;
end
else rden_a <= 1'b0;
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
type_temp <= 32'b0;
end
else begin
type_temp <= q_a;
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
type_out_valid <= 1'b0;
type_out <= 37'b0;
end
else begin
if(addr_in_validTemp[3] == 1'b1) begin
type_out_valid <= 1'b1;
case(addr_temp[3])
2'd0: type_out <= {ramIDtemp[3],type_temp,stateTemp[3]};
2'd1: type_out <= {ramIDtemp[3],type_temp[23:0],q_a[31:24],stateTemp[3]};
2'd2: type_out <= {ramIDtemp[3],type_temp[15:0],q_a[31:16],stateTemp[3]};
2'd3: type_out <= {ramIDtemp[3],type_temp[7:0],q_a[31:8],stateTemp[3]};
endcase
end
else type_out_valid <= 1'b0;
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
ramIDtemp[0] <= 5'd0;ramIDtemp[1] <= 5'd0;
ramIDtemp[2] <= 5'd0;ramIDtemp[3] <= 5'd0;
addr_temp[0] <= 2'b0;
addr_in_validTemp[0] <= 1'b0;
stateTemp[0] <= 8'd0;
end
else begin
ramIDtemp[0] <= addr_in[11:7];
ramIDtemp[1] <= ramIDtemp[0];
ramIDtemp[2] <= ramIDtemp[1];
ramIDtemp[3] <= ramIDtemp[2];
addr_temp[0] <= addr_in[1:0];
addr_temp[1] <= addr_temp[0];
addr_temp[2] <= addr_temp[1];
addr_temp[3] <= addr_temp[2];
addr_in_validTemp[0] <= addr_in_valid;
addr_in_validTemp[1] <= addr_in_validTemp[0];
addr_in_validTemp[2] <= addr_in_validTemp[1];
addr_in_validTemp[3] <= addr_in_validTemp[2];
stateTemp[0] <= addr_in[19:12];
stateTemp[1] <= stateTemp[0];
stateTemp[2] <= stateTemp[1];
stateTemp[3] <= stateTemp[2];
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
wren_b <= 1'b0;
addr_b <= 10'b0;
state_headIn <= 1'b0;
end
else begin
case(state_headIn)
1'b0: begin
if(head_in_valid==1'b1) begin
wren_b <= 1'b1;
addr_b <= {ramID,5'b0};
data_b <= head_in;
state_headIn <= 1'b1;
end
else wren_b <= 1'b0;
end
1'b1: begin
if(head_in_valid == 1'b1) begin
wren_b <= 1'b1;
addr_b <= addr_b + 10'd1;
data_b <= head_in;
state_headIn <= 1'b1;
end
else begin
wren_b <= 1'b0;
state_headIn <= 1'b0;
end
end
endcase
end
end
ram ram_32_1024(
.address_a(addr_a),
.address_b(addr_b),
.clock(clk),
.data_a(32'b0),
.data_b(data_b),
.rden_a(rden_a),
.rden_b(1'b0),
.wren_a(1'b0),
.wren_b(wren_b),
.q_a(q_a),
.q_b()
);
defparam
ram_32_1024.width = 32,
ram_32_1024.depth = 10,
ram_32_1024.words = 1024;
endmodule | 0 |
138,281 | data/full_repos/permissive/83198026/identifier.v | 83,198,026 | identifier.v | v | 211 | 88 | [] | [] | [] | null | line:198: before: "." | null | 1: b"%Error: data/full_repos/permissive/83198026/identifier.v:186: Cannot find file containing module: 'fifo'\n fifo fifo_stateType(\n ^~~~\n ... Looked in:\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/fifo\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/fifo.v\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/fifo.sv\n fifo\n fifo.v\n fifo.sv\n obj_dir/fifo\n obj_dir/fifo.v\n obj_dir/fifo.sv\n%Error: Exiting due to 1 error(s)\n" | 302,119 | module | module identifier(
clk,
reset,
stateType_valid_0,
stateType_0,
stateType_valid_1,
stateType_1,
stateType_valid_2,
stateType_2,
stateType_valid_3,
stateType_3,
stateType_valid_4,
stateType_4,
stateType_valid_5,
stateType_5,
stateType_valid_6,
stateType_6,
stateType_valid_7,
stateType_7,
type_out,
type_out_valid
);
parameter numExtraction = 8,
widthExtraction =3,
widthHeaderData = 32;
input clk;
input reset;
input stateType_valid_0;
input [44:0] stateType_0;
input stateType_valid_1;
input [44:0] stateType_1;
input stateType_valid_2;
input [44:0] stateType_2;
input stateType_valid_3;
input [44:0] stateType_3;
input stateType_valid_4;
input [44:0] stateType_4;
input stateType_valid_5;
input [44:0] stateType_5;
input stateType_valid_6;
input [44:0] stateType_6;
input stateType_valid_7;
input [44:0] stateType_7;
output reg [44:0] type_out;
output reg type_out_valid;
integer i;
wire [44:0] data_stateType[numExtraction-1:0];
wire wrreq_stateType[numExtraction-1:0];
reg rdreq_stateType[numExtraction-1:0];
wire empty_stateType[numExtraction-1:0];
wire [44:0] q_stateType[numExtraction-1:0];
assign data_stateType[0] = stateType_0;
assign data_stateType[1] = stateType_1;
assign data_stateType[2] = stateType_2;
assign data_stateType[3] = stateType_3;
assign data_stateType[4] = stateType_4;
assign data_stateType[5] = stateType_5;
assign data_stateType[6] = stateType_6;
assign data_stateType[7] = stateType_7;
assign wrreq_stateType[0]= stateType_valid_0;
assign wrreq_stateType[1]= stateType_valid_1;
assign wrreq_stateType[2]= stateType_valid_2;
assign wrreq_stateType[3]= stateType_valid_3;
assign wrreq_stateType[4]= stateType_valid_4;
assign wrreq_stateType[5]= stateType_valid_5;
assign wrreq_stateType[6]= stateType_valid_6;
assign wrreq_stateType[7]= stateType_valid_7;
wire [3:0] empty_odd_tag,empty_even_tag;
assign empty_even_tag = {empty_stateType[7],empty_stateType[5],
empty_stateType[3],empty_stateType[1]};
assign empty_odd_tag = {empty_stateType[6],empty_stateType[4],
empty_stateType[2],empty_stateType[0]};
reg stateHungry;
parameter read_odd = 1'd0,
read_even = 1'd1;
always @(posedge clk or negedge reset) begin
if(!reset) begin
stateHungry <= read_odd;
type_out_valid <= 1'b0;
type_out <= 45'b0;
for(i=0;i<numExtraction;i=i+1) rdreq_stateType[i] <= 1'b0;
end
else begin
case(stateHungry)
read_odd: begin
rdreq_stateType[1] <= 1'b0;
rdreq_stateType[3] <= 1'b0;
rdreq_stateType[5] <= 1'b0;
rdreq_stateType[7] <= 1'b0;
if(empty_stateType[0]==1'b0) rdreq_stateType[0] <= 1'b1;
else if(empty_stateType[2]==1'b0) rdreq_stateType[2] <= 1'b1;
else if(empty_stateType[4]==1'b0) rdreq_stateType[4] <= 1'b1;
else if(empty_stateType[6]==1'b0) rdreq_stateType[6] <= 1'b1;
else begin
end
stateHungry <= read_even;
case({rdreq_stateType[7],rdreq_stateType[5],rdreq_stateType[3],rdreq_stateType[1]})
4'h1: begin
type_out_valid <= 1'b1;
type_out <= q_stateType[1];
end
4'h2: begin
type_out_valid <= 1'b1;
type_out <= q_stateType[3];
end
4'h4: begin
type_out_valid <= 1'b1;
type_out <= q_stateType[5];
end
4'h8: begin
type_out_valid <= 1'b1;
type_out <= q_stateType[7];
end
default: begin
type_out_valid <= 1'b0;
end
endcase
end
read_even: begin
rdreq_stateType[0] <= 1'b0;
rdreq_stateType[2] <= 1'b0;
rdreq_stateType[4] <= 1'b0;
rdreq_stateType[6] <= 1'b0;
if(empty_stateType[1]==1'b0) rdreq_stateType[1] <= 1'b1;
else if(empty_stateType[3]==1'b0) rdreq_stateType[3] <= 1'b1;
else if(empty_stateType[5]==1'b0) rdreq_stateType[5] <= 1'b1;
else if(empty_stateType[7]==1'b0) rdreq_stateType[7] <= 1'b1;
else begin
end
stateHungry <= read_odd;
case({rdreq_stateType[6],rdreq_stateType[4],rdreq_stateType[2],rdreq_stateType[0]})
4'h1: begin
type_out_valid <= 1'b1;
type_out <= q_stateType[0];
end
4'h2: begin
type_out_valid <= 1'b1;
type_out <= q_stateType[2];
end
4'h4: begin
type_out_valid <= 1'b1;
type_out <= q_stateType[4];
end
4'h8: begin
type_out_valid <= 1'b1;
type_out <= q_stateType[6];
end
default: begin
type_out_valid <= 1'b0;
end
endcase
end
endcase
end
end
generate
genvar h;
for(h=0;h<numExtraction;h=h+1) begin : fifo
fifo fifo_stateType(
.aclr(!reset),
.clock(clk),
.data(data_stateType[h]),
.rdreq(rdreq_stateType[h]),
.wrreq(wrreq_stateType[h]),
.empty(empty_stateType[h]),
.full(),
.q(q_stateType[h]),
.usedw()
);
defparam
fifo_stateType.width = 45,
fifo_stateType.depth = 4,
fifo_stateType.words = 16;
end
endgenerate
endmodule | module identifier(
clk,
reset,
stateType_valid_0,
stateType_0,
stateType_valid_1,
stateType_1,
stateType_valid_2,
stateType_2,
stateType_valid_3,
stateType_3,
stateType_valid_4,
stateType_4,
stateType_valid_5,
stateType_5,
stateType_valid_6,
stateType_6,
stateType_valid_7,
stateType_7,
type_out,
type_out_valid
); |
parameter numExtraction = 8,
widthExtraction =3,
widthHeaderData = 32;
input clk;
input reset;
input stateType_valid_0;
input [44:0] stateType_0;
input stateType_valid_1;
input [44:0] stateType_1;
input stateType_valid_2;
input [44:0] stateType_2;
input stateType_valid_3;
input [44:0] stateType_3;
input stateType_valid_4;
input [44:0] stateType_4;
input stateType_valid_5;
input [44:0] stateType_5;
input stateType_valid_6;
input [44:0] stateType_6;
input stateType_valid_7;
input [44:0] stateType_7;
output reg [44:0] type_out;
output reg type_out_valid;
integer i;
wire [44:0] data_stateType[numExtraction-1:0];
wire wrreq_stateType[numExtraction-1:0];
reg rdreq_stateType[numExtraction-1:0];
wire empty_stateType[numExtraction-1:0];
wire [44:0] q_stateType[numExtraction-1:0];
assign data_stateType[0] = stateType_0;
assign data_stateType[1] = stateType_1;
assign data_stateType[2] = stateType_2;
assign data_stateType[3] = stateType_3;
assign data_stateType[4] = stateType_4;
assign data_stateType[5] = stateType_5;
assign data_stateType[6] = stateType_6;
assign data_stateType[7] = stateType_7;
assign wrreq_stateType[0]= stateType_valid_0;
assign wrreq_stateType[1]= stateType_valid_1;
assign wrreq_stateType[2]= stateType_valid_2;
assign wrreq_stateType[3]= stateType_valid_3;
assign wrreq_stateType[4]= stateType_valid_4;
assign wrreq_stateType[5]= stateType_valid_5;
assign wrreq_stateType[6]= stateType_valid_6;
assign wrreq_stateType[7]= stateType_valid_7;
wire [3:0] empty_odd_tag,empty_even_tag;
assign empty_even_tag = {empty_stateType[7],empty_stateType[5],
empty_stateType[3],empty_stateType[1]};
assign empty_odd_tag = {empty_stateType[6],empty_stateType[4],
empty_stateType[2],empty_stateType[0]};
reg stateHungry;
parameter read_odd = 1'd0,
read_even = 1'd1;
always @(posedge clk or negedge reset) begin
if(!reset) begin
stateHungry <= read_odd;
type_out_valid <= 1'b0;
type_out <= 45'b0;
for(i=0;i<numExtraction;i=i+1) rdreq_stateType[i] <= 1'b0;
end
else begin
case(stateHungry)
read_odd: begin
rdreq_stateType[1] <= 1'b0;
rdreq_stateType[3] <= 1'b0;
rdreq_stateType[5] <= 1'b0;
rdreq_stateType[7] <= 1'b0;
if(empty_stateType[0]==1'b0) rdreq_stateType[0] <= 1'b1;
else if(empty_stateType[2]==1'b0) rdreq_stateType[2] <= 1'b1;
else if(empty_stateType[4]==1'b0) rdreq_stateType[4] <= 1'b1;
else if(empty_stateType[6]==1'b0) rdreq_stateType[6] <= 1'b1;
else begin
end
stateHungry <= read_even;
case({rdreq_stateType[7],rdreq_stateType[5],rdreq_stateType[3],rdreq_stateType[1]})
4'h1: begin
type_out_valid <= 1'b1;
type_out <= q_stateType[1];
end
4'h2: begin
type_out_valid <= 1'b1;
type_out <= q_stateType[3];
end
4'h4: begin
type_out_valid <= 1'b1;
type_out <= q_stateType[5];
end
4'h8: begin
type_out_valid <= 1'b1;
type_out <= q_stateType[7];
end
default: begin
type_out_valid <= 1'b0;
end
endcase
end
read_even: begin
rdreq_stateType[0] <= 1'b0;
rdreq_stateType[2] <= 1'b0;
rdreq_stateType[4] <= 1'b0;
rdreq_stateType[6] <= 1'b0;
if(empty_stateType[1]==1'b0) rdreq_stateType[1] <= 1'b1;
else if(empty_stateType[3]==1'b0) rdreq_stateType[3] <= 1'b1;
else if(empty_stateType[5]==1'b0) rdreq_stateType[5] <= 1'b1;
else if(empty_stateType[7]==1'b0) rdreq_stateType[7] <= 1'b1;
else begin
end
stateHungry <= read_odd;
case({rdreq_stateType[6],rdreq_stateType[4],rdreq_stateType[2],rdreq_stateType[0]})
4'h1: begin
type_out_valid <= 1'b1;
type_out <= q_stateType[0];
end
4'h2: begin
type_out_valid <= 1'b1;
type_out <= q_stateType[2];
end
4'h4: begin
type_out_valid <= 1'b1;
type_out <= q_stateType[4];
end
4'h8: begin
type_out_valid <= 1'b1;
type_out <= q_stateType[6];
end
default: begin
type_out_valid <= 1'b0;
end
endcase
end
endcase
end
end
generate
genvar h;
for(h=0;h<numExtraction;h=h+1) begin : fifo
fifo fifo_stateType(
.aclr(!reset),
.clock(clk),
.data(data_stateType[h]),
.rdreq(rdreq_stateType[h]),
.wrreq(wrreq_stateType[h]),
.empty(empty_stateType[h]),
.full(),
.q(q_stateType[h]),
.usedw()
);
defparam
fifo_stateType.width = 45,
fifo_stateType.depth = 4,
fifo_stateType.words = 16;
end
endgenerate
endmodule | 0 |
138,282 | data/full_repos/permissive/83198026/localbus_manage.v | 83,198,026 | localbus_manage.v | v | 138 | 110 | [] | [] | [] | [(2, 138)] | null | data/verilator_xmls/b26941bb-2505-4ffa-8dae-9e4c94aea99e.xml | null | 302,120 | module | module localbus_manage(
clk,
reset,
localbus_cs_n,
localbus_rd_wr,
localbus_data,
localbus_ale,
localbus_ack_n,
localbus_data_out,
parserRuleSet_valid,
parserRuleSet,
result_valid,
result,
lookupRuleSet_valid,
lookupRuleSet
);
input clk;
input reset;
input localbus_cs_n;
input localbus_rd_wr;
input [31:0] localbus_data;
input localbus_ale;
output reg localbus_ack_n;
output reg [31:0] localbus_data_out;
output reg parserRuleSet_valid;
output reg [169:0] parserRuleSet;
input result_valid;
input [119:0] result;
output reg lookupRuleSet_valid;
output reg [63:0] lookupRuleSet;
reg [31:0] localbus_addr;
reg [119:0] result_temp;
reg [3:0] state;
parameter idle = 4'd0,
read_rule = 4'd1,
write_rule = 4'd2,
wait_back = 4'd3;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
localbus_ack_n <= 1'b1;
localbus_data_out <= 32'b0;
state <= idle;
parserRuleSet_valid <= 1'b0;
parserRuleSet <= 170'b0;
lookupRuleSet_valid <= 1'b0;
lookupRuleSet <= 64'b0;
localbus_addr <= 32'b0;
end
else begin
case(state)
idle: begin
if(localbus_ale==1'b1) begin
localbus_addr <= localbus_data;
if(localbus_rd_wr==1'b1) begin
state <= read_rule;
end
else begin
state <= write_rule;
end
end
else state <= idle;
end
read_rule: begin
if(localbus_cs_n==1'b0) begin
localbus_ack_n <= 1'b0;
state <= wait_back;
case(localbus_addr[1:0])
2'd0: localbus_data_out <= {8'b0,result_temp[119:96]};
2'd1: localbus_data_out <= result_temp[95:64];
2'd2: localbus_data_out <= result_temp[63:32];
2'd3: localbus_data_out <= result_temp[31:0];
default: localbus_data_out <= 32'b0;
endcase
end
else state <= read_rule;
end
write_rule: begin
if(localbus_cs_n==1'b0) begin
localbus_ack_n <= 1'b0;
state <= wait_back;
case(localbus_addr[2:0])
3'd0: parserRuleSet[169:160] <= localbus_data[9:0];
3'd1: parserRuleSet[159:128] <= localbus_data;
3'd2: parserRuleSet[127:96] <= localbus_data;
3'd3: parserRuleSet[95:64] <= localbus_data;
3'd4: parserRuleSet[63:32] <= localbus_data;
3'd5: begin
parserRuleSet[31:0] <= localbus_data;
parserRuleSet_valid <= 1'b1;
end
3'd6: lookupRuleSet[63:32] <= localbus_data;
3'd7: begin
lookupRuleSet[31:0] <= localbus_data;
lookupRuleSet_valid <= 1'b1;
end
default: begin
end
endcase
end
else state <= write_rule;
end
wait_back: begin
parserRuleSet_valid <= 1'b0;
lookupRuleSet_valid <= 1'b0;
if(localbus_cs_n==1'b1) begin
state <= idle;
localbus_ack_n <= 1'b1;
end
else state <= wait_back;
end
default: state <= idle;
endcase
end
end
always @ (posedge clk or negedge reset) begin
if(!reset) begin
result_temp <= 120'b0;
end
else begin
if(result_valid==1'b1) result_temp <= result;
else result_temp <= result_temp;
end
end
endmodule | module localbus_manage(
clk,
reset,
localbus_cs_n,
localbus_rd_wr,
localbus_data,
localbus_ale,
localbus_ack_n,
localbus_data_out,
parserRuleSet_valid,
parserRuleSet,
result_valid,
result,
lookupRuleSet_valid,
lookupRuleSet
); |
input clk;
input reset;
input localbus_cs_n;
input localbus_rd_wr;
input [31:0] localbus_data;
input localbus_ale;
output reg localbus_ack_n;
output reg [31:0] localbus_data_out;
output reg parserRuleSet_valid;
output reg [169:0] parserRuleSet;
input result_valid;
input [119:0] result;
output reg lookupRuleSet_valid;
output reg [63:0] lookupRuleSet;
reg [31:0] localbus_addr;
reg [119:0] result_temp;
reg [3:0] state;
parameter idle = 4'd0,
read_rule = 4'd1,
write_rule = 4'd2,
wait_back = 4'd3;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
localbus_ack_n <= 1'b1;
localbus_data_out <= 32'b0;
state <= idle;
parserRuleSet_valid <= 1'b0;
parserRuleSet <= 170'b0;
lookupRuleSet_valid <= 1'b0;
lookupRuleSet <= 64'b0;
localbus_addr <= 32'b0;
end
else begin
case(state)
idle: begin
if(localbus_ale==1'b1) begin
localbus_addr <= localbus_data;
if(localbus_rd_wr==1'b1) begin
state <= read_rule;
end
else begin
state <= write_rule;
end
end
else state <= idle;
end
read_rule: begin
if(localbus_cs_n==1'b0) begin
localbus_ack_n <= 1'b0;
state <= wait_back;
case(localbus_addr[1:0])
2'd0: localbus_data_out <= {8'b0,result_temp[119:96]};
2'd1: localbus_data_out <= result_temp[95:64];
2'd2: localbus_data_out <= result_temp[63:32];
2'd3: localbus_data_out <= result_temp[31:0];
default: localbus_data_out <= 32'b0;
endcase
end
else state <= read_rule;
end
write_rule: begin
if(localbus_cs_n==1'b0) begin
localbus_ack_n <= 1'b0;
state <= wait_back;
case(localbus_addr[2:0])
3'd0: parserRuleSet[169:160] <= localbus_data[9:0];
3'd1: parserRuleSet[159:128] <= localbus_data;
3'd2: parserRuleSet[127:96] <= localbus_data;
3'd3: parserRuleSet[95:64] <= localbus_data;
3'd4: parserRuleSet[63:32] <= localbus_data;
3'd5: begin
parserRuleSet[31:0] <= localbus_data;
parserRuleSet_valid <= 1'b1;
end
3'd6: lookupRuleSet[63:32] <= localbus_data;
3'd7: begin
lookupRuleSet[31:0] <= localbus_data;
lookupRuleSet_valid <= 1'b1;
end
default: begin
end
endcase
end
else state <= write_rule;
end
wait_back: begin
parserRuleSet_valid <= 1'b0;
lookupRuleSet_valid <= 1'b0;
if(localbus_cs_n==1'b1) begin
state <= idle;
localbus_ack_n <= 1'b1;
end
else state <= wait_back;
end
default: state <= idle;
endcase
end
end
always @ (posedge clk or negedge reset) begin
if(!reset) begin
result_temp <= 120'b0;
end
else begin
if(result_valid==1'b1) result_temp <= result;
else result_temp <= result_temp;
end
end
endmodule | 0 |
138,283 | data/full_repos/permissive/83198026/lookup.v | 83,198,026 | lookup.v | v | 85 | 89 | [] | [] | [] | [(2, 85)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/83198026/lookup.v:45: Operator EQ expects 52 bits on the LHS, but LHS\'s SEL generates 48 bits.\n : ... In instance lookup\n else if(headerVector[143:96]==rule_smac[1][51:0]) action[19:16] <= rule_smac[1][3:0];\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/83198026/lookup.v:44: Operator EQ expects 52 bits on the LHS, but LHS\'s SEL generates 48 bits.\n : ... In instance lookup\n if(headerVector[143:96]==rule_smac[0][51:0]) action[19:16] <= rule_smac[0][3:0];\n ^~\n%Error: Exiting due to 2 warning(s)\n' | 302,121 | module | module lookup(
clk,
reset,
headerVector_valid,
headerVector,
action_valid,
action,
ruleSet_valid,
ruleSet
);
input clk;
input reset;
input headerVector_valid;
input [199:0] headerVector;
output reg action_valid;
output reg [31:0] action;
input ruleSet_valid;
input [63:0] ruleSet;
reg [51:0] rule_dmac[3:0];
reg [51:0] rule_smac[1:0];
always @ (posedge clk or negedge reset) begin
if(!reset) begin
action_valid <= 1'b0;
action <= 32'b0;
end
else begin
if(headerVector_valid==1'b1) begin
action_valid <= 1'b1;
action[31:24] <= headerVector[199:192];
if(headerVector[191:144]==rule_dmac[0][51:4]) action[3:0] <= rule_dmac[0][3:0];
else if(headerVector[191:144]==rule_dmac[1][51:4]) action[3:0] <= rule_dmac[1][3:0];
else if(headerVector[191:144]==rule_dmac[2][51:4]) action[3:0] <= rule_dmac[2][3:0];
else if(headerVector[191:144]==rule_dmac[3][51:4]) action[3:0] <= rule_dmac[3][3:0];
else action[3:0] <= 4'd0;
if(headerVector[143:96]==rule_smac[0][51:0]) action[19:16] <= rule_smac[0][3:0];
else if(headerVector[143:96]==rule_smac[1][51:0]) action[19:16] <= rule_smac[1][3:0];
else action[19:16] <= 4'd0;
end
else action_valid <= 1'b0;
end
end
always @ (posedge clk or negedge reset) begin
if(!reset) begin
rule_dmac[0] <= 52'b0;rule_dmac[1] <= 52'b0;
rule_dmac[2] <= 52'b0;rule_dmac[3] <= 52'b0;
rule_smac[0] <= 52'b0;rule_smac[1] <= 52'b0;
end
else begin
if(ruleSet_valid==1'b1) begin
case(ruleSet[55:52])
4'd0: rule_dmac[0] <= ruleSet[51:0];
4'd1: rule_dmac[1] <= ruleSet[51:0];
4'd2: rule_dmac[2] <= ruleSet[51:0];
4'd3: rule_dmac[3] <= ruleSet[51:0];
4'd4: rule_smac[0] <= ruleSet[51:0];
4'd5: rule_smac[1] <= ruleSet[51:0];
default: begin
end
endcase
end
else begin
end
end
end
endmodule | module lookup(
clk,
reset,
headerVector_valid,
headerVector,
action_valid,
action,
ruleSet_valid,
ruleSet
); |
input clk;
input reset;
input headerVector_valid;
input [199:0] headerVector;
output reg action_valid;
output reg [31:0] action;
input ruleSet_valid;
input [63:0] ruleSet;
reg [51:0] rule_dmac[3:0];
reg [51:0] rule_smac[1:0];
always @ (posedge clk or negedge reset) begin
if(!reset) begin
action_valid <= 1'b0;
action <= 32'b0;
end
else begin
if(headerVector_valid==1'b1) begin
action_valid <= 1'b1;
action[31:24] <= headerVector[199:192];
if(headerVector[191:144]==rule_dmac[0][51:4]) action[3:0] <= rule_dmac[0][3:0];
else if(headerVector[191:144]==rule_dmac[1][51:4]) action[3:0] <= rule_dmac[1][3:0];
else if(headerVector[191:144]==rule_dmac[2][51:4]) action[3:0] <= rule_dmac[2][3:0];
else if(headerVector[191:144]==rule_dmac[3][51:4]) action[3:0] <= rule_dmac[3][3:0];
else action[3:0] <= 4'd0;
if(headerVector[143:96]==rule_smac[0][51:0]) action[19:16] <= rule_smac[0][3:0];
else if(headerVector[143:96]==rule_smac[1][51:0]) action[19:16] <= rule_smac[1][3:0];
else action[19:16] <= 4'd0;
end
else action_valid <= 1'b0;
end
end
always @ (posedge clk or negedge reset) begin
if(!reset) begin
rule_dmac[0] <= 52'b0;rule_dmac[1] <= 52'b0;
rule_dmac[2] <= 52'b0;rule_dmac[3] <= 52'b0;
rule_smac[0] <= 52'b0;rule_smac[1] <= 52'b0;
end
else begin
if(ruleSet_valid==1'b1) begin
case(ruleSet[55:52])
4'd0: rule_dmac[0] <= ruleSet[51:0];
4'd1: rule_dmac[1] <= ruleSet[51:0];
4'd2: rule_dmac[2] <= ruleSet[51:0];
4'd3: rule_dmac[3] <= ruleSet[51:0];
4'd4: rule_smac[0] <= ruleSet[51:0];
4'd5: rule_smac[1] <= ruleSet[51:0];
default: begin
end
endcase
end
else begin
end
end
end
endmodule | 0 |
138,284 | data/full_repos/permissive/83198026/lookup_9bit.v | 83,198,026 | lookup_9bit.v | v | 184 | 70 | [] | [] | [] | null | line:167: before: "." | null | 1: b"%Error: data/full_repos/permissive/83198026/lookup_9bit.v:152: Cannot find file containing module: 'ram'\nram ram_65_256(\n^~~\n ... Looked in:\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/ram\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/ram.v\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/ram.sv\n ram\n ram.v\n ram.sv\n obj_dir/ram\n obj_dir/ram.v\n obj_dir/ram.sv\n%Error: Exiting due to 1 error(s)\n" | 302,122 | module | module lookup_bit(
clk,
reset,
key_valid,
key,
bv_valid,
bv,
set_valid,
set
);
input clk;
input reset;
input key_valid;
input [7:0] key;
output reg bv_valid;
output reg [63:0] bv;
input set_valid;
input [16:0] set;
reg [7:0] addr_b;
reg [64:0] data_b;
reg rden_b,wren_b;
wire[64:0] q_a,q_b;
reg [7:0] rule_id;
reg [15:0] temp_shift;
reg [255:0] q_temp;
reg [255:0] data_temp;
reg [3:0] state;
reg [16:0] set_temp;
parameter idle = 4'd0,
wait_1 = 4'd1,
wait_2 = 4'd2,
read_ram= 4'd3,
write_ram=4'd4;
reg key_valid_temp[1:0];
always @ (posedge clk or negedge reset) begin
if(!reset) begin
key_valid_temp[0] <= 1'b0;
key_valid_temp[1] <= 1'b0;
end
else begin
key_valid_temp[0] <= key_valid;
key_valid_temp[1] <= key_valid_temp[0];
end
end
always @ (posedge clk or negedge reset) begin
if(!reset) begin
bv_valid <= 1'b0;
bv <= 64'b0;
end
else begin
if(key_valid_temp[1]==1'b1) begin
bv_valid <= 1'b1;
if(q_a[64]==1'b1) bv <= q_a[63:0];
else bv <= 64'b0;
end
else begin
bv_valid <= 1'b0;
end
end
end
reg [63:0] q_b_temp;
reg [63:0] data_and_temp;
always @(posedge clk or negedge reset) begin
if(!reset) begin
rden_b <= 1'b0;
wren_b <= 1'b0;
data_b <= 65'b0;
addr_b <= 8'b0;
data_and_temp <= 64'b0;
set_temp <= 17'b0;
end
else begin
case(state)
idle: begin
wren_b <= 1'b0;
if(set_valid == 1'b1) begin
state <= wait_1;
set_temp <= set;
addr_b <= set[15:8];
rden_b <= 1'b1;
end
else begin
rden_b <= 1'b0;
state <= idle;
end
end
wait_1: begin
if(set_temp[16]==1'b1) begin
data_and_temp <= 64'd1 << set_temp[5:0];
end
else begin
data_and_temp <= ~(64'd1 << set_temp[5:0]);
end
state <= wait_2;
rden_b <= 1'b0;
end
wait_2: begin
state <= read_ram;
end
read_ram: begin
if(q_b[64]==1'b1) begin
q_b_temp <= q_b[63:0];
end
else begin
q_b_temp <= 64'b0;
end
state <= write_ram;
end
write_ram: begin
wren_b <= 1'b1;
addr_b <= set_temp[15:8];
if(set_temp[16]==1'b1) data_b <= {1'b1,(q_b_temp|data_and_temp)};
else data_b <= {1'b1,(q_b_temp&data_and_temp)};
state <= idle;
end
default: state <= idle;
endcase
end
end
ram ram_65_256(
.address_a(key),
.address_b(addr_b),
.clock(clk),
.data_a(65'b0),
.data_b(data_b),
.rden_a(key_valid),
.rden_b(rden_b),
.wren_a(1'b0),
.wren_b(wren_b),
.q_a(q_a),
.q_b(q_b)
);
defparam
ram_65_256.width = 65,
ram_65_256.depth = 8,
ram_65_256.words = 256;
endmodule | module lookup_bit(
clk,
reset,
key_valid,
key,
bv_valid,
bv,
set_valid,
set
); |
input clk;
input reset;
input key_valid;
input [7:0] key;
output reg bv_valid;
output reg [63:0] bv;
input set_valid;
input [16:0] set;
reg [7:0] addr_b;
reg [64:0] data_b;
reg rden_b,wren_b;
wire[64:0] q_a,q_b;
reg [7:0] rule_id;
reg [15:0] temp_shift;
reg [255:0] q_temp;
reg [255:0] data_temp;
reg [3:0] state;
reg [16:0] set_temp;
parameter idle = 4'd0,
wait_1 = 4'd1,
wait_2 = 4'd2,
read_ram= 4'd3,
write_ram=4'd4;
reg key_valid_temp[1:0];
always @ (posedge clk or negedge reset) begin
if(!reset) begin
key_valid_temp[0] <= 1'b0;
key_valid_temp[1] <= 1'b0;
end
else begin
key_valid_temp[0] <= key_valid;
key_valid_temp[1] <= key_valid_temp[0];
end
end
always @ (posedge clk or negedge reset) begin
if(!reset) begin
bv_valid <= 1'b0;
bv <= 64'b0;
end
else begin
if(key_valid_temp[1]==1'b1) begin
bv_valid <= 1'b1;
if(q_a[64]==1'b1) bv <= q_a[63:0];
else bv <= 64'b0;
end
else begin
bv_valid <= 1'b0;
end
end
end
reg [63:0] q_b_temp;
reg [63:0] data_and_temp;
always @(posedge clk or negedge reset) begin
if(!reset) begin
rden_b <= 1'b0;
wren_b <= 1'b0;
data_b <= 65'b0;
addr_b <= 8'b0;
data_and_temp <= 64'b0;
set_temp <= 17'b0;
end
else begin
case(state)
idle: begin
wren_b <= 1'b0;
if(set_valid == 1'b1) begin
state <= wait_1;
set_temp <= set;
addr_b <= set[15:8];
rden_b <= 1'b1;
end
else begin
rden_b <= 1'b0;
state <= idle;
end
end
wait_1: begin
if(set_temp[16]==1'b1) begin
data_and_temp <= 64'd1 << set_temp[5:0];
end
else begin
data_and_temp <= ~(64'd1 << set_temp[5:0]);
end
state <= wait_2;
rden_b <= 1'b0;
end
wait_2: begin
state <= read_ram;
end
read_ram: begin
if(q_b[64]==1'b1) begin
q_b_temp <= q_b[63:0];
end
else begin
q_b_temp <= 64'b0;
end
state <= write_ram;
end
write_ram: begin
wren_b <= 1'b1;
addr_b <= set_temp[15:8];
if(set_temp[16]==1'b1) data_b <= {1'b1,(q_b_temp|data_and_temp)};
else data_b <= {1'b1,(q_b_temp&data_and_temp)};
state <= idle;
end
default: state <= idle;
endcase
end
end
ram ram_65_256(
.address_a(key),
.address_b(addr_b),
.clock(clk),
.data_a(65'b0),
.data_b(data_b),
.rden_a(key_valid),
.rden_b(rden_b),
.wren_a(1'b0),
.wren_b(wren_b),
.q_a(q_a),
.q_b(q_b)
);
defparam
ram_65_256.width = 65,
ram_65_256.depth = 8,
ram_65_256.words = 256;
endmodule | 0 |
138,285 | data/full_repos/permissive/83198026/parser.v | 83,198,026 | parser.v | v | 263 | 107 | [] | [] | [] | null | line:142: before: "." | null | 1: b"%Error: data/full_repos/permissive/83198026/parser.v:120: Cannot find file containing module: 'identifier'\nidentifier identifier(\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/identifier\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/identifier.v\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/identifier.sv\n identifier\n identifier.v\n identifier.sv\n obj_dir/identifier\n obj_dir/identifier.v\n obj_dir/identifier.sv\n%Error: data/full_repos/permissive/83198026/parser.v:146: Cannot find file containing module: 'BVbasedSearcher'\nBVbasedSearcher TCAM(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83198026/parser.v:160: Cannot find file containing module: 'actionRAM'\nactionRAM actionRAM(\n^~~~~~~~~\n%Error: data/full_repos/permissive/83198026/parser.v:178: Cannot find file containing module: 'extractor'\n extractor fieldExtractor(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/83198026/parser.v:206: Cannot find file containing module: 'result_accumulator'\n result_accumulator result(\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83198026/parser.v:222: Cannot find file containing module: 'result_mux'\nresult_mux result_mux(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/83198026/parser.v:248: Cannot find file containing module: 'ruleConfigurer'\nruleConfigurer ruleConfigurer(\n^~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n" | 302,123 | module | module parser(
clk,
reset,
headerData_valid,
headerData,
headerData_finish_valid,
pktID,
headerVector_valid,
headerVector,
ruleSet_valid,
ruleSet,
result_valid,
result,
bid_bitmap
);
parameter numExtraction =8,
widthExtraction=3,
limitTime = 50000,
widthPkt = 138,
widthHeaderData = 32,
widthHeaderVector = 200,
depthTCAM = 6;
input clk;
input reset;
input [numExtraction-1:0] headerData_valid;
input [widthHeaderData*numExtraction-1:0] headerData;
input [numExtraction-1:0] headerData_finish_valid;
input [8*numExtraction-1:0] pktID;
output wire headerVector_valid;
output wire [widthHeaderVector-1:0] headerVector;
input ruleSet_valid;
input [169:0] ruleSet;
output wire result_valid;
output wire [119:0] result;
output wire [numExtraction-1:0] bid_bitmap;
integer n;
wire [44:0] type_out;
wire type_out_valid;
wire indexTCAM_valid;
wire [depthTCAM+4:0] indexTCAM;
wire resultTCAM_valid;
wire [63:0] resultTCAM;
wire ruleSetTCAM_valid;
wire [49:0] ruleSetTCAM;
wire ruleSetActionRAM_valid;
wire [129:0] ruleSetActionRAM;
wire action_valid;
wire [124:0] action;
wire stateType_valid[numExtraction-1:0];
wire [44:0] stateType[numExtraction-1:0];
wire field_valid[numExtraction-1:0];
wire [31:0] field[numExtraction-1:0];
wire field_finish_valid[numExtraction-1:0];
wire [23:0] field_finish_bid[numExtraction-1:0];
wire [11:0] hvOffset[numExtraction-1:0];
wire metadata_valid[numExtraction-1:0];
wire [widthHeaderVector-1:0] metadata[numExtraction-1:0];
identifier identifier(
.clk(clk),
.reset(reset),
.stateType_valid_0(stateType_valid[0]),
.stateType_0(stateType[0]),
.stateType_valid_1(stateType_valid[1]),
.stateType_1(stateType[1]),
.stateType_valid_2(stateType_valid[2]),
.stateType_2(stateType[2]),
.stateType_valid_3(stateType_valid[3]),
.stateType_3(stateType[3]),
.stateType_valid_4(stateType_valid[4]),
.stateType_4(stateType[4]),
.stateType_valid_5(stateType_valid[5]),
.stateType_5(stateType[5]),
.stateType_valid_6(stateType_valid[6]),
.stateType_6(stateType[6]),
.stateType_valid_7(stateType_valid[7]),
.stateType_7(stateType[7]),
.type_out(type_out),
.type_out_valid(type_out_valid)
);
defparam identifier.numExtraction = numExtraction,
identifier.widthExtraction = widthExtraction,
identifier.widthHeaderData = widthHeaderData;
BVbasedSearcher TCAM(
.clk(clk),
.reset(reset),
.key(type_out),
.key_valid(type_out_valid),
.index_valid(indexTCAM_valid),
.index(indexTCAM),
.ruleSet_valid(ruleSetTCAM_valid),
.ruleSet(ruleSetTCAM),
.result_valid(resultTCAM_valid),
.result(resultTCAM)
);
defparam TCAM.depthTCAM = depthTCAM;
actionRAM actionRAM(
.clk(clk),
.reset(reset),
.index_valid(indexTCAM_valid),
.index(indexTCAM),
.action_valid(action_valid),
.action(action),
.ruleSet_valid(ruleSetActionRAM_valid),
.ruleSet(ruleSetActionRAM),
.result_valid(result_valid),
.result(result)
);
defparam actionRAM.depthRAM = depthTCAM;
generate
genvar i;
for(i=0;i<numExtraction;i=i+1) begin : extractor
extractor fieldExtractor(
.clk(clk),
.reset(reset),
.headerData_valid(headerData_valid[i]),
.headerData(headerData[i*32+31:i*32]),
.headerData_finish_valid(headerData_finish_valid[i]),
.pktID(pktID[i*8+7:i*8]),
.action_valid(action_valid),
.action(action),
.field_valid(field_valid[i]),
.field(field[i]),
.hvOffset(hvOffset[i]),
.field_finish_valid(field_finish_valid[i]),
.field_finish_bid(field_finish_bid[i]),
.bid_enable(bid_bitmap[i]),
.stateType_valid(stateType_valid[i]),
.stateType(stateType[i])
);
defparam fieldExtractor.extractionID = i,
fieldExtractor.widthExtraction = widthExtraction,
fieldExtractor.widthHeaderData = widthHeaderData;
end
endgenerate
generate
genvar j;
for(j=0;j<numExtraction;j=j+1) begin : result_accumulator
result_accumulator result(
.clk(clk),
.reset(reset),
.field_valid(field_valid[j]),
.field(field[j]),
.offset(hvOffset[j]),
.field_finish_valid(field_finish_valid[j]),
.field_finish_bid(field_finish_bid[j]),
.metadata_valid(metadata_valid[j]),
.metadata(metadata[j])
);
defparam result.widthHeaderData = widthHeaderData,
result.widthHeaderVector=widthHeaderVector;
end
endgenerate
result_mux result_mux(
.clk(clk),
.reset(reset),
.metadata_valid_0(metadata_valid[0]),
.metadata_0(metadata[0]),
.metadata_valid_1(metadata_valid[1]),
.metadata_1(metadata[1]),
.metadata_valid_2(metadata_valid[2]),
.metadata_2(metadata[2]),
.metadata_valid_3(metadata_valid[3]),
.metadata_3(metadata[3]),
.metadata_valid_4(metadata_valid[4]),
.metadata_4(metadata[4]),
.metadata_valid_5(metadata_valid[5]),
.metadata_5(metadata[5]),
.metadata_valid_6(metadata_valid[6]),
.metadata_6(metadata[6]),
.metadata_valid_7(metadata_valid[7]),
.metadata_7(metadata[7]),
.headerVector_valid(headerVector_valid),
.headerVector(headerVector)
);
defparam result_mux.widthHV = widthHeaderVector,
result_mux.widthHeaderData = widthHeaderData;
ruleConfigurer ruleConfigurer(
.clk(clk),
.reset(reset),
.ruleSet_valid(ruleSet_valid),
.ruleSet(ruleSet),
.ruleSetTCAM_valid(ruleSetTCAM_valid),
.ruleSetTCAM(ruleSetTCAM),
.ruleSetActionRAM_valid(ruleSetActionRAM_valid),
.ruleSetActionRAM(ruleSetActionRAM)
);
endmodule | module parser(
clk,
reset,
headerData_valid,
headerData,
headerData_finish_valid,
pktID,
headerVector_valid,
headerVector,
ruleSet_valid,
ruleSet,
result_valid,
result,
bid_bitmap
); |
parameter numExtraction =8,
widthExtraction=3,
limitTime = 50000,
widthPkt = 138,
widthHeaderData = 32,
widthHeaderVector = 200,
depthTCAM = 6;
input clk;
input reset;
input [numExtraction-1:0] headerData_valid;
input [widthHeaderData*numExtraction-1:0] headerData;
input [numExtraction-1:0] headerData_finish_valid;
input [8*numExtraction-1:0] pktID;
output wire headerVector_valid;
output wire [widthHeaderVector-1:0] headerVector;
input ruleSet_valid;
input [169:0] ruleSet;
output wire result_valid;
output wire [119:0] result;
output wire [numExtraction-1:0] bid_bitmap;
integer n;
wire [44:0] type_out;
wire type_out_valid;
wire indexTCAM_valid;
wire [depthTCAM+4:0] indexTCAM;
wire resultTCAM_valid;
wire [63:0] resultTCAM;
wire ruleSetTCAM_valid;
wire [49:0] ruleSetTCAM;
wire ruleSetActionRAM_valid;
wire [129:0] ruleSetActionRAM;
wire action_valid;
wire [124:0] action;
wire stateType_valid[numExtraction-1:0];
wire [44:0] stateType[numExtraction-1:0];
wire field_valid[numExtraction-1:0];
wire [31:0] field[numExtraction-1:0];
wire field_finish_valid[numExtraction-1:0];
wire [23:0] field_finish_bid[numExtraction-1:0];
wire [11:0] hvOffset[numExtraction-1:0];
wire metadata_valid[numExtraction-1:0];
wire [widthHeaderVector-1:0] metadata[numExtraction-1:0];
identifier identifier(
.clk(clk),
.reset(reset),
.stateType_valid_0(stateType_valid[0]),
.stateType_0(stateType[0]),
.stateType_valid_1(stateType_valid[1]),
.stateType_1(stateType[1]),
.stateType_valid_2(stateType_valid[2]),
.stateType_2(stateType[2]),
.stateType_valid_3(stateType_valid[3]),
.stateType_3(stateType[3]),
.stateType_valid_4(stateType_valid[4]),
.stateType_4(stateType[4]),
.stateType_valid_5(stateType_valid[5]),
.stateType_5(stateType[5]),
.stateType_valid_6(stateType_valid[6]),
.stateType_6(stateType[6]),
.stateType_valid_7(stateType_valid[7]),
.stateType_7(stateType[7]),
.type_out(type_out),
.type_out_valid(type_out_valid)
);
defparam identifier.numExtraction = numExtraction,
identifier.widthExtraction = widthExtraction,
identifier.widthHeaderData = widthHeaderData;
BVbasedSearcher TCAM(
.clk(clk),
.reset(reset),
.key(type_out),
.key_valid(type_out_valid),
.index_valid(indexTCAM_valid),
.index(indexTCAM),
.ruleSet_valid(ruleSetTCAM_valid),
.ruleSet(ruleSetTCAM),
.result_valid(resultTCAM_valid),
.result(resultTCAM)
);
defparam TCAM.depthTCAM = depthTCAM;
actionRAM actionRAM(
.clk(clk),
.reset(reset),
.index_valid(indexTCAM_valid),
.index(indexTCAM),
.action_valid(action_valid),
.action(action),
.ruleSet_valid(ruleSetActionRAM_valid),
.ruleSet(ruleSetActionRAM),
.result_valid(result_valid),
.result(result)
);
defparam actionRAM.depthRAM = depthTCAM;
generate
genvar i;
for(i=0;i<numExtraction;i=i+1) begin : extractor
extractor fieldExtractor(
.clk(clk),
.reset(reset),
.headerData_valid(headerData_valid[i]),
.headerData(headerData[i*32+31:i*32]),
.headerData_finish_valid(headerData_finish_valid[i]),
.pktID(pktID[i*8+7:i*8]),
.action_valid(action_valid),
.action(action),
.field_valid(field_valid[i]),
.field(field[i]),
.hvOffset(hvOffset[i]),
.field_finish_valid(field_finish_valid[i]),
.field_finish_bid(field_finish_bid[i]),
.bid_enable(bid_bitmap[i]),
.stateType_valid(stateType_valid[i]),
.stateType(stateType[i])
);
defparam fieldExtractor.extractionID = i,
fieldExtractor.widthExtraction = widthExtraction,
fieldExtractor.widthHeaderData = widthHeaderData;
end
endgenerate
generate
genvar j;
for(j=0;j<numExtraction;j=j+1) begin : result_accumulator
result_accumulator result(
.clk(clk),
.reset(reset),
.field_valid(field_valid[j]),
.field(field[j]),
.offset(hvOffset[j]),
.field_finish_valid(field_finish_valid[j]),
.field_finish_bid(field_finish_bid[j]),
.metadata_valid(metadata_valid[j]),
.metadata(metadata[j])
);
defparam result.widthHeaderData = widthHeaderData,
result.widthHeaderVector=widthHeaderVector;
end
endgenerate
result_mux result_mux(
.clk(clk),
.reset(reset),
.metadata_valid_0(metadata_valid[0]),
.metadata_0(metadata[0]),
.metadata_valid_1(metadata_valid[1]),
.metadata_1(metadata[1]),
.metadata_valid_2(metadata_valid[2]),
.metadata_2(metadata[2]),
.metadata_valid_3(metadata_valid[3]),
.metadata_3(metadata[3]),
.metadata_valid_4(metadata_valid[4]),
.metadata_4(metadata[4]),
.metadata_valid_5(metadata_valid[5]),
.metadata_5(metadata[5]),
.metadata_valid_6(metadata_valid[6]),
.metadata_6(metadata[6]),
.metadata_valid_7(metadata_valid[7]),
.metadata_7(metadata[7]),
.headerVector_valid(headerVector_valid),
.headerVector(headerVector)
);
defparam result_mux.widthHV = widthHeaderVector,
result_mux.widthHeaderData = widthHeaderData;
ruleConfigurer ruleConfigurer(
.clk(clk),
.reset(reset),
.ruleSet_valid(ruleSet_valid),
.ruleSet(ruleSet),
.ruleSetTCAM_valid(ruleSetTCAM_valid),
.ruleSetTCAM(ruleSetTCAM),
.ruleSetActionRAM_valid(ruleSetActionRAM_valid),
.ruleSetActionRAM(ruleSetActionRAM)
);
endmodule | 0 |
138,286 | data/full_repos/permissive/83198026/pktBuffer.v | 83,198,026 | pktBuffer.v | v | 316 | 97 | [] | [] | [] | null | line:288: before: "." | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/83198026/pktBuffer.v:130: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'idle_in\' generates 1 bits.\n : ... In instance pktBuffer\n state_out <= idle_in;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/83198026/pktBuffer.v:172: Operator ASSIGNDLY expects 65 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 64 bits.\n : ... In instance pktBuffer\n pktID_add <= {8\'d1,8\'d1,8\'d1,8\'d1,8\'d1,8\'d1,8\'d1,8\'d1};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83198026/pktBuffer.v:173: Operator ASSIGNDLY expects 256 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 512 bits.\n : ... In instance pktBuffer\n packet_add <= {32\'d1,32\'d1,32\'d1,32\'d1,32\'d1,32\'d1,32\'d1,32\'d1,\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83198026/pktBuffer.v:199: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s ADD generates 65 bits.\n : ... In instance pktBuffer\n pktID_out <= pktID_add + pktID_out;\n ^~\n%Error: data/full_repos/permissive/83198026/pktBuffer.v:273: Cannot find file containing module: \'ram\'\nram ram_138_1024( \n^~~\n ... Looked in:\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/ram\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/ram.v\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/ram.sv\n ram\n ram.v\n ram.sv\n obj_dir/ram\n obj_dir/ram.v\n obj_dir/ram.sv\n%Error: data/full_repos/permissive/83198026/pktBuffer.v:295: Cannot find file containing module: \'fifo\'\n fifo fifo_header(\n ^~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n' | 302,124 | module | module pktBuffer(
clk,
reset,
pktID_in_valid,
pktID_in,
cdp2um_data_valid,
cdp2um_data,
um2cdp_data_valid,
um2cdp_data,
headerData_valid,
headerData,
headerData_finish_valid,
pktID_out,
bid_bitmap,
headerIn_enable,
cdp2um_rule_usedw,
writeRule_enable
);
input clk;
input reset;
input pktID_in_valid;
input [11:0] pktID_in;
input cdp2um_data_valid;
input [138:0] cdp2um_data;
output reg um2cdp_data_valid;
output reg [138:0] um2cdp_data;
output reg [7:0] headerData_valid;
output reg [255:0] headerData;
output reg [7:0] headerData_finish_valid;
output reg [63:0] pktID_out;
input [7:0] bid_bitmap;
output reg headerIn_enable;
input [4:0] cdp2um_rule_usedw;
output reg writeRule_enable;
reg [7:0] pktID_temp;
reg [8:0] addr_a,addr_b;
reg [138:0] data_b;
reg rden_a,wren_b;
wire [138:0] q_a;
reg [7:0] wrreq_header;
wire rdreq_header[7:0];
reg [137:0] data_header;
wire empty_header[7:0];
wire [137:0] q_header[7:0];
reg [7:0] ramID,count_header;
reg state,state_in;
parameter idle_in = 1'd0,
wait_end = 1'd1;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
pktID_temp <= 8'b0;
addr_b <= 9'b0;
wren_b <= 1'b0;
data_b <= 139'b0;
state_in <= idle_in;
end
else begin
case(state_in)
idle_in: begin
if((cdp2um_data_valid==1'b1)&&(cdp2um_data[138:136]==3'b101)) begin
wren_b <= 1'b1;
addr_b <= {pktID_temp[4:0],4'b0};
data_b <= cdp2um_data;
state_in <= wait_end;
end
else begin
wren_b <= 1'b0;
state_in <= idle_in;
end
end
wait_end: begin
if(cdp2um_data[138:136]==3'b110) begin
state_in <= idle_in;
pktID_temp <= pktID_temp + 8'd1;
end
else state_in <= wait_end;
data_b <= cdp2um_data;
addr_b <= addr_b + 9'd1;
end
default: state_in <= idle_in;
endcase
end
end
reg [1:0] state_out;
parameter idle_out = 2'd0,
wait_1 = 2'd1,
wait_2 = 2'd2,
read_ram = 2'd3;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
addr_a <= 9'b0;
rden_a <= 1'b0;
um2cdp_data_valid <= 1'b0;
um2cdp_data <= 139'b0;
state_out <= idle_out;
writeRule_enable <= 1'b0;
end
else begin
case(state_out)
idle_out: begin
um2cdp_data_valid <= 1'b0;
if((pktID_in_valid==1'b1)&&(pktID_in[9:8]!=2'd1)) begin
rden_a <= 1'b1;
addr_a <= {pktID_in[4:0],4'b0};
state_out <= wait_1;
end
else begin
state_out <= idle_in;
end
if(cdp2um_rule_usedw < 5'd30) writeRule_enable <= 1'b1;
else writeRule_enable <= 1'b0;
end
wait_1: begin
writeRule_enable <= 1'b0;
state_out <= wait_2;
addr_a <= addr_a +9'd1;
end
wait_2: begin
state_out <= read_ram;
addr_a <= addr_a +9'd1;
end
read_ram: begin
if(q_a[138:136]==3'b110) state_out <= idle_out;
else state_out <= read_ram;
um2cdp_data_valid <= 1'b1;
um2cdp_data <= q_a;
addr_a <= addr_a + 9'd1;
end
default: state_out <= idle_out;
endcase
end
end
reg [255:0] packet_add;
reg [64:0] pktID_add;
reg [3:0] state_sim;
parameter idle_sim = 4'd0,
ready_sim = 4'd1,
wait_end_sim = 4'd2,
bubble_sim = 4'd3;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
headerData_valid <= 8'd0;
headerData <= 256'b0;
headerData_finish_valid <= 8'd0;
pktID_out <= 64'b0;
pktID_add <= {8'd1,8'd1,8'd1,8'd1,8'd1,8'd1,8'd1,8'd1};
packet_add <= {32'd1,32'd1,32'd1,32'd1,32'd1,32'd1,32'd1,32'd1,
32'd1,32'd1,32'd1,32'd1,32'd1,32'd1,32'd1,32'd1};
end
else begin
case(state_sim)
idle_sim: begin
if(cdp2um_data_valid==1'b1) state_sim <= ready_sim;
else state_sim <= idle_sim;
end
ready_sim: begin
headerData_finish_valid <= 8'h0;
if(bid_bitmap==8'hff) begin
headerData_valid <= 8'hff;
headerData <= packet_add;
state_sim <= wait_end_sim;
end
else begin
headerData_valid <= 8'h0;
state_sim <= ready_sim;
end
end
wait_end_sim: begin
if(headerData[7:0]==8'd15) begin
state_sim <= ready_sim;
headerData_finish_valid <= 8'hff;
pktID_out <= pktID_add + pktID_out;
end
else state_sim <= wait_end_sim;
headerData <= packet_add + headerData;
end
bubble_sim: begin
headerData_finish_valid <= 8'h0;
headerData_valid <= 8'h0;
end
default: state_sim <= idle_sim;
endcase
end
end
ram ram_138_1024(
.address_a(addr_a),
.address_b(addr_b),
.clock(clk),
.data_a(139'b0),
.data_b(data_b),
.rden_a(rden_a),
.rden_b(1'b0),
.wren_a(1'b0),
.wren_b(wren_b),
.q_a(q_a),
.q_b()
);
defparam
ram_138_1024.width = 139,
ram_138_1024.depth = 9,
ram_138_1024.words = 512;
generate
genvar i;
for(i=0;i<8;i=i+1) begin : fifo
fifo fifo_header(
.aclr(!reset),
.clock(clk),
.data(data_header),
.rdreq(rdreq_header[i]),
.wrreq(wrreq_header[i]),
.empty(empty_header[i]),
.full(),
.q(q_header[i]),
.usedw()
);
defparam
fifo_header.width = 138,
fifo_header.depth = 6,
fifo_header.words = 64;
end
endgenerate
endmodule | module pktBuffer(
clk,
reset,
pktID_in_valid,
pktID_in,
cdp2um_data_valid,
cdp2um_data,
um2cdp_data_valid,
um2cdp_data,
headerData_valid,
headerData,
headerData_finish_valid,
pktID_out,
bid_bitmap,
headerIn_enable,
cdp2um_rule_usedw,
writeRule_enable
); |
input clk;
input reset;
input pktID_in_valid;
input [11:0] pktID_in;
input cdp2um_data_valid;
input [138:0] cdp2um_data;
output reg um2cdp_data_valid;
output reg [138:0] um2cdp_data;
output reg [7:0] headerData_valid;
output reg [255:0] headerData;
output reg [7:0] headerData_finish_valid;
output reg [63:0] pktID_out;
input [7:0] bid_bitmap;
output reg headerIn_enable;
input [4:0] cdp2um_rule_usedw;
output reg writeRule_enable;
reg [7:0] pktID_temp;
reg [8:0] addr_a,addr_b;
reg [138:0] data_b;
reg rden_a,wren_b;
wire [138:0] q_a;
reg [7:0] wrreq_header;
wire rdreq_header[7:0];
reg [137:0] data_header;
wire empty_header[7:0];
wire [137:0] q_header[7:0];
reg [7:0] ramID,count_header;
reg state,state_in;
parameter idle_in = 1'd0,
wait_end = 1'd1;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
pktID_temp <= 8'b0;
addr_b <= 9'b0;
wren_b <= 1'b0;
data_b <= 139'b0;
state_in <= idle_in;
end
else begin
case(state_in)
idle_in: begin
if((cdp2um_data_valid==1'b1)&&(cdp2um_data[138:136]==3'b101)) begin
wren_b <= 1'b1;
addr_b <= {pktID_temp[4:0],4'b0};
data_b <= cdp2um_data;
state_in <= wait_end;
end
else begin
wren_b <= 1'b0;
state_in <= idle_in;
end
end
wait_end: begin
if(cdp2um_data[138:136]==3'b110) begin
state_in <= idle_in;
pktID_temp <= pktID_temp + 8'd1;
end
else state_in <= wait_end;
data_b <= cdp2um_data;
addr_b <= addr_b + 9'd1;
end
default: state_in <= idle_in;
endcase
end
end
reg [1:0] state_out;
parameter idle_out = 2'd0,
wait_1 = 2'd1,
wait_2 = 2'd2,
read_ram = 2'd3;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
addr_a <= 9'b0;
rden_a <= 1'b0;
um2cdp_data_valid <= 1'b0;
um2cdp_data <= 139'b0;
state_out <= idle_out;
writeRule_enable <= 1'b0;
end
else begin
case(state_out)
idle_out: begin
um2cdp_data_valid <= 1'b0;
if((pktID_in_valid==1'b1)&&(pktID_in[9:8]!=2'd1)) begin
rden_a <= 1'b1;
addr_a <= {pktID_in[4:0],4'b0};
state_out <= wait_1;
end
else begin
state_out <= idle_in;
end
if(cdp2um_rule_usedw < 5'd30) writeRule_enable <= 1'b1;
else writeRule_enable <= 1'b0;
end
wait_1: begin
writeRule_enable <= 1'b0;
state_out <= wait_2;
addr_a <= addr_a +9'd1;
end
wait_2: begin
state_out <= read_ram;
addr_a <= addr_a +9'd1;
end
read_ram: begin
if(q_a[138:136]==3'b110) state_out <= idle_out;
else state_out <= read_ram;
um2cdp_data_valid <= 1'b1;
um2cdp_data <= q_a;
addr_a <= addr_a + 9'd1;
end
default: state_out <= idle_out;
endcase
end
end
reg [255:0] packet_add;
reg [64:0] pktID_add;
reg [3:0] state_sim;
parameter idle_sim = 4'd0,
ready_sim = 4'd1,
wait_end_sim = 4'd2,
bubble_sim = 4'd3;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
headerData_valid <= 8'd0;
headerData <= 256'b0;
headerData_finish_valid <= 8'd0;
pktID_out <= 64'b0;
pktID_add <= {8'd1,8'd1,8'd1,8'd1,8'd1,8'd1,8'd1,8'd1};
packet_add <= {32'd1,32'd1,32'd1,32'd1,32'd1,32'd1,32'd1,32'd1,
32'd1,32'd1,32'd1,32'd1,32'd1,32'd1,32'd1,32'd1};
end
else begin
case(state_sim)
idle_sim: begin
if(cdp2um_data_valid==1'b1) state_sim <= ready_sim;
else state_sim <= idle_sim;
end
ready_sim: begin
headerData_finish_valid <= 8'h0;
if(bid_bitmap==8'hff) begin
headerData_valid <= 8'hff;
headerData <= packet_add;
state_sim <= wait_end_sim;
end
else begin
headerData_valid <= 8'h0;
state_sim <= ready_sim;
end
end
wait_end_sim: begin
if(headerData[7:0]==8'd15) begin
state_sim <= ready_sim;
headerData_finish_valid <= 8'hff;
pktID_out <= pktID_add + pktID_out;
end
else state_sim <= wait_end_sim;
headerData <= packet_add + headerData;
end
bubble_sim: begin
headerData_finish_valid <= 8'h0;
headerData_valid <= 8'h0;
end
default: state_sim <= idle_sim;
endcase
end
end
ram ram_138_1024(
.address_a(addr_a),
.address_b(addr_b),
.clock(clk),
.data_a(139'b0),
.data_b(data_b),
.rden_a(rden_a),
.rden_b(1'b0),
.wren_a(1'b0),
.wren_b(wren_b),
.q_a(q_a),
.q_b()
);
defparam
ram_138_1024.width = 139,
ram_138_1024.depth = 9,
ram_138_1024.words = 512;
generate
genvar i;
for(i=0;i<8;i=i+1) begin : fifo
fifo fifo_header(
.aclr(!reset),
.clock(clk),
.data(data_header),
.rdreq(rdreq_header[i]),
.wrreq(wrreq_header[i]),
.empty(empty_header[i]),
.full(),
.q(q_header[i]),
.usedw()
);
defparam
fifo_header.width = 138,
fifo_header.depth = 6,
fifo_header.words = 64;
end
endgenerate
endmodule | 0 |
138,287 | data/full_repos/permissive/83198026/ptk_gen.v | 83,198,026 | ptk_gen.v | v | 131 | 62 | [] | [] | [] | null | line:127: before: "." | null | 1: b"%Error: data/full_repos/permissive/83198026/ptk_gen.v:115: Cannot find file containing module: 'fifo'\nfifo fifo_header(\n^~~~\n ... Looked in:\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/fifo\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/fifo.v\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/fifo.sv\n fifo\n fifo.v\n fifo.sv\n obj_dir/fifo\n obj_dir/fifo.v\n obj_dir/fifo.sv\n%Error: Exiting due to 1 error(s)\n" | 302,125 | module | module pkt_gen(
clk,
reset,
headerData_valid,
headerData,
headerData_out_valid,
headerData_out,
headerIn_enable
);
input clk;
input reset;
input headerData_valid;
input [129:0] headerData;
output reg headerData_out_valid;
output reg [137:0] headerData_out;
input headerIn_enable;
reg [7:0] count_temp;
reg state_headerIn,state_headerOut;
reg rdreq_header,wrreq_header;
reg [129:0] data_header;
wire empty_header;
wire [129:0] q_header;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
rdreq_header <= 1'b0;
headerData_out_valid <= 1'b0;
headerData_out <= 138'b0;
state_headerOut <= 1'b0;
count_temp <= 8'd0;
end
else begin
case(state_headerOut)
1'b0: begin
headerData_out_valid <= 1'b0;
headerData_out <= 138'b0;
if((empty_header==1'b0) && (headerIn_enable==1'b1)) begin
rdreq_header <= 1'b1;
state_headerOut <= 1'b1;
end
else begin
rdreq_header <= 1'b0;
state_headerOut <= 1'b0;
end
end
1'b1: begin
headerData_out_valid <= 1'b1;
headerData_out <= {count_temp,q_header};
if(q_header[129:128]==2'b01) begin
rdreq_header <= 1'b0;
state_headerOut <= 1'b0;
count_temp <= count_temp + 8'd1;
end
else begin
rdreq_header <= 1'b1;
state_headerOut <= 1'b1;
end
end
endcase
end
end
always @ (posedge clk or negedge reset) begin
if(!reset) begin
wrreq_header <= 1'b0;
data_header <= 130'b0;
state_headerIn <= 1'b0;
end
else begin
case(state_headerIn)
1'b0: begin
if(headerData_valid == 1'b1) begin
if(headerIn_enable==1'b1) begin
wrreq_header <= 1'b1;
data_header <= headerData;
end
else begin
wrreq_header <= 1'b0;
state_headerIn <= 1'b1;
end
end
else begin
wrreq_header <= 1'b0;
state_headerIn <= 1'b0;
end
end
1'b1: begin
data_header <= headerData;
if(headerData[129:128]==2'b01) begin
state_headerIn <= 1'b0;
end
else state_headerIn <= 1'b1;
end
endcase
end
end
reg [31:0] count_time;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
count_time <= 32'b0;
end
else begin
count_time <= 32'b1 + count_time;
end
end
fifo fifo_header(
.aclr(!reset),
.clock(clk),
.data(data_header),
.rdreq(rdreq_header),
.wrreq(wrreq_header),
.empty(empty_header),
.full(),
.q(q_header),
.usedw()
);
defparam
fifo_header.width = 130,
fifo_header.depth = 8,
fifo_header.words = 256;
endmodule | module pkt_gen(
clk,
reset,
headerData_valid,
headerData,
headerData_out_valid,
headerData_out,
headerIn_enable
); |
input clk;
input reset;
input headerData_valid;
input [129:0] headerData;
output reg headerData_out_valid;
output reg [137:0] headerData_out;
input headerIn_enable;
reg [7:0] count_temp;
reg state_headerIn,state_headerOut;
reg rdreq_header,wrreq_header;
reg [129:0] data_header;
wire empty_header;
wire [129:0] q_header;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
rdreq_header <= 1'b0;
headerData_out_valid <= 1'b0;
headerData_out <= 138'b0;
state_headerOut <= 1'b0;
count_temp <= 8'd0;
end
else begin
case(state_headerOut)
1'b0: begin
headerData_out_valid <= 1'b0;
headerData_out <= 138'b0;
if((empty_header==1'b0) && (headerIn_enable==1'b1)) begin
rdreq_header <= 1'b1;
state_headerOut <= 1'b1;
end
else begin
rdreq_header <= 1'b0;
state_headerOut <= 1'b0;
end
end
1'b1: begin
headerData_out_valid <= 1'b1;
headerData_out <= {count_temp,q_header};
if(q_header[129:128]==2'b01) begin
rdreq_header <= 1'b0;
state_headerOut <= 1'b0;
count_temp <= count_temp + 8'd1;
end
else begin
rdreq_header <= 1'b1;
state_headerOut <= 1'b1;
end
end
endcase
end
end
always @ (posedge clk or negedge reset) begin
if(!reset) begin
wrreq_header <= 1'b0;
data_header <= 130'b0;
state_headerIn <= 1'b0;
end
else begin
case(state_headerIn)
1'b0: begin
if(headerData_valid == 1'b1) begin
if(headerIn_enable==1'b1) begin
wrreq_header <= 1'b1;
data_header <= headerData;
end
else begin
wrreq_header <= 1'b0;
state_headerIn <= 1'b1;
end
end
else begin
wrreq_header <= 1'b0;
state_headerIn <= 1'b0;
end
end
1'b1: begin
data_header <= headerData;
if(headerData[129:128]==2'b01) begin
state_headerIn <= 1'b0;
end
else state_headerIn <= 1'b1;
end
endcase
end
end
reg [31:0] count_time;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
count_time <= 32'b0;
end
else begin
count_time <= 32'b1 + count_time;
end
end
fifo fifo_header(
.aclr(!reset),
.clock(clk),
.data(data_header),
.rdreq(rdreq_header),
.wrreq(wrreq_header),
.empty(empty_header),
.full(),
.q(q_header),
.usedw()
);
defparam
fifo_header.width = 130,
fifo_header.depth = 8,
fifo_header.words = 256;
endmodule | 0 |
138,288 | data/full_repos/permissive/83198026/result_accumulator.v | 83,198,026 | result_accumulator.v | v | 148 | 86 | [] | [] | [] | null | line:122: before: "." | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/83198026/result_accumulator.v:85: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'addr_a\' generates 8 bits.\n : ... In instance result_accumulator\n addr_a <= addr_a + 10\'d1;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/83198026/result_accumulator.v:85: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 10 bits.\n : ... In instance result_accumulator\n addr_a <= addr_a + 10\'d1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83198026/result_accumulator.v:89: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'addr_a\' generates 8 bits.\n : ... In instance result_accumulator\n addr_a <= addr_a + 10\'d1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/83198026/result_accumulator.v:89: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 10 bits.\n : ... In instance result_accumulator\n addr_a <= addr_a + 10\'d1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83198026/result_accumulator.v:100: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'addr_a\' generates 8 bits.\n : ... In instance result_accumulator\n addr_a <= addr_a + 10\'b1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/83198026/result_accumulator.v:100: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 10 bits.\n : ... In instance result_accumulator\n addr_a <= addr_a + 10\'b1;\n ^~\n%Error: data/full_repos/permissive/83198026/result_accumulator.v:108: Cannot find file containing module: \'ram\'\nram result(\n^~~\n ... Looked in:\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/ram\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/ram.v\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/ram.sv\n ram\n ram.v\n ram.sv\n obj_dir/ram\n obj_dir/ram.v\n obj_dir/ram.sv\n%Error: data/full_repos/permissive/83198026/result_accumulator.v:128: Cannot find file containing module: \'fifo\'\nfifo fifo_finish(\n^~~~\n%Error: Exiting due to 2 error(s), 6 warning(s)\n' | 302,127 | module | module result_accumulator(
clk,
reset,
field_valid,
field,
offset,
field_finish_valid,
field_finish_bid,
metadata_valid,
metadata
);
parameter widthHeaderData = 32,
widthHeaderVector=200;
input clk;
input reset;
input field_valid;
input [widthHeaderData-1:0] field;
input [11:0] offset;
input field_finish_valid;
input [23:0] field_finish_bid;
output reg metadata_valid;
output reg [widthHeaderVector-1:0] metadata;
reg [7:0] pktID_temp;
reg [7:0] addr_a;
reg rden_a;
wire [widthHeaderData-1:0] q_a;
reg rdreq_finish;
wire empty_finish;
wire [23:0] q_finish;
reg [2:0] state;
parameter idle = 3'd0,
read_fifo = 3'd1,
wait1 = 3'd2,
wait2 = 3'd3,
read = 3'd4;
always @(posedge clk or negedge reset) begin
if(!reset) begin
metadata_valid <= 1'b0;
metadata <= {widthHeaderVector{1'b0}};
rden_a <= 1'b0;
addr_a <= 8'b0;
rdreq_finish <= 1'b0;
pktID_temp <= 8'd0;
state <= idle;
end
else begin
case(state)
idle: begin
metadata_valid <= 1'b0;
if(empty_finish == 1'b0) begin
state <= read_fifo;
rdreq_finish <= 1'b1;
end
end
read_fifo: begin
rdreq_finish <= 1'b0;
if(q_finish[23]==1'b1) begin
metadata_valid <= 1'b1;
metadata <= {q_finish[7:0],{(widthHeaderVector-8){1'b0}}};
state <= idle;
end
else begin
rden_a <= 1'b1;
addr_a <= {q_finish[9:8],6'b0};
pktID_temp <= q_finish[7:0];
state <= wait1;
end
end
wait1: begin
addr_a <= addr_a + 10'd1;
state <= wait2;
end
wait2: begin
addr_a <= addr_a + 10'd1;
state <= read;
end
read: begin
if(addr_a[3:0] == 4'd7) begin
state <= idle;
rden_a <= 1'b0;
metadata_valid <= 1'b1;
end
else state <=read;
metadata <= {pktID_temp,metadata[widthHeaderVector-41:0],q_a};
addr_a <= addr_a + 10'b1;
end
endcase
end
end
ram result(
.address_a(addr_a),
.address_b({offset[8:7],offset[5:0]}),
.clock(clk),
.data_a({widthHeaderData{1'b0}}),
.data_b(field),
.rden_a(rden_a),
.rden_b(1'b0),
.wren_a(1'b0),
.wren_b(field_valid),
.q_a(q_a),
.q_b()
);
defparam
result.width = widthHeaderData,
result.depth = 8,
result.words = 256;
fifo fifo_finish(
.aclr(!reset),
.clock(clk),
.data(field_finish_bid),
.rdreq(rdreq_finish),
.wrreq(field_finish_valid),
.empty(empty_finish),
.full(),
.q(q_finish),
.usedw()
);
defparam
fifo_finish.width = 24,
fifo_finish.depth = 5,
fifo_finish.words = 32;
endmodule | module result_accumulator(
clk,
reset,
field_valid,
field,
offset,
field_finish_valid,
field_finish_bid,
metadata_valid,
metadata
); |
parameter widthHeaderData = 32,
widthHeaderVector=200;
input clk;
input reset;
input field_valid;
input [widthHeaderData-1:0] field;
input [11:0] offset;
input field_finish_valid;
input [23:0] field_finish_bid;
output reg metadata_valid;
output reg [widthHeaderVector-1:0] metadata;
reg [7:0] pktID_temp;
reg [7:0] addr_a;
reg rden_a;
wire [widthHeaderData-1:0] q_a;
reg rdreq_finish;
wire empty_finish;
wire [23:0] q_finish;
reg [2:0] state;
parameter idle = 3'd0,
read_fifo = 3'd1,
wait1 = 3'd2,
wait2 = 3'd3,
read = 3'd4;
always @(posedge clk or negedge reset) begin
if(!reset) begin
metadata_valid <= 1'b0;
metadata <= {widthHeaderVector{1'b0}};
rden_a <= 1'b0;
addr_a <= 8'b0;
rdreq_finish <= 1'b0;
pktID_temp <= 8'd0;
state <= idle;
end
else begin
case(state)
idle: begin
metadata_valid <= 1'b0;
if(empty_finish == 1'b0) begin
state <= read_fifo;
rdreq_finish <= 1'b1;
end
end
read_fifo: begin
rdreq_finish <= 1'b0;
if(q_finish[23]==1'b1) begin
metadata_valid <= 1'b1;
metadata <= {q_finish[7:0],{(widthHeaderVector-8){1'b0}}};
state <= idle;
end
else begin
rden_a <= 1'b1;
addr_a <= {q_finish[9:8],6'b0};
pktID_temp <= q_finish[7:0];
state <= wait1;
end
end
wait1: begin
addr_a <= addr_a + 10'd1;
state <= wait2;
end
wait2: begin
addr_a <= addr_a + 10'd1;
state <= read;
end
read: begin
if(addr_a[3:0] == 4'd7) begin
state <= idle;
rden_a <= 1'b0;
metadata_valid <= 1'b1;
end
else state <=read;
metadata <= {pktID_temp,metadata[widthHeaderVector-41:0],q_a};
addr_a <= addr_a + 10'b1;
end
endcase
end
end
ram result(
.address_a(addr_a),
.address_b({offset[8:7],offset[5:0]}),
.clock(clk),
.data_a({widthHeaderData{1'b0}}),
.data_b(field),
.rden_a(rden_a),
.rden_b(1'b0),
.wren_a(1'b0),
.wren_b(field_valid),
.q_a(q_a),
.q_b()
);
defparam
result.width = widthHeaderData,
result.depth = 8,
result.words = 256;
fifo fifo_finish(
.aclr(!reset),
.clock(clk),
.data(field_finish_bid),
.rdreq(rdreq_finish),
.wrreq(field_finish_valid),
.empty(empty_finish),
.full(),
.q(q_finish),
.usedw()
);
defparam
fifo_finish.width = 24,
fifo_finish.depth = 5,
fifo_finish.words = 32;
endmodule | 0 |
138,289 | data/full_repos/permissive/83198026/result_mux.v | 83,198,026 | result_mux.v | v | 294 | 71 | [] | [] | [] | null | line:170: before: "." | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/83198026/result_mux.v:73: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'read_odd\' generates 4 bits.\n : ... In instance result_mux\n state <= read_odd;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/83198026/result_mux.v:89: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'read_fifo\' generates 4 bits.\n : ... In instance result_mux\n state <= read_fifo;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83198026/result_mux.v:93: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'read_fifo\' generates 4 bits.\n : ... In instance result_mux\n state <= read_fifo;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83198026/result_mux.v:97: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'read_fifo\' generates 4 bits.\n : ... In instance result_mux\n state <= read_fifo;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83198026/result_mux.v:101: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'read_fifo\' generates 4 bits.\n : ... In instance result_mux\n state <= read_fifo;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83198026/result_mux.v:104: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'read_even\' generates 4 bits.\n : ... In instance result_mux\n state <= read_even;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83198026/result_mux.v:113: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'read_fifo\' generates 4 bits.\n : ... In instance result_mux\n state <= read_fifo;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83198026/result_mux.v:117: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'read_fifo\' generates 4 bits.\n : ... In instance result_mux\n state <= read_fifo;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83198026/result_mux.v:121: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'read_fifo\' generates 4 bits.\n : ... In instance result_mux\n state <= read_fifo;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83198026/result_mux.v:125: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'read_fifo\' generates 4 bits.\n : ... In instance result_mux\n state <= read_fifo;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83198026/result_mux.v:128: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'read_odd\' generates 4 bits.\n : ... In instance result_mux\n state <= read_odd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83198026/result_mux.v:133: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'read_odd\' generates 4 bits.\n : ... In instance result_mux\n if(odd_even_tag==1\'b1) state <= read_odd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83198026/result_mux.v:134: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'read_even\' generates 4 bits.\n : ... In instance result_mux\n else state <= read_even;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83198026/result_mux.v:152: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'read_odd\' generates 4 bits.\n : ... In instance result_mux\n default: state <= read_odd;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83198026/result_mux.v:83: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 3 bits.\n : ... In instance result_mux\n case(state)\n ^~~~\n%Error: data/full_repos/permissive/83198026/result_mux.v:158: Cannot find file containing module: \'fifo\'\nfifo fifo_meta_0(\n^~~~\n ... Looked in:\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/fifo\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/fifo.v\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/fifo.sv\n fifo\n fifo.v\n fifo.sv\n obj_dir/fifo\n obj_dir/fifo.v\n obj_dir/fifo.sv\n%Error: data/full_repos/permissive/83198026/result_mux.v:174: Cannot find file containing module: \'fifo\'\nfifo fifo_meta_1(\n^~~~\n%Error: data/full_repos/permissive/83198026/result_mux.v:190: Cannot find file containing module: \'fifo\'\nfifo fifo_meta_2(\n^~~~\n%Error: data/full_repos/permissive/83198026/result_mux.v:206: Cannot find file containing module: \'fifo\'\nfifo fifo_meta_3(\n^~~~\n%Error: data/full_repos/permissive/83198026/result_mux.v:222: Cannot find file containing module: \'fifo\'\nfifo fifo_meta_4(\n^~~~\n%Error: data/full_repos/permissive/83198026/result_mux.v:238: Cannot find file containing module: \'fifo\'\nfifo fifo_meta_5(\n^~~~\n%Error: data/full_repos/permissive/83198026/result_mux.v:254: Cannot find file containing module: \'fifo\'\nfifo fifo_meta_6(\n^~~~\n%Error: data/full_repos/permissive/83198026/result_mux.v:270: Cannot find file containing module: \'fifo\'\nfifo fifo_meta_7(\n^~~~\n%Error: Exiting due to 8 error(s), 15 warning(s)\n' | 302,128 | module | module result_mux(
clk,
reset,
metadata_valid_0,
metadata_0,
metadata_valid_1,
metadata_1,
metadata_valid_2,
metadata_2,
metadata_valid_3,
metadata_3,
metadata_valid_4,
metadata_4,
metadata_valid_5,
metadata_5,
metadata_valid_6,
metadata_6,
metadata_valid_7,
metadata_7,
headerVector_valid,
headerVector
);
parameter numExtraction = 8,
widthHeaderData = 32;
parameter widthHV = 200,
numMeta = 4,
limitMeta=4'd5;
input clk;
input reset;
input metadata_valid_0;
input [widthHV-1:0] metadata_0;
input metadata_valid_1;
input [widthHV-1:0] metadata_1;
input metadata_valid_2;
input [widthHV-1:0] metadata_2;
input metadata_valid_3;
input [widthHV-1:0] metadata_3;
input metadata_valid_4;
input [widthHV-1:0] metadata_4;
input metadata_valid_5;
input [widthHV-1:0] metadata_5;
input metadata_valid_6;
input [widthHV-1:0] metadata_6;
input metadata_valid_7;
input [widthHV-1:0] metadata_7;
output reg headerVector_valid;
output reg [widthHV-1:0] headerVector;
reg rdreq_meta[numExtraction-1:0];
wire empty_meta[numExtraction-1:0];
wire [widthHV-1:0] q_meta[numExtraction-1:0];
reg [2:0] state;
parameter read_odd = 4'd0,
read_even = 4'd1,
read_fifo = 4'd2;
reg [numMeta-1:0] count_meta;
reg odd_even_tag;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
state <= read_odd;
count_meta <= 4'b0;
headerVector_valid <= 1'b0;
headerVector <= {widthHV{1'b0}};
odd_even_tag <= 1'b1;
rdreq_meta[0] <= 1'b0;rdreq_meta[1] <= 1'b0;rdreq_meta[2] <= 1'b0;
rdreq_meta[3] <= 1'b0;rdreq_meta[4] <= 1'b0;rdreq_meta[5] <= 1'b0;
rdreq_meta[6] <= 1'b0;rdreq_meta[7] <= 1'b0;
end
else begin
case(state)
read_odd: begin
headerVector_valid <= 1'b0;
headerVector <= {widthHV{1'b0}};
if(empty_meta[0]==1'b0) begin
rdreq_meta[0] <= 1'b1;
state <= read_fifo;
end
else if(empty_meta[2]==1'b0) begin
rdreq_meta[2] <= 1'b1;
state <= read_fifo;
end
else if(empty_meta[4]==1'b0) begin
rdreq_meta[4] <= 1'b1;
state <= read_fifo;
end
else if(empty_meta[6]==1'b0) begin
rdreq_meta[6] <= 1'b1;
state <= read_fifo;
end
else begin
state <= read_even;
odd_even_tag <= 1'b0;
end
end
read_even: begin
headerVector_valid <= 1'b0;
headerVector <= {widthHV{1'b0}};
if(empty_meta[1]==1'b0) begin
rdreq_meta[1] <= 1'b1;
state <= read_fifo;
end
else if(empty_meta[3]==1'b0) begin
rdreq_meta[3] <= 1'b1;
state <= read_fifo;
end
else if(empty_meta[5]==1'b0) begin
rdreq_meta[5] <= 1'b1;
state <= read_fifo;
end
else if(empty_meta[7]==1'b0) begin
rdreq_meta[7] <= 1'b1;
state <= read_fifo;
end
else begin
state <= read_odd;
odd_even_tag <= 1'b1;
end
end
read_fifo: begin
if(odd_even_tag==1'b1) state <= read_odd;
else state <= read_even;
headerVector_valid <= 1'b1;
odd_even_tag <= ~odd_even_tag;
rdreq_meta[0] <= 1'b0;rdreq_meta[1] <= 1'b0;rdreq_meta[2] <= 1'b0;
rdreq_meta[3] <= 1'b0;rdreq_meta[4] <= 1'b0;rdreq_meta[5] <= 1'b0;
rdreq_meta[6] <= 1'b0;rdreq_meta[7] <= 1'b0;
case({rdreq_meta[7],rdreq_meta[6],rdreq_meta[5],rdreq_meta[4],
rdreq_meta[3],rdreq_meta[2],rdreq_meta[1],rdreq_meta[0]})
8'h1: headerVector <= q_meta[0];
8'h2: headerVector <= q_meta[1];
8'h4: headerVector <= q_meta[2];
8'h8: headerVector <= q_meta[3];
8'h10: headerVector <= q_meta[4];
8'h20: headerVector <= q_meta[5];
8'h40: headerVector <= q_meta[6];
8'h80: headerVector <= q_meta[7];
endcase
end
default: state <= read_odd;
endcase
end
end
fifo fifo_meta_0(
.aclr(!reset),
.clock(clk),
.data(metadata_0),
.rdreq(rdreq_meta[0]),
.wrreq(metadata_valid_0),
.empty(empty_meta[0]),
.full(),
.q(q_meta[0]),
.usedw()
);
defparam
fifo_meta_0.width = widthHV,
fifo_meta_0.depth = 5,
fifo_meta_0.words = 32;
fifo fifo_meta_1(
.aclr(!reset),
.clock(clk),
.data(metadata_1),
.rdreq(rdreq_meta[1]),
.wrreq(metadata_valid_1),
.empty(empty_meta[1]),
.full(),
.q(q_meta[1]),
.usedw()
);
defparam
fifo_meta_1.width = widthHV,
fifo_meta_1.depth = 5,
fifo_meta_1.words = 32;
fifo fifo_meta_2(
.aclr(!reset),
.clock(clk),
.data(metadata_2),
.rdreq(rdreq_meta[2]),
.wrreq(metadata_valid_2),
.empty(empty_meta[2]),
.full(),
.q(q_meta[2]),
.usedw()
);
defparam
fifo_meta_2.width = widthHV,
fifo_meta_2.depth = 5,
fifo_meta_2.words = 32;
fifo fifo_meta_3(
.aclr(!reset),
.clock(clk),
.data(metadata_3),
.rdreq(rdreq_meta[3]),
.wrreq(metadata_valid_3),
.empty(empty_meta[3]),
.full(),
.q(q_meta[3]),
.usedw()
);
defparam
fifo_meta_3.width = widthHV,
fifo_meta_3.depth = 5,
fifo_meta_3.words = 32;
fifo fifo_meta_4(
.aclr(!reset),
.clock(clk),
.data(metadata_4),
.rdreq(rdreq_meta[4]),
.wrreq(metadata_valid_4),
.empty(empty_meta[4]),
.full(),
.q(q_meta[4]),
.usedw()
);
defparam
fifo_meta_4.width = widthHV,
fifo_meta_4.depth = 5,
fifo_meta_4.words = 32;
fifo fifo_meta_5(
.aclr(!reset),
.clock(clk),
.data(metadata_5),
.rdreq(rdreq_meta[5]),
.wrreq(metadata_valid_5),
.empty(empty_meta[5]),
.full(),
.q(q_meta[5]),
.usedw()
);
defparam
fifo_meta_5.width = widthHV,
fifo_meta_5.depth = 5,
fifo_meta_5.words = 32;
fifo fifo_meta_6(
.aclr(!reset),
.clock(clk),
.data(metadata_6),
.rdreq(rdreq_meta[6]),
.wrreq(metadata_valid_6),
.empty(empty_meta[6]),
.full(),
.q(q_meta[6]),
.usedw()
);
defparam
fifo_meta_6.width = widthHV,
fifo_meta_6.depth = 5,
fifo_meta_6.words = 32;
fifo fifo_meta_7(
.aclr(!reset),
.clock(clk),
.data(metadata_7),
.rdreq(rdreq_meta[7]),
.wrreq(metadata_valid_7),
.empty(empty_meta[7]),
.full(),
.q(q_meta[7]),
.usedw()
);
defparam
fifo_meta_7.width = widthHV,
fifo_meta_7.depth = 5,
fifo_meta_7.words = 32;
endmodule | module result_mux(
clk,
reset,
metadata_valid_0,
metadata_0,
metadata_valid_1,
metadata_1,
metadata_valid_2,
metadata_2,
metadata_valid_3,
metadata_3,
metadata_valid_4,
metadata_4,
metadata_valid_5,
metadata_5,
metadata_valid_6,
metadata_6,
metadata_valid_7,
metadata_7,
headerVector_valid,
headerVector
); |
parameter numExtraction = 8,
widthHeaderData = 32;
parameter widthHV = 200,
numMeta = 4,
limitMeta=4'd5;
input clk;
input reset;
input metadata_valid_0;
input [widthHV-1:0] metadata_0;
input metadata_valid_1;
input [widthHV-1:0] metadata_1;
input metadata_valid_2;
input [widthHV-1:0] metadata_2;
input metadata_valid_3;
input [widthHV-1:0] metadata_3;
input metadata_valid_4;
input [widthHV-1:0] metadata_4;
input metadata_valid_5;
input [widthHV-1:0] metadata_5;
input metadata_valid_6;
input [widthHV-1:0] metadata_6;
input metadata_valid_7;
input [widthHV-1:0] metadata_7;
output reg headerVector_valid;
output reg [widthHV-1:0] headerVector;
reg rdreq_meta[numExtraction-1:0];
wire empty_meta[numExtraction-1:0];
wire [widthHV-1:0] q_meta[numExtraction-1:0];
reg [2:0] state;
parameter read_odd = 4'd0,
read_even = 4'd1,
read_fifo = 4'd2;
reg [numMeta-1:0] count_meta;
reg odd_even_tag;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
state <= read_odd;
count_meta <= 4'b0;
headerVector_valid <= 1'b0;
headerVector <= {widthHV{1'b0}};
odd_even_tag <= 1'b1;
rdreq_meta[0] <= 1'b0;rdreq_meta[1] <= 1'b0;rdreq_meta[2] <= 1'b0;
rdreq_meta[3] <= 1'b0;rdreq_meta[4] <= 1'b0;rdreq_meta[5] <= 1'b0;
rdreq_meta[6] <= 1'b0;rdreq_meta[7] <= 1'b0;
end
else begin
case(state)
read_odd: begin
headerVector_valid <= 1'b0;
headerVector <= {widthHV{1'b0}};
if(empty_meta[0]==1'b0) begin
rdreq_meta[0] <= 1'b1;
state <= read_fifo;
end
else if(empty_meta[2]==1'b0) begin
rdreq_meta[2] <= 1'b1;
state <= read_fifo;
end
else if(empty_meta[4]==1'b0) begin
rdreq_meta[4] <= 1'b1;
state <= read_fifo;
end
else if(empty_meta[6]==1'b0) begin
rdreq_meta[6] <= 1'b1;
state <= read_fifo;
end
else begin
state <= read_even;
odd_even_tag <= 1'b0;
end
end
read_even: begin
headerVector_valid <= 1'b0;
headerVector <= {widthHV{1'b0}};
if(empty_meta[1]==1'b0) begin
rdreq_meta[1] <= 1'b1;
state <= read_fifo;
end
else if(empty_meta[3]==1'b0) begin
rdreq_meta[3] <= 1'b1;
state <= read_fifo;
end
else if(empty_meta[5]==1'b0) begin
rdreq_meta[5] <= 1'b1;
state <= read_fifo;
end
else if(empty_meta[7]==1'b0) begin
rdreq_meta[7] <= 1'b1;
state <= read_fifo;
end
else begin
state <= read_odd;
odd_even_tag <= 1'b1;
end
end
read_fifo: begin
if(odd_even_tag==1'b1) state <= read_odd;
else state <= read_even;
headerVector_valid <= 1'b1;
odd_even_tag <= ~odd_even_tag;
rdreq_meta[0] <= 1'b0;rdreq_meta[1] <= 1'b0;rdreq_meta[2] <= 1'b0;
rdreq_meta[3] <= 1'b0;rdreq_meta[4] <= 1'b0;rdreq_meta[5] <= 1'b0;
rdreq_meta[6] <= 1'b0;rdreq_meta[7] <= 1'b0;
case({rdreq_meta[7],rdreq_meta[6],rdreq_meta[5],rdreq_meta[4],
rdreq_meta[3],rdreq_meta[2],rdreq_meta[1],rdreq_meta[0]})
8'h1: headerVector <= q_meta[0];
8'h2: headerVector <= q_meta[1];
8'h4: headerVector <= q_meta[2];
8'h8: headerVector <= q_meta[3];
8'h10: headerVector <= q_meta[4];
8'h20: headerVector <= q_meta[5];
8'h40: headerVector <= q_meta[6];
8'h80: headerVector <= q_meta[7];
endcase
end
default: state <= read_odd;
endcase
end
end
fifo fifo_meta_0(
.aclr(!reset),
.clock(clk),
.data(metadata_0),
.rdreq(rdreq_meta[0]),
.wrreq(metadata_valid_0),
.empty(empty_meta[0]),
.full(),
.q(q_meta[0]),
.usedw()
);
defparam
fifo_meta_0.width = widthHV,
fifo_meta_0.depth = 5,
fifo_meta_0.words = 32;
fifo fifo_meta_1(
.aclr(!reset),
.clock(clk),
.data(metadata_1),
.rdreq(rdreq_meta[1]),
.wrreq(metadata_valid_1),
.empty(empty_meta[1]),
.full(),
.q(q_meta[1]),
.usedw()
);
defparam
fifo_meta_1.width = widthHV,
fifo_meta_1.depth = 5,
fifo_meta_1.words = 32;
fifo fifo_meta_2(
.aclr(!reset),
.clock(clk),
.data(metadata_2),
.rdreq(rdreq_meta[2]),
.wrreq(metadata_valid_2),
.empty(empty_meta[2]),
.full(),
.q(q_meta[2]),
.usedw()
);
defparam
fifo_meta_2.width = widthHV,
fifo_meta_2.depth = 5,
fifo_meta_2.words = 32;
fifo fifo_meta_3(
.aclr(!reset),
.clock(clk),
.data(metadata_3),
.rdreq(rdreq_meta[3]),
.wrreq(metadata_valid_3),
.empty(empty_meta[3]),
.full(),
.q(q_meta[3]),
.usedw()
);
defparam
fifo_meta_3.width = widthHV,
fifo_meta_3.depth = 5,
fifo_meta_3.words = 32;
fifo fifo_meta_4(
.aclr(!reset),
.clock(clk),
.data(metadata_4),
.rdreq(rdreq_meta[4]),
.wrreq(metadata_valid_4),
.empty(empty_meta[4]),
.full(),
.q(q_meta[4]),
.usedw()
);
defparam
fifo_meta_4.width = widthHV,
fifo_meta_4.depth = 5,
fifo_meta_4.words = 32;
fifo fifo_meta_5(
.aclr(!reset),
.clock(clk),
.data(metadata_5),
.rdreq(rdreq_meta[5]),
.wrreq(metadata_valid_5),
.empty(empty_meta[5]),
.full(),
.q(q_meta[5]),
.usedw()
);
defparam
fifo_meta_5.width = widthHV,
fifo_meta_5.depth = 5,
fifo_meta_5.words = 32;
fifo fifo_meta_6(
.aclr(!reset),
.clock(clk),
.data(metadata_6),
.rdreq(rdreq_meta[6]),
.wrreq(metadata_valid_6),
.empty(empty_meta[6]),
.full(),
.q(q_meta[6]),
.usedw()
);
defparam
fifo_meta_6.width = widthHV,
fifo_meta_6.depth = 5,
fifo_meta_6.words = 32;
fifo fifo_meta_7(
.aclr(!reset),
.clock(clk),
.data(metadata_7),
.rdreq(rdreq_meta[7]),
.wrreq(metadata_valid_7),
.empty(empty_meta[7]),
.full(),
.q(q_meta[7]),
.usedw()
);
defparam
fifo_meta_7.width = widthHV,
fifo_meta_7.depth = 5,
fifo_meta_7.words = 32;
endmodule | 0 |
138,290 | data/full_repos/permissive/83198026/ruleConfigurer.v | 83,198,026 | ruleConfigurer.v | v | 74 | 99 | [] | [] | [] | [(7, 73)] | null | data/verilator_xmls/6b8820c6-85a8-4f80-9908-769e7b0e4333.xml | null | 302,129 | module | module ruleConfigurer(
clk,
reset,
ruleSet_valid,
ruleSet,
ruleSetTCAM_valid,
ruleSetTCAM,
ruleSetActionRAM_valid,
ruleSetActionRAM
);
input clk;
input reset;
input ruleSet_valid;
input [169:0] ruleSet;
output reg ruleSetTCAM_valid;
output reg [49:0] ruleSetTCAM;
output reg ruleSetActionRAM_valid;
output reg [129:0] ruleSetActionRAM;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
ruleSetActionRAM_valid <= 1'b0;
ruleSetActionRAM <= 130'b0;
ruleSetTCAM_valid <= 1'b0;
ruleSetTCAM <= 50'b0;
end
else begin
if(ruleSet_valid==1'b1) begin
case(ruleSet[169:168])
2'd0: begin
ruleSetActionRAM_valid <= 1'b1;
ruleSetActionRAM <= {2'd0,120'b0,ruleSet[7:0]};
ruleSetTCAM_valid <= 1'b0;
end
2'd1: begin
ruleSetActionRAM_valid <= 1'b1;
ruleSetActionRAM <= {2'd1,ruleSet[127:0]};
ruleSetTCAM_valid <= 1'b1;
ruleSetTCAM <= {2'd1,ruleSet[167:128],ruleSet[7:0]};
end
2'd2: begin
ruleSetActionRAM_valid <= 1'b0;
ruleSetTCAM_valid <= 1'b1;
ruleSetTCAM <= {2'd2,ruleSet[167:128],ruleSet[7:0]};
end
default: begin
end
endcase
end
else begin
ruleSetActionRAM_valid <= 1'b0;
ruleSetTCAM_valid <= 1'b0;
end
end
end
endmodule | module ruleConfigurer(
clk,
reset,
ruleSet_valid,
ruleSet,
ruleSetTCAM_valid,
ruleSetTCAM,
ruleSetActionRAM_valid,
ruleSetActionRAM
); |
input clk;
input reset;
input ruleSet_valid;
input [169:0] ruleSet;
output reg ruleSetTCAM_valid;
output reg [49:0] ruleSetTCAM;
output reg ruleSetActionRAM_valid;
output reg [129:0] ruleSetActionRAM;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
ruleSetActionRAM_valid <= 1'b0;
ruleSetActionRAM <= 130'b0;
ruleSetTCAM_valid <= 1'b0;
ruleSetTCAM <= 50'b0;
end
else begin
if(ruleSet_valid==1'b1) begin
case(ruleSet[169:168])
2'd0: begin
ruleSetActionRAM_valid <= 1'b1;
ruleSetActionRAM <= {2'd0,120'b0,ruleSet[7:0]};
ruleSetTCAM_valid <= 1'b0;
end
2'd1: begin
ruleSetActionRAM_valid <= 1'b1;
ruleSetActionRAM <= {2'd1,ruleSet[127:0]};
ruleSetTCAM_valid <= 1'b1;
ruleSetTCAM <= {2'd1,ruleSet[167:128],ruleSet[7:0]};
end
2'd2: begin
ruleSetActionRAM_valid <= 1'b0;
ruleSetTCAM_valid <= 1'b1;
ruleSetTCAM <= {2'd2,ruleSet[167:128],ruleSet[7:0]};
end
default: begin
end
endcase
end
else begin
ruleSetActionRAM_valid <= 1'b0;
ruleSetTCAM_valid <= 1'b0;
end
end
end
endmodule | 0 |
138,291 | data/full_repos/permissive/83198026/tcam.v | 83,198,026 | tcam.v | v | 160 | 79 | [] | [] | [] | [(7, 159)] | null | null | 1: b"%Error: data/full_repos/permissive/83198026/tcam.v:84: Cannot find file containing module: 'lookup_bit'\n lookup_bit lb(\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/lookup_bit\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/lookup_bit.v\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/lookup_bit.sv\n lookup_bit\n lookup_bit.v\n lookup_bit.sv\n obj_dir/lookup_bit\n obj_dir/lookup_bit.v\n obj_dir/lookup_bit.sv\n%Error: data/full_repos/permissive/83198026/tcam.v:110: Cannot find file containing module: 'calculate_countid'\ncalculate_countid calculate_countid(\n^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 302,130 | module | module BVbasedSearcher(
clk,
reset,
key,
key_valid,
index_valid,
index,
ruleSet_valid,
ruleSet,
result_valid,
result
);
parameter depthTCAM = 6;
input clk;
input reset;
input [44:0] key;
input key_valid;
output reg index_valid;
output reg [depthTCAM+4:0] index;
input ruleSet_valid;
input [49:0] ruleSet;
output reg result_valid;
output reg [63:0] result;
integer i1,i2,i3;
wire bv_valid[4:0];
wire [63:0] bv[4:0];
reg bv_and_valid;
reg [63:0] bv_and;
reg [4:0] bid_temp[10:0];
wire countid_valid;
wire [5:0] countid;
reg set_valid[4:0];
reg [16:0] rule_set[4:0];
always @ (posedge clk or negedge reset) begin
if(!reset) begin
for(i1=0;i1<5;i1=i1+1) begin
set_valid[i1] <=1'b0;
rule_set[i1] <= 17'b0;
end
end
else begin
if(ruleSet_valid==1'b1) begin
for(i2=0;i2<5;i2=i2+1) begin
set_valid[i2] <=1'b1;
end
rule_set[0] <= {ruleSet[48],ruleSet[15:0]};
rule_set[1] <= {ruleSet[48],ruleSet[23:16],ruleSet[7:0]};
rule_set[2] <= {ruleSet[48],ruleSet[31:24],ruleSet[7:0]};
rule_set[3] <= {ruleSet[48],ruleSet[39:32],ruleSet[7:0]};
rule_set[4] <= {ruleSet[48],ruleSet[47:40],ruleSet[7:0]};
end
else begin
for(i3=0;i3<5;i3=i3+1) begin
set_valid[i3] <=1'b0;
rule_set[i3] <= 17'b0;
end
end
end
end
generate
genvar i;
for(i=0; i<5; i=i+1) begin: lookup_bit
lookup_bit lb(
.clk(clk),
.reset(reset),
.key_valid(key_valid),
.key(key[(i*8+7):i*8]),
.bv_valid(bv_valid[i]),
.bv(bv[i]),
.set_valid(set_valid[i]),
.set(rule_set[i])
);
end
endgenerate
always @(posedge clk or negedge reset) begin
if(!reset) begin
bv_and_valid <= 1'b0;
bv_and <= 64'b0;
end
else begin
bv_and <= bv[0]&bv[1]&bv[2]&bv[3]&bv[4];
bv_and_valid <= bv_valid[0];
end
end
calculate_countid calculate_countid(
.clk(clk),
.reset(reset),
.bv_in_valid(bv_and_valid),
.bv_in(bv_and),
.countid_valid(countid_valid),
.countid(countid)
);
always @ (posedge clk or negedge reset) begin
if(!reset) begin
bid_temp[0] <= 5'b0;
end
else begin
bid_temp[0] <= key[44:40];
bid_temp[1] <= bid_temp[0];
bid_temp[2] <= bid_temp[1];
bid_temp[3] <= bid_temp[2];
bid_temp[4] <= bid_temp[3];
bid_temp[5] <= bid_temp[4];
bid_temp[6] <= bid_temp[5];
bid_temp[7] <= bid_temp[6];
bid_temp[8] <= bid_temp[7];
bid_temp[9] <= bid_temp[8];
bid_temp[10] <= bid_temp[9];
end
end
always @ (posedge clk or negedge reset) begin
if(!reset) begin
index_valid <= 1'b0;
index <= 11'b0;
end
else begin
if(countid_valid==1'b1) begin
index_valid <= 1'b1;
index <= {bid_temp[9],countid};
end
else index_valid <= 1'b0;
end
end
endmodule | module BVbasedSearcher(
clk,
reset,
key,
key_valid,
index_valid,
index,
ruleSet_valid,
ruleSet,
result_valid,
result
); |
parameter depthTCAM = 6;
input clk;
input reset;
input [44:0] key;
input key_valid;
output reg index_valid;
output reg [depthTCAM+4:0] index;
input ruleSet_valid;
input [49:0] ruleSet;
output reg result_valid;
output reg [63:0] result;
integer i1,i2,i3;
wire bv_valid[4:0];
wire [63:0] bv[4:0];
reg bv_and_valid;
reg [63:0] bv_and;
reg [4:0] bid_temp[10:0];
wire countid_valid;
wire [5:0] countid;
reg set_valid[4:0];
reg [16:0] rule_set[4:0];
always @ (posedge clk or negedge reset) begin
if(!reset) begin
for(i1=0;i1<5;i1=i1+1) begin
set_valid[i1] <=1'b0;
rule_set[i1] <= 17'b0;
end
end
else begin
if(ruleSet_valid==1'b1) begin
for(i2=0;i2<5;i2=i2+1) begin
set_valid[i2] <=1'b1;
end
rule_set[0] <= {ruleSet[48],ruleSet[15:0]};
rule_set[1] <= {ruleSet[48],ruleSet[23:16],ruleSet[7:0]};
rule_set[2] <= {ruleSet[48],ruleSet[31:24],ruleSet[7:0]};
rule_set[3] <= {ruleSet[48],ruleSet[39:32],ruleSet[7:0]};
rule_set[4] <= {ruleSet[48],ruleSet[47:40],ruleSet[7:0]};
end
else begin
for(i3=0;i3<5;i3=i3+1) begin
set_valid[i3] <=1'b0;
rule_set[i3] <= 17'b0;
end
end
end
end
generate
genvar i;
for(i=0; i<5; i=i+1) begin: lookup_bit
lookup_bit lb(
.clk(clk),
.reset(reset),
.key_valid(key_valid),
.key(key[(i*8+7):i*8]),
.bv_valid(bv_valid[i]),
.bv(bv[i]),
.set_valid(set_valid[i]),
.set(rule_set[i])
);
end
endgenerate
always @(posedge clk or negedge reset) begin
if(!reset) begin
bv_and_valid <= 1'b0;
bv_and <= 64'b0;
end
else begin
bv_and <= bv[0]&bv[1]&bv[2]&bv[3]&bv[4];
bv_and_valid <= bv_valid[0];
end
end
calculate_countid calculate_countid(
.clk(clk),
.reset(reset),
.bv_in_valid(bv_and_valid),
.bv_in(bv_and),
.countid_valid(countid_valid),
.countid(countid)
);
always @ (posedge clk or negedge reset) begin
if(!reset) begin
bid_temp[0] <= 5'b0;
end
else begin
bid_temp[0] <= key[44:40];
bid_temp[1] <= bid_temp[0];
bid_temp[2] <= bid_temp[1];
bid_temp[3] <= bid_temp[2];
bid_temp[4] <= bid_temp[3];
bid_temp[5] <= bid_temp[4];
bid_temp[6] <= bid_temp[5];
bid_temp[7] <= bid_temp[6];
bid_temp[8] <= bid_temp[7];
bid_temp[9] <= bid_temp[8];
bid_temp[10] <= bid_temp[9];
end
end
always @ (posedge clk or negedge reset) begin
if(!reset) begin
index_valid <= 1'b0;
index <= 11'b0;
end
else begin
if(countid_valid==1'b1) begin
index_valid <= 1'b1;
index <= {bid_temp[9],countid};
end
else index_valid <= 1'b0;
end
end
endmodule | 0 |
138,292 | data/full_repos/permissive/83198026/test_bench.v | 83,198,026 | test_bench.v | v | 1,081 | 96 | [] | [] | [] | null | line:98: before: "begin" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:88: Unsupported: Ignoring delay on this delayed statement.\n #1 reset = 1\'b0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:89: Unsupported: Ignoring delay on this delayed statement.\n #1 reset = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:90: Unsupported: Ignoring delay on this delayed statement.\n forever #1 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:98: Unsupported: Ignoring delay on this delayed statement.\n #20 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:103: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:108: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:112: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:117: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:122: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:126: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:131: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:136: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:140: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:145: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:150: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:154: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:159: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:164: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:168: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:173: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:178: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:183: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:188: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:193: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:197: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:202: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:207: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:211: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:216: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:221: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:225: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:230: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:235: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:239: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:244: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:249: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:253: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:258: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:263: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:270: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:275: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:280: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:284: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:289: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:294: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:298: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:303: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:308: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:312: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:317: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:322: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:326: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:331: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:336: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:340: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:345: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:350: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:357: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:362: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:367: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:371: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:376: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:381: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:385: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:390: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:395: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:399: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:404: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:409: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:413: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:418: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:423: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:427: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:432: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:437: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:446: Unsupported: Ignoring delay on this delayed statement.\n #20 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:451: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:456: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:460: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:465: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:470: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:474: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:479: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:484: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:488: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:493: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:498: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:502: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:507: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:512: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:516: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:521: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:526: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:531: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:536: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:541: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:544: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:549: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:554: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:562: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:567: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:572: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:576: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:581: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:586: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:590: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:595: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:600: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:604: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:609: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:614: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:618: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:623: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:628: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:632: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:637: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:642: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:646: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:651: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:656: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:659: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:664: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:669: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:674: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:679: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:684: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:687: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:692: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:697: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:794: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:799: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:804: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:808: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:813: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:818: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:822: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:827: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:832: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:836: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:841: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:846: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:850: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:855: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:860: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:864: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:869: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:874: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:883: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:888: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:893: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:897: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:902: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:907: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:911: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:916: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:921: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:925: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:930: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:935: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:939: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:944: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:949: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:953: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:958: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:963: Unsupported: Ignoring delay on this delayed statement.\n #4 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1021: Unsupported: Ignoring delay on this delayed statement.\n #300 begin end\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1024: Unsupported: Ignoring delay on this delayed statement.\n #20 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1028: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data = pkt[1]+count;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1029: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data = pkt[2];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1030: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data = pkt[3];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1031: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data = pkt[4];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1032: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data = pkt[5];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1033: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data = pkt[6];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1034: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data_valid = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1036: Unsupported: Ignoring delay on this delayed statement.\n #2 count = count + 139\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1037: Unsupported: Ignoring delay on this delayed statement.\n #20 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1041: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data = pkt[1]+count;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1042: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data = pkt[2];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1043: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data = pkt[6];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1044: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data_valid = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1047: Unsupported: Ignoring delay on this delayed statement.\n #2 count = count + 139\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1048: Unsupported: Ignoring delay on this delayed statement.\n #2 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1052: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data = pkt[1]+count;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1053: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data = pkt[2];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1054: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data = pkt[3];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1055: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data = pkt[4];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1056: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data = pkt[5];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1057: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data = pkt[6]; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1058: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data_valid = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1064: Unsupported: Ignoring delay on this delayed statement.\n #2 count = count + 139\'d1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1065: Unsupported: Ignoring delay on this delayed statement.\n #20 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1069: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data = pkt[1]+count;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1070: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data = pkt[2];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1071: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data = pkt[3];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1072: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data = pkt[4];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1073: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data = pkt[5];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1074: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data = pkt[6];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83198026/test_bench.v:1075: Unsupported: Ignoring delay on this delayed statement.\n #2 cdp2um_data_valid = 1\'b0;\n ^\n%Error: data/full_repos/permissive/83198026/test_bench.v:34: Cannot find file containing module: \'um\'\num um(\n^~\n ... Looked in:\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/um\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/um.v\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/um.sv\n um\n um.v\n um.sv\n obj_dir/um\n obj_dir/um.v\n obj_dir/um.sv\n%Warning-WIDTH: data/full_repos/permissive/83198026/test_bench.v:81: Operator ASSIGN expects 139 bits on the Assign RHS, but Assign RHS\'s CONST \'138\'h0\' generates 138 bits.\n : ... In instance test\n cdp2um_data = 138\'b0;\n ^\n%Error: Exiting due to 1 error(s), 199 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 302,131 | module | module test();
reg clk;
reg reset;
reg localbus_cs_n;
reg localbus_rd_wr;
reg [31:0] localbus_data;
reg localbus_ale;
wire localbus_ack_n;
wire [31:0] localbus_data_out;
wire um2cdp_path;
reg cdp2um_data_valid;
reg [138:0] cdp2um_data;
wire um2cdp_tx_enable;
wire um2cdp_data_valid;
wire [138:0] um2cdp_data;
reg cdp2um_tx_enable;
wire um2cdp_rule_wrreq;
wire [29:0] um2cdp_rule;
reg [4:0] cdp2um_rule_usedw;
um um(
clk,
reset,
localbus_cs_n,
localbus_rd_wr,
localbus_data,
localbus_ale,
localbus_ack_n,
localbus_data_out,
um2cdp_path,
cdp2um_data_valid,
cdp2um_data,
um2cdp_tx_enable,
um2cdp_data_valid,
um2cdp_data,
cdp2um_tx_enable,
um2cdp_rule,
um2cdp_rule_wrreq,
cdp2um_rule_usedw
);
integer i;
reg [138:0] pkt[9:0];
initial begin
pkt[0] = {3'b101,8'b0,48'h1111_2222_3333,48'h4444_5555_6666,16'h0800,16'h4500};
pkt[1] = {3'b100,8'b0,32'h0032_7919,32'h0000_4011,32'h7dfc_c0a8,32'h0000_0000};
pkt[2] = {3'b100,8'b0,32'h0101_0800,32'h4789_0400,32'h0500_6162,32'h6364_6566};
pkt[3] = {3'b100,8'b0,32'h6768_4444,32'h5555_6666,32'h1111_2222,32'h3333_0800};
pkt[4] = {3'b100,8'b0,32'h0032_7919,32'h0000_4011,32'h7dfc_c0a8,32'h0164_c0a8};
pkt[5] = {3'b100,8'b0,32'h0032_7919,32'h0000_4011,32'h7dfc_c0a8,32'h0164_c0a8};
pkt[6] = {3'b110,8'b0,32'h0032_7919,32'h0000_4011,32'h7dfc_c0a8,32'h0164_c0a8};
pkt[7] = {3'b101,8'b0,48'hffff_ffff_ffff,48'h4444_5555_6666,16'h0806,16'h0001};
pkt[8] = {3'b101,8'b0,48'h4444_5555_6666,48'h1111_2222_3333,16'h0806,16'h0001};
pkt[9] = {3'b101,8'b0,48'h4444_5555_6666,48'h1111_2222_3333,16'h0800,16'h0001};
end
initial begin
reset = 1'b1;
clk = 1'b0;
cdp2um_data_valid = 1'b0;
cdp2um_data = 138'b0;
cdp2um_tx_enable = 1'b1;
cdp2um_rule_usedw = 5'd1;
localbus_rd_wr = 1'b1;
localbus_ale = 1'b0;
localbus_cs_n= 1'b1;
localbus_data= 32'b0;
#1 reset = 1'b0;
#1 reset = 1'b1;
forever #1 clk = ~clk;
end
initial begin
#20 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0000;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {22'b0,2'd1,8'h00};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0001;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= 32'h00_0000_00;
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0002;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {8'd1,8'd0,8'd24,1'b0,1'b0,6'b0};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0003;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {8'd4,8'b0,8'd8,1'b1,7'd0};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0004;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {8'd1,24'b0};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0005;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {24'b0,8'd9};
end
#4 begin
localbus_cs_n <= 1'b1;
end
/
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0000;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {22'b0,2'd1,8'h11};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0001;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= 32'h00_0000_01;
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0002;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {8'd2,8'd2,8'd16,1'b0,1'b1,6'b0};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0003;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {8'd5,8'b0,8'd8,1'b1,7'd0};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0004;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {8'd0,24'b0};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0005;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {24'b0,8'd3};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0000;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {22'b0,2'd1,8'h47};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0001;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= 32'h89_0000_02;
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0002;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {8'd9,8'd9,8'd0,1'b1,1'b0,6'b0};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0003;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {8'd4,8'b0,8'd20,1'b1,7'd12};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0004;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {8'd1,24'b0};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0005;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {24'b0,8'd4};
end
#4 begin
localbus_cs_n <= 1'b1;
end
end
reg [138:0] count;
initial begin
count <= 139'b0;
#300 begin end
for(i=0;i<9;i=i+1) begin
#20 begin
cdp2um_data = pkt[0];
cdp2um_data_valid = 1'b1;
end
#2 cdp2um_data = pkt[1]+count;
#2 cdp2um_data = pkt[2];
#2 cdp2um_data = pkt[3];
#2 cdp2um_data = pkt[4];
#2 cdp2um_data = pkt[5];
#2 cdp2um_data = pkt[6];
#2 cdp2um_data_valid = 1'b0;
#2 count = count + 139'd1;
#20 begin
cdp2um_data = pkt[8];
cdp2um_data_valid = 1'b1;
end
#2 cdp2um_data = pkt[1]+count;
#2 cdp2um_data = pkt[2];
#2 cdp2um_data = pkt[6];
#2 cdp2um_data_valid = 1'b0;
#2 count = count + 139'd1;
#2 begin
cdp2um_data = pkt[0];
cdp2um_data_valid = 1'b1;
end
#2 cdp2um_data = pkt[1]+count;
#2 cdp2um_data = pkt[2];
#2 cdp2um_data = pkt[3];
#2 cdp2um_data = pkt[4];
#2 cdp2um_data = pkt[5];
#2 cdp2um_data = pkt[6];
#2 cdp2um_data_valid = 1'b0;
#2 count = count + 139'd1;
#20 begin
cdp2um_data = pkt[9];
cdp2um_data_valid = 1'b1;
end
#2 cdp2um_data = pkt[1]+count;
#2 cdp2um_data = pkt[2];
#2 cdp2um_data = pkt[3];
#2 cdp2um_data = pkt[4];
#2 cdp2um_data = pkt[5];
#2 cdp2um_data = pkt[6];
#2 cdp2um_data_valid = 1'b0;
end
end
endmodule | module test(); |
reg clk;
reg reset;
reg localbus_cs_n;
reg localbus_rd_wr;
reg [31:0] localbus_data;
reg localbus_ale;
wire localbus_ack_n;
wire [31:0] localbus_data_out;
wire um2cdp_path;
reg cdp2um_data_valid;
reg [138:0] cdp2um_data;
wire um2cdp_tx_enable;
wire um2cdp_data_valid;
wire [138:0] um2cdp_data;
reg cdp2um_tx_enable;
wire um2cdp_rule_wrreq;
wire [29:0] um2cdp_rule;
reg [4:0] cdp2um_rule_usedw;
um um(
clk,
reset,
localbus_cs_n,
localbus_rd_wr,
localbus_data,
localbus_ale,
localbus_ack_n,
localbus_data_out,
um2cdp_path,
cdp2um_data_valid,
cdp2um_data,
um2cdp_tx_enable,
um2cdp_data_valid,
um2cdp_data,
cdp2um_tx_enable,
um2cdp_rule,
um2cdp_rule_wrreq,
cdp2um_rule_usedw
);
integer i;
reg [138:0] pkt[9:0];
initial begin
pkt[0] = {3'b101,8'b0,48'h1111_2222_3333,48'h4444_5555_6666,16'h0800,16'h4500};
pkt[1] = {3'b100,8'b0,32'h0032_7919,32'h0000_4011,32'h7dfc_c0a8,32'h0000_0000};
pkt[2] = {3'b100,8'b0,32'h0101_0800,32'h4789_0400,32'h0500_6162,32'h6364_6566};
pkt[3] = {3'b100,8'b0,32'h6768_4444,32'h5555_6666,32'h1111_2222,32'h3333_0800};
pkt[4] = {3'b100,8'b0,32'h0032_7919,32'h0000_4011,32'h7dfc_c0a8,32'h0164_c0a8};
pkt[5] = {3'b100,8'b0,32'h0032_7919,32'h0000_4011,32'h7dfc_c0a8,32'h0164_c0a8};
pkt[6] = {3'b110,8'b0,32'h0032_7919,32'h0000_4011,32'h7dfc_c0a8,32'h0164_c0a8};
pkt[7] = {3'b101,8'b0,48'hffff_ffff_ffff,48'h4444_5555_6666,16'h0806,16'h0001};
pkt[8] = {3'b101,8'b0,48'h4444_5555_6666,48'h1111_2222_3333,16'h0806,16'h0001};
pkt[9] = {3'b101,8'b0,48'h4444_5555_6666,48'h1111_2222_3333,16'h0800,16'h0001};
end
initial begin
reset = 1'b1;
clk = 1'b0;
cdp2um_data_valid = 1'b0;
cdp2um_data = 138'b0;
cdp2um_tx_enable = 1'b1;
cdp2um_rule_usedw = 5'd1;
localbus_rd_wr = 1'b1;
localbus_ale = 1'b0;
localbus_cs_n= 1'b1;
localbus_data= 32'b0;
#1 reset = 1'b0;
#1 reset = 1'b1;
forever #1 clk = ~clk;
end
initial begin
#20 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0000;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {22'b0,2'd1,8'h00};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0001;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= 32'h00_0000_00;
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0002;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {8'd1,8'd0,8'd24,1'b0,1'b0,6'b0};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0003;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {8'd4,8'b0,8'd8,1'b1,7'd0};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0004;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {8'd1,24'b0};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0005;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {24'b0,8'd9};
end
#4 begin
localbus_cs_n <= 1'b1;
end
/
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0000;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {22'b0,2'd1,8'h11};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0001;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= 32'h00_0000_01;
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0002;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {8'd2,8'd2,8'd16,1'b0,1'b1,6'b0};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0003;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {8'd5,8'b0,8'd8,1'b1,7'd0};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0004;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {8'd0,24'b0};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0005;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {24'b0,8'd3};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0000;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {22'b0,2'd1,8'h47};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0001;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= 32'h89_0000_02;
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0002;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {8'd9,8'd9,8'd0,1'b1,1'b0,6'b0};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0003;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {8'd4,8'b0,8'd20,1'b1,7'd12};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0004;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {8'd1,24'b0};
end
#4 begin
localbus_cs_n <= 1'b1;
end
#4 begin
localbus_ale <= 1'b1;
localbus_data <= 32'h1400_0005;
localbus_rd_wr<= 1'b0;
end
#4 begin
localbus_ale <= 1'b0;
localbus_cs_n <= 1'b0;
localbus_data <= {24'b0,8'd4};
end
#4 begin
localbus_cs_n <= 1'b1;
end
end
reg [138:0] count;
initial begin
count <= 139'b0;
#300 begin end
for(i=0;i<9;i=i+1) begin
#20 begin
cdp2um_data = pkt[0];
cdp2um_data_valid = 1'b1;
end
#2 cdp2um_data = pkt[1]+count;
#2 cdp2um_data = pkt[2];
#2 cdp2um_data = pkt[3];
#2 cdp2um_data = pkt[4];
#2 cdp2um_data = pkt[5];
#2 cdp2um_data = pkt[6];
#2 cdp2um_data_valid = 1'b0;
#2 count = count + 139'd1;
#20 begin
cdp2um_data = pkt[8];
cdp2um_data_valid = 1'b1;
end
#2 cdp2um_data = pkt[1]+count;
#2 cdp2um_data = pkt[2];
#2 cdp2um_data = pkt[6];
#2 cdp2um_data_valid = 1'b0;
#2 count = count + 139'd1;
#2 begin
cdp2um_data = pkt[0];
cdp2um_data_valid = 1'b1;
end
#2 cdp2um_data = pkt[1]+count;
#2 cdp2um_data = pkt[2];
#2 cdp2um_data = pkt[3];
#2 cdp2um_data = pkt[4];
#2 cdp2um_data = pkt[5];
#2 cdp2um_data = pkt[6];
#2 cdp2um_data_valid = 1'b0;
#2 count = count + 139'd1;
#20 begin
cdp2um_data = pkt[9];
cdp2um_data_valid = 1'b1;
end
#2 cdp2um_data = pkt[1]+count;
#2 cdp2um_data = pkt[2];
#2 cdp2um_data = pkt[3];
#2 cdp2um_data = pkt[4];
#2 cdp2um_data = pkt[5];
#2 cdp2um_data = pkt[6];
#2 cdp2um_data_valid = 1'b0;
end
end
endmodule | 0 |
138,293 | data/full_repos/permissive/83198026/transmit.v | 83,198,026 | transmit.v | v | 163 | 71 | [] | [] | [] | null | line:154: before: "." | null | 1: b"%Error: data/full_repos/permissive/83198026/transmit.v:142: Cannot find file containing module: 'fifo'\nfifo fifo_action(\n^~~~\n ... Looked in:\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/fifo\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/fifo.v\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/fifo.sv\n fifo\n fifo.v\n fifo.sv\n obj_dir/fifo\n obj_dir/fifo.v\n obj_dir/fifo.sv\n%Error: Exiting due to 1 error(s)\n" | 302,132 | module | module transmit(
clk,
reset,
action_valid,
action,
pktIDout_valid,
pktIDout,
um2cdp_rule_wrreq,
um2cdp_rule,
cdp2um_tx_enable,
writeRule_enable
);
input clk;
input reset;
input action_valid;
input [31:0] action;
output reg pktIDout_valid;
output reg [11:0] pktIDout;
output reg um2cdp_rule_wrreq;
output reg [29:0] um2cdp_rule;
input cdp2um_tx_enable;
input writeRule_enable;
reg [3:0] state;
parameter idle = 4'd0,
read_fifo = 4'd1,
wait_trans_1 = 4'd2,
wait_bubble_1 = 4'd3,
wait_bubble_2 = 4'd4,
wait_bubble_3 = 4'd5,
wait_trans_2 = 4'd6,
wait_bubble_1_b = 4'd7,
wait_bubble_2_b = 4'd8,
wait_bubble_3_b = 4'd9,
wait_write_rule = 4'd10;
reg rdreq_action;
wire empty_action;
wire [31:0] q_action;
reg [7:0] pktID_temp;
reg [3:0] rule_temp;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
pktIDout_valid <= 1'b0;
pktIDout <= 12'b0;
um2cdp_rule_wrreq <= 1'b0;
um2cdp_rule <= 30'b0;
state <= idle;
rdreq_action <= 1'b0;
end
else begin
case(state)
idle: begin
pktIDout_valid <= 1'b0;
if((writeRule_enable== 1'b1) && (empty_action == 1'b0)) begin
state <= read_fifo;
rdreq_action <= 1'b1;
end
else state <= idle;
end
read_fifo: begin
rdreq_action <= 1'b0;
if((q_action[3:0]==4'd0)||(q_action[19:16]==4'd1)) begin
state <= idle;
pktIDout_valid<=1'b1;
pktIDout <= {4'd1,q_action[31:24]};
end
else begin
pktID_temp <= q_action[31:24];
um2cdp_rule_wrreq <= 1'b1;
if(q_action[3:0]==4'hf) begin
rule_temp <= 4'd2;
um2cdp_rule <= {26'b0, 4'd1};
state <= wait_trans_2;
end
else begin
um2cdp_rule <= {26'b0,q_action[3:0]};
state <= wait_trans_1;
end
end
end
wait_trans_1: begin
um2cdp_rule_wrreq <= 1'b0;
if(cdp2um_tx_enable==1'b1) begin
pktIDout_valid <= 1'b1;
pktIDout <= {4'd0,pktID_temp};
state <= wait_bubble_1;
end
else state <= wait_trans_1;
end
wait_bubble_1: begin
pktIDout_valid <= 1'b0;
state <= wait_bubble_2;
end
wait_bubble_2: state <= wait_bubble_3;
wait_bubble_3: state <= idle;
wait_trans_2: begin
um2cdp_rule_wrreq <= 1'b0;
if(rule_temp== 4'd0) begin
if(cdp2um_tx_enable==1'b1) begin
pktIDout_valid <= 1'b1;
pktIDout <= {4'd0,pktID_temp};
state <= wait_bubble_1;
end
else state <= wait_trans_2;
end
else begin
if(cdp2um_tx_enable==1'b1) begin
pktIDout_valid <= 1'b1;
pktIDout <= {4'd2,pktID_temp};
state <= wait_bubble_1_b;
end
else state <= wait_trans_2;
end
end
wait_bubble_1_b: begin
pktIDout_valid <= 1'b0;
state <= wait_bubble_2_b;
end
wait_bubble_2_b: state <= wait_bubble_3_b;
wait_bubble_3_b: state <= wait_write_rule;
wait_write_rule: begin
pktIDout_valid <= 1'b0;
if((writeRule_enable== 1'b1) && (empty_action == 1'b0)) begin
state <= wait_trans_2;
rule_temp <= rule_temp << 2'd1;
um2cdp_rule_wrreq <= 1'b1;
um2cdp_rule <= {26'b0,rule_temp};
end
else state <= wait_write_rule;
end
default: state <= idle;
endcase
end
end
fifo fifo_action(
.aclr(!reset),
.clock(clk),
.data(action),
.rdreq(rdreq_action),
.wrreq(action_valid),
.empty(empty_action),
.full(),
.q(q_action),
.usedw()
);
defparam
fifo_action.width = 32,
fifo_action.depth = 4,
fifo_action.words = 16;
endmodule | module transmit(
clk,
reset,
action_valid,
action,
pktIDout_valid,
pktIDout,
um2cdp_rule_wrreq,
um2cdp_rule,
cdp2um_tx_enable,
writeRule_enable
); |
input clk;
input reset;
input action_valid;
input [31:0] action;
output reg pktIDout_valid;
output reg [11:0] pktIDout;
output reg um2cdp_rule_wrreq;
output reg [29:0] um2cdp_rule;
input cdp2um_tx_enable;
input writeRule_enable;
reg [3:0] state;
parameter idle = 4'd0,
read_fifo = 4'd1,
wait_trans_1 = 4'd2,
wait_bubble_1 = 4'd3,
wait_bubble_2 = 4'd4,
wait_bubble_3 = 4'd5,
wait_trans_2 = 4'd6,
wait_bubble_1_b = 4'd7,
wait_bubble_2_b = 4'd8,
wait_bubble_3_b = 4'd9,
wait_write_rule = 4'd10;
reg rdreq_action;
wire empty_action;
wire [31:0] q_action;
reg [7:0] pktID_temp;
reg [3:0] rule_temp;
always @ (posedge clk or negedge reset) begin
if(!reset) begin
pktIDout_valid <= 1'b0;
pktIDout <= 12'b0;
um2cdp_rule_wrreq <= 1'b0;
um2cdp_rule <= 30'b0;
state <= idle;
rdreq_action <= 1'b0;
end
else begin
case(state)
idle: begin
pktIDout_valid <= 1'b0;
if((writeRule_enable== 1'b1) && (empty_action == 1'b0)) begin
state <= read_fifo;
rdreq_action <= 1'b1;
end
else state <= idle;
end
read_fifo: begin
rdreq_action <= 1'b0;
if((q_action[3:0]==4'd0)||(q_action[19:16]==4'd1)) begin
state <= idle;
pktIDout_valid<=1'b1;
pktIDout <= {4'd1,q_action[31:24]};
end
else begin
pktID_temp <= q_action[31:24];
um2cdp_rule_wrreq <= 1'b1;
if(q_action[3:0]==4'hf) begin
rule_temp <= 4'd2;
um2cdp_rule <= {26'b0, 4'd1};
state <= wait_trans_2;
end
else begin
um2cdp_rule <= {26'b0,q_action[3:0]};
state <= wait_trans_1;
end
end
end
wait_trans_1: begin
um2cdp_rule_wrreq <= 1'b0;
if(cdp2um_tx_enable==1'b1) begin
pktIDout_valid <= 1'b1;
pktIDout <= {4'd0,pktID_temp};
state <= wait_bubble_1;
end
else state <= wait_trans_1;
end
wait_bubble_1: begin
pktIDout_valid <= 1'b0;
state <= wait_bubble_2;
end
wait_bubble_2: state <= wait_bubble_3;
wait_bubble_3: state <= idle;
wait_trans_2: begin
um2cdp_rule_wrreq <= 1'b0;
if(rule_temp== 4'd0) begin
if(cdp2um_tx_enable==1'b1) begin
pktIDout_valid <= 1'b1;
pktIDout <= {4'd0,pktID_temp};
state <= wait_bubble_1;
end
else state <= wait_trans_2;
end
else begin
if(cdp2um_tx_enable==1'b1) begin
pktIDout_valid <= 1'b1;
pktIDout <= {4'd2,pktID_temp};
state <= wait_bubble_1_b;
end
else state <= wait_trans_2;
end
end
wait_bubble_1_b: begin
pktIDout_valid <= 1'b0;
state <= wait_bubble_2_b;
end
wait_bubble_2_b: state <= wait_bubble_3_b;
wait_bubble_3_b: state <= wait_write_rule;
wait_write_rule: begin
pktIDout_valid <= 1'b0;
if((writeRule_enable== 1'b1) && (empty_action == 1'b0)) begin
state <= wait_trans_2;
rule_temp <= rule_temp << 2'd1;
um2cdp_rule_wrreq <= 1'b1;
um2cdp_rule <= {26'b0,rule_temp};
end
else state <= wait_write_rule;
end
default: state <= idle;
endcase
end
end
fifo fifo_action(
.aclr(!reset),
.clock(clk),
.data(action),
.rdreq(rdreq_action),
.wrreq(action_valid),
.empty(empty_action),
.full(),
.q(q_action),
.usedw()
);
defparam
fifo_action.width = 32,
fifo_action.depth = 4,
fifo_action.words = 16;
endmodule | 0 |
138,294 | data/full_repos/permissive/83198026/um.v | 83,198,026 | um.v | v | 214 | 113 | [] | [] | [] | [(10, 214)] | null | null | 1: b'%Error: data/full_repos/permissive/83198026/um.v:71: Cannot find file containing module: \'parser\'\nparser parser(\n^~~~~~\n ... Looked in:\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/parser\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/parser.v\n data/full_repos/permissive/83198026,data/full_repos/permissive/83198026/parser.sv\n parser\n parser.v\n parser.sv\n obj_dir/parser\n obj_dir/parser.v\n obj_dir/parser.sv\n%Error: data/full_repos/permissive/83198026/um.v:93: Cannot find file containing module: \'lookup\'\nlookup lookup(\n^~~~~~\n%Error: data/full_repos/permissive/83198026/um.v:109: Cannot find file containing module: \'transmit\'\ntransmit transmit(\n^~~~~~~~\n%Error: data/full_repos/permissive/83198026/um.v:122: Cannot find file containing module: \'pktBuffer\'\npktBuffer pktBuffer(\n^~~~~~~~~\n%Error: data/full_repos/permissive/83198026/um.v:144: Cannot find file containing module: \'localbus_manage\'\nlocalbus_manage localbus_manage(\n^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/83198026/um.v:204: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'h0\' generates 31 bits.\n : ... In instance um\n count_time <= 31\'b0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 5 error(s), 1 warning(s)\n' | 302,133 | module | module um(
clk,
reset,
localbus_cs_n,
localbus_rd_wr,
localbus_data,
localbus_ale,
localbus_ack_n,
localbus_data_out,
um2cdp_path,
cdp2um_data_valid,
cdp2um_data,
um2cdp_tx_enable,
um2cdp_data_valid,
um2cdp_data,
cdp2um_tx_enable,
um2cdp_rule,
um2cdp_rule_wrreq,
cdp2um_rule_usedw
);
input clk;
input reset;
input localbus_cs_n;
input localbus_rd_wr;
input [31:0] localbus_data;
input localbus_ale;
output wire localbus_ack_n;
output wire [31:0] localbus_data_out;
output reg um2cdp_path;
input cdp2um_data_valid;
input [138:0] cdp2um_data;
output reg um2cdp_tx_enable;
output wire um2cdp_data_valid;
output wire[138:0] um2cdp_data;
input cdp2um_tx_enable;
output wire um2cdp_rule_wrreq;
output wire[29:0] um2cdp_rule;
input [4:0] cdp2um_rule_usedw;
wire [7:0] headerData_valid;
wire [255:0] headerData;
wire [7:0] headerData_finish_valid;
wire [63:0] pktID;
wire headerVector_valid;
wire [199:0] headerVector;
wire parserRuleSet_valid;
wire [169:0] parserRuleSet;
wire result_valid;
wire [119:0] result;
wire headerIn_enable;
wire [7:0] bid_bitmap;
parser parser(
.clk(clk),
.reset(reset),
.headerData_valid(headerData_valid),
.headerData(headerData),
.headerData_finish_valid(headerData_finish_valid),
.pktID(pktID),
.headerVector_valid(headerVector_valid),
.headerVector(headerVector),
.ruleSet_valid(parserRuleSet_valid),
.ruleSet(parserRuleSet),
.result_valid(result_valid),
.result(result),
.bid_bitmap(bid_bitmap)
);
wire action_valid;
wire [31:0] action;
wire lookupRuleSet_valid;
wire [63:0] lookupRuleSet;
lookup lookup(
.clk(clk),
.reset(reset),
.headerVector_valid(headerVector_valid),
.headerVector(headerVector),
.action_valid(action_valid),
.action(action),
.ruleSet_valid(lookupRuleSet_valid),
.ruleSet(lookupRuleSet)
);
wire pktID2pb_valid;
wire [11:0] pktID2pb;
wire writeRule_enable;
transmit transmit(
.clk(clk),
.reset(reset),
.action_valid(action_valid),
.action(action),
.pktIDout_valid(pktID2pb_valid),
.pktIDout(pktID2pb),
.um2cdp_rule_wrreq(um2cdp_rule_wrreq),
.um2cdp_rule(um2cdp_rule),
.cdp2um_tx_enable(cdp2um_tx_enable),
.writeRule_enable(writeRule_enable)
);
pktBuffer pktBuffer(
.clk(clk),
.reset(reset),
.pktID_in_valid(pktID2pb_valid),
.pktID_in(pktID2pb),
.cdp2um_data_valid(cdp2um_data_valid),
.cdp2um_data(cdp2um_data),
.um2cdp_data_valid(um2cdp_data_valid),
.um2cdp_data(um2cdp_data),
.headerData_valid(headerData_valid),
.headerData(headerData),
.headerData_finish_valid(headerData_finish_valid),
.pktID_out(pktID),
.bid_bitmap(bid_bitmap),
.headerIn_enable(headerIn_enable),
.cdp2um_rule_usedw(cdp2um_rule_usedw),
.writeRule_enable(writeRule_enable)
);
localbus_manage localbus_manage(
.clk(clk),
.reset(reset),
.localbus_cs_n(localbus_cs_n),
.localbus_rd_wr(localbus_rd_wr),
.localbus_data(localbus_data),
.localbus_ale(localbus_ale),
.localbus_ack_n(localbus_ack_n),
.localbus_data_out(localbus_data_out),
.parserRuleSet_valid(parserRuleSet_valid),
.parserRuleSet(parserRuleSet),
.result_valid(result_valid),
.result(result),
.lookupRuleSet_valid(lookupRuleSet_valid),
.lookupRuleSet(lookupRuleSet)
);
reg state;
always @(posedge clk or negedge reset) begin
if(!reset) begin
um2cdp_path <= 1'b0;
state <= 1'b0;
um2cdp_tx_enable <= 1'b0;
end
else begin
case(state)
1'b0: begin
if((cdp2um_data_valid == 1'b0) && (bid_bitmap == 8'hff)) begin
state <= 1'b1;
um2cdp_tx_enable <= 1'b1;
end
else begin
state <= 1'b0;
um2cdp_tx_enable <= 1'b0;
end
end
1'b1: begin
if((cdp2um_data_valid == 1'b1) || (bid_bitmap != 8'hff)) begin
state <= 1'b0;
um2cdp_tx_enable <= 1'b0;
end
else begin
state <= 1'b1;
um2cdp_tx_enable <= 1'b1;
end
end
default: state <= 1'b0;
endcase
end
end
reg [31:0] count_time;
always @(posedge clk or negedge reset) begin
if(!reset) begin
count_time <= 31'b0;
end
else begin
count_time <= count_time + 32'd1;
end
end
endmodule | module um(
clk,
reset,
localbus_cs_n,
localbus_rd_wr,
localbus_data,
localbus_ale,
localbus_ack_n,
localbus_data_out,
um2cdp_path,
cdp2um_data_valid,
cdp2um_data,
um2cdp_tx_enable,
um2cdp_data_valid,
um2cdp_data,
cdp2um_tx_enable,
um2cdp_rule,
um2cdp_rule_wrreq,
cdp2um_rule_usedw
); |
input clk;
input reset;
input localbus_cs_n;
input localbus_rd_wr;
input [31:0] localbus_data;
input localbus_ale;
output wire localbus_ack_n;
output wire [31:0] localbus_data_out;
output reg um2cdp_path;
input cdp2um_data_valid;
input [138:0] cdp2um_data;
output reg um2cdp_tx_enable;
output wire um2cdp_data_valid;
output wire[138:0] um2cdp_data;
input cdp2um_tx_enable;
output wire um2cdp_rule_wrreq;
output wire[29:0] um2cdp_rule;
input [4:0] cdp2um_rule_usedw;
wire [7:0] headerData_valid;
wire [255:0] headerData;
wire [7:0] headerData_finish_valid;
wire [63:0] pktID;
wire headerVector_valid;
wire [199:0] headerVector;
wire parserRuleSet_valid;
wire [169:0] parserRuleSet;
wire result_valid;
wire [119:0] result;
wire headerIn_enable;
wire [7:0] bid_bitmap;
parser parser(
.clk(clk),
.reset(reset),
.headerData_valid(headerData_valid),
.headerData(headerData),
.headerData_finish_valid(headerData_finish_valid),
.pktID(pktID),
.headerVector_valid(headerVector_valid),
.headerVector(headerVector),
.ruleSet_valid(parserRuleSet_valid),
.ruleSet(parserRuleSet),
.result_valid(result_valid),
.result(result),
.bid_bitmap(bid_bitmap)
);
wire action_valid;
wire [31:0] action;
wire lookupRuleSet_valid;
wire [63:0] lookupRuleSet;
lookup lookup(
.clk(clk),
.reset(reset),
.headerVector_valid(headerVector_valid),
.headerVector(headerVector),
.action_valid(action_valid),
.action(action),
.ruleSet_valid(lookupRuleSet_valid),
.ruleSet(lookupRuleSet)
);
wire pktID2pb_valid;
wire [11:0] pktID2pb;
wire writeRule_enable;
transmit transmit(
.clk(clk),
.reset(reset),
.action_valid(action_valid),
.action(action),
.pktIDout_valid(pktID2pb_valid),
.pktIDout(pktID2pb),
.um2cdp_rule_wrreq(um2cdp_rule_wrreq),
.um2cdp_rule(um2cdp_rule),
.cdp2um_tx_enable(cdp2um_tx_enable),
.writeRule_enable(writeRule_enable)
);
pktBuffer pktBuffer(
.clk(clk),
.reset(reset),
.pktID_in_valid(pktID2pb_valid),
.pktID_in(pktID2pb),
.cdp2um_data_valid(cdp2um_data_valid),
.cdp2um_data(cdp2um_data),
.um2cdp_data_valid(um2cdp_data_valid),
.um2cdp_data(um2cdp_data),
.headerData_valid(headerData_valid),
.headerData(headerData),
.headerData_finish_valid(headerData_finish_valid),
.pktID_out(pktID),
.bid_bitmap(bid_bitmap),
.headerIn_enable(headerIn_enable),
.cdp2um_rule_usedw(cdp2um_rule_usedw),
.writeRule_enable(writeRule_enable)
);
localbus_manage localbus_manage(
.clk(clk),
.reset(reset),
.localbus_cs_n(localbus_cs_n),
.localbus_rd_wr(localbus_rd_wr),
.localbus_data(localbus_data),
.localbus_ale(localbus_ale),
.localbus_ack_n(localbus_ack_n),
.localbus_data_out(localbus_data_out),
.parserRuleSet_valid(parserRuleSet_valid),
.parserRuleSet(parserRuleSet),
.result_valid(result_valid),
.result(result),
.lookupRuleSet_valid(lookupRuleSet_valid),
.lookupRuleSet(lookupRuleSet)
);
reg state;
always @(posedge clk or negedge reset) begin
if(!reset) begin
um2cdp_path <= 1'b0;
state <= 1'b0;
um2cdp_tx_enable <= 1'b0;
end
else begin
case(state)
1'b0: begin
if((cdp2um_data_valid == 1'b0) && (bid_bitmap == 8'hff)) begin
state <= 1'b1;
um2cdp_tx_enable <= 1'b1;
end
else begin
state <= 1'b0;
um2cdp_tx_enable <= 1'b0;
end
end
1'b1: begin
if((cdp2um_data_valid == 1'b1) || (bid_bitmap != 8'hff)) begin
state <= 1'b0;
um2cdp_tx_enable <= 1'b0;
end
else begin
state <= 1'b1;
um2cdp_tx_enable <= 1'b1;
end
end
default: state <= 1'b0;
endcase
end
end
reg [31:0] count_time;
always @(posedge clk or negedge reset) begin
if(!reset) begin
count_time <= 31'b0;
end
else begin
count_time <= count_time + 32'd1;
end
end
endmodule | 0 |
138,295 | data/full_repos/permissive/83270534/adi/rtl/adi_top.v | 83,270,534 | adi_top.v | v | 199 | 121 | [] | [] | [] | [(7, 198)] | null | null | 1: b"%Error: data/full_repos/permissive/83270534/adi/rtl/adi_top.v:98: Cannot find file containing module: 'WB_MASTER'\n WB_MASTER wb_master\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/adi/rtl,data/full_repos/permissive/83270534/WB_MASTER\n data/full_repos/permissive/83270534/adi/rtl,data/full_repos/permissive/83270534/WB_MASTER.v\n data/full_repos/permissive/83270534/adi/rtl,data/full_repos/permissive/83270534/WB_MASTER.sv\n WB_MASTER\n WB_MASTER.v\n WB_MASTER.sv\n obj_dir/WB_MASTER\n obj_dir/WB_MASTER.v\n obj_dir/WB_MASTER.sv\n%Error: data/full_repos/permissive/83270534/adi/rtl/adi_top.v:138: Cannot find file containing module: 'EPP_BUS_BRIDGE'\n EPP_BUS_BRIDGE epp_bus_bridge\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/rtl/adi_top.v:168: Cannot find file containing module: 'EPP_SLAVE'\n EPP_SLAVE epp_slave\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 302,134 | module | module ADI_TOP
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
inout [ 7:0] EPP_DATA_INOUT ,
input EPP_WRITE_IN ,
input EPP_ASTB_IN ,
input EPP_DSTB_IN ,
output EPP_WAIT_OUT ,
output EPP_INT_OUT ,
input EPP_RESET_IN ,
output WB_ARB_REQ_OUT ,
input WB_ARB_GNT_IN ,
output [31:0] WB_ADR_OUT ,
output WB_CYC_OUT ,
output WB_STB_OUT ,
output WB_WE_OUT ,
output [ 3:0] WB_SEL_OUT ,
input WB_STALL_IN ,
input WB_ACK_IN ,
input WB_ERR_IN ,
input [31:0] WB_RD_DAT_IN ,
output [31:0] WB_WR_DAT_OUT
);
wire WbCyc ;
wire WbStb ;
wire [31:0] WbAdr ;
wire [ 3:0] WbSel ;
wire WbWe ;
wire WbStall ;
wire WbAck ;
wire [31:0] WbDatWr ;
wire [31:0] WbDatRd ;
wire [31:0] BusAddr ;
wire BusReq ;
wire BusReadAck ;
wire BusWriteAck ;
wire BusAck = BusWriteAck | BusReadAck;
wire BusRwb ;
wire [ 1:0] BusSize ;
wire [31:0] BusWriteData ;
wire [31:0] BusReadData ;
wire RegsWriteReq ;
wire RegsReadReq ;
wire RegsAddrSel ;
wire RegsDataSel ;
wire RegsReadAck ;
wire RegsWriteAck ;
wire [7:0] RegsReadData ;
wire [7:0] RegsWriteData ;
wire [ 7:0] EppData ;
wire EppWrite ;
wire EppAstb ;
wire EppDstb ;
wire EppWait ;
wire EppInt ;
wire EppReset ;
WB_MASTER wb_master
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (1'b0 ),
.RST_ASYNC (RST_ASYNC ),
.WB_ARB_REQ_OUT (WB_ARB_REQ_OUT ),
.WB_ARB_GNT_IN (WB_ARB_GNT_IN ),
.WB_ADR_OUT (WB_ADR_OUT ),
.WB_CYC_OUT (WB_CYC_OUT ),
.WB_STB_OUT (WB_STB_OUT ),
.WB_WE_OUT (WB_WE_OUT ),
.WB_SEL_OUT (WB_SEL_OUT ),
.WB_STALL_IN (WB_STALL_IN ),
.WB_ACK_IN (WB_ACK_IN ),
.WB_ERR_IN (WB_ERR_IN ),
.WB_RD_DAT_IN (WB_RD_DAT_IN ),
.WB_WR_DAT_OUT (WB_WR_DAT_OUT ),
.BUS_START_ADDR_IN (BusAddr ),
.BUS_READ_REQ_IN (BusReq & BusRwb ),
.BUS_READ_ACK_OUT (BusReadAck ),
.BUS_WRITE_REQ_IN (BusReq & ~BusRwb ),
.BUS_WRITE_ACK_OUT (BusWriteAck ),
.BUS_SIZE_IN (BusSize ),
.BUS_LEN_IN (5'd1 ),
.BUS_BURST_ADDR_INC_IN (1'b0 ),
.BUS_READ_DATA_OUT (BusReadData ),
.BUS_WRITE_DATA_IN (BusWriteData )
);
EPP_BUS_BRIDGE epp_bus_bridge
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (1'b0 ),
.RST_ASYNC (RST_ASYNC ),
.REGS_WRITE_REQ_IN (RegsWriteReq ),
.REGS_READ_REQ_IN (RegsReadReq ),
.REGS_ADDR_SEL_IN (RegsAddrSel ),
.REGS_DATA_SEL_IN (RegsDataSel ),
.REGS_READ_ACK_OUT (RegsReadAck ),
.REGS_WRITE_ACK_OUT (RegsWriteAck ),
.REGS_READ_DATA_OUT (RegsReadData ),
.REGS_WRITE_DATA_IN (RegsWriteData ),
.BUS_ADDR_OUT (BusAddr ),
.BUS_REQ_OUT (BusReq ),
.BUS_ACK_IN (BusAck ),
.BUS_RWB_OUT (BusRwb ),
.BUS_SIZE_OUT (BusSize ),
.BUS_WRITE_DATA_OUT (BusWriteData ),
.BUS_READ_DATA_IN (BusReadData )
);
EPP_SLAVE epp_slave
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (1'b0 ),
.RST_ASYNC (RST_ASYNC ),
.REGS_WRITE_REQ_OUT (RegsWriteReq ),
.REGS_READ_REQ_OUT (RegsReadReq ),
.REGS_ADDR_SEL_OUT (RegsAddrSel ),
.REGS_DATA_SEL_OUT (RegsDataSel ),
.REGS_READ_ACK_IN (RegsReadAck ),
.REGS_WRITE_ACK_IN (RegsWriteAck ),
.REGS_READ_DATA_IN (RegsReadData ),
.REGS_WRITE_DATA_OUT (RegsWriteData ),
.EPP_DATA_INOUT (EPP_DATA_INOUT ),
.EPP_WRITE_IN (EPP_WRITE_IN ),
.EPP_ASTB_IN (EPP_ASTB_IN ),
.EPP_DSTB_IN (EPP_DSTB_IN ),
.EPP_WAIT_OUT (EPP_WAIT_OUT ),
.EPP_INT_OUT (EPP_INT_OUT ),
.EPP_RESET_IN (EPP_RESET_IN )
);
endmodule | module ADI_TOP
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
inout [ 7:0] EPP_DATA_INOUT ,
input EPP_WRITE_IN ,
input EPP_ASTB_IN ,
input EPP_DSTB_IN ,
output EPP_WAIT_OUT ,
output EPP_INT_OUT ,
input EPP_RESET_IN ,
output WB_ARB_REQ_OUT ,
input WB_ARB_GNT_IN ,
output [31:0] WB_ADR_OUT ,
output WB_CYC_OUT ,
output WB_STB_OUT ,
output WB_WE_OUT ,
output [ 3:0] WB_SEL_OUT ,
input WB_STALL_IN ,
input WB_ACK_IN ,
input WB_ERR_IN ,
input [31:0] WB_RD_DAT_IN ,
output [31:0] WB_WR_DAT_OUT
); |
wire WbCyc ;
wire WbStb ;
wire [31:0] WbAdr ;
wire [ 3:0] WbSel ;
wire WbWe ;
wire WbStall ;
wire WbAck ;
wire [31:0] WbDatWr ;
wire [31:0] WbDatRd ;
wire [31:0] BusAddr ;
wire BusReq ;
wire BusReadAck ;
wire BusWriteAck ;
wire BusAck = BusWriteAck | BusReadAck;
wire BusRwb ;
wire [ 1:0] BusSize ;
wire [31:0] BusWriteData ;
wire [31:0] BusReadData ;
wire RegsWriteReq ;
wire RegsReadReq ;
wire RegsAddrSel ;
wire RegsDataSel ;
wire RegsReadAck ;
wire RegsWriteAck ;
wire [7:0] RegsReadData ;
wire [7:0] RegsWriteData ;
wire [ 7:0] EppData ;
wire EppWrite ;
wire EppAstb ;
wire EppDstb ;
wire EppWait ;
wire EppInt ;
wire EppReset ;
WB_MASTER wb_master
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (1'b0 ),
.RST_ASYNC (RST_ASYNC ),
.WB_ARB_REQ_OUT (WB_ARB_REQ_OUT ),
.WB_ARB_GNT_IN (WB_ARB_GNT_IN ),
.WB_ADR_OUT (WB_ADR_OUT ),
.WB_CYC_OUT (WB_CYC_OUT ),
.WB_STB_OUT (WB_STB_OUT ),
.WB_WE_OUT (WB_WE_OUT ),
.WB_SEL_OUT (WB_SEL_OUT ),
.WB_STALL_IN (WB_STALL_IN ),
.WB_ACK_IN (WB_ACK_IN ),
.WB_ERR_IN (WB_ERR_IN ),
.WB_RD_DAT_IN (WB_RD_DAT_IN ),
.WB_WR_DAT_OUT (WB_WR_DAT_OUT ),
.BUS_START_ADDR_IN (BusAddr ),
.BUS_READ_REQ_IN (BusReq & BusRwb ),
.BUS_READ_ACK_OUT (BusReadAck ),
.BUS_WRITE_REQ_IN (BusReq & ~BusRwb ),
.BUS_WRITE_ACK_OUT (BusWriteAck ),
.BUS_SIZE_IN (BusSize ),
.BUS_LEN_IN (5'd1 ),
.BUS_BURST_ADDR_INC_IN (1'b0 ),
.BUS_READ_DATA_OUT (BusReadData ),
.BUS_WRITE_DATA_IN (BusWriteData )
);
EPP_BUS_BRIDGE epp_bus_bridge
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (1'b0 ),
.RST_ASYNC (RST_ASYNC ),
.REGS_WRITE_REQ_IN (RegsWriteReq ),
.REGS_READ_REQ_IN (RegsReadReq ),
.REGS_ADDR_SEL_IN (RegsAddrSel ),
.REGS_DATA_SEL_IN (RegsDataSel ),
.REGS_READ_ACK_OUT (RegsReadAck ),
.REGS_WRITE_ACK_OUT (RegsWriteAck ),
.REGS_READ_DATA_OUT (RegsReadData ),
.REGS_WRITE_DATA_IN (RegsWriteData ),
.BUS_ADDR_OUT (BusAddr ),
.BUS_REQ_OUT (BusReq ),
.BUS_ACK_IN (BusAck ),
.BUS_RWB_OUT (BusRwb ),
.BUS_SIZE_OUT (BusSize ),
.BUS_WRITE_DATA_OUT (BusWriteData ),
.BUS_READ_DATA_IN (BusReadData )
);
EPP_SLAVE epp_slave
(
.CLK (CLK ),
.EN (EN ),
.RST_SYNC (1'b0 ),
.RST_ASYNC (RST_ASYNC ),
.REGS_WRITE_REQ_OUT (RegsWriteReq ),
.REGS_READ_REQ_OUT (RegsReadReq ),
.REGS_ADDR_SEL_OUT (RegsAddrSel ),
.REGS_DATA_SEL_OUT (RegsDataSel ),
.REGS_READ_ACK_IN (RegsReadAck ),
.REGS_WRITE_ACK_IN (RegsWriteAck ),
.REGS_READ_DATA_IN (RegsReadData ),
.REGS_WRITE_DATA_OUT (RegsWriteData ),
.EPP_DATA_INOUT (EPP_DATA_INOUT ),
.EPP_WRITE_IN (EPP_WRITE_IN ),
.EPP_ASTB_IN (EPP_ASTB_IN ),
.EPP_DSTB_IN (EPP_DSTB_IN ),
.EPP_WAIT_OUT (EPP_WAIT_OUT ),
.EPP_INT_OUT (EPP_INT_OUT ),
.EPP_RESET_IN (EPP_RESET_IN )
);
endmodule | 1 |
138,296 | data/full_repos/permissive/83270534/adi/rtl/epp_bus_bridge.v | 83,270,534 | epp_bus_bridge.v | v | 341 | 125 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/adi/rtl/epp_bus_bridge.v:38: Cannot find include file: epp_bus_bridge_defs.v\n`include "epp_bus_bridge_defs.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/adi/rtl,data/full_repos/permissive/83270534/epp_bus_bridge_defs.v\n data/full_repos/permissive/83270534/adi/rtl,data/full_repos/permissive/83270534/epp_bus_bridge_defs.v.v\n data/full_repos/permissive/83270534/adi/rtl,data/full_repos/permissive/83270534/epp_bus_bridge_defs.v.sv\n epp_bus_bridge_defs.v\n epp_bus_bridge_defs.v.v\n epp_bus_bridge_defs.v.sv\n obj_dir/epp_bus_bridge_defs.v\n obj_dir/epp_bus_bridge_defs.v.v\n obj_dir/epp_bus_bridge_defs.v.sv\n%Error: Exiting due to 1 error(s)\n' | 302,135 | module | module EPP_BUS_BRIDGE
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
input REGS_WRITE_REQ_IN ,
input REGS_READ_REQ_IN ,
input REGS_ADDR_SEL_IN ,
input REGS_DATA_SEL_IN ,
output REGS_READ_ACK_OUT ,
output REGS_WRITE_ACK_OUT ,
output [7:0] REGS_READ_DATA_OUT ,
input [7:0] REGS_WRITE_DATA_IN ,
output [31:0] BUS_ADDR_OUT ,
output BUS_REQ_OUT ,
input BUS_ACK_IN ,
output BUS_RWB_OUT ,
output [ 1:0] BUS_SIZE_OUT ,
output [31:0] BUS_WRITE_DATA_OUT ,
input [31:0] BUS_READ_DATA_IN
);
`include "epp_bus_bridge_defs.v"
reg [ 7:0] EppAddr ;
reg [31:0] BusAddr ;
reg BusReq ;
reg BusStreamReq ;
reg BusRwb ;
reg [ 1:0] BusSize ;
reg [31:0] BusData ;
reg BusStreamRwb ;
wire [1:0] BusStreamSize = ERW_SIZE_BYTE ;
reg [7:0] BusStreamData ;
reg RegsWriteAck ;
reg RegsReadAck ;
reg [7:0] RegsReadData ;
reg [7:0] EppReadData ;
wire EppAddrWriteEn = REGS_ADDR_SEL_IN & REGS_WRITE_REQ_IN & REGS_WRITE_ACK_OUT;
wire EppDataWriteEn = REGS_DATA_SEL_IN & REGS_WRITE_REQ_IN & REGS_WRITE_ACK_OUT;
assign REGS_WRITE_ACK_OUT = RegsWriteAck ;
assign REGS_READ_ACK_OUT = RegsReadAck ;
assign REGS_READ_DATA_OUT = RegsReadData ;
assign BUS_ADDR_OUT = BusAddr ;
assign BUS_REQ_OUT = BusReq | BusStreamReq;
assign BUS_RWB_OUT = BusStreamReq ? BusStreamRwb : BusRwb ;
assign BUS_SIZE_OUT = BusStreamReq ? ERW_SIZE_BYTE : BusSize ;
assign BUS_WRITE_DATA_OUT = BusStreamReq ? BusStreamData : BusData ;
always @(posedge CLK or posedge RST_ASYNC)
begin : EPP_ADDR_REG
if (RST_ASYNC)
begin
EppAddr <= 8'h00;
end
else if (RST_SYNC)
begin
EppAddr <= 8'h00;
end
else if (EN)
begin
if (EppAddrWriteEn)
begin
EppAddr <= REGS_WRITE_DATA_IN;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : BUS_ADDR_REG
if (RST_ASYNC)
begin
BusAddr <= 8'h00;
end
else if (RST_SYNC)
begin
BusAddr <= 8'h00;
end
else if (EN)
begin
if (BusStreamReq && BUS_ACK_IN)
begin
BusAddr <= BusAddr + 32'd1;
end
else if (EppDataWriteEn)
begin
case (EppAddr)
ERW_ADDR0 : BusAddr <= {BusAddr[31:8] , REGS_WRITE_DATA_IN };
ERW_ADDR1 : BusAddr <= {BusAddr[31:16] , REGS_WRITE_DATA_IN, BusAddr[7:0] };
ERW_ADDR2 : BusAddr <= {BusAddr[31:24] , REGS_WRITE_DATA_IN, BusAddr[15:0] };
ERW_ADDR3 : BusAddr <= {REGS_WRITE_DATA_IN , BusAddr[23:0] };
endcase
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : BUS_STREAM_REG
if (RST_ASYNC)
begin
BusStreamReq <= 1'b0;
BusStreamRwb <= 1'b0;
BusStreamData <= 8'h00;
end
else if (RST_SYNC)
begin
BusStreamReq <= 1'b0;
BusStreamRwb <= 1'b0;
BusStreamData <= 8'h00;
end
else if (EN)
begin
if (ERW_STREAM == EppAddr)
begin
if (BusStreamReq && BUS_ACK_IN)
begin
BusStreamReq <= 1'b0;
if (REGS_READ_REQ_IN)
begin
BusStreamData <= BUS_READ_DATA_IN;
end
end
else if (REGS_DATA_SEL_IN && (REGS_READ_REQ_IN || REGS_WRITE_REQ_IN) && !BusStreamReq)
begin
BusStreamReq <= 1'b1;
if (REGS_READ_REQ_IN)
begin
BusStreamRwb <= 1'b1;
end
else if (REGS_WRITE_REQ_IN)
begin
BusStreamRwb <= 1'b0;
BusStreamData <= REGS_WRITE_DATA_IN;
end
end
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : BUS_TRANS_REG
if (RST_ASYNC)
begin
BusReq <= 1'b0;
BusRwb <= 1'b0;
BusSize <= 2'b00;
end
else if (RST_SYNC)
begin
BusReq <= 1'b0;
BusRwb <= 1'b0;
BusSize <= 2'b00;
end
else if (EN)
begin
if (ERW_TRANS == EppAddr)
begin
if (BusReq && BUS_ACK_IN)
begin
BusReq <= 1'b0;
end
else if (REGS_DATA_SEL_IN && REGS_WRITE_REQ_IN && !BusReq)
begin
BusReq <= 1'b1;
BusRwb <= REGS_WRITE_DATA_IN[ERW_TRANS_RWB];
BusSize <= REGS_WRITE_DATA_IN[ERW_TRANS_SIZE_MSB:ERW_TRANS_SIZE_LSB];
end
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : BUS_DATA_REG
if (RST_ASYNC)
begin
BusData <= 32'h0000_0000;
end
else if (RST_SYNC)
begin
BusData <= 32'h0000_0000;
end
else if (EN)
begin
if (BusReq && BusRwb && BUS_ACK_IN)
begin
BusData <= BUS_READ_DATA_IN;
end
else if (EppDataWriteEn)
begin
case (EppAddr)
ERW_DATA0 : BusData <= {BusData[31:8] , REGS_WRITE_DATA_IN };
ERW_DATA1 : BusData <= {BusData[31:16] , REGS_WRITE_DATA_IN, BusData[7:0] };
ERW_DATA2 : BusData <= {BusData[31:24] , REGS_WRITE_DATA_IN, BusData[15:0] };
ERW_DATA3 : BusData <= {REGS_WRITE_DATA_IN , BusData[23:0] };
endcase
end
end
end
always @*
begin : REGS_WRITE_ACK_SEL
RegsWriteAck = 1'b0;
if (REGS_ADDR_SEL_IN)
begin
RegsWriteAck = REGS_WRITE_REQ_IN;
end
else if (REGS_WRITE_REQ_IN)
begin
case (EppAddr)
ERW_TRANS : RegsWriteAck = BusReq & BUS_ACK_IN ;
ERW_STREAM : RegsWriteAck = BusStreamReq & BUS_ACK_IN ;
default : RegsWriteAck = REGS_WRITE_REQ_IN ;
endcase
end
end
always @*
begin : REGS_READ_ACK_SEL
RegsReadAck = 1'b0;
if (ERW_STREAM == EppAddr)
begin
RegsReadAck = BusStreamReq & BUS_ACK_IN;
end
else
begin
RegsReadAck = REGS_READ_REQ_IN;
end
end
always @*
begin : REGS_READ_DATA_SEL
RegsReadData = 8'h00;
if (REGS_ADDR_SEL_IN && REGS_READ_REQ_IN)
begin
RegsReadData = EppAddr;
end
else if (REGS_DATA_SEL_IN && REGS_READ_REQ_IN)
begin
case (EppAddr)
ERW_ADDR0 : RegsReadData = BusAddr[ 7: 0];
ERW_ADDR1 : RegsReadData = BusAddr[15: 8];
ERW_ADDR2 : RegsReadData = BusAddr[23:16];
ERW_ADDR3 : RegsReadData = BusAddr[31:24];
ERW_DATA0 : RegsReadData = BusData[ 7: 0];
ERW_DATA1 : RegsReadData = BusData[15: 8];
ERW_DATA2 : RegsReadData = BusData[23:16];
ERW_DATA3 : RegsReadData = BusData[31:24];
ERW_TRANS : RegsReadData = (8'h00 | BusRwb << ERW_TRANS_RWB | BusSize << ERW_TRANS_SIZE_LSB);
ERW_STATUS : RegsReadData = (8'h00 | BusReq);
ERW_STREAM : RegsReadData = BUS_READ_DATA_IN[7:0];
endcase
end
end
endmodule | module EPP_BUS_BRIDGE
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
input REGS_WRITE_REQ_IN ,
input REGS_READ_REQ_IN ,
input REGS_ADDR_SEL_IN ,
input REGS_DATA_SEL_IN ,
output REGS_READ_ACK_OUT ,
output REGS_WRITE_ACK_OUT ,
output [7:0] REGS_READ_DATA_OUT ,
input [7:0] REGS_WRITE_DATA_IN ,
output [31:0] BUS_ADDR_OUT ,
output BUS_REQ_OUT ,
input BUS_ACK_IN ,
output BUS_RWB_OUT ,
output [ 1:0] BUS_SIZE_OUT ,
output [31:0] BUS_WRITE_DATA_OUT ,
input [31:0] BUS_READ_DATA_IN
); |
`include "epp_bus_bridge_defs.v"
reg [ 7:0] EppAddr ;
reg [31:0] BusAddr ;
reg BusReq ;
reg BusStreamReq ;
reg BusRwb ;
reg [ 1:0] BusSize ;
reg [31:0] BusData ;
reg BusStreamRwb ;
wire [1:0] BusStreamSize = ERW_SIZE_BYTE ;
reg [7:0] BusStreamData ;
reg RegsWriteAck ;
reg RegsReadAck ;
reg [7:0] RegsReadData ;
reg [7:0] EppReadData ;
wire EppAddrWriteEn = REGS_ADDR_SEL_IN & REGS_WRITE_REQ_IN & REGS_WRITE_ACK_OUT;
wire EppDataWriteEn = REGS_DATA_SEL_IN & REGS_WRITE_REQ_IN & REGS_WRITE_ACK_OUT;
assign REGS_WRITE_ACK_OUT = RegsWriteAck ;
assign REGS_READ_ACK_OUT = RegsReadAck ;
assign REGS_READ_DATA_OUT = RegsReadData ;
assign BUS_ADDR_OUT = BusAddr ;
assign BUS_REQ_OUT = BusReq | BusStreamReq;
assign BUS_RWB_OUT = BusStreamReq ? BusStreamRwb : BusRwb ;
assign BUS_SIZE_OUT = BusStreamReq ? ERW_SIZE_BYTE : BusSize ;
assign BUS_WRITE_DATA_OUT = BusStreamReq ? BusStreamData : BusData ;
always @(posedge CLK or posedge RST_ASYNC)
begin : EPP_ADDR_REG
if (RST_ASYNC)
begin
EppAddr <= 8'h00;
end
else if (RST_SYNC)
begin
EppAddr <= 8'h00;
end
else if (EN)
begin
if (EppAddrWriteEn)
begin
EppAddr <= REGS_WRITE_DATA_IN;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : BUS_ADDR_REG
if (RST_ASYNC)
begin
BusAddr <= 8'h00;
end
else if (RST_SYNC)
begin
BusAddr <= 8'h00;
end
else if (EN)
begin
if (BusStreamReq && BUS_ACK_IN)
begin
BusAddr <= BusAddr + 32'd1;
end
else if (EppDataWriteEn)
begin
case (EppAddr)
ERW_ADDR0 : BusAddr <= {BusAddr[31:8] , REGS_WRITE_DATA_IN };
ERW_ADDR1 : BusAddr <= {BusAddr[31:16] , REGS_WRITE_DATA_IN, BusAddr[7:0] };
ERW_ADDR2 : BusAddr <= {BusAddr[31:24] , REGS_WRITE_DATA_IN, BusAddr[15:0] };
ERW_ADDR3 : BusAddr <= {REGS_WRITE_DATA_IN , BusAddr[23:0] };
endcase
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : BUS_STREAM_REG
if (RST_ASYNC)
begin
BusStreamReq <= 1'b0;
BusStreamRwb <= 1'b0;
BusStreamData <= 8'h00;
end
else if (RST_SYNC)
begin
BusStreamReq <= 1'b0;
BusStreamRwb <= 1'b0;
BusStreamData <= 8'h00;
end
else if (EN)
begin
if (ERW_STREAM == EppAddr)
begin
if (BusStreamReq && BUS_ACK_IN)
begin
BusStreamReq <= 1'b0;
if (REGS_READ_REQ_IN)
begin
BusStreamData <= BUS_READ_DATA_IN;
end
end
else if (REGS_DATA_SEL_IN && (REGS_READ_REQ_IN || REGS_WRITE_REQ_IN) && !BusStreamReq)
begin
BusStreamReq <= 1'b1;
if (REGS_READ_REQ_IN)
begin
BusStreamRwb <= 1'b1;
end
else if (REGS_WRITE_REQ_IN)
begin
BusStreamRwb <= 1'b0;
BusStreamData <= REGS_WRITE_DATA_IN;
end
end
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : BUS_TRANS_REG
if (RST_ASYNC)
begin
BusReq <= 1'b0;
BusRwb <= 1'b0;
BusSize <= 2'b00;
end
else if (RST_SYNC)
begin
BusReq <= 1'b0;
BusRwb <= 1'b0;
BusSize <= 2'b00;
end
else if (EN)
begin
if (ERW_TRANS == EppAddr)
begin
if (BusReq && BUS_ACK_IN)
begin
BusReq <= 1'b0;
end
else if (REGS_DATA_SEL_IN && REGS_WRITE_REQ_IN && !BusReq)
begin
BusReq <= 1'b1;
BusRwb <= REGS_WRITE_DATA_IN[ERW_TRANS_RWB];
BusSize <= REGS_WRITE_DATA_IN[ERW_TRANS_SIZE_MSB:ERW_TRANS_SIZE_LSB];
end
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : BUS_DATA_REG
if (RST_ASYNC)
begin
BusData <= 32'h0000_0000;
end
else if (RST_SYNC)
begin
BusData <= 32'h0000_0000;
end
else if (EN)
begin
if (BusReq && BusRwb && BUS_ACK_IN)
begin
BusData <= BUS_READ_DATA_IN;
end
else if (EppDataWriteEn)
begin
case (EppAddr)
ERW_DATA0 : BusData <= {BusData[31:8] , REGS_WRITE_DATA_IN };
ERW_DATA1 : BusData <= {BusData[31:16] , REGS_WRITE_DATA_IN, BusData[7:0] };
ERW_DATA2 : BusData <= {BusData[31:24] , REGS_WRITE_DATA_IN, BusData[15:0] };
ERW_DATA3 : BusData <= {REGS_WRITE_DATA_IN , BusData[23:0] };
endcase
end
end
end
always @*
begin : REGS_WRITE_ACK_SEL
RegsWriteAck = 1'b0;
if (REGS_ADDR_SEL_IN)
begin
RegsWriteAck = REGS_WRITE_REQ_IN;
end
else if (REGS_WRITE_REQ_IN)
begin
case (EppAddr)
ERW_TRANS : RegsWriteAck = BusReq & BUS_ACK_IN ;
ERW_STREAM : RegsWriteAck = BusStreamReq & BUS_ACK_IN ;
default : RegsWriteAck = REGS_WRITE_REQ_IN ;
endcase
end
end
always @*
begin : REGS_READ_ACK_SEL
RegsReadAck = 1'b0;
if (ERW_STREAM == EppAddr)
begin
RegsReadAck = BusStreamReq & BUS_ACK_IN;
end
else
begin
RegsReadAck = REGS_READ_REQ_IN;
end
end
always @*
begin : REGS_READ_DATA_SEL
RegsReadData = 8'h00;
if (REGS_ADDR_SEL_IN && REGS_READ_REQ_IN)
begin
RegsReadData = EppAddr;
end
else if (REGS_DATA_SEL_IN && REGS_READ_REQ_IN)
begin
case (EppAddr)
ERW_ADDR0 : RegsReadData = BusAddr[ 7: 0];
ERW_ADDR1 : RegsReadData = BusAddr[15: 8];
ERW_ADDR2 : RegsReadData = BusAddr[23:16];
ERW_ADDR3 : RegsReadData = BusAddr[31:24];
ERW_DATA0 : RegsReadData = BusData[ 7: 0];
ERW_DATA1 : RegsReadData = BusData[15: 8];
ERW_DATA2 : RegsReadData = BusData[23:16];
ERW_DATA3 : RegsReadData = BusData[31:24];
ERW_TRANS : RegsReadData = (8'h00 | BusRwb << ERW_TRANS_RWB | BusSize << ERW_TRANS_SIZE_LSB);
ERW_STATUS : RegsReadData = (8'h00 | BusReq);
ERW_STREAM : RegsReadData = BUS_READ_DATA_IN[7:0];
endcase
end
end
endmodule | 1 |
138,297 | data/full_repos/permissive/83270534/adi/rtl/epp_slave.v | 83,270,534 | epp_slave.v | v | 338 | 121 | [] | [] | [] | [(21, 337)] | null | data/verilator_xmls/615274e7-6c06-4481-89ac-8bf14e2d4965.xml | null | 302,136 | module | module EPP_SLAVE
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
output REGS_WRITE_REQ_OUT ,
output REGS_READ_REQ_OUT ,
output REGS_ADDR_SEL_OUT ,
output REGS_DATA_SEL_OUT ,
input REGS_READ_ACK_IN ,
input REGS_WRITE_ACK_IN ,
input [7:0] REGS_READ_DATA_IN ,
output [7:0] REGS_WRITE_DATA_OUT ,
inout [ 7:0] EPP_DATA_INOUT ,
input EPP_WRITE_IN ,
input EPP_ASTB_IN ,
input EPP_DSTB_IN ,
output EPP_WAIT_OUT ,
output EPP_INT_OUT ,
input EPP_RESET_IN
);
parameter EPPFSM_IDLE = 2'h0;
parameter EPPFSM_REQ = 2'h1;
parameter EPPFSM_ACK = 2'h2;
reg [ 1:0] EppfsmStateCur;
reg [ 1:0] EppfsmStateNxt;
reg CRxDataVld;
wire EppAddrRd;
wire EppAddrWr;
wire EppDataRd;
wire EppDataWr;
reg DataReqNxt;
reg DataReq;
reg EppDataRegEn;
reg EppWaitNxt;
reg EppWait;
reg [1:0] EppRwbPipe;
reg [1:0] EppAstbPipe;
reg [1:0] EppDstbPipe;
wire EppRwb = EppRwbPipe[0] ;
wire EppAddrStb = EppAstbPipe[0] ;
wire EppDstbStb = EppDstbPipe[0] ;
wire EppStb = EppAddrStb | EppDstbStb;
wire DataAck = REGS_READ_ACK_IN | REGS_WRITE_ACK_IN;
wire EppTxDataRegEn = DataReq & DataAck & EppRwb ;
wire EppRxDataRegEn = EppDataRegEn & ~EppRwb ;
reg [7:0] EppTxDataReg;
reg [7:0] EppRxDataReg;
assign REGS_WRITE_REQ_OUT = DataReq & ~EppRwb ;
assign REGS_READ_REQ_OUT = DataReq & EppRwb ;
assign REGS_ADDR_SEL_OUT = EppAddrStb ;
assign REGS_DATA_SEL_OUT = EppDstbStb ;
assign REGS_WRITE_DATA_OUT = EppRxDataReg;
assign EPP_DATA_INOUT = (EppWait & EppRwb & EppStb) ? EppTxDataReg : 8'hZZ;
assign EPP_WAIT_OUT = EppWait;
assign EPP_INT_OUT = 1'b0;
always @(posedge CLK or posedge RST_ASYNC)
begin : EPP_RWB_PIPE
if (RST_ASYNC)
begin
EppRwbPipe <= 2'b00;
end
else if (RST_SYNC)
begin
EppRwbPipe <= 2'b00;
end
else if (EN)
begin
EppRwbPipe[1:0] <= {EPP_WRITE_IN, EppRwbPipe[1]};
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : EPP_ASTB_PIPE
if (RST_ASYNC)
begin
EppAstbPipe <= 2'b00;
end
else if (RST_SYNC)
begin
EppAstbPipe <= 2'b00;
end
else if (EN)
begin
EppAstbPipe[1:0] <= {~EPP_ASTB_IN, EppAstbPipe[1]};
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : EPP_DSTB_PIPE
if (RST_ASYNC)
begin
EppDstbPipe <= 2'b00;
end
else if (RST_SYNC)
begin
EppDstbPipe <= 2'b00;
end
else if (EN)
begin
EppDstbPipe[1:0] <= {~EPP_DSTB_IN, EppDstbPipe[1]};
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : RX_DATA_REG
if (RST_ASYNC)
begin
EppRxDataReg <= 8'h00;
end
else if (RST_SYNC)
begin
EppRxDataReg <= 8'h00;
end
else if (EN)
begin
if (EppRxDataRegEn)
begin
EppRxDataReg <= EPP_DATA_INOUT;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : TX_DATA_REG
if (RST_ASYNC)
begin
EppTxDataReg <= 8'h00;
end
else if (RST_SYNC)
begin
EppTxDataReg <= 8'h00;
end
else if (EN)
begin
if (EppTxDataRegEn)
begin
EppTxDataReg <= REGS_READ_DATA_IN;
end
end
end
always @*
begin : EPPFSM_ST
EppfsmStateNxt = EppfsmStateCur;
DataReqNxt = 1'b0;
EppDataRegEn = 1'b0;
EppWaitNxt = 1'b0;
case (EppfsmStateCur)
EPPFSM_IDLE :
begin
if (EppStb)
begin
EppDataRegEn = 1'b1;
DataReqNxt = 1'b1;
EppfsmStateNxt = EPPFSM_REQ;
end
end
EPPFSM_REQ :
begin
DataReqNxt = 1'b1;
if (DataAck)
begin
DataReqNxt = 1'b0;
EppWaitNxt = 1'b1;
EppfsmStateNxt = EPPFSM_ACK;
end
end
EPPFSM_ACK :
begin
EppWaitNxt = 1'b1;
if (!EppStb)
begin
EppWaitNxt = 1'b0;
EppfsmStateNxt = EPPFSM_IDLE;
end
end
default : EppfsmStateNxt = EPPFSM_IDLE;
endcase
end
always @(posedge CLK or posedge RST_ASYNC)
begin : EPPFSM_CP
if (RST_ASYNC)
begin
EppfsmStateCur <= EPPFSM_IDLE;
EppWait <= 1'b0;
DataReq <= 1'b0;
end
else if (RST_SYNC)
begin
EppfsmStateCur <= EPPFSM_IDLE;
EppWait <= 1'b0;
DataReq <= 1'b0;
end
else if (EN)
begin
EppfsmStateCur <= EppfsmStateNxt;
EppWait <= EppWaitNxt;
DataReq <= DataReqNxt;
end
end
endmodule | module EPP_SLAVE
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
output REGS_WRITE_REQ_OUT ,
output REGS_READ_REQ_OUT ,
output REGS_ADDR_SEL_OUT ,
output REGS_DATA_SEL_OUT ,
input REGS_READ_ACK_IN ,
input REGS_WRITE_ACK_IN ,
input [7:0] REGS_READ_DATA_IN ,
output [7:0] REGS_WRITE_DATA_OUT ,
inout [ 7:0] EPP_DATA_INOUT ,
input EPP_WRITE_IN ,
input EPP_ASTB_IN ,
input EPP_DSTB_IN ,
output EPP_WAIT_OUT ,
output EPP_INT_OUT ,
input EPP_RESET_IN
); |
parameter EPPFSM_IDLE = 2'h0;
parameter EPPFSM_REQ = 2'h1;
parameter EPPFSM_ACK = 2'h2;
reg [ 1:0] EppfsmStateCur;
reg [ 1:0] EppfsmStateNxt;
reg CRxDataVld;
wire EppAddrRd;
wire EppAddrWr;
wire EppDataRd;
wire EppDataWr;
reg DataReqNxt;
reg DataReq;
reg EppDataRegEn;
reg EppWaitNxt;
reg EppWait;
reg [1:0] EppRwbPipe;
reg [1:0] EppAstbPipe;
reg [1:0] EppDstbPipe;
wire EppRwb = EppRwbPipe[0] ;
wire EppAddrStb = EppAstbPipe[0] ;
wire EppDstbStb = EppDstbPipe[0] ;
wire EppStb = EppAddrStb | EppDstbStb;
wire DataAck = REGS_READ_ACK_IN | REGS_WRITE_ACK_IN;
wire EppTxDataRegEn = DataReq & DataAck & EppRwb ;
wire EppRxDataRegEn = EppDataRegEn & ~EppRwb ;
reg [7:0] EppTxDataReg;
reg [7:0] EppRxDataReg;
assign REGS_WRITE_REQ_OUT = DataReq & ~EppRwb ;
assign REGS_READ_REQ_OUT = DataReq & EppRwb ;
assign REGS_ADDR_SEL_OUT = EppAddrStb ;
assign REGS_DATA_SEL_OUT = EppDstbStb ;
assign REGS_WRITE_DATA_OUT = EppRxDataReg;
assign EPP_DATA_INOUT = (EppWait & EppRwb & EppStb) ? EppTxDataReg : 8'hZZ;
assign EPP_WAIT_OUT = EppWait;
assign EPP_INT_OUT = 1'b0;
always @(posedge CLK or posedge RST_ASYNC)
begin : EPP_RWB_PIPE
if (RST_ASYNC)
begin
EppRwbPipe <= 2'b00;
end
else if (RST_SYNC)
begin
EppRwbPipe <= 2'b00;
end
else if (EN)
begin
EppRwbPipe[1:0] <= {EPP_WRITE_IN, EppRwbPipe[1]};
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : EPP_ASTB_PIPE
if (RST_ASYNC)
begin
EppAstbPipe <= 2'b00;
end
else if (RST_SYNC)
begin
EppAstbPipe <= 2'b00;
end
else if (EN)
begin
EppAstbPipe[1:0] <= {~EPP_ASTB_IN, EppAstbPipe[1]};
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : EPP_DSTB_PIPE
if (RST_ASYNC)
begin
EppDstbPipe <= 2'b00;
end
else if (RST_SYNC)
begin
EppDstbPipe <= 2'b00;
end
else if (EN)
begin
EppDstbPipe[1:0] <= {~EPP_DSTB_IN, EppDstbPipe[1]};
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : RX_DATA_REG
if (RST_ASYNC)
begin
EppRxDataReg <= 8'h00;
end
else if (RST_SYNC)
begin
EppRxDataReg <= 8'h00;
end
else if (EN)
begin
if (EppRxDataRegEn)
begin
EppRxDataReg <= EPP_DATA_INOUT;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : TX_DATA_REG
if (RST_ASYNC)
begin
EppTxDataReg <= 8'h00;
end
else if (RST_SYNC)
begin
EppTxDataReg <= 8'h00;
end
else if (EN)
begin
if (EppTxDataRegEn)
begin
EppTxDataReg <= REGS_READ_DATA_IN;
end
end
end
always @*
begin : EPPFSM_ST
EppfsmStateNxt = EppfsmStateCur;
DataReqNxt = 1'b0;
EppDataRegEn = 1'b0;
EppWaitNxt = 1'b0;
case (EppfsmStateCur)
EPPFSM_IDLE :
begin
if (EppStb)
begin
EppDataRegEn = 1'b1;
DataReqNxt = 1'b1;
EppfsmStateNxt = EPPFSM_REQ;
end
end
EPPFSM_REQ :
begin
DataReqNxt = 1'b1;
if (DataAck)
begin
DataReqNxt = 1'b0;
EppWaitNxt = 1'b1;
EppfsmStateNxt = EPPFSM_ACK;
end
end
EPPFSM_ACK :
begin
EppWaitNxt = 1'b1;
if (!EppStb)
begin
EppWaitNxt = 1'b0;
EppfsmStateNxt = EPPFSM_IDLE;
end
end
default : EppfsmStateNxt = EPPFSM_IDLE;
endcase
end
always @(posedge CLK or posedge RST_ASYNC)
begin : EPPFSM_CP
if (RST_ASYNC)
begin
EppfsmStateCur <= EPPFSM_IDLE;
EppWait <= 1'b0;
DataReq <= 1'b0;
end
else if (RST_SYNC)
begin
EppfsmStateCur <= EPPFSM_IDLE;
EppWait <= 1'b0;
DataReq <= 1'b0;
end
else if (EN)
begin
EppfsmStateCur <= EppfsmStateNxt;
EppWait <= EppWaitNxt;
DataReq <= DataReqNxt;
end
end
endmodule | 1 |
138,298 | data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v | 83,270,534 | testcase.v | v | 147 | 183 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:8: Cannot find include file: epp_bus_bridge_defs.v\n`include "epp_bus_bridge_defs.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill,data/full_repos/permissive/83270534/epp_bus_bridge_defs.v\n data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill,data/full_repos/permissive/83270534/epp_bus_bridge_defs.v.v\n data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill,data/full_repos/permissive/83270534/epp_bus_bridge_defs.v.sv\n epp_bus_bridge_defs.v\n epp_bus_bridge_defs.v.v\n epp_bus_bridge_defs.v.sv\n obj_dir/epp_bus_bridge_defs.v\n obj_dir/epp_bus_bridge_defs.v.v\n obj_dir/epp_bus_bridge_defs.v.sv\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:33: Unsupported or unknown PLI call: $urandom\n randomData[dataLoop] = $urandom();\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:38: syntax error, unexpected \'@\'\n @(negedge `RST);\n ^\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:38: Define or directive not defined: \'`RST\'\n @(negedge `RST);\n ^~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:49: Unsupported or unknown PLI call: $urandom_range\n fillType = $urandom_range(0, 2);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:55: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doBusWrite((addrLoop << 2) + 3, {24\'hDEADDE, randomData[addrLoop][31:24]}, fillType);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:55: syntax error, unexpected \'.\'\n `EPP_MASTER.doBusWrite((addrLoop << 2) + 3, {24\'hDEADDE, randomData[addrLoop][31:24]}, fillType);\n ^\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:56: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doBusWrite((addrLoop << 2) + 1, {24\'hDEADDE, randomData[addrLoop][15: 8]}, fillType);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:57: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doBusWrite((addrLoop << 2) + 0, {24\'hDEADDE, randomData[addrLoop][ 7: 0]}, fillType);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:58: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doBusWrite((addrLoop << 2) + 2, {24\'hDEADDE, randomData[addrLoop][23:16]}, fillType);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:62: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doBusWrite((addrLoop << 2) + 2, {16\'hDEAD, randomData[addrLoop][31:16]}, fillType);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:62: syntax error, unexpected \'.\'\n `EPP_MASTER.doBusWrite((addrLoop << 2) + 2, {16\'hDEAD, randomData[addrLoop][31:16]}, fillType);\n ^\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:63: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doBusWrite((addrLoop << 2) + 0, {16\'hDEAD, randomData[addrLoop][15: 0]}, fillType);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:67: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doBusWrite((addrLoop << 2) + 0, randomData[addrLoop][31: 0], fillType);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:67: syntax error, unexpected \'.\'\n `EPP_MASTER.doBusWrite((addrLoop << 2) + 0, randomData[addrLoop][31: 0], fillType);\n ^\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:78: Unsupported or unknown PLI call: $urandom_range\n fillType = $urandom_range(0, 2);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:84: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doBusRead((addrLoop << 2) + 2, readData8[2], fillType);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:84: syntax error, unexpected \'.\'\n `EPP_MASTER.doBusRead((addrLoop << 2) + 2, readData8[2], fillType);\n ^\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:85: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doBusRead((addrLoop << 2) + 1, readData8[1], fillType);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:86: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doBusRead((addrLoop << 2) + 3, readData8[3], fillType);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:87: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doBusRead((addrLoop << 2) + 0, readData8[0], fillType);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:92: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doBusRead((addrLoop << 2) + 2, readData16[1] , fillType);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:92: syntax error, unexpected \'.\'\n `EPP_MASTER.doBusRead((addrLoop << 2) + 2, readData16[1] , fillType);\n ^\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:93: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doBusRead((addrLoop << 2) + 0, readData16[0] , fillType);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:99: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doBusRead((addrLoop << 2) + 0, readData, fillType);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:99: syntax error, unexpected \'.\'\n `EPP_MASTER.doBusRead((addrLoop << 2) + 0, readData, fillType);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:131: Unsupported: Ignoring delay on this delayed statement.\n #1000ns;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/83270534/adi/sim/bus_access/mixed_fill/testcase.v:138: Unsupported: Ignoring delay on this delayed statement.\n #100ms;\n ^\n%Error: Exiting due to 26 error(s), 2 warning(s)\n' | 302,138 | module | module TESTCASE ();
`include "epp_bus_bridge_defs.v"
parameter RAM_SIZE_32B = 1024;
logic [31:0] randomData [RAM_SIZE_32B-1:0];
initial
begin
int dataLoop;
int addrLoop;
int fillType;
int readData;
int readData16 [1:0] ;
byte readData8 [3:0] ;
bit verifyOk = 0;
bit testPass = 1;
for (dataLoop = 0 ; dataLoop < RAM_SIZE_32B ; dataLoop = dataLoop + 1)
begin
randomData[dataLoop] = $urandom();
end
@(negedge `RST);
$display("[INFO ] Reset de-asserted at time %t", $time);
addrLoop = 0;
$display("[INFO ] Filling Memory (mixed accesses) at time %t", $time);
for (addrLoop = 0 ; addrLoop < RAM_SIZE_32B ; addrLoop++)
begin
fillType = $urandom_range(0, 2);
case (fillType)
0 :
begin
`EPP_MASTER.doBusWrite((addrLoop << 2) + 3, {24'hDEADDE, randomData[addrLoop][31:24]}, fillType);
`EPP_MASTER.doBusWrite((addrLoop << 2) + 1, {24'hDEADDE, randomData[addrLoop][15: 8]}, fillType);
`EPP_MASTER.doBusWrite((addrLoop << 2) + 0, {24'hDEADDE, randomData[addrLoop][ 7: 0]}, fillType);
`EPP_MASTER.doBusWrite((addrLoop << 2) + 2, {24'hDEADDE, randomData[addrLoop][23:16]}, fillType);
end
1 :
begin
`EPP_MASTER.doBusWrite((addrLoop << 2) + 2, {16'hDEAD, randomData[addrLoop][31:16]}, fillType);
`EPP_MASTER.doBusWrite((addrLoop << 2) + 0, {16'hDEAD, randomData[addrLoop][15: 0]}, fillType);
end
2 :
begin
`EPP_MASTER.doBusWrite((addrLoop << 2) + 0, randomData[addrLoop][31: 0], fillType);
end
endcase
end
$display("[INFO ] Reading back memory contents (word accesses) at time %t", $time);
for (addrLoop = 0 ; addrLoop < RAM_SIZE_32B ; addrLoop++)
begin
fillType = $urandom_range(0, 2);
case (fillType)
0 :
begin
`EPP_MASTER.doBusRead((addrLoop << 2) + 2, readData8[2], fillType);
`EPP_MASTER.doBusRead((addrLoop << 2) + 1, readData8[1], fillType);
`EPP_MASTER.doBusRead((addrLoop << 2) + 3, readData8[3], fillType);
`EPP_MASTER.doBusRead((addrLoop << 2) + 0, readData8[0], fillType);
readData = {readData8[3], readData8[2], readData8[1], readData8[0]};
end
1 :
begin
`EPP_MASTER.doBusRead((addrLoop << 2) + 2, readData16[1] , fillType);
`EPP_MASTER.doBusRead((addrLoop << 2) + 0, readData16[0] , fillType);
readData = {readData16[1][15:0], readData16[0][15:0]};
end
2 :
begin
`EPP_MASTER.doBusRead((addrLoop << 2) + 0, readData, fillType);
end
endcase
if (randomData[addrLoop] === readData)
begin
$display("[INFO ] EPP Data readback of Address 0x%x verified at time %t", addrLoop << 2, $time);
end
else
begin
$display("[ERROR] EPP Data readback of Address 0x%x FAILED, Read 0x%x, Expected 0x%x at time %t", addrLoop << 2, readData, randomData[addrLoop], $time); testPass = 0;
end
end
if (testPass)
begin
$display("[PASS ] Test PASSED at time %t", $time);
$display("");
end
else
begin
$display("[FAIL ] Test FAILED at time %t", $time);
$display("");
end
#1000ns;
$finish();
end
initial
begin
#100ms;
$display("[FAIL] Epp test FAILED (timed out) at time %t", $time);
$display("");
$finish();
end
endmodule | module TESTCASE (); |
`include "epp_bus_bridge_defs.v"
parameter RAM_SIZE_32B = 1024;
logic [31:0] randomData [RAM_SIZE_32B-1:0];
initial
begin
int dataLoop;
int addrLoop;
int fillType;
int readData;
int readData16 [1:0] ;
byte readData8 [3:0] ;
bit verifyOk = 0;
bit testPass = 1;
for (dataLoop = 0 ; dataLoop < RAM_SIZE_32B ; dataLoop = dataLoop + 1)
begin
randomData[dataLoop] = $urandom();
end
@(negedge `RST);
$display("[INFO ] Reset de-asserted at time %t", $time);
addrLoop = 0;
$display("[INFO ] Filling Memory (mixed accesses) at time %t", $time);
for (addrLoop = 0 ; addrLoop < RAM_SIZE_32B ; addrLoop++)
begin
fillType = $urandom_range(0, 2);
case (fillType)
0 :
begin
`EPP_MASTER.doBusWrite((addrLoop << 2) + 3, {24'hDEADDE, randomData[addrLoop][31:24]}, fillType);
`EPP_MASTER.doBusWrite((addrLoop << 2) + 1, {24'hDEADDE, randomData[addrLoop][15: 8]}, fillType);
`EPP_MASTER.doBusWrite((addrLoop << 2) + 0, {24'hDEADDE, randomData[addrLoop][ 7: 0]}, fillType);
`EPP_MASTER.doBusWrite((addrLoop << 2) + 2, {24'hDEADDE, randomData[addrLoop][23:16]}, fillType);
end
1 :
begin
`EPP_MASTER.doBusWrite((addrLoop << 2) + 2, {16'hDEAD, randomData[addrLoop][31:16]}, fillType);
`EPP_MASTER.doBusWrite((addrLoop << 2) + 0, {16'hDEAD, randomData[addrLoop][15: 0]}, fillType);
end
2 :
begin
`EPP_MASTER.doBusWrite((addrLoop << 2) + 0, randomData[addrLoop][31: 0], fillType);
end
endcase
end
$display("[INFO ] Reading back memory contents (word accesses) at time %t", $time);
for (addrLoop = 0 ; addrLoop < RAM_SIZE_32B ; addrLoop++)
begin
fillType = $urandom_range(0, 2);
case (fillType)
0 :
begin
`EPP_MASTER.doBusRead((addrLoop << 2) + 2, readData8[2], fillType);
`EPP_MASTER.doBusRead((addrLoop << 2) + 1, readData8[1], fillType);
`EPP_MASTER.doBusRead((addrLoop << 2) + 3, readData8[3], fillType);
`EPP_MASTER.doBusRead((addrLoop << 2) + 0, readData8[0], fillType);
readData = {readData8[3], readData8[2], readData8[1], readData8[0]};
end
1 :
begin
`EPP_MASTER.doBusRead((addrLoop << 2) + 2, readData16[1] , fillType);
`EPP_MASTER.doBusRead((addrLoop << 2) + 0, readData16[0] , fillType);
readData = {readData16[1][15:0], readData16[0][15:0]};
end
2 :
begin
`EPP_MASTER.doBusRead((addrLoop << 2) + 0, readData, fillType);
end
endcase
if (randomData[addrLoop] === readData)
begin
$display("[INFO ] EPP Data readback of Address 0x%x verified at time %t", addrLoop << 2, $time);
end
else
begin
$display("[ERROR] EPP Data readback of Address 0x%x FAILED, Read 0x%x, Expected 0x%x at time %t", addrLoop << 2, readData, randomData[addrLoop], $time); testPass = 0;
end
end
if (testPass)
begin
$display("[PASS ] Test PASSED at time %t", $time);
$display("");
end
else
begin
$display("[FAIL ] Test FAILED at time %t", $time);
$display("");
end
#1000ns;
$finish();
end
initial
begin
#100ms;
$display("[FAIL] Epp test FAILED (timed out) at time %t", $time);
$display("");
$finish();
end
endmodule | 1 |
138,300 | data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v | 83,270,534 | testcase.v | v | 121 | 183 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:8: Cannot find include file: epp_bus_bridge_defs.v\n`include "epp_bus_bridge_defs.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/adi/sim/bus_access/streaming,data/full_repos/permissive/83270534/epp_bus_bridge_defs.v\n data/full_repos/permissive/83270534/adi/sim/bus_access/streaming,data/full_repos/permissive/83270534/epp_bus_bridge_defs.v.v\n data/full_repos/permissive/83270534/adi/sim/bus_access/streaming,data/full_repos/permissive/83270534/epp_bus_bridge_defs.v.sv\n epp_bus_bridge_defs.v\n epp_bus_bridge_defs.v.v\n epp_bus_bridge_defs.v.sv\n obj_dir/epp_bus_bridge_defs.v\n obj_dir/epp_bus_bridge_defs.v.v\n obj_dir/epp_bus_bridge_defs.v.sv\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:33: Unsupported or unknown PLI call: $urandom\n randomData[dataLoop] = $urandom();\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:38: syntax error, unexpected \'@\'\n @(negedge `RST);\n ^\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:38: Define or directive not defined: \'`RST\'\n @(negedge `RST);\n ^~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:47: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppRegWrite(ERW_ADDR0, 8\'h00);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:47: syntax error, unexpected \'.\'\n `EPP_MASTER.doEppRegWrite(ERW_ADDR0, 8\'h00);\n ^\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:48: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppRegWrite(ERW_ADDR1, 8\'h00);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:49: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppRegWrite(ERW_ADDR2, 8\'h00);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:50: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppRegWrite(ERW_ADDR3, 8\'h00);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:53: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppAddrWrite(ERW_STREAM);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:58: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppDataWrite(randomData[addrLoop][ 7: 0]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:58: syntax error, unexpected \'.\'\n `EPP_MASTER.doEppDataWrite(randomData[addrLoop][ 7: 0]);\n ^\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:59: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppDataWrite(randomData[addrLoop][15: 8]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:60: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppDataWrite(randomData[addrLoop][23:16]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:61: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppDataWrite(randomData[addrLoop][31:24]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:67: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppRegWrite(ERW_ADDR0, 8\'h00);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:67: syntax error, unexpected \'.\'\n `EPP_MASTER.doEppRegWrite(ERW_ADDR0, 8\'h00);\n ^\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:68: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppRegWrite(ERW_ADDR1, 8\'h00);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:69: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppRegWrite(ERW_ADDR2, 8\'h00);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:70: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppRegWrite(ERW_ADDR3, 8\'h00);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:73: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppAddrWrite(ERW_STREAM);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:79: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppDataRead(readData8[0]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:79: syntax error, unexpected \'.\'\n `EPP_MASTER.doEppDataRead(readData8[0]);\n ^\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:80: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppDataRead(readData8[1]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:81: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppDataRead(readData8[2]);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:82: Define or directive not defined: \'`EPP_MASTER\'\n `EPP_MASTER.doEppDataRead(readData8[3]);\n ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:105: Unsupported: Ignoring delay on this delayed statement.\n #1000ns;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/83270534/adi/sim/bus_access/streaming/testcase.v:112: Unsupported: Ignoring delay on this delayed statement.\n #100ms;\n ^\n%Error: Exiting due to 26 error(s), 2 warning(s)\n' | 302,140 | module | module TESTCASE ();
`include "epp_bus_bridge_defs.v"
parameter RAM_SIZE_32B = 1024;
logic [31:0] randomData [RAM_SIZE_32B-1:0];
initial
begin
int dataLoop;
int addrLoop;
int fillType;
int readData;
int readData16 [1:0] ;
byte readData8 [3:0] ;
bit verifyOk = 0;
bit testPass = 1;
for (dataLoop = 0 ; dataLoop < RAM_SIZE_32B ; dataLoop = dataLoop + 1)
begin
randomData[dataLoop] = $urandom();
end
@(negedge `RST);
$display("[INFO ] Reset de-asserted at time %t", $time);
addrLoop = 0;
$display("[INFO ] Filling Memory (streaming accesses) at time %t", $time);
`EPP_MASTER.doEppRegWrite(ERW_ADDR0, 8'h00);
`EPP_MASTER.doEppRegWrite(ERW_ADDR1, 8'h00);
`EPP_MASTER.doEppRegWrite(ERW_ADDR2, 8'h00);
`EPP_MASTER.doEppRegWrite(ERW_ADDR3, 8'h00);
`EPP_MASTER.doEppAddrWrite(ERW_STREAM);
for (addrLoop = 0 ; addrLoop < RAM_SIZE_32B ; addrLoop++)
begin
`EPP_MASTER.doEppDataWrite(randomData[addrLoop][ 7: 0]);
`EPP_MASTER.doEppDataWrite(randomData[addrLoop][15: 8]);
`EPP_MASTER.doEppDataWrite(randomData[addrLoop][23:16]);
`EPP_MASTER.doEppDataWrite(randomData[addrLoop][31:24]);
end
$display("[INFO ] Reading back the Memory (streaming accesses) at time %t", $time);
`EPP_MASTER.doEppRegWrite(ERW_ADDR0, 8'h00);
`EPP_MASTER.doEppRegWrite(ERW_ADDR1, 8'h00);
`EPP_MASTER.doEppRegWrite(ERW_ADDR2, 8'h00);
`EPP_MASTER.doEppRegWrite(ERW_ADDR3, 8'h00);
`EPP_MASTER.doEppAddrWrite(ERW_STREAM);
for (addrLoop = 0 ; addrLoop < RAM_SIZE_32B ; addrLoop++)
begin
`EPP_MASTER.doEppDataRead(readData8[0]);
`EPP_MASTER.doEppDataRead(readData8[1]);
`EPP_MASTER.doEppDataRead(readData8[2]);
`EPP_MASTER.doEppDataRead(readData8[3]);
readData = {readData8[3], readData8[2], readData8[1], readData8[0]};
if (randomData[addrLoop] === readData)
begin
$display("[INFO ] EPP Data readback of Address 0x%x verified at time %t", addrLoop << 2, $time);
end
else
begin
$display("[ERROR] EPP Data readback of Address 0x%x FAILED, Read 0x%x, Expected 0x%x at time %t", addrLoop << 2, readData, randomData[addrLoop], $time); testPass = 0;
end
end
if (!testPass)
begin
$display("[FAIL ] Test FAILED !");
end
else
begin
$display("[PASS ] Test PASSED !");
end
#1000ns;
$finish();
end
initial
begin
#100ms;
$display("[FAIL] Epp test FAILED (timed out) at time %t", $time);
$display("");
$finish();
end
endmodule | module TESTCASE (); |
`include "epp_bus_bridge_defs.v"
parameter RAM_SIZE_32B = 1024;
logic [31:0] randomData [RAM_SIZE_32B-1:0];
initial
begin
int dataLoop;
int addrLoop;
int fillType;
int readData;
int readData16 [1:0] ;
byte readData8 [3:0] ;
bit verifyOk = 0;
bit testPass = 1;
for (dataLoop = 0 ; dataLoop < RAM_SIZE_32B ; dataLoop = dataLoop + 1)
begin
randomData[dataLoop] = $urandom();
end
@(negedge `RST);
$display("[INFO ] Reset de-asserted at time %t", $time);
addrLoop = 0;
$display("[INFO ] Filling Memory (streaming accesses) at time %t", $time);
`EPP_MASTER.doEppRegWrite(ERW_ADDR0, 8'h00);
`EPP_MASTER.doEppRegWrite(ERW_ADDR1, 8'h00);
`EPP_MASTER.doEppRegWrite(ERW_ADDR2, 8'h00);
`EPP_MASTER.doEppRegWrite(ERW_ADDR3, 8'h00);
`EPP_MASTER.doEppAddrWrite(ERW_STREAM);
for (addrLoop = 0 ; addrLoop < RAM_SIZE_32B ; addrLoop++)
begin
`EPP_MASTER.doEppDataWrite(randomData[addrLoop][ 7: 0]);
`EPP_MASTER.doEppDataWrite(randomData[addrLoop][15: 8]);
`EPP_MASTER.doEppDataWrite(randomData[addrLoop][23:16]);
`EPP_MASTER.doEppDataWrite(randomData[addrLoop][31:24]);
end
$display("[INFO ] Reading back the Memory (streaming accesses) at time %t", $time);
`EPP_MASTER.doEppRegWrite(ERW_ADDR0, 8'h00);
`EPP_MASTER.doEppRegWrite(ERW_ADDR1, 8'h00);
`EPP_MASTER.doEppRegWrite(ERW_ADDR2, 8'h00);
`EPP_MASTER.doEppRegWrite(ERW_ADDR3, 8'h00);
`EPP_MASTER.doEppAddrWrite(ERW_STREAM);
for (addrLoop = 0 ; addrLoop < RAM_SIZE_32B ; addrLoop++)
begin
`EPP_MASTER.doEppDataRead(readData8[0]);
`EPP_MASTER.doEppDataRead(readData8[1]);
`EPP_MASTER.doEppDataRead(readData8[2]);
`EPP_MASTER.doEppDataRead(readData8[3]);
readData = {readData8[3], readData8[2], readData8[1], readData8[0]};
if (randomData[addrLoop] === readData)
begin
$display("[INFO ] EPP Data readback of Address 0x%x verified at time %t", addrLoop << 2, $time);
end
else
begin
$display("[ERROR] EPP Data readback of Address 0x%x FAILED, Read 0x%x, Expected 0x%x at time %t", addrLoop << 2, readData, randomData[addrLoop], $time); testPass = 0;
end
end
if (!testPass)
begin
$display("[FAIL ] Test FAILED !");
end
else
begin
$display("[PASS ] Test PASSED !");
end
#1000ns;
$finish();
end
initial
begin
#100ms;
$display("[FAIL] Epp test FAILED (timed out) at time %t", $time);
$display("");
$finish();
end
endmodule | 1 |
138,303 | data/full_repos/permissive/83270534/common/fpga/fpga_top.v | 83,270,534 | fpga_top.v | v | 330 | 108 | [] | [] | [] | [(1, 329)] | null | null | 1: b"%Error: data/full_repos/permissive/83270534/common/fpga/fpga_top.v:265: Cannot find file containing module: 'FPGA_BUS_TOP'\n FPGA_BUS_TOP fpga_bus_top\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/common/fpga,data/full_repos/permissive/83270534/FPGA_BUS_TOP\n data/full_repos/permissive/83270534/common/fpga,data/full_repos/permissive/83270534/FPGA_BUS_TOP.v\n data/full_repos/permissive/83270534/common/fpga,data/full_repos/permissive/83270534/FPGA_BUS_TOP.sv\n FPGA_BUS_TOP\n FPGA_BUS_TOP.v\n FPGA_BUS_TOP.sv\n obj_dir/FPGA_BUS_TOP\n obj_dir/FPGA_BUS_TOP.v\n obj_dir/FPGA_BUS_TOP.sv\n%Error: Exiting due to 1 error(s)\n" | 302,144 | module | module FPGA_TOP
(
input BTN_0_IN ,
input BTN_1_IN ,
input BTN_2_IN ,
input BTN_3_IN ,
input CLK_IN ,
input EPP_ASTB_IN ,
input EPP_DSTB_IN ,
output EPP_WAIT_OUT ,
output FLASH_CS_OUT ,
output FLASH_RP_OUT ,
input FLASH_ST_STS_IN ,
output LED_0_OUT ,
output LED_1_OUT ,
output LED_2_OUT ,
output LED_3_OUT ,
output LED_4_OUT ,
output LED_5_OUT ,
output LED_6_OUT ,
output LED_7_OUT ,
output MEM_ADDR_1_OUT ,
output MEM_ADDR_2_OUT ,
output MEM_ADDR_3_OUT ,
output MEM_ADDR_4_OUT ,
output MEM_ADDR_5_OUT ,
output MEM_ADDR_6_OUT ,
output MEM_ADDR_7_OUT ,
output MEM_ADDR_8_OUT ,
output MEM_ADDR_9_OUT ,
output MEM_ADDR_10_OUT ,
output MEM_ADDR_11_OUT ,
output MEM_ADDR_12_OUT ,
output MEM_ADDR_13_OUT ,
output MEM_ADDR_14_OUT ,
output MEM_ADDR_15_OUT ,
output MEM_ADDR_16_OUT ,
output MEM_ADDR_17_OUT ,
output MEM_ADDR_18_OUT ,
output MEM_ADDR_19_OUT ,
output MEM_ADDR_20_OUT ,
output MEM_ADDR_21_OUT ,
output MEM_ADDR_22_OUT ,
output MEM_ADDR_23_OUT ,
inout MEM_DATA_0_INOUT ,
inout MEM_DATA_1_INOUT ,
inout MEM_DATA_2_INOUT ,
inout MEM_DATA_3_INOUT ,
inout MEM_DATA_4_INOUT ,
inout MEM_DATA_5_INOUT ,
inout MEM_DATA_6_INOUT ,
inout MEM_DATA_7_INOUT ,
inout MEM_DATA_8_INOUT ,
inout MEM_DATA_9_INOUT ,
inout MEM_DATA_10_INOUT ,
inout MEM_DATA_11_INOUT ,
inout MEM_DATA_12_INOUT ,
inout MEM_DATA_13_INOUT ,
inout MEM_DATA_14_INOUT ,
inout MEM_DATA_15_INOUT ,
output MEM_OE_OUT ,
output MEM_WR_OUT ,
inout PS2_CLK_INOUT ,
inout PS2_DATA_INOUT ,
output RAM_ADV_OUT ,
output RAM_CLK_OUT ,
output RAM_CRE_OUT ,
output RAM_CS_OUT ,
output RAM_LB_OUT ,
output RAM_UB_OUT ,
input RAM_WAIT_IN ,
input RS232_RX_IN ,
inout RS232_TX_INOUT ,
output SSEG_AN_0_OUT ,
output SSEG_AN_1_OUT ,
output SSEG_AN_2_OUT ,
output SSEG_AN_3_OUT ,
output SSEG_K_0_OUT ,
output SSEG_K_1_OUT ,
output SSEG_K_2_OUT ,
output SSEG_K_3_OUT ,
output SSEG_K_4_OUT ,
output SSEG_K_5_OUT ,
output SSEG_K_6_OUT ,
output SSEG_K_7_OUT ,
input SW_0_IN ,
input SW_1_IN ,
input SW_2_IN ,
input SW_3_IN ,
input SW_4_IN ,
input SW_5_IN ,
input SW_6_IN ,
input SW_7_IN ,
output USB_ADDR_0_OUT ,
output USB_ADDR_1_OUT ,
input USB_CLK_IN ,
inout USB_DATA_0_INOUT ,
inout USB_DATA_1_INOUT ,
inout USB_DATA_2_INOUT ,
inout USB_DATA_3_INOUT ,
inout USB_DATA_4_INOUT ,
inout USB_DATA_5_INOUT ,
inout USB_DATA_6_INOUT ,
inout USB_DATA_7_INOUT ,
input USB_DIR_IN ,
input USB_FLAG_IN ,
input USB_MODE_IN ,
output USB_OE_OUT ,
output USB_PKTEND_OUT ,
output USB_WR_OUT ,
output VGA_BLUE_0_OUT ,
output VGA_BLUE_1_OUT ,
output VGA_GREEN_0_OUT ,
output VGA_GREEN_1_OUT ,
output VGA_GREEN_2_OUT ,
output VGA_HSYNC_OUT ,
output VGA_RED_0_OUT ,
output VGA_RED_1_OUT ,
output VGA_RED_2_OUT ,
output VGA_VSYNC_OUT
);
wire [3:0] BTN = {BTN_3_IN, BTN_2_IN, BTN_1_IN, BTN_0_IN};
wire [7:0] SW = {SW_7_IN, SW_6_IN, SW_5_IN, SW_4_IN, SW_3_IN, SW_2_IN, SW_1_IN, SW_0_IN};
wire [7:0] LED;
assign LED_7_OUT = LED[7];
assign LED_6_OUT = LED[6];
assign LED_5_OUT = LED[5];
assign LED_4_OUT = LED[4];
assign LED_3_OUT = LED[3];
assign LED_2_OUT = LED[2];
assign LED_1_OUT = LED[1];
assign LED_0_OUT = LED[0];
wire [23:1] MEM_ADDR;
assign MEM_ADDR_23_OUT = MEM_ADDR[23];
assign MEM_ADDR_22_OUT = MEM_ADDR[22];
assign MEM_ADDR_21_OUT = MEM_ADDR[21];
assign MEM_ADDR_20_OUT = MEM_ADDR[20];
assign MEM_ADDR_19_OUT = MEM_ADDR[19];
assign MEM_ADDR_18_OUT = MEM_ADDR[18];
assign MEM_ADDR_17_OUT = MEM_ADDR[17];
assign MEM_ADDR_16_OUT = MEM_ADDR[16];
assign MEM_ADDR_15_OUT = MEM_ADDR[15];
assign MEM_ADDR_14_OUT = MEM_ADDR[14];
assign MEM_ADDR_13_OUT = MEM_ADDR[13];
assign MEM_ADDR_12_OUT = MEM_ADDR[12];
assign MEM_ADDR_11_OUT = MEM_ADDR[11];
assign MEM_ADDR_10_OUT = MEM_ADDR[10];
assign MEM_ADDR_9_OUT = MEM_ADDR[ 9];
assign MEM_ADDR_8_OUT = MEM_ADDR[ 8];
assign MEM_ADDR_7_OUT = MEM_ADDR[ 7];
assign MEM_ADDR_6_OUT = MEM_ADDR[ 6];
assign MEM_ADDR_5_OUT = MEM_ADDR[ 5];
assign MEM_ADDR_4_OUT = MEM_ADDR[ 4];
assign MEM_ADDR_3_OUT = MEM_ADDR[ 3];
assign MEM_ADDR_2_OUT = MEM_ADDR[ 2];
assign MEM_ADDR_1_OUT = MEM_ADDR[ 1];
wire [3:0] SSEG_AN;
assign SSEG_AN_0_OUT = SSEG_AN[0];
assign SSEG_AN_1_OUT = SSEG_AN[1];
assign SSEG_AN_2_OUT = SSEG_AN[2];
assign SSEG_AN_3_OUT = SSEG_AN[3];
wire [7:0] SSEG_K;
assign SSEG_K_0_OUT = SSEG_K[0];
assign SSEG_K_1_OUT = SSEG_K[1];
assign SSEG_K_2_OUT = SSEG_K[2];
assign SSEG_K_3_OUT = SSEG_K[3];
assign SSEG_K_4_OUT = SSEG_K[4];
assign SSEG_K_5_OUT = SSEG_K[5];
assign SSEG_K_6_OUT = SSEG_K[6];
assign SSEG_K_7_OUT = SSEG_K[7];
wire [1:0] USB_ADDR ;
assign USB_ADDR_0_OUT = USB_ADDR[0];
assign USB_ADDR_1_OUT = USB_ADDR[1];
wire [1:0] VGA_BLUE;
wire [2:0] VGA_GREEN;
wire [2:0] VGA_RED;
assign VGA_BLUE_0_OUT = VGA_BLUE[0];
assign VGA_BLUE_1_OUT = VGA_BLUE[1];
assign VGA_GREEN_0_OUT = VGA_GREEN[0];
assign VGA_GREEN_1_OUT = VGA_GREEN[1];
assign VGA_GREEN_2_OUT = VGA_GREEN[2];
assign VGA_RED_0_OUT = VGA_RED[0];
assign VGA_RED_1_OUT = VGA_RED[1];
assign VGA_RED_2_OUT = VGA_RED[2];
FPGA_BUS_TOP fpga_bus_top
(
.BTN_IN (BTN ),
.CLK_IN (CLK_IN ),
.EPP_ASTB_IN (EPP_ASTB_IN ),
.EPP_DSTB_IN (EPP_DSTB_IN ),
.EPP_WAIT_OUT (EPP_WAIT_OUT ),
.FLASH_CS_OUT (FLASH_CS_OUT ),
.FLASH_RP_OUT (FLASH_RP_OUT ),
.FLASH_ST_STS_IN (FLASH_ST_STS_IN ),
.LED_OUT (LED ),
.MEM_ADDR_OUT (MEM_ADDR ),
.MEM_DATA_INOUT ({MEM_DATA_15_INOUT, MEM_DATA_14_INOUT, MEM_DATA_13_INOUT, MEM_DATA_12_INOUT ,
MEM_DATA_11_INOUT, MEM_DATA_10_INOUT, MEM_DATA_9_INOUT , MEM_DATA_8_INOUT ,
MEM_DATA_7_INOUT , MEM_DATA_6_INOUT , MEM_DATA_5_INOUT , MEM_DATA_4_INOUT ,
MEM_DATA_3_INOUT , MEM_DATA_2_INOUT , MEM_DATA_1_INOUT , MEM_DATA_0_INOUT }),
.MEM_OE_OUT (MEM_OE_OUT ),
.MEM_WR_OUT (MEM_WR_OUT ),
.PS2_CLK_INOUT (PS2_CLK_INOUT ),
.PS2_DATA_INOUT (PS2_DATA_INOUT ),
.RAM_ADV_OUT (RAM_ADV_OUT ),
.RAM_CLK_OUT (RAM_CLK_OUT ),
.RAM_CRE_OUT (RAM_CRE_OUT ),
.RAM_CS_OUT (RAM_CS_OUT ),
.RAM_LB_OUT (RAM_LB_OUT ),
.RAM_UB_OUT (RAM_UB_OUT ),
.RAM_WAIT_IN (RAM_WAIT_IN ),
.RS232_RX_IN (RS232_RX_IN ),
.RS232_TX_INOUT (RS232_TX_INOUT ),
.SSEG_AN_OUT (SSEG_AN ),
.SSEG_K_OUT (SSEG_K ),
.SW_IN (SW ),
.USB_ADDR_OUT (USB_ADDR ),
.USB_CLK_IN (USB_CLK_IN ),
.USB_DATA_INOUT ({USB_DATA_7_INOUT ,
USB_DATA_6_INOUT ,
USB_DATA_5_INOUT ,
USB_DATA_4_INOUT ,
USB_DATA_3_INOUT ,
USB_DATA_2_INOUT ,
USB_DATA_1_INOUT ,
USB_DATA_0_INOUT } ),
.USB_DIR_IN (USB_DIR_IN ),
.USB_FLAG_IN (USB_FLAG_IN ),
.USB_MODE_IN (USB_MODE_IN ),
.USB_OE_OUT (USB_OE_OUT ),
.USB_PKTEND_OUT (USB_PKTEND_OUT ),
.USB_WR_OUT (USB_WR_OUT ),
.VGA_BLUE_OUT (VGA_BLUE ),
.VGA_GREEN_OUT (VGA_GREEN ),
.VGA_HSYNC_OUT (VGA_HSYNC_OUT ),
.VGA_RED_OUT (VGA_RED ),
.VGA_VSYNC_OUT (VGA_VSYNC_OUT )
);
endmodule | module FPGA_TOP
(
input BTN_0_IN ,
input BTN_1_IN ,
input BTN_2_IN ,
input BTN_3_IN ,
input CLK_IN ,
input EPP_ASTB_IN ,
input EPP_DSTB_IN ,
output EPP_WAIT_OUT ,
output FLASH_CS_OUT ,
output FLASH_RP_OUT ,
input FLASH_ST_STS_IN ,
output LED_0_OUT ,
output LED_1_OUT ,
output LED_2_OUT ,
output LED_3_OUT ,
output LED_4_OUT ,
output LED_5_OUT ,
output LED_6_OUT ,
output LED_7_OUT ,
output MEM_ADDR_1_OUT ,
output MEM_ADDR_2_OUT ,
output MEM_ADDR_3_OUT ,
output MEM_ADDR_4_OUT ,
output MEM_ADDR_5_OUT ,
output MEM_ADDR_6_OUT ,
output MEM_ADDR_7_OUT ,
output MEM_ADDR_8_OUT ,
output MEM_ADDR_9_OUT ,
output MEM_ADDR_10_OUT ,
output MEM_ADDR_11_OUT ,
output MEM_ADDR_12_OUT ,
output MEM_ADDR_13_OUT ,
output MEM_ADDR_14_OUT ,
output MEM_ADDR_15_OUT ,
output MEM_ADDR_16_OUT ,
output MEM_ADDR_17_OUT ,
output MEM_ADDR_18_OUT ,
output MEM_ADDR_19_OUT ,
output MEM_ADDR_20_OUT ,
output MEM_ADDR_21_OUT ,
output MEM_ADDR_22_OUT ,
output MEM_ADDR_23_OUT ,
inout MEM_DATA_0_INOUT ,
inout MEM_DATA_1_INOUT ,
inout MEM_DATA_2_INOUT ,
inout MEM_DATA_3_INOUT ,
inout MEM_DATA_4_INOUT ,
inout MEM_DATA_5_INOUT ,
inout MEM_DATA_6_INOUT ,
inout MEM_DATA_7_INOUT ,
inout MEM_DATA_8_INOUT ,
inout MEM_DATA_9_INOUT ,
inout MEM_DATA_10_INOUT ,
inout MEM_DATA_11_INOUT ,
inout MEM_DATA_12_INOUT ,
inout MEM_DATA_13_INOUT ,
inout MEM_DATA_14_INOUT ,
inout MEM_DATA_15_INOUT ,
output MEM_OE_OUT ,
output MEM_WR_OUT ,
inout PS2_CLK_INOUT ,
inout PS2_DATA_INOUT ,
output RAM_ADV_OUT ,
output RAM_CLK_OUT ,
output RAM_CRE_OUT ,
output RAM_CS_OUT ,
output RAM_LB_OUT ,
output RAM_UB_OUT ,
input RAM_WAIT_IN ,
input RS232_RX_IN ,
inout RS232_TX_INOUT ,
output SSEG_AN_0_OUT ,
output SSEG_AN_1_OUT ,
output SSEG_AN_2_OUT ,
output SSEG_AN_3_OUT ,
output SSEG_K_0_OUT ,
output SSEG_K_1_OUT ,
output SSEG_K_2_OUT ,
output SSEG_K_3_OUT ,
output SSEG_K_4_OUT ,
output SSEG_K_5_OUT ,
output SSEG_K_6_OUT ,
output SSEG_K_7_OUT ,
input SW_0_IN ,
input SW_1_IN ,
input SW_2_IN ,
input SW_3_IN ,
input SW_4_IN ,
input SW_5_IN ,
input SW_6_IN ,
input SW_7_IN ,
output USB_ADDR_0_OUT ,
output USB_ADDR_1_OUT ,
input USB_CLK_IN ,
inout USB_DATA_0_INOUT ,
inout USB_DATA_1_INOUT ,
inout USB_DATA_2_INOUT ,
inout USB_DATA_3_INOUT ,
inout USB_DATA_4_INOUT ,
inout USB_DATA_5_INOUT ,
inout USB_DATA_6_INOUT ,
inout USB_DATA_7_INOUT ,
input USB_DIR_IN ,
input USB_FLAG_IN ,
input USB_MODE_IN ,
output USB_OE_OUT ,
output USB_PKTEND_OUT ,
output USB_WR_OUT ,
output VGA_BLUE_0_OUT ,
output VGA_BLUE_1_OUT ,
output VGA_GREEN_0_OUT ,
output VGA_GREEN_1_OUT ,
output VGA_GREEN_2_OUT ,
output VGA_HSYNC_OUT ,
output VGA_RED_0_OUT ,
output VGA_RED_1_OUT ,
output VGA_RED_2_OUT ,
output VGA_VSYNC_OUT
); |
wire [3:0] BTN = {BTN_3_IN, BTN_2_IN, BTN_1_IN, BTN_0_IN};
wire [7:0] SW = {SW_7_IN, SW_6_IN, SW_5_IN, SW_4_IN, SW_3_IN, SW_2_IN, SW_1_IN, SW_0_IN};
wire [7:0] LED;
assign LED_7_OUT = LED[7];
assign LED_6_OUT = LED[6];
assign LED_5_OUT = LED[5];
assign LED_4_OUT = LED[4];
assign LED_3_OUT = LED[3];
assign LED_2_OUT = LED[2];
assign LED_1_OUT = LED[1];
assign LED_0_OUT = LED[0];
wire [23:1] MEM_ADDR;
assign MEM_ADDR_23_OUT = MEM_ADDR[23];
assign MEM_ADDR_22_OUT = MEM_ADDR[22];
assign MEM_ADDR_21_OUT = MEM_ADDR[21];
assign MEM_ADDR_20_OUT = MEM_ADDR[20];
assign MEM_ADDR_19_OUT = MEM_ADDR[19];
assign MEM_ADDR_18_OUT = MEM_ADDR[18];
assign MEM_ADDR_17_OUT = MEM_ADDR[17];
assign MEM_ADDR_16_OUT = MEM_ADDR[16];
assign MEM_ADDR_15_OUT = MEM_ADDR[15];
assign MEM_ADDR_14_OUT = MEM_ADDR[14];
assign MEM_ADDR_13_OUT = MEM_ADDR[13];
assign MEM_ADDR_12_OUT = MEM_ADDR[12];
assign MEM_ADDR_11_OUT = MEM_ADDR[11];
assign MEM_ADDR_10_OUT = MEM_ADDR[10];
assign MEM_ADDR_9_OUT = MEM_ADDR[ 9];
assign MEM_ADDR_8_OUT = MEM_ADDR[ 8];
assign MEM_ADDR_7_OUT = MEM_ADDR[ 7];
assign MEM_ADDR_6_OUT = MEM_ADDR[ 6];
assign MEM_ADDR_5_OUT = MEM_ADDR[ 5];
assign MEM_ADDR_4_OUT = MEM_ADDR[ 4];
assign MEM_ADDR_3_OUT = MEM_ADDR[ 3];
assign MEM_ADDR_2_OUT = MEM_ADDR[ 2];
assign MEM_ADDR_1_OUT = MEM_ADDR[ 1];
wire [3:0] SSEG_AN;
assign SSEG_AN_0_OUT = SSEG_AN[0];
assign SSEG_AN_1_OUT = SSEG_AN[1];
assign SSEG_AN_2_OUT = SSEG_AN[2];
assign SSEG_AN_3_OUT = SSEG_AN[3];
wire [7:0] SSEG_K;
assign SSEG_K_0_OUT = SSEG_K[0];
assign SSEG_K_1_OUT = SSEG_K[1];
assign SSEG_K_2_OUT = SSEG_K[2];
assign SSEG_K_3_OUT = SSEG_K[3];
assign SSEG_K_4_OUT = SSEG_K[4];
assign SSEG_K_5_OUT = SSEG_K[5];
assign SSEG_K_6_OUT = SSEG_K[6];
assign SSEG_K_7_OUT = SSEG_K[7];
wire [1:0] USB_ADDR ;
assign USB_ADDR_0_OUT = USB_ADDR[0];
assign USB_ADDR_1_OUT = USB_ADDR[1];
wire [1:0] VGA_BLUE;
wire [2:0] VGA_GREEN;
wire [2:0] VGA_RED;
assign VGA_BLUE_0_OUT = VGA_BLUE[0];
assign VGA_BLUE_1_OUT = VGA_BLUE[1];
assign VGA_GREEN_0_OUT = VGA_GREEN[0];
assign VGA_GREEN_1_OUT = VGA_GREEN[1];
assign VGA_GREEN_2_OUT = VGA_GREEN[2];
assign VGA_RED_0_OUT = VGA_RED[0];
assign VGA_RED_1_OUT = VGA_RED[1];
assign VGA_RED_2_OUT = VGA_RED[2];
FPGA_BUS_TOP fpga_bus_top
(
.BTN_IN (BTN ),
.CLK_IN (CLK_IN ),
.EPP_ASTB_IN (EPP_ASTB_IN ),
.EPP_DSTB_IN (EPP_DSTB_IN ),
.EPP_WAIT_OUT (EPP_WAIT_OUT ),
.FLASH_CS_OUT (FLASH_CS_OUT ),
.FLASH_RP_OUT (FLASH_RP_OUT ),
.FLASH_ST_STS_IN (FLASH_ST_STS_IN ),
.LED_OUT (LED ),
.MEM_ADDR_OUT (MEM_ADDR ),
.MEM_DATA_INOUT ({MEM_DATA_15_INOUT, MEM_DATA_14_INOUT, MEM_DATA_13_INOUT, MEM_DATA_12_INOUT ,
MEM_DATA_11_INOUT, MEM_DATA_10_INOUT, MEM_DATA_9_INOUT , MEM_DATA_8_INOUT ,
MEM_DATA_7_INOUT , MEM_DATA_6_INOUT , MEM_DATA_5_INOUT , MEM_DATA_4_INOUT ,
MEM_DATA_3_INOUT , MEM_DATA_2_INOUT , MEM_DATA_1_INOUT , MEM_DATA_0_INOUT }),
.MEM_OE_OUT (MEM_OE_OUT ),
.MEM_WR_OUT (MEM_WR_OUT ),
.PS2_CLK_INOUT (PS2_CLK_INOUT ),
.PS2_DATA_INOUT (PS2_DATA_INOUT ),
.RAM_ADV_OUT (RAM_ADV_OUT ),
.RAM_CLK_OUT (RAM_CLK_OUT ),
.RAM_CRE_OUT (RAM_CRE_OUT ),
.RAM_CS_OUT (RAM_CS_OUT ),
.RAM_LB_OUT (RAM_LB_OUT ),
.RAM_UB_OUT (RAM_UB_OUT ),
.RAM_WAIT_IN (RAM_WAIT_IN ),
.RS232_RX_IN (RS232_RX_IN ),
.RS232_TX_INOUT (RS232_TX_INOUT ),
.SSEG_AN_OUT (SSEG_AN ),
.SSEG_K_OUT (SSEG_K ),
.SW_IN (SW ),
.USB_ADDR_OUT (USB_ADDR ),
.USB_CLK_IN (USB_CLK_IN ),
.USB_DATA_INOUT ({USB_DATA_7_INOUT ,
USB_DATA_6_INOUT ,
USB_DATA_5_INOUT ,
USB_DATA_4_INOUT ,
USB_DATA_3_INOUT ,
USB_DATA_2_INOUT ,
USB_DATA_1_INOUT ,
USB_DATA_0_INOUT } ),
.USB_DIR_IN (USB_DIR_IN ),
.USB_FLAG_IN (USB_FLAG_IN ),
.USB_MODE_IN (USB_MODE_IN ),
.USB_OE_OUT (USB_OE_OUT ),
.USB_PKTEND_OUT (USB_PKTEND_OUT ),
.USB_WR_OUT (USB_WR_OUT ),
.VGA_BLUE_OUT (VGA_BLUE ),
.VGA_GREEN_OUT (VGA_GREEN ),
.VGA_HSYNC_OUT (VGA_HSYNC_OUT ),
.VGA_RED_OUT (VGA_RED ),
.VGA_VSYNC_OUT (VGA_VSYNC_OUT )
);
endmodule | 1 |
138,304 | data/full_repos/permissive/83270534/common/rtl/async_fifo.v | 83,270,534 | async_fifo.v | v | 77 | 89 | [] | [] | [] | [(3, 76)] | null | null | 1: b"%Error: data/full_repos/permissive/83270534/common/rtl/async_fifo.v:18: Cannot find file containing module: 'ASYNC_FIFO_SYNC_R2W'\n ASYNC_FIFO_SYNC_R2W \n ^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/common/rtl,data/full_repos/permissive/83270534/ASYNC_FIFO_SYNC_R2W\n data/full_repos/permissive/83270534/common/rtl,data/full_repos/permissive/83270534/ASYNC_FIFO_SYNC_R2W.v\n data/full_repos/permissive/83270534/common/rtl,data/full_repos/permissive/83270534/ASYNC_FIFO_SYNC_R2W.sv\n ASYNC_FIFO_SYNC_R2W\n ASYNC_FIFO_SYNC_R2W.v\n ASYNC_FIFO_SYNC_R2W.sv\n obj_dir/ASYNC_FIFO_SYNC_R2W\n obj_dir/ASYNC_FIFO_SYNC_R2W.v\n obj_dir/ASYNC_FIFO_SYNC_R2W.sv\n%Error: data/full_repos/permissive/83270534/common/rtl/async_fifo.v:28: Cannot find file containing module: 'ASYNC_FIFO_SYNC_W2R'\n ASYNC_FIFO_SYNC_W2R \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/common/rtl/async_fifo.v:38: Cannot find file containing module: 'ASYNC_FIFO_FIFOMEM'\n ASYNC_FIFO_FIFOMEM \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/common/rtl/async_fifo.v:52: Cannot find file containing module: 'ASYNC_FIFO_RPTR_EMPTY'\n ASYNC_FIFO_RPTR_EMPTY\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/common/rtl/async_fifo.v:64: Cannot find file containing module: 'ASYNC_FIFO_WPTR_FULL'\n ASYNC_FIFO_WPTR_FULL \n ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n" | 302,145 | module | module ASYNC_FIFO
#(parameter DSIZE = 8,
parameter ASIZE = 4)
(
output [DSIZE-1:0] rdata,
output wfull,
output rempty,
input [DSIZE-1:0] wdata,
input winc, wclk, wrst_n,
input rinc, rclk, rrst_n
);
wire [ASIZE-1:0] waddr, raddr;
wire [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr;
ASYNC_FIFO_SYNC_R2W
#(.ADDRSIZE (ASIZE))
sync_r2w
(
.wq2_rptr (wq2_rptr ),
.rptr (rptr ),
.wclk (wclk ),
.wrst_n (wrst_n )
);
ASYNC_FIFO_SYNC_W2R
#(.ADDRSIZE (ASIZE))
sync_w2r
(
.rq2_wptr (rq2_wptr ),
.wptr (wptr ),
.rclk (rclk ),
.rrst_n (rrst_n )
);
ASYNC_FIFO_FIFOMEM
#(.DATASIZE (DSIZE),
.ADDRSIZE (ASIZE) )
fifomem
(
.rdata (rdata ),
.wdata (wdata ),
.waddr (waddr ),
.raddr (raddr ),
.wclken (winc ),
.wfull (wfull ),
.wclk (wclk )
);
ASYNC_FIFO_RPTR_EMPTY
#(.ADDRSIZE (ASIZE) )
rptr_empty
(.rempty (rempty ),
.raddr (raddr ),
.rptr (rptr ),
.rq2_wptr (rq2_wptr ),
.rinc (rinc ),
.rclk (rclk ),
.rrst_n (rrst_n )
);
ASYNC_FIFO_WPTR_FULL
#(.ADDRSIZE (ASIZE) )
wptr_full
(.wfull (wfull ),
.waddr (waddr ),
.wptr (wptr ),
.wq2_rptr (wq2_rptr ),
.winc (winc ),
.wclk (wclk ),
.wrst_n (wrst_n )
);
endmodule | module ASYNC_FIFO
#(parameter DSIZE = 8,
parameter ASIZE = 4)
(
output [DSIZE-1:0] rdata,
output wfull,
output rempty,
input [DSIZE-1:0] wdata,
input winc, wclk, wrst_n,
input rinc, rclk, rrst_n
); |
wire [ASIZE-1:0] waddr, raddr;
wire [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr;
ASYNC_FIFO_SYNC_R2W
#(.ADDRSIZE (ASIZE))
sync_r2w
(
.wq2_rptr (wq2_rptr ),
.rptr (rptr ),
.wclk (wclk ),
.wrst_n (wrst_n )
);
ASYNC_FIFO_SYNC_W2R
#(.ADDRSIZE (ASIZE))
sync_w2r
(
.rq2_wptr (rq2_wptr ),
.wptr (wptr ),
.rclk (rclk ),
.rrst_n (rrst_n )
);
ASYNC_FIFO_FIFOMEM
#(.DATASIZE (DSIZE),
.ADDRSIZE (ASIZE) )
fifomem
(
.rdata (rdata ),
.wdata (wdata ),
.waddr (waddr ),
.raddr (raddr ),
.wclken (winc ),
.wfull (wfull ),
.wclk (wclk )
);
ASYNC_FIFO_RPTR_EMPTY
#(.ADDRSIZE (ASIZE) )
rptr_empty
(.rempty (rempty ),
.raddr (raddr ),
.rptr (rptr ),
.rq2_wptr (rq2_wptr ),
.rinc (rinc ),
.rclk (rclk ),
.rrst_n (rrst_n )
);
ASYNC_FIFO_WPTR_FULL
#(.ADDRSIZE (ASIZE) )
wptr_full
(.wfull (wfull ),
.waddr (waddr ),
.wptr (wptr ),
.wq2_rptr (wq2_rptr ),
.winc (winc ),
.wclk (wclk ),
.wrst_n (wrst_n )
);
endmodule | 1 |
138,306 | data/full_repos/permissive/83270534/common/rtl/async_fifo_rptr_empty.v | 83,270,534 | async_fifo_rptr_empty.v | v | 35 | 73 | [] | [] | [] | [(3, 32)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/83270534/common/rtl/async_fifo_rptr_empty.v:27: Signal definition not found, creating implicitly: \'rempty_val\'\n : ... Suggested alternative: \'rempty\'\n assign rempty_val = (rgraynext == rq2_wptr);\n ^~~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/83270534/common/rtl/async_fifo_rptr_empty.v:21: Operator AND expects 5 bits on the LHS, but LHS\'s VARREF \'rinc\' generates 1 bits.\n : ... In instance ASYNC_FIFO_RPTR_EMPTY\n assign rbinnext = rbin + (rinc & ~rempty);\n ^\n%Warning-WIDTH: data/full_repos/permissive/83270534/common/rtl/async_fifo_rptr_empty.v:21: Operator NOT expects 5 bits on the LHS, but LHS\'s VARREF \'rempty\' generates 1 bits.\n : ... In instance ASYNC_FIFO_RPTR_EMPTY\n assign rbinnext = rbin + (rinc & ~rempty);\n ^\n%Error: Exiting due to 3 warning(s)\n' | 302,147 | module | module ASYNC_FIFO_RPTR_EMPTY #(parameter ADDRSIZE = 4)
(output reg rempty,
output [ADDRSIZE-1:0] raddr,
output reg [ADDRSIZE :0] rptr,
input [ADDRSIZE :0] rq2_wptr,
input rinc, rclk, rrst_n);
reg [ADDRSIZE:0] rbin;
wire [ADDRSIZE:0] rgraynext, rbinnext;
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) {rbin, rptr} <= 0;
else {rbin, rptr} <= {rbinnext, rgraynext};
assign raddr = rbin[ADDRSIZE-1:0];
assign rbinnext = rbin + (rinc & ~rempty);
assign rgraynext = (rbinnext>>1) ^ rbinnext;
assign rempty_val = (rgraynext == rq2_wptr);
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) rempty <= 1'b1;
else rempty <= rempty_val;
endmodule | module ASYNC_FIFO_RPTR_EMPTY #(parameter ADDRSIZE = 4)
(output reg rempty,
output [ADDRSIZE-1:0] raddr,
output reg [ADDRSIZE :0] rptr,
input [ADDRSIZE :0] rq2_wptr,
input rinc, rclk, rrst_n); |
reg [ADDRSIZE:0] rbin;
wire [ADDRSIZE:0] rgraynext, rbinnext;
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) {rbin, rptr} <= 0;
else {rbin, rptr} <= {rbinnext, rgraynext};
assign raddr = rbin[ADDRSIZE-1:0];
assign rbinnext = rbin + (rinc & ~rempty);
assign rgraynext = (rbinnext>>1) ^ rbinnext;
assign rempty_val = (rgraynext == rq2_wptr);
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) rempty <= 1'b1;
else rempty <= rempty_val;
endmodule | 1 |
138,307 | data/full_repos/permissive/83270534/common/rtl/async_fifo_sync_r2w.v | 83,270,534 | async_fifo_sync_r2w.v | v | 17 | 66 | [] | [] | [] | [(3, 15)] | null | data/verilator_xmls/168260ba-9d9e-465a-807f-0c43849043c3.xml | null | 302,148 | module | module ASYNC_FIFO_SYNC_R2W
#(parameter ADDRSIZE = 4)
(output reg [ADDRSIZE:0] wq2_rptr,
input [ADDRSIZE:0] rptr,
input wclk, wrst_n);
reg [ADDRSIZE:0] wq1_rptr;
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) {wq2_rptr,wq1_rptr} <= 0;
else {wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr};
endmodule | module ASYNC_FIFO_SYNC_R2W
#(parameter ADDRSIZE = 4)
(output reg [ADDRSIZE:0] wq2_rptr,
input [ADDRSIZE:0] rptr,
input wclk, wrst_n); |
reg [ADDRSIZE:0] wq1_rptr;
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) {wq2_rptr,wq1_rptr} <= 0;
else {wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr};
endmodule | 1 |
138,309 | data/full_repos/permissive/83270534/common/rtl/spram.v | 83,270,534 | spram.v | v | 70 | 132 | [] | [] | [] | [(40, 70)] | null | data/verilator_xmls/12fad145-072f-4192-af69-95f7d83f3183.xml | null | 302,152 | module | module SPRAM
#(parameter ADDR_WIDTH = 9 ,
parameter DATA_WIDTH = 32
)
(
input CLK ,
input EN ,
input WRITE_EN_IN ,
input [ADDR_WIDTH-1:0] ADDR_IN ,
input [DATA_WIDTH-1:0] WRITE_DATA_IN ,
output reg [DATA_WIDTH-1:0] READ_DATA_OUT
);
reg [DATA_WIDTH-1:0] RamArray [(2 ** ADDR_WIDTH)-1:0];
always @(posedge CLK)
begin
if (EN)
begin
if (WRITE_EN_IN)
begin
RamArray[ADDR_IN] <= WRITE_DATA_IN;
READ_DATA_OUT <= WRITE_DATA_IN;
end
else
READ_DATA_OUT <= RamArray[ADDR_IN];
end
end
endmodule | module SPRAM
#(parameter ADDR_WIDTH = 9 ,
parameter DATA_WIDTH = 32
)
(
input CLK ,
input EN ,
input WRITE_EN_IN ,
input [ADDR_WIDTH-1:0] ADDR_IN ,
input [DATA_WIDTH-1:0] WRITE_DATA_IN ,
output reg [DATA_WIDTH-1:0] READ_DATA_OUT
); |
reg [DATA_WIDTH-1:0] RamArray [(2 ** ADDR_WIDTH)-1:0];
always @(posedge CLK)
begin
if (EN)
begin
if (WRITE_EN_IN)
begin
RamArray[ADDR_IN] <= WRITE_DATA_IN;
READ_DATA_OUT <= WRITE_DATA_IN;
end
else
READ_DATA_OUT <= RamArray[ADDR_IN];
end
end
endmodule | 1 |
138,310 | data/full_repos/permissive/83270534/common/rtl/sync_fifo.v | 83,270,534 | sync_fifo.v | v | 231 | 129 | [] | [] | [] | [(1, 228)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/83270534/common/rtl/sync_fifo.v:114: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n : ... In instance SYNC_FIFO\n WritePtr <= {WPW{1\'b0}};\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/83270534/common/rtl/sync_fifo.v:118: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n : ... In instance SYNC_FIFO\n WritePtr <= {WPW{1\'b0}};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/common/rtl/sync_fifo.v:134: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n : ... In instance SYNC_FIFO\n ReadPtr <= {RPW{1\'b0}};\n ^~\n%Warning-WIDTH: data/full_repos/permissive/83270534/common/rtl/sync_fifo.v:138: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n : ... In instance SYNC_FIFO\n ReadPtr <= {RPW{1\'b0}};\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 302,153 | module | module SYNC_FIFO
#(
parameter D_P2 = 4 ,
parameter BW = 8 ,
parameter WWM = 1 ,
parameter RWM = 1 ,
parameter USE_RAM = 0
)
(
input WR_CLK ,
input RD_CLK ,
input RST_SYNC ,
input RST_ASYNC ,
input WRITE_EN_IN ,
input [(BW * WWM)-1:0] WRITE_DATA_IN ,
output WRITE_FULL_OUT ,
input READ_EN_IN ,
output [(BW * RWM)-1:0] READ_DATA_OUT ,
output READ_EMPTY_OUT
);
parameter D = (2 ** D_P2) ;
parameter RD = (2 ** (D_P2 + WWM - RWM)) ;
parameter WW = BW * WWM ;
parameter RW = BW * RWM ;
parameter WPW = D_P2 ;
parameter RPW = D_P2 + WWM - RWM ;
reg [WPW :0] WritePtr ;
wire [WPW-1:0] WritePtrWrap = WritePtr[WPW-1:0] ;
reg [RPW :0] ReadPtr ;
wire [RPW-1:0] ReadPtrWrap = ReadPtr[RPW-1:0] ;
wire WriteEn ;
wire ReadEn ;
wire WriteFull ;
wire ReadEmpty ;
wire PtrMatch ;
generate if (WPW > RPW)
begin : WRITE_GT_READ
assign PtrMatch = (WritePtr[WPW-1:WPW-RPW] == ReadPtr[RPW-1:0]);
end
else if (WPW == RPW)
begin : WRITE_EQ_READ
assign PtrMatch = (WritePtr[WPW-1:0] == ReadPtr[RPW-1:0]);
end
else if (WPW < RPW)
begin : WRITE_LT_READ
assign PtrMatch = (WritePtr[WPW-1:0] == ReadPtr[RPW-1:RPW-WPW]);
end
endgenerate
assign WriteEn = WRITE_EN_IN & ~WriteFull;
assign ReadEn = READ_EN_IN & ~ReadEmpty;
assign WriteFull = ((WritePtr[WPW] ^ ReadPtr[RPW]) && PtrMatch);
assign ReadEmpty = ((WritePtr[WPW] == ReadPtr[RPW]) && PtrMatch);
assign WRITE_FULL_OUT = WriteFull;
assign READ_EMPTY_OUT = ReadEmpty;
`ifdef REPORT_FIFO
initial
begin
$display("");
$display("[INFO ] FIFO parameters for %m");
$display("[INFO ] --------------------------------------------");
$display("[INFO ] SIZE = %03d (bits)", (D*WW));
$display("[INFO ] D_P2 = %03d (Depth as power-of-2, units of WW = %03d)", D_P2, WW);
$display("[INFO ] D = %03d (Write 2d array depth, units of WW = %03d)", D, WW);
$display("[INFO ] RD = %03d (Read 2d array depth, units of RW = %03d)", RD, RW);
$display("[INFO ] BW = %03d (Base width for read and write data widths)", BW);
$display("[INFO ] WWM = %03d (Write width multiplier)" , WWM);
$display("[INFO ] RWM = %03d (Read width multiplier)" , RWM);
$display("[INFO ] WW = %03d (Write data width in bits)" , WW);
$display("[INFO ] RW = %03d (Read data width in bits)", RW);
$display("[INFO ] WPW = %03d (Write Pointer Width - in units of WW = %03d)", WPW, WW);
$display("[INFO ] RPW = %03d (Read Pointer Width - in units of RW = %03d)", RPW, RW);
$display("");
end
`endif
always @(posedge WR_CLK or posedge RST_ASYNC)
begin
if (RST_ASYNC)
begin
WritePtr <= {WPW{1'b0}};
end
else if (RST_SYNC)
begin
WritePtr <= {WPW{1'b0}};
end
else
begin
if (WriteEn)
begin
WritePtr <= WritePtr + 1;
end
end
end
always @(posedge RD_CLK or posedge RST_ASYNC)
begin
if (RST_ASYNC)
begin
ReadPtr <= {RPW{1'b0}};
end
else if (RST_SYNC)
begin
ReadPtr <= {RPW{1'b0}};
end
else
begin
if (ReadEn)
begin
ReadPtr <= ReadPtr + 1;
end
end
end
genvar FifoVar;
genvar i, j, k;
genvar l, m;
generate if (!USE_RAM)
begin : FIFO_REGS_STORAGE
reg [WW-1:0] FifoDataReg [D-1:0];
wire [(D*WW)-1:0] ReadDataArray ;
wire [RW-1:0] ReadDataMem [RD-1:0];
for (i = 0 ; i < D ; i = i + 1)
begin : FIFO_WRITE_DATA_REG
always @(posedge WR_CLK or posedge RST_ASYNC)
begin
if (RST_ASYNC)
begin
FifoDataReg[i] <= {WW{1'b0}};
end
else if (RST_SYNC)
begin
FifoDataReg[i] <= {WW{1'b0}};
end
else
begin
if (WriteEn && (i == WritePtr[WPW-1:0]))
begin
FifoDataReg[i] <= WRITE_DATA_IN;
end
end
end
end
for (j = 0 ; j < D ; j = j + 1)
begin : READ_DATA_WORD_FLATTEN
for (k = 0 ; k < WW ; k = k + 1)
begin : READ_DATA_ARRAY_FILL
assign ReadDataArray[(j*WW) + k] = FifoDataReg[j][k];
end
end
for (l = 0 ; l < RD; l = l + 1)
begin : READ_DATA_WORD_PACK
for (m = 0 ; m < RW ; m = m + 1)
begin : READ_DATA_MEM_PACK
assign ReadDataMem[l][m] = ReadDataArray[(l * RW)+m];
end
end
assign READ_DATA_OUT = ReadDataMem[ReadPtr[RPW-1:0]];
end
else
begin : FIFO_RAM_STORAGE
end
endgenerate
endmodule | module SYNC_FIFO
#(
parameter D_P2 = 4 ,
parameter BW = 8 ,
parameter WWM = 1 ,
parameter RWM = 1 ,
parameter USE_RAM = 0
)
(
input WR_CLK ,
input RD_CLK ,
input RST_SYNC ,
input RST_ASYNC ,
input WRITE_EN_IN ,
input [(BW * WWM)-1:0] WRITE_DATA_IN ,
output WRITE_FULL_OUT ,
input READ_EN_IN ,
output [(BW * RWM)-1:0] READ_DATA_OUT ,
output READ_EMPTY_OUT
); |
parameter D = (2 ** D_P2) ;
parameter RD = (2 ** (D_P2 + WWM - RWM)) ;
parameter WW = BW * WWM ;
parameter RW = BW * RWM ;
parameter WPW = D_P2 ;
parameter RPW = D_P2 + WWM - RWM ;
reg [WPW :0] WritePtr ;
wire [WPW-1:0] WritePtrWrap = WritePtr[WPW-1:0] ;
reg [RPW :0] ReadPtr ;
wire [RPW-1:0] ReadPtrWrap = ReadPtr[RPW-1:0] ;
wire WriteEn ;
wire ReadEn ;
wire WriteFull ;
wire ReadEmpty ;
wire PtrMatch ;
generate if (WPW > RPW)
begin : WRITE_GT_READ
assign PtrMatch = (WritePtr[WPW-1:WPW-RPW] == ReadPtr[RPW-1:0]);
end
else if (WPW == RPW)
begin : WRITE_EQ_READ
assign PtrMatch = (WritePtr[WPW-1:0] == ReadPtr[RPW-1:0]);
end
else if (WPW < RPW)
begin : WRITE_LT_READ
assign PtrMatch = (WritePtr[WPW-1:0] == ReadPtr[RPW-1:RPW-WPW]);
end
endgenerate
assign WriteEn = WRITE_EN_IN & ~WriteFull;
assign ReadEn = READ_EN_IN & ~ReadEmpty;
assign WriteFull = ((WritePtr[WPW] ^ ReadPtr[RPW]) && PtrMatch);
assign ReadEmpty = ((WritePtr[WPW] == ReadPtr[RPW]) && PtrMatch);
assign WRITE_FULL_OUT = WriteFull;
assign READ_EMPTY_OUT = ReadEmpty;
`ifdef REPORT_FIFO
initial
begin
$display("");
$display("[INFO ] FIFO parameters for %m");
$display("[INFO ] --------------------------------------------");
$display("[INFO ] SIZE = %03d (bits)", (D*WW));
$display("[INFO ] D_P2 = %03d (Depth as power-of-2, units of WW = %03d)", D_P2, WW);
$display("[INFO ] D = %03d (Write 2d array depth, units of WW = %03d)", D, WW);
$display("[INFO ] RD = %03d (Read 2d array depth, units of RW = %03d)", RD, RW);
$display("[INFO ] BW = %03d (Base width for read and write data widths)", BW);
$display("[INFO ] WWM = %03d (Write width multiplier)" , WWM);
$display("[INFO ] RWM = %03d (Read width multiplier)" , RWM);
$display("[INFO ] WW = %03d (Write data width in bits)" , WW);
$display("[INFO ] RW = %03d (Read data width in bits)", RW);
$display("[INFO ] WPW = %03d (Write Pointer Width - in units of WW = %03d)", WPW, WW);
$display("[INFO ] RPW = %03d (Read Pointer Width - in units of RW = %03d)", RPW, RW);
$display("");
end
`endif
always @(posedge WR_CLK or posedge RST_ASYNC)
begin
if (RST_ASYNC)
begin
WritePtr <= {WPW{1'b0}};
end
else if (RST_SYNC)
begin
WritePtr <= {WPW{1'b0}};
end
else
begin
if (WriteEn)
begin
WritePtr <= WritePtr + 1;
end
end
end
always @(posedge RD_CLK or posedge RST_ASYNC)
begin
if (RST_ASYNC)
begin
ReadPtr <= {RPW{1'b0}};
end
else if (RST_SYNC)
begin
ReadPtr <= {RPW{1'b0}};
end
else
begin
if (ReadEn)
begin
ReadPtr <= ReadPtr + 1;
end
end
end
genvar FifoVar;
genvar i, j, k;
genvar l, m;
generate if (!USE_RAM)
begin : FIFO_REGS_STORAGE
reg [WW-1:0] FifoDataReg [D-1:0];
wire [(D*WW)-1:0] ReadDataArray ;
wire [RW-1:0] ReadDataMem [RD-1:0];
for (i = 0 ; i < D ; i = i + 1)
begin : FIFO_WRITE_DATA_REG
always @(posedge WR_CLK or posedge RST_ASYNC)
begin
if (RST_ASYNC)
begin
FifoDataReg[i] <= {WW{1'b0}};
end
else if (RST_SYNC)
begin
FifoDataReg[i] <= {WW{1'b0}};
end
else
begin
if (WriteEn && (i == WritePtr[WPW-1:0]))
begin
FifoDataReg[i] <= WRITE_DATA_IN;
end
end
end
end
for (j = 0 ; j < D ; j = j + 1)
begin : READ_DATA_WORD_FLATTEN
for (k = 0 ; k < WW ; k = k + 1)
begin : READ_DATA_ARRAY_FILL
assign ReadDataArray[(j*WW) + k] = FifoDataReg[j][k];
end
end
for (l = 0 ; l < RD; l = l + 1)
begin : READ_DATA_WORD_PACK
for (m = 0 ; m < RW ; m = m + 1)
begin : READ_DATA_MEM_PACK
assign ReadDataMem[l][m] = ReadDataArray[(l * RW)+m];
end
end
assign READ_DATA_OUT = ReadDataMem[ReadPtr[RPW-1:0]];
end
else
begin : FIFO_RAM_STORAGE
end
endgenerate
endmodule | 1 |
138,311 | data/full_repos/permissive/83270534/common/rtl/wb_arb_2m_1s.v | 83,270,534 | wb_arb_2m_1s.v | v | 234 | 141 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/83270534/common/rtl/wb_arb_2m_1s.v:86: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'WbAdr\' generates 30 bits.\n : ... In instance WB_ARB_2M_1S\n assign WB_M0_ADR_OUT = WbAdr ;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/83270534/common/rtl/wb_arb_2m_1s.v:187: Operator ASSIGN expects 30 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n : ... In instance WB_ARB_2M_1S\n WbAdr = 32\'h0000_0000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/83270534/common/rtl/wb_arb_2m_1s.v:199: Operator ASSIGN expects 30 bits on the Assign RHS, but Assign RHS\'s VARREF \'WB_SL0_ADR_IN\' generates 32 bits.\n : ... In instance WB_ARB_2M_1S\n WbAdr = WB_SL0_ADR_IN ;\n ^\n%Warning-WIDTH: data/full_repos/permissive/83270534/common/rtl/wb_arb_2m_1s.v:211: Operator ASSIGN expects 30 bits on the Assign RHS, but Assign RHS\'s VARREF \'WB_SL1_ADR_IN\' generates 32 bits.\n : ... In instance WB_ARB_2M_1S\n WbAdr = WB_SL1_ADR_IN ;\n ^\n%Error: Exiting due to 4 warning(s)\n' | 302,154 | module | module WB_ARB_2M_1S
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
input [31:0] WB_SL0_ADR_IN ,
input WB_SL0_CYC_IN ,
input WB_SL0_STB_IN ,
input WB_SL0_WE_IN ,
input [ 3:0] WB_SL0_SEL_IN ,
input [ 2:0] WB_SL0_CTI_IN ,
input [ 1:0] WB_SL0_BTE_IN ,
output WB_SL0_STALL_OUT ,
output WB_SL0_ACK_OUT ,
output WB_SL0_ERR_OUT ,
output [31:0] WB_SL0_RD_DAT_OUT ,
input [31:0] WB_SL0_WR_DAT_IN ,
input [31:0] WB_SL1_ADR_IN ,
input WB_SL1_CYC_IN ,
input WB_SL1_STB_IN ,
input WB_SL1_WE_IN ,
input [ 3:0] WB_SL1_SEL_IN ,
input [ 2:0] WB_SL1_CTI_IN ,
input [ 1:0] WB_SL1_BTE_IN ,
output WB_SL1_STALL_OUT ,
output WB_SL1_ACK_OUT ,
output WB_SL1_ERR_OUT ,
output [31:0] WB_SL1_RD_DAT_OUT ,
input [31:0] WB_SL1_WR_DAT_IN ,
output [31:0] WB_M0_ADR_OUT ,
output WB_M0_CYC_OUT ,
output WB_M0_STB_OUT ,
output WB_M0_WE_OUT ,
output [ 3:0] WB_M0_SEL_OUT ,
output [ 2:0] WB_M0_CTI_OUT ,
output [ 1:0] WB_M0_BTE_OUT ,
input WB_M0_STALL_IN ,
input WB_M0_ACK_IN ,
input WB_M0_ERR_IN ,
input [31:0] WB_M0_RD_DAT_IN ,
output [31:0] WB_M0_WR_DAT_OUT
);
reg [1:0] WbArbGnt ;
reg [1:0] WbArbGntReg ;
reg WbArbGntRegEn ;
reg [31:2] WbAdr ;
reg WbCyc ;
reg WbStb ;
reg WbWe ;
reg [ 3:0] WbSel ;
reg [ 2:0] WbCti ;
reg [ 1:0] WbBte ;
reg [31:0] WbWrDat ;
reg WbStall ;
reg WbAck ;
reg WbErr ;
reg [31:0] WbRdDat ;
assign WB_M0_ADR_OUT = WbAdr ;
assign WB_M0_CYC_OUT = WbCyc ;
assign WB_M0_STB_OUT = WbStb ;
assign WB_M0_WE_OUT = WbWe ;
assign WB_M0_SEL_OUT = WbSel ;
assign WB_M0_CTI_OUT = WbCti ;
assign WB_M0_BTE_OUT = WbBte ;
assign WB_M0_WR_DAT_OUT = WbWrDat ;
assign WB_SL0_STALL_OUT = (WbArbGntReg == 2'b01) ? WB_M0_STALL_IN : WB_SL0_CYC_IN ;
assign WB_SL0_ACK_OUT = (WbArbGntReg == 2'b01) ? WB_M0_ACK_IN : 1'b0 ;
assign WB_SL0_ERR_OUT = (WbArbGntReg == 2'b01) ? WB_M0_ERR_IN : 1'b0 ;
assign WB_SL0_RD_DAT_OUT = (WbArbGntReg == 2'b01) ? WB_M0_RD_DAT_IN : 32'h0000_0000 ;
assign WB_SL1_STALL_OUT = (WbArbGntReg == 2'b10) ? WB_M0_STALL_IN : WB_SL1_CYC_IN ;
assign WB_SL1_ACK_OUT = (WbArbGntReg == 2'b10) ? WB_M0_ACK_IN : 1'b0 ;
assign WB_SL1_ERR_OUT = (WbArbGntReg == 2'b10) ? WB_M0_ERR_IN : 1'b0 ;
assign WB_SL1_RD_DAT_OUT = (WbArbGntReg == 2'b10) ? WB_M0_RD_DAT_IN : 32'h0000_0000 ;
always @*
begin : GNT_DECODE
WbArbGntRegEn = 1'b0;
WbArbGnt = 2'b00;
if ((2'b00 == WbArbGntReg) && (WB_SL0_CYC_IN || WB_SL1_CYC_IN))
begin
WbArbGntRegEn = 1'b1;
if (WB_SL0_CYC_IN)
begin
WbArbGnt = 2'b01;
end
else if (WB_SL1_CYC_IN)
begin
WbArbGnt = 2'b10;
end
end
else if ((2'b01 == WbArbGntReg) && !WB_SL0_CYC_IN)
begin
WbArbGntRegEn = 1'b1;
if (WB_SL1_CYC_IN)
begin
WbArbGnt = 2'b10;
end
else
begin
WbArbGnt = 2'b00;
end
end
else if ((2'b10 == WbArbGntReg) && !WB_SL1_CYC_IN)
begin
WbArbGntRegEn = 1'b1;
if (WB_SL0_CYC_IN)
begin
WbArbGnt = 2'b01;
end
else
begin
WbArbGnt = 2'b00;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : GNT_REG
if (RST_ASYNC)
begin
WbArbGntReg <= 2'b00;
end
else if (RST_SYNC)
begin
WbArbGntReg <= 2'b00;
end
else if (EN && WbArbGntRegEn)
begin
WbArbGntReg <= WbArbGnt;
end
end
always @(*)
begin : MASTER_TO_SLAVE_MUX
WbAdr = 32'h0000_0000;
WbCyc = 1'b0;
WbStb = 1'b0;
WbWe = 1'b0;
WbSel = 4'b0000;
WbCti = 3'b000;
WbBte = 2'b00;
WbWrDat = 32'h0000_0000;
case (WbArbGntReg)
2'b01 :
begin
WbAdr = WB_SL0_ADR_IN ;
WbCyc = WB_SL0_CYC_IN ;
WbStb = WB_SL0_STB_IN ;
WbWe = WB_SL0_WE_IN ;
WbSel = WB_SL0_SEL_IN ;
WbCti = WB_SL0_CTI_IN ;
WbBte = WB_SL0_BTE_IN ;
WbWrDat = WB_SL0_WR_DAT_IN ;
end
2'b10 :
begin
WbAdr = WB_SL1_ADR_IN ;
WbCyc = WB_SL1_CYC_IN ;
WbStb = WB_SL1_STB_IN ;
WbWe = WB_SL1_WE_IN ;
WbSel = WB_SL1_SEL_IN ;
WbCti = WB_SL1_CTI_IN ;
WbBte = WB_SL1_BTE_IN ;
WbWrDat = WB_SL1_WR_DAT_IN ;
end
endcase
end
endmodule | module WB_ARB_2M_1S
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
input [31:0] WB_SL0_ADR_IN ,
input WB_SL0_CYC_IN ,
input WB_SL0_STB_IN ,
input WB_SL0_WE_IN ,
input [ 3:0] WB_SL0_SEL_IN ,
input [ 2:0] WB_SL0_CTI_IN ,
input [ 1:0] WB_SL0_BTE_IN ,
output WB_SL0_STALL_OUT ,
output WB_SL0_ACK_OUT ,
output WB_SL0_ERR_OUT ,
output [31:0] WB_SL0_RD_DAT_OUT ,
input [31:0] WB_SL0_WR_DAT_IN ,
input [31:0] WB_SL1_ADR_IN ,
input WB_SL1_CYC_IN ,
input WB_SL1_STB_IN ,
input WB_SL1_WE_IN ,
input [ 3:0] WB_SL1_SEL_IN ,
input [ 2:0] WB_SL1_CTI_IN ,
input [ 1:0] WB_SL1_BTE_IN ,
output WB_SL1_STALL_OUT ,
output WB_SL1_ACK_OUT ,
output WB_SL1_ERR_OUT ,
output [31:0] WB_SL1_RD_DAT_OUT ,
input [31:0] WB_SL1_WR_DAT_IN ,
output [31:0] WB_M0_ADR_OUT ,
output WB_M0_CYC_OUT ,
output WB_M0_STB_OUT ,
output WB_M0_WE_OUT ,
output [ 3:0] WB_M0_SEL_OUT ,
output [ 2:0] WB_M0_CTI_OUT ,
output [ 1:0] WB_M0_BTE_OUT ,
input WB_M0_STALL_IN ,
input WB_M0_ACK_IN ,
input WB_M0_ERR_IN ,
input [31:0] WB_M0_RD_DAT_IN ,
output [31:0] WB_M0_WR_DAT_OUT
); |
reg [1:0] WbArbGnt ;
reg [1:0] WbArbGntReg ;
reg WbArbGntRegEn ;
reg [31:2] WbAdr ;
reg WbCyc ;
reg WbStb ;
reg WbWe ;
reg [ 3:0] WbSel ;
reg [ 2:0] WbCti ;
reg [ 1:0] WbBte ;
reg [31:0] WbWrDat ;
reg WbStall ;
reg WbAck ;
reg WbErr ;
reg [31:0] WbRdDat ;
assign WB_M0_ADR_OUT = WbAdr ;
assign WB_M0_CYC_OUT = WbCyc ;
assign WB_M0_STB_OUT = WbStb ;
assign WB_M0_WE_OUT = WbWe ;
assign WB_M0_SEL_OUT = WbSel ;
assign WB_M0_CTI_OUT = WbCti ;
assign WB_M0_BTE_OUT = WbBte ;
assign WB_M0_WR_DAT_OUT = WbWrDat ;
assign WB_SL0_STALL_OUT = (WbArbGntReg == 2'b01) ? WB_M0_STALL_IN : WB_SL0_CYC_IN ;
assign WB_SL0_ACK_OUT = (WbArbGntReg == 2'b01) ? WB_M0_ACK_IN : 1'b0 ;
assign WB_SL0_ERR_OUT = (WbArbGntReg == 2'b01) ? WB_M0_ERR_IN : 1'b0 ;
assign WB_SL0_RD_DAT_OUT = (WbArbGntReg == 2'b01) ? WB_M0_RD_DAT_IN : 32'h0000_0000 ;
assign WB_SL1_STALL_OUT = (WbArbGntReg == 2'b10) ? WB_M0_STALL_IN : WB_SL1_CYC_IN ;
assign WB_SL1_ACK_OUT = (WbArbGntReg == 2'b10) ? WB_M0_ACK_IN : 1'b0 ;
assign WB_SL1_ERR_OUT = (WbArbGntReg == 2'b10) ? WB_M0_ERR_IN : 1'b0 ;
assign WB_SL1_RD_DAT_OUT = (WbArbGntReg == 2'b10) ? WB_M0_RD_DAT_IN : 32'h0000_0000 ;
always @*
begin : GNT_DECODE
WbArbGntRegEn = 1'b0;
WbArbGnt = 2'b00;
if ((2'b00 == WbArbGntReg) && (WB_SL0_CYC_IN || WB_SL1_CYC_IN))
begin
WbArbGntRegEn = 1'b1;
if (WB_SL0_CYC_IN)
begin
WbArbGnt = 2'b01;
end
else if (WB_SL1_CYC_IN)
begin
WbArbGnt = 2'b10;
end
end
else if ((2'b01 == WbArbGntReg) && !WB_SL0_CYC_IN)
begin
WbArbGntRegEn = 1'b1;
if (WB_SL1_CYC_IN)
begin
WbArbGnt = 2'b10;
end
else
begin
WbArbGnt = 2'b00;
end
end
else if ((2'b10 == WbArbGntReg) && !WB_SL1_CYC_IN)
begin
WbArbGntRegEn = 1'b1;
if (WB_SL0_CYC_IN)
begin
WbArbGnt = 2'b01;
end
else
begin
WbArbGnt = 2'b00;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : GNT_REG
if (RST_ASYNC)
begin
WbArbGntReg <= 2'b00;
end
else if (RST_SYNC)
begin
WbArbGntReg <= 2'b00;
end
else if (EN && WbArbGntRegEn)
begin
WbArbGntReg <= WbArbGnt;
end
end
always @(*)
begin : MASTER_TO_SLAVE_MUX
WbAdr = 32'h0000_0000;
WbCyc = 1'b0;
WbStb = 1'b0;
WbWe = 1'b0;
WbSel = 4'b0000;
WbCti = 3'b000;
WbBte = 2'b00;
WbWrDat = 32'h0000_0000;
case (WbArbGntReg)
2'b01 :
begin
WbAdr = WB_SL0_ADR_IN ;
WbCyc = WB_SL0_CYC_IN ;
WbStb = WB_SL0_STB_IN ;
WbWe = WB_SL0_WE_IN ;
WbSel = WB_SL0_SEL_IN ;
WbCti = WB_SL0_CTI_IN ;
WbBte = WB_SL0_BTE_IN ;
WbWrDat = WB_SL0_WR_DAT_IN ;
end
2'b10 :
begin
WbAdr = WB_SL1_ADR_IN ;
WbCyc = WB_SL1_CYC_IN ;
WbStb = WB_SL1_STB_IN ;
WbWe = WB_SL1_WE_IN ;
WbSel = WB_SL1_SEL_IN ;
WbCti = WB_SL1_CTI_IN ;
WbBte = WB_SL1_BTE_IN ;
WbWrDat = WB_SL1_WR_DAT_IN ;
end
endcase
end
endmodule | 1 |
138,314 | data/full_repos/permissive/83270534/common/rtl/wb_master.v | 83,270,534 | wb_master.v | v | 465 | 145 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/common/rtl/wb_master.v:51: Cannot find include file: wb_defs.v\n`include "wb_defs.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/common/rtl,data/full_repos/permissive/83270534/wb_defs.v\n data/full_repos/permissive/83270534/common/rtl,data/full_repos/permissive/83270534/wb_defs.v.v\n data/full_repos/permissive/83270534/common/rtl,data/full_repos/permissive/83270534/wb_defs.v.sv\n wb_defs.v\n wb_defs.v.v\n wb_defs.v.sv\n obj_dir/wb_defs.v\n obj_dir/wb_defs.v.v\n obj_dir/wb_defs.v.sv\n%Error: Exiting due to 1 error(s)\n' | 302,157 | module | module WB_MASTER
#(parameter COMB_CYC = 0)
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
output [31:0] WB_ADR_OUT ,
output WB_CYC_OUT ,
output WB_STB_OUT ,
output WB_WE_OUT ,
output [ 3:0] WB_SEL_OUT ,
output [ 2:0] WB_CTI_OUT ,
output [ 1:0] WB_BTE_OUT ,
input WB_ACK_IN ,
input WB_STALL_IN ,
input WB_ERR_IN ,
input [31:0] WB_DAT_RD_IN ,
output [31:0] WB_DAT_WR_OUT ,
input [31:0] BUS_START_ADDR_IN ,
input BUS_READ_REQ_IN ,
output BUS_READ_ACK_OUT ,
input BUS_WRITE_REQ_IN ,
output BUS_WRITE_ACK_OUT ,
output BUS_LAST_ACK_OUT ,
input [ 1:0] BUS_SIZE_IN ,
input [ 4:0] BUS_LEN_IN ,
input BUS_BURST_ADDR_INC_IN ,
output [31:0] BUS_READ_DATA_OUT ,
input [31:0] BUS_WRITE_DATA_IN
);
`include "wb_defs.v"
wire BusReq ;
reg BusReqReg ;
wire BusReqRedge ;
wire WbLastAck ;
wire WbLastStb ;
wire BurstTmrDec ;
wire AckTmrDec ;
reg [ 4:0] BurstTmrVal;
reg [ 4:0] AckTmrVal;
reg [31:0] AddrCntVal;
reg [31:0] BusReadData ;
reg [31:0] WrWbDat ;
reg WbCyc;
reg WbStb;
reg WbWe ;
reg [ 3:0] WbSelLocal ;
reg [ 3:0] WbSel ;
reg [ 3:0] WbSelNxt;
reg [ 2:0] WbCti;
wire [ 2:0] WbCtiNxt;
assign BusReq = BUS_WRITE_REQ_IN | BUS_READ_REQ_IN;
assign BusReqRedge = BusReq & ~BusReqReg;
assign WbLastAck = BusReq & (5'd1 == AckTmrVal ) & AckTmrDec;
assign WbLastStb = BusReq & (5'd1 == BurstTmrVal) & BurstTmrDec;
assign Wb2ndLastStb = BusReq & (5'd2 == BurstTmrVal) & BurstTmrDec;
assign BurstTmrDec = WB_CYC_OUT & WB_STB_OUT & ~WB_STALL_IN;
assign AckTmrDec = WB_ACK_IN;
generate if (COMB_CYC)
begin : GEN_CYC_COMB
assign WB_CYC_OUT = WbCyc | BUS_READ_REQ_IN | BUS_WRITE_REQ_IN;
end
else
begin
assign WB_CYC_OUT = WbCyc ;
end
endgenerate
assign WB_ADR_OUT = {AddrCntVal[31:2], 2'b00};
assign WB_STB_OUT = WbStb ;
assign WB_WE_OUT = WbWe ;
assign WB_SEL_OUT = WbSel ;
assign WB_CTI_OUT = WbCti;
assign WB_BTE_OUT = BTE_LINEAR_BURST;
assign BUS_WRITE_ACK_OUT = BUS_WRITE_REQ_IN & WB_ACK_IN ;
assign BUS_READ_ACK_OUT = BUS_READ_REQ_IN & WB_ACK_IN ;
assign BUS_LAST_ACK_OUT = WbLastAck;
assign BUS_READ_DATA_OUT = BusReadData ;
assign WB_DAT_WR_OUT = WrWbDat ;
always @(posedge CLK or posedge RST_ASYNC)
begin : BUS_REQ_REG
if (RST_ASYNC)
begin
BusReqReg <= 1'b0;
end
else if (RST_SYNC)
begin
BusReqReg <= 1'b0;
end
else if (EN)
begin
BusReqReg <= BusReq;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_CYC_REG
if (RST_ASYNC)
begin
WbCyc <= 1'b0;
end
else if (RST_SYNC)
begin
WbCyc <= 1'b0;
end
else if (EN)
begin
if (BusReqRedge)
begin
WbCyc <= 1'b1;
end
else if (BusReq && WbLastAck)
begin
WbCyc <= 1'b0;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_STB_REG
if (RST_ASYNC)
begin
WbStb <= 1'b0;
end
else if (RST_SYNC)
begin
WbStb <= 1'b0;
end
else if (EN)
begin
if (BusReqRedge)
begin
WbStb <= 1'b1;
end
else if (BusReq && WbLastStb)
begin
WbStb <= 1'b0;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_WE_REG
if (RST_ASYNC)
begin
WbWe <= 1'b0;
end
else if (RST_SYNC)
begin
WbWe <= 1'b0;
end
else if (EN)
begin
if (BusReqRedge && BUS_WRITE_REQ_IN)
begin
WbWe <= 1'b1;
end
else if (BusReq && WbLastStb)
begin
WbWe <= 1'b0;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_SEL_REG
if (RST_ASYNC)
begin
WbSel <= 1'b0;
end
else if (RST_SYNC)
begin
WbSel <= 1'b0;
end
else if (EN)
begin
if (BusReqRedge)
begin
WbSel <= WbSelNxt;
end
else if (WbLastStb)
begin
WbSel <= 4'b0000;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_SEL_LOCAL_REG
if (RST_ASYNC)
begin
WbSelLocal <= 1'b0;
end
else if (RST_SYNC)
begin
WbSelLocal <= 1'b0;
end
else if (EN)
begin
if (BusReqRedge)
begin
WbSelLocal <= WbSelNxt;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_CTI_REG
if (RST_ASYNC)
begin
WbCti <= CTI_CLASSIC;
end
else if (RST_SYNC)
begin
WbCti <= CTI_CLASSIC;
end
else if (EN)
begin
if (BusReqRedge)
begin
if (BUS_BURST_ADDR_INC_IN)
begin
WbCti <= CTI_INCR_ADDR;
end
else
begin
WbCti <= CTI_CLASSIC;
end
end
else if (Wb2ndLastStb)
begin
WbCti <= CTI_END_BURST;
end
else if (WbLastStb)
begin
WbCti <= CTI_CLASSIC;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : BURST_TIMER
if (RST_ASYNC)
begin
BurstTmrVal <= 5'd0;
end
else if (RST_SYNC)
begin
BurstTmrVal <= 5'd0;
end
else if (EN)
begin
if (BusReqRedge)
begin
BurstTmrVal <= BUS_LEN_IN;
end
else if (BurstTmrDec && (| BurstTmrVal))
begin
BurstTmrVal <= BurstTmrVal - 5'd1;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : ACK_TIMER
if (RST_ASYNC)
begin
AckTmrVal <= 5'd0;
end
else if (RST_SYNC)
begin
AckTmrVal <= 5'd0;
end
else if (EN)
begin
if (BusReqRedge)
begin
AckTmrVal <= BUS_LEN_IN;
end
else if (WB_ACK_IN && (| AckTmrVal))
begin
AckTmrVal <= AckTmrVal - 5'd1;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : ADDR_CNT
if (RST_ASYNC)
begin
AddrCntVal <= 32'h0000_0000;
end
else if (RST_SYNC)
begin
AddrCntVal <= 32'h0000_0000;
end
else if (EN)
begin
if (BusReqRedge)
begin
AddrCntVal <= BUS_START_ADDR_IN;
end
else if (BUS_BURST_ADDR_INC_IN && BurstTmrDec)
begin
AddrCntVal <= AddrCntVal + 32'd4;
end
end
end
always @*
begin : WB_SEL_DECODE
WbSelNxt = 4'b0000;
case (BUS_SIZE_IN)
2'b00 :
begin
case (BUS_START_ADDR_IN[1:0])
2'b00 : WbSelNxt = 4'b0001;
2'b01 : WbSelNxt = 4'b0010;
2'b10 : WbSelNxt = 4'b0100;
2'b11 : WbSelNxt = 4'b1000;
endcase
end
2'b01 :
begin
case (BUS_START_ADDR_IN[1])
1'b0 : WbSelNxt = 4'b0011;
1'b1 : WbSelNxt = 4'b1100;
endcase
end
2'b10 : WbSelNxt = 4'b1111;
default : WbSelNxt = 4'b0000;
endcase
end
always @(*)
begin : BUS_READ_DATA_ALIGN
BusReadData = 32'h0000_0000;
case (WbSelLocal)
4'b0001 : BusReadData = {24'h00_0000, WB_DAT_RD_IN[ 7: 0]};
4'b0010 : BusReadData = {24'h00_0000, WB_DAT_RD_IN[15: 8]};
4'b0100 : BusReadData = {24'h00_0000, WB_DAT_RD_IN[23:16]};
4'b1000 : BusReadData = {24'h00_0000, WB_DAT_RD_IN[31:24]};
4'b0011 : BusReadData = {16'h0000, WB_DAT_RD_IN[15: 0]};
4'b1100 : BusReadData = {16'h0000, WB_DAT_RD_IN[31:16]};
4'b1111 : BusReadData = WB_DAT_RD_IN;
endcase
end
always @(*)
begin : WB_WRITE_DATA_ALIGN
WrWbDat = 32'h0000_0000;
case (WbSel)
4'b0001 : WrWbDat = {24'h00_0000, BUS_WRITE_DATA_IN[7:0]};
4'b0010 : WrWbDat = {16'h0000, BUS_WRITE_DATA_IN[7:0], 8'h00};
4'b0100 : WrWbDat = {8'h00,BUS_WRITE_DATA_IN[7:0], 16'h0000};
4'b1000 : WrWbDat = {BUS_WRITE_DATA_IN[7:0], 24'h00_0000};
4'b0011 : WrWbDat = {16'h0000, BUS_WRITE_DATA_IN[15: 0]};
4'b1100 : WrWbDat = {BUS_WRITE_DATA_IN[15: 0], 16'h0000};
4'b1111 : WrWbDat = BUS_WRITE_DATA_IN;
endcase
end
endmodule | module WB_MASTER
#(parameter COMB_CYC = 0)
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
output [31:0] WB_ADR_OUT ,
output WB_CYC_OUT ,
output WB_STB_OUT ,
output WB_WE_OUT ,
output [ 3:0] WB_SEL_OUT ,
output [ 2:0] WB_CTI_OUT ,
output [ 1:0] WB_BTE_OUT ,
input WB_ACK_IN ,
input WB_STALL_IN ,
input WB_ERR_IN ,
input [31:0] WB_DAT_RD_IN ,
output [31:0] WB_DAT_WR_OUT ,
input [31:0] BUS_START_ADDR_IN ,
input BUS_READ_REQ_IN ,
output BUS_READ_ACK_OUT ,
input BUS_WRITE_REQ_IN ,
output BUS_WRITE_ACK_OUT ,
output BUS_LAST_ACK_OUT ,
input [ 1:0] BUS_SIZE_IN ,
input [ 4:0] BUS_LEN_IN ,
input BUS_BURST_ADDR_INC_IN ,
output [31:0] BUS_READ_DATA_OUT ,
input [31:0] BUS_WRITE_DATA_IN
); |
`include "wb_defs.v"
wire BusReq ;
reg BusReqReg ;
wire BusReqRedge ;
wire WbLastAck ;
wire WbLastStb ;
wire BurstTmrDec ;
wire AckTmrDec ;
reg [ 4:0] BurstTmrVal;
reg [ 4:0] AckTmrVal;
reg [31:0] AddrCntVal;
reg [31:0] BusReadData ;
reg [31:0] WrWbDat ;
reg WbCyc;
reg WbStb;
reg WbWe ;
reg [ 3:0] WbSelLocal ;
reg [ 3:0] WbSel ;
reg [ 3:0] WbSelNxt;
reg [ 2:0] WbCti;
wire [ 2:0] WbCtiNxt;
assign BusReq = BUS_WRITE_REQ_IN | BUS_READ_REQ_IN;
assign BusReqRedge = BusReq & ~BusReqReg;
assign WbLastAck = BusReq & (5'd1 == AckTmrVal ) & AckTmrDec;
assign WbLastStb = BusReq & (5'd1 == BurstTmrVal) & BurstTmrDec;
assign Wb2ndLastStb = BusReq & (5'd2 == BurstTmrVal) & BurstTmrDec;
assign BurstTmrDec = WB_CYC_OUT & WB_STB_OUT & ~WB_STALL_IN;
assign AckTmrDec = WB_ACK_IN;
generate if (COMB_CYC)
begin : GEN_CYC_COMB
assign WB_CYC_OUT = WbCyc | BUS_READ_REQ_IN | BUS_WRITE_REQ_IN;
end
else
begin
assign WB_CYC_OUT = WbCyc ;
end
endgenerate
assign WB_ADR_OUT = {AddrCntVal[31:2], 2'b00};
assign WB_STB_OUT = WbStb ;
assign WB_WE_OUT = WbWe ;
assign WB_SEL_OUT = WbSel ;
assign WB_CTI_OUT = WbCti;
assign WB_BTE_OUT = BTE_LINEAR_BURST;
assign BUS_WRITE_ACK_OUT = BUS_WRITE_REQ_IN & WB_ACK_IN ;
assign BUS_READ_ACK_OUT = BUS_READ_REQ_IN & WB_ACK_IN ;
assign BUS_LAST_ACK_OUT = WbLastAck;
assign BUS_READ_DATA_OUT = BusReadData ;
assign WB_DAT_WR_OUT = WrWbDat ;
always @(posedge CLK or posedge RST_ASYNC)
begin : BUS_REQ_REG
if (RST_ASYNC)
begin
BusReqReg <= 1'b0;
end
else if (RST_SYNC)
begin
BusReqReg <= 1'b0;
end
else if (EN)
begin
BusReqReg <= BusReq;
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_CYC_REG
if (RST_ASYNC)
begin
WbCyc <= 1'b0;
end
else if (RST_SYNC)
begin
WbCyc <= 1'b0;
end
else if (EN)
begin
if (BusReqRedge)
begin
WbCyc <= 1'b1;
end
else if (BusReq && WbLastAck)
begin
WbCyc <= 1'b0;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_STB_REG
if (RST_ASYNC)
begin
WbStb <= 1'b0;
end
else if (RST_SYNC)
begin
WbStb <= 1'b0;
end
else if (EN)
begin
if (BusReqRedge)
begin
WbStb <= 1'b1;
end
else if (BusReq && WbLastStb)
begin
WbStb <= 1'b0;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_WE_REG
if (RST_ASYNC)
begin
WbWe <= 1'b0;
end
else if (RST_SYNC)
begin
WbWe <= 1'b0;
end
else if (EN)
begin
if (BusReqRedge && BUS_WRITE_REQ_IN)
begin
WbWe <= 1'b1;
end
else if (BusReq && WbLastStb)
begin
WbWe <= 1'b0;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_SEL_REG
if (RST_ASYNC)
begin
WbSel <= 1'b0;
end
else if (RST_SYNC)
begin
WbSel <= 1'b0;
end
else if (EN)
begin
if (BusReqRedge)
begin
WbSel <= WbSelNxt;
end
else if (WbLastStb)
begin
WbSel <= 4'b0000;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_SEL_LOCAL_REG
if (RST_ASYNC)
begin
WbSelLocal <= 1'b0;
end
else if (RST_SYNC)
begin
WbSelLocal <= 1'b0;
end
else if (EN)
begin
if (BusReqRedge)
begin
WbSelLocal <= WbSelNxt;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_CTI_REG
if (RST_ASYNC)
begin
WbCti <= CTI_CLASSIC;
end
else if (RST_SYNC)
begin
WbCti <= CTI_CLASSIC;
end
else if (EN)
begin
if (BusReqRedge)
begin
if (BUS_BURST_ADDR_INC_IN)
begin
WbCti <= CTI_INCR_ADDR;
end
else
begin
WbCti <= CTI_CLASSIC;
end
end
else if (Wb2ndLastStb)
begin
WbCti <= CTI_END_BURST;
end
else if (WbLastStb)
begin
WbCti <= CTI_CLASSIC;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : BURST_TIMER
if (RST_ASYNC)
begin
BurstTmrVal <= 5'd0;
end
else if (RST_SYNC)
begin
BurstTmrVal <= 5'd0;
end
else if (EN)
begin
if (BusReqRedge)
begin
BurstTmrVal <= BUS_LEN_IN;
end
else if (BurstTmrDec && (| BurstTmrVal))
begin
BurstTmrVal <= BurstTmrVal - 5'd1;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : ACK_TIMER
if (RST_ASYNC)
begin
AckTmrVal <= 5'd0;
end
else if (RST_SYNC)
begin
AckTmrVal <= 5'd0;
end
else if (EN)
begin
if (BusReqRedge)
begin
AckTmrVal <= BUS_LEN_IN;
end
else if (WB_ACK_IN && (| AckTmrVal))
begin
AckTmrVal <= AckTmrVal - 5'd1;
end
end
end
always @(posedge CLK or posedge RST_ASYNC)
begin : ADDR_CNT
if (RST_ASYNC)
begin
AddrCntVal <= 32'h0000_0000;
end
else if (RST_SYNC)
begin
AddrCntVal <= 32'h0000_0000;
end
else if (EN)
begin
if (BusReqRedge)
begin
AddrCntVal <= BUS_START_ADDR_IN;
end
else if (BUS_BURST_ADDR_INC_IN && BurstTmrDec)
begin
AddrCntVal <= AddrCntVal + 32'd4;
end
end
end
always @*
begin : WB_SEL_DECODE
WbSelNxt = 4'b0000;
case (BUS_SIZE_IN)
2'b00 :
begin
case (BUS_START_ADDR_IN[1:0])
2'b00 : WbSelNxt = 4'b0001;
2'b01 : WbSelNxt = 4'b0010;
2'b10 : WbSelNxt = 4'b0100;
2'b11 : WbSelNxt = 4'b1000;
endcase
end
2'b01 :
begin
case (BUS_START_ADDR_IN[1])
1'b0 : WbSelNxt = 4'b0011;
1'b1 : WbSelNxt = 4'b1100;
endcase
end
2'b10 : WbSelNxt = 4'b1111;
default : WbSelNxt = 4'b0000;
endcase
end
always @(*)
begin : BUS_READ_DATA_ALIGN
BusReadData = 32'h0000_0000;
case (WbSelLocal)
4'b0001 : BusReadData = {24'h00_0000, WB_DAT_RD_IN[ 7: 0]};
4'b0010 : BusReadData = {24'h00_0000, WB_DAT_RD_IN[15: 8]};
4'b0100 : BusReadData = {24'h00_0000, WB_DAT_RD_IN[23:16]};
4'b1000 : BusReadData = {24'h00_0000, WB_DAT_RD_IN[31:24]};
4'b0011 : BusReadData = {16'h0000, WB_DAT_RD_IN[15: 0]};
4'b1100 : BusReadData = {16'h0000, WB_DAT_RD_IN[31:16]};
4'b1111 : BusReadData = WB_DAT_RD_IN;
endcase
end
always @(*)
begin : WB_WRITE_DATA_ALIGN
WrWbDat = 32'h0000_0000;
case (WbSel)
4'b0001 : WrWbDat = {24'h00_0000, BUS_WRITE_DATA_IN[7:0]};
4'b0010 : WrWbDat = {16'h0000, BUS_WRITE_DATA_IN[7:0], 8'h00};
4'b0100 : WrWbDat = {8'h00,BUS_WRITE_DATA_IN[7:0], 16'h0000};
4'b1000 : WrWbDat = {BUS_WRITE_DATA_IN[7:0], 24'h00_0000};
4'b0011 : WrWbDat = {16'h0000, BUS_WRITE_DATA_IN[15: 0]};
4'b1100 : WrWbDat = {BUS_WRITE_DATA_IN[15: 0], 16'h0000};
4'b1111 : WrWbDat = BUS_WRITE_DATA_IN;
endcase
end
endmodule | 1 |
138,315 | data/full_repos/permissive/83270534/common/rtl/wb_slave_ctrl.v | 83,270,534 | wb_slave_ctrl.v | v | 126 | 114 | [] | [] | [] | [(1, 125)] | null | data/verilator_xmls/f3c6582a-04f8-423a-ab49-468ed5f57a58.xml | null | 302,158 | module | module WB_SLAVE_CTRL
#(parameter DEFAULT_SLAVE = 0,
parameter DEFAULT_ERR = 0,
parameter WB_ADDR_MSB = 11,
parameter WB_ADDR_LSB = 8,
parameter WB_ADDR_VAL = 0
)
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
input [31:0] WB_REGS_ADR_IN ,
input WB_REGS_CYC_IN ,
input WB_REGS_STB_IN ,
input WB_REGS_WE_IN ,
input [ 3:0] WB_REGS_SEL_IN ,
output WB_REGS_ACK_OUT ,
output WB_REGS_STALL_OUT ,
output WB_REGS_ERR_OUT ,
output WB_WRITE_ADDR_STB_OUT ,
output WB_READ_ADDR_STB_OUT ,
output WB_VALID_OUT
);
wire WbReadAddrStb ;
wire WbWriteAddrStb ;
wire WbAddrStb ;
reg WbAddrStbReg ;
wire WbAddrValid ;
wire WbSelValid ;
wire WbValid ;
assign WbReadAddrStb = WB_REGS_CYC_IN & WB_REGS_STB_IN & ~WB_REGS_WE_IN & ~WB_REGS_STALL_OUT;
assign WbWriteAddrStb = WB_REGS_CYC_IN & WB_REGS_STB_IN & WB_REGS_WE_IN & ~WB_REGS_STALL_OUT;
assign WbAddrStb = WbReadAddrStb | WbWriteAddrStb;
assign WbSelValid = ( ((4'b1111 == WB_REGS_SEL_IN) && (WB_REGS_ADR_IN[1:0] == 2'b00))
| ((4'b1100 == WB_REGS_SEL_IN) && (WB_REGS_ADR_IN[ 0] == 1'b0 ))
| ((4'b0011 == WB_REGS_SEL_IN) && (WB_REGS_ADR_IN[ 0] == 1'b0 ))
);
assign WbAddrValid = (WB_ADDR_VAL == WB_REGS_ADR_IN[WB_ADDR_MSB:WB_ADDR_LSB]);
generate if (DEFAULT_SLAVE)
begin : DEFAULT_RESPONSE
assign WB_WRITE_ADDR_STB_OUT = 1'b0;
assign WB_READ_ADDR_STB_OUT = 1'b0 ;
assign WB_VALID_OUT = 1'b0;
assign WbValid = 1'b1;
end
else
begin
assign WB_WRITE_ADDR_STB_OUT = WbWriteAddrStb;
assign WB_READ_ADDR_STB_OUT = WbReadAddrStb ;
assign WB_VALID_OUT = WbValid;
assign WbValid = WbAddrValid & WbSelValid;
end
endgenerate
generate if (DEFAULT_ERR)
begin : DEFAULT_ERR_GEN
assign WB_REGS_ACK_OUT = 1'b0;
assign WB_REGS_ERR_OUT = WbAddrStbReg;
end
else
begin
assign WB_REGS_ACK_OUT = WbAddrStbReg & WbValid;
assign WB_REGS_ERR_OUT = 1'b0;
end
endgenerate
assign WB_REGS_STALL_OUT = WbAddrStbReg;
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_ADDR_STB_REG
if (RST_ASYNC)
begin
WbAddrStbReg <= 1'b0;
end
else if (RST_SYNC)
begin
WbAddrStbReg <= 1'b0;
end
else if (EN)
begin
WbAddrStbReg <= WbAddrStb & WbValid;
end
end
endmodule | module WB_SLAVE_CTRL
#(parameter DEFAULT_SLAVE = 0,
parameter DEFAULT_ERR = 0,
parameter WB_ADDR_MSB = 11,
parameter WB_ADDR_LSB = 8,
parameter WB_ADDR_VAL = 0
)
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
input [31:0] WB_REGS_ADR_IN ,
input WB_REGS_CYC_IN ,
input WB_REGS_STB_IN ,
input WB_REGS_WE_IN ,
input [ 3:0] WB_REGS_SEL_IN ,
output WB_REGS_ACK_OUT ,
output WB_REGS_STALL_OUT ,
output WB_REGS_ERR_OUT ,
output WB_WRITE_ADDR_STB_OUT ,
output WB_READ_ADDR_STB_OUT ,
output WB_VALID_OUT
); |
wire WbReadAddrStb ;
wire WbWriteAddrStb ;
wire WbAddrStb ;
reg WbAddrStbReg ;
wire WbAddrValid ;
wire WbSelValid ;
wire WbValid ;
assign WbReadAddrStb = WB_REGS_CYC_IN & WB_REGS_STB_IN & ~WB_REGS_WE_IN & ~WB_REGS_STALL_OUT;
assign WbWriteAddrStb = WB_REGS_CYC_IN & WB_REGS_STB_IN & WB_REGS_WE_IN & ~WB_REGS_STALL_OUT;
assign WbAddrStb = WbReadAddrStb | WbWriteAddrStb;
assign WbSelValid = ( ((4'b1111 == WB_REGS_SEL_IN) && (WB_REGS_ADR_IN[1:0] == 2'b00))
| ((4'b1100 == WB_REGS_SEL_IN) && (WB_REGS_ADR_IN[ 0] == 1'b0 ))
| ((4'b0011 == WB_REGS_SEL_IN) && (WB_REGS_ADR_IN[ 0] == 1'b0 ))
);
assign WbAddrValid = (WB_ADDR_VAL == WB_REGS_ADR_IN[WB_ADDR_MSB:WB_ADDR_LSB]);
generate if (DEFAULT_SLAVE)
begin : DEFAULT_RESPONSE
assign WB_WRITE_ADDR_STB_OUT = 1'b0;
assign WB_READ_ADDR_STB_OUT = 1'b0 ;
assign WB_VALID_OUT = 1'b0;
assign WbValid = 1'b1;
end
else
begin
assign WB_WRITE_ADDR_STB_OUT = WbWriteAddrStb;
assign WB_READ_ADDR_STB_OUT = WbReadAddrStb ;
assign WB_VALID_OUT = WbValid;
assign WbValid = WbAddrValid & WbSelValid;
end
endgenerate
generate if (DEFAULT_ERR)
begin : DEFAULT_ERR_GEN
assign WB_REGS_ACK_OUT = 1'b0;
assign WB_REGS_ERR_OUT = WbAddrStbReg;
end
else
begin
assign WB_REGS_ACK_OUT = WbAddrStbReg & WbValid;
assign WB_REGS_ERR_OUT = 1'b0;
end
endgenerate
assign WB_REGS_STALL_OUT = WbAddrStbReg;
always @(posedge CLK or posedge RST_ASYNC)
begin : WB_ADDR_STB_REG
if (RST_ASYNC)
begin
WbAddrStbReg <= 1'b0;
end
else if (RST_SYNC)
begin
WbAddrStbReg <= 1'b0;
end
else if (EN)
begin
WbAddrStbReg <= WbAddrStb & WbValid;
end
end
endmodule | 1 |
138,316 | data/full_repos/permissive/83270534/common/rtl/wb_spram_wrap.v | 83,270,534 | wb_spram_wrap.v | v | 101 | 82 | [] | [] | [] | [(1, 99)] | null | null | 1: b"%Error: data/full_repos/permissive/83270534/common/rtl/wb_spram_wrap.v:80: Cannot find file containing module: 'SPRAM'\n SPRAM \n ^~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/common/rtl,data/full_repos/permissive/83270534/SPRAM\n data/full_repos/permissive/83270534/common/rtl,data/full_repos/permissive/83270534/SPRAM.v\n data/full_repos/permissive/83270534/common/rtl,data/full_repos/permissive/83270534/SPRAM.sv\n SPRAM\n SPRAM.v\n SPRAM.sv\n obj_dir/SPRAM\n obj_dir/SPRAM.v\n obj_dir/SPRAM.sv\n%Error: Exiting due to 1 error(s)\n" | 302,159 | module | module WB_SPRAM_WRAP
#(
parameter [31:0] WBA = 32'h0000_0000,
parameter WS_P2 = 10 ,
parameter DW = 32
)
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
input [31:0] WB_ADR_IN ,
input WB_CYC_IN ,
input WB_STB_IN ,
input WB_WE_IN ,
input [ 3:0] WB_SEL_IN ,
input [ 2:0] WB_CTI_IN ,
input [ 1:0] WB_BTE_IN ,
output WB_ACK_OUT ,
output WB_STALL_OUT ,
output WB_ERR_OUT ,
input [DW-1:0] WB_WR_DAT_IN ,
output [DW-1:0] WB_RD_DAT_OUT
);
wire [31:0] WbAddrOffset = WB_ADR_IN - WBA;
wire WbAddrInRange = ~(| WbAddrOffset[31:WS_P2]);
wire RamEn = EN & WB_CYC_IN & WB_STB_IN & WbAddrInRange;
wire RamWriteEn = EN & WB_CYC_IN & WB_STB_IN & WB_WE_IN & WbAddrInRange;
wire [WS_P2-1:0] RamAddr = WbAddrOffset[WS_P2-1:0];
reg WbAck;
reg WbErr;
assign WB_ACK_OUT = WbAck;
assign WB_ERR_OUT = WbErr;
assign WB_STALL_OUT = 1'b0;
always @(posedge CLK or posedge RST_ASYNC)
begin
if (RST_ASYNC)
begin
WbAck <= 1'b0;
WbErr <= 1'b0;
end
else if (RST_SYNC)
begin
WbAck <= 1'b0;
WbErr <= 1'b0;
end
else if (EN)
begin
WbAck <= RamEn;
WbErr <= EN & WB_CYC_IN & WB_STB_IN & ~WbAddrInRange;
end
end
genvar i;
generate for (i = 0 ; i < 4 ; i = i + 1)
begin : RAM_BYTE_GEN
SPRAM
#(.ADDR_WIDTH (WS_P2 ),
.DATA_WIDTH (DW >> 2 )
)
spram
(
.CLK (CLK ),
.EN (RamEn & WB_SEL_IN[i] ),
.WRITE_EN_IN (RamWriteEn & WB_SEL_IN[i] ),
.ADDR_IN (RamAddr ),
.WRITE_DATA_IN (WB_WR_DAT_IN [((i+1)*8)-1:(i*8)] ),
.READ_DATA_OUT (WB_RD_DAT_OUT[((i+1)*8)-1:(i*8)] )
);
end
endgenerate
endmodule | module WB_SPRAM_WRAP
#(
parameter [31:0] WBA = 32'h0000_0000,
parameter WS_P2 = 10 ,
parameter DW = 32
)
(
input CLK ,
input EN ,
input RST_SYNC ,
input RST_ASYNC ,
input [31:0] WB_ADR_IN ,
input WB_CYC_IN ,
input WB_STB_IN ,
input WB_WE_IN ,
input [ 3:0] WB_SEL_IN ,
input [ 2:0] WB_CTI_IN ,
input [ 1:0] WB_BTE_IN ,
output WB_ACK_OUT ,
output WB_STALL_OUT ,
output WB_ERR_OUT ,
input [DW-1:0] WB_WR_DAT_IN ,
output [DW-1:0] WB_RD_DAT_OUT
); |
wire [31:0] WbAddrOffset = WB_ADR_IN - WBA;
wire WbAddrInRange = ~(| WbAddrOffset[31:WS_P2]);
wire RamEn = EN & WB_CYC_IN & WB_STB_IN & WbAddrInRange;
wire RamWriteEn = EN & WB_CYC_IN & WB_STB_IN & WB_WE_IN & WbAddrInRange;
wire [WS_P2-1:0] RamAddr = WbAddrOffset[WS_P2-1:0];
reg WbAck;
reg WbErr;
assign WB_ACK_OUT = WbAck;
assign WB_ERR_OUT = WbErr;
assign WB_STALL_OUT = 1'b0;
always @(posedge CLK or posedge RST_ASYNC)
begin
if (RST_ASYNC)
begin
WbAck <= 1'b0;
WbErr <= 1'b0;
end
else if (RST_SYNC)
begin
WbAck <= 1'b0;
WbErr <= 1'b0;
end
else if (EN)
begin
WbAck <= RamEn;
WbErr <= EN & WB_CYC_IN & WB_STB_IN & ~WbAddrInRange;
end
end
genvar i;
generate for (i = 0 ; i < 4 ; i = i + 1)
begin : RAM_BYTE_GEN
SPRAM
#(.ADDR_WIDTH (WS_P2 ),
.DATA_WIDTH (DW >> 2 )
)
spram
(
.CLK (CLK ),
.EN (RamEn & WB_SEL_IN[i] ),
.WRITE_EN_IN (RamWriteEn & WB_SEL_IN[i] ),
.ADDR_IN (RamAddr ),
.WRITE_DATA_IN (WB_WR_DAT_IN [((i+1)*8)-1:(i*8)] ),
.READ_DATA_OUT (WB_RD_DAT_OUT[((i+1)*8)-1:(i*8)] )
);
end
endgenerate
endmodule | 1 |
138,319 | data/full_repos/permissive/83270534/common/tb/btn_sw_bfm.v | 83,270,534 | btn_sw_bfm.v | v | 115 | 82 | [] | [] | [] | null | line:39: before: "BtnPush" | data/verilator_xmls/37ac01d2-57e1-4e44-b3e7-2d49dc1b6b45.xml | null | 302,163 | module | module BTN_SW_BFM
(
output reg BTN_0 ,
output reg BTN_1 ,
output reg BTN_2 ,
output reg BTN_3 ,
output reg SW_0 ,
output reg SW_1 ,
output reg SW_2 ,
output reg SW_3 ,
output reg SW_4 ,
output reg SW_5 ,
output reg SW_6 ,
output reg SW_7
);
initial
begin : RESET_ALL_OUTPUTS
BTN_0 = 1'b0;
BTN_1 = 1'b0;
BTN_2 = 1'b0;
BTN_3 = 1'b0;
SW_0 = 1'b0;
SW_1 = 1'b0;
SW_2 = 1'b0;
SW_3 = 1'b0;
SW_4 = 1'b0;
SW_5 = 1'b0;
SW_6 = 1'b0;
SW_7 = 1'b0;
end
task automatic BtnPush (input int ButtonNumber);
begin
case (ButtonNumber)
0 : BTN_0 = 1'b1;
1 : BTN_1 = 1'b1;
2 : BTN_2 = 1'b1;
3 : BTN_3 = 1'b1;
default : $display("[ERROR] Button number %03d doesn't exist", ButtonNumber);
endcase
end
endtask
task automatic BtnRelease (input int ButtonNumber);
begin
case (ButtonNumber)
0 : BTN_0 = 1'b0;
1 : BTN_1 = 1'b0;
2 : BTN_2 = 1'b0;
3 : BTN_3 = 1'b0;
default : $display("[ERROR] Button number %03d doesn't exist", ButtonNumber);
endcase
end
endtask
task automatic SwClose (input int ButtonNumber);
begin
case (ButtonNumber)
0 : SW_0 = 1'b1;
1 : SW_1 = 1'b1;
2 : SW_2 = 1'b1;
3 : SW_3 = 1'b1;
4 : SW_4 = 1'b1;
5 : SW_5 = 1'b1;
6 : SW_6 = 1'b1;
7 : SW_7 = 1'b1;
default : $display("[ERROR] Switch number %03d doesn't exist", ButtonNumber);
endcase
end
endtask
task automatic SwOpen (input int ButtonNumber);
begin
case (ButtonNumber)
0 : SW_0 = 1'b0;
1 : SW_1 = 1'b0;
2 : SW_2 = 1'b0;
3 : SW_3 = 1'b0;
4 : SW_4 = 1'b0;
5 : SW_5 = 1'b0;
6 : SW_6 = 1'b0;
7 : SW_7 = 1'b0;
default : $display("[ERROR] Switch number %03d doesn't exist", ButtonNumber);
endcase
end
endtask
task automatic readSwitches (output byte swStatus);
begin
swStatus = {SW_0 ,
SW_1 ,
SW_2 ,
SW_3 ,
SW_4 ,
SW_5 ,
SW_6 ,
SW_7 };
end
endtask
endmodule | module BTN_SW_BFM
(
output reg BTN_0 ,
output reg BTN_1 ,
output reg BTN_2 ,
output reg BTN_3 ,
output reg SW_0 ,
output reg SW_1 ,
output reg SW_2 ,
output reg SW_3 ,
output reg SW_4 ,
output reg SW_5 ,
output reg SW_6 ,
output reg SW_7
); |
initial
begin : RESET_ALL_OUTPUTS
BTN_0 = 1'b0;
BTN_1 = 1'b0;
BTN_2 = 1'b0;
BTN_3 = 1'b0;
SW_0 = 1'b0;
SW_1 = 1'b0;
SW_2 = 1'b0;
SW_3 = 1'b0;
SW_4 = 1'b0;
SW_5 = 1'b0;
SW_6 = 1'b0;
SW_7 = 1'b0;
end
task automatic BtnPush (input int ButtonNumber);
begin
case (ButtonNumber)
0 : BTN_0 = 1'b1;
1 : BTN_1 = 1'b1;
2 : BTN_2 = 1'b1;
3 : BTN_3 = 1'b1;
default : $display("[ERROR] Button number %03d doesn't exist", ButtonNumber);
endcase
end
endtask
task automatic BtnRelease (input int ButtonNumber);
begin
case (ButtonNumber)
0 : BTN_0 = 1'b0;
1 : BTN_1 = 1'b0;
2 : BTN_2 = 1'b0;
3 : BTN_3 = 1'b0;
default : $display("[ERROR] Button number %03d doesn't exist", ButtonNumber);
endcase
end
endtask
task automatic SwClose (input int ButtonNumber);
begin
case (ButtonNumber)
0 : SW_0 = 1'b1;
1 : SW_1 = 1'b1;
2 : SW_2 = 1'b1;
3 : SW_3 = 1'b1;
4 : SW_4 = 1'b1;
5 : SW_5 = 1'b1;
6 : SW_6 = 1'b1;
7 : SW_7 = 1'b1;
default : $display("[ERROR] Switch number %03d doesn't exist", ButtonNumber);
endcase
end
endtask
task automatic SwOpen (input int ButtonNumber);
begin
case (ButtonNumber)
0 : SW_0 = 1'b0;
1 : SW_1 = 1'b0;
2 : SW_2 = 1'b0;
3 : SW_3 = 1'b0;
4 : SW_4 = 1'b0;
5 : SW_5 = 1'b0;
6 : SW_6 = 1'b0;
7 : SW_7 = 1'b0;
default : $display("[ERROR] Switch number %03d doesn't exist", ButtonNumber);
endcase
end
endtask
task automatic readSwitches (output byte swStatus);
begin
swStatus = {SW_0 ,
SW_1 ,
SW_2 ,
SW_3 ,
SW_4 ,
SW_5 ,
SW_6 ,
SW_7 };
end
endtask
endmodule | 1 |
138,325 | data/full_repos/permissive/83270534/common/tb/epp_master_bfm.v | 83,270,534 | epp_master_bfm.v | v | 341 | 146 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/common/tb/epp_master_bfm.v:17: Cannot find include file: epp_bus_bridge_defs.v\n`include "epp_bus_bridge_defs.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/common/tb,data/full_repos/permissive/83270534/epp_bus_bridge_defs.v\n data/full_repos/permissive/83270534/common/tb,data/full_repos/permissive/83270534/epp_bus_bridge_defs.v.v\n data/full_repos/permissive/83270534/common/tb,data/full_repos/permissive/83270534/epp_bus_bridge_defs.v.sv\n epp_bus_bridge_defs.v\n epp_bus_bridge_defs.v.v\n epp_bus_bridge_defs.v.sv\n obj_dir/epp_bus_bridge_defs.v\n obj_dir/epp_bus_bridge_defs.v.v\n obj_dir/epp_bus_bridge_defs.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/83270534/common/tb/epp_master_bfm.v:49: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/83270534/common/tb/epp_master_bfm.v:56: Unsupported: Ignoring delay on this delayed statement.\n #100ns;\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/epp_master_bfm.v:68: Unsupported or unknown PLI call: $urandom\n writeData = $urandom();\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/common/tb/epp_master_bfm.v:172: Unsupported or unknown PLI call: $urandom\n writeData = $urandom();\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/common/tb/epp_master_bfm.v:215: Unsupported or unknown PLI call: $urandom\n writeData = $urandom();\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/common/tb/epp_master_bfm.v:237: Unsupported or unknown PLI call: $urandom\n writeData = $urandom();\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/common/tb/epp_master_bfm.v:266: syntax error, unexpected \'@\'\n @(posedge EPP_WAIT_IN);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/epp_master_bfm.v:272: syntax error, unexpected \'@\'\n @(negedge EPP_WAIT_IN);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/epp_master_bfm.v:288: syntax error, unexpected \'@\'\n @(posedge EPP_WAIT_IN);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/epp_master_bfm.v:294: syntax error, unexpected \'@\'\n @(negedge EPP_WAIT_IN);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/epp_master_bfm.v:308: syntax error, unexpected \'@\'\n @(posedge EPP_WAIT_IN);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/epp_master_bfm.v:313: syntax error, unexpected \'@\'\n @(negedge EPP_WAIT_IN);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/epp_master_bfm.v:327: syntax error, unexpected \'@\'\n @(posedge EPP_WAIT_IN);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/epp_master_bfm.v:332: syntax error, unexpected \'@\'\n @(negedge EPP_WAIT_IN);\n ^\n%Error: Exiting due to 13 error(s), 2 warning(s)\n' | 302,166 | module | module EPP_MASTER_BFM (
inout [ 7:0] EPP_DATA_INOUT ,
output reg EPP_WRITE_OUT ,
output reg EPP_ASTB_OUT ,
output reg EPP_DSTB_OUT ,
input EPP_WAIT_IN ,
input EPP_INT_IN ,
output reg EPP_RESET_OUT
);
`include "epp_bus_bridge_defs.v"
parameter EPP_MIN_DELAY = 100;
parameter EPP_MAX_DELAY = 255;
reg [7:0] EppData;
reg EppDataDriveEn;
assign EPP_DATA_INOUT = EppDataDriveEn ? EppData : 8'hzz;
initial
begin
EPP_RESET_OUT = 1'b0;
EPP_WRITE_OUT = 1'b1;
EPP_ASTB_OUT = 1'b1;
EPP_DSTB_OUT = 1'b1;
EppDataDriveEn = 1'b0;
EppData = 8'h00;
end
always @*
begin : DATA_CONTENTION_CHECK
if (EPP_DATA_INOUT === 8'hX)
begin
$display("[ERROR] EPP Data contention at time %t", $time);
$display("[FAIL ] Test FAILED at time %t", $time);
#100;
$finish();
end
end
task automatic doEppDelay ();
#100ns;
endtask
task automatic doBusVerify(input [31:0] BusAddr, output bit passFail, input [1:0] BusSize = ERW_SIZE_WORD, input [31:0] Mask = 32'hffff_ffff);
int writeData;
int readData;
writeData = $urandom();
doBusWrite(BusAddr, writeData, BusSize);
doBusRead(BusAddr, readData, BusSize);
if ((writeData & Mask) === readData)
begin
$display("[INFO ] EPP Data readback of Address 0x%x verified at time %t", BusAddr, $time);
passFail = 1;
end
else
begin
$display("[ERROR] EPP Data readback of Address 0x%x at time %t", BusAddr, $time);
passFail = 0;
end
endtask
task automatic doBusWrite(input [31:0] BusAddr, input [31:0] BusWriteData, input [1:0] BusSize);
$display("[INFO ] BUS Write, Address = 0x%x, Data = 0x%x, Size = %d at time %t", BusAddr, BusWriteData, BusSize, $time);
doEppRegWrite(ERW_ADDR0, BusAddr[ 7: 0]);
doEppRegWrite(ERW_ADDR1, BusAddr[15: 8]);
doEppRegWrite(ERW_ADDR2, BusAddr[23:16]);
doEppRegWrite(ERW_ADDR3, BusAddr[31:24]);
case (BusSize)
ERW_SIZE_BYTE :
begin
doEppRegWrite(ERW_DATA0, BusWriteData[ 7: 0]);
end
ERW_SIZE_2BYTE :
begin
doEppRegWrite(ERW_DATA0, BusWriteData[ 7: 0]);
doEppRegWrite(ERW_DATA1, BusWriteData[15: 8]);
end
ERW_SIZE_WORD :
begin
doEppRegWrite(ERW_DATA0, BusWriteData[ 7: 0]);
doEppRegWrite(ERW_DATA1, BusWriteData[15: 8]);
doEppRegWrite(ERW_DATA2, BusWriteData[23:16]);
doEppRegWrite(ERW_DATA3, BusWriteData[31:24]);
end
endcase
doEppRegWrite(ERW_TRANS, (8'h00 | 1'b0 << ERW_TRANS_RWB | BusSize << ERW_TRANS_SIZE_LSB));
endtask
task automatic doBusRead(input [31:0] BusAddr, output [31:0] BusReadData, input [1:0] BusSize);
doEppRegWrite(ERW_ADDR0, BusAddr[ 7: 0]);
doEppRegWrite(ERW_ADDR1, BusAddr[15: 8]);
doEppRegWrite(ERW_ADDR2, BusAddr[23:16]);
doEppRegWrite(ERW_ADDR3, BusAddr[31:24]);
doEppRegWrite(ERW_TRANS, (8'h00 | 1'b1 << ERW_TRANS_RWB | BusSize << ERW_TRANS_SIZE_LSB));
case (BusSize)
ERW_SIZE_BYTE :
begin
doEppRegRead(ERW_DATA0, BusReadData[ 7: 0]);
BusReadData[31: 8] = 24'd0;
end
ERW_SIZE_2BYTE :
begin
doEppRegRead(ERW_DATA0, BusReadData[ 7: 0]);
doEppRegRead(ERW_DATA1, BusReadData[15: 8]);
BusReadData[31:16] = 16'd0;
end
ERW_SIZE_WORD :
begin
doEppRegRead(ERW_DATA0, BusReadData[ 7: 0]);
doEppRegRead(ERW_DATA1, BusReadData[15: 8]);
doEppRegRead(ERW_DATA2, BusReadData[23:16]);
doEppRegRead(ERW_DATA3, BusReadData[31:24]);
end
endcase
$display("[INFO ] BUS Read, Address = 0x%x, Data = 0x%x, Size = %d at time %t", BusAddr, BusReadData, BusSize, $time);
endtask
task automatic doEppRegVerify(input bit [7:0] EppRegAddr, output bit passFail, input bit [7:0] Mask = 8'hff);
byte writeData;
byte readData;
writeData = $urandom();
doEppAddrWrite(EppRegAddr);
doEppDataWrite(writeData);
doEppDataRead(readData);
if ((writeData & Mask) === readData)
begin
$display("[INFO ] EPP Data readback of Address 0x%x verified at time %t", EppRegAddr, $time);
passFail = 1;
end
else
begin
$display("[ERROR] EPP Data readbackof Address 0x%x FAILED at time %t", EppRegAddr, $time);
passFail = 0;
end
endtask
task automatic doEppRegWrite(input bit [7:0] RegAddr, input bit [7:0] RegWriteData);
doEppAddrWrite(RegAddr);
doEppDataWrite(RegWriteData);
endtask
task automatic doEppRegRead(input bit [7:0] RegAddr, output bit [7:0] RegReadData);
doEppAddrWrite(RegAddr);
doEppDataRead(RegReadData);
endtask
task automatic doEppAddrVerify();
byte writeData;
byte readData;
writeData = $urandom();
doEppAddrWrite(writeData);
doEppAddrRead(readData);
if (writeData === readData)
begin
$display("[INFO ] EPP Address readback verified at time %t", $time);
end
else
begin
$display("[ERROR] EPP Address readback FAILED at time %t", $time);
end
endtask
task automatic doEppDataVerify(input bit [7:0] EppAddr);
byte writeData;
byte readData;
writeData = $urandom();
doEppAddrWrite(EppAddr);
doEppDataWrite(writeData);
doEppDataRead(readData);
if (writeData === readData)
begin
$display("[INFO ] EPP Data readback of Address 0x%x verified at time %t", EppAddr, $time);
end
else
begin
$display("[ERROR] EPP Data readbackof Address 0x%x FAILED at time %t", EppAddr, $time);
end
endtask
task automatic doEppDataWrite(input bit [7:0] EppWriteData);
doEppDelay();
EppData = EppWriteData;
EppDataDriveEn = 1'b1;
EPP_WRITE_OUT = 1'b0;
doEppDelay();
EPP_DSTB_OUT = 1'b0;
@(posedge EPP_WAIT_IN);
doEppDelay();
EPP_WRITE_OUT = 1'b1;
EPP_DSTB_OUT = 1'b1;
EppDataDriveEn = 1'b0;
@(negedge EPP_WAIT_IN);
doEppDelay();
endtask
task automatic doEppAddrWrite(input bit [7:0] EppWriteAddr);
doEppDelay();
EppData = EppWriteAddr;
EppDataDriveEn = 1'b1;
EPP_WRITE_OUT = 1'b0;
doEppDelay();
EPP_ASTB_OUT = 1'b0;
@(posedge EPP_WAIT_IN);
doEppDelay();
EPP_WRITE_OUT = 1'b1;
EPP_ASTB_OUT = 1'b1;
EppDataDriveEn = 1'b0;
@(negedge EPP_WAIT_IN);
doEppDelay();
endtask
task automatic doEppDataRead(output bit [7:0] EppReadData);
doEppDelay();
EPP_WRITE_OUT = 1'b1;
doEppDelay();
EPP_DSTB_OUT = 1'b0;
@(posedge EPP_WAIT_IN);
doEppDelay();
EppReadData = EPP_DATA_INOUT;
EPP_DSTB_OUT = 1'b1;
@(negedge EPP_WAIT_IN);
doEppDelay();
endtask
task automatic doEppAddrRead(output bit [7:0] EppReadAddr);
doEppDelay();
EPP_WRITE_OUT = 1'b1;
doEppDelay();
EPP_ASTB_OUT = 1'b0;
@(posedge EPP_WAIT_IN);
doEppDelay();
EppReadAddr = EPP_DATA_INOUT;
EPP_ASTB_OUT = 1'b1;
@(negedge EPP_WAIT_IN);
doEppDelay();
endtask
endmodule | module EPP_MASTER_BFM (
inout [ 7:0] EPP_DATA_INOUT ,
output reg EPP_WRITE_OUT ,
output reg EPP_ASTB_OUT ,
output reg EPP_DSTB_OUT ,
input EPP_WAIT_IN ,
input EPP_INT_IN ,
output reg EPP_RESET_OUT
); |
`include "epp_bus_bridge_defs.v"
parameter EPP_MIN_DELAY = 100;
parameter EPP_MAX_DELAY = 255;
reg [7:0] EppData;
reg EppDataDriveEn;
assign EPP_DATA_INOUT = EppDataDriveEn ? EppData : 8'hzz;
initial
begin
EPP_RESET_OUT = 1'b0;
EPP_WRITE_OUT = 1'b1;
EPP_ASTB_OUT = 1'b1;
EPP_DSTB_OUT = 1'b1;
EppDataDriveEn = 1'b0;
EppData = 8'h00;
end
always @*
begin : DATA_CONTENTION_CHECK
if (EPP_DATA_INOUT === 8'hX)
begin
$display("[ERROR] EPP Data contention at time %t", $time);
$display("[FAIL ] Test FAILED at time %t", $time);
#100;
$finish();
end
end
task automatic doEppDelay ();
#100ns;
endtask
task automatic doBusVerify(input [31:0] BusAddr, output bit passFail, input [1:0] BusSize = ERW_SIZE_WORD, input [31:0] Mask = 32'hffff_ffff);
int writeData;
int readData;
writeData = $urandom();
doBusWrite(BusAddr, writeData, BusSize);
doBusRead(BusAddr, readData, BusSize);
if ((writeData & Mask) === readData)
begin
$display("[INFO ] EPP Data readback of Address 0x%x verified at time %t", BusAddr, $time);
passFail = 1;
end
else
begin
$display("[ERROR] EPP Data readback of Address 0x%x at time %t", BusAddr, $time);
passFail = 0;
end
endtask
task automatic doBusWrite(input [31:0] BusAddr, input [31:0] BusWriteData, input [1:0] BusSize);
$display("[INFO ] BUS Write, Address = 0x%x, Data = 0x%x, Size = %d at time %t", BusAddr, BusWriteData, BusSize, $time);
doEppRegWrite(ERW_ADDR0, BusAddr[ 7: 0]);
doEppRegWrite(ERW_ADDR1, BusAddr[15: 8]);
doEppRegWrite(ERW_ADDR2, BusAddr[23:16]);
doEppRegWrite(ERW_ADDR3, BusAddr[31:24]);
case (BusSize)
ERW_SIZE_BYTE :
begin
doEppRegWrite(ERW_DATA0, BusWriteData[ 7: 0]);
end
ERW_SIZE_2BYTE :
begin
doEppRegWrite(ERW_DATA0, BusWriteData[ 7: 0]);
doEppRegWrite(ERW_DATA1, BusWriteData[15: 8]);
end
ERW_SIZE_WORD :
begin
doEppRegWrite(ERW_DATA0, BusWriteData[ 7: 0]);
doEppRegWrite(ERW_DATA1, BusWriteData[15: 8]);
doEppRegWrite(ERW_DATA2, BusWriteData[23:16]);
doEppRegWrite(ERW_DATA3, BusWriteData[31:24]);
end
endcase
doEppRegWrite(ERW_TRANS, (8'h00 | 1'b0 << ERW_TRANS_RWB | BusSize << ERW_TRANS_SIZE_LSB));
endtask
task automatic doBusRead(input [31:0] BusAddr, output [31:0] BusReadData, input [1:0] BusSize);
doEppRegWrite(ERW_ADDR0, BusAddr[ 7: 0]);
doEppRegWrite(ERW_ADDR1, BusAddr[15: 8]);
doEppRegWrite(ERW_ADDR2, BusAddr[23:16]);
doEppRegWrite(ERW_ADDR3, BusAddr[31:24]);
doEppRegWrite(ERW_TRANS, (8'h00 | 1'b1 << ERW_TRANS_RWB | BusSize << ERW_TRANS_SIZE_LSB));
case (BusSize)
ERW_SIZE_BYTE :
begin
doEppRegRead(ERW_DATA0, BusReadData[ 7: 0]);
BusReadData[31: 8] = 24'd0;
end
ERW_SIZE_2BYTE :
begin
doEppRegRead(ERW_DATA0, BusReadData[ 7: 0]);
doEppRegRead(ERW_DATA1, BusReadData[15: 8]);
BusReadData[31:16] = 16'd0;
end
ERW_SIZE_WORD :
begin
doEppRegRead(ERW_DATA0, BusReadData[ 7: 0]);
doEppRegRead(ERW_DATA1, BusReadData[15: 8]);
doEppRegRead(ERW_DATA2, BusReadData[23:16]);
doEppRegRead(ERW_DATA3, BusReadData[31:24]);
end
endcase
$display("[INFO ] BUS Read, Address = 0x%x, Data = 0x%x, Size = %d at time %t", BusAddr, BusReadData, BusSize, $time);
endtask
task automatic doEppRegVerify(input bit [7:0] EppRegAddr, output bit passFail, input bit [7:0] Mask = 8'hff);
byte writeData;
byte readData;
writeData = $urandom();
doEppAddrWrite(EppRegAddr);
doEppDataWrite(writeData);
doEppDataRead(readData);
if ((writeData & Mask) === readData)
begin
$display("[INFO ] EPP Data readback of Address 0x%x verified at time %t", EppRegAddr, $time);
passFail = 1;
end
else
begin
$display("[ERROR] EPP Data readbackof Address 0x%x FAILED at time %t", EppRegAddr, $time);
passFail = 0;
end
endtask
task automatic doEppRegWrite(input bit [7:0] RegAddr, input bit [7:0] RegWriteData);
doEppAddrWrite(RegAddr);
doEppDataWrite(RegWriteData);
endtask
task automatic doEppRegRead(input bit [7:0] RegAddr, output bit [7:0] RegReadData);
doEppAddrWrite(RegAddr);
doEppDataRead(RegReadData);
endtask
task automatic doEppAddrVerify();
byte writeData;
byte readData;
writeData = $urandom();
doEppAddrWrite(writeData);
doEppAddrRead(readData);
if (writeData === readData)
begin
$display("[INFO ] EPP Address readback verified at time %t", $time);
end
else
begin
$display("[ERROR] EPP Address readback FAILED at time %t", $time);
end
endtask
task automatic doEppDataVerify(input bit [7:0] EppAddr);
byte writeData;
byte readData;
writeData = $urandom();
doEppAddrWrite(EppAddr);
doEppDataWrite(writeData);
doEppDataRead(readData);
if (writeData === readData)
begin
$display("[INFO ] EPP Data readback of Address 0x%x verified at time %t", EppAddr, $time);
end
else
begin
$display("[ERROR] EPP Data readbackof Address 0x%x FAILED at time %t", EppAddr, $time);
end
endtask
task automatic doEppDataWrite(input bit [7:0] EppWriteData);
doEppDelay();
EppData = EppWriteData;
EppDataDriveEn = 1'b1;
EPP_WRITE_OUT = 1'b0;
doEppDelay();
EPP_DSTB_OUT = 1'b0;
@(posedge EPP_WAIT_IN);
doEppDelay();
EPP_WRITE_OUT = 1'b1;
EPP_DSTB_OUT = 1'b1;
EppDataDriveEn = 1'b0;
@(negedge EPP_WAIT_IN);
doEppDelay();
endtask
task automatic doEppAddrWrite(input bit [7:0] EppWriteAddr);
doEppDelay();
EppData = EppWriteAddr;
EppDataDriveEn = 1'b1;
EPP_WRITE_OUT = 1'b0;
doEppDelay();
EPP_ASTB_OUT = 1'b0;
@(posedge EPP_WAIT_IN);
doEppDelay();
EPP_WRITE_OUT = 1'b1;
EPP_ASTB_OUT = 1'b1;
EppDataDriveEn = 1'b0;
@(negedge EPP_WAIT_IN);
doEppDelay();
endtask
task automatic doEppDataRead(output bit [7:0] EppReadData);
doEppDelay();
EPP_WRITE_OUT = 1'b1;
doEppDelay();
EPP_DSTB_OUT = 1'b0;
@(posedge EPP_WAIT_IN);
doEppDelay();
EppReadData = EPP_DATA_INOUT;
EPP_DSTB_OUT = 1'b1;
@(negedge EPP_WAIT_IN);
doEppDelay();
endtask
task automatic doEppAddrRead(output bit [7:0] EppReadAddr);
doEppDelay();
EPP_WRITE_OUT = 1'b1;
doEppDelay();
EPP_ASTB_OUT = 1'b0;
@(posedge EPP_WAIT_IN);
doEppDelay();
EppReadAddr = EPP_DATA_INOUT;
EPP_ASTB_OUT = 1'b1;
@(negedge EPP_WAIT_IN);
doEppDelay();
endtask
endmodule | 1 |
138,327 | data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v | 83,270,534 | wb_master_bfm.v | v | 641 | 177 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:31: Cannot find include file: wb_defs.v\n`include "wb_defs.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/common/tb,data/full_repos/permissive/83270534/wb_defs.v\n data/full_repos/permissive/83270534/common/tb,data/full_repos/permissive/83270534/wb_defs.v.v\n data/full_repos/permissive/83270534/common/tb,data/full_repos/permissive/83270534/wb_defs.v.sv\n wb_defs.v\n wb_defs.v.v\n wb_defs.v.sv\n obj_dir/wb_defs.v\n obj_dir/wb_defs.v.v\n obj_dir/wb_defs.v.sv\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:61: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:130: Unsupported: wait statements\n wait (resetDone);\n ^~~~\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:145: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:150: syntax error, unexpected \'@\'\n while (WB_STALL_IN) @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:161: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:162: syntax error, unexpected \'@\'\n while (!(WB_ACK_IN || WB_ERR_IN)) @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:213: Unsupported: wait statements\n wait (resetDone);\n ^~~~\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:229: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:233: syntax error, unexpected \'@\'\n while (WB_STALL_IN) @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:242: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:243: syntax error, unexpected \'@\'\n while (!(WB_ACK_IN || WB_ERR_IN)) @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:278: Unsupported: wait statements\n wait (resetDone);\n ^~~~\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:291: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:294: syntax error, unexpected \'@\'\n while (WB_STALL_IN) @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:301: syntax error, unexpected \'@\'\n while (!(WB_ACK_IN || WB_ERR_IN)) @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:373: Unsupported: Dynamic array new\n startClk = new[burstBeatNum]; \n ^~~\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:374: Unsupported: Dynamic array new\n endClk = new[burstBeatNum]; \n ^~~\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:381: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:395: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:398: syntax error, unexpected \'@\'\n while (WB_STALL_IN) @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:413: syntax error, unexpected \'@\'\n while (!((WB_ACK_IN || WB_ERR_IN) && (addrCount > i))) @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:428: syntax error, unexpected \'@\'\n if (dataCount < burstBeatNum) @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:456: Unsupported: Dynamic array new\n ReadData = new[burstBeatNum]; \n ^~~\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:457: Unsupported: Dynamic array new\n startClk = new[burstBeatNum]; \n ^~~\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:458: Unsupported: Dynamic array new\n endClk = new[burstBeatNum]; \n ^~~\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:465: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:480: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:483: syntax error, unexpected \'@\'\n while (WB_STALL_IN) @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:499: syntax error, unexpected \'@\'\n while (!((WB_ACK_IN || WB_ERR_IN) && (addrCount > i))) @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:516: syntax error, unexpected \'@\'\n if (dataCount < burstBeatNum) @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:546: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:550: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:558: Unsupported or unknown PLI call: $urandom\n WriteData = $urandom();\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:567: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:571: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:582: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:586: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:597: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/83270534/common/tb/wb_master_bfm.v:624: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: Exiting due to 40 error(s)\n' | 302,168 | module | module WB_MASTER_BFM
(
input CLK ,
input RST_SYNC ,
output [31:0] WB_ADR_OUT ,
output WB_CYC_OUT ,
output WB_STB_OUT ,
output WB_WE_OUT ,
output [ 3:0] WB_SEL_OUT ,
output [ 2:0] WB_CTI_OUT ,
output [ 1:0] WB_BTE_OUT ,
input WB_ACK_IN ,
input WB_STALL_IN ,
input WB_ERR_IN ,
input [31:0] WB_DAT_RD_IN ,
output [31:0] WB_DAT_WR_OUT
);
`include "wb_defs.v"
reg [31:0] WbAdr ;
reg WbCyc ;
reg WbStb ;
reg WbWe ;
reg [ 3:0] WbSel ;
reg [ 2:0] WbCti ;
reg [ 1:0] WbBte ;
reg [31:0] WbDatWr ;
reg resetDone;
int unsigned clkCount = 0;
assign WB_ADR_OUT = WbAdr ;
assign WB_CYC_OUT = WbCyc ;
assign WB_STB_OUT = WbStb ;
assign WB_WE_OUT = WbWe ;
assign WB_SEL_OUT = WbSel ;
assign WB_CTI_OUT = WbCti ;
assign WB_BTE_OUT = WbBte ;
assign WB_DAT_WR_OUT = WbDatWr ;
initial
begin
resetDone = 1'b0;
while (RST_SYNC)
@(posedge CLK);
resetDone = 1'b1;
end
always @(posedge CLK)
begin
if (!RST_SYNC)
begin
clkCount <= clkCount + 1;
end
end
initial
begin : zero_outputs
WbAdr = 32'h0000_0000;
WbCyc = 1'b0;
WbStb = 1'b0;
WbWe = 1'b0;
WbSel = 4'h0;
WbCti = 3'b000;
WbBte = 2'b00;
WbDatWr = 32'h0000_0000;
end
task automatic wbWriteByte
(
input [31:0] Addr,
input [ 7:0] DataByte
);
begin
case (Addr[1:0])
2'b00 : wbWrite({Addr[31:2], 2'b00}, 4'b0001, {24'h00_0000, DataByte });
2'b01 : wbWrite({Addr[31:2], 2'b00}, 4'b0010, {16'h0000, DataByte, 8'h00 });
2'b10 : wbWrite({Addr[31:2], 2'b00}, 4'b0100, {8'h00, DataByte, 16'h0000 });
2'b11 : wbWrite({Addr[31:2], 2'b00}, 4'b1000, {DataByte, 24'h00_0000 });
endcase
end
endtask
task automatic wbWriteHalf
(
input [31:0] Addr,
input [15:0] DataHalf
);
begin
case (Addr[1])
1'b0 : wbWrite({Addr[31:2], 2'b00}, 4'b0011, {16'h0000, DataHalf });
1'b1 : wbWrite({Addr[31:2], 2'b00}, 4'b1100, {DataHalf, 16'h0000 });
endcase
end
endtask
task automatic wbWrite
(
input [31:0] Addr,
input [ 3:0] Sel,
input [31:0] Data
);
begin
int unsigned startClk = 0;
int unsigned endClk = 0;
wait (resetDone);
if (| Addr[1:0])
begin
$display("[ERROR] WRITE: Addr = 0x%h, Unaligned access. Time = %d", Addr, $realtime);
end
$display("[INFO ] WRITE: Beginning transaction at time %4t", $realtime);
WbCyc <= 1'b1;
WbStb <= 1'b1;
WbAdr <= Addr;
WbSel <= Sel;
WbWe <= 1'b1;
WbDatWr <= Data;
@(posedge CLK);
startClk = clkCount;
while (WB_STALL_IN) @(posedge CLK);
WbStb <= 1'b0;
WbAdr <= 32'h0000_0000;
WbSel <= 4'b0000;
WbWe <= 1'b0;
WbDatWr <= 32'h0000_0000;
@(posedge CLK);
while (!(WB_ACK_IN || WB_ERR_IN)) @(posedge CLK);
endClk = clkCount;
if (WB_ACK_IN)
begin
$display("[INFO ] SINGLE WRITE: Addr = 0x%x, Sel = 0x%x, Data = 0x%x. Latency = %3d CLKs at time %4t", Addr, Sel, Data, (endClk - startClk-1), $time);
end
else if (WB_ERR_IN)
begin
$display("[ERROR] SINGLE WRITE: Failed - Addr = 0x%x, Sel = 0x%x, Data = 0x%x. Latency = %3d CLKs at time %4t", Addr, Sel, Data, (endClk - startClk-1), $time);
end
WbCyc <= 1'b0;
WbSel <= 4'h0;
WbWe <= 1'b0;
end
endtask
task automatic wbReadCompareByte
(
input [31:0] Addr,
input [ 7:0] ExpDataByte
);
begin
case (Addr[1:0])
2'b00 : wbReadCompare({Addr[31:2], 2'b00}, 4'b0001, {24'h00_0000, ExpDataByte });
2'b01 : wbReadCompare({Addr[31:2], 2'b00}, 4'b0010, {16'h0000, ExpDataByte, 8'h00 });
2'b10 : wbReadCompare({Addr[31:2], 2'b00}, 4'b0100, {8'h00, ExpDataByte, 16'h0000 });
2'b11 : wbReadCompare({Addr[31:2], 2'b00}, 4'b1000, {ExpDataByte, 24'h00_0000 });
endcase
end
endtask
task automatic wbRead
(
input [31:0] Addr,
input [ 3:0] Sel,
output [31:0] ReadData
);
begin
int unsigned startClk = 0;
int unsigned endClk = 0;
wait (resetDone);
if (| Addr[1:0])
begin
$display("[ERROR] WRITE: Addr = 0x%h, Unaligned access. Time = %d", Addr, $realtime);
end
ReadData = 0;
$display("[INFO ] READ: Requesting bus at time %4t", $realtime);
WbCyc <= 1'b1;
WbStb <= 1'b1;
WbAdr <= Addr;
WbSel <= Sel;
WbWe <= 1'b0;
@(posedge CLK);
startClk = clkCount;
while (WB_STALL_IN) @(posedge CLK);
WbStb <= 1'b0;
WbAdr <= 32'h0000_0000;
WbSel <= 4'b0000;
WbWe <= 1'b0;
@(posedge CLK);
while (!(WB_ACK_IN || WB_ERR_IN)) @(posedge CLK);
endClk = clkCount;
if (WB_ACK_IN)
begin
ReadData = WB_DAT_RD_IN;
$display("[INFO ] SINGLE READ : Addr = 0x%x, Sel = 0x%x, Data = 0x%x. Latency = %3d CLKs at time %4t", Addr, Sel, ReadData, (endClk - startClk-1), $time);
end
else if (WB_ERR_IN)
begin
ReadData = 32'hxxxx_xxxx;
$display("[ERROR] SINGLE READ : Failed - Addr = 0x%x, Sel = 0x%x, Data = 0x%x. Latency = %3d CLKs at time %4t", Addr, Sel, ReadData, (endClk - startClk-1), $time);
end
WbCyc <= 1'b0;
end
endtask
task automatic wbReadCompare
(
input [31:0] Addr,
input [ 3:0] Sel,
input [31:0] ExpData
);
reg [31:0] ReadData;
reg [31:0] ReadDataMasked;
reg [31:0] ExpDataMasked;
begin
wait (resetDone);
if (| Addr[1:0])
begin
$display("[ERROR] WRITE: Addr = 0x%h, Unaligned access. Time = %d", Addr, $realtime);
end
WbCyc <= 1'b1;
WbStb <= 1'b1;
WbAdr <= Addr;
WbSel <= Sel;
WbWe <= 1'b0;
@(posedge CLK);
while (WB_STALL_IN) @(posedge CLK);
$display("[INFO ] WB Read Address and Data accepted at time %4t", $time);
WbStb <= 1'b0;
WbAdr <= 32'h0000_0000;
while (!(WB_ACK_IN || WB_ERR_IN)) @(posedge CLK);
$display("[INFO ] WB Read Data ready at time %4t", $time);
if (WB_ACK_IN)
begin
ReadData = WB_DAT_RD_IN;
ReadDataMasked[31:24] = Sel[3] ? ReadData[31:24] : 8'h00;
ReadDataMasked[23:16] = Sel[2] ? ReadData[23:16] : 8'h00;
ReadDataMasked[15: 8] = Sel[1] ? ReadData[15: 8] : 8'h00;
ReadDataMasked[ 7: 0] = Sel[0] ? ReadData[ 7: 0] : 8'h00;
ExpDataMasked [31:24] = Sel[3] ? ExpData[31:24] : 8'h00;
ExpDataMasked [23:16] = Sel[2] ? ExpData[23:16] : 8'h00;
ExpDataMasked [15: 8] = Sel[1] ? ExpData[15: 8] : 8'h00;
ExpDataMasked [ 7: 0] = Sel[0] ? ExpData[ 7: 0] : 8'h00;
end
else if (WB_ERR_IN)
begin
$display("[ERROR] WB Read Failed - at time %4t", $time);
ReadData = WB_DAT_RD_IN;
ExpDataMasked = ~ WB_DAT_RD_IN;
end
if (ReadDataMasked !== ExpDataMasked)
begin
$display("[ERROR] READ : Addr = 0x%h, Sel = 0x%h, Read Data = 0x%h, Expected Data = 0x%h, Time = %d", Addr, Sel, ReadData, ExpData, $realtime);
$display("[ERROR] Masked Read Data is 0x%h, Masked Expected Data is 0x%h", ReadDataMasked, ExpDataMasked);
end
else
begin
$display("[INFO ] READ : Addr = 0x%h, Sel = 0x%h, Read Data = 0x%h, Expected Data = 0x%h, Time = %d", Addr, Sel, ReadData, ExpData, $realtime);
end
WbCyc <= 1'b0;
WbStb <= 1'b0;
WbAdr <= 32'h0000_0000;
WbSel <= 4'h0;
WbWe <= 1'b0;
end
endtask
task automatic wbBurstWrite32b
(
input int Addr [],
input int WriteData []
);
int burstBeatNum;
int unsigned startClk [] ;
int unsigned endClk [] ;
int unsigned addrCount = 0;
int unsigned dataCount = 0;
burstBeatNum = Addr.size();
startClk = new[burstBeatNum];
endClk = new[burstBeatNum];
$display("[INFO ] BURST WRITE: Burst starting at 0x%x, length %02d at time %4t", Addr[0], burstBeatNum, $realtime);
WbCyc <= 1'b1;
fork
begin : ADDR_ISSUE
foreach (Addr[i])
begin
if (| Addr[i][1:0])
begin
$display("[ERROR] BURST WRITE: Addr = 0x%h, Unaligned access. Time = %d", Addr[i], $realtime);
end
WbStb <= 1'b1;
WbAdr <= Addr[i];
WbSel <= 4'b1111;
WbWe <= 1'b1;
WbDatWr <= WriteData[i];
@(posedge CLK);
startClk[i] = clkCount;
while (WB_STALL_IN) @(posedge CLK);
addrCount++;
$display("[INFO ] BURST WRITE: Address 0x%x (%3d of %3d), Data 0x%x accepted at time %4t", Addr[i], addrCount, burstBeatNum, WriteData[i], $realtime);
end
WbStb <= 1'b0;
WbAdr <= 32'h0000_0000;
WbSel <= 4'b0000;
WbWe <= 1'b0;
WbDatWr <= 32'h0000_0000;
end
begin : DATA_ACK
foreach (Addr[i])
begin
while (!((WB_ACK_IN || WB_ERR_IN) && (addrCount > i))) @(posedge CLK);
endClk[i] = clkCount;
dataCount++;
if (WB_ACK_IN)
begin
$display("[INFO ] BURST WRITE: Address 0x%x , Data 0x%x ACK seen (%3d of %3d). Latency = %3d at time %4t",
Addr[i], WriteData[i], dataCount, burstBeatNum, (endClk[i] - startClk[i]-1), $realtime);
end
else if (WB_ERR_IN)
begin
$display("[ERROR] BURST WRITE: Failed - Address 0x%x , Data 0x%x ERR seen (%3d of %3d). Latency = %3d at time %4t",
Addr[i], WriteData[i], dataCount, burstBeatNum, (endClk[i] - startClk[i]-1), $realtime);
end
if (dataCount < burstBeatNum) @(posedge CLK);
end
end
join
$display("[INFO ] BURST WRITE: Completed at time %4t", $realtime);
WbCyc <= 1'b0;
endtask
task automatic wbBurstRead32b
(
input int Addr [],
output int ReadData []
);
int burstBeatNum;
int unsigned startClk [] ;
int unsigned endClk [] ;
int unsigned addrCount = 0;
int unsigned dataCount = 0;
burstBeatNum = Addr.size();
ReadData = new[burstBeatNum];
startClk = new[burstBeatNum];
endClk = new[burstBeatNum];
$display("[INFO ] BURST READ: Burst starting at 0x%x, length %02d at time %4t", Addr[0], burstBeatNum, $realtime);
WbCyc <= 1'b1;
WbDatWr <= 32'h0000_0000;
fork
begin : ADDR_ISSUE
foreach (Addr[i])
begin
if (| Addr[i][1:0])
begin
$display("[ERROR] BURST READ: Addr = 0x%h, Unaligned access. Time = %d", Addr[i], $realtime);
end
WbStb <= 1'b1;
WbAdr <= Addr[i];
WbSel <= 4'b1111;
WbWe <= 1'b0;
@(posedge CLK);
startClk[i] = clkCount;
while (WB_STALL_IN) @(posedge CLK);
addrCount++;
$display("[INFO ] BURST READ: Address 0x%x (%3d of %3d) accepted at time %4t", Addr[i], addrCount, burstBeatNum, $realtime);
end
WbStb <= 1'b0;
WbAdr <= 32'h0000_0000;
WbSel <= 4'b0000;
WbWe <= 1'b0;
end
begin : DATA_ACK
foreach (Addr[i])
begin
while (!((WB_ACK_IN || WB_ERR_IN) && (addrCount > i))) @(posedge CLK);
endClk[i] = clkCount;
dataCount++;
if (WB_ACK_IN)
begin
$display("[INFO ] BURST READ: Address 0x%x , Data = 0x%x (%3d of %3d). Latency = %3d CLKs at time %4t",
Addr[i], WB_DAT_RD_IN, dataCount, burstBeatNum, (endClk[i] - startClk[i]-1), $realtime);
ReadData[i] = WB_DAT_RD_IN;
end
else if (WB_ERR_IN)
begin
$display("[ERROR] BURST READ: Failed - Address 0x%x , Data = 0x%x (%3d of %3d). Latency = %3d CLKs at time %4t",
Addr[i], WB_DAT_RD_IN, dataCount, burstBeatNum, (endClk[i] - startClk[i]-1), $realtime);
ReadData[i] = 32'hxxxx_xxxx;
end
if (dataCount < burstBeatNum) @(posedge CLK);
end
end
join
$display("[INFO ] BURST READ: Completed at time %4t", $realtime);
WbCyc <= 1'b0;
endtask
task automatic wbOverlapWriteVerify
(
input int RamBaseAddr ,
input int RamSizeByte ,
output int TestPass
);
begin
int AddrLoop;
int WriteData;
int expReadData;
int expReadAddr;
int DataQ [$];
@(posedge CLK);
TestPass = 1;
fork
begin : ADDR_PHASE
for (AddrLoop = RamBaseAddr ; AddrLoop < (RamBaseAddr + RamSizeByte) ; AddrLoop = AddrLoop + 4)
begin
WriteData = $urandom();
WbCyc <= 1'b1;
WbStb <= 1'b1;
WbWe <= 1'b1;
WbSel <= 4'b1111;
WbAdr <= AddrLoop;
WbDatWr <= WriteData;
@(posedge CLK);
while (WB_STALL_IN)
@(posedge CLK);
DataQ.push_front(WriteData);
$display("[DEBUG] SRAM Write Accepted. Addr = 0x%x, Sel = 0b%b, Write Data = 0x%x", AddrLoop, 4'b1111, WriteData);
WbCyc <= 1'b1;
WbStb <= 1'b1;
WbWe <= 1'b0;
WbSel <= 4'b1111;
WbAdr <= AddrLoop;
WbDatWr <= 32'h0000_0000;
@(posedge CLK);
while (WB_STALL_IN)
@(posedge CLK);
$display("[DEBUG] SRAM Read Accepted. Addr = 0x%x, Sel = 0b%b, ", AddrLoop, 4'b1111);
end
end
begin : RD_DATA_PHASE
while (!(WbCyc && WbStb && !WbWe && !WB_STALL_IN))
@(posedge CLK);
@(posedge CLK);
expReadData = DataQ.pop_back();
if (expReadData != WB_DAT_RD_IN)
begin
$display("[ERROR] Read Data Mismatch at Addr = 0x%x, Expected = 0x%x, Read = 0x%x", expReadAddr, expReadData, WB_DAT_RD_IN );
TestPass = 0;
end
else
begin
end
end
join
WbStb <= 1'b0;
while (WB_ACK_IN)
@(posedge CLK);
WbCyc <= 1'b0;
WbWe <= 1'b0;
WbSel <= 4'b0000;
WbAdr <= 32'h0000_0000;
WbDatWr <= 32'h0000_0000;
end
endtask
endmodule | module WB_MASTER_BFM
(
input CLK ,
input RST_SYNC ,
output [31:0] WB_ADR_OUT ,
output WB_CYC_OUT ,
output WB_STB_OUT ,
output WB_WE_OUT ,
output [ 3:0] WB_SEL_OUT ,
output [ 2:0] WB_CTI_OUT ,
output [ 1:0] WB_BTE_OUT ,
input WB_ACK_IN ,
input WB_STALL_IN ,
input WB_ERR_IN ,
input [31:0] WB_DAT_RD_IN ,
output [31:0] WB_DAT_WR_OUT
); |
`include "wb_defs.v"
reg [31:0] WbAdr ;
reg WbCyc ;
reg WbStb ;
reg WbWe ;
reg [ 3:0] WbSel ;
reg [ 2:0] WbCti ;
reg [ 1:0] WbBte ;
reg [31:0] WbDatWr ;
reg resetDone;
int unsigned clkCount = 0;
assign WB_ADR_OUT = WbAdr ;
assign WB_CYC_OUT = WbCyc ;
assign WB_STB_OUT = WbStb ;
assign WB_WE_OUT = WbWe ;
assign WB_SEL_OUT = WbSel ;
assign WB_CTI_OUT = WbCti ;
assign WB_BTE_OUT = WbBte ;
assign WB_DAT_WR_OUT = WbDatWr ;
initial
begin
resetDone = 1'b0;
while (RST_SYNC)
@(posedge CLK);
resetDone = 1'b1;
end
always @(posedge CLK)
begin
if (!RST_SYNC)
begin
clkCount <= clkCount + 1;
end
end
initial
begin : zero_outputs
WbAdr = 32'h0000_0000;
WbCyc = 1'b0;
WbStb = 1'b0;
WbWe = 1'b0;
WbSel = 4'h0;
WbCti = 3'b000;
WbBte = 2'b00;
WbDatWr = 32'h0000_0000;
end
task automatic wbWriteByte
(
input [31:0] Addr,
input [ 7:0] DataByte
);
begin
case (Addr[1:0])
2'b00 : wbWrite({Addr[31:2], 2'b00}, 4'b0001, {24'h00_0000, DataByte });
2'b01 : wbWrite({Addr[31:2], 2'b00}, 4'b0010, {16'h0000, DataByte, 8'h00 });
2'b10 : wbWrite({Addr[31:2], 2'b00}, 4'b0100, {8'h00, DataByte, 16'h0000 });
2'b11 : wbWrite({Addr[31:2], 2'b00}, 4'b1000, {DataByte, 24'h00_0000 });
endcase
end
endtask
task automatic wbWriteHalf
(
input [31:0] Addr,
input [15:0] DataHalf
);
begin
case (Addr[1])
1'b0 : wbWrite({Addr[31:2], 2'b00}, 4'b0011, {16'h0000, DataHalf });
1'b1 : wbWrite({Addr[31:2], 2'b00}, 4'b1100, {DataHalf, 16'h0000 });
endcase
end
endtask
task automatic wbWrite
(
input [31:0] Addr,
input [ 3:0] Sel,
input [31:0] Data
);
begin
int unsigned startClk = 0;
int unsigned endClk = 0;
wait (resetDone);
if (| Addr[1:0])
begin
$display("[ERROR] WRITE: Addr = 0x%h, Unaligned access. Time = %d", Addr, $realtime);
end
$display("[INFO ] WRITE: Beginning transaction at time %4t", $realtime);
WbCyc <= 1'b1;
WbStb <= 1'b1;
WbAdr <= Addr;
WbSel <= Sel;
WbWe <= 1'b1;
WbDatWr <= Data;
@(posedge CLK);
startClk = clkCount;
while (WB_STALL_IN) @(posedge CLK);
WbStb <= 1'b0;
WbAdr <= 32'h0000_0000;
WbSel <= 4'b0000;
WbWe <= 1'b0;
WbDatWr <= 32'h0000_0000;
@(posedge CLK);
while (!(WB_ACK_IN || WB_ERR_IN)) @(posedge CLK);
endClk = clkCount;
if (WB_ACK_IN)
begin
$display("[INFO ] SINGLE WRITE: Addr = 0x%x, Sel = 0x%x, Data = 0x%x. Latency = %3d CLKs at time %4t", Addr, Sel, Data, (endClk - startClk-1), $time);
end
else if (WB_ERR_IN)
begin
$display("[ERROR] SINGLE WRITE: Failed - Addr = 0x%x, Sel = 0x%x, Data = 0x%x. Latency = %3d CLKs at time %4t", Addr, Sel, Data, (endClk - startClk-1), $time);
end
WbCyc <= 1'b0;
WbSel <= 4'h0;
WbWe <= 1'b0;
end
endtask
task automatic wbReadCompareByte
(
input [31:0] Addr,
input [ 7:0] ExpDataByte
);
begin
case (Addr[1:0])
2'b00 : wbReadCompare({Addr[31:2], 2'b00}, 4'b0001, {24'h00_0000, ExpDataByte });
2'b01 : wbReadCompare({Addr[31:2], 2'b00}, 4'b0010, {16'h0000, ExpDataByte, 8'h00 });
2'b10 : wbReadCompare({Addr[31:2], 2'b00}, 4'b0100, {8'h00, ExpDataByte, 16'h0000 });
2'b11 : wbReadCompare({Addr[31:2], 2'b00}, 4'b1000, {ExpDataByte, 24'h00_0000 });
endcase
end
endtask
task automatic wbRead
(
input [31:0] Addr,
input [ 3:0] Sel,
output [31:0] ReadData
);
begin
int unsigned startClk = 0;
int unsigned endClk = 0;
wait (resetDone);
if (| Addr[1:0])
begin
$display("[ERROR] WRITE: Addr = 0x%h, Unaligned access. Time = %d", Addr, $realtime);
end
ReadData = 0;
$display("[INFO ] READ: Requesting bus at time %4t", $realtime);
WbCyc <= 1'b1;
WbStb <= 1'b1;
WbAdr <= Addr;
WbSel <= Sel;
WbWe <= 1'b0;
@(posedge CLK);
startClk = clkCount;
while (WB_STALL_IN) @(posedge CLK);
WbStb <= 1'b0;
WbAdr <= 32'h0000_0000;
WbSel <= 4'b0000;
WbWe <= 1'b0;
@(posedge CLK);
while (!(WB_ACK_IN || WB_ERR_IN)) @(posedge CLK);
endClk = clkCount;
if (WB_ACK_IN)
begin
ReadData = WB_DAT_RD_IN;
$display("[INFO ] SINGLE READ : Addr = 0x%x, Sel = 0x%x, Data = 0x%x. Latency = %3d CLKs at time %4t", Addr, Sel, ReadData, (endClk - startClk-1), $time);
end
else if (WB_ERR_IN)
begin
ReadData = 32'hxxxx_xxxx;
$display("[ERROR] SINGLE READ : Failed - Addr = 0x%x, Sel = 0x%x, Data = 0x%x. Latency = %3d CLKs at time %4t", Addr, Sel, ReadData, (endClk - startClk-1), $time);
end
WbCyc <= 1'b0;
end
endtask
task automatic wbReadCompare
(
input [31:0] Addr,
input [ 3:0] Sel,
input [31:0] ExpData
);
reg [31:0] ReadData;
reg [31:0] ReadDataMasked;
reg [31:0] ExpDataMasked;
begin
wait (resetDone);
if (| Addr[1:0])
begin
$display("[ERROR] WRITE: Addr = 0x%h, Unaligned access. Time = %d", Addr, $realtime);
end
WbCyc <= 1'b1;
WbStb <= 1'b1;
WbAdr <= Addr;
WbSel <= Sel;
WbWe <= 1'b0;
@(posedge CLK);
while (WB_STALL_IN) @(posedge CLK);
$display("[INFO ] WB Read Address and Data accepted at time %4t", $time);
WbStb <= 1'b0;
WbAdr <= 32'h0000_0000;
while (!(WB_ACK_IN || WB_ERR_IN)) @(posedge CLK);
$display("[INFO ] WB Read Data ready at time %4t", $time);
if (WB_ACK_IN)
begin
ReadData = WB_DAT_RD_IN;
ReadDataMasked[31:24] = Sel[3] ? ReadData[31:24] : 8'h00;
ReadDataMasked[23:16] = Sel[2] ? ReadData[23:16] : 8'h00;
ReadDataMasked[15: 8] = Sel[1] ? ReadData[15: 8] : 8'h00;
ReadDataMasked[ 7: 0] = Sel[0] ? ReadData[ 7: 0] : 8'h00;
ExpDataMasked [31:24] = Sel[3] ? ExpData[31:24] : 8'h00;
ExpDataMasked [23:16] = Sel[2] ? ExpData[23:16] : 8'h00;
ExpDataMasked [15: 8] = Sel[1] ? ExpData[15: 8] : 8'h00;
ExpDataMasked [ 7: 0] = Sel[0] ? ExpData[ 7: 0] : 8'h00;
end
else if (WB_ERR_IN)
begin
$display("[ERROR] WB Read Failed - at time %4t", $time);
ReadData = WB_DAT_RD_IN;
ExpDataMasked = ~ WB_DAT_RD_IN;
end
if (ReadDataMasked !== ExpDataMasked)
begin
$display("[ERROR] READ : Addr = 0x%h, Sel = 0x%h, Read Data = 0x%h, Expected Data = 0x%h, Time = %d", Addr, Sel, ReadData, ExpData, $realtime);
$display("[ERROR] Masked Read Data is 0x%h, Masked Expected Data is 0x%h", ReadDataMasked, ExpDataMasked);
end
else
begin
$display("[INFO ] READ : Addr = 0x%h, Sel = 0x%h, Read Data = 0x%h, Expected Data = 0x%h, Time = %d", Addr, Sel, ReadData, ExpData, $realtime);
end
WbCyc <= 1'b0;
WbStb <= 1'b0;
WbAdr <= 32'h0000_0000;
WbSel <= 4'h0;
WbWe <= 1'b0;
end
endtask
task automatic wbBurstWrite32b
(
input int Addr [],
input int WriteData []
);
int burstBeatNum;
int unsigned startClk [] ;
int unsigned endClk [] ;
int unsigned addrCount = 0;
int unsigned dataCount = 0;
burstBeatNum = Addr.size();
startClk = new[burstBeatNum];
endClk = new[burstBeatNum];
$display("[INFO ] BURST WRITE: Burst starting at 0x%x, length %02d at time %4t", Addr[0], burstBeatNum, $realtime);
WbCyc <= 1'b1;
fork
begin : ADDR_ISSUE
foreach (Addr[i])
begin
if (| Addr[i][1:0])
begin
$display("[ERROR] BURST WRITE: Addr = 0x%h, Unaligned access. Time = %d", Addr[i], $realtime);
end
WbStb <= 1'b1;
WbAdr <= Addr[i];
WbSel <= 4'b1111;
WbWe <= 1'b1;
WbDatWr <= WriteData[i];
@(posedge CLK);
startClk[i] = clkCount;
while (WB_STALL_IN) @(posedge CLK);
addrCount++;
$display("[INFO ] BURST WRITE: Address 0x%x (%3d of %3d), Data 0x%x accepted at time %4t", Addr[i], addrCount, burstBeatNum, WriteData[i], $realtime);
end
WbStb <= 1'b0;
WbAdr <= 32'h0000_0000;
WbSel <= 4'b0000;
WbWe <= 1'b0;
WbDatWr <= 32'h0000_0000;
end
begin : DATA_ACK
foreach (Addr[i])
begin
while (!((WB_ACK_IN || WB_ERR_IN) && (addrCount > i))) @(posedge CLK);
endClk[i] = clkCount;
dataCount++;
if (WB_ACK_IN)
begin
$display("[INFO ] BURST WRITE: Address 0x%x , Data 0x%x ACK seen (%3d of %3d). Latency = %3d at time %4t",
Addr[i], WriteData[i], dataCount, burstBeatNum, (endClk[i] - startClk[i]-1), $realtime);
end
else if (WB_ERR_IN)
begin
$display("[ERROR] BURST WRITE: Failed - Address 0x%x , Data 0x%x ERR seen (%3d of %3d). Latency = %3d at time %4t",
Addr[i], WriteData[i], dataCount, burstBeatNum, (endClk[i] - startClk[i]-1), $realtime);
end
if (dataCount < burstBeatNum) @(posedge CLK);
end
end
join
$display("[INFO ] BURST WRITE: Completed at time %4t", $realtime);
WbCyc <= 1'b0;
endtask
task automatic wbBurstRead32b
(
input int Addr [],
output int ReadData []
);
int burstBeatNum;
int unsigned startClk [] ;
int unsigned endClk [] ;
int unsigned addrCount = 0;
int unsigned dataCount = 0;
burstBeatNum = Addr.size();
ReadData = new[burstBeatNum];
startClk = new[burstBeatNum];
endClk = new[burstBeatNum];
$display("[INFO ] BURST READ: Burst starting at 0x%x, length %02d at time %4t", Addr[0], burstBeatNum, $realtime);
WbCyc <= 1'b1;
WbDatWr <= 32'h0000_0000;
fork
begin : ADDR_ISSUE
foreach (Addr[i])
begin
if (| Addr[i][1:0])
begin
$display("[ERROR] BURST READ: Addr = 0x%h, Unaligned access. Time = %d", Addr[i], $realtime);
end
WbStb <= 1'b1;
WbAdr <= Addr[i];
WbSel <= 4'b1111;
WbWe <= 1'b0;
@(posedge CLK);
startClk[i] = clkCount;
while (WB_STALL_IN) @(posedge CLK);
addrCount++;
$display("[INFO ] BURST READ: Address 0x%x (%3d of %3d) accepted at time %4t", Addr[i], addrCount, burstBeatNum, $realtime);
end
WbStb <= 1'b0;
WbAdr <= 32'h0000_0000;
WbSel <= 4'b0000;
WbWe <= 1'b0;
end
begin : DATA_ACK
foreach (Addr[i])
begin
while (!((WB_ACK_IN || WB_ERR_IN) && (addrCount > i))) @(posedge CLK);
endClk[i] = clkCount;
dataCount++;
if (WB_ACK_IN)
begin
$display("[INFO ] BURST READ: Address 0x%x , Data = 0x%x (%3d of %3d). Latency = %3d CLKs at time %4t",
Addr[i], WB_DAT_RD_IN, dataCount, burstBeatNum, (endClk[i] - startClk[i]-1), $realtime);
ReadData[i] = WB_DAT_RD_IN;
end
else if (WB_ERR_IN)
begin
$display("[ERROR] BURST READ: Failed - Address 0x%x , Data = 0x%x (%3d of %3d). Latency = %3d CLKs at time %4t",
Addr[i], WB_DAT_RD_IN, dataCount, burstBeatNum, (endClk[i] - startClk[i]-1), $realtime);
ReadData[i] = 32'hxxxx_xxxx;
end
if (dataCount < burstBeatNum) @(posedge CLK);
end
end
join
$display("[INFO ] BURST READ: Completed at time %4t", $realtime);
WbCyc <= 1'b0;
endtask
task automatic wbOverlapWriteVerify
(
input int RamBaseAddr ,
input int RamSizeByte ,
output int TestPass
);
begin
int AddrLoop;
int WriteData;
int expReadData;
int expReadAddr;
int DataQ [$];
@(posedge CLK);
TestPass = 1;
fork
begin : ADDR_PHASE
for (AddrLoop = RamBaseAddr ; AddrLoop < (RamBaseAddr + RamSizeByte) ; AddrLoop = AddrLoop + 4)
begin
WriteData = $urandom();
WbCyc <= 1'b1;
WbStb <= 1'b1;
WbWe <= 1'b1;
WbSel <= 4'b1111;
WbAdr <= AddrLoop;
WbDatWr <= WriteData;
@(posedge CLK);
while (WB_STALL_IN)
@(posedge CLK);
DataQ.push_front(WriteData);
$display("[DEBUG] SRAM Write Accepted. Addr = 0x%x, Sel = 0b%b, Write Data = 0x%x", AddrLoop, 4'b1111, WriteData);
WbCyc <= 1'b1;
WbStb <= 1'b1;
WbWe <= 1'b0;
WbSel <= 4'b1111;
WbAdr <= AddrLoop;
WbDatWr <= 32'h0000_0000;
@(posedge CLK);
while (WB_STALL_IN)
@(posedge CLK);
$display("[DEBUG] SRAM Read Accepted. Addr = 0x%x, Sel = 0b%b, ", AddrLoop, 4'b1111);
end
end
begin : RD_DATA_PHASE
while (!(WbCyc && WbStb && !WbWe && !WB_STALL_IN))
@(posedge CLK);
@(posedge CLK);
expReadData = DataQ.pop_back();
if (expReadData != WB_DAT_RD_IN)
begin
$display("[ERROR] Read Data Mismatch at Addr = 0x%x, Expected = 0x%x, Read = 0x%x", expReadAddr, expReadData, WB_DAT_RD_IN );
TestPass = 0;
end
else
begin
end
end
join
WbStb <= 1'b0;
while (WB_ACK_IN)
@(posedge CLK);
WbCyc <= 1'b0;
WbWe <= 1'b0;
WbSel <= 4'b0000;
WbAdr <= 32'h0000_0000;
WbDatWr <= 32'h0000_0000;
end
endtask
endmodule | 1 |
138,332 | data/full_repos/permissive/83270534/mercury/rtl/digital_top.v | 83,270,534 | digital_top.v | v | 438 | 114 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/mercury/rtl/digital_top.v:98: Cannot find include file: mem_map.v\n`include "mem_map.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/mercury/rtl,data/full_repos/permissive/83270534/mem_map.v\n data/full_repos/permissive/83270534/mercury/rtl,data/full_repos/permissive/83270534/mem_map.v.v\n data/full_repos/permissive/83270534/mercury/rtl,data/full_repos/permissive/83270534/mem_map.v.sv\n mem_map.v\n mem_map.v.v\n mem_map.v.sv\n obj_dir/mem_map.v\n obj_dir/mem_map.v.v\n obj_dir/mem_map.v.sv\n%Error: Exiting due to 1 error(s)\n' | 302,174 | module | module DIGITAL_TOP
(
input CLK ,
input RST_SYNC ,
input [ 3:0] BTN_IN ,
input EPP_ASTB_IN ,
input EPP_DSTB_IN ,
output EPP_WAIT_OUT ,
output FLASH_CS_OUT ,
output FLASH_RP_OUT ,
input FLASH_ST_STS_IN ,
output [ 7:0] LED_OUT ,
output [23:0] MEM_ADDR_OUT ,
inout [15:0] MEM_DATA_INOUT ,
output MEM_OE_OUT ,
output MEM_WR_OUT ,
inout PS2_CLK_INOUT ,
inout PS2_DATA_INOUT ,
output RAM_ADV_OUT ,
output RAM_CLK_OUT ,
output RAM_CRE_OUT ,
output RAM_CS_OUT ,
output RAM_LB_OUT ,
output RAM_UB_OUT ,
input RAM_WAIT_IN ,
input RS232_RX_IN ,
inout RS232_TX_INOUT ,
output [3:0] SSEG_AN_OUT ,
output [7:0] SSEG_K_OUT ,
input [7:0] SW_IN ,
output [1:0] USB_ADDR_OUT ,
input USB_CLK_IN ,
inout [7:0] USB_DATA_INOUT ,
input USB_DIR_IN ,
input USB_FLAG_IN ,
input USB_MODE_IN ,
output USB_OE_OUT ,
output USB_PKTEND_OUT ,
output USB_WR_OUT ,
output [1:0] VGA_BLUE_OUT ,
output [2:0] VGA_GREEN_OUT ,
output VGA_HSYNC_OUT ,
output [2:0] VGA_RED_OUT ,
output VGA_VSYNC_OUT
);
`include "mem_map.v"
reg [1:0] Button [3:0];
reg [1:0] Switch [7:0];
wire CoreInstCyc ;
wire CoreInstStb ;
wire [31:0] CoreInstAdr ;
wire CoreInstAck ;
wire [31:0] CoreInstDatRd ;
wire CoreDataCyc ;
wire CoreDataStb ;
wire [31:0] CoreDataAdr ;
wire [ 3:0] CoreDataSel ;
wire CoreDataWe ;
wire CoreDataAck ;
wire [31:0] CoreDataDatRd ;
wire [31:0] CoreDataDatWr ;
wire RomInstCyc ;
wire RomInstStb ;
wire [31:0] RomInstAdr ;
wire RomInstAck ;
wire [31:0] RomInstDatRd ;
wire RamDataCyc ;
wire RamDataStb ;
wire [31:0] RamDataAdr ;
wire [ 3:0] RamDataSel ;
wire RamDataWe ;
wire RamDataAck ;
wire [31:0] RamDataDatRd ;
wire [31:0] RamDataDatWr ;
wire UartRegsDataCyc ;
wire UartRegsDataStb ;
reg [ 2:0] UartRegsDataAdr ;
wire [ 3:0] UartRegsDataSel ;
wire UartRegsDataWe ;
wire UartRegsDataAck ;
wire [ 7:0] UartRegsDataDatRd ;
reg [31:0] UartRegsDataDatRd32b ;
reg [ 7:0] UartRegsDataDatWr ;
wire UartIrq ;
wire Nexys2RegsDataCyc ;
wire Nexys2RegsDataStb ;
wire [31:0] Nexys2RegsDataAdr ;
wire [ 3:0] Nexys2RegsDataSel ;
wire Nexys2RegsDataWe ;
wire Nexys2RegsDataAck ;
wire [31:0] Nexys2RegsDataDatRd ;
wire [31:0] Nexys2RegsDataDatWr ;
wire RamAddrValid;
wire UartRegsAddrValid;
wire Nexys2RegsAddrValid;
assign RamAddrValid = (CoreDataAdr[31:16] == DATA_RAM_BASE[31:16]);
assign UartRegsAddrValid = (CoreDataAdr[31:16] == UART_REGS_BASE[31:16]);
assign Nexys2RegsAddrValid = (CoreDataAdr[31:16] == NEXYS2_REGS_BASE[31:16]);
assign RomInstEn = CoreInstCyc & CoreInstStb;
assign RomInstCyc = CoreInstCyc;
assign RomInstStb = CoreInstStb;
assign RomInstAdr =CoreInstAdr;
assign RamDataCyc = RamAddrValid & CoreDataCyc ;
assign RamDataStb = RamAddrValid & CoreDataStb ;
assign RamDataAdr = {32{RamAddrValid}} & CoreDataAdr ;
assign RamDataSel = {4{RamAddrValid}} & CoreDataSel ;
assign RamDataWe = RamAddrValid & CoreDataWe ;
assign RamDataDatWr = {32{RamAddrValid}} & CoreDataDatWr ;
assign UartRegsDataCyc = UartRegsAddrValid & CoreDataCyc ;
assign UartRegsDataStb = UartRegsAddrValid & CoreDataStb ;
assign UartRegsDataSel = {4{UartRegsAddrValid}} & CoreDataSel ;
assign UartRegsDataWe = UartRegsAddrValid & CoreDataWe ;
assign CoreInstAck = RomInstAck;
assign CoreInstDatRd = RomInstDatRd;
assign CoreDataAck = ( (RamAddrValid & RamDataAck)
| (UartRegsAddrValid & UartRegsDataAck)
| (Nexys2RegsAddrValid & Nexys2RegsDataAck)
);
assign CoreDataDatRd = ( ({32{RamAddrValid}} & RamDataDatRd)
| ({32{UartRegsAddrValid}} & UartRegsDataDatRd32b)
| ({32{Nexys2RegsAddrValid}} & Nexys2RegsDataDatRd)
);
assign EPP_WAIT_OUT = 1'b0;
assign FLASH_CS_OUT = 1'b0;
assign FLASH_RP_OUT = 1'b0;
assign LED_OUT = 8'h00;
assign MEM_ADDR_OUT = 24'h000000;
assign MEM_DATA_INOUT = 16'h0000;
assign MEM_OE_OUT = 1'b0;
assign MEM_WR_OUT = 1'b0;
assign PS2_CLK_INOUT = 1'b0;
assign PS2_DATA_INOUT = 1'b0;
assign RAM_ADV_OUT = 1'b0;
assign RAM_CLK_OUT = 1'b0;
assign RAM_CRE_OUT = 1'b0;
assign RAM_CS_OUT = 1'b0;
assign RAM_LB_OUT = 1'b0;
assign RAM_UB_OUT = 1'b0;
assign SSEG_AN_OUT = 4'hF;
assign SSEG_K_OUT = 8'hFF;
assign USB_ADDR_OUT = 2'b00;
assign USB_DATA_INOUT = 8'h00;
assign USB_OE_OUT = 1'b0;
assign USB_PKTEND_OUT = 1'b0;
assign USB_WR_OUT = 1'b0;
assign VGA_BLUE_OUT = 2'b00;
assign VGA_GREEN_OUT = 3'b000;
assign VGA_HSYNC_OUT = 1'b0;
assign VGA_RED_OUT = 3'b000;
assign VGA_VSYNC_OUT = 1'b0;
always @*
begin
UartRegsDataAdr = 3'b000;
if (UartRegsAddrValid)
begin
UartRegsDataAdr[2] = CoreDataAdr[2];
case (UartRegsDataSel[3:0])
4'b0001 : UartRegsDataAdr[1:0] = 2'h0;
4'b0010 : UartRegsDataAdr[1:0] = 2'h1;
4'b0100 : UartRegsDataAdr[1:0] = 2'h2;
4'b1000 : UartRegsDataAdr[1:0] = 2'h3;
endcase
end
end
always @*
begin
UartRegsDataDatWr = 8'h00;
case (UartRegsDataSel[3:0])
4'b0001 : UartRegsDataDatWr = CoreDataDatWr[ 7: 0];
4'b0010 : UartRegsDataDatWr = CoreDataDatWr[15: 8];
4'b0100 : UartRegsDataDatWr = CoreDataDatWr[23:16];
4'b1000 : UartRegsDataDatWr = CoreDataDatWr[31:24];
endcase
end
always @*
begin
UartRegsDataDatRd32b = 32'h0000_0000;
case (UartRegsDataSel[3:0])
4'b0001 : UartRegsDataDatRd32b = {24'h00_0000, UartRegsDataDatRd };
4'b0010 : UartRegsDataDatRd32b = {16'h0000, UartRegsDataDatRd, 8'h00 };
4'b0100 : UartRegsDataDatRd32b = {8'h00, UartRegsDataDatRd, 16'h0000 };
4'b1000 : UartRegsDataDatRd32b = {UartRegsDataDatRd, 24'h00_0000 };
endcase
end
INST_ROM_WRAP inst_rom_wrap
(
.CLK (CLK ),
.RST_SYNC (RST_SYNC ),
.WB_CYC_IN (RomInstCyc ),
.WB_STB_IN (RomInstStb ),
.WB_ADR_IN (RomInstAdr ),
.WB_ACK_OUT (RomInstAck ),
.WB_DAT_RD_OUT (RomInstDatRd )
);
DATA_RAM
#(.ADDR_WIDTH (RAM_ADDR_WIDTH))
data_ram
(
.CLK (CLK ),
.RST_SYNC (RST_SYNC ),
.RAM_CYC_IN (RamDataCyc ),
.RAM_STB_IN (RamDataStb ),
.RAM_ADR_IN ({ {32 - RAM_ADDR_WIDTH{1'b0}} , RamDataAdr[RAM_ADDR_WIDTH-1+2:2] }),
.RAM_SEL_IN (RamDataSel ),
.RAM_WE_IN (RamDataWe ),
.RAM_ACK_OUT (RamDataAck ),
.RAM_DAT_RD_OUT (RamDataDatRd ),
.RAM_DAT_WR_IN (RamDataDatWr )
);
`define DATA_BUS_WIDTH_8
uart_top uart_top
(
.wb_clk_i (CLK ),
.wb_rst_i (RST_SYNC ),
.wb_adr_i (UartRegsDataAdr ),
.wb_dat_i (UartRegsDataDatWr ),
.wb_dat_o (UartRegsDataDatRd ),
.wb_we_i (UartRegsDataWe ),
.wb_stb_i (UartRegsDataStb ),
.wb_cyc_i (UartRegsDataCyc ),
.wb_ack_o (UartRegsDataAck ),
.wb_sel_i (UartRegsDataSel ),
.int_o (UartIrq ),
.stx_pad_o (RS232_TX_INOUT ),
.srx_pad_i (RS232_RX_IN ),
.rts_pad_o ( ),
.cts_pad_i (1'b0 ),
.dtr_pad_o ( ),
.dsr_pad_i (1'b0 ),
.ri_pad_i (1'b0 ),
.dcd_pad_i (1'b0 )
);
CPU_CORE
#(.PC_RST_VALUE (32'hBFC0_0000 ))
cpu_core
(
.CLK (CLK ),
.RST_SYNC (RST_SYNC ),
.CORE_INST_CYC_OUT (CoreInstCyc ),
.CORE_INST_STB_OUT (CoreInstStb ),
.CORE_INST_ADR_OUT (CoreInstAdr ),
.CORE_INST_ACK_IN (CoreInstAck ),
.CORE_INST_DAT_RD_IN (CoreInstDatRd ),
.CORE_DATA_CYC_OUT (CoreDataCyc ),
.CORE_DATA_STB_OUT (CoreDataStb ),
.CORE_DATA_ADR_OUT (CoreDataAdr ),
.CORE_DATA_SEL_OUT (CoreDataSel ),
.CORE_DATA_WE_OUT (CoreDataWe ),
.CORE_DATA_ACK_IN (CoreDataAck ),
.CORE_DATA_DAT_RD_IN (CoreDataDatRd ),
.CORE_DATA_DAT_WR_OUT (CoreDataDatWr )
);
endmodule | module DIGITAL_TOP
(
input CLK ,
input RST_SYNC ,
input [ 3:0] BTN_IN ,
input EPP_ASTB_IN ,
input EPP_DSTB_IN ,
output EPP_WAIT_OUT ,
output FLASH_CS_OUT ,
output FLASH_RP_OUT ,
input FLASH_ST_STS_IN ,
output [ 7:0] LED_OUT ,
output [23:0] MEM_ADDR_OUT ,
inout [15:0] MEM_DATA_INOUT ,
output MEM_OE_OUT ,
output MEM_WR_OUT ,
inout PS2_CLK_INOUT ,
inout PS2_DATA_INOUT ,
output RAM_ADV_OUT ,
output RAM_CLK_OUT ,
output RAM_CRE_OUT ,
output RAM_CS_OUT ,
output RAM_LB_OUT ,
output RAM_UB_OUT ,
input RAM_WAIT_IN ,
input RS232_RX_IN ,
inout RS232_TX_INOUT ,
output [3:0] SSEG_AN_OUT ,
output [7:0] SSEG_K_OUT ,
input [7:0] SW_IN ,
output [1:0] USB_ADDR_OUT ,
input USB_CLK_IN ,
inout [7:0] USB_DATA_INOUT ,
input USB_DIR_IN ,
input USB_FLAG_IN ,
input USB_MODE_IN ,
output USB_OE_OUT ,
output USB_PKTEND_OUT ,
output USB_WR_OUT ,
output [1:0] VGA_BLUE_OUT ,
output [2:0] VGA_GREEN_OUT ,
output VGA_HSYNC_OUT ,
output [2:0] VGA_RED_OUT ,
output VGA_VSYNC_OUT
); |
`include "mem_map.v"
reg [1:0] Button [3:0];
reg [1:0] Switch [7:0];
wire CoreInstCyc ;
wire CoreInstStb ;
wire [31:0] CoreInstAdr ;
wire CoreInstAck ;
wire [31:0] CoreInstDatRd ;
wire CoreDataCyc ;
wire CoreDataStb ;
wire [31:0] CoreDataAdr ;
wire [ 3:0] CoreDataSel ;
wire CoreDataWe ;
wire CoreDataAck ;
wire [31:0] CoreDataDatRd ;
wire [31:0] CoreDataDatWr ;
wire RomInstCyc ;
wire RomInstStb ;
wire [31:0] RomInstAdr ;
wire RomInstAck ;
wire [31:0] RomInstDatRd ;
wire RamDataCyc ;
wire RamDataStb ;
wire [31:0] RamDataAdr ;
wire [ 3:0] RamDataSel ;
wire RamDataWe ;
wire RamDataAck ;
wire [31:0] RamDataDatRd ;
wire [31:0] RamDataDatWr ;
wire UartRegsDataCyc ;
wire UartRegsDataStb ;
reg [ 2:0] UartRegsDataAdr ;
wire [ 3:0] UartRegsDataSel ;
wire UartRegsDataWe ;
wire UartRegsDataAck ;
wire [ 7:0] UartRegsDataDatRd ;
reg [31:0] UartRegsDataDatRd32b ;
reg [ 7:0] UartRegsDataDatWr ;
wire UartIrq ;
wire Nexys2RegsDataCyc ;
wire Nexys2RegsDataStb ;
wire [31:0] Nexys2RegsDataAdr ;
wire [ 3:0] Nexys2RegsDataSel ;
wire Nexys2RegsDataWe ;
wire Nexys2RegsDataAck ;
wire [31:0] Nexys2RegsDataDatRd ;
wire [31:0] Nexys2RegsDataDatWr ;
wire RamAddrValid;
wire UartRegsAddrValid;
wire Nexys2RegsAddrValid;
assign RamAddrValid = (CoreDataAdr[31:16] == DATA_RAM_BASE[31:16]);
assign UartRegsAddrValid = (CoreDataAdr[31:16] == UART_REGS_BASE[31:16]);
assign Nexys2RegsAddrValid = (CoreDataAdr[31:16] == NEXYS2_REGS_BASE[31:16]);
assign RomInstEn = CoreInstCyc & CoreInstStb;
assign RomInstCyc = CoreInstCyc;
assign RomInstStb = CoreInstStb;
assign RomInstAdr =CoreInstAdr;
assign RamDataCyc = RamAddrValid & CoreDataCyc ;
assign RamDataStb = RamAddrValid & CoreDataStb ;
assign RamDataAdr = {32{RamAddrValid}} & CoreDataAdr ;
assign RamDataSel = {4{RamAddrValid}} & CoreDataSel ;
assign RamDataWe = RamAddrValid & CoreDataWe ;
assign RamDataDatWr = {32{RamAddrValid}} & CoreDataDatWr ;
assign UartRegsDataCyc = UartRegsAddrValid & CoreDataCyc ;
assign UartRegsDataStb = UartRegsAddrValid & CoreDataStb ;
assign UartRegsDataSel = {4{UartRegsAddrValid}} & CoreDataSel ;
assign UartRegsDataWe = UartRegsAddrValid & CoreDataWe ;
assign CoreInstAck = RomInstAck;
assign CoreInstDatRd = RomInstDatRd;
assign CoreDataAck = ( (RamAddrValid & RamDataAck)
| (UartRegsAddrValid & UartRegsDataAck)
| (Nexys2RegsAddrValid & Nexys2RegsDataAck)
);
assign CoreDataDatRd = ( ({32{RamAddrValid}} & RamDataDatRd)
| ({32{UartRegsAddrValid}} & UartRegsDataDatRd32b)
| ({32{Nexys2RegsAddrValid}} & Nexys2RegsDataDatRd)
);
assign EPP_WAIT_OUT = 1'b0;
assign FLASH_CS_OUT = 1'b0;
assign FLASH_RP_OUT = 1'b0;
assign LED_OUT = 8'h00;
assign MEM_ADDR_OUT = 24'h000000;
assign MEM_DATA_INOUT = 16'h0000;
assign MEM_OE_OUT = 1'b0;
assign MEM_WR_OUT = 1'b0;
assign PS2_CLK_INOUT = 1'b0;
assign PS2_DATA_INOUT = 1'b0;
assign RAM_ADV_OUT = 1'b0;
assign RAM_CLK_OUT = 1'b0;
assign RAM_CRE_OUT = 1'b0;
assign RAM_CS_OUT = 1'b0;
assign RAM_LB_OUT = 1'b0;
assign RAM_UB_OUT = 1'b0;
assign SSEG_AN_OUT = 4'hF;
assign SSEG_K_OUT = 8'hFF;
assign USB_ADDR_OUT = 2'b00;
assign USB_DATA_INOUT = 8'h00;
assign USB_OE_OUT = 1'b0;
assign USB_PKTEND_OUT = 1'b0;
assign USB_WR_OUT = 1'b0;
assign VGA_BLUE_OUT = 2'b00;
assign VGA_GREEN_OUT = 3'b000;
assign VGA_HSYNC_OUT = 1'b0;
assign VGA_RED_OUT = 3'b000;
assign VGA_VSYNC_OUT = 1'b0;
always @*
begin
UartRegsDataAdr = 3'b000;
if (UartRegsAddrValid)
begin
UartRegsDataAdr[2] = CoreDataAdr[2];
case (UartRegsDataSel[3:0])
4'b0001 : UartRegsDataAdr[1:0] = 2'h0;
4'b0010 : UartRegsDataAdr[1:0] = 2'h1;
4'b0100 : UartRegsDataAdr[1:0] = 2'h2;
4'b1000 : UartRegsDataAdr[1:0] = 2'h3;
endcase
end
end
always @*
begin
UartRegsDataDatWr = 8'h00;
case (UartRegsDataSel[3:0])
4'b0001 : UartRegsDataDatWr = CoreDataDatWr[ 7: 0];
4'b0010 : UartRegsDataDatWr = CoreDataDatWr[15: 8];
4'b0100 : UartRegsDataDatWr = CoreDataDatWr[23:16];
4'b1000 : UartRegsDataDatWr = CoreDataDatWr[31:24];
endcase
end
always @*
begin
UartRegsDataDatRd32b = 32'h0000_0000;
case (UartRegsDataSel[3:0])
4'b0001 : UartRegsDataDatRd32b = {24'h00_0000, UartRegsDataDatRd };
4'b0010 : UartRegsDataDatRd32b = {16'h0000, UartRegsDataDatRd, 8'h00 };
4'b0100 : UartRegsDataDatRd32b = {8'h00, UartRegsDataDatRd, 16'h0000 };
4'b1000 : UartRegsDataDatRd32b = {UartRegsDataDatRd, 24'h00_0000 };
endcase
end
INST_ROM_WRAP inst_rom_wrap
(
.CLK (CLK ),
.RST_SYNC (RST_SYNC ),
.WB_CYC_IN (RomInstCyc ),
.WB_STB_IN (RomInstStb ),
.WB_ADR_IN (RomInstAdr ),
.WB_ACK_OUT (RomInstAck ),
.WB_DAT_RD_OUT (RomInstDatRd )
);
DATA_RAM
#(.ADDR_WIDTH (RAM_ADDR_WIDTH))
data_ram
(
.CLK (CLK ),
.RST_SYNC (RST_SYNC ),
.RAM_CYC_IN (RamDataCyc ),
.RAM_STB_IN (RamDataStb ),
.RAM_ADR_IN ({ {32 - RAM_ADDR_WIDTH{1'b0}} , RamDataAdr[RAM_ADDR_WIDTH-1+2:2] }),
.RAM_SEL_IN (RamDataSel ),
.RAM_WE_IN (RamDataWe ),
.RAM_ACK_OUT (RamDataAck ),
.RAM_DAT_RD_OUT (RamDataDatRd ),
.RAM_DAT_WR_IN (RamDataDatWr )
);
`define DATA_BUS_WIDTH_8
uart_top uart_top
(
.wb_clk_i (CLK ),
.wb_rst_i (RST_SYNC ),
.wb_adr_i (UartRegsDataAdr ),
.wb_dat_i (UartRegsDataDatWr ),
.wb_dat_o (UartRegsDataDatRd ),
.wb_we_i (UartRegsDataWe ),
.wb_stb_i (UartRegsDataStb ),
.wb_cyc_i (UartRegsDataCyc ),
.wb_ack_o (UartRegsDataAck ),
.wb_sel_i (UartRegsDataSel ),
.int_o (UartIrq ),
.stx_pad_o (RS232_TX_INOUT ),
.srx_pad_i (RS232_RX_IN ),
.rts_pad_o ( ),
.cts_pad_i (1'b0 ),
.dtr_pad_o ( ),
.dsr_pad_i (1'b0 ),
.ri_pad_i (1'b0 ),
.dcd_pad_i (1'b0 )
);
CPU_CORE
#(.PC_RST_VALUE (32'hBFC0_0000 ))
cpu_core
(
.CLK (CLK ),
.RST_SYNC (RST_SYNC ),
.CORE_INST_CYC_OUT (CoreInstCyc ),
.CORE_INST_STB_OUT (CoreInstStb ),
.CORE_INST_ADR_OUT (CoreInstAdr ),
.CORE_INST_ACK_IN (CoreInstAck ),
.CORE_INST_DAT_RD_IN (CoreInstDatRd ),
.CORE_DATA_CYC_OUT (CoreDataCyc ),
.CORE_DATA_STB_OUT (CoreDataStb ),
.CORE_DATA_ADR_OUT (CoreDataAdr ),
.CORE_DATA_SEL_OUT (CoreDataSel ),
.CORE_DATA_WE_OUT (CoreDataWe ),
.CORE_DATA_ACK_IN (CoreDataAck ),
.CORE_DATA_DAT_RD_IN (CoreDataDatRd ),
.CORE_DATA_DAT_WR_OUT (CoreDataDatWr )
);
endmodule | 1 |
138,334 | data/full_repos/permissive/83270534/mercury/rtl/inst_rom.v | 83,270,534 | inst_rom.v | v | 18 | 84 | [] | [] | [] | [(1, 17)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/83270534/mercury/rtl/inst_rom.v:13: Bit extraction of array[2047:0] requires 11 bit index, not 13 bits.\n : ... In instance INST_ROM\n data <= RomArray[addr[12:0]]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 302,176 | module | module INST_ROM (clk, en, addr, data);
input clk;
input en;
input [12:0] addr;
output reg [31:0] data;
reg [31:0] RomArray [2047:0];
always @(posedge clk) begin
if (en)
begin
data <= RomArray[addr[12:0]];
end
end
endmodule | module INST_ROM (clk, en, addr, data); |
input clk;
input en;
input [12:0] addr;
output reg [31:0] data;
reg [31:0] RomArray [2047:0];
always @(posedge clk) begin
if (en)
begin
data <= RomArray[addr[12:0]];
end
end
endmodule | 1 |
138,336 | data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v | 83,270,534 | testcase.v | v | 125 | 144 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:3: Cannot find include file: mem_map.v\n`include "mem_map.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram,data/full_repos/permissive/83270534/mem_map.v\n data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram,data/full_repos/permissive/83270534/mem_map.v.v\n data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram,data/full_repos/permissive/83270534/mem_map.v.sv\n mem_map.v\n mem_map.v.v\n mem_map.v.sv\n obj_dir/mem_map.v\n obj_dir/mem_map.v.v\n obj_dir/mem_map.v.sv\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:4: Cannot find include file: tb_defines.v\n`include "tb_defines.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:27: Define or directive not defined: \'`dataBfm\'\n `dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4\'hF, randomData[ramAddrLoop]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:27: syntax error, unexpected \'.\'\n `dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4\'hF, randomData[ramAddrLoop]);\n ^\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:28: Define or directive not defined: \'`dataBfm\'\n `dataBfm.wbReadCompare (DATA_RAM_BASE + (ramAddrLoop << 2), 4\'hF, randomData[ramAddrLoop]);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:35: Define or directive not defined: \'`dataBfmArrayB3\'\n dataBfmArrayWd = {`dataBfmArrayB3[ramAddrLoop], `dataBfmArrayB2[ramAddrLoop], `dataBfmArrayB1[ramAddrLoop], `dataBfmArrayB0[ramAddrLoop]};\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:35: syntax error, unexpected \'[\', expecting TYPE-IDENTIFIER\n dataBfmArrayWd = {`dataBfmArrayB3[ramAddrLoop], `dataBfmArrayB2[ramAddrLoop], `dataBfmArrayB1[ramAddrLoop], `dataBfmArrayB0[ramAddrLoop]};\n ^\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:35: Define or directive not defined: \'`dataBfmArrayB2\'\n dataBfmArrayWd = {`dataBfmArrayB3[ramAddrLoop], `dataBfmArrayB2[ramAddrLoop], `dataBfmArrayB1[ramAddrLoop], `dataBfmArrayB0[ramAddrLoop]};\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:35: Define or directive not defined: \'`dataBfmArrayB1\'\n dataBfmArrayWd = {`dataBfmArrayB3[ramAddrLoop], `dataBfmArrayB2[ramAddrLoop], `dataBfmArrayB1[ramAddrLoop], `dataBfmArrayB0[ramAddrLoop]};\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:35: Define or directive not defined: \'`dataBfmArrayB0\'\n dataBfmArrayWd = {`dataBfmArrayB3[ramAddrLoop], `dataBfmArrayB2[ramAddrLoop], `dataBfmArrayB1[ramAddrLoop], `dataBfmArrayB0[ramAddrLoop]};\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:39: Define or directive not defined: \'`dataBfmArrayB3\'\n `dataBfmArrayB3[ramAddrLoop] = 8\'hxx;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:39: syntax error, unexpected \'[\'\n `dataBfmArrayB3[ramAddrLoop] = 8\'hxx;\n ^\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:40: Define or directive not defined: \'`dataBfmArrayB2\'\n `dataBfmArrayB2[ramAddrLoop] = 8\'hxx;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:41: Define or directive not defined: \'`dataBfmArrayB1\'\n `dataBfmArrayB1[ramAddrLoop] = 8\'hxx;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:42: Define or directive not defined: \'`dataBfmArrayB0\'\n `dataBfmArrayB0[ramAddrLoop] = 8\'hxx;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:53: Define or directive not defined: \'`dataBfm\'\n `dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4\'h3, {16\'h0000, randomData[ramAddrLoop][15:0]}); \n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:53: syntax error, unexpected \'.\'\n `dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4\'h3, {16\'h0000, randomData[ramAddrLoop][15:0]}); \n ^\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:54: Define or directive not defined: \'`dataBfm\'\n `dataBfm.wbReadCompare (DATA_RAM_BASE + (ramAddrLoop << 2), 4\'h3, {16\'h0000, randomData[ramAddrLoop][15:0]});\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:55: Define or directive not defined: \'`dataBfm\'\n `dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4\'hC, {randomData[ramAddrLoop][31:16], 16\'h0000}); \n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:56: Define or directive not defined: \'`dataBfm\'\n `dataBfm.wbReadCompare (DATA_RAM_BASE + (ramAddrLoop << 2), 4\'hC, {randomData[ramAddrLoop][31:16], 16\'h0000});\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:63: Define or directive not defined: \'`dataBfmArrayB3\'\n dataBfmArrayWd = {`dataBfmArrayB3[ramAddrLoop], `dataBfmArrayB2[ramAddrLoop], `dataBfmArrayB1[ramAddrLoop], `dataBfmArrayB0[ramAddrLoop]};\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:63: syntax error, unexpected \'[\', expecting TYPE-IDENTIFIER\n dataBfmArrayWd = {`dataBfmArrayB3[ramAddrLoop], `dataBfmArrayB2[ramAddrLoop], `dataBfmArrayB1[ramAddrLoop], `dataBfmArrayB0[ramAddrLoop]};\n ^\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:63: Define or directive not defined: \'`dataBfmArrayB2\'\n dataBfmArrayWd = {`dataBfmArrayB3[ramAddrLoop], `dataBfmArrayB2[ramAddrLoop], `dataBfmArrayB1[ramAddrLoop], `dataBfmArrayB0[ramAddrLoop]};\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:63: Define or directive not defined: \'`dataBfmArrayB1\'\n dataBfmArrayWd = {`dataBfmArrayB3[ramAddrLoop], `dataBfmArrayB2[ramAddrLoop], `dataBfmArrayB1[ramAddrLoop], `dataBfmArrayB0[ramAddrLoop]};\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:63: Define or directive not defined: \'`dataBfmArrayB0\'\n dataBfmArrayWd = {`dataBfmArrayB3[ramAddrLoop], `dataBfmArrayB2[ramAddrLoop], `dataBfmArrayB1[ramAddrLoop], `dataBfmArrayB0[ramAddrLoop]};\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:67: Define or directive not defined: \'`dataBfmArrayB3\'\n `dataBfmArrayB3[ramAddrLoop] = 8\'hxx;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:67: syntax error, unexpected \'[\'\n `dataBfmArrayB3[ramAddrLoop] = 8\'hxx;\n ^\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:68: Define or directive not defined: \'`dataBfmArrayB2\'\n `dataBfmArrayB2[ramAddrLoop] = 8\'hxx;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:69: Define or directive not defined: \'`dataBfmArrayB1\'\n `dataBfmArrayB1[ramAddrLoop] = 8\'hxx;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:70: Define or directive not defined: \'`dataBfmArrayB0\'\n `dataBfmArrayB0[ramAddrLoop] = 8\'hxx;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:81: Define or directive not defined: \'`dataBfm\'\n `dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4\'h1, {24\'h000000, randomData[ramAddrLoop][ 7: 0]}); \n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:81: syntax error, unexpected \'.\'\n `dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4\'h1, {24\'h000000, randomData[ramAddrLoop][ 7: 0]}); \n ^\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:82: Define or directive not defined: \'`dataBfm\'\n `dataBfm.wbReadCompare (DATA_RAM_BASE + (ramAddrLoop << 2), 4\'h1, {24\'h000000, randomData[ramAddrLoop][ 7: 0]});\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:83: Define or directive not defined: \'`dataBfm\'\n `dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4\'h2, {16\'h0000, randomData[ramAddrLoop][15: 8], 8\'h00}); \n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:84: Define or directive not defined: \'`dataBfm\'\n `dataBfm.wbReadCompare (DATA_RAM_BASE + (ramAddrLoop << 2), 4\'h2, {16\'h0000, randomData[ramAddrLoop][15: 8], 8\'h00});\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:85: Define or directive not defined: \'`dataBfm\'\n `dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4\'h4, {8\'h00, randomData[ramAddrLoop][23:16], 16\'h0000}); \n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:86: Define or directive not defined: \'`dataBfm\'\n `dataBfm.wbReadCompare (DATA_RAM_BASE + (ramAddrLoop << 2), 4\'h4, {8\'h00, randomData[ramAddrLoop][23:16], 16\'h0000});\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:87: Define or directive not defined: \'`dataBfm\'\n `dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4\'h8, {randomData[ramAddrLoop][31:24] , 24\'h000000 }); \n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:88: Define or directive not defined: \'`dataBfm\'\n `dataBfm.wbReadCompare (DATA_RAM_BASE + (ramAddrLoop << 2), 4\'h8, {randomData[ramAddrLoop][31:24] , 24\'h000000 });\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:95: Define or directive not defined: \'`dataBfmArrayB3\'\n dataBfmArrayWd = {`dataBfmArrayB3[ramAddrLoop], `dataBfmArrayB2[ramAddrLoop], `dataBfmArrayB1[ramAddrLoop], `dataBfmArrayB0[ramAddrLoop]};\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:95: syntax error, unexpected \'[\', expecting TYPE-IDENTIFIER\n dataBfmArrayWd = {`dataBfmArrayB3[ramAddrLoop], `dataBfmArrayB2[ramAddrLoop], `dataBfmArrayB1[ramAddrLoop], `dataBfmArrayB0[ramAddrLoop]};\n ^\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:95: Define or directive not defined: \'`dataBfmArrayB2\'\n dataBfmArrayWd = {`dataBfmArrayB3[ramAddrLoop], `dataBfmArrayB2[ramAddrLoop], `dataBfmArrayB1[ramAddrLoop], `dataBfmArrayB0[ramAddrLoop]};\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:95: Define or directive not defined: \'`dataBfmArrayB1\'\n dataBfmArrayWd = {`dataBfmArrayB3[ramAddrLoop], `dataBfmArrayB2[ramAddrLoop], `dataBfmArrayB1[ramAddrLoop], `dataBfmArrayB0[ramAddrLoop]};\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:95: Define or directive not defined: \'`dataBfmArrayB0\'\n dataBfmArrayWd = {`dataBfmArrayB3[ramAddrLoop], `dataBfmArrayB2[ramAddrLoop], `dataBfmArrayB1[ramAddrLoop], `dataBfmArrayB0[ramAddrLoop]};\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:99: Define or directive not defined: \'`dataBfmArrayB3\'\n `dataBfmArrayB3[ramAddrLoop] = 8\'hxx;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:99: syntax error, unexpected \'[\'\n `dataBfmArrayB3[ramAddrLoop] = 8\'hxx;\n ^\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:100: Define or directive not defined: \'`dataBfmArrayB2\'\n `dataBfmArrayB2[ramAddrLoop] = 8\'hxx;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:101: Define or directive not defined: \'`dataBfmArrayB1\'\n `dataBfmArrayB1[ramAddrLoop] = 8\'hxx;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:102: Define or directive not defined: \'`dataBfmArrayB0\'\n `dataBfmArrayB0[ramAddrLoop] = 8\'hxx;\n ^~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/83270534/mercury/sim/mem_tests/data_ram/testcase.v:117: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 49 error(s), 1 warning(s)\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 302,180 | module | module TESTCASE ();
`include "mem_map.v"
`include "tb_defines.v"
integer dataLoop;
integer ramAddrLoop;
reg [31:0] dataBfmArrayWd;
reg [31:0] randomData [RAM_SIZE_WORD-1:0];
initial
begin
for (dataLoop = 0 ; dataLoop < RAM_SIZE_WORD ; dataLoop = dataLoop + 1)
begin
randomData[dataLoop] = $random();
end
end
initial
begin
$display("[INFO ] ***** DATA RAM TEST: Running 32 bit incremental test *****");
for (ramAddrLoop = 0 ; ramAddrLoop < RAM_SIZE_WORD ; ramAddrLoop = ramAddrLoop + 1)
begin
`dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4'hF, randomData[ramAddrLoop]);
`dataBfm.wbReadCompare (DATA_RAM_BASE + (ramAddrLoop << 2), 4'hF, randomData[ramAddrLoop]);
end
$display("[INFO ] ***** Checking and Clearing Data Ram ***** ");
for (ramAddrLoop = 0 ; ramAddrLoop < RAM_SIZE_WORD ; ramAddrLoop = ramAddrLoop + 1)
begin
dataBfmArrayWd = {`dataBfmArrayB3[ramAddrLoop], `dataBfmArrayB2[ramAddrLoop], `dataBfmArrayB1[ramAddrLoop], `dataBfmArrayB0[ramAddrLoop]};
if (randomData[ramAddrLoop] === dataBfmArrayWd)
begin
`dataBfmArrayB3[ramAddrLoop] = 8'hxx;
`dataBfmArrayB2[ramAddrLoop] = 8'hxx;
`dataBfmArrayB1[ramAddrLoop] = 8'hxx;
`dataBfmArrayB0[ramAddrLoop] = 8'hxx;
end
else
begin
$display("[ERROR] RAM Data at Address 0x%h is 0x%h, Expected 0x%h", ramAddrLoop, dataBfmArrayWd, randomData[ramAddrLoop]);
end
end
$display("[INFO ] ***** DATA RAM TEST: Running 16 bit incremental test *****");
for (ramAddrLoop = 0 ; ramAddrLoop < RAM_SIZE_WORD ; ramAddrLoop = ramAddrLoop + 1)
begin
`dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4'h3, {16'h0000, randomData[ramAddrLoop][15:0]});
`dataBfm.wbReadCompare (DATA_RAM_BASE + (ramAddrLoop << 2), 4'h3, {16'h0000, randomData[ramAddrLoop][15:0]});
`dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4'hC, {randomData[ramAddrLoop][31:16], 16'h0000});
`dataBfm.wbReadCompare (DATA_RAM_BASE + (ramAddrLoop << 2), 4'hC, {randomData[ramAddrLoop][31:16], 16'h0000});
end
$display("[INFO ] ***** Checking and Clearing Data Ram ***** ");
for (ramAddrLoop = 0 ; ramAddrLoop < RAM_SIZE_WORD ; ramAddrLoop = ramAddrLoop + 1)
begin
dataBfmArrayWd = {`dataBfmArrayB3[ramAddrLoop], `dataBfmArrayB2[ramAddrLoop], `dataBfmArrayB1[ramAddrLoop], `dataBfmArrayB0[ramAddrLoop]};
if (randomData[ramAddrLoop] === dataBfmArrayWd)
begin
`dataBfmArrayB3[ramAddrLoop] = 8'hxx;
`dataBfmArrayB2[ramAddrLoop] = 8'hxx;
`dataBfmArrayB1[ramAddrLoop] = 8'hxx;
`dataBfmArrayB0[ramAddrLoop] = 8'hxx;
end
else
begin
$display("[ERROR] RAM Data at Address 0x%h is 0x%h, Expected 0x%h", ramAddrLoop, dataBfmArrayWd, randomData[ramAddrLoop]);
end
end
$display("[INFO ] ***** DATA RAM TEST: Running 8 bit incremental test *****");
for (ramAddrLoop = 0 ; ramAddrLoop < RAM_SIZE_WORD ; ramAddrLoop = ramAddrLoop + 1)
begin
`dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4'h1, {24'h000000, randomData[ramAddrLoop][ 7: 0]});
`dataBfm.wbReadCompare (DATA_RAM_BASE + (ramAddrLoop << 2), 4'h1, {24'h000000, randomData[ramAddrLoop][ 7: 0]});
`dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4'h2, {16'h0000, randomData[ramAddrLoop][15: 8], 8'h00});
`dataBfm.wbReadCompare (DATA_RAM_BASE + (ramAddrLoop << 2), 4'h2, {16'h0000, randomData[ramAddrLoop][15: 8], 8'h00});
`dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4'h4, {8'h00, randomData[ramAddrLoop][23:16], 16'h0000});
`dataBfm.wbReadCompare (DATA_RAM_BASE + (ramAddrLoop << 2), 4'h4, {8'h00, randomData[ramAddrLoop][23:16], 16'h0000});
`dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4'h8, {randomData[ramAddrLoop][31:24] , 24'h000000 });
`dataBfm.wbReadCompare (DATA_RAM_BASE + (ramAddrLoop << 2), 4'h8, {randomData[ramAddrLoop][31:24] , 24'h000000 });
end
$display("[INFO ] ***** Checking and Clearing Data Ram ***** ");
for (ramAddrLoop = 0 ; ramAddrLoop < RAM_SIZE_WORD ; ramAddrLoop = ramAddrLoop + 1)
begin
dataBfmArrayWd = {`dataBfmArrayB3[ramAddrLoop], `dataBfmArrayB2[ramAddrLoop], `dataBfmArrayB1[ramAddrLoop], `dataBfmArrayB0[ramAddrLoop]};
if (randomData[ramAddrLoop] === dataBfmArrayWd)
begin
`dataBfmArrayB3[ramAddrLoop] = 8'hxx;
`dataBfmArrayB2[ramAddrLoop] = 8'hxx;
`dataBfmArrayB1[ramAddrLoop] = 8'hxx;
`dataBfmArrayB0[ramAddrLoop] = 8'hxx;
end
else
begin
$display("[ERROR] RAM Data at Address 0x%h is 0x%h, Expected 0x%h", ramAddrLoop, dataBfmArrayWd, randomData[ramAddrLoop]);
end
end
$display("[INFO ] **********************************************************");
$display("");
$display("");
#1000;
$finish();
end
endmodule | module TESTCASE (); |
`include "mem_map.v"
`include "tb_defines.v"
integer dataLoop;
integer ramAddrLoop;
reg [31:0] dataBfmArrayWd;
reg [31:0] randomData [RAM_SIZE_WORD-1:0];
initial
begin
for (dataLoop = 0 ; dataLoop < RAM_SIZE_WORD ; dataLoop = dataLoop + 1)
begin
randomData[dataLoop] = $random();
end
end
initial
begin
$display("[INFO ] ***** DATA RAM TEST: Running 32 bit incremental test *****");
for (ramAddrLoop = 0 ; ramAddrLoop < RAM_SIZE_WORD ; ramAddrLoop = ramAddrLoop + 1)
begin
`dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4'hF, randomData[ramAddrLoop]);
`dataBfm.wbReadCompare (DATA_RAM_BASE + (ramAddrLoop << 2), 4'hF, randomData[ramAddrLoop]);
end
$display("[INFO ] ***** Checking and Clearing Data Ram ***** ");
for (ramAddrLoop = 0 ; ramAddrLoop < RAM_SIZE_WORD ; ramAddrLoop = ramAddrLoop + 1)
begin
dataBfmArrayWd = {`dataBfmArrayB3[ramAddrLoop], `dataBfmArrayB2[ramAddrLoop], `dataBfmArrayB1[ramAddrLoop], `dataBfmArrayB0[ramAddrLoop]};
if (randomData[ramAddrLoop] === dataBfmArrayWd)
begin
`dataBfmArrayB3[ramAddrLoop] = 8'hxx;
`dataBfmArrayB2[ramAddrLoop] = 8'hxx;
`dataBfmArrayB1[ramAddrLoop] = 8'hxx;
`dataBfmArrayB0[ramAddrLoop] = 8'hxx;
end
else
begin
$display("[ERROR] RAM Data at Address 0x%h is 0x%h, Expected 0x%h", ramAddrLoop, dataBfmArrayWd, randomData[ramAddrLoop]);
end
end
$display("[INFO ] ***** DATA RAM TEST: Running 16 bit incremental test *****");
for (ramAddrLoop = 0 ; ramAddrLoop < RAM_SIZE_WORD ; ramAddrLoop = ramAddrLoop + 1)
begin
`dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4'h3, {16'h0000, randomData[ramAddrLoop][15:0]});
`dataBfm.wbReadCompare (DATA_RAM_BASE + (ramAddrLoop << 2), 4'h3, {16'h0000, randomData[ramAddrLoop][15:0]});
`dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4'hC, {randomData[ramAddrLoop][31:16], 16'h0000});
`dataBfm.wbReadCompare (DATA_RAM_BASE + (ramAddrLoop << 2), 4'hC, {randomData[ramAddrLoop][31:16], 16'h0000});
end
$display("[INFO ] ***** Checking and Clearing Data Ram ***** ");
for (ramAddrLoop = 0 ; ramAddrLoop < RAM_SIZE_WORD ; ramAddrLoop = ramAddrLoop + 1)
begin
dataBfmArrayWd = {`dataBfmArrayB3[ramAddrLoop], `dataBfmArrayB2[ramAddrLoop], `dataBfmArrayB1[ramAddrLoop], `dataBfmArrayB0[ramAddrLoop]};
if (randomData[ramAddrLoop] === dataBfmArrayWd)
begin
`dataBfmArrayB3[ramAddrLoop] = 8'hxx;
`dataBfmArrayB2[ramAddrLoop] = 8'hxx;
`dataBfmArrayB1[ramAddrLoop] = 8'hxx;
`dataBfmArrayB0[ramAddrLoop] = 8'hxx;
end
else
begin
$display("[ERROR] RAM Data at Address 0x%h is 0x%h, Expected 0x%h", ramAddrLoop, dataBfmArrayWd, randomData[ramAddrLoop]);
end
end
$display("[INFO ] ***** DATA RAM TEST: Running 8 bit incremental test *****");
for (ramAddrLoop = 0 ; ramAddrLoop < RAM_SIZE_WORD ; ramAddrLoop = ramAddrLoop + 1)
begin
`dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4'h1, {24'h000000, randomData[ramAddrLoop][ 7: 0]});
`dataBfm.wbReadCompare (DATA_RAM_BASE + (ramAddrLoop << 2), 4'h1, {24'h000000, randomData[ramAddrLoop][ 7: 0]});
`dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4'h2, {16'h0000, randomData[ramAddrLoop][15: 8], 8'h00});
`dataBfm.wbReadCompare (DATA_RAM_BASE + (ramAddrLoop << 2), 4'h2, {16'h0000, randomData[ramAddrLoop][15: 8], 8'h00});
`dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4'h4, {8'h00, randomData[ramAddrLoop][23:16], 16'h0000});
`dataBfm.wbReadCompare (DATA_RAM_BASE + (ramAddrLoop << 2), 4'h4, {8'h00, randomData[ramAddrLoop][23:16], 16'h0000});
`dataBfm.wbWrite (DATA_RAM_BASE + (ramAddrLoop << 2), 4'h8, {randomData[ramAddrLoop][31:24] , 24'h000000 });
`dataBfm.wbReadCompare (DATA_RAM_BASE + (ramAddrLoop << 2), 4'h8, {randomData[ramAddrLoop][31:24] , 24'h000000 });
end
$display("[INFO ] ***** Checking and Clearing Data Ram ***** ");
for (ramAddrLoop = 0 ; ramAddrLoop < RAM_SIZE_WORD ; ramAddrLoop = ramAddrLoop + 1)
begin
dataBfmArrayWd = {`dataBfmArrayB3[ramAddrLoop], `dataBfmArrayB2[ramAddrLoop], `dataBfmArrayB1[ramAddrLoop], `dataBfmArrayB0[ramAddrLoop]};
if (randomData[ramAddrLoop] === dataBfmArrayWd)
begin
`dataBfmArrayB3[ramAddrLoop] = 8'hxx;
`dataBfmArrayB2[ramAddrLoop] = 8'hxx;
`dataBfmArrayB1[ramAddrLoop] = 8'hxx;
`dataBfmArrayB0[ramAddrLoop] = 8'hxx;
end
else
begin
$display("[ERROR] RAM Data at Address 0x%h is 0x%h, Expected 0x%h", ramAddrLoop, dataBfmArrayWd, randomData[ramAddrLoop]);
end
end
$display("[INFO ] **********************************************************");
$display("");
$display("");
#1000;
$finish();
end
endmodule | 1 |
138,339 | data/full_repos/permissive/83270534/mercury/sim/uart_tests/loopback/testcase.v | 83,270,534 | testcase.v | v | 65 | 88 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/83270534/mercury/sim/uart_tests/loopback/testcase.v:3: Cannot find include file: mem_map.v\n`include "mem_map.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/83270534/mercury/sim/uart_tests/loopback,data/full_repos/permissive/83270534/mem_map.v\n data/full_repos/permissive/83270534/mercury/sim/uart_tests/loopback,data/full_repos/permissive/83270534/mem_map.v.v\n data/full_repos/permissive/83270534/mercury/sim/uart_tests/loopback,data/full_repos/permissive/83270534/mem_map.v.sv\n mem_map.v\n mem_map.v.v\n mem_map.v.sv\n obj_dir/mem_map.v\n obj_dir/mem_map.v.v\n obj_dir/mem_map.v.sv\n%Error: data/full_repos/permissive/83270534/mercury/sim/uart_tests/loopback/testcase.v:4: Cannot find include file: tb_defines.v\n`include "tb_defines.v" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/uart_tests/loopback/testcase.v:16: Define or directive not defined: \'`dataBfm\'\n `dataBfm.wbWriteByte(UART_RW_LINE_CTL, 8\'b1000_0011);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/uart_tests/loopback/testcase.v:16: syntax error, unexpected \'.\'\n `dataBfm.wbWriteByte(UART_RW_LINE_CTL, 8\'b1000_0011);\n ^\n%Error: data/full_repos/permissive/83270534/mercury/sim/uart_tests/loopback/testcase.v:19: Define or directive not defined: \'`dataBfm\'\n `dataBfm.wbWriteByte(UART_RW_DIV_MSB, 8\'h00); \n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/uart_tests/loopback/testcase.v:20: Define or directive not defined: \'`dataBfm\'\n `dataBfm.wbWriteByte(UART_RW_DIV_LSB, 8\'h01);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/uart_tests/loopback/testcase.v:23: Define or directive not defined: \'`dataBfm\'\n `dataBfm.wbWriteByte(UART_RW_LINE_CTL, 8\'b0000_0011);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/uart_tests/loopback/testcase.v:26: Define or directive not defined: \'`dataBfm\'\n `dataBfm.wbWriteByte(UART_RW_IRQ_EN, 8\'b0000_0001);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/uart_tests/loopback/testcase.v:32: Define or directive not defined: \'`dataBfm\'\n `dataBfm.wbWriteByte(UART_W_TX_FIFO, byteLoop+1);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/uart_tests/loopback/testcase.v:32: syntax error, unexpected \'.\'\n `dataBfm.wbWriteByte(UART_W_TX_FIFO, byteLoop+1);\n ^\n%Error: data/full_repos/permissive/83270534/mercury/sim/uart_tests/loopback/testcase.v:42: Define or directive not defined: \'`uartTop\'\n wait (`uartTop.int_o == 1\'b1);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/uart_tests/loopback/testcase.v:42: syntax error, unexpected \'.\', expecting TYPE-IDENTIFIER\n wait (`uartTop.int_o == 1\'b1);\n ^\n%Error: data/full_repos/permissive/83270534/mercury/sim/uart_tests/loopback/testcase.v:45: Define or directive not defined: \'`dataBfm\'\n `dataBfm.wbReadCompareByte (UART_R_RX_FIFO, byteLoop + 1);\n ^~~~~~~~\n%Error: data/full_repos/permissive/83270534/mercury/sim/uart_tests/loopback/testcase.v:45: syntax error, unexpected \'.\'\n `dataBfm.wbReadCompareByte (UART_R_RX_FIFO, byteLoop + 1);\n ^\n%Error: Exiting due to 14 error(s)\n' | 302,183 | module | module TESTCASE ();
`include "mem_map.v"
`include "tb_defines.v"
integer byteLoop;
initial
begin
$display("[INFO ] *************** Beginning UART Test ****************************");
$display("[INFO ] Configuring UART Registers");
`dataBfm.wbWriteByte(UART_RW_LINE_CTL, 8'b1000_0011);
`dataBfm.wbWriteByte(UART_RW_DIV_MSB, 8'h00);
`dataBfm.wbWriteByte(UART_RW_DIV_LSB, 8'h01);
`dataBfm.wbWriteByte(UART_RW_LINE_CTL, 8'b0000_0011);
`dataBfm.wbWriteByte(UART_RW_IRQ_EN, 8'b0000_0001);
$display("[INFO ] Writing incrementing values into TX fifo");
for (byteLoop = 0 ; byteLoop < 4 ; byteLoop = byteLoop + 1)
begin
`dataBfm.wbWriteByte(UART_W_TX_FIFO, byteLoop+1);
end
for (byteLoop = 0 ; byteLoop < 4 ; byteLoop = byteLoop + 1)
begin
$display("[INFO ] Waiting for the RX FIFO Irq from the UART");
wait (`uartTop.int_o == 1'b1);
$display("[INFO ] Reading the RX Fifo back");
`dataBfm.wbReadCompareByte (UART_R_RX_FIFO, byteLoop + 1);
end
$display("[INFO ] **********************************************************");
$display("");
$display("");
$finish();
end
endmodule | module TESTCASE (); |
`include "mem_map.v"
`include "tb_defines.v"
integer byteLoop;
initial
begin
$display("[INFO ] *************** Beginning UART Test ****************************");
$display("[INFO ] Configuring UART Registers");
`dataBfm.wbWriteByte(UART_RW_LINE_CTL, 8'b1000_0011);
`dataBfm.wbWriteByte(UART_RW_DIV_MSB, 8'h00);
`dataBfm.wbWriteByte(UART_RW_DIV_LSB, 8'h01);
`dataBfm.wbWriteByte(UART_RW_LINE_CTL, 8'b0000_0011);
`dataBfm.wbWriteByte(UART_RW_IRQ_EN, 8'b0000_0001);
$display("[INFO ] Writing incrementing values into TX fifo");
for (byteLoop = 0 ; byteLoop < 4 ; byteLoop = byteLoop + 1)
begin
`dataBfm.wbWriteByte(UART_W_TX_FIFO, byteLoop+1);
end
for (byteLoop = 0 ; byteLoop < 4 ; byteLoop = byteLoop + 1)
begin
$display("[INFO ] Waiting for the RX FIFO Irq from the UART");
wait (`uartTop.int_o == 1'b1);
$display("[INFO ] Reading the RX Fifo back");
`dataBfm.wbReadCompareByte (UART_R_RX_FIFO, byteLoop + 1);
end
$display("[INFO ] **********************************************************");
$display("");
$display("");
$finish();
end
endmodule | 1 |
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